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49ba9447 | 1 | /**@file\r |
2 | Memory Detection for Virtual Machines.\r | |
3 | \r | |
035ce3b3 | 4 | Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r |
b26f0cf9 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
49ba9447 | 6 | \r |
7 | Module Name:\r | |
8 | \r | |
9 | MemDetect.c\r | |
10 | \r | |
11 | **/\r | |
12 | \r | |
13 | //\r | |
14 | // The package level header files this module uses\r | |
15 | //\r | |
1fceaddb | 16 | #include <IndustryStandard/E820.h>\r |
49edde15 | 17 | #include <IndustryStandard/I440FxPiix4.h>\r |
d5e06444 | 18 | #include <IndustryStandard/Q35MchIch9.h>\r |
49ba9447 | 19 | #include <PiPei.h>\r |
20 | \r | |
21 | //\r | |
22 | // The Library classes this module consumes\r | |
23 | //\r | |
d5e06444 | 24 | #include <Library/BaseLib.h>\r |
6a7cba79 | 25 | #include <Library/BaseMemoryLib.h>\r |
49ba9447 | 26 | #include <Library/DebugLib.h>\r |
27 | #include <Library/HobLib.h>\r | |
28 | #include <Library/IoLib.h>\r | |
c1c2669c | 29 | #include <Library/PcdLib.h>\r |
d5e06444 | 30 | #include <Library/PciLib.h>\r |
49ba9447 | 31 | #include <Library/PeimEntryPoint.h>\r |
32 | #include <Library/ResourcePublicationLib.h>\r | |
e8e5cd4a | 33 | #include <Library/MtrrLib.h>\r |
7e5b1b67 | 34 | #include <Library/QemuFwCfgLib.h>\r |
49ba9447 | 35 | \r |
36 | #include "Platform.h"\r | |
37 | #include "Cmos.h"\r | |
38 | \r | |
bc89fe48 LE |
39 | UINT8 mPhysMemAddressWidth;\r |
40 | \r | |
45d87081 LE |
41 | STATIC UINT32 mS3AcpiReservedMemoryBase;\r |
42 | STATIC UINT32 mS3AcpiReservedMemorySize;\r | |
43 | \r | |
23bfb5c0 LE |
44 | STATIC UINT16 mQ35TsegMbytes;\r |
45 | \r | |
49edde15 LE |
46 | UINT32 mQemuUc32Base;\r |
47 | \r | |
23bfb5c0 LE |
48 | VOID\r |
49 | Q35TsegMbytesInitialization (\r | |
50 | VOID\r | |
51 | )\r | |
52 | {\r | |
d5e06444 LE |
53 | UINT16 ExtendedTsegMbytes;\r |
54 | RETURN_STATUS PcdStatus;\r | |
55 | \r | |
56 | if (mHostBridgeDevId != INTEL_Q35_MCH_DEVICE_ID) {\r | |
57 | DEBUG ((\r | |
58 | DEBUG_ERROR,\r | |
59 | "%a: no TSEG (SMRAM) on host bridge DID=0x%04x; "\r | |
60 | "only DID=0x%04x (Q35) is supported\n",\r | |
61 | __FUNCTION__,\r | |
62 | mHostBridgeDevId,\r | |
63 | INTEL_Q35_MCH_DEVICE_ID\r | |
64 | ));\r | |
65 | ASSERT (FALSE);\r | |
66 | CpuDeadLoop ();\r | |
67 | }\r | |
68 | \r | |
69 | //\r | |
70 | // Check if QEMU offers an extended TSEG.\r | |
71 | //\r | |
72 | // This can be seen from writing MCH_EXT_TSEG_MB_QUERY to the MCH_EXT_TSEG_MB\r | |
73 | // register, and reading back the register.\r | |
74 | //\r | |
75 | // On a QEMU machine type that does not offer an extended TSEG, the initial\r | |
76 | // write overwrites whatever value a malicious guest OS may have placed in\r | |
77 | // the (unimplemented) register, before entering S3 or rebooting.\r | |
78 | // Subsequently, the read returns MCH_EXT_TSEG_MB_QUERY unchanged.\r | |
79 | //\r | |
80 | // On a QEMU machine type that offers an extended TSEG, the initial write\r | |
81 | // triggers an update to the register. Subsequently, the value read back\r | |
82 | // (which is guaranteed to differ from MCH_EXT_TSEG_MB_QUERY) tells us the\r | |
83 | // number of megabytes.\r | |
84 | //\r | |
85 | PciWrite16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB), MCH_EXT_TSEG_MB_QUERY);\r | |
86 | ExtendedTsegMbytes = PciRead16 (DRAMC_REGISTER_Q35 (MCH_EXT_TSEG_MB));\r | |
87 | if (ExtendedTsegMbytes == MCH_EXT_TSEG_MB_QUERY) {\r | |
88 | mQ35TsegMbytes = PcdGet16 (PcdQ35TsegMbytes);\r | |
89 | return;\r | |
90 | }\r | |
91 | \r | |
92 | DEBUG ((\r | |
93 | DEBUG_INFO,\r | |
94 | "%a: QEMU offers an extended TSEG (%d MB)\n",\r | |
95 | __FUNCTION__,\r | |
96 | ExtendedTsegMbytes\r | |
97 | ));\r | |
98 | PcdStatus = PcdSet16S (PcdQ35TsegMbytes, ExtendedTsegMbytes);\r | |
99 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
100 | mQ35TsegMbytes = ExtendedTsegMbytes;\r | |
23bfb5c0 LE |
101 | }\r |
102 | \r | |
103 | \r | |
49edde15 LE |
104 | VOID\r |
105 | QemuUc32BaseInitialization (\r | |
106 | VOID\r | |
107 | )\r | |
108 | {\r | |
109 | UINT32 LowerMemorySize;\r | |
110 | UINT32 Uc32Size;\r | |
111 | \r | |
112 | if (mXen) {\r | |
113 | return;\r | |
114 | }\r | |
115 | \r | |
116 | if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r | |
117 | //\r | |
118 | // On q35, the 32-bit area that we'll mark as UC, through variable MTRRs,\r | |
119 | // starts at PcdPciExpressBaseAddress. The platform DSC is responsible for\r | |
120 | // setting PcdPciExpressBaseAddress such that describing the\r | |
121 | // [PcdPciExpressBaseAddress, 4GB) range require a very small number of\r | |
122 | // variable MTRRs (preferably 1 or 2).\r | |
123 | //\r | |
124 | ASSERT (FixedPcdGet64 (PcdPciExpressBaseAddress) <= MAX_UINT32);\r | |
125 | mQemuUc32Base = (UINT32)FixedPcdGet64 (PcdPciExpressBaseAddress);\r | |
126 | return;\r | |
127 | }\r | |
128 | \r | |
129 | ASSERT (mHostBridgeDevId == INTEL_82441_DEVICE_ID);\r | |
130 | //\r | |
131 | // On i440fx, start with the [LowerMemorySize, 4GB) range. Make sure one\r | |
132 | // variable MTRR suffices by truncating the size to a whole power of two,\r | |
133 | // while keeping the end affixed to 4GB. This will round the base up.\r | |
134 | //\r | |
135 | LowerMemorySize = GetSystemMemorySizeBelow4gb ();\r | |
136 | Uc32Size = GetPowerOfTwo32 ((UINT32)(SIZE_4GB - LowerMemorySize));\r | |
137 | mQemuUc32Base = (UINT32)(SIZE_4GB - Uc32Size);\r | |
138 | //\r | |
139 | // Assuming that LowerMemorySize is at least 1 byte, Uc32Size is at most 2GB.\r | |
140 | // Therefore mQemuUc32Base is at least 2GB.\r | |
141 | //\r | |
142 | ASSERT (mQemuUc32Base >= BASE_2GB);\r | |
143 | \r | |
144 | if (mQemuUc32Base != LowerMemorySize) {\r | |
145 | DEBUG ((DEBUG_VERBOSE, "%a: rounded UC32 base from 0x%x up to 0x%x, for "\r | |
146 | "an UC32 size of 0x%x\n", __FUNCTION__, LowerMemorySize, mQemuUc32Base,\r | |
147 | Uc32Size));\r | |
148 | }\r | |
149 | }\r | |
150 | \r | |
151 | \r | |
1fceaddb LE |
152 | /**\r |
153 | Iterate over the RAM entries in QEMU's fw_cfg E820 RAM map that start outside\r | |
154 | of the 32-bit address range.\r | |
155 | \r | |
156 | Find the highest exclusive >=4GB RAM address, or produce memory resource\r | |
157 | descriptor HOBs for RAM entries that start at or above 4GB.\r | |
158 | \r | |
159 | @param[out] MaxAddress If MaxAddress is NULL, then ScanOrAdd64BitE820Ram()\r | |
160 | produces memory resource descriptor HOBs for RAM\r | |
161 | entries that start at or above 4GB.\r | |
162 | \r | |
163 | Otherwise, MaxAddress holds the highest exclusive\r | |
164 | >=4GB RAM address on output. If QEMU's fw_cfg E820\r | |
165 | RAM map contains no RAM entry that starts outside of\r | |
166 | the 32-bit address range, then MaxAddress is exactly\r | |
167 | 4GB on output.\r | |
168 | \r | |
169 | @retval EFI_SUCCESS The fw_cfg E820 RAM map was found and processed.\r | |
170 | \r | |
171 | @retval EFI_PROTOCOL_ERROR The RAM map was found, but its size wasn't a\r | |
172 | whole multiple of sizeof(EFI_E820_ENTRY64). No\r | |
173 | RAM entry was processed.\r | |
174 | \r | |
175 | @return Error codes from QemuFwCfgFindFile(). No RAM\r | |
176 | entry was processed.\r | |
177 | **/\r | |
178 | STATIC\r | |
179 | EFI_STATUS\r | |
180 | ScanOrAdd64BitE820Ram (\r | |
181 | OUT UINT64 *MaxAddress OPTIONAL\r | |
182 | )\r | |
183 | {\r | |
184 | EFI_STATUS Status;\r | |
185 | FIRMWARE_CONFIG_ITEM FwCfgItem;\r | |
186 | UINTN FwCfgSize;\r | |
187 | EFI_E820_ENTRY64 E820Entry;\r | |
188 | UINTN Processed;\r | |
189 | \r | |
190 | Status = QemuFwCfgFindFile ("etc/e820", &FwCfgItem, &FwCfgSize);\r | |
191 | if (EFI_ERROR (Status)) {\r | |
192 | return Status;\r | |
193 | }\r | |
194 | if (FwCfgSize % sizeof E820Entry != 0) {\r | |
195 | return EFI_PROTOCOL_ERROR;\r | |
196 | }\r | |
197 | \r | |
198 | if (MaxAddress != NULL) {\r | |
199 | *MaxAddress = BASE_4GB;\r | |
200 | }\r | |
201 | \r | |
202 | QemuFwCfgSelectItem (FwCfgItem);\r | |
203 | for (Processed = 0; Processed < FwCfgSize; Processed += sizeof E820Entry) {\r | |
204 | QemuFwCfgReadBytes (sizeof E820Entry, &E820Entry);\r | |
205 | DEBUG ((\r | |
206 | DEBUG_VERBOSE,\r | |
207 | "%a: Base=0x%Lx Length=0x%Lx Type=%u\n",\r | |
208 | __FUNCTION__,\r | |
209 | E820Entry.BaseAddr,\r | |
210 | E820Entry.Length,\r | |
211 | E820Entry.Type\r | |
212 | ));\r | |
213 | if (E820Entry.Type == EfiAcpiAddressRangeMemory &&\r | |
214 | E820Entry.BaseAddr >= BASE_4GB) {\r | |
215 | if (MaxAddress == NULL) {\r | |
216 | UINT64 Base;\r | |
217 | UINT64 End;\r | |
218 | \r | |
219 | //\r | |
220 | // Round up the start address, and round down the end address.\r | |
221 | //\r | |
222 | Base = ALIGN_VALUE (E820Entry.BaseAddr, (UINT64)EFI_PAGE_SIZE);\r | |
223 | End = (E820Entry.BaseAddr + E820Entry.Length) &\r | |
224 | ~(UINT64)EFI_PAGE_MASK;\r | |
225 | if (Base < End) {\r | |
226 | AddMemoryRangeHob (Base, End);\r | |
227 | DEBUG ((\r | |
228 | DEBUG_VERBOSE,\r | |
229 | "%a: AddMemoryRangeHob [0x%Lx, 0x%Lx)\n",\r | |
230 | __FUNCTION__,\r | |
231 | Base,\r | |
232 | End\r | |
233 | ));\r | |
234 | }\r | |
235 | } else {\r | |
236 | UINT64 Candidate;\r | |
237 | \r | |
238 | Candidate = E820Entry.BaseAddr + E820Entry.Length;\r | |
239 | if (Candidate > *MaxAddress) {\r | |
240 | *MaxAddress = Candidate;\r | |
241 | DEBUG ((\r | |
242 | DEBUG_VERBOSE,\r | |
243 | "%a: MaxAddress=0x%Lx\n",\r | |
244 | __FUNCTION__,\r | |
245 | *MaxAddress\r | |
246 | ));\r | |
247 | }\r | |
248 | }\r | |
249 | }\r | |
250 | }\r | |
251 | return EFI_SUCCESS;\r | |
252 | }\r | |
253 | \r | |
254 | \r | |
4b455f7b | 255 | UINT32\r |
c0e10976 | 256 | GetSystemMemorySizeBelow4gb (\r |
4b455f7b | 257 | VOID\r |
49ba9447 | 258 | )\r |
259 | {\r | |
260 | UINT8 Cmos0x34;\r | |
261 | UINT8 Cmos0x35;\r | |
262 | \r | |
263 | //\r | |
264 | // CMOS 0x34/0x35 specifies the system memory above 16 MB.\r | |
265 | // * CMOS(0x35) is the high byte\r | |
266 | // * CMOS(0x34) is the low byte\r | |
267 | // * The size is specified in 64kb chunks\r | |
268 | // * Since this is memory above 16MB, the 16MB must be added\r | |
269 | // into the calculation to get the total memory size.\r | |
270 | //\r | |
271 | \r | |
272 | Cmos0x34 = (UINT8) CmosRead8 (0x34);\r | |
273 | Cmos0x35 = (UINT8) CmosRead8 (0x35);\r | |
274 | \r | |
c4046161 | 275 | return (UINT32) (((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB);\r |
49ba9447 | 276 | }\r |
277 | \r | |
278 | \r | |
c0e10976 | 279 | STATIC\r |
280 | UINT64\r | |
281 | GetSystemMemorySizeAbove4gb (\r | |
282 | )\r | |
283 | {\r | |
284 | UINT32 Size;\r | |
285 | UINTN CmosIndex;\r | |
286 | \r | |
287 | //\r | |
288 | // CMOS 0x5b-0x5d specifies the system memory above 4GB MB.\r | |
289 | // * CMOS(0x5d) is the most significant size byte\r | |
290 | // * CMOS(0x5c) is the middle size byte\r | |
291 | // * CMOS(0x5b) is the least significant size byte\r | |
292 | // * The size is specified in 64kb chunks\r | |
293 | //\r | |
294 | \r | |
295 | Size = 0;\r | |
296 | for (CmosIndex = 0x5d; CmosIndex >= 0x5b; CmosIndex--) {\r | |
297 | Size = (UINT32) (Size << 8) + (UINT32) CmosRead8 (CmosIndex);\r | |
298 | }\r | |
299 | \r | |
300 | return LShiftU64 (Size, 16);\r | |
301 | }\r | |
302 | \r | |
bc89fe48 | 303 | \r |
d5371680 LE |
304 | /**\r |
305 | Return the highest address that DXE could possibly use, plus one.\r | |
306 | **/\r | |
307 | STATIC\r | |
308 | UINT64\r | |
309 | GetFirstNonAddress (\r | |
310 | VOID\r | |
311 | )\r | |
312 | {\r | |
313 | UINT64 FirstNonAddress;\r | |
7e5b1b67 LE |
314 | UINT64 Pci64Base, Pci64Size;\r |
315 | CHAR8 MbString[7 + 1];\r | |
316 | EFI_STATUS Status;\r | |
317 | FIRMWARE_CONFIG_ITEM FwCfgItem;\r | |
318 | UINTN FwCfgSize;\r | |
319 | UINT64 HotPlugMemoryEnd;\r | |
32e083c7 | 320 | RETURN_STATUS PcdStatus;\r |
d5371680 | 321 | \r |
1fceaddb LE |
322 | //\r |
323 | // set FirstNonAddress to suppress incorrect compiler/analyzer warnings\r | |
324 | //\r | |
325 | FirstNonAddress = 0;\r | |
326 | \r | |
327 | //\r | |
328 | // If QEMU presents an E820 map, then get the highest exclusive >=4GB RAM\r | |
329 | // address from it. This can express an address >= 4GB+1TB.\r | |
330 | //\r | |
331 | // Otherwise, get the flat size of the memory above 4GB from the CMOS (which\r | |
332 | // can only express a size smaller than 1TB), and add it to 4GB.\r | |
333 | //\r | |
334 | Status = ScanOrAdd64BitE820Ram (&FirstNonAddress);\r | |
335 | if (EFI_ERROR (Status)) {\r | |
336 | FirstNonAddress = BASE_4GB + GetSystemMemorySizeAbove4gb ();\r | |
337 | }\r | |
7e5b1b67 LE |
338 | \r |
339 | //\r | |
340 | // If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO\r | |
341 | // resources to 32-bit anyway. See DegradeResource() in\r | |
342 | // "PciResourceSupport.c".\r | |
343 | //\r | |
344 | #ifdef MDE_CPU_IA32\r | |
345 | if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r | |
346 | return FirstNonAddress;\r | |
347 | }\r | |
348 | #endif\r | |
349 | \r | |
350 | //\r | |
351 | // Otherwise, in order to calculate the highest address plus one, we must\r | |
352 | // consider the 64-bit PCI host aperture too. Fetch the default size.\r | |
353 | //\r | |
354 | Pci64Size = PcdGet64 (PcdPciMmio64Size);\r | |
355 | \r | |
356 | //\r | |
357 | // See if the user specified the number of megabytes for the 64-bit PCI host\r | |
358 | // aperture. The number of non-NUL characters in MbString allows for\r | |
359 | // 9,999,999 MB, which is approximately 10 TB.\r | |
360 | //\r | |
361 | // As signaled by the "X-" prefix, this knob is experimental, and might go\r | |
362 | // away at any time.\r | |
363 | //\r | |
364 | Status = QemuFwCfgFindFile ("opt/ovmf/X-PciMmio64Mb", &FwCfgItem,\r | |
365 | &FwCfgSize);\r | |
366 | if (!EFI_ERROR (Status)) {\r | |
367 | if (FwCfgSize >= sizeof MbString) {\r | |
368 | DEBUG ((EFI_D_WARN,\r | |
369 | "%a: ignoring malformed 64-bit PCI host aperture size from fw_cfg\n",\r | |
370 | __FUNCTION__));\r | |
371 | } else {\r | |
372 | QemuFwCfgSelectItem (FwCfgItem);\r | |
373 | QemuFwCfgReadBytes (FwCfgSize, MbString);\r | |
374 | MbString[FwCfgSize] = '\0';\r | |
375 | Pci64Size = LShiftU64 (AsciiStrDecimalToUint64 (MbString), 20);\r | |
376 | }\r | |
377 | }\r | |
378 | \r | |
379 | if (Pci64Size == 0) {\r | |
380 | if (mBootMode != BOOT_ON_S3_RESUME) {\r | |
381 | DEBUG ((EFI_D_INFO, "%a: disabling 64-bit PCI host aperture\n",\r | |
382 | __FUNCTION__));\r | |
32e083c7 LE |
383 | PcdStatus = PcdSet64S (PcdPciMmio64Size, 0);\r |
384 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
7e5b1b67 LE |
385 | }\r |
386 | \r | |
387 | //\r | |
388 | // There's nothing more to do; the amount of memory above 4GB fully\r | |
389 | // determines the highest address plus one. The memory hotplug area (see\r | |
390 | // below) plays no role for the firmware in this case.\r | |
391 | //\r | |
392 | return FirstNonAddress;\r | |
393 | }\r | |
394 | \r | |
395 | //\r | |
396 | // The "etc/reserved-memory-end" fw_cfg file, when present, contains an\r | |
397 | // absolute, exclusive end address for the memory hotplug area. This area\r | |
398 | // starts right at the end of the memory above 4GB. The 64-bit PCI host\r | |
399 | // aperture must be placed above it.\r | |
400 | //\r | |
401 | Status = QemuFwCfgFindFile ("etc/reserved-memory-end", &FwCfgItem,\r | |
402 | &FwCfgSize);\r | |
403 | if (!EFI_ERROR (Status) && FwCfgSize == sizeof HotPlugMemoryEnd) {\r | |
404 | QemuFwCfgSelectItem (FwCfgItem);\r | |
405 | QemuFwCfgReadBytes (FwCfgSize, &HotPlugMemoryEnd);\r | |
c27c0003 LE |
406 | DEBUG ((DEBUG_VERBOSE, "%a: HotPlugMemoryEnd=0x%Lx\n", __FUNCTION__,\r |
407 | HotPlugMemoryEnd));\r | |
7e5b1b67 LE |
408 | \r |
409 | ASSERT (HotPlugMemoryEnd >= FirstNonAddress);\r | |
410 | FirstNonAddress = HotPlugMemoryEnd;\r | |
411 | }\r | |
412 | \r | |
413 | //\r | |
414 | // SeaBIOS aligns both boundaries of the 64-bit PCI host aperture to 1GB, so\r | |
415 | // that the host can map it with 1GB hugepages. Follow suit.\r | |
416 | //\r | |
417 | Pci64Base = ALIGN_VALUE (FirstNonAddress, (UINT64)SIZE_1GB);\r | |
418 | Pci64Size = ALIGN_VALUE (Pci64Size, (UINT64)SIZE_1GB);\r | |
419 | \r | |
420 | //\r | |
421 | // The 64-bit PCI host aperture should also be "naturally" aligned. The\r | |
422 | // alignment is determined by rounding the size of the aperture down to the\r | |
423 | // next smaller or equal power of two. That is, align the aperture by the\r | |
424 | // largest BAR size that can fit into it.\r | |
425 | //\r | |
426 | Pci64Base = ALIGN_VALUE (Pci64Base, GetPowerOfTwo64 (Pci64Size));\r | |
427 | \r | |
428 | if (mBootMode != BOOT_ON_S3_RESUME) {\r | |
429 | //\r | |
430 | // The core PciHostBridgeDxe driver will automatically add this range to\r | |
431 | // the GCD memory space map through our PciHostBridgeLib instance; here we\r | |
432 | // only need to set the PCDs.\r | |
433 | //\r | |
32e083c7 LE |
434 | PcdStatus = PcdSet64S (PcdPciMmio64Base, Pci64Base);\r |
435 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
436 | PcdStatus = PcdSet64S (PcdPciMmio64Size, Pci64Size);\r | |
437 | ASSERT_RETURN_ERROR (PcdStatus);\r | |
438 | \r | |
7e5b1b67 LE |
439 | DEBUG ((EFI_D_INFO, "%a: Pci64Base=0x%Lx Pci64Size=0x%Lx\n",\r |
440 | __FUNCTION__, Pci64Base, Pci64Size));\r | |
441 | }\r | |
442 | \r | |
443 | //\r | |
444 | // The useful address space ends with the 64-bit PCI host aperture.\r | |
445 | //\r | |
446 | FirstNonAddress = Pci64Base + Pci64Size;\r | |
d5371680 LE |
447 | return FirstNonAddress;\r |
448 | }\r | |
449 | \r | |
450 | \r | |
bc89fe48 LE |
451 | /**\r |
452 | Initialize the mPhysMemAddressWidth variable, based on guest RAM size.\r | |
453 | **/\r | |
454 | VOID\r | |
455 | AddressWidthInitialization (\r | |
456 | VOID\r | |
457 | )\r | |
458 | {\r | |
459 | UINT64 FirstNonAddress;\r | |
460 | \r | |
461 | //\r | |
462 | // As guest-physical memory size grows, the permanent PEI RAM requirements\r | |
463 | // are dominated by the identity-mapping page tables built by the DXE IPL.\r | |
464 | // The DXL IPL keys off of the physical address bits advertized in the CPU\r | |
465 | // HOB. To conserve memory, we calculate the minimum address width here.\r | |
466 | //\r | |
d5371680 | 467 | FirstNonAddress = GetFirstNonAddress ();\r |
bc89fe48 LE |
468 | mPhysMemAddressWidth = (UINT8)HighBitSet64 (FirstNonAddress);\r |
469 | \r | |
470 | //\r | |
471 | // If FirstNonAddress is not an integral power of two, then we need an\r | |
472 | // additional bit.\r | |
473 | //\r | |
474 | if ((FirstNonAddress & (FirstNonAddress - 1)) != 0) {\r | |
475 | ++mPhysMemAddressWidth;\r | |
476 | }\r | |
477 | \r | |
478 | //\r | |
479 | // The minimum address width is 36 (covers up to and excluding 64 GB, which\r | |
480 | // is the maximum for Ia32 + PAE). The theoretical architecture maximum for\r | |
481 | // X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits. We\r | |
482 | // can simply assert that here, since 48 bits are good enough for 256 TB.\r | |
483 | //\r | |
484 | if (mPhysMemAddressWidth <= 36) {\r | |
485 | mPhysMemAddressWidth = 36;\r | |
486 | }\r | |
487 | ASSERT (mPhysMemAddressWidth <= 48);\r | |
488 | }\r | |
489 | \r | |
490 | \r | |
491 | /**\r | |
492 | Calculate the cap for the permanent PEI memory.\r | |
493 | **/\r | |
494 | STATIC\r | |
495 | UINT32\r | |
496 | GetPeiMemoryCap (\r | |
497 | VOID\r | |
498 | )\r | |
499 | {\r | |
500 | BOOLEAN Page1GSupport;\r | |
501 | UINT32 RegEax;\r | |
502 | UINT32 RegEdx;\r | |
503 | UINT32 Pml4Entries;\r | |
504 | UINT32 PdpEntries;\r | |
505 | UINTN TotalPages;\r | |
506 | \r | |
507 | //\r | |
508 | // If DXE is 32-bit, then just return the traditional 64 MB cap.\r | |
509 | //\r | |
510 | #ifdef MDE_CPU_IA32\r | |
511 | if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r | |
512 | return SIZE_64MB;\r | |
513 | }\r | |
514 | #endif\r | |
515 | \r | |
516 | //\r | |
517 | // Dependent on physical address width, PEI memory allocations can be\r | |
518 | // dominated by the page tables built for 64-bit DXE. So we key the cap off\r | |
519 | // of those. The code below is based on CreateIdentityMappingPageTables() in\r | |
520 | // "MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c".\r | |
521 | //\r | |
522 | Page1GSupport = FALSE;\r | |
523 | if (PcdGetBool (PcdUse1GPageTable)) {\r | |
524 | AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);\r | |
525 | if (RegEax >= 0x80000001) {\r | |
526 | AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);\r | |
527 | if ((RegEdx & BIT26) != 0) {\r | |
528 | Page1GSupport = TRUE;\r | |
529 | }\r | |
530 | }\r | |
531 | }\r | |
532 | \r | |
533 | if (mPhysMemAddressWidth <= 39) {\r | |
534 | Pml4Entries = 1;\r | |
535 | PdpEntries = 1 << (mPhysMemAddressWidth - 30);\r | |
536 | ASSERT (PdpEntries <= 0x200);\r | |
537 | } else {\r | |
538 | Pml4Entries = 1 << (mPhysMemAddressWidth - 39);\r | |
539 | ASSERT (Pml4Entries <= 0x200);\r | |
540 | PdpEntries = 512;\r | |
541 | }\r | |
542 | \r | |
543 | TotalPages = Page1GSupport ? Pml4Entries + 1 :\r | |
544 | (PdpEntries + 1) * Pml4Entries + 1;\r | |
545 | ASSERT (TotalPages <= 0x40201);\r | |
546 | \r | |
547 | //\r | |
548 | // Add 64 MB for miscellaneous allocations. Note that for\r | |
549 | // mPhysMemAddressWidth values close to 36, the cap will actually be\r | |
550 | // dominated by this increment.\r | |
551 | //\r | |
552 | return (UINT32)(EFI_PAGES_TO_SIZE (TotalPages) + SIZE_64MB);\r | |
553 | }\r | |
554 | \r | |
555 | \r | |
36658fff WL |
556 | /**\r |
557 | Publish PEI core memory\r | |
558 | \r | |
559 | @return EFI_SUCCESS The PEIM initialized successfully.\r | |
560 | \r | |
561 | **/\r | |
562 | EFI_STATUS\r | |
563 | PublishPeiMemory (\r | |
564 | VOID\r | |
565 | )\r | |
566 | {\r | |
567 | EFI_STATUS Status;\r | |
568 | EFI_PHYSICAL_ADDRESS MemoryBase;\r | |
569 | UINT64 MemorySize;\r | |
fc3f005a | 570 | UINT32 LowerMemorySize;\r |
bc89fe48 | 571 | UINT32 PeiMemoryCap;\r |
36658fff | 572 | \r |
45d87081 LE |
573 | LowerMemorySize = GetSystemMemorySizeBelow4gb ();\r |
574 | if (FeaturePcdGet (PcdSmmSmramRequire)) {\r | |
575 | //\r | |
576 | // TSEG is chipped from the end of low RAM\r | |
577 | //\r | |
23bfb5c0 | 578 | LowerMemorySize -= mQ35TsegMbytes * SIZE_1MB;\r |
45d87081 LE |
579 | }\r |
580 | \r | |
581 | //\r | |
582 | // If S3 is supported, then the S3 permanent PEI memory is placed next,\r | |
583 | // downwards. Its size is primarily dictated by CpuMpPei. The formula below\r | |
584 | // is an approximation.\r | |
585 | //\r | |
586 | if (mS3Supported) {\r | |
587 | mS3AcpiReservedMemorySize = SIZE_512KB +\r | |
45a70db3 | 588 | mMaxCpuCount *\r |
45d87081 LE |
589 | PcdGet32 (PcdCpuApStackSize);\r |
590 | mS3AcpiReservedMemoryBase = LowerMemorySize - mS3AcpiReservedMemorySize;\r | |
591 | LowerMemorySize = mS3AcpiReservedMemoryBase;\r | |
592 | }\r | |
593 | \r | |
8e54500f | 594 | if (mBootMode == BOOT_ON_S3_RESUME) {\r |
45d87081 LE |
595 | MemoryBase = mS3AcpiReservedMemoryBase;\r |
596 | MemorySize = mS3AcpiReservedMemorySize;\r | |
8e54500f | 597 | } else {\r |
bc89fe48 LE |
598 | PeiMemoryCap = GetPeiMemoryCap ();\r |
599 | DEBUG ((EFI_D_INFO, "%a: mPhysMemAddressWidth=%d PeiMemoryCap=%u KB\n",\r | |
600 | __FUNCTION__, mPhysMemAddressWidth, PeiMemoryCap >> 10));\r | |
601 | \r | |
8e54500f JJ |
602 | //\r |
603 | // Determine the range of memory to use during PEI\r | |
604 | //\r | |
efb0f16e LE |
605 | // Technically we could lay the permanent PEI RAM over SEC's temporary\r |
606 | // decompression and scratch buffer even if "secure S3" is needed, since\r | |
607 | // their lifetimes don't overlap. However, PeiFvInitialization() will cover\r | |
608 | // RAM up to PcdOvmfDecompressionScratchEnd with an EfiACPIMemoryNVS memory\r | |
609 | // allocation HOB, and other allocations served from the permanent PEI RAM\r | |
610 | // shouldn't overlap with that HOB.\r | |
611 | //\r | |
612 | MemoryBase = mS3Supported && FeaturePcdGet (PcdSmmSmramRequire) ?\r | |
613 | PcdGet32 (PcdOvmfDecompressionScratchEnd) :\r | |
614 | PcdGet32 (PcdOvmfDxeMemFvBase) + PcdGet32 (PcdOvmfDxeMemFvSize);\r | |
8e54500f | 615 | MemorySize = LowerMemorySize - MemoryBase;\r |
bc89fe48 LE |
616 | if (MemorySize > PeiMemoryCap) {\r |
617 | MemoryBase = LowerMemorySize - PeiMemoryCap;\r | |
618 | MemorySize = PeiMemoryCap;\r | |
8e54500f | 619 | }\r |
36658fff WL |
620 | }\r |
621 | \r | |
622 | //\r | |
623 | // Publish this memory to the PEI Core\r | |
624 | //\r | |
625 | Status = PublishSystemMemory(MemoryBase, MemorySize);\r | |
626 | ASSERT_EFI_ERROR (Status);\r | |
627 | \r | |
628 | return Status;\r | |
629 | }\r | |
630 | \r | |
c0e10976 | 631 | \r |
49ba9447 | 632 | /**\r |
c034906e | 633 | Peform Memory Detection for QEMU / KVM\r |
49ba9447 | 634 | \r |
635 | **/\r | |
c034906e JJ |
636 | STATIC\r |
637 | VOID\r | |
638 | QemuInitializeRam (\r | |
639 | VOID\r | |
49ba9447 | 640 | )\r |
641 | {\r | |
c0e10976 | 642 | UINT64 LowerMemorySize;\r |
643 | UINT64 UpperMemorySize;\r | |
79d274b8 LE |
644 | MTRR_SETTINGS MtrrSettings;\r |
645 | EFI_STATUS Status;\r | |
49ba9447 | 646 | \r |
c034906e | 647 | DEBUG ((EFI_D_INFO, "%a called\n", __FUNCTION__));\r |
49ba9447 | 648 | \r |
649 | //\r | |
650 | // Determine total memory size available\r | |
651 | //\r | |
c0e10976 | 652 | LowerMemorySize = GetSystemMemorySizeBelow4gb ();\r |
653 | UpperMemorySize = GetSystemMemorySizeAbove4gb ();\r | |
49ba9447 | 654 | \r |
e3e3090a LE |
655 | if (mBootMode == BOOT_ON_S3_RESUME) {\r |
656 | //\r | |
657 | // Create the following memory HOB as an exception on the S3 boot path.\r | |
658 | //\r | |
659 | // Normally we'd create memory HOBs only on the normal boot path. However,\r | |
660 | // CpuMpPei specifically needs such a low-memory HOB on the S3 path as\r | |
661 | // well, for "borrowing" a subset of it temporarily, for the AP startup\r | |
662 | // vector.\r | |
663 | //\r | |
664 | // CpuMpPei saves the original contents of the borrowed area in permanent\r | |
665 | // PEI RAM, in a backup buffer allocated with the normal PEI services.\r | |
666 | // CpuMpPei restores the original contents ("returns" the borrowed area) at\r | |
667 | // End-of-PEI. End-of-PEI in turn is emitted by S3Resume2Pei before\r | |
8c0b0b34 | 668 | // transferring control to the OS's wakeup vector in the FACS.\r |
e3e3090a LE |
669 | //\r |
670 | // We expect any other PEIMs that "borrow" memory similarly to CpuMpPei to\r | |
671 | // restore the original contents. Furthermore, we expect all such PEIMs\r | |
672 | // (CpuMpPei included) to claim the borrowed areas by producing memory\r | |
673 | // allocation HOBs, and to honor preexistent memory allocation HOBs when\r | |
674 | // looking for an area to borrow.\r | |
675 | //\r | |
676 | AddMemoryRangeHob (0, BASE_512KB + BASE_128KB);\r | |
677 | } else {\r | |
bd386eaf JJ |
678 | //\r |
679 | // Create memory HOBs\r | |
680 | //\r | |
bd386eaf | 681 | AddMemoryRangeHob (0, BASE_512KB + BASE_128KB);\r |
b09c1c6f LE |
682 | \r |
683 | if (FeaturePcdGet (PcdSmmSmramRequire)) {\r | |
684 | UINT32 TsegSize;\r | |
685 | \r | |
23bfb5c0 | 686 | TsegSize = mQ35TsegMbytes * SIZE_1MB;\r |
b09c1c6f LE |
687 | AddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize);\r |
688 | AddReservedMemoryBaseSizeHob (LowerMemorySize - TsegSize, TsegSize,\r | |
689 | TRUE);\r | |
690 | } else {\r | |
691 | AddMemoryRangeHob (BASE_1MB, LowerMemorySize);\r | |
692 | }\r | |
693 | \r | |
1fceaddb LE |
694 | //\r |
695 | // If QEMU presents an E820 map, then create memory HOBs for the >=4GB RAM\r | |
696 | // entries. Otherwise, create a single memory HOB with the flat >=4GB\r | |
697 | // memory size read from the CMOS.\r | |
698 | //\r | |
699 | Status = ScanOrAdd64BitE820Ram (NULL);\r | |
700 | if (EFI_ERROR (Status) && UpperMemorySize != 0) {\r | |
035ce3b3 | 701 | AddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize);\r |
cfc80e2e | 702 | }\r |
bd386eaf | 703 | }\r |
49ba9447 | 704 | \r |
79d274b8 LE |
705 | //\r |
706 | // We'd like to keep the following ranges uncached:\r | |
707 | // - [640 KB, 1 MB)\r | |
708 | // - [LowerMemorySize, 4 GB)\r | |
709 | //\r | |
710 | // Everything else should be WB. Unfortunately, programming the inverse (ie.\r | |
711 | // keeping the default UC, and configuring the complement set of the above as\r | |
712 | // WB) is not reliable in general, because the end of the upper RAM can have\r | |
713 | // practically any alignment, and we may not have enough variable MTRRs to\r | |
714 | // cover it exactly.\r | |
715 | //\r | |
716 | if (IsMtrrSupported ()) {\r | |
717 | MtrrGetAllMtrrs (&MtrrSettings);\r | |
718 | \r | |
719 | //\r | |
720 | // MTRRs disabled, fixed MTRRs disabled, default type is uncached\r | |
721 | //\r | |
722 | ASSERT ((MtrrSettings.MtrrDefType & BIT11) == 0);\r | |
723 | ASSERT ((MtrrSettings.MtrrDefType & BIT10) == 0);\r | |
724 | ASSERT ((MtrrSettings.MtrrDefType & 0xFF) == 0);\r | |
725 | \r | |
726 | //\r | |
727 | // flip default type to writeback\r | |
728 | //\r | |
729 | SetMem (&MtrrSettings.Fixed, sizeof MtrrSettings.Fixed, 0x06);\r | |
730 | ZeroMem (&MtrrSettings.Variables, sizeof MtrrSettings.Variables);\r | |
731 | MtrrSettings.MtrrDefType |= BIT11 | BIT10 | 6;\r | |
732 | MtrrSetAllMtrrs (&MtrrSettings);\r | |
e8e5cd4a | 733 | \r |
79d274b8 LE |
734 | //\r |
735 | // Set memory range from 640KB to 1MB to uncacheable\r | |
736 | //\r | |
737 | Status = MtrrSetMemoryAttribute (BASE_512KB + BASE_128KB,\r | |
738 | BASE_1MB - (BASE_512KB + BASE_128KB), CacheUncacheable);\r | |
739 | ASSERT_EFI_ERROR (Status);\r | |
e8e5cd4a | 740 | \r |
79d274b8 | 741 | //\r |
49edde15 LE |
742 | // Set the memory range from the start of the 32-bit MMIO area (32-bit PCI\r |
743 | // MMIO aperture on i440fx, PCIEXBAR on q35) to 4GB as uncacheable.\r | |
79d274b8 | 744 | //\r |
49edde15 LE |
745 | Status = MtrrSetMemoryAttribute (mQemuUc32Base, SIZE_4GB - mQemuUc32Base,\r |
746 | CacheUncacheable);\r | |
79d274b8 | 747 | ASSERT_EFI_ERROR (Status);\r |
c0e10976 | 748 | }\r |
49ba9447 | 749 | }\r |
750 | \r | |
c034906e JJ |
751 | /**\r |
752 | Publish system RAM and reserve memory regions\r | |
753 | \r | |
754 | **/\r | |
755 | VOID\r | |
756 | InitializeRamRegions (\r | |
757 | VOID\r | |
758 | )\r | |
759 | {\r | |
2818c158 JJ |
760 | if (!mXen) {\r |
761 | QemuInitializeRam ();\r | |
762 | } else {\r | |
2818c158 JJ |
763 | XenPublishRamRegions ();\r |
764 | }\r | |
8e54500f JJ |
765 | \r |
766 | if (mS3Supported && mBootMode != BOOT_ON_S3_RESUME) {\r | |
767 | //\r | |
768 | // This is the memory range that will be used for PEI on S3 resume\r | |
769 | //\r | |
770 | BuildMemoryAllocationHob (\r | |
45d87081 LE |
771 | mS3AcpiReservedMemoryBase,\r |
772 | mS3AcpiReservedMemorySize,\r | |
8e54500f JJ |
773 | EfiACPIMemoryNVS\r |
774 | );\r | |
e249f906 LE |
775 | \r |
776 | //\r | |
777 | // Cover the initial RAM area used as stack and temporary PEI heap.\r | |
778 | //\r | |
779 | // This is reserved as ACPI NVS so it can be used on S3 resume.\r | |
780 | //\r | |
781 | BuildMemoryAllocationHob (\r | |
782 | PcdGet32 (PcdOvmfSecPeiTempRamBase),\r | |
783 | PcdGet32 (PcdOvmfSecPeiTempRamSize),\r | |
784 | EfiACPIMemoryNVS\r | |
785 | );\r | |
78a38b73 | 786 | \r |
ad43bc6b LE |
787 | //\r |
788 | // SEC stores its table of GUIDed section handlers here.\r | |
789 | //\r | |
790 | BuildMemoryAllocationHob (\r | |
791 | PcdGet64 (PcdGuidedExtractHandlerTableAddress),\r | |
792 | PcdGet32 (PcdGuidedExtractHandlerTableSize),\r | |
793 | EfiACPIMemoryNVS\r | |
794 | );\r | |
795 | \r | |
78a38b73 LE |
796 | #ifdef MDE_CPU_X64\r |
797 | //\r | |
798 | // Reserve the initial page tables built by the reset vector code.\r | |
799 | //\r | |
800 | // Since this memory range will be used by the Reset Vector on S3\r | |
801 | // resume, it must be reserved as ACPI NVS.\r | |
802 | //\r | |
803 | BuildMemoryAllocationHob (\r | |
804 | (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfSecPageTablesBase),\r | |
805 | (UINT64)(UINTN) PcdGet32 (PcdOvmfSecPageTablesSize),\r | |
806 | EfiACPIMemoryNVS\r | |
807 | );\r | |
808 | #endif\r | |
0e8a31f5 | 809 | }\r |
6a7cba79 | 810 | \r |
0e8a31f5 | 811 | if (mBootMode != BOOT_ON_S3_RESUME) {\r |
1a7edbbc LE |
812 | if (!FeaturePcdGet (PcdSmmSmramRequire)) {\r |
813 | //\r | |
814 | // Reserve the lock box storage area\r | |
815 | //\r | |
816 | // Since this memory range will be used on S3 resume, it must be\r | |
817 | // reserved as ACPI NVS.\r | |
818 | //\r | |
819 | // If S3 is unsupported, then various drivers might still write to the\r | |
820 | // LockBox area. We ought to prevent DXE from serving allocation requests\r | |
821 | // such that they would overlap the LockBox storage.\r | |
822 | //\r | |
823 | ZeroMem (\r | |
824 | (VOID*)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),\r | |
825 | (UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize)\r | |
826 | );\r | |
827 | BuildMemoryAllocationHob (\r | |
828 | (EFI_PHYSICAL_ADDRESS)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageBase),\r | |
829 | (UINT64)(UINTN) PcdGet32 (PcdOvmfLockBoxStorageSize),\r | |
830 | mS3Supported ? EfiACPIMemoryNVS : EfiBootServicesData\r | |
831 | );\r | |
832 | }\r | |
b09c1c6f LE |
833 | \r |
834 | if (FeaturePcdGet (PcdSmmSmramRequire)) {\r | |
835 | UINT32 TsegSize;\r | |
836 | \r | |
837 | //\r | |
838 | // Make sure the TSEG area that we reported as a reserved memory resource\r | |
839 | // cannot be used for reserved memory allocations.\r | |
840 | //\r | |
23bfb5c0 | 841 | TsegSize = mQ35TsegMbytes * SIZE_1MB;\r |
b09c1c6f LE |
842 | BuildMemoryAllocationHob (\r |
843 | GetSystemMemorySizeBelow4gb() - TsegSize,\r | |
844 | TsegSize,\r | |
845 | EfiReservedMemoryType\r | |
846 | );\r | |
847 | }\r | |
8e54500f | 848 | }\r |
c034906e | 849 | }\r |