[mirror_edk2.git] / QuarkSocPkg / QuarkSocPkg.dec

## @file\r
# INTEL Quark SoC Module Package Reference Implementations\r
#\r
# This Module provides FRAMEWORK reference implementation for INTEL Quark SoC.\r
# Copyright (c) 2013-2015 Intel Corporation.\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution.  The full text of the license may be found at\r
# http://opensource.org/licenses/bsd-license.php\r
#\r
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
#\r
##\r
\r
\r
################################################################################\r
#\r
# Defines Section - statements that will be processed to create a Makefile.\r
#\r
################################################################################\r
\r
[Defines]\r
  DEC_SPECIFICATION              = 0x00010005\r
  PACKAGE_NAME                   = QuarkSocPkg\r
  PACKAGE_GUID                   = 28DECF17-6C75-448f-87DC-BDE4BD579919\r
  PACKAGE_VERSION                = 0.1\r
\r
\r
\r
################################################################################\r
#\r
# Include Section - list of Include Paths that are provided by this package.\r
#                   Comments are used for Keywords and Module Types.\r
#\r
# Supported Module Types:\r
#  SEC PEIM DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER BASE\r
#\r
################################################################################\r
[Includes]\r
  #\r
  # North Cluster\r
  #\r
  QuarkNorthCluster/Include\r
  QuarkNorthCluster/MemoryInit/Pei\r
\r
  #\r
  # South Cluster\r
  #\r
  QuarkSouthCluster/Include\r
\r
################################################################################\r
#\r
# Library Class Header section - list of Library Class header files that are\r
#                                provided by this package.\r
#\r
################################################################################\r
[LibraryClasses]\r
  #\r
  # North Cluster\r
  #\r
  QNCAccessLib|QuarkNorthCluster/Include/Library/QNCAccessLib.h\r
  IntelQNCLib|QuarkNorthCluster/Include/Library/IntelQNCLib.h\r
  IohLib|QuarkSouthCluster/Include/Library/IohLib.h\r
  I2cLib|QuarkSouthCluster/Include/Library/I2cLib.h\r
\r
################################################################################\r
#\r
# Global Guid Definition section - list of Global Guid C Name Data Structures\r
#                                  that are provided by this package.\r
#\r
################################################################################\r
[Guids]\r
  #\r
  # North Cluster\r
  #\r
  gEfiQuarkNcSocIdTokenSpaceGuid  = { 0xca452c6a, 0xdf0c, 0x4dc9, { 0x82, 0xfb, 0xea, 0xe2, 0xab, 0x31, 0x29, 0x46 }}\r
  gQncS3CodeInLockBoxGuid   =  { 0x1f18c5b3, 0x29ed, 0x4d9e, {0xa5, 0x4, 0x6d, 0x97, 0x8e, 0x7e, 0xd5, 0x69}}\r
  gQncS3ContextInLockBoxGuid = { 0xe5769ea9, 0xe706, 0x454b, {0x95, 0x7f, 0xaf, 0xc6, 0xdb, 0x4b, 0x8a, 0xd}}\r
\r
  #\r
  # South Cluster\r
  #\r
  gEfiQuarkSCSocIdTokenSpaceGuid  = { 0xef251b71, 0xceed, 0x484e, { 0x82, 0xe3, 0x3a, 0x1f, 0x34, 0xf5, 0x12, 0xe2 }}\r
\r
################################################################################\r
#\r
# Global Ppi Definition section - list of Global Ppi C Name Data Structures\r
#                                  that are provided by this package.\r
#\r
################################################################################\r
[Ppis]\r
  #\r
  # North Cluster\r
  #\r
  gQNCMemoryInitPpiGuid = { 0x21ff1fee, 0xd33a, 0x4fce, { 0xa6, 0x5e, 0x95, 0x5e, 0xa3, 0xc4, 0x1f, 0x40}}\r
\r
################################################################################\r
#\r
# Global Protocols Definition section - list of Global Protocols C Name Data\r
#                                  Structures that are provided by this package.\r
#\r
################################################################################\r
[Protocols]\r
  #\r
  # North Cluster\r
  #\r
  gEfiPlatformPolicyProtocolGuid = { 0x2977064F, 0xAB96, 0x4FA9, { 0x85, 0x45, 0xF9, 0xC4, 0x02, 0x51, 0xE0, 0x7F }}\r
  gEfiSmmIchnDispatch2ProtocolGuid = { 0xadf3a128, 0x416d, 0x4060, { 0x8d, 0xdf, 0x30, 0xa1, 0xd7, 0xaa, 0xb6, 0x99 }}\r
  gEfiSpiProtocolGuid = { 0x1156efc6, 0xea32, 0x4396, { 0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13 }}\r
  gEfiSmmSpiProtocolGuid  = { 0xD9072C35, 0xEB8F, 0x43ad, { 0xA2, 0x20, 0x34, 0xD4, 0x0E, 0x2A, 0x82, 0x85 }}\r
  gEfiQncS3SupportProtocolGuid  = { 0xe287d20b, 0xd897, 0x4e1e, { 0xa5, 0xd9, 0x97, 0x77, 0x63, 0x93, 0x6a, 0x4 }}\r
\r
  #\r
  # South Cluster\r
  #\r
  gEfiSDHostIoProtocolGuid = {0xb63f8ec7, 0xa9c9, 0x4472, {0xa4, 0xc0, 0x4d, 0x8b, 0xf3, 0x65, 0xcc, 0x51}}\r
\r
################################################################################\r
#\r
# PCD Declarations section - list of all PCDs Declared by this Package\r
#                            Only this package should be providing the\r
#                            declaration, other packages should not.\r
#\r
################################################################################\r
\r
[PcdsFeatureFlag]\r
  #\r
  # North Cluster\r
  #\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdSmbaIoBaseAddressFixed|TRUE|BOOLEAN|0x10000001\r
\r
  #\r
  # South Cluster\r
  #\r
  gEfiQuarkSCSocIdTokenSpaceGuid.PcdEhciRecoveryEnabled|FALSE|BOOLEAN|0x10000003\r
  gEfiQuarkSCSocIdTokenSpaceGuid.PcdI2CFastModeEnabled|FALSE|BOOLEAN|0x10000005\r
\r
  #\r
  # Feature Flag equivalent to linux SDHCI_QUIRK_NO_HISPD_BIT to stop\r
  # setting of SD HCI hi_spd_en bit in HOST_CTL register.\r
  #\r
  # Alway TRUE ie high speed enable bit must never\r
  # be set so we stay within SD interface Setup/Hold time.\r
  #\r
  gEfiQuarkSCSocIdTokenSpaceGuid.PcdSdHciQuirkNoHiSpd|TRUE|BOOLEAN|0x10000004\r
\r
[PcdsFixedAtBuild]\r
  #\r
  # North Cluster\r
  #\r
\r
  # Values of Io Port Base Address, MMIO base address and space size.\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdPm1blkIoBaseAddress|0x1000|UINT16|0x10000200\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdPmbaIoBaseAddress|0x1010|UINT16|0x10000201\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdPmbaIoLVL2|0x1014|UINT16|0x10000202\r
\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdGbaIoBaseAddress|0x1080|UINT16|0x10000205\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdGpe0blkIoBaseAddress|0x1100|UINT16|0x10000206\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdSmbaIoBaseAddress|0x1040|UINT16|0x10000207\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdWdtbaIoBaseAddress|0x1140|UINT16|0x10000209\r
\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdRcbaMmioBaseAddress|0xFED1C000|UINT64|0x1000020B\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdIoApicBaseAddress|0xFEC00000|UINT64|0x1000020C\r
\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdIoApicSize|0x1000|UINT64|0x1000020D\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdRcbaMmioSize|0x4000|UINT64|0x1000020E\r
\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciExpressSize|0x02000000|UINT64|0x1000020F\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdHpetBaseAddress|0xFED00000|UINT64|0x10000210\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdHpetSize|0x400|UINT64|0x10000211\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdTSegSize|0x200000|UINT32|0x10000212\r
\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeIoBase|0x2000|UINT16|0x10000214\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeIoSize|0xE000|UINT16|0x10000215\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory32Base|0x90000000|UINT32|0x1000021B\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory32Size|0x20000000|UINT32|0x1000021C\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory64Base|0xB0000000|UINT64|0x1000021D\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory64Size|0x30000000|UINT64|0x1000021E\r
\r
  # Values for programming Interrupt Route Configuration Registers:\r
  # Indicates which interrupt routing is connected to the INTA/B/C/D pins reported in the\r
  # "DxIP" register fields. This will be the internal routing, the device interrupt is connected\r
  # to the interrupt controller.\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkAgent0IR|0x0000|UINT16|0x10000223\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkAgent1IR|0x7654|UINT16|0x10000224\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkAgent2IR|0x0000|UINT16|0x10000225\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkAgent3IR|0x3210|UINT16|0x10000226\r
\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdSmmActivationPort|0xb2|UINT16|0x10000232\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdSmmDataPort|0xb3|UINT16|0x10000233\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdSmmActivationData|0x55|UINT8|0x10000234\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdPlatformSmbusAddrNum|0x0|UINT32|0x10000235\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdPlatformSmbusAddrTable|0x0|UINT64|0x10000236\r
\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdESramMemorySize|0x00080000|UINT32|0x10000240\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdDeviceEnables|0x03|UINT32|0x10000237\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdPcieRootPortConfiguration|{0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00}|VOID*|0x10000239\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkMicrocodeFile |{ 0x8B, 0xEA, 0x5E, 0xD7, 0xD2, 0x23, 0xD4, 0x4E, 0xBC, 0x4F, 0x57, 0x51, 0xD4, 0xA1, 0x8D, 0xCF }|VOID*|0x1000023A\r
\r
  #\r
  # South Cluster\r
  #\r
  gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohI2cMmioBase|0xA001F000|UINT64|0x20000005\r
  gEfiQuarkSCSocIdTokenSpaceGuid.PcdPeiP2PMemoryBaseAddress|0xA0000000|UINT32|0x20000006\r
  gEfiQuarkSCSocIdTokenSpaceGuid.PcdPeiQNCUsbControllerMemoryBaseAddress|0xA0010000|UINT32|0x20000007\r
  gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioMmioBase|0xA0020000|UINT64|0x20000008\r
  gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohMac0MmioBase|0xA0024000|UINT64|0x20000009\r
  gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohMac1MmioBase|0xA0028000|UINT64|0x2000000A\r
\r
  gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohUartBusNumber|0x00|UINT8|0x20000013\r
  gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohUartDevNumber|0x14|UINT8|0x20000014\r
  gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohUartFunctionNumber|0x5|UINT8|0x20000001\r
  gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioBusNumber|0x00|UINT8|0x20000029\r
  gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioDevNumber|0x15|UINT8|0x2000002A\r
  gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioFunctionNumber|0x2|UINT8|0x2000002B\r
  gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioBarRegister|0x14|UINT8|0x2000002D\r
\r
[PcdsDynamic, PcdsDynamicEx]\r
  #\r
  # North Cluster\r
  #\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdQncS3CodeInLockBoxAddress|0|UINT64|0x30000026\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdQncS3CodeInLockBoxSize|0|UINT64|0x30000027\r
\r
  ## Intel(R) Quark(TM) Soc X1000 processor MRC Parameters.  Default is for Galileo Gen 2 platform.<BR><BR>\r
  # @Prompt Intel(R) Quark(TM) Soc X1000 processor MRC Parameters.\r
  gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters|{0x08, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x01, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06}|VOID*|0x40000001\r
\r
  #\r
  # South Cluster\r
  #\r
  ## MAC0 address for the Ethernet Controller in Intel(R) Quark(TM) Soc X1000 processor.  Default is 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff.<BR><BR>\r
  # @Prompt Ethernet MAC 0 Address.\r
  gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohEthernetMac0|{0xff, 0xff, 0xff, 0xff, 0xff, 0xff}|VOID*|0x50000001\r
\r
  ## MAC1 address for the Ethernet Controller in Intel(R) Quark(TM) Soc X1000 processor.  Default is 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff.<BR><BR>\r
  # @Prompt Ethernet MAC 1 Address.\r
  gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohEthernetMac1|{0xff, 0xff, 0xff, 0xff, 0xff, 0xff}|VOID*|0x50000002\r
Commit	Line	Data
9b6bbcdb MK	1	## @file\r
	2	# INTEL Quark SoC Module Package Reference Implementations\r
	3	#\r
	4	# This Module provides FRAMEWORK reference implementation for INTEL Quark SoC.\r
	5	# Copyright (c) 2013-2015 Intel Corporation.\r
	6	#\r
	7	# This program and the accompanying materials\r
	8	# are licensed and made available under the terms and conditions of the BSD License\r
	9	# which accompanies this distribution. The full text of the license may be found at\r
	10	# http://opensource.org/licenses/bsd-license.php\r
	11	#\r
	12	# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	13	# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	14	#\r
	15	##\r
	16	\r
	17	\r
	18	################################################################################\r
	19	#\r
	20	# Defines Section - statements that will be processed to create a Makefile.\r
	21	#\r
	22	################################################################################\r
	23	\r
	24	[Defines]\r
	25	DEC_SPECIFICATION = 0x00010005\r
	26	PACKAGE_NAME = QuarkSocPkg\r
	27	PACKAGE_GUID = 28DECF17-6C75-448f-87DC-BDE4BD579919\r
	28	PACKAGE_VERSION = 0.1\r
	29	\r
	30	\r
	31	\r
	32	################################################################################\r
	33	#\r
	34	# Include Section - list of Include Paths that are provided by this package.\r
	35	# Comments are used for Keywords and Module Types.\r
	36	#\r
	37	# Supported Module Types:\r
	38	# SEC PEIM DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER BASE\r
	39	#\r
	40	################################################################################\r
	41	[Includes]\r
	42	#\r
	43	# North Cluster\r
	44	#\r
	45	QuarkNorthCluster/Include\r
	46	QuarkNorthCluster/MemoryInit/Pei\r
	47	\r
	48	#\r
	49	# South Cluster\r
	50	#\r
	51	QuarkSouthCluster/Include\r
	52	\r
	53	################################################################################\r
	54	#\r
	55	# Library Class Header section - list of Library Class header files that are\r
	56	# provided by this package.\r
	57	#\r
	58	################################################################################\r
	59	[LibraryClasses]\r
	60	#\r
	61	# North Cluster\r
	62	#\r
	63	QNCAccessLib\|QuarkNorthCluster/Include/Library/QNCAccessLib.h\r
	64	IntelQNCLib\|QuarkNorthCluster/Include/Library/IntelQNCLib.h\r
65	IohLib\|QuarkSouthCluster/Include/Library/IohLib.h\r
66	I2cLib\|QuarkSouthCluster/Include/Library/I2cLib.h\r
67	\r
68	################################################################################\r
69	#\r
70	# Global Guid Definition section - list of Global Guid C Name Data Structures\r
71	# that are provided by this package.\r
72	#\r
73	################################################################################\r
74	[Guids]\r
75	#\r
76	# North Cluster\r
77	#\r
78	gEfiQuarkNcSocIdTokenSpaceGuid = { 0xca452c6a, 0xdf0c, 0x4dc9, { 0x82, 0xfb, 0xea, 0xe2, 0xab, 0x31, 0x29, 0x46 }}\r
79	gQncS3CodeInLockBoxGuid = { 0x1f18c5b3, 0x29ed, 0x4d9e, {0xa5, 0x4, 0x6d, 0x97, 0x8e, 0x7e, 0xd5, 0x69}}\r
80	gQncS3ContextInLockBoxGuid = { 0xe5769ea9, 0xe706, 0x454b, {0x95, 0x7f, 0xaf, 0xc6, 0xdb, 0x4b, 0x8a, 0xd}}\r
81	\r
82	#\r
83	# South Cluster\r
84	#\r
85	gEfiQuarkSCSocIdTokenSpaceGuid = { 0xef251b71, 0xceed, 0x484e, { 0x82, 0xe3, 0x3a, 0x1f, 0x34, 0xf5, 0x12, 0xe2 }}\r
86	\r
87	################################################################################\r
88	#\r
89	# Global Ppi Definition section - list of Global Ppi C Name Data Structures\r
90	# that are provided by this package.\r
91	#\r
92	################################################################################\r
93	[Ppis]\r
94	#\r
95	# North Cluster\r
96	#\r
97	gQNCMemoryInitPpiGuid = { 0x21ff1fee, 0xd33a, 0x4fce, { 0xa6, 0x5e, 0x95, 0x5e, 0xa3, 0xc4, 0x1f, 0x40}}\r
98	\r
99	################################################################################\r
100	#\r
101	# Global Protocols Definition section - list of Global Protocols C Name Data\r
102	# Structures that are provided by this package.\r
103	#\r
104	################################################################################\r
105	[Protocols]\r
106	#\r
107	# North Cluster\r
108	#\r
109	gEfiPlatformPolicyProtocolGuid = { 0x2977064F, 0xAB96, 0x4FA9, { 0x85, 0x45, 0xF9, 0xC4, 0x02, 0x51, 0xE0, 0x7F }}\r
110	gEfiSmmIchnDispatch2ProtocolGuid = { 0xadf3a128, 0x416d, 0x4060, { 0x8d, 0xdf, 0x30, 0xa1, 0xd7, 0xaa, 0xb6, 0x99 }}\r
111	gEfiSpiProtocolGuid = { 0x1156efc6, 0xea32, 0x4396, { 0xb5, 0xd5, 0x26, 0x93, 0x2e, 0x83, 0xc3, 0x13 }}\r
112	gEfiSmmSpiProtocolGuid = { 0xD9072C35, 0xEB8F, 0x43ad, { 0xA2, 0x20, 0x34, 0xD4, 0x0E, 0x2A, 0x82, 0x85 }}\r
113	gEfiQncS3SupportProtocolGuid = { 0xe287d20b, 0xd897, 0x4e1e, { 0xa5, 0xd9, 0x97, 0x77, 0x63, 0x93, 0x6a, 0x4 }}\r
114	\r
115	#\r
116	# South Cluster\r
117	#\r
118	gEfiSDHostIoProtocolGuid = {0xb63f8ec7, 0xa9c9, 0x4472, {0xa4, 0xc0, 0x4d, 0x8b, 0xf3, 0x65, 0xcc, 0x51}}\r
119	\r
120	################################################################################\r
121	#\r
122	# PCD Declarations section - list of all PCDs Declared by this Package\r
123	# Only this package should be providing the\r
124	# declaration, other packages should not.\r
125	#\r
126	################################################################################\r
127	\r
128	[PcdsFeatureFlag]\r
129	#\r
130	# North Cluster\r
131	#\r
132	gEfiQuarkNcSocIdTokenSpaceGuid.PcdSmbaIoBaseAddressFixed\|TRUE\|BOOLEAN\|0x10000001\r
133	\r
134	#\r
135	# South Cluster\r
136	#\r
137	gEfiQuarkSCSocIdTokenSpaceGuid.PcdEhciRecoveryEnabled\|FALSE\|BOOLEAN\|0x10000003\r
138	gEfiQuarkSCSocIdTokenSpaceGuid.PcdI2CFastModeEnabled\|FALSE\|BOOLEAN\|0x10000005\r
139	\r
140	#\r
141	# Feature Flag equivalent to linux SDHCI_QUIRK_NO_HISPD_BIT to stop\r
142	# setting of SD HCI hi_spd_en bit in HOST_CTL register.\r
143	#\r
144	# Alway TRUE ie high speed enable bit must never\r
145	# be set so we stay within SD interface Setup/Hold time.\r
146	#\r
147	gEfiQuarkSCSocIdTokenSpaceGuid.PcdSdHciQuirkNoHiSpd\|TRUE\|BOOLEAN\|0x10000004\r
148	\r
149	[PcdsFixedAtBuild]\r
150	#\r
151	# North Cluster\r
152	#\r
153	\r
154	# Values of Io Port Base Address, MMIO base address and space size.\r
155	gEfiQuarkNcSocIdTokenSpaceGuid.PcdPm1blkIoBaseAddress\|0x1000\|UINT16\|0x10000200\r
156	gEfiQuarkNcSocIdTokenSpaceGuid.PcdPmbaIoBaseAddress\|0x1010\|UINT16\|0x10000201\r
157	gEfiQuarkNcSocIdTokenSpaceGuid.PcdPmbaIoLVL2\|0x1014\|UINT16\|0x10000202\r
158	\r
159	gEfiQuarkNcSocIdTokenSpaceGuid.PcdGbaIoBaseAddress\|0x1080\|UINT16\|0x10000205\r
160	gEfiQuarkNcSocIdTokenSpaceGuid.PcdGpe0blkIoBaseAddress\|0x1100\|UINT16\|0x10000206\r
161	gEfiQuarkNcSocIdTokenSpaceGuid.PcdSmbaIoBaseAddress\|0x1040\|UINT16\|0x10000207\r
162	gEfiQuarkNcSocIdTokenSpaceGuid.PcdWdtbaIoBaseAddress\|0x1140\|UINT16\|0x10000209\r
163	\r
164	gEfiQuarkNcSocIdTokenSpaceGuid.PcdRcbaMmioBaseAddress\|0xFED1C000\|UINT64\|0x1000020B\r
165	gEfiQuarkNcSocIdTokenSpaceGuid.PcdIoApicBaseAddress\|0xFEC00000\|UINT64\|0x1000020C\r
166	\r
167	gEfiQuarkNcSocIdTokenSpaceGuid.PcdIoApicSize\|0x1000\|UINT64\|0x1000020D\r
168	gEfiQuarkNcSocIdTokenSpaceGuid.PcdRcbaMmioSize\|0x4000\|UINT64\|0x1000020E\r
169	\r
170	gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciExpressSize\|0x02000000\|UINT64\|0x1000020F\r
171	gEfiQuarkNcSocIdTokenSpaceGuid.PcdHpetBaseAddress\|0xFED00000\|UINT64\|0x10000210\r
172	gEfiQuarkNcSocIdTokenSpaceGuid.PcdHpetSize\|0x400\|UINT64\|0x10000211\r
173	gEfiQuarkNcSocIdTokenSpaceGuid.PcdTSegSize\|0x200000\|UINT32\|0x10000212\r
174	\r
175	gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeIoBase\|0x2000\|UINT16\|0x10000214\r
176	gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeIoSize\|0xE000\|UINT16\|0x10000215\r
177	gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory32Base\|0x90000000\|UINT32\|0x1000021B\r
178	gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory32Size\|0x20000000\|UINT32\|0x1000021C\r
179	gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory64Base\|0xB0000000\|UINT64\|0x1000021D\r
180	gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory64Size\|0x30000000\|UINT64\|0x1000021E\r
181	\r
182	# Values for programming Interrupt Route Configuration Registers:\r
183	# Indicates which interrupt routing is connected to the INTA/B/C/D pins reported in the\r
184	# "DxIP" register fields. This will be the internal routing, the device interrupt is connected\r
185	# to the interrupt controller.\r
186	gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkAgent0IR\|0x0000\|UINT16\|0x10000223\r
187	gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkAgent1IR\|0x7654\|UINT16\|0x10000224\r
188	gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkAgent2IR\|0x0000\|UINT16\|0x10000225\r
189	gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkAgent3IR\|0x3210\|UINT16\|0x10000226\r
190	\r
191	gEfiQuarkNcSocIdTokenSpaceGuid.PcdSmmActivationPort\|0xb2\|UINT16\|0x10000232\r
192	gEfiQuarkNcSocIdTokenSpaceGuid.PcdSmmDataPort\|0xb3\|UINT16\|0x10000233\r
193	gEfiQuarkNcSocIdTokenSpaceGuid.PcdSmmActivationData\|0x55\|UINT8\|0x10000234\r
194	gEfiQuarkNcSocIdTokenSpaceGuid.PcdPlatformSmbusAddrNum\|0x0\|UINT32\|0x10000235\r
195	gEfiQuarkNcSocIdTokenSpaceGuid.PcdPlatformSmbusAddrTable\|0x0\|UINT64\|0x10000236\r
196	\r
197	gEfiQuarkNcSocIdTokenSpaceGuid.PcdESramMemorySize\|0x00080000\|UINT32\|0x10000240\r
198	gEfiQuarkNcSocIdTokenSpaceGuid.PcdDeviceEnables\|0x03\|UINT32\|0x10000237\r
199	gEfiQuarkNcSocIdTokenSpaceGuid.PcdPcieRootPortConfiguration\|{0x00, 0x01, 0x01, 0x00, 0x00, 0x01, 0x02, 0x00}\|VOID*\|0x10000239\r
200	gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkMicrocodeFile \|{ 0x8B, 0xEA, 0x5E, 0xD7, 0xD2, 0x23, 0xD4, 0x4E, 0xBC, 0x4F, 0x57, 0x51, 0xD4, 0xA1, 0x8D, 0xCF }\|VOID*\|0x1000023A\r
201	\r
202	#\r
203	# South Cluster\r
204	#\r
205	gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohI2cMmioBase\|0xA001F000\|UINT64\|0x20000005\r
206	gEfiQuarkSCSocIdTokenSpaceGuid.PcdPeiP2PMemoryBaseAddress\|0xA0000000\|UINT32\|0x20000006\r
207	gEfiQuarkSCSocIdTokenSpaceGuid.PcdPeiQNCUsbControllerMemoryBaseAddress\|0xA0010000\|UINT32\|0x20000007\r
208	gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioMmioBase\|0xA0020000\|UINT64\|0x20000008\r
209	gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohMac0MmioBase\|0xA0024000\|UINT64\|0x20000009\r
210	gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohMac1MmioBase\|0xA0028000\|UINT64\|0x2000000A\r
211	\r
212	gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohUartBusNumber\|0x00\|UINT8\|0x20000013\r
213	gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohUartDevNumber\|0x14\|UINT8\|0x20000014\r
214	gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohUartFunctionNumber\|0x5\|UINT8\|0x20000001\r
215	gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioBusNumber\|0x00\|UINT8\|0x20000029\r
216	gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioDevNumber\|0x15\|UINT8\|0x2000002A\r
217	gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioFunctionNumber\|0x2\|UINT8\|0x2000002B\r
218	gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioBarRegister\|0x14\|UINT8\|0x2000002D\r
219	\r
220	[PcdsDynamic, PcdsDynamicEx]\r
221	#\r
222	# North Cluster\r
223	#\r
224	gEfiQuarkNcSocIdTokenSpaceGuid.PcdQncS3CodeInLockBoxAddress\|0\|UINT64\|0x30000026\r
225	gEfiQuarkNcSocIdTokenSpaceGuid.PcdQncS3CodeInLockBoxSize\|0\|UINT64\|0x30000027\r
226	\r
227	## Intel(R) Quark(TM) Soc X1000 processor MRC Parameters. Default is for Galileo Gen 2 platform.<BR><BR>\r
228	# @Prompt Intel(R) Quark(TM) Soc X1000 processor MRC Parameters.\r
229	gEfiQuarkNcSocIdTokenSpaceGuid.PcdMrcParameters\|{0x08, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x00, 0x01, 0x01, 0x01, 0x7c, 0x92, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x10, 0x27, 0x00, 0x00, 0x40, 0x9c, 0x00, 0x00, 0x06}\|VOID*\|0x40000001\r
230	\r
231	#\r
232	# South Cluster\r
233	#\r
234	## MAC0 address for the Ethernet Controller in Intel(R) Quark(TM) Soc X1000 processor. Default is 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff.<BR><BR>\r
235	# @Prompt Ethernet MAC 0 Address.\r
236	gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohEthernetMac0\|{0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\|VOID*\|0x50000001\r
237	\r
238	## MAC1 address for the Ethernet Controller in Intel(R) Quark(TM) Soc X1000 processor. Default is 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff.<BR><BR>\r
239	# @Prompt Ethernet MAC 1 Address.\r
240	gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohEthernetMac1\|{0xff, 0xff, 0xff, 0xff, 0xff, 0xff}\|VOID*\|0x50000002\r