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1 | /** @file\r |
2 | This header file provides common definitions just for MCH using to avoid including extra module's file.\r | |
3 | \r | |
4 | Copyright (c) 2013-2015 Intel Corporation.\r | |
5 | \r | |
6 | This program and the accompanying materials\r | |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #ifndef _IOH_COMMON_DEFINITIONS_H_\r | |
17 | #define _IOH_COMMON_DEFINITIONS_H_\r | |
18 | \r | |
19 | //\r | |
20 | // PCI CONFIGURATION MAP REGISTER OFFSETS\r | |
21 | //\r | |
22 | #ifndef PCI_VID\r | |
23 | #define PCI_VID 0x0000 // Vendor ID Register\r | |
24 | #define PCI_DID 0x0002 // Device ID Register\r | |
25 | #define PCI_CMD 0x0004 // PCI Command Register\r | |
26 | #define PCI_STS 0x0006 // PCI Status Register\r | |
27 | #define PCI_RID 0x0008 // Revision ID Register\r | |
28 | #define PCI_IFT 0x0009 // Interface Type\r | |
29 | #define PCI_SCC 0x000A // Sub Class Code Register\r | |
30 | #define PCI_BCC 0x000B // Base Class Code Register\r | |
31 | #define PCI_CLS 0x000C // Cache Line Size\r | |
32 | #define PCI_PMLT 0x000D // Primary Master Latency Timer\r | |
33 | #define PCI_HDR 0x000E // Header Type Register\r | |
34 | #define PCI_BIST 0x000F // Built in Self Test Register\r | |
35 | #define PCI_BAR0 0x0010 // Base Address Register 0\r | |
36 | #define PCI_BAR1 0x0014 // Base Address Register 1\r | |
37 | #define PCI_BAR2 0x0018 // Base Address Register 2\r | |
38 | #define PCI_PBUS 0x0018 // Primary Bus Number Register\r | |
39 | #define PCI_SBUS 0x0019 // Secondary Bus Number Register\r | |
40 | #define PCI_SUBUS 0x001A // Subordinate Bus Number Register\r | |
41 | #define PCI_SMLT 0x001B // Secondary Master Latency Timer\r | |
42 | #define PCI_BAR3 0x001C // Base Address Register 3\r | |
43 | #define PCI_IOBASE 0x001C // I/O base Register\r | |
44 | #define PCI_IOLIMIT 0x001D // I/O Limit Register\r | |
45 | #define PCI_SECSTATUS 0x001E // Secondary Status Register\r | |
46 | #define PCI_BAR4 0x0020 // Base Address Register 4\r | |
47 | #define PCI_MEMBASE 0x0020 // Memory Base Register\r | |
48 | #define PCI_MEMLIMIT 0x0022 // Memory Limit Register\r | |
49 | #define PCI_BAR5 0x0024 // Base Address Register 5\r | |
50 | #define PCI_PRE_MEMBASE 0x0024 // Prefetchable memory Base register\r | |
51 | #define PCI_PRE_MEMLIMIT 0x0026 // Prefetchable memory Limit register\r | |
52 | #define PCI_PRE_MEMBASE_U 0x0028 // Prefetchable memory base upper 32 bits\r | |
53 | #define PCI_PRE_MEMLIMIT_U 0x002C // Prefetchable memory limit upper 32 bits\r | |
54 | #define PCI_SVID 0x002C // Subsystem Vendor ID\r | |
55 | #define PCI_SID 0x002E // Subsystem ID\r | |
56 | #define PCI_IOBASE_U 0x0030 // I/O base Upper Register\r | |
57 | #define PCI_IOLIMIT_U 0x0032 // I/O Limit Upper Register\r | |
58 | #define PCI_CAPP 0x0034 // Capabilities Pointer\r | |
59 | #define PCI_EROM 0x0038 // Expansion ROM Base Address\r | |
60 | #define PCI_INTLINE 0x003C // Interrupt Line Register\r | |
61 | #define PCI_INTPIN 0x003D // Interrupt Pin Register\r | |
62 | #define PCI_MAXGNT 0x003E // Max Grant Register\r | |
63 | #define PCI_BRIDGE_CNTL 0x003E // Bridge Control Register\r | |
64 | #define PCI_MAXLAT 0x003F // Max Latency Register\r | |
65 | #endif\r | |
66 | //\r | |
67 | // Bit Difinitions\r | |
68 | //\r | |
69 | #ifndef BIT0\r | |
70 | #define BIT0 0x0001\r | |
71 | #define BIT1 0x0002\r | |
72 | #define BIT2 0x0004\r | |
73 | #define BIT3 0x0008\r | |
74 | #define BIT4 0x0010\r | |
75 | #define BIT5 0x0020\r | |
76 | #define BIT6 0x0040\r | |
77 | #define BIT7 0x0080\r | |
78 | #define BIT8 0x0100\r | |
79 | #define BIT9 0x0200\r | |
80 | #define BIT10 0x0400\r | |
81 | #define BIT11 0x0800\r | |
82 | #define BIT12 0x1000\r | |
83 | #define BIT13 0x2000\r | |
84 | #define BIT14 0x4000\r | |
85 | #define BIT15 0x8000\r | |
86 | #define BIT16 0x00010000\r | |
87 | #define BIT17 0x00020000\r | |
88 | #define BIT18 0x00040000\r | |
89 | #define BIT19 0x00080000\r | |
90 | #define BIT20 0x00100000\r | |
91 | #define BIT21 0x00200000\r | |
92 | #define BIT22 0x00400000\r | |
93 | #define BIT23 0x00800000\r | |
94 | #define BIT24 0x01000000\r | |
95 | #define BIT25 0x02000000\r | |
96 | #define BIT26 0x04000000\r | |
97 | #define BIT27 0x08000000\r | |
98 | #define BIT28 0x10000000\r | |
99 | #define BIT29 0x20000000\r | |
100 | #define BIT30 0x40000000\r | |
101 | #define BIT31 0x80000000\r | |
102 | #endif\r | |
103 | \r | |
104 | \r | |
105 | //\r | |
106 | // Common Memory mapped Io access macros ------------------------------------------\r | |
107 | //\r | |
108 | #define IohMmioAddress( BaseAddr, Register ) \\r | |
109 | ( (UINTN)BaseAddr + \\r | |
110 | (UINTN)(Register) \\r | |
111 | )\r | |
112 | \r | |
113 | //\r | |
114 | // UINT64\r | |
115 | //\r | |
116 | #define IohMmio64Ptr( BaseAddr, Register ) \\r | |
117 | ( (volatile UINT64 *)IohMmioAddress( BaseAddr, Register ) )\r | |
118 | \r | |
119 | #define IohMmio64( BaseAddr, Register ) \\r | |
120 | *IohMmio64Ptr( BaseAddr, Register )\r | |
121 | \r | |
122 | #define IohMmio64Or( BaseAddr, Register, OrData ) \\r | |
123 | IohMmio64( BaseAddr, Register ) = \\r | |
124 | (UINT64) ( \\r | |
125 | IohMmio64( BaseAddr, Register ) | \\r | |
126 | (UINT64)(OrData) \\r | |
127 | )\r | |
128 | \r | |
129 | #define IohMmio64And( BaseAddr, Register, AndData ) \\r | |
130 | IohMmio64( BaseAddr, Register ) = \\r | |
131 | (UINT64) ( \\r | |
132 | IohMmio64( BaseAddr, Register ) & \\r | |
133 | (UINT64)(AndData) \\r | |
134 | )\r | |
135 | \r | |
136 | #define IohMmio64AndThenOr( BaseAddr, Register, AndData, OrData ) \\r | |
137 | IohMmio64( BaseAddr, Register ) = \\r | |
138 | (UINT64) ( \\r | |
139 | ( IohMmio64( BaseAddr, Register ) & \\r | |
140 | (UINT64)(AndData) \\r | |
141 | ) | \\r | |
142 | (UINT64)(OrData) \\r | |
143 | )\r | |
144 | \r | |
145 | //\r | |
146 | // UINT32\r | |
147 | //\r | |
148 | #define IohMmio32Ptr( BaseAddr, Register ) \\r | |
149 | ( (volatile UINT32 *)IohMmioAddress( BaseAddr, Register ) )\r | |
150 | \r | |
151 | #define IohMmio32( BaseAddr, Register ) \\r | |
152 | *IohMmio32Ptr( BaseAddr, Register )\r | |
153 | \r | |
154 | #define IohMmio32Or( BaseAddr, Register, OrData ) \\r | |
155 | IohMmio32( BaseAddr, Register ) = \\r | |
156 | (UINT32) ( \\r | |
157 | IohMmio32( BaseAddr, Register ) | \\r | |
158 | (UINT32)(OrData) \\r | |
159 | )\r | |
160 | \r | |
161 | #define IohMmio32And( BaseAddr, Register, AndData ) \\r | |
162 | IohMmio32( BaseAddr, Register ) = \\r | |
163 | (UINT32) ( \\r | |
164 | IohMmio32( BaseAddr, Register ) & \\r | |
165 | (UINT32)(AndData) \\r | |
166 | )\r | |
167 | \r | |
168 | #define IohMmio32AndThenOr( BaseAddr, Register, AndData, OrData ) \\r | |
169 | IohMmio32( BaseAddr, Register ) = \\r | |
170 | (UINT32) ( \\r | |
171 | ( IohMmio32( BaseAddr, Register ) & \\r | |
172 | (UINT32)(AndData) \\r | |
173 | ) | \\r | |
174 | (UINT32)(OrData) \\r | |
175 | )\r | |
176 | //\r | |
177 | // UINT16\r | |
178 | //\r | |
179 | \r | |
180 | #define IohMmio16Ptr( BaseAddr, Register ) \\r | |
181 | ( (volatile UINT16 *)IohMmioAddress( BaseAddr, Register ) )\r | |
182 | \r | |
183 | #define IohMmio16( BaseAddr, Register ) \\r | |
184 | *IohMmio16Ptr( BaseAddr, Register )\r | |
185 | \r | |
186 | #define IohMmio16Or( BaseAddr, Register, OrData ) \\r | |
187 | IohMmio16( BaseAddr, Register ) = \\r | |
188 | (UINT16) ( \\r | |
189 | IohMmio16( BaseAddr, Register ) | \\r | |
190 | (UINT16)(OrData) \\r | |
191 | )\r | |
192 | \r | |
193 | #define IohMmio16And( BaseAddr, Register, AndData ) \\r | |
194 | IohMmio16( BaseAddr, Register ) = \\r | |
195 | (UINT16) ( \\r | |
196 | IohMmio16( BaseAddr, Register ) & \\r | |
197 | (UINT16)(AndData) \\r | |
198 | )\r | |
199 | \r | |
200 | #define IohMmio16AndThenOr( BaseAddr, Register, AndData, OrData ) \\r | |
201 | IohMmio16( BaseAddr, Register ) = \\r | |
202 | (UINT16) ( \\r | |
203 | ( IohMmio16( BaseAddr, Register ) & \\r | |
204 | (UINT16)(AndData) \\r | |
205 | ) | \\r | |
206 | (UINT16)(OrData) \\r | |
207 | )\r | |
208 | //\r | |
209 | // UINT8\r | |
210 | //\r | |
211 | #define IohMmio8Ptr( BaseAddr, Register ) \\r | |
212 | ( (volatile UINT8 *)IohMmioAddress( BaseAddr, Register ) )\r | |
213 | \r | |
214 | #define IohMmio8( BaseAddr, Register ) \\r | |
215 | *IohMmio8Ptr( BaseAddr, Register )\r | |
216 | \r | |
217 | #define IohMmio8Or( BaseAddr, Register, OrData ) \\r | |
218 | IohMmio8( BaseAddr, Register ) = \\r | |
219 | (UINT8) ( \\r | |
220 | IohMmio8( BaseAddr, Register ) | \\r | |
221 | (UINT8)(OrData) \\r | |
222 | )\r | |
223 | \r | |
224 | #define IohMmio8And( BaseAddr, Register, AndData ) \\r | |
225 | IohMmio8( BaseAddr, Register ) = \\r | |
226 | (UINT8) ( \\r | |
227 | IohMmio8( BaseAddr, Register ) & \\r | |
228 | (UINT8)(AndData) \\r | |
229 | )\r | |
230 | \r | |
231 | #define IohMmio8AndThenOr( BaseAddr, Register, AndData, OrData ) \\r | |
232 | IohMmio8( BaseAddr, Register ) = \\r | |
233 | (UINT8) ( \\r | |
234 | ( IohMmio8( BaseAddr, Register ) & \\r | |
235 | (UINT8)(AndData) \\r | |
236 | ) | \\r | |
237 | (UINT8)(OrData) \\r | |
238 | )\r | |
239 | \r | |
240 | //\r | |
241 | // Common Memory mapped Pci access macros ------------------------------------------\r | |
242 | //\r | |
243 | #define Ioh_PCI_EXPRESS_BASE_ADDRESS 0xE0000000\r | |
244 | \r | |
245 | \r | |
246 | #define IohMmPciAddress( Segment, Bus, Device, Function, Register ) \\r | |
247 | ( (UINTN)Ioh_PCI_EXPRESS_BASE_ADDRESS + \\r | |
248 | (UINTN)(Bus << 20) + \\r | |
249 | (UINTN)(Device << 15) + \\r | |
250 | (UINTN)(Function << 12) + \\r | |
251 | (UINTN)(Register) \\r | |
252 | )\r | |
253 | \r | |
254 | //\r | |
255 | // UINT32\r | |
256 | //\r | |
257 | #define IohMmPci32Ptr( Segment, Bus, Device, Function, Register ) \\r | |
258 | ( (volatile UINT32 *)IohMmPciAddress( Segment, Bus, Device, Function, Register ) )\r | |
259 | \r | |
260 | #define IohMmPci32( Segment, Bus, Device, Function, Register ) \\r | |
261 | *IohMmPci32Ptr( Segment, Bus, Device, Function, Register )\r | |
262 | \r | |
263 | #define IohMmPci32Or( Segment, Bus, Device, Function, Register, OrData ) \\r | |
264 | IohMmPci32( Segment, Bus, Device, Function, Register ) = \\r | |
265 | (UINT32) ( \\r | |
266 | IohMmPci32( Segment, Bus, Device, Function, Register ) | \\r | |
267 | (UINT32)(OrData) \\r | |
268 | )\r | |
269 | \r | |
270 | #define IohMmPci32And( Segment, Bus, Device, Function, Register, AndData ) \\r | |
271 | IohMmPci32( Segment, Bus, Device, Function, Register ) = \\r | |
272 | (UINT32) ( \\r | |
273 | IohMmPci32( Segment, Bus, Device, Function, Register ) & \\r | |
274 | (UINT32)(AndData) \\r | |
275 | )\r | |
276 | \r | |
277 | #define IohMmPci32AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \\r | |
278 | IohMmPci32( Segment, Bus, Device, Function, Register ) = \\r | |
279 | (UINT32) ( \\r | |
280 | ( IohMmPci32( Segment, Bus, Device, Function, Register ) & \\r | |
281 | (UINT32)(AndData) \\r | |
282 | ) | \\r | |
283 | (UINT32)(OrData) \\r | |
284 | )\r | |
285 | //\r | |
286 | // UINT16\r | |
287 | //\r | |
288 | #define IohMmPci16Ptr( Segment, Bus, Device, Function, Register ) \\r | |
289 | ( (volatile UINT16 *)IohMmPciAddress( Segment, Bus, Device, Function, Register ) )\r | |
290 | \r | |
291 | #define IohMmPci16( Segment, Bus, Device, Function, Register ) \\r | |
292 | *IohMmPci16Ptr( Segment, Bus, Device, Function, Register )\r | |
293 | \r | |
294 | #define IohMmPci16Or( Segment, Bus, Device, Function, Register, OrData ) \\r | |
295 | IohMmPci16( Segment, Bus, Device, Function, Register ) = \\r | |
296 | (UINT16) ( \\r | |
297 | IohMmPci16( Segment, Bus, Device, Function, Register ) | \\r | |
298 | (UINT16)(OrData) \\r | |
299 | )\r | |
300 | \r | |
301 | #define IohMmPci16And( Segment, Bus, Device, Function, Register, AndData ) \\r | |
302 | IohMmPci16( Segment, Bus, Device, Function, Register ) = \\r | |
303 | (UINT16) ( \\r | |
304 | IohMmPci16( Segment, Bus, Device, Function, Register ) & \\r | |
305 | (UINT16)(AndData) \\r | |
306 | )\r | |
307 | \r | |
308 | #define IohMmPci16AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \\r | |
309 | IohMmPci16( Segment, Bus, Device, Function, Register ) = \\r | |
310 | (UINT16) ( \\r | |
311 | ( IohMmPci16( Segment, Bus, Device, Function, Register ) & \\r | |
312 | (UINT16)(AndData) \\r | |
313 | ) | \\r | |
314 | (UINT16)(OrData) \\r | |
315 | )\r | |
316 | //\r | |
317 | // UINT8\r | |
318 | //\r | |
319 | #define IohMmPci8Ptr( Segment, Bus, Device, Function, Register ) \\r | |
320 | ( (volatile UINT8 *)IohMmPciAddress( Segment, Bus, Device, Function, Register ) )\r | |
321 | \r | |
322 | #define IohMmPci8( Segment, Bus, Device, Function, Register ) \\r | |
323 | *IohMmPci8Ptr( Segment, Bus, Device, Function, Register )\r | |
324 | \r | |
325 | #define IohMmPci8Or( Segment, Bus, Device, Function, Register, OrData ) \\r | |
326 | IohMmPci8( Segment, Bus, Device, Function, Register ) = \\r | |
327 | (UINT8) ( \\r | |
328 | IohMmPci8( Segment, Bus, Device, Function, Register ) | \\r | |
329 | (UINT8)(OrData) \\r | |
330 | )\r | |
331 | \r | |
332 | #define IohMmPci8And( Segment, Bus, Device, Function, Register, AndData ) \\r | |
333 | IohMmPci8( Segment, Bus, Device, Function, Register ) = \\r | |
334 | (UINT8) ( \\r | |
335 | IohMmPci8( Segment, Bus, Device, Function, Register ) & \\r | |
336 | (UINT8)(AndData) \\r | |
337 | )\r | |
338 | \r | |
339 | #define IohMmPci8AndThenOr( Segment, Bus, Device, Function, Register, AndData, OrData ) \\r | |
340 | IohMmPci8( Segment, Bus, Device, Function, Register ) = \\r | |
341 | (UINT8) ( \\r | |
342 | ( IohMmPci8( Segment, Bus, Device, Function, Register ) & \\r | |
343 | (UINT8)(AndData) \\r | |
344 | ) | \\r | |
345 | (UINT8)(OrData) \\r | |
346 | )\r | |
347 | \r | |
348 | #endif\r |