[mirror_edk2.git] / StdLib / Include / Arm / machine / atomic.h

/* $NetBSD: atomic.h,v 1.5 2005/12/28 19:09:29 perry Exp $ */\r
\r
/*\r
 * Copyright (C) 1994-1997 Mark Brinicombe\r
 * Copyright (C) 1994 Brini\r
 * All rights reserved.\r
 *\r
 * This code is derived from software written for Brini by Mark Brinicombe\r
 *\r
 * Redistribution and use in source and binary forms, with or without\r
 * modification, are permitted provided that the following conditions\r
 * are met:\r
 * 1. Redistributions of source code must retain the above copyright\r
 *    notice, this list of conditions and the following disclaimer.\r
 * 2. Redistributions in binary form must reproduce the above copyright\r
 *    notice, this list of conditions and the following disclaimer in the\r
 *    documentation and/or other materials provided with the distribution.\r
 * 3. All advertising materials mentioning features or use of this software\r
 *    must display the following acknowledgement:\r
 *	This product includes software developed by Brini.\r
 * 4. The name of Brini may not be used to endorse or promote products\r
 *    derived from this software without specific prior written permission.\r
 *\r
 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR\r
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES\r
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.\r
 * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF\r
 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
 */\r
\r
#ifndef	_ARM_ATOMIC_H_\r
#define	_ARM_ATOMIC_H_\r
\r
#ifndef ATOMIC_SET_BIT_NONINLINE_REQUIRED\r
\r
#if defined(__PROG26) || defined(ATOMIC_SET_BIT_NOINLINE)\r
#define	ATOMIC_SET_BIT_NONINLINE_REQUIRED\r
#endif\r
\r
#endif /* ATOMIC_SET_BIT_NONINLINE_REQUIRED */\r
\r
\r
#ifndef _LOCORE\r
\r
#include <sys/types.h>\r
#include <arm/armreg.h>			/* I32_bit */\r
\r
#ifdef ATOMIC_SET_BIT_NONINLINE_REQUIRED\r
void atomic_set_bit( u_int *, u_int );\r
void atomic_clear_bit( u_int *, u_int );\r
#endif\r
\r
#ifdef __PROG32\r
#define __with_interrupts_disabled(expr) \\r
	do {						\\r
		u_int cpsr_save, tmp;			\\r
							\\r
		__asm volatile(			\\r
			"mrs  %0, cpsr;"		\\r
			"orr  %1, %0, %2;"		\\r
			"msr  cpsr_all, %1;"		\\r
			: "=r" (cpsr_save), "=r" (tmp)	\\r
			: "I" (I32_bit)		\\r
		        : "cc" );		\\r
		(expr);				\\r
		 __asm volatile(		\\r
			"msr  cpsr_all, %0"	\\r
			: /* no output */	\\r
			: "r" (cpsr_save)	\\r
			: "cc" );		\\r
	} while(0)\r
\r
static __inline void\r
inline_atomic_set_bit( u_int *address, u_int setmask )\r
{\r
	__with_interrupts_disabled( *address |= setmask );\r
}\r
\r
static __inline void\r
inline_atomic_clear_bit( u_int *address, u_int clearmask )\r
{\r
	__with_interrupts_disabled( *address &= ~clearmask );\r
}\r
\r
#if !defined(ATOMIC_SET_BIT_NOINLINE)\r
\r
#define atomic_set_bit(a,m)   inline_atomic_set_bit(a,m)\r
#define atomic_clear_bit(a,m) inline_atomic_clear_bit(a,m)\r
\r
#endif\r
\r
#endif /* __PROG32 */\r
\r
#undef __with_interrupts_disabled\r
\r
#endif /* _LOCORE */\r
#endif /* _ARM_ATOMIC_H_ */\r
Commit	Line	Data
2aa62f2b	1	/* $NetBSD: atomic.h,v 1.5 2005/12/28 19:09:29 perry Exp $ */\r
	2	\r
	3	/*\r
	4	* Copyright (C) 1994-1997 Mark Brinicombe\r
	5	* Copyright (C) 1994 Brini\r
	6	* All rights reserved.\r
	7	*\r
	8	* This code is derived from software written for Brini by Mark Brinicombe\r
	9	*\r
	10	* Redistribution and use in source and binary forms, with or without\r
	11	* modification, are permitted provided that the following conditions\r
	12	* are met:\r
	13	* 1. Redistributions of source code must retain the above copyright\r
	14	* notice, this list of conditions and the following disclaimer.\r
	15	* 2. Redistributions in binary form must reproduce the above copyright\r
	16	* notice, this list of conditions and the following disclaimer in the\r
	17	* documentation and/or other materials provided with the distribution.\r
	18	* 3. All advertising materials mentioning features or use of this software\r
	19	* must display the following acknowledgement:\r
	20	* This product includes software developed by Brini.\r
	21	* 4. The name of Brini may not be used to endorse or promote products\r
	22	* derived from this software without specific prior written permission.\r
	23	*\r
	24	* THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR\r
	25	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES\r
	26	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.\r
	27	* IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
	28	* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,\r
	29	* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;\r
	30	* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,\r
	31	* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR\r
	32	* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF\r
	33	* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
	34	*/\r
	35	\r
	36	#ifndef _ARM_ATOMIC_H_\r
	37	#define _ARM_ATOMIC_H_\r
	38	\r
	39	#ifndef ATOMIC_SET_BIT_NONINLINE_REQUIRED\r
	40	\r
	41	#if defined(__PROG26) \|\| defined(ATOMIC_SET_BIT_NOINLINE)\r
	42	#define ATOMIC_SET_BIT_NONINLINE_REQUIRED\r
	43	#endif\r
	44	\r
	45	#endif /* ATOMIC_SET_BIT_NONINLINE_REQUIRED */\r
	46	\r
	47	\r
	48	#ifndef _LOCORE\r
	49	\r
	50	#include <sys/types.h>\r
	51	#include <arm/armreg.h> /* I32_bit */\r
	52	\r
	53	#ifdef ATOMIC_SET_BIT_NONINLINE_REQUIRED\r
	54	void atomic_set_bit( u_int *, u_int );\r
	55	void atomic_clear_bit( u_int *, u_int );\r
	56	#endif\r
	57	\r
	58	#ifdef __PROG32\r
	59	#define __with_interrupts_disabled(expr) \\r
	60	do { \\r
	61	u_int cpsr_save, tmp; \\r
	62	\\r
	63	__asm volatile( \\r
	64	"mrs %0, cpsr;" \\r
65	"orr %1, %0, %2;" \\r
66	"msr cpsr_all, %1;" \\r
67	: "=r" (cpsr_save), "=r" (tmp) \\r
68	: "I" (I32_bit) \\r
69	: "cc" ); \\r
70	(expr); \\r
71	__asm volatile( \\r
72	"msr cpsr_all, %0" \\r
73	: /* no output */ \\r
74	: "r" (cpsr_save) \\r
75	: "cc" ); \\r
76	} while(0)\r
77	\r
78	static __inline void\r
79	inline_atomic_set_bit( u_int *address, u_int setmask )\r
80	{\r
81	__with_interrupts_disabled( *address \|= setmask );\r
82	}\r
83	\r
84	static __inline void\r
85	inline_atomic_clear_bit( u_int *address, u_int clearmask )\r
86	{\r
87	__with_interrupts_disabled( *address &= ~clearmask );\r
88	}\r
89	\r
90	#if !defined(ATOMIC_SET_BIT_NOINLINE)\r
91	\r
92	#define atomic_set_bit(a,m) inline_atomic_set_bit(a,m)\r
93	#define atomic_clear_bit(a,m) inline_atomic_clear_bit(a,m)\r
94	\r
95	#endif\r
96	\r
97	#endif /* __PROG32 */\r
98	\r
99	#undef __with_interrupts_disabled\r
100	\r
101	#endif /* _LOCORE */\r
102	#endif /* _ARM_ATOMIC_H_ */\r