[mirror_edk2.git] / UefiCpuPkg / Include / Register / Msr / BroadwellMsr.h

/** @file\r
  MSR Definitions for Intel processors based on the Broadwell microarchitecture.\r
\r
  Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
  are provided for MSRs that contain one or more bit fields.  If the MSR value\r
  returned is a single 32-bit or 64-bit value, then a data structure is not\r
  provided for that MSR.\r
\r
  Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
  @par Specification Reference:\r
  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
  May 2018, Volume 4: Model-Specific-Registers (MSR)\r
\r
**/\r
\r
#ifndef __BROADWELL_MSR_H__\r
#define __BROADWELL_MSR_H__\r
\r
#include <Register/ArchitecturalMsr.h>\r
\r
/**\r
  Is Intel processors based on the Broadwell microarchitecture?\r
\r
  @param   DisplayFamily  Display Family ID\r
  @param   DisplayModel   Display Model ID\r
\r
  @retval  TRUE   Yes, it is.\r
  @retval  FALSE  No, it isn't.\r
**/\r
#define IS_BROADWELL_PROCESSOR(DisplayFamily, DisplayModel) \\r
  (DisplayFamily == 0x06 && \\r
   (                        \\r
    DisplayModel == 0x3D || \\r
    DisplayModel == 0x47 || \\r
    DisplayModel == 0x4F || \\r
    DisplayModel == 0x56    \\r
    )                       \\r
   )\r
\r
/**\r
  Thread. See Table 2-2. See Section 18.6.2.2, "Global Counter Control\r
  Facilities.".\r
\r
  @param  ECX  MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS (0x0000038E)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS);\r
  AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);\r
  @endcode\r
  @note MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r
**/\r
#define MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS    0x0000038E\r
\r
/**\r
  MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bit 0] Ovf_PMC0.\r
    ///\r
    UINT32  Ovf_PMC0:1;\r
    ///\r
    /// [Bit 1] Ovf_PMC1.\r
    ///\r
    UINT32  Ovf_PMC1:1;\r
    ///\r
    /// [Bit 2] Ovf_PMC2.\r
    ///\r
    UINT32  Ovf_PMC2:1;\r
    ///\r
    /// [Bit 3] Ovf_PMC3.\r
    ///\r
    UINT32  Ovf_PMC3:1;\r
    UINT32  Reserved1:28;\r
    ///\r
    /// [Bit 32] Ovf_FixedCtr0.\r
    ///\r
    UINT32  Ovf_FixedCtr0:1;\r
    ///\r
    /// [Bit 33] Ovf_FixedCtr1.\r
    ///\r
    UINT32  Ovf_FixedCtr1:1;\r
    ///\r
    /// [Bit 34] Ovf_FixedCtr2.\r
    ///\r
    UINT32  Ovf_FixedCtr2:1;\r
    UINT32  Reserved2:20;\r
    ///\r
    /// [Bit 55] Trace_ToPA_PMI. See Section 36.2.6.2, "Table of Physical\r
    /// Addresses (ToPA).".\r
    ///\r
    UINT32  Trace_ToPA_PMI:1;\r
    UINT32  Reserved3:5;\r
    ///\r
    /// [Bit 61] Ovf_Uncore.\r
    ///\r
    UINT32  Ovf_Uncore:1;\r
    ///\r
    /// [Bit 62] Ovf_BufDSSAVE.\r
    ///\r
    UINT32  OvfBuf:1;\r
    ///\r
    /// [Bit 63] CondChgd.\r
    ///\r
    UINT32  CondChgd:1;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER;\r
\r
\r
/**\r
  Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
  specific C-state code names, unrelated to MWAIT extension C-state parameters\r
  or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.\r
\r
  @param  ECX  MSR_BROADWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL);\r
  AsmWriteMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
  @endcode\r
  @note MSR_BROADWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
**/\r
#define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL     0x000000E2\r
\r
/**\r
  MSR information returned for MSR index #MSR_BROADWELL_PKG_CST_CONFIG_CONTROL\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest\r
    /// processor-specific C-state code name (consuming the least power) for\r
    /// the package. The default is set as factory-configured package C-state\r
    /// limit. The following C-state code name encodings are supported: 0000b:\r
    /// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6\r
    /// 0100b: C7 0101b: C7s 0110b: C8 0111b: C9 1000b: C10.\r
    ///\r
    UINT32  Limit:4;\r
    UINT32  Reserved1:6;\r
    ///\r
    /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
    ///\r
    UINT32  IO_MWAIT:1;\r
    UINT32  Reserved2:4;\r
    ///\r
    /// [Bit 15] CFG Lock (R/WO).\r
    ///\r
    UINT32  CFGLock:1;\r
    UINT32  Reserved3:9;\r
    ///\r
    /// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
    ///\r
    UINT32  C3AutoDemotion:1;\r
    ///\r
    /// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
    ///\r
    UINT32  C1AutoDemotion:1;\r
    ///\r
    /// [Bit 27] Enable C3 Undemotion (R/W).\r
    ///\r
    UINT32  C3Undemotion:1;\r
    ///\r
    /// [Bit 28] Enable C1 Undemotion (R/W).\r
    ///\r
    UINT32  C1Undemotion:1;\r
    ///\r
    /// [Bit 29] Enable Package C-State Auto-demotion (R/W).\r
    ///\r
    UINT32  CStateAutoDemotion:1;\r
    ///\r
    /// [Bit 30] Enable Package C-State Undemotion (R/W).\r
    ///\r
    UINT32  CStateUndemotion:1;\r
    UINT32  Reserved4:1;\r
    UINT32  Reserved5:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER;\r
\r
\r
/**\r
  Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
  RW if MSR_PLATFORM_INFO.[28] = 1.\r
\r
  @param  ECX  MSR_BROADWELL_TURBO_RATIO_LIMIT (0x000001AD)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_TURBO_RATIO_LIMIT);\r
  @endcode\r
  @note MSR_BROADWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
**/\r
#define MSR_BROADWELL_TURBO_RATIO_LIMIT          0x000001AD\r
\r
/**\r
  MSR information returned for MSR index #MSR_BROADWELL_TURBO_RATIO_LIMIT\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
    /// limit of 1 core active.\r
    ///\r
    UINT32  Maximum1C:8;\r
    ///\r
    /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
    /// limit of 2 core active.\r
    ///\r
    UINT32  Maximum2C:8;\r
    ///\r
    /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
    /// limit of 3 core active.\r
    ///\r
    UINT32  Maximum3C:8;\r
    ///\r
    /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
    /// limit of 4 core active.\r
    ///\r
    UINT32  Maximum4C:8;\r
    ///\r
    /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
    /// limit of 5core active.\r
    ///\r
    UINT32  Maximum5C:8;\r
    ///\r
    /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
    /// limit of 6core active.\r
    ///\r
    UINT32  Maximum6C:8;\r
    UINT32  Reserved:16;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER;\r
\r
\r
/**\r
  Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r
  fields represent the widest possible range of uncore frequencies. Writing to\r
  these fields allows software to control the minimum and the maximum\r
  frequency that hardware will select.\r
\r
  @param  ECX  MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT (0x00000620)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT);\r
  AsmWriteMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r
  @endcode\r
**/\r
#define MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT      0x00000620\r
\r
/**\r
  MSR information returned for MSR index #MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r
    /// LLC/Ring.\r
    ///\r
    UINT32  MAX_RATIO:7;\r
    UINT32  Reserved2:1;\r
    ///\r
    /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r
    /// possible ratio of the LLC/Ring.\r
    ///\r
    UINT32  MIN_RATIO:7;\r
    UINT32  Reserved3:17;\r
    UINT32  Reserved4:32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32  Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64  Uint64;\r
} MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER;\r
\r
/**\r
  Package. PP0 Energy Status (R/O)  See Section 14.9.4, "PP0/PP1 RAPL\r
  Domains.".\r
\r
  @param  ECX  MSR_BROADWELL_PP0_ENERGY_STATUS (0x00000639)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_BROADWELL_PP0_ENERGY_STATUS);\r
  @endcode\r
  @note MSR_BROADWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
**/\r
#define MSR_BROADWELL_PP0_ENERGY_STATUS          0x00000639\r
\r
#endif\r
Commit	Line	Data
d57201c0 MK	1	/** @file\r
	2	MSR Definitions for Intel processors based on the Broadwell microarchitecture.\r
	3	\r
	4	Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
	5	are provided for MSRs that contain one or more bit fields. If the MSR value\r
	6	returned is a single 32-bit or 64-bit value, then a data structure is not\r
	7	provided for that MSR.\r
	8	\r
ba1a2d11	9	Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
0acd8697	10	SPDX-License-Identifier: BSD-2-Clause-Patent\r
d57201c0 MK	11	\r
d57201c0 MK	12	@par Specification Reference:\r
ba1a2d11 ED	13	Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
ba1a2d11 ED	14	May 2018, Volume 4: Model-Specific-Registers (MSR)\r
d57201c0 MK	15	\r
	16	**/\r
	17	\r
	18	#ifndef __BROADWELL_MSR_H__\r
	19	#define __BROADWELL_MSR_H__\r
	20	\r
	21	#include <Register/ArchitecturalMsr.h>\r
	22	\r
f4c982bf JF	23	/**\r
	24	Is Intel processors based on the Broadwell microarchitecture?\r
	25	\r
	26	@param DisplayFamily Display Family ID\r
	27	@param DisplayModel Display Model ID\r
	28	\r
	29	@retval TRUE Yes, it is.\r
	30	@retval FALSE No, it isn't.\r
	31	**/\r
	32	#define IS_BROADWELL_PROCESSOR(DisplayFamily, DisplayModel) \\r
	33	(DisplayFamily == 0x06 && \\r
	34	( \\r
	35	DisplayModel == 0x3D \|\| \\r
	36	DisplayModel == 0x47 \|\| \\r
	37	DisplayModel == 0x4F \|\| \\r
	38	DisplayModel == 0x56 \\r
	39	) \\r
	40	)\r
	41	\r
d57201c0	42	/**\r
ba1a2d11	43	Thread. See Table 2-2. See Section 18.6.2.2, "Global Counter Control\r
d57201c0 MK	44	Facilities.".\r
d57201c0 MK	45	\r
0f16be6d	46	@param ECX MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS (0x0000038E)\r
d57201c0	47	@param EAX Lower 32-bits of MSR value.\r
0f16be6d	48	Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
d57201c0	49	@param EDX Upper 32-bits of MSR value.\r
0f16be6d	50	Described by the type MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER.\r
d57201c0 MK	51	\r
	52	<b>Example usage</b>\r
	53	@code\r
0f16be6d	54	MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;\r
d57201c0	55	\r
0f16be6d HW	56	Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS);\r
0f16be6d HW	57	AsmWriteMsr64 (MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);\r
d57201c0	58	@endcode\r
0f16be6d	59	@note MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r
d57201c0	60	**/\r
0f16be6d	61	#define MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS 0x0000038E\r
d57201c0 MK	62	\r
d57201c0 MK	63	/**\r
0f16be6d	64	MSR information returned for MSR index #MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS\r
d57201c0 MK	65	**/\r
	66	typedef union {\r
	67	///\r
	68	/// Individual bit fields\r
	69	///\r
	70	struct {\r
	71	///\r
	72	/// [Bit 0] Ovf_PMC0.\r
	73	///\r
	74	UINT32 Ovf_PMC0:1;\r
	75	///\r
	76	/// [Bit 1] Ovf_PMC1.\r
	77	///\r
	78	UINT32 Ovf_PMC1:1;\r
	79	///\r
	80	/// [Bit 2] Ovf_PMC2.\r
	81	///\r
	82	UINT32 Ovf_PMC2:1;\r
	83	///\r
	84	/// [Bit 3] Ovf_PMC3.\r
	85	///\r
	86	UINT32 Ovf_PMC3:1;\r
	87	UINT32 Reserved1:28;\r
	88	///\r
	89	/// [Bit 32] Ovf_FixedCtr0.\r
	90	///\r
	91	UINT32 Ovf_FixedCtr0:1;\r
	92	///\r
	93	/// [Bit 33] Ovf_FixedCtr1.\r
	94	///\r
	95	UINT32 Ovf_FixedCtr1:1;\r
	96	///\r
	97	/// [Bit 34] Ovf_FixedCtr2.\r
	98	///\r
	99	UINT32 Ovf_FixedCtr2:1;\r
	100	UINT32 Reserved2:20;\r
	101	///\r
0f16be6d	102	/// [Bit 55] Trace_ToPA_PMI. See Section 36.2.6.2, "Table of Physical\r
d57201c0 MK	103	/// Addresses (ToPA).".\r
	104	///\r
	105	UINT32 Trace_ToPA_PMI:1;\r
	106	UINT32 Reserved3:5;\r
	107	///\r
	108	/// [Bit 61] Ovf_Uncore.\r
	109	///\r
	110	UINT32 Ovf_Uncore:1;\r
	111	///\r
	112	/// [Bit 62] Ovf_BufDSSAVE.\r
	113	///\r
	114	UINT32 OvfBuf:1;\r
	115	///\r
	116	/// [Bit 63] CondChgd.\r
	117	///\r
	118	UINT32 CondChgd:1;\r
	119	} Bits;\r
	120	///\r
	121	/// All bit fields as a 64-bit value\r
	122	///\r
	123	UINT64 Uint64;\r
0f16be6d	124	} MSR_BROADWELL_IA32_PERF_GLOBAL_STATUS_REGISTER;\r
d57201c0 MK	125	\r
	126	\r
	127	/**\r
	128	Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
	129	specific C-state code names, unrelated to MWAIT extension C-state parameters\r
	130	or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.\r
	131	\r
	132	@param ECX MSR_BROADWELL_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
	133	@param EAX Lower 32-bits of MSR value.\r
	134	Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.\r
	135	@param EDX Upper 32-bits of MSR value.\r
	136	Described by the type MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER.\r
	137	\r
	138	<b>Example usage</b>\r
	139	@code\r
	140	MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
	141	\r
	142	Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL);\r
	143	AsmWriteMsr64 (MSR_BROADWELL_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
	144	@endcode\r
a6b7bc3c	145	@note MSR_BROADWELL_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
d57201c0 MK	146	**/\r
	147	#define MSR_BROADWELL_PKG_CST_CONFIG_CONTROL 0x000000E2\r
	148	\r
	149	/**\r
	150	MSR information returned for MSR index #MSR_BROADWELL_PKG_CST_CONFIG_CONTROL\r
	151	**/\r
	152	typedef union {\r
	153	///\r
	154	/// Individual bit fields\r
	155	///\r
	156	struct {\r
	157	///\r
	158	/// [Bits 3:0] Package C-State Limit (R/W) Specifies the lowest\r
	159	/// processor-specific C-state code name (consuming the least power) for\r
	160	/// the package. The default is set as factory-configured package C-state\r
	161	/// limit. The following C-state code name encodings are supported: 0000b:\r
	162	/// C0/C1 (no package C-state support) 0001b: C2 0010b: C3 0011b: C6\r
	163	/// 0100b: C7 0101b: C7s 0110b: C8 0111b: C9 1000b: C10.\r
	164	///\r
	165	UINT32 Limit:4;\r
	166	UINT32 Reserved1:6;\r
	167	///\r
	168	/// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
	169	///\r
	170	UINT32 IO_MWAIT:1;\r
	171	UINT32 Reserved2:4;\r
	172	///\r
	173	/// [Bit 15] CFG Lock (R/WO).\r
	174	///\r
	175	UINT32 CFGLock:1;\r
	176	UINT32 Reserved3:9;\r
	177	///\r
	178	/// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
	179	///\r
	180	UINT32 C3AutoDemotion:1;\r
	181	///\r
	182	/// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
	183	///\r
	184	UINT32 C1AutoDemotion:1;\r
	185	///\r
	186	/// [Bit 27] Enable C3 Undemotion (R/W).\r
	187	///\r
	188	UINT32 C3Undemotion:1;\r
	189	///\r
	190	/// [Bit 28] Enable C1 Undemotion (R/W).\r
	191	///\r
	192	UINT32 C1Undemotion:1;\r
	193	///\r
	194	/// [Bit 29] Enable Package C-State Auto-demotion (R/W).\r
	195	///\r
	196	UINT32 CStateAutoDemotion:1;\r
	197	///\r
	198	/// [Bit 30] Enable Package C-State Undemotion (R/W).\r
	199	///\r
	200	UINT32 CStateUndemotion:1;\r
	201	UINT32 Reserved4:1;\r
	202	UINT32 Reserved5:32;\r
	203	} Bits;\r
	204	///\r
	205	/// All bit fields as a 32-bit value\r
	206	///\r
	207	UINT32 Uint32;\r
	208	///\r
	209	/// All bit fields as a 64-bit value\r
210	///\r
211	UINT64 Uint64;\r
212	} MSR_BROADWELL_PKG_CST_CONFIG_CONTROL_REGISTER;\r
213	\r
214	\r
215	/**\r
216	Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
217	RW if MSR_PLATFORM_INFO.[28] = 1.\r
218	\r
219	@param ECX MSR_BROADWELL_TURBO_RATIO_LIMIT (0x000001AD)\r
220	@param EAX Lower 32-bits of MSR value.\r
221	Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.\r
222	@param EDX Upper 32-bits of MSR value.\r
223	Described by the type MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER.\r
224	\r
225	<b>Example usage</b>\r
226	@code\r
227	MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER Msr;\r
228	\r
229	Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_TURBO_RATIO_LIMIT);\r
230	@endcode\r
a6b7bc3c	231	@note MSR_BROADWELL_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
d57201c0 MK	232	**/\r
	233	#define MSR_BROADWELL_TURBO_RATIO_LIMIT 0x000001AD\r
	234	\r
	235	/**\r
	236	MSR information returned for MSR index #MSR_BROADWELL_TURBO_RATIO_LIMIT\r
	237	**/\r
	238	typedef union {\r
	239	///\r
	240	/// Individual bit fields\r
	241	///\r
	242	struct {\r
	243	///\r
	244	/// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
	245	/// limit of 1 core active.\r
	246	///\r
	247	UINT32 Maximum1C:8;\r
	248	///\r
	249	/// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
	250	/// limit of 2 core active.\r
	251	///\r
	252	UINT32 Maximum2C:8;\r
	253	///\r
	254	/// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
	255	/// limit of 3 core active.\r
	256	///\r
	257	UINT32 Maximum3C:8;\r
	258	///\r
	259	/// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
	260	/// limit of 4 core active.\r
	261	///\r
	262	UINT32 Maximum4C:8;\r
	263	///\r
	264	/// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
	265	/// limit of 5core active.\r
	266	///\r
	267	UINT32 Maximum5C:8;\r
	268	///\r
	269	/// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
	270	/// limit of 6core active.\r
	271	///\r
	272	UINT32 Maximum6C:8;\r
	273	UINT32 Reserved:16;\r
	274	} Bits;\r
	275	///\r
	276	/// All bit fields as a 64-bit value\r
	277	///\r
	278	UINT64 Uint64;\r
	279	} MSR_BROADWELL_TURBO_RATIO_LIMIT_REGISTER;\r
	280	\r
0f16be6d	281	\r
c4b07363 ED	282	/**\r
	283	Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r
	284	fields represent the widest possible range of uncore frequencies. Writing to\r
	285	these fields allows software to control the minimum and the maximum\r
	286	frequency that hardware will select.\r
	287	\r
	288	@param ECX MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT (0x00000620)\r
	289	@param EAX Lower 32-bits of MSR value.\r
	290	Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
	291	@param EDX Upper 32-bits of MSR value.\r
	292	Described by the type MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
	293	\r
	294	<b>Example usage</b>\r
	295	@code\r
	296	MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;\r
	297	\r
	298	Msr.Uint64 = AsmReadMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT);\r
	299	AsmWriteMsr64 (MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r
	300	@endcode\r
	301	**/\r
	302	#define MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT 0x00000620\r
	303	\r
	304	/**\r
	305	MSR information returned for MSR index #MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT\r
	306	**/\r
	307	typedef union {\r
	308	///\r
	309	/// Individual bit fields\r
	310	///\r
	311	struct {\r
	312	///\r
	313	/// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r
	314	/// LLC/Ring.\r
	315	///\r
	316	UINT32 MAX_RATIO:7;\r
	317	UINT32 Reserved2:1;\r
	318	///\r
	319	/// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r
	320	/// possible ratio of the LLC/Ring.\r
	321	///\r
	322	UINT32 MIN_RATIO:7;\r
	323	UINT32 Reserved3:17;\r
	324	UINT32 Reserved4:32;\r
	325	} Bits;\r
	326	///\r
	327	/// All bit fields as a 32-bit value\r
	328	///\r
	329	UINT32 Uint32;\r
	330	///\r
	331	/// All bit fields as a 64-bit value\r
	332	///\r
	333	UINT64 Uint64;\r
	334	} MSR_BROADWELL_MSRUNCORE_RATIO_LIMIT_REGISTER;\r
	335	\r
0f16be6d HW	336	/**\r
	337	Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r
	338	Domains.".\r
	339	\r
	340	@param ECX MSR_BROADWELL_PP0_ENERGY_STATUS (0x00000639)\r
	341	@param EAX Lower 32-bits of MSR value.\r
	342	@param EDX Upper 32-bits of MSR value.\r
	343	\r
	344	<b>Example usage</b>\r
	345	@code\r
	346	UINT64 Msr;\r
	347	\r
	348	Msr = AsmReadMsr64 (MSR_BROADWELL_PP0_ENERGY_STATUS);\r
	349	@endcode\r
	350	@note MSR_BROADWELL_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
	351	**/\r
	352	#define MSR_BROADWELL_PP0_ENERGY_STATUS 0x00000639\r
	353	\r
d57201c0	354	#endif\r