]>
Commit | Line | Data |
---|---|---|
bf73cc4b | 1 | /** @file\r |
2 | Local APIC Library.\r | |
3 | \r | |
4 | This local APIC library instance supports xAPIC mode only.\r | |
5 | \r | |
59d67246 | 6 | Copyright (c) 2010 - 2015, Intel Corporation. All rights reserved.<BR>\r |
bf73cc4b | 7 | This program and the accompanying materials\r |
8 | are licensed and made available under the terms and conditions of the BSD License\r | |
9 | which accompanies this distribution. The full text of the license may be found at\r | |
10 | http://opensource.org/licenses/bsd-license.php\r | |
11 | \r | |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | \r | |
15 | **/\r | |
16 | \r | |
17 | #include <Register/LocalApic.h>\r | |
18 | \r | |
19 | #include <Library/BaseLib.h>\r | |
20 | #include <Library/DebugLib.h>\r | |
21 | #include <Library/LocalApicLib.h>\r | |
22 | #include <Library/IoLib.h>\r | |
23 | #include <Library/TimerLib.h>\r | |
59d67246 | 24 | #include <Library/PcdLib.h>\r |
bf73cc4b | 25 | \r |
26 | //\r | |
27 | // Library internal functions\r | |
28 | //\r | |
29 | \r | |
59d67246 MK |
30 | /**\r |
31 | Determine if the CPU supports the Local APIC Base Address MSR.\r | |
32 | \r | |
33 | @retval TRUE The CPU supports the Local APIC Base Address MSR.\r | |
34 | @retval FALSE The CPU does not support the Local APIC Base Address MSR.\r | |
35 | \r | |
36 | **/\r | |
37 | BOOLEAN\r | |
38 | LocalApicBaseAddressMsrSupported (\r | |
39 | VOID\r | |
40 | )\r | |
41 | {\r | |
42 | UINT32 RegEax;\r | |
43 | UINTN FamilyId;\r | |
44 | \r | |
45 | AsmCpuid (1, &RegEax, NULL, NULL, NULL);\r | |
46 | FamilyId = BitFieldRead32 (RegEax, 8, 11);\r | |
47 | if (FamilyId == 0x04 || FamilyId == 0x05) {\r | |
48 | //\r | |
49 | // CPUs with a FamilyId of 0x04 or 0x05 do not support the \r | |
50 | // Local APIC Base Address MSR\r | |
51 | //\r | |
52 | return FALSE;\r | |
53 | }\r | |
54 | return TRUE;\r | |
55 | }\r | |
56 | \r | |
a66e0c7d | 57 | /**\r |
58 | Retrieve the base address of local APIC.\r | |
59 | \r | |
60 | @return The base address of local APIC.\r | |
61 | \r | |
62 | **/\r | |
63 | UINTN\r | |
64 | EFIAPI\r | |
65 | GetLocalApicBaseAddress (\r | |
66 | VOID\r | |
67 | )\r | |
68 | {\r | |
59d67246 MK |
69 | MSR_IA32_APIC_BASE ApicBaseMsr;\r |
70 | \r | |
71 | if (!LocalApicBaseAddressMsrSupported ()) {\r | |
72 | //\r | |
73 | // If CPU does not support Local APIC Base Address MSR, then retrieve\r | |
74 | // Local APIC Base Address from PCD\r | |
75 | //\r | |
76 | return PcdGet32 (PcdCpuLocalApicBaseAddress);\r | |
77 | }\r | |
78 | \r | |
a66e0c7d | 79 | ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r |
80 | \r | |
81 | return (UINTN)(LShiftU64 ((UINT64) ApicBaseMsr.Bits.ApicBaseHigh, 32)) +\r | |
82 | (((UINTN)ApicBaseMsr.Bits.ApicBaseLow) << 12);\r | |
83 | }\r | |
84 | \r | |
85 | /**\r | |
86 | Set the base address of local APIC.\r | |
87 | \r | |
88 | If BaseAddress is not aligned on a 4KB boundary, then ASSERT().\r | |
89 | \r | |
90 | @param[in] BaseAddress Local APIC base address to be set.\r | |
91 | \r | |
92 | **/\r | |
93 | VOID\r | |
94 | EFIAPI\r | |
95 | SetLocalApicBaseAddress (\r | |
96 | IN UINTN BaseAddress\r | |
97 | )\r | |
98 | {\r | |
59d67246 | 99 | MSR_IA32_APIC_BASE ApicBaseMsr;\r |
a66e0c7d | 100 | \r |
101 | ASSERT ((BaseAddress & (SIZE_4KB - 1)) == 0);\r | |
102 | \r | |
59d67246 MK |
103 | if (!LocalApicBaseAddressMsrSupported ()) {\r |
104 | //\r | |
105 | // Ignore set request if the CPU does not support APIC Base Address MSR\r | |
106 | //\r | |
107 | return;\r | |
108 | }\r | |
109 | \r | |
a66e0c7d | 110 | ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r |
111 | \r | |
112 | ApicBaseMsr.Bits.ApicBaseLow = (UINT32) (BaseAddress >> 12);\r | |
113 | ApicBaseMsr.Bits.ApicBaseHigh = (UINT32) (RShiftU64((UINT64) BaseAddress, 32));\r | |
114 | \r | |
115 | AsmWriteMsr64 (MSR_IA32_APIC_BASE_ADDRESS, ApicBaseMsr.Uint64);\r | |
116 | }\r | |
117 | \r | |
bf73cc4b | 118 | /**\r |
119 | Read from a local APIC register.\r | |
120 | \r | |
121 | This function reads from a local APIC register either in xAPIC or x2APIC mode.\r | |
122 | It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be\r | |
123 | accessed using multiple 32-bit loads or stores, so this function only performs\r | |
124 | 32-bit read.\r | |
125 | \r | |
126 | @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.\r | |
127 | It must be 16-byte aligned.\r | |
128 | \r | |
129 | @return 32-bit Value read from the register.\r | |
130 | **/\r | |
131 | UINT32\r | |
132 | EFIAPI\r | |
133 | ReadLocalApicReg (\r | |
134 | IN UINTN MmioOffset\r | |
135 | )\r | |
136 | {\r | |
137 | ASSERT ((MmioOffset & 0xf) == 0);\r | |
138 | ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r | |
139 | \r | |
a66e0c7d | 140 | return MmioRead32 (GetLocalApicBaseAddress() + MmioOffset);\r |
bf73cc4b | 141 | }\r |
142 | \r | |
143 | /**\r | |
144 | Write to a local APIC register.\r | |
145 | \r | |
146 | This function writes to a local APIC register either in xAPIC or x2APIC mode.\r | |
147 | It is required that in xAPIC mode wider registers (64-bit or 256-bit) must be\r | |
148 | accessed using multiple 32-bit loads or stores, so this function only performs\r | |
149 | 32-bit write.\r | |
150 | \r | |
151 | if the register index is invalid or unsupported in current APIC mode, then ASSERT.\r | |
152 | \r | |
153 | @param MmioOffset The MMIO offset of the local APIC register in xAPIC mode.\r | |
154 | It must be 16-byte aligned.\r | |
155 | @param Value Value to be written to the register.\r | |
156 | **/\r | |
157 | VOID\r | |
158 | EFIAPI\r | |
159 | WriteLocalApicReg (\r | |
160 | IN UINTN MmioOffset,\r | |
161 | IN UINT32 Value\r | |
162 | )\r | |
163 | {\r | |
164 | ASSERT ((MmioOffset & 0xf) == 0);\r | |
165 | ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r | |
166 | \r | |
a66e0c7d | 167 | MmioWrite32 (GetLocalApicBaseAddress() + MmioOffset, Value);\r |
bf73cc4b | 168 | }\r |
169 | \r | |
170 | /**\r | |
171 | Send an IPI by writing to ICR.\r | |
172 | \r | |
173 | This function returns after the IPI has been accepted by the target processor. \r | |
174 | \r | |
175 | @param IcrLow 32-bit value to be written to the low half of ICR.\r | |
176 | @param ApicId APIC ID of the target processor if this IPI is targeted for a specific processor.\r | |
177 | **/\r | |
178 | VOID\r | |
179 | SendIpi (\r | |
180 | IN UINT32 IcrLow,\r | |
181 | IN UINT32 ApicId\r | |
182 | )\r | |
183 | {\r | |
184 | LOCAL_APIC_ICR_LOW IcrLowReg;\r | |
9c71e1e0 JF |
185 | UINT32 IcrHigh;\r |
186 | BOOLEAN InterruptState;\r | |
bf73cc4b | 187 | \r |
188 | ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r | |
189 | ASSERT (ApicId <= 0xff);\r | |
190 | \r | |
9c71e1e0 JF |
191 | InterruptState = SaveAndDisableInterrupts ();\r |
192 | \r | |
193 | //\r | |
194 | // Save existing contents of ICR high 32 bits\r | |
195 | //\r | |
196 | IcrHigh = ReadLocalApicReg (XAPIC_ICR_HIGH_OFFSET);\r | |
197 | \r | |
198 | //\r | |
199 | // Wait for DeliveryStatus clear in case a previous IPI\r | |
200 | // is still being sent\r | |
201 | //\r | |
202 | do {\r | |
203 | IcrLowReg.Uint32 = ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET);\r | |
204 | } while (IcrLowReg.Bits.DeliveryStatus != 0);\r | |
205 | \r | |
bf73cc4b | 206 | //\r |
207 | // For xAPIC, the act of writing to the low doubleword of the ICR causes the IPI to be sent.\r | |
208 | //\r | |
209 | WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, ApicId << 24);\r | |
210 | WriteLocalApicReg (XAPIC_ICR_LOW_OFFSET, IcrLow);\r | |
9c71e1e0 JF |
211 | \r |
212 | //\r | |
213 | // Wait for DeliveryStatus clear again\r | |
214 | //\r | |
bf73cc4b | 215 | do {\r |
216 | IcrLowReg.Uint32 = ReadLocalApicReg (XAPIC_ICR_LOW_OFFSET);\r | |
217 | } while (IcrLowReg.Bits.DeliveryStatus != 0);\r | |
9c71e1e0 JF |
218 | \r |
219 | //\r | |
220 | // And restore old contents of ICR high\r | |
221 | //\r | |
222 | WriteLocalApicReg (XAPIC_ICR_HIGH_OFFSET, IcrHigh);\r | |
223 | \r | |
224 | SetInterruptState (InterruptState);\r | |
225 | \r | |
bf73cc4b | 226 | }\r |
227 | \r | |
228 | //\r | |
229 | // Library API implementation functions\r | |
230 | //\r | |
231 | \r | |
232 | /**\r | |
233 | Get the current local APIC mode.\r | |
234 | \r | |
235 | If local APIC is disabled, then ASSERT.\r | |
236 | \r | |
237 | @retval LOCAL_APIC_MODE_XAPIC current APIC mode is xAPIC.\r | |
238 | @retval LOCAL_APIC_MODE_X2APIC current APIC mode is x2APIC.\r | |
239 | **/\r | |
240 | UINTN\r | |
241 | EFIAPI\r | |
242 | GetApicMode (\r | |
243 | VOID\r | |
244 | )\r | |
245 | {\r | |
246 | DEBUG_CODE (\r | |
247 | {\r | |
59d67246 | 248 | MSR_IA32_APIC_BASE ApicBaseMsr;\r |
bf73cc4b | 249 | \r |
bf73cc4b | 250 | //\r |
59d67246 | 251 | // Check to see if the CPU supports the APIC Base Address MSR \r |
bf73cc4b | 252 | //\r |
59d67246 MK |
253 | if (LocalApicBaseAddressMsrSupported ()) {\r |
254 | ApicBaseMsr.Uint64 = AsmReadMsr64 (MSR_IA32_APIC_BASE_ADDRESS);\r | |
255 | //\r | |
256 | // Local APIC should have been enabled\r | |
257 | //\r | |
258 | ASSERT (ApicBaseMsr.Bits.En != 0);\r | |
259 | ASSERT (ApicBaseMsr.Bits.Extd == 0);\r | |
260 | }\r | |
bf73cc4b | 261 | }\r |
262 | );\r | |
263 | return LOCAL_APIC_MODE_XAPIC;\r | |
264 | }\r | |
265 | \r | |
266 | /**\r | |
267 | Set the current local APIC mode.\r | |
268 | \r | |
269 | If the specified local APIC mode is not valid, then ASSERT.\r | |
270 | If the specified local APIC mode can't be set as current, then ASSERT.\r | |
271 | \r | |
272 | @param ApicMode APIC mode to be set.\r | |
9c71e1e0 JF |
273 | \r |
274 | @note This API must not be called from an interrupt handler or SMI handler.\r | |
275 | It may result in unpredictable behavior.\r | |
bf73cc4b | 276 | **/\r |
277 | VOID\r | |
278 | EFIAPI\r | |
279 | SetApicMode (\r | |
280 | IN UINTN ApicMode\r | |
281 | )\r | |
282 | {\r | |
283 | ASSERT (ApicMode == LOCAL_APIC_MODE_XAPIC);\r | |
284 | ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r | |
285 | }\r | |
286 | \r | |
287 | /**\r | |
288 | Get the initial local APIC ID of the executing processor assigned by hardware upon power on or reset.\r | |
289 | \r | |
6e3e4d70 | 290 | In xAPIC mode, the initial local APIC ID may be different from current APIC ID.\r |
bf73cc4b | 291 | In x2APIC mode, the local APIC ID can't be changed and there is no concept of initial APIC ID. In this case, \r |
292 | the 32-bit local APIC ID is returned as initial APIC ID.\r | |
293 | \r | |
294 | @return 32-bit initial local APIC ID of the executing processor.\r | |
295 | **/\r | |
296 | UINT32\r | |
297 | EFIAPI\r | |
298 | GetInitialApicId (\r | |
299 | VOID\r | |
300 | )\r | |
301 | {\r | |
6e3e4d70 JF |
302 | UINT32 ApicId;\r |
303 | UINT32 MaxCpuIdIndex;\r | |
bf73cc4b | 304 | UINT32 RegEbx;\r |
305 | \r | |
306 | ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r | |
307 | \r | |
6e3e4d70 JF |
308 | //\r |
309 | // Get the max index of basic CPUID\r | |
310 | //\r | |
311 | AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);\r | |
312 | \r | |
313 | //\r | |
314 | // If CPUID Leaf B is supported, \r | |
315 | // Then the initial 32-bit APIC ID = CPUID.0BH:EDX\r | |
316 | // Else the initial 8-bit APIC ID = CPUID.1:EBX[31:24]\r | |
317 | //\r | |
318 | if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {\r | |
319 | AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, NULL, NULL, NULL, &ApicId);\r | |
320 | return ApicId;\r | |
321 | }\r | |
322 | \r | |
bf73cc4b | 323 | AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);\r |
324 | return RegEbx >> 24;\r | |
325 | }\r | |
326 | \r | |
327 | /**\r | |
328 | Get the local APIC ID of the executing processor.\r | |
329 | \r | |
330 | @return 32-bit local APIC ID of the executing processor.\r | |
331 | **/\r | |
332 | UINT32\r | |
333 | EFIAPI\r | |
334 | GetApicId (\r | |
335 | VOID\r | |
336 | )\r | |
337 | {\r | |
338 | UINT32 ApicId;\r | |
339 | \r | |
340 | ASSERT (GetApicMode () == LOCAL_APIC_MODE_XAPIC);\r | |
6e3e4d70 JF |
341 | \r |
342 | if ((ApicId = GetInitialApicId ()) < 0x100) {\r | |
343 | //\r | |
344 | // If the initial local APIC ID is less 0x100, read APIC ID from\r | |
345 | // XAPIC_ID_OFFSET, otherwise return the initial local APIC ID.\r | |
346 | //\r | |
347 | ApicId = ReadLocalApicReg (XAPIC_ID_OFFSET);\r | |
348 | ApicId >>= 24;\r | |
349 | }\r | |
bf73cc4b | 350 | return ApicId;\r |
351 | }\r | |
352 | \r | |
ae40aef1 | 353 | /**\r |
354 | Get the value of the local APIC version register.\r | |
355 | \r | |
356 | @return the value of the local APIC version register.\r | |
357 | **/\r | |
358 | UINT32\r | |
359 | EFIAPI\r | |
360 | GetApicVersion (\r | |
361 | VOID\r | |
362 | )\r | |
363 | {\r | |
364 | return ReadLocalApicReg (XAPIC_VERSION_OFFSET);\r | |
365 | }\r | |
366 | \r | |
367 | /**\r | |
368 | Send a Fixed IPI to a specified target processor.\r | |
369 | \r | |
370 | This function returns after the IPI has been accepted by the target processor. \r | |
371 | \r | |
372 | @param ApicId The local APIC ID of the target processor.\r | |
373 | @param Vector The vector number of the interrupt being sent.\r | |
374 | **/\r | |
375 | VOID\r | |
376 | EFIAPI\r | |
377 | SendFixedIpi (\r | |
378 | IN UINT32 ApicId,\r | |
379 | IN UINT8 Vector\r | |
380 | )\r | |
381 | {\r | |
382 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
383 | \r | |
384 | IcrLow.Uint32 = 0;\r | |
385 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;\r | |
386 | IcrLow.Bits.Level = 1;\r | |
387 | IcrLow.Bits.Vector = Vector;\r | |
388 | SendIpi (IcrLow.Uint32, ApicId);\r | |
389 | }\r | |
390 | \r | |
391 | /**\r | |
392 | Send a Fixed IPI to all processors excluding self.\r | |
393 | \r | |
394 | This function returns after the IPI has been accepted by the target processors. \r | |
395 | \r | |
396 | @param Vector The vector number of the interrupt being sent.\r | |
397 | **/\r | |
398 | VOID\r | |
399 | EFIAPI\r | |
400 | SendFixedIpiAllExcludingSelf (\r | |
401 | IN UINT8 Vector\r | |
402 | )\r | |
403 | {\r | |
404 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
405 | \r | |
406 | IcrLow.Uint32 = 0;\r | |
407 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_FIXED;\r | |
408 | IcrLow.Bits.Level = 1;\r | |
409 | IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r | |
410 | IcrLow.Bits.Vector = Vector;\r | |
411 | SendIpi (IcrLow.Uint32, 0);\r | |
412 | }\r | |
413 | \r | |
bf73cc4b | 414 | /**\r |
415 | Send a SMI IPI to a specified target processor.\r | |
416 | \r | |
417 | This function returns after the IPI has been accepted by the target processor. \r | |
418 | \r | |
419 | @param ApicId Specify the local APIC ID of the target processor.\r | |
420 | **/\r | |
421 | VOID\r | |
422 | EFIAPI\r | |
423 | SendSmiIpi (\r | |
424 | IN UINT32 ApicId\r | |
425 | )\r | |
426 | {\r | |
427 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
428 | \r | |
429 | IcrLow.Uint32 = 0;\r | |
430 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;\r | |
431 | IcrLow.Bits.Level = 1;\r | |
432 | SendIpi (IcrLow.Uint32, ApicId);\r | |
433 | }\r | |
434 | \r | |
435 | /**\r | |
436 | Send a SMI IPI to all processors excluding self.\r | |
437 | \r | |
438 | This function returns after the IPI has been accepted by the target processors. \r | |
439 | **/\r | |
440 | VOID\r | |
441 | EFIAPI\r | |
442 | SendSmiIpiAllExcludingSelf (\r | |
443 | VOID\r | |
444 | )\r | |
445 | {\r | |
446 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
447 | \r | |
448 | IcrLow.Uint32 = 0;\r | |
449 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_SMI;\r | |
450 | IcrLow.Bits.Level = 1;\r | |
451 | IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r | |
452 | SendIpi (IcrLow.Uint32, 0);\r | |
453 | }\r | |
454 | \r | |
455 | /**\r | |
456 | Send an INIT IPI to a specified target processor.\r | |
457 | \r | |
458 | This function returns after the IPI has been accepted by the target processor. \r | |
459 | \r | |
460 | @param ApicId Specify the local APIC ID of the target processor.\r | |
461 | **/\r | |
462 | VOID\r | |
463 | EFIAPI\r | |
464 | SendInitIpi (\r | |
465 | IN UINT32 ApicId\r | |
466 | )\r | |
467 | {\r | |
468 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
469 | \r | |
470 | IcrLow.Uint32 = 0;\r | |
471 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;\r | |
472 | IcrLow.Bits.Level = 1;\r | |
473 | SendIpi (IcrLow.Uint32, ApicId);\r | |
474 | }\r | |
475 | \r | |
476 | /**\r | |
477 | Send an INIT IPI to all processors excluding self.\r | |
478 | \r | |
479 | This function returns after the IPI has been accepted by the target processors. \r | |
480 | **/\r | |
481 | VOID\r | |
482 | EFIAPI\r | |
483 | SendInitIpiAllExcludingSelf (\r | |
484 | VOID\r | |
485 | )\r | |
486 | {\r | |
487 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
488 | \r | |
489 | IcrLow.Uint32 = 0;\r | |
490 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_INIT;\r | |
491 | IcrLow.Bits.Level = 1;\r | |
492 | IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r | |
493 | SendIpi (IcrLow.Uint32, 0);\r | |
494 | }\r | |
495 | \r | |
496 | /**\r | |
497 | Send an INIT-Start-up-Start-up IPI sequence to a specified target processor.\r | |
498 | \r | |
499 | This function returns after the IPI has been accepted by the target processor. \r | |
500 | \r | |
501 | if StartupRoutine >= 1M, then ASSERT.\r | |
502 | if StartupRoutine is not multiple of 4K, then ASSERT.\r | |
503 | \r | |
504 | @param ApicId Specify the local APIC ID of the target processor.\r | |
505 | @param StartupRoutine Points to a start-up routine which is below 1M physical\r | |
506 | address and 4K aligned.\r | |
507 | **/\r | |
508 | VOID\r | |
509 | EFIAPI\r | |
510 | SendInitSipiSipi (\r | |
511 | IN UINT32 ApicId,\r | |
512 | IN UINT32 StartupRoutine\r | |
513 | )\r | |
514 | {\r | |
515 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
516 | \r | |
517 | ASSERT (StartupRoutine < 0x100000);\r | |
518 | ASSERT ((StartupRoutine & 0xfff) == 0);\r | |
519 | \r | |
520 | SendInitIpi (ApicId);\r | |
cf1eb6e6 | 521 | MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));\r |
bf73cc4b | 522 | IcrLow.Uint32 = 0;\r |
523 | IcrLow.Bits.Vector = (StartupRoutine >> 12);\r | |
524 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r | |
525 | IcrLow.Bits.Level = 1;\r | |
526 | SendIpi (IcrLow.Uint32, ApicId);\r | |
527 | MicroSecondDelay (200);\r | |
528 | SendIpi (IcrLow.Uint32, ApicId);\r | |
529 | }\r | |
530 | \r | |
531 | /**\r | |
532 | Send an INIT-Start-up-Start-up IPI sequence to all processors excluding self.\r | |
533 | \r | |
534 | This function returns after the IPI has been accepted by the target processors. \r | |
535 | \r | |
536 | if StartupRoutine >= 1M, then ASSERT.\r | |
537 | if StartupRoutine is not multiple of 4K, then ASSERT.\r | |
538 | \r | |
539 | @param StartupRoutine Points to a start-up routine which is below 1M physical\r | |
540 | address and 4K aligned.\r | |
541 | **/\r | |
542 | VOID\r | |
543 | EFIAPI\r | |
544 | SendInitSipiSipiAllExcludingSelf (\r | |
545 | IN UINT32 StartupRoutine\r | |
546 | )\r | |
547 | {\r | |
548 | LOCAL_APIC_ICR_LOW IcrLow;\r | |
549 | \r | |
550 | ASSERT (StartupRoutine < 0x100000);\r | |
551 | ASSERT ((StartupRoutine & 0xfff) == 0);\r | |
552 | \r | |
553 | SendInitIpiAllExcludingSelf ();\r | |
cf1eb6e6 | 554 | MicroSecondDelay (PcdGet32(PcdCpuInitIpiDelayInMicroSeconds));\r |
bf73cc4b | 555 | IcrLow.Uint32 = 0;\r |
556 | IcrLow.Bits.Vector = (StartupRoutine >> 12);\r | |
557 | IcrLow.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_STARTUP;\r | |
558 | IcrLow.Bits.Level = 1;\r | |
559 | IcrLow.Bits.DestinationShorthand = LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF;\r | |
560 | SendIpi (IcrLow.Uint32, 0);\r | |
561 | MicroSecondDelay (200);\r | |
562 | SendIpi (IcrLow.Uint32, 0);\r | |
563 | }\r | |
564 | \r | |
565 | /**\r | |
566 | Programming Virtual Wire Mode.\r | |
567 | \r | |
568 | This function programs the local APIC for virtual wire mode following\r | |
569 | the example described in chapter A.3 of the MP 1.4 spec.\r | |
570 | \r | |
571 | IOxAPIC is not involved in this type of virtual wire mode.\r | |
572 | **/\r | |
573 | VOID\r | |
574 | EFIAPI\r | |
575 | ProgramVirtualWireMode (\r | |
576 | VOID\r | |
577 | )\r | |
578 | {\r | |
579 | LOCAL_APIC_SVR Svr;\r | |
580 | LOCAL_APIC_LVT_LINT Lint;\r | |
581 | \r | |
582 | //\r | |
583 | // Enable the APIC via SVR and set the spurious interrupt to use Int 00F.\r | |
584 | //\r | |
585 | Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);\r | |
586 | Svr.Bits.SpuriousVector = 0xf;\r | |
587 | Svr.Bits.SoftwareEnable = 1;\r | |
588 | WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r | |
589 | \r | |
590 | //\r | |
591 | // Program the LINT0 vector entry as ExtInt. Not masked, edge, active high.\r | |
592 | //\r | |
ae40aef1 | 593 | Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);\r |
bf73cc4b | 594 | Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_EXTINT;\r |
595 | Lint.Bits.InputPinPolarity = 0;\r | |
596 | Lint.Bits.TriggerMode = 0;\r | |
597 | Lint.Bits.Mask = 0;\r | |
ae40aef1 | 598 | WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, Lint.Uint32);\r |
bf73cc4b | 599 | \r |
600 | //\r | |
601 | // Program the LINT0 vector entry as NMI. Not masked, edge, active high.\r | |
602 | //\r | |
ae40aef1 | 603 | Lint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);\r |
bf73cc4b | 604 | Lint.Bits.DeliveryMode = LOCAL_APIC_DELIVERY_MODE_NMI;\r |
605 | Lint.Bits.InputPinPolarity = 0;\r | |
606 | Lint.Bits.TriggerMode = 0;\r | |
607 | Lint.Bits.Mask = 0;\r | |
ae40aef1 | 608 | WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, Lint.Uint32);\r |
bf73cc4b | 609 | }\r |
610 | \r | |
b1b8c631 | 611 | /**\r |
612 | Disable LINT0 & LINT1 interrupts.\r | |
613 | \r | |
614 | This function sets the mask flag in the LVT LINT0 & LINT1 registers.\r | |
615 | **/\r | |
616 | VOID\r | |
617 | EFIAPI\r | |
618 | DisableLvtInterrupts (\r | |
619 | VOID\r | |
620 | )\r | |
621 | {\r | |
622 | LOCAL_APIC_LVT_LINT LvtLint;\r | |
623 | \r | |
624 | LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT0_OFFSET);\r | |
625 | LvtLint.Bits.Mask = 1;\r | |
626 | WriteLocalApicReg (XAPIC_LVT_LINT0_OFFSET, LvtLint.Uint32);\r | |
627 | \r | |
628 | LvtLint.Uint32 = ReadLocalApicReg (XAPIC_LVT_LINT1_OFFSET);\r | |
629 | LvtLint.Bits.Mask = 1;\r | |
630 | WriteLocalApicReg (XAPIC_LVT_LINT1_OFFSET, LvtLint.Uint32);\r | |
631 | }\r | |
632 | \r | |
bf73cc4b | 633 | /**\r |
634 | Read the initial count value from the init-count register.\r | |
635 | \r | |
636 | @return The initial count value read from the init-count register.\r | |
637 | **/\r | |
638 | UINT32\r | |
639 | EFIAPI\r | |
640 | GetApicTimerInitCount (\r | |
641 | VOID\r | |
642 | )\r | |
643 | {\r | |
644 | return ReadLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET);\r | |
645 | }\r | |
646 | \r | |
647 | /**\r | |
648 | Read the current count value from the current-count register.\r | |
649 | \r | |
650 | @return The current count value read from the current-count register.\r | |
651 | **/\r | |
652 | UINT32\r | |
653 | EFIAPI\r | |
654 | GetApicTimerCurrentCount (\r | |
655 | VOID\r | |
656 | )\r | |
657 | {\r | |
658 | return ReadLocalApicReg (XAPIC_TIMER_CURRENT_COUNT_OFFSET);\r | |
659 | }\r | |
660 | \r | |
661 | /**\r | |
662 | Initialize the local APIC timer.\r | |
663 | \r | |
664 | The local APIC timer is initialized and enabled.\r | |
665 | \r | |
666 | @param DivideValue The divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r | |
667 | If it is 0, then use the current divide value in the DCR.\r | |
668 | @param InitCount The initial count value.\r | |
669 | @param PeriodicMode If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r | |
670 | @param Vector The timer interrupt vector number.\r | |
671 | **/\r | |
672 | VOID\r | |
673 | EFIAPI\r | |
674 | InitializeApicTimer (\r | |
675 | IN UINTN DivideValue,\r | |
676 | IN UINT32 InitCount,\r | |
677 | IN BOOLEAN PeriodicMode,\r | |
678 | IN UINT8 Vector\r | |
679 | )\r | |
680 | {\r | |
681 | LOCAL_APIC_SVR Svr;\r | |
682 | LOCAL_APIC_DCR Dcr;\r | |
683 | LOCAL_APIC_LVT_TIMER LvtTimer;\r | |
684 | UINT32 Divisor;\r | |
685 | \r | |
686 | //\r | |
687 | // Ensure local APIC is in software-enabled state.\r | |
688 | //\r | |
689 | Svr.Uint32 = ReadLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET);\r | |
690 | Svr.Bits.SoftwareEnable = 1;\r | |
691 | WriteLocalApicReg (XAPIC_SPURIOUS_VECTOR_OFFSET, Svr.Uint32);\r | |
692 | \r | |
693 | //\r | |
694 | // Program init-count register.\r | |
695 | //\r | |
696 | WriteLocalApicReg (XAPIC_TIMER_INIT_COUNT_OFFSET, InitCount);\r | |
697 | \r | |
698 | if (DivideValue != 0) {\r | |
699 | ASSERT (DivideValue <= 128);\r | |
700 | ASSERT (DivideValue == GetPowerOfTwo32((UINT32)DivideValue));\r | |
701 | Divisor = (UINT32)((HighBitSet32 ((UINT32)DivideValue) - 1) & 0x7);\r | |
702 | \r | |
703 | Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r | |
704 | Dcr.Bits.DivideValue1 = (Divisor & 0x3);\r | |
705 | Dcr.Bits.DivideValue2 = (Divisor >> 2);\r | |
706 | WriteLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET, Dcr.Uint32); \r | |
707 | }\r | |
708 | \r | |
709 | //\r | |
710 | // Enable APIC timer interrupt with specified timer mode.\r | |
711 | //\r | |
712 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r | |
713 | if (PeriodicMode) {\r | |
714 | LvtTimer.Bits.TimerMode = 1;\r | |
715 | } else {\r | |
716 | LvtTimer.Bits.TimerMode = 0;\r | |
717 | }\r | |
718 | LvtTimer.Bits.Mask = 0;\r | |
719 | LvtTimer.Bits.Vector = Vector;\r | |
720 | WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r | |
721 | }\r | |
722 | \r | |
ae40aef1 | 723 | /**\r |
724 | Get the state of the local APIC timer.\r | |
725 | \r | |
726 | @param DivideValue Return the divide value for the DCR. It is one of 1,2,4,8,16,32,64,128.\r | |
727 | @param PeriodicMode Return the timer mode. If TRUE, timer mode is peridoic. Othewise, timer mode is one-shot.\r | |
728 | @param Vector Return the timer interrupt vector number.\r | |
729 | **/\r | |
730 | VOID\r | |
731 | EFIAPI\r | |
732 | GetApicTimerState (\r | |
733 | OUT UINTN *DivideValue OPTIONAL,\r | |
734 | OUT BOOLEAN *PeriodicMode OPTIONAL,\r | |
735 | OUT UINT8 *Vector OPTIONAL\r | |
736 | )\r | |
737 | {\r | |
738 | UINT32 Divisor;\r | |
739 | LOCAL_APIC_DCR Dcr;\r | |
740 | LOCAL_APIC_LVT_TIMER LvtTimer;\r | |
741 | \r | |
742 | if (DivideValue != NULL) {\r | |
743 | Dcr.Uint32 = ReadLocalApicReg (XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET);\r | |
744 | Divisor = Dcr.Bits.DivideValue1 | (Dcr.Bits.DivideValue2 << 2);\r | |
745 | Divisor = (Divisor + 1) & 0x7;\r | |
746 | *DivideValue = ((UINTN)1) << Divisor;\r | |
747 | }\r | |
748 | \r | |
749 | if (PeriodicMode != NULL || Vector != NULL) {\r | |
750 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r | |
751 | if (PeriodicMode != NULL) {\r | |
752 | if (LvtTimer.Bits.TimerMode == 1) {\r | |
753 | *PeriodicMode = TRUE;\r | |
754 | } else {\r | |
755 | *PeriodicMode = FALSE;\r | |
756 | }\r | |
757 | }\r | |
758 | if (Vector != NULL) {\r | |
759 | *Vector = (UINT8) LvtTimer.Bits.Vector;\r | |
760 | }\r | |
761 | }\r | |
762 | }\r | |
763 | \r | |
bf73cc4b | 764 | /**\r |
765 | Enable the local APIC timer interrupt.\r | |
766 | **/\r | |
767 | VOID\r | |
768 | EFIAPI\r | |
769 | EnableApicTimerInterrupt (\r | |
770 | VOID\r | |
771 | )\r | |
772 | {\r | |
773 | LOCAL_APIC_LVT_TIMER LvtTimer;\r | |
774 | \r | |
775 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r | |
776 | LvtTimer.Bits.Mask = 0;\r | |
777 | WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r | |
778 | }\r | |
779 | \r | |
780 | /**\r | |
781 | Disable the local APIC timer interrupt.\r | |
782 | **/\r | |
783 | VOID\r | |
784 | EFIAPI\r | |
785 | DisableApicTimerInterrupt (\r | |
786 | VOID\r | |
787 | )\r | |
788 | {\r | |
789 | LOCAL_APIC_LVT_TIMER LvtTimer;\r | |
790 | \r | |
791 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r | |
792 | LvtTimer.Bits.Mask = 1;\r | |
793 | WriteLocalApicReg (XAPIC_LVT_TIMER_OFFSET, LvtTimer.Uint32);\r | |
794 | }\r | |
795 | \r | |
796 | /**\r | |
797 | Get the local APIC timer interrupt state.\r | |
798 | \r | |
799 | @retval TRUE The local APIC timer interrupt is enabled.\r | |
800 | @retval FALSE The local APIC timer interrupt is disabled.\r | |
801 | **/\r | |
802 | BOOLEAN\r | |
803 | EFIAPI\r | |
804 | GetApicTimerInterruptState (\r | |
805 | VOID\r | |
806 | )\r | |
807 | {\r | |
808 | LOCAL_APIC_LVT_TIMER LvtTimer;\r | |
809 | \r | |
810 | LvtTimer.Uint32 = ReadLocalApicReg (XAPIC_LVT_TIMER_OFFSET);\r | |
811 | return (BOOLEAN)(LvtTimer.Bits.Mask == 0);\r | |
812 | }\r | |
813 | \r | |
814 | /**\r | |
815 | Send EOI to the local APIC.\r | |
816 | **/\r | |
817 | VOID\r | |
818 | EFIAPI\r | |
819 | SendApicEoi (\r | |
820 | VOID\r | |
821 | )\r | |
822 | {\r | |
823 | WriteLocalApicReg (XAPIC_EOI_OFFSET, 0);\r | |
824 | }\r | |
825 | \r | |
5f867ad0 | 826 | /**\r |
827 | Get the 32-bit address that a device should use to send a Message Signaled \r | |
828 | Interrupt (MSI) to the Local APIC of the currently executing processor.\r | |
829 | \r | |
830 | @return 32-bit address used to send an MSI to the Local APIC.\r | |
831 | **/\r | |
832 | UINT32\r | |
833 | EFIAPI \r | |
834 | GetApicMsiAddress (\r | |
835 | VOID\r | |
836 | )\r | |
837 | {\r | |
838 | LOCAL_APIC_MSI_ADDRESS MsiAddress;\r | |
839 | \r | |
840 | //\r | |
841 | // Return address for an MSI interrupt to be delivered only to the APIC ID \r | |
842 | // of the currently executing processor.\r | |
843 | //\r | |
844 | MsiAddress.Uint32 = 0;\r | |
845 | MsiAddress.Bits.BaseAddress = 0xFEE;\r | |
846 | MsiAddress.Bits.DestinationId = GetApicId ();\r | |
847 | return MsiAddress.Uint32;\r | |
848 | }\r | |
849 | \r | |
850 | /**\r | |
851 | Get the 64-bit data value that a device should use to send a Message Signaled \r | |
852 | Interrupt (MSI) to the Local APIC of the currently executing processor.\r | |
853 | \r | |
854 | If Vector is not in range 0x10..0xFE, then ASSERT().\r | |
855 | If DeliveryMode is not supported, then ASSERT().\r | |
856 | \r | |
857 | @param Vector The 8-bit interrupt vector associated with the MSI. \r | |
858 | Must be in the range 0x10..0xFE\r | |
859 | @param DeliveryMode A 3-bit value that specifies how the recept of the MSI \r | |
860 | is handled. The only supported values are:\r | |
861 | 0: LOCAL_APIC_DELIVERY_MODE_FIXED\r | |
862 | 1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY\r | |
863 | 2: LOCAL_APIC_DELIVERY_MODE_SMI\r | |
864 | 4: LOCAL_APIC_DELIVERY_MODE_NMI\r | |
865 | 5: LOCAL_APIC_DELIVERY_MODE_INIT\r | |
866 | 7: LOCAL_APIC_DELIVERY_MODE_EXTINT\r | |
867 | \r | |
868 | @param LevelTriggered TRUE specifies a level triggered interrupt. \r | |
869 | FALSE specifies an edge triggered interrupt.\r | |
870 | @param AssertionLevel Ignored if LevelTriggered is FALSE.\r | |
871 | TRUE specifies a level triggered interrupt that active \r | |
872 | when the interrupt line is asserted.\r | |
873 | FALSE specifies a level triggered interrupt that active \r | |
874 | when the interrupt line is deasserted.\r | |
875 | \r | |
876 | @return 64-bit data value used to send an MSI to the Local APIC.\r | |
877 | **/\r | |
878 | UINT64\r | |
879 | EFIAPI \r | |
880 | GetApicMsiValue (\r | |
881 | IN UINT8 Vector,\r | |
882 | IN UINTN DeliveryMode,\r | |
883 | IN BOOLEAN LevelTriggered,\r | |
884 | IN BOOLEAN AssertionLevel\r | |
885 | )\r | |
886 | {\r | |
887 | LOCAL_APIC_MSI_DATA MsiData;\r | |
888 | \r | |
889 | ASSERT (Vector >= 0x10 && Vector <= 0xFE);\r | |
890 | ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);\r | |
891 | \r | |
892 | MsiData.Uint64 = 0;\r | |
893 | MsiData.Bits.Vector = Vector;\r | |
894 | MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;\r | |
895 | if (LevelTriggered) {\r | |
896 | MsiData.Bits.TriggerMode = 1;\r | |
897 | if (AssertionLevel) {\r | |
898 | MsiData.Bits.Level = 1;\r | |
899 | }\r | |
900 | }\r | |
901 | return MsiData.Uint64;\r | |
902 | }\r |