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3e8ad6bd JF |
1 | /** @file\r |
2 | Common header file for MP Initialize Library.\r | |
3 | \r | |
08a475df | 4 | Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.<BR>\r |
4c0f6e34 LD |
5 | Copyright (c) 2020, AMD Inc. All rights reserved.<BR>\r |
6 | \r | |
0acd8697 | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
3e8ad6bd JF |
8 | \r |
9 | **/\r | |
10 | \r | |
11 | #ifndef _MP_LIB_H_\r | |
12 | #define _MP_LIB_H_\r | |
13 | \r | |
14 | #include <PiPei.h>\r | |
15 | \r | |
01acb06c | 16 | #include <Register/Intel/Cpuid.h>\r |
4c0f6e34 | 17 | #include <Register/Amd/Cpuid.h>\r |
01acb06c RN |
18 | #include <Register/Intel/Msr.h>\r |
19 | #include <Register/Intel/LocalApic.h>\r | |
20 | #include <Register/Intel/Microcode.h>\r | |
3e8ad6bd JF |
21 | \r |
22 | #include <Library/MpInitLib.h>\r | |
23 | #include <Library/BaseLib.h>\r | |
24 | #include <Library/BaseMemoryLib.h>\r | |
25 | #include <Library/MemoryAllocationLib.h>\r | |
26 | #include <Library/DebugLib.h>\r | |
27 | #include <Library/LocalApicLib.h>\r | |
28 | #include <Library/CpuLib.h>\r | |
29 | #include <Library/UefiCpuLib.h>\r | |
30 | #include <Library/TimerLib.h>\r | |
31 | #include <Library/SynchronizationLib.h>\r | |
32 | #include <Library/MtrrLib.h>\r | |
33 | #include <Library/HobLib.h>\r | |
34 | \r | |
348a34d9 HW |
35 | #include <Guid/MicrocodePatchHob.h>\r |
36 | \r | |
b8b04307 JF |
37 | #define WAKEUP_AP_SIGNAL SIGNATURE_32 ('S', 'T', 'A', 'P')\r |
38 | \r | |
93ca4c0f JF |
39 | #define CPU_INIT_MP_LIB_HOB_GUID \\r |
40 | { \\r | |
41 | 0x58eb6a19, 0x3699, 0x4c68, { 0xa8, 0x36, 0xda, 0xcd, 0x8e, 0xdc, 0xad, 0x4a } \\r | |
42 | }\r | |
43 | \r | |
41be0da5 JF |
44 | //\r |
45 | // The MP data for switch BSP\r | |
46 | //\r | |
47 | #define CPU_SWITCH_STATE_IDLE 0\r | |
48 | #define CPU_SWITCH_STATE_STORED 1\r | |
49 | #define CPU_SWITCH_STATE_LOADED 2\r | |
50 | \r | |
d786a172 HW |
51 | //\r |
52 | // Default maximum number of entries to store the microcode patches information\r | |
53 | //\r | |
54 | #define DEFAULT_MAX_MICROCODE_PATCH_NUM 8\r | |
55 | \r | |
56 | //\r | |
57 | // Data structure for microcode patch information\r | |
58 | //\r | |
59 | typedef struct {\r | |
60 | UINTN Address;\r | |
61 | UINTN Size;\r | |
d786a172 HW |
62 | } MICROCODE_PATCH_INFO;\r |
63 | \r | |
41be0da5 JF |
64 | //\r |
65 | // CPU exchange information for switch BSP\r | |
66 | //\r | |
67 | typedef struct {\r | |
68 | UINT8 State; // offset 0\r | |
69 | UINTN StackPointer; // offset 4 / 8\r | |
70 | IA32_DESCRIPTOR Gdtr; // offset 8 / 16\r | |
71 | IA32_DESCRIPTOR Idtr; // offset 14 / 26\r | |
72 | } CPU_EXCHANGE_ROLE_INFO;\r | |
73 | \r | |
9ebcf0f4 JF |
74 | //\r |
75 | // AP loop state when APs are in idle state\r | |
76 | // It's value is the same with PcdCpuApLoopMode\r | |
77 | //\r | |
78 | typedef enum {\r | |
79 | ApInHltLoop = 1,\r | |
80 | ApInMwaitLoop = 2,\r | |
81 | ApInRunLoop = 3\r | |
82 | } AP_LOOP_MODE;\r | |
83 | \r | |
e59f8f6b JF |
84 | //\r |
85 | // AP initialization state during APs wakeup\r | |
86 | //\r | |
87 | typedef enum {\r | |
88 | ApInitConfig = 1,\r | |
89 | ApInitReconfig = 2,\r | |
90 | ApInitDone = 3\r | |
91 | } AP_INIT_STATE;\r | |
92 | \r | |
03a1a925 JF |
93 | //\r |
94 | // AP state\r | |
95 | //\r | |
2a5997f8 ED |
96 | // The state transitions for an AP when it process a procedure are:\r |
97 | // Idle ----> Ready ----> Busy ----> Idle\r | |
98 | // [BSP] [AP] [AP]\r | |
99 | //\r | |
03a1a925 JF |
100 | typedef enum {\r |
101 | CpuStateIdle,\r | |
102 | CpuStateReady,\r | |
103 | CpuStateBusy,\r | |
e048ce88 | 104 | CpuStateFinished,\r |
03a1a925 JF |
105 | CpuStateDisabled\r |
106 | } CPU_STATE;\r | |
107 | \r | |
68cb9330 JF |
108 | //\r |
109 | // CPU volatile registers around INIT-SIPI-SIPI\r | |
110 | //\r | |
111 | typedef struct {\r | |
112 | UINTN Cr0;\r | |
113 | UINTN Cr3;\r | |
114 | UINTN Cr4;\r | |
115 | UINTN Dr0;\r | |
116 | UINTN Dr1;\r | |
117 | UINTN Dr2;\r | |
118 | UINTN Dr3;\r | |
119 | UINTN Dr6;\r | |
120 | UINTN Dr7;\r | |
e9415e48 JW |
121 | IA32_DESCRIPTOR Gdtr;\r |
122 | IA32_DESCRIPTOR Idtr;\r | |
123 | UINT16 Tr;\r | |
68cb9330 JF |
124 | } CPU_VOLATILE_REGISTERS;\r |
125 | \r | |
e59f8f6b JF |
126 | //\r |
127 | // AP related data\r | |
128 | //\r | |
129 | typedef struct {\r | |
130 | SPIN_LOCK ApLock;\r | |
131 | volatile UINT32 *StartupApSignal;\r | |
132 | volatile UINTN ApFunction;\r | |
133 | volatile UINTN ApFunctionArgument;\r | |
e59f8f6b | 134 | BOOLEAN CpuHealthy;\r |
03a1a925 | 135 | volatile CPU_STATE State;\r |
68cb9330 | 136 | CPU_VOLATILE_REGISTERS VolatileRegisters;\r |
e59f8f6b JF |
137 | BOOLEAN Waiting;\r |
138 | BOOLEAN *Finished;\r | |
139 | UINT64 ExpectedTime;\r | |
140 | UINT64 CurrentTime;\r | |
141 | UINT64 TotalTime;\r | |
142 | EFI_EVENT WaitEvent;\r | |
999463c8 HW |
143 | UINT32 ProcessorSignature;\r |
144 | UINT8 PlatformId;\r | |
e1ed5573 | 145 | UINT64 MicrocodeEntryAddr;\r |
e59f8f6b JF |
146 | } CPU_AP_DATA;\r |
147 | \r | |
148 | //\r | |
149 | // Basic CPU information saved in Guided HOB.\r | |
150 | // Because the contents will be shard between PEI and DXE,\r | |
151 | // we need to make sure the each fields offset same in different\r | |
152 | // architecture.\r | |
153 | //\r | |
dd3fa0cd | 154 | #pragma pack (1)\r |
e59f8f6b JF |
155 | typedef struct {\r |
156 | UINT32 InitialApicId;\r | |
157 | UINT32 ApicId;\r | |
158 | UINT32 Health;\r | |
dd3fa0cd | 159 | UINT64 ApTopOfStack;\r |
e59f8f6b | 160 | } CPU_INFO_IN_HOB;\r |
dd3fa0cd | 161 | #pragma pack ()\r |
e59f8f6b | 162 | \r |
f7f85d83 JF |
163 | //\r |
164 | // AP reset code information including code address and size,\r | |
165 | // this structure will be shared be C code and assembly code.\r | |
166 | // It is natural aligned by design.\r | |
167 | //\r | |
168 | typedef struct {\r | |
169 | UINT8 *RendezvousFunnelAddress;\r | |
170 | UINTN ModeEntryOffset;\r | |
171 | UINTN RendezvousFunnelSize;\r | |
172 | UINT8 *RelocateApLoopFuncAddress;\r | |
173 | UINTN RelocateApLoopFuncSize;\r | |
f32bfe6d | 174 | UINTN ModeTransitionOffset;\r |
f7f85d83 | 175 | } MP_ASSEMBLY_ADDRESS_MAP;\r |
3e8ad6bd | 176 | \r |
e59f8f6b JF |
177 | typedef struct _CPU_MP_DATA CPU_MP_DATA;\r |
178 | \r | |
d94e5f67 JF |
179 | #pragma pack(1)\r |
180 | \r | |
181 | //\r | |
182 | // MP CPU exchange information for AP reset code\r | |
183 | // This structure is required to be packed because fixed field offsets\r | |
184 | // into this structure are used in assembly code in this module\r | |
185 | //\r | |
186 | typedef struct {\r | |
187 | UINTN Lock;\r | |
188 | UINTN StackStart;\r | |
189 | UINTN StackSize;\r | |
190 | UINTN CFunction;\r | |
191 | IA32_DESCRIPTOR GdtrProfile;\r | |
192 | IA32_DESCRIPTOR IdtrProfile;\r | |
193 | UINTN BufferStart;\r | |
194 | UINTN ModeOffset;\r | |
37676b9f | 195 | UINTN ApIndex;\r |
d94e5f67 JF |
196 | UINTN CodeSegment;\r |
197 | UINTN DataSegment;\r | |
5c66d125 | 198 | UINTN EnableExecuteDisable;\r |
d94e5f67 | 199 | UINTN Cr3;\r |
46d4b885 JF |
200 | UINTN InitFlag;\r |
201 | CPU_INFO_IN_HOB *CpuInfo;\r | |
0594ec41 | 202 | UINTN NumApsExecuting;\r |
e59f8f6b | 203 | CPU_MP_DATA *CpuMpData;\r |
3b2928b4 | 204 | UINTN InitializeFloatingPointUnitsAddress;\r |
f32bfe6d JW |
205 | UINT32 ModeTransitionMemory;\r |
206 | UINT16 ModeTransitionSegment;\r | |
207 | UINT32 ModeHighMemory;\r | |
208 | UINT16 ModeHighSegment;\r | |
09f69a87 RN |
209 | //\r |
210 | // Enable5LevelPaging indicates whether 5-level paging is enabled in long mode.\r | |
211 | //\r | |
212 | BOOLEAN Enable5LevelPaging;\r | |
d94e5f67 JF |
213 | } MP_CPU_EXCHANGE_INFO;\r |
214 | \r | |
215 | #pragma pack()\r | |
e59f8f6b JF |
216 | \r |
217 | //\r | |
218 | // CPU MP Data save in memory\r | |
219 | //\r | |
220 | struct _CPU_MP_DATA {\r | |
221 | UINT64 CpuInfoInHob;\r | |
222 | UINT32 CpuCount;\r | |
223 | UINT32 BspNumber;\r | |
224 | //\r | |
225 | // The above fields data will be passed from PEI to DXE\r | |
226 | // Please make sure the fields offset same in the different\r | |
227 | // architecture.\r | |
228 | //\r | |
229 | SPIN_LOCK MpLock;\r | |
230 | UINTN Buffer;\r | |
231 | UINTN CpuApStackSize;\r | |
232 | MP_ASSEMBLY_ADDRESS_MAP AddressMap;\r | |
233 | UINTN WakeupBuffer;\r | |
66833b2a | 234 | UINTN WakeupBufferHigh;\r |
e59f8f6b JF |
235 | UINTN BackupBuffer;\r |
236 | UINTN BackupBufferSize;\r | |
e59f8f6b | 237 | \r |
e59f8f6b | 238 | volatile UINT32 FinishedCount;\r |
2da3e96c | 239 | UINT32 RunningCount;\r |
e59f8f6b JF |
240 | BOOLEAN SingleThread;\r |
241 | EFI_AP_PROCEDURE Procedure;\r | |
242 | VOID *ProcArguments;\r | |
243 | BOOLEAN *Finished;\r | |
244 | UINT64 ExpectedTime;\r | |
245 | UINT64 CurrentTime;\r | |
246 | UINT64 TotalTime;\r | |
247 | EFI_EVENT WaitEvent;\r | |
248 | UINTN **FailedCpuList;\r | |
249 | \r | |
250 | AP_INIT_STATE InitFlag;\r | |
41be0da5 | 251 | BOOLEAN SwitchBspFlag;\r |
b3775af2 | 252 | UINTN NewBspNumber;\r |
41be0da5 JF |
253 | CPU_EXCHANGE_ROLE_INFO BSPInfo;\r |
254 | CPU_EXCHANGE_ROLE_INFO APInfo;\r | |
e59f8f6b JF |
255 | MTRR_SETTINGS MtrrTable;\r |
256 | UINT8 ApLoopMode;\r | |
257 | UINT8 ApTargetCState;\r | |
258 | UINT16 PmCodeSegment;\r | |
259 | CPU_AP_DATA *CpuData;\r | |
260 | volatile MP_CPU_EXCHANGE_INFO *MpCpuExchangeInfo;\r | |
ffab2442 JF |
261 | \r |
262 | UINT32 CurrentTimerCount;\r | |
263 | UINTN DivideValue;\r | |
264 | UINT8 Vector;\r | |
265 | BOOLEAN PeriodicMode;\r | |
266 | BOOLEAN TimerInterruptState;\r | |
d148a178 HW |
267 | UINT64 MicrocodePatchAddress;\r |
268 | UINT64 MicrocodePatchRegionSize;\r | |
2a089134 | 269 | \r |
58942277 ED |
270 | //\r |
271 | // Whether need to use Init-Sipi-Sipi to wake up the APs.\r | |
272 | // Two cases need to set this value to TRUE. One is in HLT\r | |
273 | // loop mode, the other is resume from S3 which loop mode\r | |
e23d9c3e | 274 | // will be hardcode change to HLT mode by PiSmmCpuDxeSmm\r |
58942277 ED |
275 | // driver.\r |
276 | //\r | |
277 | BOOLEAN WakeUpByInitSipiSipi;\r | |
e59f8f6b | 278 | };\r |
93ca4c0f JF |
279 | \r |
280 | extern EFI_GUID mCpuInitMpLibHobGuid;\r | |
281 | \r | |
76157021 JF |
282 | /**\r |
283 | Assembly code to place AP into safe loop mode.\r | |
284 | \r | |
285 | Place AP into targeted C-State if MONITOR is supported, otherwise\r | |
286 | place AP into hlt state.\r | |
287 | Place AP in protected mode if the current is long mode. Due to AP maybe\r | |
288 | wakeup by some hardware event. It could avoid accessing page table that\r | |
289 | may not available during booting to OS.\r | |
290 | \r | |
291 | @param[in] MwaitSupport TRUE indicates MONITOR is supported.\r | |
292 | FALSE indicates MONITOR is not supported.\r | |
293 | @param[in] ApTargetCState Target C-State value.\r | |
294 | @param[in] PmCodeSegment Protected mode code segment value.\r | |
295 | **/\r | |
296 | typedef\r | |
297 | VOID\r | |
298 | (EFIAPI * ASM_RELOCATE_AP_LOOP) (\r | |
299 | IN BOOLEAN MwaitSupport,\r | |
300 | IN UINTN ApTargetCState,\r | |
bf2786dc | 301 | IN UINTN PmCodeSegment,\r |
9f91cb01 JF |
302 | IN UINTN TopOfApStack,\r |
303 | IN UINTN NumberToFinish\r | |
76157021 | 304 | );\r |
f7f85d83 JF |
305 | \r |
306 | /**\r | |
307 | Assembly code to get starting address and size of the rendezvous entry for APs.\r | |
308 | Information for fixing a jump instruction in the code is also returned.\r | |
309 | \r | |
310 | @param[out] AddressMap Output buffer for address map information.\r | |
311 | **/\r | |
312 | VOID\r | |
313 | EFIAPI\r | |
314 | AsmGetAddressMap (\r | |
315 | OUT MP_ASSEMBLY_ADDRESS_MAP *AddressMap\r | |
316 | );\r | |
317 | \r | |
41be0da5 JF |
318 | /**\r |
319 | This function is called by both the BSP and the AP which is to become the BSP to\r | |
320 | Exchange execution context including stack between them. After return from this\r | |
321 | function, the BSP becomes AP and the AP becomes the BSP.\r | |
322 | \r | |
323 | @param[in] MyInfo Pointer to buffer holding the exchanging information for the executing processor.\r | |
324 | @param[in] OthersInfo Pointer to buffer holding the exchanging information for the peer.\r | |
325 | \r | |
326 | **/\r | |
327 | VOID\r | |
328 | EFIAPI\r | |
329 | AsmExchangeRole (\r | |
330 | IN CPU_EXCHANGE_ROLE_INFO *MyInfo,\r | |
331 | IN CPU_EXCHANGE_ROLE_INFO *OthersInfo\r | |
332 | );\r | |
333 | \r | |
93ca4c0f JF |
334 | /**\r |
335 | Get the pointer to CPU MP Data structure.\r | |
336 | \r | |
337 | @return The pointer to CPU MP Data structure.\r | |
338 | **/\r | |
339 | CPU_MP_DATA *\r | |
340 | GetCpuMpData (\r | |
341 | VOID\r | |
342 | );\r | |
343 | \r | |
344 | /**\r | |
345 | Save the pointer to CPU MP Data structure.\r | |
346 | \r | |
347 | @param[in] CpuMpData The pointer to CPU MP Data structure will be saved.\r | |
348 | **/\r | |
349 | VOID\r | |
350 | SaveCpuMpData (\r | |
351 | IN CPU_MP_DATA *CpuMpData\r | |
352 | );\r | |
353 | \r | |
ed66e0e3 JF |
354 | \r |
355 | /**\r | |
a6b3d753 | 356 | Get available system memory below 1MB by specified size.\r |
ed66e0e3 | 357 | \r |
a6b3d753 SZ |
358 | @param[in] WakeupBufferSize Wakeup buffer size required\r |
359 | \r | |
360 | @retval other Return wakeup buffer address below 1MB.\r | |
361 | @retval -1 Cannot find free memory below 1MB.\r | |
ed66e0e3 | 362 | **/\r |
a6b3d753 SZ |
363 | UINTN\r |
364 | GetWakeupBuffer (\r | |
365 | IN UINTN WakeupBufferSize\r | |
ed66e0e3 JF |
366 | );\r |
367 | \r | |
f32bfe6d JW |
368 | /**\r |
369 | Get available EfiBootServicesCode memory below 4GB by specified size.\r | |
370 | \r | |
371 | This buffer is required to safely transfer AP from real address mode to\r | |
372 | protected mode or long mode, due to the fact that the buffer returned by\r | |
373 | GetWakeupBuffer() may be marked as non-executable.\r | |
374 | \r | |
375 | @param[in] BufferSize Wakeup transition buffer size.\r | |
376 | \r | |
377 | @retval other Return wakeup transition buffer address below 4GB.\r | |
378 | @retval 0 Cannot find free memory below 4GB.\r | |
379 | **/\r | |
380 | UINTN\r | |
381 | GetModeTransitionBuffer (\r | |
382 | IN UINTN BufferSize\r | |
383 | );\r | |
384 | \r | |
96f5920d JF |
385 | /**\r |
386 | This function will be called by BSP to wakeup AP.\r | |
387 | \r | |
388 | @param[in] CpuMpData Pointer to CPU MP Data\r | |
389 | @param[in] Broadcast TRUE: Send broadcast IPI to all APs\r | |
390 | FALSE: Send IPI to AP by ApicId\r | |
391 | @param[in] ProcessorNumber The handle number of specified processor\r | |
392 | @param[in] Procedure The function to be invoked by AP\r | |
393 | @param[in] ProcedureArgument The argument to be passed into AP function\r | |
cf4e79e4 | 394 | @param[in] WakeUpDisabledAps Whether need to wake up disabled APs in broadcast mode.\r |
96f5920d JF |
395 | **/\r |
396 | VOID\r | |
397 | WakeUpAP (\r | |
398 | IN CPU_MP_DATA *CpuMpData,\r | |
399 | IN BOOLEAN Broadcast,\r | |
400 | IN UINTN ProcessorNumber,\r | |
401 | IN EFI_AP_PROCEDURE Procedure, OPTIONAL\r | |
cf4e79e4 ED |
402 | IN VOID *ProcedureArgument, OPTIONAL\r |
403 | IN BOOLEAN WakeUpDisabledAps OPTIONAL\r | |
96f5920d JF |
404 | );\r |
405 | \r | |
93ca4c0f JF |
406 | /**\r |
407 | Initialize global data for MP support.\r | |
408 | \r | |
409 | @param[in] CpuMpData The pointer to CPU MP Data structure.\r | |
410 | **/\r | |
411 | VOID\r | |
412 | InitMpGlobalData (\r | |
413 | IN CPU_MP_DATA *CpuMpData\r | |
414 | );\r | |
415 | \r | |
86efe976 JF |
416 | /**\r |
417 | Worker function to execute a caller provided function on all enabled APs.\r | |
418 | \r | |
419 | @param[in] Procedure A pointer to the function to be run on\r | |
420 | enabled APs of the system.\r | |
421 | @param[in] SingleThread If TRUE, then all the enabled APs execute\r | |
422 | the function specified by Procedure one by\r | |
423 | one, in ascending order of processor handle\r | |
424 | number. If FALSE, then all the enabled APs\r | |
425 | execute the function specified by Procedure\r | |
426 | simultaneously.\r | |
ee0c39fa | 427 | @param[in] ExcludeBsp Whether let BSP also trig this task.\r |
86efe976 JF |
428 | @param[in] WaitEvent The event created by the caller with CreateEvent()\r |
429 | service.\r | |
367284e7 | 430 | @param[in] TimeoutInMicroseconds Indicates the time limit in microseconds for\r |
86efe976 JF |
431 | APs to return from Procedure, either for\r |
432 | blocking or non-blocking mode.\r | |
433 | @param[in] ProcedureArgument The parameter passed into Procedure for\r | |
434 | all APs.\r | |
435 | @param[out] FailedCpuList If all APs finish successfully, then its\r | |
436 | content is set to NULL. If not all APs\r | |
437 | finish before timeout expires, then its\r | |
438 | content is set to address of the buffer\r | |
439 | holding handle numbers of the failed APs.\r | |
440 | \r | |
441 | @retval EFI_SUCCESS In blocking mode, all APs have finished before\r | |
442 | the timeout expired.\r | |
443 | @retval EFI_SUCCESS In non-blocking mode, function has been dispatched\r | |
444 | to all enabled APs.\r | |
445 | @retval others Failed to Startup all APs.\r | |
446 | \r | |
447 | **/\r | |
448 | EFI_STATUS\r | |
ee0c39fa | 449 | StartupAllCPUsWorker (\r |
86efe976 JF |
450 | IN EFI_AP_PROCEDURE Procedure,\r |
451 | IN BOOLEAN SingleThread,\r | |
ee0c39fa | 452 | IN BOOLEAN ExcludeBsp,\r |
86efe976 JF |
453 | IN EFI_EVENT WaitEvent OPTIONAL,\r |
454 | IN UINTN TimeoutInMicroseconds,\r | |
455 | IN VOID *ProcedureArgument OPTIONAL,\r | |
456 | OUT UINTN **FailedCpuList OPTIONAL\r | |
457 | );\r | |
458 | \r | |
20ae5774 JF |
459 | /**\r |
460 | Worker function to let the caller get one enabled AP to execute a caller-provided\r | |
461 | function.\r | |
462 | \r | |
463 | @param[in] Procedure A pointer to the function to be run on\r | |
464 | enabled APs of the system.\r | |
465 | @param[in] ProcessorNumber The handle number of the AP.\r | |
466 | @param[in] WaitEvent The event created by the caller with CreateEvent()\r | |
467 | service.\r | |
367284e7 | 468 | @param[in] TimeoutInMicroseconds Indicates the time limit in microseconds for\r |
20ae5774 JF |
469 | APs to return from Procedure, either for\r |
470 | blocking or non-blocking mode.\r | |
471 | @param[in] ProcedureArgument The parameter passed into Procedure for\r | |
472 | all APs.\r | |
473 | @param[out] Finished If AP returns from Procedure before the\r | |
474 | timeout expires, its content is set to TRUE.\r | |
475 | Otherwise, the value is set to FALSE.\r | |
476 | \r | |
477 | @retval EFI_SUCCESS In blocking mode, specified AP finished before\r | |
478 | the timeout expires.\r | |
479 | @retval others Failed to Startup AP.\r | |
480 | \r | |
481 | **/\r | |
482 | EFI_STATUS\r | |
483 | StartupThisAPWorker (\r | |
484 | IN EFI_AP_PROCEDURE Procedure,\r | |
485 | IN UINTN ProcessorNumber,\r | |
486 | IN EFI_EVENT WaitEvent OPTIONAL,\r | |
487 | IN UINTN TimeoutInMicroseconds,\r | |
488 | IN VOID *ProcedureArgument OPTIONAL,\r | |
489 | OUT BOOLEAN *Finished OPTIONAL\r | |
490 | );\r | |
491 | \r | |
41be0da5 JF |
492 | /**\r |
493 | Worker function to switch the requested AP to be the BSP from that point onward.\r | |
494 | \r | |
495 | @param[in] ProcessorNumber The handle number of AP that is to become the new BSP.\r | |
496 | @param[in] EnableOldBSP If TRUE, then the old BSP will be listed as an\r | |
497 | enabled AP. Otherwise, it will be disabled.\r | |
498 | \r | |
499 | @retval EFI_SUCCESS BSP successfully switched.\r | |
7367cc6c | 500 | @retval others Failed to switch BSP.\r |
41be0da5 JF |
501 | \r |
502 | **/\r | |
503 | EFI_STATUS\r | |
504 | SwitchBSPWorker (\r | |
505 | IN UINTN ProcessorNumber,\r | |
506 | IN BOOLEAN EnableOldBSP\r | |
507 | );\r | |
508 | \r | |
e37109bc JF |
509 | /**\r |
510 | Worker function to let the caller enable or disable an AP from this point onward.\r | |
511 | This service may only be called from the BSP.\r | |
512 | \r | |
513 | @param[in] ProcessorNumber The handle number of AP.\r | |
514 | @param[in] EnableAP Specifies the new state for the processor for\r | |
515 | enabled, FALSE for disabled.\r | |
516 | @param[in] HealthFlag If not NULL, a pointer to a value that specifies\r | |
517 | the new health status of the AP.\r | |
518 | \r | |
519 | @retval EFI_SUCCESS The specified AP was enabled or disabled successfully.\r | |
520 | @retval others Failed to Enable/Disable AP.\r | |
521 | \r | |
522 | **/\r | |
523 | EFI_STATUS\r | |
524 | EnableDisableApWorker (\r | |
525 | IN UINTN ProcessorNumber,\r | |
526 | IN BOOLEAN EnableAP,\r | |
527 | IN UINT32 *HealthFlag OPTIONAL\r | |
528 | );\r | |
529 | \r | |
93ca4c0f JF |
530 | /**\r |
531 | Get pointer to CPU MP Data structure from GUIDed HOB.\r | |
532 | \r | |
533 | @return The pointer to CPU MP Data structure.\r | |
534 | **/\r | |
535 | CPU_MP_DATA *\r | |
536 | GetCpuMpDataFromGuidedHob (\r | |
537 | VOID\r | |
538 | );\r | |
08085f08 JF |
539 | \r |
540 | /** Checks status of specified AP.\r | |
541 | \r | |
542 | This function checks whether the specified AP has finished the task assigned\r | |
543 | by StartupThisAP(), and whether timeout expires.\r | |
544 | \r | |
545 | @param[in] ProcessorNumber The handle number of processor.\r | |
546 | \r | |
547 | @retval EFI_SUCCESS Specified AP has finished task assigned by StartupThisAPs().\r | |
548 | @retval EFI_TIMEOUT The timeout expires.\r | |
549 | @retval EFI_NOT_READY Specified AP has not finished task and timeout has not expired.\r | |
550 | **/\r | |
551 | EFI_STATUS\r | |
552 | CheckThisAP (\r | |
553 | IN UINTN ProcessorNumber\r | |
554 | );\r | |
555 | \r | |
556 | /**\r | |
557 | Checks status of all APs.\r | |
558 | \r | |
559 | This function checks whether all APs have finished task assigned by StartupAllAPs(),\r | |
560 | and whether timeout expires.\r | |
561 | \r | |
562 | @retval EFI_SUCCESS All APs have finished task assigned by StartupAllAPs().\r | |
563 | @retval EFI_TIMEOUT The timeout expires.\r | |
564 | @retval EFI_NOT_READY APs have not finished task and timeout has not expired.\r | |
565 | **/\r | |
566 | EFI_STATUS\r | |
567 | CheckAllAPs (\r | |
568 | VOID\r | |
569 | );\r | |
570 | \r | |
571 | /**\r | |
572 | Checks APs status and updates APs status if needed.\r | |
573 | \r | |
574 | **/\r | |
575 | VOID\r | |
576 | CheckAndUpdateApsStatus (\r | |
577 | VOID\r | |
578 | );\r | |
579 | \r | |
94f63c76 JF |
580 | /**\r |
581 | Detect whether specified processor can find matching microcode patch and load it.\r | |
582 | \r | |
e1ed5573 HW |
583 | @param[in] CpuMpData The pointer to CPU MP Data structure.\r |
584 | @param[in] ProcessorNumber The handle number of the processor. The range is\r | |
585 | from 0 to the total number of logical processors\r | |
586 | minus 1.\r | |
94f63c76 JF |
587 | **/\r |
588 | VOID\r | |
589 | MicrocodeDetect (\r | |
2a089134 | 590 | IN CPU_MP_DATA *CpuMpData,\r |
e1ed5573 | 591 | IN UINTN ProcessorNumber\r |
94f63c76 JF |
592 | );\r |
593 | \r | |
d786a172 | 594 | /**\r |
dd017041 | 595 | Shadow the required microcode patches data into memory.\r |
d786a172 HW |
596 | \r |
597 | @param[in, out] CpuMpData The pointer to CPU MP Data structure.\r | |
598 | **/\r | |
599 | VOID\r | |
dd017041 | 600 | ShadowMicrocodeUpdatePatch (\r |
d786a172 HW |
601 | IN OUT CPU_MP_DATA *CpuMpData\r |
602 | );\r | |
603 | \r | |
348a34d9 HW |
604 | /**\r |
605 | Get the cached microcode patch base address and size from the microcode patch\r | |
606 | information cache HOB.\r | |
607 | \r | |
608 | @param[out] Address Base address of the microcode patches data.\r | |
609 | It will be updated if the microcode patch\r | |
610 | information cache HOB is found.\r | |
611 | @param[out] RegionSize Size of the microcode patches data.\r | |
612 | It will be updated if the microcode patch\r | |
613 | information cache HOB is found.\r | |
614 | \r | |
615 | @retval TRUE The microcode patch information cache HOB is found.\r | |
616 | @retval FALSE The microcode patch information cache HOB is not found.\r | |
617 | \r | |
618 | **/\r | |
619 | BOOLEAN\r | |
620 | GetMicrocodePatchInfoFromHob (\r | |
621 | UINT64 *Address,\r | |
622 | UINT64 *RegionSize\r | |
623 | );\r | |
624 | \r | |
4d3314f6 JF |
625 | /**\r |
626 | Detect whether Mwait-monitor feature is supported.\r | |
627 | \r | |
628 | @retval TRUE Mwait-monitor feature is supported.\r | |
629 | @retval FALSE Mwait-monitor feature is not supported.\r | |
630 | **/\r | |
631 | BOOLEAN\r | |
632 | IsMwaitSupport (\r | |
633 | VOID\r | |
634 | );\r | |
635 | \r | |
43c9fdcc JF |
636 | /**\r |
637 | Enable Debug Agent to support source debugging on AP function.\r | |
638 | \r | |
639 | **/\r | |
640 | VOID\r | |
641 | EnableDebugAgent (\r | |
642 | VOID\r | |
643 | );\r | |
644 | \r | |
e1ed5573 HW |
645 | /**\r |
646 | Find the current Processor number by APIC ID.\r | |
647 | \r | |
648 | @param[in] CpuMpData Pointer to PEI CPU MP Data\r | |
649 | @param[out] ProcessorNumber Return the pocessor number found\r | |
650 | \r | |
651 | @retval EFI_SUCCESS ProcessorNumber is found and returned.\r | |
652 | @retval EFI_NOT_FOUND ProcessorNumber is not found.\r | |
653 | **/\r | |
654 | EFI_STATUS\r | |
655 | GetProcessorNumber (\r | |
656 | IN CPU_MP_DATA *CpuMpData,\r | |
657 | OUT UINTN *ProcessorNumber\r | |
658 | );\r | |
659 | \r | |
c788c2b1 SF |
660 | /**\r |
661 | This funtion will try to invoke platform specific microcode shadow logic to\r | |
662 | relocate microcode update patches into memory.\r | |
663 | \r | |
4ac82ea1 | 664 | @param[in, out] CpuMpData The pointer to CPU MP Data structure.\r |
c788c2b1 SF |
665 | \r |
666 | @retval EFI_SUCCESS Shadow microcode success.\r | |
667 | @retval EFI_OUT_OF_RESOURCES No enough resource to complete the operation.\r | |
668 | @retval EFI_UNSUPPORTED Can't find platform specific microcode shadow\r | |
669 | PPI/Protocol.\r | |
670 | **/\r | |
671 | EFI_STATUS\r | |
672 | PlatformShadowMicrocode (\r | |
673 | IN OUT CPU_MP_DATA *CpuMpData\r | |
674 | );\r | |
675 | \r | |
3e8ad6bd JF |
676 | #endif\r |
677 | \r |