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Commit | Line | Data |
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246cd908 | 1 | ;------------------------------------------------------------------------------ ;\r |
e21e355e | 2 | ; Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r |
0acd8697 | 3 | ; SPDX-License-Identifier: BSD-2-Clause-Patent\r |
246cd908 LG |
4 | ;\r |
5 | ; Module Name:\r | |
6 | ;\r | |
7 | ; SmmInit.nasm\r | |
8 | ;\r | |
9 | ; Abstract:\r | |
10 | ;\r | |
11 | ; Functions for relocating SMBASE's for all processors\r | |
12 | ;\r | |
13 | ;-------------------------------------------------------------------------------\r | |
14 | \r | |
ada4a003 | 15 | %include "StuffRsbNasm.inc"\r |
02f7fd15 | 16 | \r |
246cd908 LG |
17 | extern ASM_PFX(SmmInitHandler)\r |
18 | extern ASM_PFX(mRebasedFlag)\r | |
19 | extern ASM_PFX(mSmmRelocationOriginalAddress)\r | |
20 | \r | |
6b0841c1 | 21 | global ASM_PFX(gPatchSmmCr3)\r |
351b49c1 | 22 | global ASM_PFX(gPatchSmmCr4)\r |
f0053e83 | 23 | global ASM_PFX(gPatchSmmCr0)\r |
5830d2c3 | 24 | global ASM_PFX(gPatchSmmInitStack)\r |
246cd908 LG |
25 | global ASM_PFX(gcSmiInitGdtr)\r |
26 | global ASM_PFX(gcSmmInitSize)\r | |
27 | global ASM_PFX(gcSmmInitTemplate)\r | |
28 | \r | |
29 | %define PROTECT_MODE_CS 0x8\r | |
30 | %define PROTECT_MODE_DS 0x20\r | |
31 | \r | |
32 | SECTION .text\r | |
33 | \r | |
34 | ASM_PFX(gcSmiInitGdtr):\r | |
35 | DW 0\r | |
36 | DQ 0\r | |
37 | \r | |
38 | global ASM_PFX(SmmStartup)\r | |
e75ee972 LE |
39 | \r |
40 | BITS 16\r | |
246cd908 | 41 | ASM_PFX(SmmStartup):\r |
d4d87596 JW |
42 | mov eax, 0x80000001 ; read capability\r |
43 | cpuid\r | |
d4d87596 | 44 | mov ebx, edx ; rdmsr will change edx. keep it in ebx.\r |
8d4d55b1 LE |
45 | and ebx, BIT20 ; extract NX capability bit\r |
46 | shr ebx, 9 ; shift bit to IA32_EFER.NXE[BIT11] position\r | |
6b0841c1 LE |
47 | mov eax, strict dword 0 ; source operand will be patched\r |
48 | ASM_PFX(gPatchSmmCr3):\r | |
246cd908 | 49 | mov cr3, eax\r |
e75ee972 | 50 | o32 lgdt [cs:ebp + (ASM_PFX(gcSmiInitGdtr) - ASM_PFX(SmmStartup))]\r |
351b49c1 LE |
51 | mov eax, strict dword 0 ; source operand will be patched\r |
52 | ASM_PFX(gPatchSmmCr4):\r | |
246cd908 | 53 | mov cr4, eax\r |
d4d87596 JW |
54 | mov ecx, 0xc0000080 ; IA32_EFER MSR\r |
55 | rdmsr\r | |
8d4d55b1 | 56 | or eax, ebx ; set NXE bit if NX is available\r |
d4d87596 | 57 | wrmsr\r |
f0053e83 LE |
58 | mov eax, strict dword 0 ; source operand will be patched\r |
59 | ASM_PFX(gPatchSmmCr0):\r | |
e75ee972 | 60 | mov di, PROTECT_MODE_DS\r |
246cd908 | 61 | mov cr0, eax\r |
456c4cca | 62 | jmp PROTECT_MODE_CS : dword @32bit\r |
e75ee972 LE |
63 | \r |
64 | BITS 32\r | |
246cd908 LG |
65 | @32bit:\r |
66 | mov ds, edi\r | |
67 | mov es, edi\r | |
68 | mov fs, edi\r | |
69 | mov gs, edi\r | |
70 | mov ss, edi\r | |
5830d2c3 LE |
71 | mov esp, strict dword 0 ; source operand will be patched\r |
72 | ASM_PFX(gPatchSmmInitStack):\r | |
246cd908 | 73 | call ASM_PFX(SmmInitHandler)\r |
02f7fd15 | 74 | StuffRsb32\r |
246cd908 LG |
75 | rsm\r |
76 | \r | |
77 | BITS 16\r | |
78 | ASM_PFX(gcSmmInitTemplate):\r | |
79 | mov ebp, ASM_PFX(SmmStartup)\r | |
80 | sub ebp, 0x30000\r | |
81 | jmp ebp\r | |
82 | \r | |
83 | ASM_PFX(gcSmmInitSize): DW $ - ASM_PFX(gcSmmInitTemplate)\r | |
84 | \r | |
85 | BITS 32\r | |
86 | global ASM_PFX(SmmRelocationSemaphoreComplete)\r | |
87 | ASM_PFX(SmmRelocationSemaphoreComplete):\r | |
88 | push eax\r | |
89 | mov eax, [ASM_PFX(mRebasedFlag)]\r | |
90 | mov byte [eax], 1\r | |
91 | pop eax\r | |
92 | jmp [ASM_PFX(mSmmRelocationOriginalAddress)]\r | |
e21e355e LG |
93 | \r |
94 | global ASM_PFX(PiSmmCpuSmmInitFixupAddress)\r | |
95 | ASM_PFX(PiSmmCpuSmmInitFixupAddress):\r | |
96 | ret\r |