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1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>\r | |
4 | \r\r | |
5 | This program and the accompanying materials are licensed and made available under\r\r | |
6 | the terms and conditions of the BSD License that accompanies this distribution. \r\r | |
7 | The full text of the license may be found at \r\r | |
8 | http://opensource.org/licenses/bsd-license.php. \r\r | |
9 | \r\r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r\r | |
12 | \r\r | |
13 | \r | |
14 | \r | |
15 | Module Name:\r | |
16 | \r | |
17 | IdeBus.h\r | |
18 | \r | |
19 | Abstract:\r | |
20 | \r | |
21 | System reset Library Services. This library class provides a set of\r | |
22 | methods to reset whole system with manipulate ICH.\r | |
23 | \r | |
24 | **/\r | |
25 | \r | |
26 | \r | |
27 | #include <Base.h>\r | |
28 | \r | |
29 | \r | |
30 | #include <Library/ResetSystemLib.h>\r | |
31 | #include <Library/BaseLib.h>\r | |
32 | #include <Library/IoLib.h>\r | |
33 | #include <Library/DebugLib.h>\r | |
34 | #include <Library/PciLib.h>\r | |
35 | \r | |
36 | #include "PchRegs.h"\r | |
37 | #include "Rsci.h"\r | |
38 | #include "Platform.h"\r | |
39 | \r | |
40 | #define RESET_GENERATOR_PORT R_PCH_RST_CNT\r | |
41 | \r | |
42 | VOID\r | |
43 | EFIAPI\r | |
44 | PlatformResetHook (\r | |
45 | UINT8 ResetType\r | |
46 | )\r | |
47 | {\r | |
48 | //\r | |
49 | // Platform need to save OS reset request/types for next Android boot\r | |
50 | //\r | |
51 | IoWrite8 (0x72, CMOS_RESET_TYPE_BY_OS);\r | |
52 | IoWrite8 (0x73, ResetType);\r | |
53 | }\r | |
54 | \r | |
55 | /**\r | |
56 | Calling this function causes a system-wide reset. This sets\r | |
57 | all circuitry within the system to its initial state. This type of reset\r | |
58 | is asynchronous to system operation and operates without regard to\r | |
59 | cycle boundaries.\r | |
60 | \r | |
61 | System reset should not return, if it returns, it means the system does\r | |
62 | not support cold reset.\r | |
63 | **/\r | |
64 | VOID\r | |
65 | EFIAPI\r | |
66 | ResetCold (\r | |
67 | VOID\r | |
68 | )\r | |
69 | {\r | |
70 | PlatformResetHook(COLD_RESET);\r | |
71 | IoWrite8 (RESET_GENERATOR_PORT, 0x2);\r | |
72 | IoWrite8 (RESET_GENERATOR_PORT, 0x6);\r | |
73 | }\r | |
74 | \r | |
75 | /**\r | |
76 | Calling this function causes a system-wide initialization. The processors\r | |
77 | are set to their initial state, and pending cycles are not corrupted.\r | |
78 | \r | |
79 | System reset should not return, if it returns, it means the system does\r | |
80 | not support warm reset.\r | |
81 | **/\r | |
82 | VOID\r | |
83 | EFIAPI\r | |
84 | ResetWarm (\r | |
85 | VOID\r | |
86 | )\r | |
87 | {\r | |
88 | PlatformResetHook(WARM_RESET);\r | |
89 | IoWrite8 (RESET_GENERATOR_PORT, 0x0);\r | |
90 | IoWrite8 (RESET_GENERATOR_PORT, 0x4);\r | |
91 | }\r | |
92 | \r | |
93 | /**\r | |
94 | Calling this function causes the system to enter a power state equivalent\r | |
95 | to the ACPI G2/S5 or G3 states.\r | |
96 | \r | |
97 | System shutdown should not return, if it returns, it means the system does\r | |
98 | not support shut down reset.\r | |
99 | **/\r | |
100 | VOID\r | |
101 | EFIAPI\r | |
102 | ResetShutdown (\r | |
103 | VOID\r | |
104 | )\r | |
105 | {\r | |
106 | UINT16 PchPmioBase;\r | |
107 | UINT16 Data16;\r | |
108 | UINT32 Data32;\r | |
109 | \r | |
110 | PchPmioBase = (UINT16) (PciRead16 (PCI_LIB_ADDRESS(0, PCI_DEVICE_NUMBER_PCH_LPC, 0, R_PCH_LPC_ACPI_BASE)) & ~BIT0);\r | |
111 | \r | |
112 | //\r | |
113 | // Then, GPE0_EN should be disabled to avoid any GPI waking up the system from S5\r | |
114 | //\r | |
115 | Data16 = 0;\r | |
116 | IoWrite16 (\r | |
117 | (UINTN)(PchPmioBase + R_PCH_ACPI_GPE0a_EN),\r | |
118 | (UINT16)Data16\r | |
119 | );\r | |
120 | \r | |
121 | //\r | |
122 | // Clear Sleep SMI Status\r | |
123 | //\r | |
124 | IoWrite16 (PchPmioBase + R_PCH_SMI_STS,\r | |
125 | (UINT16)(IoRead16 (PchPmioBase + R_PCH_SMI_STS) | B_PCH_SMI_STS_ON_SLP_EN));\r | |
126 | //\r | |
127 | // Clear Sleep Type Enable\r | |
128 | //\r | |
129 | IoWrite16 (PchPmioBase + R_PCH_SMI_EN,\r | |
130 | (UINT16)(IoRead16 (PchPmioBase + R_PCH_SMI_EN) & (~B_PCH_SMI_EN_ON_SLP_EN)));\r | |
131 | //\r | |
132 | // Clear Power Button Status\r | |
133 | //\r | |
134 | IoWrite16(PchPmioBase + R_PCH_ACPI_PM1_STS, B_PCH_ACPI_PM1_STS_PWRBTN);\r | |
135 | \r | |
136 | //\r | |
137 | // Secondly, Power Button Status bit must be cleared\r | |
138 | //\r | |
139 | // Write a "1" to bit[8] of power button status register at\r | |
140 | // (ABASE + PM1_STS) to clear this bit\r | |
141 | // Clear it through SMI Status register\r | |
142 | //\r | |
143 | Data16 = B_PCH_SMI_STS_PM1_STS_REG;\r | |
144 | IoWrite16 ((UINTN) (PchPmioBase + R_PCH_SMI_STS), Data16);\r | |
145 | \r | |
146 | //\r | |
147 | // Finally, transform system into S5 sleep state\r | |
148 | //\r | |
149 | Data32 = IoRead32 ((UINTN) (PchPmioBase + R_PCH_ACPI_PM1_CNT));\r | |
150 | \r | |
151 | Data32 = (UINT32) ((Data32 &~(B_PCH_ACPI_PM1_CNT_SLP_TYP + B_PCH_ACPI_PM1_CNT_SLP_EN)) | V_PCH_ACPI_PM1_CNT_S5);\r | |
152 | \r | |
153 | IoWrite32 ((UINTN) (PchPmioBase + R_PCH_ACPI_PM1_CNT), Data32);\r | |
154 | \r | |
155 | Data32 = Data32 | B_PCH_ACPI_PM1_CNT_SLP_EN;\r | |
156 | \r | |
157 | IoWrite32 ((UINTN) (PchPmioBase + R_PCH_ACPI_PM1_CNT), Data32);\r | |
158 | \r | |
159 | return;\r | |
160 | }\r | |
161 | \r | |
162 | /**\r | |
163 | Calling this function causes the system to enter a power state for capsule\r | |
164 | update.\r | |
165 | \r | |
166 | Reset update should not return, if it returns, it means the system does\r | |
167 | not support capsule update.\r | |
168 | \r | |
169 | **/\r | |
170 | VOID\r | |
171 | EFIAPI\r | |
172 | EnterS3WithImmediateWake (\r | |
173 | VOID\r | |
174 | )\r | |
175 | {\r | |
176 | ASSERT (FALSE);\r | |
177 | }\r | |
178 | \r |