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3cbfba02 DW |
1 | /** @file\r |
2 | \r | |
d71c25cf DW |
3 | Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.<BR>\r |
4 | \r | |
5 | \r | |
6 | This program and the accompanying materials are licensed and made available under\r | |
7 | \r | |
8 | the terms and conditions of the BSD License that accompanies this distribution. \r | |
9 | \r | |
10 | The full text of the license may be found at \r | |
11 | \r | |
12 | http://opensource.org/licenses/bsd-license.php. \r | |
13 | \r | |
14 | \r | |
15 | \r | |
16 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
17 | \r | |
18 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
19 | \r | |
20 | \r | |
21 | \r | |
3cbfba02 DW |
22 | \r |
23 | Module Name:\r | |
24 | \r | |
25 | \r | |
26 | Platform.c\r | |
27 | \r | |
28 | Abstract:\r | |
29 | \r | |
30 | Platform Initialization Driver.\r | |
31 | \r | |
32 | \r | |
33 | --*/\r | |
34 | \r | |
35 | #include "PlatformDxe.h"\r | |
36 | #include "Platform.h"\r | |
37 | #include "PchCommonDefinitions.h"\r | |
38 | #include <Protocol/UsbPolicy.h>\r | |
39 | #include <Protocol/PchPlatformPolicy.h>\r | |
40 | #include <Protocol/TpmMp.h>\r | |
41 | #include <Protocol/CpuIo2.h>\r | |
42 | #include <Library/S3BootScriptLib.h>\r | |
43 | #include <Guid/PciLanInfo.h>\r | |
44 | #include <Guid/ItkData.h>\r | |
45 | #include <Library/PciLib.h>\r | |
46 | #include <PlatformBootMode.h>\r | |
47 | #include <Guid/EventGroup.h>\r | |
48 | #include <Guid/Vlv2Variable.h>\r | |
49 | #include <Protocol/GlobalNvsArea.h>\r | |
50 | #include <Protocol/IgdOpRegion.h>\r | |
51 | #include <Library/PcdLib.h>\r | |
620f2891 TH |
52 | #include <Protocol/VariableLock.h>\r |
53 | \r | |
3cbfba02 DW |
54 | \r |
55 | //\r | |
56 | // VLV2 GPIO GROUP OFFSET\r | |
57 | //\r | |
58 | #define GPIO_SCORE_OFFSET 0x0000\r | |
59 | #define GPIO_NCORE_OFFSET 0x1000\r | |
60 | #define GPIO_SSUS_OFFSET 0x2000\r | |
61 | \r | |
62 | typedef struct {\r | |
63 | UINT32 offset;\r | |
64 | UINT32 val;\r | |
65 | } CFIO_PNP_INIT;\r | |
66 | \r | |
67 | GPIO_CONF_PAD_INIT mTB_BL_GpioInitData_SC_TRI_Exit_boot_Service[] =\r | |
68 | {\r | |
69 | // Pad Name GPIO Number Used As GPO Default Function# INT Capable Interrupt Type PULL H/L MMIO Offset\r | |
70 | GPIO_INIT_ITEM("LPC_CLKOUT0 GPIOC_47 " ,TRISTS ,NA ,F0 , , ,NONE ,0x47),\r | |
71 | GPIO_INIT_ITEM("LPC_CLKOUT1 GPIOC_48 " ,TRISTS ,NA ,F0 , , ,NONE ,0x41),\r | |
72 | };\r | |
73 | \r | |
74 | \r | |
75 | EFI_GUID mSystemHiiExportDatabase = EFI_HII_EXPORT_DATABASE_GUID;\r | |
76 | EFI_GUID mPlatformDriverGuid = EFI_PLATFORM_DRIVER_GUID;\r | |
77 | SYSTEM_CONFIGURATION mSystemConfiguration;\r | |
78 | SYSTEM_PASSWORDS mSystemPassword;\r | |
79 | EFI_HANDLE mImageHandle;\r | |
80 | BOOLEAN mMfgMode = FALSE;\r | |
81 | VOID *mDxePlatformStringPack;\r | |
82 | UINT32 mPlatformBootMode = PLATFORM_NORMAL_MODE;\r | |
83 | extern CHAR16 gItkDataVarName[];\r | |
84 | \r | |
85 | \r | |
86 | EFI_PLATFORM_INFO_HOB mPlatformInfo;\r | |
87 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo;\r | |
88 | EFI_EVENT mReadyToBootEvent;\r | |
89 | \r | |
90 | UINT8 mSmbusRsvdAddresses[] = PLATFORM_SMBUS_RSVD_ADDRESSES;\r | |
91 | UINT8 mNumberSmbusAddress = sizeof( mSmbusRsvdAddresses ) / sizeof( mSmbusRsvdAddresses[0] );\r | |
92 | UINT32 mSubsystemVidDid;\r | |
93 | UINT32 mSubsystemAudioVidDid;\r | |
94 | \r | |
95 | UINTN mPciLanCount = 0;\r | |
96 | VOID *mPciLanInfo = NULL;\r | |
97 | UINTN SpiBase;\r | |
98 | \r | |
99 | static EFI_SPEAKER_IF_PROTOCOL mSpeakerInterface = {\r | |
100 | ProgramToneFrequency,\r | |
101 | GenerateBeepTone\r | |
102 | };\r | |
103 | \r | |
104 | EFI_USB_POLICY_PROTOCOL mUsbPolicyData = {0};\r | |
105 | \r | |
106 | \r | |
107 | CFIO_PNP_INIT mTB_BL_GpioInitData_SC_TRI_S0ix_Exit_boot_Service[] =\r | |
108 | {\r | |
109 | {0x410 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout1_pconf0\r | |
110 | {0x470 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout0_pconf0\r | |
111 | {0x560 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_ilb_serirq_pconf0\r | |
112 | {0x450 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_frameb_pconf0\r | |
113 | {0x480 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkrunb_pconf0\r | |
114 | {0x420 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad3_pconf0\r | |
115 | {0x430 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad2_pconf0\r | |
116 | {0x440 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad1_pconf0\r | |
117 | {0x460 ,0x20038e10}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad0_pconf0\r | |
118 | {0x418 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout1_pad_val\r | |
119 | {0x478 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkout0_pad_val\r | |
120 | {0x568 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_ilb_serirq_pad_val\r | |
121 | {0x458 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_frameb_pad_val\r | |
122 | {0x488 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_clkrunb_pad_val\r | |
123 | {0x428 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad3_pad_val\r | |
124 | {0x438 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad2_pad_val\r | |
125 | {0x448 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad1_pad_val\r | |
126 | {0x468 ,0x00000006}, //vlv.gpio.gpscore.cfio_regs_pad_lpc_ad0_pad_val\r | |
127 | };\r | |
128 | \r | |
129 | VOID\r | |
130 | EfiOrMem (\r | |
131 | IN VOID *Destination,\r | |
132 | IN VOID *Source,\r | |
133 | IN UINTN Length\r | |
134 | );\r | |
135 | \r | |
136 | #if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)\r | |
137 | STATIC\r | |
138 | VOID\r | |
139 | InitFirmwareId();\r | |
140 | #endif\r | |
141 | \r | |
142 | \r | |
143 | VOID\r | |
144 | InitializeClockRouting(\r | |
145 | );\r | |
146 | \r | |
147 | VOID\r | |
148 | InitializeSlotInfo (\r | |
149 | );\r | |
150 | \r | |
151 | #if defined(SENSOR_INFO_VAR_SUPPORT) && SENSOR_INFO_VAR_SUPPORT != 0\r | |
152 | VOID\r | |
153 | InitializeSensorInfoVariable (\r | |
154 | );\r | |
155 | #endif\r | |
156 | \r | |
157 | VOID\r | |
158 | InitTcoReset (\r | |
159 | );\r | |
160 | \r | |
161 | VOID\r | |
162 | InitExI ();\r | |
163 | \r | |
164 | VOID\r | |
165 | InitItk();\r | |
166 | \r | |
167 | VOID\r | |
168 | InitPlatformBootMode();\r | |
169 | \r | |
170 | VOID\r | |
171 | InitMfgAndConfigModeStateVar();\r | |
172 | \r | |
173 | VOID\r | |
174 | InitPchPlatformPolicy (\r | |
175 | IN EFI_PLATFORM_INFO_HOB *PlatformInfo\r | |
176 | );\r | |
177 | \r | |
178 | VOID\r | |
179 | InitVlvPlatformPolicy (\r | |
180 | );\r | |
181 | \r | |
182 | VOID\r | |
183 | InitSioPlatformPolicy(\r | |
184 | );\r | |
185 | \r | |
186 | VOID\r | |
187 | PchInitBeforeBoot(\r | |
188 | );\r | |
189 | \r | |
190 | VOID\r | |
191 | UpdateDVMTSetup(\r | |
192 | );\r | |
193 | \r | |
194 | VOID\r | |
195 | InitPlatformUsbPolicy (\r | |
196 | VOID\r | |
197 | );\r | |
198 | \r | |
199 | VOID\r | |
200 | InitRC6Policy(\r | |
201 | VOID\r | |
202 | );\r | |
203 | \r | |
204 | \r | |
620f2891 TH |
205 | EFI_STATUS\r |
206 | EFIAPI\r | |
207 | SaveSetupRecoveryVar(\r | |
208 | VOID\r | |
209 | )\r | |
210 | {\r | |
211 | EFI_STATUS Status = EFI_SUCCESS;\r | |
212 | UINTN SizeOfNvStore = 0;\r | |
213 | UINTN SizeOfSetupVar = 0;\r | |
214 | SYSTEM_CONFIGURATION *SetupData = NULL;\r | |
215 | SYSTEM_CONFIGURATION *RecoveryNvData = NULL;\r | |
216 | EDKII_VARIABLE_LOCK_PROTOCOL *VariableLock = NULL;\r | |
217 | \r | |
218 | \r | |
219 | DEBUG ((EFI_D_INFO, "SaveSetupRecoveryVar() Entry \n"));\r | |
220 | SizeOfNvStore = sizeof(SYSTEM_CONFIGURATION);\r | |
221 | RecoveryNvData = AllocateZeroPool (sizeof(SYSTEM_CONFIGURATION));\r | |
222 | if (NULL == RecoveryNvData) {\r | |
223 | Status = EFI_OUT_OF_RESOURCES;\r | |
224 | goto Exit; \r | |
225 | }\r | |
226 | \r | |
227 | Status = gRT->GetVariable(\r | |
228 | L"SetupRecovery",\r | |
229 | &gEfiNormalSetupGuid,\r | |
230 | NULL,\r | |
231 | &SizeOfNvStore,\r | |
232 | RecoveryNvData\r | |
233 | );\r | |
234 | \r | |
235 | if (EFI_ERROR (Status)) {\r | |
236 | // Don't find the "SetupRecovery" variable.\r | |
237 | // have to copy "Setup" variable to "SetupRecovery" variable.\r | |
238 | SetupData = AllocateZeroPool (sizeof(SYSTEM_CONFIGURATION));\r | |
239 | if (NULL == SetupData) {\r | |
240 | Status = EFI_OUT_OF_RESOURCES;\r | |
241 | goto Exit; \r | |
242 | }\r | |
243 | SizeOfSetupVar = sizeof(SYSTEM_CONFIGURATION);\r | |
244 | Status = gRT->GetVariable(\r | |
245 | NORMAL_SETUP_NAME,\r | |
246 | &gEfiNormalSetupGuid,\r | |
247 | NULL,\r | |
248 | &SizeOfSetupVar,\r | |
249 | SetupData\r | |
250 | );\r | |
251 | ASSERT_EFI_ERROR (Status);\r | |
252 | \r | |
253 | Status = gRT->SetVariable (\r | |
254 | L"SetupRecovery",\r | |
255 | &gEfiNormalSetupGuid,\r | |
256 | EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,\r | |
257 | sizeof(SYSTEM_CONFIGURATION),\r | |
258 | SetupData\r | |
259 | );\r | |
260 | ASSERT_EFI_ERROR (Status);\r | |
261 | \r | |
262 | Status = gBS->LocateProtocol (&gEdkiiVariableLockProtocolGuid, NULL, (VOID **) &VariableLock);\r | |
263 | if (!EFI_ERROR (Status)) {\r | |
264 | Status = VariableLock->RequestToLock (VariableLock, L"SetupRecovery", &gEfiNormalSetupGuid);\r | |
265 | ASSERT_EFI_ERROR (Status);\r | |
266 | }\r | |
267 | \r | |
268 | }\r | |
269 | \r | |
270 | Exit:\r | |
271 | if (RecoveryNvData)\r | |
272 | FreePool (RecoveryNvData);\r | |
273 | if (SetupData)\r | |
274 | FreePool (SetupData);\r | |
275 | \r | |
276 | return Status;\r | |
277 | \r | |
278 | }\r | |
279 | \r | |
280 | \r | |
3cbfba02 DW |
281 | VOID\r |
282 | TristateLpcGpioConfig (\r | |
283 | IN UINT32 Gpio_Mmio_Offset,\r | |
284 | IN UINT32 Gpio_Pin_Num,\r | |
285 | GPIO_CONF_PAD_INIT* Gpio_Conf_Data\r | |
286 | )\r | |
287 | \r | |
288 | {\r | |
289 | UINT32 index;\r | |
290 | UINT32 mmio_conf0;\r | |
291 | UINT32 mmio_padval;\r | |
292 | PAD_CONF0 conf0_val;\r | |
293 | PAD_VAL pad_val;\r | |
294 | \r | |
295 | //\r | |
296 | // GPIO WELL -- Memory base registers\r | |
297 | //\r | |
298 | \r | |
299 | //\r | |
300 | // A0 BIOS Spec doesn't mention it although X0 does. comment out now.\r | |
301 | // GPIO write 0x01001002 to IOBASE + Gpio_Mmio_Offset + 0x0900\r | |
302 | //\r | |
303 | \r | |
304 | for(index=0; index < Gpio_Pin_Num; index++)\r | |
305 | {\r | |
306 | //\r | |
307 | // Calculate the MMIO Address for specific GPIO pin CONF0 register pointed by index.\r | |
308 | //\r | |
309 | mmio_conf0 = IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_CONF0 + Gpio_Conf_Data[index].offset * 16;\r | |
310 | mmio_padval= IO_BASE_ADDRESS + Gpio_Mmio_Offset + R_PCH_CFIO_PAD_VAL + Gpio_Conf_Data[index].offset * 16;\r | |
311 | \r | |
312 | #ifdef EFI_DEBUG\r | |
313 | DEBUG ((EFI_D_INFO, "%s, ", Gpio_Conf_Data[index].pad_name));\r | |
314 | \r | |
315 | #endif\r | |
316 | DEBUG ((EFI_D_INFO, "Usage = %d, Func# = %d, IntType = %d, Pull Up/Down = %d, MMIO Base = 0x%08x, ",\r | |
317 | Gpio_Conf_Data[index].usage,\r | |
318 | Gpio_Conf_Data[index].func,\r | |
319 | Gpio_Conf_Data[index].int_type,\r | |
320 | Gpio_Conf_Data[index].pull,\r | |
321 | mmio_conf0));\r | |
322 | \r | |
323 | //\r | |
324 | // Step 1: PadVal Programming\r | |
325 | //\r | |
326 | pad_val.dw = MmioRead32(mmio_padval);\r | |
327 | \r | |
328 | //\r | |
329 | // Config PAD_VAL only for GPIO (Non-Native) Pin\r | |
330 | //\r | |
331 | if(Native != Gpio_Conf_Data[index].usage)\r | |
332 | {\r | |
333 | pad_val.dw &= ~0x6; // Clear bits 1:2\r | |
334 | pad_val.dw |= (Gpio_Conf_Data[index].usage & 0x6); // Set bits 1:2 according to PadVal\r | |
335 | \r | |
336 | //\r | |
337 | // set GPO default value\r | |
338 | //\r | |
339 | if(Gpio_Conf_Data[index].usage == GPO && Gpio_Conf_Data[index].gpod4 != NA)\r | |
340 | {\r | |
341 | pad_val.r.pad_val = Gpio_Conf_Data[index].gpod4;\r | |
342 | }\r | |
343 | }\r | |
344 | \r | |
345 | \r | |
346 | DEBUG ((EFI_D_INFO, "Set PAD_VAL = 0x%08x, ", pad_val.dw));\r | |
347 | \r | |
348 | MmioWrite32(mmio_padval, pad_val.dw);\r | |
349 | \r | |
350 | //\r | |
351 | // Step 2: CONF0 Programming\r | |
352 | // Read GPIO default CONF0 value, which is assumed to be default value after reset.\r | |
353 | //\r | |
354 | conf0_val.dw = MmioRead32(mmio_conf0);\r | |
355 | \r | |
356 | //\r | |
357 | // Set Function #\r | |
358 | //\r | |
359 | conf0_val.r.Func_Pin_Mux = Gpio_Conf_Data[index].func;\r | |
360 | \r | |
361 | if(GPO == Gpio_Conf_Data[index].usage)\r | |
362 | {\r | |
363 | //\r | |
364 | // If used as GPO, then internal pull need to be disabled\r | |
365 | //\r | |
366 | conf0_val.r.Pull_assign = 0; // Non-pull\r | |
367 | }\r | |
368 | else\r | |
369 | {\r | |
370 | //\r | |
371 | // Set PullUp / PullDown\r | |
372 | //\r | |
373 | if(P_20K_H == Gpio_Conf_Data[index].pull)\r | |
374 | {\r | |
375 | conf0_val.r.Pull_assign = 0x1; // PullUp\r | |
376 | conf0_val.r.Pull_strength = 0x2;// 20K\r | |
377 | }\r | |
378 | else if(P_20K_L == Gpio_Conf_Data[index].pull)\r | |
379 | {\r | |
380 | conf0_val.r.Pull_assign = 0x2; // PullDown\r | |
381 | conf0_val.r.Pull_strength = 0x2;// 20K\r | |
382 | }\r | |
383 | else if(P_NONE == Gpio_Conf_Data[index].pull)\r | |
384 | {\r | |
385 | conf0_val.r.Pull_assign = 0; // Non-pull\r | |
386 | }\r | |
387 | else\r | |
388 | {\r | |
389 | ASSERT(FALSE); // Invalid value\r | |
390 | }\r | |
391 | }\r | |
392 | \r | |
393 | //\r | |
394 | // Set INT Trigger Type\r | |
395 | //\r | |
396 | conf0_val.dw &= ~0x0f000000; // Clear bits 27:24\r | |
397 | \r | |
398 | //\r | |
399 | // Set INT Trigger Type\r | |
400 | //\r | |
401 | if(TRIG_ == Gpio_Conf_Data[index].int_type)\r | |
402 | {\r | |
403 | //\r | |
404 | // Interrupt not capable, clear bits 27:24\r | |
405 | //\r | |
406 | }\r | |
407 | else\r | |
408 | {\r | |
409 | conf0_val.dw |= (Gpio_Conf_Data[index].int_type & 0x0f)<<24;\r | |
410 | }\r | |
411 | \r | |
412 | DEBUG ((EFI_D_INFO, "Set CONF0 = 0x%08x\n", conf0_val.dw));\r | |
413 | \r | |
414 | //\r | |
415 | // Write back the targeted GPIO config value according to platform (board) GPIO setting\r | |
416 | //\r | |
417 | MmioWrite32 (mmio_conf0, conf0_val.dw);\r | |
418 | }\r | |
419 | \r | |
420 | // A0 BIOS Spec doesn't mention it although X0 does. comment out now.\r | |
421 | // GPIO SCORE write 0x01001002 to IOBASE + 0x0900\r | |
422 | //\r | |
423 | }\r | |
424 | \r | |
425 | VOID\r | |
426 | EFIAPI\r | |
427 | SpiBiosProtectionFunction(\r | |
428 | EFI_EVENT Event,\r | |
429 | VOID *Context\r | |
430 | )\r | |
431 | {\r | |
432 | \r | |
433 | UINTN mPciD31F0RegBase;\r | |
fb1a4e36 SL |
434 | UINTN BiosFlaLower0;\r |
435 | UINTN BiosFlaLimit0;\r | |
436 | UINTN BiosFlaLower1;\r | |
437 | UINTN BiosFlaLimit1; \r | |
438 | \r | |
3cbfba02 | 439 | \r |
fb1a4e36 SL |
440 | BiosFlaLower0 = PcdGet32(PcdFlashMicroCodeAddress)-PcdGet32(PcdFlashAreaBaseAddress);\r |
441 | BiosFlaLimit0 = PcdGet32(PcdFlashMicroCodeSize)-1; \r | |
442 | #ifdef MINNOW2_FSP_BUILD\r | |
443 | BiosFlaLower1 = PcdGet32(PcdFlashFvFspBase)-PcdGet32(PcdFlashAreaBaseAddress);\r | |
444 | BiosFlaLimit1 = (PcdGet32(PcdFlashFvRecoveryBase)-PcdGet32(PcdFlashFvFspBase)+PcdGet32(PcdFlashFvRecoverySize))-1;\r | |
445 | #else\r | |
446 | BiosFlaLower1 = PcdGet32(PcdFlashFvMainBase)-PcdGet32(PcdFlashAreaBaseAddress);\r | |
447 | BiosFlaLimit1 = (PcdGet32(PcdFlashFvRecoveryBase)-PcdGet32(PcdFlashFvMainBase)+PcdGet32(PcdFlashFvRecoverySize))-1;\r | |
448 | #endif\r | |
3cbfba02 | 449 | \r |
fb1a4e36 | 450 | \r |
3cbfba02 DW |
451 | mPciD31F0RegBase = MmPciAddress (0,\r |
452 | DEFAULT_PCI_BUS_NUMBER_PCH,\r | |
453 | PCI_DEVICE_NUMBER_PCH_LPC,\r | |
454 | PCI_FUNCTION_NUMBER_PCH_LPC,\r | |
455 | 0\r | |
456 | );\r | |
457 | SpiBase = MmioRead32(mPciD31F0RegBase + R_PCH_LPC_SPI_BASE) & B_PCH_LPC_SPI_BASE_BAR;\r | |
458 | \r | |
459 | //\r | |
460 | //Set SMM_BWP, WPD and LE bit\r | |
461 | //\r | |
462 | MmioOr32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8) B_PCH_SPI_BCR_SMM_BWP);\r | |
463 | MmioAnd32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8)(~B_PCH_SPI_BCR_BIOSWE));\r | |
464 | MmioOr32 ((UINTN) (SpiBase + R_PCH_SPI_BCR), (UINT8) B_PCH_SPI_BCR_BLE);\r | |
465 | \r | |
466 | //\r | |
467 | //First check if FLOCKDN or PR0FLOCKDN is set. No action if either of them set already.\r | |
468 | //\r | |
469 | if( (MmioRead16(SpiBase + R_PCH_SPI_HSFS) & B_PCH_SPI_HSFS_FLOCKDN) != 0 ||\r | |
470 | (MmioRead32(SpiBase + R_PCH_SPI_IND_LOCK)& B_PCH_SPI_IND_LOCK_PR0) != 0) {\r | |
471 | //\r | |
472 | //Already locked. we could take no action here\r | |
473 | //\r | |
474 | DEBUG((EFI_D_INFO, "PR0 already locked down. Stop configuring PR0.\n"));\r | |
475 | return;\r | |
476 | }\r | |
477 | \r | |
478 | //\r | |
479 | //Set PR0\r | |
480 | //\r | |
481 | MmioOr32((UINTN)(SpiBase + R_PCH_SPI_PR0),\r | |
482 | B_PCH_SPI_PR0_RPE|B_PCH_SPI_PR0_WPE|\\r | |
fb1a4e36 | 483 | (B_PCH_SPI_PR0_PRB_MASK&(BiosFlaLower0>>12))|(B_PCH_SPI_PR0_PRL_MASK&(BiosFlaLimit0>>12)<<16));\r |
3cbfba02 | 484 | \r |
fb1a4e36 SL |
485 | //\r |
486 | //Set PR1\r | |
487 | //\r | |
488 | \r | |
489 | MmioOr32((UINTN)(SpiBase + R_PCH_SPI_PR1),\r | |
490 | B_PCH_SPI_PR1_RPE|B_PCH_SPI_PR1_WPE|\\r | |
491 | (B_PCH_SPI_PR1_PRB_MASK&(BiosFlaLower1>>12))|(B_PCH_SPI_PR1_PRL_MASK&(BiosFlaLimit1>>12)<<16));\r | |
492 | \r | |
493 | //\r | |
6f2ef18e | 494 | //Lock down PRx\r |
fb1a4e36 SL |
495 | //\r |
496 | MmioOr16 ((UINTN) (SpiBase + R_PCH_SPI_HSFS), (UINT16) (B_PCH_SPI_HSFS_FLOCKDN));\r | |
497 | \r | |
498 | //\r | |
499 | // Verify if it's really locked.\r | |
500 | //\r | |
501 | if ((MmioRead16 (SpiBase + R_PCH_SPI_HSFS) & B_PCH_SPI_HSFS_FLOCKDN) == 0) {\r | |
6f2ef18e | 502 | DEBUG((EFI_D_ERROR, "Failed to lock down PRx.\n"));\r |
fb1a4e36 | 503 | }\r |
3cbfba02 DW |
504 | return;\r |
505 | \r | |
506 | }\r | |
507 | \r | |
508 | VOID\r | |
509 | EFIAPI\r | |
510 | InitPciDevPME (\r | |
511 | EFI_EVENT Event,\r | |
512 | VOID *Context\r | |
513 | )\r | |
514 | {\r | |
515 | UINTN VarSize;\r | |
516 | EFI_STATUS Status;\r | |
517 | \r | |
518 | VarSize = sizeof(SYSTEM_CONFIGURATION);\r | |
519 | Status = gRT->GetVariable(\r | |
520 | NORMAL_SETUP_NAME,\r | |
521 | &gEfiNormalSetupGuid,\r | |
522 | NULL,\r | |
523 | &VarSize,\r | |
524 | &mSystemConfiguration\r | |
525 | );\r | |
526 | \r | |
527 | //\r | |
528 | //Program HDA PME_EN\r | |
529 | //\r | |
530 | PchAzaliaPciCfg32Or (R_PCH_HDA_PCS, B_PCH_HDA_PCS_PMEE);\r | |
531 | \r | |
532 | //\r | |
533 | //Program SATA PME_EN\r | |
534 | //\r | |
535 | PchSataPciCfg32Or (R_PCH_SATA_PMCS, B_PCH_SATA_PMCS_PMEE);\r | |
536 | \r | |
537 | DEBUG ((EFI_D_INFO, "InitPciDevPME mSystemConfiguration.EhciPllCfgEnable = 0x%x \n",mSystemConfiguration.EhciPllCfgEnable));\r | |
538 | if (mSystemConfiguration.EhciPllCfgEnable != 1) {\r | |
539 | //\r | |
540 | //Program EHCI PME_EN\r | |
541 | //\r | |
542 | PchMmPci32Or (\r | |
543 | 0,\r | |
544 | 0,\r | |
545 | PCI_DEVICE_NUMBER_PCH_USB,\r | |
546 | PCI_FUNCTION_NUMBER_PCH_EHCI,\r | |
547 | R_PCH_EHCI_PWR_CNTL_STS,\r | |
548 | B_PCH_EHCI_PWR_CNTL_STS_PME_EN\r | |
549 | );\r | |
550 | }\r | |
551 | {\r | |
552 | UINTN EhciPciMmBase;\r | |
553 | UINT32 Buffer32 = 0;\r | |
554 | \r | |
555 | EhciPciMmBase = MmPciAddress (0,\r | |
556 | 0,\r | |
557 | PCI_DEVICE_NUMBER_PCH_USB,\r | |
558 | PCI_FUNCTION_NUMBER_PCH_EHCI,\r | |
559 | 0\r | |
560 | );\r | |
561 | DEBUG ((EFI_D_INFO, "ConfigureAdditionalPm() EhciPciMmBase = 0x%x \n",EhciPciMmBase));\r | |
562 | Buffer32 = MmioRead32(EhciPciMmBase + R_PCH_EHCI_PWR_CNTL_STS);\r | |
563 | DEBUG ((EFI_D_INFO, "ConfigureAdditionalPm() R_PCH_EHCI_PWR_CNTL_STS = 0x%x \n",Buffer32));\r | |
564 | }\r | |
565 | }\r | |
566 | \r | |
6f2ef18e TH |
567 | VOID\r |
568 | EFIAPI\r | |
569 | InitThermalZone (\r | |
570 | EFI_EVENT Event,\r | |
571 | VOID *Context\r | |
572 | )\r | |
573 | {\r | |
574 | UINTN VarSize;\r | |
575 | EFI_STATUS Status;\r | |
576 | EFI_GLOBAL_NVS_AREA_PROTOCOL *GlobalNvsArea;\r | |
577 | VarSize = sizeof(SYSTEM_CONFIGURATION);\r | |
578 | Status = gRT->GetVariable(\r | |
579 | NORMAL_SETUP_NAME,\r | |
580 | &gEfiNormalSetupGuid,\r | |
581 | NULL,\r | |
582 | &VarSize,\r | |
583 | &mSystemConfiguration\r | |
584 | );\r | |
585 | Status = gBS->LocateProtocol (\r | |
586 | &gEfiGlobalNvsAreaProtocolGuid,\r | |
587 | NULL,\r | |
588 | (void **)&GlobalNvsArea\r | |
589 | );\r | |
590 | GlobalNvsArea->Area->CriticalThermalTripPoint = mSystemConfiguration.CriticalThermalTripPoint;\r | |
591 | GlobalNvsArea->Area->PassiveThermalTripPoint = mSystemConfiguration.PassiveThermalTripPoint;\r | |
592 | }\r | |
3cbfba02 DW |
593 | #if defined SUPPORT_LVDS_DISPLAY && SUPPORT_LVDS_DISPLAY\r |
594 | \r | |
595 | #endif\r | |
596 | \r | |
597 | \r | |
598 | EFI_STATUS\r | |
599 | EFIAPI\r | |
600 | TristateLpcGpioS0i3Config (\r | |
601 | UINT32 Gpio_Mmio_Offset,\r | |
602 | UINT32 Gpio_Pin_Num,\r | |
603 | CFIO_PNP_INIT* Gpio_Conf_Data\r | |
604 | )\r | |
605 | {\r | |
606 | \r | |
607 | UINT32 index;\r | |
608 | UINT32 mmio_reg;\r | |
609 | UINT32 mmio_val;\r | |
610 | \r | |
611 | DEBUG ((DEBUG_INFO, "TristateLpcGpioS0i3Config\n"));\r | |
612 | \r | |
613 | for(index=0; index < Gpio_Pin_Num; index++)\r | |
614 | {\r | |
615 | mmio_reg = IO_BASE_ADDRESS + Gpio_Mmio_Offset + Gpio_Conf_Data[index].offset;\r | |
616 | \r | |
617 | MmioWrite32(mmio_reg, Gpio_Conf_Data[index].val);\r | |
618 | mmio_val = 0;\r | |
619 | mmio_val = MmioRead32(mmio_reg);\r | |
620 | \r | |
621 | DEBUG ((EFI_D_INFO, "Set MMIO=0x%08x PAD_VAL = 0x%08x,\n", mmio_reg, mmio_val));\r | |
622 | }\r | |
623 | \r | |
624 | return EFI_SUCCESS;\r | |
625 | }\r | |
626 | \r | |
627 | \r | |
628 | EFI_BOOT_SCRIPT_SAVE_PROTOCOL *mBootScriptSave;\r | |
629 | \r | |
630 | /**\r | |
631 | Event Notification during exit boot service to enabel ACPI mode\r | |
632 | \r | |
633 | Disable SW SMI Timer, SMI from USB & Intel Specific USB 2\r | |
634 | \r | |
635 | Clear all ACPI event status and disable all ACPI events\r | |
636 | Disable PM sources except power button\r | |
637 | Clear status bits\r | |
638 | \r | |
639 | Guarantee day-of-month alarm is invalid (ACPI 5.0 Section 4.8.2.4 "Real Time Clock Alarm")\r | |
640 | \r | |
641 | Update EC to disable SMI and enable SCI\r | |
642 | \r | |
643 | Enable SCI\r | |
644 | \r | |
645 | Enable PME_B0_EN in GPE0a_EN\r | |
646 | \r | |
647 | @param Event - EFI Event Handle\r | |
648 | @param Context - Pointer to Notify Context\r | |
649 | \r | |
650 | @retval Nothing\r | |
651 | \r | |
652 | **/\r | |
653 | VOID\r | |
654 | EFIAPI\r | |
655 | EnableAcpiCallback (\r | |
656 | IN EFI_EVENT Event,\r | |
657 | IN VOID *Context\r | |
658 | )\r | |
659 | {\r | |
660 | UINT32 RegData32;\r | |
661 | UINT16 Pm1Cnt;\r | |
662 | UINT16 AcpiBase;\r | |
663 | UINT32 Gpe0aEn;\r | |
664 | \r | |
665 | AcpiBase = MmioRead16 (\r | |
666 | PchPciDeviceMmBase (DEFAULT_PCI_BUS_NUMBER_PCH,\r | |
667 | PCI_DEVICE_NUMBER_PCH_LPC,\r | |
668 | PCI_FUNCTION_NUMBER_PCH_LPC) + R_PCH_LPC_ACPI_BASE\r | |
669 | ) & B_PCH_LPC_ACPI_BASE_BAR;\r | |
670 | \r | |
671 | DEBUG ((EFI_D_INFO, "EnableAcpiCallback: AcpiBase = %x\n", AcpiBase));\r | |
672 | \r | |
673 | //\r | |
674 | // Disable SW SMI Timer, SMI from USB & Intel Specific USB 2\r | |
675 | //\r | |
676 | RegData32 = IoRead32(AcpiBase + R_PCH_SMI_EN);\r | |
677 | RegData32 &= ~(B_PCH_SMI_EN_SWSMI_TMR | B_PCH_SMI_EN_LEGACY_USB2 | B_PCH_SMI_EN_INTEL_USB2);\r | |
678 | IoWrite32(AcpiBase + R_PCH_SMI_EN, RegData32);\r | |
679 | \r | |
680 | RegData32 = IoRead32(AcpiBase + R_PCH_SMI_STS);\r | |
681 | RegData32 |= B_PCH_SMI_STS_SWSMI_TMR;\r | |
682 | IoWrite32(AcpiBase + R_PCH_SMI_STS, RegData32);\r | |
683 | \r | |
684 | //\r | |
685 | // Disable PM sources except power button\r | |
686 | // power button is enabled only for PCAT. Disabled it on Tablet platform\r | |
687 | //\r | |
688 | \r | |
689 | IoWrite16(AcpiBase + R_PCH_ACPI_PM1_EN, B_PCH_ACPI_PM1_EN_PWRBTN);\r | |
690 | IoWrite16(AcpiBase + R_PCH_ACPI_PM1_STS, 0xffff);\r | |
691 | \r | |
692 | //\r | |
693 | // Guarantee day-of-month alarm is invalid (ACPI 5.0 Section 4.8.2.4 "Real Time Clock Alarm")\r | |
694 | // Clear Status D reg VM bit, Date of month Alarm to make Data in CMOS RAM is no longer Valid\r | |
695 | //\r | |
696 | IoWrite8 (PCAT_RTC_ADDRESS_REGISTER, RTC_ADDRESS_REGISTER_D);\r | |
697 | IoWrite8 (PCAT_RTC_DATA_REGISTER, 0x0);\r | |
698 | \r | |
699 | RegData32 = IoRead32(AcpiBase + R_PCH_ALT_GP_SMI_EN);\r | |
700 | RegData32 &= ~(BIT7);\r | |
701 | IoWrite32((AcpiBase + R_PCH_ALT_GP_SMI_EN), RegData32);\r | |
702 | \r | |
703 | //\r | |
704 | // Enable SCI\r | |
705 | //\r | |
706 | Pm1Cnt = IoRead16(AcpiBase + R_PCH_ACPI_PM1_CNT);\r | |
707 | Pm1Cnt |= B_PCH_ACPI_PM1_CNT_SCI_EN;\r | |
708 | IoWrite16(AcpiBase + R_PCH_ACPI_PM1_CNT, Pm1Cnt);\r | |
709 | \r | |
710 | IoWrite8(0x80, 0xA0); //SW_SMI_ACPI_ENABLE\r | |
711 | \r | |
712 | //\r | |
713 | // Enable PME_B0_EN in GPE0a_EN\r | |
714 | // Caution: Enable PME_B0_EN must be placed after enabling SCI.\r | |
715 | // Otherwise, USB PME could not be handled as SMI event since no handler is there.\r | |
716 | //\r | |
717 | Gpe0aEn = IoRead32 (AcpiBase + R_PCH_ACPI_GPE0a_EN);\r | |
718 | Gpe0aEn |= B_PCH_ACPI_GPE0a_EN_PME_B0;\r | |
719 | IoWrite32(AcpiBase + R_PCH_ACPI_GPE0a_EN, Gpe0aEn);\r | |
720 | \r | |
721 | }\r | |
722 | \r | |
723 | /**\r | |
724 | \r | |
725 | Routine Description:\r | |
726 | \r | |
727 | This is the standard EFI driver point for the Driver. This\r | |
728 | driver is responsible for setting up any platform specific policy or\r | |
729 | initialization information.\r | |
730 | \r | |
731 | @param ImageHandle Handle for the image of this driver.\r | |
732 | @param SystemTable Pointer to the EFI System Table.\r | |
733 | \r | |
734 | @retval EFI_SUCCESS Policy decisions set.\r | |
735 | \r | |
736 | **/\r | |
737 | EFI_STATUS\r | |
738 | EFIAPI\r | |
739 | InitializePlatform (\r | |
740 | IN EFI_HANDLE ImageHandle,\r | |
741 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
742 | )\r | |
743 | {\r | |
744 | EFI_STATUS Status;\r | |
745 | UINTN VarSize;\r | |
746 | EFI_HANDLE Handle = NULL;\r | |
3cbfba02 | 747 | EFI_EVENT mEfiExitBootServicesEvent;\r |
d71c25cf DW |
748 | EFI_EVENT RtcEvent;\r |
749 | VOID *RtcCallbackReg = NULL;\r | |
750 | \r | |
751 | mImageHandle = ImageHandle;\r | |
3cbfba02 DW |
752 | \r |
753 | Status = gBS->InstallProtocolInterface (\r | |
754 | &Handle,\r | |
755 | &gEfiSpeakerInterfaceProtocolGuid,\r | |
756 | EFI_NATIVE_INTERFACE,\r | |
757 | &mSpeakerInterface\r | |
758 | );\r | |
759 | \r | |
760 | Status = gBS->LocateProtocol (\r | |
761 | &gEfiPciRootBridgeIoProtocolGuid,\r | |
762 | NULL,\r | |
763 | (VOID **) &mPciRootBridgeIo\r | |
764 | );\r | |
765 | ASSERT_EFI_ERROR (Status);\r | |
766 | \r | |
767 | VarSize = sizeof(EFI_PLATFORM_INFO_HOB);\r | |
768 | Status = gRT->GetVariable(\r | |
769 | L"PlatformInfo",\r | |
770 | &gEfiVlv2VariableGuid,\r | |
771 | NULL,\r | |
772 | &VarSize,\r | |
773 | &mPlatformInfo\r | |
774 | );\r | |
775 | \r | |
776 | //\r | |
777 | // Initialize Product Board ID variable\r | |
778 | //\r | |
779 | InitMfgAndConfigModeStateVar();\r | |
780 | InitPlatformBootMode();\r | |
781 | \r | |
782 | //\r | |
783 | // Install Observable protocol\r | |
784 | //\r | |
785 | InitializeObservableProtocol();\r | |
786 | \r | |
620f2891 TH |
787 | Status = SaveSetupRecoveryVar();\r |
788 | if (EFI_ERROR (Status)) {\r | |
789 | DEBUG ((EFI_D_ERROR, "InitializePlatform() Save SetupRecovery variable failed \n"));\r | |
790 | }\r | |
3cbfba02 DW |
791 | \r |
792 | VarSize = sizeof(SYSTEM_CONFIGURATION);\r | |
793 | Status = gRT->GetVariable(\r | |
794 | NORMAL_SETUP_NAME,\r | |
795 | &gEfiNormalSetupGuid,\r | |
796 | NULL,\r | |
797 | &VarSize,\r | |
798 | &mSystemConfiguration\r | |
799 | );\r | |
620f2891 TH |
800 | if (EFI_ERROR (Status) || VarSize != sizeof(SYSTEM_CONFIGURATION)) {\r |
801 | //The setup variable is corrupted\r | |
802 | VarSize = sizeof(SYSTEM_CONFIGURATION);\r | |
803 | Status = gRT->GetVariable(\r | |
804 | L"SetupRecovery",\r | |
805 | &gEfiNormalSetupGuid,\r | |
806 | NULL,\r | |
807 | &VarSize,\r | |
808 | &mSystemConfiguration\r | |
809 | );\r | |
810 | ASSERT_EFI_ERROR (Status);\r | |
811 | Status = gRT->SetVariable (\r | |
812 | NORMAL_SETUP_NAME,\r | |
813 | &gEfiNormalSetupGuid,\r | |
814 | EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,\r | |
815 | sizeof(SYSTEM_CONFIGURATION),\r | |
816 | &mSystemConfiguration\r | |
817 | ); \r | |
818 | }\r | |
819 | \r | |
3cbfba02 DW |
820 | Status = EfiCreateEventReadyToBootEx (\r |
821 | TPL_CALLBACK,\r | |
822 | ReadyToBootFunction,\r | |
823 | NULL,\r | |
824 | &mReadyToBootEvent\r | |
825 | );\r | |
826 | \r | |
827 | //\r | |
828 | // Create a ReadyToBoot Event to run the PME init process\r | |
829 | //\r | |
830 | Status = EfiCreateEventReadyToBootEx (\r | |
831 | TPL_CALLBACK,\r | |
832 | InitPciDevPME,\r | |
833 | NULL,\r | |
834 | &mReadyToBootEvent\r | |
835 | );\r | |
836 | //\r | |
fb1a4e36 | 837 | // Create a ReadyToBoot Event to run enable PR0/PR1 and lock down,unlock variable region\r |
3cbfba02 DW |
838 | //\r |
839 | if(mSystemConfiguration.SpiRwProtect==1) {\r | |
840 | Status = EfiCreateEventReadyToBootEx (\r | |
841 | TPL_CALLBACK,\r | |
842 | SpiBiosProtectionFunction,\r | |
843 | NULL,\r | |
844 | &mReadyToBootEvent\r | |
845 | );\r | |
846 | }\r | |
6f2ef18e TH |
847 | //\r |
848 | // Create a ReadyToBoot Event to run the thermalzone init process\r | |
849 | //\r | |
850 | Status = EfiCreateEventReadyToBootEx (\r | |
851 | TPL_CALLBACK,\r | |
852 | InitThermalZone,\r | |
853 | NULL,\r | |
854 | &mReadyToBootEvent\r | |
855 | ); \r | |
856 | \r | |
3cbfba02 DW |
857 | ReportStatusCodeEx (\r |
858 | EFI_PROGRESS_CODE,\r | |
859 | EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP1,\r | |
860 | 0,\r | |
861 | &gEfiCallerIdGuid,\r | |
862 | NULL,\r | |
863 | NULL,\r | |
864 | 0\r | |
865 | );\r | |
866 | \r | |
867 | #if defined(SENSOR_INFO_VAR_SUPPORT) && SENSOR_INFO_VAR_SUPPORT != 0\r | |
868 | //\r | |
869 | // Initialize Sensor Info variable\r | |
870 | //\r | |
871 | InitializeSensorInfoVariable();\r | |
872 | #endif\r | |
873 | InitPchPlatformPolicy(&mPlatformInfo);\r | |
874 | InitVlvPlatformPolicy();\r | |
875 | \r | |
876 | //\r | |
877 | // Add usb policy\r | |
878 | //\r | |
879 | InitPlatformUsbPolicy();\r | |
880 | InitSioPlatformPolicy();\r | |
881 | InitializeClockRouting();\r | |
882 | InitializeSlotInfo();\r | |
883 | InitTcoReset();\r | |
884 | \r | |
885 | //\r | |
886 | //Init ExI\r | |
887 | //\r | |
888 | InitExI();\r | |
889 | \r | |
890 | ReportStatusCodeEx (\r | |
891 | EFI_PROGRESS_CODE,\r | |
892 | EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP2,\r | |
893 | 0,\r | |
894 | &gEfiCallerIdGuid,\r | |
895 | NULL,\r | |
896 | NULL,\r | |
897 | 0\r | |
898 | );\r | |
899 | \r | |
900 | //\r | |
901 | // Install PCI Bus Driver Hook\r | |
902 | //\r | |
903 | PciBusDriverHook();\r | |
904 | \r | |
905 | InitItk();\r | |
906 | \r | |
907 | ReportStatusCodeEx (\r | |
908 | EFI_PROGRESS_CODE,\r | |
909 | EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP3,\r | |
910 | 0,\r | |
911 | &gEfiCallerIdGuid,\r | |
912 | NULL,\r | |
913 | NULL,\r | |
914 | 0\r | |
915 | );\r | |
916 | \r | |
917 | \r | |
918 | //\r | |
919 | // Initialize Password States and Callbacks\r | |
920 | //\r | |
921 | PchInitBeforeBoot();\r | |
922 | \r | |
923 | #if defined SUPPORT_LVDS_DISPLAY && SUPPORT_LVDS_DISPLAY\r | |
924 | \r | |
925 | #endif\r | |
926 | \r | |
927 | #if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)\r | |
928 | //\r | |
929 | // Re-write Firmware ID if it is changed\r | |
930 | //\r | |
931 | InitFirmwareId();\r | |
932 | #endif\r | |
933 | \r | |
934 | ReportStatusCodeEx (\r | |
935 | EFI_PROGRESS_CODE,\r | |
936 | EFI_COMPUTING_UNIT_CHIPSET | EFI_CU_PLATFORM_DXE_STEP4,\r | |
937 | 0,\r | |
938 | &gEfiCallerIdGuid,\r | |
939 | NULL,\r | |
940 | NULL,\r | |
941 | 0\r | |
942 | );\r | |
943 | \r | |
944 | \r | |
945 | Status = gBS->CreateEventEx (\r | |
946 | EVT_NOTIFY_SIGNAL,\r | |
947 | TPL_NOTIFY,\r | |
948 | EnableAcpiCallback,\r | |
949 | NULL,\r | |
950 | &gEfiEventExitBootServicesGuid,\r | |
951 | &mEfiExitBootServicesEvent\r | |
952 | );\r | |
953 | \r | |
d71c25cf DW |
954 | //\r |
955 | // Adjust RTC deafult time to be BIOS-built time.\r | |
956 | //\r | |
957 | Status = gBS->CreateEvent (\r | |
958 | EVT_NOTIFY_SIGNAL,\r | |
959 | TPL_CALLBACK,\r | |
960 | AdjustDefaultRtcTimeCallback,\r | |
961 | NULL,\r | |
962 | &RtcEvent\r | |
963 | );\r | |
964 | if (!EFI_ERROR (Status)) {\r | |
965 | Status = gBS->RegisterProtocolNotify (\r | |
966 | &gExitPmAuthProtocolGuid,\r | |
967 | RtcEvent,\r | |
968 | &RtcCallbackReg\r | |
969 | );\r | |
3cbfba02 | 970 | \r |
d71c25cf | 971 | }\r |
3cbfba02 DW |
972 | \r |
973 | return EFI_SUCCESS;\r | |
974 | }\r | |
975 | \r | |
976 | /**\r | |
977 | Source Or Destination with Length bytes.\r | |
978 | \r | |
979 | @param[in] Destination Target memory\r | |
980 | @param[in] Source Source memory\r | |
981 | @param[in] Length Number of bytes\r | |
982 | \r | |
983 | @retval None\r | |
984 | \r | |
985 | **/\r | |
986 | VOID\r | |
987 | EfiOrMem (\r | |
988 | IN VOID *Destination,\r | |
989 | IN VOID *Source,\r | |
990 | IN UINTN Length\r | |
991 | )\r | |
992 | {\r | |
993 | CHAR8 *Destination8;\r | |
994 | CHAR8 *Source8;\r | |
995 | \r | |
996 | if (Source < Destination) {\r | |
997 | Destination8 = (CHAR8 *) Destination + Length - 1;\r | |
998 | Source8 = (CHAR8 *) Source + Length - 1;\r | |
999 | while (Length--) {\r | |
1000 | *(Destination8--) |= *(Source8--);\r | |
1001 | }\r | |
1002 | } else {\r | |
1003 | Destination8 = (CHAR8 *) Destination;\r | |
1004 | Source8 = (CHAR8 *) Source;\r | |
1005 | while (Length--) {\r | |
1006 | *(Destination8++) |= *(Source8++);\r | |
1007 | }\r | |
1008 | }\r | |
1009 | }\r | |
1010 | \r | |
1011 | VOID\r | |
1012 | PchInitBeforeBoot()\r | |
1013 | {\r | |
1014 | //\r | |
1015 | // Saved SPI Opcode menu to fix EFI variable unable to write after S3 resume.\r | |
1016 | //\r | |
1017 | S3BootScriptSaveMemWrite (\r | |
1018 | EfiBootScriptWidthUint32,\r | |
1019 | (UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU0)),\r | |
1020 | 1,\r | |
1021 | (VOID *)(UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU0)));\r | |
1022 | \r | |
1023 | S3BootScriptSaveMemWrite (\r | |
1024 | EfiBootScriptWidthUint32,\r | |
1025 | (UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU1)),\r | |
1026 | 1,\r | |
1027 | (VOID *)(UINTN)(SPI_BASE_ADDRESS + (R_PCH_SPI_OPMENU1)));\r | |
1028 | \r | |
1029 | S3BootScriptSaveMemWrite (\r | |
1030 | EfiBootScriptWidthUint16,\r | |
1031 | (UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_OPTYPE),\r | |
1032 | 1,\r | |
1033 | (VOID *)(UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_OPTYPE));\r | |
1034 | \r | |
1035 | S3BootScriptSaveMemWrite (\r | |
1036 | EfiBootScriptWidthUint16,\r | |
1037 | (UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_PREOP),\r | |
1038 | 1,\r | |
1039 | (VOID *)(UINTN)(SPI_BASE_ADDRESS + R_PCH_SPI_PREOP));\r | |
1040 | \r | |
1041 | //\r | |
1042 | // Saved MTPMC_1 for S3 resume.\r | |
1043 | //\r | |
1044 | S3BootScriptSaveMemWrite (\r | |
1045 | EfiBootScriptWidthUint32,\r | |
1046 | (UINTN)(PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1),\r | |
1047 | 1,\r | |
1048 | (VOID *)(UINTN)(PMC_BASE_ADDRESS + R_PCH_PMC_MTPMC1));\r | |
1049 | return;\r | |
1050 | }\r | |
1051 | \r | |
1052 | VOID\r | |
1053 | EFIAPI\r | |
1054 | ReadyToBootFunction (\r | |
1055 | EFI_EVENT Event,\r | |
1056 | VOID *Context\r | |
1057 | )\r | |
1058 | {\r | |
1059 | EFI_STATUS Status;\r | |
1060 | EFI_ISA_ACPI_PROTOCOL *IsaAcpi;\r | |
1061 | EFI_ISA_ACPI_DEVICE_ID IsaDevice;\r | |
1062 | UINTN Size;\r | |
1063 | UINT16 State;\r | |
1064 | EFI_TPM_MP_DRIVER_PROTOCOL *TpmMpDriver;\r | |
1065 | EFI_CPU_IO_PROTOCOL *CpuIo;\r | |
1066 | UINT8 Data;\r | |
1067 | UINT8 ReceiveBuffer [64];\r | |
1068 | UINT32 ReceiveBufferSize;\r | |
1069 | \r | |
1070 | UINT8 TpmForceClearCommand [] = {0x00, 0xC1,\r | |
1071 | 0x00, 0x00, 0x00, 0x0A,\r | |
1072 | 0x00, 0x00, 0x00, 0x5D};\r | |
1073 | UINT8 TpmPhysicalPresenceCommand [] = {0x00, 0xC1,\r | |
1074 | 0x00, 0x00, 0x00, 0x0C,\r | |
1075 | 0x40, 0x00, 0x00, 0x0A,\r | |
1076 | 0x00, 0x00};\r | |
1077 | UINT8 TpmPhysicalDisableCommand [] = {0x00, 0xC1,\r | |
1078 | 0x00, 0x00, 0x00, 0x0A,\r | |
1079 | 0x00, 0x00, 0x00, 0x70};\r | |
1080 | UINT8 TpmPhysicalEnableCommand [] = {0x00, 0xC1,\r | |
1081 | 0x00, 0x00, 0x00, 0x0A,\r | |
1082 | 0x00, 0x00, 0x00, 0x6F};\r | |
1083 | UINT8 TpmPhysicalSetDeactivatedCommand [] = {0x00, 0xC1,\r | |
1084 | 0x00, 0x00, 0x00, 0x0B,\r | |
1085 | 0x00, 0x00, 0x00, 0x72,\r | |
1086 | 0x00};\r | |
1087 | UINT8 TpmSetOwnerInstallCommand [] = {0x00, 0xC1,\r | |
1088 | 0x00, 0x00, 0x00, 0x0B,\r | |
1089 | 0x00, 0x00, 0x00, 0x71,\r | |
1090 | 0x00};\r | |
1091 | \r | |
1092 | Size = sizeof(UINT16);\r | |
1093 | Status = gRT->GetVariable (\r | |
1094 | VAR_EQ_FLOPPY_MODE_DECIMAL_NAME,\r | |
1095 | &gEfiNormalSetupGuid,\r | |
1096 | NULL,\r | |
1097 | &Size,\r | |
1098 | &State\r | |
1099 | );\r | |
1100 | \r | |
1101 | //\r | |
1102 | // Disable Floppy Controller if needed\r | |
1103 | //\r | |
1104 | Status = gBS->LocateProtocol (&gEfiIsaAcpiProtocolGuid, NULL, (VOID **) &IsaAcpi);\r | |
1105 | if (!EFI_ERROR(Status) && (State == 0x00)) {\r | |
1106 | IsaDevice.HID = EISA_PNP_ID(0x604);\r | |
1107 | IsaDevice.UID = 0;\r | |
1108 | Status = IsaAcpi->EnableDevice(IsaAcpi, &IsaDevice, FALSE);\r | |
1109 | }\r | |
1110 | \r | |
1111 | //\r | |
1112 | // save LAN info to a variable\r | |
1113 | //\r | |
1114 | if (NULL != mPciLanInfo) {\r | |
1115 | gRT->SetVariable (\r | |
1116 | L"PciLanInfo",\r | |
1117 | &gEfiPciLanInfoGuid,\r | |
1118 | EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS,\r | |
1119 | mPciLanCount * sizeof(PCI_LAN_INFO),\r | |
1120 | mPciLanInfo\r | |
1121 | );\r | |
1122 | }\r | |
1123 | \r | |
1124 | if (NULL != mPciLanInfo) {\r | |
1125 | gBS->FreePool (mPciLanInfo);\r | |
1126 | mPciLanInfo = NULL;\r | |
1127 | }\r | |
1128 | \r | |
1129 | \r | |
1130 | //\r | |
1131 | // Handle ACPI OS TPM requests here\r | |
1132 | //\r | |
1133 | Status = gBS->LocateProtocol (\r | |
1134 | &gEfiCpuIoProtocolGuid,\r | |
1135 | NULL,\r | |
1136 | (VOID **)&CpuIo\r | |
1137 | );\r | |
1138 | Status = gBS->LocateProtocol (\r | |
1139 | &gEfiTpmMpDriverProtocolGuid,\r | |
1140 | NULL,\r | |
1141 | (VOID **)&TpmMpDriver\r | |
1142 | );\r | |
1143 | if (!EFI_ERROR (Status))\r | |
1144 | {\r | |
1145 | Data = ReadCmosBank1Byte (CpuIo, ACPI_TPM_REQUEST);\r | |
1146 | \r | |
1147 | //\r | |
1148 | // Clear pending ACPI TPM request indicator\r | |
1149 | //\r | |
1150 | WriteCmosBank1Byte (CpuIo, ACPI_TPM_REQUEST, 0x00);\r | |
1151 | if (Data != 0)\r | |
1152 | {\r | |
1153 | WriteCmosBank1Byte (CpuIo, ACPI_TPM_LAST_REQUEST, Data);\r | |
1154 | \r | |
1155 | //\r | |
1156 | // Assert Physical Presence for these commands\r | |
1157 | //\r | |
1158 | TpmPhysicalPresenceCommand [11] = 0x20;\r | |
1159 | ReceiveBufferSize = sizeof(ReceiveBuffer);\r | |
1160 | Status = TpmMpDriver->Transmit (\r | |
1161 | TpmMpDriver, TpmPhysicalPresenceCommand,\r | |
1162 | sizeof (TpmPhysicalPresenceCommand),\r | |
1163 | ReceiveBuffer, &ReceiveBufferSize\r | |
1164 | );\r | |
1165 | //\r | |
1166 | // PF PhysicalPresence = TRUE\r | |
1167 | //\r | |
1168 | TpmPhysicalPresenceCommand [11] = 0x08;\r | |
1169 | ReceiveBufferSize = sizeof(ReceiveBuffer);\r | |
1170 | Status = TpmMpDriver->Transmit (\r | |
1171 | TpmMpDriver, TpmPhysicalPresenceCommand,\r | |
1172 | sizeof (TpmPhysicalPresenceCommand),\r | |
1173 | ReceiveBuffer,\r | |
1174 | &ReceiveBufferSize\r | |
1175 | );\r | |
1176 | if (Data == 0x01)\r | |
1177 | {\r | |
1178 | //\r | |
1179 | // TPM_PhysicalEnable\r | |
1180 | //\r | |
1181 | ReceiveBufferSize = sizeof(ReceiveBuffer);\r | |
1182 | Status = TpmMpDriver->Transmit (\r | |
1183 | TpmMpDriver, TpmPhysicalEnableCommand,\r | |
1184 | sizeof (TpmPhysicalEnableCommand),\r | |
1185 | ReceiveBuffer, &ReceiveBufferSize\r | |
1186 | );\r | |
1187 | }\r | |
1188 | if (Data == 0x02)\r | |
1189 | {\r | |
1190 | //\r | |
1191 | // TPM_PhysicalDisable\r | |
1192 | //\r | |
1193 | ReceiveBufferSize = sizeof(ReceiveBuffer);\r | |
1194 | Status = TpmMpDriver->Transmit (\r | |
1195 | TpmMpDriver, TpmPhysicalDisableCommand,\r | |
1196 | sizeof (TpmPhysicalDisableCommand),\r | |
1197 | ReceiveBuffer,\r | |
1198 | &ReceiveBufferSize\r | |
1199 | );\r | |
1200 | }\r | |
1201 | if (Data == 0x03)\r | |
1202 | {\r | |
1203 | //\r | |
1204 | // TPM_PhysicalSetDeactivated=FALSE\r | |
1205 | //\r | |
1206 | ReceiveBufferSize = sizeof(ReceiveBuffer);\r | |
1207 | TpmPhysicalSetDeactivatedCommand [10] = 0x00;\r | |
1208 | Status = TpmMpDriver->Transmit (\r | |
1209 | TpmMpDriver,\r | |
1210 | TpmPhysicalSetDeactivatedCommand,\r | |
1211 | sizeof (TpmPhysicalSetDeactivatedCommand),\r | |
1212 | ReceiveBuffer, &ReceiveBufferSize\r | |
1213 | );\r | |
1214 | gRT->ResetSystem (EfiResetWarm, EFI_SUCCESS, 0, NULL);\r | |
1215 | }\r | |
1216 | if (Data == 0x04)\r | |
1217 | {\r | |
1218 | //\r | |
1219 | // TPM_PhysicalSetDeactivated=TRUE\r | |
1220 | //\r | |
1221 | ReceiveBufferSize = sizeof(ReceiveBuffer);\r | |
1222 | TpmPhysicalSetDeactivatedCommand [10] = 0x01;\r | |
1223 | Status = TpmMpDriver->Transmit (\r | |
1224 | TpmMpDriver,\r | |
1225 | TpmPhysicalSetDeactivatedCommand,\r | |
1226 | sizeof (TpmPhysicalSetDeactivatedCommand),\r | |
1227 | ReceiveBuffer,\r | |
1228 | &ReceiveBufferSize\r | |
1229 | );\r | |
1230 | gRT->ResetSystem (\r | |
1231 | EfiResetWarm,\r | |
1232 | EFI_SUCCESS,\r | |
1233 | 0,\r | |
1234 | NULL\r | |
1235 | );\r | |
1236 | }\r | |
1237 | if (Data == 0x05)\r | |
1238 | {\r | |
1239 | //\r | |
1240 | // TPM_ForceClear\r | |
1241 | //\r | |
1242 | ReceiveBufferSize = sizeof(ReceiveBuffer);\r | |
1243 | Status = TpmMpDriver->Transmit (\r | |
1244 | TpmMpDriver,\r | |
1245 | TpmForceClearCommand,\r | |
1246 | sizeof (TpmForceClearCommand),\r | |
1247 | ReceiveBuffer,\r | |
1248 | &ReceiveBufferSize\r | |
1249 | );\r | |
1250 | gRT->ResetSystem (\r | |
1251 | EfiResetWarm,\r | |
1252 | EFI_SUCCESS,\r | |
1253 | 0,\r | |
1254 | NULL\r | |
1255 | );\r | |
1256 | }\r | |
1257 | if (Data == 0x06)\r | |
1258 | {\r | |
1259 | //\r | |
1260 | // TPM_PhysicalEnable\r | |
1261 | //\r | |
1262 | ReceiveBufferSize = sizeof(ReceiveBuffer);\r | |
1263 | Status = TpmMpDriver->Transmit (\r | |
1264 | TpmMpDriver,\r | |
1265 | TpmPhysicalEnableCommand,\r | |
1266 | sizeof (TpmPhysicalEnableCommand),\r | |
1267 | ReceiveBuffer,\r | |
1268 | &ReceiveBufferSize\r | |
1269 | );\r | |
1270 | //\r | |
1271 | // TPM_PhysicalSetDeactivated=FALSE\r | |
1272 | //\r | |
1273 | ReceiveBufferSize = sizeof(ReceiveBuffer);\r | |
1274 | TpmPhysicalSetDeactivatedCommand [10] = 0x00;\r | |
1275 | Status = TpmMpDriver->Transmit (\r | |
1276 | TpmMpDriver,\r | |
1277 | TpmPhysicalSetDeactivatedCommand,\r | |
1278 | sizeof (TpmPhysicalSetDeactivatedCommand),\r | |
1279 | ReceiveBuffer,\r | |
1280 | &ReceiveBufferSize\r | |
1281 | );\r | |
1282 | gRT->ResetSystem (\r | |
1283 | EfiResetWarm,\r | |
1284 | EFI_SUCCESS,\r | |
1285 | 0,\r | |
1286 | NULL\r | |
1287 | );\r | |
1288 | }\r | |
1289 | if (Data == 0x07)\r | |
1290 | {\r | |
1291 | //\r | |
1292 | // TPM_PhysicalSetDeactivated=TRUE\r | |
1293 | //\r | |
1294 | ReceiveBufferSize = sizeof(ReceiveBuffer);\r | |
1295 | TpmPhysicalSetDeactivatedCommand [10] = 0x01;\r | |
1296 | Status = TpmMpDriver->Transmit (\r | |
1297 | TpmMpDriver,\r | |
1298 | TpmPhysicalSetDeactivatedCommand,\r | |
1299 | sizeof (TpmPhysicalSetDeactivatedCommand),\r | |
1300 | ReceiveBuffer,\r | |
1301 | &ReceiveBufferSize\r | |
1302 | );\r | |
1303 | //\r | |
1304 | // TPM_PhysicalDisable\r | |
1305 | //\r | |
1306 | ReceiveBufferSize = sizeof(ReceiveBuffer);\r | |
1307 | Status = TpmMpDriver->Transmit (\r | |
1308 | TpmMpDriver,\r | |
1309 | TpmPhysicalDisableCommand,\r | |
1310 | sizeof (TpmPhysicalDisableCommand),\r | |
1311 | ReceiveBuffer,\r | |
1312 | &ReceiveBufferSize\r | |
1313 | );\r | |
1314 | gRT->ResetSystem (\r | |
1315 | EfiResetWarm,\r | |
1316 | EFI_SUCCESS,\r | |
1317 | 0,\r | |
1318 | NULL\r | |
1319 | );\r | |
1320 | }\r | |
1321 | if (Data == 0x08)\r | |
1322 | {\r | |
1323 | //\r | |
1324 | // TPM_SetOwnerInstall=TRUE\r | |
1325 | //\r | |
1326 | ReceiveBufferSize = sizeof(ReceiveBuffer);\r | |
1327 | TpmSetOwnerInstallCommand [10] = 0x01;\r | |
1328 | Status = TpmMpDriver->Transmit (\r | |
1329 | TpmMpDriver,\r | |
1330 | TpmSetOwnerInstallCommand,\r | |
1331 | sizeof (TpmSetOwnerInstallCommand),\r | |
1332 | ReceiveBuffer,\r | |
1333 | &ReceiveBufferSize\r | |
1334 | );\r | |
1335 | }\r | |
1336 | if (Data == 0x09)\r | |
1337 | {\r | |
1338 | //\r | |
1339 | // TPM_SetOwnerInstall=FALSE\r | |
1340 | //\r | |
1341 | ReceiveBufferSize = sizeof(ReceiveBuffer);\r | |
1342 | TpmSetOwnerInstallCommand [10] = 0x00;\r | |
1343 | Status = TpmMpDriver->Transmit (\r | |
1344 | TpmMpDriver,\r | |
1345 | TpmSetOwnerInstallCommand,\r | |
1346 | sizeof (TpmSetOwnerInstallCommand),\r | |
1347 | ReceiveBuffer,\r | |
1348 | &ReceiveBufferSize\r | |
1349 | );\r | |
1350 | }\r | |
1351 | if (Data == 0x0A)\r | |
1352 | {\r | |
1353 | //\r | |
1354 | // TPM_PhysicalEnable\r | |
1355 | //\r | |
1356 | ReceiveBufferSize = sizeof(ReceiveBuffer);\r | |
1357 | Status = TpmMpDriver->Transmit (\r | |
1358 | TpmMpDriver,\r | |
1359 | TpmPhysicalEnableCommand,\r | |
1360 | sizeof (TpmPhysicalEnableCommand),\r | |
1361 | ReceiveBuffer,\r | |
1362 | &ReceiveBufferSize\r | |
1363 | );\r | |
1364 | //\r | |
1365 | // TPM_PhysicalSetDeactivated=FALSE\r | |
1366 | //\r | |
1367 | ReceiveBufferSize = sizeof(ReceiveBuffer);\r | |
1368 | TpmPhysicalSetDeactivatedCommand [10] = 0x00;\r | |
1369 | Status = TpmMpDriver->Transmit (\r | |
1370 | TpmMpDriver,\r | |
1371 | TpmPhysicalSetDeactivatedCommand,\r | |
1372 | sizeof (TpmPhysicalSetDeactivatedCommand),\r | |
1373 | ReceiveBuffer,\r | |
1374 | &ReceiveBufferSize\r | |
1375 | );\r | |
1376 | //\r | |
1377 | // Do TPM_SetOwnerInstall=TRUE on next reboot\r | |
1378 | //\r | |
1379 | \r | |
1380 | WriteCmosBank1Byte (CpuIo, ACPI_TPM_REQUEST, 0xF0);\r | |
1381 | \r | |
1382 | gRT->ResetSystem (\r | |
1383 | EfiResetWarm,\r | |
1384 | EFI_SUCCESS,\r | |
1385 | 0,\r | |
1386 | NULL\r | |
1387 | );\r | |
1388 | }\r | |
1389 | if (Data == 0x0B)\r | |
1390 | {\r | |
1391 | //\r | |
1392 | // TPM_SetOwnerInstall=FALSE\r | |
1393 | //\r | |
1394 | ReceiveBufferSize = sizeof(ReceiveBuffer);\r | |
1395 | TpmSetOwnerInstallCommand [10] = 0x00;\r | |
1396 | Status = TpmMpDriver->Transmit (\r | |
1397 | TpmMpDriver,\r | |
1398 | TpmSetOwnerInstallCommand,\r | |
1399 | sizeof (TpmSetOwnerInstallCommand),\r | |
1400 | ReceiveBuffer,\r | |
1401 | &ReceiveBufferSize\r | |
1402 | );\r | |
1403 | //\r | |
1404 | // TPM_PhysicalSetDeactivated=TRUE\r | |
1405 | //\r | |
1406 | ReceiveBufferSize = sizeof(ReceiveBuffer);\r | |
1407 | TpmPhysicalSetDeactivatedCommand [10] = 0x01;\r | |
1408 | Status = TpmMpDriver->Transmit (\r | |
1409 | TpmMpDriver,\r | |
1410 | TpmPhysicalSetDeactivatedCommand,\r | |
1411 | sizeof (TpmPhysicalSetDeactivatedCommand),\r | |
1412 | ReceiveBuffer,\r | |
1413 | &ReceiveBufferSize\r | |
1414 | );\r | |
1415 | //\r | |
1416 | // TPM_PhysicalDisable\r | |
1417 | //\r | |
1418 | ReceiveBufferSize = sizeof(ReceiveBuffer);\r | |
1419 | Status = TpmMpDriver->Transmit (\r | |
1420 | TpmMpDriver,\r | |
1421 | TpmPhysicalDisableCommand,\r | |
1422 | sizeof (TpmPhysicalDisableCommand),\r | |
1423 | ReceiveBuffer,\r | |
1424 | &ReceiveBufferSize\r | |
1425 | );\r | |
1426 | gRT->ResetSystem (\r | |
1427 | EfiResetWarm,\r | |
1428 | EFI_SUCCESS,\r | |
1429 | 0,\r | |
1430 | NULL\r | |
1431 | );\r | |
1432 | }\r | |
1433 | if (Data == 0x0E)\r | |
1434 | {\r | |
1435 | //\r | |
1436 | // TPM_ForceClear\r | |
1437 | //\r | |
1438 | ReceiveBufferSize = sizeof(ReceiveBuffer);\r | |
1439 | Status = TpmMpDriver->Transmit (\r | |
1440 | TpmMpDriver,\r | |
1441 | TpmForceClearCommand,\r | |
1442 | sizeof (TpmForceClearCommand),\r | |
1443 | ReceiveBuffer,\r | |
1444 | &ReceiveBufferSize\r | |
1445 | );\r | |
1446 | //\r | |
1447 | // TPM_PhysicalEnable\r | |
1448 | //\r | |
1449 | ReceiveBufferSize = sizeof(ReceiveBuffer);\r | |
1450 | Status = TpmMpDriver->Transmit (\r | |
1451 | TpmMpDriver,\r | |
1452 | TpmPhysicalEnableCommand,\r | |
1453 | sizeof (TpmPhysicalEnableCommand),\r | |
1454 | ReceiveBuffer,\r | |
1455 | &ReceiveBufferSize\r | |
1456 | );\r | |
1457 | //\r | |
1458 | // TPM_PhysicalSetDeactivated=FALSE\r | |
1459 | //\r | |
1460 | ReceiveBufferSize = sizeof(ReceiveBuffer);\r | |
1461 | TpmPhysicalSetDeactivatedCommand [10] = 0x00;\r | |
1462 | Status = TpmMpDriver->Transmit (\r | |
1463 | TpmMpDriver,\r | |
1464 | TpmPhysicalSetDeactivatedCommand,\r | |
1465 | sizeof (TpmPhysicalSetDeactivatedCommand),\r | |
1466 | ReceiveBuffer,\r | |
1467 | &ReceiveBufferSize\r | |
1468 | );\r | |
1469 | gRT->ResetSystem (\r | |
1470 | EfiResetWarm,\r | |
1471 | EFI_SUCCESS,\r | |
1472 | 0,\r | |
1473 | NULL\r | |
1474 | );\r | |
1475 | }\r | |
1476 | if (Data == 0xF0)\r | |
1477 | {\r | |
1478 | //\r | |
1479 | // Second part of ACPI TPM request 0x0A: OEM custom TPM_SetOwnerInstall=TRUE\r | |
1480 | //\r | |
1481 | ReceiveBufferSize = sizeof(ReceiveBuffer);\r | |
1482 | TpmSetOwnerInstallCommand [10] = 0x01;\r | |
1483 | Status = TpmMpDriver->Transmit (\r | |
1484 | TpmMpDriver,\r | |
1485 | TpmSetOwnerInstallCommand,\r | |
1486 | sizeof (TpmSetOwnerInstallCommand),\r | |
1487 | ReceiveBuffer,\r | |
1488 | &ReceiveBufferSize\r | |
1489 | );\r | |
1490 | WriteCmosBank1Byte (CpuIo, ACPI_TPM_LAST_REQUEST, 0x0A);\r | |
1491 | }\r | |
1492 | //\r | |
1493 | // Deassert Physical Presence\r | |
1494 | //\r | |
1495 | TpmPhysicalPresenceCommand [11] = 0x10;\r | |
1496 | ReceiveBufferSize = sizeof(ReceiveBuffer);\r | |
1497 | Status = TpmMpDriver->Transmit (\r | |
1498 | TpmMpDriver,\r | |
1499 | TpmPhysicalPresenceCommand,\r | |
1500 | sizeof (TpmPhysicalPresenceCommand),\r | |
1501 | ReceiveBuffer,\r | |
1502 | &ReceiveBufferSize\r | |
1503 | );\r | |
1504 | }\r | |
1505 | }\r | |
1506 | \r | |
1507 | return;\r | |
1508 | }\r | |
1509 | \r | |
1510 | /**\r | |
1511 | \r | |
1512 | Initializes manufacturing and config mode setting.\r | |
1513 | \r | |
1514 | **/\r | |
1515 | VOID\r | |
1516 | InitMfgAndConfigModeStateVar()\r | |
1517 | {\r | |
1518 | EFI_PLATFORM_SETUP_ID *BootModeBuffer;\r | |
1519 | VOID *HobList;\r | |
3cbfba02 | 1520 | \r |
3cbfba02 DW |
1521 | \r |
1522 | HobList = GetFirstGuidHob(&gEfiPlatformBootModeGuid);\r | |
1523 | if (HobList != NULL) {\r | |
1524 | BootModeBuffer = GET_GUID_HOB_DATA (HobList);\r | |
1525 | \r | |
1526 | //\r | |
1527 | // Check if in Manufacturing mode\r | |
1528 | //\r | |
1529 | if ( !CompareMem (\r | |
1530 | &BootModeBuffer->SetupName,\r | |
1531 | MANUFACTURE_SETUP_NAME,\r | |
1532 | StrSize (MANUFACTURE_SETUP_NAME)\r | |
1533 | ) ) {\r | |
1534 | mMfgMode = TRUE;\r | |
1535 | }\r | |
1536 | \r | |
620f2891 TH |
1537 | \r |
1538 | \r | |
3cbfba02 DW |
1539 | }\r |
1540 | \r | |
1541 | }\r | |
1542 | \r | |
1543 | /**\r | |
1544 | \r | |
1545 | Initializes manufacturing and config mode setting.\r | |
1546 | \r | |
1547 | **/\r | |
1548 | VOID\r | |
1549 | InitPlatformBootMode()\r | |
1550 | {\r | |
1551 | EFI_PLATFORM_SETUP_ID *BootModeBuffer;\r | |
1552 | VOID *HobList;\r | |
1553 | \r | |
1554 | HobList = GetFirstGuidHob(&gEfiPlatformBootModeGuid);\r | |
1555 | if (HobList != NULL) {\r | |
1556 | BootModeBuffer = GET_GUID_HOB_DATA (HobList);\r | |
1557 | mPlatformBootMode = BootModeBuffer->PlatformBootMode;\r | |
1558 | }\r | |
1559 | }\r | |
1560 | \r | |
1561 | /**\r | |
1562 | \r | |
1563 | Initializes ITK.\r | |
1564 | \r | |
1565 | **/\r | |
1566 | VOID\r | |
1567 | InitItk(\r | |
1568 | )\r | |
1569 | {\r | |
1570 | EFI_STATUS Status;\r | |
1571 | UINT16 ItkModBiosState;\r | |
1572 | UINT8 Value;\r | |
1573 | UINTN DataSize;\r | |
1574 | UINT32 Attributes;\r | |
1575 | \r | |
1576 | //\r | |
1577 | // Setup local variable according to ITK variable\r | |
1578 | //\r | |
1579 | //\r | |
1580 | // Read ItkBiosModVar to determine if BIOS has been modified by ITK\r | |
1581 | // If ItkBiosModVar = 0 or if variable hasn't been initialized then BIOS has not been modified by ITK modified\r | |
1582 | // Set local variable VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME=0 if BIOS has not been modified by ITK\r | |
1583 | //\r | |
1584 | DataSize = sizeof (Value);\r | |
1585 | Status = gRT->GetVariable (\r | |
1586 | ITK_BIOS_MOD_VAR_NAME,\r | |
1587 | &gItkDataVarGuid,\r | |
1588 | &Attributes,\r | |
1589 | &DataSize,\r | |
1590 | &Value\r | |
1591 | );\r | |
1592 | if (Status == EFI_NOT_FOUND) {\r | |
1593 | //\r | |
1594 | // Variable not found, hasn't been initialized, intialize to 0\r | |
1595 | //\r | |
1596 | Value=0x00;\r | |
1597 | //\r | |
1598 | // Write variable to flash.\r | |
1599 | //\r | |
1600 | gRT->SetVariable (\r | |
1601 | ITK_BIOS_MOD_VAR_NAME,\r | |
1602 | &gItkDataVarGuid,\r | |
1603 | EFI_VARIABLE_RUNTIME_ACCESS |\r | |
1604 | EFI_VARIABLE_NON_VOLATILE |\r | |
1605 | EFI_VARIABLE_BOOTSERVICE_ACCESS,\r | |
1606 | sizeof (Value),\r | |
1607 | &Value\r | |
1608 | );\r | |
1609 | \r | |
1610 | }\r | |
1611 | if ( (!EFI_ERROR (Status)) || (Status == EFI_NOT_FOUND) ) {\r | |
1612 | if (Value == 0x00) {\r | |
1613 | ItkModBiosState = 0x00;\r | |
1614 | } else {\r | |
1615 | ItkModBiosState = 0x01;\r | |
1616 | }\r | |
1617 | gRT->SetVariable (\r | |
1618 | VAR_EQ_ITK_BIOS_MOD_DECIMAL_NAME,\r | |
1619 | &gEfiNormalSetupGuid,\r | |
1620 | EFI_VARIABLE_BOOTSERVICE_ACCESS,\r | |
1621 | 2,\r | |
1622 | (void *)&ItkModBiosState\r | |
1623 | );\r | |
1624 | }\r | |
1625 | }\r | |
1626 | \r | |
1627 | #if defined(FIRMWARE_ID_BACKWARD_COMPATIBLE) && (FIRMWARE_ID_BACKWARD_COMPATIBLE != 0)\r | |
1628 | \r | |
1629 | /**\r | |
1630 | \r | |
1631 | Initializes the BIOS FIRMWARE ID from the FIRMWARE_ID build variable.\r | |
1632 | \r | |
1633 | **/\r | |
1634 | STATIC\r | |
1635 | VOID\r | |
1636 | InitFirmwareId(\r | |
1637 | )\r | |
1638 | {\r | |
1639 | EFI_STATUS Status;\r | |
1640 | CHAR16 FirmwareIdNameWithPassword[] = FIRMWARE_ID_NAME_WITH_PASSWORD;\r | |
1641 | \r | |
1642 | //\r | |
1643 | // First try writing the variable without a password in case we are\r | |
1644 | // upgrading from a BIOS without password protection on the FirmwareId\r | |
1645 | //\r | |
1646 | Status = gRT->SetVariable(\r | |
1647 | (CHAR16 *)&gFirmwareIdName,\r | |
1648 | &gFirmwareIdGuid,\r | |
1649 | EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS |\r | |
1650 | EFI_VARIABLE_RUNTIME_ACCESS,\r | |
1651 | sizeof( FIRMWARE_ID ) - 1,\r | |
1652 | FIRMWARE_ID\r | |
1653 | );\r | |
1654 | \r | |
1655 | if (Status == EFI_INVALID_PARAMETER) {\r | |
1656 | \r | |
1657 | //\r | |
1658 | // Since setting the firmware id without the password failed,\r | |
1659 | // a password must be required.\r | |
1660 | //\r | |
1661 | Status = gRT->SetVariable(\r | |
1662 | (CHAR16 *)&FirmwareIdNameWithPassword,\r | |
1663 | &gFirmwareIdGuid,\r | |
1664 | EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS |\r | |
1665 | EFI_VARIABLE_RUNTIME_ACCESS,\r | |
1666 | sizeof( FIRMWARE_ID ) - 1,\r | |
1667 | FIRMWARE_ID\r | |
1668 | );\r | |
1669 | }\r | |
1670 | }\r | |
1671 | #endif\r | |
1672 | \r | |
1673 | VOID\r | |
1674 | UpdateDVMTSetup(\r | |
1675 | )\r | |
1676 | {\r | |
1677 | //\r | |
1678 | // Workaround to support IIA bug.\r | |
1679 | // IIA request to change option value to 4, 5 and 7 relatively\r | |
1680 | // instead of 1, 2, and 3 which follow Lakeport Specs.\r | |
1681 | // Check option value, temporary hardcode GraphicsDriverMemorySize\r | |
1682 | // Option value to fulfill IIA requirment. So that user no need to\r | |
1683 | // load default and update setupvariable after update BIOS.\r | |
1684 | // Option value hardcoded as: 1 to 4, 2 to 5, 3 to 7.\r | |
1685 | // *This is for broadwater and above product only.\r | |
1686 | //\r | |
1687 | \r | |
1688 | SYSTEM_CONFIGURATION SystemConfiguration;\r | |
1689 | UINTN VarSize;\r | |
1690 | EFI_STATUS Status;\r | |
1691 | \r | |
1692 | VarSize = sizeof(SYSTEM_CONFIGURATION);\r | |
1693 | Status = gRT->GetVariable(\r | |
1694 | NORMAL_SETUP_NAME,\r | |
1695 | &gEfiNormalSetupGuid,\r | |
1696 | NULL,\r | |
1697 | &VarSize,\r | |
1698 | &SystemConfiguration\r | |
1699 | );\r | |
1700 | \r | |
620f2891 TH |
1701 | if (EFI_ERROR (Status) || VarSize != sizeof(SYSTEM_CONFIGURATION)) {\r |
1702 | //The setup variable is corrupted\r | |
1703 | VarSize = sizeof(SYSTEM_CONFIGURATION);\r | |
1704 | Status = gRT->GetVariable(\r | |
1705 | L"SetupRecovery",\r | |
1706 | &gEfiNormalSetupGuid,\r | |
1707 | NULL,\r | |
1708 | &VarSize,\r | |
1709 | &SystemConfiguration\r | |
1710 | );\r | |
1711 | ASSERT_EFI_ERROR (Status);\r | |
1712 | }\r | |
1713 | \r | |
3cbfba02 DW |
1714 | if((SystemConfiguration.GraphicsDriverMemorySize < 4) && !EFI_ERROR(Status) ) {\r |
1715 | switch (SystemConfiguration.GraphicsDriverMemorySize){\r | |
1716 | case 1:\r | |
1717 | SystemConfiguration.GraphicsDriverMemorySize = 4;\r | |
1718 | break;\r | |
1719 | case 2:\r | |
1720 | SystemConfiguration.GraphicsDriverMemorySize = 5;\r | |
1721 | break;\r | |
1722 | case 3:\r | |
1723 | SystemConfiguration.GraphicsDriverMemorySize = 7;\r | |
1724 | break;\r | |
1725 | default:\r | |
1726 | break;\r | |
1727 | }\r | |
1728 | \r | |
1729 | Status = gRT->SetVariable (\r | |
1730 | NORMAL_SETUP_NAME,\r | |
1731 | &gEfiNormalSetupGuid,\r | |
1732 | EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,\r | |
1733 | sizeof(SYSTEM_CONFIGURATION),\r | |
1734 | &SystemConfiguration\r | |
1735 | );\r | |
1736 | }\r | |
1737 | }\r | |
1738 | \r | |
1739 | VOID\r | |
1740 | InitPlatformUsbPolicy (\r | |
1741 | VOID\r | |
1742 | )\r | |
1743 | \r | |
1744 | {\r | |
1745 | EFI_HANDLE Handle;\r | |
1746 | EFI_STATUS Status;\r | |
1747 | \r | |
1748 | Handle = NULL;\r | |
1749 | \r | |
1750 | mUsbPolicyData.Version = (UINT8)USB_POLICY_PROTOCOL_REVISION_2;\r | |
1751 | mUsbPolicyData.UsbMassStorageEmulationType = mSystemConfiguration.UsbBIOSINT13DeviceEmulation;\r | |
1752 | if(mUsbPolicyData.UsbMassStorageEmulationType == 3) {\r | |
1753 | mUsbPolicyData.UsbEmulationSize = mSystemConfiguration.UsbBIOSINT13DeviceEmulationSize;\r | |
1754 | } else {\r | |
1755 | mUsbPolicyData.UsbEmulationSize = 0;\r | |
1756 | }\r | |
1757 | mUsbPolicyData.UsbZipEmulationType = mSystemConfiguration.UsbZipEmulation;\r | |
1758 | mUsbPolicyData.UsbOperationMode = HIGH_SPEED;\r | |
1759 | \r | |
1760 | //\r | |
1761 | // Some chipset need Period smi, 0 = LEGACY_PERIOD_UN_SUPP\r | |
1762 | //\r | |
1763 | mUsbPolicyData.USBPeriodSupport = LEGACY_PERIOD_UN_SUPP;\r | |
1764 | \r | |
1765 | //\r | |
1766 | // Some platform need legacyfree, 0 = LEGACY_FREE_UN_SUPP\r | |
1767 | //\r | |
1768 | mUsbPolicyData.LegacyFreeSupport = LEGACY_FREE_UN_SUPP;\r | |
1769 | \r | |
1770 | //\r | |
1771 | // Set Code base , TIANO_CODE_BASE =0x01, ICBD =0x00\r | |
1772 | //\r | |
1773 | mUsbPolicyData.CodeBase = (UINT8)ICBD_CODE_BASE;\r | |
1774 | \r | |
1775 | //\r | |
1776 | // Some chispet 's LpcAcpibase are diffrent,set by platform or chipset,\r | |
1777 | // default is Ich acpibase =0x040. acpitimerreg=0x08.\r | |
1778 | mUsbPolicyData.LpcAcpiBase = 0x40;\r | |
1779 | mUsbPolicyData.AcpiTimerReg = 0x08;\r | |
1780 | \r | |
1781 | //\r | |
1782 | // Set for reduce usb post time\r | |
1783 | //\r | |
1784 | mUsbPolicyData.UsbTimeTue = 0x00;\r | |
1785 | mUsbPolicyData.InternelHubExist = 0x00; //TigerPoint doesn't have RMH\r | |
1786 | mUsbPolicyData.EnumWaitPortStableStall = 100;\r | |
1787 | \r | |
1788 | \r | |
1789 | Status = gBS->InstallProtocolInterface (\r | |
1790 | &Handle,\r | |
1791 | &gUsbPolicyGuid,\r | |
1792 | EFI_NATIVE_INTERFACE,\r | |
1793 | &mUsbPolicyData\r | |
1794 | );\r | |
1795 | ASSERT_EFI_ERROR(Status);\r | |
1796 | \r | |
1797 | }\r | |
1798 | \r | |
1799 | UINT8\r | |
1800 | ReadCmosBank1Byte (\r | |
1801 | IN EFI_CPU_IO_PROTOCOL *CpuIo,\r | |
1802 | IN UINT8 Index\r | |
1803 | )\r | |
1804 | {\r | |
1805 | UINT8 Data;\r | |
1806 | \r | |
1807 | CpuIo->Io.Write (CpuIo, EfiCpuIoWidthUint8, 0x72, 1, &Index);\r | |
1808 | CpuIo->Io.Read (CpuIo, EfiCpuIoWidthUint8, 0x73, 1, &Data);\r | |
1809 | return Data;\r | |
1810 | }\r | |
1811 | \r | |
1812 | VOID\r | |
1813 | WriteCmosBank1Byte (\r | |
1814 | IN EFI_CPU_IO_PROTOCOL *CpuIo,\r | |
1815 | IN UINT8 Index,\r | |
1816 | IN UINT8 Data\r | |
1817 | )\r | |
1818 | {\r | |
1819 | CpuIo->Io.Write (\r | |
1820 | CpuIo,\r | |
1821 | EfiCpuIoWidthUint8,\r | |
1822 | 0x72,\r | |
1823 | 1,\r | |
1824 | &Index\r | |
1825 | );\r | |
1826 | CpuIo->Io.Write (\r | |
1827 | CpuIo,\r | |
1828 | EfiCpuIoWidthUint8,\r | |
1829 | 0x73,\r | |
1830 | 1,\r | |
1831 | &Data\r | |
1832 | );\r | |
1833 | }\r | |
1834 | \r |