]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - arch/x86/kvm/vmx.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: VMX: Move real-mode interrupt injection fixup to vmx_complete_interrupts()
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
221d059d 8 * Copyright 2010 Red Hat, Inc. and/or its affilates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
e495606d 21
edf88417 22#include <linux/kvm_host.h>
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/mm.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
c7addb90 28#include <linux/moduleparam.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
cafd6659 31#include <linux/tboot.h>
5fdbf976 32#include "kvm_cache_regs.h"
35920a35 33#include "x86.h"
e495606d 34
6aa8b732 35#include <asm/io.h>
3b3be0d1 36#include <asm/desc.h>
13673a90 37#include <asm/vmx.h>
6210e37b 38#include <asm/virtext.h>
a0861c02 39#include <asm/mce.h>
2acf923e
DC		 40#include <asm/i387.h>
41#include <asm/xcr.h>
6aa8b732 42
229456fc
MT		 43#include "trace.h"
44
4ecac3fd
AK		 45#define __ex(x) __kvm_handle_fault_on_reboot(x)
46
6aa8b732
AK		 47MODULE_AUTHOR("Qumranet");
48MODULE_LICENSE("GPL");
49
4462d21a 50static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 51module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 52
4462d21a 53static int __read_mostly enable_vpid = 1;
736caefe 54module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 55
4462d21a 56static int __read_mostly flexpriority_enabled = 1;
736caefe 57module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 58
4462d21a 59static int __read_mostly enable_ept = 1;
736caefe 60module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 61
3a624e29
NK		 62static int __read_mostly enable_unrestricted_guest = 1;
63module_param_named(unrestricted_guest,
64 enable_unrestricted_guest, bool, S_IRUGO);
65
4462d21a 66static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 67module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 68
b923e62e
DX		 69static int __read_mostly vmm_exclusive = 1;
70module_param(vmm_exclusive, bool, S_IRUGO);
71
cdc0e244
AK		 72#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
73 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
74#define KVM_GUEST_CR0_MASK \
75 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
76#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 77 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 78#define KVM_VM_CR0_ALWAYS_ON \
79 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 80#define KVM_CR4_GUEST_OWNED_BITS \
81 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
82 | X86_CR4_OSXMMEXCPT)
83
cdc0e244
AK		 84#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
85#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
86
78ac8b47
AK		 87#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
88
4b8d54f9
ZE		 89/*
90 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
91 * ple_gap: upper bound on the amount of time between two successive
92 * executions of PAUSE in a loop. Also indicate if ple enabled.
93 * According to test, this time is usually small than 41 cycles.
94 * ple_window: upper bound on the amount of time a guest is allowed to execute
95 * in a PAUSE loop. Tests indicate that most spinlocks are held for
96 * less than 2^12 cycles
97 * Time is measured based on a counter that runs at the same rate as the TSC,
98 * refer SDM volume 3b section 21.6.13 & 22.1.3.
99 */
100#define KVM_VMX_DEFAULT_PLE_GAP 41
101#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
102static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
103module_param(ple_gap, int, S_IRUGO);
104
105static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
106module_param(ple_window, int, S_IRUGO);
107
61d2ef2c
AK		 108#define NR_AUTOLOAD_MSRS 1
109
a2fa3e9f
GH		 110struct vmcs {
111 u32 revision_id;
112 u32 abort;
113 char data[0];
114};
115
26bb0981
AK		 116struct shared_msr_entry {
117 unsigned index;
118 u64 data;
d5696725 119 u64 mask;
26bb0981
AK		 120};
121
a2fa3e9f 122struct vcpu_vmx {
fb3f0f51 123 struct kvm_vcpu vcpu;
543e4243 124 struct list_head local_vcpus_link;
313dbd49 125 unsigned long host_rsp;
a2fa3e9f 126 int launched;
29bd8a78 127 u8 fail;
51aa01d1 128 u32 exit_intr_info;
1155f76a 129 u32 idt_vectoring_info;
26bb0981 130 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 131 int nmsrs;
132 int save_nmsrs;
a2fa3e9f 133#ifdef CONFIG_X86_64
44ea2b17
AK		 134 u64 msr_host_kernel_gs_base;
135 u64 msr_guest_kernel_gs_base;
a2fa3e9f
GH		 136#endif
137 struct vmcs *vmcs;
61d2ef2c
AK		 138 struct msr_autoload {
139 unsigned nr;
140 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
141 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
142 } msr_autoload;
a2fa3e9f
GH		 143 struct {
144 int loaded;
145 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 146 int gs_ldt_reload_needed;
147 int fs_reload_needed;
d77c26fc 148 } host_state;
9c8cba37 149 struct {
7ffd92c5 150 int vm86_active;
78ac8b47 151 ulong save_rflags;
7ffd92c5
AK		 152 struct kvm_save_segment {
153 u16 selector;
154 unsigned long base;
155 u32 limit;
156 u32 ar;
157 } tr, es, ds, fs, gs;
9c8cba37
AK		 158 struct {
159 bool pending;
160 u8 vector;
161 unsigned rip;
162 } irq;
163 } rmode;
2384d2b3 164 int vpid;
04fa4d32 165 bool emulation_required;
3b86cd99
JK		 166
167 /* Support for vnmi-less CPUs */
168 int soft_vnmi_blocked;
169 ktime_t entry_time;
170 s64 vnmi_blocked_time;
a0861c02 171 u32 exit_reason;
4e47c7a6
SY		 172
173 bool rdtscp_enabled;
a2fa3e9f
GH		 174};
175
176static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
177{
fb3f0f51 178 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 179}
180
b7ebfb05 181static int init_rmode(struct kvm *kvm);
4e1096d2 182static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 183static void kvm_cpu_vmxon(u64 addr);
184static void kvm_cpu_vmxoff(void);
537b37e2 185static void fixup_rmode_irq(struct vcpu_vmx *vmx);
75880a01 186
6aa8b732
AK		 187static DEFINE_PER_CPU(struct vmcs *, vmxarea);
188static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 189static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
3444d7da 190static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 191
3e7c73e9
AK		 192static unsigned long *vmx_io_bitmap_a;
193static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 194static unsigned long *vmx_msr_bitmap_legacy;
195static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 196
2384d2b3
SY		 197static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
198static DEFINE_SPINLOCK(vmx_vpid_lock);
199
1c3d14fe 200static struct vmcs_config {
6aa8b732
AK		 201 int size;
202 int order;
203 u32 revision_id;
1c3d14fe
YS		 204 u32 pin_based_exec_ctrl;
205 u32 cpu_based_exec_ctrl;
f78e0e2e 206 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 207 u32 vmexit_ctrl;
208 u32 vmentry_ctrl;
209} vmcs_config;
6aa8b732 210
efff9e53 211static struct vmx_capability {
d56f546d
SY		 212 u32 ept;
213 u32 vpid;
214} vmx_capability;
215
6aa8b732
AK		 216#define VMX_SEGMENT_FIELD(seg) \
217 [VCPU_SREG_##seg] = { \
218 .selector = GUEST_##seg##_SELECTOR, \
219 .base = GUEST_##seg##_BASE, \
220 .limit = GUEST_##seg##_LIMIT, \
221 .ar_bytes = GUEST_##seg##_AR_BYTES, \
222 }
223
224static struct kvm_vmx_segment_field {
225 unsigned selector;
226 unsigned base;
227 unsigned limit;
228 unsigned ar_bytes;
229} kvm_vmx_segment_fields[] = {
230 VMX_SEGMENT_FIELD(CS),
231 VMX_SEGMENT_FIELD(DS),
232 VMX_SEGMENT_FIELD(ES),
233 VMX_SEGMENT_FIELD(FS),
234 VMX_SEGMENT_FIELD(GS),
235 VMX_SEGMENT_FIELD(SS),
236 VMX_SEGMENT_FIELD(TR),
237 VMX_SEGMENT_FIELD(LDTR),
238};
239
26bb0981
AK		 240static u64 host_efer;
241
6de4f3ad
AK		 242static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
243
4d56c8a7 244/*
8c06585d 245 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 246 * away by decrementing the array size.
247 */
6aa8b732 248static const u32 vmx_msr_index[] = {
05b3e0c2 249#ifdef CONFIG_X86_64
44ea2b17 250 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 251#endif
8c06585d 252 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 253};
9d8f549d 254#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 255
31299944 256static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 257{
258 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
259 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 260 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 261}
262
31299944 263static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 264{
265 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
266 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 267 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 268}
269
31299944 270static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 271{
272 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
273 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 274 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 275}
276
31299944 277static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 278{
279 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
280 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
281}
282
31299944 283static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 284{
285 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
286 INTR_INFO_VALID_MASK)) ==
287 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
288}
289
31299944 290static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 291{
04547156 292 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 293}
294
31299944 295static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 296{
04547156 297 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 298}
299
31299944 300static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 301{
04547156 302 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 303}
304
31299944 305static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 306{
04547156
SY		 307 return vmcs_config.cpu_based_exec_ctrl &
308 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 309}
310
774ead3a 311static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 312{
04547156
SY		 313 return vmcs_config.cpu_based_2nd_exec_ctrl &
314 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
315}
316
317static inline bool cpu_has_vmx_flexpriority(void)
318{
319 return cpu_has_vmx_tpr_shadow() &&
320 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 321}
322
e799794e
MT		 323static inline bool cpu_has_vmx_ept_execute_only(void)
324{
31299944 325 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 326}
327
328static inline bool cpu_has_vmx_eptp_uncacheable(void)
329{
31299944 330 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 331}
332
333static inline bool cpu_has_vmx_eptp_writeback(void)
334{
31299944 335 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 336}
337
338static inline bool cpu_has_vmx_ept_2m_page(void)
339{
31299944 340 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 341}
342
878403b7
SY		 343static inline bool cpu_has_vmx_ept_1g_page(void)
344{
31299944 345 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 346}
347
4bc9b982
SY		 348static inline bool cpu_has_vmx_ept_4levels(void)
349{
350 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
351}
352
31299944 353static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 354{
31299944 355 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 356}
357
31299944 358static inline bool cpu_has_vmx_invept_context(void)
d56f546d 359{
31299944 360 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 361}
362
31299944 363static inline bool cpu_has_vmx_invept_global(void)
d56f546d 364{
31299944 365 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 366}
367
518c8aee
GJ		 368static inline bool cpu_has_vmx_invvpid_single(void)
369{
370 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
371}
372
b9d762fa
GJ		 373static inline bool cpu_has_vmx_invvpid_global(void)
374{
375 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
376}
377
31299944 378static inline bool cpu_has_vmx_ept(void)
d56f546d 379{
04547156
SY		 380 return vmcs_config.cpu_based_2nd_exec_ctrl &
381 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 382}
383
31299944 384static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 385{
386 return vmcs_config.cpu_based_2nd_exec_ctrl &
387 SECONDARY_EXEC_UNRESTRICTED_GUEST;
388}
389
31299944 390static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 391{
392 return vmcs_config.cpu_based_2nd_exec_ctrl &
393 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
394}
395
31299944 396static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 397{
6d3e435e 398 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 399}
400
31299944 401static inline bool cpu_has_vmx_vpid(void)
2384d2b3 402{
04547156
SY		 403 return vmcs_config.cpu_based_2nd_exec_ctrl &
404 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 405}
406
31299944 407static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 408{
409 return vmcs_config.cpu_based_2nd_exec_ctrl &
410 SECONDARY_EXEC_RDTSCP;
411}
412
31299944 413static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 414{
415 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
416}
417
f5f48ee1
SY		 418static inline bool cpu_has_vmx_wbinvd_exit(void)
419{
420 return vmcs_config.cpu_based_2nd_exec_ctrl &
421 SECONDARY_EXEC_WBINVD_EXITING;
422}
423
04547156
SY		 424static inline bool report_flexpriority(void)
425{
426 return flexpriority_enabled;
427}
428
8b9cf98c 429static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 430{
431 int i;
432
a2fa3e9f 433 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 434 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 435 return i;
436 return -1;
437}
438
2384d2b3
SY		 439static inline void __invvpid(int ext, u16 vpid, gva_t gva)
440{
441 struct {
442 u64 vpid : 16;
443 u64 rsvd : 48;
444 u64 gva;
445 } operand = { vpid, 0, gva };
446
4ecac3fd 447 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 448 /* CF==1 or ZF==1 --> rc = -1 */
449 "; ja 1f ; ud2 ; 1:"
450 : : "a"(&operand), "c"(ext) : "cc", "memory");
451}
452
1439442c
SY		 453static inline void __invept(int ext, u64 eptp, gpa_t gpa)
454{
455 struct {
456 u64 eptp, gpa;
457 } operand = {eptp, gpa};
458
4ecac3fd 459 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 460 /* CF==1 or ZF==1 --> rc = -1 */
461 "; ja 1f ; ud2 ; 1:\n"
462 : : "a" (&operand), "c" (ext) : "cc", "memory");
463}
464
26bb0981 465static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 466{
467 int i;
468
8b9cf98c 469 i = __find_msr_index(vmx, msr);
a75beee6 470 if (i >= 0)
a2fa3e9f 471 return &vmx->guest_msrs[i];
8b6d44c7 472 return NULL;
7725f0ba
AK		 473}
474
6aa8b732
AK		 475static void vmcs_clear(struct vmcs *vmcs)
476{
477 u64 phys_addr = __pa(vmcs);
478 u8 error;
479
4ecac3fd 480 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
6aa8b732
AK		 481 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
482 : "cc", "memory");
483 if (error)
484 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
485 vmcs, phys_addr);
486}
487
7725b894
DX		 488static void vmcs_load(struct vmcs *vmcs)
489{
490 u64 phys_addr = __pa(vmcs);
491 u8 error;
492
493 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
494 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
495 : "cc", "memory");
496 if (error)
497 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
498 vmcs, phys_addr);
499}
500
6aa8b732
AK		 501static void __vcpu_clear(void *arg)
502{
8b9cf98c 503 struct vcpu_vmx *vmx = arg;
d3b2c338 504 int cpu = raw_smp_processor_id();
6aa8b732 505
8b9cf98c 506 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 507 vmcs_clear(vmx->vmcs);
508 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 509 per_cpu(current_vmcs, cpu) = NULL;
543e4243
AK		 510 list_del(&vmx->local_vcpus_link);
511 vmx->vcpu.cpu = -1;
512 vmx->launched = 0;
6aa8b732
AK		 513}
514
8b9cf98c 515static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 516{
eae5ecb5
AK		 517 if (vmx->vcpu.cpu == -1)
518 return;
8691e5a8 519 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 520}
521
1760dd49 522static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 523{
524 if (vmx->vpid == 0)
525 return;
526
518c8aee
GJ		 527 if (cpu_has_vmx_invvpid_single())
528 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 529}
530
b9d762fa
GJ		 531static inline void vpid_sync_vcpu_global(void)
532{
533 if (cpu_has_vmx_invvpid_global())
534 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
535}
536
537static inline void vpid_sync_context(struct vcpu_vmx *vmx)
538{
539 if (cpu_has_vmx_invvpid_single())
1760dd49 540 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 541 else
542 vpid_sync_vcpu_global();
543}
544
1439442c
SY		 545static inline void ept_sync_global(void)
546{
547 if (cpu_has_vmx_invept_global())
548 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
549}
550
551static inline void ept_sync_context(u64 eptp)
552{
089d034e 553 if (enable_ept) {
1439442c
SY		 554 if (cpu_has_vmx_invept_context())
555 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
556 else
557 ept_sync_global();
558 }
559}
560
561static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
562{
089d034e 563 if (enable_ept) {
1439442c
SY		 564 if (cpu_has_vmx_invept_individual_addr())
565 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
566 eptp, gpa);
567 else
568 ept_sync_context(eptp);
569 }
570}
571
6aa8b732
AK		 572static unsigned long vmcs_readl(unsigned long field)
573{
574 unsigned long value;
575
4ecac3fd 576 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
6aa8b732
AK		 577 : "=a"(value) : "d"(field) : "cc");
578 return value;
579}
580
581static u16 vmcs_read16(unsigned long field)
582{
583 return vmcs_readl(field);
584}
585
586static u32 vmcs_read32(unsigned long field)
587{
588 return vmcs_readl(field);
589}
590
591static u64 vmcs_read64(unsigned long field)
592{
05b3e0c2 593#ifdef CONFIG_X86_64
6aa8b732
AK		 594 return vmcs_readl(field);
595#else
596 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
597#endif
598}
599
e52de1b8
AK		 600static noinline void vmwrite_error(unsigned long field, unsigned long value)
601{
602 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
603 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
604 dump_stack();
605}
606
6aa8b732
AK		 607static void vmcs_writel(unsigned long field, unsigned long value)
608{
609 u8 error;
610
4ecac3fd 611 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 612 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 613 if (unlikely(error))
614 vmwrite_error(field, value);
6aa8b732
AK		 615}
616
617static void vmcs_write16(unsigned long field, u16 value)
618{
619 vmcs_writel(field, value);
620}
621
622static void vmcs_write32(unsigned long field, u32 value)
623{
624 vmcs_writel(field, value);
625}
626
627static void vmcs_write64(unsigned long field, u64 value)
628{
6aa8b732 629 vmcs_writel(field, value);
7682f2d0 630#ifndef CONFIG_X86_64
6aa8b732
AK		 631 asm volatile ("");
632 vmcs_writel(field+1, value >> 32);
633#endif
634}
635
2ab455cc
AL		 636static void vmcs_clear_bits(unsigned long field, u32 mask)
637{
638 vmcs_writel(field, vmcs_readl(field) & ~mask);
639}
640
641static void vmcs_set_bits(unsigned long field, u32 mask)
642{
643 vmcs_writel(field, vmcs_readl(field) | mask);
644}
645
abd3f2d6
AK		 646static void update_exception_bitmap(struct kvm_vcpu *vcpu)
647{
648 u32 eb;
649
fd7373cc
JK		 650 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
651 (1u << NM_VECTOR) | (1u << DB_VECTOR);
652 if ((vcpu->guest_debug &
653 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
654 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
655 eb |= 1u << BP_VECTOR;
7ffd92c5 656 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 657 eb = ~0;
089d034e 658 if (enable_ept)
1439442c 659 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 660 if (vcpu->fpu_active)
661 eb &= ~(1u << NM_VECTOR);
abd3f2d6
AK		 662 vmcs_write32(EXCEPTION_BITMAP, eb);
663}
664
61d2ef2c
AK		 665static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
666{
667 unsigned i;
668 struct msr_autoload *m = &vmx->msr_autoload;
669
670 for (i = 0; i < m->nr; ++i)
671 if (m->guest[i].index == msr)
672 break;
673
674 if (i == m->nr)
675 return;
676 --m->nr;
677 m->guest[i] = m->guest[m->nr];
678 m->host[i] = m->host[m->nr];
679 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
680 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
681}
682
683static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
684 u64 guest_val, u64 host_val)
685{
686 unsigned i;
687 struct msr_autoload *m = &vmx->msr_autoload;
688
689 for (i = 0; i < m->nr; ++i)
690 if (m->guest[i].index == msr)
691 break;
692
693 if (i == m->nr) {
694 ++m->nr;
695 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
696 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
697 }
698
699 m->guest[i].index = msr;
700 m->guest[i].value = guest_val;
701 m->host[i].index = msr;
702 m->host[i].value = host_val;
703}
704
33ed6329
AK		 705static void reload_tss(void)
706{
33ed6329
AK		 707 /*
708 * VT restores TR but not its size. Useless.
709 */
d359192f 710 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 711 struct desc_struct *descs;
33ed6329 712
d359192f 713 descs = (void *)gdt->address;
33ed6329
AK		 714 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
715 load_TR_desc();
33ed6329
AK		 716}
717
92c0d900 718static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 719{
3a34a881 720 u64 guest_efer;
51c6cf66
AK		 721 u64 ignore_bits;
722
f6801dff 723 guest_efer = vmx->vcpu.arch.efer;
3a34a881 724
51c6cf66
AK		 725 /*
726 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
727 * outside long mode
728 */
729 ignore_bits = EFER_NX | EFER_SCE;
730#ifdef CONFIG_X86_64
731 ignore_bits |= EFER_LMA | EFER_LME;
732 /* SCE is meaningful only in long mode on Intel */
733 if (guest_efer & EFER_LMA)
734 ignore_bits &= ~(u64)EFER_SCE;
735#endif
51c6cf66
AK		 736 guest_efer &= ~ignore_bits;
737 guest_efer |= host_efer & ignore_bits;
26bb0981 738 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 739 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 740
741 clear_atomic_switch_msr(vmx, MSR_EFER);
742 /* On ept, can't emulate nx, and must switch nx atomically */
743 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
744 guest_efer = vmx->vcpu.arch.efer;
745 if (!(guest_efer & EFER_LMA))
746 guest_efer &= ~EFER_LME;
747 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
748 return false;
749 }
750
26bb0981 751 return true;
51c6cf66
AK		 752}
753
2d49ec72
GN		 754static unsigned long segment_base(u16 selector)
755{
d359192f 756 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 757 struct desc_struct *d;
758 unsigned long table_base;
759 unsigned long v;
760
761 if (!(selector & ~3))
762 return 0;
763
d359192f 764 table_base = gdt->address;
2d49ec72
GN		 765
766 if (selector & 4) { /* from ldt */
767 u16 ldt_selector = kvm_read_ldt();
768
769 if (!(ldt_selector & ~3))
770 return 0;
771
772 table_base = segment_base(ldt_selector);
773 }
774 d = (struct desc_struct *)(table_base + (selector & ~7));
775 v = get_desc_base(d);
776#ifdef CONFIG_X86_64
777 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
778 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
779#endif
780 return v;
781}
782
783static inline unsigned long kvm_read_tr_base(void)
784{
785 u16 tr;
786 asm("str %0" : "=g"(tr));
787 return segment_base(tr);
788}
789
04d2cc77 790static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 791{
04d2cc77 792 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 793 int i;
04d2cc77 794
a2fa3e9f 795 if (vmx->host_state.loaded)
33ed6329
AK		 796 return;
797
a2fa3e9f 798 vmx->host_state.loaded = 1;
33ed6329
AK		 799 /*
800 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
801 * allow segment selectors with cpl > 0 or ti == 1.
802 */
d6e88aec 803 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 804 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 805 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 806 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 807 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 808 vmx->host_state.fs_reload_needed = 0;
809 } else {
33ed6329 810 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 811 vmx->host_state.fs_reload_needed = 1;
33ed6329 812 }
9581d442 813 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 814 if (!(vmx->host_state.gs_sel & 7))
815 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 816 else {
817 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 818 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 819 }
820
821#ifdef CONFIG_X86_64
822 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
823 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
824#else
a2fa3e9f
GH		 825 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
826 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 827#endif
707c0874
AK		 828
829#ifdef CONFIG_X86_64
44ea2b17
AK		 830 if (is_long_mode(&vmx->vcpu)) {
831 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
832 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
833 }
707c0874 834#endif
26bb0981
AK		 835 for (i = 0; i < vmx->save_nmsrs; ++i)
836 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 837 vmx->guest_msrs[i].data,
838 vmx->guest_msrs[i].mask);
33ed6329
AK		 839}
840
a9b21b62 841static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 842{
a2fa3e9f 843 if (!vmx->host_state.loaded)
33ed6329
AK		 844 return;
845
e1beb1d3 846 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 847 vmx->host_state.loaded = 0;
152d3f2f 848 if (vmx->host_state.fs_reload_needed)
9581d442 849 loadsegment(fs, vmx->host_state.fs_sel);
152d3f2f 850 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 851 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 852#ifdef CONFIG_X86_64
9581d442
AK		 853 load_gs_index(vmx->host_state.gs_sel);
854 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
855#else
856 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 857#endif
33ed6329 858 }
152d3f2f 859 reload_tss();
44ea2b17
AK		 860#ifdef CONFIG_X86_64
861 if (is_long_mode(&vmx->vcpu)) {
862 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
863 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
864 }
865#endif
1c11e713
AK		 866 if (current_thread_info()->status & TS_USEDFPU)
867 clts();
3444d7da 868 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 869}
870
a9b21b62
AK		 871static void vmx_load_host_state(struct vcpu_vmx *vmx)
872{
873 preempt_disable();
874 __vmx_load_host_state(vmx);
875 preempt_enable();
876}
877
6aa8b732
AK		 878/*
879 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
880 * vcpu mutex is already taken.
881 */
15ad7146 882static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 883{
a2fa3e9f 884 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 885 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 886
4610c9cc
DX		 887 if (!vmm_exclusive)
888 kvm_cpu_vmxon(phys_addr);
889 else if (vcpu->cpu != cpu)
8b9cf98c 890 vcpu_clear(vmx);
6aa8b732 891
a2fa3e9f 892 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
a2fa3e9f 893 per_cpu(current_vmcs, cpu) = vmx->vmcs;
7725b894 894 vmcs_load(vmx->vmcs);
6aa8b732
AK		 895 }
896
897 if (vcpu->cpu != cpu) {
d359192f 898 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 899 unsigned long sysenter_esp;
900
a8eeb04a 901 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be
DX		 902 local_irq_disable();
903 list_add(&vmx->local_vcpus_link,
904 &per_cpu(vcpus_on_cpu, cpu));
905 local_irq_enable();
906
6aa8b732
AK		 907 /*
908 * Linux uses per-cpu TSS and GDT, so set these when switching
909 * processors.
910 */
d6e88aec 911 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 912 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 913
914 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
915 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
916 }
6aa8b732
AK		 917}
918
919static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
920{
a9b21b62 921 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 922 if (!vmm_exclusive) {
b923e62e 923 __vcpu_clear(to_vmx(vcpu));
4610c9cc
DX		 924 kvm_cpu_vmxoff();
925 }
6aa8b732
AK		 926}
927
5fd86fcf
AK		 928static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
929{
81231c69
AK		 930 ulong cr0;
931
5fd86fcf
AK		 932 if (vcpu->fpu_active)
933 return;
934 vcpu->fpu_active = 1;
81231c69
AK		 935 cr0 = vmcs_readl(GUEST_CR0);
936 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
937 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
938 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 939 update_exception_bitmap(vcpu);
edcafe3c
AK		 940 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
941 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 942}
943
edcafe3c
AK		 944static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
945
5fd86fcf
AK		 946static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
947{
edcafe3c 948 vmx_decache_cr0_guest_bits(vcpu);
81231c69 949 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 950 update_exception_bitmap(vcpu);
edcafe3c
AK		 951 vcpu->arch.cr0_guest_owned_bits = 0;
952 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
953 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 954}
955
6aa8b732
AK		 956static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
957{
78ac8b47 958 unsigned long rflags, save_rflags;
345dcaa8
AK		 959
960 rflags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 961 if (to_vmx(vcpu)->rmode.vm86_active) {
962 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
963 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
964 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
965 }
345dcaa8 966 return rflags;
6aa8b732
AK		 967}
968
969static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
970{
78ac8b47
AK		 971 if (to_vmx(vcpu)->rmode.vm86_active) {
972 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 973 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 974 }
6aa8b732
AK		 975 vmcs_writel(GUEST_RFLAGS, rflags);
976}
977
2809f5d2
GC		 978static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
979{
980 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
981 int ret = 0;
982
983 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 984 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 985 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 986 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 987
988 return ret & mask;
989}
990
991static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
992{
993 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
994 u32 interruptibility = interruptibility_old;
995
996 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
997
48005f64 998 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 999 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1000 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1001 interruptibility |= GUEST_INTR_STATE_STI;
1002
1003 if ((interruptibility != interruptibility_old))
1004 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1005}
1006
6aa8b732
AK		 1007static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1008{
1009 unsigned long rip;
6aa8b732 1010
5fdbf976 1011 rip = kvm_rip_read(vcpu);
6aa8b732 1012 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1013 kvm_rip_write(vcpu, rip);
6aa8b732 1014
2809f5d2
GC		 1015 /* skipping an emulated instruction also counts */
1016 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1017}
1018
298101da 1019static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1020 bool has_error_code, u32 error_code,
1021 bool reinject)
298101da 1022{
77ab6db0 1023 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1024 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1025
8ab2d2e2 1026 if (has_error_code) {
77ab6db0 1027 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1028 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1029 }
77ab6db0 1030
7ffd92c5 1031 if (vmx->rmode.vm86_active) {
77ab6db0
JK		 1032 vmx->rmode.irq.pending = true;
1033 vmx->rmode.irq.vector = nr;
1034 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 1035 if (kvm_exception_is_soft(nr))
1036 vmx->rmode.irq.rip +=
1037 vmx->vcpu.arch.event_exit_inst_len;
8ab2d2e2
JK		 1038 intr_info |= INTR_TYPE_SOFT_INTR;
1039 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
77ab6db0
JK		 1040 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1041 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
1042 return;
1043 }
1044
66fd3f7f
GN		 1045 if (kvm_exception_is_soft(nr)) {
1046 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1047 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1048 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1049 } else
1050 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1051
1052 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
298101da
AK		 1053}
1054
4e47c7a6
SY		 1055static bool vmx_rdtscp_supported(void)
1056{
1057 return cpu_has_vmx_rdtscp();
1058}
1059
a75beee6
ED		 1060/*
1061 * Swap MSR entry in host/guest MSR entry array.
1062 */
8b9cf98c 1063static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1064{
26bb0981 1065 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1066
1067 tmp = vmx->guest_msrs[to];
1068 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1069 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1070}
1071
e38aea3e
AK		 1072/*
1073 * Set up the vmcs to automatically save and restore system
1074 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1075 * mode, as fiddling with msrs is very expensive.
1076 */
8b9cf98c 1077static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1078{
26bb0981 1079 int save_nmsrs, index;
5897297b 1080 unsigned long *msr_bitmap;
e38aea3e 1081
33f9c505 1082 vmx_load_host_state(vmx);
a75beee6
ED		 1083 save_nmsrs = 0;
1084#ifdef CONFIG_X86_64
8b9cf98c 1085 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1086 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1087 if (index >= 0)
8b9cf98c
RR		 1088 move_msr_up(vmx, index, save_nmsrs++);
1089 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1090 if (index >= 0)
8b9cf98c
RR		 1091 move_msr_up(vmx, index, save_nmsrs++);
1092 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1093 if (index >= 0)
8b9cf98c 1094 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1095 index = __find_msr_index(vmx, MSR_TSC_AUX);
1096 if (index >= 0 && vmx->rdtscp_enabled)
1097 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1098 /*
8c06585d 1099 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1100 * if efer.sce is enabled.
1101 */
8c06585d 1102 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1103 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1104 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1105 }
1106#endif
92c0d900
AK		 1107 index = __find_msr_index(vmx, MSR_EFER);
1108 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1109 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1110
26bb0981 1111 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1112
1113 if (cpu_has_vmx_msr_bitmap()) {
1114 if (is_long_mode(&vmx->vcpu))
1115 msr_bitmap = vmx_msr_bitmap_longmode;
1116 else
1117 msr_bitmap = vmx_msr_bitmap_legacy;
1118
1119 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1120 }
e38aea3e
AK		 1121}
1122
6aa8b732
AK		 1123/*
1124 * reads and returns guest's timestamp counter "register"
1125 * guest_tsc = host_tsc + tsc_offset -- 21.3
1126 */
1127static u64 guest_read_tsc(void)
1128{
1129 u64 host_tsc, tsc_offset;
1130
1131 rdtscll(host_tsc);
1132 tsc_offset = vmcs_read64(TSC_OFFSET);
1133 return host_tsc + tsc_offset;
1134}
1135
1136/*
99e3e30a 1137 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1138 */
99e3e30a 1139static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1140{
f4e1b3c8 1141 vmcs_write64(TSC_OFFSET, offset);
6aa8b732
AK		 1142}
1143
e48672fa
ZA		 1144static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1145{
1146 u64 offset = vmcs_read64(TSC_OFFSET);
1147 vmcs_write64(TSC_OFFSET, offset + adjustment);
1148}
1149
6aa8b732
AK		 1150/*
1151 * Reads an msr value (of 'msr_index') into 'pdata'.
1152 * Returns 0 on success, non-0 otherwise.
1153 * Assumes vcpu_load() was already called.
1154 */
1155static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1156{
1157 u64 data;
26bb0981 1158 struct shared_msr_entry *msr;
6aa8b732
AK		 1159
1160 if (!pdata) {
1161 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1162 return -EINVAL;
1163 }
1164
1165 switch (msr_index) {
05b3e0c2 1166#ifdef CONFIG_X86_64
6aa8b732
AK		 1167 case MSR_FS_BASE:
1168 data = vmcs_readl(GUEST_FS_BASE);
1169 break;
1170 case MSR_GS_BASE:
1171 data = vmcs_readl(GUEST_GS_BASE);
1172 break;
44ea2b17
AK		 1173 case MSR_KERNEL_GS_BASE:
1174 vmx_load_host_state(to_vmx(vcpu));
1175 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1176 break;
26bb0981 1177#endif
6aa8b732 1178 case MSR_EFER:
3bab1f5d 1179 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 1180 case MSR_IA32_TSC:
6aa8b732
AK		 1181 data = guest_read_tsc();
1182 break;
1183 case MSR_IA32_SYSENTER_CS:
1184 data = vmcs_read32(GUEST_SYSENTER_CS);
1185 break;
1186 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1187 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1188 break;
1189 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1190 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1191 break;
4e47c7a6
SY		 1192 case MSR_TSC_AUX:
1193 if (!to_vmx(vcpu)->rdtscp_enabled)
1194 return 1;
1195 /* Otherwise falls through */
6aa8b732 1196 default:
26bb0981 1197 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 1198 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 1199 if (msr) {
542423b0 1200 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 1201 data = msr->data;
1202 break;
6aa8b732 1203 }
3bab1f5d 1204 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 1205 }
1206
1207 *pdata = data;
1208 return 0;
1209}
1210
1211/*
1212 * Writes msr value into into the appropriate "register".
1213 * Returns 0 on success, non-0 otherwise.
1214 * Assumes vcpu_load() was already called.
1215 */
1216static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1217{
a2fa3e9f 1218 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1219 struct shared_msr_entry *msr;
2cc51560
ED		 1220 int ret = 0;
1221
6aa8b732 1222 switch (msr_index) {
3bab1f5d 1223 case MSR_EFER:
a9b21b62 1224 vmx_load_host_state(vmx);
2cc51560 1225 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1226 break;
16175a79 1227#ifdef CONFIG_X86_64
6aa8b732
AK		 1228 case MSR_FS_BASE:
1229 vmcs_writel(GUEST_FS_BASE, data);
1230 break;
1231 case MSR_GS_BASE:
1232 vmcs_writel(GUEST_GS_BASE, data);
1233 break;
44ea2b17
AK		 1234 case MSR_KERNEL_GS_BASE:
1235 vmx_load_host_state(vmx);
1236 vmx->msr_guest_kernel_gs_base = data;
1237 break;
6aa8b732
AK		 1238#endif
1239 case MSR_IA32_SYSENTER_CS:
1240 vmcs_write32(GUEST_SYSENTER_CS, data);
1241 break;
1242 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1243 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1244 break;
1245 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1246 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1247 break;
af24a4e4 1248 case MSR_IA32_TSC:
99e3e30a 1249 kvm_write_tsc(vcpu, data);
6aa8b732 1250 break;
468d472f
SY		 1251 case MSR_IA32_CR_PAT:
1252 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1253 vmcs_write64(GUEST_IA32_PAT, data);
1254 vcpu->arch.pat = data;
1255 break;
1256 }
4e47c7a6
SY		 1257 ret = kvm_set_msr_common(vcpu, msr_index, data);
1258 break;
1259 case MSR_TSC_AUX:
1260 if (!vmx->rdtscp_enabled)
1261 return 1;
1262 /* Check reserved bit, higher 32 bits should be zero */
1263 if ((data >> 32) != 0)
1264 return 1;
1265 /* Otherwise falls through */
6aa8b732 1266 default:
8b9cf98c 1267 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 1268 if (msr) {
542423b0 1269 vmx_load_host_state(vmx);
3bab1f5d
AK		 1270 msr->data = data;
1271 break;
6aa8b732 1272 }
2cc51560 1273 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1274 }
1275
2cc51560 1276 return ret;
6aa8b732
AK		 1277}
1278
5fdbf976 1279static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1280{
5fdbf976
MT		 1281 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1282 switch (reg) {
1283 case VCPU_REGS_RSP:
1284 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1285 break;
1286 case VCPU_REGS_RIP:
1287 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1288 break;
6de4f3ad
AK		 1289 case VCPU_EXREG_PDPTR:
1290 if (enable_ept)
1291 ept_save_pdptrs(vcpu);
1292 break;
5fdbf976
MT		 1293 default:
1294 break;
1295 }
6aa8b732
AK		 1296}
1297
355be0b9 1298static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1299{
ae675ef0
JK		 1300 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1301 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1302 else
1303 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1304
abd3f2d6 1305 update_exception_bitmap(vcpu);
6aa8b732
AK		 1306}
1307
1308static __init int cpu_has_kvm_support(void)
1309{
6210e37b 1310 return cpu_has_vmx();
6aa8b732
AK		 1311}
1312
1313static __init int vmx_disabled_by_bios(void)
1314{
1315 u64 msr;
1316
1317 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659
SW		 1318 if (msr & FEATURE_CONTROL_LOCKED) {
1319 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1320 && tboot_enabled())
1321 return 1;
1322 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1323 && !tboot_enabled())
1324 return 1;
1325 }
1326
1327 return 0;
62b3ffb8 1328 /* locked but not enabled */
6aa8b732
AK		 1329}
1330
7725b894
DX		 1331static void kvm_cpu_vmxon(u64 addr)
1332{
1333 asm volatile (ASM_VMX_VMXON_RAX
1334 : : "a"(&addr), "m"(addr)
1335 : "memory", "cc");
1336}
1337
10474ae8 1338static int hardware_enable(void *garbage)
6aa8b732
AK		 1339{
1340 int cpu = raw_smp_processor_id();
1341 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 1342 u64 old, test_bits;
6aa8b732 1343
10474ae8
AG		 1344 if (read_cr4() & X86_CR4_VMXE)
1345 return -EBUSY;
1346
543e4243 1347 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1348 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 1349
1350 test_bits = FEATURE_CONTROL_LOCKED;
1351 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1352 if (tboot_enabled())
1353 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1354
1355 if ((old & test_bits) != test_bits) {
6aa8b732 1356 /* enable and lock */
cafd6659
SW		 1357 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1358 }
66aee91a 1359 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 1360
4610c9cc
DX		 1361 if (vmm_exclusive) {
1362 kvm_cpu_vmxon(phys_addr);
1363 ept_sync_global();
1364 }
10474ae8 1365
3444d7da
AK		 1366 store_gdt(&__get_cpu_var(host_gdt));
1367
10474ae8 1368 return 0;
6aa8b732
AK		 1369}
1370
543e4243
AK		 1371static void vmclear_local_vcpus(void)
1372{
1373 int cpu = raw_smp_processor_id();
1374 struct vcpu_vmx *vmx, *n;
1375
1376 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1377 local_vcpus_link)
1378 __vcpu_clear(vmx);
1379}
1380
710ff4a8
EH		 1381
1382/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1383 * tricks.
1384 */
1385static void kvm_cpu_vmxoff(void)
6aa8b732 1386{
4ecac3fd 1387 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 1388}
1389
710ff4a8
EH		 1390static void hardware_disable(void *garbage)
1391{
4610c9cc
DX		 1392 if (vmm_exclusive) {
1393 vmclear_local_vcpus();
1394 kvm_cpu_vmxoff();
1395 }
7725b894 1396 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 1397}
1398
1c3d14fe 1399static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1400 u32 msr, u32 *result)
1c3d14fe
YS		 1401{
1402 u32 vmx_msr_low, vmx_msr_high;
1403 u32 ctl = ctl_min | ctl_opt;
1404
1405 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1406
1407 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1408 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1409
1410 /* Ensure minimum (required) set of control bits are supported. */
1411 if (ctl_min & ~ctl)
002c7f7c 1412 return -EIO;
1c3d14fe
YS		 1413
1414 *result = ctl;
1415 return 0;
1416}
1417
002c7f7c 1418static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1419{
1420 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1421 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1422 u32 _pin_based_exec_control = 0;
1423 u32 _cpu_based_exec_control = 0;
f78e0e2e 1424 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1425 u32 _vmexit_control = 0;
1426 u32 _vmentry_control = 0;
1427
1428 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1429 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1430 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1431 &_pin_based_exec_control) < 0)
002c7f7c 1432 return -EIO;
1c3d14fe
YS		 1433
1434 min = CPU_BASED_HLT_EXITING |
1435#ifdef CONFIG_X86_64
1436 CPU_BASED_CR8_LOAD_EXITING |
1437 CPU_BASED_CR8_STORE_EXITING |
1438#endif
d56f546d
SY		 1439 CPU_BASED_CR3_LOAD_EXITING |
1440 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1441 CPU_BASED_USE_IO_BITMAPS |
1442 CPU_BASED_MOV_DR_EXITING |
a7052897 1443 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 1444 CPU_BASED_MWAIT_EXITING |
1445 CPU_BASED_MONITOR_EXITING |
a7052897 1446 CPU_BASED_INVLPG_EXITING;
f78e0e2e 1447 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1448 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1449 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1450 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1451 &_cpu_based_exec_control) < 0)
002c7f7c 1452 return -EIO;
6e5d865c
YS		 1453#ifdef CONFIG_X86_64
1454 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1455 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1456 ~CPU_BASED_CR8_STORE_EXITING;
1457#endif
f78e0e2e 1458 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1459 min2 = 0;
1460 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1461 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1462 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 1463 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 1464 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 1465 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1466 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 1467 if (adjust_vmx_controls(min2, opt2,
1468 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1469 &_cpu_based_2nd_exec_control) < 0)
1470 return -EIO;
1471 }
1472#ifndef CONFIG_X86_64
1473 if (!(_cpu_based_2nd_exec_control &
1474 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1475 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1476#endif
d56f546d 1477 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1478 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1479 enabled */
5fff7d27
GN		 1480 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1481 CPU_BASED_CR3_STORE_EXITING |
1482 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1483 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1484 vmx_capability.ept, vmx_capability.vpid);
1485 }
1c3d14fe
YS		 1486
1487 min = 0;
1488#ifdef CONFIG_X86_64
1489 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1490#endif
468d472f 1491 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1492 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1493 &_vmexit_control) < 0)
002c7f7c 1494 return -EIO;
1c3d14fe 1495
468d472f
SY		 1496 min = 0;
1497 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1498 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1499 &_vmentry_control) < 0)
002c7f7c 1500 return -EIO;
6aa8b732 1501
c68876fd 1502 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1503
1504 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1505 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1506 return -EIO;
1c3d14fe
YS		 1507
1508#ifdef CONFIG_X86_64
1509 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1510 if (vmx_msr_high & (1u<<16))
002c7f7c 1511 return -EIO;
1c3d14fe
YS		 1512#endif
1513
1514 /* Require Write-Back (WB) memory type for VMCS accesses. */
1515 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1516 return -EIO;
1c3d14fe 1517
002c7f7c
YS		 1518 vmcs_conf->size = vmx_msr_high & 0x1fff;
1519 vmcs_conf->order = get_order(vmcs_config.size);
1520 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1521
002c7f7c
YS		 1522 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1523 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1524 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1525 vmcs_conf->vmexit_ctrl = _vmexit_control;
1526 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe
YS		 1527
1528 return 0;
c68876fd 1529}
6aa8b732
AK		 1530
1531static struct vmcs *alloc_vmcs_cpu(int cpu)
1532{
1533 int node = cpu_to_node(cpu);
1534 struct page *pages;
1535 struct vmcs *vmcs;
1536
6484eb3e 1537 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1538 if (!pages)
1539 return NULL;
1540 vmcs = page_address(pages);
1c3d14fe
YS		 1541 memset(vmcs, 0, vmcs_config.size);
1542 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1543 return vmcs;
1544}
1545
1546static struct vmcs *alloc_vmcs(void)
1547{
d3b2c338 1548 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1549}
1550
1551static void free_vmcs(struct vmcs *vmcs)
1552{
1c3d14fe 1553 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1554}
1555
39959588 1556static void free_kvm_area(void)
6aa8b732
AK		 1557{
1558 int cpu;
1559
3230bb47 1560 for_each_possible_cpu(cpu) {
6aa8b732 1561 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 1562 per_cpu(vmxarea, cpu) = NULL;
1563 }
6aa8b732
AK		 1564}
1565
6aa8b732
AK		 1566static __init int alloc_kvm_area(void)
1567{
1568 int cpu;
1569
3230bb47 1570 for_each_possible_cpu(cpu) {
6aa8b732
AK		 1571 struct vmcs *vmcs;
1572
1573 vmcs = alloc_vmcs_cpu(cpu);
1574 if (!vmcs) {
1575 free_kvm_area();
1576 return -ENOMEM;
1577 }
1578
1579 per_cpu(vmxarea, cpu) = vmcs;
1580 }
1581 return 0;
1582}
1583
1584static __init int hardware_setup(void)
1585{
002c7f7c
YS		 1586 if (setup_vmcs_config(&vmcs_config) < 0)
1587 return -EIO;
50a37eb4
JR		 1588
1589 if (boot_cpu_has(X86_FEATURE_NX))
1590 kvm_enable_efer_bits(EFER_NX);
1591
93ba03c2
SY		 1592 if (!cpu_has_vmx_vpid())
1593 enable_vpid = 0;
1594
4bc9b982
SY		 1595 if (!cpu_has_vmx_ept() ||
1596 !cpu_has_vmx_ept_4levels()) {
93ba03c2 1597 enable_ept = 0;
3a624e29
NK		 1598 enable_unrestricted_guest = 0;
1599 }
1600
1601 if (!cpu_has_vmx_unrestricted_guest())
1602 enable_unrestricted_guest = 0;
93ba03c2
SY		 1603
1604 if (!cpu_has_vmx_flexpriority())
1605 flexpriority_enabled = 0;
1606
95ba8273
GN		 1607 if (!cpu_has_vmx_tpr_shadow())
1608 kvm_x86_ops->update_cr8_intercept = NULL;
1609
54dee993
MT		 1610 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1611 kvm_disable_largepages();
1612
4b8d54f9
ZE		 1613 if (!cpu_has_vmx_ple())
1614 ple_gap = 0;
1615
6aa8b732
AK		 1616 return alloc_kvm_area();
1617}
1618
1619static __exit void hardware_unsetup(void)
1620{
1621 free_kvm_area();
1622}
1623
6aa8b732
AK		 1624static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1625{
1626 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1627
6af11b9e 1628 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1629 vmcs_write16(sf->selector, save->selector);
1630 vmcs_writel(sf->base, save->base);
1631 vmcs_write32(sf->limit, save->limit);
1632 vmcs_write32(sf->ar_bytes, save->ar);
1633 } else {
1634 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1635 << AR_DPL_SHIFT;
1636 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1637 }
1638}
1639
1640static void enter_pmode(struct kvm_vcpu *vcpu)
1641{
1642 unsigned long flags;
a89a8fb9 1643 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1644
a89a8fb9 1645 vmx->emulation_required = 1;
7ffd92c5 1646 vmx->rmode.vm86_active = 0;
6aa8b732 1647
7ffd92c5
AK		 1648 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1649 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1650 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 1651
1652 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 1653 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1654 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 1655 vmcs_writel(GUEST_RFLAGS, flags);
1656
66aee91a
RR		 1657 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1658 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1659
1660 update_exception_bitmap(vcpu);
1661
a89a8fb9
MG		 1662 if (emulate_invalid_guest_state)
1663 return;
1664
7ffd92c5
AK		 1665 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1666 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1667 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1668 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732
AK		 1669
1670 vmcs_write16(GUEST_SS_SELECTOR, 0);
1671 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1672
1673 vmcs_write16(GUEST_CS_SELECTOR,
1674 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1675 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1676}
1677
d77c26fc 1678static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1679{
bfc6d222 1680 if (!kvm->arch.tss_addr) {
bc6678a3
MT		 1681 struct kvm_memslots *slots;
1682 gfn_t base_gfn;
1683
90d83dc3 1684 slots = kvm_memslots(kvm);
f495c6e5 1685 base_gfn = slots->memslots[0].base_gfn +
46a26bf5 1686 kvm->memslots->memslots[0].npages - 3;
cbc94022
IE		 1687 return base_gfn << PAGE_SHIFT;
1688 }
bfc6d222 1689 return kvm->arch.tss_addr;
6aa8b732
AK		 1690}
1691
1692static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1693{
1694 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1695
1696 save->selector = vmcs_read16(sf->selector);
1697 save->base = vmcs_readl(sf->base);
1698 save->limit = vmcs_read32(sf->limit);
1699 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32
JK		 1700 vmcs_write16(sf->selector, save->base >> 4);
1701 vmcs_write32(sf->base, save->base & 0xfffff);
6aa8b732
AK		 1702 vmcs_write32(sf->limit, 0xffff);
1703 vmcs_write32(sf->ar_bytes, 0xf3);
1704}
1705
1706static void enter_rmode(struct kvm_vcpu *vcpu)
1707{
1708 unsigned long flags;
a89a8fb9 1709 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1710
3a624e29
NK		 1711 if (enable_unrestricted_guest)
1712 return;
1713
a89a8fb9 1714 vmx->emulation_required = 1;
7ffd92c5 1715 vmx->rmode.vm86_active = 1;
6aa8b732 1716
7ffd92c5 1717 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1718 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1719
7ffd92c5 1720 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1721 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1722
7ffd92c5 1723 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1724 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1725
1726 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 1727 vmx->rmode.save_rflags = flags;
6aa8b732 1728
053de044 1729 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1730
1731 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1732 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1733 update_exception_bitmap(vcpu);
1734
a89a8fb9
MG		 1735 if (emulate_invalid_guest_state)
1736 goto continue_rmode;
1737
6aa8b732
AK		 1738 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1739 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1740 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1741
1742 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1743 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1744 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1745 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1746 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1747
7ffd92c5
AK		 1748 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1749 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1750 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1751 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 1752
a89a8fb9 1753continue_rmode:
8668a3c4 1754 kvm_mmu_reset_context(vcpu);
b7ebfb05 1755 init_rmode(vcpu->kvm);
6aa8b732
AK		 1756}
1757
401d10de
AS		 1758static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1759{
1760 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 1761 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1762
1763 if (!msr)
1764 return;
401d10de 1765
44ea2b17
AK		 1766 /*
1767 * Force kernel_gs_base reloading before EFER changes, as control
1768 * of this msr depends on is_long_mode().
1769 */
1770 vmx_load_host_state(to_vmx(vcpu));
f6801dff 1771 vcpu->arch.efer = efer;
401d10de
AS		 1772 if (efer & EFER_LMA) {
1773 vmcs_write32(VM_ENTRY_CONTROLS,
1774 vmcs_read32(VM_ENTRY_CONTROLS) |
1775 VM_ENTRY_IA32E_MODE);
1776 msr->data = efer;
1777 } else {
1778 vmcs_write32(VM_ENTRY_CONTROLS,
1779 vmcs_read32(VM_ENTRY_CONTROLS) &
1780 ~VM_ENTRY_IA32E_MODE);
1781
1782 msr->data = efer & ~EFER_LME;
1783 }
1784 setup_msrs(vmx);
1785}
1786
05b3e0c2 1787#ifdef CONFIG_X86_64
6aa8b732
AK		 1788
1789static void enter_lmode(struct kvm_vcpu *vcpu)
1790{
1791 u32 guest_tr_ar;
1792
1793 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1794 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1795 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1796 __func__);
6aa8b732
AK		 1797 vmcs_write32(GUEST_TR_AR_BYTES,
1798 (guest_tr_ar & ~AR_TYPE_MASK)
1799 | AR_TYPE_BUSY_64_TSS);
1800 }
da38f438 1801 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 1802}
1803
1804static void exit_lmode(struct kvm_vcpu *vcpu)
1805{
6aa8b732
AK		 1806 vmcs_write32(VM_ENTRY_CONTROLS,
1807 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1808 & ~VM_ENTRY_IA32E_MODE);
da38f438 1809 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 1810}
1811
1812#endif
1813
2384d2b3
SY		 1814static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1815{
b9d762fa 1816 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 1817 if (enable_ept) {
1818 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
1819 return;
4e1096d2 1820 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 1821 }
2384d2b3
SY		 1822}
1823
e8467fda
AK		 1824static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1825{
1826 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1827
1828 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1829 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1830}
1831
25c4c276 1832static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1833{
fc78f519
AK		 1834 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1835
1836 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1837 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 1838}
1839
1439442c
SY		 1840static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1841{
6de4f3ad
AK		 1842 if (!test_bit(VCPU_EXREG_PDPTR,
1843 (unsigned long *)&vcpu->arch.regs_dirty))
1844 return;
1845
1439442c 1846 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 1847 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
1848 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
1849 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
1850 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 1851 }
1852}
1853
8f5d549f
AK		 1854static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1855{
1856 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 1857 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1858 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1859 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1860 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 1861 }
6de4f3ad
AK		 1862
1863 __set_bit(VCPU_EXREG_PDPTR,
1864 (unsigned long *)&vcpu->arch.regs_avail);
1865 __set_bit(VCPU_EXREG_PDPTR,
1866 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 1867}
1868
1439442c
SY		 1869static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1870
1871static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1872 unsigned long cr0,
1873 struct kvm_vcpu *vcpu)
1874{
1875 if (!(cr0 & X86_CR0_PG)) {
1876 /* From paging/starting to nonpaging */
1877 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1878 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1879 (CPU_BASED_CR3_LOAD_EXITING |
1880 CPU_BASED_CR3_STORE_EXITING));
1881 vcpu->arch.cr0 = cr0;
fc78f519 1882 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 1883 } else if (!is_paging(vcpu)) {
1884 /* From nonpaging to paging */
1885 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1886 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1887 ~(CPU_BASED_CR3_LOAD_EXITING |
1888 CPU_BASED_CR3_STORE_EXITING));
1889 vcpu->arch.cr0 = cr0;
fc78f519 1890 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 1891 }
95eb84a7
SY		 1892
1893 if (!(cr0 & X86_CR0_WP))
1894 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 1895}
1896
6aa8b732
AK		 1897static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1898{
7ffd92c5 1899 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 1900 unsigned long hw_cr0;
1901
1902 if (enable_unrestricted_guest)
1903 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1904 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1905 else
1906 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 1907
7ffd92c5 1908 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 1909 enter_pmode(vcpu);
1910
7ffd92c5 1911 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 1912 enter_rmode(vcpu);
1913
05b3e0c2 1914#ifdef CONFIG_X86_64
f6801dff 1915 if (vcpu->arch.efer & EFER_LME) {
707d92fa 1916 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 1917 enter_lmode(vcpu);
707d92fa 1918 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 1919 exit_lmode(vcpu);
1920 }
1921#endif
1922
089d034e 1923 if (enable_ept)
1439442c
SY		 1924 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1925
02daab21 1926 if (!vcpu->fpu_active)
81231c69 1927 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 1928
6aa8b732 1929 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 1930 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 1931 vcpu->arch.cr0 = cr0;
6aa8b732
AK		 1932}
1933
1439442c
SY		 1934static u64 construct_eptp(unsigned long root_hpa)
1935{
1936 u64 eptp;
1937
1938 /* TODO write the value reading from MSR */
1939 eptp = VMX_EPT_DEFAULT_MT |
1940 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1941 eptp |= (root_hpa & PAGE_MASK);
1942
1943 return eptp;
1944}
1945
6aa8b732
AK		 1946static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1947{
1439442c
SY		 1948 unsigned long guest_cr3;
1949 u64 eptp;
1950
1951 guest_cr3 = cr3;
089d034e 1952 if (enable_ept) {
1439442c
SY		 1953 eptp = construct_eptp(cr3);
1954 vmcs_write64(EPT_POINTER, eptp);
1439442c 1955 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
b927a3ce 1956 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 1957 ept_load_pdptrs(vcpu);
1439442c
SY		 1958 }
1959
2384d2b3 1960 vmx_flush_tlb(vcpu);
1439442c 1961 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 1962}
1963
1964static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1965{
7ffd92c5 1966 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 1967 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1968
ad312c7c 1969 vcpu->arch.cr4 = cr4;
bc23008b
AK		 1970 if (enable_ept) {
1971 if (!is_paging(vcpu)) {
1972 hw_cr4 &= ~X86_CR4_PAE;
1973 hw_cr4 |= X86_CR4_PSE;
1974 } else if (!(cr4 & X86_CR4_PAE)) {
1975 hw_cr4 &= ~X86_CR4_PAE;
1976 }
1977 }
1439442c
SY		 1978
1979 vmcs_writel(CR4_READ_SHADOW, cr4);
1980 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 1981}
1982
6aa8b732
AK		 1983static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1984{
1985 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1986
1987 return vmcs_readl(sf->base);
1988}
1989
1990static void vmx_get_segment(struct kvm_vcpu *vcpu,
1991 struct kvm_segment *var, int seg)
1992{
1993 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1994 u32 ar;
1995
1996 var->base = vmcs_readl(sf->base);
1997 var->limit = vmcs_read32(sf->limit);
1998 var->selector = vmcs_read16(sf->selector);
1999 ar = vmcs_read32(sf->ar_bytes);
9fd4a3b7 2000 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 2001 ar = 0;
2002 var->type = ar & 15;
2003 var->s = (ar >> 4) & 1;
2004 var->dpl = (ar >> 5) & 3;
2005 var->present = (ar >> 7) & 1;
2006 var->avl = (ar >> 12) & 1;
2007 var->l = (ar >> 13) & 1;
2008 var->db = (ar >> 14) & 1;
2009 var->g = (ar >> 15) & 1;
2010 var->unusable = (ar >> 16) & 1;
2011}
2012
2e4d2653
IE		 2013static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2014{
3eeb3288 2015 if (!is_protmode(vcpu))
2e4d2653
IE		 2016 return 0;
2017
2018 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
2019 return 3;
2020
eab4b8aa 2021 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2e4d2653
IE		 2022}
2023
653e3108 2024static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 2025{
6aa8b732
AK		 2026 u32 ar;
2027
653e3108 2028 if (var->unusable)
6aa8b732
AK		 2029 ar = 1 << 16;
2030 else {
2031 ar = var->type & 15;
2032 ar |= (var->s & 1) << 4;
2033 ar |= (var->dpl & 3) << 5;
2034 ar |= (var->present & 1) << 7;
2035 ar |= (var->avl & 1) << 12;
2036 ar |= (var->l & 1) << 13;
2037 ar |= (var->db & 1) << 14;
2038 ar |= (var->g & 1) << 15;
2039 }
f7fbf1fd
UL		 2040 if (ar == 0) /* a 0 value means unusable */
2041 ar = AR_UNUSABLE_MASK;
653e3108
AK		 2042
2043 return ar;
2044}
2045
2046static void vmx_set_segment(struct kvm_vcpu *vcpu,
2047 struct kvm_segment *var, int seg)
2048{
7ffd92c5 2049 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 2050 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2051 u32 ar;
2052
7ffd92c5
AK		 2053 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2054 vmx->rmode.tr.selector = var->selector;
2055 vmx->rmode.tr.base = var->base;
2056 vmx->rmode.tr.limit = var->limit;
2057 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 2058 return;
2059 }
2060 vmcs_writel(sf->base, var->base);
2061 vmcs_write32(sf->limit, var->limit);
2062 vmcs_write16(sf->selector, var->selector);
7ffd92c5 2063 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 2064 /*
2065 * Hack real-mode segments into vm86 compatibility.
2066 */
2067 if (var->base == 0xffff0000 && var->selector == 0xf000)
2068 vmcs_writel(sf->base, 0xf0000);
2069 ar = 0xf3;
2070 } else
2071 ar = vmx_segment_access_rights(var);
3a624e29
NK		 2072
2073 /*
2074 * Fix the "Accessed" bit in AR field of segment registers for older
2075 * qemu binaries.
2076 * IA32 arch specifies that at the time of processor reset the
2077 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2078 * is setting it to 0 in the usedland code. This causes invalid guest
2079 * state vmexit when "unrestricted guest" mode is turned on.
2080 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2081 * tree. Newer qemu binaries with that qemu fix would not need this
2082 * kvm hack.
2083 */
2084 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2085 ar |= 0x1; /* Accessed */
2086
6aa8b732
AK		 2087 vmcs_write32(sf->ar_bytes, ar);
2088}
2089
6aa8b732
AK		 2090static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2091{
2092 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2093
2094 *db = (ar >> 14) & 1;
2095 *l = (ar >> 13) & 1;
2096}
2097
89a27f4d 2098static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2099{
89a27f4d
GN		 2100 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2101 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 2102}
2103
89a27f4d 2104static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2105{
89a27f4d
GN		 2106 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2107 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 2108}
2109
89a27f4d 2110static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2111{
89a27f4d
GN		 2112 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2113 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 2114}
2115
89a27f4d 2116static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2117{
89a27f4d
GN		 2118 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2119 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 2120}
2121
648dfaa7
MG		 2122static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2123{
2124 struct kvm_segment var;
2125 u32 ar;
2126
2127 vmx_get_segment(vcpu, &var, seg);
2128 ar = vmx_segment_access_rights(&var);
2129
2130 if (var.base != (var.selector << 4))
2131 return false;
2132 if (var.limit != 0xffff)
2133 return false;
2134 if (ar != 0xf3)
2135 return false;
2136
2137 return true;
2138}
2139
2140static bool code_segment_valid(struct kvm_vcpu *vcpu)
2141{
2142 struct kvm_segment cs;
2143 unsigned int cs_rpl;
2144
2145 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2146 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2147
1872a3f4
AK		 2148 if (cs.unusable)
2149 return false;
648dfaa7
MG		 2150 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2151 return false;
2152 if (!cs.s)
2153 return false;
1872a3f4 2154 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 2155 if (cs.dpl > cs_rpl)
2156 return false;
1872a3f4 2157 } else {
648dfaa7
MG		 2158 if (cs.dpl != cs_rpl)
2159 return false;
2160 }
2161 if (!cs.present)
2162 return false;
2163
2164 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2165 return true;
2166}
2167
2168static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2169{
2170 struct kvm_segment ss;
2171 unsigned int ss_rpl;
2172
2173 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2174 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2175
1872a3f4
AK		 2176 if (ss.unusable)
2177 return true;
2178 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 2179 return false;
2180 if (!ss.s)
2181 return false;
2182 if (ss.dpl != ss_rpl) /* DPL != RPL */
2183 return false;
2184 if (!ss.present)
2185 return false;
2186
2187 return true;
2188}
2189
2190static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2191{
2192 struct kvm_segment var;
2193 unsigned int rpl;
2194
2195 vmx_get_segment(vcpu, &var, seg);
2196 rpl = var.selector & SELECTOR_RPL_MASK;
2197
1872a3f4
AK		 2198 if (var.unusable)
2199 return true;
648dfaa7
MG		 2200 if (!var.s)
2201 return false;
2202 if (!var.present)
2203 return false;
2204 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2205 if (var.dpl < rpl) /* DPL < RPL */
2206 return false;
2207 }
2208
2209 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2210 * rights flags
2211 */
2212 return true;
2213}
2214
2215static bool tr_valid(struct kvm_vcpu *vcpu)
2216{
2217 struct kvm_segment tr;
2218
2219 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2220
1872a3f4
AK		 2221 if (tr.unusable)
2222 return false;
648dfaa7
MG		 2223 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2224 return false;
1872a3f4 2225 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 2226 return false;
2227 if (!tr.present)
2228 return false;
2229
2230 return true;
2231}
2232
2233static bool ldtr_valid(struct kvm_vcpu *vcpu)
2234{
2235 struct kvm_segment ldtr;
2236
2237 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2238
1872a3f4
AK		 2239 if (ldtr.unusable)
2240 return true;
648dfaa7
MG		 2241 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2242 return false;
2243 if (ldtr.type != 2)
2244 return false;
2245 if (!ldtr.present)
2246 return false;
2247
2248 return true;
2249}
2250
2251static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2252{
2253 struct kvm_segment cs, ss;
2254
2255 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2256 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2257
2258 return ((cs.selector & SELECTOR_RPL_MASK) ==
2259 (ss.selector & SELECTOR_RPL_MASK));
2260}
2261
2262/*
2263 * Check if guest state is valid. Returns true if valid, false if
2264 * not.
2265 * We assume that registers are always usable
2266 */
2267static bool guest_state_valid(struct kvm_vcpu *vcpu)
2268{
2269 /* real mode guest state checks */
3eeb3288 2270 if (!is_protmode(vcpu)) {
648dfaa7
MG		 2271 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2272 return false;
2273 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2274 return false;
2275 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2276 return false;
2277 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2278 return false;
2279 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2280 return false;
2281 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2282 return false;
2283 } else {
2284 /* protected mode guest state checks */
2285 if (!cs_ss_rpl_check(vcpu))
2286 return false;
2287 if (!code_segment_valid(vcpu))
2288 return false;
2289 if (!stack_segment_valid(vcpu))
2290 return false;
2291 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2292 return false;
2293 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2294 return false;
2295 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2296 return false;
2297 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2298 return false;
2299 if (!tr_valid(vcpu))
2300 return false;
2301 if (!ldtr_valid(vcpu))
2302 return false;
2303 }
2304 /* TODO:
2305 * - Add checks on RIP
2306 * - Add checks on RFLAGS
2307 */
2308
2309 return true;
2310}
2311
d77c26fc 2312static int init_rmode_tss(struct kvm *kvm)
6aa8b732 2313{
6aa8b732 2314 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde 2315 u16 data = 0;
10589a46 2316 int ret = 0;
195aefde 2317 int r;
6aa8b732 2318
195aefde
IE		 2319 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2320 if (r < 0)
10589a46 2321 goto out;
195aefde 2322 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 2323 r = kvm_write_guest_page(kvm, fn++, &data,
2324 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 2325 if (r < 0)
10589a46 2326 goto out;
195aefde
IE		 2327 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2328 if (r < 0)
10589a46 2329 goto out;
195aefde
IE		 2330 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2331 if (r < 0)
10589a46 2332 goto out;
195aefde 2333 data = ~0;
10589a46
MT		 2334 r = kvm_write_guest_page(kvm, fn, &data,
2335 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2336 sizeof(u8));
195aefde 2337 if (r < 0)
10589a46
MT		 2338 goto out;
2339
2340 ret = 1;
2341out:
10589a46 2342 return ret;
6aa8b732
AK		 2343}
2344
b7ebfb05
SY		 2345static int init_rmode_identity_map(struct kvm *kvm)
2346{
2347 int i, r, ret;
2348 pfn_t identity_map_pfn;
2349 u32 tmp;
2350
089d034e 2351 if (!enable_ept)
b7ebfb05
SY		 2352 return 1;
2353 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2354 printk(KERN_ERR "EPT: identity-mapping pagetable "
2355 "haven't been allocated!\n");
2356 return 0;
2357 }
2358 if (likely(kvm->arch.ept_identity_pagetable_done))
2359 return 1;
2360 ret = 0;
b927a3ce 2361 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
b7ebfb05
SY		 2362 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2363 if (r < 0)
2364 goto out;
2365 /* Set up identity-mapping pagetable for EPT in real mode */
2366 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2367 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2368 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2369 r = kvm_write_guest_page(kvm, identity_map_pfn,
2370 &tmp, i * sizeof(tmp), sizeof(tmp));
2371 if (r < 0)
2372 goto out;
2373 }
2374 kvm->arch.ept_identity_pagetable_done = true;
2375 ret = 1;
2376out:
2377 return ret;
2378}
2379
6aa8b732
AK		 2380static void seg_setup(int seg)
2381{
2382 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 2383 unsigned int ar;
6aa8b732
AK		 2384
2385 vmcs_write16(sf->selector, 0);
2386 vmcs_writel(sf->base, 0);
2387 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 2388 if (enable_unrestricted_guest) {
2389 ar = 0x93;
2390 if (seg == VCPU_SREG_CS)
2391 ar |= 0x08; /* code segment */
2392 } else
2393 ar = 0xf3;
2394
2395 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 2396}
2397
f78e0e2e
SY		 2398static int alloc_apic_access_page(struct kvm *kvm)
2399{
2400 struct kvm_userspace_memory_region kvm_userspace_mem;
2401 int r = 0;
2402
79fac95e 2403 mutex_lock(&kvm->slots_lock);
bfc6d222 2404 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2405 goto out;
2406 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2407 kvm_userspace_mem.flags = 0;
2408 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2409 kvm_userspace_mem.memory_size = PAGE_SIZE;
2410 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2411 if (r)
2412 goto out;
72dc67a6 2413
bfc6d222 2414 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2415out:
79fac95e 2416 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 2417 return r;
2418}
2419
b7ebfb05
SY		 2420static int alloc_identity_pagetable(struct kvm *kvm)
2421{
2422 struct kvm_userspace_memory_region kvm_userspace_mem;
2423 int r = 0;
2424
79fac95e 2425 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 2426 if (kvm->arch.ept_identity_pagetable)
2427 goto out;
2428 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2429 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 2430 kvm_userspace_mem.guest_phys_addr =
2431 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 2432 kvm_userspace_mem.memory_size = PAGE_SIZE;
2433 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2434 if (r)
2435 goto out;
2436
b7ebfb05 2437 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 2438 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 2439out:
79fac95e 2440 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 2441 return r;
2442}
2443
2384d2b3
SY		 2444static void allocate_vpid(struct vcpu_vmx *vmx)
2445{
2446 int vpid;
2447
2448 vmx->vpid = 0;
919818ab 2449 if (!enable_vpid)
2384d2b3
SY		 2450 return;
2451 spin_lock(&vmx_vpid_lock);
2452 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2453 if (vpid < VMX_NR_VPIDS) {
2454 vmx->vpid = vpid;
2455 __set_bit(vpid, vmx_vpid_bitmap);
2456 }
2457 spin_unlock(&vmx_vpid_lock);
2458}
2459
cdbecfc3
LJ		 2460static void free_vpid(struct vcpu_vmx *vmx)
2461{
2462 if (!enable_vpid)
2463 return;
2464 spin_lock(&vmx_vpid_lock);
2465 if (vmx->vpid != 0)
2466 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2467 spin_unlock(&vmx_vpid_lock);
2468}
2469
5897297b 2470static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2471{
3e7c73e9 2472 int f = sizeof(unsigned long);
25c5f225
SY		 2473
2474 if (!cpu_has_vmx_msr_bitmap())
2475 return;
2476
2477 /*
2478 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2479 * have the write-low and read-high bitmap offsets the wrong way round.
2480 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2481 */
25c5f225 2482 if (msr <= 0x1fff) {
3e7c73e9
AK		 2483 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2484 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2485 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2486 msr &= 0x1fff;
3e7c73e9
AK		 2487 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2488 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2489 }
25c5f225
SY		 2490}
2491
5897297b
AK		 2492static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2493{
2494 if (!longmode_only)
2495 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2496 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2497}
2498
6aa8b732
AK		 2499/*
2500 * Sets up the vmcs for emulated real mode.
2501 */
8b9cf98c 2502static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2503{
468d472f 2504 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2505 u32 junk;
f4e1b3c8 2506 u64 host_pat;
6aa8b732 2507 unsigned long a;
89a27f4d 2508 struct desc_ptr dt;
6aa8b732 2509 int i;
cd2276a7 2510 unsigned long kvm_vmx_return;
6e5d865c 2511 u32 exec_control;
6aa8b732 2512
6aa8b732 2513 /* I/O */
3e7c73e9
AK		 2514 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2515 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2516
25c5f225 2517 if (cpu_has_vmx_msr_bitmap())
5897297b 2518 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2519
6aa8b732
AK		 2520 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2521
6aa8b732 2522 /* Control */
1c3d14fe
YS		 2523 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2524 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2525
2526 exec_control = vmcs_config.cpu_based_exec_ctrl;
2527 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2528 exec_control &= ~CPU_BASED_TPR_SHADOW;
2529#ifdef CONFIG_X86_64
2530 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2531 CPU_BASED_CR8_LOAD_EXITING;
2532#endif
2533 }
089d034e 2534 if (!enable_ept)
d56f546d 2535 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2536 CPU_BASED_CR3_LOAD_EXITING |
2537 CPU_BASED_INVLPG_EXITING;
6e5d865c 2538 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2539
83ff3b9d
SY		 2540 if (cpu_has_secondary_exec_ctrls()) {
2541 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2542 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2543 exec_control &=
2544 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2545 if (vmx->vpid == 0)
2546 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
046d8710 2547 if (!enable_ept) {
d56f546d 2548 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
046d8710
SY		 2549 enable_unrestricted_guest = 0;
2550 }
3a624e29
NK		 2551 if (!enable_unrestricted_guest)
2552 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4b8d54f9
ZE		 2553 if (!ple_gap)
2554 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
83ff3b9d
SY		 2555 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2556 }
f78e0e2e 2557
4b8d54f9
ZE		 2558 if (ple_gap) {
2559 vmcs_write32(PLE_GAP, ple_gap);
2560 vmcs_write32(PLE_WINDOW, ple_window);
2561 }
2562
c7addb90
AK		 2563 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2564 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2565 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2566
1c11e713 2567 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
6aa8b732
AK		 2568 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2569 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2570
2571 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2572 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2573 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
9581d442
AK		 2574 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
2575 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
6aa8b732 2576 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2577#ifdef CONFIG_X86_64
6aa8b732
AK		 2578 rdmsrl(MSR_FS_BASE, a);
2579 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2580 rdmsrl(MSR_GS_BASE, a);
2581 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2582#else
2583 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2584 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2585#endif
2586
2587 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2588
ec68798c 2589 native_store_idt(&dt);
89a27f4d 2590 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
6aa8b732 2591
d77c26fc 2592 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2593 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2594 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2595 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 2596 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 2597 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 2598 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732
AK		 2599
2600 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2601 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2602 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2603 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2604 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2605 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2606
468d472f
SY		 2607 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2608 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2609 host_pat = msr_low | ((u64) msr_high << 32);
2610 vmcs_write64(HOST_IA32_PAT, host_pat);
2611 }
2612 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2613 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2614 host_pat = msr_low | ((u64) msr_high << 32);
2615 /* Write the default value follow host pat */
2616 vmcs_write64(GUEST_IA32_PAT, host_pat);
2617 /* Keep arch.pat sync with GUEST_IA32_PAT */
2618 vmx->vcpu.arch.pat = host_pat;
2619 }
2620
6aa8b732
AK		 2621 for (i = 0; i < NR_VMX_MSR; ++i) {
2622 u32 index = vmx_msr_index[i];
2623 u32 data_low, data_high;
a2fa3e9f 2624 int j = vmx->nmsrs;
6aa8b732
AK		 2625
2626 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2627 continue;
432bd6cb
AK		 2628 if (wrmsr_safe(index, data_low, data_high) < 0)
2629 continue;
26bb0981
AK		 2630 vmx->guest_msrs[j].index = i;
2631 vmx->guest_msrs[j].data = 0;
d5696725 2632 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 2633 ++vmx->nmsrs;
6aa8b732 2634 }
6aa8b732 2635
1c3d14fe 2636 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2637
2638 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2639 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2640
e00c8cf2 2641 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4c38609a 2642 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
ce03e4f2
AK		 2643 if (enable_ept)
2644 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4c38609a 2645 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
e00c8cf2 2646
99e3e30a 2647 kvm_write_tsc(&vmx->vcpu, 0);
f78e0e2e 2648
e00c8cf2
AK		 2649 return 0;
2650}
2651
b7ebfb05
SY		 2652static int init_rmode(struct kvm *kvm)
2653{
4b9d3a04
XG		 2654 int idx, ret = 0;
2655
2656 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05 2657 if (!init_rmode_tss(kvm))
4b9d3a04 2658 goto exit;
b7ebfb05 2659 if (!init_rmode_identity_map(kvm))
4b9d3a04
XG		 2660 goto exit;
2661
2662 ret = 1;
2663exit:
2664 srcu_read_unlock(&kvm->srcu, idx);
2665 return ret;
b7ebfb05
SY		 2666}
2667
e00c8cf2
AK		 2668static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2669{
2670 struct vcpu_vmx *vmx = to_vmx(vcpu);
2671 u64 msr;
4b9d3a04 2672 int ret;
e00c8cf2 2673
5fdbf976 2674 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
b7ebfb05 2675 if (!init_rmode(vmx->vcpu.kvm)) {
e00c8cf2
AK		 2676 ret = -ENOMEM;
2677 goto out;
2678 }
2679
7ffd92c5 2680 vmx->rmode.vm86_active = 0;
e00c8cf2 2681
3b86cd99
JK		 2682 vmx->soft_vnmi_blocked = 0;
2683
ad312c7c 2684 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2685 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 2686 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 2687 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 2688 msr |= MSR_IA32_APICBASE_BSP;
2689 kvm_set_apic_base(&vmx->vcpu, msr);
2690
10ab25cd
JK		 2691 ret = fx_init(&vmx->vcpu);
2692 if (ret != 0)
2693 goto out;
e00c8cf2 2694
5706be0d 2695 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2696 /*
2697 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2698 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2699 */
c5af89b6 2700 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 2701 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2702 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2703 } else {
ad312c7c
ZX		 2704 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2705 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2706 }
e00c8cf2
AK		 2707
2708 seg_setup(VCPU_SREG_DS);
2709 seg_setup(VCPU_SREG_ES);
2710 seg_setup(VCPU_SREG_FS);
2711 seg_setup(VCPU_SREG_GS);
2712 seg_setup(VCPU_SREG_SS);
2713
2714 vmcs_write16(GUEST_TR_SELECTOR, 0);
2715 vmcs_writel(GUEST_TR_BASE, 0);
2716 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2717 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2718
2719 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2720 vmcs_writel(GUEST_LDTR_BASE, 0);
2721 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2722 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2723
2724 vmcs_write32(GUEST_SYSENTER_CS, 0);
2725 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2726 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2727
2728 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 2729 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 2730 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2731 else
5fdbf976
MT		 2732 kvm_rip_write(vcpu, 0);
2733 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2734
e00c8cf2
AK		 2735 vmcs_writel(GUEST_DR7, 0x400);
2736
2737 vmcs_writel(GUEST_GDTR_BASE, 0);
2738 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2739
2740 vmcs_writel(GUEST_IDTR_BASE, 0);
2741 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2742
2743 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2744 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2745 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2746
e00c8cf2
AK		 2747 /* Special registers */
2748 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2749
2750 setup_msrs(vmx);
2751
6aa8b732
AK		 2752 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2753
f78e0e2e
SY		 2754 if (cpu_has_vmx_tpr_shadow()) {
2755 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2756 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2757 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
ad312c7c 2758 page_to_phys(vmx->vcpu.arch.apic->regs_page));
f78e0e2e
SY		 2759 vmcs_write32(TPR_THRESHOLD, 0);
2760 }
2761
2762 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2763 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2764 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2765
2384d2b3
SY		 2766 if (vmx->vpid != 0)
2767 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2768
fa40052c 2769 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 2770 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 2771 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2772 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2773 vmx_fpu_activate(&vmx->vcpu);
2774 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2775
b9d762fa 2776 vpid_sync_context(vmx);
2384d2b3 2777
3200f405 2778 ret = 0;
6aa8b732 2779
a89a8fb9
MG		 2780 /* HACK: Don't enable emulation on guest boot/reset */
2781 vmx->emulation_required = 0;
2782
6aa8b732
AK		 2783out:
2784 return ret;
2785}
2786
3b86cd99
JK		 2787static void enable_irq_window(struct kvm_vcpu *vcpu)
2788{
2789 u32 cpu_based_vm_exec_control;
2790
2791 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2792 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2793 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2794}
2795
2796static void enable_nmi_window(struct kvm_vcpu *vcpu)
2797{
2798 u32 cpu_based_vm_exec_control;
2799
2800 if (!cpu_has_virtual_nmis()) {
2801 enable_irq_window(vcpu);
2802 return;
2803 }
2804
2805 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2806 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2807 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2808}
2809
66fd3f7f 2810static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 2811{
9c8cba37 2812 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 2813 uint32_t intr;
2814 int irq = vcpu->arch.interrupt.nr;
9c8cba37 2815
229456fc 2816 trace_kvm_inj_virq(irq);
2714d1d3 2817
fa89a817 2818 ++vcpu->stat.irq_injections;
7ffd92c5 2819 if (vmx->rmode.vm86_active) {
9c8cba37
AK		 2820 vmx->rmode.irq.pending = true;
2821 vmx->rmode.irq.vector = irq;
5fdbf976 2822 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
ae0bb3e0
GN		 2823 if (vcpu->arch.interrupt.soft)
2824 vmx->rmode.irq.rip +=
2825 vmx->vcpu.arch.event_exit_inst_len;
9c5623e3
AK		 2826 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2827 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2828 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
5fdbf976 2829 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
85f455f7
ED		 2830 return;
2831 }
66fd3f7f
GN		 2832 intr = irq | INTR_INFO_VALID_MASK;
2833 if (vcpu->arch.interrupt.soft) {
2834 intr |= INTR_TYPE_SOFT_INTR;
2835 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2836 vmx->vcpu.arch.event_exit_inst_len);
2837 } else
2838 intr |= INTR_TYPE_EXT_INTR;
2839 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
85f455f7
ED		 2840}
2841
f08864b4
SY		 2842static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2843{
66a5a347
JK		 2844 struct vcpu_vmx *vmx = to_vmx(vcpu);
2845
3b86cd99
JK		 2846 if (!cpu_has_virtual_nmis()) {
2847 /*
2848 * Tracking the NMI-blocked state in software is built upon
2849 * finding the next open IRQ window. This, in turn, depends on
2850 * well-behaving guests: They have to keep IRQs disabled at
2851 * least as long as the NMI handler runs. Otherwise we may
2852 * cause NMI nesting, maybe breaking the guest. But as this is
2853 * highly unlikely, we can live with the residual risk.
2854 */
2855 vmx->soft_vnmi_blocked = 1;
2856 vmx->vnmi_blocked_time = 0;
2857 }
2858
487b391d 2859 ++vcpu->stat.nmi_injections;
7ffd92c5 2860 if (vmx->rmode.vm86_active) {
66a5a347
JK		 2861 vmx->rmode.irq.pending = true;
2862 vmx->rmode.irq.vector = NMI_VECTOR;
2863 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2864 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2865 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2866 INTR_INFO_VALID_MASK);
2867 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2868 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2869 return;
2870 }
f08864b4
SY		 2871 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2872 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
f08864b4
SY		 2873}
2874
c4282df9 2875static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2876{
3b86cd99 2877 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2878 return 0;
33f089ca 2879
c4282df9 2880 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
f8c5fae1 2881 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_NMI));
33f089ca
JK		 2882}
2883
3cfc3092
JK		 2884static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2885{
2886 if (!cpu_has_virtual_nmis())
2887 return to_vmx(vcpu)->soft_vnmi_blocked;
c332c83a 2888 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 2889}
2890
2891static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2892{
2893 struct vcpu_vmx *vmx = to_vmx(vcpu);
2894
2895 if (!cpu_has_virtual_nmis()) {
2896 if (vmx->soft_vnmi_blocked != masked) {
2897 vmx->soft_vnmi_blocked = masked;
2898 vmx->vnmi_blocked_time = 0;
2899 }
2900 } else {
2901 if (masked)
2902 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2903 GUEST_INTR_STATE_NMI);
2904 else
2905 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2906 GUEST_INTR_STATE_NMI);
2907 }
2908}
2909
78646121
GN		 2910static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2911{
c4282df9
GN		 2912 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2913 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2914 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 2915}
2916
cbc94022
IE		 2917static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2918{
2919 int ret;
2920 struct kvm_userspace_memory_region tss_mem = {
6fe63979 2921 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 2922 .guest_phys_addr = addr,
2923 .memory_size = PAGE_SIZE * 3,
2924 .flags = 0,
2925 };
2926
2927 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2928 if (ret)
2929 return ret;
bfc6d222 2930 kvm->arch.tss_addr = addr;
cbc94022
IE		 2931 return 0;
2932}
2933
6aa8b732
AK		 2934static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2935 int vec, u32 err_code)
2936{
b3f37707
NK		 2937 /*
2938 * Instruction with address size override prefix opcode 0x67
2939 * Cause the #SS fault with 0 error code in VM86 mode.
2940 */
2941 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
851ba692 2942 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
6aa8b732 2943 return 1;
77ab6db0
JK		 2944 /*
2945 * Forward all other exceptions that are valid in real mode.
2946 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2947 * the required debugging infrastructure rework.
2948 */
2949 switch (vec) {
77ab6db0 2950 case DB_VECTOR:
d0bfb940
JK		 2951 if (vcpu->guest_debug &
2952 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2953 return 0;
2954 kvm_queue_exception(vcpu, vec);
2955 return 1;
77ab6db0 2956 case BP_VECTOR:
c573cd22
JK		 2957 /*
2958 * Update instruction length as we may reinject the exception
2959 * from user space while in guest debugging mode.
2960 */
2961 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2962 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 2963 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2964 return 0;
2965 /* fall through */
2966 case DE_VECTOR:
77ab6db0
JK		 2967 case OF_VECTOR:
2968 case BR_VECTOR:
2969 case UD_VECTOR:
2970 case DF_VECTOR:
2971 case SS_VECTOR:
2972 case GP_VECTOR:
2973 case MF_VECTOR:
2974 kvm_queue_exception(vcpu, vec);
2975 return 1;
2976 }
6aa8b732
AK		 2977 return 0;
2978}
2979
a0861c02
AK		 2980/*
2981 * Trigger machine check on the host. We assume all the MSRs are already set up
2982 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2983 * We pass a fake environment to the machine check handler because we want
2984 * the guest to be always treated like user space, no matter what context
2985 * it used internally.
2986 */
2987static void kvm_machine_check(void)
2988{
2989#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2990 struct pt_regs regs = {
2991 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2992 .flags = X86_EFLAGS_IF,
2993 };
2994
2995 do_machine_check(&regs, 0);
2996#endif
2997}
2998
851ba692 2999static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 3000{
3001 /* already handled by vcpu_run */
3002 return 1;
3003}
3004
851ba692 3005static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 3006{
1155f76a 3007 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 3008 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 3009 u32 intr_info, ex_no, error_code;
42dbaa5a 3010 unsigned long cr2, rip, dr6;
6aa8b732
AK		 3011 u32 vect_info;
3012 enum emulation_result er;
3013
1155f76a 3014 vect_info = vmx->idt_vectoring_info;
6aa8b732
AK		 3015 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3016
a0861c02 3017 if (is_machine_check(intr_info))
851ba692 3018 return handle_machine_check(vcpu);
a0861c02 3019
6aa8b732 3020 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 3021 !is_page_fault(intr_info)) {
3022 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3023 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3024 vcpu->run->internal.ndata = 2;
3025 vcpu->run->internal.data[0] = vect_info;
3026 vcpu->run->internal.data[1] = intr_info;
3027 return 0;
3028 }
6aa8b732 3029
e4a41889 3030 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 3031 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 3032
3033 if (is_no_device(intr_info)) {
5fd86fcf 3034 vmx_fpu_activate(vcpu);
2ab455cc
AL		 3035 return 1;
3036 }
3037
7aa81cc0 3038 if (is_invalid_opcode(intr_info)) {
851ba692 3039 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
7aa81cc0 3040 if (er != EMULATE_DONE)
7ee5d940 3041 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 3042 return 1;
3043 }
3044
6aa8b732 3045 error_code = 0;
5fdbf976 3046 rip = kvm_rip_read(vcpu);
2e11384c 3047 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 3048 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3049 if (is_page_fault(intr_info)) {
1439442c 3050 /* EPT won't cause page fault directly */
089d034e 3051 if (enable_ept)
1439442c 3052 BUG();
6aa8b732 3053 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 3054 trace_kvm_page_fault(cr2, error_code);
3055
3298b75c 3056 if (kvm_event_needs_reinjection(vcpu))
577bdc49 3057 kvm_mmu_unprotect_page_virt(vcpu, cr2);
3067714c 3058 return kvm_mmu_page_fault(vcpu, cr2, error_code);
6aa8b732
AK		 3059 }
3060
7ffd92c5 3061 if (vmx->rmode.vm86_active &&
6aa8b732 3062 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 3063 error_code)) {
ad312c7c
ZX		 3064 if (vcpu->arch.halt_request) {
3065 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 3066 return kvm_emulate_halt(vcpu);
3067 }
6aa8b732 3068 return 1;
72d6e5a0 3069 }
6aa8b732 3070
d0bfb940 3071 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 3072 switch (ex_no) {
3073 case DB_VECTOR:
3074 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3075 if (!(vcpu->guest_debug &
3076 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3077 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3078 kvm_queue_exception(vcpu, DB_VECTOR);
3079 return 1;
3080 }
3081 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3082 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3083 /* fall through */
3084 case BP_VECTOR:
c573cd22
JK		 3085 /*
3086 * Update instruction length as we may reinject #BP from
3087 * user space while in guest debugging mode. Reading it for
3088 * #DB as well causes no harm, it is not used in that case.
3089 */
3090 vmx->vcpu.arch.event_exit_inst_len =
3091 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 3092 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 3093 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3094 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 3095 break;
3096 default:
d0bfb940
JK		 3097 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3098 kvm_run->ex.exception = ex_no;
3099 kvm_run->ex.error_code = error_code;
42dbaa5a 3100 break;
6aa8b732 3101 }
6aa8b732
AK		 3102 return 0;
3103}
3104
851ba692 3105static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 3106{
1165f5fe 3107 ++vcpu->stat.irq_exits;
6aa8b732
AK		 3108 return 1;
3109}
3110
851ba692 3111static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 3112{
851ba692 3113 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 3114 return 0;
3115}
6aa8b732 3116
851ba692 3117static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 3118{
bfdaab09 3119 unsigned long exit_qualification;
34c33d16 3120 int size, in, string;
039576c0 3121 unsigned port;
6aa8b732 3122
bfdaab09 3123 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 3124 string = (exit_qualification & 16) != 0;
cf8f70bf 3125 in = (exit_qualification & 8) != 0;
e70669ab 3126
cf8f70bf 3127 ++vcpu->stat.io_exits;
e70669ab 3128
cf8f70bf 3129 if (string || in)
6d77dbfc 3130 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
e70669ab 3131
cf8f70bf
GN		 3132 port = exit_qualification >> 16;
3133 size = (exit_qualification & 7) + 1;
e93f36bc 3134 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 3135
3136 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 3137}
3138
102d8325
IM		 3139static void
3140vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3141{
3142 /*
3143 * Patch in the VMCALL instruction:
3144 */
3145 hypercall[0] = 0x0f;
3146 hypercall[1] = 0x01;
3147 hypercall[2] = 0xc1;
102d8325
IM		 3148}
3149
49a9b07e
AK		 3150static void complete_insn_gp(struct kvm_vcpu *vcpu, int err)
3151{
3152 if (err)
3153 kvm_inject_gp(vcpu, 0);
3154 else
3155 skip_emulated_instruction(vcpu);
3156}
3157
851ba692 3158static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 3159{
229456fc 3160 unsigned long exit_qualification, val;
6aa8b732
AK		 3161 int cr;
3162 int reg;
49a9b07e 3163 int err;
6aa8b732 3164
bfdaab09 3165 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 3166 cr = exit_qualification & 15;
3167 reg = (exit_qualification >> 8) & 15;
3168 switch ((exit_qualification >> 4) & 3) {
3169 case 0: /* mov to cr */
229456fc
MT		 3170 val = kvm_register_read(vcpu, reg);
3171 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 3172 switch (cr) {
3173 case 0:
49a9b07e
AK		 3174 err = kvm_set_cr0(vcpu, val);
3175 complete_insn_gp(vcpu, err);
6aa8b732
AK		 3176 return 1;
3177 case 3:
2390218b
AK		 3178 err = kvm_set_cr3(vcpu, val);
3179 complete_insn_gp(vcpu, err);
6aa8b732
AK		 3180 return 1;
3181 case 4:
a83b29c6
AK		 3182 err = kvm_set_cr4(vcpu, val);
3183 complete_insn_gp(vcpu, err);
6aa8b732 3184 return 1;
0a5fff19
GN		 3185 case 8: {
3186 u8 cr8_prev = kvm_get_cr8(vcpu);
3187 u8 cr8 = kvm_register_read(vcpu, reg);
3188 kvm_set_cr8(vcpu, cr8);
3189 skip_emulated_instruction(vcpu);
3190 if (irqchip_in_kernel(vcpu->kvm))
3191 return 1;
3192 if (cr8_prev <= cr8)
3193 return 1;
851ba692 3194 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 3195 return 0;
3196 }
6aa8b732
AK		 3197 };
3198 break;
25c4c276 3199 case 2: /* clts */
edcafe3c 3200 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 3201 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 3202 skip_emulated_instruction(vcpu);
6b52d186 3203 vmx_fpu_activate(vcpu);
25c4c276 3204 return 1;
6aa8b732
AK		 3205 case 1: /*mov from cr*/
3206 switch (cr) {
3207 case 3:
5fdbf976 3208 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
229456fc 3209 trace_kvm_cr_read(cr, vcpu->arch.cr3);
6aa8b732
AK		 3210 skip_emulated_instruction(vcpu);
3211 return 1;
3212 case 8:
229456fc
MT		 3213 val = kvm_get_cr8(vcpu);
3214 kvm_register_write(vcpu, reg, val);
3215 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 3216 skip_emulated_instruction(vcpu);
3217 return 1;
3218 }
3219 break;
3220 case 3: /* lmsw */
a1f83a74 3221 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 3222 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 3223 kvm_lmsw(vcpu, val);
6aa8b732
AK		 3224
3225 skip_emulated_instruction(vcpu);
3226 return 1;
3227 default:
3228 break;
3229 }
851ba692 3230 vcpu->run->exit_reason = 0;
f0242478 3231 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 3232 (int)(exit_qualification >> 4) & 3, cr);
3233 return 0;
3234}
3235
851ba692 3236static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 3237{
bfdaab09 3238 unsigned long exit_qualification;
6aa8b732
AK		 3239 int dr, reg;
3240
f2483415 3241 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 3242 if (!kvm_require_cpl(vcpu, 0))
3243 return 1;
42dbaa5a
JK		 3244 dr = vmcs_readl(GUEST_DR7);
3245 if (dr & DR7_GD) {
3246 /*
3247 * As the vm-exit takes precedence over the debug trap, we
3248 * need to emulate the latter, either for the host or the
3249 * guest debugging itself.
3250 */
3251 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 3252 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3253 vcpu->run->debug.arch.dr7 = dr;
3254 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 3255 vmcs_readl(GUEST_CS_BASE) +
3256 vmcs_readl(GUEST_RIP);
851ba692
AK		 3257 vcpu->run->debug.arch.exception = DB_VECTOR;
3258 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 3259 return 0;
3260 } else {
3261 vcpu->arch.dr7 &= ~DR7_GD;
3262 vcpu->arch.dr6 |= DR6_BD;
3263 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3264 kvm_queue_exception(vcpu, DB_VECTOR);
3265 return 1;
3266 }
3267 }
3268
bfdaab09 3269 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 3270 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3271 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3272 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 3273 unsigned long val;
3274 if (!kvm_get_dr(vcpu, dr, &val))
3275 kvm_register_write(vcpu, reg, val);
3276 } else
3277 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 3278 skip_emulated_instruction(vcpu);
3279 return 1;
3280}
3281
020df079
GN		 3282static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3283{
3284 vmcs_writel(GUEST_DR7, val);
3285}
3286
851ba692 3287static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 3288{
06465c5a
AK		 3289 kvm_emulate_cpuid(vcpu);
3290 return 1;
6aa8b732
AK		 3291}
3292
851ba692 3293static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 3294{
ad312c7c 3295 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 3296 u64 data;
3297
3298 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 3299 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 3300 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3301 return 1;
3302 }
3303
229456fc 3304 trace_kvm_msr_read(ecx, data);
2714d1d3 3305
6aa8b732 3306 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 3307 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3308 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 3309 skip_emulated_instruction(vcpu);
3310 return 1;
3311}
3312
851ba692 3313static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 3314{
ad312c7c
ZX		 3315 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3316 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3317 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 3318
3319 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 3320 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 3321 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3322 return 1;
3323 }
3324
59200273 3325 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 3326 skip_emulated_instruction(vcpu);
3327 return 1;
3328}
3329
851ba692 3330static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 3331{
3842d135 3332 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 3333 return 1;
3334}
3335
851ba692 3336static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 3337{
85f455f7
ED		 3338 u32 cpu_based_vm_exec_control;
3339
3340 /* clear pending irq */
3341 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3342 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3343 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 3344
3842d135
AK		 3345 kvm_make_request(KVM_REQ_EVENT, vcpu);
3346
a26bf12a 3347 ++vcpu->stat.irq_window_exits;
2714d1d3 3348
c1150d8c
DL		 3349 /*
3350 * If the user space waits to inject interrupts, exit as soon as
3351 * possible
3352 */
8061823a 3353 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 3354 vcpu->run->request_interrupt_window &&
8061823a 3355 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 3356 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 3357 return 0;
3358 }
6aa8b732
AK		 3359 return 1;
3360}
3361
851ba692 3362static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 3363{
3364 skip_emulated_instruction(vcpu);
d3bef15f 3365 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 3366}
3367
851ba692 3368static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 3369{
510043da 3370 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 3371 kvm_emulate_hypercall(vcpu);
3372 return 1;
c21415e8
IM		 3373}
3374
851ba692 3375static int handle_vmx_insn(struct kvm_vcpu *vcpu)
e3c7cb6a
AK		 3376{
3377 kvm_queue_exception(vcpu, UD_VECTOR);
3378 return 1;
3379}
3380
851ba692 3381static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 3382{
f9c617f6 3383 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 3384
3385 kvm_mmu_invlpg(vcpu, exit_qualification);
3386 skip_emulated_instruction(vcpu);
3387 return 1;
3388}
3389
851ba692 3390static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 3391{
3392 skip_emulated_instruction(vcpu);
f5f48ee1 3393 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 3394 return 1;
3395}
3396
2acf923e
DC		 3397static int handle_xsetbv(struct kvm_vcpu *vcpu)
3398{
3399 u64 new_bv = kvm_read_edx_eax(vcpu);
3400 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3401
3402 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3403 skip_emulated_instruction(vcpu);
3404 return 1;
3405}
3406
851ba692 3407static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 3408{
6d77dbfc 3409 return emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE;
f78e0e2e
SY		 3410}
3411
851ba692 3412static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 3413{
60637aac 3414 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 3415 unsigned long exit_qualification;
e269fb21
JK		 3416 bool has_error_code = false;
3417 u32 error_code = 0;
37817f29 3418 u16 tss_selector;
64a7ec06
GN		 3419 int reason, type, idt_v;
3420
3421 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3422 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3423
3424 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3425
3426 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3427 if (reason == TASK_SWITCH_GATE && idt_v) {
3428 switch (type) {
3429 case INTR_TYPE_NMI_INTR:
3430 vcpu->arch.nmi_injected = false;
3431 if (cpu_has_virtual_nmis())
3432 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3433 GUEST_INTR_STATE_NMI);
3434 break;
3435 case INTR_TYPE_EXT_INTR:
66fd3f7f 3436 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 3437 kvm_clear_interrupt_queue(vcpu);
3438 break;
3439 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 3440 if (vmx->idt_vectoring_info &
3441 VECTORING_INFO_DELIVER_CODE_MASK) {
3442 has_error_code = true;
3443 error_code =
3444 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3445 }
3446 /* fall through */
64a7ec06
GN		 3447 case INTR_TYPE_SOFT_EXCEPTION:
3448 kvm_clear_exception_queue(vcpu);
3449 break;
3450 default:
3451 break;
3452 }
60637aac 3453 }
37817f29
IE		 3454 tss_selector = exit_qualification;
3455
64a7ec06
GN		 3456 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3457 type != INTR_TYPE_EXT_INTR &&
3458 type != INTR_TYPE_NMI_INTR))
3459 skip_emulated_instruction(vcpu);
3460
acb54517
GN		 3461 if (kvm_task_switch(vcpu, tss_selector, reason,
3462 has_error_code, error_code) == EMULATE_FAIL) {
3463 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3464 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3465 vcpu->run->internal.ndata = 0;
42dbaa5a 3466 return 0;
acb54517 3467 }
42dbaa5a
JK		 3468
3469 /* clear all local breakpoint enable flags */
3470 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3471
3472 /*
3473 * TODO: What about debug traps on tss switch?
3474 * Are we supposed to inject them and update dr6?
3475 */
3476
3477 return 1;
37817f29
IE		 3478}
3479
851ba692 3480static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 3481{
f9c617f6 3482 unsigned long exit_qualification;
1439442c 3483 gpa_t gpa;
1439442c 3484 int gla_validity;
1439442c 3485
f9c617f6 3486 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3487
3488 if (exit_qualification & (1 << 6)) {
3489 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 3490 return -EINVAL;
1439442c
SY		 3491 }
3492
3493 gla_validity = (exit_qualification >> 7) & 0x3;
3494 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3495 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3496 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3497 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3498 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3499 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3500 (long unsigned int)exit_qualification);
851ba692
AK		 3501 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3502 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 3503 return 0;
1439442c
SY		 3504 }
3505
3506 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 3507 trace_kvm_page_fault(gpa, exit_qualification);
49cd7d22 3508 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
1439442c
SY		 3509}
3510
68f89400
MT		 3511static u64 ept_rsvd_mask(u64 spte, int level)
3512{
3513 int i;
3514 u64 mask = 0;
3515
3516 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3517 mask |= (1ULL << i);
3518
3519 if (level > 2)
3520 /* bits 7:3 reserved */
3521 mask |= 0xf8;
3522 else if (level == 2) {
3523 if (spte & (1ULL << 7))
3524 /* 2MB ref, bits 20:12 reserved */
3525 mask |= 0x1ff000;
3526 else
3527 /* bits 6:3 reserved */
3528 mask |= 0x78;
3529 }
3530
3531 return mask;
3532}
3533
3534static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3535 int level)
3536{
3537 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3538
3539 /* 010b (write-only) */
3540 WARN_ON((spte & 0x7) == 0x2);
3541
3542 /* 110b (write/execute) */
3543 WARN_ON((spte & 0x7) == 0x6);
3544
3545 /* 100b (execute-only) and value not supported by logical processor */
3546 if (!cpu_has_vmx_ept_execute_only())
3547 WARN_ON((spte & 0x7) == 0x4);
3548
3549 /* not 000b */
3550 if ((spte & 0x7)) {
3551 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3552
3553 if (rsvd_bits != 0) {
3554 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3555 __func__, rsvd_bits);
3556 WARN_ON(1);
3557 }
3558
3559 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3560 u64 ept_mem_type = (spte & 0x38) >> 3;
3561
3562 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3563 ept_mem_type == 7) {
3564 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3565 __func__, ept_mem_type);
3566 WARN_ON(1);
3567 }
3568 }
3569 }
3570}
3571
851ba692 3572static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 3573{
3574 u64 sptes[4];
3575 int nr_sptes, i;
3576 gpa_t gpa;
3577
3578 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3579
3580 printk(KERN_ERR "EPT: Misconfiguration.\n");
3581 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3582
3583 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3584
3585 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3586 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3587
851ba692
AK		 3588 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3589 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 3590
3591 return 0;
3592}
3593
851ba692 3594static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 3595{
3596 u32 cpu_based_vm_exec_control;
3597
3598 /* clear pending NMI */
3599 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3600 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3601 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3602 ++vcpu->stat.nmi_window_exits;
3842d135 3603 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 3604
3605 return 1;
3606}
3607
80ced186 3608static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 3609{
8b3079a5
AK		 3610 struct vcpu_vmx *vmx = to_vmx(vcpu);
3611 enum emulation_result err = EMULATE_DONE;
80ced186 3612 int ret = 1;
ea953ef0
MG		 3613
3614 while (!guest_state_valid(vcpu)) {
851ba692 3615 err = emulate_instruction(vcpu, 0, 0, 0);
ea953ef0 3616
80ced186
MG		 3617 if (err == EMULATE_DO_MMIO) {
3618 ret = 0;
3619 goto out;
3620 }
1d5a4d9b 3621
6d77dbfc
GN		 3622 if (err != EMULATE_DONE)
3623 return 0;
ea953ef0
MG		 3624
3625 if (signal_pending(current))
80ced186 3626 goto out;
ea953ef0
MG		 3627 if (need_resched())
3628 schedule();
3629 }
3630
80ced186
MG		 3631 vmx->emulation_required = 0;
3632out:
3633 return ret;
ea953ef0
MG		 3634}
3635
4b8d54f9
ZE		 3636/*
3637 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3638 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3639 */
9fb41ba8 3640static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 3641{
3642 skip_emulated_instruction(vcpu);
3643 kvm_vcpu_on_spin(vcpu);
3644
3645 return 1;
3646}
3647
59708670
SY		 3648static int handle_invalid_op(struct kvm_vcpu *vcpu)
3649{
3650 kvm_queue_exception(vcpu, UD_VECTOR);
3651 return 1;
3652}
3653
6aa8b732
AK		 3654/*
3655 * The exit handlers return 1 if the exit was handled fully and guest execution
3656 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3657 * to be done to userspace and return 0.
3658 */
851ba692 3659static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 3660 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3661 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3662 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3663 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3664 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3665 [EXIT_REASON_CR_ACCESS] = handle_cr,
3666 [EXIT_REASON_DR_ACCESS] = handle_dr,
3667 [EXIT_REASON_CPUID] = handle_cpuid,
3668 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3669 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3670 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3671 [EXIT_REASON_HLT] = handle_halt,
a7052897 3672 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3673 [EXIT_REASON_VMCALL] = handle_vmcall,
e3c7cb6a
AK		 3674 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3675 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3676 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3677 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3678 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3679 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3680 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3681 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3682 [EXIT_REASON_VMON] = handle_vmx_insn,
f78e0e2e
SY		 3683 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3684 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3685 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 3686 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 3687 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 3688 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 3689 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3690 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 3691 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 3692 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3693 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 3694};
3695
3696static const int kvm_vmx_max_exit_handlers =
50a3485c 3697 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732
AK		 3698
3699/*
3700 * The guest has exited. See if we can fix it or if we need userspace
3701 * assistance.
3702 */
851ba692 3703static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3704{
29bd8a78 3705 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 3706 u32 exit_reason = vmx->exit_reason;
1155f76a 3707 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3708
5bfd8b54 3709 trace_kvm_exit(exit_reason, vcpu);
2714d1d3 3710
80ced186
MG		 3711 /* If guest state is invalid, start emulating */
3712 if (vmx->emulation_required && emulate_invalid_guest_state)
3713 return handle_invalid_guest_state(vcpu);
1d5a4d9b 3714
1439442c
SY		 3715 /* Access CR3 don't cause VMExit in paging mode, so we need
3716 * to sync with guest real CR3. */
6de4f3ad 3717 if (enable_ept && is_paging(vcpu))
1439442c 3718 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1439442c 3719
5120702e
MG		 3720 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3721 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3722 vcpu->run->fail_entry.hardware_entry_failure_reason
3723 = exit_reason;
3724 return 0;
3725 }
3726
29bd8a78 3727 if (unlikely(vmx->fail)) {
851ba692
AK		 3728 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3729 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 3730 = vmcs_read32(VM_INSTRUCTION_ERROR);
3731 return 0;
3732 }
6aa8b732 3733
d77c26fc 3734 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3735 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3736 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3737 exit_reason != EXIT_REASON_TASK_SWITCH))
3738 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3739 "(0x%x) and exit reason is 0x%x\n",
3740 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3741
3742 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3743 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3744 vmx->soft_vnmi_blocked = 0;
3b86cd99 3745 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3746 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3747 /*
3748 * This CPU don't support us in finding the end of an
3749 * NMI-blocked window if the guest runs with IRQs
3750 * disabled. So we pull the trigger after 1 s of
3751 * futile waiting, but inform the user about this.
3752 */
3753 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3754 "state on VCPU %d after 1 s timeout\n",
3755 __func__, vcpu->vcpu_id);
3756 vmx->soft_vnmi_blocked = 0;
3b86cd99 3757 }
3b86cd99
JK		 3758 }
3759
6aa8b732
AK		 3760 if (exit_reason < kvm_vmx_max_exit_handlers
3761 && kvm_vmx_exit_handlers[exit_reason])
851ba692 3762 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 3763 else {
851ba692
AK		 3764 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3765 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 3766 }
3767 return 0;
3768}
3769
95ba8273 3770static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3771{
95ba8273 3772 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3773 vmcs_write32(TPR_THRESHOLD, 0);
3774 return;
3775 }
3776
95ba8273 3777 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3778}
3779
51aa01d1 3780static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 3781{
51aa01d1 3782 u32 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 3783
3784 /* Handle machine checks before interrupts are enabled */
3785 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3786 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3787 && is_machine_check(exit_intr_info)))
3788 kvm_machine_check();
3789
20f65983
GN		 3790 /* We need to handle NMIs before interrupts are enabled */
3791 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 3792 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3793 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 3794 asm("int $2");
ff9d07a0
ZY		 3795 kvm_after_handle_nmi(&vmx->vcpu);
3796 }
51aa01d1 3797}
20f65983 3798
51aa01d1
AK		 3799static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
3800{
3801 u32 exit_intr_info = vmx->exit_intr_info;
3802 bool unblock_nmi;
3803 u8 vector;
3804 bool idtv_info_valid;
3805
3806 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 3807
cf393f75
AK		 3808 if (cpu_has_virtual_nmis()) {
3809 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3810 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3811 /*
7b4a25cb 3812 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3813 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3814 * a guest IRET fault.
7b4a25cb
GN		 3815 * SDM 3: 23.2.2 (September 2008)
3816 * Bit 12 is undefined in any of the following cases:
3817 * If the VM exit sets the valid bit in the IDT-vectoring
3818 * information field.
3819 * If the VM exit is due to a double fault.
cf393f75 3820 */
7b4a25cb
GN		 3821 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3822 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3823 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3824 GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3825 } else if (unlikely(vmx->soft_vnmi_blocked))
3826 vmx->vnmi_blocked_time +=
3827 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 3828}
3829
3830static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3831{
537b37e2 3832 u32 idt_vectoring_info;
51aa01d1
AK		 3833 u8 vector;
3834 int type;
3835 bool idtv_info_valid;
3836
537b37e2
AK		 3837 if (vmx->rmode.irq.pending)
3838 fixup_rmode_irq(vmx);
3839
3840 idt_vectoring_info = vmx->idt_vectoring_info;
51aa01d1 3841 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 3842
37b96e98
GN		 3843 vmx->vcpu.arch.nmi_injected = false;
3844 kvm_clear_exception_queue(&vmx->vcpu);
3845 kvm_clear_interrupt_queue(&vmx->vcpu);
3846
3847 if (!idtv_info_valid)
3848 return;
3849
3842d135
AK		 3850 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
3851
668f612f
AK		 3852 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3853 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 3854
64a7ec06 3855 switch (type) {
37b96e98
GN		 3856 case INTR_TYPE_NMI_INTR:
3857 vmx->vcpu.arch.nmi_injected = true;
668f612f 3858 /*
7b4a25cb 3859 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 3860 * Clear bit "block by NMI" before VM entry if a NMI
3861 * delivery faulted.
668f612f 3862 */
37b96e98
GN		 3863 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3864 GUEST_INTR_STATE_NMI);
3865 break;
37b96e98 3866 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f
GN		 3867 vmx->vcpu.arch.event_exit_inst_len =
3868 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3869 /* fall through */
3870 case INTR_TYPE_HARD_EXCEPTION:
35920a35 3871 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
37b96e98
GN		 3872 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3873 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 3874 } else
3875 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 3876 break;
66fd3f7f
GN		 3877 case INTR_TYPE_SOFT_INTR:
3878 vmx->vcpu.arch.event_exit_inst_len =
3879 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3880 /* fall through */
37b96e98 3881 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 3882 kvm_queue_interrupt(&vmx->vcpu, vector,
3883 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 3884 break;
3885 default:
3886 break;
f7d9238f 3887 }
cf393f75
AK		 3888}
3889
9c8cba37
AK		 3890/*
3891 * Failure to inject an interrupt should give us the information
3892 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3893 * when fetching the interrupt redirection bitmap in the real-mode
3894 * tss, this doesn't happen. So we do it ourselves.
3895 */
3896static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3897{
3898 vmx->rmode.irq.pending = 0;
5fdbf976 3899 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
9c8cba37 3900 return;
5fdbf976 3901 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
9c8cba37
AK		 3902 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3903 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3904 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3905 return;
3906 }
3907 vmx->idt_vectoring_info =
3908 VECTORING_INFO_VALID_MASK
3909 | INTR_TYPE_EXT_INTR
3910 | vmx->rmode.irq.vector;
3911}
3912
c801949d
AK		 3913#ifdef CONFIG_X86_64
3914#define R "r"
3915#define Q "q"
3916#else
3917#define R "e"
3918#define Q "l"
3919#endif
3920
851ba692 3921static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 3922{
a2fa3e9f 3923 struct vcpu_vmx *vmx = to_vmx(vcpu);
e6adf283 3924
3b86cd99
JK		 3925 /* Record the guest's net vcpu time for enforced NMI injections. */
3926 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3927 vmx->entry_time = ktime_get();
3928
80ced186
MG		 3929 /* Don't enter VMX if guest state is invalid, let the exit handler
3930 start emulation until we arrive back to a valid state */
3931 if (vmx->emulation_required && emulate_invalid_guest_state)
a89a8fb9 3932 return;
a89a8fb9 3933
5fdbf976
MT		 3934 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3935 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3936 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3937 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3938
787ff736
GN		 3939 /* When single-stepping over STI and MOV SS, we must clear the
3940 * corresponding interruptibility bits in the guest state. Otherwise
3941 * vmentry fails as it then expects bit 14 (BS) in pending debug
3942 * exceptions being set, but that's not correct for the guest debugging
3943 * case. */
3944 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3945 vmx_set_interrupt_shadow(vcpu, 0);
3946
d77c26fc 3947 asm(
6aa8b732 3948 /* Store host registers */
c801949d
AK		 3949 "push %%"R"dx; push %%"R"bp;"
3950 "push %%"R"cx \n\t"
313dbd49
AK		 3951 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3952 "je 1f \n\t"
3953 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 3954 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 3955 "1: \n\t"
d3edefc0
AK		 3956 /* Reload cr2 if changed */
3957 "mov %c[cr2](%0), %%"R"ax \n\t"
3958 "mov %%cr2, %%"R"dx \n\t"
3959 "cmp %%"R"ax, %%"R"dx \n\t"
3960 "je 2f \n\t"
3961 "mov %%"R"ax, %%cr2 \n\t"
3962 "2: \n\t"
6aa8b732 3963 /* Check if vmlaunch of vmresume is needed */
e08aa78a 3964 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 3965 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 3966 "mov %c[rax](%0), %%"R"ax \n\t"
3967 "mov %c[rbx](%0), %%"R"bx \n\t"
3968 "mov %c[rdx](%0), %%"R"dx \n\t"
3969 "mov %c[rsi](%0), %%"R"si \n\t"
3970 "mov %c[rdi](%0), %%"R"di \n\t"
3971 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 3972#ifdef CONFIG_X86_64
e08aa78a
AK		 3973 "mov %c[r8](%0), %%r8 \n\t"
3974 "mov %c[r9](%0), %%r9 \n\t"
3975 "mov %c[r10](%0), %%r10 \n\t"
3976 "mov %c[r11](%0), %%r11 \n\t"
3977 "mov %c[r12](%0), %%r12 \n\t"
3978 "mov %c[r13](%0), %%r13 \n\t"
3979 "mov %c[r14](%0), %%r14 \n\t"
3980 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 3981#endif
c801949d
AK		 3982 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3983
6aa8b732 3984 /* Enter guest mode */
cd2276a7 3985 "jne .Llaunched \n\t"
4ecac3fd 3986 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 3987 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 3988 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 3989 ".Lkvm_vmx_return: "
6aa8b732 3990 /* Save guest registers, load host registers, keep flags */
c801949d
AK		 3991 "xchg %0, (%%"R"sp) \n\t"
3992 "mov %%"R"ax, %c[rax](%0) \n\t"
3993 "mov %%"R"bx, %c[rbx](%0) \n\t"
3994 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3995 "mov %%"R"dx, %c[rdx](%0) \n\t"
3996 "mov %%"R"si, %c[rsi](%0) \n\t"
3997 "mov %%"R"di, %c[rdi](%0) \n\t"
3998 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 3999#ifdef CONFIG_X86_64
e08aa78a
AK		 4000 "mov %%r8, %c[r8](%0) \n\t"
4001 "mov %%r9, %c[r9](%0) \n\t"
4002 "mov %%r10, %c[r10](%0) \n\t"
4003 "mov %%r11, %c[r11](%0) \n\t"
4004 "mov %%r12, %c[r12](%0) \n\t"
4005 "mov %%r13, %c[r13](%0) \n\t"
4006 "mov %%r14, %c[r14](%0) \n\t"
4007 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 4008#endif
c801949d
AK		 4009 "mov %%cr2, %%"R"ax \n\t"
4010 "mov %%"R"ax, %c[cr2](%0) \n\t"
4011
4012 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 4013 "setbe %c[fail](%0) \n\t"
4014 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
4015 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
4016 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 4017 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 4018 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
4019 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
4020 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4021 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4022 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4023 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4024 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 4025#ifdef CONFIG_X86_64
ad312c7c
ZX		 4026 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4027 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4028 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4029 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4030 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4031 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4032 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4033 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 4034#endif
ad312c7c 4035 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
c2036300 4036 : "cc", "memory"
c801949d 4037 , R"bx", R"di", R"si"
c2036300 4038#ifdef CONFIG_X86_64
c2036300
LV		 4039 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4040#endif
4041 );
6aa8b732 4042
6de4f3ad
AK		 4043 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
4044 | (1 << VCPU_EXREG_PDPTR));
5fdbf976
MT		 4045 vcpu->arch.regs_dirty = 0;
4046
1155f76a
AK		 4047 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4048
d77c26fc 4049 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 4050 vmx->launched = 1;
1b6269db 4051
51aa01d1
AK		 4052 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
4053 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
4054
4055 vmx_complete_atomic_exit(vmx);
4056 vmx_recover_nmi_blocking(vmx);
cf393f75 4057 vmx_complete_interrupts(vmx);
6aa8b732
AK		 4058}
4059
c801949d
AK		 4060#undef R
4061#undef Q
4062
6aa8b732
AK		 4063static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4064{
a2fa3e9f
GH		 4065 struct vcpu_vmx *vmx = to_vmx(vcpu);
4066
4067 if (vmx->vmcs) {
543e4243 4068 vcpu_clear(vmx);
a2fa3e9f
GH		 4069 free_vmcs(vmx->vmcs);
4070 vmx->vmcs = NULL;
6aa8b732
AK		 4071 }
4072}
4073
4074static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4075{
fb3f0f51
RR		 4076 struct vcpu_vmx *vmx = to_vmx(vcpu);
4077
cdbecfc3 4078 free_vpid(vmx);
6aa8b732 4079 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 4080 kfree(vmx->guest_msrs);
4081 kvm_vcpu_uninit(vcpu);
a4770347 4082 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 4083}
4084
4610c9cc
DX		 4085static inline void vmcs_init(struct vmcs *vmcs)
4086{
4087 u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4088
4089 if (!vmm_exclusive)
4090 kvm_cpu_vmxon(phys_addr);
4091
4092 vmcs_clear(vmcs);
4093
4094 if (!vmm_exclusive)
4095 kvm_cpu_vmxoff();
4096}
4097
fb3f0f51 4098static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 4099{
fb3f0f51 4100 int err;
c16f862d 4101 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 4102 int cpu;
6aa8b732 4103
a2fa3e9f 4104 if (!vmx)
fb3f0f51
RR		 4105 return ERR_PTR(-ENOMEM);
4106
2384d2b3
SY		 4107 allocate_vpid(vmx);
4108
fb3f0f51
RR		 4109 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4110 if (err)
4111 goto free_vcpu;
965b58a5 4112
a2fa3e9f 4113 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
fb3f0f51
RR		 4114 if (!vmx->guest_msrs) {
4115 err = -ENOMEM;
4116 goto uninit_vcpu;
4117 }
965b58a5 4118
a2fa3e9f
GH		 4119 vmx->vmcs = alloc_vmcs();
4120 if (!vmx->vmcs)
fb3f0f51 4121 goto free_msrs;
a2fa3e9f 4122
4610c9cc 4123 vmcs_init(vmx->vmcs);
a2fa3e9f 4124
15ad7146
AK		 4125 cpu = get_cpu();
4126 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 4127 vmx->vcpu.cpu = cpu;
8b9cf98c 4128 err = vmx_vcpu_setup(vmx);
fb3f0f51 4129 vmx_vcpu_put(&vmx->vcpu);
15ad7146 4130 put_cpu();
fb3f0f51
RR		 4131 if (err)
4132 goto free_vmcs;
5e4a0b3c
MT		 4133 if (vm_need_virtualize_apic_accesses(kvm))
4134 if (alloc_apic_access_page(kvm) != 0)
4135 goto free_vmcs;
fb3f0f51 4136
b927a3ce
SY		 4137 if (enable_ept) {
4138 if (!kvm->arch.ept_identity_map_addr)
4139 kvm->arch.ept_identity_map_addr =
4140 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
b7ebfb05
SY		 4141 if (alloc_identity_pagetable(kvm) != 0)
4142 goto free_vmcs;
b927a3ce 4143 }
b7ebfb05 4144
fb3f0f51
RR		 4145 return &vmx->vcpu;
4146
4147free_vmcs:
4148 free_vmcs(vmx->vmcs);
4149free_msrs:
fb3f0f51
RR		 4150 kfree(vmx->guest_msrs);
4151uninit_vcpu:
4152 kvm_vcpu_uninit(&vmx->vcpu);
4153free_vcpu:
cdbecfc3 4154 free_vpid(vmx);
a4770347 4155 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 4156 return ERR_PTR(err);
6aa8b732
AK		 4157}
4158
002c7f7c
YS		 4159static void __init vmx_check_processor_compat(void *rtn)
4160{
4161 struct vmcs_config vmcs_conf;
4162
4163 *(int *)rtn = 0;
4164 if (setup_vmcs_config(&vmcs_conf) < 0)
4165 *(int *)rtn = -EIO;
4166 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4167 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4168 smp_processor_id());
4169 *(int *)rtn = -EIO;
4170 }
4171}
4172
67253af5
SY		 4173static int get_ept_level(void)
4174{
4175 return VMX_EPT_DEFAULT_GAW + 1;
4176}
4177
4b12f0de 4178static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 4179{
4b12f0de
SY		 4180 u64 ret;
4181
522c68c4
SY		 4182 /* For VT-d and EPT combination
4183 * 1. MMIO: always map as UC
4184 * 2. EPT with VT-d:
4185 * a. VT-d without snooping control feature: can't guarantee the
4186 * result, try to trust guest.
4187 * b. VT-d with snooping control feature: snooping control feature of
4188 * VT-d engine can guarantee the cache correctness. Just set it
4189 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 4190 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 4191 * consistent with host MTRR
4192 */
4b12f0de
SY		 4193 if (is_mmio)
4194 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 4195 else if (vcpu->kvm->arch.iommu_domain &&
4196 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4197 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4198 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 4199 else
522c68c4 4200 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 4201 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 4202
4203 return ret;
64d4d521
SY		 4204}
4205
f4c9e87c
AK		 4206#define _ER(x) { EXIT_REASON_##x, #x }
4207
229456fc 4208static const struct trace_print_flags vmx_exit_reasons_str[] = {
f4c9e87c
AK		 4209 _ER(EXCEPTION_NMI),
4210 _ER(EXTERNAL_INTERRUPT),
4211 _ER(TRIPLE_FAULT),
4212 _ER(PENDING_INTERRUPT),
4213 _ER(NMI_WINDOW),
4214 _ER(TASK_SWITCH),
4215 _ER(CPUID),
4216 _ER(HLT),
4217 _ER(INVLPG),
4218 _ER(RDPMC),
4219 _ER(RDTSC),
4220 _ER(VMCALL),
4221 _ER(VMCLEAR),
4222 _ER(VMLAUNCH),
4223 _ER(VMPTRLD),
4224 _ER(VMPTRST),
4225 _ER(VMREAD),
4226 _ER(VMRESUME),
4227 _ER(VMWRITE),
4228 _ER(VMOFF),
4229 _ER(VMON),
4230 _ER(CR_ACCESS),
4231 _ER(DR_ACCESS),
4232 _ER(IO_INSTRUCTION),
4233 _ER(MSR_READ),
4234 _ER(MSR_WRITE),
4235 _ER(MWAIT_INSTRUCTION),
4236 _ER(MONITOR_INSTRUCTION),
4237 _ER(PAUSE_INSTRUCTION),
4238 _ER(MCE_DURING_VMENTRY),
4239 _ER(TPR_BELOW_THRESHOLD),
4240 _ER(APIC_ACCESS),
4241 _ER(EPT_VIOLATION),
4242 _ER(EPT_MISCONFIG),
4243 _ER(WBINVD),
229456fc
MT		 4244 { -1, NULL }
4245};
4246
f4c9e87c
AK		 4247#undef _ER
4248
17cc3935 4249static int vmx_get_lpage_level(void)
344f414f 4250{
878403b7
SY		 4251 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4252 return PT_DIRECTORY_LEVEL;
4253 else
4254 /* For shadow and EPT supported 1GB page */
4255 return PT_PDPE_LEVEL;
344f414f
JR		 4256}
4257
4e47c7a6
SY		 4258static inline u32 bit(int bitno)
4259{
4260 return 1 << (bitno & 31);
4261}
4262
0e851880
SY		 4263static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4264{
4e47c7a6
SY		 4265 struct kvm_cpuid_entry2 *best;
4266 struct vcpu_vmx *vmx = to_vmx(vcpu);
4267 u32 exec_control;
4268
4269 vmx->rdtscp_enabled = false;
4270 if (vmx_rdtscp_supported()) {
4271 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4272 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4273 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4274 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4275 vmx->rdtscp_enabled = true;
4276 else {
4277 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4278 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4279 exec_control);
4280 }
4281 }
4282 }
0e851880
SY		 4283}
4284
d4330ef2
JR		 4285static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4286{
4287}
4288
cbdd1bea 4289static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 4290 .cpu_has_kvm_support = cpu_has_kvm_support,
4291 .disabled_by_bios = vmx_disabled_by_bios,
4292 .hardware_setup = hardware_setup,
4293 .hardware_unsetup = hardware_unsetup,
002c7f7c 4294 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 4295 .hardware_enable = hardware_enable,
4296 .hardware_disable = hardware_disable,
04547156 4297 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 4298
4299 .vcpu_create = vmx_create_vcpu,
4300 .vcpu_free = vmx_free_vcpu,
04d2cc77 4301 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 4302
04d2cc77 4303 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 4304 .vcpu_load = vmx_vcpu_load,
4305 .vcpu_put = vmx_vcpu_put,
4306
4307 .set_guest_debug = set_guest_debug,
4308 .get_msr = vmx_get_msr,
4309 .set_msr = vmx_set_msr,
4310 .get_segment_base = vmx_get_segment_base,
4311 .get_segment = vmx_get_segment,
4312 .set_segment = vmx_set_segment,
2e4d2653 4313 .get_cpl = vmx_get_cpl,
6aa8b732 4314 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 4315 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
25c4c276 4316 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 4317 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 4318 .set_cr3 = vmx_set_cr3,
4319 .set_cr4 = vmx_set_cr4,
6aa8b732 4320 .set_efer = vmx_set_efer,
6aa8b732
AK		 4321 .get_idt = vmx_get_idt,
4322 .set_idt = vmx_set_idt,
4323 .get_gdt = vmx_get_gdt,
4324 .set_gdt = vmx_set_gdt,
020df079 4325 .set_dr7 = vmx_set_dr7,
5fdbf976 4326 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 4327 .get_rflags = vmx_get_rflags,
4328 .set_rflags = vmx_set_rflags,
ebcbab4c 4329 .fpu_activate = vmx_fpu_activate,
02daab21 4330 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 4331
4332 .tlb_flush = vmx_flush_tlb,
6aa8b732 4333
6aa8b732 4334 .run = vmx_vcpu_run,
6062d012 4335 .handle_exit = vmx_handle_exit,
6aa8b732 4336 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 4337 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4338 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 4339 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 4340 .set_irq = vmx_inject_irq,
95ba8273 4341 .set_nmi = vmx_inject_nmi,
298101da 4342 .queue_exception = vmx_queue_exception,
78646121 4343 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 4344 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 4345 .get_nmi_mask = vmx_get_nmi_mask,
4346 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 4347 .enable_nmi_window = enable_nmi_window,
4348 .enable_irq_window = enable_irq_window,
4349 .update_cr8_intercept = update_cr8_intercept,
95ba8273 4350
cbc94022 4351 .set_tss_addr = vmx_set_tss_addr,
67253af5 4352 .get_tdp_level = get_ept_level,
4b12f0de 4353 .get_mt_mask = vmx_get_mt_mask,
229456fc
MT		 4354
4355 .exit_reasons_str = vmx_exit_reasons_str,
17cc3935 4356 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 4357
4358 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 4359
4360 .rdtscp_supported = vmx_rdtscp_supported,
d4330ef2
JR		 4361
4362 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 4363
4364 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a
ZA		 4365
4366 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 4367 .adjust_tsc_offset = vmx_adjust_tsc_offset,
1c97f0a0
JR		 4368
4369 .set_tdp_cr3 = vmx_set_cr3,
6aa8b732
AK		 4370};
4371
4372static int __init vmx_init(void)
4373{
26bb0981
AK		 4374 int r, i;
4375
4376 rdmsrl_safe(MSR_EFER, &host_efer);
4377
4378 for (i = 0; i < NR_VMX_MSR; ++i)
4379 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 4380
3e7c73e9 4381 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4382 if (!vmx_io_bitmap_a)
4383 return -ENOMEM;
4384
3e7c73e9 4385 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4386 if (!vmx_io_bitmap_b) {
4387 r = -ENOMEM;
4388 goto out;
4389 }
4390
5897297b
AK		 4391 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4392 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 4393 r = -ENOMEM;
4394 goto out1;
4395 }
4396
5897297b
AK		 4397 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4398 if (!vmx_msr_bitmap_longmode) {
4399 r = -ENOMEM;
4400 goto out2;
4401 }
4402
fdef3ad1
HQ		 4403 /*
4404 * Allow direct access to the PC debug port (it is often used for I/O
4405 * delays, but the vmexits simply slow things down).
4406 */
3e7c73e9
AK		 4407 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4408 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 4409
3e7c73e9 4410 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 4411
5897297b
AK		 4412 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4413 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 4414
2384d2b3
SY		 4415 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4416
0ee75bea
AK		 4417 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4418 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 4419 if (r)
5897297b 4420 goto out3;
25c5f225 4421
5897297b
AK		 4422 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4423 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4424 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4425 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4426 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4427 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 4428
089d034e 4429 if (enable_ept) {
1439442c 4430 bypass_guest_pf = 0;
5fdbcb9d 4431 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
2aaf69dc 4432 VMX_EPT_WRITABLE_MASK);
534e38b4 4433 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 4434 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 4435 kvm_enable_tdp();
4436 } else
4437 kvm_disable_tdp();
1439442c 4438
c7addb90
AK		 4439 if (bypass_guest_pf)
4440 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4441
fdef3ad1
HQ		 4442 return 0;
4443
5897297b
AK		 4444out3:
4445 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 4446out2:
5897297b 4447 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 4448out1:
3e7c73e9 4449 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 4450out:
3e7c73e9 4451 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4452 return r;
6aa8b732
AK		 4453}
4454
4455static void __exit vmx_exit(void)
4456{
5897297b
AK		 4457 free_page((unsigned long)vmx_msr_bitmap_legacy);
4458 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 4459 free_page((unsigned long)vmx_io_bitmap_b);
4460 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4461
cb498ea2 4462 kvm_exit();
6aa8b732
AK		 4463}
4464
4465module_init(vmx_init)
4466module_exit(vmx_exit)
ubuntu-bionic-kernel mirror