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KVM: nVMX: Move host-state field setup to a function
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
e495606d 21
edf88417 22#include <linux/kvm_host.h>
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/mm.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
c7addb90 28#include <linux/moduleparam.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
cafd6659 31#include <linux/tboot.h>
5fdbf976 32#include "kvm_cache_regs.h"
35920a35 33#include "x86.h"
e495606d 34
6aa8b732 35#include <asm/io.h>
3b3be0d1 36#include <asm/desc.h>
13673a90 37#include <asm/vmx.h>
6210e37b 38#include <asm/virtext.h>
a0861c02 39#include <asm/mce.h>
2acf923e
DC		 40#include <asm/i387.h>
41#include <asm/xcr.h>
6aa8b732 42
229456fc
MT		 43#include "trace.h"
44
4ecac3fd 45#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 46#define __ex_clear(x, reg) \
47 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 48
6aa8b732
AK		 49MODULE_AUTHOR("Qumranet");
50MODULE_LICENSE("GPL");
51
4462d21a 52static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 53module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 54
4462d21a 55static int __read_mostly enable_vpid = 1;
736caefe 56module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 57
4462d21a 58static int __read_mostly flexpriority_enabled = 1;
736caefe 59module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 60
4462d21a 61static int __read_mostly enable_ept = 1;
736caefe 62module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 63
3a624e29
NK		 64static int __read_mostly enable_unrestricted_guest = 1;
65module_param_named(unrestricted_guest,
66 enable_unrestricted_guest, bool, S_IRUGO);
67
4462d21a 68static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 69module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 70
b923e62e
DX		 71static int __read_mostly vmm_exclusive = 1;
72module_param(vmm_exclusive, bool, S_IRUGO);
73
443381a8
AL		 74static int __read_mostly yield_on_hlt = 1;
75module_param(yield_on_hlt, bool, S_IRUGO);
76
801d3424
NHE		 77/*
78 * If nested=1, nested virtualization is supported, i.e., guests may use
79 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
80 * use VMX instructions.
81 */
82static int __read_mostly nested = 0;
83module_param(nested, bool, S_IRUGO);
84
cdc0e244
AK		 85#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
86 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
87#define KVM_GUEST_CR0_MASK \
88 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
89#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 90 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 91#define KVM_VM_CR0_ALWAYS_ON \
92 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 93#define KVM_CR4_GUEST_OWNED_BITS \
94 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
95 | X86_CR4_OSXMMEXCPT)
96
cdc0e244
AK		 97#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
98#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
99
78ac8b47
AK		 100#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
101
4b8d54f9
ZE		 102/*
103 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
104 * ple_gap: upper bound on the amount of time between two successive
105 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 106 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 107 * ple_window: upper bound on the amount of time a guest is allowed to execute
108 * in a PAUSE loop. Tests indicate that most spinlocks are held for
109 * less than 2^12 cycles
110 * Time is measured based on a counter that runs at the same rate as the TSC,
111 * refer SDM volume 3b section 21.6.13 & 22.1.3.
112 */
00c25bce 113#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 114#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
115static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
116module_param(ple_gap, int, S_IRUGO);
117
118static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
119module_param(ple_window, int, S_IRUGO);
120
61d2ef2c 121#define NR_AUTOLOAD_MSRS 1
ff2f6fe9 122#define VMCS02_POOL_SIZE 1
61d2ef2c 123
a2fa3e9f
GH		 124struct vmcs {
125 u32 revision_id;
126 u32 abort;
127 char data[0];
128};
129
d462b819
NHE		 130/*
131 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
132 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
133 * loaded on this CPU (so we can clear them if the CPU goes down).
134 */
135struct loaded_vmcs {
136 struct vmcs *vmcs;
137 int cpu;
138 int launched;
139 struct list_head loaded_vmcss_on_cpu_link;
140};
141
26bb0981
AK		 142struct shared_msr_entry {
143 unsigned index;
144 u64 data;
d5696725 145 u64 mask;
26bb0981
AK		 146};
147
a9d30f33
NHE		 148/*
149 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
150 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
151 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
152 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
153 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
154 * More than one of these structures may exist, if L1 runs multiple L2 guests.
155 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
156 * underlying hardware which will be used to run L2.
157 * This structure is packed to ensure that its layout is identical across
158 * machines (necessary for live migration).
159 * If there are changes in this struct, VMCS12_REVISION must be changed.
160 */
22bd0358 161typedef u64 natural_width;
a9d30f33
NHE		 162struct __packed vmcs12 {
163 /* According to the Intel spec, a VMCS region must start with the
164 * following two fields. Then follow implementation-specific data.
165 */
166 u32 revision_id;
167 u32 abort;
22bd0358 168
27d6c865
NHE		 169 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
170 u32 padding[7]; /* room for future expansion */
171
22bd0358
NHE		 172 u64 io_bitmap_a;
173 u64 io_bitmap_b;
174 u64 msr_bitmap;
175 u64 vm_exit_msr_store_addr;
176 u64 vm_exit_msr_load_addr;
177 u64 vm_entry_msr_load_addr;
178 u64 tsc_offset;
179 u64 virtual_apic_page_addr;
180 u64 apic_access_addr;
181 u64 ept_pointer;
182 u64 guest_physical_address;
183 u64 vmcs_link_pointer;
184 u64 guest_ia32_debugctl;
185 u64 guest_ia32_pat;
186 u64 guest_ia32_efer;
187 u64 guest_ia32_perf_global_ctrl;
188 u64 guest_pdptr0;
189 u64 guest_pdptr1;
190 u64 guest_pdptr2;
191 u64 guest_pdptr3;
192 u64 host_ia32_pat;
193 u64 host_ia32_efer;
194 u64 host_ia32_perf_global_ctrl;
195 u64 padding64[8]; /* room for future expansion */
196 /*
197 * To allow migration of L1 (complete with its L2 guests) between
198 * machines of different natural widths (32 or 64 bit), we cannot have
199 * unsigned long fields with no explict size. We use u64 (aliased
200 * natural_width) instead. Luckily, x86 is little-endian.
201 */
202 natural_width cr0_guest_host_mask;
203 natural_width cr4_guest_host_mask;
204 natural_width cr0_read_shadow;
205 natural_width cr4_read_shadow;
206 natural_width cr3_target_value0;
207 natural_width cr3_target_value1;
208 natural_width cr3_target_value2;
209 natural_width cr3_target_value3;
210 natural_width exit_qualification;
211 natural_width guest_linear_address;
212 natural_width guest_cr0;
213 natural_width guest_cr3;
214 natural_width guest_cr4;
215 natural_width guest_es_base;
216 natural_width guest_cs_base;
217 natural_width guest_ss_base;
218 natural_width guest_ds_base;
219 natural_width guest_fs_base;
220 natural_width guest_gs_base;
221 natural_width guest_ldtr_base;
222 natural_width guest_tr_base;
223 natural_width guest_gdtr_base;
224 natural_width guest_idtr_base;
225 natural_width guest_dr7;
226 natural_width guest_rsp;
227 natural_width guest_rip;
228 natural_width guest_rflags;
229 natural_width guest_pending_dbg_exceptions;
230 natural_width guest_sysenter_esp;
231 natural_width guest_sysenter_eip;
232 natural_width host_cr0;
233 natural_width host_cr3;
234 natural_width host_cr4;
235 natural_width host_fs_base;
236 natural_width host_gs_base;
237 natural_width host_tr_base;
238 natural_width host_gdtr_base;
239 natural_width host_idtr_base;
240 natural_width host_ia32_sysenter_esp;
241 natural_width host_ia32_sysenter_eip;
242 natural_width host_rsp;
243 natural_width host_rip;
244 natural_width paddingl[8]; /* room for future expansion */
245 u32 pin_based_vm_exec_control;
246 u32 cpu_based_vm_exec_control;
247 u32 exception_bitmap;
248 u32 page_fault_error_code_mask;
249 u32 page_fault_error_code_match;
250 u32 cr3_target_count;
251 u32 vm_exit_controls;
252 u32 vm_exit_msr_store_count;
253 u32 vm_exit_msr_load_count;
254 u32 vm_entry_controls;
255 u32 vm_entry_msr_load_count;
256 u32 vm_entry_intr_info_field;
257 u32 vm_entry_exception_error_code;
258 u32 vm_entry_instruction_len;
259 u32 tpr_threshold;
260 u32 secondary_vm_exec_control;
261 u32 vm_instruction_error;
262 u32 vm_exit_reason;
263 u32 vm_exit_intr_info;
264 u32 vm_exit_intr_error_code;
265 u32 idt_vectoring_info_field;
266 u32 idt_vectoring_error_code;
267 u32 vm_exit_instruction_len;
268 u32 vmx_instruction_info;
269 u32 guest_es_limit;
270 u32 guest_cs_limit;
271 u32 guest_ss_limit;
272 u32 guest_ds_limit;
273 u32 guest_fs_limit;
274 u32 guest_gs_limit;
275 u32 guest_ldtr_limit;
276 u32 guest_tr_limit;
277 u32 guest_gdtr_limit;
278 u32 guest_idtr_limit;
279 u32 guest_es_ar_bytes;
280 u32 guest_cs_ar_bytes;
281 u32 guest_ss_ar_bytes;
282 u32 guest_ds_ar_bytes;
283 u32 guest_fs_ar_bytes;
284 u32 guest_gs_ar_bytes;
285 u32 guest_ldtr_ar_bytes;
286 u32 guest_tr_ar_bytes;
287 u32 guest_interruptibility_info;
288 u32 guest_activity_state;
289 u32 guest_sysenter_cs;
290 u32 host_ia32_sysenter_cs;
291 u32 padding32[8]; /* room for future expansion */
292 u16 virtual_processor_id;
293 u16 guest_es_selector;
294 u16 guest_cs_selector;
295 u16 guest_ss_selector;
296 u16 guest_ds_selector;
297 u16 guest_fs_selector;
298 u16 guest_gs_selector;
299 u16 guest_ldtr_selector;
300 u16 guest_tr_selector;
301 u16 host_es_selector;
302 u16 host_cs_selector;
303 u16 host_ss_selector;
304 u16 host_ds_selector;
305 u16 host_fs_selector;
306 u16 host_gs_selector;
307 u16 host_tr_selector;
a9d30f33
NHE		 308};
309
310/*
311 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
312 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
313 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
314 */
315#define VMCS12_REVISION 0x11e57ed0
316
317/*
318 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
319 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
320 * current implementation, 4K are reserved to avoid future complications.
321 */
322#define VMCS12_SIZE 0x1000
323
ff2f6fe9
NHE		 324/* Used to remember the last vmcs02 used for some recently used vmcs12s */
325struct vmcs02_list {
326 struct list_head list;
327 gpa_t vmptr;
328 struct loaded_vmcs vmcs02;
329};
330
ec378aee
NHE		 331/*
332 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
333 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
334 */
335struct nested_vmx {
336 /* Has the level1 guest done vmxon? */
337 bool vmxon;
a9d30f33
NHE		 338
339 /* The guest-physical address of the current VMCS L1 keeps for L2 */
340 gpa_t current_vmptr;
341 /* The host-usable pointer to the above */
342 struct page *current_vmcs12_page;
343 struct vmcs12 *current_vmcs12;
ff2f6fe9
NHE		 344
345 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
346 struct list_head vmcs02_pool;
347 int vmcs02_num;
ec378aee
NHE		 348};
349
a2fa3e9f 350struct vcpu_vmx {
fb3f0f51 351 struct kvm_vcpu vcpu;
313dbd49 352 unsigned long host_rsp;
29bd8a78 353 u8 fail;
69c73028 354 u8 cpl;
9d58b931 355 bool nmi_known_unmasked;
51aa01d1 356 u32 exit_intr_info;
1155f76a 357 u32 idt_vectoring_info;
6de12732 358 ulong rflags;
26bb0981 359 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 360 int nmsrs;
361 int save_nmsrs;
a2fa3e9f 362#ifdef CONFIG_X86_64
44ea2b17
AK		 363 u64 msr_host_kernel_gs_base;
364 u64 msr_guest_kernel_gs_base;
a2fa3e9f 365#endif
d462b819
NHE		 366 /*
367 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
368 * non-nested (L1) guest, it always points to vmcs01. For a nested
369 * guest (L2), it points to a different VMCS.
370 */
371 struct loaded_vmcs vmcs01;
372 struct loaded_vmcs *loaded_vmcs;
373 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 374 struct msr_autoload {
375 unsigned nr;
376 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
377 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
378 } msr_autoload;
a2fa3e9f
GH		 379 struct {
380 int loaded;
381 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 382 int gs_ldt_reload_needed;
383 int fs_reload_needed;
d77c26fc 384 } host_state;
9c8cba37 385 struct {
7ffd92c5 386 int vm86_active;
78ac8b47 387 ulong save_rflags;
7ffd92c5
AK		 388 struct kvm_save_segment {
389 u16 selector;
390 unsigned long base;
391 u32 limit;
392 u32 ar;
393 } tr, es, ds, fs, gs;
9c8cba37 394 } rmode;
2fb92db1
AK		 395 struct {
396 u32 bitmask; /* 4 bits per segment (1 bit per field) */
397 struct kvm_save_segment seg[8];
398 } segment_cache;
2384d2b3 399 int vpid;
04fa4d32 400 bool emulation_required;
3b86cd99
JK		 401
402 /* Support for vnmi-less CPUs */
403 int soft_vnmi_blocked;
404 ktime_t entry_time;
405 s64 vnmi_blocked_time;
a0861c02 406 u32 exit_reason;
4e47c7a6
SY		 407
408 bool rdtscp_enabled;
ec378aee
NHE		 409
410 /* Support for a guest hypervisor (nested VMX) */
411 struct nested_vmx nested;
a2fa3e9f
GH		 412};
413
2fb92db1
AK		 414enum segment_cache_field {
415 SEG_FIELD_SEL = 0,
416 SEG_FIELD_BASE = 1,
417 SEG_FIELD_LIMIT = 2,
418 SEG_FIELD_AR = 3,
419
420 SEG_FIELD_NR = 4
421};
422
a2fa3e9f
GH		 423static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
424{
fb3f0f51 425 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 426}
427
22bd0358
NHE		 428#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
429#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
430#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
431 [number##_HIGH] = VMCS12_OFFSET(name)+4
432
433static unsigned short vmcs_field_to_offset_table[] = {
434 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
435 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
436 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
437 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
438 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
439 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
440 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
441 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
442 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
443 FIELD(HOST_ES_SELECTOR, host_es_selector),
444 FIELD(HOST_CS_SELECTOR, host_cs_selector),
445 FIELD(HOST_SS_SELECTOR, host_ss_selector),
446 FIELD(HOST_DS_SELECTOR, host_ds_selector),
447 FIELD(HOST_FS_SELECTOR, host_fs_selector),
448 FIELD(HOST_GS_SELECTOR, host_gs_selector),
449 FIELD(HOST_TR_SELECTOR, host_tr_selector),
450 FIELD64(IO_BITMAP_A, io_bitmap_a),
451 FIELD64(IO_BITMAP_B, io_bitmap_b),
452 FIELD64(MSR_BITMAP, msr_bitmap),
453 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
454 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
455 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
456 FIELD64(TSC_OFFSET, tsc_offset),
457 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
458 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
459 FIELD64(EPT_POINTER, ept_pointer),
460 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
461 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
462 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
463 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
464 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
465 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
466 FIELD64(GUEST_PDPTR0, guest_pdptr0),
467 FIELD64(GUEST_PDPTR1, guest_pdptr1),
468 FIELD64(GUEST_PDPTR2, guest_pdptr2),
469 FIELD64(GUEST_PDPTR3, guest_pdptr3),
470 FIELD64(HOST_IA32_PAT, host_ia32_pat),
471 FIELD64(HOST_IA32_EFER, host_ia32_efer),
472 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
473 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
474 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
475 FIELD(EXCEPTION_BITMAP, exception_bitmap),
476 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
477 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
478 FIELD(CR3_TARGET_COUNT, cr3_target_count),
479 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
480 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
481 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
482 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
483 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
484 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
485 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
486 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
487 FIELD(TPR_THRESHOLD, tpr_threshold),
488 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
489 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
490 FIELD(VM_EXIT_REASON, vm_exit_reason),
491 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
492 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
493 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
494 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
495 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
496 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
497 FIELD(GUEST_ES_LIMIT, guest_es_limit),
498 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
499 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
500 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
501 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
502 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
503 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
504 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
505 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
506 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
507 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
508 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
509 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
510 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
511 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
512 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
513 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
514 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
515 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
516 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
517 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
518 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
519 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
520 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
521 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
522 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
523 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
524 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
525 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
526 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
527 FIELD(EXIT_QUALIFICATION, exit_qualification),
528 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
529 FIELD(GUEST_CR0, guest_cr0),
530 FIELD(GUEST_CR3, guest_cr3),
531 FIELD(GUEST_CR4, guest_cr4),
532 FIELD(GUEST_ES_BASE, guest_es_base),
533 FIELD(GUEST_CS_BASE, guest_cs_base),
534 FIELD(GUEST_SS_BASE, guest_ss_base),
535 FIELD(GUEST_DS_BASE, guest_ds_base),
536 FIELD(GUEST_FS_BASE, guest_fs_base),
537 FIELD(GUEST_GS_BASE, guest_gs_base),
538 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
539 FIELD(GUEST_TR_BASE, guest_tr_base),
540 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
541 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
542 FIELD(GUEST_DR7, guest_dr7),
543 FIELD(GUEST_RSP, guest_rsp),
544 FIELD(GUEST_RIP, guest_rip),
545 FIELD(GUEST_RFLAGS, guest_rflags),
546 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
547 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
548 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
549 FIELD(HOST_CR0, host_cr0),
550 FIELD(HOST_CR3, host_cr3),
551 FIELD(HOST_CR4, host_cr4),
552 FIELD(HOST_FS_BASE, host_fs_base),
553 FIELD(HOST_GS_BASE, host_gs_base),
554 FIELD(HOST_TR_BASE, host_tr_base),
555 FIELD(HOST_GDTR_BASE, host_gdtr_base),
556 FIELD(HOST_IDTR_BASE, host_idtr_base),
557 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
558 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
559 FIELD(HOST_RSP, host_rsp),
560 FIELD(HOST_RIP, host_rip),
561};
562static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
563
564static inline short vmcs_field_to_offset(unsigned long field)
565{
566 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
567 return -1;
568 return vmcs_field_to_offset_table[field];
569}
570
a9d30f33
NHE		 571static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
572{
573 return to_vmx(vcpu)->nested.current_vmcs12;
574}
575
576static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
577{
578 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
579 if (is_error_page(page)) {
580 kvm_release_page_clean(page);
581 return NULL;
582 }
583 return page;
584}
585
586static void nested_release_page(struct page *page)
587{
588 kvm_release_page_dirty(page);
589}
590
591static void nested_release_page_clean(struct page *page)
592{
593 kvm_release_page_clean(page);
594}
595
4e1096d2 596static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 597static void kvm_cpu_vmxon(u64 addr);
598static void kvm_cpu_vmxoff(void);
aff48baa 599static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 600static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
75880a01 601
6aa8b732
AK		 602static DEFINE_PER_CPU(struct vmcs *, vmxarea);
603static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 604/*
605 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
606 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
607 */
608static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 609static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 610
3e7c73e9
AK		 611static unsigned long *vmx_io_bitmap_a;
612static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 613static unsigned long *vmx_msr_bitmap_legacy;
614static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 615
110312c8
AK		 616static bool cpu_has_load_ia32_efer;
617
2384d2b3
SY		 618static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
619static DEFINE_SPINLOCK(vmx_vpid_lock);
620
1c3d14fe 621static struct vmcs_config {
6aa8b732
AK		 622 int size;
623 int order;
624 u32 revision_id;
1c3d14fe
YS		 625 u32 pin_based_exec_ctrl;
626 u32 cpu_based_exec_ctrl;
f78e0e2e 627 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 628 u32 vmexit_ctrl;
629 u32 vmentry_ctrl;
630} vmcs_config;
6aa8b732 631
efff9e53 632static struct vmx_capability {
d56f546d
SY		 633 u32 ept;
634 u32 vpid;
635} vmx_capability;
636
6aa8b732
AK		 637#define VMX_SEGMENT_FIELD(seg) \
638 [VCPU_SREG_##seg] = { \
639 .selector = GUEST_##seg##_SELECTOR, \
640 .base = GUEST_##seg##_BASE, \
641 .limit = GUEST_##seg##_LIMIT, \
642 .ar_bytes = GUEST_##seg##_AR_BYTES, \
643 }
644
645static struct kvm_vmx_segment_field {
646 unsigned selector;
647 unsigned base;
648 unsigned limit;
649 unsigned ar_bytes;
650} kvm_vmx_segment_fields[] = {
651 VMX_SEGMENT_FIELD(CS),
652 VMX_SEGMENT_FIELD(DS),
653 VMX_SEGMENT_FIELD(ES),
654 VMX_SEGMENT_FIELD(FS),
655 VMX_SEGMENT_FIELD(GS),
656 VMX_SEGMENT_FIELD(SS),
657 VMX_SEGMENT_FIELD(TR),
658 VMX_SEGMENT_FIELD(LDTR),
659};
660
26bb0981
AK		 661static u64 host_efer;
662
6de4f3ad
AK		 663static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
664
4d56c8a7 665/*
8c06585d 666 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 667 * away by decrementing the array size.
668 */
6aa8b732 669static const u32 vmx_msr_index[] = {
05b3e0c2 670#ifdef CONFIG_X86_64
44ea2b17 671 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 672#endif
8c06585d 673 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 674};
9d8f549d 675#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 676
31299944 677static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 678{
679 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
680 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 681 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 682}
683
31299944 684static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 685{
686 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
687 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 688 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 689}
690
31299944 691static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 692{
693 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
694 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 695 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 696}
697
31299944 698static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 699{
700 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
701 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
702}
703
31299944 704static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 705{
706 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
707 INTR_INFO_VALID_MASK)) ==
708 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
709}
710
31299944 711static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 712{
04547156 713 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 714}
715
31299944 716static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 717{
04547156 718 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 719}
720
31299944 721static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 722{
04547156 723 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 724}
725
31299944 726static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 727{
04547156
SY		 728 return vmcs_config.cpu_based_exec_ctrl &
729 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 730}
731
774ead3a 732static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 733{
04547156
SY		 734 return vmcs_config.cpu_based_2nd_exec_ctrl &
735 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
736}
737
738static inline bool cpu_has_vmx_flexpriority(void)
739{
740 return cpu_has_vmx_tpr_shadow() &&
741 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 742}
743
e799794e
MT		 744static inline bool cpu_has_vmx_ept_execute_only(void)
745{
31299944 746 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 747}
748
749static inline bool cpu_has_vmx_eptp_uncacheable(void)
750{
31299944 751 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 752}
753
754static inline bool cpu_has_vmx_eptp_writeback(void)
755{
31299944 756 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 757}
758
759static inline bool cpu_has_vmx_ept_2m_page(void)
760{
31299944 761 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 762}
763
878403b7
SY		 764static inline bool cpu_has_vmx_ept_1g_page(void)
765{
31299944 766 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 767}
768
4bc9b982
SY		 769static inline bool cpu_has_vmx_ept_4levels(void)
770{
771 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
772}
773
31299944 774static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 775{
31299944 776 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 777}
778
31299944 779static inline bool cpu_has_vmx_invept_context(void)
d56f546d 780{
31299944 781 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 782}
783
31299944 784static inline bool cpu_has_vmx_invept_global(void)
d56f546d 785{
31299944 786 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 787}
788
518c8aee
GJ		 789static inline bool cpu_has_vmx_invvpid_single(void)
790{
791 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
792}
793
b9d762fa
GJ		 794static inline bool cpu_has_vmx_invvpid_global(void)
795{
796 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
797}
798
31299944 799static inline bool cpu_has_vmx_ept(void)
d56f546d 800{
04547156
SY		 801 return vmcs_config.cpu_based_2nd_exec_ctrl &
802 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 803}
804
31299944 805static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 806{
807 return vmcs_config.cpu_based_2nd_exec_ctrl &
808 SECONDARY_EXEC_UNRESTRICTED_GUEST;
809}
810
31299944 811static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 812{
813 return vmcs_config.cpu_based_2nd_exec_ctrl &
814 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
815}
816
31299944 817static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 818{
6d3e435e 819 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 820}
821
31299944 822static inline bool cpu_has_vmx_vpid(void)
2384d2b3 823{
04547156
SY		 824 return vmcs_config.cpu_based_2nd_exec_ctrl &
825 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 826}
827
31299944 828static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 829{
830 return vmcs_config.cpu_based_2nd_exec_ctrl &
831 SECONDARY_EXEC_RDTSCP;
832}
833
31299944 834static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 835{
836 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
837}
838
f5f48ee1
SY		 839static inline bool cpu_has_vmx_wbinvd_exit(void)
840{
841 return vmcs_config.cpu_based_2nd_exec_ctrl &
842 SECONDARY_EXEC_WBINVD_EXITING;
843}
844
04547156
SY		 845static inline bool report_flexpriority(void)
846{
847 return flexpriority_enabled;
848}
849
8b9cf98c 850static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 851{
852 int i;
853
a2fa3e9f 854 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 855 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 856 return i;
857 return -1;
858}
859
2384d2b3
SY		 860static inline void __invvpid(int ext, u16 vpid, gva_t gva)
861{
862 struct {
863 u64 vpid : 16;
864 u64 rsvd : 48;
865 u64 gva;
866 } operand = { vpid, 0, gva };
867
4ecac3fd 868 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 869 /* CF==1 or ZF==1 --> rc = -1 */
870 "; ja 1f ; ud2 ; 1:"
871 : : "a"(&operand), "c"(ext) : "cc", "memory");
872}
873
1439442c
SY		 874static inline void __invept(int ext, u64 eptp, gpa_t gpa)
875{
876 struct {
877 u64 eptp, gpa;
878 } operand = {eptp, gpa};
879
4ecac3fd 880 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 881 /* CF==1 or ZF==1 --> rc = -1 */
882 "; ja 1f ; ud2 ; 1:\n"
883 : : "a" (&operand), "c" (ext) : "cc", "memory");
884}
885
26bb0981 886static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 887{
888 int i;
889
8b9cf98c 890 i = __find_msr_index(vmx, msr);
a75beee6 891 if (i >= 0)
a2fa3e9f 892 return &vmx->guest_msrs[i];
8b6d44c7 893 return NULL;
7725f0ba
AK		 894}
895
6aa8b732
AK		 896static void vmcs_clear(struct vmcs *vmcs)
897{
898 u64 phys_addr = __pa(vmcs);
899 u8 error;
900
4ecac3fd 901 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 902 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 903 : "cc", "memory");
904 if (error)
905 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
906 vmcs, phys_addr);
907}
908
d462b819
NHE		 909static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
910{
911 vmcs_clear(loaded_vmcs->vmcs);
912 loaded_vmcs->cpu = -1;
913 loaded_vmcs->launched = 0;
914}
915
7725b894
DX		 916static void vmcs_load(struct vmcs *vmcs)
917{
918 u64 phys_addr = __pa(vmcs);
919 u8 error;
920
921 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 922 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 923 : "cc", "memory");
924 if (error)
925 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
926 vmcs, phys_addr);
927}
928
d462b819 929static void __loaded_vmcs_clear(void *arg)
6aa8b732 930{
d462b819 931 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 932 int cpu = raw_smp_processor_id();
6aa8b732 933
d462b819
NHE		 934 if (loaded_vmcs->cpu != cpu)
935 return; /* vcpu migration can race with cpu offline */
936 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 937 per_cpu(current_vmcs, cpu) = NULL;
d462b819
NHE		 938 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
939 loaded_vmcs_init(loaded_vmcs);
6aa8b732
AK		 940}
941
d462b819 942static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 943{
d462b819
NHE		 944 if (loaded_vmcs->cpu != -1)
945 smp_call_function_single(
946 loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 947}
948
1760dd49 949static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 950{
951 if (vmx->vpid == 0)
952 return;
953
518c8aee
GJ		 954 if (cpu_has_vmx_invvpid_single())
955 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 956}
957
b9d762fa
GJ		 958static inline void vpid_sync_vcpu_global(void)
959{
960 if (cpu_has_vmx_invvpid_global())
961 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
962}
963
964static inline void vpid_sync_context(struct vcpu_vmx *vmx)
965{
966 if (cpu_has_vmx_invvpid_single())
1760dd49 967 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 968 else
969 vpid_sync_vcpu_global();
970}
971
1439442c
SY		 972static inline void ept_sync_global(void)
973{
974 if (cpu_has_vmx_invept_global())
975 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
976}
977
978static inline void ept_sync_context(u64 eptp)
979{
089d034e 980 if (enable_ept) {
1439442c
SY		 981 if (cpu_has_vmx_invept_context())
982 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
983 else
984 ept_sync_global();
985 }
986}
987
988static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
989{
089d034e 990 if (enable_ept) {
1439442c
SY		 991 if (cpu_has_vmx_invept_individual_addr())
992 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
993 eptp, gpa);
994 else
995 ept_sync_context(eptp);
996 }
997}
998
96304217 999static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1000{
5e520e62 1001 unsigned long value;
6aa8b732 1002
5e520e62
AK		 1003 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1004 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1005 return value;
1006}
1007
96304217 1008static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1009{
1010 return vmcs_readl(field);
1011}
1012
96304217 1013static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1014{
1015 return vmcs_readl(field);
1016}
1017
96304217 1018static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1019{
05b3e0c2 1020#ifdef CONFIG_X86_64
6aa8b732
AK		 1021 return vmcs_readl(field);
1022#else
1023 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1024#endif
1025}
1026
e52de1b8
AK		 1027static noinline void vmwrite_error(unsigned long field, unsigned long value)
1028{
1029 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1030 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1031 dump_stack();
1032}
1033
6aa8b732
AK		 1034static void vmcs_writel(unsigned long field, unsigned long value)
1035{
1036 u8 error;
1037
4ecac3fd 1038 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1039 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1040 if (unlikely(error))
1041 vmwrite_error(field, value);
6aa8b732
AK		 1042}
1043
1044static void vmcs_write16(unsigned long field, u16 value)
1045{
1046 vmcs_writel(field, value);
1047}
1048
1049static void vmcs_write32(unsigned long field, u32 value)
1050{
1051 vmcs_writel(field, value);
1052}
1053
1054static void vmcs_write64(unsigned long field, u64 value)
1055{
6aa8b732 1056 vmcs_writel(field, value);
7682f2d0 1057#ifndef CONFIG_X86_64
6aa8b732
AK		 1058 asm volatile ("");
1059 vmcs_writel(field+1, value >> 32);
1060#endif
1061}
1062
2ab455cc
AL		 1063static void vmcs_clear_bits(unsigned long field, u32 mask)
1064{
1065 vmcs_writel(field, vmcs_readl(field) & ~mask);
1066}
1067
1068static void vmcs_set_bits(unsigned long field, u32 mask)
1069{
1070 vmcs_writel(field, vmcs_readl(field) | mask);
1071}
1072
2fb92db1
AK		 1073static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1074{
1075 vmx->segment_cache.bitmask = 0;
1076}
1077
1078static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1079 unsigned field)
1080{
1081 bool ret;
1082 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1083
1084 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1085 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1086 vmx->segment_cache.bitmask = 0;
1087 }
1088 ret = vmx->segment_cache.bitmask & mask;
1089 vmx->segment_cache.bitmask |= mask;
1090 return ret;
1091}
1092
1093static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1094{
1095 u16 *p = &vmx->segment_cache.seg[seg].selector;
1096
1097 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1098 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1099 return *p;
1100}
1101
1102static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1103{
1104 ulong *p = &vmx->segment_cache.seg[seg].base;
1105
1106 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1107 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1108 return *p;
1109}
1110
1111static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1112{
1113 u32 *p = &vmx->segment_cache.seg[seg].limit;
1114
1115 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1116 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1117 return *p;
1118}
1119
1120static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1121{
1122 u32 *p = &vmx->segment_cache.seg[seg].ar;
1123
1124 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1125 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1126 return *p;
1127}
1128
abd3f2d6
AK		 1129static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1130{
1131 u32 eb;
1132
fd7373cc
JK		 1133 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1134 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1135 if ((vcpu->guest_debug &
1136 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1137 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1138 eb |= 1u << BP_VECTOR;
7ffd92c5 1139 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1140 eb = ~0;
089d034e 1141 if (enable_ept)
1439442c 1142 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1143 if (vcpu->fpu_active)
1144 eb &= ~(1u << NM_VECTOR);
abd3f2d6
AK		 1145 vmcs_write32(EXCEPTION_BITMAP, eb);
1146}
1147
61d2ef2c
AK		 1148static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1149{
1150 unsigned i;
1151 struct msr_autoload *m = &vmx->msr_autoload;
1152
110312c8
AK		 1153 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1154 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1155 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1156 return;
1157 }
1158
61d2ef2c
AK		 1159 for (i = 0; i < m->nr; ++i)
1160 if (m->guest[i].index == msr)
1161 break;
1162
1163 if (i == m->nr)
1164 return;
1165 --m->nr;
1166 m->guest[i] = m->guest[m->nr];
1167 m->host[i] = m->host[m->nr];
1168 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1169 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1170}
1171
1172static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1173 u64 guest_val, u64 host_val)
1174{
1175 unsigned i;
1176 struct msr_autoload *m = &vmx->msr_autoload;
1177
110312c8
AK		 1178 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1179 vmcs_write64(GUEST_IA32_EFER, guest_val);
1180 vmcs_write64(HOST_IA32_EFER, host_val);
1181 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1182 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1183 return;
1184 }
1185
61d2ef2c
AK		 1186 for (i = 0; i < m->nr; ++i)
1187 if (m->guest[i].index == msr)
1188 break;
1189
1190 if (i == m->nr) {
1191 ++m->nr;
1192 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1193 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1194 }
1195
1196 m->guest[i].index = msr;
1197 m->guest[i].value = guest_val;
1198 m->host[i].index = msr;
1199 m->host[i].value = host_val;
1200}
1201
33ed6329
AK		 1202static void reload_tss(void)
1203{
33ed6329
AK		 1204 /*
1205 * VT restores TR but not its size. Useless.
1206 */
d359192f 1207 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1208 struct desc_struct *descs;
33ed6329 1209
d359192f 1210 descs = (void *)gdt->address;
33ed6329
AK		 1211 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1212 load_TR_desc();
33ed6329
AK		 1213}
1214
92c0d900 1215static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1216{
3a34a881 1217 u64 guest_efer;
51c6cf66
AK		 1218 u64 ignore_bits;
1219
f6801dff 1220 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1221
51c6cf66
AK		 1222 /*
1223 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1224 * outside long mode
1225 */
1226 ignore_bits = EFER_NX | EFER_SCE;
1227#ifdef CONFIG_X86_64
1228 ignore_bits |= EFER_LMA | EFER_LME;
1229 /* SCE is meaningful only in long mode on Intel */
1230 if (guest_efer & EFER_LMA)
1231 ignore_bits &= ~(u64)EFER_SCE;
1232#endif
51c6cf66
AK		 1233 guest_efer &= ~ignore_bits;
1234 guest_efer |= host_efer & ignore_bits;
26bb0981 1235 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1236 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1237
1238 clear_atomic_switch_msr(vmx, MSR_EFER);
1239 /* On ept, can't emulate nx, and must switch nx atomically */
1240 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1241 guest_efer = vmx->vcpu.arch.efer;
1242 if (!(guest_efer & EFER_LMA))
1243 guest_efer &= ~EFER_LME;
1244 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1245 return false;
1246 }
1247
26bb0981 1248 return true;
51c6cf66
AK		 1249}
1250
2d49ec72
GN		 1251static unsigned long segment_base(u16 selector)
1252{
d359192f 1253 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1254 struct desc_struct *d;
1255 unsigned long table_base;
1256 unsigned long v;
1257
1258 if (!(selector & ~3))
1259 return 0;
1260
d359192f 1261 table_base = gdt->address;
2d49ec72
GN		 1262
1263 if (selector & 4) { /* from ldt */
1264 u16 ldt_selector = kvm_read_ldt();
1265
1266 if (!(ldt_selector & ~3))
1267 return 0;
1268
1269 table_base = segment_base(ldt_selector);
1270 }
1271 d = (struct desc_struct *)(table_base + (selector & ~7));
1272 v = get_desc_base(d);
1273#ifdef CONFIG_X86_64
1274 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1275 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1276#endif
1277 return v;
1278}
1279
1280static inline unsigned long kvm_read_tr_base(void)
1281{
1282 u16 tr;
1283 asm("str %0" : "=g"(tr));
1284 return segment_base(tr);
1285}
1286
04d2cc77 1287static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1288{
04d2cc77 1289 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1290 int i;
04d2cc77 1291
a2fa3e9f 1292 if (vmx->host_state.loaded)
33ed6329
AK		 1293 return;
1294
a2fa3e9f 1295 vmx->host_state.loaded = 1;
33ed6329
AK		 1296 /*
1297 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1298 * allow segment selectors with cpl > 0 or ti == 1.
1299 */
d6e88aec 1300 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1301 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1302 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1303 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1304 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1305 vmx->host_state.fs_reload_needed = 0;
1306 } else {
33ed6329 1307 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1308 vmx->host_state.fs_reload_needed = 1;
33ed6329 1309 }
9581d442 1310 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1311 if (!(vmx->host_state.gs_sel & 7))
1312 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1313 else {
1314 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1315 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1316 }
1317
1318#ifdef CONFIG_X86_64
1319 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1320 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1321#else
a2fa3e9f
GH		 1322 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1323 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1324#endif
707c0874
AK		 1325
1326#ifdef CONFIG_X86_64
c8770e7b
AK		 1327 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1328 if (is_long_mode(&vmx->vcpu))
44ea2b17 1329 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1330#endif
26bb0981
AK		 1331 for (i = 0; i < vmx->save_nmsrs; ++i)
1332 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1333 vmx->guest_msrs[i].data,
1334 vmx->guest_msrs[i].mask);
33ed6329
AK		 1335}
1336
a9b21b62 1337static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1338{
a2fa3e9f 1339 if (!vmx->host_state.loaded)
33ed6329
AK		 1340 return;
1341
e1beb1d3 1342 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1343 vmx->host_state.loaded = 0;
c8770e7b
AK		 1344#ifdef CONFIG_X86_64
1345 if (is_long_mode(&vmx->vcpu))
1346 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1347#endif
152d3f2f 1348 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1349 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1350#ifdef CONFIG_X86_64
9581d442 1351 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1352#else
1353 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1354#endif
33ed6329 1355 }
0a77fe4c
AK		 1356 if (vmx->host_state.fs_reload_needed)
1357 loadsegment(fs, vmx->host_state.fs_sel);
152d3f2f 1358 reload_tss();
44ea2b17 1359#ifdef CONFIG_X86_64
c8770e7b 1360 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1361#endif
1c11e713
AK		 1362 if (current_thread_info()->status & TS_USEDFPU)
1363 clts();
3444d7da 1364 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1365}
1366
a9b21b62
AK		 1367static void vmx_load_host_state(struct vcpu_vmx *vmx)
1368{
1369 preempt_disable();
1370 __vmx_load_host_state(vmx);
1371 preempt_enable();
1372}
1373
6aa8b732
AK		 1374/*
1375 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1376 * vcpu mutex is already taken.
1377 */
15ad7146 1378static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1379{
a2fa3e9f 1380 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1381 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1382
4610c9cc
DX		 1383 if (!vmm_exclusive)
1384 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1385 else if (vmx->loaded_vmcs->cpu != cpu)
1386 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1387
d462b819
NHE		 1388 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1389 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1390 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1391 }
1392
d462b819 1393 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1394 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1395 unsigned long sysenter_esp;
1396
a8eeb04a 1397 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1398 local_irq_disable();
d462b819
NHE		 1399 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1400 &per_cpu(loaded_vmcss_on_cpu, cpu));
92fe13be
DX		 1401 local_irq_enable();
1402
6aa8b732
AK		 1403 /*
1404 * Linux uses per-cpu TSS and GDT, so set these when switching
1405 * processors.
1406 */
d6e88aec 1407 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1408 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1409
1410 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1411 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1412 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1413 }
6aa8b732
AK		 1414}
1415
1416static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1417{
a9b21b62 1418 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1419 if (!vmm_exclusive) {
d462b819
NHE		 1420 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1421 vcpu->cpu = -1;
4610c9cc
DX		 1422 kvm_cpu_vmxoff();
1423 }
6aa8b732
AK		 1424}
1425
5fd86fcf
AK		 1426static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1427{
81231c69
AK		 1428 ulong cr0;
1429
5fd86fcf
AK		 1430 if (vcpu->fpu_active)
1431 return;
1432 vcpu->fpu_active = 1;
81231c69
AK		 1433 cr0 = vmcs_readl(GUEST_CR0);
1434 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1435 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1436 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1437 update_exception_bitmap(vcpu);
edcafe3c
AK		 1438 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1439 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1440}
1441
edcafe3c
AK		 1442static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1443
5fd86fcf
AK		 1444static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1445{
edcafe3c 1446 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1447 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1448 update_exception_bitmap(vcpu);
edcafe3c
AK		 1449 vcpu->arch.cr0_guest_owned_bits = 0;
1450 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1451 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1452}
1453
6aa8b732
AK		 1454static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1455{
78ac8b47 1456 unsigned long rflags, save_rflags;
345dcaa8 1457
6de12732
AK		 1458 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1459 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1460 rflags = vmcs_readl(GUEST_RFLAGS);
1461 if (to_vmx(vcpu)->rmode.vm86_active) {
1462 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1463 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1464 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1465 }
1466 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1467 }
6de12732 1468 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1469}
1470
1471static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1472{
6de12732 1473 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
69c73028 1474 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6de12732 1475 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1476 if (to_vmx(vcpu)->rmode.vm86_active) {
1477 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1478 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1479 }
6aa8b732
AK		 1480 vmcs_writel(GUEST_RFLAGS, rflags);
1481}
1482
2809f5d2
GC		 1483static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1484{
1485 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1486 int ret = 0;
1487
1488 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1489 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1490 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1491 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1492
1493 return ret & mask;
1494}
1495
1496static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1497{
1498 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1499 u32 interruptibility = interruptibility_old;
1500
1501 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1502
48005f64 1503 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1504 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1505 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1506 interruptibility |= GUEST_INTR_STATE_STI;
1507
1508 if ((interruptibility != interruptibility_old))
1509 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1510}
1511
6aa8b732
AK		 1512static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1513{
1514 unsigned long rip;
6aa8b732 1515
5fdbf976 1516 rip = kvm_rip_read(vcpu);
6aa8b732 1517 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1518 kvm_rip_write(vcpu, rip);
6aa8b732 1519
2809f5d2
GC		 1520 /* skipping an emulated instruction also counts */
1521 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1522}
1523
443381a8
AL		 1524static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1525{
1526 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1527 * explicitly skip the instruction because if the HLT state is set, then
1528 * the instruction is already executing and RIP has already been
1529 * advanced. */
1530 if (!yield_on_hlt &&
1531 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1532 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1533}
1534
298101da 1535static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1536 bool has_error_code, u32 error_code,
1537 bool reinject)
298101da 1538{
77ab6db0 1539 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1540 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1541
8ab2d2e2 1542 if (has_error_code) {
77ab6db0 1543 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1544 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1545 }
77ab6db0 1546
7ffd92c5 1547 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1548 int inc_eip = 0;
1549 if (kvm_exception_is_soft(nr))
1550 inc_eip = vcpu->arch.event_exit_inst_len;
1551 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1552 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1553 return;
1554 }
1555
66fd3f7f
GN		 1556 if (kvm_exception_is_soft(nr)) {
1557 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1558 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1559 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1560 } else
1561 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1562
1563 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
443381a8 1564 vmx_clear_hlt(vcpu);
298101da
AK		 1565}
1566
4e47c7a6
SY		 1567static bool vmx_rdtscp_supported(void)
1568{
1569 return cpu_has_vmx_rdtscp();
1570}
1571
a75beee6
ED		 1572/*
1573 * Swap MSR entry in host/guest MSR entry array.
1574 */
8b9cf98c 1575static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1576{
26bb0981 1577 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1578
1579 tmp = vmx->guest_msrs[to];
1580 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1581 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1582}
1583
e38aea3e
AK		 1584/*
1585 * Set up the vmcs to automatically save and restore system
1586 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1587 * mode, as fiddling with msrs is very expensive.
1588 */
8b9cf98c 1589static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1590{
26bb0981 1591 int save_nmsrs, index;
5897297b 1592 unsigned long *msr_bitmap;
e38aea3e 1593
33f9c505 1594 vmx_load_host_state(vmx);
a75beee6
ED		 1595 save_nmsrs = 0;
1596#ifdef CONFIG_X86_64
8b9cf98c 1597 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1598 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1599 if (index >= 0)
8b9cf98c
RR		 1600 move_msr_up(vmx, index, save_nmsrs++);
1601 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1602 if (index >= 0)
8b9cf98c
RR		 1603 move_msr_up(vmx, index, save_nmsrs++);
1604 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1605 if (index >= 0)
8b9cf98c 1606 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1607 index = __find_msr_index(vmx, MSR_TSC_AUX);
1608 if (index >= 0 && vmx->rdtscp_enabled)
1609 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1610 /*
8c06585d 1611 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1612 * if efer.sce is enabled.
1613 */
8c06585d 1614 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1615 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1616 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1617 }
1618#endif
92c0d900
AK		 1619 index = __find_msr_index(vmx, MSR_EFER);
1620 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1621 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1622
26bb0981 1623 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1624
1625 if (cpu_has_vmx_msr_bitmap()) {
1626 if (is_long_mode(&vmx->vcpu))
1627 msr_bitmap = vmx_msr_bitmap_longmode;
1628 else
1629 msr_bitmap = vmx_msr_bitmap_legacy;
1630
1631 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1632 }
e38aea3e
AK		 1633}
1634
6aa8b732
AK		 1635/*
1636 * reads and returns guest's timestamp counter "register"
1637 * guest_tsc = host_tsc + tsc_offset -- 21.3
1638 */
1639static u64 guest_read_tsc(void)
1640{
1641 u64 host_tsc, tsc_offset;
1642
1643 rdtscll(host_tsc);
1644 tsc_offset = vmcs_read64(TSC_OFFSET);
1645 return host_tsc + tsc_offset;
1646}
1647
4051b188
JR		 1648/*
1649 * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1650 * ioctl. In this case the call-back should update internal vmx state to make
1651 * the changes effective.
1652 */
1653static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1654{
1655 /* Nothing to do here */
1656}
1657
6aa8b732 1658/*
99e3e30a 1659 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1660 */
99e3e30a 1661static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1662{
f4e1b3c8 1663 vmcs_write64(TSC_OFFSET, offset);
6aa8b732
AK		 1664}
1665
e48672fa
ZA		 1666static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1667{
1668 u64 offset = vmcs_read64(TSC_OFFSET);
1669 vmcs_write64(TSC_OFFSET, offset + adjustment);
1670}
1671
857e4099
JR		 1672static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1673{
1674 return target_tsc - native_read_tsc();
1675}
1676
801d3424
NHE		 1677static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1678{
1679 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1680 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1681}
1682
1683/*
1684 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1685 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1686 * all guests if the "nested" module option is off, and can also be disabled
1687 * for a single guest by disabling its VMX cpuid bit.
1688 */
1689static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1690{
1691 return nested && guest_cpuid_has_vmx(vcpu);
1692}
1693
b87a51ae
NHE		 1694/*
1695 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1696 * returned for the various VMX controls MSRs when nested VMX is enabled.
1697 * The same values should also be used to verify that vmcs12 control fields are
1698 * valid during nested entry from L1 to L2.
1699 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1700 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1701 * bit in the high half is on if the corresponding bit in the control field
1702 * may be on. See also vmx_control_verify().
1703 * TODO: allow these variables to be modified (downgraded) by module options
1704 * or other means.
1705 */
1706static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1707static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1708static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1709static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1710static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1711static __init void nested_vmx_setup_ctls_msrs(void)
1712{
1713 /*
1714 * Note that as a general rule, the high half of the MSRs (bits in
1715 * the control fields which may be 1) should be initialized by the
1716 * intersection of the underlying hardware's MSR (i.e., features which
1717 * can be supported) and the list of features we want to expose -
1718 * because they are known to be properly supported in our code.
1719 * Also, usually, the low half of the MSRs (bits which must be 1) can
1720 * be set to 0, meaning that L1 may turn off any of these bits. The
1721 * reason is that if one of these bits is necessary, it will appear
1722 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1723 * fields of vmcs01 and vmcs02, will turn these bits off - and
1724 * nested_vmx_exit_handled() will not pass related exits to L1.
1725 * These rules have exceptions below.
1726 */
1727
1728 /* pin-based controls */
1729 /*
1730 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1731 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1732 */
1733 nested_vmx_pinbased_ctls_low = 0x16 ;
1734 nested_vmx_pinbased_ctls_high = 0x16 |
1735 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1736 PIN_BASED_VIRTUAL_NMIS;
1737
1738 /* exit controls */
1739 nested_vmx_exit_ctls_low = 0;
1740#ifdef CONFIG_X86_64
1741 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1742#else
1743 nested_vmx_exit_ctls_high = 0;
1744#endif
1745
1746 /* entry controls */
1747 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1748 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1749 nested_vmx_entry_ctls_low = 0;
1750 nested_vmx_entry_ctls_high &=
1751 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1752
1753 /* cpu-based controls */
1754 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1755 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1756 nested_vmx_procbased_ctls_low = 0;
1757 nested_vmx_procbased_ctls_high &=
1758 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1759 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1760 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1761 CPU_BASED_CR3_STORE_EXITING |
1762#ifdef CONFIG_X86_64
1763 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1764#endif
1765 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1766 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1767 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1768 /*
1769 * We can allow some features even when not supported by the
1770 * hardware. For example, L1 can specify an MSR bitmap - and we
1771 * can use it to avoid exits to L1 - even when L0 runs L2
1772 * without MSR bitmaps.
1773 */
1774 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1775
1776 /* secondary cpu-based controls */
1777 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1778 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1779 nested_vmx_secondary_ctls_low = 0;
1780 nested_vmx_secondary_ctls_high &=
1781 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1782}
1783
1784static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1785{
1786 /*
1787 * Bits 0 in high must be 0, and bits 1 in low must be 1.
1788 */
1789 return ((control & high) | low) == control;
1790}
1791
1792static inline u64 vmx_control_msr(u32 low, u32 high)
1793{
1794 return low | ((u64)high << 32);
1795}
1796
1797/*
1798 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1799 * also let it use VMX-specific MSRs.
1800 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1801 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1802 * like all other MSRs).
1803 */
1804static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1805{
1806 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
1807 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
1808 /*
1809 * According to the spec, processors which do not support VMX
1810 * should throw a #GP(0) when VMX capability MSRs are read.
1811 */
1812 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
1813 return 1;
1814 }
1815
1816 switch (msr_index) {
1817 case MSR_IA32_FEATURE_CONTROL:
1818 *pdata = 0;
1819 break;
1820 case MSR_IA32_VMX_BASIC:
1821 /*
1822 * This MSR reports some information about VMX support. We
1823 * should return information about the VMX we emulate for the
1824 * guest, and the VMCS structure we give it - not about the
1825 * VMX support of the underlying hardware.
1826 */
1827 *pdata = VMCS12_REVISION |
1828 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
1829 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
1830 break;
1831 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
1832 case MSR_IA32_VMX_PINBASED_CTLS:
1833 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
1834 nested_vmx_pinbased_ctls_high);
1835 break;
1836 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
1837 case MSR_IA32_VMX_PROCBASED_CTLS:
1838 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
1839 nested_vmx_procbased_ctls_high);
1840 break;
1841 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
1842 case MSR_IA32_VMX_EXIT_CTLS:
1843 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
1844 nested_vmx_exit_ctls_high);
1845 break;
1846 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
1847 case MSR_IA32_VMX_ENTRY_CTLS:
1848 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
1849 nested_vmx_entry_ctls_high);
1850 break;
1851 case MSR_IA32_VMX_MISC:
1852 *pdata = 0;
1853 break;
1854 /*
1855 * These MSRs specify bits which the guest must keep fixed (on or off)
1856 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
1857 * We picked the standard core2 setting.
1858 */
1859#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
1860#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
1861 case MSR_IA32_VMX_CR0_FIXED0:
1862 *pdata = VMXON_CR0_ALWAYSON;
1863 break;
1864 case MSR_IA32_VMX_CR0_FIXED1:
1865 *pdata = -1ULL;
1866 break;
1867 case MSR_IA32_VMX_CR4_FIXED0:
1868 *pdata = VMXON_CR4_ALWAYSON;
1869 break;
1870 case MSR_IA32_VMX_CR4_FIXED1:
1871 *pdata = -1ULL;
1872 break;
1873 case MSR_IA32_VMX_VMCS_ENUM:
1874 *pdata = 0x1f;
1875 break;
1876 case MSR_IA32_VMX_PROCBASED_CTLS2:
1877 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
1878 nested_vmx_secondary_ctls_high);
1879 break;
1880 case MSR_IA32_VMX_EPT_VPID_CAP:
1881 /* Currently, no nested ept or nested vpid */
1882 *pdata = 0;
1883 break;
1884 default:
1885 return 0;
1886 }
1887
1888 return 1;
1889}
1890
1891static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1892{
1893 if (!nested_vmx_allowed(vcpu))
1894 return 0;
1895
1896 if (msr_index == MSR_IA32_FEATURE_CONTROL)
1897 /* TODO: the right thing. */
1898 return 1;
1899 /*
1900 * No need to treat VMX capability MSRs specially: If we don't handle
1901 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
1902 */
1903 return 0;
1904}
1905
6aa8b732
AK		 1906/*
1907 * Reads an msr value (of 'msr_index') into 'pdata'.
1908 * Returns 0 on success, non-0 otherwise.
1909 * Assumes vcpu_load() was already called.
1910 */
1911static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1912{
1913 u64 data;
26bb0981 1914 struct shared_msr_entry *msr;
6aa8b732
AK		 1915
1916 if (!pdata) {
1917 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1918 return -EINVAL;
1919 }
1920
1921 switch (msr_index) {
05b3e0c2 1922#ifdef CONFIG_X86_64
6aa8b732
AK		 1923 case MSR_FS_BASE:
1924 data = vmcs_readl(GUEST_FS_BASE);
1925 break;
1926 case MSR_GS_BASE:
1927 data = vmcs_readl(GUEST_GS_BASE);
1928 break;
44ea2b17
AK		 1929 case MSR_KERNEL_GS_BASE:
1930 vmx_load_host_state(to_vmx(vcpu));
1931 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1932 break;
26bb0981 1933#endif
6aa8b732 1934 case MSR_EFER:
3bab1f5d 1935 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 1936 case MSR_IA32_TSC:
6aa8b732
AK		 1937 data = guest_read_tsc();
1938 break;
1939 case MSR_IA32_SYSENTER_CS:
1940 data = vmcs_read32(GUEST_SYSENTER_CS);
1941 break;
1942 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1943 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1944 break;
1945 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1946 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1947 break;
4e47c7a6
SY		 1948 case MSR_TSC_AUX:
1949 if (!to_vmx(vcpu)->rdtscp_enabled)
1950 return 1;
1951 /* Otherwise falls through */
6aa8b732 1952 default:
26bb0981 1953 vmx_load_host_state(to_vmx(vcpu));
b87a51ae
NHE		 1954 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
1955 return 0;
8b9cf98c 1956 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 1957 if (msr) {
542423b0 1958 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 1959 data = msr->data;
1960 break;
6aa8b732 1961 }
3bab1f5d 1962 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 1963 }
1964
1965 *pdata = data;
1966 return 0;
1967}
1968
1969/*
1970 * Writes msr value into into the appropriate "register".
1971 * Returns 0 on success, non-0 otherwise.
1972 * Assumes vcpu_load() was already called.
1973 */
1974static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1975{
a2fa3e9f 1976 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1977 struct shared_msr_entry *msr;
2cc51560
ED		 1978 int ret = 0;
1979
6aa8b732 1980 switch (msr_index) {
3bab1f5d 1981 case MSR_EFER:
a9b21b62 1982 vmx_load_host_state(vmx);
2cc51560 1983 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1984 break;
16175a79 1985#ifdef CONFIG_X86_64
6aa8b732 1986 case MSR_FS_BASE:
2fb92db1 1987 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 1988 vmcs_writel(GUEST_FS_BASE, data);
1989 break;
1990 case MSR_GS_BASE:
2fb92db1 1991 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 1992 vmcs_writel(GUEST_GS_BASE, data);
1993 break;
44ea2b17
AK		 1994 case MSR_KERNEL_GS_BASE:
1995 vmx_load_host_state(vmx);
1996 vmx->msr_guest_kernel_gs_base = data;
1997 break;
6aa8b732
AK		 1998#endif
1999 case MSR_IA32_SYSENTER_CS:
2000 vmcs_write32(GUEST_SYSENTER_CS, data);
2001 break;
2002 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2003 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2004 break;
2005 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2006 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2007 break;
af24a4e4 2008 case MSR_IA32_TSC:
99e3e30a 2009 kvm_write_tsc(vcpu, data);
6aa8b732 2010 break;
468d472f
SY		 2011 case MSR_IA32_CR_PAT:
2012 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2013 vmcs_write64(GUEST_IA32_PAT, data);
2014 vcpu->arch.pat = data;
2015 break;
2016 }
4e47c7a6
SY		 2017 ret = kvm_set_msr_common(vcpu, msr_index, data);
2018 break;
2019 case MSR_TSC_AUX:
2020 if (!vmx->rdtscp_enabled)
2021 return 1;
2022 /* Check reserved bit, higher 32 bits should be zero */
2023 if ((data >> 32) != 0)
2024 return 1;
2025 /* Otherwise falls through */
6aa8b732 2026 default:
b87a51ae
NHE		 2027 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2028 break;
8b9cf98c 2029 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2030 if (msr) {
542423b0 2031 vmx_load_host_state(vmx);
3bab1f5d
AK		 2032 msr->data = data;
2033 break;
6aa8b732 2034 }
2cc51560 2035 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 2036 }
2037
2cc51560 2038 return ret;
6aa8b732
AK		 2039}
2040
5fdbf976 2041static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2042{
5fdbf976
MT		 2043 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2044 switch (reg) {
2045 case VCPU_REGS_RSP:
2046 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2047 break;
2048 case VCPU_REGS_RIP:
2049 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2050 break;
6de4f3ad
AK		 2051 case VCPU_EXREG_PDPTR:
2052 if (enable_ept)
2053 ept_save_pdptrs(vcpu);
2054 break;
5fdbf976
MT		 2055 default:
2056 break;
2057 }
6aa8b732
AK		 2058}
2059
355be0b9 2060static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 2061{
ae675ef0
JK		 2062 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2063 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2064 else
2065 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2066
abd3f2d6 2067 update_exception_bitmap(vcpu);
6aa8b732
AK		 2068}
2069
2070static __init int cpu_has_kvm_support(void)
2071{
6210e37b 2072 return cpu_has_vmx();
6aa8b732
AK		 2073}
2074
2075static __init int vmx_disabled_by_bios(void)
2076{
2077 u64 msr;
2078
2079 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2080 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2081 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2082 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2083 && tboot_enabled())
2084 return 1;
23f3e991 2085 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2086 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2087 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2088 && !tboot_enabled()) {
2089 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2090 "activate TXT before enabling KVM\n");
cafd6659 2091 return 1;
f9335afe 2092 }
23f3e991
JC		 2093 /* launched w/o TXT and VMX disabled */
2094 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2095 && !tboot_enabled())
2096 return 1;
cafd6659
SW		 2097 }
2098
2099 return 0;
6aa8b732
AK		 2100}
2101
7725b894
DX		 2102static void kvm_cpu_vmxon(u64 addr)
2103{
2104 asm volatile (ASM_VMX_VMXON_RAX
2105 : : "a"(&addr), "m"(addr)
2106 : "memory", "cc");
2107}
2108
10474ae8 2109static int hardware_enable(void *garbage)
6aa8b732
AK		 2110{
2111 int cpu = raw_smp_processor_id();
2112 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2113 u64 old, test_bits;
6aa8b732 2114
10474ae8
AG		 2115 if (read_cr4() & X86_CR4_VMXE)
2116 return -EBUSY;
2117
d462b819 2118 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
6aa8b732 2119 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2120
2121 test_bits = FEATURE_CONTROL_LOCKED;
2122 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2123 if (tboot_enabled())
2124 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2125
2126 if ((old & test_bits) != test_bits) {
6aa8b732 2127 /* enable and lock */
cafd6659
SW		 2128 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2129 }
66aee91a 2130 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2131
4610c9cc
DX		 2132 if (vmm_exclusive) {
2133 kvm_cpu_vmxon(phys_addr);
2134 ept_sync_global();
2135 }
10474ae8 2136
3444d7da
AK		 2137 store_gdt(&__get_cpu_var(host_gdt));
2138
10474ae8 2139 return 0;
6aa8b732
AK		 2140}
2141
d462b819 2142static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2143{
2144 int cpu = raw_smp_processor_id();
d462b819 2145 struct loaded_vmcs *v, *n;
543e4243 2146
d462b819
NHE		 2147 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2148 loaded_vmcss_on_cpu_link)
2149 __loaded_vmcs_clear(v);
543e4243
AK		 2150}
2151
710ff4a8
EH		 2152
2153/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2154 * tricks.
2155 */
2156static void kvm_cpu_vmxoff(void)
6aa8b732 2157{
4ecac3fd 2158 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2159}
2160
710ff4a8
EH		 2161static void hardware_disable(void *garbage)
2162{
4610c9cc 2163 if (vmm_exclusive) {
d462b819 2164 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2165 kvm_cpu_vmxoff();
2166 }
7725b894 2167 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2168}
2169
1c3d14fe 2170static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2171 u32 msr, u32 *result)
1c3d14fe
YS		 2172{
2173 u32 vmx_msr_low, vmx_msr_high;
2174 u32 ctl = ctl_min | ctl_opt;
2175
2176 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2177
2178 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2179 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2180
2181 /* Ensure minimum (required) set of control bits are supported. */
2182 if (ctl_min & ~ctl)
002c7f7c 2183 return -EIO;
1c3d14fe
YS		 2184
2185 *result = ctl;
2186 return 0;
2187}
2188
110312c8
AK		 2189static __init bool allow_1_setting(u32 msr, u32 ctl)
2190{
2191 u32 vmx_msr_low, vmx_msr_high;
2192
2193 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2194 return vmx_msr_high & ctl;
2195}
2196
002c7f7c 2197static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2198{
2199 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2200 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2201 u32 _pin_based_exec_control = 0;
2202 u32 _cpu_based_exec_control = 0;
f78e0e2e 2203 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2204 u32 _vmexit_control = 0;
2205 u32 _vmentry_control = 0;
2206
2207 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 2208 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 2209 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2210 &_pin_based_exec_control) < 0)
002c7f7c 2211 return -EIO;
1c3d14fe 2212
443381a8 2213 min =
1c3d14fe
YS		 2214#ifdef CONFIG_X86_64
2215 CPU_BASED_CR8_LOAD_EXITING |
2216 CPU_BASED_CR8_STORE_EXITING |
2217#endif
d56f546d
SY		 2218 CPU_BASED_CR3_LOAD_EXITING |
2219 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2220 CPU_BASED_USE_IO_BITMAPS |
2221 CPU_BASED_MOV_DR_EXITING |
a7052897 2222 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2223 CPU_BASED_MWAIT_EXITING |
2224 CPU_BASED_MONITOR_EXITING |
a7052897 2225 CPU_BASED_INVLPG_EXITING;
443381a8
AL		 2226
2227 if (yield_on_hlt)
2228 min |= CPU_BASED_HLT_EXITING;
2229
f78e0e2e 2230 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2231 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2232 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2233 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2234 &_cpu_based_exec_control) < 0)
002c7f7c 2235 return -EIO;
6e5d865c
YS		 2236#ifdef CONFIG_X86_64
2237 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2238 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2239 ~CPU_BASED_CR8_STORE_EXITING;
2240#endif
f78e0e2e 2241 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2242 min2 = 0;
2243 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 2244 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2245 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2246 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2247 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 2248 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2249 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 2250 if (adjust_vmx_controls(min2, opt2,
2251 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2252 &_cpu_based_2nd_exec_control) < 0)
2253 return -EIO;
2254 }
2255#ifndef CONFIG_X86_64
2256 if (!(_cpu_based_2nd_exec_control &
2257 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2258 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2259#endif
d56f546d 2260 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2261 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2262 enabled */
5fff7d27
GN		 2263 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2264 CPU_BASED_CR3_STORE_EXITING |
2265 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2266 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2267 vmx_capability.ept, vmx_capability.vpid);
2268 }
1c3d14fe
YS		 2269
2270 min = 0;
2271#ifdef CONFIG_X86_64
2272 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2273#endif
468d472f 2274 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 2275 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2276 &_vmexit_control) < 0)
002c7f7c 2277 return -EIO;
1c3d14fe 2278
468d472f
SY		 2279 min = 0;
2280 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2281 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2282 &_vmentry_control) < 0)
002c7f7c 2283 return -EIO;
6aa8b732 2284
c68876fd 2285 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2286
2287 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2288 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2289 return -EIO;
1c3d14fe
YS		 2290
2291#ifdef CONFIG_X86_64
2292 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2293 if (vmx_msr_high & (1u<<16))
002c7f7c 2294 return -EIO;
1c3d14fe
YS		 2295#endif
2296
2297 /* Require Write-Back (WB) memory type for VMCS accesses. */
2298 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2299 return -EIO;
1c3d14fe 2300
002c7f7c
YS		 2301 vmcs_conf->size = vmx_msr_high & 0x1fff;
2302 vmcs_conf->order = get_order(vmcs_config.size);
2303 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2304
002c7f7c
YS		 2305 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2306 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2307 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2308 vmcs_conf->vmexit_ctrl = _vmexit_control;
2309 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2310
110312c8
AK		 2311 cpu_has_load_ia32_efer =
2312 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2313 VM_ENTRY_LOAD_IA32_EFER)
2314 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2315 VM_EXIT_LOAD_IA32_EFER);
2316
1c3d14fe 2317 return 0;
c68876fd 2318}
6aa8b732
AK		 2319
2320static struct vmcs *alloc_vmcs_cpu(int cpu)
2321{
2322 int node = cpu_to_node(cpu);
2323 struct page *pages;
2324 struct vmcs *vmcs;
2325
6484eb3e 2326 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2327 if (!pages)
2328 return NULL;
2329 vmcs = page_address(pages);
1c3d14fe
YS		 2330 memset(vmcs, 0, vmcs_config.size);
2331 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2332 return vmcs;
2333}
2334
2335static struct vmcs *alloc_vmcs(void)
2336{
d3b2c338 2337 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2338}
2339
2340static void free_vmcs(struct vmcs *vmcs)
2341{
1c3d14fe 2342 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2343}
2344
d462b819
NHE		 2345/*
2346 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2347 */
2348static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2349{
2350 if (!loaded_vmcs->vmcs)
2351 return;
2352 loaded_vmcs_clear(loaded_vmcs);
2353 free_vmcs(loaded_vmcs->vmcs);
2354 loaded_vmcs->vmcs = NULL;
2355}
2356
39959588 2357static void free_kvm_area(void)
6aa8b732
AK		 2358{
2359 int cpu;
2360
3230bb47 2361 for_each_possible_cpu(cpu) {
6aa8b732 2362 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2363 per_cpu(vmxarea, cpu) = NULL;
2364 }
6aa8b732
AK		 2365}
2366
6aa8b732
AK		 2367static __init int alloc_kvm_area(void)
2368{
2369 int cpu;
2370
3230bb47 2371 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2372 struct vmcs *vmcs;
2373
2374 vmcs = alloc_vmcs_cpu(cpu);
2375 if (!vmcs) {
2376 free_kvm_area();
2377 return -ENOMEM;
2378 }
2379
2380 per_cpu(vmxarea, cpu) = vmcs;
2381 }
2382 return 0;
2383}
2384
2385static __init int hardware_setup(void)
2386{
002c7f7c
YS		 2387 if (setup_vmcs_config(&vmcs_config) < 0)
2388 return -EIO;
50a37eb4
JR		 2389
2390 if (boot_cpu_has(X86_FEATURE_NX))
2391 kvm_enable_efer_bits(EFER_NX);
2392
93ba03c2
SY		 2393 if (!cpu_has_vmx_vpid())
2394 enable_vpid = 0;
2395
4bc9b982
SY		 2396 if (!cpu_has_vmx_ept() ||
2397 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2398 enable_ept = 0;
3a624e29
NK		 2399 enable_unrestricted_guest = 0;
2400 }
2401
2402 if (!cpu_has_vmx_unrestricted_guest())
2403 enable_unrestricted_guest = 0;
93ba03c2
SY		 2404
2405 if (!cpu_has_vmx_flexpriority())
2406 flexpriority_enabled = 0;
2407
95ba8273
GN		 2408 if (!cpu_has_vmx_tpr_shadow())
2409 kvm_x86_ops->update_cr8_intercept = NULL;
2410
54dee993
MT		 2411 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2412 kvm_disable_largepages();
2413
4b8d54f9
ZE		 2414 if (!cpu_has_vmx_ple())
2415 ple_gap = 0;
2416
b87a51ae
NHE		 2417 if (nested)
2418 nested_vmx_setup_ctls_msrs();
2419
6aa8b732
AK		 2420 return alloc_kvm_area();
2421}
2422
2423static __exit void hardware_unsetup(void)
2424{
2425 free_kvm_area();
2426}
2427
6aa8b732
AK		 2428static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2429{
2430 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2431
6af11b9e 2432 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 2433 vmcs_write16(sf->selector, save->selector);
2434 vmcs_writel(sf->base, save->base);
2435 vmcs_write32(sf->limit, save->limit);
2436 vmcs_write32(sf->ar_bytes, save->ar);
2437 } else {
2438 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2439 << AR_DPL_SHIFT;
2440 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2441 }
2442}
2443
2444static void enter_pmode(struct kvm_vcpu *vcpu)
2445{
2446 unsigned long flags;
a89a8fb9 2447 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2448
a89a8fb9 2449 vmx->emulation_required = 1;
7ffd92c5 2450 vmx->rmode.vm86_active = 0;
6aa8b732 2451
2fb92db1
AK		 2452 vmx_segment_cache_clear(vmx);
2453
d0ba64f9 2454 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
7ffd92c5
AK		 2455 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2456 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2457 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 2458
2459 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2460 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2461 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2462 vmcs_writel(GUEST_RFLAGS, flags);
2463
66aee91a
RR		 2464 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2465 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2466
2467 update_exception_bitmap(vcpu);
2468
a89a8fb9
MG		 2469 if (emulate_invalid_guest_state)
2470 return;
2471
7ffd92c5
AK		 2472 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2473 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2474 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2475 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732 2476
2fb92db1
AK		 2477 vmx_segment_cache_clear(vmx);
2478
6aa8b732
AK		 2479 vmcs_write16(GUEST_SS_SELECTOR, 0);
2480 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2481
2482 vmcs_write16(GUEST_CS_SELECTOR,
2483 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2484 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2485}
2486
d77c26fc 2487static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 2488{
bfc6d222 2489 if (!kvm->arch.tss_addr) {
bc6678a3
MT		 2490 struct kvm_memslots *slots;
2491 gfn_t base_gfn;
2492
90d83dc3 2493 slots = kvm_memslots(kvm);
f495c6e5 2494 base_gfn = slots->memslots[0].base_gfn +
46a26bf5 2495 kvm->memslots->memslots[0].npages - 3;
cbc94022
IE		 2496 return base_gfn << PAGE_SHIFT;
2497 }
bfc6d222 2498 return kvm->arch.tss_addr;
6aa8b732
AK		 2499}
2500
2501static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2502{
2503 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2504
2505 save->selector = vmcs_read16(sf->selector);
2506 save->base = vmcs_readl(sf->base);
2507 save->limit = vmcs_read32(sf->limit);
2508 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32 2509 vmcs_write16(sf->selector, save->base >> 4);
444e863d 2510 vmcs_write32(sf->base, save->base & 0xffff0);
6aa8b732
AK		 2511 vmcs_write32(sf->limit, 0xffff);
2512 vmcs_write32(sf->ar_bytes, 0xf3);
444e863d
GN		 2513 if (save->base & 0xf)
2514 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2515 " aligned when entering protected mode (seg=%d)",
2516 seg);
6aa8b732
AK		 2517}
2518
2519static void enter_rmode(struct kvm_vcpu *vcpu)
2520{
2521 unsigned long flags;
a89a8fb9 2522 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2523
3a624e29
NK		 2524 if (enable_unrestricted_guest)
2525 return;
2526
a89a8fb9 2527 vmx->emulation_required = 1;
7ffd92c5 2528 vmx->rmode.vm86_active = 1;
6aa8b732 2529
776e58ea
GN		 2530 /*
2531 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2532 * vcpu. Call it here with phys address pointing 16M below 4G.
2533 */
2534 if (!vcpu->kvm->arch.tss_addr) {
2535 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2536 "called before entering vcpu\n");
2537 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2538 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2539 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2540 }
2541
2fb92db1
AK		 2542 vmx_segment_cache_clear(vmx);
2543
d0ba64f9 2544 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
7ffd92c5 2545 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 2546 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2547
7ffd92c5 2548 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 2549 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2550
7ffd92c5 2551 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 2552 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2553
2554 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2555 vmx->rmode.save_rflags = flags;
6aa8b732 2556
053de044 2557 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2558
2559 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2560 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2561 update_exception_bitmap(vcpu);
2562
a89a8fb9
MG		 2563 if (emulate_invalid_guest_state)
2564 goto continue_rmode;
2565
6aa8b732
AK		 2566 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2567 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2568 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2569
2570 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 2571 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 2572 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2573 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 2574 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2575
7ffd92c5
AK		 2576 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2577 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2578 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2579 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 2580
a89a8fb9 2581continue_rmode:
8668a3c4 2582 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2583}
2584
401d10de
AS		 2585static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2586{
2587 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2588 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2589
2590 if (!msr)
2591 return;
401d10de 2592
44ea2b17
AK		 2593 /*
2594 * Force kernel_gs_base reloading before EFER changes, as control
2595 * of this msr depends on is_long_mode().
2596 */
2597 vmx_load_host_state(to_vmx(vcpu));
f6801dff 2598 vcpu->arch.efer = efer;
401d10de
AS		 2599 if (efer & EFER_LMA) {
2600 vmcs_write32(VM_ENTRY_CONTROLS,
2601 vmcs_read32(VM_ENTRY_CONTROLS) |
2602 VM_ENTRY_IA32E_MODE);
2603 msr->data = efer;
2604 } else {
2605 vmcs_write32(VM_ENTRY_CONTROLS,
2606 vmcs_read32(VM_ENTRY_CONTROLS) &
2607 ~VM_ENTRY_IA32E_MODE);
2608
2609 msr->data = efer & ~EFER_LME;
2610 }
2611 setup_msrs(vmx);
2612}
2613
05b3e0c2 2614#ifdef CONFIG_X86_64
6aa8b732
AK		 2615
2616static void enter_lmode(struct kvm_vcpu *vcpu)
2617{
2618 u32 guest_tr_ar;
2619
2fb92db1
AK		 2620 vmx_segment_cache_clear(to_vmx(vcpu));
2621
6aa8b732
AK		 2622 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2623 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2624 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 2625 __func__);
6aa8b732
AK		 2626 vmcs_write32(GUEST_TR_AR_BYTES,
2627 (guest_tr_ar & ~AR_TYPE_MASK)
2628 | AR_TYPE_BUSY_64_TSS);
2629 }
da38f438 2630 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2631}
2632
2633static void exit_lmode(struct kvm_vcpu *vcpu)
2634{
6aa8b732
AK		 2635 vmcs_write32(VM_ENTRY_CONTROLS,
2636 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 2637 & ~VM_ENTRY_IA32E_MODE);
da38f438 2638 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2639}
2640
2641#endif
2642
2384d2b3
SY		 2643static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2644{
b9d762fa 2645 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 2646 if (enable_ept) {
2647 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2648 return;
4e1096d2 2649 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 2650 }
2384d2b3
SY		 2651}
2652
e8467fda
AK		 2653static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2654{
2655 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2656
2657 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2658 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2659}
2660
aff48baa
AK		 2661static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2662{
2663 if (enable_ept && is_paging(vcpu))
2664 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2665 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2666}
2667
25c4c276 2668static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 2669{
fc78f519
AK		 2670 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2671
2672 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2673 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 2674}
2675
1439442c
SY		 2676static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2677{
6de4f3ad
AK		 2678 if (!test_bit(VCPU_EXREG_PDPTR,
2679 (unsigned long *)&vcpu->arch.regs_dirty))
2680 return;
2681
1439442c 2682 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2683 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2684 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2685 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2686 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 2687 }
2688}
2689
8f5d549f
AK		 2690static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2691{
2692 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2693 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2694 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2695 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2696 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 2697 }
6de4f3ad
AK		 2698
2699 __set_bit(VCPU_EXREG_PDPTR,
2700 (unsigned long *)&vcpu->arch.regs_avail);
2701 __set_bit(VCPU_EXREG_PDPTR,
2702 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 2703}
2704
5e1746d6 2705static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 2706
2707static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2708 unsigned long cr0,
2709 struct kvm_vcpu *vcpu)
2710{
5233dd51
MT		 2711 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2712 vmx_decache_cr3(vcpu);
1439442c
SY		 2713 if (!(cr0 & X86_CR0_PG)) {
2714 /* From paging/starting to nonpaging */
2715 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2716 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 2717 (CPU_BASED_CR3_LOAD_EXITING |
2718 CPU_BASED_CR3_STORE_EXITING));
2719 vcpu->arch.cr0 = cr0;
fc78f519 2720 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 2721 } else if (!is_paging(vcpu)) {
2722 /* From nonpaging to paging */
2723 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2724 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 2725 ~(CPU_BASED_CR3_LOAD_EXITING |
2726 CPU_BASED_CR3_STORE_EXITING));
2727 vcpu->arch.cr0 = cr0;
fc78f519 2728 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 2729 }
95eb84a7
SY		 2730
2731 if (!(cr0 & X86_CR0_WP))
2732 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 2733}
2734
6aa8b732
AK		 2735static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2736{
7ffd92c5 2737 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 2738 unsigned long hw_cr0;
2739
2740 if (enable_unrestricted_guest)
2741 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2742 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2743 else
2744 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 2745
7ffd92c5 2746 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 2747 enter_pmode(vcpu);
2748
7ffd92c5 2749 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 2750 enter_rmode(vcpu);
2751
05b3e0c2 2752#ifdef CONFIG_X86_64
f6801dff 2753 if (vcpu->arch.efer & EFER_LME) {
707d92fa 2754 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 2755 enter_lmode(vcpu);
707d92fa 2756 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 2757 exit_lmode(vcpu);
2758 }
2759#endif
2760
089d034e 2761 if (enable_ept)
1439442c
SY		 2762 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2763
02daab21 2764 if (!vcpu->fpu_active)
81231c69 2765 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 2766
6aa8b732 2767 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 2768 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 2769 vcpu->arch.cr0 = cr0;
69c73028 2770 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 2771}
2772
1439442c
SY		 2773static u64 construct_eptp(unsigned long root_hpa)
2774{
2775 u64 eptp;
2776
2777 /* TODO write the value reading from MSR */
2778 eptp = VMX_EPT_DEFAULT_MT |
2779 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
2780 eptp |= (root_hpa & PAGE_MASK);
2781
2782 return eptp;
2783}
2784
6aa8b732
AK		 2785static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2786{
1439442c
SY		 2787 unsigned long guest_cr3;
2788 u64 eptp;
2789
2790 guest_cr3 = cr3;
089d034e 2791 if (enable_ept) {
1439442c
SY		 2792 eptp = construct_eptp(cr3);
2793 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 2794 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 2795 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 2796 ept_load_pdptrs(vcpu);
1439442c
SY		 2797 }
2798
2384d2b3 2799 vmx_flush_tlb(vcpu);
1439442c 2800 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 2801}
2802
5e1746d6 2803static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 2804{
7ffd92c5 2805 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 2806 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2807
5e1746d6
NHE		 2808 if (cr4 & X86_CR4_VMXE) {
2809 /*
2810 * To use VMXON (and later other VMX instructions), a guest
2811 * must first be able to turn on cr4.VMXE (see handle_vmon()).
2812 * So basically the check on whether to allow nested VMX
2813 * is here.
2814 */
2815 if (!nested_vmx_allowed(vcpu))
2816 return 1;
2817 } else if (to_vmx(vcpu)->nested.vmxon)
2818 return 1;
2819
ad312c7c 2820 vcpu->arch.cr4 = cr4;
bc23008b
AK		 2821 if (enable_ept) {
2822 if (!is_paging(vcpu)) {
2823 hw_cr4 &= ~X86_CR4_PAE;
2824 hw_cr4 |= X86_CR4_PSE;
2825 } else if (!(cr4 & X86_CR4_PAE)) {
2826 hw_cr4 &= ~X86_CR4_PAE;
2827 }
2828 }
1439442c
SY		 2829
2830 vmcs_writel(CR4_READ_SHADOW, cr4);
2831 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 2832 return 0;
6aa8b732
AK		 2833}
2834
6aa8b732
AK		 2835static void vmx_get_segment(struct kvm_vcpu *vcpu,
2836 struct kvm_segment *var, int seg)
2837{
a9179499 2838 struct vcpu_vmx *vmx = to_vmx(vcpu);
a9179499 2839 struct kvm_save_segment *save;
6aa8b732
AK		 2840 u32 ar;
2841
a9179499
AK		 2842 if (vmx->rmode.vm86_active
2843 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
2844 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
2845 || seg == VCPU_SREG_GS)
2846 && !emulate_invalid_guest_state) {
2847 switch (seg) {
2848 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
2849 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
2850 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
2851 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
2852 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
2853 default: BUG();
2854 }
2855 var->selector = save->selector;
2856 var->base = save->base;
2857 var->limit = save->limit;
2858 ar = save->ar;
2859 if (seg == VCPU_SREG_TR
2fb92db1 2860 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
a9179499
AK		 2861 goto use_saved_rmode_seg;
2862 }
2fb92db1
AK		 2863 var->base = vmx_read_guest_seg_base(vmx, seg);
2864 var->limit = vmx_read_guest_seg_limit(vmx, seg);
2865 var->selector = vmx_read_guest_seg_selector(vmx, seg);
2866 ar = vmx_read_guest_seg_ar(vmx, seg);
a9179499 2867use_saved_rmode_seg:
9fd4a3b7 2868 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 2869 ar = 0;
2870 var->type = ar & 15;
2871 var->s = (ar >> 4) & 1;
2872 var->dpl = (ar >> 5) & 3;
2873 var->present = (ar >> 7) & 1;
2874 var->avl = (ar >> 12) & 1;
2875 var->l = (ar >> 13) & 1;
2876 var->db = (ar >> 14) & 1;
2877 var->g = (ar >> 15) & 1;
2878 var->unusable = (ar >> 16) & 1;
2879}
2880
a9179499
AK		 2881static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2882{
a9179499
AK		 2883 struct kvm_segment s;
2884
2885 if (to_vmx(vcpu)->rmode.vm86_active) {
2886 vmx_get_segment(vcpu, &s, seg);
2887 return s.base;
2888 }
2fb92db1 2889 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 2890}
2891
69c73028 2892static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 2893{
3eeb3288 2894 if (!is_protmode(vcpu))
2e4d2653
IE		 2895 return 0;
2896
f4c63e5d
AK		 2897 if (!is_long_mode(vcpu)
2898 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 2899 return 3;
2900
2fb92db1 2901 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2e4d2653
IE		 2902}
2903
69c73028
AK		 2904static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2905{
2906 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
2907 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2908 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
2909 }
2910 return to_vmx(vcpu)->cpl;
2911}
2912
2913
653e3108 2914static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 2915{
6aa8b732
AK		 2916 u32 ar;
2917
653e3108 2918 if (var->unusable)
6aa8b732
AK		 2919 ar = 1 << 16;
2920 else {
2921 ar = var->type & 15;
2922 ar |= (var->s & 1) << 4;
2923 ar |= (var->dpl & 3) << 5;
2924 ar |= (var->present & 1) << 7;
2925 ar |= (var->avl & 1) << 12;
2926 ar |= (var->l & 1) << 13;
2927 ar |= (var->db & 1) << 14;
2928 ar |= (var->g & 1) << 15;
2929 }
f7fbf1fd
UL		 2930 if (ar == 0) /* a 0 value means unusable */
2931 ar = AR_UNUSABLE_MASK;
653e3108
AK		 2932
2933 return ar;
2934}
2935
2936static void vmx_set_segment(struct kvm_vcpu *vcpu,
2937 struct kvm_segment *var, int seg)
2938{
7ffd92c5 2939 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 2940 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2941 u32 ar;
2942
2fb92db1
AK		 2943 vmx_segment_cache_clear(vmx);
2944
7ffd92c5 2945 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
a8ba6c26 2946 vmcs_write16(sf->selector, var->selector);
7ffd92c5
AK		 2947 vmx->rmode.tr.selector = var->selector;
2948 vmx->rmode.tr.base = var->base;
2949 vmx->rmode.tr.limit = var->limit;
2950 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 2951 return;
2952 }
2953 vmcs_writel(sf->base, var->base);
2954 vmcs_write32(sf->limit, var->limit);
2955 vmcs_write16(sf->selector, var->selector);
7ffd92c5 2956 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 2957 /*
2958 * Hack real-mode segments into vm86 compatibility.
2959 */
2960 if (var->base == 0xffff0000 && var->selector == 0xf000)
2961 vmcs_writel(sf->base, 0xf0000);
2962 ar = 0xf3;
2963 } else
2964 ar = vmx_segment_access_rights(var);
3a624e29
NK		 2965
2966 /*
2967 * Fix the "Accessed" bit in AR field of segment registers for older
2968 * qemu binaries.
2969 * IA32 arch specifies that at the time of processor reset the
2970 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2971 * is setting it to 0 in the usedland code. This causes invalid guest
2972 * state vmexit when "unrestricted guest" mode is turned on.
2973 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2974 * tree. Newer qemu binaries with that qemu fix would not need this
2975 * kvm hack.
2976 */
2977 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2978 ar |= 0x1; /* Accessed */
2979
6aa8b732 2980 vmcs_write32(sf->ar_bytes, ar);
69c73028 2981 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 2982}
2983
6aa8b732
AK		 2984static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2985{
2fb92db1 2986 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 2987
2988 *db = (ar >> 14) & 1;
2989 *l = (ar >> 13) & 1;
2990}
2991
89a27f4d 2992static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2993{
89a27f4d
GN		 2994 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2995 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 2996}
2997
89a27f4d 2998static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2999{
89a27f4d
GN		 3000 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3001 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3002}
3003
89a27f4d 3004static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3005{
89a27f4d
GN		 3006 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3007 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3008}
3009
89a27f4d 3010static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3011{
89a27f4d
GN		 3012 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3013 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3014}
3015
648dfaa7
MG		 3016static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3017{
3018 struct kvm_segment var;
3019 u32 ar;
3020
3021 vmx_get_segment(vcpu, &var, seg);
3022 ar = vmx_segment_access_rights(&var);
3023
3024 if (var.base != (var.selector << 4))
3025 return false;
3026 if (var.limit != 0xffff)
3027 return false;
3028 if (ar != 0xf3)
3029 return false;
3030
3031 return true;
3032}
3033
3034static bool code_segment_valid(struct kvm_vcpu *vcpu)
3035{
3036 struct kvm_segment cs;
3037 unsigned int cs_rpl;
3038
3039 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3040 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3041
1872a3f4
AK		 3042 if (cs.unusable)
3043 return false;
648dfaa7
MG		 3044 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3045 return false;
3046 if (!cs.s)
3047 return false;
1872a3f4 3048 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3049 if (cs.dpl > cs_rpl)
3050 return false;
1872a3f4 3051 } else {
648dfaa7
MG		 3052 if (cs.dpl != cs_rpl)
3053 return false;
3054 }
3055 if (!cs.present)
3056 return false;
3057
3058 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3059 return true;
3060}
3061
3062static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3063{
3064 struct kvm_segment ss;
3065 unsigned int ss_rpl;
3066
3067 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3068 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3069
1872a3f4
AK		 3070 if (ss.unusable)
3071 return true;
3072 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3073 return false;
3074 if (!ss.s)
3075 return false;
3076 if (ss.dpl != ss_rpl) /* DPL != RPL */
3077 return false;
3078 if (!ss.present)
3079 return false;
3080
3081 return true;
3082}
3083
3084static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3085{
3086 struct kvm_segment var;
3087 unsigned int rpl;
3088
3089 vmx_get_segment(vcpu, &var, seg);
3090 rpl = var.selector & SELECTOR_RPL_MASK;
3091
1872a3f4
AK		 3092 if (var.unusable)
3093 return true;
648dfaa7
MG		 3094 if (!var.s)
3095 return false;
3096 if (!var.present)
3097 return false;
3098 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3099 if (var.dpl < rpl) /* DPL < RPL */
3100 return false;
3101 }
3102
3103 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3104 * rights flags
3105 */
3106 return true;
3107}
3108
3109static bool tr_valid(struct kvm_vcpu *vcpu)
3110{
3111 struct kvm_segment tr;
3112
3113 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3114
1872a3f4
AK		 3115 if (tr.unusable)
3116 return false;
648dfaa7
MG		 3117 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3118 return false;
1872a3f4 3119 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3120 return false;
3121 if (!tr.present)
3122 return false;
3123
3124 return true;
3125}
3126
3127static bool ldtr_valid(struct kvm_vcpu *vcpu)
3128{
3129 struct kvm_segment ldtr;
3130
3131 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3132
1872a3f4
AK		 3133 if (ldtr.unusable)
3134 return true;
648dfaa7
MG		 3135 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3136 return false;
3137 if (ldtr.type != 2)
3138 return false;
3139 if (!ldtr.present)
3140 return false;
3141
3142 return true;
3143}
3144
3145static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3146{
3147 struct kvm_segment cs, ss;
3148
3149 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3150 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3151
3152 return ((cs.selector & SELECTOR_RPL_MASK) ==
3153 (ss.selector & SELECTOR_RPL_MASK));
3154}
3155
3156/*
3157 * Check if guest state is valid. Returns true if valid, false if
3158 * not.
3159 * We assume that registers are always usable
3160 */
3161static bool guest_state_valid(struct kvm_vcpu *vcpu)
3162{
3163 /* real mode guest state checks */
3eeb3288 3164 if (!is_protmode(vcpu)) {
648dfaa7
MG		 3165 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3166 return false;
3167 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3168 return false;
3169 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3170 return false;
3171 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3172 return false;
3173 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3174 return false;
3175 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3176 return false;
3177 } else {
3178 /* protected mode guest state checks */
3179 if (!cs_ss_rpl_check(vcpu))
3180 return false;
3181 if (!code_segment_valid(vcpu))
3182 return false;
3183 if (!stack_segment_valid(vcpu))
3184 return false;
3185 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3186 return false;
3187 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3188 return false;
3189 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3190 return false;
3191 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3192 return false;
3193 if (!tr_valid(vcpu))
3194 return false;
3195 if (!ldtr_valid(vcpu))
3196 return false;
3197 }
3198 /* TODO:
3199 * - Add checks on RIP
3200 * - Add checks on RFLAGS
3201 */
3202
3203 return true;
3204}
3205
d77c26fc 3206static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3207{
40dcaa9f 3208 gfn_t fn;
195aefde 3209 u16 data = 0;
40dcaa9f 3210 int r, idx, ret = 0;
6aa8b732 3211
40dcaa9f
XG		 3212 idx = srcu_read_lock(&kvm->srcu);
3213 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE		 3214 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3215 if (r < 0)
10589a46 3216 goto out;
195aefde 3217 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3218 r = kvm_write_guest_page(kvm, fn++, &data,
3219 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3220 if (r < 0)
10589a46 3221 goto out;
195aefde
IE		 3222 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3223 if (r < 0)
10589a46 3224 goto out;
195aefde
IE		 3225 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3226 if (r < 0)
10589a46 3227 goto out;
195aefde 3228 data = ~0;
10589a46
MT		 3229 r = kvm_write_guest_page(kvm, fn, &data,
3230 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3231 sizeof(u8));
195aefde 3232 if (r < 0)
10589a46
MT		 3233 goto out;
3234
3235 ret = 1;
3236out:
40dcaa9f 3237 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3238 return ret;
6aa8b732
AK		 3239}
3240
b7ebfb05
SY		 3241static int init_rmode_identity_map(struct kvm *kvm)
3242{
40dcaa9f 3243 int i, idx, r, ret;
b7ebfb05
SY		 3244 pfn_t identity_map_pfn;
3245 u32 tmp;
3246
089d034e 3247 if (!enable_ept)
b7ebfb05
SY		 3248 return 1;
3249 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3250 printk(KERN_ERR "EPT: identity-mapping pagetable "
3251 "haven't been allocated!\n");
3252 return 0;
3253 }
3254 if (likely(kvm->arch.ept_identity_pagetable_done))
3255 return 1;
3256 ret = 0;
b927a3ce 3257 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3258 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3259 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3260 if (r < 0)
3261 goto out;
3262 /* Set up identity-mapping pagetable for EPT in real mode */
3263 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3264 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3265 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3266 r = kvm_write_guest_page(kvm, identity_map_pfn,
3267 &tmp, i * sizeof(tmp), sizeof(tmp));
3268 if (r < 0)
3269 goto out;
3270 }
3271 kvm->arch.ept_identity_pagetable_done = true;
3272 ret = 1;
3273out:
40dcaa9f 3274 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3275 return ret;
3276}
3277
6aa8b732
AK		 3278static void seg_setup(int seg)
3279{
3280 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3281 unsigned int ar;
6aa8b732
AK		 3282
3283 vmcs_write16(sf->selector, 0);
3284 vmcs_writel(sf->base, 0);
3285 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 3286 if (enable_unrestricted_guest) {
3287 ar = 0x93;
3288 if (seg == VCPU_SREG_CS)
3289 ar |= 0x08; /* code segment */
3290 } else
3291 ar = 0xf3;
3292
3293 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3294}
3295
f78e0e2e
SY		 3296static int alloc_apic_access_page(struct kvm *kvm)
3297{
3298 struct kvm_userspace_memory_region kvm_userspace_mem;
3299 int r = 0;
3300
79fac95e 3301 mutex_lock(&kvm->slots_lock);
bfc6d222 3302 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3303 goto out;
3304 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3305 kvm_userspace_mem.flags = 0;
3306 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3307 kvm_userspace_mem.memory_size = PAGE_SIZE;
3308 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3309 if (r)
3310 goto out;
72dc67a6 3311
bfc6d222 3312 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 3313out:
79fac95e 3314 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3315 return r;
3316}
3317
b7ebfb05
SY		 3318static int alloc_identity_pagetable(struct kvm *kvm)
3319{
3320 struct kvm_userspace_memory_region kvm_userspace_mem;
3321 int r = 0;
3322
79fac95e 3323 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3324 if (kvm->arch.ept_identity_pagetable)
3325 goto out;
3326 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3327 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3328 kvm_userspace_mem.guest_phys_addr =
3329 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 3330 kvm_userspace_mem.memory_size = PAGE_SIZE;
3331 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3332 if (r)
3333 goto out;
3334
b7ebfb05 3335 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 3336 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 3337out:
79fac95e 3338 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3339 return r;
3340}
3341
2384d2b3
SY		 3342static void allocate_vpid(struct vcpu_vmx *vmx)
3343{
3344 int vpid;
3345
3346 vmx->vpid = 0;
919818ab 3347 if (!enable_vpid)
2384d2b3
SY		 3348 return;
3349 spin_lock(&vmx_vpid_lock);
3350 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3351 if (vpid < VMX_NR_VPIDS) {
3352 vmx->vpid = vpid;
3353 __set_bit(vpid, vmx_vpid_bitmap);
3354 }
3355 spin_unlock(&vmx_vpid_lock);
3356}
3357
cdbecfc3
LJ		 3358static void free_vpid(struct vcpu_vmx *vmx)
3359{
3360 if (!enable_vpid)
3361 return;
3362 spin_lock(&vmx_vpid_lock);
3363 if (vmx->vpid != 0)
3364 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3365 spin_unlock(&vmx_vpid_lock);
3366}
3367
5897297b 3368static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 3369{
3e7c73e9 3370 int f = sizeof(unsigned long);
25c5f225
SY		 3371
3372 if (!cpu_has_vmx_msr_bitmap())
3373 return;
3374
3375 /*
3376 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3377 * have the write-low and read-high bitmap offsets the wrong way round.
3378 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3379 */
25c5f225 3380 if (msr <= 0x1fff) {
3e7c73e9
AK		 3381 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3382 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 3383 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3384 msr &= 0x1fff;
3e7c73e9
AK		 3385 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3386 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 3387 }
25c5f225
SY		 3388}
3389
5897297b
AK		 3390static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3391{
3392 if (!longmode_only)
3393 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3394 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3395}
3396
a3a8ff8e
NHE		 3397/*
3398 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3399 * will not change in the lifetime of the guest.
3400 * Note that host-state that does change is set elsewhere. E.g., host-state
3401 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3402 */
3403static void vmx_set_constant_host_state(void)
3404{
3405 u32 low32, high32;
3406 unsigned long tmpl;
3407 struct desc_ptr dt;
3408
3409 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
3410 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3411 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3412
3413 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3414 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3415 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3416 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3417 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3418
3419 native_store_idt(&dt);
3420 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3421
3422 asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3423 vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3424
3425 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3426 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3427 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3428 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3429
3430 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3431 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3432 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3433 }
3434}
3435
6aa8b732
AK		 3436/*
3437 * Sets up the vmcs for emulated real mode.
3438 */
8b9cf98c 3439static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 3440{
6aa8b732 3441 unsigned long a;
6aa8b732 3442 int i;
6e5d865c 3443 u32 exec_control;
6aa8b732 3444
6aa8b732 3445 /* I/O */
3e7c73e9
AK		 3446 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3447 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 3448
25c5f225 3449 if (cpu_has_vmx_msr_bitmap())
5897297b 3450 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 3451
6aa8b732
AK		 3452 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3453
6aa8b732 3454 /* Control */
1c3d14fe
YS		 3455 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3456 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 3457
3458 exec_control = vmcs_config.cpu_based_exec_ctrl;
3459 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3460 exec_control &= ~CPU_BASED_TPR_SHADOW;
3461#ifdef CONFIG_X86_64
3462 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3463 CPU_BASED_CR8_LOAD_EXITING;
3464#endif
3465 }
089d034e 3466 if (!enable_ept)
d56f546d 3467 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 3468 CPU_BASED_CR3_LOAD_EXITING |
3469 CPU_BASED_INVLPG_EXITING;
6e5d865c 3470 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 3471
83ff3b9d
SY		 3472 if (cpu_has_secondary_exec_ctrls()) {
3473 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3474 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3475 exec_control &=
3476 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 3477 if (vmx->vpid == 0)
3478 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
046d8710 3479 if (!enable_ept) {
d56f546d 3480 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
046d8710
SY		 3481 enable_unrestricted_guest = 0;
3482 }
3a624e29
NK		 3483 if (!enable_unrestricted_guest)
3484 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4b8d54f9
ZE		 3485 if (!ple_gap)
3486 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
83ff3b9d
SY		 3487 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
3488 }
f78e0e2e 3489
4b8d54f9
ZE		 3490 if (ple_gap) {
3491 vmcs_write32(PLE_GAP, ple_gap);
3492 vmcs_write32(PLE_WINDOW, ple_window);
3493 }
3494
c7addb90
AK		 3495 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
3496 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 3497 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3498
9581d442
AK		 3499 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3500 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a3a8ff8e 3501 vmx_set_constant_host_state();
05b3e0c2 3502#ifdef CONFIG_X86_64
6aa8b732
AK		 3503 rdmsrl(MSR_FS_BASE, a);
3504 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3505 rdmsrl(MSR_GS_BASE, a);
3506 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3507#else
3508 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3509 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3510#endif
3511
2cc51560
ED		 3512 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3513 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 3514 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 3515 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 3516 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 3517
468d472f 3518 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 3519 u32 msr_low, msr_high;
3520 u64 host_pat;
468d472f
SY		 3521 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3522 host_pat = msr_low | ((u64) msr_high << 32);
3523 /* Write the default value follow host pat */
3524 vmcs_write64(GUEST_IA32_PAT, host_pat);
3525 /* Keep arch.pat sync with GUEST_IA32_PAT */
3526 vmx->vcpu.arch.pat = host_pat;
3527 }
3528
6aa8b732
AK		 3529 for (i = 0; i < NR_VMX_MSR; ++i) {
3530 u32 index = vmx_msr_index[i];
3531 u32 data_low, data_high;
a2fa3e9f 3532 int j = vmx->nmsrs;
6aa8b732
AK		 3533
3534 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3535 continue;
432bd6cb
AK		 3536 if (wrmsr_safe(index, data_low, data_high) < 0)
3537 continue;
26bb0981
AK		 3538 vmx->guest_msrs[j].index = i;
3539 vmx->guest_msrs[j].data = 0;
d5696725 3540 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 3541 ++vmx->nmsrs;
6aa8b732 3542 }
6aa8b732 3543
1c3d14fe 3544 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 3545
3546 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 3547 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3548
e00c8cf2 3549 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4c38609a 3550 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
ce03e4f2
AK		 3551 if (enable_ept)
3552 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4c38609a 3553 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
e00c8cf2 3554
99e3e30a 3555 kvm_write_tsc(&vmx->vcpu, 0);
f78e0e2e 3556
e00c8cf2
AK		 3557 return 0;
3558}
3559
3560static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3561{
3562 struct vcpu_vmx *vmx = to_vmx(vcpu);
3563 u64 msr;
4b9d3a04 3564 int ret;
e00c8cf2 3565
5fdbf976 3566 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
e00c8cf2 3567
7ffd92c5 3568 vmx->rmode.vm86_active = 0;
e00c8cf2 3569
3b86cd99
JK		 3570 vmx->soft_vnmi_blocked = 0;
3571
ad312c7c 3572 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 3573 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 3574 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 3575 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 3576 msr |= MSR_IA32_APICBASE_BSP;
3577 kvm_set_apic_base(&vmx->vcpu, msr);
3578
10ab25cd
JK		 3579 ret = fx_init(&vmx->vcpu);
3580 if (ret != 0)
3581 goto out;
e00c8cf2 3582
2fb92db1
AK		 3583 vmx_segment_cache_clear(vmx);
3584
5706be0d 3585 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 3586 /*
3587 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3588 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3589 */
c5af89b6 3590 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 3591 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3592 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3593 } else {
ad312c7c
ZX		 3594 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3595 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 3596 }
e00c8cf2
AK		 3597
3598 seg_setup(VCPU_SREG_DS);
3599 seg_setup(VCPU_SREG_ES);
3600 seg_setup(VCPU_SREG_FS);
3601 seg_setup(VCPU_SREG_GS);
3602 seg_setup(VCPU_SREG_SS);
3603
3604 vmcs_write16(GUEST_TR_SELECTOR, 0);
3605 vmcs_writel(GUEST_TR_BASE, 0);
3606 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3607 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3608
3609 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3610 vmcs_writel(GUEST_LDTR_BASE, 0);
3611 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3612 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3613
3614 vmcs_write32(GUEST_SYSENTER_CS, 0);
3615 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3616 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3617
3618 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 3619 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 3620 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 3621 else
5fdbf976
MT		 3622 kvm_rip_write(vcpu, 0);
3623 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 3624
e00c8cf2
AK		 3625 vmcs_writel(GUEST_DR7, 0x400);
3626
3627 vmcs_writel(GUEST_GDTR_BASE, 0);
3628 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3629
3630 vmcs_writel(GUEST_IDTR_BASE, 0);
3631 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3632
443381a8 3633 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 3634 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3635 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3636
e00c8cf2
AK		 3637 /* Special registers */
3638 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3639
3640 setup_msrs(vmx);
3641
6aa8b732
AK		 3642 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
3643
f78e0e2e
SY		 3644 if (cpu_has_vmx_tpr_shadow()) {
3645 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3646 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3647 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 3648 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 3649 vmcs_write32(TPR_THRESHOLD, 0);
3650 }
3651
3652 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3653 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 3654 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 3655
2384d2b3
SY		 3656 if (vmx->vpid != 0)
3657 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3658
fa40052c 3659 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 3660 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 3661 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 3662 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 3663 vmx_fpu_activate(&vmx->vcpu);
3664 update_exception_bitmap(&vmx->vcpu);
6aa8b732 3665
b9d762fa 3666 vpid_sync_context(vmx);
2384d2b3 3667
3200f405 3668 ret = 0;
6aa8b732 3669
a89a8fb9
MG		 3670 /* HACK: Don't enable emulation on guest boot/reset */
3671 vmx->emulation_required = 0;
3672
6aa8b732
AK		 3673out:
3674 return ret;
3675}
3676
3b86cd99
JK		 3677static void enable_irq_window(struct kvm_vcpu *vcpu)
3678{
3679 u32 cpu_based_vm_exec_control;
3680
3681 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3682 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3683 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3684}
3685
3686static void enable_nmi_window(struct kvm_vcpu *vcpu)
3687{
3688 u32 cpu_based_vm_exec_control;
3689
3690 if (!cpu_has_virtual_nmis()) {
3691 enable_irq_window(vcpu);
3692 return;
3693 }
3694
30bd0c4c
AK		 3695 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3696 enable_irq_window(vcpu);
3697 return;
3698 }
3b86cd99
JK		 3699 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3700 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3701 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3702}
3703
66fd3f7f 3704static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 3705{
9c8cba37 3706 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 3707 uint32_t intr;
3708 int irq = vcpu->arch.interrupt.nr;
9c8cba37 3709
229456fc 3710 trace_kvm_inj_virq(irq);
2714d1d3 3711
fa89a817 3712 ++vcpu->stat.irq_injections;
7ffd92c5 3713 if (vmx->rmode.vm86_active) {
71f9833b
SH		 3714 int inc_eip = 0;
3715 if (vcpu->arch.interrupt.soft)
3716 inc_eip = vcpu->arch.event_exit_inst_len;
3717 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 3718 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 3719 return;
3720 }
66fd3f7f
GN		 3721 intr = irq | INTR_INFO_VALID_MASK;
3722 if (vcpu->arch.interrupt.soft) {
3723 intr |= INTR_TYPE_SOFT_INTR;
3724 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3725 vmx->vcpu.arch.event_exit_inst_len);
3726 } else
3727 intr |= INTR_TYPE_EXT_INTR;
3728 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
443381a8 3729 vmx_clear_hlt(vcpu);
85f455f7
ED		 3730}
3731
f08864b4
SY		 3732static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
3733{
66a5a347
JK		 3734 struct vcpu_vmx *vmx = to_vmx(vcpu);
3735
3b86cd99
JK		 3736 if (!cpu_has_virtual_nmis()) {
3737 /*
3738 * Tracking the NMI-blocked state in software is built upon
3739 * finding the next open IRQ window. This, in turn, depends on
3740 * well-behaving guests: They have to keep IRQs disabled at
3741 * least as long as the NMI handler runs. Otherwise we may
3742 * cause NMI nesting, maybe breaking the guest. But as this is
3743 * highly unlikely, we can live with the residual risk.
3744 */
3745 vmx->soft_vnmi_blocked = 1;
3746 vmx->vnmi_blocked_time = 0;
3747 }
3748
487b391d 3749 ++vcpu->stat.nmi_injections;
9d58b931 3750 vmx->nmi_known_unmasked = false;
7ffd92c5 3751 if (vmx->rmode.vm86_active) {
71f9833b 3752 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 3753 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 3754 return;
3755 }
f08864b4
SY		 3756 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
3757 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
443381a8 3758 vmx_clear_hlt(vcpu);
f08864b4
SY		 3759}
3760
c4282df9 3761static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 3762{
3b86cd99 3763 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 3764 return 0;
33f089ca 3765
c4282df9 3766 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 3767 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
3768 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 3769}
3770
3cfc3092
JK		 3771static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
3772{
3773 if (!cpu_has_virtual_nmis())
3774 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 3775 if (to_vmx(vcpu)->nmi_known_unmasked)
3776 return false;
c332c83a 3777 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 3778}
3779
3780static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3781{
3782 struct vcpu_vmx *vmx = to_vmx(vcpu);
3783
3784 if (!cpu_has_virtual_nmis()) {
3785 if (vmx->soft_vnmi_blocked != masked) {
3786 vmx->soft_vnmi_blocked = masked;
3787 vmx->vnmi_blocked_time = 0;
3788 }
3789 } else {
9d58b931 3790 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 3791 if (masked)
3792 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3793 GUEST_INTR_STATE_NMI);
3794 else
3795 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3796 GUEST_INTR_STATE_NMI);
3797 }
3798}
3799
78646121
GN		 3800static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
3801{
c4282df9
GN		 3802 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
3803 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3804 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 3805}
3806
cbc94022
IE		 3807static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
3808{
3809 int ret;
3810 struct kvm_userspace_memory_region tss_mem = {
6fe63979 3811 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 3812 .guest_phys_addr = addr,
3813 .memory_size = PAGE_SIZE * 3,
3814 .flags = 0,
3815 };
3816
3817 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
3818 if (ret)
3819 return ret;
bfc6d222 3820 kvm->arch.tss_addr = addr;
93ea5388
GN		 3821 if (!init_rmode_tss(kvm))
3822 return -ENOMEM;
3823
cbc94022
IE		 3824 return 0;
3825}
3826
6aa8b732
AK		 3827static int handle_rmode_exception(struct kvm_vcpu *vcpu,
3828 int vec, u32 err_code)
3829{
b3f37707
NK		 3830 /*
3831 * Instruction with address size override prefix opcode 0x67
3832 * Cause the #SS fault with 0 error code in VM86 mode.
3833 */
3834 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
51d8b661 3835 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
6aa8b732 3836 return 1;
77ab6db0
JK		 3837 /*
3838 * Forward all other exceptions that are valid in real mode.
3839 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
3840 * the required debugging infrastructure rework.
3841 */
3842 switch (vec) {
77ab6db0 3843 case DB_VECTOR:
d0bfb940
JK		 3844 if (vcpu->guest_debug &
3845 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
3846 return 0;
3847 kvm_queue_exception(vcpu, vec);
3848 return 1;
77ab6db0 3849 case BP_VECTOR:
c573cd22
JK		 3850 /*
3851 * Update instruction length as we may reinject the exception
3852 * from user space while in guest debugging mode.
3853 */
3854 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
3855 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 3856 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
3857 return 0;
3858 /* fall through */
3859 case DE_VECTOR:
77ab6db0
JK		 3860 case OF_VECTOR:
3861 case BR_VECTOR:
3862 case UD_VECTOR:
3863 case DF_VECTOR:
3864 case SS_VECTOR:
3865 case GP_VECTOR:
3866 case MF_VECTOR:
3867 kvm_queue_exception(vcpu, vec);
3868 return 1;
3869 }
6aa8b732
AK		 3870 return 0;
3871}
3872
a0861c02
AK		 3873/*
3874 * Trigger machine check on the host. We assume all the MSRs are already set up
3875 * by the CPU and that we still run on the same CPU as the MCE occurred on.
3876 * We pass a fake environment to the machine check handler because we want
3877 * the guest to be always treated like user space, no matter what context
3878 * it used internally.
3879 */
3880static void kvm_machine_check(void)
3881{
3882#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3883 struct pt_regs regs = {
3884 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3885 .flags = X86_EFLAGS_IF,
3886 };
3887
3888 do_machine_check(&regs, 0);
3889#endif
3890}
3891
851ba692 3892static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 3893{
3894 /* already handled by vcpu_run */
3895 return 1;
3896}
3897
851ba692 3898static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 3899{
1155f76a 3900 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 3901 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 3902 u32 intr_info, ex_no, error_code;
42dbaa5a 3903 unsigned long cr2, rip, dr6;
6aa8b732
AK		 3904 u32 vect_info;
3905 enum emulation_result er;
3906
1155f76a 3907 vect_info = vmx->idt_vectoring_info;
88786475 3908 intr_info = vmx->exit_intr_info;
6aa8b732 3909
a0861c02 3910 if (is_machine_check(intr_info))
851ba692 3911 return handle_machine_check(vcpu);
a0861c02 3912
6aa8b732 3913 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 3914 !is_page_fault(intr_info)) {
3915 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3916 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3917 vcpu->run->internal.ndata = 2;
3918 vcpu->run->internal.data[0] = vect_info;
3919 vcpu->run->internal.data[1] = intr_info;
3920 return 0;
3921 }
6aa8b732 3922
e4a41889 3923 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 3924 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 3925
3926 if (is_no_device(intr_info)) {
5fd86fcf 3927 vmx_fpu_activate(vcpu);
2ab455cc
AL		 3928 return 1;
3929 }
3930
7aa81cc0 3931 if (is_invalid_opcode(intr_info)) {
51d8b661 3932 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 3933 if (er != EMULATE_DONE)
7ee5d940 3934 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 3935 return 1;
3936 }
3937
6aa8b732 3938 error_code = 0;
2e11384c 3939 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 3940 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3941 if (is_page_fault(intr_info)) {
1439442c 3942 /* EPT won't cause page fault directly */
089d034e 3943 if (enable_ept)
1439442c 3944 BUG();
6aa8b732 3945 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 3946 trace_kvm_page_fault(cr2, error_code);
3947
3298b75c 3948 if (kvm_event_needs_reinjection(vcpu))
577bdc49 3949 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 3950 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 3951 }
3952
7ffd92c5 3953 if (vmx->rmode.vm86_active &&
6aa8b732 3954 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 3955 error_code)) {
ad312c7c
ZX		 3956 if (vcpu->arch.halt_request) {
3957 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 3958 return kvm_emulate_halt(vcpu);
3959 }
6aa8b732 3960 return 1;
72d6e5a0 3961 }
6aa8b732 3962
d0bfb940 3963 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 3964 switch (ex_no) {
3965 case DB_VECTOR:
3966 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3967 if (!(vcpu->guest_debug &
3968 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3969 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3970 kvm_queue_exception(vcpu, DB_VECTOR);
3971 return 1;
3972 }
3973 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3974 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3975 /* fall through */
3976 case BP_VECTOR:
c573cd22
JK		 3977 /*
3978 * Update instruction length as we may reinject #BP from
3979 * user space while in guest debugging mode. Reading it for
3980 * #DB as well causes no harm, it is not used in that case.
3981 */
3982 vmx->vcpu.arch.event_exit_inst_len =
3983 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 3984 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 3985 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 3986 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3987 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 3988 break;
3989 default:
d0bfb940
JK		 3990 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3991 kvm_run->ex.exception = ex_no;
3992 kvm_run->ex.error_code = error_code;
42dbaa5a 3993 break;
6aa8b732 3994 }
6aa8b732
AK		 3995 return 0;
3996}
3997
851ba692 3998static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 3999{
1165f5fe 4000 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4001 return 1;
4002}
4003
851ba692 4004static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4005{
851ba692 4006 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4007 return 0;
4008}
6aa8b732 4009
851ba692 4010static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4011{
bfdaab09 4012 unsigned long exit_qualification;
34c33d16 4013 int size, in, string;
039576c0 4014 unsigned port;
6aa8b732 4015
bfdaab09 4016 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4017 string = (exit_qualification & 16) != 0;
cf8f70bf 4018 in = (exit_qualification & 8) != 0;
e70669ab 4019
cf8f70bf 4020 ++vcpu->stat.io_exits;
e70669ab 4021
cf8f70bf 4022 if (string || in)
51d8b661 4023 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4024
cf8f70bf
GN		 4025 port = exit_qualification >> 16;
4026 size = (exit_qualification & 7) + 1;
e93f36bc 4027 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4028
4029 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4030}
4031
102d8325
IM		 4032static void
4033vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4034{
4035 /*
4036 * Patch in the VMCALL instruction:
4037 */
4038 hypercall[0] = 0x0f;
4039 hypercall[1] = 0x01;
4040 hypercall[2] = 0xc1;
102d8325
IM		 4041}
4042
851ba692 4043static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4044{
229456fc 4045 unsigned long exit_qualification, val;
6aa8b732
AK		 4046 int cr;
4047 int reg;
49a9b07e 4048 int err;
6aa8b732 4049
bfdaab09 4050 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4051 cr = exit_qualification & 15;
4052 reg = (exit_qualification >> 8) & 15;
4053 switch ((exit_qualification >> 4) & 3) {
4054 case 0: /* mov to cr */
229456fc
MT		 4055 val = kvm_register_read(vcpu, reg);
4056 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4057 switch (cr) {
4058 case 0:
49a9b07e 4059 err = kvm_set_cr0(vcpu, val);
db8fcefa 4060 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4061 return 1;
4062 case 3:
2390218b 4063 err = kvm_set_cr3(vcpu, val);
db8fcefa 4064 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4065 return 1;
4066 case 4:
a83b29c6 4067 err = kvm_set_cr4(vcpu, val);
db8fcefa 4068 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4069 return 1;
0a5fff19
GN		 4070 case 8: {
4071 u8 cr8_prev = kvm_get_cr8(vcpu);
4072 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4073 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4074 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4075 if (irqchip_in_kernel(vcpu->kvm))
4076 return 1;
4077 if (cr8_prev <= cr8)
4078 return 1;
851ba692 4079 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4080 return 0;
4081 }
6aa8b732
AK		 4082 };
4083 break;
25c4c276 4084 case 2: /* clts */
edcafe3c 4085 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 4086 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4087 skip_emulated_instruction(vcpu);
6b52d186 4088 vmx_fpu_activate(vcpu);
25c4c276 4089 return 1;
6aa8b732
AK		 4090 case 1: /*mov from cr*/
4091 switch (cr) {
4092 case 3:
9f8fe504
AK		 4093 val = kvm_read_cr3(vcpu);
4094 kvm_register_write(vcpu, reg, val);
4095 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4096 skip_emulated_instruction(vcpu);
4097 return 1;
4098 case 8:
229456fc
MT		 4099 val = kvm_get_cr8(vcpu);
4100 kvm_register_write(vcpu, reg, val);
4101 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4102 skip_emulated_instruction(vcpu);
4103 return 1;
4104 }
4105 break;
4106 case 3: /* lmsw */
a1f83a74 4107 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4108 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4109 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4110
4111 skip_emulated_instruction(vcpu);
4112 return 1;
4113 default:
4114 break;
4115 }
851ba692 4116 vcpu->run->exit_reason = 0;
f0242478 4117 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4118 (int)(exit_qualification >> 4) & 3, cr);
4119 return 0;
4120}
4121
851ba692 4122static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4123{
bfdaab09 4124 unsigned long exit_qualification;
6aa8b732
AK		 4125 int dr, reg;
4126
f2483415 4127 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4128 if (!kvm_require_cpl(vcpu, 0))
4129 return 1;
42dbaa5a
JK		 4130 dr = vmcs_readl(GUEST_DR7);
4131 if (dr & DR7_GD) {
4132 /*
4133 * As the vm-exit takes precedence over the debug trap, we
4134 * need to emulate the latter, either for the host or the
4135 * guest debugging itself.
4136 */
4137 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 4138 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4139 vcpu->run->debug.arch.dr7 = dr;
4140 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 4141 vmcs_readl(GUEST_CS_BASE) +
4142 vmcs_readl(GUEST_RIP);
851ba692
AK		 4143 vcpu->run->debug.arch.exception = DB_VECTOR;
4144 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4145 return 0;
4146 } else {
4147 vcpu->arch.dr7 &= ~DR7_GD;
4148 vcpu->arch.dr6 |= DR6_BD;
4149 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4150 kvm_queue_exception(vcpu, DB_VECTOR);
4151 return 1;
4152 }
4153 }
4154
bfdaab09 4155 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 4156 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4157 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4158 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 4159 unsigned long val;
4160 if (!kvm_get_dr(vcpu, dr, &val))
4161 kvm_register_write(vcpu, reg, val);
4162 } else
4163 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 4164 skip_emulated_instruction(vcpu);
4165 return 1;
4166}
4167
020df079
GN		 4168static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4169{
4170 vmcs_writel(GUEST_DR7, val);
4171}
4172
851ba692 4173static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4174{
06465c5a
AK		 4175 kvm_emulate_cpuid(vcpu);
4176 return 1;
6aa8b732
AK		 4177}
4178
851ba692 4179static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4180{
ad312c7c 4181 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 4182 u64 data;
4183
4184 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 4185 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 4186 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4187 return 1;
4188 }
4189
229456fc 4190 trace_kvm_msr_read(ecx, data);
2714d1d3 4191
6aa8b732 4192 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 4193 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4194 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 4195 skip_emulated_instruction(vcpu);
4196 return 1;
4197}
4198
851ba692 4199static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4200{
ad312c7c
ZX		 4201 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4202 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4203 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 4204
4205 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 4206 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 4207 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4208 return 1;
4209 }
4210
59200273 4211 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 4212 skip_emulated_instruction(vcpu);
4213 return 1;
4214}
4215
851ba692 4216static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4217{
3842d135 4218 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 4219 return 1;
4220}
4221
851ba692 4222static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4223{
85f455f7
ED		 4224 u32 cpu_based_vm_exec_control;
4225
4226 /* clear pending irq */
4227 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4228 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4229 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 4230
3842d135
AK		 4231 kvm_make_request(KVM_REQ_EVENT, vcpu);
4232
a26bf12a 4233 ++vcpu->stat.irq_window_exits;
2714d1d3 4234
c1150d8c
DL		 4235 /*
4236 * If the user space waits to inject interrupts, exit as soon as
4237 * possible
4238 */
8061823a 4239 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 4240 vcpu->run->request_interrupt_window &&
8061823a 4241 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 4242 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 4243 return 0;
4244 }
6aa8b732
AK		 4245 return 1;
4246}
4247
851ba692 4248static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 4249{
4250 skip_emulated_instruction(vcpu);
d3bef15f 4251 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 4252}
4253
851ba692 4254static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4255{
510043da 4256 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 4257 kvm_emulate_hypercall(vcpu);
4258 return 1;
c21415e8
IM		 4259}
4260
851ba692 4261static int handle_vmx_insn(struct kvm_vcpu *vcpu)
e3c7cb6a
AK		 4262{
4263 kvm_queue_exception(vcpu, UD_VECTOR);
4264 return 1;
4265}
4266
ec25d5e6
GN		 4267static int handle_invd(struct kvm_vcpu *vcpu)
4268{
51d8b661 4269 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 4270}
4271
851ba692 4272static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4273{
f9c617f6 4274 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4275
4276 kvm_mmu_invlpg(vcpu, exit_qualification);
4277 skip_emulated_instruction(vcpu);
4278 return 1;
4279}
4280
851ba692 4281static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 4282{
4283 skip_emulated_instruction(vcpu);
f5f48ee1 4284 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 4285 return 1;
4286}
4287
2acf923e
DC		 4288static int handle_xsetbv(struct kvm_vcpu *vcpu)
4289{
4290 u64 new_bv = kvm_read_edx_eax(vcpu);
4291 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4292
4293 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4294 skip_emulated_instruction(vcpu);
4295 return 1;
4296}
4297
851ba692 4298static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 4299{
51d8b661 4300 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 4301}
4302
851ba692 4303static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 4304{
60637aac 4305 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 4306 unsigned long exit_qualification;
e269fb21
JK		 4307 bool has_error_code = false;
4308 u32 error_code = 0;
37817f29 4309 u16 tss_selector;
64a7ec06
GN		 4310 int reason, type, idt_v;
4311
4312 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4313 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 4314
4315 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4316
4317 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 4318 if (reason == TASK_SWITCH_GATE && idt_v) {
4319 switch (type) {
4320 case INTR_TYPE_NMI_INTR:
4321 vcpu->arch.nmi_injected = false;
654f06fc 4322 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 4323 break;
4324 case INTR_TYPE_EXT_INTR:
66fd3f7f 4325 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 4326 kvm_clear_interrupt_queue(vcpu);
4327 break;
4328 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 4329 if (vmx->idt_vectoring_info &
4330 VECTORING_INFO_DELIVER_CODE_MASK) {
4331 has_error_code = true;
4332 error_code =
4333 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4334 }
4335 /* fall through */
64a7ec06
GN		 4336 case INTR_TYPE_SOFT_EXCEPTION:
4337 kvm_clear_exception_queue(vcpu);
4338 break;
4339 default:
4340 break;
4341 }
60637aac 4342 }
37817f29
IE		 4343 tss_selector = exit_qualification;
4344
64a7ec06
GN		 4345 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4346 type != INTR_TYPE_EXT_INTR &&
4347 type != INTR_TYPE_NMI_INTR))
4348 skip_emulated_instruction(vcpu);
4349
acb54517
GN		 4350 if (kvm_task_switch(vcpu, tss_selector, reason,
4351 has_error_code, error_code) == EMULATE_FAIL) {
4352 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4353 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4354 vcpu->run->internal.ndata = 0;
42dbaa5a 4355 return 0;
acb54517 4356 }
42dbaa5a
JK		 4357
4358 /* clear all local breakpoint enable flags */
4359 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4360
4361 /*
4362 * TODO: What about debug traps on tss switch?
4363 * Are we supposed to inject them and update dr6?
4364 */
4365
4366 return 1;
37817f29
IE		 4367}
4368
851ba692 4369static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 4370{
f9c617f6 4371 unsigned long exit_qualification;
1439442c 4372 gpa_t gpa;
1439442c 4373 int gla_validity;
1439442c 4374
f9c617f6 4375 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 4376
4377 if (exit_qualification & (1 << 6)) {
4378 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 4379 return -EINVAL;
1439442c
SY		 4380 }
4381
4382 gla_validity = (exit_qualification >> 7) & 0x3;
4383 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4384 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4385 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4386 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 4387 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 4388 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4389 (long unsigned int)exit_qualification);
851ba692
AK		 4390 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4391 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 4392 return 0;
1439442c
SY		 4393 }
4394
4395 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 4396 trace_kvm_page_fault(gpa, exit_qualification);
dc25e89e 4397 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
1439442c
SY		 4398}
4399
68f89400
MT		 4400static u64 ept_rsvd_mask(u64 spte, int level)
4401{
4402 int i;
4403 u64 mask = 0;
4404
4405 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4406 mask |= (1ULL << i);
4407
4408 if (level > 2)
4409 /* bits 7:3 reserved */
4410 mask |= 0xf8;
4411 else if (level == 2) {
4412 if (spte & (1ULL << 7))
4413 /* 2MB ref, bits 20:12 reserved */
4414 mask |= 0x1ff000;
4415 else
4416 /* bits 6:3 reserved */
4417 mask |= 0x78;
4418 }
4419
4420 return mask;
4421}
4422
4423static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4424 int level)
4425{
4426 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4427
4428 /* 010b (write-only) */
4429 WARN_ON((spte & 0x7) == 0x2);
4430
4431 /* 110b (write/execute) */
4432 WARN_ON((spte & 0x7) == 0x6);
4433
4434 /* 100b (execute-only) and value not supported by logical processor */
4435 if (!cpu_has_vmx_ept_execute_only())
4436 WARN_ON((spte & 0x7) == 0x4);
4437
4438 /* not 000b */
4439 if ((spte & 0x7)) {
4440 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4441
4442 if (rsvd_bits != 0) {
4443 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4444 __func__, rsvd_bits);
4445 WARN_ON(1);
4446 }
4447
4448 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4449 u64 ept_mem_type = (spte & 0x38) >> 3;
4450
4451 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4452 ept_mem_type == 7) {
4453 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4454 __func__, ept_mem_type);
4455 WARN_ON(1);
4456 }
4457 }
4458 }
4459}
4460
851ba692 4461static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 4462{
4463 u64 sptes[4];
4464 int nr_sptes, i;
4465 gpa_t gpa;
4466
4467 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4468
4469 printk(KERN_ERR "EPT: Misconfiguration.\n");
4470 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4471
4472 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4473
4474 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4475 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4476
851ba692
AK		 4477 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4478 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 4479
4480 return 0;
4481}
4482
851ba692 4483static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 4484{
4485 u32 cpu_based_vm_exec_control;
4486
4487 /* clear pending NMI */
4488 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4489 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4490 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4491 ++vcpu->stat.nmi_window_exits;
3842d135 4492 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 4493
4494 return 1;
4495}
4496
80ced186 4497static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 4498{
8b3079a5
AK		 4499 struct vcpu_vmx *vmx = to_vmx(vcpu);
4500 enum emulation_result err = EMULATE_DONE;
80ced186 4501 int ret = 1;
49e9d557
AK		 4502 u32 cpu_exec_ctrl;
4503 bool intr_window_requested;
4504
4505 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4506 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0
MG		 4507
4508 while (!guest_state_valid(vcpu)) {
49e9d557
AK		 4509 if (intr_window_requested
4510 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4511 return handle_interrupt_window(&vmx->vcpu);
4512
51d8b661 4513 err = emulate_instruction(vcpu, 0);
ea953ef0 4514
80ced186
MG		 4515 if (err == EMULATE_DO_MMIO) {
4516 ret = 0;
4517 goto out;
4518 }
1d5a4d9b 4519
6d77dbfc
GN		 4520 if (err != EMULATE_DONE)
4521 return 0;
ea953ef0
MG		 4522
4523 if (signal_pending(current))
80ced186 4524 goto out;
ea953ef0
MG		 4525 if (need_resched())
4526 schedule();
4527 }
4528
80ced186
MG		 4529 vmx->emulation_required = 0;
4530out:
4531 return ret;
ea953ef0
MG		 4532}
4533
4b8d54f9
ZE		 4534/*
4535 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4536 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4537 */
9fb41ba8 4538static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 4539{
4540 skip_emulated_instruction(vcpu);
4541 kvm_vcpu_on_spin(vcpu);
4542
4543 return 1;
4544}
4545
59708670
SY		 4546static int handle_invalid_op(struct kvm_vcpu *vcpu)
4547{
4548 kvm_queue_exception(vcpu, UD_VECTOR);
4549 return 1;
4550}
4551
ff2f6fe9
NHE		 4552/*
4553 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4554 * We could reuse a single VMCS for all the L2 guests, but we also want the
4555 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4556 * allows keeping them loaded on the processor, and in the future will allow
4557 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4558 * every entry if they never change.
4559 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4560 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4561 *
4562 * The following functions allocate and free a vmcs02 in this pool.
4563 */
4564
4565/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4566static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
4567{
4568 struct vmcs02_list *item;
4569 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4570 if (item->vmptr == vmx->nested.current_vmptr) {
4571 list_move(&item->list, &vmx->nested.vmcs02_pool);
4572 return &item->vmcs02;
4573 }
4574
4575 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
4576 /* Recycle the least recently used VMCS. */
4577 item = list_entry(vmx->nested.vmcs02_pool.prev,
4578 struct vmcs02_list, list);
4579 item->vmptr = vmx->nested.current_vmptr;
4580 list_move(&item->list, &vmx->nested.vmcs02_pool);
4581 return &item->vmcs02;
4582 }
4583
4584 /* Create a new VMCS */
4585 item = (struct vmcs02_list *)
4586 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
4587 if (!item)
4588 return NULL;
4589 item->vmcs02.vmcs = alloc_vmcs();
4590 if (!item->vmcs02.vmcs) {
4591 kfree(item);
4592 return NULL;
4593 }
4594 loaded_vmcs_init(&item->vmcs02);
4595 item->vmptr = vmx->nested.current_vmptr;
4596 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
4597 vmx->nested.vmcs02_num++;
4598 return &item->vmcs02;
4599}
4600
4601/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4602static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
4603{
4604 struct vmcs02_list *item;
4605 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4606 if (item->vmptr == vmptr) {
4607 free_loaded_vmcs(&item->vmcs02);
4608 list_del(&item->list);
4609 kfree(item);
4610 vmx->nested.vmcs02_num--;
4611 return;
4612 }
4613}
4614
4615/*
4616 * Free all VMCSs saved for this vcpu, except the one pointed by
4617 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4618 * currently used, if running L2), and vmcs01 when running L2.
4619 */
4620static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
4621{
4622 struct vmcs02_list *item, *n;
4623 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4624 if (vmx->loaded_vmcs != &item->vmcs02)
4625 free_loaded_vmcs(&item->vmcs02);
4626 list_del(&item->list);
4627 kfree(item);
4628 }
4629 vmx->nested.vmcs02_num = 0;
4630
4631 if (vmx->loaded_vmcs != &vmx->vmcs01)
4632 free_loaded_vmcs(&vmx->vmcs01);
4633}
4634
ec378aee
NHE		 4635/*
4636 * Emulate the VMXON instruction.
4637 * Currently, we just remember that VMX is active, and do not save or even
4638 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
4639 * do not currently need to store anything in that guest-allocated memory
4640 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
4641 * argument is different from the VMXON pointer (which the spec says they do).
4642 */
4643static int handle_vmon(struct kvm_vcpu *vcpu)
4644{
4645 struct kvm_segment cs;
4646 struct vcpu_vmx *vmx = to_vmx(vcpu);
4647
4648 /* The Intel VMX Instruction Reference lists a bunch of bits that
4649 * are prerequisite to running VMXON, most notably cr4.VMXE must be
4650 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
4651 * Otherwise, we should fail with #UD. We test these now:
4652 */
4653 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
4654 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
4655 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4656 kvm_queue_exception(vcpu, UD_VECTOR);
4657 return 1;
4658 }
4659
4660 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4661 if (is_long_mode(vcpu) && !cs.l) {
4662 kvm_queue_exception(vcpu, UD_VECTOR);
4663 return 1;
4664 }
4665
4666 if (vmx_get_cpl(vcpu)) {
4667 kvm_inject_gp(vcpu, 0);
4668 return 1;
4669 }
4670
ff2f6fe9
NHE		 4671 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
4672 vmx->nested.vmcs02_num = 0;
4673
ec378aee
NHE		 4674 vmx->nested.vmxon = true;
4675
4676 skip_emulated_instruction(vcpu);
4677 return 1;
4678}
4679
4680/*
4681 * Intel's VMX Instruction Reference specifies a common set of prerequisites
4682 * for running VMX instructions (except VMXON, whose prerequisites are
4683 * slightly different). It also specifies what exception to inject otherwise.
4684 */
4685static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
4686{
4687 struct kvm_segment cs;
4688 struct vcpu_vmx *vmx = to_vmx(vcpu);
4689
4690 if (!vmx->nested.vmxon) {
4691 kvm_queue_exception(vcpu, UD_VECTOR);
4692 return 0;
4693 }
4694
4695 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4696 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
4697 (is_long_mode(vcpu) && !cs.l)) {
4698 kvm_queue_exception(vcpu, UD_VECTOR);
4699 return 0;
4700 }
4701
4702 if (vmx_get_cpl(vcpu)) {
4703 kvm_inject_gp(vcpu, 0);
4704 return 0;
4705 }
4706
4707 return 1;
4708}
4709
4710/*
4711 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
4712 * just stops using VMX.
4713 */
4714static void free_nested(struct vcpu_vmx *vmx)
4715{
4716 if (!vmx->nested.vmxon)
4717 return;
4718 vmx->nested.vmxon = false;
a9d30f33
NHE		 4719 if (vmx->nested.current_vmptr != -1ull) {
4720 kunmap(vmx->nested.current_vmcs12_page);
4721 nested_release_page(vmx->nested.current_vmcs12_page);
4722 vmx->nested.current_vmptr = -1ull;
4723 vmx->nested.current_vmcs12 = NULL;
4724 }
ff2f6fe9
NHE		 4725
4726 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 4727}
4728
4729/* Emulate the VMXOFF instruction */
4730static int handle_vmoff(struct kvm_vcpu *vcpu)
4731{
4732 if (!nested_vmx_check_permission(vcpu))
4733 return 1;
4734 free_nested(to_vmx(vcpu));
4735 skip_emulated_instruction(vcpu);
4736 return 1;
4737}
4738
064aea77
NHE		 4739/*
4740 * Decode the memory-address operand of a vmx instruction, as recorded on an
4741 * exit caused by such an instruction (run by a guest hypervisor).
4742 * On success, returns 0. When the operand is invalid, returns 1 and throws
4743 * #UD or #GP.
4744 */
4745static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
4746 unsigned long exit_qualification,
4747 u32 vmx_instruction_info, gva_t *ret)
4748{
4749 /*
4750 * According to Vol. 3B, "Information for VM Exits Due to Instruction
4751 * Execution", on an exit, vmx_instruction_info holds most of the
4752 * addressing components of the operand. Only the displacement part
4753 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
4754 * For how an actual address is calculated from all these components,
4755 * refer to Vol. 1, "Operand Addressing".
4756 */
4757 int scaling = vmx_instruction_info & 3;
4758 int addr_size = (vmx_instruction_info >> 7) & 7;
4759 bool is_reg = vmx_instruction_info & (1u << 10);
4760 int seg_reg = (vmx_instruction_info >> 15) & 7;
4761 int index_reg = (vmx_instruction_info >> 18) & 0xf;
4762 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
4763 int base_reg = (vmx_instruction_info >> 23) & 0xf;
4764 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
4765
4766 if (is_reg) {
4767 kvm_queue_exception(vcpu, UD_VECTOR);
4768 return 1;
4769 }
4770
4771 /* Addr = segment_base + offset */
4772 /* offset = base + [index * scale] + displacement */
4773 *ret = vmx_get_segment_base(vcpu, seg_reg);
4774 if (base_is_valid)
4775 *ret += kvm_register_read(vcpu, base_reg);
4776 if (index_is_valid)
4777 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
4778 *ret += exit_qualification; /* holds the displacement */
4779
4780 if (addr_size == 1) /* 32 bit */
4781 *ret &= 0xffffffff;
4782
4783 /*
4784 * TODO: throw #GP (and return 1) in various cases that the VM*
4785 * instructions require it - e.g., offset beyond segment limit,
4786 * unusable or unreadable/unwritable segment, non-canonical 64-bit
4787 * address, and so on. Currently these are not checked.
4788 */
4789 return 0;
4790}
4791
0140caea
NHE		 4792/*
4793 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
4794 * set the success or error code of an emulated VMX instruction, as specified
4795 * by Vol 2B, VMX Instruction Reference, "Conventions".
4796 */
4797static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
4798{
4799 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
4800 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
4801 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
4802}
4803
4804static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
4805{
4806 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
4807 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
4808 X86_EFLAGS_SF | X86_EFLAGS_OF))
4809 | X86_EFLAGS_CF);
4810}
4811
4812static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
4813 u32 vm_instruction_error)
4814{
4815 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
4816 /*
4817 * failValid writes the error number to the current VMCS, which
4818 * can't be done there isn't a current VMCS.
4819 */
4820 nested_vmx_failInvalid(vcpu);
4821 return;
4822 }
4823 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
4824 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
4825 X86_EFLAGS_SF | X86_EFLAGS_OF))
4826 | X86_EFLAGS_ZF);
4827 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
4828}
4829
27d6c865
NHE		 4830/* Emulate the VMCLEAR instruction */
4831static int handle_vmclear(struct kvm_vcpu *vcpu)
4832{
4833 struct vcpu_vmx *vmx = to_vmx(vcpu);
4834 gva_t gva;
4835 gpa_t vmptr;
4836 struct vmcs12 *vmcs12;
4837 struct page *page;
4838 struct x86_exception e;
4839
4840 if (!nested_vmx_check_permission(vcpu))
4841 return 1;
4842
4843 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
4844 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
4845 return 1;
4846
4847 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
4848 sizeof(vmptr), &e)) {
4849 kvm_inject_page_fault(vcpu, &e);
4850 return 1;
4851 }
4852
4853 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
4854 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
4855 skip_emulated_instruction(vcpu);
4856 return 1;
4857 }
4858
4859 if (vmptr == vmx->nested.current_vmptr) {
4860 kunmap(vmx->nested.current_vmcs12_page);
4861 nested_release_page(vmx->nested.current_vmcs12_page);
4862 vmx->nested.current_vmptr = -1ull;
4863 vmx->nested.current_vmcs12 = NULL;
4864 }
4865
4866 page = nested_get_page(vcpu, vmptr);
4867 if (page == NULL) {
4868 /*
4869 * For accurate processor emulation, VMCLEAR beyond available
4870 * physical memory should do nothing at all. However, it is
4871 * possible that a nested vmx bug, not a guest hypervisor bug,
4872 * resulted in this case, so let's shut down before doing any
4873 * more damage:
4874 */
4875 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4876 return 1;
4877 }
4878 vmcs12 = kmap(page);
4879 vmcs12->launch_state = 0;
4880 kunmap(page);
4881 nested_release_page(page);
4882
4883 nested_free_vmcs02(vmx, vmptr);
4884
4885 skip_emulated_instruction(vcpu);
4886 nested_vmx_succeed(vcpu);
4887 return 1;
4888}
4889
49f705c5
NHE		 4890enum vmcs_field_type {
4891 VMCS_FIELD_TYPE_U16 = 0,
4892 VMCS_FIELD_TYPE_U64 = 1,
4893 VMCS_FIELD_TYPE_U32 = 2,
4894 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
4895};
4896
4897static inline int vmcs_field_type(unsigned long field)
4898{
4899 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
4900 return VMCS_FIELD_TYPE_U32;
4901 return (field >> 13) & 0x3 ;
4902}
4903
4904static inline int vmcs_field_readonly(unsigned long field)
4905{
4906 return (((field >> 10) & 0x3) == 1);
4907}
4908
4909/*
4910 * Read a vmcs12 field. Since these can have varying lengths and we return
4911 * one type, we chose the biggest type (u64) and zero-extend the return value
4912 * to that size. Note that the caller, handle_vmread, might need to use only
4913 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
4914 * 64-bit fields are to be returned).
4915 */
4916static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
4917 unsigned long field, u64 *ret)
4918{
4919 short offset = vmcs_field_to_offset(field);
4920 char *p;
4921
4922 if (offset < 0)
4923 return 0;
4924
4925 p = ((char *)(get_vmcs12(vcpu))) + offset;
4926
4927 switch (vmcs_field_type(field)) {
4928 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
4929 *ret = *((natural_width *)p);
4930 return 1;
4931 case VMCS_FIELD_TYPE_U16:
4932 *ret = *((u16 *)p);
4933 return 1;
4934 case VMCS_FIELD_TYPE_U32:
4935 *ret = *((u32 *)p);
4936 return 1;
4937 case VMCS_FIELD_TYPE_U64:
4938 *ret = *((u64 *)p);
4939 return 1;
4940 default:
4941 return 0; /* can never happen. */
4942 }
4943}
4944
4945/*
4946 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
4947 * used before) all generate the same failure when it is missing.
4948 */
4949static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
4950{
4951 struct vcpu_vmx *vmx = to_vmx(vcpu);
4952 if (vmx->nested.current_vmptr == -1ull) {
4953 nested_vmx_failInvalid(vcpu);
4954 skip_emulated_instruction(vcpu);
4955 return 0;
4956 }
4957 return 1;
4958}
4959
4960static int handle_vmread(struct kvm_vcpu *vcpu)
4961{
4962 unsigned long field;
4963 u64 field_value;
4964 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4965 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
4966 gva_t gva = 0;
4967
4968 if (!nested_vmx_check_permission(vcpu) ||
4969 !nested_vmx_check_vmcs12(vcpu))
4970 return 1;
4971
4972 /* Decode instruction info and find the field to read */
4973 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
4974 /* Read the field, zero-extended to a u64 field_value */
4975 if (!vmcs12_read_any(vcpu, field, &field_value)) {
4976 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
4977 skip_emulated_instruction(vcpu);
4978 return 1;
4979 }
4980 /*
4981 * Now copy part of this value to register or memory, as requested.
4982 * Note that the number of bits actually copied is 32 or 64 depending
4983 * on the guest's mode (32 or 64 bit), not on the given field's length.
4984 */
4985 if (vmx_instruction_info & (1u << 10)) {
4986 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
4987 field_value);
4988 } else {
4989 if (get_vmx_mem_address(vcpu, exit_qualification,
4990 vmx_instruction_info, &gva))
4991 return 1;
4992 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
4993 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
4994 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
4995 }
4996
4997 nested_vmx_succeed(vcpu);
4998 skip_emulated_instruction(vcpu);
4999 return 1;
5000}
5001
5002
5003static int handle_vmwrite(struct kvm_vcpu *vcpu)
5004{
5005 unsigned long field;
5006 gva_t gva;
5007 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5008 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5009 char *p;
5010 short offset;
5011 /* The value to write might be 32 or 64 bits, depending on L1's long
5012 * mode, and eventually we need to write that into a field of several
5013 * possible lengths. The code below first zero-extends the value to 64
5014 * bit (field_value), and then copies only the approriate number of
5015 * bits into the vmcs12 field.
5016 */
5017 u64 field_value = 0;
5018 struct x86_exception e;
5019
5020 if (!nested_vmx_check_permission(vcpu) ||
5021 !nested_vmx_check_vmcs12(vcpu))
5022 return 1;
5023
5024 if (vmx_instruction_info & (1u << 10))
5025 field_value = kvm_register_read(vcpu,
5026 (((vmx_instruction_info) >> 3) & 0xf));
5027 else {
5028 if (get_vmx_mem_address(vcpu, exit_qualification,
5029 vmx_instruction_info, &gva))
5030 return 1;
5031 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5032 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5033 kvm_inject_page_fault(vcpu, &e);
5034 return 1;
5035 }
5036 }
5037
5038
5039 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5040 if (vmcs_field_readonly(field)) {
5041 nested_vmx_failValid(vcpu,
5042 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5043 skip_emulated_instruction(vcpu);
5044 return 1;
5045 }
5046
5047 offset = vmcs_field_to_offset(field);
5048 if (offset < 0) {
5049 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5050 skip_emulated_instruction(vcpu);
5051 return 1;
5052 }
5053 p = ((char *) get_vmcs12(vcpu)) + offset;
5054
5055 switch (vmcs_field_type(field)) {
5056 case VMCS_FIELD_TYPE_U16:
5057 *(u16 *)p = field_value;
5058 break;
5059 case VMCS_FIELD_TYPE_U32:
5060 *(u32 *)p = field_value;
5061 break;
5062 case VMCS_FIELD_TYPE_U64:
5063 *(u64 *)p = field_value;
5064 break;
5065 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5066 *(natural_width *)p = field_value;
5067 break;
5068 default:
5069 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5070 skip_emulated_instruction(vcpu);
5071 return 1;
5072 }
5073
5074 nested_vmx_succeed(vcpu);
5075 skip_emulated_instruction(vcpu);
5076 return 1;
5077}
5078
63846663
NHE		 5079/* Emulate the VMPTRLD instruction */
5080static int handle_vmptrld(struct kvm_vcpu *vcpu)
5081{
5082 struct vcpu_vmx *vmx = to_vmx(vcpu);
5083 gva_t gva;
5084 gpa_t vmptr;
5085 struct x86_exception e;
5086
5087 if (!nested_vmx_check_permission(vcpu))
5088 return 1;
5089
5090 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5091 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5092 return 1;
5093
5094 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5095 sizeof(vmptr), &e)) {
5096 kvm_inject_page_fault(vcpu, &e);
5097 return 1;
5098 }
5099
5100 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5101 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5102 skip_emulated_instruction(vcpu);
5103 return 1;
5104 }
5105
5106 if (vmx->nested.current_vmptr != vmptr) {
5107 struct vmcs12 *new_vmcs12;
5108 struct page *page;
5109 page = nested_get_page(vcpu, vmptr);
5110 if (page == NULL) {
5111 nested_vmx_failInvalid(vcpu);
5112 skip_emulated_instruction(vcpu);
5113 return 1;
5114 }
5115 new_vmcs12 = kmap(page);
5116 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5117 kunmap(page);
5118 nested_release_page_clean(page);
5119 nested_vmx_failValid(vcpu,
5120 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5121 skip_emulated_instruction(vcpu);
5122 return 1;
5123 }
5124 if (vmx->nested.current_vmptr != -1ull) {
5125 kunmap(vmx->nested.current_vmcs12_page);
5126 nested_release_page(vmx->nested.current_vmcs12_page);
5127 }
5128
5129 vmx->nested.current_vmptr = vmptr;
5130 vmx->nested.current_vmcs12 = new_vmcs12;
5131 vmx->nested.current_vmcs12_page = page;
5132 }
5133
5134 nested_vmx_succeed(vcpu);
5135 skip_emulated_instruction(vcpu);
5136 return 1;
5137}
5138
6a4d7550
NHE		 5139/* Emulate the VMPTRST instruction */
5140static int handle_vmptrst(struct kvm_vcpu *vcpu)
5141{
5142 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5143 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5144 gva_t vmcs_gva;
5145 struct x86_exception e;
5146
5147 if (!nested_vmx_check_permission(vcpu))
5148 return 1;
5149
5150 if (get_vmx_mem_address(vcpu, exit_qualification,
5151 vmx_instruction_info, &vmcs_gva))
5152 return 1;
5153 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5154 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5155 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5156 sizeof(u64), &e)) {
5157 kvm_inject_page_fault(vcpu, &e);
5158 return 1;
5159 }
5160 nested_vmx_succeed(vcpu);
5161 skip_emulated_instruction(vcpu);
5162 return 1;
5163}
5164
6aa8b732
AK		 5165/*
5166 * The exit handlers return 1 if the exit was handled fully and guest execution
5167 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5168 * to be done to userspace and return 0.
5169 */
851ba692 5170static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 5171 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5172 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 5173 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 5174 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 5175 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 5176 [EXIT_REASON_CR_ACCESS] = handle_cr,
5177 [EXIT_REASON_DR_ACCESS] = handle_dr,
5178 [EXIT_REASON_CPUID] = handle_cpuid,
5179 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5180 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5181 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5182 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 5183 [EXIT_REASON_INVD] = handle_invd,
a7052897 5184 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 5185 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 5186 [EXIT_REASON_VMCLEAR] = handle_vmclear,
e3c7cb6a 5187 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
63846663 5188 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 5189 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 5190 [EXIT_REASON_VMREAD] = handle_vmread,
e3c7cb6a 5191 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
49f705c5 5192 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 5193 [EXIT_REASON_VMOFF] = handle_vmoff,
5194 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 5195 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5196 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 5197 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 5198 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 5199 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 5200 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 5201 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5202 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 5203 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 5204 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5205 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 5206};
5207
5208static const int kvm_vmx_max_exit_handlers =
50a3485c 5209 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 5210
586f9607
AK		 5211static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5212{
5213 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5214 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5215}
5216
6aa8b732
AK		 5217/*
5218 * The guest has exited. See if we can fix it or if we need userspace
5219 * assistance.
5220 */
851ba692 5221static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 5222{
29bd8a78 5223 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 5224 u32 exit_reason = vmx->exit_reason;
1155f76a 5225 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 5226
aa17911e 5227 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
2714d1d3 5228
80ced186
MG		 5229 /* If guest state is invalid, start emulating */
5230 if (vmx->emulation_required && emulate_invalid_guest_state)
5231 return handle_invalid_guest_state(vcpu);
1d5a4d9b 5232
5120702e
MG		 5233 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5234 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5235 vcpu->run->fail_entry.hardware_entry_failure_reason
5236 = exit_reason;
5237 return 0;
5238 }
5239
29bd8a78 5240 if (unlikely(vmx->fail)) {
851ba692
AK		 5241 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5242 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 5243 = vmcs_read32(VM_INSTRUCTION_ERROR);
5244 return 0;
5245 }
6aa8b732 5246
d77c26fc 5247 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 5248 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 5249 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5250 exit_reason != EXIT_REASON_TASK_SWITCH))
5251 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5252 "(0x%x) and exit reason is 0x%x\n",
5253 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 5254
5255 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 5256 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 5257 vmx->soft_vnmi_blocked = 0;
3b86cd99 5258 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 5259 vcpu->arch.nmi_pending) {
3b86cd99
JK		 5260 /*
5261 * This CPU don't support us in finding the end of an
5262 * NMI-blocked window if the guest runs with IRQs
5263 * disabled. So we pull the trigger after 1 s of
5264 * futile waiting, but inform the user about this.
5265 */
5266 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5267 "state on VCPU %d after 1 s timeout\n",
5268 __func__, vcpu->vcpu_id);
5269 vmx->soft_vnmi_blocked = 0;
3b86cd99 5270 }
3b86cd99
JK		 5271 }
5272
6aa8b732
AK		 5273 if (exit_reason < kvm_vmx_max_exit_handlers
5274 && kvm_vmx_exit_handlers[exit_reason])
851ba692 5275 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 5276 else {
851ba692
AK		 5277 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5278 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 5279 }
5280 return 0;
5281}
5282
95ba8273 5283static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 5284{
95ba8273 5285 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 5286 vmcs_write32(TPR_THRESHOLD, 0);
5287 return;
5288 }
5289
95ba8273 5290 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 5291}
5292
51aa01d1 5293static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 5294{
00eba012
AK		 5295 u32 exit_intr_info;
5296
5297 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
5298 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
5299 return;
5300
c5ca8e57 5301 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 5302 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 5303
5304 /* Handle machine checks before interrupts are enabled */
00eba012 5305 if (is_machine_check(exit_intr_info))
a0861c02
AK		 5306 kvm_machine_check();
5307
20f65983 5308 /* We need to handle NMIs before interrupts are enabled */
00eba012 5309 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 5310 (exit_intr_info & INTR_INFO_VALID_MASK)) {
5311 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 5312 asm("int $2");
ff9d07a0
ZY		 5313 kvm_after_handle_nmi(&vmx->vcpu);
5314 }
51aa01d1 5315}
20f65983 5316
51aa01d1
AK		 5317static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
5318{
c5ca8e57 5319 u32 exit_intr_info;
51aa01d1
AK		 5320 bool unblock_nmi;
5321 u8 vector;
5322 bool idtv_info_valid;
5323
5324 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 5325
cf393f75 5326 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 5327 if (vmx->nmi_known_unmasked)
5328 return;
c5ca8e57
AK		 5329 /*
5330 * Can't use vmx->exit_intr_info since we're not sure what
5331 * the exit reason is.
5332 */
5333 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 5334 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
5335 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
5336 /*
7b4a25cb 5337 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 5338 * Re-set bit "block by NMI" before VM entry if vmexit caused by
5339 * a guest IRET fault.
7b4a25cb
GN		 5340 * SDM 3: 23.2.2 (September 2008)
5341 * Bit 12 is undefined in any of the following cases:
5342 * If the VM exit sets the valid bit in the IDT-vectoring
5343 * information field.
5344 * If the VM exit is due to a double fault.
cf393f75 5345 */
7b4a25cb
GN		 5346 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
5347 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 5348 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5349 GUEST_INTR_STATE_NMI);
9d58b931
AK		 5350 else
5351 vmx->nmi_known_unmasked =
5352 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
5353 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 5354 } else if (unlikely(vmx->soft_vnmi_blocked))
5355 vmx->vnmi_blocked_time +=
5356 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 5357}
5358
83422e17
AK		 5359static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
5360 u32 idt_vectoring_info,
5361 int instr_len_field,
5362 int error_code_field)
51aa01d1 5363{
51aa01d1
AK		 5364 u8 vector;
5365 int type;
5366 bool idtv_info_valid;
5367
5368 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 5369
37b96e98
GN		 5370 vmx->vcpu.arch.nmi_injected = false;
5371 kvm_clear_exception_queue(&vmx->vcpu);
5372 kvm_clear_interrupt_queue(&vmx->vcpu);
5373
5374 if (!idtv_info_valid)
5375 return;
5376
3842d135
AK		 5377 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5378
668f612f
AK		 5379 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
5380 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 5381
64a7ec06 5382 switch (type) {
37b96e98
GN		 5383 case INTR_TYPE_NMI_INTR:
5384 vmx->vcpu.arch.nmi_injected = true;
668f612f 5385 /*
7b4a25cb 5386 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 5387 * Clear bit "block by NMI" before VM entry if a NMI
5388 * delivery faulted.
668f612f 5389 */
654f06fc 5390 vmx_set_nmi_mask(&vmx->vcpu, false);
37b96e98 5391 break;
37b96e98 5392 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f 5393 vmx->vcpu.arch.event_exit_inst_len =
83422e17 5394 vmcs_read32(instr_len_field);
66fd3f7f
GN		 5395 /* fall through */
5396 case INTR_TYPE_HARD_EXCEPTION:
35920a35 5397 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 5398 u32 err = vmcs_read32(error_code_field);
37b96e98 5399 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 5400 } else
5401 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 5402 break;
66fd3f7f
GN		 5403 case INTR_TYPE_SOFT_INTR:
5404 vmx->vcpu.arch.event_exit_inst_len =
83422e17 5405 vmcs_read32(instr_len_field);
66fd3f7f 5406 /* fall through */
37b96e98 5407 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 5408 kvm_queue_interrupt(&vmx->vcpu, vector,
5409 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 5410 break;
5411 default:
5412 break;
f7d9238f 5413 }
cf393f75
AK		 5414}
5415
83422e17
AK		 5416static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
5417{
5418 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
5419 VM_EXIT_INSTRUCTION_LEN,
5420 IDT_VECTORING_ERROR_CODE);
5421}
5422
b463a6f7
AK		 5423static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
5424{
5425 __vmx_complete_interrupts(to_vmx(vcpu),
5426 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5427 VM_ENTRY_INSTRUCTION_LEN,
5428 VM_ENTRY_EXCEPTION_ERROR_CODE);
5429
5430 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
5431}
5432
c801949d
AK		 5433#ifdef CONFIG_X86_64
5434#define R "r"
5435#define Q "q"
5436#else
5437#define R "e"
5438#define Q "l"
5439#endif
5440
a3b5ba49 5441static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 5442{
a2fa3e9f 5443 struct vcpu_vmx *vmx = to_vmx(vcpu);
104f226b
AK		 5444
5445 /* Record the guest's net vcpu time for enforced NMI injections. */
5446 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
5447 vmx->entry_time = ktime_get();
5448
5449 /* Don't enter VMX if guest state is invalid, let the exit handler
5450 start emulation until we arrive back to a valid state */
5451 if (vmx->emulation_required && emulate_invalid_guest_state)
5452 return;
5453
5454 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
5455 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
5456 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
5457 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
5458
5459 /* When single-stepping over STI and MOV SS, we must clear the
5460 * corresponding interruptibility bits in the guest state. Otherwise
5461 * vmentry fails as it then expects bit 14 (BS) in pending debug
5462 * exceptions being set, but that's not correct for the guest debugging
5463 * case. */
5464 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5465 vmx_set_interrupt_shadow(vcpu, 0);
5466
d462b819 5467 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 5468 asm(
6aa8b732 5469 /* Store host registers */
c801949d 5470 "push %%"R"dx; push %%"R"bp;"
40712fae 5471 "push %%"R"cx \n\t" /* placeholder for guest rcx */
c801949d 5472 "push %%"R"cx \n\t"
313dbd49
AK		 5473 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
5474 "je 1f \n\t"
5475 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 5476 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 5477 "1: \n\t"
d3edefc0
AK		 5478 /* Reload cr2 if changed */
5479 "mov %c[cr2](%0), %%"R"ax \n\t"
5480 "mov %%cr2, %%"R"dx \n\t"
5481 "cmp %%"R"ax, %%"R"dx \n\t"
5482 "je 2f \n\t"
5483 "mov %%"R"ax, %%cr2 \n\t"
5484 "2: \n\t"
6aa8b732 5485 /* Check if vmlaunch of vmresume is needed */
e08aa78a 5486 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 5487 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 5488 "mov %c[rax](%0), %%"R"ax \n\t"
5489 "mov %c[rbx](%0), %%"R"bx \n\t"
5490 "mov %c[rdx](%0), %%"R"dx \n\t"
5491 "mov %c[rsi](%0), %%"R"si \n\t"
5492 "mov %c[rdi](%0), %%"R"di \n\t"
5493 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 5494#ifdef CONFIG_X86_64
e08aa78a
AK		 5495 "mov %c[r8](%0), %%r8 \n\t"
5496 "mov %c[r9](%0), %%r9 \n\t"
5497 "mov %c[r10](%0), %%r10 \n\t"
5498 "mov %c[r11](%0), %%r11 \n\t"
5499 "mov %c[r12](%0), %%r12 \n\t"
5500 "mov %c[r13](%0), %%r13 \n\t"
5501 "mov %c[r14](%0), %%r14 \n\t"
5502 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 5503#endif
c801949d
AK		 5504 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
5505
6aa8b732 5506 /* Enter guest mode */
cd2276a7 5507 "jne .Llaunched \n\t"
4ecac3fd 5508 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 5509 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 5510 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 5511 ".Lkvm_vmx_return: "
6aa8b732 5512 /* Save guest registers, load host registers, keep flags */
40712fae
AK		 5513 "mov %0, %c[wordsize](%%"R"sp) \n\t"
5514 "pop %0 \n\t"
c801949d
AK		 5515 "mov %%"R"ax, %c[rax](%0) \n\t"
5516 "mov %%"R"bx, %c[rbx](%0) \n\t"
1c696d0e 5517 "pop"Q" %c[rcx](%0) \n\t"
c801949d
AK		 5518 "mov %%"R"dx, %c[rdx](%0) \n\t"
5519 "mov %%"R"si, %c[rsi](%0) \n\t"
5520 "mov %%"R"di, %c[rdi](%0) \n\t"
5521 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 5522#ifdef CONFIG_X86_64
e08aa78a
AK		 5523 "mov %%r8, %c[r8](%0) \n\t"
5524 "mov %%r9, %c[r9](%0) \n\t"
5525 "mov %%r10, %c[r10](%0) \n\t"
5526 "mov %%r11, %c[r11](%0) \n\t"
5527 "mov %%r12, %c[r12](%0) \n\t"
5528 "mov %%r13, %c[r13](%0) \n\t"
5529 "mov %%r14, %c[r14](%0) \n\t"
5530 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 5531#endif
c801949d
AK		 5532 "mov %%cr2, %%"R"ax \n\t"
5533 "mov %%"R"ax, %c[cr2](%0) \n\t"
5534
1c696d0e 5535 "pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 5536 "setbe %c[fail](%0) \n\t"
5537 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 5538 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 5539 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 5540 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 5541 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
5542 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
5543 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
5544 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
5545 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
5546 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
5547 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 5548#ifdef CONFIG_X86_64
ad312c7c
ZX		 5549 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
5550 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
5551 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
5552 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
5553 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
5554 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
5555 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
5556 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 5557#endif
40712fae
AK		 5558 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
5559 [wordsize]"i"(sizeof(ulong))
c2036300 5560 : "cc", "memory"
07d6f555 5561 , R"ax", R"bx", R"di", R"si"
c2036300 5562#ifdef CONFIG_X86_64
c2036300
LV		 5563 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
5564#endif
5565 );
6aa8b732 5566
6de4f3ad 5567 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 5568 | (1 << VCPU_EXREG_RFLAGS)
69c73028 5569 | (1 << VCPU_EXREG_CPL)
aff48baa 5570 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 5571 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 5572 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 5573 vcpu->arch.regs_dirty = 0;
5574
1155f76a
AK		 5575 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
5576
d77c26fc 5577 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
d462b819 5578 vmx->loaded_vmcs->launched = 1;
1b6269db 5579
51aa01d1 5580 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
51aa01d1
AK		 5581
5582 vmx_complete_atomic_exit(vmx);
5583 vmx_recover_nmi_blocking(vmx);
cf393f75 5584 vmx_complete_interrupts(vmx);
6aa8b732
AK		 5585}
5586
c801949d
AK		 5587#undef R
5588#undef Q
5589
6aa8b732
AK		 5590static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
5591{
fb3f0f51
RR		 5592 struct vcpu_vmx *vmx = to_vmx(vcpu);
5593
cdbecfc3 5594 free_vpid(vmx);
ec378aee 5595 free_nested(vmx);
d462b819 5596 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 5597 kfree(vmx->guest_msrs);
5598 kvm_vcpu_uninit(vcpu);
a4770347 5599 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 5600}
5601
fb3f0f51 5602static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 5603{
fb3f0f51 5604 int err;
c16f862d 5605 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 5606 int cpu;
6aa8b732 5607
a2fa3e9f 5608 if (!vmx)
fb3f0f51
RR		 5609 return ERR_PTR(-ENOMEM);
5610
2384d2b3
SY		 5611 allocate_vpid(vmx);
5612
fb3f0f51
RR		 5613 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
5614 if (err)
5615 goto free_vcpu;
965b58a5 5616
a2fa3e9f 5617 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 5618 err = -ENOMEM;
fb3f0f51 5619 if (!vmx->guest_msrs) {
fb3f0f51
RR		 5620 goto uninit_vcpu;
5621 }
965b58a5 5622
d462b819
NHE		 5623 vmx->loaded_vmcs = &vmx->vmcs01;
5624 vmx->loaded_vmcs->vmcs = alloc_vmcs();
5625 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 5626 goto free_msrs;
d462b819
NHE		 5627 if (!vmm_exclusive)
5628 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
5629 loaded_vmcs_init(vmx->loaded_vmcs);
5630 if (!vmm_exclusive)
5631 kvm_cpu_vmxoff();
a2fa3e9f 5632
15ad7146
AK		 5633 cpu = get_cpu();
5634 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 5635 vmx->vcpu.cpu = cpu;
8b9cf98c 5636 err = vmx_vcpu_setup(vmx);
fb3f0f51 5637 vmx_vcpu_put(&vmx->vcpu);
15ad7146 5638 put_cpu();
fb3f0f51
RR		 5639 if (err)
5640 goto free_vmcs;
5e4a0b3c 5641 if (vm_need_virtualize_apic_accesses(kvm))
be6d05cf
JK		 5642 err = alloc_apic_access_page(kvm);
5643 if (err)
5e4a0b3c 5644 goto free_vmcs;
fb3f0f51 5645
b927a3ce
SY		 5646 if (enable_ept) {
5647 if (!kvm->arch.ept_identity_map_addr)
5648 kvm->arch.ept_identity_map_addr =
5649 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 5650 err = -ENOMEM;
b7ebfb05
SY		 5651 if (alloc_identity_pagetable(kvm) != 0)
5652 goto free_vmcs;
93ea5388
GN		 5653 if (!init_rmode_identity_map(kvm))
5654 goto free_vmcs;
b927a3ce 5655 }
b7ebfb05 5656
a9d30f33
NHE		 5657 vmx->nested.current_vmptr = -1ull;
5658 vmx->nested.current_vmcs12 = NULL;
5659
fb3f0f51
RR		 5660 return &vmx->vcpu;
5661
5662free_vmcs:
d462b819 5663 free_vmcs(vmx->loaded_vmcs->vmcs);
fb3f0f51 5664free_msrs:
fb3f0f51
RR		 5665 kfree(vmx->guest_msrs);
5666uninit_vcpu:
5667 kvm_vcpu_uninit(&vmx->vcpu);
5668free_vcpu:
cdbecfc3 5669 free_vpid(vmx);
a4770347 5670 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 5671 return ERR_PTR(err);
6aa8b732
AK		 5672}
5673
002c7f7c
YS		 5674static void __init vmx_check_processor_compat(void *rtn)
5675{
5676 struct vmcs_config vmcs_conf;
5677
5678 *(int *)rtn = 0;
5679 if (setup_vmcs_config(&vmcs_conf) < 0)
5680 *(int *)rtn = -EIO;
5681 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
5682 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
5683 smp_processor_id());
5684 *(int *)rtn = -EIO;
5685 }
5686}
5687
67253af5
SY		 5688static int get_ept_level(void)
5689{
5690 return VMX_EPT_DEFAULT_GAW + 1;
5691}
5692
4b12f0de 5693static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 5694{
4b12f0de
SY		 5695 u64 ret;
5696
522c68c4
SY		 5697 /* For VT-d and EPT combination
5698 * 1. MMIO: always map as UC
5699 * 2. EPT with VT-d:
5700 * a. VT-d without snooping control feature: can't guarantee the
5701 * result, try to trust guest.
5702 * b. VT-d with snooping control feature: snooping control feature of
5703 * VT-d engine can guarantee the cache correctness. Just set it
5704 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 5705 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 5706 * consistent with host MTRR
5707 */
4b12f0de
SY		 5708 if (is_mmio)
5709 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 5710 else if (vcpu->kvm->arch.iommu_domain &&
5711 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
5712 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
5713 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 5714 else
522c68c4 5715 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 5716 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 5717
5718 return ret;
64d4d521
SY		 5719}
5720
f4c9e87c
AK		 5721#define _ER(x) { EXIT_REASON_##x, #x }
5722
229456fc 5723static const struct trace_print_flags vmx_exit_reasons_str[] = {
f4c9e87c
AK		 5724 _ER(EXCEPTION_NMI),
5725 _ER(EXTERNAL_INTERRUPT),
5726 _ER(TRIPLE_FAULT),
5727 _ER(PENDING_INTERRUPT),
5728 _ER(NMI_WINDOW),
5729 _ER(TASK_SWITCH),
5730 _ER(CPUID),
5731 _ER(HLT),
5732 _ER(INVLPG),
5733 _ER(RDPMC),
5734 _ER(RDTSC),
5735 _ER(VMCALL),
5736 _ER(VMCLEAR),
5737 _ER(VMLAUNCH),
5738 _ER(VMPTRLD),
5739 _ER(VMPTRST),
5740 _ER(VMREAD),
5741 _ER(VMRESUME),
5742 _ER(VMWRITE),
5743 _ER(VMOFF),
5744 _ER(VMON),
5745 _ER(CR_ACCESS),
5746 _ER(DR_ACCESS),
5747 _ER(IO_INSTRUCTION),
5748 _ER(MSR_READ),
5749 _ER(MSR_WRITE),
5750 _ER(MWAIT_INSTRUCTION),
5751 _ER(MONITOR_INSTRUCTION),
5752 _ER(PAUSE_INSTRUCTION),
5753 _ER(MCE_DURING_VMENTRY),
5754 _ER(TPR_BELOW_THRESHOLD),
5755 _ER(APIC_ACCESS),
5756 _ER(EPT_VIOLATION),
5757 _ER(EPT_MISCONFIG),
5758 _ER(WBINVD),
229456fc
MT		 5759 { -1, NULL }
5760};
5761
f4c9e87c
AK		 5762#undef _ER
5763
17cc3935 5764static int vmx_get_lpage_level(void)
344f414f 5765{
878403b7
SY		 5766 if (enable_ept && !cpu_has_vmx_ept_1g_page())
5767 return PT_DIRECTORY_LEVEL;
5768 else
5769 /* For shadow and EPT supported 1GB page */
5770 return PT_PDPE_LEVEL;
344f414f
JR		 5771}
5772
0e851880
SY		 5773static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
5774{
4e47c7a6
SY		 5775 struct kvm_cpuid_entry2 *best;
5776 struct vcpu_vmx *vmx = to_vmx(vcpu);
5777 u32 exec_control;
5778
5779 vmx->rdtscp_enabled = false;
5780 if (vmx_rdtscp_supported()) {
5781 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5782 if (exec_control & SECONDARY_EXEC_RDTSCP) {
5783 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
5784 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
5785 vmx->rdtscp_enabled = true;
5786 else {
5787 exec_control &= ~SECONDARY_EXEC_RDTSCP;
5788 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
5789 exec_control);
5790 }
5791 }
5792 }
0e851880
SY		 5793}
5794
d4330ef2
JR		 5795static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
5796{
5797}
5798
8a76d7f2
JR		 5799static int vmx_check_intercept(struct kvm_vcpu *vcpu,
5800 struct x86_instruction_info *info,
5801 enum x86_intercept_stage stage)
5802{
5803 return X86EMUL_CONTINUE;
5804}
5805
cbdd1bea 5806static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 5807 .cpu_has_kvm_support = cpu_has_kvm_support,
5808 .disabled_by_bios = vmx_disabled_by_bios,
5809 .hardware_setup = hardware_setup,
5810 .hardware_unsetup = hardware_unsetup,
002c7f7c 5811 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 5812 .hardware_enable = hardware_enable,
5813 .hardware_disable = hardware_disable,
04547156 5814 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 5815
5816 .vcpu_create = vmx_create_vcpu,
5817 .vcpu_free = vmx_free_vcpu,
04d2cc77 5818 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 5819
04d2cc77 5820 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 5821 .vcpu_load = vmx_vcpu_load,
5822 .vcpu_put = vmx_vcpu_put,
5823
5824 .set_guest_debug = set_guest_debug,
5825 .get_msr = vmx_get_msr,
5826 .set_msr = vmx_set_msr,
5827 .get_segment_base = vmx_get_segment_base,
5828 .get_segment = vmx_get_segment,
5829 .set_segment = vmx_set_segment,
2e4d2653 5830 .get_cpl = vmx_get_cpl,
6aa8b732 5831 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 5832 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 5833 .decache_cr3 = vmx_decache_cr3,
25c4c276 5834 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 5835 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 5836 .set_cr3 = vmx_set_cr3,
5837 .set_cr4 = vmx_set_cr4,
6aa8b732 5838 .set_efer = vmx_set_efer,
6aa8b732
AK		 5839 .get_idt = vmx_get_idt,
5840 .set_idt = vmx_set_idt,
5841 .get_gdt = vmx_get_gdt,
5842 .set_gdt = vmx_set_gdt,
020df079 5843 .set_dr7 = vmx_set_dr7,
5fdbf976 5844 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 5845 .get_rflags = vmx_get_rflags,
5846 .set_rflags = vmx_set_rflags,
ebcbab4c 5847 .fpu_activate = vmx_fpu_activate,
02daab21 5848 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 5849
5850 .tlb_flush = vmx_flush_tlb,
6aa8b732 5851
6aa8b732 5852 .run = vmx_vcpu_run,
6062d012 5853 .handle_exit = vmx_handle_exit,
6aa8b732 5854 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 5855 .set_interrupt_shadow = vmx_set_interrupt_shadow,
5856 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 5857 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 5858 .set_irq = vmx_inject_irq,
95ba8273 5859 .set_nmi = vmx_inject_nmi,
298101da 5860 .queue_exception = vmx_queue_exception,
b463a6f7 5861 .cancel_injection = vmx_cancel_injection,
78646121 5862 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 5863 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 5864 .get_nmi_mask = vmx_get_nmi_mask,
5865 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 5866 .enable_nmi_window = enable_nmi_window,
5867 .enable_irq_window = enable_irq_window,
5868 .update_cr8_intercept = update_cr8_intercept,
95ba8273 5869
cbc94022 5870 .set_tss_addr = vmx_set_tss_addr,
67253af5 5871 .get_tdp_level = get_ept_level,
4b12f0de 5872 .get_mt_mask = vmx_get_mt_mask,
229456fc 5873
586f9607 5874 .get_exit_info = vmx_get_exit_info,
229456fc 5875 .exit_reasons_str = vmx_exit_reasons_str,
586f9607 5876
17cc3935 5877 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 5878
5879 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 5880
5881 .rdtscp_supported = vmx_rdtscp_supported,
d4330ef2
JR		 5882
5883 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 5884
5885 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 5886
4051b188 5887 .set_tsc_khz = vmx_set_tsc_khz,
99e3e30a 5888 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 5889 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 5890 .compute_tsc_offset = vmx_compute_tsc_offset,
1c97f0a0
JR		 5891
5892 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 5893
5894 .check_intercept = vmx_check_intercept,
6aa8b732
AK		 5895};
5896
5897static int __init vmx_init(void)
5898{
26bb0981
AK		 5899 int r, i;
5900
5901 rdmsrl_safe(MSR_EFER, &host_efer);
5902
5903 for (i = 0; i < NR_VMX_MSR; ++i)
5904 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 5905
3e7c73e9 5906 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 5907 if (!vmx_io_bitmap_a)
5908 return -ENOMEM;
5909
3e7c73e9 5910 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 5911 if (!vmx_io_bitmap_b) {
5912 r = -ENOMEM;
5913 goto out;
5914 }
5915
5897297b
AK		 5916 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
5917 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 5918 r = -ENOMEM;
5919 goto out1;
5920 }
5921
5897297b
AK		 5922 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
5923 if (!vmx_msr_bitmap_longmode) {
5924 r = -ENOMEM;
5925 goto out2;
5926 }
5927
fdef3ad1
HQ		 5928 /*
5929 * Allow direct access to the PC debug port (it is often used for I/O
5930 * delays, but the vmexits simply slow things down).
5931 */
3e7c73e9
AK		 5932 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
5933 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 5934
3e7c73e9 5935 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 5936
5897297b
AK		 5937 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
5938 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 5939
2384d2b3
SY		 5940 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
5941
0ee75bea
AK		 5942 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
5943 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 5944 if (r)
5897297b 5945 goto out3;
25c5f225 5946
5897297b
AK		 5947 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
5948 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
5949 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
5950 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
5951 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
5952 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 5953
089d034e 5954 if (enable_ept) {
1439442c 5955 bypass_guest_pf = 0;
534e38b4 5956 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 5957 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 5958 kvm_enable_tdp();
5959 } else
5960 kvm_disable_tdp();
1439442c 5961
c7addb90
AK		 5962 if (bypass_guest_pf)
5963 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
5964
fdef3ad1
HQ		 5965 return 0;
5966
5897297b
AK		 5967out3:
5968 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 5969out2:
5897297b 5970 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 5971out1:
3e7c73e9 5972 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 5973out:
3e7c73e9 5974 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 5975 return r;
6aa8b732
AK		 5976}
5977
5978static void __exit vmx_exit(void)
5979{
5897297b
AK		 5980 free_page((unsigned long)vmx_msr_bitmap_legacy);
5981 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 5982 free_page((unsigned long)vmx_io_bitmap_b);
5983 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 5984
cb498ea2 5985 kvm_exit();
6aa8b732
AK		 5986}
5987
5988module_init(vmx_init)
5989module_exit(vmx_exit)
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