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KVM: SVM: Make dump_vmcb static, reduce text
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
e495606d 21
edf88417 22#include <linux/kvm_host.h>
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/mm.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
c7addb90 28#include <linux/moduleparam.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
cafd6659 31#include <linux/tboot.h>
5fdbf976 32#include "kvm_cache_regs.h"
35920a35 33#include "x86.h"
e495606d 34
6aa8b732 35#include <asm/io.h>
3b3be0d1 36#include <asm/desc.h>
13673a90 37#include <asm/vmx.h>
6210e37b 38#include <asm/virtext.h>
a0861c02 39#include <asm/mce.h>
2acf923e
DC		 40#include <asm/i387.h>
41#include <asm/xcr.h>
6aa8b732 42
229456fc
MT		 43#include "trace.h"
44
4ecac3fd
AK		 45#define __ex(x) __kvm_handle_fault_on_reboot(x)
46
6aa8b732
AK		 47MODULE_AUTHOR("Qumranet");
48MODULE_LICENSE("GPL");
49
4462d21a 50static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 51module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 52
4462d21a 53static int __read_mostly enable_vpid = 1;
736caefe 54module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 55
4462d21a 56static int __read_mostly flexpriority_enabled = 1;
736caefe 57module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 58
4462d21a 59static int __read_mostly enable_ept = 1;
736caefe 60module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 61
3a624e29
NK		 62static int __read_mostly enable_unrestricted_guest = 1;
63module_param_named(unrestricted_guest,
64 enable_unrestricted_guest, bool, S_IRUGO);
65
4462d21a 66static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 67module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 68
b923e62e
DX		 69static int __read_mostly vmm_exclusive = 1;
70module_param(vmm_exclusive, bool, S_IRUGO);
71
443381a8
AL		 72static int __read_mostly yield_on_hlt = 1;
73module_param(yield_on_hlt, bool, S_IRUGO);
74
cdc0e244
AK		 75#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
76 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
77#define KVM_GUEST_CR0_MASK \
78 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
79#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 80 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 81#define KVM_VM_CR0_ALWAYS_ON \
82 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 83#define KVM_CR4_GUEST_OWNED_BITS \
84 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
85 | X86_CR4_OSXMMEXCPT)
86
cdc0e244
AK		 87#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
88#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
89
78ac8b47
AK		 90#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
91
4b8d54f9
ZE		 92/*
93 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
94 * ple_gap: upper bound on the amount of time between two successive
95 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 96 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 97 * ple_window: upper bound on the amount of time a guest is allowed to execute
98 * in a PAUSE loop. Tests indicate that most spinlocks are held for
99 * less than 2^12 cycles
100 * Time is measured based on a counter that runs at the same rate as the TSC,
101 * refer SDM volume 3b section 21.6.13 & 22.1.3.
102 */
00c25bce 103#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 104#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
105static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
106module_param(ple_gap, int, S_IRUGO);
107
108static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
109module_param(ple_window, int, S_IRUGO);
110
61d2ef2c
AK		 111#define NR_AUTOLOAD_MSRS 1
112
a2fa3e9f
GH		 113struct vmcs {
114 u32 revision_id;
115 u32 abort;
116 char data[0];
117};
118
26bb0981
AK		 119struct shared_msr_entry {
120 unsigned index;
121 u64 data;
d5696725 122 u64 mask;
26bb0981
AK		 123};
124
a2fa3e9f 125struct vcpu_vmx {
fb3f0f51 126 struct kvm_vcpu vcpu;
543e4243 127 struct list_head local_vcpus_link;
313dbd49 128 unsigned long host_rsp;
a2fa3e9f 129 int launched;
29bd8a78 130 u8 fail;
69c73028 131 u8 cpl;
9d58b931 132 bool nmi_known_unmasked;
51aa01d1 133 u32 exit_intr_info;
1155f76a 134 u32 idt_vectoring_info;
6de12732 135 ulong rflags;
26bb0981 136 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 137 int nmsrs;
138 int save_nmsrs;
a2fa3e9f 139#ifdef CONFIG_X86_64
44ea2b17
AK		 140 u64 msr_host_kernel_gs_base;
141 u64 msr_guest_kernel_gs_base;
a2fa3e9f
GH		 142#endif
143 struct vmcs *vmcs;
61d2ef2c
AK		 144 struct msr_autoload {
145 unsigned nr;
146 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
147 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
148 } msr_autoload;
a2fa3e9f
GH		 149 struct {
150 int loaded;
151 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 152 int gs_ldt_reload_needed;
153 int fs_reload_needed;
d77c26fc 154 } host_state;
9c8cba37 155 struct {
7ffd92c5 156 int vm86_active;
78ac8b47 157 ulong save_rflags;
7ffd92c5
AK		 158 struct kvm_save_segment {
159 u16 selector;
160 unsigned long base;
161 u32 limit;
162 u32 ar;
163 } tr, es, ds, fs, gs;
9c8cba37 164 } rmode;
2384d2b3 165 int vpid;
04fa4d32 166 bool emulation_required;
3b86cd99
JK		 167
168 /* Support for vnmi-less CPUs */
169 int soft_vnmi_blocked;
170 ktime_t entry_time;
171 s64 vnmi_blocked_time;
a0861c02 172 u32 exit_reason;
4e47c7a6
SY		 173
174 bool rdtscp_enabled;
a2fa3e9f
GH		 175};
176
177static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
178{
fb3f0f51 179 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 180}
181
4e1096d2 182static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 183static void kvm_cpu_vmxon(u64 addr);
184static void kvm_cpu_vmxoff(void);
aff48baa 185static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 186static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
75880a01 187
6aa8b732
AK		 188static DEFINE_PER_CPU(struct vmcs *, vmxarea);
189static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
543e4243 190static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
3444d7da 191static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 192
3e7c73e9
AK		 193static unsigned long *vmx_io_bitmap_a;
194static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 195static unsigned long *vmx_msr_bitmap_legacy;
196static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 197
110312c8
AK		 198static bool cpu_has_load_ia32_efer;
199
2384d2b3
SY		 200static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
201static DEFINE_SPINLOCK(vmx_vpid_lock);
202
1c3d14fe 203static struct vmcs_config {
6aa8b732
AK		 204 int size;
205 int order;
206 u32 revision_id;
1c3d14fe
YS		 207 u32 pin_based_exec_ctrl;
208 u32 cpu_based_exec_ctrl;
f78e0e2e 209 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 210 u32 vmexit_ctrl;
211 u32 vmentry_ctrl;
212} vmcs_config;
6aa8b732 213
efff9e53 214static struct vmx_capability {
d56f546d
SY		 215 u32 ept;
216 u32 vpid;
217} vmx_capability;
218
6aa8b732
AK		 219#define VMX_SEGMENT_FIELD(seg) \
220 [VCPU_SREG_##seg] = { \
221 .selector = GUEST_##seg##_SELECTOR, \
222 .base = GUEST_##seg##_BASE, \
223 .limit = GUEST_##seg##_LIMIT, \
224 .ar_bytes = GUEST_##seg##_AR_BYTES, \
225 }
226
227static struct kvm_vmx_segment_field {
228 unsigned selector;
229 unsigned base;
230 unsigned limit;
231 unsigned ar_bytes;
232} kvm_vmx_segment_fields[] = {
233 VMX_SEGMENT_FIELD(CS),
234 VMX_SEGMENT_FIELD(DS),
235 VMX_SEGMENT_FIELD(ES),
236 VMX_SEGMENT_FIELD(FS),
237 VMX_SEGMENT_FIELD(GS),
238 VMX_SEGMENT_FIELD(SS),
239 VMX_SEGMENT_FIELD(TR),
240 VMX_SEGMENT_FIELD(LDTR),
241};
242
26bb0981
AK		 243static u64 host_efer;
244
6de4f3ad
AK		 245static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
246
4d56c8a7 247/*
8c06585d 248 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 249 * away by decrementing the array size.
250 */
6aa8b732 251static const u32 vmx_msr_index[] = {
05b3e0c2 252#ifdef CONFIG_X86_64
44ea2b17 253 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 254#endif
8c06585d 255 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 256};
9d8f549d 257#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 258
31299944 259static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 260{
261 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
262 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 263 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 264}
265
31299944 266static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 267{
268 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
269 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 270 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 271}
272
31299944 273static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 274{
275 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
276 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 277 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 278}
279
31299944 280static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 281{
282 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
283 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
284}
285
31299944 286static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 287{
288 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
289 INTR_INFO_VALID_MASK)) ==
290 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
291}
292
31299944 293static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 294{
04547156 295 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 296}
297
31299944 298static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 299{
04547156 300 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 301}
302
31299944 303static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 304{
04547156 305 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 306}
307
31299944 308static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 309{
04547156
SY		 310 return vmcs_config.cpu_based_exec_ctrl &
311 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 312}
313
774ead3a 314static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 315{
04547156
SY		 316 return vmcs_config.cpu_based_2nd_exec_ctrl &
317 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
318}
319
320static inline bool cpu_has_vmx_flexpriority(void)
321{
322 return cpu_has_vmx_tpr_shadow() &&
323 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 324}
325
e799794e
MT		 326static inline bool cpu_has_vmx_ept_execute_only(void)
327{
31299944 328 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 329}
330
331static inline bool cpu_has_vmx_eptp_uncacheable(void)
332{
31299944 333 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 334}
335
336static inline bool cpu_has_vmx_eptp_writeback(void)
337{
31299944 338 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 339}
340
341static inline bool cpu_has_vmx_ept_2m_page(void)
342{
31299944 343 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 344}
345
878403b7
SY		 346static inline bool cpu_has_vmx_ept_1g_page(void)
347{
31299944 348 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 349}
350
4bc9b982
SY		 351static inline bool cpu_has_vmx_ept_4levels(void)
352{
353 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
354}
355
31299944 356static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 357{
31299944 358 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 359}
360
31299944 361static inline bool cpu_has_vmx_invept_context(void)
d56f546d 362{
31299944 363 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 364}
365
31299944 366static inline bool cpu_has_vmx_invept_global(void)
d56f546d 367{
31299944 368 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 369}
370
518c8aee
GJ		 371static inline bool cpu_has_vmx_invvpid_single(void)
372{
373 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
374}
375
b9d762fa
GJ		 376static inline bool cpu_has_vmx_invvpid_global(void)
377{
378 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
379}
380
31299944 381static inline bool cpu_has_vmx_ept(void)
d56f546d 382{
04547156
SY		 383 return vmcs_config.cpu_based_2nd_exec_ctrl &
384 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 385}
386
31299944 387static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 388{
389 return vmcs_config.cpu_based_2nd_exec_ctrl &
390 SECONDARY_EXEC_UNRESTRICTED_GUEST;
391}
392
31299944 393static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 394{
395 return vmcs_config.cpu_based_2nd_exec_ctrl &
396 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
397}
398
31299944 399static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 400{
6d3e435e 401 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 402}
403
31299944 404static inline bool cpu_has_vmx_vpid(void)
2384d2b3 405{
04547156
SY		 406 return vmcs_config.cpu_based_2nd_exec_ctrl &
407 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 408}
409
31299944 410static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 411{
412 return vmcs_config.cpu_based_2nd_exec_ctrl &
413 SECONDARY_EXEC_RDTSCP;
414}
415
31299944 416static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 417{
418 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
419}
420
f5f48ee1
SY		 421static inline bool cpu_has_vmx_wbinvd_exit(void)
422{
423 return vmcs_config.cpu_based_2nd_exec_ctrl &
424 SECONDARY_EXEC_WBINVD_EXITING;
425}
426
04547156
SY		 427static inline bool report_flexpriority(void)
428{
429 return flexpriority_enabled;
430}
431
8b9cf98c 432static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 433{
434 int i;
435
a2fa3e9f 436 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 437 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 438 return i;
439 return -1;
440}
441
2384d2b3
SY		 442static inline void __invvpid(int ext, u16 vpid, gva_t gva)
443{
444 struct {
445 u64 vpid : 16;
446 u64 rsvd : 48;
447 u64 gva;
448 } operand = { vpid, 0, gva };
449
4ecac3fd 450 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 451 /* CF==1 or ZF==1 --> rc = -1 */
452 "; ja 1f ; ud2 ; 1:"
453 : : "a"(&operand), "c"(ext) : "cc", "memory");
454}
455
1439442c
SY		 456static inline void __invept(int ext, u64 eptp, gpa_t gpa)
457{
458 struct {
459 u64 eptp, gpa;
460 } operand = {eptp, gpa};
461
4ecac3fd 462 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 463 /* CF==1 or ZF==1 --> rc = -1 */
464 "; ja 1f ; ud2 ; 1:\n"
465 : : "a" (&operand), "c" (ext) : "cc", "memory");
466}
467
26bb0981 468static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 469{
470 int i;
471
8b9cf98c 472 i = __find_msr_index(vmx, msr);
a75beee6 473 if (i >= 0)
a2fa3e9f 474 return &vmx->guest_msrs[i];
8b6d44c7 475 return NULL;
7725f0ba
AK		 476}
477
6aa8b732
AK		 478static void vmcs_clear(struct vmcs *vmcs)
479{
480 u64 phys_addr = __pa(vmcs);
481 u8 error;
482
4ecac3fd 483 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 484 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 485 : "cc", "memory");
486 if (error)
487 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
488 vmcs, phys_addr);
489}
490
7725b894
DX		 491static void vmcs_load(struct vmcs *vmcs)
492{
493 u64 phys_addr = __pa(vmcs);
494 u8 error;
495
496 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 497 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 498 : "cc", "memory");
499 if (error)
500 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
501 vmcs, phys_addr);
502}
503
6aa8b732
AK		 504static void __vcpu_clear(void *arg)
505{
8b9cf98c 506 struct vcpu_vmx *vmx = arg;
d3b2c338 507 int cpu = raw_smp_processor_id();
6aa8b732 508
8b9cf98c 509 if (vmx->vcpu.cpu == cpu)
a2fa3e9f
GH		 510 vmcs_clear(vmx->vmcs);
511 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
6aa8b732 512 per_cpu(current_vmcs, cpu) = NULL;
543e4243
AK		 513 list_del(&vmx->local_vcpus_link);
514 vmx->vcpu.cpu = -1;
515 vmx->launched = 0;
6aa8b732
AK		 516}
517
8b9cf98c 518static void vcpu_clear(struct vcpu_vmx *vmx)
8d0be2b3 519{
eae5ecb5
AK		 520 if (vmx->vcpu.cpu == -1)
521 return;
8691e5a8 522 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
8d0be2b3
AK		 523}
524
1760dd49 525static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 526{
527 if (vmx->vpid == 0)
528 return;
529
518c8aee
GJ		 530 if (cpu_has_vmx_invvpid_single())
531 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 532}
533
b9d762fa
GJ		 534static inline void vpid_sync_vcpu_global(void)
535{
536 if (cpu_has_vmx_invvpid_global())
537 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
538}
539
540static inline void vpid_sync_context(struct vcpu_vmx *vmx)
541{
542 if (cpu_has_vmx_invvpid_single())
1760dd49 543 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 544 else
545 vpid_sync_vcpu_global();
546}
547
1439442c
SY		 548static inline void ept_sync_global(void)
549{
550 if (cpu_has_vmx_invept_global())
551 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
552}
553
554static inline void ept_sync_context(u64 eptp)
555{
089d034e 556 if (enable_ept) {
1439442c
SY		 557 if (cpu_has_vmx_invept_context())
558 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
559 else
560 ept_sync_global();
561 }
562}
563
564static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
565{
089d034e 566 if (enable_ept) {
1439442c
SY		 567 if (cpu_has_vmx_invept_individual_addr())
568 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
569 eptp, gpa);
570 else
571 ept_sync_context(eptp);
572 }
573}
574
6aa8b732
AK		 575static unsigned long vmcs_readl(unsigned long field)
576{
a295673a 577 unsigned long value = 0;
6aa8b732 578
4ecac3fd 579 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
a295673a 580 : "+a"(value) : "d"(field) : "cc");
6aa8b732
AK		 581 return value;
582}
583
584static u16 vmcs_read16(unsigned long field)
585{
586 return vmcs_readl(field);
587}
588
589static u32 vmcs_read32(unsigned long field)
590{
591 return vmcs_readl(field);
592}
593
594static u64 vmcs_read64(unsigned long field)
595{
05b3e0c2 596#ifdef CONFIG_X86_64
6aa8b732
AK		 597 return vmcs_readl(field);
598#else
599 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
600#endif
601}
602
e52de1b8
AK		 603static noinline void vmwrite_error(unsigned long field, unsigned long value)
604{
605 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
606 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
607 dump_stack();
608}
609
6aa8b732
AK		 610static void vmcs_writel(unsigned long field, unsigned long value)
611{
612 u8 error;
613
4ecac3fd 614 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 615 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 616 if (unlikely(error))
617 vmwrite_error(field, value);
6aa8b732
AK		 618}
619
620static void vmcs_write16(unsigned long field, u16 value)
621{
622 vmcs_writel(field, value);
623}
624
625static void vmcs_write32(unsigned long field, u32 value)
626{
627 vmcs_writel(field, value);
628}
629
630static void vmcs_write64(unsigned long field, u64 value)
631{
6aa8b732 632 vmcs_writel(field, value);
7682f2d0 633#ifndef CONFIG_X86_64
6aa8b732
AK		 634 asm volatile ("");
635 vmcs_writel(field+1, value >> 32);
636#endif
637}
638
2ab455cc
AL		 639static void vmcs_clear_bits(unsigned long field, u32 mask)
640{
641 vmcs_writel(field, vmcs_readl(field) & ~mask);
642}
643
644static void vmcs_set_bits(unsigned long field, u32 mask)
645{
646 vmcs_writel(field, vmcs_readl(field) | mask);
647}
648
abd3f2d6
AK		 649static void update_exception_bitmap(struct kvm_vcpu *vcpu)
650{
651 u32 eb;
652
fd7373cc
JK		 653 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
654 (1u << NM_VECTOR) | (1u << DB_VECTOR);
655 if ((vcpu->guest_debug &
656 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
657 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
658 eb |= 1u << BP_VECTOR;
7ffd92c5 659 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 660 eb = ~0;
089d034e 661 if (enable_ept)
1439442c 662 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 663 if (vcpu->fpu_active)
664 eb &= ~(1u << NM_VECTOR);
abd3f2d6
AK		 665 vmcs_write32(EXCEPTION_BITMAP, eb);
666}
667
61d2ef2c
AK		 668static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
669{
670 unsigned i;
671 struct msr_autoload *m = &vmx->msr_autoload;
672
110312c8
AK		 673 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
674 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
675 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
676 return;
677 }
678
61d2ef2c
AK		 679 for (i = 0; i < m->nr; ++i)
680 if (m->guest[i].index == msr)
681 break;
682
683 if (i == m->nr)
684 return;
685 --m->nr;
686 m->guest[i] = m->guest[m->nr];
687 m->host[i] = m->host[m->nr];
688 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
689 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
690}
691
692static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
693 u64 guest_val, u64 host_val)
694{
695 unsigned i;
696 struct msr_autoload *m = &vmx->msr_autoload;
697
110312c8
AK		 698 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
699 vmcs_write64(GUEST_IA32_EFER, guest_val);
700 vmcs_write64(HOST_IA32_EFER, host_val);
701 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
702 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
703 return;
704 }
705
61d2ef2c
AK		 706 for (i = 0; i < m->nr; ++i)
707 if (m->guest[i].index == msr)
708 break;
709
710 if (i == m->nr) {
711 ++m->nr;
712 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
713 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
714 }
715
716 m->guest[i].index = msr;
717 m->guest[i].value = guest_val;
718 m->host[i].index = msr;
719 m->host[i].value = host_val;
720}
721
33ed6329
AK		 722static void reload_tss(void)
723{
33ed6329
AK		 724 /*
725 * VT restores TR but not its size. Useless.
726 */
d359192f 727 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 728 struct desc_struct *descs;
33ed6329 729
d359192f 730 descs = (void *)gdt->address;
33ed6329
AK		 731 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
732 load_TR_desc();
33ed6329
AK		 733}
734
92c0d900 735static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 736{
3a34a881 737 u64 guest_efer;
51c6cf66
AK		 738 u64 ignore_bits;
739
f6801dff 740 guest_efer = vmx->vcpu.arch.efer;
3a34a881 741
51c6cf66
AK		 742 /*
743 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
744 * outside long mode
745 */
746 ignore_bits = EFER_NX | EFER_SCE;
747#ifdef CONFIG_X86_64
748 ignore_bits |= EFER_LMA | EFER_LME;
749 /* SCE is meaningful only in long mode on Intel */
750 if (guest_efer & EFER_LMA)
751 ignore_bits &= ~(u64)EFER_SCE;
752#endif
51c6cf66
AK		 753 guest_efer &= ~ignore_bits;
754 guest_efer |= host_efer & ignore_bits;
26bb0981 755 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 756 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 757
758 clear_atomic_switch_msr(vmx, MSR_EFER);
759 /* On ept, can't emulate nx, and must switch nx atomically */
760 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
761 guest_efer = vmx->vcpu.arch.efer;
762 if (!(guest_efer & EFER_LMA))
763 guest_efer &= ~EFER_LME;
764 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
765 return false;
766 }
767
26bb0981 768 return true;
51c6cf66
AK		 769}
770
2d49ec72
GN		 771static unsigned long segment_base(u16 selector)
772{
d359192f 773 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 774 struct desc_struct *d;
775 unsigned long table_base;
776 unsigned long v;
777
778 if (!(selector & ~3))
779 return 0;
780
d359192f 781 table_base = gdt->address;
2d49ec72
GN		 782
783 if (selector & 4) { /* from ldt */
784 u16 ldt_selector = kvm_read_ldt();
785
786 if (!(ldt_selector & ~3))
787 return 0;
788
789 table_base = segment_base(ldt_selector);
790 }
791 d = (struct desc_struct *)(table_base + (selector & ~7));
792 v = get_desc_base(d);
793#ifdef CONFIG_X86_64
794 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
795 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
796#endif
797 return v;
798}
799
800static inline unsigned long kvm_read_tr_base(void)
801{
802 u16 tr;
803 asm("str %0" : "=g"(tr));
804 return segment_base(tr);
805}
806
04d2cc77 807static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 808{
04d2cc77 809 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 810 int i;
04d2cc77 811
a2fa3e9f 812 if (vmx->host_state.loaded)
33ed6329
AK		 813 return;
814
a2fa3e9f 815 vmx->host_state.loaded = 1;
33ed6329
AK		 816 /*
817 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
818 * allow segment selectors with cpl > 0 or ti == 1.
819 */
d6e88aec 820 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 821 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 822 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 823 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 824 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 825 vmx->host_state.fs_reload_needed = 0;
826 } else {
33ed6329 827 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 828 vmx->host_state.fs_reload_needed = 1;
33ed6329 829 }
9581d442 830 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 831 if (!(vmx->host_state.gs_sel & 7))
832 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 833 else {
834 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 835 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 836 }
837
838#ifdef CONFIG_X86_64
839 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
840 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
841#else
a2fa3e9f
GH		 842 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
843 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 844#endif
707c0874
AK		 845
846#ifdef CONFIG_X86_64
c8770e7b
AK		 847 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
848 if (is_long_mode(&vmx->vcpu))
44ea2b17 849 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 850#endif
26bb0981
AK		 851 for (i = 0; i < vmx->save_nmsrs; ++i)
852 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 853 vmx->guest_msrs[i].data,
854 vmx->guest_msrs[i].mask);
33ed6329
AK		 855}
856
a9b21b62 857static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 858{
a2fa3e9f 859 if (!vmx->host_state.loaded)
33ed6329
AK		 860 return;
861
e1beb1d3 862 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 863 vmx->host_state.loaded = 0;
c8770e7b
AK		 864#ifdef CONFIG_X86_64
865 if (is_long_mode(&vmx->vcpu))
866 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
867#endif
152d3f2f 868 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 869 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 870#ifdef CONFIG_X86_64
9581d442 871 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 872#else
873 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 874#endif
33ed6329 875 }
0a77fe4c
AK		 876 if (vmx->host_state.fs_reload_needed)
877 loadsegment(fs, vmx->host_state.fs_sel);
152d3f2f 878 reload_tss();
44ea2b17 879#ifdef CONFIG_X86_64
c8770e7b 880 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 881#endif
1c11e713
AK		 882 if (current_thread_info()->status & TS_USEDFPU)
883 clts();
3444d7da 884 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 885}
886
a9b21b62
AK		 887static void vmx_load_host_state(struct vcpu_vmx *vmx)
888{
889 preempt_disable();
890 __vmx_load_host_state(vmx);
891 preempt_enable();
892}
893
6aa8b732
AK		 894/*
895 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
896 * vcpu mutex is already taken.
897 */
15ad7146 898static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 899{
a2fa3e9f 900 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 901 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 902
4610c9cc
DX		 903 if (!vmm_exclusive)
904 kvm_cpu_vmxon(phys_addr);
905 else if (vcpu->cpu != cpu)
8b9cf98c 906 vcpu_clear(vmx);
6aa8b732 907
a2fa3e9f 908 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
a2fa3e9f 909 per_cpu(current_vmcs, cpu) = vmx->vmcs;
7725b894 910 vmcs_load(vmx->vmcs);
6aa8b732
AK		 911 }
912
913 if (vcpu->cpu != cpu) {
d359192f 914 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 915 unsigned long sysenter_esp;
916
a8eeb04a 917 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be
DX		 918 local_irq_disable();
919 list_add(&vmx->local_vcpus_link,
920 &per_cpu(vcpus_on_cpu, cpu));
921 local_irq_enable();
922
6aa8b732
AK		 923 /*
924 * Linux uses per-cpu TSS and GDT, so set these when switching
925 * processors.
926 */
d6e88aec 927 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 928 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 929
930 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
931 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
932 }
6aa8b732
AK		 933}
934
935static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
936{
a9b21b62 937 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 938 if (!vmm_exclusive) {
b923e62e 939 __vcpu_clear(to_vmx(vcpu));
4610c9cc
DX		 940 kvm_cpu_vmxoff();
941 }
6aa8b732
AK		 942}
943
5fd86fcf
AK		 944static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
945{
81231c69
AK		 946 ulong cr0;
947
5fd86fcf
AK		 948 if (vcpu->fpu_active)
949 return;
950 vcpu->fpu_active = 1;
81231c69
AK		 951 cr0 = vmcs_readl(GUEST_CR0);
952 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
953 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
954 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 955 update_exception_bitmap(vcpu);
edcafe3c
AK		 956 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
957 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 958}
959
edcafe3c
AK		 960static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
961
5fd86fcf
AK		 962static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
963{
edcafe3c 964 vmx_decache_cr0_guest_bits(vcpu);
81231c69 965 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 966 update_exception_bitmap(vcpu);
edcafe3c
AK		 967 vcpu->arch.cr0_guest_owned_bits = 0;
968 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
969 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 970}
971
6aa8b732
AK		 972static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
973{
78ac8b47 974 unsigned long rflags, save_rflags;
345dcaa8 975
6de12732
AK		 976 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
977 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
978 rflags = vmcs_readl(GUEST_RFLAGS);
979 if (to_vmx(vcpu)->rmode.vm86_active) {
980 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
981 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
982 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
983 }
984 to_vmx(vcpu)->rflags = rflags;
78ac8b47 985 }
6de12732 986 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 987}
988
989static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
990{
6de12732 991 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
69c73028 992 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6de12732 993 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 994 if (to_vmx(vcpu)->rmode.vm86_active) {
995 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 996 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 997 }
6aa8b732
AK		 998 vmcs_writel(GUEST_RFLAGS, rflags);
999}
1000
2809f5d2
GC		 1001static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1002{
1003 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1004 int ret = 0;
1005
1006 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1007 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1008 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1009 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1010
1011 return ret & mask;
1012}
1013
1014static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1015{
1016 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1017 u32 interruptibility = interruptibility_old;
1018
1019 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1020
48005f64 1021 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1022 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1023 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1024 interruptibility |= GUEST_INTR_STATE_STI;
1025
1026 if ((interruptibility != interruptibility_old))
1027 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1028}
1029
6aa8b732
AK		 1030static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1031{
1032 unsigned long rip;
6aa8b732 1033
5fdbf976 1034 rip = kvm_rip_read(vcpu);
6aa8b732 1035 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1036 kvm_rip_write(vcpu, rip);
6aa8b732 1037
2809f5d2
GC		 1038 /* skipping an emulated instruction also counts */
1039 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1040}
1041
443381a8
AL		 1042static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1043{
1044 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1045 * explicitly skip the instruction because if the HLT state is set, then
1046 * the instruction is already executing and RIP has already been
1047 * advanced. */
1048 if (!yield_on_hlt &&
1049 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1050 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1051}
1052
298101da 1053static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1054 bool has_error_code, u32 error_code,
1055 bool reinject)
298101da 1056{
77ab6db0 1057 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1058 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1059
8ab2d2e2 1060 if (has_error_code) {
77ab6db0 1061 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1062 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1063 }
77ab6db0 1064
7ffd92c5 1065 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1066 int inc_eip = 0;
1067 if (kvm_exception_is_soft(nr))
1068 inc_eip = vcpu->arch.event_exit_inst_len;
1069 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1070 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1071 return;
1072 }
1073
66fd3f7f
GN		 1074 if (kvm_exception_is_soft(nr)) {
1075 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1076 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1077 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1078 } else
1079 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1080
1081 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
443381a8 1082 vmx_clear_hlt(vcpu);
298101da
AK		 1083}
1084
4e47c7a6
SY		 1085static bool vmx_rdtscp_supported(void)
1086{
1087 return cpu_has_vmx_rdtscp();
1088}
1089
a75beee6
ED		 1090/*
1091 * Swap MSR entry in host/guest MSR entry array.
1092 */
8b9cf98c 1093static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1094{
26bb0981 1095 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1096
1097 tmp = vmx->guest_msrs[to];
1098 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1099 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1100}
1101
e38aea3e
AK		 1102/*
1103 * Set up the vmcs to automatically save and restore system
1104 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1105 * mode, as fiddling with msrs is very expensive.
1106 */
8b9cf98c 1107static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1108{
26bb0981 1109 int save_nmsrs, index;
5897297b 1110 unsigned long *msr_bitmap;
e38aea3e 1111
33f9c505 1112 vmx_load_host_state(vmx);
a75beee6
ED		 1113 save_nmsrs = 0;
1114#ifdef CONFIG_X86_64
8b9cf98c 1115 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1116 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1117 if (index >= 0)
8b9cf98c
RR		 1118 move_msr_up(vmx, index, save_nmsrs++);
1119 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1120 if (index >= 0)
8b9cf98c
RR		 1121 move_msr_up(vmx, index, save_nmsrs++);
1122 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1123 if (index >= 0)
8b9cf98c 1124 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1125 index = __find_msr_index(vmx, MSR_TSC_AUX);
1126 if (index >= 0 && vmx->rdtscp_enabled)
1127 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1128 /*
8c06585d 1129 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1130 * if efer.sce is enabled.
1131 */
8c06585d 1132 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1133 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1134 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1135 }
1136#endif
92c0d900
AK		 1137 index = __find_msr_index(vmx, MSR_EFER);
1138 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1139 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1140
26bb0981 1141 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1142
1143 if (cpu_has_vmx_msr_bitmap()) {
1144 if (is_long_mode(&vmx->vcpu))
1145 msr_bitmap = vmx_msr_bitmap_longmode;
1146 else
1147 msr_bitmap = vmx_msr_bitmap_legacy;
1148
1149 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1150 }
e38aea3e
AK		 1151}
1152
6aa8b732
AK		 1153/*
1154 * reads and returns guest's timestamp counter "register"
1155 * guest_tsc = host_tsc + tsc_offset -- 21.3
1156 */
1157static u64 guest_read_tsc(void)
1158{
1159 u64 host_tsc, tsc_offset;
1160
1161 rdtscll(host_tsc);
1162 tsc_offset = vmcs_read64(TSC_OFFSET);
1163 return host_tsc + tsc_offset;
1164}
1165
4051b188
JR		 1166/*
1167 * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1168 * ioctl. In this case the call-back should update internal vmx state to make
1169 * the changes effective.
1170 */
1171static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1172{
1173 /* Nothing to do here */
1174}
1175
6aa8b732 1176/*
99e3e30a 1177 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1178 */
99e3e30a 1179static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1180{
f4e1b3c8 1181 vmcs_write64(TSC_OFFSET, offset);
6aa8b732
AK		 1182}
1183
e48672fa
ZA		 1184static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1185{
1186 u64 offset = vmcs_read64(TSC_OFFSET);
1187 vmcs_write64(TSC_OFFSET, offset + adjustment);
1188}
1189
857e4099
JR		 1190static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1191{
1192 return target_tsc - native_read_tsc();
1193}
1194
6aa8b732
AK		 1195/*
1196 * Reads an msr value (of 'msr_index') into 'pdata'.
1197 * Returns 0 on success, non-0 otherwise.
1198 * Assumes vcpu_load() was already called.
1199 */
1200static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1201{
1202 u64 data;
26bb0981 1203 struct shared_msr_entry *msr;
6aa8b732
AK		 1204
1205 if (!pdata) {
1206 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1207 return -EINVAL;
1208 }
1209
1210 switch (msr_index) {
05b3e0c2 1211#ifdef CONFIG_X86_64
6aa8b732
AK		 1212 case MSR_FS_BASE:
1213 data = vmcs_readl(GUEST_FS_BASE);
1214 break;
1215 case MSR_GS_BASE:
1216 data = vmcs_readl(GUEST_GS_BASE);
1217 break;
44ea2b17
AK		 1218 case MSR_KERNEL_GS_BASE:
1219 vmx_load_host_state(to_vmx(vcpu));
1220 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1221 break;
26bb0981 1222#endif
6aa8b732 1223 case MSR_EFER:
3bab1f5d 1224 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 1225 case MSR_IA32_TSC:
6aa8b732
AK		 1226 data = guest_read_tsc();
1227 break;
1228 case MSR_IA32_SYSENTER_CS:
1229 data = vmcs_read32(GUEST_SYSENTER_CS);
1230 break;
1231 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1232 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1233 break;
1234 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1235 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1236 break;
4e47c7a6
SY		 1237 case MSR_TSC_AUX:
1238 if (!to_vmx(vcpu)->rdtscp_enabled)
1239 return 1;
1240 /* Otherwise falls through */
6aa8b732 1241 default:
26bb0981 1242 vmx_load_host_state(to_vmx(vcpu));
8b9cf98c 1243 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 1244 if (msr) {
542423b0 1245 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 1246 data = msr->data;
1247 break;
6aa8b732 1248 }
3bab1f5d 1249 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 1250 }
1251
1252 *pdata = data;
1253 return 0;
1254}
1255
1256/*
1257 * Writes msr value into into the appropriate "register".
1258 * Returns 0 on success, non-0 otherwise.
1259 * Assumes vcpu_load() was already called.
1260 */
1261static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1262{
a2fa3e9f 1263 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1264 struct shared_msr_entry *msr;
2cc51560
ED		 1265 int ret = 0;
1266
6aa8b732 1267 switch (msr_index) {
3bab1f5d 1268 case MSR_EFER:
a9b21b62 1269 vmx_load_host_state(vmx);
2cc51560 1270 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 1271 break;
16175a79 1272#ifdef CONFIG_X86_64
6aa8b732
AK		 1273 case MSR_FS_BASE:
1274 vmcs_writel(GUEST_FS_BASE, data);
1275 break;
1276 case MSR_GS_BASE:
1277 vmcs_writel(GUEST_GS_BASE, data);
1278 break;
44ea2b17
AK		 1279 case MSR_KERNEL_GS_BASE:
1280 vmx_load_host_state(vmx);
1281 vmx->msr_guest_kernel_gs_base = data;
1282 break;
6aa8b732
AK		 1283#endif
1284 case MSR_IA32_SYSENTER_CS:
1285 vmcs_write32(GUEST_SYSENTER_CS, data);
1286 break;
1287 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1288 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1289 break;
1290 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1291 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1292 break;
af24a4e4 1293 case MSR_IA32_TSC:
99e3e30a 1294 kvm_write_tsc(vcpu, data);
6aa8b732 1295 break;
468d472f
SY		 1296 case MSR_IA32_CR_PAT:
1297 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1298 vmcs_write64(GUEST_IA32_PAT, data);
1299 vcpu->arch.pat = data;
1300 break;
1301 }
4e47c7a6
SY		 1302 ret = kvm_set_msr_common(vcpu, msr_index, data);
1303 break;
1304 case MSR_TSC_AUX:
1305 if (!vmx->rdtscp_enabled)
1306 return 1;
1307 /* Check reserved bit, higher 32 bits should be zero */
1308 if ((data >> 32) != 0)
1309 return 1;
1310 /* Otherwise falls through */
6aa8b732 1311 default:
8b9cf98c 1312 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 1313 if (msr) {
542423b0 1314 vmx_load_host_state(vmx);
3bab1f5d
AK		 1315 msr->data = data;
1316 break;
6aa8b732 1317 }
2cc51560 1318 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 1319 }
1320
2cc51560 1321 return ret;
6aa8b732
AK		 1322}
1323
5fdbf976 1324static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1325{
5fdbf976
MT		 1326 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1327 switch (reg) {
1328 case VCPU_REGS_RSP:
1329 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1330 break;
1331 case VCPU_REGS_RIP:
1332 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1333 break;
6de4f3ad
AK		 1334 case VCPU_EXREG_PDPTR:
1335 if (enable_ept)
1336 ept_save_pdptrs(vcpu);
1337 break;
5fdbf976
MT		 1338 default:
1339 break;
1340 }
6aa8b732
AK		 1341}
1342
355be0b9 1343static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 1344{
ae675ef0
JK		 1345 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1346 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1347 else
1348 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1349
abd3f2d6 1350 update_exception_bitmap(vcpu);
6aa8b732
AK		 1351}
1352
1353static __init int cpu_has_kvm_support(void)
1354{
6210e37b 1355 return cpu_has_vmx();
6aa8b732
AK		 1356}
1357
1358static __init int vmx_disabled_by_bios(void)
1359{
1360 u64 msr;
1361
1362 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 1363 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 1364 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 1365 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1366 && tboot_enabled())
1367 return 1;
23f3e991 1368 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 1369 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 1370 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 1371 && !tboot_enabled()) {
1372 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 1373 "activate TXT before enabling KVM\n");
cafd6659 1374 return 1;
f9335afe 1375 }
23f3e991
JC		 1376 /* launched w/o TXT and VMX disabled */
1377 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1378 && !tboot_enabled())
1379 return 1;
cafd6659
SW		 1380 }
1381
1382 return 0;
6aa8b732
AK		 1383}
1384
7725b894
DX		 1385static void kvm_cpu_vmxon(u64 addr)
1386{
1387 asm volatile (ASM_VMX_VMXON_RAX
1388 : : "a"(&addr), "m"(addr)
1389 : "memory", "cc");
1390}
1391
10474ae8 1392static int hardware_enable(void *garbage)
6aa8b732
AK		 1393{
1394 int cpu = raw_smp_processor_id();
1395 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 1396 u64 old, test_bits;
6aa8b732 1397
10474ae8
AG		 1398 if (read_cr4() & X86_CR4_VMXE)
1399 return -EBUSY;
1400
543e4243 1401 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
6aa8b732 1402 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 1403
1404 test_bits = FEATURE_CONTROL_LOCKED;
1405 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1406 if (tboot_enabled())
1407 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1408
1409 if ((old & test_bits) != test_bits) {
6aa8b732 1410 /* enable and lock */
cafd6659
SW		 1411 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1412 }
66aee91a 1413 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 1414
4610c9cc
DX		 1415 if (vmm_exclusive) {
1416 kvm_cpu_vmxon(phys_addr);
1417 ept_sync_global();
1418 }
10474ae8 1419
3444d7da
AK		 1420 store_gdt(&__get_cpu_var(host_gdt));
1421
10474ae8 1422 return 0;
6aa8b732
AK		 1423}
1424
543e4243
AK		 1425static void vmclear_local_vcpus(void)
1426{
1427 int cpu = raw_smp_processor_id();
1428 struct vcpu_vmx *vmx, *n;
1429
1430 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1431 local_vcpus_link)
1432 __vcpu_clear(vmx);
1433}
1434
710ff4a8
EH		 1435
1436/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1437 * tricks.
1438 */
1439static void kvm_cpu_vmxoff(void)
6aa8b732 1440{
4ecac3fd 1441 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 1442}
1443
710ff4a8
EH		 1444static void hardware_disable(void *garbage)
1445{
4610c9cc
DX		 1446 if (vmm_exclusive) {
1447 vmclear_local_vcpus();
1448 kvm_cpu_vmxoff();
1449 }
7725b894 1450 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 1451}
1452
1c3d14fe 1453static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1454 u32 msr, u32 *result)
1c3d14fe
YS		 1455{
1456 u32 vmx_msr_low, vmx_msr_high;
1457 u32 ctl = ctl_min | ctl_opt;
1458
1459 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1460
1461 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1462 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1463
1464 /* Ensure minimum (required) set of control bits are supported. */
1465 if (ctl_min & ~ctl)
002c7f7c 1466 return -EIO;
1c3d14fe
YS		 1467
1468 *result = ctl;
1469 return 0;
1470}
1471
110312c8
AK		 1472static __init bool allow_1_setting(u32 msr, u32 ctl)
1473{
1474 u32 vmx_msr_low, vmx_msr_high;
1475
1476 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1477 return vmx_msr_high & ctl;
1478}
1479
002c7f7c 1480static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 1481{
1482 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1483 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1484 u32 _pin_based_exec_control = 0;
1485 u32 _cpu_based_exec_control = 0;
f78e0e2e 1486 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1487 u32 _vmexit_control = 0;
1488 u32 _vmentry_control = 0;
1489
1490 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 1491 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 1492 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1493 &_pin_based_exec_control) < 0)
002c7f7c 1494 return -EIO;
1c3d14fe 1495
443381a8 1496 min =
1c3d14fe
YS		 1497#ifdef CONFIG_X86_64
1498 CPU_BASED_CR8_LOAD_EXITING |
1499 CPU_BASED_CR8_STORE_EXITING |
1500#endif
d56f546d
SY		 1501 CPU_BASED_CR3_LOAD_EXITING |
1502 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 1503 CPU_BASED_USE_IO_BITMAPS |
1504 CPU_BASED_MOV_DR_EXITING |
a7052897 1505 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 1506 CPU_BASED_MWAIT_EXITING |
1507 CPU_BASED_MONITOR_EXITING |
a7052897 1508 CPU_BASED_INVLPG_EXITING;
443381a8
AL		 1509
1510 if (yield_on_hlt)
1511 min |= CPU_BASED_HLT_EXITING;
1512
f78e0e2e 1513 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1514 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1515 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1516 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1517 &_cpu_based_exec_control) < 0)
002c7f7c 1518 return -EIO;
6e5d865c
YS		 1519#ifdef CONFIG_X86_64
1520 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1521 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1522 ~CPU_BASED_CR8_STORE_EXITING;
1523#endif
f78e0e2e 1524 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1525 min2 = 0;
1526 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 1527 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1528 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 1529 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 1530 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 1531 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1532 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 1533 if (adjust_vmx_controls(min2, opt2,
1534 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1535 &_cpu_based_2nd_exec_control) < 0)
1536 return -EIO;
1537 }
1538#ifndef CONFIG_X86_64
1539 if (!(_cpu_based_2nd_exec_control &
1540 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1541 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1542#endif
d56f546d 1543 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 1544 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1545 enabled */
5fff7d27
GN		 1546 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1547 CPU_BASED_CR3_STORE_EXITING |
1548 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 1549 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1550 vmx_capability.ept, vmx_capability.vpid);
1551 }
1c3d14fe
YS		 1552
1553 min = 0;
1554#ifdef CONFIG_X86_64
1555 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1556#endif
468d472f 1557 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 1558 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1559 &_vmexit_control) < 0)
002c7f7c 1560 return -EIO;
1c3d14fe 1561
468d472f
SY		 1562 min = 0;
1563 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 1564 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1565 &_vmentry_control) < 0)
002c7f7c 1566 return -EIO;
6aa8b732 1567
c68876fd 1568 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 1569
1570 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1571 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 1572 return -EIO;
1c3d14fe
YS		 1573
1574#ifdef CONFIG_X86_64
1575 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1576 if (vmx_msr_high & (1u<<16))
002c7f7c 1577 return -EIO;
1c3d14fe
YS		 1578#endif
1579
1580 /* Require Write-Back (WB) memory type for VMCS accesses. */
1581 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 1582 return -EIO;
1c3d14fe 1583
002c7f7c
YS		 1584 vmcs_conf->size = vmx_msr_high & 0x1fff;
1585 vmcs_conf->order = get_order(vmcs_config.size);
1586 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 1587
002c7f7c
YS		 1588 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1589 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 1590 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 1591 vmcs_conf->vmexit_ctrl = _vmexit_control;
1592 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 1593
110312c8
AK		 1594 cpu_has_load_ia32_efer =
1595 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
1596 VM_ENTRY_LOAD_IA32_EFER)
1597 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
1598 VM_EXIT_LOAD_IA32_EFER);
1599
1c3d14fe 1600 return 0;
c68876fd 1601}
6aa8b732
AK		 1602
1603static struct vmcs *alloc_vmcs_cpu(int cpu)
1604{
1605 int node = cpu_to_node(cpu);
1606 struct page *pages;
1607 struct vmcs *vmcs;
1608
6484eb3e 1609 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 1610 if (!pages)
1611 return NULL;
1612 vmcs = page_address(pages);
1c3d14fe
YS		 1613 memset(vmcs, 0, vmcs_config.size);
1614 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 1615 return vmcs;
1616}
1617
1618static struct vmcs *alloc_vmcs(void)
1619{
d3b2c338 1620 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 1621}
1622
1623static void free_vmcs(struct vmcs *vmcs)
1624{
1c3d14fe 1625 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 1626}
1627
39959588 1628static void free_kvm_area(void)
6aa8b732
AK		 1629{
1630 int cpu;
1631
3230bb47 1632 for_each_possible_cpu(cpu) {
6aa8b732 1633 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 1634 per_cpu(vmxarea, cpu) = NULL;
1635 }
6aa8b732
AK		 1636}
1637
6aa8b732
AK		 1638static __init int alloc_kvm_area(void)
1639{
1640 int cpu;
1641
3230bb47 1642 for_each_possible_cpu(cpu) {
6aa8b732
AK		 1643 struct vmcs *vmcs;
1644
1645 vmcs = alloc_vmcs_cpu(cpu);
1646 if (!vmcs) {
1647 free_kvm_area();
1648 return -ENOMEM;
1649 }
1650
1651 per_cpu(vmxarea, cpu) = vmcs;
1652 }
1653 return 0;
1654}
1655
1656static __init int hardware_setup(void)
1657{
002c7f7c
YS		 1658 if (setup_vmcs_config(&vmcs_config) < 0)
1659 return -EIO;
50a37eb4
JR		 1660
1661 if (boot_cpu_has(X86_FEATURE_NX))
1662 kvm_enable_efer_bits(EFER_NX);
1663
93ba03c2
SY		 1664 if (!cpu_has_vmx_vpid())
1665 enable_vpid = 0;
1666
4bc9b982
SY		 1667 if (!cpu_has_vmx_ept() ||
1668 !cpu_has_vmx_ept_4levels()) {
93ba03c2 1669 enable_ept = 0;
3a624e29
NK		 1670 enable_unrestricted_guest = 0;
1671 }
1672
1673 if (!cpu_has_vmx_unrestricted_guest())
1674 enable_unrestricted_guest = 0;
93ba03c2
SY		 1675
1676 if (!cpu_has_vmx_flexpriority())
1677 flexpriority_enabled = 0;
1678
95ba8273
GN		 1679 if (!cpu_has_vmx_tpr_shadow())
1680 kvm_x86_ops->update_cr8_intercept = NULL;
1681
54dee993
MT		 1682 if (enable_ept && !cpu_has_vmx_ept_2m_page())
1683 kvm_disable_largepages();
1684
4b8d54f9
ZE		 1685 if (!cpu_has_vmx_ple())
1686 ple_gap = 0;
1687
6aa8b732
AK		 1688 return alloc_kvm_area();
1689}
1690
1691static __exit void hardware_unsetup(void)
1692{
1693 free_kvm_area();
1694}
1695
6aa8b732
AK		 1696static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1697{
1698 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1699
6af11b9e 1700 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 1701 vmcs_write16(sf->selector, save->selector);
1702 vmcs_writel(sf->base, save->base);
1703 vmcs_write32(sf->limit, save->limit);
1704 vmcs_write32(sf->ar_bytes, save->ar);
1705 } else {
1706 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1707 << AR_DPL_SHIFT;
1708 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1709 }
1710}
1711
1712static void enter_pmode(struct kvm_vcpu *vcpu)
1713{
1714 unsigned long flags;
a89a8fb9 1715 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1716
a89a8fb9 1717 vmx->emulation_required = 1;
7ffd92c5 1718 vmx->rmode.vm86_active = 0;
6aa8b732 1719
d0ba64f9 1720 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
7ffd92c5
AK		 1721 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1722 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1723 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 1724
1725 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 1726 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1727 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 1728 vmcs_writel(GUEST_RFLAGS, flags);
1729
66aee91a
RR		 1730 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1731 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 1732
1733 update_exception_bitmap(vcpu);
1734
a89a8fb9
MG		 1735 if (emulate_invalid_guest_state)
1736 return;
1737
7ffd92c5
AK		 1738 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1739 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1740 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1741 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732
AK		 1742
1743 vmcs_write16(GUEST_SS_SELECTOR, 0);
1744 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1745
1746 vmcs_write16(GUEST_CS_SELECTOR,
1747 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1748 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1749}
1750
d77c26fc 1751static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 1752{
bfc6d222 1753 if (!kvm->arch.tss_addr) {
bc6678a3
MT		 1754 struct kvm_memslots *slots;
1755 gfn_t base_gfn;
1756
90d83dc3 1757 slots = kvm_memslots(kvm);
f495c6e5 1758 base_gfn = slots->memslots[0].base_gfn +
46a26bf5 1759 kvm->memslots->memslots[0].npages - 3;
cbc94022
IE		 1760 return base_gfn << PAGE_SHIFT;
1761 }
bfc6d222 1762 return kvm->arch.tss_addr;
6aa8b732
AK		 1763}
1764
1765static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1766{
1767 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1768
1769 save->selector = vmcs_read16(sf->selector);
1770 save->base = vmcs_readl(sf->base);
1771 save->limit = vmcs_read32(sf->limit);
1772 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32 1773 vmcs_write16(sf->selector, save->base >> 4);
444e863d 1774 vmcs_write32(sf->base, save->base & 0xffff0);
6aa8b732
AK		 1775 vmcs_write32(sf->limit, 0xffff);
1776 vmcs_write32(sf->ar_bytes, 0xf3);
444e863d
GN		 1777 if (save->base & 0xf)
1778 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
1779 " aligned when entering protected mode (seg=%d)",
1780 seg);
6aa8b732
AK		 1781}
1782
1783static void enter_rmode(struct kvm_vcpu *vcpu)
1784{
1785 unsigned long flags;
a89a8fb9 1786 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 1787
3a624e29
NK		 1788 if (enable_unrestricted_guest)
1789 return;
1790
a89a8fb9 1791 vmx->emulation_required = 1;
7ffd92c5 1792 vmx->rmode.vm86_active = 1;
6aa8b732 1793
776e58ea
GN		 1794 /*
1795 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
1796 * vcpu. Call it here with phys address pointing 16M below 4G.
1797 */
1798 if (!vcpu->kvm->arch.tss_addr) {
1799 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
1800 "called before entering vcpu\n");
1801 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
1802 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
1803 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
1804 }
1805
d0ba64f9 1806 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
7ffd92c5 1807 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 1808 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1809
7ffd92c5 1810 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 1811 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1812
7ffd92c5 1813 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 1814 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1815
1816 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 1817 vmx->rmode.save_rflags = flags;
6aa8b732 1818
053de044 1819 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 1820
1821 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 1822 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 1823 update_exception_bitmap(vcpu);
1824
a89a8fb9
MG		 1825 if (emulate_invalid_guest_state)
1826 goto continue_rmode;
1827
6aa8b732
AK		 1828 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1829 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1830 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1831
1832 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 1833 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 1834 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1835 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 1836 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1837
7ffd92c5
AK		 1838 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1839 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1840 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1841 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 1842
a89a8fb9 1843continue_rmode:
8668a3c4 1844 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 1845}
1846
401d10de
AS		 1847static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1848{
1849 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 1850 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1851
1852 if (!msr)
1853 return;
401d10de 1854
44ea2b17
AK		 1855 /*
1856 * Force kernel_gs_base reloading before EFER changes, as control
1857 * of this msr depends on is_long_mode().
1858 */
1859 vmx_load_host_state(to_vmx(vcpu));
f6801dff 1860 vcpu->arch.efer = efer;
401d10de
AS		 1861 if (efer & EFER_LMA) {
1862 vmcs_write32(VM_ENTRY_CONTROLS,
1863 vmcs_read32(VM_ENTRY_CONTROLS) |
1864 VM_ENTRY_IA32E_MODE);
1865 msr->data = efer;
1866 } else {
1867 vmcs_write32(VM_ENTRY_CONTROLS,
1868 vmcs_read32(VM_ENTRY_CONTROLS) &
1869 ~VM_ENTRY_IA32E_MODE);
1870
1871 msr->data = efer & ~EFER_LME;
1872 }
1873 setup_msrs(vmx);
1874}
1875
05b3e0c2 1876#ifdef CONFIG_X86_64
6aa8b732
AK		 1877
1878static void enter_lmode(struct kvm_vcpu *vcpu)
1879{
1880 u32 guest_tr_ar;
1881
1882 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1883 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1884 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 1885 __func__);
6aa8b732
AK		 1886 vmcs_write32(GUEST_TR_AR_BYTES,
1887 (guest_tr_ar & ~AR_TYPE_MASK)
1888 | AR_TYPE_BUSY_64_TSS);
1889 }
da38f438 1890 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 1891}
1892
1893static void exit_lmode(struct kvm_vcpu *vcpu)
1894{
6aa8b732
AK		 1895 vmcs_write32(VM_ENTRY_CONTROLS,
1896 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 1897 & ~VM_ENTRY_IA32E_MODE);
da38f438 1898 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 1899}
1900
1901#endif
1902
2384d2b3
SY		 1903static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1904{
b9d762fa 1905 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 1906 if (enable_ept) {
1907 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
1908 return;
4e1096d2 1909 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 1910 }
2384d2b3
SY		 1911}
1912
e8467fda
AK		 1913static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1914{
1915 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1916
1917 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1918 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1919}
1920
aff48baa
AK		 1921static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
1922{
1923 if (enable_ept && is_paging(vcpu))
1924 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
1925 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
1926}
1927
25c4c276 1928static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 1929{
fc78f519
AK		 1930 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1931
1932 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1933 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 1934}
1935
1439442c
SY		 1936static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1937{
6de4f3ad
AK		 1938 if (!test_bit(VCPU_EXREG_PDPTR,
1939 (unsigned long *)&vcpu->arch.regs_dirty))
1940 return;
1941
1439442c 1942 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 1943 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
1944 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
1945 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
1946 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 1947 }
1948}
1949
8f5d549f
AK		 1950static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1951{
1952 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 1953 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1954 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1955 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1956 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 1957 }
6de4f3ad
AK		 1958
1959 __set_bit(VCPU_EXREG_PDPTR,
1960 (unsigned long *)&vcpu->arch.regs_avail);
1961 __set_bit(VCPU_EXREG_PDPTR,
1962 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 1963}
1964
1439442c
SY		 1965static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1966
1967static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1968 unsigned long cr0,
1969 struct kvm_vcpu *vcpu)
1970{
aff48baa 1971 vmx_decache_cr3(vcpu);
1439442c
SY		 1972 if (!(cr0 & X86_CR0_PG)) {
1973 /* From paging/starting to nonpaging */
1974 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1975 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 1976 (CPU_BASED_CR3_LOAD_EXITING |
1977 CPU_BASED_CR3_STORE_EXITING));
1978 vcpu->arch.cr0 = cr0;
fc78f519 1979 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 1980 } else if (!is_paging(vcpu)) {
1981 /* From nonpaging to paging */
1982 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 1983 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 1984 ~(CPU_BASED_CR3_LOAD_EXITING |
1985 CPU_BASED_CR3_STORE_EXITING));
1986 vcpu->arch.cr0 = cr0;
fc78f519 1987 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 1988 }
95eb84a7
SY		 1989
1990 if (!(cr0 & X86_CR0_WP))
1991 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 1992}
1993
6aa8b732
AK		 1994static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1995{
7ffd92c5 1996 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 1997 unsigned long hw_cr0;
1998
1999 if (enable_unrestricted_guest)
2000 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2001 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2002 else
2003 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 2004
7ffd92c5 2005 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 2006 enter_pmode(vcpu);
2007
7ffd92c5 2008 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 2009 enter_rmode(vcpu);
2010
05b3e0c2 2011#ifdef CONFIG_X86_64
f6801dff 2012 if (vcpu->arch.efer & EFER_LME) {
707d92fa 2013 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 2014 enter_lmode(vcpu);
707d92fa 2015 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 2016 exit_lmode(vcpu);
2017 }
2018#endif
2019
089d034e 2020 if (enable_ept)
1439442c
SY		 2021 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2022
02daab21 2023 if (!vcpu->fpu_active)
81231c69 2024 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 2025
6aa8b732 2026 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 2027 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 2028 vcpu->arch.cr0 = cr0;
69c73028 2029 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 2030}
2031
1439442c
SY		 2032static u64 construct_eptp(unsigned long root_hpa)
2033{
2034 u64 eptp;
2035
2036 /* TODO write the value reading from MSR */
2037 eptp = VMX_EPT_DEFAULT_MT |
2038 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
2039 eptp |= (root_hpa & PAGE_MASK);
2040
2041 return eptp;
2042}
2043
6aa8b732
AK		 2044static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2045{
1439442c
SY		 2046 unsigned long guest_cr3;
2047 u64 eptp;
2048
2049 guest_cr3 = cr3;
089d034e 2050 if (enable_ept) {
1439442c
SY		 2051 eptp = construct_eptp(cr3);
2052 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 2053 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 2054 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 2055 ept_load_pdptrs(vcpu);
1439442c
SY		 2056 }
2057
2384d2b3 2058 vmx_flush_tlb(vcpu);
1439442c 2059 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 2060}
2061
2062static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2063{
7ffd92c5 2064 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 2065 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2066
ad312c7c 2067 vcpu->arch.cr4 = cr4;
bc23008b
AK		 2068 if (enable_ept) {
2069 if (!is_paging(vcpu)) {
2070 hw_cr4 &= ~X86_CR4_PAE;
2071 hw_cr4 |= X86_CR4_PSE;
2072 } else if (!(cr4 & X86_CR4_PAE)) {
2073 hw_cr4 &= ~X86_CR4_PAE;
2074 }
2075 }
1439442c
SY		 2076
2077 vmcs_writel(CR4_READ_SHADOW, cr4);
2078 vmcs_writel(GUEST_CR4, hw_cr4);
6aa8b732
AK		 2079}
2080
6aa8b732
AK		 2081static void vmx_get_segment(struct kvm_vcpu *vcpu,
2082 struct kvm_segment *var, int seg)
2083{
a9179499 2084 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2085 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
a9179499 2086 struct kvm_save_segment *save;
6aa8b732
AK		 2087 u32 ar;
2088
a9179499
AK		 2089 if (vmx->rmode.vm86_active
2090 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
2091 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
2092 || seg == VCPU_SREG_GS)
2093 && !emulate_invalid_guest_state) {
2094 switch (seg) {
2095 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
2096 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
2097 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
2098 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
2099 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
2100 default: BUG();
2101 }
2102 var->selector = save->selector;
2103 var->base = save->base;
2104 var->limit = save->limit;
2105 ar = save->ar;
2106 if (seg == VCPU_SREG_TR
2107 || var->selector == vmcs_read16(sf->selector))
2108 goto use_saved_rmode_seg;
2109 }
6aa8b732
AK		 2110 var->base = vmcs_readl(sf->base);
2111 var->limit = vmcs_read32(sf->limit);
2112 var->selector = vmcs_read16(sf->selector);
2113 ar = vmcs_read32(sf->ar_bytes);
a9179499 2114use_saved_rmode_seg:
9fd4a3b7 2115 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 2116 ar = 0;
2117 var->type = ar & 15;
2118 var->s = (ar >> 4) & 1;
2119 var->dpl = (ar >> 5) & 3;
2120 var->present = (ar >> 7) & 1;
2121 var->avl = (ar >> 12) & 1;
2122 var->l = (ar >> 13) & 1;
2123 var->db = (ar >> 14) & 1;
2124 var->g = (ar >> 15) & 1;
2125 var->unusable = (ar >> 16) & 1;
2126}
2127
a9179499
AK		 2128static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2129{
2130 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2131 struct kvm_segment s;
2132
2133 if (to_vmx(vcpu)->rmode.vm86_active) {
2134 vmx_get_segment(vcpu, &s, seg);
2135 return s.base;
2136 }
2137 return vmcs_readl(sf->base);
2138}
2139
69c73028 2140static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 2141{
3eeb3288 2142 if (!is_protmode(vcpu))
2e4d2653
IE		 2143 return 0;
2144
f4c63e5d
AK		 2145 if (!is_long_mode(vcpu)
2146 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 2147 return 3;
2148
eab4b8aa 2149 return vmcs_read16(GUEST_CS_SELECTOR) & 3;
2e4d2653
IE		 2150}
2151
69c73028
AK		 2152static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2153{
2154 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
2155 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2156 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
2157 }
2158 return to_vmx(vcpu)->cpl;
2159}
2160
2161
653e3108 2162static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 2163{
6aa8b732
AK		 2164 u32 ar;
2165
653e3108 2166 if (var->unusable)
6aa8b732
AK		 2167 ar = 1 << 16;
2168 else {
2169 ar = var->type & 15;
2170 ar |= (var->s & 1) << 4;
2171 ar |= (var->dpl & 3) << 5;
2172 ar |= (var->present & 1) << 7;
2173 ar |= (var->avl & 1) << 12;
2174 ar |= (var->l & 1) << 13;
2175 ar |= (var->db & 1) << 14;
2176 ar |= (var->g & 1) << 15;
2177 }
f7fbf1fd
UL		 2178 if (ar == 0) /* a 0 value means unusable */
2179 ar = AR_UNUSABLE_MASK;
653e3108
AK		 2180
2181 return ar;
2182}
2183
2184static void vmx_set_segment(struct kvm_vcpu *vcpu,
2185 struct kvm_segment *var, int seg)
2186{
7ffd92c5 2187 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 2188 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2189 u32 ar;
2190
7ffd92c5 2191 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
a8ba6c26 2192 vmcs_write16(sf->selector, var->selector);
7ffd92c5
AK		 2193 vmx->rmode.tr.selector = var->selector;
2194 vmx->rmode.tr.base = var->base;
2195 vmx->rmode.tr.limit = var->limit;
2196 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 2197 return;
2198 }
2199 vmcs_writel(sf->base, var->base);
2200 vmcs_write32(sf->limit, var->limit);
2201 vmcs_write16(sf->selector, var->selector);
7ffd92c5 2202 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 2203 /*
2204 * Hack real-mode segments into vm86 compatibility.
2205 */
2206 if (var->base == 0xffff0000 && var->selector == 0xf000)
2207 vmcs_writel(sf->base, 0xf0000);
2208 ar = 0xf3;
2209 } else
2210 ar = vmx_segment_access_rights(var);
3a624e29
NK		 2211
2212 /*
2213 * Fix the "Accessed" bit in AR field of segment registers for older
2214 * qemu binaries.
2215 * IA32 arch specifies that at the time of processor reset the
2216 * "Accessed" bit in the AR field of segment registers is 1. And qemu
2217 * is setting it to 0 in the usedland code. This causes invalid guest
2218 * state vmexit when "unrestricted guest" mode is turned on.
2219 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2220 * tree. Newer qemu binaries with that qemu fix would not need this
2221 * kvm hack.
2222 */
2223 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2224 ar |= 0x1; /* Accessed */
2225
6aa8b732 2226 vmcs_write32(sf->ar_bytes, ar);
69c73028 2227 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 2228}
2229
6aa8b732
AK		 2230static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2231{
2232 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2233
2234 *db = (ar >> 14) & 1;
2235 *l = (ar >> 13) & 1;
2236}
2237
89a27f4d 2238static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2239{
89a27f4d
GN		 2240 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2241 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 2242}
2243
89a27f4d 2244static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2245{
89a27f4d
GN		 2246 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2247 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 2248}
2249
89a27f4d 2250static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2251{
89a27f4d
GN		 2252 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2253 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 2254}
2255
89a27f4d 2256static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2257{
89a27f4d
GN		 2258 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2259 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 2260}
2261
648dfaa7
MG		 2262static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2263{
2264 struct kvm_segment var;
2265 u32 ar;
2266
2267 vmx_get_segment(vcpu, &var, seg);
2268 ar = vmx_segment_access_rights(&var);
2269
2270 if (var.base != (var.selector << 4))
2271 return false;
2272 if (var.limit != 0xffff)
2273 return false;
2274 if (ar != 0xf3)
2275 return false;
2276
2277 return true;
2278}
2279
2280static bool code_segment_valid(struct kvm_vcpu *vcpu)
2281{
2282 struct kvm_segment cs;
2283 unsigned int cs_rpl;
2284
2285 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2286 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2287
1872a3f4
AK		 2288 if (cs.unusable)
2289 return false;
648dfaa7
MG		 2290 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2291 return false;
2292 if (!cs.s)
2293 return false;
1872a3f4 2294 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 2295 if (cs.dpl > cs_rpl)
2296 return false;
1872a3f4 2297 } else {
648dfaa7
MG		 2298 if (cs.dpl != cs_rpl)
2299 return false;
2300 }
2301 if (!cs.present)
2302 return false;
2303
2304 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2305 return true;
2306}
2307
2308static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2309{
2310 struct kvm_segment ss;
2311 unsigned int ss_rpl;
2312
2313 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2314 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2315
1872a3f4
AK		 2316 if (ss.unusable)
2317 return true;
2318 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 2319 return false;
2320 if (!ss.s)
2321 return false;
2322 if (ss.dpl != ss_rpl) /* DPL != RPL */
2323 return false;
2324 if (!ss.present)
2325 return false;
2326
2327 return true;
2328}
2329
2330static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2331{
2332 struct kvm_segment var;
2333 unsigned int rpl;
2334
2335 vmx_get_segment(vcpu, &var, seg);
2336 rpl = var.selector & SELECTOR_RPL_MASK;
2337
1872a3f4
AK		 2338 if (var.unusable)
2339 return true;
648dfaa7
MG		 2340 if (!var.s)
2341 return false;
2342 if (!var.present)
2343 return false;
2344 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2345 if (var.dpl < rpl) /* DPL < RPL */
2346 return false;
2347 }
2348
2349 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2350 * rights flags
2351 */
2352 return true;
2353}
2354
2355static bool tr_valid(struct kvm_vcpu *vcpu)
2356{
2357 struct kvm_segment tr;
2358
2359 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2360
1872a3f4
AK		 2361 if (tr.unusable)
2362 return false;
648dfaa7
MG		 2363 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2364 return false;
1872a3f4 2365 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 2366 return false;
2367 if (!tr.present)
2368 return false;
2369
2370 return true;
2371}
2372
2373static bool ldtr_valid(struct kvm_vcpu *vcpu)
2374{
2375 struct kvm_segment ldtr;
2376
2377 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2378
1872a3f4
AK		 2379 if (ldtr.unusable)
2380 return true;
648dfaa7
MG		 2381 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2382 return false;
2383 if (ldtr.type != 2)
2384 return false;
2385 if (!ldtr.present)
2386 return false;
2387
2388 return true;
2389}
2390
2391static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2392{
2393 struct kvm_segment cs, ss;
2394
2395 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2396 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2397
2398 return ((cs.selector & SELECTOR_RPL_MASK) ==
2399 (ss.selector & SELECTOR_RPL_MASK));
2400}
2401
2402/*
2403 * Check if guest state is valid. Returns true if valid, false if
2404 * not.
2405 * We assume that registers are always usable
2406 */
2407static bool guest_state_valid(struct kvm_vcpu *vcpu)
2408{
2409 /* real mode guest state checks */
3eeb3288 2410 if (!is_protmode(vcpu)) {
648dfaa7
MG		 2411 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2412 return false;
2413 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2414 return false;
2415 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2416 return false;
2417 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2418 return false;
2419 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2420 return false;
2421 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2422 return false;
2423 } else {
2424 /* protected mode guest state checks */
2425 if (!cs_ss_rpl_check(vcpu))
2426 return false;
2427 if (!code_segment_valid(vcpu))
2428 return false;
2429 if (!stack_segment_valid(vcpu))
2430 return false;
2431 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2432 return false;
2433 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2434 return false;
2435 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2436 return false;
2437 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2438 return false;
2439 if (!tr_valid(vcpu))
2440 return false;
2441 if (!ldtr_valid(vcpu))
2442 return false;
2443 }
2444 /* TODO:
2445 * - Add checks on RIP
2446 * - Add checks on RFLAGS
2447 */
2448
2449 return true;
2450}
2451
d77c26fc 2452static int init_rmode_tss(struct kvm *kvm)
6aa8b732 2453{
40dcaa9f 2454 gfn_t fn;
195aefde 2455 u16 data = 0;
40dcaa9f 2456 int r, idx, ret = 0;
6aa8b732 2457
40dcaa9f
XG		 2458 idx = srcu_read_lock(&kvm->srcu);
2459 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE		 2460 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2461 if (r < 0)
10589a46 2462 goto out;
195aefde 2463 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 2464 r = kvm_write_guest_page(kvm, fn++, &data,
2465 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 2466 if (r < 0)
10589a46 2467 goto out;
195aefde
IE		 2468 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2469 if (r < 0)
10589a46 2470 goto out;
195aefde
IE		 2471 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2472 if (r < 0)
10589a46 2473 goto out;
195aefde 2474 data = ~0;
10589a46
MT		 2475 r = kvm_write_guest_page(kvm, fn, &data,
2476 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2477 sizeof(u8));
195aefde 2478 if (r < 0)
10589a46
MT		 2479 goto out;
2480
2481 ret = 1;
2482out:
40dcaa9f 2483 srcu_read_unlock(&kvm->srcu, idx);
10589a46 2484 return ret;
6aa8b732
AK		 2485}
2486
b7ebfb05
SY		 2487static int init_rmode_identity_map(struct kvm *kvm)
2488{
40dcaa9f 2489 int i, idx, r, ret;
b7ebfb05
SY		 2490 pfn_t identity_map_pfn;
2491 u32 tmp;
2492
089d034e 2493 if (!enable_ept)
b7ebfb05
SY		 2494 return 1;
2495 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2496 printk(KERN_ERR "EPT: identity-mapping pagetable "
2497 "haven't been allocated!\n");
2498 return 0;
2499 }
2500 if (likely(kvm->arch.ept_identity_pagetable_done))
2501 return 1;
2502 ret = 0;
b927a3ce 2503 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 2504 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 2505 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2506 if (r < 0)
2507 goto out;
2508 /* Set up identity-mapping pagetable for EPT in real mode */
2509 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2510 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2511 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2512 r = kvm_write_guest_page(kvm, identity_map_pfn,
2513 &tmp, i * sizeof(tmp), sizeof(tmp));
2514 if (r < 0)
2515 goto out;
2516 }
2517 kvm->arch.ept_identity_pagetable_done = true;
2518 ret = 1;
2519out:
40dcaa9f 2520 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 2521 return ret;
2522}
2523
6aa8b732
AK		 2524static void seg_setup(int seg)
2525{
2526 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 2527 unsigned int ar;
6aa8b732
AK		 2528
2529 vmcs_write16(sf->selector, 0);
2530 vmcs_writel(sf->base, 0);
2531 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 2532 if (enable_unrestricted_guest) {
2533 ar = 0x93;
2534 if (seg == VCPU_SREG_CS)
2535 ar |= 0x08; /* code segment */
2536 } else
2537 ar = 0xf3;
2538
2539 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 2540}
2541
f78e0e2e
SY		 2542static int alloc_apic_access_page(struct kvm *kvm)
2543{
2544 struct kvm_userspace_memory_region kvm_userspace_mem;
2545 int r = 0;
2546
79fac95e 2547 mutex_lock(&kvm->slots_lock);
bfc6d222 2548 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 2549 goto out;
2550 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2551 kvm_userspace_mem.flags = 0;
2552 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2553 kvm_userspace_mem.memory_size = PAGE_SIZE;
2554 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2555 if (r)
2556 goto out;
72dc67a6 2557
bfc6d222 2558 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 2559out:
79fac95e 2560 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 2561 return r;
2562}
2563
b7ebfb05
SY		 2564static int alloc_identity_pagetable(struct kvm *kvm)
2565{
2566 struct kvm_userspace_memory_region kvm_userspace_mem;
2567 int r = 0;
2568
79fac95e 2569 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 2570 if (kvm->arch.ept_identity_pagetable)
2571 goto out;
2572 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2573 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 2574 kvm_userspace_mem.guest_phys_addr =
2575 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 2576 kvm_userspace_mem.memory_size = PAGE_SIZE;
2577 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2578 if (r)
2579 goto out;
2580
b7ebfb05 2581 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 2582 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 2583out:
79fac95e 2584 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 2585 return r;
2586}
2587
2384d2b3
SY		 2588static void allocate_vpid(struct vcpu_vmx *vmx)
2589{
2590 int vpid;
2591
2592 vmx->vpid = 0;
919818ab 2593 if (!enable_vpid)
2384d2b3
SY		 2594 return;
2595 spin_lock(&vmx_vpid_lock);
2596 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2597 if (vpid < VMX_NR_VPIDS) {
2598 vmx->vpid = vpid;
2599 __set_bit(vpid, vmx_vpid_bitmap);
2600 }
2601 spin_unlock(&vmx_vpid_lock);
2602}
2603
cdbecfc3
LJ		 2604static void free_vpid(struct vcpu_vmx *vmx)
2605{
2606 if (!enable_vpid)
2607 return;
2608 spin_lock(&vmx_vpid_lock);
2609 if (vmx->vpid != 0)
2610 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2611 spin_unlock(&vmx_vpid_lock);
2612}
2613
5897297b 2614static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 2615{
3e7c73e9 2616 int f = sizeof(unsigned long);
25c5f225
SY		 2617
2618 if (!cpu_has_vmx_msr_bitmap())
2619 return;
2620
2621 /*
2622 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2623 * have the write-low and read-high bitmap offsets the wrong way round.
2624 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2625 */
25c5f225 2626 if (msr <= 0x1fff) {
3e7c73e9
AK		 2627 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2628 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 2629 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2630 msr &= 0x1fff;
3e7c73e9
AK		 2631 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2632 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 2633 }
25c5f225
SY		 2634}
2635
5897297b
AK		 2636static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2637{
2638 if (!longmode_only)
2639 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2640 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2641}
2642
6aa8b732
AK		 2643/*
2644 * Sets up the vmcs for emulated real mode.
2645 */
8b9cf98c 2646static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 2647{
468d472f 2648 u32 host_sysenter_cs, msr_low, msr_high;
6aa8b732 2649 u32 junk;
f4e1b3c8 2650 u64 host_pat;
6aa8b732 2651 unsigned long a;
89a27f4d 2652 struct desc_ptr dt;
6aa8b732 2653 int i;
cd2276a7 2654 unsigned long kvm_vmx_return;
6e5d865c 2655 u32 exec_control;
6aa8b732 2656
6aa8b732 2657 /* I/O */
3e7c73e9
AK		 2658 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2659 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 2660
25c5f225 2661 if (cpu_has_vmx_msr_bitmap())
5897297b 2662 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 2663
6aa8b732
AK		 2664 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2665
6aa8b732 2666 /* Control */
1c3d14fe
YS		 2667 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2668 vmcs_config.pin_based_exec_ctrl);
6e5d865c
YS		 2669
2670 exec_control = vmcs_config.cpu_based_exec_ctrl;
2671 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2672 exec_control &= ~CPU_BASED_TPR_SHADOW;
2673#ifdef CONFIG_X86_64
2674 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2675 CPU_BASED_CR8_LOAD_EXITING;
2676#endif
2677 }
089d034e 2678 if (!enable_ept)
d56f546d 2679 exec_control |= CPU_BASED_CR3_STORE_EXITING |
83dbc83a
MT		 2680 CPU_BASED_CR3_LOAD_EXITING |
2681 CPU_BASED_INVLPG_EXITING;
6e5d865c 2682 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6aa8b732 2683
83ff3b9d
SY		 2684 if (cpu_has_secondary_exec_ctrls()) {
2685 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2686 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2687 exec_control &=
2688 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2384d2b3
SY		 2689 if (vmx->vpid == 0)
2690 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
046d8710 2691 if (!enable_ept) {
d56f546d 2692 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
046d8710
SY		 2693 enable_unrestricted_guest = 0;
2694 }
3a624e29
NK		 2695 if (!enable_unrestricted_guest)
2696 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
4b8d54f9
ZE		 2697 if (!ple_gap)
2698 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
83ff3b9d
SY		 2699 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2700 }
f78e0e2e 2701
4b8d54f9
ZE		 2702 if (ple_gap) {
2703 vmcs_write32(PLE_GAP, ple_gap);
2704 vmcs_write32(PLE_WINDOW, ple_window);
2705 }
2706
c7addb90
AK		 2707 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2708 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 2709 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2710
1c11e713 2711 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
6aa8b732
AK		 2712 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2713 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2714
2715 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2716 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2717 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
9581d442
AK		 2718 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
2719 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
6aa8b732 2720 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
05b3e0c2 2721#ifdef CONFIG_X86_64
6aa8b732
AK		 2722 rdmsrl(MSR_FS_BASE, a);
2723 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2724 rdmsrl(MSR_GS_BASE, a);
2725 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2726#else
2727 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2728 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2729#endif
2730
2731 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2732
ec68798c 2733 native_store_idt(&dt);
89a27f4d 2734 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
6aa8b732 2735
d77c26fc 2736 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
cd2276a7 2737 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2cc51560
ED		 2738 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2739 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 2740 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 2741 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 2742 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732
AK		 2743
2744 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2745 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2746 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2747 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2748 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2749 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2750
468d472f
SY		 2751 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2752 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2753 host_pat = msr_low | ((u64) msr_high << 32);
2754 vmcs_write64(HOST_IA32_PAT, host_pat);
2755 }
2756 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2757 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2758 host_pat = msr_low | ((u64) msr_high << 32);
2759 /* Write the default value follow host pat */
2760 vmcs_write64(GUEST_IA32_PAT, host_pat);
2761 /* Keep arch.pat sync with GUEST_IA32_PAT */
2762 vmx->vcpu.arch.pat = host_pat;
2763 }
2764
6aa8b732
AK		 2765 for (i = 0; i < NR_VMX_MSR; ++i) {
2766 u32 index = vmx_msr_index[i];
2767 u32 data_low, data_high;
a2fa3e9f 2768 int j = vmx->nmsrs;
6aa8b732
AK		 2769
2770 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2771 continue;
432bd6cb
AK		 2772 if (wrmsr_safe(index, data_low, data_high) < 0)
2773 continue;
26bb0981
AK		 2774 vmx->guest_msrs[j].index = i;
2775 vmx->guest_msrs[j].data = 0;
d5696725 2776 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 2777 ++vmx->nmsrs;
6aa8b732 2778 }
6aa8b732 2779
1c3d14fe 2780 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 2781
2782 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 2783 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2784
e00c8cf2 2785 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
4c38609a 2786 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
ce03e4f2
AK		 2787 if (enable_ept)
2788 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
4c38609a 2789 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
e00c8cf2 2790
99e3e30a 2791 kvm_write_tsc(&vmx->vcpu, 0);
f78e0e2e 2792
e00c8cf2
AK		 2793 return 0;
2794}
2795
2796static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2797{
2798 struct vcpu_vmx *vmx = to_vmx(vcpu);
2799 u64 msr;
4b9d3a04 2800 int ret;
e00c8cf2 2801
5fdbf976 2802 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
e00c8cf2 2803
7ffd92c5 2804 vmx->rmode.vm86_active = 0;
e00c8cf2 2805
3b86cd99
JK		 2806 vmx->soft_vnmi_blocked = 0;
2807
ad312c7c 2808 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 2809 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 2810 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 2811 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 2812 msr |= MSR_IA32_APICBASE_BSP;
2813 kvm_set_apic_base(&vmx->vcpu, msr);
2814
10ab25cd
JK		 2815 ret = fx_init(&vmx->vcpu);
2816 if (ret != 0)
2817 goto out;
e00c8cf2 2818
5706be0d 2819 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 2820 /*
2821 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2822 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2823 */
c5af89b6 2824 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 2825 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2826 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2827 } else {
ad312c7c
ZX		 2828 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2829 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 2830 }
e00c8cf2
AK		 2831
2832 seg_setup(VCPU_SREG_DS);
2833 seg_setup(VCPU_SREG_ES);
2834 seg_setup(VCPU_SREG_FS);
2835 seg_setup(VCPU_SREG_GS);
2836 seg_setup(VCPU_SREG_SS);
2837
2838 vmcs_write16(GUEST_TR_SELECTOR, 0);
2839 vmcs_writel(GUEST_TR_BASE, 0);
2840 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2841 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2842
2843 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2844 vmcs_writel(GUEST_LDTR_BASE, 0);
2845 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2846 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2847
2848 vmcs_write32(GUEST_SYSENTER_CS, 0);
2849 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2850 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2851
2852 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 2853 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 2854 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 2855 else
5fdbf976
MT		 2856 kvm_rip_write(vcpu, 0);
2857 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 2858
e00c8cf2
AK		 2859 vmcs_writel(GUEST_DR7, 0x400);
2860
2861 vmcs_writel(GUEST_GDTR_BASE, 0);
2862 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2863
2864 vmcs_writel(GUEST_IDTR_BASE, 0);
2865 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2866
443381a8 2867 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 2868 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2869 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2870
e00c8cf2
AK		 2871 /* Special registers */
2872 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2873
2874 setup_msrs(vmx);
2875
6aa8b732
AK		 2876 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2877
f78e0e2e
SY		 2878 if (cpu_has_vmx_tpr_shadow()) {
2879 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2880 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2881 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 2882 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 2883 vmcs_write32(TPR_THRESHOLD, 0);
2884 }
2885
2886 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2887 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 2888 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 2889
2384d2b3
SY		 2890 if (vmx->vpid != 0)
2891 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2892
fa40052c 2893 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 2894 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 2895 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 2896 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 2897 vmx_fpu_activate(&vmx->vcpu);
2898 update_exception_bitmap(&vmx->vcpu);
6aa8b732 2899
b9d762fa 2900 vpid_sync_context(vmx);
2384d2b3 2901
3200f405 2902 ret = 0;
6aa8b732 2903
a89a8fb9
MG		 2904 /* HACK: Don't enable emulation on guest boot/reset */
2905 vmx->emulation_required = 0;
2906
6aa8b732
AK		 2907out:
2908 return ret;
2909}
2910
3b86cd99
JK		 2911static void enable_irq_window(struct kvm_vcpu *vcpu)
2912{
2913 u32 cpu_based_vm_exec_control;
2914
2915 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2916 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2917 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2918}
2919
2920static void enable_nmi_window(struct kvm_vcpu *vcpu)
2921{
2922 u32 cpu_based_vm_exec_control;
2923
2924 if (!cpu_has_virtual_nmis()) {
2925 enable_irq_window(vcpu);
2926 return;
2927 }
2928
30bd0c4c
AK		 2929 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
2930 enable_irq_window(vcpu);
2931 return;
2932 }
3b86cd99
JK		 2933 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2934 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2935 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2936}
2937
66fd3f7f 2938static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 2939{
9c8cba37 2940 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 2941 uint32_t intr;
2942 int irq = vcpu->arch.interrupt.nr;
9c8cba37 2943
229456fc 2944 trace_kvm_inj_virq(irq);
2714d1d3 2945
fa89a817 2946 ++vcpu->stat.irq_injections;
7ffd92c5 2947 if (vmx->rmode.vm86_active) {
71f9833b
SH		 2948 int inc_eip = 0;
2949 if (vcpu->arch.interrupt.soft)
2950 inc_eip = vcpu->arch.event_exit_inst_len;
2951 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 2952 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 2953 return;
2954 }
66fd3f7f
GN		 2955 intr = irq | INTR_INFO_VALID_MASK;
2956 if (vcpu->arch.interrupt.soft) {
2957 intr |= INTR_TYPE_SOFT_INTR;
2958 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2959 vmx->vcpu.arch.event_exit_inst_len);
2960 } else
2961 intr |= INTR_TYPE_EXT_INTR;
2962 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
443381a8 2963 vmx_clear_hlt(vcpu);
85f455f7
ED		 2964}
2965
f08864b4
SY		 2966static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2967{
66a5a347
JK		 2968 struct vcpu_vmx *vmx = to_vmx(vcpu);
2969
3b86cd99
JK		 2970 if (!cpu_has_virtual_nmis()) {
2971 /*
2972 * Tracking the NMI-blocked state in software is built upon
2973 * finding the next open IRQ window. This, in turn, depends on
2974 * well-behaving guests: They have to keep IRQs disabled at
2975 * least as long as the NMI handler runs. Otherwise we may
2976 * cause NMI nesting, maybe breaking the guest. But as this is
2977 * highly unlikely, we can live with the residual risk.
2978 */
2979 vmx->soft_vnmi_blocked = 1;
2980 vmx->vnmi_blocked_time = 0;
2981 }
2982
487b391d 2983 ++vcpu->stat.nmi_injections;
9d58b931 2984 vmx->nmi_known_unmasked = false;
7ffd92c5 2985 if (vmx->rmode.vm86_active) {
71f9833b 2986 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 2987 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 2988 return;
2989 }
f08864b4
SY		 2990 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2991 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
443381a8 2992 vmx_clear_hlt(vcpu);
f08864b4
SY		 2993}
2994
c4282df9 2995static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 2996{
3b86cd99 2997 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 2998 return 0;
33f089ca 2999
c4282df9 3000 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 3001 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
3002 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 3003}
3004
3cfc3092
JK		 3005static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
3006{
3007 if (!cpu_has_virtual_nmis())
3008 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 3009 if (to_vmx(vcpu)->nmi_known_unmasked)
3010 return false;
c332c83a 3011 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 3012}
3013
3014static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3015{
3016 struct vcpu_vmx *vmx = to_vmx(vcpu);
3017
3018 if (!cpu_has_virtual_nmis()) {
3019 if (vmx->soft_vnmi_blocked != masked) {
3020 vmx->soft_vnmi_blocked = masked;
3021 vmx->vnmi_blocked_time = 0;
3022 }
3023 } else {
9d58b931 3024 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 3025 if (masked)
3026 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3027 GUEST_INTR_STATE_NMI);
3028 else
3029 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3030 GUEST_INTR_STATE_NMI);
3031 }
3032}
3033
78646121
GN		 3034static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
3035{
c4282df9
GN		 3036 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
3037 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3038 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 3039}
3040
cbc94022
IE		 3041static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
3042{
3043 int ret;
3044 struct kvm_userspace_memory_region tss_mem = {
6fe63979 3045 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 3046 .guest_phys_addr = addr,
3047 .memory_size = PAGE_SIZE * 3,
3048 .flags = 0,
3049 };
3050
3051 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
3052 if (ret)
3053 return ret;
bfc6d222 3054 kvm->arch.tss_addr = addr;
93ea5388
GN		 3055 if (!init_rmode_tss(kvm))
3056 return -ENOMEM;
3057
cbc94022
IE		 3058 return 0;
3059}
3060
6aa8b732
AK		 3061static int handle_rmode_exception(struct kvm_vcpu *vcpu,
3062 int vec, u32 err_code)
3063{
b3f37707
NK		 3064 /*
3065 * Instruction with address size override prefix opcode 0x67
3066 * Cause the #SS fault with 0 error code in VM86 mode.
3067 */
3068 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
51d8b661 3069 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
6aa8b732 3070 return 1;
77ab6db0
JK		 3071 /*
3072 * Forward all other exceptions that are valid in real mode.
3073 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
3074 * the required debugging infrastructure rework.
3075 */
3076 switch (vec) {
77ab6db0 3077 case DB_VECTOR:
d0bfb940
JK		 3078 if (vcpu->guest_debug &
3079 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
3080 return 0;
3081 kvm_queue_exception(vcpu, vec);
3082 return 1;
77ab6db0 3083 case BP_VECTOR:
c573cd22
JK		 3084 /*
3085 * Update instruction length as we may reinject the exception
3086 * from user space while in guest debugging mode.
3087 */
3088 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
3089 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 3090 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
3091 return 0;
3092 /* fall through */
3093 case DE_VECTOR:
77ab6db0
JK		 3094 case OF_VECTOR:
3095 case BR_VECTOR:
3096 case UD_VECTOR:
3097 case DF_VECTOR:
3098 case SS_VECTOR:
3099 case GP_VECTOR:
3100 case MF_VECTOR:
3101 kvm_queue_exception(vcpu, vec);
3102 return 1;
3103 }
6aa8b732
AK		 3104 return 0;
3105}
3106
a0861c02
AK		 3107/*
3108 * Trigger machine check on the host. We assume all the MSRs are already set up
3109 * by the CPU and that we still run on the same CPU as the MCE occurred on.
3110 * We pass a fake environment to the machine check handler because we want
3111 * the guest to be always treated like user space, no matter what context
3112 * it used internally.
3113 */
3114static void kvm_machine_check(void)
3115{
3116#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
3117 struct pt_regs regs = {
3118 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
3119 .flags = X86_EFLAGS_IF,
3120 };
3121
3122 do_machine_check(&regs, 0);
3123#endif
3124}
3125
851ba692 3126static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 3127{
3128 /* already handled by vcpu_run */
3129 return 1;
3130}
3131
851ba692 3132static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 3133{
1155f76a 3134 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 3135 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 3136 u32 intr_info, ex_no, error_code;
42dbaa5a 3137 unsigned long cr2, rip, dr6;
6aa8b732
AK		 3138 u32 vect_info;
3139 enum emulation_result er;
3140
1155f76a 3141 vect_info = vmx->idt_vectoring_info;
88786475 3142 intr_info = vmx->exit_intr_info;
6aa8b732 3143
a0861c02 3144 if (is_machine_check(intr_info))
851ba692 3145 return handle_machine_check(vcpu);
a0861c02 3146
6aa8b732 3147 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 3148 !is_page_fault(intr_info)) {
3149 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3150 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
3151 vcpu->run->internal.ndata = 2;
3152 vcpu->run->internal.data[0] = vect_info;
3153 vcpu->run->internal.data[1] = intr_info;
3154 return 0;
3155 }
6aa8b732 3156
e4a41889 3157 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 3158 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 3159
3160 if (is_no_device(intr_info)) {
5fd86fcf 3161 vmx_fpu_activate(vcpu);
2ab455cc
AL		 3162 return 1;
3163 }
3164
7aa81cc0 3165 if (is_invalid_opcode(intr_info)) {
51d8b661 3166 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 3167 if (er != EMULATE_DONE)
7ee5d940 3168 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 3169 return 1;
3170 }
3171
6aa8b732 3172 error_code = 0;
5fdbf976 3173 rip = kvm_rip_read(vcpu);
2e11384c 3174 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 3175 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
3176 if (is_page_fault(intr_info)) {
1439442c 3177 /* EPT won't cause page fault directly */
089d034e 3178 if (enable_ept)
1439442c 3179 BUG();
6aa8b732 3180 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 3181 trace_kvm_page_fault(cr2, error_code);
3182
3298b75c 3183 if (kvm_event_needs_reinjection(vcpu))
577bdc49 3184 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 3185 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 3186 }
3187
7ffd92c5 3188 if (vmx->rmode.vm86_active &&
6aa8b732 3189 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 3190 error_code)) {
ad312c7c
ZX		 3191 if (vcpu->arch.halt_request) {
3192 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 3193 return kvm_emulate_halt(vcpu);
3194 }
6aa8b732 3195 return 1;
72d6e5a0 3196 }
6aa8b732 3197
d0bfb940 3198 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 3199 switch (ex_no) {
3200 case DB_VECTOR:
3201 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3202 if (!(vcpu->guest_debug &
3203 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3204 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3205 kvm_queue_exception(vcpu, DB_VECTOR);
3206 return 1;
3207 }
3208 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3209 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3210 /* fall through */
3211 case BP_VECTOR:
c573cd22
JK		 3212 /*
3213 * Update instruction length as we may reinject #BP from
3214 * user space while in guest debugging mode. Reading it for
3215 * #DB as well causes no harm, it is not used in that case.
3216 */
3217 vmx->vcpu.arch.event_exit_inst_len =
3218 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 3219 kvm_run->exit_reason = KVM_EXIT_DEBUG;
d0bfb940
JK		 3220 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3221 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 3222 break;
3223 default:
d0bfb940
JK		 3224 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3225 kvm_run->ex.exception = ex_no;
3226 kvm_run->ex.error_code = error_code;
42dbaa5a 3227 break;
6aa8b732 3228 }
6aa8b732
AK		 3229 return 0;
3230}
3231
851ba692 3232static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 3233{
1165f5fe 3234 ++vcpu->stat.irq_exits;
6aa8b732
AK		 3235 return 1;
3236}
3237
851ba692 3238static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 3239{
851ba692 3240 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 3241 return 0;
3242}
6aa8b732 3243
851ba692 3244static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 3245{
bfdaab09 3246 unsigned long exit_qualification;
34c33d16 3247 int size, in, string;
039576c0 3248 unsigned port;
6aa8b732 3249
bfdaab09 3250 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 3251 string = (exit_qualification & 16) != 0;
cf8f70bf 3252 in = (exit_qualification & 8) != 0;
e70669ab 3253
cf8f70bf 3254 ++vcpu->stat.io_exits;
e70669ab 3255
cf8f70bf 3256 if (string || in)
51d8b661 3257 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 3258
cf8f70bf
GN		 3259 port = exit_qualification >> 16;
3260 size = (exit_qualification & 7) + 1;
e93f36bc 3261 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 3262
3263 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 3264}
3265
102d8325
IM		 3266static void
3267vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3268{
3269 /*
3270 * Patch in the VMCALL instruction:
3271 */
3272 hypercall[0] = 0x0f;
3273 hypercall[1] = 0x01;
3274 hypercall[2] = 0xc1;
102d8325
IM		 3275}
3276
851ba692 3277static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 3278{
229456fc 3279 unsigned long exit_qualification, val;
6aa8b732
AK		 3280 int cr;
3281 int reg;
49a9b07e 3282 int err;
6aa8b732 3283
bfdaab09 3284 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 3285 cr = exit_qualification & 15;
3286 reg = (exit_qualification >> 8) & 15;
3287 switch ((exit_qualification >> 4) & 3) {
3288 case 0: /* mov to cr */
229456fc
MT		 3289 val = kvm_register_read(vcpu, reg);
3290 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 3291 switch (cr) {
3292 case 0:
49a9b07e 3293 err = kvm_set_cr0(vcpu, val);
db8fcefa 3294 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 3295 return 1;
3296 case 3:
2390218b 3297 err = kvm_set_cr3(vcpu, val);
db8fcefa 3298 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 3299 return 1;
3300 case 4:
a83b29c6 3301 err = kvm_set_cr4(vcpu, val);
db8fcefa 3302 kvm_complete_insn_gp(vcpu, err);
6aa8b732 3303 return 1;
0a5fff19
GN		 3304 case 8: {
3305 u8 cr8_prev = kvm_get_cr8(vcpu);
3306 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 3307 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 3308 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 3309 if (irqchip_in_kernel(vcpu->kvm))
3310 return 1;
3311 if (cr8_prev <= cr8)
3312 return 1;
851ba692 3313 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 3314 return 0;
3315 }
6aa8b732
AK		 3316 };
3317 break;
25c4c276 3318 case 2: /* clts */
edcafe3c 3319 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 3320 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 3321 skip_emulated_instruction(vcpu);
6b52d186 3322 vmx_fpu_activate(vcpu);
25c4c276 3323 return 1;
6aa8b732
AK		 3324 case 1: /*mov from cr*/
3325 switch (cr) {
3326 case 3:
9f8fe504
AK		 3327 val = kvm_read_cr3(vcpu);
3328 kvm_register_write(vcpu, reg, val);
3329 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 3330 skip_emulated_instruction(vcpu);
3331 return 1;
3332 case 8:
229456fc
MT		 3333 val = kvm_get_cr8(vcpu);
3334 kvm_register_write(vcpu, reg, val);
3335 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 3336 skip_emulated_instruction(vcpu);
3337 return 1;
3338 }
3339 break;
3340 case 3: /* lmsw */
a1f83a74 3341 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 3342 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 3343 kvm_lmsw(vcpu, val);
6aa8b732
AK		 3344
3345 skip_emulated_instruction(vcpu);
3346 return 1;
3347 default:
3348 break;
3349 }
851ba692 3350 vcpu->run->exit_reason = 0;
f0242478 3351 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 3352 (int)(exit_qualification >> 4) & 3, cr);
3353 return 0;
3354}
3355
851ba692 3356static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 3357{
bfdaab09 3358 unsigned long exit_qualification;
6aa8b732
AK		 3359 int dr, reg;
3360
f2483415 3361 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 3362 if (!kvm_require_cpl(vcpu, 0))
3363 return 1;
42dbaa5a
JK		 3364 dr = vmcs_readl(GUEST_DR7);
3365 if (dr & DR7_GD) {
3366 /*
3367 * As the vm-exit takes precedence over the debug trap, we
3368 * need to emulate the latter, either for the host or the
3369 * guest debugging itself.
3370 */
3371 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 3372 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3373 vcpu->run->debug.arch.dr7 = dr;
3374 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 3375 vmcs_readl(GUEST_CS_BASE) +
3376 vmcs_readl(GUEST_RIP);
851ba692
AK		 3377 vcpu->run->debug.arch.exception = DB_VECTOR;
3378 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 3379 return 0;
3380 } else {
3381 vcpu->arch.dr7 &= ~DR7_GD;
3382 vcpu->arch.dr6 |= DR6_BD;
3383 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3384 kvm_queue_exception(vcpu, DB_VECTOR);
3385 return 1;
3386 }
3387 }
3388
bfdaab09 3389 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 3390 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3391 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3392 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 3393 unsigned long val;
3394 if (!kvm_get_dr(vcpu, dr, &val))
3395 kvm_register_write(vcpu, reg, val);
3396 } else
3397 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 3398 skip_emulated_instruction(vcpu);
3399 return 1;
3400}
3401
020df079
GN		 3402static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3403{
3404 vmcs_writel(GUEST_DR7, val);
3405}
3406
851ba692 3407static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 3408{
06465c5a
AK		 3409 kvm_emulate_cpuid(vcpu);
3410 return 1;
6aa8b732
AK		 3411}
3412
851ba692 3413static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 3414{
ad312c7c 3415 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 3416 u64 data;
3417
3418 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 3419 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 3420 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3421 return 1;
3422 }
3423
229456fc 3424 trace_kvm_msr_read(ecx, data);
2714d1d3 3425
6aa8b732 3426 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 3427 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3428 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 3429 skip_emulated_instruction(vcpu);
3430 return 1;
3431}
3432
851ba692 3433static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 3434{
ad312c7c
ZX		 3435 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3436 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3437 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 3438
3439 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 3440 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 3441 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 3442 return 1;
3443 }
3444
59200273 3445 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 3446 skip_emulated_instruction(vcpu);
3447 return 1;
3448}
3449
851ba692 3450static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 3451{
3842d135 3452 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 3453 return 1;
3454}
3455
851ba692 3456static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 3457{
85f455f7
ED		 3458 u32 cpu_based_vm_exec_control;
3459
3460 /* clear pending irq */
3461 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3462 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3463 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 3464
3842d135
AK		 3465 kvm_make_request(KVM_REQ_EVENT, vcpu);
3466
a26bf12a 3467 ++vcpu->stat.irq_window_exits;
2714d1d3 3468
c1150d8c
DL		 3469 /*
3470 * If the user space waits to inject interrupts, exit as soon as
3471 * possible
3472 */
8061823a 3473 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 3474 vcpu->run->request_interrupt_window &&
8061823a 3475 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 3476 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 3477 return 0;
3478 }
6aa8b732
AK		 3479 return 1;
3480}
3481
851ba692 3482static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 3483{
3484 skip_emulated_instruction(vcpu);
d3bef15f 3485 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 3486}
3487
851ba692 3488static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 3489{
510043da 3490 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 3491 kvm_emulate_hypercall(vcpu);
3492 return 1;
c21415e8
IM		 3493}
3494
851ba692 3495static int handle_vmx_insn(struct kvm_vcpu *vcpu)
e3c7cb6a
AK		 3496{
3497 kvm_queue_exception(vcpu, UD_VECTOR);
3498 return 1;
3499}
3500
ec25d5e6
GN		 3501static int handle_invd(struct kvm_vcpu *vcpu)
3502{
51d8b661 3503 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 3504}
3505
851ba692 3506static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 3507{
f9c617f6 3508 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 3509
3510 kvm_mmu_invlpg(vcpu, exit_qualification);
3511 skip_emulated_instruction(vcpu);
3512 return 1;
3513}
3514
851ba692 3515static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 3516{
3517 skip_emulated_instruction(vcpu);
f5f48ee1 3518 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 3519 return 1;
3520}
3521
2acf923e
DC		 3522static int handle_xsetbv(struct kvm_vcpu *vcpu)
3523{
3524 u64 new_bv = kvm_read_edx_eax(vcpu);
3525 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3526
3527 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
3528 skip_emulated_instruction(vcpu);
3529 return 1;
3530}
3531
851ba692 3532static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 3533{
51d8b661 3534 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 3535}
3536
851ba692 3537static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 3538{
60637aac 3539 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 3540 unsigned long exit_qualification;
e269fb21
JK		 3541 bool has_error_code = false;
3542 u32 error_code = 0;
37817f29 3543 u16 tss_selector;
64a7ec06
GN		 3544 int reason, type, idt_v;
3545
3546 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3547 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 3548
3549 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3550
3551 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 3552 if (reason == TASK_SWITCH_GATE && idt_v) {
3553 switch (type) {
3554 case INTR_TYPE_NMI_INTR:
3555 vcpu->arch.nmi_injected = false;
654f06fc 3556 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 3557 break;
3558 case INTR_TYPE_EXT_INTR:
66fd3f7f 3559 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 3560 kvm_clear_interrupt_queue(vcpu);
3561 break;
3562 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 3563 if (vmx->idt_vectoring_info &
3564 VECTORING_INFO_DELIVER_CODE_MASK) {
3565 has_error_code = true;
3566 error_code =
3567 vmcs_read32(IDT_VECTORING_ERROR_CODE);
3568 }
3569 /* fall through */
64a7ec06
GN		 3570 case INTR_TYPE_SOFT_EXCEPTION:
3571 kvm_clear_exception_queue(vcpu);
3572 break;
3573 default:
3574 break;
3575 }
60637aac 3576 }
37817f29
IE		 3577 tss_selector = exit_qualification;
3578
64a7ec06
GN		 3579 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3580 type != INTR_TYPE_EXT_INTR &&
3581 type != INTR_TYPE_NMI_INTR))
3582 skip_emulated_instruction(vcpu);
3583
acb54517
GN		 3584 if (kvm_task_switch(vcpu, tss_selector, reason,
3585 has_error_code, error_code) == EMULATE_FAIL) {
3586 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3587 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3588 vcpu->run->internal.ndata = 0;
42dbaa5a 3589 return 0;
acb54517 3590 }
42dbaa5a
JK		 3591
3592 /* clear all local breakpoint enable flags */
3593 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3594
3595 /*
3596 * TODO: What about debug traps on tss switch?
3597 * Are we supposed to inject them and update dr6?
3598 */
3599
3600 return 1;
37817f29
IE		 3601}
3602
851ba692 3603static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 3604{
f9c617f6 3605 unsigned long exit_qualification;
1439442c 3606 gpa_t gpa;
1439442c 3607 int gla_validity;
1439442c 3608
f9c617f6 3609 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 3610
3611 if (exit_qualification & (1 << 6)) {
3612 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 3613 return -EINVAL;
1439442c
SY		 3614 }
3615
3616 gla_validity = (exit_qualification >> 7) & 0x3;
3617 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3618 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3619 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3620 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 3621 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 3622 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3623 (long unsigned int)exit_qualification);
851ba692
AK		 3624 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3625 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 3626 return 0;
1439442c
SY		 3627 }
3628
3629 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 3630 trace_kvm_page_fault(gpa, exit_qualification);
dc25e89e 3631 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
1439442c
SY		 3632}
3633
68f89400
MT		 3634static u64 ept_rsvd_mask(u64 spte, int level)
3635{
3636 int i;
3637 u64 mask = 0;
3638
3639 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3640 mask |= (1ULL << i);
3641
3642 if (level > 2)
3643 /* bits 7:3 reserved */
3644 mask |= 0xf8;
3645 else if (level == 2) {
3646 if (spte & (1ULL << 7))
3647 /* 2MB ref, bits 20:12 reserved */
3648 mask |= 0x1ff000;
3649 else
3650 /* bits 6:3 reserved */
3651 mask |= 0x78;
3652 }
3653
3654 return mask;
3655}
3656
3657static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3658 int level)
3659{
3660 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3661
3662 /* 010b (write-only) */
3663 WARN_ON((spte & 0x7) == 0x2);
3664
3665 /* 110b (write/execute) */
3666 WARN_ON((spte & 0x7) == 0x6);
3667
3668 /* 100b (execute-only) and value not supported by logical processor */
3669 if (!cpu_has_vmx_ept_execute_only())
3670 WARN_ON((spte & 0x7) == 0x4);
3671
3672 /* not 000b */
3673 if ((spte & 0x7)) {
3674 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3675
3676 if (rsvd_bits != 0) {
3677 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3678 __func__, rsvd_bits);
3679 WARN_ON(1);
3680 }
3681
3682 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3683 u64 ept_mem_type = (spte & 0x38) >> 3;
3684
3685 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3686 ept_mem_type == 7) {
3687 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3688 __func__, ept_mem_type);
3689 WARN_ON(1);
3690 }
3691 }
3692 }
3693}
3694
851ba692 3695static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 3696{
3697 u64 sptes[4];
3698 int nr_sptes, i;
3699 gpa_t gpa;
3700
3701 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3702
3703 printk(KERN_ERR "EPT: Misconfiguration.\n");
3704 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3705
3706 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3707
3708 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3709 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3710
851ba692
AK		 3711 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3712 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 3713
3714 return 0;
3715}
3716
851ba692 3717static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 3718{
3719 u32 cpu_based_vm_exec_control;
3720
3721 /* clear pending NMI */
3722 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3723 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3724 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3725 ++vcpu->stat.nmi_window_exits;
3842d135 3726 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 3727
3728 return 1;
3729}
3730
80ced186 3731static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 3732{
8b3079a5
AK		 3733 struct vcpu_vmx *vmx = to_vmx(vcpu);
3734 enum emulation_result err = EMULATE_DONE;
80ced186 3735 int ret = 1;
49e9d557
AK		 3736 u32 cpu_exec_ctrl;
3737 bool intr_window_requested;
3738
3739 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3740 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0
MG		 3741
3742 while (!guest_state_valid(vcpu)) {
49e9d557
AK		 3743 if (intr_window_requested
3744 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
3745 return handle_interrupt_window(&vmx->vcpu);
3746
51d8b661 3747 err = emulate_instruction(vcpu, 0);
ea953ef0 3748
80ced186
MG		 3749 if (err == EMULATE_DO_MMIO) {
3750 ret = 0;
3751 goto out;
3752 }
1d5a4d9b 3753
6d77dbfc
GN		 3754 if (err != EMULATE_DONE)
3755 return 0;
ea953ef0
MG		 3756
3757 if (signal_pending(current))
80ced186 3758 goto out;
ea953ef0
MG		 3759 if (need_resched())
3760 schedule();
3761 }
3762
80ced186
MG		 3763 vmx->emulation_required = 0;
3764out:
3765 return ret;
ea953ef0
MG		 3766}
3767
4b8d54f9
ZE		 3768/*
3769 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3770 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3771 */
9fb41ba8 3772static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 3773{
3774 skip_emulated_instruction(vcpu);
3775 kvm_vcpu_on_spin(vcpu);
3776
3777 return 1;
3778}
3779
59708670
SY		 3780static int handle_invalid_op(struct kvm_vcpu *vcpu)
3781{
3782 kvm_queue_exception(vcpu, UD_VECTOR);
3783 return 1;
3784}
3785
6aa8b732
AK		 3786/*
3787 * The exit handlers return 1 if the exit was handled fully and guest execution
3788 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3789 * to be done to userspace and return 0.
3790 */
851ba692 3791static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 3792 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3793 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 3794 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 3795 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 3796 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 3797 [EXIT_REASON_CR_ACCESS] = handle_cr,
3798 [EXIT_REASON_DR_ACCESS] = handle_dr,
3799 [EXIT_REASON_CPUID] = handle_cpuid,
3800 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3801 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3802 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3803 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 3804 [EXIT_REASON_INVD] = handle_invd,
a7052897 3805 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 3806 [EXIT_REASON_VMCALL] = handle_vmcall,
e3c7cb6a
AK		 3807 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3808 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3809 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3810 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3811 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3812 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3813 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3814 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3815 [EXIT_REASON_VMON] = handle_vmx_insn,
f78e0e2e
SY		 3816 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3817 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 3818 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 3819 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 3820 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 3821 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 3822 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3823 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 3824 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 3825 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
3826 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 3827};
3828
3829static const int kvm_vmx_max_exit_handlers =
50a3485c 3830 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 3831
586f9607
AK		 3832static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3833{
3834 *info1 = vmcs_readl(EXIT_QUALIFICATION);
3835 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
3836}
3837
6aa8b732
AK		 3838/*
3839 * The guest has exited. See if we can fix it or if we need userspace
3840 * assistance.
3841 */
851ba692 3842static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 3843{
29bd8a78 3844 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 3845 u32 exit_reason = vmx->exit_reason;
1155f76a 3846 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 3847
aa17911e 3848 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
2714d1d3 3849
80ced186
MG		 3850 /* If guest state is invalid, start emulating */
3851 if (vmx->emulation_required && emulate_invalid_guest_state)
3852 return handle_invalid_guest_state(vcpu);
1d5a4d9b 3853
5120702e
MG		 3854 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
3855 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3856 vcpu->run->fail_entry.hardware_entry_failure_reason
3857 = exit_reason;
3858 return 0;
3859 }
3860
29bd8a78 3861 if (unlikely(vmx->fail)) {
851ba692
AK		 3862 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3863 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 3864 = vmcs_read32(VM_INSTRUCTION_ERROR);
3865 return 0;
3866 }
6aa8b732 3867
d77c26fc 3868 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 3869 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 3870 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3871 exit_reason != EXIT_REASON_TASK_SWITCH))
3872 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3873 "(0x%x) and exit reason is 0x%x\n",
3874 __func__, vectoring_info, exit_reason);
3b86cd99
JK		 3875
3876 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
c4282df9 3877 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 3878 vmx->soft_vnmi_blocked = 0;
3b86cd99 3879 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 3880 vcpu->arch.nmi_pending) {
3b86cd99
JK		 3881 /*
3882 * This CPU don't support us in finding the end of an
3883 * NMI-blocked window if the guest runs with IRQs
3884 * disabled. So we pull the trigger after 1 s of
3885 * futile waiting, but inform the user about this.
3886 */
3887 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3888 "state on VCPU %d after 1 s timeout\n",
3889 __func__, vcpu->vcpu_id);
3890 vmx->soft_vnmi_blocked = 0;
3b86cd99 3891 }
3b86cd99
JK		 3892 }
3893
6aa8b732
AK		 3894 if (exit_reason < kvm_vmx_max_exit_handlers
3895 && kvm_vmx_exit_handlers[exit_reason])
851ba692 3896 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 3897 else {
851ba692
AK		 3898 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3899 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 3900 }
3901 return 0;
3902}
3903
95ba8273 3904static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 3905{
95ba8273 3906 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 3907 vmcs_write32(TPR_THRESHOLD, 0);
3908 return;
3909 }
3910
95ba8273 3911 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 3912}
3913
51aa01d1 3914static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 3915{
00eba012
AK		 3916 u32 exit_intr_info;
3917
3918 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
3919 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
3920 return;
3921
c5ca8e57 3922 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 3923 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 3924
3925 /* Handle machine checks before interrupts are enabled */
00eba012 3926 if (is_machine_check(exit_intr_info))
a0861c02
AK		 3927 kvm_machine_check();
3928
20f65983 3929 /* We need to handle NMIs before interrupts are enabled */
00eba012 3930 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 3931 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3932 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 3933 asm("int $2");
ff9d07a0
ZY		 3934 kvm_after_handle_nmi(&vmx->vcpu);
3935 }
51aa01d1 3936}
20f65983 3937
51aa01d1
AK		 3938static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
3939{
c5ca8e57 3940 u32 exit_intr_info;
51aa01d1
AK		 3941 bool unblock_nmi;
3942 u8 vector;
3943 bool idtv_info_valid;
3944
3945 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 3946
cf393f75 3947 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 3948 if (vmx->nmi_known_unmasked)
3949 return;
c5ca8e57
AK		 3950 /*
3951 * Can't use vmx->exit_intr_info since we're not sure what
3952 * the exit reason is.
3953 */
3954 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 3955 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3956 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3957 /*
7b4a25cb 3958 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 3959 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3960 * a guest IRET fault.
7b4a25cb
GN		 3961 * SDM 3: 23.2.2 (September 2008)
3962 * Bit 12 is undefined in any of the following cases:
3963 * If the VM exit sets the valid bit in the IDT-vectoring
3964 * information field.
3965 * If the VM exit is due to a double fault.
cf393f75 3966 */
7b4a25cb
GN		 3967 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3968 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 3969 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3970 GUEST_INTR_STATE_NMI);
9d58b931
AK		 3971 else
3972 vmx->nmi_known_unmasked =
3973 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
3974 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 3975 } else if (unlikely(vmx->soft_vnmi_blocked))
3976 vmx->vnmi_blocked_time +=
3977 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 3978}
3979
83422e17
AK		 3980static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
3981 u32 idt_vectoring_info,
3982 int instr_len_field,
3983 int error_code_field)
51aa01d1 3984{
51aa01d1
AK		 3985 u8 vector;
3986 int type;
3987 bool idtv_info_valid;
3988
3989 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 3990
37b96e98
GN		 3991 vmx->vcpu.arch.nmi_injected = false;
3992 kvm_clear_exception_queue(&vmx->vcpu);
3993 kvm_clear_interrupt_queue(&vmx->vcpu);
3994
3995 if (!idtv_info_valid)
3996 return;
3997
3842d135
AK		 3998 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
3999
668f612f
AK		 4000 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
4001 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 4002
64a7ec06 4003 switch (type) {
37b96e98
GN		 4004 case INTR_TYPE_NMI_INTR:
4005 vmx->vcpu.arch.nmi_injected = true;
668f612f 4006 /*
7b4a25cb 4007 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 4008 * Clear bit "block by NMI" before VM entry if a NMI
4009 * delivery faulted.
668f612f 4010 */
654f06fc 4011 vmx_set_nmi_mask(&vmx->vcpu, false);
37b96e98 4012 break;
37b96e98 4013 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f 4014 vmx->vcpu.arch.event_exit_inst_len =
83422e17 4015 vmcs_read32(instr_len_field);
66fd3f7f
GN		 4016 /* fall through */
4017 case INTR_TYPE_HARD_EXCEPTION:
35920a35 4018 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 4019 u32 err = vmcs_read32(error_code_field);
37b96e98 4020 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 4021 } else
4022 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 4023 break;
66fd3f7f
GN		 4024 case INTR_TYPE_SOFT_INTR:
4025 vmx->vcpu.arch.event_exit_inst_len =
83422e17 4026 vmcs_read32(instr_len_field);
66fd3f7f 4027 /* fall through */
37b96e98 4028 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 4029 kvm_queue_interrupt(&vmx->vcpu, vector,
4030 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 4031 break;
4032 default:
4033 break;
f7d9238f 4034 }
cf393f75
AK		 4035}
4036
83422e17
AK		 4037static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
4038{
4039 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
4040 VM_EXIT_INSTRUCTION_LEN,
4041 IDT_VECTORING_ERROR_CODE);
4042}
4043
b463a6f7
AK		 4044static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
4045{
4046 __vmx_complete_interrupts(to_vmx(vcpu),
4047 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
4048 VM_ENTRY_INSTRUCTION_LEN,
4049 VM_ENTRY_EXCEPTION_ERROR_CODE);
4050
4051 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
4052}
4053
c801949d
AK		 4054#ifdef CONFIG_X86_64
4055#define R "r"
4056#define Q "q"
4057#else
4058#define R "e"
4059#define Q "l"
4060#endif
4061
a3b5ba49 4062static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 4063{
a2fa3e9f 4064 struct vcpu_vmx *vmx = to_vmx(vcpu);
104f226b
AK		 4065
4066 /* Record the guest's net vcpu time for enforced NMI injections. */
4067 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
4068 vmx->entry_time = ktime_get();
4069
4070 /* Don't enter VMX if guest state is invalid, let the exit handler
4071 start emulation until we arrive back to a valid state */
4072 if (vmx->emulation_required && emulate_invalid_guest_state)
4073 return;
4074
4075 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
4076 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
4077 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
4078 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
4079
4080 /* When single-stepping over STI and MOV SS, we must clear the
4081 * corresponding interruptibility bits in the guest state. Otherwise
4082 * vmentry fails as it then expects bit 14 (BS) in pending debug
4083 * exceptions being set, but that's not correct for the guest debugging
4084 * case. */
4085 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
4086 vmx_set_interrupt_shadow(vcpu, 0);
4087
4088 asm(
6aa8b732 4089 /* Store host registers */
c801949d 4090 "push %%"R"dx; push %%"R"bp;"
40712fae 4091 "push %%"R"cx \n\t" /* placeholder for guest rcx */
c801949d 4092 "push %%"R"cx \n\t"
313dbd49
AK		 4093 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
4094 "je 1f \n\t"
4095 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 4096 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 4097 "1: \n\t"
d3edefc0
AK		 4098 /* Reload cr2 if changed */
4099 "mov %c[cr2](%0), %%"R"ax \n\t"
4100 "mov %%cr2, %%"R"dx \n\t"
4101 "cmp %%"R"ax, %%"R"dx \n\t"
4102 "je 2f \n\t"
4103 "mov %%"R"ax, %%cr2 \n\t"
4104 "2: \n\t"
6aa8b732 4105 /* Check if vmlaunch of vmresume is needed */
e08aa78a 4106 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 4107 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 4108 "mov %c[rax](%0), %%"R"ax \n\t"
4109 "mov %c[rbx](%0), %%"R"bx \n\t"
4110 "mov %c[rdx](%0), %%"R"dx \n\t"
4111 "mov %c[rsi](%0), %%"R"si \n\t"
4112 "mov %c[rdi](%0), %%"R"di \n\t"
4113 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 4114#ifdef CONFIG_X86_64
e08aa78a
AK		 4115 "mov %c[r8](%0), %%r8 \n\t"
4116 "mov %c[r9](%0), %%r9 \n\t"
4117 "mov %c[r10](%0), %%r10 \n\t"
4118 "mov %c[r11](%0), %%r11 \n\t"
4119 "mov %c[r12](%0), %%r12 \n\t"
4120 "mov %c[r13](%0), %%r13 \n\t"
4121 "mov %c[r14](%0), %%r14 \n\t"
4122 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 4123#endif
c801949d
AK		 4124 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
4125
6aa8b732 4126 /* Enter guest mode */
cd2276a7 4127 "jne .Llaunched \n\t"
4ecac3fd 4128 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 4129 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 4130 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 4131 ".Lkvm_vmx_return: "
6aa8b732 4132 /* Save guest registers, load host registers, keep flags */
40712fae
AK		 4133 "mov %0, %c[wordsize](%%"R"sp) \n\t"
4134 "pop %0 \n\t"
c801949d
AK		 4135 "mov %%"R"ax, %c[rax](%0) \n\t"
4136 "mov %%"R"bx, %c[rbx](%0) \n\t"
1c696d0e 4137 "pop"Q" %c[rcx](%0) \n\t"
c801949d
AK		 4138 "mov %%"R"dx, %c[rdx](%0) \n\t"
4139 "mov %%"R"si, %c[rsi](%0) \n\t"
4140 "mov %%"R"di, %c[rdi](%0) \n\t"
4141 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 4142#ifdef CONFIG_X86_64
e08aa78a
AK		 4143 "mov %%r8, %c[r8](%0) \n\t"
4144 "mov %%r9, %c[r9](%0) \n\t"
4145 "mov %%r10, %c[r10](%0) \n\t"
4146 "mov %%r11, %c[r11](%0) \n\t"
4147 "mov %%r12, %c[r12](%0) \n\t"
4148 "mov %%r13, %c[r13](%0) \n\t"
4149 "mov %%r14, %c[r14](%0) \n\t"
4150 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 4151#endif
c801949d
AK		 4152 "mov %%cr2, %%"R"ax \n\t"
4153 "mov %%"R"ax, %c[cr2](%0) \n\t"
4154
1c696d0e 4155 "pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 4156 "setbe %c[fail](%0) \n\t"
4157 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
4158 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
4159 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 4160 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 4161 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
4162 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
4163 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
4164 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
4165 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
4166 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
4167 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 4168#ifdef CONFIG_X86_64
ad312c7c
ZX		 4169 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
4170 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
4171 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
4172 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
4173 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
4174 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
4175 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
4176 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 4177#endif
40712fae
AK		 4178 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
4179 [wordsize]"i"(sizeof(ulong))
c2036300 4180 : "cc", "memory"
07d6f555 4181 , R"ax", R"bx", R"di", R"si"
c2036300 4182#ifdef CONFIG_X86_64
c2036300
LV		 4183 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
4184#endif
4185 );
6aa8b732 4186
6de4f3ad 4187 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 4188 | (1 << VCPU_EXREG_RFLAGS)
69c73028 4189 | (1 << VCPU_EXREG_CPL)
aff48baa
AK		 4190 | (1 << VCPU_EXREG_PDPTR)
4191 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 4192 vcpu->arch.regs_dirty = 0;
4193
1155f76a
AK		 4194 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
4195
d77c26fc 4196 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
15ad7146 4197 vmx->launched = 1;
1b6269db 4198
51aa01d1 4199 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
51aa01d1
AK		 4200
4201 vmx_complete_atomic_exit(vmx);
4202 vmx_recover_nmi_blocking(vmx);
cf393f75 4203 vmx_complete_interrupts(vmx);
6aa8b732
AK		 4204}
4205
c801949d
AK		 4206#undef R
4207#undef Q
4208
6aa8b732
AK		 4209static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
4210{
a2fa3e9f
GH		 4211 struct vcpu_vmx *vmx = to_vmx(vcpu);
4212
4213 if (vmx->vmcs) {
543e4243 4214 vcpu_clear(vmx);
a2fa3e9f
GH		 4215 free_vmcs(vmx->vmcs);
4216 vmx->vmcs = NULL;
6aa8b732
AK		 4217 }
4218}
4219
4220static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
4221{
fb3f0f51
RR		 4222 struct vcpu_vmx *vmx = to_vmx(vcpu);
4223
cdbecfc3 4224 free_vpid(vmx);
6aa8b732 4225 vmx_free_vmcs(vcpu);
fb3f0f51
RR		 4226 kfree(vmx->guest_msrs);
4227 kvm_vcpu_uninit(vcpu);
a4770347 4228 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 4229}
4230
4610c9cc
DX		 4231static inline void vmcs_init(struct vmcs *vmcs)
4232{
4233 u64 phys_addr = __pa(per_cpu(vmxarea, raw_smp_processor_id()));
4234
4235 if (!vmm_exclusive)
4236 kvm_cpu_vmxon(phys_addr);
4237
4238 vmcs_clear(vmcs);
4239
4240 if (!vmm_exclusive)
4241 kvm_cpu_vmxoff();
4242}
4243
fb3f0f51 4244static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 4245{
fb3f0f51 4246 int err;
c16f862d 4247 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 4248 int cpu;
6aa8b732 4249
a2fa3e9f 4250 if (!vmx)
fb3f0f51
RR		 4251 return ERR_PTR(-ENOMEM);
4252
2384d2b3
SY		 4253 allocate_vpid(vmx);
4254
fb3f0f51
RR		 4255 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4256 if (err)
4257 goto free_vcpu;
965b58a5 4258
a2fa3e9f 4259 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 4260 err = -ENOMEM;
fb3f0f51 4261 if (!vmx->guest_msrs) {
fb3f0f51
RR		 4262 goto uninit_vcpu;
4263 }
965b58a5 4264
a2fa3e9f
GH		 4265 vmx->vmcs = alloc_vmcs();
4266 if (!vmx->vmcs)
fb3f0f51 4267 goto free_msrs;
a2fa3e9f 4268
4610c9cc 4269 vmcs_init(vmx->vmcs);
a2fa3e9f 4270
15ad7146
AK		 4271 cpu = get_cpu();
4272 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 4273 vmx->vcpu.cpu = cpu;
8b9cf98c 4274 err = vmx_vcpu_setup(vmx);
fb3f0f51 4275 vmx_vcpu_put(&vmx->vcpu);
15ad7146 4276 put_cpu();
fb3f0f51
RR		 4277 if (err)
4278 goto free_vmcs;
5e4a0b3c 4279 if (vm_need_virtualize_apic_accesses(kvm))
be6d05cf
JK		 4280 err = alloc_apic_access_page(kvm);
4281 if (err)
5e4a0b3c 4282 goto free_vmcs;
fb3f0f51 4283
b927a3ce
SY		 4284 if (enable_ept) {
4285 if (!kvm->arch.ept_identity_map_addr)
4286 kvm->arch.ept_identity_map_addr =
4287 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 4288 err = -ENOMEM;
b7ebfb05
SY		 4289 if (alloc_identity_pagetable(kvm) != 0)
4290 goto free_vmcs;
93ea5388
GN		 4291 if (!init_rmode_identity_map(kvm))
4292 goto free_vmcs;
b927a3ce 4293 }
b7ebfb05 4294
fb3f0f51
RR		 4295 return &vmx->vcpu;
4296
4297free_vmcs:
4298 free_vmcs(vmx->vmcs);
4299free_msrs:
fb3f0f51
RR		 4300 kfree(vmx->guest_msrs);
4301uninit_vcpu:
4302 kvm_vcpu_uninit(&vmx->vcpu);
4303free_vcpu:
cdbecfc3 4304 free_vpid(vmx);
a4770347 4305 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 4306 return ERR_PTR(err);
6aa8b732
AK		 4307}
4308
002c7f7c
YS		 4309static void __init vmx_check_processor_compat(void *rtn)
4310{
4311 struct vmcs_config vmcs_conf;
4312
4313 *(int *)rtn = 0;
4314 if (setup_vmcs_config(&vmcs_conf) < 0)
4315 *(int *)rtn = -EIO;
4316 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4317 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4318 smp_processor_id());
4319 *(int *)rtn = -EIO;
4320 }
4321}
4322
67253af5
SY		 4323static int get_ept_level(void)
4324{
4325 return VMX_EPT_DEFAULT_GAW + 1;
4326}
4327
4b12f0de 4328static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 4329{
4b12f0de
SY		 4330 u64 ret;
4331
522c68c4
SY		 4332 /* For VT-d and EPT combination
4333 * 1. MMIO: always map as UC
4334 * 2. EPT with VT-d:
4335 * a. VT-d without snooping control feature: can't guarantee the
4336 * result, try to trust guest.
4337 * b. VT-d with snooping control feature: snooping control feature of
4338 * VT-d engine can guarantee the cache correctness. Just set it
4339 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 4340 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 4341 * consistent with host MTRR
4342 */
4b12f0de
SY		 4343 if (is_mmio)
4344 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 4345 else if (vcpu->kvm->arch.iommu_domain &&
4346 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4347 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4348 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 4349 else
522c68c4 4350 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 4351 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 4352
4353 return ret;
64d4d521
SY		 4354}
4355
f4c9e87c
AK		 4356#define _ER(x) { EXIT_REASON_##x, #x }
4357
229456fc 4358static const struct trace_print_flags vmx_exit_reasons_str[] = {
f4c9e87c
AK		 4359 _ER(EXCEPTION_NMI),
4360 _ER(EXTERNAL_INTERRUPT),
4361 _ER(TRIPLE_FAULT),
4362 _ER(PENDING_INTERRUPT),
4363 _ER(NMI_WINDOW),
4364 _ER(TASK_SWITCH),
4365 _ER(CPUID),
4366 _ER(HLT),
4367 _ER(INVLPG),
4368 _ER(RDPMC),
4369 _ER(RDTSC),
4370 _ER(VMCALL),
4371 _ER(VMCLEAR),
4372 _ER(VMLAUNCH),
4373 _ER(VMPTRLD),
4374 _ER(VMPTRST),
4375 _ER(VMREAD),
4376 _ER(VMRESUME),
4377 _ER(VMWRITE),
4378 _ER(VMOFF),
4379 _ER(VMON),
4380 _ER(CR_ACCESS),
4381 _ER(DR_ACCESS),
4382 _ER(IO_INSTRUCTION),
4383 _ER(MSR_READ),
4384 _ER(MSR_WRITE),
4385 _ER(MWAIT_INSTRUCTION),
4386 _ER(MONITOR_INSTRUCTION),
4387 _ER(PAUSE_INSTRUCTION),
4388 _ER(MCE_DURING_VMENTRY),
4389 _ER(TPR_BELOW_THRESHOLD),
4390 _ER(APIC_ACCESS),
4391 _ER(EPT_VIOLATION),
4392 _ER(EPT_MISCONFIG),
4393 _ER(WBINVD),
229456fc
MT		 4394 { -1, NULL }
4395};
4396
f4c9e87c
AK		 4397#undef _ER
4398
17cc3935 4399static int vmx_get_lpage_level(void)
344f414f 4400{
878403b7
SY		 4401 if (enable_ept && !cpu_has_vmx_ept_1g_page())
4402 return PT_DIRECTORY_LEVEL;
4403 else
4404 /* For shadow and EPT supported 1GB page */
4405 return PT_PDPE_LEVEL;
344f414f
JR		 4406}
4407
0e851880
SY		 4408static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4409{
4e47c7a6
SY		 4410 struct kvm_cpuid_entry2 *best;
4411 struct vcpu_vmx *vmx = to_vmx(vcpu);
4412 u32 exec_control;
4413
4414 vmx->rdtscp_enabled = false;
4415 if (vmx_rdtscp_supported()) {
4416 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4417 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4418 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4419 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4420 vmx->rdtscp_enabled = true;
4421 else {
4422 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4423 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4424 exec_control);
4425 }
4426 }
4427 }
0e851880
SY		 4428}
4429
d4330ef2
JR		 4430static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4431{
4432}
4433
8a76d7f2
JR		 4434static int vmx_check_intercept(struct kvm_vcpu *vcpu,
4435 struct x86_instruction_info *info,
4436 enum x86_intercept_stage stage)
4437{
4438 return X86EMUL_CONTINUE;
4439}
4440
cbdd1bea 4441static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 4442 .cpu_has_kvm_support = cpu_has_kvm_support,
4443 .disabled_by_bios = vmx_disabled_by_bios,
4444 .hardware_setup = hardware_setup,
4445 .hardware_unsetup = hardware_unsetup,
002c7f7c 4446 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 4447 .hardware_enable = hardware_enable,
4448 .hardware_disable = hardware_disable,
04547156 4449 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 4450
4451 .vcpu_create = vmx_create_vcpu,
4452 .vcpu_free = vmx_free_vcpu,
04d2cc77 4453 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 4454
04d2cc77 4455 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 4456 .vcpu_load = vmx_vcpu_load,
4457 .vcpu_put = vmx_vcpu_put,
4458
4459 .set_guest_debug = set_guest_debug,
4460 .get_msr = vmx_get_msr,
4461 .set_msr = vmx_set_msr,
4462 .get_segment_base = vmx_get_segment_base,
4463 .get_segment = vmx_get_segment,
4464 .set_segment = vmx_set_segment,
2e4d2653 4465 .get_cpl = vmx_get_cpl,
6aa8b732 4466 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 4467 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 4468 .decache_cr3 = vmx_decache_cr3,
25c4c276 4469 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 4470 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 4471 .set_cr3 = vmx_set_cr3,
4472 .set_cr4 = vmx_set_cr4,
6aa8b732 4473 .set_efer = vmx_set_efer,
6aa8b732
AK		 4474 .get_idt = vmx_get_idt,
4475 .set_idt = vmx_set_idt,
4476 .get_gdt = vmx_get_gdt,
4477 .set_gdt = vmx_set_gdt,
020df079 4478 .set_dr7 = vmx_set_dr7,
5fdbf976 4479 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 4480 .get_rflags = vmx_get_rflags,
4481 .set_rflags = vmx_set_rflags,
ebcbab4c 4482 .fpu_activate = vmx_fpu_activate,
02daab21 4483 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 4484
4485 .tlb_flush = vmx_flush_tlb,
6aa8b732 4486
6aa8b732 4487 .run = vmx_vcpu_run,
6062d012 4488 .handle_exit = vmx_handle_exit,
6aa8b732 4489 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 4490 .set_interrupt_shadow = vmx_set_interrupt_shadow,
4491 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 4492 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 4493 .set_irq = vmx_inject_irq,
95ba8273 4494 .set_nmi = vmx_inject_nmi,
298101da 4495 .queue_exception = vmx_queue_exception,
b463a6f7 4496 .cancel_injection = vmx_cancel_injection,
78646121 4497 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 4498 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 4499 .get_nmi_mask = vmx_get_nmi_mask,
4500 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 4501 .enable_nmi_window = enable_nmi_window,
4502 .enable_irq_window = enable_irq_window,
4503 .update_cr8_intercept = update_cr8_intercept,
95ba8273 4504
cbc94022 4505 .set_tss_addr = vmx_set_tss_addr,
67253af5 4506 .get_tdp_level = get_ept_level,
4b12f0de 4507 .get_mt_mask = vmx_get_mt_mask,
229456fc 4508
586f9607 4509 .get_exit_info = vmx_get_exit_info,
229456fc 4510 .exit_reasons_str = vmx_exit_reasons_str,
586f9607 4511
17cc3935 4512 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 4513
4514 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 4515
4516 .rdtscp_supported = vmx_rdtscp_supported,
d4330ef2
JR		 4517
4518 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 4519
4520 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 4521
4051b188 4522 .set_tsc_khz = vmx_set_tsc_khz,
99e3e30a 4523 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 4524 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 4525 .compute_tsc_offset = vmx_compute_tsc_offset,
1c97f0a0
JR		 4526
4527 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 4528
4529 .check_intercept = vmx_check_intercept,
6aa8b732
AK		 4530};
4531
4532static int __init vmx_init(void)
4533{
26bb0981
AK		 4534 int r, i;
4535
4536 rdmsrl_safe(MSR_EFER, &host_efer);
4537
4538 for (i = 0; i < NR_VMX_MSR; ++i)
4539 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 4540
3e7c73e9 4541 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4542 if (!vmx_io_bitmap_a)
4543 return -ENOMEM;
4544
3e7c73e9 4545 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 4546 if (!vmx_io_bitmap_b) {
4547 r = -ENOMEM;
4548 goto out;
4549 }
4550
5897297b
AK		 4551 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4552 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 4553 r = -ENOMEM;
4554 goto out1;
4555 }
4556
5897297b
AK		 4557 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4558 if (!vmx_msr_bitmap_longmode) {
4559 r = -ENOMEM;
4560 goto out2;
4561 }
4562
fdef3ad1
HQ		 4563 /*
4564 * Allow direct access to the PC debug port (it is often used for I/O
4565 * delays, but the vmexits simply slow things down).
4566 */
3e7c73e9
AK		 4567 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4568 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 4569
3e7c73e9 4570 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 4571
5897297b
AK		 4572 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4573 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 4574
2384d2b3
SY		 4575 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4576
0ee75bea
AK		 4577 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4578 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 4579 if (r)
5897297b 4580 goto out3;
25c5f225 4581
5897297b
AK		 4582 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4583 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4584 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4585 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4586 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4587 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 4588
089d034e 4589 if (enable_ept) {
1439442c 4590 bypass_guest_pf = 0;
534e38b4 4591 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 4592 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 4593 kvm_enable_tdp();
4594 } else
4595 kvm_disable_tdp();
1439442c 4596
c7addb90
AK		 4597 if (bypass_guest_pf)
4598 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4599
fdef3ad1
HQ		 4600 return 0;
4601
5897297b
AK		 4602out3:
4603 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 4604out2:
5897297b 4605 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 4606out1:
3e7c73e9 4607 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 4608out:
3e7c73e9 4609 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4610 return r;
6aa8b732
AK		 4611}
4612
4613static void __exit vmx_exit(void)
4614{
5897297b
AK		 4615 free_page((unsigned long)vmx_msr_bitmap_legacy);
4616 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 4617 free_page((unsigned long)vmx_io_bitmap_b);
4618 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 4619
cb498ea2 4620 kvm_exit();
6aa8b732
AK		 4621}
4622
4623module_init(vmx_init)
4624module_exit(vmx_exit)
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