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KVM: nVMX: Document 'nested' parameter
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
e495606d 21
edf88417 22#include <linux/kvm_host.h>
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/mm.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
c7addb90 28#include <linux/moduleparam.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
cafd6659 31#include <linux/tboot.h>
5fdbf976 32#include "kvm_cache_regs.h"
35920a35 33#include "x86.h"
e495606d 34
6aa8b732 35#include <asm/io.h>
3b3be0d1 36#include <asm/desc.h>
13673a90 37#include <asm/vmx.h>
6210e37b 38#include <asm/virtext.h>
a0861c02 39#include <asm/mce.h>
2acf923e
DC		 40#include <asm/i387.h>
41#include <asm/xcr.h>
6aa8b732 42
229456fc
MT		 43#include "trace.h"
44
4ecac3fd 45#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 46#define __ex_clear(x, reg) \
47 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 48
6aa8b732
AK		 49MODULE_AUTHOR("Qumranet");
50MODULE_LICENSE("GPL");
51
4462d21a 52static int __read_mostly enable_vpid = 1;
736caefe 53module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 54
4462d21a 55static int __read_mostly flexpriority_enabled = 1;
736caefe 56module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 57
4462d21a 58static int __read_mostly enable_ept = 1;
736caefe 59module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 60
3a624e29
NK		 61static int __read_mostly enable_unrestricted_guest = 1;
62module_param_named(unrestricted_guest,
63 enable_unrestricted_guest, bool, S_IRUGO);
64
4462d21a 65static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 66module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 67
b923e62e
DX		 68static int __read_mostly vmm_exclusive = 1;
69module_param(vmm_exclusive, bool, S_IRUGO);
70
443381a8
AL		 71static int __read_mostly yield_on_hlt = 1;
72module_param(yield_on_hlt, bool, S_IRUGO);
73
801d3424
NHE		 74/*
75 * If nested=1, nested virtualization is supported, i.e., guests may use
76 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
77 * use VMX instructions.
78 */
79static int __read_mostly nested = 0;
80module_param(nested, bool, S_IRUGO);
81
cdc0e244
AK		 82#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
83 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
84#define KVM_GUEST_CR0_MASK \
85 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
86#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 87 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 88#define KVM_VM_CR0_ALWAYS_ON \
89 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 90#define KVM_CR4_GUEST_OWNED_BITS \
91 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
92 | X86_CR4_OSXMMEXCPT)
93
cdc0e244
AK		 94#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
95#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
96
78ac8b47
AK		 97#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
98
4b8d54f9
ZE		 99/*
100 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
101 * ple_gap: upper bound on the amount of time between two successive
102 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 103 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 104 * ple_window: upper bound on the amount of time a guest is allowed to execute
105 * in a PAUSE loop. Tests indicate that most spinlocks are held for
106 * less than 2^12 cycles
107 * Time is measured based on a counter that runs at the same rate as the TSC,
108 * refer SDM volume 3b section 21.6.13 & 22.1.3.
109 */
00c25bce 110#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 111#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
112static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
113module_param(ple_gap, int, S_IRUGO);
114
115static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
116module_param(ple_window, int, S_IRUGO);
117
61d2ef2c 118#define NR_AUTOLOAD_MSRS 1
ff2f6fe9 119#define VMCS02_POOL_SIZE 1
61d2ef2c 120
a2fa3e9f
GH		 121struct vmcs {
122 u32 revision_id;
123 u32 abort;
124 char data[0];
125};
126
d462b819
NHE		 127/*
128 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
129 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
130 * loaded on this CPU (so we can clear them if the CPU goes down).
131 */
132struct loaded_vmcs {
133 struct vmcs *vmcs;
134 int cpu;
135 int launched;
136 struct list_head loaded_vmcss_on_cpu_link;
137};
138
26bb0981
AK		 139struct shared_msr_entry {
140 unsigned index;
141 u64 data;
d5696725 142 u64 mask;
26bb0981
AK		 143};
144
a9d30f33
NHE		 145/*
146 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
147 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
148 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
149 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
150 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
151 * More than one of these structures may exist, if L1 runs multiple L2 guests.
152 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
153 * underlying hardware which will be used to run L2.
154 * This structure is packed to ensure that its layout is identical across
155 * machines (necessary for live migration).
156 * If there are changes in this struct, VMCS12_REVISION must be changed.
157 */
22bd0358 158typedef u64 natural_width;
a9d30f33
NHE		 159struct __packed vmcs12 {
160 /* According to the Intel spec, a VMCS region must start with the
161 * following two fields. Then follow implementation-specific data.
162 */
163 u32 revision_id;
164 u32 abort;
22bd0358 165
27d6c865
NHE		 166 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
167 u32 padding[7]; /* room for future expansion */
168
22bd0358
NHE		 169 u64 io_bitmap_a;
170 u64 io_bitmap_b;
171 u64 msr_bitmap;
172 u64 vm_exit_msr_store_addr;
173 u64 vm_exit_msr_load_addr;
174 u64 vm_entry_msr_load_addr;
175 u64 tsc_offset;
176 u64 virtual_apic_page_addr;
177 u64 apic_access_addr;
178 u64 ept_pointer;
179 u64 guest_physical_address;
180 u64 vmcs_link_pointer;
181 u64 guest_ia32_debugctl;
182 u64 guest_ia32_pat;
183 u64 guest_ia32_efer;
184 u64 guest_ia32_perf_global_ctrl;
185 u64 guest_pdptr0;
186 u64 guest_pdptr1;
187 u64 guest_pdptr2;
188 u64 guest_pdptr3;
189 u64 host_ia32_pat;
190 u64 host_ia32_efer;
191 u64 host_ia32_perf_global_ctrl;
192 u64 padding64[8]; /* room for future expansion */
193 /*
194 * To allow migration of L1 (complete with its L2 guests) between
195 * machines of different natural widths (32 or 64 bit), we cannot have
196 * unsigned long fields with no explict size. We use u64 (aliased
197 * natural_width) instead. Luckily, x86 is little-endian.
198 */
199 natural_width cr0_guest_host_mask;
200 natural_width cr4_guest_host_mask;
201 natural_width cr0_read_shadow;
202 natural_width cr4_read_shadow;
203 natural_width cr3_target_value0;
204 natural_width cr3_target_value1;
205 natural_width cr3_target_value2;
206 natural_width cr3_target_value3;
207 natural_width exit_qualification;
208 natural_width guest_linear_address;
209 natural_width guest_cr0;
210 natural_width guest_cr3;
211 natural_width guest_cr4;
212 natural_width guest_es_base;
213 natural_width guest_cs_base;
214 natural_width guest_ss_base;
215 natural_width guest_ds_base;
216 natural_width guest_fs_base;
217 natural_width guest_gs_base;
218 natural_width guest_ldtr_base;
219 natural_width guest_tr_base;
220 natural_width guest_gdtr_base;
221 natural_width guest_idtr_base;
222 natural_width guest_dr7;
223 natural_width guest_rsp;
224 natural_width guest_rip;
225 natural_width guest_rflags;
226 natural_width guest_pending_dbg_exceptions;
227 natural_width guest_sysenter_esp;
228 natural_width guest_sysenter_eip;
229 natural_width host_cr0;
230 natural_width host_cr3;
231 natural_width host_cr4;
232 natural_width host_fs_base;
233 natural_width host_gs_base;
234 natural_width host_tr_base;
235 natural_width host_gdtr_base;
236 natural_width host_idtr_base;
237 natural_width host_ia32_sysenter_esp;
238 natural_width host_ia32_sysenter_eip;
239 natural_width host_rsp;
240 natural_width host_rip;
241 natural_width paddingl[8]; /* room for future expansion */
242 u32 pin_based_vm_exec_control;
243 u32 cpu_based_vm_exec_control;
244 u32 exception_bitmap;
245 u32 page_fault_error_code_mask;
246 u32 page_fault_error_code_match;
247 u32 cr3_target_count;
248 u32 vm_exit_controls;
249 u32 vm_exit_msr_store_count;
250 u32 vm_exit_msr_load_count;
251 u32 vm_entry_controls;
252 u32 vm_entry_msr_load_count;
253 u32 vm_entry_intr_info_field;
254 u32 vm_entry_exception_error_code;
255 u32 vm_entry_instruction_len;
256 u32 tpr_threshold;
257 u32 secondary_vm_exec_control;
258 u32 vm_instruction_error;
259 u32 vm_exit_reason;
260 u32 vm_exit_intr_info;
261 u32 vm_exit_intr_error_code;
262 u32 idt_vectoring_info_field;
263 u32 idt_vectoring_error_code;
264 u32 vm_exit_instruction_len;
265 u32 vmx_instruction_info;
266 u32 guest_es_limit;
267 u32 guest_cs_limit;
268 u32 guest_ss_limit;
269 u32 guest_ds_limit;
270 u32 guest_fs_limit;
271 u32 guest_gs_limit;
272 u32 guest_ldtr_limit;
273 u32 guest_tr_limit;
274 u32 guest_gdtr_limit;
275 u32 guest_idtr_limit;
276 u32 guest_es_ar_bytes;
277 u32 guest_cs_ar_bytes;
278 u32 guest_ss_ar_bytes;
279 u32 guest_ds_ar_bytes;
280 u32 guest_fs_ar_bytes;
281 u32 guest_gs_ar_bytes;
282 u32 guest_ldtr_ar_bytes;
283 u32 guest_tr_ar_bytes;
284 u32 guest_interruptibility_info;
285 u32 guest_activity_state;
286 u32 guest_sysenter_cs;
287 u32 host_ia32_sysenter_cs;
288 u32 padding32[8]; /* room for future expansion */
289 u16 virtual_processor_id;
290 u16 guest_es_selector;
291 u16 guest_cs_selector;
292 u16 guest_ss_selector;
293 u16 guest_ds_selector;
294 u16 guest_fs_selector;
295 u16 guest_gs_selector;
296 u16 guest_ldtr_selector;
297 u16 guest_tr_selector;
298 u16 host_es_selector;
299 u16 host_cs_selector;
300 u16 host_ss_selector;
301 u16 host_ds_selector;
302 u16 host_fs_selector;
303 u16 host_gs_selector;
304 u16 host_tr_selector;
a9d30f33
NHE		 305};
306
307/*
308 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
309 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
310 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
311 */
312#define VMCS12_REVISION 0x11e57ed0
313
314/*
315 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
316 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
317 * current implementation, 4K are reserved to avoid future complications.
318 */
319#define VMCS12_SIZE 0x1000
320
ff2f6fe9
NHE		 321/* Used to remember the last vmcs02 used for some recently used vmcs12s */
322struct vmcs02_list {
323 struct list_head list;
324 gpa_t vmptr;
325 struct loaded_vmcs vmcs02;
326};
327
ec378aee
NHE		 328/*
329 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
330 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
331 */
332struct nested_vmx {
333 /* Has the level1 guest done vmxon? */
334 bool vmxon;
a9d30f33
NHE		 335
336 /* The guest-physical address of the current VMCS L1 keeps for L2 */
337 gpa_t current_vmptr;
338 /* The host-usable pointer to the above */
339 struct page *current_vmcs12_page;
340 struct vmcs12 *current_vmcs12;
ff2f6fe9
NHE		 341
342 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
343 struct list_head vmcs02_pool;
344 int vmcs02_num;
fe3ef05c 345 u64 vmcs01_tsc_offset;
644d711a
NHE		 346 /* L2 must run next, and mustn't decide to exit to L1. */
347 bool nested_run_pending;
fe3ef05c
NHE		 348 /*
349 * Guest pages referred to in vmcs02 with host-physical pointers, so
350 * we must keep them pinned while L2 runs.
351 */
352 struct page *apic_access_page;
ec378aee
NHE		 353};
354
a2fa3e9f 355struct vcpu_vmx {
fb3f0f51 356 struct kvm_vcpu vcpu;
313dbd49 357 unsigned long host_rsp;
29bd8a78 358 u8 fail;
69c73028 359 u8 cpl;
9d58b931 360 bool nmi_known_unmasked;
51aa01d1 361 u32 exit_intr_info;
1155f76a 362 u32 idt_vectoring_info;
6de12732 363 ulong rflags;
26bb0981 364 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 365 int nmsrs;
366 int save_nmsrs;
a2fa3e9f 367#ifdef CONFIG_X86_64
44ea2b17
AK		 368 u64 msr_host_kernel_gs_base;
369 u64 msr_guest_kernel_gs_base;
a2fa3e9f 370#endif
d462b819
NHE		 371 /*
372 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
373 * non-nested (L1) guest, it always points to vmcs01. For a nested
374 * guest (L2), it points to a different VMCS.
375 */
376 struct loaded_vmcs vmcs01;
377 struct loaded_vmcs *loaded_vmcs;
378 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 379 struct msr_autoload {
380 unsigned nr;
381 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
382 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
383 } msr_autoload;
a2fa3e9f
GH		 384 struct {
385 int loaded;
386 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 387 int gs_ldt_reload_needed;
388 int fs_reload_needed;
d77c26fc 389 } host_state;
9c8cba37 390 struct {
7ffd92c5 391 int vm86_active;
78ac8b47 392 ulong save_rflags;
7ffd92c5
AK		 393 struct kvm_save_segment {
394 u16 selector;
395 unsigned long base;
396 u32 limit;
397 u32 ar;
398 } tr, es, ds, fs, gs;
9c8cba37 399 } rmode;
2fb92db1
AK		 400 struct {
401 u32 bitmask; /* 4 bits per segment (1 bit per field) */
402 struct kvm_save_segment seg[8];
403 } segment_cache;
2384d2b3 404 int vpid;
04fa4d32 405 bool emulation_required;
3b86cd99
JK		 406
407 /* Support for vnmi-less CPUs */
408 int soft_vnmi_blocked;
409 ktime_t entry_time;
410 s64 vnmi_blocked_time;
a0861c02 411 u32 exit_reason;
4e47c7a6
SY		 412
413 bool rdtscp_enabled;
ec378aee
NHE		 414
415 /* Support for a guest hypervisor (nested VMX) */
416 struct nested_vmx nested;
a2fa3e9f
GH		 417};
418
2fb92db1
AK		 419enum segment_cache_field {
420 SEG_FIELD_SEL = 0,
421 SEG_FIELD_BASE = 1,
422 SEG_FIELD_LIMIT = 2,
423 SEG_FIELD_AR = 3,
424
425 SEG_FIELD_NR = 4
426};
427
a2fa3e9f
GH		 428static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
429{
fb3f0f51 430 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 431}
432
22bd0358
NHE		 433#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
434#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
435#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
436 [number##_HIGH] = VMCS12_OFFSET(name)+4
437
438static unsigned short vmcs_field_to_offset_table[] = {
439 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
440 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
441 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
442 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
443 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
444 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
445 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
446 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
447 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
448 FIELD(HOST_ES_SELECTOR, host_es_selector),
449 FIELD(HOST_CS_SELECTOR, host_cs_selector),
450 FIELD(HOST_SS_SELECTOR, host_ss_selector),
451 FIELD(HOST_DS_SELECTOR, host_ds_selector),
452 FIELD(HOST_FS_SELECTOR, host_fs_selector),
453 FIELD(HOST_GS_SELECTOR, host_gs_selector),
454 FIELD(HOST_TR_SELECTOR, host_tr_selector),
455 FIELD64(IO_BITMAP_A, io_bitmap_a),
456 FIELD64(IO_BITMAP_B, io_bitmap_b),
457 FIELD64(MSR_BITMAP, msr_bitmap),
458 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
459 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
460 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
461 FIELD64(TSC_OFFSET, tsc_offset),
462 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
463 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
464 FIELD64(EPT_POINTER, ept_pointer),
465 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
466 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
467 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
468 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
469 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
470 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
471 FIELD64(GUEST_PDPTR0, guest_pdptr0),
472 FIELD64(GUEST_PDPTR1, guest_pdptr1),
473 FIELD64(GUEST_PDPTR2, guest_pdptr2),
474 FIELD64(GUEST_PDPTR3, guest_pdptr3),
475 FIELD64(HOST_IA32_PAT, host_ia32_pat),
476 FIELD64(HOST_IA32_EFER, host_ia32_efer),
477 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
478 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
479 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
480 FIELD(EXCEPTION_BITMAP, exception_bitmap),
481 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
482 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
483 FIELD(CR3_TARGET_COUNT, cr3_target_count),
484 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
485 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
486 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
487 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
488 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
489 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
490 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
491 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
492 FIELD(TPR_THRESHOLD, tpr_threshold),
493 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
494 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
495 FIELD(VM_EXIT_REASON, vm_exit_reason),
496 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
497 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
498 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
499 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
500 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
501 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
502 FIELD(GUEST_ES_LIMIT, guest_es_limit),
503 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
504 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
505 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
506 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
507 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
508 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
509 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
510 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
511 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
512 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
513 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
514 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
515 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
516 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
517 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
518 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
519 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
520 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
521 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
522 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
523 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
524 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
525 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
526 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
527 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
528 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
529 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
530 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
531 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
532 FIELD(EXIT_QUALIFICATION, exit_qualification),
533 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
534 FIELD(GUEST_CR0, guest_cr0),
535 FIELD(GUEST_CR3, guest_cr3),
536 FIELD(GUEST_CR4, guest_cr4),
537 FIELD(GUEST_ES_BASE, guest_es_base),
538 FIELD(GUEST_CS_BASE, guest_cs_base),
539 FIELD(GUEST_SS_BASE, guest_ss_base),
540 FIELD(GUEST_DS_BASE, guest_ds_base),
541 FIELD(GUEST_FS_BASE, guest_fs_base),
542 FIELD(GUEST_GS_BASE, guest_gs_base),
543 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
544 FIELD(GUEST_TR_BASE, guest_tr_base),
545 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
546 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
547 FIELD(GUEST_DR7, guest_dr7),
548 FIELD(GUEST_RSP, guest_rsp),
549 FIELD(GUEST_RIP, guest_rip),
550 FIELD(GUEST_RFLAGS, guest_rflags),
551 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
552 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
553 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
554 FIELD(HOST_CR0, host_cr0),
555 FIELD(HOST_CR3, host_cr3),
556 FIELD(HOST_CR4, host_cr4),
557 FIELD(HOST_FS_BASE, host_fs_base),
558 FIELD(HOST_GS_BASE, host_gs_base),
559 FIELD(HOST_TR_BASE, host_tr_base),
560 FIELD(HOST_GDTR_BASE, host_gdtr_base),
561 FIELD(HOST_IDTR_BASE, host_idtr_base),
562 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
563 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
564 FIELD(HOST_RSP, host_rsp),
565 FIELD(HOST_RIP, host_rip),
566};
567static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
568
569static inline short vmcs_field_to_offset(unsigned long field)
570{
571 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
572 return -1;
573 return vmcs_field_to_offset_table[field];
574}
575
a9d30f33
NHE		 576static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
577{
578 return to_vmx(vcpu)->nested.current_vmcs12;
579}
580
581static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
582{
583 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
584 if (is_error_page(page)) {
585 kvm_release_page_clean(page);
586 return NULL;
587 }
588 return page;
589}
590
591static void nested_release_page(struct page *page)
592{
593 kvm_release_page_dirty(page);
594}
595
596static void nested_release_page_clean(struct page *page)
597{
598 kvm_release_page_clean(page);
599}
600
4e1096d2 601static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 602static void kvm_cpu_vmxon(u64 addr);
603static void kvm_cpu_vmxoff(void);
aff48baa 604static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 605static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
75880a01 606
6aa8b732
AK		 607static DEFINE_PER_CPU(struct vmcs *, vmxarea);
608static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 609/*
610 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
611 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
612 */
613static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 614static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 615
3e7c73e9
AK		 616static unsigned long *vmx_io_bitmap_a;
617static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 618static unsigned long *vmx_msr_bitmap_legacy;
619static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 620
110312c8
AK		 621static bool cpu_has_load_ia32_efer;
622
2384d2b3
SY		 623static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
624static DEFINE_SPINLOCK(vmx_vpid_lock);
625
1c3d14fe 626static struct vmcs_config {
6aa8b732
AK		 627 int size;
628 int order;
629 u32 revision_id;
1c3d14fe
YS		 630 u32 pin_based_exec_ctrl;
631 u32 cpu_based_exec_ctrl;
f78e0e2e 632 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 633 u32 vmexit_ctrl;
634 u32 vmentry_ctrl;
635} vmcs_config;
6aa8b732 636
efff9e53 637static struct vmx_capability {
d56f546d
SY		 638 u32 ept;
639 u32 vpid;
640} vmx_capability;
641
6aa8b732
AK		 642#define VMX_SEGMENT_FIELD(seg) \
643 [VCPU_SREG_##seg] = { \
644 .selector = GUEST_##seg##_SELECTOR, \
645 .base = GUEST_##seg##_BASE, \
646 .limit = GUEST_##seg##_LIMIT, \
647 .ar_bytes = GUEST_##seg##_AR_BYTES, \
648 }
649
650static struct kvm_vmx_segment_field {
651 unsigned selector;
652 unsigned base;
653 unsigned limit;
654 unsigned ar_bytes;
655} kvm_vmx_segment_fields[] = {
656 VMX_SEGMENT_FIELD(CS),
657 VMX_SEGMENT_FIELD(DS),
658 VMX_SEGMENT_FIELD(ES),
659 VMX_SEGMENT_FIELD(FS),
660 VMX_SEGMENT_FIELD(GS),
661 VMX_SEGMENT_FIELD(SS),
662 VMX_SEGMENT_FIELD(TR),
663 VMX_SEGMENT_FIELD(LDTR),
664};
665
26bb0981
AK		 666static u64 host_efer;
667
6de4f3ad
AK		 668static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
669
4d56c8a7 670/*
8c06585d 671 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 672 * away by decrementing the array size.
673 */
6aa8b732 674static const u32 vmx_msr_index[] = {
05b3e0c2 675#ifdef CONFIG_X86_64
44ea2b17 676 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 677#endif
8c06585d 678 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 679};
9d8f549d 680#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 681
31299944 682static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 683{
684 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
685 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 686 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 687}
688
31299944 689static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 690{
691 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
692 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 693 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 694}
695
31299944 696static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 697{
698 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
699 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 700 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 701}
702
31299944 703static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 704{
705 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
706 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
707}
708
31299944 709static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 710{
711 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
712 INTR_INFO_VALID_MASK)) ==
713 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
714}
715
31299944 716static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 717{
04547156 718 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 719}
720
31299944 721static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 722{
04547156 723 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 724}
725
31299944 726static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 727{
04547156 728 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 729}
730
31299944 731static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 732{
04547156
SY		 733 return vmcs_config.cpu_based_exec_ctrl &
734 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 735}
736
774ead3a 737static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 738{
04547156
SY		 739 return vmcs_config.cpu_based_2nd_exec_ctrl &
740 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
741}
742
743static inline bool cpu_has_vmx_flexpriority(void)
744{
745 return cpu_has_vmx_tpr_shadow() &&
746 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 747}
748
e799794e
MT		 749static inline bool cpu_has_vmx_ept_execute_only(void)
750{
31299944 751 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 752}
753
754static inline bool cpu_has_vmx_eptp_uncacheable(void)
755{
31299944 756 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 757}
758
759static inline bool cpu_has_vmx_eptp_writeback(void)
760{
31299944 761 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 762}
763
764static inline bool cpu_has_vmx_ept_2m_page(void)
765{
31299944 766 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 767}
768
878403b7
SY		 769static inline bool cpu_has_vmx_ept_1g_page(void)
770{
31299944 771 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 772}
773
4bc9b982
SY		 774static inline bool cpu_has_vmx_ept_4levels(void)
775{
776 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
777}
778
31299944 779static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 780{
31299944 781 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 782}
783
31299944 784static inline bool cpu_has_vmx_invept_context(void)
d56f546d 785{
31299944 786 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 787}
788
31299944 789static inline bool cpu_has_vmx_invept_global(void)
d56f546d 790{
31299944 791 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 792}
793
518c8aee
GJ		 794static inline bool cpu_has_vmx_invvpid_single(void)
795{
796 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
797}
798
b9d762fa
GJ		 799static inline bool cpu_has_vmx_invvpid_global(void)
800{
801 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
802}
803
31299944 804static inline bool cpu_has_vmx_ept(void)
d56f546d 805{
04547156
SY		 806 return vmcs_config.cpu_based_2nd_exec_ctrl &
807 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 808}
809
31299944 810static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 811{
812 return vmcs_config.cpu_based_2nd_exec_ctrl &
813 SECONDARY_EXEC_UNRESTRICTED_GUEST;
814}
815
31299944 816static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 817{
818 return vmcs_config.cpu_based_2nd_exec_ctrl &
819 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
820}
821
31299944 822static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 823{
6d3e435e 824 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 825}
826
31299944 827static inline bool cpu_has_vmx_vpid(void)
2384d2b3 828{
04547156
SY		 829 return vmcs_config.cpu_based_2nd_exec_ctrl &
830 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 831}
832
31299944 833static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 834{
835 return vmcs_config.cpu_based_2nd_exec_ctrl &
836 SECONDARY_EXEC_RDTSCP;
837}
838
31299944 839static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 840{
841 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
842}
843
f5f48ee1
SY		 844static inline bool cpu_has_vmx_wbinvd_exit(void)
845{
846 return vmcs_config.cpu_based_2nd_exec_ctrl &
847 SECONDARY_EXEC_WBINVD_EXITING;
848}
849
04547156
SY		 850static inline bool report_flexpriority(void)
851{
852 return flexpriority_enabled;
853}
854
fe3ef05c
NHE		 855static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
856{
857 return vmcs12->cpu_based_vm_exec_control & bit;
858}
859
860static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
861{
862 return (vmcs12->cpu_based_vm_exec_control &
863 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
864 (vmcs12->secondary_vm_exec_control & bit);
865}
866
644d711a
NHE		 867static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
868 struct kvm_vcpu *vcpu)
869{
870 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
871}
872
873static inline bool is_exception(u32 intr_info)
874{
875 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
876 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
877}
878
879static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 880static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
881 struct vmcs12 *vmcs12,
882 u32 reason, unsigned long qualification);
883
8b9cf98c 884static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 885{
886 int i;
887
a2fa3e9f 888 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 889 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 890 return i;
891 return -1;
892}
893
2384d2b3
SY		 894static inline void __invvpid(int ext, u16 vpid, gva_t gva)
895{
896 struct {
897 u64 vpid : 16;
898 u64 rsvd : 48;
899 u64 gva;
900 } operand = { vpid, 0, gva };
901
4ecac3fd 902 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 903 /* CF==1 or ZF==1 --> rc = -1 */
904 "; ja 1f ; ud2 ; 1:"
905 : : "a"(&operand), "c"(ext) : "cc", "memory");
906}
907
1439442c
SY		 908static inline void __invept(int ext, u64 eptp, gpa_t gpa)
909{
910 struct {
911 u64 eptp, gpa;
912 } operand = {eptp, gpa};
913
4ecac3fd 914 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 915 /* CF==1 or ZF==1 --> rc = -1 */
916 "; ja 1f ; ud2 ; 1:\n"
917 : : "a" (&operand), "c" (ext) : "cc", "memory");
918}
919
26bb0981 920static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 921{
922 int i;
923
8b9cf98c 924 i = __find_msr_index(vmx, msr);
a75beee6 925 if (i >= 0)
a2fa3e9f 926 return &vmx->guest_msrs[i];
8b6d44c7 927 return NULL;
7725f0ba
AK		 928}
929
6aa8b732
AK		 930static void vmcs_clear(struct vmcs *vmcs)
931{
932 u64 phys_addr = __pa(vmcs);
933 u8 error;
934
4ecac3fd 935 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 936 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 937 : "cc", "memory");
938 if (error)
939 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
940 vmcs, phys_addr);
941}
942
d462b819
NHE		 943static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
944{
945 vmcs_clear(loaded_vmcs->vmcs);
946 loaded_vmcs->cpu = -1;
947 loaded_vmcs->launched = 0;
948}
949
7725b894
DX		 950static void vmcs_load(struct vmcs *vmcs)
951{
952 u64 phys_addr = __pa(vmcs);
953 u8 error;
954
955 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 956 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 957 : "cc", "memory");
958 if (error)
2844d849 959 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
7725b894
DX		 960 vmcs, phys_addr);
961}
962
d462b819 963static void __loaded_vmcs_clear(void *arg)
6aa8b732 964{
d462b819 965 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 966 int cpu = raw_smp_processor_id();
6aa8b732 967
d462b819
NHE		 968 if (loaded_vmcs->cpu != cpu)
969 return; /* vcpu migration can race with cpu offline */
970 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 971 per_cpu(current_vmcs, cpu) = NULL;
d462b819
NHE		 972 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
973 loaded_vmcs_init(loaded_vmcs);
6aa8b732
AK		 974}
975
d462b819 976static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 977{
d462b819
NHE		 978 if (loaded_vmcs->cpu != -1)
979 smp_call_function_single(
980 loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 981}
982
1760dd49 983static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 984{
985 if (vmx->vpid == 0)
986 return;
987
518c8aee
GJ		 988 if (cpu_has_vmx_invvpid_single())
989 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 990}
991
b9d762fa
GJ		 992static inline void vpid_sync_vcpu_global(void)
993{
994 if (cpu_has_vmx_invvpid_global())
995 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
996}
997
998static inline void vpid_sync_context(struct vcpu_vmx *vmx)
999{
1000 if (cpu_has_vmx_invvpid_single())
1760dd49 1001 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1002 else
1003 vpid_sync_vcpu_global();
1004}
1005
1439442c
SY		 1006static inline void ept_sync_global(void)
1007{
1008 if (cpu_has_vmx_invept_global())
1009 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1010}
1011
1012static inline void ept_sync_context(u64 eptp)
1013{
089d034e 1014 if (enable_ept) {
1439442c
SY		 1015 if (cpu_has_vmx_invept_context())
1016 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1017 else
1018 ept_sync_global();
1019 }
1020}
1021
1022static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1023{
089d034e 1024 if (enable_ept) {
1439442c
SY		 1025 if (cpu_has_vmx_invept_individual_addr())
1026 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1027 eptp, gpa);
1028 else
1029 ept_sync_context(eptp);
1030 }
1031}
1032
96304217 1033static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1034{
5e520e62 1035 unsigned long value;
6aa8b732 1036
5e520e62
AK		 1037 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1038 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1039 return value;
1040}
1041
96304217 1042static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1043{
1044 return vmcs_readl(field);
1045}
1046
96304217 1047static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1048{
1049 return vmcs_readl(field);
1050}
1051
96304217 1052static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1053{
05b3e0c2 1054#ifdef CONFIG_X86_64
6aa8b732
AK		 1055 return vmcs_readl(field);
1056#else
1057 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1058#endif
1059}
1060
e52de1b8
AK		 1061static noinline void vmwrite_error(unsigned long field, unsigned long value)
1062{
1063 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1064 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1065 dump_stack();
1066}
1067
6aa8b732
AK		 1068static void vmcs_writel(unsigned long field, unsigned long value)
1069{
1070 u8 error;
1071
4ecac3fd 1072 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1073 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1074 if (unlikely(error))
1075 vmwrite_error(field, value);
6aa8b732
AK		 1076}
1077
1078static void vmcs_write16(unsigned long field, u16 value)
1079{
1080 vmcs_writel(field, value);
1081}
1082
1083static void vmcs_write32(unsigned long field, u32 value)
1084{
1085 vmcs_writel(field, value);
1086}
1087
1088static void vmcs_write64(unsigned long field, u64 value)
1089{
6aa8b732 1090 vmcs_writel(field, value);
7682f2d0 1091#ifndef CONFIG_X86_64
6aa8b732
AK		 1092 asm volatile ("");
1093 vmcs_writel(field+1, value >> 32);
1094#endif
1095}
1096
2ab455cc
AL		 1097static void vmcs_clear_bits(unsigned long field, u32 mask)
1098{
1099 vmcs_writel(field, vmcs_readl(field) & ~mask);
1100}
1101
1102static void vmcs_set_bits(unsigned long field, u32 mask)
1103{
1104 vmcs_writel(field, vmcs_readl(field) | mask);
1105}
1106
2fb92db1
AK		 1107static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1108{
1109 vmx->segment_cache.bitmask = 0;
1110}
1111
1112static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1113 unsigned field)
1114{
1115 bool ret;
1116 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1117
1118 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1119 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1120 vmx->segment_cache.bitmask = 0;
1121 }
1122 ret = vmx->segment_cache.bitmask & mask;
1123 vmx->segment_cache.bitmask |= mask;
1124 return ret;
1125}
1126
1127static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1128{
1129 u16 *p = &vmx->segment_cache.seg[seg].selector;
1130
1131 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1132 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1133 return *p;
1134}
1135
1136static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1137{
1138 ulong *p = &vmx->segment_cache.seg[seg].base;
1139
1140 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1141 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1142 return *p;
1143}
1144
1145static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1146{
1147 u32 *p = &vmx->segment_cache.seg[seg].limit;
1148
1149 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1150 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1151 return *p;
1152}
1153
1154static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1155{
1156 u32 *p = &vmx->segment_cache.seg[seg].ar;
1157
1158 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1159 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1160 return *p;
1161}
1162
abd3f2d6
AK		 1163static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1164{
1165 u32 eb;
1166
fd7373cc
JK		 1167 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1168 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1169 if ((vcpu->guest_debug &
1170 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1171 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1172 eb |= 1u << BP_VECTOR;
7ffd92c5 1173 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1174 eb = ~0;
089d034e 1175 if (enable_ept)
1439442c 1176 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1177 if (vcpu->fpu_active)
1178 eb &= ~(1u << NM_VECTOR);
36cf24e0
NHE		 1179
1180 /* When we are running a nested L2 guest and L1 specified for it a
1181 * certain exception bitmap, we must trap the same exceptions and pass
1182 * them to L1. When running L2, we will only handle the exceptions
1183 * specified above if L1 did not want them.
1184 */
1185 if (is_guest_mode(vcpu))
1186 eb |= get_vmcs12(vcpu)->exception_bitmap;
1187
abd3f2d6
AK		 1188 vmcs_write32(EXCEPTION_BITMAP, eb);
1189}
1190
61d2ef2c
AK		 1191static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1192{
1193 unsigned i;
1194 struct msr_autoload *m = &vmx->msr_autoload;
1195
110312c8
AK		 1196 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1197 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1198 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1199 return;
1200 }
1201
61d2ef2c
AK		 1202 for (i = 0; i < m->nr; ++i)
1203 if (m->guest[i].index == msr)
1204 break;
1205
1206 if (i == m->nr)
1207 return;
1208 --m->nr;
1209 m->guest[i] = m->guest[m->nr];
1210 m->host[i] = m->host[m->nr];
1211 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1212 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1213}
1214
1215static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1216 u64 guest_val, u64 host_val)
1217{
1218 unsigned i;
1219 struct msr_autoload *m = &vmx->msr_autoload;
1220
110312c8
AK		 1221 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1222 vmcs_write64(GUEST_IA32_EFER, guest_val);
1223 vmcs_write64(HOST_IA32_EFER, host_val);
1224 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1225 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1226 return;
1227 }
1228
61d2ef2c
AK		 1229 for (i = 0; i < m->nr; ++i)
1230 if (m->guest[i].index == msr)
1231 break;
1232
1233 if (i == m->nr) {
1234 ++m->nr;
1235 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1236 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1237 }
1238
1239 m->guest[i].index = msr;
1240 m->guest[i].value = guest_val;
1241 m->host[i].index = msr;
1242 m->host[i].value = host_val;
1243}
1244
33ed6329
AK		 1245static void reload_tss(void)
1246{
33ed6329
AK		 1247 /*
1248 * VT restores TR but not its size. Useless.
1249 */
d359192f 1250 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1251 struct desc_struct *descs;
33ed6329 1252
d359192f 1253 descs = (void *)gdt->address;
33ed6329
AK		 1254 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1255 load_TR_desc();
33ed6329
AK		 1256}
1257
92c0d900 1258static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1259{
3a34a881 1260 u64 guest_efer;
51c6cf66
AK		 1261 u64 ignore_bits;
1262
f6801dff 1263 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1264
51c6cf66
AK		 1265 /*
1266 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1267 * outside long mode
1268 */
1269 ignore_bits = EFER_NX | EFER_SCE;
1270#ifdef CONFIG_X86_64
1271 ignore_bits |= EFER_LMA | EFER_LME;
1272 /* SCE is meaningful only in long mode on Intel */
1273 if (guest_efer & EFER_LMA)
1274 ignore_bits &= ~(u64)EFER_SCE;
1275#endif
51c6cf66
AK		 1276 guest_efer &= ~ignore_bits;
1277 guest_efer |= host_efer & ignore_bits;
26bb0981 1278 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1279 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1280
1281 clear_atomic_switch_msr(vmx, MSR_EFER);
1282 /* On ept, can't emulate nx, and must switch nx atomically */
1283 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1284 guest_efer = vmx->vcpu.arch.efer;
1285 if (!(guest_efer & EFER_LMA))
1286 guest_efer &= ~EFER_LME;
1287 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1288 return false;
1289 }
1290
26bb0981 1291 return true;
51c6cf66
AK		 1292}
1293
2d49ec72
GN		 1294static unsigned long segment_base(u16 selector)
1295{
d359192f 1296 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1297 struct desc_struct *d;
1298 unsigned long table_base;
1299 unsigned long v;
1300
1301 if (!(selector & ~3))
1302 return 0;
1303
d359192f 1304 table_base = gdt->address;
2d49ec72
GN		 1305
1306 if (selector & 4) { /* from ldt */
1307 u16 ldt_selector = kvm_read_ldt();
1308
1309 if (!(ldt_selector & ~3))
1310 return 0;
1311
1312 table_base = segment_base(ldt_selector);
1313 }
1314 d = (struct desc_struct *)(table_base + (selector & ~7));
1315 v = get_desc_base(d);
1316#ifdef CONFIG_X86_64
1317 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1318 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1319#endif
1320 return v;
1321}
1322
1323static inline unsigned long kvm_read_tr_base(void)
1324{
1325 u16 tr;
1326 asm("str %0" : "=g"(tr));
1327 return segment_base(tr);
1328}
1329
04d2cc77 1330static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1331{
04d2cc77 1332 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1333 int i;
04d2cc77 1334
a2fa3e9f 1335 if (vmx->host_state.loaded)
33ed6329
AK		 1336 return;
1337
a2fa3e9f 1338 vmx->host_state.loaded = 1;
33ed6329
AK		 1339 /*
1340 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1341 * allow segment selectors with cpl > 0 or ti == 1.
1342 */
d6e88aec 1343 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1344 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1345 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1346 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1347 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1348 vmx->host_state.fs_reload_needed = 0;
1349 } else {
33ed6329 1350 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1351 vmx->host_state.fs_reload_needed = 1;
33ed6329 1352 }
9581d442 1353 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1354 if (!(vmx->host_state.gs_sel & 7))
1355 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1356 else {
1357 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1358 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1359 }
1360
1361#ifdef CONFIG_X86_64
1362 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1363 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1364#else
a2fa3e9f
GH		 1365 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1366 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1367#endif
707c0874
AK		 1368
1369#ifdef CONFIG_X86_64
c8770e7b
AK		 1370 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1371 if (is_long_mode(&vmx->vcpu))
44ea2b17 1372 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1373#endif
26bb0981
AK		 1374 for (i = 0; i < vmx->save_nmsrs; ++i)
1375 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1376 vmx->guest_msrs[i].data,
1377 vmx->guest_msrs[i].mask);
33ed6329
AK		 1378}
1379
a9b21b62 1380static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1381{
a2fa3e9f 1382 if (!vmx->host_state.loaded)
33ed6329
AK		 1383 return;
1384
e1beb1d3 1385 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1386 vmx->host_state.loaded = 0;
c8770e7b
AK		 1387#ifdef CONFIG_X86_64
1388 if (is_long_mode(&vmx->vcpu))
1389 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1390#endif
152d3f2f 1391 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1392 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1393#ifdef CONFIG_X86_64
9581d442 1394 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1395#else
1396 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1397#endif
33ed6329 1398 }
0a77fe4c
AK		 1399 if (vmx->host_state.fs_reload_needed)
1400 loadsegment(fs, vmx->host_state.fs_sel);
152d3f2f 1401 reload_tss();
44ea2b17 1402#ifdef CONFIG_X86_64
c8770e7b 1403 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1404#endif
1c11e713
AK		 1405 if (current_thread_info()->status & TS_USEDFPU)
1406 clts();
3444d7da 1407 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1408}
1409
a9b21b62
AK		 1410static void vmx_load_host_state(struct vcpu_vmx *vmx)
1411{
1412 preempt_disable();
1413 __vmx_load_host_state(vmx);
1414 preempt_enable();
1415}
1416
6aa8b732
AK		 1417/*
1418 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1419 * vcpu mutex is already taken.
1420 */
15ad7146 1421static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1422{
a2fa3e9f 1423 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1424 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1425
4610c9cc
DX		 1426 if (!vmm_exclusive)
1427 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1428 else if (vmx->loaded_vmcs->cpu != cpu)
1429 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1430
d462b819
NHE		 1431 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1432 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1433 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1434 }
1435
d462b819 1436 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1437 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1438 unsigned long sysenter_esp;
1439
a8eeb04a 1440 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1441 local_irq_disable();
d462b819
NHE		 1442 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1443 &per_cpu(loaded_vmcss_on_cpu, cpu));
92fe13be
DX		 1444 local_irq_enable();
1445
6aa8b732
AK		 1446 /*
1447 * Linux uses per-cpu TSS and GDT, so set these when switching
1448 * processors.
1449 */
d6e88aec 1450 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1451 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1452
1453 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1454 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1455 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1456 }
6aa8b732
AK		 1457}
1458
1459static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1460{
a9b21b62 1461 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1462 if (!vmm_exclusive) {
d462b819
NHE		 1463 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1464 vcpu->cpu = -1;
4610c9cc
DX		 1465 kvm_cpu_vmxoff();
1466 }
6aa8b732
AK		 1467}
1468
5fd86fcf
AK		 1469static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1470{
81231c69
AK		 1471 ulong cr0;
1472
5fd86fcf
AK		 1473 if (vcpu->fpu_active)
1474 return;
1475 vcpu->fpu_active = 1;
81231c69
AK		 1476 cr0 = vmcs_readl(GUEST_CR0);
1477 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1478 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1479 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1480 update_exception_bitmap(vcpu);
edcafe3c 1481 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
36cf24e0
NHE		 1482 if (is_guest_mode(vcpu))
1483 vcpu->arch.cr0_guest_owned_bits &=
1484 ~get_vmcs12(vcpu)->cr0_guest_host_mask;
edcafe3c 1485 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1486}
1487
edcafe3c
AK		 1488static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1489
fe3ef05c
NHE		 1490/*
1491 * Return the cr0 value that a nested guest would read. This is a combination
1492 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1493 * its hypervisor (cr0_read_shadow).
1494 */
1495static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1496{
1497 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1498 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1499}
1500static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1501{
1502 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1503 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1504}
1505
5fd86fcf
AK		 1506static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1507{
36cf24e0
NHE		 1508 /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1509 * set this *before* calling this function.
1510 */
edcafe3c 1511 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1512 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1513 update_exception_bitmap(vcpu);
edcafe3c
AK		 1514 vcpu->arch.cr0_guest_owned_bits = 0;
1515 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
36cf24e0
NHE		 1516 if (is_guest_mode(vcpu)) {
1517 /*
1518 * L1's specified read shadow might not contain the TS bit,
1519 * so now that we turned on shadowing of this bit, we need to
1520 * set this bit of the shadow. Like in nested_vmx_run we need
1521 * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1522 * up-to-date here because we just decached cr0.TS (and we'll
1523 * only update vmcs12->guest_cr0 on nested exit).
1524 */
1525 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1526 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1527 (vcpu->arch.cr0 & X86_CR0_TS);
1528 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1529 } else
1530 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1531}
1532
6aa8b732
AK		 1533static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1534{
78ac8b47 1535 unsigned long rflags, save_rflags;
345dcaa8 1536
6de12732
AK		 1537 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1538 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1539 rflags = vmcs_readl(GUEST_RFLAGS);
1540 if (to_vmx(vcpu)->rmode.vm86_active) {
1541 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1542 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1543 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1544 }
1545 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1546 }
6de12732 1547 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1548}
1549
1550static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1551{
6de12732 1552 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
69c73028 1553 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6de12732 1554 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1555 if (to_vmx(vcpu)->rmode.vm86_active) {
1556 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1557 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1558 }
6aa8b732
AK		 1559 vmcs_writel(GUEST_RFLAGS, rflags);
1560}
1561
2809f5d2
GC		 1562static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1563{
1564 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1565 int ret = 0;
1566
1567 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1568 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1569 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1570 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1571
1572 return ret & mask;
1573}
1574
1575static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1576{
1577 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1578 u32 interruptibility = interruptibility_old;
1579
1580 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1581
48005f64 1582 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1583 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1584 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1585 interruptibility |= GUEST_INTR_STATE_STI;
1586
1587 if ((interruptibility != interruptibility_old))
1588 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1589}
1590
6aa8b732
AK		 1591static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1592{
1593 unsigned long rip;
6aa8b732 1594
5fdbf976 1595 rip = kvm_rip_read(vcpu);
6aa8b732 1596 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1597 kvm_rip_write(vcpu, rip);
6aa8b732 1598
2809f5d2
GC		 1599 /* skipping an emulated instruction also counts */
1600 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1601}
1602
443381a8
AL		 1603static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1604{
1605 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1606 * explicitly skip the instruction because if the HLT state is set, then
1607 * the instruction is already executing and RIP has already been
1608 * advanced. */
1609 if (!yield_on_hlt &&
1610 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1611 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1612}
1613
0b6ac343
NHE		 1614/*
1615 * KVM wants to inject page-faults which it got to the guest. This function
1616 * checks whether in a nested guest, we need to inject them to L1 or L2.
1617 * This function assumes it is called with the exit reason in vmcs02 being
1618 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1619 * is running).
1620 */
1621static int nested_pf_handled(struct kvm_vcpu *vcpu)
1622{
1623 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1624
1625 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1626 if (!(vmcs12->exception_bitmap & PF_VECTOR))
1627 return 0;
1628
1629 nested_vmx_vmexit(vcpu);
1630 return 1;
1631}
1632
298101da 1633static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1634 bool has_error_code, u32 error_code,
1635 bool reinject)
298101da 1636{
77ab6db0 1637 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1638 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1639
0b6ac343
NHE		 1640 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1641 nested_pf_handled(vcpu))
1642 return;
1643
8ab2d2e2 1644 if (has_error_code) {
77ab6db0 1645 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1646 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1647 }
77ab6db0 1648
7ffd92c5 1649 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1650 int inc_eip = 0;
1651 if (kvm_exception_is_soft(nr))
1652 inc_eip = vcpu->arch.event_exit_inst_len;
1653 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1654 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1655 return;
1656 }
1657
66fd3f7f
GN		 1658 if (kvm_exception_is_soft(nr)) {
1659 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1660 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1661 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1662 } else
1663 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1664
1665 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
443381a8 1666 vmx_clear_hlt(vcpu);
298101da
AK		 1667}
1668
4e47c7a6
SY		 1669static bool vmx_rdtscp_supported(void)
1670{
1671 return cpu_has_vmx_rdtscp();
1672}
1673
a75beee6
ED		 1674/*
1675 * Swap MSR entry in host/guest MSR entry array.
1676 */
8b9cf98c 1677static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1678{
26bb0981 1679 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1680
1681 tmp = vmx->guest_msrs[to];
1682 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1683 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1684}
1685
e38aea3e
AK		 1686/*
1687 * Set up the vmcs to automatically save and restore system
1688 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1689 * mode, as fiddling with msrs is very expensive.
1690 */
8b9cf98c 1691static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1692{
26bb0981 1693 int save_nmsrs, index;
5897297b 1694 unsigned long *msr_bitmap;
e38aea3e 1695
33f9c505 1696 vmx_load_host_state(vmx);
a75beee6
ED		 1697 save_nmsrs = 0;
1698#ifdef CONFIG_X86_64
8b9cf98c 1699 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1700 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1701 if (index >= 0)
8b9cf98c
RR		 1702 move_msr_up(vmx, index, save_nmsrs++);
1703 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1704 if (index >= 0)
8b9cf98c
RR		 1705 move_msr_up(vmx, index, save_nmsrs++);
1706 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1707 if (index >= 0)
8b9cf98c 1708 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1709 index = __find_msr_index(vmx, MSR_TSC_AUX);
1710 if (index >= 0 && vmx->rdtscp_enabled)
1711 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1712 /*
8c06585d 1713 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1714 * if efer.sce is enabled.
1715 */
8c06585d 1716 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1717 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1718 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1719 }
1720#endif
92c0d900
AK		 1721 index = __find_msr_index(vmx, MSR_EFER);
1722 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1723 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1724
26bb0981 1725 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1726
1727 if (cpu_has_vmx_msr_bitmap()) {
1728 if (is_long_mode(&vmx->vcpu))
1729 msr_bitmap = vmx_msr_bitmap_longmode;
1730 else
1731 msr_bitmap = vmx_msr_bitmap_legacy;
1732
1733 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1734 }
e38aea3e
AK		 1735}
1736
6aa8b732
AK		 1737/*
1738 * reads and returns guest's timestamp counter "register"
1739 * guest_tsc = host_tsc + tsc_offset -- 21.3
1740 */
1741static u64 guest_read_tsc(void)
1742{
1743 u64 host_tsc, tsc_offset;
1744
1745 rdtscll(host_tsc);
1746 tsc_offset = vmcs_read64(TSC_OFFSET);
1747 return host_tsc + tsc_offset;
1748}
1749
4051b188
JR		 1750/*
1751 * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1752 * ioctl. In this case the call-back should update internal vmx state to make
1753 * the changes effective.
1754 */
1755static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1756{
1757 /* Nothing to do here */
1758}
1759
6aa8b732 1760/*
99e3e30a 1761 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1762 */
99e3e30a 1763static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1764{
f4e1b3c8 1765 vmcs_write64(TSC_OFFSET, offset);
7991825b
NHE		 1766 if (is_guest_mode(vcpu))
1767 /*
1768 * We're here if L1 chose not to trap the TSC MSR. Since
1769 * prepare_vmcs12() does not copy tsc_offset, we need to also
1770 * set the vmcs12 field here.
1771 */
1772 get_vmcs12(vcpu)->tsc_offset = offset -
1773 to_vmx(vcpu)->nested.vmcs01_tsc_offset;
6aa8b732
AK		 1774}
1775
e48672fa
ZA		 1776static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1777{
1778 u64 offset = vmcs_read64(TSC_OFFSET);
1779 vmcs_write64(TSC_OFFSET, offset + adjustment);
7991825b
NHE		 1780 if (is_guest_mode(vcpu)) {
1781 /* Even when running L2, the adjustment needs to apply to L1 */
1782 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1783 }
e48672fa
ZA		 1784}
1785
857e4099
JR		 1786static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1787{
1788 return target_tsc - native_read_tsc();
1789}
1790
801d3424
NHE		 1791static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1792{
1793 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1794 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1795}
1796
1797/*
1798 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1799 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1800 * all guests if the "nested" module option is off, and can also be disabled
1801 * for a single guest by disabling its VMX cpuid bit.
1802 */
1803static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1804{
1805 return nested && guest_cpuid_has_vmx(vcpu);
1806}
1807
b87a51ae
NHE		 1808/*
1809 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1810 * returned for the various VMX controls MSRs when nested VMX is enabled.
1811 * The same values should also be used to verify that vmcs12 control fields are
1812 * valid during nested entry from L1 to L2.
1813 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1814 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1815 * bit in the high half is on if the corresponding bit in the control field
1816 * may be on. See also vmx_control_verify().
1817 * TODO: allow these variables to be modified (downgraded) by module options
1818 * or other means.
1819 */
1820static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1821static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1822static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1823static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1824static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1825static __init void nested_vmx_setup_ctls_msrs(void)
1826{
1827 /*
1828 * Note that as a general rule, the high half of the MSRs (bits in
1829 * the control fields which may be 1) should be initialized by the
1830 * intersection of the underlying hardware's MSR (i.e., features which
1831 * can be supported) and the list of features we want to expose -
1832 * because they are known to be properly supported in our code.
1833 * Also, usually, the low half of the MSRs (bits which must be 1) can
1834 * be set to 0, meaning that L1 may turn off any of these bits. The
1835 * reason is that if one of these bits is necessary, it will appear
1836 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1837 * fields of vmcs01 and vmcs02, will turn these bits off - and
1838 * nested_vmx_exit_handled() will not pass related exits to L1.
1839 * These rules have exceptions below.
1840 */
1841
1842 /* pin-based controls */
1843 /*
1844 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1845 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1846 */
1847 nested_vmx_pinbased_ctls_low = 0x16 ;
1848 nested_vmx_pinbased_ctls_high = 0x16 |
1849 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1850 PIN_BASED_VIRTUAL_NMIS;
1851
1852 /* exit controls */
1853 nested_vmx_exit_ctls_low = 0;
b6f1250e 1854 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 1855#ifdef CONFIG_X86_64
1856 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1857#else
1858 nested_vmx_exit_ctls_high = 0;
1859#endif
1860
1861 /* entry controls */
1862 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1863 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1864 nested_vmx_entry_ctls_low = 0;
1865 nested_vmx_entry_ctls_high &=
1866 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1867
1868 /* cpu-based controls */
1869 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1870 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1871 nested_vmx_procbased_ctls_low = 0;
1872 nested_vmx_procbased_ctls_high &=
1873 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1874 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1875 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1876 CPU_BASED_CR3_STORE_EXITING |
1877#ifdef CONFIG_X86_64
1878 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1879#endif
1880 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1881 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1882 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1883 /*
1884 * We can allow some features even when not supported by the
1885 * hardware. For example, L1 can specify an MSR bitmap - and we
1886 * can use it to avoid exits to L1 - even when L0 runs L2
1887 * without MSR bitmaps.
1888 */
1889 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1890
1891 /* secondary cpu-based controls */
1892 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1893 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1894 nested_vmx_secondary_ctls_low = 0;
1895 nested_vmx_secondary_ctls_high &=
1896 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1897}
1898
1899static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1900{
1901 /*
1902 * Bits 0 in high must be 0, and bits 1 in low must be 1.
1903 */
1904 return ((control & high) | low) == control;
1905}
1906
1907static inline u64 vmx_control_msr(u32 low, u32 high)
1908{
1909 return low | ((u64)high << 32);
1910}
1911
1912/*
1913 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1914 * also let it use VMX-specific MSRs.
1915 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1916 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1917 * like all other MSRs).
1918 */
1919static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1920{
1921 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
1922 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
1923 /*
1924 * According to the spec, processors which do not support VMX
1925 * should throw a #GP(0) when VMX capability MSRs are read.
1926 */
1927 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
1928 return 1;
1929 }
1930
1931 switch (msr_index) {
1932 case MSR_IA32_FEATURE_CONTROL:
1933 *pdata = 0;
1934 break;
1935 case MSR_IA32_VMX_BASIC:
1936 /*
1937 * This MSR reports some information about VMX support. We
1938 * should return information about the VMX we emulate for the
1939 * guest, and the VMCS structure we give it - not about the
1940 * VMX support of the underlying hardware.
1941 */
1942 *pdata = VMCS12_REVISION |
1943 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
1944 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
1945 break;
1946 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
1947 case MSR_IA32_VMX_PINBASED_CTLS:
1948 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
1949 nested_vmx_pinbased_ctls_high);
1950 break;
1951 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
1952 case MSR_IA32_VMX_PROCBASED_CTLS:
1953 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
1954 nested_vmx_procbased_ctls_high);
1955 break;
1956 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
1957 case MSR_IA32_VMX_EXIT_CTLS:
1958 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
1959 nested_vmx_exit_ctls_high);
1960 break;
1961 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
1962 case MSR_IA32_VMX_ENTRY_CTLS:
1963 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
1964 nested_vmx_entry_ctls_high);
1965 break;
1966 case MSR_IA32_VMX_MISC:
1967 *pdata = 0;
1968 break;
1969 /*
1970 * These MSRs specify bits which the guest must keep fixed (on or off)
1971 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
1972 * We picked the standard core2 setting.
1973 */
1974#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
1975#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
1976 case MSR_IA32_VMX_CR0_FIXED0:
1977 *pdata = VMXON_CR0_ALWAYSON;
1978 break;
1979 case MSR_IA32_VMX_CR0_FIXED1:
1980 *pdata = -1ULL;
1981 break;
1982 case MSR_IA32_VMX_CR4_FIXED0:
1983 *pdata = VMXON_CR4_ALWAYSON;
1984 break;
1985 case MSR_IA32_VMX_CR4_FIXED1:
1986 *pdata = -1ULL;
1987 break;
1988 case MSR_IA32_VMX_VMCS_ENUM:
1989 *pdata = 0x1f;
1990 break;
1991 case MSR_IA32_VMX_PROCBASED_CTLS2:
1992 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
1993 nested_vmx_secondary_ctls_high);
1994 break;
1995 case MSR_IA32_VMX_EPT_VPID_CAP:
1996 /* Currently, no nested ept or nested vpid */
1997 *pdata = 0;
1998 break;
1999 default:
2000 return 0;
2001 }
2002
2003 return 1;
2004}
2005
2006static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2007{
2008 if (!nested_vmx_allowed(vcpu))
2009 return 0;
2010
2011 if (msr_index == MSR_IA32_FEATURE_CONTROL)
2012 /* TODO: the right thing. */
2013 return 1;
2014 /*
2015 * No need to treat VMX capability MSRs specially: If we don't handle
2016 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2017 */
2018 return 0;
2019}
2020
6aa8b732
AK		 2021/*
2022 * Reads an msr value (of 'msr_index') into 'pdata'.
2023 * Returns 0 on success, non-0 otherwise.
2024 * Assumes vcpu_load() was already called.
2025 */
2026static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2027{
2028 u64 data;
26bb0981 2029 struct shared_msr_entry *msr;
6aa8b732
AK		 2030
2031 if (!pdata) {
2032 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2033 return -EINVAL;
2034 }
2035
2036 switch (msr_index) {
05b3e0c2 2037#ifdef CONFIG_X86_64
6aa8b732
AK		 2038 case MSR_FS_BASE:
2039 data = vmcs_readl(GUEST_FS_BASE);
2040 break;
2041 case MSR_GS_BASE:
2042 data = vmcs_readl(GUEST_GS_BASE);
2043 break;
44ea2b17
AK		 2044 case MSR_KERNEL_GS_BASE:
2045 vmx_load_host_state(to_vmx(vcpu));
2046 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2047 break;
26bb0981 2048#endif
6aa8b732 2049 case MSR_EFER:
3bab1f5d 2050 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2051 case MSR_IA32_TSC:
6aa8b732
AK		 2052 data = guest_read_tsc();
2053 break;
2054 case MSR_IA32_SYSENTER_CS:
2055 data = vmcs_read32(GUEST_SYSENTER_CS);
2056 break;
2057 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2058 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2059 break;
2060 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2061 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2062 break;
4e47c7a6
SY		 2063 case MSR_TSC_AUX:
2064 if (!to_vmx(vcpu)->rdtscp_enabled)
2065 return 1;
2066 /* Otherwise falls through */
6aa8b732 2067 default:
26bb0981 2068 vmx_load_host_state(to_vmx(vcpu));
b87a51ae
NHE		 2069 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2070 return 0;
8b9cf98c 2071 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 2072 if (msr) {
542423b0 2073 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 2074 data = msr->data;
2075 break;
6aa8b732 2076 }
3bab1f5d 2077 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2078 }
2079
2080 *pdata = data;
2081 return 0;
2082}
2083
2084/*
2085 * Writes msr value into into the appropriate "register".
2086 * Returns 0 on success, non-0 otherwise.
2087 * Assumes vcpu_load() was already called.
2088 */
2089static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2090{
a2fa3e9f 2091 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2092 struct shared_msr_entry *msr;
2cc51560
ED		 2093 int ret = 0;
2094
6aa8b732 2095 switch (msr_index) {
3bab1f5d 2096 case MSR_EFER:
a9b21b62 2097 vmx_load_host_state(vmx);
2cc51560 2098 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 2099 break;
16175a79 2100#ifdef CONFIG_X86_64
6aa8b732 2101 case MSR_FS_BASE:
2fb92db1 2102 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2103 vmcs_writel(GUEST_FS_BASE, data);
2104 break;
2105 case MSR_GS_BASE:
2fb92db1 2106 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2107 vmcs_writel(GUEST_GS_BASE, data);
2108 break;
44ea2b17
AK		 2109 case MSR_KERNEL_GS_BASE:
2110 vmx_load_host_state(vmx);
2111 vmx->msr_guest_kernel_gs_base = data;
2112 break;
6aa8b732
AK		 2113#endif
2114 case MSR_IA32_SYSENTER_CS:
2115 vmcs_write32(GUEST_SYSENTER_CS, data);
2116 break;
2117 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2118 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2119 break;
2120 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2121 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2122 break;
af24a4e4 2123 case MSR_IA32_TSC:
99e3e30a 2124 kvm_write_tsc(vcpu, data);
6aa8b732 2125 break;
468d472f
SY		 2126 case MSR_IA32_CR_PAT:
2127 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2128 vmcs_write64(GUEST_IA32_PAT, data);
2129 vcpu->arch.pat = data;
2130 break;
2131 }
4e47c7a6
SY		 2132 ret = kvm_set_msr_common(vcpu, msr_index, data);
2133 break;
2134 case MSR_TSC_AUX:
2135 if (!vmx->rdtscp_enabled)
2136 return 1;
2137 /* Check reserved bit, higher 32 bits should be zero */
2138 if ((data >> 32) != 0)
2139 return 1;
2140 /* Otherwise falls through */
6aa8b732 2141 default:
b87a51ae
NHE		 2142 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2143 break;
8b9cf98c 2144 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2145 if (msr) {
542423b0 2146 vmx_load_host_state(vmx);
3bab1f5d
AK		 2147 msr->data = data;
2148 break;
6aa8b732 2149 }
2cc51560 2150 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 2151 }
2152
2cc51560 2153 return ret;
6aa8b732
AK		 2154}
2155
5fdbf976 2156static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2157{
5fdbf976
MT		 2158 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2159 switch (reg) {
2160 case VCPU_REGS_RSP:
2161 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2162 break;
2163 case VCPU_REGS_RIP:
2164 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2165 break;
6de4f3ad
AK		 2166 case VCPU_EXREG_PDPTR:
2167 if (enable_ept)
2168 ept_save_pdptrs(vcpu);
2169 break;
5fdbf976
MT		 2170 default:
2171 break;
2172 }
6aa8b732
AK		 2173}
2174
355be0b9 2175static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 2176{
ae675ef0
JK		 2177 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2178 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2179 else
2180 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2181
abd3f2d6 2182 update_exception_bitmap(vcpu);
6aa8b732
AK		 2183}
2184
2185static __init int cpu_has_kvm_support(void)
2186{
6210e37b 2187 return cpu_has_vmx();
6aa8b732
AK		 2188}
2189
2190static __init int vmx_disabled_by_bios(void)
2191{
2192 u64 msr;
2193
2194 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2195 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2196 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2197 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2198 && tboot_enabled())
2199 return 1;
23f3e991 2200 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2201 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2202 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2203 && !tboot_enabled()) {
2204 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2205 "activate TXT before enabling KVM\n");
cafd6659 2206 return 1;
f9335afe 2207 }
23f3e991
JC		 2208 /* launched w/o TXT and VMX disabled */
2209 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2210 && !tboot_enabled())
2211 return 1;
cafd6659
SW		 2212 }
2213
2214 return 0;
6aa8b732
AK		 2215}
2216
7725b894
DX		 2217static void kvm_cpu_vmxon(u64 addr)
2218{
2219 asm volatile (ASM_VMX_VMXON_RAX
2220 : : "a"(&addr), "m"(addr)
2221 : "memory", "cc");
2222}
2223
10474ae8 2224static int hardware_enable(void *garbage)
6aa8b732
AK		 2225{
2226 int cpu = raw_smp_processor_id();
2227 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2228 u64 old, test_bits;
6aa8b732 2229
10474ae8
AG		 2230 if (read_cr4() & X86_CR4_VMXE)
2231 return -EBUSY;
2232
d462b819 2233 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
6aa8b732 2234 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2235
2236 test_bits = FEATURE_CONTROL_LOCKED;
2237 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2238 if (tboot_enabled())
2239 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2240
2241 if ((old & test_bits) != test_bits) {
6aa8b732 2242 /* enable and lock */
cafd6659
SW		 2243 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2244 }
66aee91a 2245 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2246
4610c9cc
DX		 2247 if (vmm_exclusive) {
2248 kvm_cpu_vmxon(phys_addr);
2249 ept_sync_global();
2250 }
10474ae8 2251
3444d7da
AK		 2252 store_gdt(&__get_cpu_var(host_gdt));
2253
10474ae8 2254 return 0;
6aa8b732
AK		 2255}
2256
d462b819 2257static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2258{
2259 int cpu = raw_smp_processor_id();
d462b819 2260 struct loaded_vmcs *v, *n;
543e4243 2261
d462b819
NHE		 2262 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2263 loaded_vmcss_on_cpu_link)
2264 __loaded_vmcs_clear(v);
543e4243
AK		 2265}
2266
710ff4a8
EH		 2267
2268/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2269 * tricks.
2270 */
2271static void kvm_cpu_vmxoff(void)
6aa8b732 2272{
4ecac3fd 2273 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2274}
2275
710ff4a8
EH		 2276static void hardware_disable(void *garbage)
2277{
4610c9cc 2278 if (vmm_exclusive) {
d462b819 2279 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2280 kvm_cpu_vmxoff();
2281 }
7725b894 2282 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2283}
2284
1c3d14fe 2285static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2286 u32 msr, u32 *result)
1c3d14fe
YS		 2287{
2288 u32 vmx_msr_low, vmx_msr_high;
2289 u32 ctl = ctl_min | ctl_opt;
2290
2291 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2292
2293 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2294 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2295
2296 /* Ensure minimum (required) set of control bits are supported. */
2297 if (ctl_min & ~ctl)
002c7f7c 2298 return -EIO;
1c3d14fe
YS		 2299
2300 *result = ctl;
2301 return 0;
2302}
2303
110312c8
AK		 2304static __init bool allow_1_setting(u32 msr, u32 ctl)
2305{
2306 u32 vmx_msr_low, vmx_msr_high;
2307
2308 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2309 return vmx_msr_high & ctl;
2310}
2311
002c7f7c 2312static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2313{
2314 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2315 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2316 u32 _pin_based_exec_control = 0;
2317 u32 _cpu_based_exec_control = 0;
f78e0e2e 2318 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2319 u32 _vmexit_control = 0;
2320 u32 _vmentry_control = 0;
2321
2322 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 2323 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 2324 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2325 &_pin_based_exec_control) < 0)
002c7f7c 2326 return -EIO;
1c3d14fe 2327
443381a8 2328 min =
1c3d14fe
YS		 2329#ifdef CONFIG_X86_64
2330 CPU_BASED_CR8_LOAD_EXITING |
2331 CPU_BASED_CR8_STORE_EXITING |
2332#endif
d56f546d
SY		 2333 CPU_BASED_CR3_LOAD_EXITING |
2334 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2335 CPU_BASED_USE_IO_BITMAPS |
2336 CPU_BASED_MOV_DR_EXITING |
a7052897 2337 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2338 CPU_BASED_MWAIT_EXITING |
2339 CPU_BASED_MONITOR_EXITING |
a7052897 2340 CPU_BASED_INVLPG_EXITING;
443381a8
AL		 2341
2342 if (yield_on_hlt)
2343 min |= CPU_BASED_HLT_EXITING;
2344
f78e0e2e 2345 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2346 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2347 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2348 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2349 &_cpu_based_exec_control) < 0)
002c7f7c 2350 return -EIO;
6e5d865c
YS		 2351#ifdef CONFIG_X86_64
2352 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2353 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2354 ~CPU_BASED_CR8_STORE_EXITING;
2355#endif
f78e0e2e 2356 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2357 min2 = 0;
2358 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 2359 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2360 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2361 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2362 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 2363 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2364 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 2365 if (adjust_vmx_controls(min2, opt2,
2366 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2367 &_cpu_based_2nd_exec_control) < 0)
2368 return -EIO;
2369 }
2370#ifndef CONFIG_X86_64
2371 if (!(_cpu_based_2nd_exec_control &
2372 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2373 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2374#endif
d56f546d 2375 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2376 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2377 enabled */
5fff7d27
GN		 2378 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2379 CPU_BASED_CR3_STORE_EXITING |
2380 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2381 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2382 vmx_capability.ept, vmx_capability.vpid);
2383 }
1c3d14fe
YS		 2384
2385 min = 0;
2386#ifdef CONFIG_X86_64
2387 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2388#endif
468d472f 2389 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 2390 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2391 &_vmexit_control) < 0)
002c7f7c 2392 return -EIO;
1c3d14fe 2393
468d472f
SY		 2394 min = 0;
2395 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2396 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2397 &_vmentry_control) < 0)
002c7f7c 2398 return -EIO;
6aa8b732 2399
c68876fd 2400 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2401
2402 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2403 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2404 return -EIO;
1c3d14fe
YS		 2405
2406#ifdef CONFIG_X86_64
2407 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2408 if (vmx_msr_high & (1u<<16))
002c7f7c 2409 return -EIO;
1c3d14fe
YS		 2410#endif
2411
2412 /* Require Write-Back (WB) memory type for VMCS accesses. */
2413 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2414 return -EIO;
1c3d14fe 2415
002c7f7c
YS		 2416 vmcs_conf->size = vmx_msr_high & 0x1fff;
2417 vmcs_conf->order = get_order(vmcs_config.size);
2418 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2419
002c7f7c
YS		 2420 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2421 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2422 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2423 vmcs_conf->vmexit_ctrl = _vmexit_control;
2424 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2425
110312c8
AK		 2426 cpu_has_load_ia32_efer =
2427 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2428 VM_ENTRY_LOAD_IA32_EFER)
2429 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2430 VM_EXIT_LOAD_IA32_EFER);
2431
1c3d14fe 2432 return 0;
c68876fd 2433}
6aa8b732
AK		 2434
2435static struct vmcs *alloc_vmcs_cpu(int cpu)
2436{
2437 int node = cpu_to_node(cpu);
2438 struct page *pages;
2439 struct vmcs *vmcs;
2440
6484eb3e 2441 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2442 if (!pages)
2443 return NULL;
2444 vmcs = page_address(pages);
1c3d14fe
YS		 2445 memset(vmcs, 0, vmcs_config.size);
2446 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2447 return vmcs;
2448}
2449
2450static struct vmcs *alloc_vmcs(void)
2451{
d3b2c338 2452 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2453}
2454
2455static void free_vmcs(struct vmcs *vmcs)
2456{
1c3d14fe 2457 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2458}
2459
d462b819
NHE		 2460/*
2461 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2462 */
2463static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2464{
2465 if (!loaded_vmcs->vmcs)
2466 return;
2467 loaded_vmcs_clear(loaded_vmcs);
2468 free_vmcs(loaded_vmcs->vmcs);
2469 loaded_vmcs->vmcs = NULL;
2470}
2471
39959588 2472static void free_kvm_area(void)
6aa8b732
AK		 2473{
2474 int cpu;
2475
3230bb47 2476 for_each_possible_cpu(cpu) {
6aa8b732 2477 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2478 per_cpu(vmxarea, cpu) = NULL;
2479 }
6aa8b732
AK		 2480}
2481
6aa8b732
AK		 2482static __init int alloc_kvm_area(void)
2483{
2484 int cpu;
2485
3230bb47 2486 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2487 struct vmcs *vmcs;
2488
2489 vmcs = alloc_vmcs_cpu(cpu);
2490 if (!vmcs) {
2491 free_kvm_area();
2492 return -ENOMEM;
2493 }
2494
2495 per_cpu(vmxarea, cpu) = vmcs;
2496 }
2497 return 0;
2498}
2499
2500static __init int hardware_setup(void)
2501{
002c7f7c
YS		 2502 if (setup_vmcs_config(&vmcs_config) < 0)
2503 return -EIO;
50a37eb4
JR		 2504
2505 if (boot_cpu_has(X86_FEATURE_NX))
2506 kvm_enable_efer_bits(EFER_NX);
2507
93ba03c2
SY		 2508 if (!cpu_has_vmx_vpid())
2509 enable_vpid = 0;
2510
4bc9b982
SY		 2511 if (!cpu_has_vmx_ept() ||
2512 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2513 enable_ept = 0;
3a624e29
NK		 2514 enable_unrestricted_guest = 0;
2515 }
2516
2517 if (!cpu_has_vmx_unrestricted_guest())
2518 enable_unrestricted_guest = 0;
93ba03c2
SY		 2519
2520 if (!cpu_has_vmx_flexpriority())
2521 flexpriority_enabled = 0;
2522
95ba8273
GN		 2523 if (!cpu_has_vmx_tpr_shadow())
2524 kvm_x86_ops->update_cr8_intercept = NULL;
2525
54dee993
MT		 2526 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2527 kvm_disable_largepages();
2528
4b8d54f9
ZE		 2529 if (!cpu_has_vmx_ple())
2530 ple_gap = 0;
2531
b87a51ae
NHE		 2532 if (nested)
2533 nested_vmx_setup_ctls_msrs();
2534
6aa8b732
AK		 2535 return alloc_kvm_area();
2536}
2537
2538static __exit void hardware_unsetup(void)
2539{
2540 free_kvm_area();
2541}
2542
6aa8b732
AK		 2543static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2544{
2545 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2546
6af11b9e 2547 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 2548 vmcs_write16(sf->selector, save->selector);
2549 vmcs_writel(sf->base, save->base);
2550 vmcs_write32(sf->limit, save->limit);
2551 vmcs_write32(sf->ar_bytes, save->ar);
2552 } else {
2553 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2554 << AR_DPL_SHIFT;
2555 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2556 }
2557}
2558
2559static void enter_pmode(struct kvm_vcpu *vcpu)
2560{
2561 unsigned long flags;
a89a8fb9 2562 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2563
a89a8fb9 2564 vmx->emulation_required = 1;
7ffd92c5 2565 vmx->rmode.vm86_active = 0;
6aa8b732 2566
2fb92db1
AK		 2567 vmx_segment_cache_clear(vmx);
2568
d0ba64f9 2569 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
7ffd92c5
AK		 2570 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2571 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2572 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 2573
2574 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2575 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2576 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2577 vmcs_writel(GUEST_RFLAGS, flags);
2578
66aee91a
RR		 2579 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2580 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2581
2582 update_exception_bitmap(vcpu);
2583
a89a8fb9
MG		 2584 if (emulate_invalid_guest_state)
2585 return;
2586
7ffd92c5
AK		 2587 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2588 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2589 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2590 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732 2591
2fb92db1
AK		 2592 vmx_segment_cache_clear(vmx);
2593
6aa8b732
AK		 2594 vmcs_write16(GUEST_SS_SELECTOR, 0);
2595 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2596
2597 vmcs_write16(GUEST_CS_SELECTOR,
2598 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2599 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2600}
2601
d77c26fc 2602static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 2603{
bfc6d222 2604 if (!kvm->arch.tss_addr) {
bc6678a3
MT		 2605 struct kvm_memslots *slots;
2606 gfn_t base_gfn;
2607
90d83dc3 2608 slots = kvm_memslots(kvm);
f495c6e5 2609 base_gfn = slots->memslots[0].base_gfn +
46a26bf5 2610 kvm->memslots->memslots[0].npages - 3;
cbc94022
IE		 2611 return base_gfn << PAGE_SHIFT;
2612 }
bfc6d222 2613 return kvm->arch.tss_addr;
6aa8b732
AK		 2614}
2615
2616static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2617{
2618 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2619
2620 save->selector = vmcs_read16(sf->selector);
2621 save->base = vmcs_readl(sf->base);
2622 save->limit = vmcs_read32(sf->limit);
2623 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32 2624 vmcs_write16(sf->selector, save->base >> 4);
444e863d 2625 vmcs_write32(sf->base, save->base & 0xffff0);
6aa8b732
AK		 2626 vmcs_write32(sf->limit, 0xffff);
2627 vmcs_write32(sf->ar_bytes, 0xf3);
444e863d
GN		 2628 if (save->base & 0xf)
2629 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2630 " aligned when entering protected mode (seg=%d)",
2631 seg);
6aa8b732
AK		 2632}
2633
2634static void enter_rmode(struct kvm_vcpu *vcpu)
2635{
2636 unsigned long flags;
a89a8fb9 2637 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2638
3a624e29
NK		 2639 if (enable_unrestricted_guest)
2640 return;
2641
a89a8fb9 2642 vmx->emulation_required = 1;
7ffd92c5 2643 vmx->rmode.vm86_active = 1;
6aa8b732 2644
776e58ea
GN		 2645 /*
2646 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2647 * vcpu. Call it here with phys address pointing 16M below 4G.
2648 */
2649 if (!vcpu->kvm->arch.tss_addr) {
2650 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2651 "called before entering vcpu\n");
2652 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2653 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2654 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2655 }
2656
2fb92db1
AK		 2657 vmx_segment_cache_clear(vmx);
2658
d0ba64f9 2659 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
7ffd92c5 2660 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 2661 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2662
7ffd92c5 2663 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 2664 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2665
7ffd92c5 2666 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 2667 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2668
2669 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2670 vmx->rmode.save_rflags = flags;
6aa8b732 2671
053de044 2672 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2673
2674 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2675 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2676 update_exception_bitmap(vcpu);
2677
a89a8fb9
MG		 2678 if (emulate_invalid_guest_state)
2679 goto continue_rmode;
2680
6aa8b732
AK		 2681 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2682 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2683 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2684
2685 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 2686 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 2687 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2688 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 2689 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2690
7ffd92c5
AK		 2691 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2692 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2693 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2694 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 2695
a89a8fb9 2696continue_rmode:
8668a3c4 2697 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2698}
2699
401d10de
AS		 2700static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2701{
2702 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2703 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2704
2705 if (!msr)
2706 return;
401d10de 2707
44ea2b17
AK		 2708 /*
2709 * Force kernel_gs_base reloading before EFER changes, as control
2710 * of this msr depends on is_long_mode().
2711 */
2712 vmx_load_host_state(to_vmx(vcpu));
f6801dff 2713 vcpu->arch.efer = efer;
401d10de
AS		 2714 if (efer & EFER_LMA) {
2715 vmcs_write32(VM_ENTRY_CONTROLS,
2716 vmcs_read32(VM_ENTRY_CONTROLS) |
2717 VM_ENTRY_IA32E_MODE);
2718 msr->data = efer;
2719 } else {
2720 vmcs_write32(VM_ENTRY_CONTROLS,
2721 vmcs_read32(VM_ENTRY_CONTROLS) &
2722 ~VM_ENTRY_IA32E_MODE);
2723
2724 msr->data = efer & ~EFER_LME;
2725 }
2726 setup_msrs(vmx);
2727}
2728
05b3e0c2 2729#ifdef CONFIG_X86_64
6aa8b732
AK		 2730
2731static void enter_lmode(struct kvm_vcpu *vcpu)
2732{
2733 u32 guest_tr_ar;
2734
2fb92db1
AK		 2735 vmx_segment_cache_clear(to_vmx(vcpu));
2736
6aa8b732
AK		 2737 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2738 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2739 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 2740 __func__);
6aa8b732
AK		 2741 vmcs_write32(GUEST_TR_AR_BYTES,
2742 (guest_tr_ar & ~AR_TYPE_MASK)
2743 | AR_TYPE_BUSY_64_TSS);
2744 }
da38f438 2745 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2746}
2747
2748static void exit_lmode(struct kvm_vcpu *vcpu)
2749{
6aa8b732
AK		 2750 vmcs_write32(VM_ENTRY_CONTROLS,
2751 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 2752 & ~VM_ENTRY_IA32E_MODE);
da38f438 2753 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2754}
2755
2756#endif
2757
2384d2b3
SY		 2758static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2759{
b9d762fa 2760 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 2761 if (enable_ept) {
2762 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2763 return;
4e1096d2 2764 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 2765 }
2384d2b3
SY		 2766}
2767
e8467fda
AK		 2768static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2769{
2770 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2771
2772 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2773 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2774}
2775
aff48baa
AK		 2776static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2777{
2778 if (enable_ept && is_paging(vcpu))
2779 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2780 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2781}
2782
25c4c276 2783static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 2784{
fc78f519
AK		 2785 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2786
2787 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2788 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 2789}
2790
1439442c
SY		 2791static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2792{
6de4f3ad
AK		 2793 if (!test_bit(VCPU_EXREG_PDPTR,
2794 (unsigned long *)&vcpu->arch.regs_dirty))
2795 return;
2796
1439442c 2797 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2798 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2799 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2800 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2801 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 2802 }
2803}
2804
8f5d549f
AK		 2805static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2806{
2807 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2808 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2809 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2810 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2811 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 2812 }
6de4f3ad
AK		 2813
2814 __set_bit(VCPU_EXREG_PDPTR,
2815 (unsigned long *)&vcpu->arch.regs_avail);
2816 __set_bit(VCPU_EXREG_PDPTR,
2817 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 2818}
2819
5e1746d6 2820static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 2821
2822static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2823 unsigned long cr0,
2824 struct kvm_vcpu *vcpu)
2825{
5233dd51
MT		 2826 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2827 vmx_decache_cr3(vcpu);
1439442c
SY		 2828 if (!(cr0 & X86_CR0_PG)) {
2829 /* From paging/starting to nonpaging */
2830 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2831 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 2832 (CPU_BASED_CR3_LOAD_EXITING |
2833 CPU_BASED_CR3_STORE_EXITING));
2834 vcpu->arch.cr0 = cr0;
fc78f519 2835 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 2836 } else if (!is_paging(vcpu)) {
2837 /* From nonpaging to paging */
2838 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2839 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 2840 ~(CPU_BASED_CR3_LOAD_EXITING |
2841 CPU_BASED_CR3_STORE_EXITING));
2842 vcpu->arch.cr0 = cr0;
fc78f519 2843 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 2844 }
95eb84a7
SY		 2845
2846 if (!(cr0 & X86_CR0_WP))
2847 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 2848}
2849
6aa8b732
AK		 2850static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2851{
7ffd92c5 2852 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 2853 unsigned long hw_cr0;
2854
2855 if (enable_unrestricted_guest)
2856 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2857 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2858 else
2859 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 2860
7ffd92c5 2861 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 2862 enter_pmode(vcpu);
2863
7ffd92c5 2864 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 2865 enter_rmode(vcpu);
2866
05b3e0c2 2867#ifdef CONFIG_X86_64
f6801dff 2868 if (vcpu->arch.efer & EFER_LME) {
707d92fa 2869 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 2870 enter_lmode(vcpu);
707d92fa 2871 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 2872 exit_lmode(vcpu);
2873 }
2874#endif
2875
089d034e 2876 if (enable_ept)
1439442c
SY		 2877 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2878
02daab21 2879 if (!vcpu->fpu_active)
81231c69 2880 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 2881
6aa8b732 2882 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 2883 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 2884 vcpu->arch.cr0 = cr0;
69c73028 2885 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 2886}
2887
1439442c
SY		 2888static u64 construct_eptp(unsigned long root_hpa)
2889{
2890 u64 eptp;
2891
2892 /* TODO write the value reading from MSR */
2893 eptp = VMX_EPT_DEFAULT_MT |
2894 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
2895 eptp |= (root_hpa & PAGE_MASK);
2896
2897 return eptp;
2898}
2899
6aa8b732
AK		 2900static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2901{
1439442c
SY		 2902 unsigned long guest_cr3;
2903 u64 eptp;
2904
2905 guest_cr3 = cr3;
089d034e 2906 if (enable_ept) {
1439442c
SY		 2907 eptp = construct_eptp(cr3);
2908 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 2909 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 2910 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 2911 ept_load_pdptrs(vcpu);
1439442c
SY		 2912 }
2913
2384d2b3 2914 vmx_flush_tlb(vcpu);
1439442c 2915 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 2916}
2917
5e1746d6 2918static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 2919{
7ffd92c5 2920 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 2921 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2922
5e1746d6
NHE		 2923 if (cr4 & X86_CR4_VMXE) {
2924 /*
2925 * To use VMXON (and later other VMX instructions), a guest
2926 * must first be able to turn on cr4.VMXE (see handle_vmon()).
2927 * So basically the check on whether to allow nested VMX
2928 * is here.
2929 */
2930 if (!nested_vmx_allowed(vcpu))
2931 return 1;
2932 } else if (to_vmx(vcpu)->nested.vmxon)
2933 return 1;
2934
ad312c7c 2935 vcpu->arch.cr4 = cr4;
bc23008b
AK		 2936 if (enable_ept) {
2937 if (!is_paging(vcpu)) {
2938 hw_cr4 &= ~X86_CR4_PAE;
2939 hw_cr4 |= X86_CR4_PSE;
2940 } else if (!(cr4 & X86_CR4_PAE)) {
2941 hw_cr4 &= ~X86_CR4_PAE;
2942 }
2943 }
1439442c
SY		 2944
2945 vmcs_writel(CR4_READ_SHADOW, cr4);
2946 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 2947 return 0;
6aa8b732
AK		 2948}
2949
6aa8b732
AK		 2950static void vmx_get_segment(struct kvm_vcpu *vcpu,
2951 struct kvm_segment *var, int seg)
2952{
a9179499 2953 struct vcpu_vmx *vmx = to_vmx(vcpu);
a9179499 2954 struct kvm_save_segment *save;
6aa8b732
AK		 2955 u32 ar;
2956
a9179499
AK		 2957 if (vmx->rmode.vm86_active
2958 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
2959 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
2960 || seg == VCPU_SREG_GS)
2961 && !emulate_invalid_guest_state) {
2962 switch (seg) {
2963 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
2964 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
2965 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
2966 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
2967 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
2968 default: BUG();
2969 }
2970 var->selector = save->selector;
2971 var->base = save->base;
2972 var->limit = save->limit;
2973 ar = save->ar;
2974 if (seg == VCPU_SREG_TR
2fb92db1 2975 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
a9179499
AK		 2976 goto use_saved_rmode_seg;
2977 }
2fb92db1
AK		 2978 var->base = vmx_read_guest_seg_base(vmx, seg);
2979 var->limit = vmx_read_guest_seg_limit(vmx, seg);
2980 var->selector = vmx_read_guest_seg_selector(vmx, seg);
2981 ar = vmx_read_guest_seg_ar(vmx, seg);
a9179499 2982use_saved_rmode_seg:
9fd4a3b7 2983 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 2984 ar = 0;
2985 var->type = ar & 15;
2986 var->s = (ar >> 4) & 1;
2987 var->dpl = (ar >> 5) & 3;
2988 var->present = (ar >> 7) & 1;
2989 var->avl = (ar >> 12) & 1;
2990 var->l = (ar >> 13) & 1;
2991 var->db = (ar >> 14) & 1;
2992 var->g = (ar >> 15) & 1;
2993 var->unusable = (ar >> 16) & 1;
2994}
2995
a9179499
AK		 2996static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2997{
a9179499
AK		 2998 struct kvm_segment s;
2999
3000 if (to_vmx(vcpu)->rmode.vm86_active) {
3001 vmx_get_segment(vcpu, &s, seg);
3002 return s.base;
3003 }
2fb92db1 3004 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 3005}
3006
69c73028 3007static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 3008{
3eeb3288 3009 if (!is_protmode(vcpu))
2e4d2653
IE		 3010 return 0;
3011
f4c63e5d
AK		 3012 if (!is_long_mode(vcpu)
3013 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 3014 return 3;
3015
2fb92db1 3016 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2e4d2653
IE		 3017}
3018
69c73028
AK		 3019static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3020{
3021 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3022 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3023 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
3024 }
3025 return to_vmx(vcpu)->cpl;
3026}
3027
3028
653e3108 3029static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 3030{
6aa8b732
AK		 3031 u32 ar;
3032
653e3108 3033 if (var->unusable)
6aa8b732
AK		 3034 ar = 1 << 16;
3035 else {
3036 ar = var->type & 15;
3037 ar |= (var->s & 1) << 4;
3038 ar |= (var->dpl & 3) << 5;
3039 ar |= (var->present & 1) << 7;
3040 ar |= (var->avl & 1) << 12;
3041 ar |= (var->l & 1) << 13;
3042 ar |= (var->db & 1) << 14;
3043 ar |= (var->g & 1) << 15;
3044 }
f7fbf1fd
UL		 3045 if (ar == 0) /* a 0 value means unusable */
3046 ar = AR_UNUSABLE_MASK;
653e3108
AK		 3047
3048 return ar;
3049}
3050
3051static void vmx_set_segment(struct kvm_vcpu *vcpu,
3052 struct kvm_segment *var, int seg)
3053{
7ffd92c5 3054 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 3055 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3056 u32 ar;
3057
2fb92db1
AK		 3058 vmx_segment_cache_clear(vmx);
3059
7ffd92c5 3060 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
a8ba6c26 3061 vmcs_write16(sf->selector, var->selector);
7ffd92c5
AK		 3062 vmx->rmode.tr.selector = var->selector;
3063 vmx->rmode.tr.base = var->base;
3064 vmx->rmode.tr.limit = var->limit;
3065 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 3066 return;
3067 }
3068 vmcs_writel(sf->base, var->base);
3069 vmcs_write32(sf->limit, var->limit);
3070 vmcs_write16(sf->selector, var->selector);
7ffd92c5 3071 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 3072 /*
3073 * Hack real-mode segments into vm86 compatibility.
3074 */
3075 if (var->base == 0xffff0000 && var->selector == 0xf000)
3076 vmcs_writel(sf->base, 0xf0000);
3077 ar = 0xf3;
3078 } else
3079 ar = vmx_segment_access_rights(var);
3a624e29
NK		 3080
3081 /*
3082 * Fix the "Accessed" bit in AR field of segment registers for older
3083 * qemu binaries.
3084 * IA32 arch specifies that at the time of processor reset the
3085 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3086 * is setting it to 0 in the usedland code. This causes invalid guest
3087 * state vmexit when "unrestricted guest" mode is turned on.
3088 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3089 * tree. Newer qemu binaries with that qemu fix would not need this
3090 * kvm hack.
3091 */
3092 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3093 ar |= 0x1; /* Accessed */
3094
6aa8b732 3095 vmcs_write32(sf->ar_bytes, ar);
69c73028 3096 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 3097}
3098
6aa8b732
AK		 3099static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3100{
2fb92db1 3101 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3102
3103 *db = (ar >> 14) & 1;
3104 *l = (ar >> 13) & 1;
3105}
3106
89a27f4d 3107static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3108{
89a27f4d
GN		 3109 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3110 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3111}
3112
89a27f4d 3113static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3114{
89a27f4d
GN		 3115 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3116 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3117}
3118
89a27f4d 3119static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3120{
89a27f4d
GN		 3121 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3122 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3123}
3124
89a27f4d 3125static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3126{
89a27f4d
GN		 3127 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3128 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3129}
3130
648dfaa7
MG		 3131static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3132{
3133 struct kvm_segment var;
3134 u32 ar;
3135
3136 vmx_get_segment(vcpu, &var, seg);
3137 ar = vmx_segment_access_rights(&var);
3138
3139 if (var.base != (var.selector << 4))
3140 return false;
3141 if (var.limit != 0xffff)
3142 return false;
3143 if (ar != 0xf3)
3144 return false;
3145
3146 return true;
3147}
3148
3149static bool code_segment_valid(struct kvm_vcpu *vcpu)
3150{
3151 struct kvm_segment cs;
3152 unsigned int cs_rpl;
3153
3154 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3155 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3156
1872a3f4
AK		 3157 if (cs.unusable)
3158 return false;
648dfaa7
MG		 3159 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3160 return false;
3161 if (!cs.s)
3162 return false;
1872a3f4 3163 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3164 if (cs.dpl > cs_rpl)
3165 return false;
1872a3f4 3166 } else {
648dfaa7
MG		 3167 if (cs.dpl != cs_rpl)
3168 return false;
3169 }
3170 if (!cs.present)
3171 return false;
3172
3173 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3174 return true;
3175}
3176
3177static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3178{
3179 struct kvm_segment ss;
3180 unsigned int ss_rpl;
3181
3182 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3183 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3184
1872a3f4
AK		 3185 if (ss.unusable)
3186 return true;
3187 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3188 return false;
3189 if (!ss.s)
3190 return false;
3191 if (ss.dpl != ss_rpl) /* DPL != RPL */
3192 return false;
3193 if (!ss.present)
3194 return false;
3195
3196 return true;
3197}
3198
3199static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3200{
3201 struct kvm_segment var;
3202 unsigned int rpl;
3203
3204 vmx_get_segment(vcpu, &var, seg);
3205 rpl = var.selector & SELECTOR_RPL_MASK;
3206
1872a3f4
AK		 3207 if (var.unusable)
3208 return true;
648dfaa7
MG		 3209 if (!var.s)
3210 return false;
3211 if (!var.present)
3212 return false;
3213 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3214 if (var.dpl < rpl) /* DPL < RPL */
3215 return false;
3216 }
3217
3218 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3219 * rights flags
3220 */
3221 return true;
3222}
3223
3224static bool tr_valid(struct kvm_vcpu *vcpu)
3225{
3226 struct kvm_segment tr;
3227
3228 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3229
1872a3f4
AK		 3230 if (tr.unusable)
3231 return false;
648dfaa7
MG		 3232 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3233 return false;
1872a3f4 3234 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3235 return false;
3236 if (!tr.present)
3237 return false;
3238
3239 return true;
3240}
3241
3242static bool ldtr_valid(struct kvm_vcpu *vcpu)
3243{
3244 struct kvm_segment ldtr;
3245
3246 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3247
1872a3f4
AK		 3248 if (ldtr.unusable)
3249 return true;
648dfaa7
MG		 3250 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3251 return false;
3252 if (ldtr.type != 2)
3253 return false;
3254 if (!ldtr.present)
3255 return false;
3256
3257 return true;
3258}
3259
3260static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3261{
3262 struct kvm_segment cs, ss;
3263
3264 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3265 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3266
3267 return ((cs.selector & SELECTOR_RPL_MASK) ==
3268 (ss.selector & SELECTOR_RPL_MASK));
3269}
3270
3271/*
3272 * Check if guest state is valid. Returns true if valid, false if
3273 * not.
3274 * We assume that registers are always usable
3275 */
3276static bool guest_state_valid(struct kvm_vcpu *vcpu)
3277{
3278 /* real mode guest state checks */
3eeb3288 3279 if (!is_protmode(vcpu)) {
648dfaa7
MG		 3280 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3281 return false;
3282 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3283 return false;
3284 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3285 return false;
3286 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3287 return false;
3288 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3289 return false;
3290 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3291 return false;
3292 } else {
3293 /* protected mode guest state checks */
3294 if (!cs_ss_rpl_check(vcpu))
3295 return false;
3296 if (!code_segment_valid(vcpu))
3297 return false;
3298 if (!stack_segment_valid(vcpu))
3299 return false;
3300 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3301 return false;
3302 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3303 return false;
3304 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3305 return false;
3306 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3307 return false;
3308 if (!tr_valid(vcpu))
3309 return false;
3310 if (!ldtr_valid(vcpu))
3311 return false;
3312 }
3313 /* TODO:
3314 * - Add checks on RIP
3315 * - Add checks on RFLAGS
3316 */
3317
3318 return true;
3319}
3320
d77c26fc 3321static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3322{
40dcaa9f 3323 gfn_t fn;
195aefde 3324 u16 data = 0;
40dcaa9f 3325 int r, idx, ret = 0;
6aa8b732 3326
40dcaa9f
XG		 3327 idx = srcu_read_lock(&kvm->srcu);
3328 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE		 3329 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3330 if (r < 0)
10589a46 3331 goto out;
195aefde 3332 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3333 r = kvm_write_guest_page(kvm, fn++, &data,
3334 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3335 if (r < 0)
10589a46 3336 goto out;
195aefde
IE		 3337 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3338 if (r < 0)
10589a46 3339 goto out;
195aefde
IE		 3340 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3341 if (r < 0)
10589a46 3342 goto out;
195aefde 3343 data = ~0;
10589a46
MT		 3344 r = kvm_write_guest_page(kvm, fn, &data,
3345 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3346 sizeof(u8));
195aefde 3347 if (r < 0)
10589a46
MT		 3348 goto out;
3349
3350 ret = 1;
3351out:
40dcaa9f 3352 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3353 return ret;
6aa8b732
AK		 3354}
3355
b7ebfb05
SY		 3356static int init_rmode_identity_map(struct kvm *kvm)
3357{
40dcaa9f 3358 int i, idx, r, ret;
b7ebfb05
SY		 3359 pfn_t identity_map_pfn;
3360 u32 tmp;
3361
089d034e 3362 if (!enable_ept)
b7ebfb05
SY		 3363 return 1;
3364 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3365 printk(KERN_ERR "EPT: identity-mapping pagetable "
3366 "haven't been allocated!\n");
3367 return 0;
3368 }
3369 if (likely(kvm->arch.ept_identity_pagetable_done))
3370 return 1;
3371 ret = 0;
b927a3ce 3372 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3373 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3374 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3375 if (r < 0)
3376 goto out;
3377 /* Set up identity-mapping pagetable for EPT in real mode */
3378 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3379 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3380 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3381 r = kvm_write_guest_page(kvm, identity_map_pfn,
3382 &tmp, i * sizeof(tmp), sizeof(tmp));
3383 if (r < 0)
3384 goto out;
3385 }
3386 kvm->arch.ept_identity_pagetable_done = true;
3387 ret = 1;
3388out:
40dcaa9f 3389 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3390 return ret;
3391}
3392
6aa8b732
AK		 3393static void seg_setup(int seg)
3394{
3395 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3396 unsigned int ar;
6aa8b732
AK		 3397
3398 vmcs_write16(sf->selector, 0);
3399 vmcs_writel(sf->base, 0);
3400 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 3401 if (enable_unrestricted_guest) {
3402 ar = 0x93;
3403 if (seg == VCPU_SREG_CS)
3404 ar |= 0x08; /* code segment */
3405 } else
3406 ar = 0xf3;
3407
3408 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3409}
3410
f78e0e2e
SY		 3411static int alloc_apic_access_page(struct kvm *kvm)
3412{
3413 struct kvm_userspace_memory_region kvm_userspace_mem;
3414 int r = 0;
3415
79fac95e 3416 mutex_lock(&kvm->slots_lock);
bfc6d222 3417 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3418 goto out;
3419 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3420 kvm_userspace_mem.flags = 0;
3421 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3422 kvm_userspace_mem.memory_size = PAGE_SIZE;
3423 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3424 if (r)
3425 goto out;
72dc67a6 3426
bfc6d222 3427 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 3428out:
79fac95e 3429 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3430 return r;
3431}
3432
b7ebfb05
SY		 3433static int alloc_identity_pagetable(struct kvm *kvm)
3434{
3435 struct kvm_userspace_memory_region kvm_userspace_mem;
3436 int r = 0;
3437
79fac95e 3438 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3439 if (kvm->arch.ept_identity_pagetable)
3440 goto out;
3441 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3442 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3443 kvm_userspace_mem.guest_phys_addr =
3444 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 3445 kvm_userspace_mem.memory_size = PAGE_SIZE;
3446 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3447 if (r)
3448 goto out;
3449
b7ebfb05 3450 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 3451 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 3452out:
79fac95e 3453 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3454 return r;
3455}
3456
2384d2b3
SY		 3457static void allocate_vpid(struct vcpu_vmx *vmx)
3458{
3459 int vpid;
3460
3461 vmx->vpid = 0;
919818ab 3462 if (!enable_vpid)
2384d2b3
SY		 3463 return;
3464 spin_lock(&vmx_vpid_lock);
3465 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3466 if (vpid < VMX_NR_VPIDS) {
3467 vmx->vpid = vpid;
3468 __set_bit(vpid, vmx_vpid_bitmap);
3469 }
3470 spin_unlock(&vmx_vpid_lock);
3471}
3472
cdbecfc3
LJ		 3473static void free_vpid(struct vcpu_vmx *vmx)
3474{
3475 if (!enable_vpid)
3476 return;
3477 spin_lock(&vmx_vpid_lock);
3478 if (vmx->vpid != 0)
3479 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3480 spin_unlock(&vmx_vpid_lock);
3481}
3482
5897297b 3483static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 3484{
3e7c73e9 3485 int f = sizeof(unsigned long);
25c5f225
SY		 3486
3487 if (!cpu_has_vmx_msr_bitmap())
3488 return;
3489
3490 /*
3491 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3492 * have the write-low and read-high bitmap offsets the wrong way round.
3493 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3494 */
25c5f225 3495 if (msr <= 0x1fff) {
3e7c73e9
AK		 3496 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3497 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 3498 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3499 msr &= 0x1fff;
3e7c73e9
AK		 3500 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3501 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 3502 }
25c5f225
SY		 3503}
3504
5897297b
AK		 3505static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3506{
3507 if (!longmode_only)
3508 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3509 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3510}
3511
a3a8ff8e
NHE		 3512/*
3513 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3514 * will not change in the lifetime of the guest.
3515 * Note that host-state that does change is set elsewhere. E.g., host-state
3516 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3517 */
3518static void vmx_set_constant_host_state(void)
3519{
3520 u32 low32, high32;
3521 unsigned long tmpl;
3522 struct desc_ptr dt;
3523
3524 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
3525 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3526 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3527
3528 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3529 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3530 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3531 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3532 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3533
3534 native_store_idt(&dt);
3535 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3536
3537 asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3538 vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3539
3540 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3541 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3542 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3543 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3544
3545 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3546 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3547 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3548 }
3549}
3550
bf8179a0
NHE		 3551static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3552{
3553 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3554 if (enable_ept)
3555 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3556 if (is_guest_mode(&vmx->vcpu))
3557 vmx->vcpu.arch.cr4_guest_owned_bits &=
3558 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3559 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3560}
3561
3562static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3563{
3564 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3565 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3566 exec_control &= ~CPU_BASED_TPR_SHADOW;
3567#ifdef CONFIG_X86_64
3568 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3569 CPU_BASED_CR8_LOAD_EXITING;
3570#endif
3571 }
3572 if (!enable_ept)
3573 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3574 CPU_BASED_CR3_LOAD_EXITING |
3575 CPU_BASED_INVLPG_EXITING;
3576 return exec_control;
3577}
3578
3579static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3580{
3581 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3582 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3583 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3584 if (vmx->vpid == 0)
3585 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3586 if (!enable_ept) {
3587 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3588 enable_unrestricted_guest = 0;
3589 }
3590 if (!enable_unrestricted_guest)
3591 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3592 if (!ple_gap)
3593 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3594 return exec_control;
3595}
3596
ce88decf
XG		 3597static void ept_set_mmio_spte_mask(void)
3598{
3599 /*
3600 * EPT Misconfigurations can be generated if the value of bits 2:0
3601 * of an EPT paging-structure entry is 110b (write/execute).
3602 * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3603 * spte.
3604 */
3605 kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3606}
3607
6aa8b732
AK		 3608/*
3609 * Sets up the vmcs for emulated real mode.
3610 */
8b9cf98c 3611static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 3612{
2e4ce7f5 3613#ifdef CONFIG_X86_64
6aa8b732 3614 unsigned long a;
2e4ce7f5 3615#endif
6aa8b732 3616 int i;
6aa8b732 3617
6aa8b732 3618 /* I/O */
3e7c73e9
AK		 3619 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3620 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 3621
25c5f225 3622 if (cpu_has_vmx_msr_bitmap())
5897297b 3623 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 3624
6aa8b732
AK		 3625 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3626
6aa8b732 3627 /* Control */
1c3d14fe
YS		 3628 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3629 vmcs_config.pin_based_exec_ctrl);
6e5d865c 3630
bf8179a0 3631 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 3632
83ff3b9d 3633 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 3634 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3635 vmx_secondary_exec_control(vmx));
83ff3b9d 3636 }
f78e0e2e 3637
4b8d54f9
ZE		 3638 if (ple_gap) {
3639 vmcs_write32(PLE_GAP, ple_gap);
3640 vmcs_write32(PLE_WINDOW, ple_window);
3641 }
3642
c3707958
XG		 3643 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3644 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 3645 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3646
9581d442
AK		 3647 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3648 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a3a8ff8e 3649 vmx_set_constant_host_state();
05b3e0c2 3650#ifdef CONFIG_X86_64
6aa8b732
AK		 3651 rdmsrl(MSR_FS_BASE, a);
3652 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3653 rdmsrl(MSR_GS_BASE, a);
3654 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3655#else
3656 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3657 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3658#endif
3659
2cc51560
ED		 3660 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3661 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 3662 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 3663 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 3664 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 3665
468d472f 3666 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 3667 u32 msr_low, msr_high;
3668 u64 host_pat;
468d472f
SY		 3669 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3670 host_pat = msr_low | ((u64) msr_high << 32);
3671 /* Write the default value follow host pat */
3672 vmcs_write64(GUEST_IA32_PAT, host_pat);
3673 /* Keep arch.pat sync with GUEST_IA32_PAT */
3674 vmx->vcpu.arch.pat = host_pat;
3675 }
3676
6aa8b732
AK		 3677 for (i = 0; i < NR_VMX_MSR; ++i) {
3678 u32 index = vmx_msr_index[i];
3679 u32 data_low, data_high;
a2fa3e9f 3680 int j = vmx->nmsrs;
6aa8b732
AK		 3681
3682 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3683 continue;
432bd6cb
AK		 3684 if (wrmsr_safe(index, data_low, data_high) < 0)
3685 continue;
26bb0981
AK		 3686 vmx->guest_msrs[j].index = i;
3687 vmx->guest_msrs[j].data = 0;
d5696725 3688 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 3689 ++vmx->nmsrs;
6aa8b732 3690 }
6aa8b732 3691
1c3d14fe 3692 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 3693
3694 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 3695 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3696
e00c8cf2 3697 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 3698 set_cr4_guest_host_mask(vmx);
e00c8cf2 3699
99e3e30a 3700 kvm_write_tsc(&vmx->vcpu, 0);
f78e0e2e 3701
e00c8cf2
AK		 3702 return 0;
3703}
3704
3705static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3706{
3707 struct vcpu_vmx *vmx = to_vmx(vcpu);
3708 u64 msr;
4b9d3a04 3709 int ret;
e00c8cf2 3710
5fdbf976 3711 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
e00c8cf2 3712
7ffd92c5 3713 vmx->rmode.vm86_active = 0;
e00c8cf2 3714
3b86cd99
JK		 3715 vmx->soft_vnmi_blocked = 0;
3716
ad312c7c 3717 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 3718 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 3719 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 3720 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 3721 msr |= MSR_IA32_APICBASE_BSP;
3722 kvm_set_apic_base(&vmx->vcpu, msr);
3723
10ab25cd
JK		 3724 ret = fx_init(&vmx->vcpu);
3725 if (ret != 0)
3726 goto out;
e00c8cf2 3727
2fb92db1
AK		 3728 vmx_segment_cache_clear(vmx);
3729
5706be0d 3730 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 3731 /*
3732 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3733 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3734 */
c5af89b6 3735 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 3736 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3737 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3738 } else {
ad312c7c
ZX		 3739 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3740 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 3741 }
e00c8cf2
AK		 3742
3743 seg_setup(VCPU_SREG_DS);
3744 seg_setup(VCPU_SREG_ES);
3745 seg_setup(VCPU_SREG_FS);
3746 seg_setup(VCPU_SREG_GS);
3747 seg_setup(VCPU_SREG_SS);
3748
3749 vmcs_write16(GUEST_TR_SELECTOR, 0);
3750 vmcs_writel(GUEST_TR_BASE, 0);
3751 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3752 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3753
3754 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3755 vmcs_writel(GUEST_LDTR_BASE, 0);
3756 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3757 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3758
3759 vmcs_write32(GUEST_SYSENTER_CS, 0);
3760 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3761 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3762
3763 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 3764 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 3765 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 3766 else
5fdbf976
MT		 3767 kvm_rip_write(vcpu, 0);
3768 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 3769
e00c8cf2
AK		 3770 vmcs_writel(GUEST_DR7, 0x400);
3771
3772 vmcs_writel(GUEST_GDTR_BASE, 0);
3773 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3774
3775 vmcs_writel(GUEST_IDTR_BASE, 0);
3776 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3777
443381a8 3778 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 3779 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3780 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3781
e00c8cf2
AK		 3782 /* Special registers */
3783 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3784
3785 setup_msrs(vmx);
3786
6aa8b732
AK		 3787 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
3788
f78e0e2e
SY		 3789 if (cpu_has_vmx_tpr_shadow()) {
3790 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3791 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3792 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 3793 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 3794 vmcs_write32(TPR_THRESHOLD, 0);
3795 }
3796
3797 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3798 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 3799 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 3800
2384d2b3
SY		 3801 if (vmx->vpid != 0)
3802 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3803
fa40052c 3804 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 3805 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 3806 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 3807 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 3808 vmx_fpu_activate(&vmx->vcpu);
3809 update_exception_bitmap(&vmx->vcpu);
6aa8b732 3810
b9d762fa 3811 vpid_sync_context(vmx);
2384d2b3 3812
3200f405 3813 ret = 0;
6aa8b732 3814
a89a8fb9
MG		 3815 /* HACK: Don't enable emulation on guest boot/reset */
3816 vmx->emulation_required = 0;
3817
6aa8b732
AK		 3818out:
3819 return ret;
3820}
3821
b6f1250e
NHE		 3822/*
3823 * In nested virtualization, check if L1 asked to exit on external interrupts.
3824 * For most existing hypervisors, this will always return true.
3825 */
3826static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
3827{
3828 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
3829 PIN_BASED_EXT_INTR_MASK;
3830}
3831
3b86cd99
JK		 3832static void enable_irq_window(struct kvm_vcpu *vcpu)
3833{
3834 u32 cpu_based_vm_exec_control;
b6f1250e
NHE		 3835 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
3836 /* We can get here when nested_run_pending caused
3837 * vmx_interrupt_allowed() to return false. In this case, do
3838 * nothing - the interrupt will be injected later.
3839 */
3840 return;
3b86cd99
JK		 3841
3842 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3843 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3844 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3845}
3846
3847static void enable_nmi_window(struct kvm_vcpu *vcpu)
3848{
3849 u32 cpu_based_vm_exec_control;
3850
3851 if (!cpu_has_virtual_nmis()) {
3852 enable_irq_window(vcpu);
3853 return;
3854 }
3855
30bd0c4c
AK		 3856 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3857 enable_irq_window(vcpu);
3858 return;
3859 }
3b86cd99
JK		 3860 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3861 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3862 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3863}
3864
66fd3f7f 3865static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 3866{
9c8cba37 3867 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 3868 uint32_t intr;
3869 int irq = vcpu->arch.interrupt.nr;
9c8cba37 3870
229456fc 3871 trace_kvm_inj_virq(irq);
2714d1d3 3872
fa89a817 3873 ++vcpu->stat.irq_injections;
7ffd92c5 3874 if (vmx->rmode.vm86_active) {
71f9833b
SH		 3875 int inc_eip = 0;
3876 if (vcpu->arch.interrupt.soft)
3877 inc_eip = vcpu->arch.event_exit_inst_len;
3878 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 3879 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 3880 return;
3881 }
66fd3f7f
GN		 3882 intr = irq | INTR_INFO_VALID_MASK;
3883 if (vcpu->arch.interrupt.soft) {
3884 intr |= INTR_TYPE_SOFT_INTR;
3885 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3886 vmx->vcpu.arch.event_exit_inst_len);
3887 } else
3888 intr |= INTR_TYPE_EXT_INTR;
3889 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
443381a8 3890 vmx_clear_hlt(vcpu);
85f455f7
ED		 3891}
3892
f08864b4
SY		 3893static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
3894{
66a5a347
JK		 3895 struct vcpu_vmx *vmx = to_vmx(vcpu);
3896
0b6ac343
NHE		 3897 if (is_guest_mode(vcpu))
3898 return;
3899
3b86cd99
JK		 3900 if (!cpu_has_virtual_nmis()) {
3901 /*
3902 * Tracking the NMI-blocked state in software is built upon
3903 * finding the next open IRQ window. This, in turn, depends on
3904 * well-behaving guests: They have to keep IRQs disabled at
3905 * least as long as the NMI handler runs. Otherwise we may
3906 * cause NMI nesting, maybe breaking the guest. But as this is
3907 * highly unlikely, we can live with the residual risk.
3908 */
3909 vmx->soft_vnmi_blocked = 1;
3910 vmx->vnmi_blocked_time = 0;
3911 }
3912
487b391d 3913 ++vcpu->stat.nmi_injections;
9d58b931 3914 vmx->nmi_known_unmasked = false;
7ffd92c5 3915 if (vmx->rmode.vm86_active) {
71f9833b 3916 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 3917 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 3918 return;
3919 }
f08864b4
SY		 3920 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
3921 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
443381a8 3922 vmx_clear_hlt(vcpu);
f08864b4
SY		 3923}
3924
c4282df9 3925static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 3926{
3b86cd99 3927 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 3928 return 0;
33f089ca 3929
c4282df9 3930 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 3931 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
3932 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 3933}
3934
3cfc3092
JK		 3935static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
3936{
3937 if (!cpu_has_virtual_nmis())
3938 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 3939 if (to_vmx(vcpu)->nmi_known_unmasked)
3940 return false;
c332c83a 3941 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 3942}
3943
3944static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3945{
3946 struct vcpu_vmx *vmx = to_vmx(vcpu);
3947
3948 if (!cpu_has_virtual_nmis()) {
3949 if (vmx->soft_vnmi_blocked != masked) {
3950 vmx->soft_vnmi_blocked = masked;
3951 vmx->vnmi_blocked_time = 0;
3952 }
3953 } else {
9d58b931 3954 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 3955 if (masked)
3956 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3957 GUEST_INTR_STATE_NMI);
3958 else
3959 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3960 GUEST_INTR_STATE_NMI);
3961 }
3962}
3963
78646121
GN		 3964static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
3965{
b6f1250e
NHE		 3966 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
3967 struct vmcs12 *vmcs12;
3968 if (to_vmx(vcpu)->nested.nested_run_pending)
3969 return 0;
3970 nested_vmx_vmexit(vcpu);
3971 vmcs12 = get_vmcs12(vcpu);
3972 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
3973 vmcs12->vm_exit_intr_info = 0;
3974 /* fall through to normal code, but now in L1, not L2 */
3975 }
3976
c4282df9
GN		 3977 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
3978 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3979 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 3980}
3981
cbc94022
IE		 3982static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
3983{
3984 int ret;
3985 struct kvm_userspace_memory_region tss_mem = {
6fe63979 3986 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 3987 .guest_phys_addr = addr,
3988 .memory_size = PAGE_SIZE * 3,
3989 .flags = 0,
3990 };
3991
3992 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
3993 if (ret)
3994 return ret;
bfc6d222 3995 kvm->arch.tss_addr = addr;
93ea5388
GN		 3996 if (!init_rmode_tss(kvm))
3997 return -ENOMEM;
3998
cbc94022
IE		 3999 return 0;
4000}
4001
6aa8b732
AK		 4002static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4003 int vec, u32 err_code)
4004{
b3f37707
NK		 4005 /*
4006 * Instruction with address size override prefix opcode 0x67
4007 * Cause the #SS fault with 0 error code in VM86 mode.
4008 */
4009 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
51d8b661 4010 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
6aa8b732 4011 return 1;
77ab6db0
JK		 4012 /*
4013 * Forward all other exceptions that are valid in real mode.
4014 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4015 * the required debugging infrastructure rework.
4016 */
4017 switch (vec) {
77ab6db0 4018 case DB_VECTOR:
d0bfb940
JK		 4019 if (vcpu->guest_debug &
4020 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4021 return 0;
4022 kvm_queue_exception(vcpu, vec);
4023 return 1;
77ab6db0 4024 case BP_VECTOR:
c573cd22
JK		 4025 /*
4026 * Update instruction length as we may reinject the exception
4027 * from user space while in guest debugging mode.
4028 */
4029 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4030 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 4031 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4032 return 0;
4033 /* fall through */
4034 case DE_VECTOR:
77ab6db0
JK		 4035 case OF_VECTOR:
4036 case BR_VECTOR:
4037 case UD_VECTOR:
4038 case DF_VECTOR:
4039 case SS_VECTOR:
4040 case GP_VECTOR:
4041 case MF_VECTOR:
4042 kvm_queue_exception(vcpu, vec);
4043 return 1;
4044 }
6aa8b732
AK		 4045 return 0;
4046}
4047
a0861c02
AK		 4048/*
4049 * Trigger machine check on the host. We assume all the MSRs are already set up
4050 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4051 * We pass a fake environment to the machine check handler because we want
4052 * the guest to be always treated like user space, no matter what context
4053 * it used internally.
4054 */
4055static void kvm_machine_check(void)
4056{
4057#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4058 struct pt_regs regs = {
4059 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4060 .flags = X86_EFLAGS_IF,
4061 };
4062
4063 do_machine_check(&regs, 0);
4064#endif
4065}
4066
851ba692 4067static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4068{
4069 /* already handled by vcpu_run */
4070 return 1;
4071}
4072
851ba692 4073static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4074{
1155f76a 4075 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4076 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4077 u32 intr_info, ex_no, error_code;
42dbaa5a 4078 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4079 u32 vect_info;
4080 enum emulation_result er;
4081
1155f76a 4082 vect_info = vmx->idt_vectoring_info;
88786475 4083 intr_info = vmx->exit_intr_info;
6aa8b732 4084
a0861c02 4085 if (is_machine_check(intr_info))
851ba692 4086 return handle_machine_check(vcpu);
a0861c02 4087
6aa8b732 4088 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 4089 !is_page_fault(intr_info)) {
4090 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4091 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4092 vcpu->run->internal.ndata = 2;
4093 vcpu->run->internal.data[0] = vect_info;
4094 vcpu->run->internal.data[1] = intr_info;
4095 return 0;
4096 }
6aa8b732 4097
e4a41889 4098 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4099 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4100
4101 if (is_no_device(intr_info)) {
5fd86fcf 4102 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4103 return 1;
4104 }
4105
7aa81cc0 4106 if (is_invalid_opcode(intr_info)) {
51d8b661 4107 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4108 if (er != EMULATE_DONE)
7ee5d940 4109 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4110 return 1;
4111 }
4112
6aa8b732 4113 error_code = 0;
2e11384c 4114 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 4115 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4116 if (is_page_fault(intr_info)) {
1439442c 4117 /* EPT won't cause page fault directly */
cf3ace79 4118 BUG_ON(enable_ept);
6aa8b732 4119 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4120 trace_kvm_page_fault(cr2, error_code);
4121
3298b75c 4122 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4123 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4124 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4125 }
4126
7ffd92c5 4127 if (vmx->rmode.vm86_active &&
6aa8b732 4128 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 4129 error_code)) {
ad312c7c
ZX		 4130 if (vcpu->arch.halt_request) {
4131 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 4132 return kvm_emulate_halt(vcpu);
4133 }
6aa8b732 4134 return 1;
72d6e5a0 4135 }
6aa8b732 4136
d0bfb940 4137 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 4138 switch (ex_no) {
4139 case DB_VECTOR:
4140 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4141 if (!(vcpu->guest_debug &
4142 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4143 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4144 kvm_queue_exception(vcpu, DB_VECTOR);
4145 return 1;
4146 }
4147 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4148 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4149 /* fall through */
4150 case BP_VECTOR:
c573cd22
JK		 4151 /*
4152 * Update instruction length as we may reinject #BP from
4153 * user space while in guest debugging mode. Reading it for
4154 * #DB as well causes no harm, it is not used in that case.
4155 */
4156 vmx->vcpu.arch.event_exit_inst_len =
4157 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4158 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4159 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4160 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4161 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4162 break;
4163 default:
d0bfb940
JK		 4164 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4165 kvm_run->ex.exception = ex_no;
4166 kvm_run->ex.error_code = error_code;
42dbaa5a 4167 break;
6aa8b732 4168 }
6aa8b732
AK		 4169 return 0;
4170}
4171
851ba692 4172static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4173{
1165f5fe 4174 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4175 return 1;
4176}
4177
851ba692 4178static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4179{
851ba692 4180 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4181 return 0;
4182}
6aa8b732 4183
851ba692 4184static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4185{
bfdaab09 4186 unsigned long exit_qualification;
34c33d16 4187 int size, in, string;
039576c0 4188 unsigned port;
6aa8b732 4189
bfdaab09 4190 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4191 string = (exit_qualification & 16) != 0;
cf8f70bf 4192 in = (exit_qualification & 8) != 0;
e70669ab 4193
cf8f70bf 4194 ++vcpu->stat.io_exits;
e70669ab 4195
cf8f70bf 4196 if (string || in)
51d8b661 4197 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4198
cf8f70bf
GN		 4199 port = exit_qualification >> 16;
4200 size = (exit_qualification & 7) + 1;
e93f36bc 4201 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4202
4203 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4204}
4205
102d8325
IM		 4206static void
4207vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4208{
4209 /*
4210 * Patch in the VMCALL instruction:
4211 */
4212 hypercall[0] = 0x0f;
4213 hypercall[1] = 0x01;
4214 hypercall[2] = 0xc1;
102d8325
IM		 4215}
4216
eeadf9e7
NHE		 4217/* called to set cr0 as approriate for a mov-to-cr0 exit. */
4218static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4219{
4220 if (to_vmx(vcpu)->nested.vmxon &&
4221 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4222 return 1;
4223
4224 if (is_guest_mode(vcpu)) {
4225 /*
4226 * We get here when L2 changed cr0 in a way that did not change
4227 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4228 * but did change L0 shadowed bits. This can currently happen
4229 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4230 * loading) while pretending to allow the guest to change it.
4231 */
4232 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4233 (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4234 return 1;
4235 vmcs_writel(CR0_READ_SHADOW, val);
4236 return 0;
4237 } else
4238 return kvm_set_cr0(vcpu, val);
4239}
4240
4241static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4242{
4243 if (is_guest_mode(vcpu)) {
4244 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4245 (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4246 return 1;
4247 vmcs_writel(CR4_READ_SHADOW, val);
4248 return 0;
4249 } else
4250 return kvm_set_cr4(vcpu, val);
4251}
4252
4253/* called to set cr0 as approriate for clts instruction exit. */
4254static void handle_clts(struct kvm_vcpu *vcpu)
4255{
4256 if (is_guest_mode(vcpu)) {
4257 /*
4258 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4259 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4260 * just pretend it's off (also in arch.cr0 for fpu_activate).
4261 */
4262 vmcs_writel(CR0_READ_SHADOW,
4263 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4264 vcpu->arch.cr0 &= ~X86_CR0_TS;
4265 } else
4266 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4267}
4268
851ba692 4269static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4270{
229456fc 4271 unsigned long exit_qualification, val;
6aa8b732
AK		 4272 int cr;
4273 int reg;
49a9b07e 4274 int err;
6aa8b732 4275
bfdaab09 4276 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4277 cr = exit_qualification & 15;
4278 reg = (exit_qualification >> 8) & 15;
4279 switch ((exit_qualification >> 4) & 3) {
4280 case 0: /* mov to cr */
229456fc
MT		 4281 val = kvm_register_read(vcpu, reg);
4282 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4283 switch (cr) {
4284 case 0:
eeadf9e7 4285 err = handle_set_cr0(vcpu, val);
db8fcefa 4286 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4287 return 1;
4288 case 3:
2390218b 4289 err = kvm_set_cr3(vcpu, val);
db8fcefa 4290 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4291 return 1;
4292 case 4:
eeadf9e7 4293 err = handle_set_cr4(vcpu, val);
db8fcefa 4294 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4295 return 1;
0a5fff19
GN		 4296 case 8: {
4297 u8 cr8_prev = kvm_get_cr8(vcpu);
4298 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4299 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4300 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4301 if (irqchip_in_kernel(vcpu->kvm))
4302 return 1;
4303 if (cr8_prev <= cr8)
4304 return 1;
851ba692 4305 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4306 return 0;
4307 }
6aa8b732
AK		 4308 };
4309 break;
25c4c276 4310 case 2: /* clts */
eeadf9e7 4311 handle_clts(vcpu);
4d4ec087 4312 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4313 skip_emulated_instruction(vcpu);
6b52d186 4314 vmx_fpu_activate(vcpu);
25c4c276 4315 return 1;
6aa8b732
AK		 4316 case 1: /*mov from cr*/
4317 switch (cr) {
4318 case 3:
9f8fe504
AK		 4319 val = kvm_read_cr3(vcpu);
4320 kvm_register_write(vcpu, reg, val);
4321 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4322 skip_emulated_instruction(vcpu);
4323 return 1;
4324 case 8:
229456fc
MT		 4325 val = kvm_get_cr8(vcpu);
4326 kvm_register_write(vcpu, reg, val);
4327 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4328 skip_emulated_instruction(vcpu);
4329 return 1;
4330 }
4331 break;
4332 case 3: /* lmsw */
a1f83a74 4333 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4334 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4335 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4336
4337 skip_emulated_instruction(vcpu);
4338 return 1;
4339 default:
4340 break;
4341 }
851ba692 4342 vcpu->run->exit_reason = 0;
f0242478 4343 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4344 (int)(exit_qualification >> 4) & 3, cr);
4345 return 0;
4346}
4347
851ba692 4348static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4349{
bfdaab09 4350 unsigned long exit_qualification;
6aa8b732
AK		 4351 int dr, reg;
4352
f2483415 4353 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4354 if (!kvm_require_cpl(vcpu, 0))
4355 return 1;
42dbaa5a
JK		 4356 dr = vmcs_readl(GUEST_DR7);
4357 if (dr & DR7_GD) {
4358 /*
4359 * As the vm-exit takes precedence over the debug trap, we
4360 * need to emulate the latter, either for the host or the
4361 * guest debugging itself.
4362 */
4363 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 4364 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4365 vcpu->run->debug.arch.dr7 = dr;
4366 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 4367 vmcs_readl(GUEST_CS_BASE) +
4368 vmcs_readl(GUEST_RIP);
851ba692
AK		 4369 vcpu->run->debug.arch.exception = DB_VECTOR;
4370 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4371 return 0;
4372 } else {
4373 vcpu->arch.dr7 &= ~DR7_GD;
4374 vcpu->arch.dr6 |= DR6_BD;
4375 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4376 kvm_queue_exception(vcpu, DB_VECTOR);
4377 return 1;
4378 }
4379 }
4380
bfdaab09 4381 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 4382 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4383 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4384 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 4385 unsigned long val;
4386 if (!kvm_get_dr(vcpu, dr, &val))
4387 kvm_register_write(vcpu, reg, val);
4388 } else
4389 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 4390 skip_emulated_instruction(vcpu);
4391 return 1;
4392}
4393
020df079
GN		 4394static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4395{
4396 vmcs_writel(GUEST_DR7, val);
4397}
4398
851ba692 4399static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4400{
06465c5a
AK		 4401 kvm_emulate_cpuid(vcpu);
4402 return 1;
6aa8b732
AK		 4403}
4404
851ba692 4405static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4406{
ad312c7c 4407 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 4408 u64 data;
4409
4410 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 4411 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 4412 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4413 return 1;
4414 }
4415
229456fc 4416 trace_kvm_msr_read(ecx, data);
2714d1d3 4417
6aa8b732 4418 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 4419 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4420 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 4421 skip_emulated_instruction(vcpu);
4422 return 1;
4423}
4424
851ba692 4425static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4426{
ad312c7c
ZX		 4427 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4428 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4429 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 4430
4431 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 4432 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 4433 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4434 return 1;
4435 }
4436
59200273 4437 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 4438 skip_emulated_instruction(vcpu);
4439 return 1;
4440}
4441
851ba692 4442static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4443{
3842d135 4444 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 4445 return 1;
4446}
4447
851ba692 4448static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4449{
85f455f7
ED		 4450 u32 cpu_based_vm_exec_control;
4451
4452 /* clear pending irq */
4453 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4454 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4455 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 4456
3842d135
AK		 4457 kvm_make_request(KVM_REQ_EVENT, vcpu);
4458
a26bf12a 4459 ++vcpu->stat.irq_window_exits;
2714d1d3 4460
c1150d8c
DL		 4461 /*
4462 * If the user space waits to inject interrupts, exit as soon as
4463 * possible
4464 */
8061823a 4465 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 4466 vcpu->run->request_interrupt_window &&
8061823a 4467 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 4468 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 4469 return 0;
4470 }
6aa8b732
AK		 4471 return 1;
4472}
4473
851ba692 4474static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 4475{
4476 skip_emulated_instruction(vcpu);
d3bef15f 4477 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 4478}
4479
851ba692 4480static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4481{
510043da 4482 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 4483 kvm_emulate_hypercall(vcpu);
4484 return 1;
c21415e8
IM		 4485}
4486
ec25d5e6
GN		 4487static int handle_invd(struct kvm_vcpu *vcpu)
4488{
51d8b661 4489 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 4490}
4491
851ba692 4492static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4493{
f9c617f6 4494 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4495
4496 kvm_mmu_invlpg(vcpu, exit_qualification);
4497 skip_emulated_instruction(vcpu);
4498 return 1;
4499}
4500
851ba692 4501static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 4502{
4503 skip_emulated_instruction(vcpu);
f5f48ee1 4504 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 4505 return 1;
4506}
4507
2acf923e
DC		 4508static int handle_xsetbv(struct kvm_vcpu *vcpu)
4509{
4510 u64 new_bv = kvm_read_edx_eax(vcpu);
4511 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4512
4513 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4514 skip_emulated_instruction(vcpu);
4515 return 1;
4516}
4517
851ba692 4518static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 4519{
51d8b661 4520 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 4521}
4522
851ba692 4523static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 4524{
60637aac 4525 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 4526 unsigned long exit_qualification;
e269fb21
JK		 4527 bool has_error_code = false;
4528 u32 error_code = 0;
37817f29 4529 u16 tss_selector;
64a7ec06
GN		 4530 int reason, type, idt_v;
4531
4532 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4533 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 4534
4535 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4536
4537 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 4538 if (reason == TASK_SWITCH_GATE && idt_v) {
4539 switch (type) {
4540 case INTR_TYPE_NMI_INTR:
4541 vcpu->arch.nmi_injected = false;
654f06fc 4542 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 4543 break;
4544 case INTR_TYPE_EXT_INTR:
66fd3f7f 4545 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 4546 kvm_clear_interrupt_queue(vcpu);
4547 break;
4548 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 4549 if (vmx->idt_vectoring_info &
4550 VECTORING_INFO_DELIVER_CODE_MASK) {
4551 has_error_code = true;
4552 error_code =
4553 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4554 }
4555 /* fall through */
64a7ec06
GN		 4556 case INTR_TYPE_SOFT_EXCEPTION:
4557 kvm_clear_exception_queue(vcpu);
4558 break;
4559 default:
4560 break;
4561 }
60637aac 4562 }
37817f29
IE		 4563 tss_selector = exit_qualification;
4564
64a7ec06
GN		 4565 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4566 type != INTR_TYPE_EXT_INTR &&
4567 type != INTR_TYPE_NMI_INTR))
4568 skip_emulated_instruction(vcpu);
4569
acb54517
GN		 4570 if (kvm_task_switch(vcpu, tss_selector, reason,
4571 has_error_code, error_code) == EMULATE_FAIL) {
4572 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4573 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4574 vcpu->run->internal.ndata = 0;
42dbaa5a 4575 return 0;
acb54517 4576 }
42dbaa5a
JK		 4577
4578 /* clear all local breakpoint enable flags */
4579 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4580
4581 /*
4582 * TODO: What about debug traps on tss switch?
4583 * Are we supposed to inject them and update dr6?
4584 */
4585
4586 return 1;
37817f29
IE		 4587}
4588
851ba692 4589static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 4590{
f9c617f6 4591 unsigned long exit_qualification;
1439442c 4592 gpa_t gpa;
1439442c 4593 int gla_validity;
1439442c 4594
f9c617f6 4595 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 4596
4597 if (exit_qualification & (1 << 6)) {
4598 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 4599 return -EINVAL;
1439442c
SY		 4600 }
4601
4602 gla_validity = (exit_qualification >> 7) & 0x3;
4603 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4604 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4605 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4606 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 4607 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 4608 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4609 (long unsigned int)exit_qualification);
851ba692
AK		 4610 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4611 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 4612 return 0;
1439442c
SY		 4613 }
4614
4615 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 4616 trace_kvm_page_fault(gpa, exit_qualification);
dc25e89e 4617 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
1439442c
SY		 4618}
4619
68f89400
MT		 4620static u64 ept_rsvd_mask(u64 spte, int level)
4621{
4622 int i;
4623 u64 mask = 0;
4624
4625 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4626 mask |= (1ULL << i);
4627
4628 if (level > 2)
4629 /* bits 7:3 reserved */
4630 mask |= 0xf8;
4631 else if (level == 2) {
4632 if (spte & (1ULL << 7))
4633 /* 2MB ref, bits 20:12 reserved */
4634 mask |= 0x1ff000;
4635 else
4636 /* bits 6:3 reserved */
4637 mask |= 0x78;
4638 }
4639
4640 return mask;
4641}
4642
4643static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4644 int level)
4645{
4646 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4647
4648 /* 010b (write-only) */
4649 WARN_ON((spte & 0x7) == 0x2);
4650
4651 /* 110b (write/execute) */
4652 WARN_ON((spte & 0x7) == 0x6);
4653
4654 /* 100b (execute-only) and value not supported by logical processor */
4655 if (!cpu_has_vmx_ept_execute_only())
4656 WARN_ON((spte & 0x7) == 0x4);
4657
4658 /* not 000b */
4659 if ((spte & 0x7)) {
4660 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4661
4662 if (rsvd_bits != 0) {
4663 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4664 __func__, rsvd_bits);
4665 WARN_ON(1);
4666 }
4667
4668 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4669 u64 ept_mem_type = (spte & 0x38) >> 3;
4670
4671 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4672 ept_mem_type == 7) {
4673 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4674 __func__, ept_mem_type);
4675 WARN_ON(1);
4676 }
4677 }
4678 }
4679}
4680
851ba692 4681static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 4682{
4683 u64 sptes[4];
ce88decf 4684 int nr_sptes, i, ret;
68f89400
MT		 4685 gpa_t gpa;
4686
4687 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4688
ce88decf
XG		 4689 ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4690 if (likely(ret == 1))
4691 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4692 EMULATE_DONE;
4693 if (unlikely(!ret))
4694 return 1;
4695
4696 /* It is the real ept misconfig */
68f89400
MT		 4697 printk(KERN_ERR "EPT: Misconfiguration.\n");
4698 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4699
4700 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4701
4702 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4703 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4704
851ba692
AK		 4705 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4706 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 4707
4708 return 0;
4709}
4710
851ba692 4711static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 4712{
4713 u32 cpu_based_vm_exec_control;
4714
4715 /* clear pending NMI */
4716 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4717 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4718 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4719 ++vcpu->stat.nmi_window_exits;
3842d135 4720 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 4721
4722 return 1;
4723}
4724
80ced186 4725static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 4726{
8b3079a5
AK		 4727 struct vcpu_vmx *vmx = to_vmx(vcpu);
4728 enum emulation_result err = EMULATE_DONE;
80ced186 4729 int ret = 1;
49e9d557
AK		 4730 u32 cpu_exec_ctrl;
4731 bool intr_window_requested;
4732
4733 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4734 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0
MG		 4735
4736 while (!guest_state_valid(vcpu)) {
49e9d557
AK		 4737 if (intr_window_requested
4738 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4739 return handle_interrupt_window(&vmx->vcpu);
4740
51d8b661 4741 err = emulate_instruction(vcpu, 0);
ea953ef0 4742
80ced186
MG		 4743 if (err == EMULATE_DO_MMIO) {
4744 ret = 0;
4745 goto out;
4746 }
1d5a4d9b 4747
6d77dbfc
GN		 4748 if (err != EMULATE_DONE)
4749 return 0;
ea953ef0
MG		 4750
4751 if (signal_pending(current))
80ced186 4752 goto out;
ea953ef0
MG		 4753 if (need_resched())
4754 schedule();
4755 }
4756
80ced186
MG		 4757 vmx->emulation_required = 0;
4758out:
4759 return ret;
ea953ef0
MG		 4760}
4761
4b8d54f9
ZE		 4762/*
4763 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4764 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4765 */
9fb41ba8 4766static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 4767{
4768 skip_emulated_instruction(vcpu);
4769 kvm_vcpu_on_spin(vcpu);
4770
4771 return 1;
4772}
4773
59708670
SY		 4774static int handle_invalid_op(struct kvm_vcpu *vcpu)
4775{
4776 kvm_queue_exception(vcpu, UD_VECTOR);
4777 return 1;
4778}
4779
ff2f6fe9
NHE		 4780/*
4781 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4782 * We could reuse a single VMCS for all the L2 guests, but we also want the
4783 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4784 * allows keeping them loaded on the processor, and in the future will allow
4785 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4786 * every entry if they never change.
4787 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4788 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4789 *
4790 * The following functions allocate and free a vmcs02 in this pool.
4791 */
4792
4793/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4794static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
4795{
4796 struct vmcs02_list *item;
4797 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4798 if (item->vmptr == vmx->nested.current_vmptr) {
4799 list_move(&item->list, &vmx->nested.vmcs02_pool);
4800 return &item->vmcs02;
4801 }
4802
4803 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
4804 /* Recycle the least recently used VMCS. */
4805 item = list_entry(vmx->nested.vmcs02_pool.prev,
4806 struct vmcs02_list, list);
4807 item->vmptr = vmx->nested.current_vmptr;
4808 list_move(&item->list, &vmx->nested.vmcs02_pool);
4809 return &item->vmcs02;
4810 }
4811
4812 /* Create a new VMCS */
4813 item = (struct vmcs02_list *)
4814 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
4815 if (!item)
4816 return NULL;
4817 item->vmcs02.vmcs = alloc_vmcs();
4818 if (!item->vmcs02.vmcs) {
4819 kfree(item);
4820 return NULL;
4821 }
4822 loaded_vmcs_init(&item->vmcs02);
4823 item->vmptr = vmx->nested.current_vmptr;
4824 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
4825 vmx->nested.vmcs02_num++;
4826 return &item->vmcs02;
4827}
4828
4829/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4830static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
4831{
4832 struct vmcs02_list *item;
4833 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4834 if (item->vmptr == vmptr) {
4835 free_loaded_vmcs(&item->vmcs02);
4836 list_del(&item->list);
4837 kfree(item);
4838 vmx->nested.vmcs02_num--;
4839 return;
4840 }
4841}
4842
4843/*
4844 * Free all VMCSs saved for this vcpu, except the one pointed by
4845 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4846 * currently used, if running L2), and vmcs01 when running L2.
4847 */
4848static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
4849{
4850 struct vmcs02_list *item, *n;
4851 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4852 if (vmx->loaded_vmcs != &item->vmcs02)
4853 free_loaded_vmcs(&item->vmcs02);
4854 list_del(&item->list);
4855 kfree(item);
4856 }
4857 vmx->nested.vmcs02_num = 0;
4858
4859 if (vmx->loaded_vmcs != &vmx->vmcs01)
4860 free_loaded_vmcs(&vmx->vmcs01);
4861}
4862
ec378aee
NHE		 4863/*
4864 * Emulate the VMXON instruction.
4865 * Currently, we just remember that VMX is active, and do not save or even
4866 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
4867 * do not currently need to store anything in that guest-allocated memory
4868 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
4869 * argument is different from the VMXON pointer (which the spec says they do).
4870 */
4871static int handle_vmon(struct kvm_vcpu *vcpu)
4872{
4873 struct kvm_segment cs;
4874 struct vcpu_vmx *vmx = to_vmx(vcpu);
4875
4876 /* The Intel VMX Instruction Reference lists a bunch of bits that
4877 * are prerequisite to running VMXON, most notably cr4.VMXE must be
4878 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
4879 * Otherwise, we should fail with #UD. We test these now:
4880 */
4881 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
4882 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
4883 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4884 kvm_queue_exception(vcpu, UD_VECTOR);
4885 return 1;
4886 }
4887
4888 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4889 if (is_long_mode(vcpu) && !cs.l) {
4890 kvm_queue_exception(vcpu, UD_VECTOR);
4891 return 1;
4892 }
4893
4894 if (vmx_get_cpl(vcpu)) {
4895 kvm_inject_gp(vcpu, 0);
4896 return 1;
4897 }
4898
ff2f6fe9
NHE		 4899 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
4900 vmx->nested.vmcs02_num = 0;
4901
ec378aee
NHE		 4902 vmx->nested.vmxon = true;
4903
4904 skip_emulated_instruction(vcpu);
4905 return 1;
4906}
4907
4908/*
4909 * Intel's VMX Instruction Reference specifies a common set of prerequisites
4910 * for running VMX instructions (except VMXON, whose prerequisites are
4911 * slightly different). It also specifies what exception to inject otherwise.
4912 */
4913static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
4914{
4915 struct kvm_segment cs;
4916 struct vcpu_vmx *vmx = to_vmx(vcpu);
4917
4918 if (!vmx->nested.vmxon) {
4919 kvm_queue_exception(vcpu, UD_VECTOR);
4920 return 0;
4921 }
4922
4923 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4924 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
4925 (is_long_mode(vcpu) && !cs.l)) {
4926 kvm_queue_exception(vcpu, UD_VECTOR);
4927 return 0;
4928 }
4929
4930 if (vmx_get_cpl(vcpu)) {
4931 kvm_inject_gp(vcpu, 0);
4932 return 0;
4933 }
4934
4935 return 1;
4936}
4937
4938/*
4939 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
4940 * just stops using VMX.
4941 */
4942static void free_nested(struct vcpu_vmx *vmx)
4943{
4944 if (!vmx->nested.vmxon)
4945 return;
4946 vmx->nested.vmxon = false;
a9d30f33
NHE		 4947 if (vmx->nested.current_vmptr != -1ull) {
4948 kunmap(vmx->nested.current_vmcs12_page);
4949 nested_release_page(vmx->nested.current_vmcs12_page);
4950 vmx->nested.current_vmptr = -1ull;
4951 vmx->nested.current_vmcs12 = NULL;
4952 }
fe3ef05c
NHE		 4953 /* Unpin physical memory we referred to in current vmcs02 */
4954 if (vmx->nested.apic_access_page) {
4955 nested_release_page(vmx->nested.apic_access_page);
4956 vmx->nested.apic_access_page = 0;
4957 }
ff2f6fe9
NHE		 4958
4959 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 4960}
4961
4962/* Emulate the VMXOFF instruction */
4963static int handle_vmoff(struct kvm_vcpu *vcpu)
4964{
4965 if (!nested_vmx_check_permission(vcpu))
4966 return 1;
4967 free_nested(to_vmx(vcpu));
4968 skip_emulated_instruction(vcpu);
4969 return 1;
4970}
4971
064aea77
NHE		 4972/*
4973 * Decode the memory-address operand of a vmx instruction, as recorded on an
4974 * exit caused by such an instruction (run by a guest hypervisor).
4975 * On success, returns 0. When the operand is invalid, returns 1 and throws
4976 * #UD or #GP.
4977 */
4978static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
4979 unsigned long exit_qualification,
4980 u32 vmx_instruction_info, gva_t *ret)
4981{
4982 /*
4983 * According to Vol. 3B, "Information for VM Exits Due to Instruction
4984 * Execution", on an exit, vmx_instruction_info holds most of the
4985 * addressing components of the operand. Only the displacement part
4986 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
4987 * For how an actual address is calculated from all these components,
4988 * refer to Vol. 1, "Operand Addressing".
4989 */
4990 int scaling = vmx_instruction_info & 3;
4991 int addr_size = (vmx_instruction_info >> 7) & 7;
4992 bool is_reg = vmx_instruction_info & (1u << 10);
4993 int seg_reg = (vmx_instruction_info >> 15) & 7;
4994 int index_reg = (vmx_instruction_info >> 18) & 0xf;
4995 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
4996 int base_reg = (vmx_instruction_info >> 23) & 0xf;
4997 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
4998
4999 if (is_reg) {
5000 kvm_queue_exception(vcpu, UD_VECTOR);
5001 return 1;
5002 }
5003
5004 /* Addr = segment_base + offset */
5005 /* offset = base + [index * scale] + displacement */
5006 *ret = vmx_get_segment_base(vcpu, seg_reg);
5007 if (base_is_valid)
5008 *ret += kvm_register_read(vcpu, base_reg);
5009 if (index_is_valid)
5010 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5011 *ret += exit_qualification; /* holds the displacement */
5012
5013 if (addr_size == 1) /* 32 bit */
5014 *ret &= 0xffffffff;
5015
5016 /*
5017 * TODO: throw #GP (and return 1) in various cases that the VM*
5018 * instructions require it - e.g., offset beyond segment limit,
5019 * unusable or unreadable/unwritable segment, non-canonical 64-bit
5020 * address, and so on. Currently these are not checked.
5021 */
5022 return 0;
5023}
5024
0140caea
NHE		 5025/*
5026 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5027 * set the success or error code of an emulated VMX instruction, as specified
5028 * by Vol 2B, VMX Instruction Reference, "Conventions".
5029 */
5030static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5031{
5032 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5033 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5034 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5035}
5036
5037static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5038{
5039 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5040 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5041 X86_EFLAGS_SF | X86_EFLAGS_OF))
5042 | X86_EFLAGS_CF);
5043}
5044
5045static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5046 u32 vm_instruction_error)
5047{
5048 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5049 /*
5050 * failValid writes the error number to the current VMCS, which
5051 * can't be done there isn't a current VMCS.
5052 */
5053 nested_vmx_failInvalid(vcpu);
5054 return;
5055 }
5056 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5057 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5058 X86_EFLAGS_SF | X86_EFLAGS_OF))
5059 | X86_EFLAGS_ZF);
5060 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5061}
5062
27d6c865
NHE		 5063/* Emulate the VMCLEAR instruction */
5064static int handle_vmclear(struct kvm_vcpu *vcpu)
5065{
5066 struct vcpu_vmx *vmx = to_vmx(vcpu);
5067 gva_t gva;
5068 gpa_t vmptr;
5069 struct vmcs12 *vmcs12;
5070 struct page *page;
5071 struct x86_exception e;
5072
5073 if (!nested_vmx_check_permission(vcpu))
5074 return 1;
5075
5076 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5077 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5078 return 1;
5079
5080 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5081 sizeof(vmptr), &e)) {
5082 kvm_inject_page_fault(vcpu, &e);
5083 return 1;
5084 }
5085
5086 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5087 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5088 skip_emulated_instruction(vcpu);
5089 return 1;
5090 }
5091
5092 if (vmptr == vmx->nested.current_vmptr) {
5093 kunmap(vmx->nested.current_vmcs12_page);
5094 nested_release_page(vmx->nested.current_vmcs12_page);
5095 vmx->nested.current_vmptr = -1ull;
5096 vmx->nested.current_vmcs12 = NULL;
5097 }
5098
5099 page = nested_get_page(vcpu, vmptr);
5100 if (page == NULL) {
5101 /*
5102 * For accurate processor emulation, VMCLEAR beyond available
5103 * physical memory should do nothing at all. However, it is
5104 * possible that a nested vmx bug, not a guest hypervisor bug,
5105 * resulted in this case, so let's shut down before doing any
5106 * more damage:
5107 */
5108 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5109 return 1;
5110 }
5111 vmcs12 = kmap(page);
5112 vmcs12->launch_state = 0;
5113 kunmap(page);
5114 nested_release_page(page);
5115
5116 nested_free_vmcs02(vmx, vmptr);
5117
5118 skip_emulated_instruction(vcpu);
5119 nested_vmx_succeed(vcpu);
5120 return 1;
5121}
5122
cd232ad0
NHE		 5123static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5124
5125/* Emulate the VMLAUNCH instruction */
5126static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5127{
5128 return nested_vmx_run(vcpu, true);
5129}
5130
5131/* Emulate the VMRESUME instruction */
5132static int handle_vmresume(struct kvm_vcpu *vcpu)
5133{
5134
5135 return nested_vmx_run(vcpu, false);
5136}
5137
49f705c5
NHE		 5138enum vmcs_field_type {
5139 VMCS_FIELD_TYPE_U16 = 0,
5140 VMCS_FIELD_TYPE_U64 = 1,
5141 VMCS_FIELD_TYPE_U32 = 2,
5142 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5143};
5144
5145static inline int vmcs_field_type(unsigned long field)
5146{
5147 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5148 return VMCS_FIELD_TYPE_U32;
5149 return (field >> 13) & 0x3 ;
5150}
5151
5152static inline int vmcs_field_readonly(unsigned long field)
5153{
5154 return (((field >> 10) & 0x3) == 1);
5155}
5156
5157/*
5158 * Read a vmcs12 field. Since these can have varying lengths and we return
5159 * one type, we chose the biggest type (u64) and zero-extend the return value
5160 * to that size. Note that the caller, handle_vmread, might need to use only
5161 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5162 * 64-bit fields are to be returned).
5163 */
5164static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5165 unsigned long field, u64 *ret)
5166{
5167 short offset = vmcs_field_to_offset(field);
5168 char *p;
5169
5170 if (offset < 0)
5171 return 0;
5172
5173 p = ((char *)(get_vmcs12(vcpu))) + offset;
5174
5175 switch (vmcs_field_type(field)) {
5176 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5177 *ret = *((natural_width *)p);
5178 return 1;
5179 case VMCS_FIELD_TYPE_U16:
5180 *ret = *((u16 *)p);
5181 return 1;
5182 case VMCS_FIELD_TYPE_U32:
5183 *ret = *((u32 *)p);
5184 return 1;
5185 case VMCS_FIELD_TYPE_U64:
5186 *ret = *((u64 *)p);
5187 return 1;
5188 default:
5189 return 0; /* can never happen. */
5190 }
5191}
5192
5193/*
5194 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5195 * used before) all generate the same failure when it is missing.
5196 */
5197static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5198{
5199 struct vcpu_vmx *vmx = to_vmx(vcpu);
5200 if (vmx->nested.current_vmptr == -1ull) {
5201 nested_vmx_failInvalid(vcpu);
5202 skip_emulated_instruction(vcpu);
5203 return 0;
5204 }
5205 return 1;
5206}
5207
5208static int handle_vmread(struct kvm_vcpu *vcpu)
5209{
5210 unsigned long field;
5211 u64 field_value;
5212 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5213 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5214 gva_t gva = 0;
5215
5216 if (!nested_vmx_check_permission(vcpu) ||
5217 !nested_vmx_check_vmcs12(vcpu))
5218 return 1;
5219
5220 /* Decode instruction info and find the field to read */
5221 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5222 /* Read the field, zero-extended to a u64 field_value */
5223 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5224 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5225 skip_emulated_instruction(vcpu);
5226 return 1;
5227 }
5228 /*
5229 * Now copy part of this value to register or memory, as requested.
5230 * Note that the number of bits actually copied is 32 or 64 depending
5231 * on the guest's mode (32 or 64 bit), not on the given field's length.
5232 */
5233 if (vmx_instruction_info & (1u << 10)) {
5234 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5235 field_value);
5236 } else {
5237 if (get_vmx_mem_address(vcpu, exit_qualification,
5238 vmx_instruction_info, &gva))
5239 return 1;
5240 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5241 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5242 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5243 }
5244
5245 nested_vmx_succeed(vcpu);
5246 skip_emulated_instruction(vcpu);
5247 return 1;
5248}
5249
5250
5251static int handle_vmwrite(struct kvm_vcpu *vcpu)
5252{
5253 unsigned long field;
5254 gva_t gva;
5255 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5256 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5257 char *p;
5258 short offset;
5259 /* The value to write might be 32 or 64 bits, depending on L1's long
5260 * mode, and eventually we need to write that into a field of several
5261 * possible lengths. The code below first zero-extends the value to 64
5262 * bit (field_value), and then copies only the approriate number of
5263 * bits into the vmcs12 field.
5264 */
5265 u64 field_value = 0;
5266 struct x86_exception e;
5267
5268 if (!nested_vmx_check_permission(vcpu) ||
5269 !nested_vmx_check_vmcs12(vcpu))
5270 return 1;
5271
5272 if (vmx_instruction_info & (1u << 10))
5273 field_value = kvm_register_read(vcpu,
5274 (((vmx_instruction_info) >> 3) & 0xf));
5275 else {
5276 if (get_vmx_mem_address(vcpu, exit_qualification,
5277 vmx_instruction_info, &gva))
5278 return 1;
5279 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5280 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5281 kvm_inject_page_fault(vcpu, &e);
5282 return 1;
5283 }
5284 }
5285
5286
5287 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5288 if (vmcs_field_readonly(field)) {
5289 nested_vmx_failValid(vcpu,
5290 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5291 skip_emulated_instruction(vcpu);
5292 return 1;
5293 }
5294
5295 offset = vmcs_field_to_offset(field);
5296 if (offset < 0) {
5297 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5298 skip_emulated_instruction(vcpu);
5299 return 1;
5300 }
5301 p = ((char *) get_vmcs12(vcpu)) + offset;
5302
5303 switch (vmcs_field_type(field)) {
5304 case VMCS_FIELD_TYPE_U16:
5305 *(u16 *)p = field_value;
5306 break;
5307 case VMCS_FIELD_TYPE_U32:
5308 *(u32 *)p = field_value;
5309 break;
5310 case VMCS_FIELD_TYPE_U64:
5311 *(u64 *)p = field_value;
5312 break;
5313 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5314 *(natural_width *)p = field_value;
5315 break;
5316 default:
5317 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5318 skip_emulated_instruction(vcpu);
5319 return 1;
5320 }
5321
5322 nested_vmx_succeed(vcpu);
5323 skip_emulated_instruction(vcpu);
5324 return 1;
5325}
5326
63846663
NHE		 5327/* Emulate the VMPTRLD instruction */
5328static int handle_vmptrld(struct kvm_vcpu *vcpu)
5329{
5330 struct vcpu_vmx *vmx = to_vmx(vcpu);
5331 gva_t gva;
5332 gpa_t vmptr;
5333 struct x86_exception e;
5334
5335 if (!nested_vmx_check_permission(vcpu))
5336 return 1;
5337
5338 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5339 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5340 return 1;
5341
5342 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5343 sizeof(vmptr), &e)) {
5344 kvm_inject_page_fault(vcpu, &e);
5345 return 1;
5346 }
5347
5348 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5349 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5350 skip_emulated_instruction(vcpu);
5351 return 1;
5352 }
5353
5354 if (vmx->nested.current_vmptr != vmptr) {
5355 struct vmcs12 *new_vmcs12;
5356 struct page *page;
5357 page = nested_get_page(vcpu, vmptr);
5358 if (page == NULL) {
5359 nested_vmx_failInvalid(vcpu);
5360 skip_emulated_instruction(vcpu);
5361 return 1;
5362 }
5363 new_vmcs12 = kmap(page);
5364 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5365 kunmap(page);
5366 nested_release_page_clean(page);
5367 nested_vmx_failValid(vcpu,
5368 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5369 skip_emulated_instruction(vcpu);
5370 return 1;
5371 }
5372 if (vmx->nested.current_vmptr != -1ull) {
5373 kunmap(vmx->nested.current_vmcs12_page);
5374 nested_release_page(vmx->nested.current_vmcs12_page);
5375 }
5376
5377 vmx->nested.current_vmptr = vmptr;
5378 vmx->nested.current_vmcs12 = new_vmcs12;
5379 vmx->nested.current_vmcs12_page = page;
5380 }
5381
5382 nested_vmx_succeed(vcpu);
5383 skip_emulated_instruction(vcpu);
5384 return 1;
5385}
5386
6a4d7550
NHE		 5387/* Emulate the VMPTRST instruction */
5388static int handle_vmptrst(struct kvm_vcpu *vcpu)
5389{
5390 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5391 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5392 gva_t vmcs_gva;
5393 struct x86_exception e;
5394
5395 if (!nested_vmx_check_permission(vcpu))
5396 return 1;
5397
5398 if (get_vmx_mem_address(vcpu, exit_qualification,
5399 vmx_instruction_info, &vmcs_gva))
5400 return 1;
5401 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5402 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5403 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5404 sizeof(u64), &e)) {
5405 kvm_inject_page_fault(vcpu, &e);
5406 return 1;
5407 }
5408 nested_vmx_succeed(vcpu);
5409 skip_emulated_instruction(vcpu);
5410 return 1;
5411}
5412
6aa8b732
AK		 5413/*
5414 * The exit handlers return 1 if the exit was handled fully and guest execution
5415 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5416 * to be done to userspace and return 0.
5417 */
851ba692 5418static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 5419 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5420 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 5421 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 5422 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 5423 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 5424 [EXIT_REASON_CR_ACCESS] = handle_cr,
5425 [EXIT_REASON_DR_ACCESS] = handle_dr,
5426 [EXIT_REASON_CPUID] = handle_cpuid,
5427 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5428 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5429 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5430 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 5431 [EXIT_REASON_INVD] = handle_invd,
a7052897 5432 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 5433 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 5434 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 5435 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 5436 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 5437 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 5438 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 5439 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 5440 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 5441 [EXIT_REASON_VMOFF] = handle_vmoff,
5442 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 5443 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5444 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 5445 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 5446 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 5447 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 5448 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 5449 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5450 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 5451 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 5452 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5453 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 5454};
5455
5456static const int kvm_vmx_max_exit_handlers =
50a3485c 5457 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 5458
644d711a
NHE		 5459/*
5460 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5461 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5462 * disinterest in the current event (read or write a specific MSR) by using an
5463 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5464 */
5465static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5466 struct vmcs12 *vmcs12, u32 exit_reason)
5467{
5468 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5469 gpa_t bitmap;
5470
5471 if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5472 return 1;
5473
5474 /*
5475 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5476 * for the four combinations of read/write and low/high MSR numbers.
5477 * First we need to figure out which of the four to use:
5478 */
5479 bitmap = vmcs12->msr_bitmap;
5480 if (exit_reason == EXIT_REASON_MSR_WRITE)
5481 bitmap += 2048;
5482 if (msr_index >= 0xc0000000) {
5483 msr_index -= 0xc0000000;
5484 bitmap += 1024;
5485 }
5486
5487 /* Then read the msr_index'th bit from this bitmap: */
5488 if (msr_index < 1024*8) {
5489 unsigned char b;
5490 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5491 return 1 & (b >> (msr_index & 7));
5492 } else
5493 return 1; /* let L1 handle the wrong parameter */
5494}
5495
5496/*
5497 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5498 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5499 * intercept (via guest_host_mask etc.) the current event.
5500 */
5501static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5502 struct vmcs12 *vmcs12)
5503{
5504 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5505 int cr = exit_qualification & 15;
5506 int reg = (exit_qualification >> 8) & 15;
5507 unsigned long val = kvm_register_read(vcpu, reg);
5508
5509 switch ((exit_qualification >> 4) & 3) {
5510 case 0: /* mov to cr */
5511 switch (cr) {
5512 case 0:
5513 if (vmcs12->cr0_guest_host_mask &
5514 (val ^ vmcs12->cr0_read_shadow))
5515 return 1;
5516 break;
5517 case 3:
5518 if ((vmcs12->cr3_target_count >= 1 &&
5519 vmcs12->cr3_target_value0 == val) ||
5520 (vmcs12->cr3_target_count >= 2 &&
5521 vmcs12->cr3_target_value1 == val) ||
5522 (vmcs12->cr3_target_count >= 3 &&
5523 vmcs12->cr3_target_value2 == val) ||
5524 (vmcs12->cr3_target_count >= 4 &&
5525 vmcs12->cr3_target_value3 == val))
5526 return 0;
5527 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5528 return 1;
5529 break;
5530 case 4:
5531 if (vmcs12->cr4_guest_host_mask &
5532 (vmcs12->cr4_read_shadow ^ val))
5533 return 1;
5534 break;
5535 case 8:
5536 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5537 return 1;
5538 break;
5539 }
5540 break;
5541 case 2: /* clts */
5542 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5543 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5544 return 1;
5545 break;
5546 case 1: /* mov from cr */
5547 switch (cr) {
5548 case 3:
5549 if (vmcs12->cpu_based_vm_exec_control &
5550 CPU_BASED_CR3_STORE_EXITING)
5551 return 1;
5552 break;
5553 case 8:
5554 if (vmcs12->cpu_based_vm_exec_control &
5555 CPU_BASED_CR8_STORE_EXITING)
5556 return 1;
5557 break;
5558 }
5559 break;
5560 case 3: /* lmsw */
5561 /*
5562 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5563 * cr0. Other attempted changes are ignored, with no exit.
5564 */
5565 if (vmcs12->cr0_guest_host_mask & 0xe &
5566 (val ^ vmcs12->cr0_read_shadow))
5567 return 1;
5568 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5569 !(vmcs12->cr0_read_shadow & 0x1) &&
5570 (val & 0x1))
5571 return 1;
5572 break;
5573 }
5574 return 0;
5575}
5576
5577/*
5578 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5579 * should handle it ourselves in L0 (and then continue L2). Only call this
5580 * when in is_guest_mode (L2).
5581 */
5582static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5583{
5584 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5585 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5586 struct vcpu_vmx *vmx = to_vmx(vcpu);
5587 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5588
5589 if (vmx->nested.nested_run_pending)
5590 return 0;
5591
5592 if (unlikely(vmx->fail)) {
5593 printk(KERN_INFO "%s failed vm entry %x\n",
5594 __func__, vmcs_read32(VM_INSTRUCTION_ERROR));
5595 return 1;
5596 }
5597
5598 switch (exit_reason) {
5599 case EXIT_REASON_EXCEPTION_NMI:
5600 if (!is_exception(intr_info))
5601 return 0;
5602 else if (is_page_fault(intr_info))
5603 return enable_ept;
5604 return vmcs12->exception_bitmap &
5605 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5606 case EXIT_REASON_EXTERNAL_INTERRUPT:
5607 return 0;
5608 case EXIT_REASON_TRIPLE_FAULT:
5609 return 1;
5610 case EXIT_REASON_PENDING_INTERRUPT:
5611 case EXIT_REASON_NMI_WINDOW:
5612 /*
5613 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5614 * (aka Interrupt Window Exiting) only when L1 turned it on,
5615 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5616 * Same for NMI Window Exiting.
5617 */
5618 return 1;
5619 case EXIT_REASON_TASK_SWITCH:
5620 return 1;
5621 case EXIT_REASON_CPUID:
5622 return 1;
5623 case EXIT_REASON_HLT:
5624 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5625 case EXIT_REASON_INVD:
5626 return 1;
5627 case EXIT_REASON_INVLPG:
5628 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5629 case EXIT_REASON_RDPMC:
5630 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5631 case EXIT_REASON_RDTSC:
5632 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5633 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5634 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5635 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5636 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5637 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5638 /*
5639 * VMX instructions trap unconditionally. This allows L1 to
5640 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5641 */
5642 return 1;
5643 case EXIT_REASON_CR_ACCESS:
5644 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5645 case EXIT_REASON_DR_ACCESS:
5646 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5647 case EXIT_REASON_IO_INSTRUCTION:
5648 /* TODO: support IO bitmaps */
5649 return 1;
5650 case EXIT_REASON_MSR_READ:
5651 case EXIT_REASON_MSR_WRITE:
5652 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5653 case EXIT_REASON_INVALID_STATE:
5654 return 1;
5655 case EXIT_REASON_MWAIT_INSTRUCTION:
5656 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5657 case EXIT_REASON_MONITOR_INSTRUCTION:
5658 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5659 case EXIT_REASON_PAUSE_INSTRUCTION:
5660 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5661 nested_cpu_has2(vmcs12,
5662 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5663 case EXIT_REASON_MCE_DURING_VMENTRY:
5664 return 0;
5665 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5666 return 1;
5667 case EXIT_REASON_APIC_ACCESS:
5668 return nested_cpu_has2(vmcs12,
5669 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5670 case EXIT_REASON_EPT_VIOLATION:
5671 case EXIT_REASON_EPT_MISCONFIG:
5672 return 0;
5673 case EXIT_REASON_WBINVD:
5674 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5675 case EXIT_REASON_XSETBV:
5676 return 1;
5677 default:
5678 return 1;
5679 }
5680}
5681
586f9607
AK		 5682static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5683{
5684 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5685 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5686}
5687
6aa8b732
AK		 5688/*
5689 * The guest has exited. See if we can fix it or if we need userspace
5690 * assistance.
5691 */
851ba692 5692static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 5693{
29bd8a78 5694 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 5695 u32 exit_reason = vmx->exit_reason;
1155f76a 5696 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 5697
aa17911e 5698 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
2714d1d3 5699
80ced186
MG		 5700 /* If guest state is invalid, start emulating */
5701 if (vmx->emulation_required && emulate_invalid_guest_state)
5702 return handle_invalid_guest_state(vcpu);
1d5a4d9b 5703
b6f1250e
NHE		 5704 /*
5705 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5706 * we did not inject a still-pending event to L1 now because of
5707 * nested_run_pending, we need to re-enable this bit.
5708 */
5709 if (vmx->nested.nested_run_pending)
5710 kvm_make_request(KVM_REQ_EVENT, vcpu);
5711
509c75ea
NHE		 5712 if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5713 exit_reason == EXIT_REASON_VMRESUME))
644d711a
NHE		 5714 vmx->nested.nested_run_pending = 1;
5715 else
5716 vmx->nested.nested_run_pending = 0;
5717
5718 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5719 nested_vmx_vmexit(vcpu);
5720 return 1;
5721 }
5722
5120702e
MG		 5723 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5724 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5725 vcpu->run->fail_entry.hardware_entry_failure_reason
5726 = exit_reason;
5727 return 0;
5728 }
5729
29bd8a78 5730 if (unlikely(vmx->fail)) {
851ba692
AK		 5731 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5732 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 5733 = vmcs_read32(VM_INSTRUCTION_ERROR);
5734 return 0;
5735 }
6aa8b732 5736
d77c26fc 5737 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 5738 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 5739 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5740 exit_reason != EXIT_REASON_TASK_SWITCH))
5741 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5742 "(0x%x) and exit reason is 0x%x\n",
5743 __func__, vectoring_info, exit_reason);
3b86cd99 5744
644d711a
NHE		 5745 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5746 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5747 get_vmcs12(vcpu), vcpu)))) {
c4282df9 5748 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 5749 vmx->soft_vnmi_blocked = 0;
3b86cd99 5750 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 5751 vcpu->arch.nmi_pending) {
3b86cd99
JK		 5752 /*
5753 * This CPU don't support us in finding the end of an
5754 * NMI-blocked window if the guest runs with IRQs
5755 * disabled. So we pull the trigger after 1 s of
5756 * futile waiting, but inform the user about this.
5757 */
5758 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5759 "state on VCPU %d after 1 s timeout\n",
5760 __func__, vcpu->vcpu_id);
5761 vmx->soft_vnmi_blocked = 0;
3b86cd99 5762 }
3b86cd99
JK		 5763 }
5764
6aa8b732
AK		 5765 if (exit_reason < kvm_vmx_max_exit_handlers
5766 && kvm_vmx_exit_handlers[exit_reason])
851ba692 5767 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 5768 else {
851ba692
AK		 5769 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5770 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 5771 }
5772 return 0;
5773}
5774
95ba8273 5775static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 5776{
95ba8273 5777 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 5778 vmcs_write32(TPR_THRESHOLD, 0);
5779 return;
5780 }
5781
95ba8273 5782 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 5783}
5784
51aa01d1 5785static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 5786{
00eba012
AK		 5787 u32 exit_intr_info;
5788
5789 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
5790 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
5791 return;
5792
c5ca8e57 5793 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 5794 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 5795
5796 /* Handle machine checks before interrupts are enabled */
00eba012 5797 if (is_machine_check(exit_intr_info))
a0861c02
AK		 5798 kvm_machine_check();
5799
20f65983 5800 /* We need to handle NMIs before interrupts are enabled */
00eba012 5801 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 5802 (exit_intr_info & INTR_INFO_VALID_MASK)) {
5803 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 5804 asm("int $2");
ff9d07a0
ZY		 5805 kvm_after_handle_nmi(&vmx->vcpu);
5806 }
51aa01d1 5807}
20f65983 5808
51aa01d1
AK		 5809static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
5810{
c5ca8e57 5811 u32 exit_intr_info;
51aa01d1
AK		 5812 bool unblock_nmi;
5813 u8 vector;
5814 bool idtv_info_valid;
5815
5816 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 5817
cf393f75 5818 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 5819 if (vmx->nmi_known_unmasked)
5820 return;
c5ca8e57
AK		 5821 /*
5822 * Can't use vmx->exit_intr_info since we're not sure what
5823 * the exit reason is.
5824 */
5825 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 5826 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
5827 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
5828 /*
7b4a25cb 5829 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 5830 * Re-set bit "block by NMI" before VM entry if vmexit caused by
5831 * a guest IRET fault.
7b4a25cb
GN		 5832 * SDM 3: 23.2.2 (September 2008)
5833 * Bit 12 is undefined in any of the following cases:
5834 * If the VM exit sets the valid bit in the IDT-vectoring
5835 * information field.
5836 * If the VM exit is due to a double fault.
cf393f75 5837 */
7b4a25cb
GN		 5838 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
5839 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 5840 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5841 GUEST_INTR_STATE_NMI);
9d58b931
AK		 5842 else
5843 vmx->nmi_known_unmasked =
5844 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
5845 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 5846 } else if (unlikely(vmx->soft_vnmi_blocked))
5847 vmx->vnmi_blocked_time +=
5848 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 5849}
5850
83422e17
AK		 5851static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
5852 u32 idt_vectoring_info,
5853 int instr_len_field,
5854 int error_code_field)
51aa01d1 5855{
51aa01d1
AK		 5856 u8 vector;
5857 int type;
5858 bool idtv_info_valid;
5859
5860 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 5861
37b96e98
GN		 5862 vmx->vcpu.arch.nmi_injected = false;
5863 kvm_clear_exception_queue(&vmx->vcpu);
5864 kvm_clear_interrupt_queue(&vmx->vcpu);
5865
5866 if (!idtv_info_valid)
5867 return;
5868
3842d135
AK		 5869 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5870
668f612f
AK		 5871 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
5872 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 5873
64a7ec06 5874 switch (type) {
37b96e98
GN		 5875 case INTR_TYPE_NMI_INTR:
5876 vmx->vcpu.arch.nmi_injected = true;
668f612f 5877 /*
7b4a25cb 5878 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 5879 * Clear bit "block by NMI" before VM entry if a NMI
5880 * delivery faulted.
668f612f 5881 */
654f06fc 5882 vmx_set_nmi_mask(&vmx->vcpu, false);
37b96e98 5883 break;
37b96e98 5884 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f 5885 vmx->vcpu.arch.event_exit_inst_len =
83422e17 5886 vmcs_read32(instr_len_field);
66fd3f7f
GN		 5887 /* fall through */
5888 case INTR_TYPE_HARD_EXCEPTION:
35920a35 5889 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 5890 u32 err = vmcs_read32(error_code_field);
37b96e98 5891 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 5892 } else
5893 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 5894 break;
66fd3f7f
GN		 5895 case INTR_TYPE_SOFT_INTR:
5896 vmx->vcpu.arch.event_exit_inst_len =
83422e17 5897 vmcs_read32(instr_len_field);
66fd3f7f 5898 /* fall through */
37b96e98 5899 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 5900 kvm_queue_interrupt(&vmx->vcpu, vector,
5901 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 5902 break;
5903 default:
5904 break;
f7d9238f 5905 }
cf393f75
AK		 5906}
5907
83422e17
AK		 5908static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
5909{
66c78ae4
NHE		 5910 if (is_guest_mode(&vmx->vcpu))
5911 return;
83422e17
AK		 5912 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
5913 VM_EXIT_INSTRUCTION_LEN,
5914 IDT_VECTORING_ERROR_CODE);
5915}
5916
b463a6f7
AK		 5917static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
5918{
66c78ae4
NHE		 5919 if (is_guest_mode(vcpu))
5920 return;
b463a6f7
AK		 5921 __vmx_complete_interrupts(to_vmx(vcpu),
5922 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5923 VM_ENTRY_INSTRUCTION_LEN,
5924 VM_ENTRY_EXCEPTION_ERROR_CODE);
5925
5926 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
5927}
5928
c801949d
AK		 5929#ifdef CONFIG_X86_64
5930#define R "r"
5931#define Q "q"
5932#else
5933#define R "e"
5934#define Q "l"
5935#endif
5936
a3b5ba49 5937static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 5938{
a2fa3e9f 5939 struct vcpu_vmx *vmx = to_vmx(vcpu);
104f226b 5940
66c78ae4
NHE		 5941 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
5942 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5943 if (vmcs12->idt_vectoring_info_field &
5944 VECTORING_INFO_VALID_MASK) {
5945 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5946 vmcs12->idt_vectoring_info_field);
5947 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5948 vmcs12->vm_exit_instruction_len);
5949 if (vmcs12->idt_vectoring_info_field &
5950 VECTORING_INFO_DELIVER_CODE_MASK)
5951 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
5952 vmcs12->idt_vectoring_error_code);
5953 }
5954 }
5955
104f226b
AK		 5956 /* Record the guest's net vcpu time for enforced NMI injections. */
5957 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
5958 vmx->entry_time = ktime_get();
5959
5960 /* Don't enter VMX if guest state is invalid, let the exit handler
5961 start emulation until we arrive back to a valid state */
5962 if (vmx->emulation_required && emulate_invalid_guest_state)
5963 return;
5964
5965 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
5966 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
5967 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
5968 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
5969
5970 /* When single-stepping over STI and MOV SS, we must clear the
5971 * corresponding interruptibility bits in the guest state. Otherwise
5972 * vmentry fails as it then expects bit 14 (BS) in pending debug
5973 * exceptions being set, but that's not correct for the guest debugging
5974 * case. */
5975 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5976 vmx_set_interrupt_shadow(vcpu, 0);
5977
d462b819 5978 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 5979 asm(
6aa8b732 5980 /* Store host registers */
c801949d 5981 "push %%"R"dx; push %%"R"bp;"
40712fae 5982 "push %%"R"cx \n\t" /* placeholder for guest rcx */
c801949d 5983 "push %%"R"cx \n\t"
313dbd49
AK		 5984 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
5985 "je 1f \n\t"
5986 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 5987 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 5988 "1: \n\t"
d3edefc0
AK		 5989 /* Reload cr2 if changed */
5990 "mov %c[cr2](%0), %%"R"ax \n\t"
5991 "mov %%cr2, %%"R"dx \n\t"
5992 "cmp %%"R"ax, %%"R"dx \n\t"
5993 "je 2f \n\t"
5994 "mov %%"R"ax, %%cr2 \n\t"
5995 "2: \n\t"
6aa8b732 5996 /* Check if vmlaunch of vmresume is needed */
e08aa78a 5997 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 5998 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 5999 "mov %c[rax](%0), %%"R"ax \n\t"
6000 "mov %c[rbx](%0), %%"R"bx \n\t"
6001 "mov %c[rdx](%0), %%"R"dx \n\t"
6002 "mov %c[rsi](%0), %%"R"si \n\t"
6003 "mov %c[rdi](%0), %%"R"di \n\t"
6004 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 6005#ifdef CONFIG_X86_64
e08aa78a
AK		 6006 "mov %c[r8](%0), %%r8 \n\t"
6007 "mov %c[r9](%0), %%r9 \n\t"
6008 "mov %c[r10](%0), %%r10 \n\t"
6009 "mov %c[r11](%0), %%r11 \n\t"
6010 "mov %c[r12](%0), %%r12 \n\t"
6011 "mov %c[r13](%0), %%r13 \n\t"
6012 "mov %c[r14](%0), %%r14 \n\t"
6013 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 6014#endif
c801949d
AK		 6015 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
6016
6aa8b732 6017 /* Enter guest mode */
cd2276a7 6018 "jne .Llaunched \n\t"
4ecac3fd 6019 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 6020 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 6021 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 6022 ".Lkvm_vmx_return: "
6aa8b732 6023 /* Save guest registers, load host registers, keep flags */
40712fae
AK		 6024 "mov %0, %c[wordsize](%%"R"sp) \n\t"
6025 "pop %0 \n\t"
c801949d
AK		 6026 "mov %%"R"ax, %c[rax](%0) \n\t"
6027 "mov %%"R"bx, %c[rbx](%0) \n\t"
1c696d0e 6028 "pop"Q" %c[rcx](%0) \n\t"
c801949d
AK		 6029 "mov %%"R"dx, %c[rdx](%0) \n\t"
6030 "mov %%"R"si, %c[rsi](%0) \n\t"
6031 "mov %%"R"di, %c[rdi](%0) \n\t"
6032 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 6033#ifdef CONFIG_X86_64
e08aa78a
AK		 6034 "mov %%r8, %c[r8](%0) \n\t"
6035 "mov %%r9, %c[r9](%0) \n\t"
6036 "mov %%r10, %c[r10](%0) \n\t"
6037 "mov %%r11, %c[r11](%0) \n\t"
6038 "mov %%r12, %c[r12](%0) \n\t"
6039 "mov %%r13, %c[r13](%0) \n\t"
6040 "mov %%r14, %c[r14](%0) \n\t"
6041 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 6042#endif
c801949d
AK		 6043 "mov %%cr2, %%"R"ax \n\t"
6044 "mov %%"R"ax, %c[cr2](%0) \n\t"
6045
1c696d0e 6046 "pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 6047 "setbe %c[fail](%0) \n\t"
6048 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 6049 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 6050 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 6051 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 6052 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6053 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6054 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6055 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6056 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6057 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6058 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 6059#ifdef CONFIG_X86_64
ad312c7c
ZX		 6060 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6061 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6062 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6063 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6064 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6065 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6066 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6067 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 6068#endif
40712fae
AK		 6069 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6070 [wordsize]"i"(sizeof(ulong))
c2036300 6071 : "cc", "memory"
07d6f555 6072 , R"ax", R"bx", R"di", R"si"
c2036300 6073#ifdef CONFIG_X86_64
c2036300
LV		 6074 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6075#endif
6076 );
6aa8b732 6077
6de4f3ad 6078 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 6079 | (1 << VCPU_EXREG_RFLAGS)
69c73028 6080 | (1 << VCPU_EXREG_CPL)
aff48baa 6081 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 6082 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 6083 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 6084 vcpu->arch.regs_dirty = 0;
6085
1155f76a
AK		 6086 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6087
66c78ae4
NHE		 6088 if (is_guest_mode(vcpu)) {
6089 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6090 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6091 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6092 vmcs12->idt_vectoring_error_code =
6093 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6094 vmcs12->vm_exit_instruction_len =
6095 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6096 }
6097 }
6098
d77c26fc 6099 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
d462b819 6100 vmx->loaded_vmcs->launched = 1;
1b6269db 6101
51aa01d1 6102 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
51aa01d1
AK		 6103
6104 vmx_complete_atomic_exit(vmx);
6105 vmx_recover_nmi_blocking(vmx);
cf393f75 6106 vmx_complete_interrupts(vmx);
6aa8b732
AK		 6107}
6108
c801949d
AK		 6109#undef R
6110#undef Q
6111
6aa8b732
AK		 6112static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6113{
fb3f0f51
RR		 6114 struct vcpu_vmx *vmx = to_vmx(vcpu);
6115
cdbecfc3 6116 free_vpid(vmx);
ec378aee 6117 free_nested(vmx);
d462b819 6118 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 6119 kfree(vmx->guest_msrs);
6120 kvm_vcpu_uninit(vcpu);
a4770347 6121 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 6122}
6123
fb3f0f51 6124static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 6125{
fb3f0f51 6126 int err;
c16f862d 6127 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 6128 int cpu;
6aa8b732 6129
a2fa3e9f 6130 if (!vmx)
fb3f0f51
RR		 6131 return ERR_PTR(-ENOMEM);
6132
2384d2b3
SY		 6133 allocate_vpid(vmx);
6134
fb3f0f51
RR		 6135 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6136 if (err)
6137 goto free_vcpu;
965b58a5 6138
a2fa3e9f 6139 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 6140 err = -ENOMEM;
fb3f0f51 6141 if (!vmx->guest_msrs) {
fb3f0f51
RR		 6142 goto uninit_vcpu;
6143 }
965b58a5 6144
d462b819
NHE		 6145 vmx->loaded_vmcs = &vmx->vmcs01;
6146 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6147 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 6148 goto free_msrs;
d462b819
NHE		 6149 if (!vmm_exclusive)
6150 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6151 loaded_vmcs_init(vmx->loaded_vmcs);
6152 if (!vmm_exclusive)
6153 kvm_cpu_vmxoff();
a2fa3e9f 6154
15ad7146
AK		 6155 cpu = get_cpu();
6156 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 6157 vmx->vcpu.cpu = cpu;
8b9cf98c 6158 err = vmx_vcpu_setup(vmx);
fb3f0f51 6159 vmx_vcpu_put(&vmx->vcpu);
15ad7146 6160 put_cpu();
fb3f0f51
RR		 6161 if (err)
6162 goto free_vmcs;
5e4a0b3c 6163 if (vm_need_virtualize_apic_accesses(kvm))
be6d05cf
JK		 6164 err = alloc_apic_access_page(kvm);
6165 if (err)
5e4a0b3c 6166 goto free_vmcs;
fb3f0f51 6167
b927a3ce
SY		 6168 if (enable_ept) {
6169 if (!kvm->arch.ept_identity_map_addr)
6170 kvm->arch.ept_identity_map_addr =
6171 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 6172 err = -ENOMEM;
b7ebfb05
SY		 6173 if (alloc_identity_pagetable(kvm) != 0)
6174 goto free_vmcs;
93ea5388
GN		 6175 if (!init_rmode_identity_map(kvm))
6176 goto free_vmcs;
b927a3ce 6177 }
b7ebfb05 6178
a9d30f33
NHE		 6179 vmx->nested.current_vmptr = -1ull;
6180 vmx->nested.current_vmcs12 = NULL;
6181
fb3f0f51
RR		 6182 return &vmx->vcpu;
6183
6184free_vmcs:
d462b819 6185 free_vmcs(vmx->loaded_vmcs->vmcs);
fb3f0f51 6186free_msrs:
fb3f0f51
RR		 6187 kfree(vmx->guest_msrs);
6188uninit_vcpu:
6189 kvm_vcpu_uninit(&vmx->vcpu);
6190free_vcpu:
cdbecfc3 6191 free_vpid(vmx);
a4770347 6192 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 6193 return ERR_PTR(err);
6aa8b732
AK		 6194}
6195
002c7f7c
YS		 6196static void __init vmx_check_processor_compat(void *rtn)
6197{
6198 struct vmcs_config vmcs_conf;
6199
6200 *(int *)rtn = 0;
6201 if (setup_vmcs_config(&vmcs_conf) < 0)
6202 *(int *)rtn = -EIO;
6203 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6204 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6205 smp_processor_id());
6206 *(int *)rtn = -EIO;
6207 }
6208}
6209
67253af5
SY		 6210static int get_ept_level(void)
6211{
6212 return VMX_EPT_DEFAULT_GAW + 1;
6213}
6214
4b12f0de 6215static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 6216{
4b12f0de
SY		 6217 u64 ret;
6218
522c68c4
SY		 6219 /* For VT-d and EPT combination
6220 * 1. MMIO: always map as UC
6221 * 2. EPT with VT-d:
6222 * a. VT-d without snooping control feature: can't guarantee the
6223 * result, try to trust guest.
6224 * b. VT-d with snooping control feature: snooping control feature of
6225 * VT-d engine can guarantee the cache correctness. Just set it
6226 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 6227 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 6228 * consistent with host MTRR
6229 */
4b12f0de
SY		 6230 if (is_mmio)
6231 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 6232 else if (vcpu->kvm->arch.iommu_domain &&
6233 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6234 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6235 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 6236 else
522c68c4 6237 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 6238 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 6239
6240 return ret;
64d4d521
SY		 6241}
6242
17cc3935 6243static int vmx_get_lpage_level(void)
344f414f 6244{
878403b7
SY		 6245 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6246 return PT_DIRECTORY_LEVEL;
6247 else
6248 /* For shadow and EPT supported 1GB page */
6249 return PT_PDPE_LEVEL;
344f414f
JR		 6250}
6251
0e851880
SY		 6252static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6253{
4e47c7a6
SY		 6254 struct kvm_cpuid_entry2 *best;
6255 struct vcpu_vmx *vmx = to_vmx(vcpu);
6256 u32 exec_control;
6257
6258 vmx->rdtscp_enabled = false;
6259 if (vmx_rdtscp_supported()) {
6260 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6261 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6262 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6263 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6264 vmx->rdtscp_enabled = true;
6265 else {
6266 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6267 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6268 exec_control);
6269 }
6270 }
6271 }
0e851880
SY		 6272}
6273
d4330ef2
JR		 6274static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6275{
7b8050f5
NHE		 6276 if (func == 1 && nested)
6277 entry->ecx |= bit(X86_FEATURE_VMX);
d4330ef2
JR		 6278}
6279
fe3ef05c
NHE		 6280/*
6281 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6282 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6283 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6284 * guest in a way that will both be appropriate to L1's requests, and our
6285 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6286 * function also has additional necessary side-effects, like setting various
6287 * vcpu->arch fields.
6288 */
6289static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6290{
6291 struct vcpu_vmx *vmx = to_vmx(vcpu);
6292 u32 exec_control;
6293
6294 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6295 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6296 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6297 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6298 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6299 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6300 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6301 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6302 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6303 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6304 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6305 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6306 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6307 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6308 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6309 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6310 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6311 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6312 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6313 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6314 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6315 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6316 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6317 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6318 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6319 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6320 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6321 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6322 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6323 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6324 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6325 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6326 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6327 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6328 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6329 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6330
6331 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6332 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6333 vmcs12->vm_entry_intr_info_field);
6334 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6335 vmcs12->vm_entry_exception_error_code);
6336 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6337 vmcs12->vm_entry_instruction_len);
6338 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6339 vmcs12->guest_interruptibility_info);
6340 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6341 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6342 vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6343 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6344 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6345 vmcs12->guest_pending_dbg_exceptions);
6346 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6347 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6348
6349 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6350
6351 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6352 (vmcs_config.pin_based_exec_ctrl |
6353 vmcs12->pin_based_vm_exec_control));
6354
6355 /*
6356 * Whether page-faults are trapped is determined by a combination of
6357 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6358 * If enable_ept, L0 doesn't care about page faults and we should
6359 * set all of these to L1's desires. However, if !enable_ept, L0 does
6360 * care about (at least some) page faults, and because it is not easy
6361 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6362 * to exit on each and every L2 page fault. This is done by setting
6363 * MASK=MATCH=0 and (see below) EB.PF=1.
6364 * Note that below we don't need special code to set EB.PF beyond the
6365 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6366 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6367 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6368 *
6369 * A problem with this approach (when !enable_ept) is that L1 may be
6370 * injected with more page faults than it asked for. This could have
6371 * caused problems, but in practice existing hypervisors don't care.
6372 * To fix this, we will need to emulate the PFEC checking (on the L1
6373 * page tables), using walk_addr(), when injecting PFs to L1.
6374 */
6375 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6376 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6377 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6378 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6379
6380 if (cpu_has_secondary_exec_ctrls()) {
6381 u32 exec_control = vmx_secondary_exec_control(vmx);
6382 if (!vmx->rdtscp_enabled)
6383 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6384 /* Take the following fields only from vmcs12 */
6385 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6386 if (nested_cpu_has(vmcs12,
6387 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6388 exec_control |= vmcs12->secondary_vm_exec_control;
6389
6390 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6391 /*
6392 * Translate L1 physical address to host physical
6393 * address for vmcs02. Keep the page pinned, so this
6394 * physical address remains valid. We keep a reference
6395 * to it so we can release it later.
6396 */
6397 if (vmx->nested.apic_access_page) /* shouldn't happen */
6398 nested_release_page(vmx->nested.apic_access_page);
6399 vmx->nested.apic_access_page =
6400 nested_get_page(vcpu, vmcs12->apic_access_addr);
6401 /*
6402 * If translation failed, no matter: This feature asks
6403 * to exit when accessing the given address, and if it
6404 * can never be accessed, this feature won't do
6405 * anything anyway.
6406 */
6407 if (!vmx->nested.apic_access_page)
6408 exec_control &=
6409 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6410 else
6411 vmcs_write64(APIC_ACCESS_ADDR,
6412 page_to_phys(vmx->nested.apic_access_page));
6413 }
6414
6415 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6416 }
6417
6418
6419 /*
6420 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6421 * Some constant fields are set here by vmx_set_constant_host_state().
6422 * Other fields are different per CPU, and will be set later when
6423 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6424 */
6425 vmx_set_constant_host_state();
6426
6427 /*
6428 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6429 * entry, but only if the current (host) sp changed from the value
6430 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6431 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6432 * here we just force the write to happen on entry.
6433 */
6434 vmx->host_rsp = 0;
6435
6436 exec_control = vmx_exec_control(vmx); /* L0's desires */
6437 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6438 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6439 exec_control &= ~CPU_BASED_TPR_SHADOW;
6440 exec_control |= vmcs12->cpu_based_vm_exec_control;
6441 /*
6442 * Merging of IO and MSR bitmaps not currently supported.
6443 * Rather, exit every time.
6444 */
6445 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6446 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6447 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6448
6449 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6450
6451 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6452 * bitwise-or of what L1 wants to trap for L2, and what we want to
6453 * trap. Note that CR0.TS also needs updating - we do this later.
6454 */
6455 update_exception_bitmap(vcpu);
6456 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6457 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6458
6459 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6460 vmcs_write32(VM_EXIT_CONTROLS,
6461 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6462 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6463 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6464
6465 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6466 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6467 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6468 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6469
6470
6471 set_cr4_guest_host_mask(vmx);
6472
6473 vmcs_write64(TSC_OFFSET,
6474 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6475
6476 if (enable_vpid) {
6477 /*
6478 * Trivially support vpid by letting L2s share their parent
6479 * L1's vpid. TODO: move to a more elaborate solution, giving
6480 * each L2 its own vpid and exposing the vpid feature to L1.
6481 */
6482 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6483 vmx_flush_tlb(vcpu);
6484 }
6485
6486 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6487 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6488 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6489 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6490 else
6491 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6492 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6493 vmx_set_efer(vcpu, vcpu->arch.efer);
6494
6495 /*
6496 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6497 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6498 * The CR0_READ_SHADOW is what L2 should have expected to read given
6499 * the specifications by L1; It's not enough to take
6500 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6501 * have more bits than L1 expected.
6502 */
6503 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6504 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6505
6506 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6507 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6508
6509 /* shadow page tables on either EPT or shadow page tables */
6510 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6511 kvm_mmu_reset_context(vcpu);
6512
6513 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6514 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6515}
6516
cd232ad0
NHE		 6517/*
6518 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6519 * for running an L2 nested guest.
6520 */
6521static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6522{
6523 struct vmcs12 *vmcs12;
6524 struct vcpu_vmx *vmx = to_vmx(vcpu);
6525 int cpu;
6526 struct loaded_vmcs *vmcs02;
6527
6528 if (!nested_vmx_check_permission(vcpu) ||
6529 !nested_vmx_check_vmcs12(vcpu))
6530 return 1;
6531
6532 skip_emulated_instruction(vcpu);
6533 vmcs12 = get_vmcs12(vcpu);
6534
7c177938
NHE		 6535 /*
6536 * The nested entry process starts with enforcing various prerequisites
6537 * on vmcs12 as required by the Intel SDM, and act appropriately when
6538 * they fail: As the SDM explains, some conditions should cause the
6539 * instruction to fail, while others will cause the instruction to seem
6540 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6541 * To speed up the normal (success) code path, we should avoid checking
6542 * for misconfigurations which will anyway be caught by the processor
6543 * when using the merged vmcs02.
6544 */
6545 if (vmcs12->launch_state == launch) {
6546 nested_vmx_failValid(vcpu,
6547 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6548 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6549 return 1;
6550 }
6551
6552 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6553 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6554 /*TODO: Also verify bits beyond physical address width are 0*/
6555 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6556 return 1;
6557 }
6558
6559 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6560 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6561 /*TODO: Also verify bits beyond physical address width are 0*/
6562 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6563 return 1;
6564 }
6565
6566 if (vmcs12->vm_entry_msr_load_count > 0 ||
6567 vmcs12->vm_exit_msr_load_count > 0 ||
6568 vmcs12->vm_exit_msr_store_count > 0) {
6569 if (printk_ratelimit())
6570 printk(KERN_WARNING
6571 "%s: VMCS MSR_{LOAD,STORE} unsupported\n", __func__);
6572 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6573 return 1;
6574 }
6575
6576 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6577 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6578 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6579 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6580 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6581 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6582 !vmx_control_verify(vmcs12->vm_exit_controls,
6583 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6584 !vmx_control_verify(vmcs12->vm_entry_controls,
6585 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6586 {
6587 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6588 return 1;
6589 }
6590
6591 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6592 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6593 nested_vmx_failValid(vcpu,
6594 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6595 return 1;
6596 }
6597
6598 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6599 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6600 nested_vmx_entry_failure(vcpu, vmcs12,
6601 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6602 return 1;
6603 }
6604 if (vmcs12->vmcs_link_pointer != -1ull) {
6605 nested_vmx_entry_failure(vcpu, vmcs12,
6606 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6607 return 1;
6608 }
6609
6610 /*
6611 * We're finally done with prerequisite checking, and can start with
6612 * the nested entry.
6613 */
6614
cd232ad0
NHE		 6615 vmcs02 = nested_get_current_vmcs02(vmx);
6616 if (!vmcs02)
6617 return -ENOMEM;
6618
6619 enter_guest_mode(vcpu);
6620
6621 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6622
6623 cpu = get_cpu();
6624 vmx->loaded_vmcs = vmcs02;
6625 vmx_vcpu_put(vcpu);
6626 vmx_vcpu_load(vcpu, cpu);
6627 vcpu->cpu = cpu;
6628 put_cpu();
6629
6630 vmcs12->launch_state = 1;
6631
6632 prepare_vmcs02(vcpu, vmcs12);
6633
6634 /*
6635 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6636 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6637 * returned as far as L1 is concerned. It will only return (and set
6638 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6639 */
6640 return 1;
6641}
6642
4704d0be
NHE		 6643/*
6644 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6645 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6646 * This function returns the new value we should put in vmcs12.guest_cr0.
6647 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6648 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6649 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6650 * didn't trap the bit, because if L1 did, so would L0).
6651 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6652 * been modified by L2, and L1 knows it. So just leave the old value of
6653 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6654 * isn't relevant, because if L0 traps this bit it can set it to anything.
6655 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6656 * changed these bits, and therefore they need to be updated, but L0
6657 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6658 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6659 */
6660static inline unsigned long
6661vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6662{
6663 return
6664 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6665 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6666 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6667 vcpu->arch.cr0_guest_owned_bits));
6668}
6669
6670static inline unsigned long
6671vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6672{
6673 return
6674 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6675 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6676 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6677 vcpu->arch.cr4_guest_owned_bits));
6678}
6679
6680/*
6681 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6682 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6683 * and this function updates it to reflect the changes to the guest state while
6684 * L2 was running (and perhaps made some exits which were handled directly by L0
6685 * without going back to L1), and to reflect the exit reason.
6686 * Note that we do not have to copy here all VMCS fields, just those that
6687 * could have changed by the L2 guest or the exit - i.e., the guest-state and
6688 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6689 * which already writes to vmcs12 directly.
6690 */
6691void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6692{
6693 /* update guest state fields: */
6694 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
6695 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
6696
6697 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
6698 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6699 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
6700 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
6701
6702 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
6703 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
6704 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
6705 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
6706 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
6707 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
6708 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
6709 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
6710 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
6711 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
6712 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
6713 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
6714 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
6715 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
6716 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
6717 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
6718 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
6719 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
6720 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
6721 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
6722 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
6723 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
6724 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
6725 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
6726 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
6727 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
6728 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
6729 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
6730 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
6731 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
6732 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
6733 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
6734 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
6735 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
6736 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
6737 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
6738
6739 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
6740 vmcs12->guest_interruptibility_info =
6741 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
6742 vmcs12->guest_pending_dbg_exceptions =
6743 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
6744
6745 /* TODO: These cannot have changed unless we have MSR bitmaps and
6746 * the relevant bit asks not to trap the change */
6747 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
6748 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
6749 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
6750 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
6751 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
6752 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
6753
6754 /* update exit information fields: */
6755
6756 vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON);
6757 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6758
6759 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6760 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6761 vmcs12->idt_vectoring_info_field =
6762 vmcs_read32(IDT_VECTORING_INFO_FIELD);
6763 vmcs12->idt_vectoring_error_code =
6764 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6765 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6766 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6767
6768 /* clear vm-entry fields which are to be cleared on exit */
6769 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6770 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
6771}
6772
6773/*
6774 * A part of what we need to when the nested L2 guest exits and we want to
6775 * run its L1 parent, is to reset L1's guest state to the host state specified
6776 * in vmcs12.
6777 * This function is to be called not only on normal nested exit, but also on
6778 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
6779 * Failures During or After Loading Guest State").
6780 * This function should be called when the active VMCS is L1's (vmcs01).
6781 */
6782void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6783{
6784 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
6785 vcpu->arch.efer = vmcs12->host_ia32_efer;
6786 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
6787 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6788 else
6789 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6790 vmx_set_efer(vcpu, vcpu->arch.efer);
6791
6792 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
6793 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
6794 /*
6795 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
6796 * actually changed, because it depends on the current state of
6797 * fpu_active (which may have changed).
6798 * Note that vmx_set_cr0 refers to efer set above.
6799 */
6800 kvm_set_cr0(vcpu, vmcs12->host_cr0);
6801 /*
6802 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
6803 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
6804 * but we also need to update cr0_guest_host_mask and exception_bitmap.
6805 */
6806 update_exception_bitmap(vcpu);
6807 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
6808 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6809
6810 /*
6811 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
6812 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
6813 */
6814 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
6815 kvm_set_cr4(vcpu, vmcs12->host_cr4);
6816
6817 /* shadow page tables on either EPT or shadow page tables */
6818 kvm_set_cr3(vcpu, vmcs12->host_cr3);
6819 kvm_mmu_reset_context(vcpu);
6820
6821 if (enable_vpid) {
6822 /*
6823 * Trivially support vpid by letting L2s share their parent
6824 * L1's vpid. TODO: move to a more elaborate solution, giving
6825 * each L2 its own vpid and exposing the vpid feature to L1.
6826 */
6827 vmx_flush_tlb(vcpu);
6828 }
6829
6830
6831 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
6832 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
6833 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
6834 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
6835 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
6836 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
6837 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
6838 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
6839 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
6840 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
6841 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
6842 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
6843 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
6844 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
6845 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
6846
6847 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
6848 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
6849 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
6850 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
6851 vmcs12->host_ia32_perf_global_ctrl);
6852}
6853
6854/*
6855 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
6856 * and modify vmcs12 to make it see what it would expect to see there if
6857 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
6858 */
6859static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
6860{
6861 struct vcpu_vmx *vmx = to_vmx(vcpu);
6862 int cpu;
6863 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6864
6865 leave_guest_mode(vcpu);
6866 prepare_vmcs12(vcpu, vmcs12);
6867
6868 cpu = get_cpu();
6869 vmx->loaded_vmcs = &vmx->vmcs01;
6870 vmx_vcpu_put(vcpu);
6871 vmx_vcpu_load(vcpu, cpu);
6872 vcpu->cpu = cpu;
6873 put_cpu();
6874
6875 /* if no vmcs02 cache requested, remove the one we used */
6876 if (VMCS02_POOL_SIZE == 0)
6877 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
6878
6879 load_vmcs12_host_state(vcpu, vmcs12);
6880
6881 /* Update TSC_OFFSET if vmx_adjust_tsc_offset() was used while L2 ran */
6882 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
6883
6884 /* This is needed for same reason as it was needed in prepare_vmcs02 */
6885 vmx->host_rsp = 0;
6886
6887 /* Unpin physical memory we referred to in vmcs02 */
6888 if (vmx->nested.apic_access_page) {
6889 nested_release_page(vmx->nested.apic_access_page);
6890 vmx->nested.apic_access_page = 0;
6891 }
6892
6893 /*
6894 * Exiting from L2 to L1, we're now back to L1 which thinks it just
6895 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
6896 * success or failure flag accordingly.
6897 */
6898 if (unlikely(vmx->fail)) {
6899 vmx->fail = 0;
6900 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
6901 } else
6902 nested_vmx_succeed(vcpu);
6903}
6904
7c177938
NHE		 6905/*
6906 * L1's failure to enter L2 is a subset of a normal exit, as explained in
6907 * 23.7 "VM-entry failures during or after loading guest state" (this also
6908 * lists the acceptable exit-reason and exit-qualification parameters).
6909 * It should only be called before L2 actually succeeded to run, and when
6910 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
6911 */
6912static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
6913 struct vmcs12 *vmcs12,
6914 u32 reason, unsigned long qualification)
6915{
6916 load_vmcs12_host_state(vcpu, vmcs12);
6917 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
6918 vmcs12->exit_qualification = qualification;
6919 nested_vmx_succeed(vcpu);
6920}
6921
8a76d7f2
JR		 6922static int vmx_check_intercept(struct kvm_vcpu *vcpu,
6923 struct x86_instruction_info *info,
6924 enum x86_intercept_stage stage)
6925{
6926 return X86EMUL_CONTINUE;
6927}
6928
cbdd1bea 6929static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 6930 .cpu_has_kvm_support = cpu_has_kvm_support,
6931 .disabled_by_bios = vmx_disabled_by_bios,
6932 .hardware_setup = hardware_setup,
6933 .hardware_unsetup = hardware_unsetup,
002c7f7c 6934 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 6935 .hardware_enable = hardware_enable,
6936 .hardware_disable = hardware_disable,
04547156 6937 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 6938
6939 .vcpu_create = vmx_create_vcpu,
6940 .vcpu_free = vmx_free_vcpu,
04d2cc77 6941 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 6942
04d2cc77 6943 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 6944 .vcpu_load = vmx_vcpu_load,
6945 .vcpu_put = vmx_vcpu_put,
6946
6947 .set_guest_debug = set_guest_debug,
6948 .get_msr = vmx_get_msr,
6949 .set_msr = vmx_set_msr,
6950 .get_segment_base = vmx_get_segment_base,
6951 .get_segment = vmx_get_segment,
6952 .set_segment = vmx_set_segment,
2e4d2653 6953 .get_cpl = vmx_get_cpl,
6aa8b732 6954 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 6955 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 6956 .decache_cr3 = vmx_decache_cr3,
25c4c276 6957 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 6958 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 6959 .set_cr3 = vmx_set_cr3,
6960 .set_cr4 = vmx_set_cr4,
6aa8b732 6961 .set_efer = vmx_set_efer,
6aa8b732
AK		 6962 .get_idt = vmx_get_idt,
6963 .set_idt = vmx_set_idt,
6964 .get_gdt = vmx_get_gdt,
6965 .set_gdt = vmx_set_gdt,
020df079 6966 .set_dr7 = vmx_set_dr7,
5fdbf976 6967 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 6968 .get_rflags = vmx_get_rflags,
6969 .set_rflags = vmx_set_rflags,
ebcbab4c 6970 .fpu_activate = vmx_fpu_activate,
02daab21 6971 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 6972
6973 .tlb_flush = vmx_flush_tlb,
6aa8b732 6974
6aa8b732 6975 .run = vmx_vcpu_run,
6062d012 6976 .handle_exit = vmx_handle_exit,
6aa8b732 6977 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 6978 .set_interrupt_shadow = vmx_set_interrupt_shadow,
6979 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 6980 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 6981 .set_irq = vmx_inject_irq,
95ba8273 6982 .set_nmi = vmx_inject_nmi,
298101da 6983 .queue_exception = vmx_queue_exception,
b463a6f7 6984 .cancel_injection = vmx_cancel_injection,
78646121 6985 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 6986 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 6987 .get_nmi_mask = vmx_get_nmi_mask,
6988 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 6989 .enable_nmi_window = enable_nmi_window,
6990 .enable_irq_window = enable_irq_window,
6991 .update_cr8_intercept = update_cr8_intercept,
95ba8273 6992
cbc94022 6993 .set_tss_addr = vmx_set_tss_addr,
67253af5 6994 .get_tdp_level = get_ept_level,
4b12f0de 6995 .get_mt_mask = vmx_get_mt_mask,
229456fc 6996
586f9607 6997 .get_exit_info = vmx_get_exit_info,
586f9607 6998
17cc3935 6999 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7000
7001 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7002
7003 .rdtscp_supported = vmx_rdtscp_supported,
d4330ef2
JR		 7004
7005 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7006
7007 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7008
4051b188 7009 .set_tsc_khz = vmx_set_tsc_khz,
99e3e30a 7010 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 7011 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 7012 .compute_tsc_offset = vmx_compute_tsc_offset,
1c97f0a0
JR		 7013
7014 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7015
7016 .check_intercept = vmx_check_intercept,
6aa8b732
AK		 7017};
7018
7019static int __init vmx_init(void)
7020{
26bb0981
AK		 7021 int r, i;
7022
7023 rdmsrl_safe(MSR_EFER, &host_efer);
7024
7025 for (i = 0; i < NR_VMX_MSR; ++i)
7026 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 7027
3e7c73e9 7028 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7029 if (!vmx_io_bitmap_a)
7030 return -ENOMEM;
7031
3e7c73e9 7032 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7033 if (!vmx_io_bitmap_b) {
7034 r = -ENOMEM;
7035 goto out;
7036 }
7037
5897297b
AK		 7038 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7039 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 7040 r = -ENOMEM;
7041 goto out1;
7042 }
7043
5897297b
AK		 7044 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7045 if (!vmx_msr_bitmap_longmode) {
7046 r = -ENOMEM;
7047 goto out2;
7048 }
7049
fdef3ad1
HQ		 7050 /*
7051 * Allow direct access to the PC debug port (it is often used for I/O
7052 * delays, but the vmexits simply slow things down).
7053 */
3e7c73e9
AK		 7054 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7055 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 7056
3e7c73e9 7057 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 7058
5897297b
AK		 7059 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7060 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 7061
2384d2b3
SY		 7062 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7063
0ee75bea
AK		 7064 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7065 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 7066 if (r)
5897297b 7067 goto out3;
25c5f225 7068
5897297b
AK		 7069 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7070 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7071 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7072 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7073 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7074 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 7075
089d034e 7076 if (enable_ept) {
534e38b4 7077 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 7078 VMX_EPT_EXECUTABLE_MASK);
ce88decf 7079 ept_set_mmio_spte_mask();
5fdbcb9d
SY		 7080 kvm_enable_tdp();
7081 } else
7082 kvm_disable_tdp();
1439442c 7083
fdef3ad1
HQ		 7084 return 0;
7085
5897297b
AK		 7086out3:
7087 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 7088out2:
5897297b 7089 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 7090out1:
3e7c73e9 7091 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 7092out:
3e7c73e9 7093 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7094 return r;
6aa8b732
AK		 7095}
7096
7097static void __exit vmx_exit(void)
7098{
5897297b
AK		 7099 free_page((unsigned long)vmx_msr_bitmap_legacy);
7100 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 7101 free_page((unsigned long)vmx_io_bitmap_b);
7102 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7103
cb498ea2 7104 kvm_exit();
6aa8b732
AK		 7105}
7106
7107module_init(vmx_init)
7108module_exit(vmx_exit)
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