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KVM: nVMX: Handling of CR0 and CR4 modifying instructions
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
85f455f7 19#include "irq.h"
1d737c8a 20#include "mmu.h"
e495606d 21
edf88417 22#include <linux/kvm_host.h>
6aa8b732 23#include <linux/module.h>
9d8f549d 24#include <linux/kernel.h>
6aa8b732
AK		 25#include <linux/mm.h>
26#include <linux/highmem.h>
e8edc6e0 27#include <linux/sched.h>
c7addb90 28#include <linux/moduleparam.h>
229456fc 29#include <linux/ftrace_event.h>
5a0e3ad6 30#include <linux/slab.h>
cafd6659 31#include <linux/tboot.h>
5fdbf976 32#include "kvm_cache_regs.h"
35920a35 33#include "x86.h"
e495606d 34
6aa8b732 35#include <asm/io.h>
3b3be0d1 36#include <asm/desc.h>
13673a90 37#include <asm/vmx.h>
6210e37b 38#include <asm/virtext.h>
a0861c02 39#include <asm/mce.h>
2acf923e
DC		 40#include <asm/i387.h>
41#include <asm/xcr.h>
6aa8b732 42
229456fc
MT		 43#include "trace.h"
44
4ecac3fd 45#define __ex(x) __kvm_handle_fault_on_reboot(x)
5e520e62
AK		 46#define __ex_clear(x, reg) \
47 ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
4ecac3fd 48
6aa8b732
AK		 49MODULE_AUTHOR("Qumranet");
50MODULE_LICENSE("GPL");
51
4462d21a 52static int __read_mostly bypass_guest_pf = 1;
c1f8bc04 53module_param(bypass_guest_pf, bool, S_IRUGO);
c7addb90 54
4462d21a 55static int __read_mostly enable_vpid = 1;
736caefe 56module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 57
4462d21a 58static int __read_mostly flexpriority_enabled = 1;
736caefe 59module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 60
4462d21a 61static int __read_mostly enable_ept = 1;
736caefe 62module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 63
3a624e29
NK		 64static int __read_mostly enable_unrestricted_guest = 1;
65module_param_named(unrestricted_guest,
66 enable_unrestricted_guest, bool, S_IRUGO);
67
4462d21a 68static int __read_mostly emulate_invalid_guest_state = 0;
c1f8bc04 69module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 70
b923e62e
DX		 71static int __read_mostly vmm_exclusive = 1;
72module_param(vmm_exclusive, bool, S_IRUGO);
73
443381a8
AL		 74static int __read_mostly yield_on_hlt = 1;
75module_param(yield_on_hlt, bool, S_IRUGO);
76
801d3424
NHE		 77/*
78 * If nested=1, nested virtualization is supported, i.e., guests may use
79 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
80 * use VMX instructions.
81 */
82static int __read_mostly nested = 0;
83module_param(nested, bool, S_IRUGO);
84
cdc0e244
AK		 85#define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST \
86 (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
87#define KVM_GUEST_CR0_MASK \
88 (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
89#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST \
81231c69 90 (X86_CR0_WP | X86_CR0_NE)
cdc0e244
AK		 91#define KVM_VM_CR0_ALWAYS_ON \
92 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 93#define KVM_CR4_GUEST_OWNED_BITS \
94 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
95 | X86_CR4_OSXMMEXCPT)
96
cdc0e244
AK		 97#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
98#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
99
78ac8b47
AK		 100#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
101
4b8d54f9
ZE		 102/*
103 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
104 * ple_gap: upper bound on the amount of time between two successive
105 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 106 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 107 * ple_window: upper bound on the amount of time a guest is allowed to execute
108 * in a PAUSE loop. Tests indicate that most spinlocks are held for
109 * less than 2^12 cycles
110 * Time is measured based on a counter that runs at the same rate as the TSC,
111 * refer SDM volume 3b section 21.6.13 & 22.1.3.
112 */
00c25bce 113#define KVM_VMX_DEFAULT_PLE_GAP 128
4b8d54f9
ZE		 114#define KVM_VMX_DEFAULT_PLE_WINDOW 4096
115static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
116module_param(ple_gap, int, S_IRUGO);
117
118static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
119module_param(ple_window, int, S_IRUGO);
120
61d2ef2c 121#define NR_AUTOLOAD_MSRS 1
ff2f6fe9 122#define VMCS02_POOL_SIZE 1
61d2ef2c 123
a2fa3e9f
GH		 124struct vmcs {
125 u32 revision_id;
126 u32 abort;
127 char data[0];
128};
129
d462b819
NHE		 130/*
131 * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
132 * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
133 * loaded on this CPU (so we can clear them if the CPU goes down).
134 */
135struct loaded_vmcs {
136 struct vmcs *vmcs;
137 int cpu;
138 int launched;
139 struct list_head loaded_vmcss_on_cpu_link;
140};
141
26bb0981
AK		 142struct shared_msr_entry {
143 unsigned index;
144 u64 data;
d5696725 145 u64 mask;
26bb0981
AK		 146};
147
a9d30f33
NHE		 148/*
149 * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
150 * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
151 * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
152 * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
153 * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
154 * More than one of these structures may exist, if L1 runs multiple L2 guests.
155 * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
156 * underlying hardware which will be used to run L2.
157 * This structure is packed to ensure that its layout is identical across
158 * machines (necessary for live migration).
159 * If there are changes in this struct, VMCS12_REVISION must be changed.
160 */
22bd0358 161typedef u64 natural_width;
a9d30f33
NHE		 162struct __packed vmcs12 {
163 /* According to the Intel spec, a VMCS region must start with the
164 * following two fields. Then follow implementation-specific data.
165 */
166 u32 revision_id;
167 u32 abort;
22bd0358 168
27d6c865
NHE		 169 u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
170 u32 padding[7]; /* room for future expansion */
171
22bd0358
NHE		 172 u64 io_bitmap_a;
173 u64 io_bitmap_b;
174 u64 msr_bitmap;
175 u64 vm_exit_msr_store_addr;
176 u64 vm_exit_msr_load_addr;
177 u64 vm_entry_msr_load_addr;
178 u64 tsc_offset;
179 u64 virtual_apic_page_addr;
180 u64 apic_access_addr;
181 u64 ept_pointer;
182 u64 guest_physical_address;
183 u64 vmcs_link_pointer;
184 u64 guest_ia32_debugctl;
185 u64 guest_ia32_pat;
186 u64 guest_ia32_efer;
187 u64 guest_ia32_perf_global_ctrl;
188 u64 guest_pdptr0;
189 u64 guest_pdptr1;
190 u64 guest_pdptr2;
191 u64 guest_pdptr3;
192 u64 host_ia32_pat;
193 u64 host_ia32_efer;
194 u64 host_ia32_perf_global_ctrl;
195 u64 padding64[8]; /* room for future expansion */
196 /*
197 * To allow migration of L1 (complete with its L2 guests) between
198 * machines of different natural widths (32 or 64 bit), we cannot have
199 * unsigned long fields with no explict size. We use u64 (aliased
200 * natural_width) instead. Luckily, x86 is little-endian.
201 */
202 natural_width cr0_guest_host_mask;
203 natural_width cr4_guest_host_mask;
204 natural_width cr0_read_shadow;
205 natural_width cr4_read_shadow;
206 natural_width cr3_target_value0;
207 natural_width cr3_target_value1;
208 natural_width cr3_target_value2;
209 natural_width cr3_target_value3;
210 natural_width exit_qualification;
211 natural_width guest_linear_address;
212 natural_width guest_cr0;
213 natural_width guest_cr3;
214 natural_width guest_cr4;
215 natural_width guest_es_base;
216 natural_width guest_cs_base;
217 natural_width guest_ss_base;
218 natural_width guest_ds_base;
219 natural_width guest_fs_base;
220 natural_width guest_gs_base;
221 natural_width guest_ldtr_base;
222 natural_width guest_tr_base;
223 natural_width guest_gdtr_base;
224 natural_width guest_idtr_base;
225 natural_width guest_dr7;
226 natural_width guest_rsp;
227 natural_width guest_rip;
228 natural_width guest_rflags;
229 natural_width guest_pending_dbg_exceptions;
230 natural_width guest_sysenter_esp;
231 natural_width guest_sysenter_eip;
232 natural_width host_cr0;
233 natural_width host_cr3;
234 natural_width host_cr4;
235 natural_width host_fs_base;
236 natural_width host_gs_base;
237 natural_width host_tr_base;
238 natural_width host_gdtr_base;
239 natural_width host_idtr_base;
240 natural_width host_ia32_sysenter_esp;
241 natural_width host_ia32_sysenter_eip;
242 natural_width host_rsp;
243 natural_width host_rip;
244 natural_width paddingl[8]; /* room for future expansion */
245 u32 pin_based_vm_exec_control;
246 u32 cpu_based_vm_exec_control;
247 u32 exception_bitmap;
248 u32 page_fault_error_code_mask;
249 u32 page_fault_error_code_match;
250 u32 cr3_target_count;
251 u32 vm_exit_controls;
252 u32 vm_exit_msr_store_count;
253 u32 vm_exit_msr_load_count;
254 u32 vm_entry_controls;
255 u32 vm_entry_msr_load_count;
256 u32 vm_entry_intr_info_field;
257 u32 vm_entry_exception_error_code;
258 u32 vm_entry_instruction_len;
259 u32 tpr_threshold;
260 u32 secondary_vm_exec_control;
261 u32 vm_instruction_error;
262 u32 vm_exit_reason;
263 u32 vm_exit_intr_info;
264 u32 vm_exit_intr_error_code;
265 u32 idt_vectoring_info_field;
266 u32 idt_vectoring_error_code;
267 u32 vm_exit_instruction_len;
268 u32 vmx_instruction_info;
269 u32 guest_es_limit;
270 u32 guest_cs_limit;
271 u32 guest_ss_limit;
272 u32 guest_ds_limit;
273 u32 guest_fs_limit;
274 u32 guest_gs_limit;
275 u32 guest_ldtr_limit;
276 u32 guest_tr_limit;
277 u32 guest_gdtr_limit;
278 u32 guest_idtr_limit;
279 u32 guest_es_ar_bytes;
280 u32 guest_cs_ar_bytes;
281 u32 guest_ss_ar_bytes;
282 u32 guest_ds_ar_bytes;
283 u32 guest_fs_ar_bytes;
284 u32 guest_gs_ar_bytes;
285 u32 guest_ldtr_ar_bytes;
286 u32 guest_tr_ar_bytes;
287 u32 guest_interruptibility_info;
288 u32 guest_activity_state;
289 u32 guest_sysenter_cs;
290 u32 host_ia32_sysenter_cs;
291 u32 padding32[8]; /* room for future expansion */
292 u16 virtual_processor_id;
293 u16 guest_es_selector;
294 u16 guest_cs_selector;
295 u16 guest_ss_selector;
296 u16 guest_ds_selector;
297 u16 guest_fs_selector;
298 u16 guest_gs_selector;
299 u16 guest_ldtr_selector;
300 u16 guest_tr_selector;
301 u16 host_es_selector;
302 u16 host_cs_selector;
303 u16 host_ss_selector;
304 u16 host_ds_selector;
305 u16 host_fs_selector;
306 u16 host_gs_selector;
307 u16 host_tr_selector;
a9d30f33
NHE		 308};
309
310/*
311 * VMCS12_REVISION is an arbitrary id that should be changed if the content or
312 * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
313 * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
314 */
315#define VMCS12_REVISION 0x11e57ed0
316
317/*
318 * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
319 * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
320 * current implementation, 4K are reserved to avoid future complications.
321 */
322#define VMCS12_SIZE 0x1000
323
ff2f6fe9
NHE		 324/* Used to remember the last vmcs02 used for some recently used vmcs12s */
325struct vmcs02_list {
326 struct list_head list;
327 gpa_t vmptr;
328 struct loaded_vmcs vmcs02;
329};
330
ec378aee
NHE		 331/*
332 * The nested_vmx structure is part of vcpu_vmx, and holds information we need
333 * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
334 */
335struct nested_vmx {
336 /* Has the level1 guest done vmxon? */
337 bool vmxon;
a9d30f33
NHE		 338
339 /* The guest-physical address of the current VMCS L1 keeps for L2 */
340 gpa_t current_vmptr;
341 /* The host-usable pointer to the above */
342 struct page *current_vmcs12_page;
343 struct vmcs12 *current_vmcs12;
ff2f6fe9
NHE		 344
345 /* vmcs02_list cache of VMCSs recently used to run L2 guests */
346 struct list_head vmcs02_pool;
347 int vmcs02_num;
fe3ef05c 348 u64 vmcs01_tsc_offset;
644d711a
NHE		 349 /* L2 must run next, and mustn't decide to exit to L1. */
350 bool nested_run_pending;
fe3ef05c
NHE		 351 /*
352 * Guest pages referred to in vmcs02 with host-physical pointers, so
353 * we must keep them pinned while L2 runs.
354 */
355 struct page *apic_access_page;
ec378aee
NHE		 356};
357
a2fa3e9f 358struct vcpu_vmx {
fb3f0f51 359 struct kvm_vcpu vcpu;
313dbd49 360 unsigned long host_rsp;
29bd8a78 361 u8 fail;
69c73028 362 u8 cpl;
9d58b931 363 bool nmi_known_unmasked;
51aa01d1 364 u32 exit_intr_info;
1155f76a 365 u32 idt_vectoring_info;
6de12732 366 ulong rflags;
26bb0981 367 struct shared_msr_entry *guest_msrs;
a2fa3e9f
GH		 368 int nmsrs;
369 int save_nmsrs;
a2fa3e9f 370#ifdef CONFIG_X86_64
44ea2b17
AK		 371 u64 msr_host_kernel_gs_base;
372 u64 msr_guest_kernel_gs_base;
a2fa3e9f 373#endif
d462b819
NHE		 374 /*
375 * loaded_vmcs points to the VMCS currently used in this vcpu. For a
376 * non-nested (L1) guest, it always points to vmcs01. For a nested
377 * guest (L2), it points to a different VMCS.
378 */
379 struct loaded_vmcs vmcs01;
380 struct loaded_vmcs *loaded_vmcs;
381 bool __launched; /* temporary, used in vmx_vcpu_run */
61d2ef2c
AK		 382 struct msr_autoload {
383 unsigned nr;
384 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
385 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
386 } msr_autoload;
a2fa3e9f
GH		 387 struct {
388 int loaded;
389 u16 fs_sel, gs_sel, ldt_sel;
152d3f2f
LV		 390 int gs_ldt_reload_needed;
391 int fs_reload_needed;
d77c26fc 392 } host_state;
9c8cba37 393 struct {
7ffd92c5 394 int vm86_active;
78ac8b47 395 ulong save_rflags;
7ffd92c5
AK		 396 struct kvm_save_segment {
397 u16 selector;
398 unsigned long base;
399 u32 limit;
400 u32 ar;
401 } tr, es, ds, fs, gs;
9c8cba37 402 } rmode;
2fb92db1
AK		 403 struct {
404 u32 bitmask; /* 4 bits per segment (1 bit per field) */
405 struct kvm_save_segment seg[8];
406 } segment_cache;
2384d2b3 407 int vpid;
04fa4d32 408 bool emulation_required;
3b86cd99
JK		 409
410 /* Support for vnmi-less CPUs */
411 int soft_vnmi_blocked;
412 ktime_t entry_time;
413 s64 vnmi_blocked_time;
a0861c02 414 u32 exit_reason;
4e47c7a6
SY		 415
416 bool rdtscp_enabled;
ec378aee
NHE		 417
418 /* Support for a guest hypervisor (nested VMX) */
419 struct nested_vmx nested;
a2fa3e9f
GH		 420};
421
2fb92db1
AK		 422enum segment_cache_field {
423 SEG_FIELD_SEL = 0,
424 SEG_FIELD_BASE = 1,
425 SEG_FIELD_LIMIT = 2,
426 SEG_FIELD_AR = 3,
427
428 SEG_FIELD_NR = 4
429};
430
a2fa3e9f
GH		 431static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
432{
fb3f0f51 433 return container_of(vcpu, struct vcpu_vmx, vcpu);
a2fa3e9f
GH		 434}
435
22bd0358
NHE		 436#define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
437#define FIELD(number, name) [number] = VMCS12_OFFSET(name)
438#define FIELD64(number, name) [number] = VMCS12_OFFSET(name), \
439 [number##_HIGH] = VMCS12_OFFSET(name)+4
440
441static unsigned short vmcs_field_to_offset_table[] = {
442 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
443 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
444 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
445 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
446 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
447 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
448 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
449 FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
450 FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
451 FIELD(HOST_ES_SELECTOR, host_es_selector),
452 FIELD(HOST_CS_SELECTOR, host_cs_selector),
453 FIELD(HOST_SS_SELECTOR, host_ss_selector),
454 FIELD(HOST_DS_SELECTOR, host_ds_selector),
455 FIELD(HOST_FS_SELECTOR, host_fs_selector),
456 FIELD(HOST_GS_SELECTOR, host_gs_selector),
457 FIELD(HOST_TR_SELECTOR, host_tr_selector),
458 FIELD64(IO_BITMAP_A, io_bitmap_a),
459 FIELD64(IO_BITMAP_B, io_bitmap_b),
460 FIELD64(MSR_BITMAP, msr_bitmap),
461 FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
462 FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
463 FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
464 FIELD64(TSC_OFFSET, tsc_offset),
465 FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
466 FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
467 FIELD64(EPT_POINTER, ept_pointer),
468 FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
469 FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
470 FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
471 FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
472 FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
473 FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
474 FIELD64(GUEST_PDPTR0, guest_pdptr0),
475 FIELD64(GUEST_PDPTR1, guest_pdptr1),
476 FIELD64(GUEST_PDPTR2, guest_pdptr2),
477 FIELD64(GUEST_PDPTR3, guest_pdptr3),
478 FIELD64(HOST_IA32_PAT, host_ia32_pat),
479 FIELD64(HOST_IA32_EFER, host_ia32_efer),
480 FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
481 FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
482 FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
483 FIELD(EXCEPTION_BITMAP, exception_bitmap),
484 FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
485 FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
486 FIELD(CR3_TARGET_COUNT, cr3_target_count),
487 FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
488 FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
489 FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
490 FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
491 FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
492 FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
493 FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
494 FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
495 FIELD(TPR_THRESHOLD, tpr_threshold),
496 FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
497 FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
498 FIELD(VM_EXIT_REASON, vm_exit_reason),
499 FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
500 FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
501 FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
502 FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
503 FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
504 FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
505 FIELD(GUEST_ES_LIMIT, guest_es_limit),
506 FIELD(GUEST_CS_LIMIT, guest_cs_limit),
507 FIELD(GUEST_SS_LIMIT, guest_ss_limit),
508 FIELD(GUEST_DS_LIMIT, guest_ds_limit),
509 FIELD(GUEST_FS_LIMIT, guest_fs_limit),
510 FIELD(GUEST_GS_LIMIT, guest_gs_limit),
511 FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
512 FIELD(GUEST_TR_LIMIT, guest_tr_limit),
513 FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
514 FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
515 FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
516 FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
517 FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
518 FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
519 FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
520 FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
521 FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
522 FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
523 FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
524 FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
525 FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
526 FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
527 FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
528 FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
529 FIELD(CR0_READ_SHADOW, cr0_read_shadow),
530 FIELD(CR4_READ_SHADOW, cr4_read_shadow),
531 FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
532 FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
533 FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
534 FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
535 FIELD(EXIT_QUALIFICATION, exit_qualification),
536 FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
537 FIELD(GUEST_CR0, guest_cr0),
538 FIELD(GUEST_CR3, guest_cr3),
539 FIELD(GUEST_CR4, guest_cr4),
540 FIELD(GUEST_ES_BASE, guest_es_base),
541 FIELD(GUEST_CS_BASE, guest_cs_base),
542 FIELD(GUEST_SS_BASE, guest_ss_base),
543 FIELD(GUEST_DS_BASE, guest_ds_base),
544 FIELD(GUEST_FS_BASE, guest_fs_base),
545 FIELD(GUEST_GS_BASE, guest_gs_base),
546 FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
547 FIELD(GUEST_TR_BASE, guest_tr_base),
548 FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
549 FIELD(GUEST_IDTR_BASE, guest_idtr_base),
550 FIELD(GUEST_DR7, guest_dr7),
551 FIELD(GUEST_RSP, guest_rsp),
552 FIELD(GUEST_RIP, guest_rip),
553 FIELD(GUEST_RFLAGS, guest_rflags),
554 FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
555 FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
556 FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
557 FIELD(HOST_CR0, host_cr0),
558 FIELD(HOST_CR3, host_cr3),
559 FIELD(HOST_CR4, host_cr4),
560 FIELD(HOST_FS_BASE, host_fs_base),
561 FIELD(HOST_GS_BASE, host_gs_base),
562 FIELD(HOST_TR_BASE, host_tr_base),
563 FIELD(HOST_GDTR_BASE, host_gdtr_base),
564 FIELD(HOST_IDTR_BASE, host_idtr_base),
565 FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
566 FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
567 FIELD(HOST_RSP, host_rsp),
568 FIELD(HOST_RIP, host_rip),
569};
570static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
571
572static inline short vmcs_field_to_offset(unsigned long field)
573{
574 if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
575 return -1;
576 return vmcs_field_to_offset_table[field];
577}
578
a9d30f33
NHE		 579static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
580{
581 return to_vmx(vcpu)->nested.current_vmcs12;
582}
583
584static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
585{
586 struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
587 if (is_error_page(page)) {
588 kvm_release_page_clean(page);
589 return NULL;
590 }
591 return page;
592}
593
594static void nested_release_page(struct page *page)
595{
596 kvm_release_page_dirty(page);
597}
598
599static void nested_release_page_clean(struct page *page)
600{
601 kvm_release_page_clean(page);
602}
603
4e1096d2 604static u64 construct_eptp(unsigned long root_hpa);
4610c9cc
DX		 605static void kvm_cpu_vmxon(u64 addr);
606static void kvm_cpu_vmxoff(void);
aff48baa 607static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
776e58ea 608static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
75880a01 609
6aa8b732
AK		 610static DEFINE_PER_CPU(struct vmcs *, vmxarea);
611static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 612/*
613 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
614 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
615 */
616static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
3444d7da 617static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
6aa8b732 618
3e7c73e9
AK		 619static unsigned long *vmx_io_bitmap_a;
620static unsigned long *vmx_io_bitmap_b;
5897297b
AK		 621static unsigned long *vmx_msr_bitmap_legacy;
622static unsigned long *vmx_msr_bitmap_longmode;
fdef3ad1 623
110312c8
AK		 624static bool cpu_has_load_ia32_efer;
625
2384d2b3
SY		 626static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
627static DEFINE_SPINLOCK(vmx_vpid_lock);
628
1c3d14fe 629static struct vmcs_config {
6aa8b732
AK		 630 int size;
631 int order;
632 u32 revision_id;
1c3d14fe
YS		 633 u32 pin_based_exec_ctrl;
634 u32 cpu_based_exec_ctrl;
f78e0e2e 635 u32 cpu_based_2nd_exec_ctrl;
1c3d14fe
YS		 636 u32 vmexit_ctrl;
637 u32 vmentry_ctrl;
638} vmcs_config;
6aa8b732 639
efff9e53 640static struct vmx_capability {
d56f546d
SY		 641 u32 ept;
642 u32 vpid;
643} vmx_capability;
644
6aa8b732
AK		 645#define VMX_SEGMENT_FIELD(seg) \
646 [VCPU_SREG_##seg] = { \
647 .selector = GUEST_##seg##_SELECTOR, \
648 .base = GUEST_##seg##_BASE, \
649 .limit = GUEST_##seg##_LIMIT, \
650 .ar_bytes = GUEST_##seg##_AR_BYTES, \
651 }
652
653static struct kvm_vmx_segment_field {
654 unsigned selector;
655 unsigned base;
656 unsigned limit;
657 unsigned ar_bytes;
658} kvm_vmx_segment_fields[] = {
659 VMX_SEGMENT_FIELD(CS),
660 VMX_SEGMENT_FIELD(DS),
661 VMX_SEGMENT_FIELD(ES),
662 VMX_SEGMENT_FIELD(FS),
663 VMX_SEGMENT_FIELD(GS),
664 VMX_SEGMENT_FIELD(SS),
665 VMX_SEGMENT_FIELD(TR),
666 VMX_SEGMENT_FIELD(LDTR),
667};
668
26bb0981
AK		 669static u64 host_efer;
670
6de4f3ad
AK		 671static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
672
4d56c8a7 673/*
8c06585d 674 * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
4d56c8a7
AK		 675 * away by decrementing the array size.
676 */
6aa8b732 677static const u32 vmx_msr_index[] = {
05b3e0c2 678#ifdef CONFIG_X86_64
44ea2b17 679 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 680#endif
8c06585d 681 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 682};
9d8f549d 683#define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
6aa8b732 684
31299944 685static inline bool is_page_fault(u32 intr_info)
6aa8b732
AK		 686{
687 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
688 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 689 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
6aa8b732
AK		 690}
691
31299944 692static inline bool is_no_device(u32 intr_info)
2ab455cc
AL		 693{
694 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
695 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 696 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
2ab455cc
AL		 697}
698
31299944 699static inline bool is_invalid_opcode(u32 intr_info)
7aa81cc0
AL		 700{
701 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
702 INTR_INFO_VALID_MASK)) ==
8ab2d2e2 703 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
7aa81cc0
AL		 704}
705
31299944 706static inline bool is_external_interrupt(u32 intr_info)
6aa8b732
AK		 707{
708 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
709 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
710}
711
31299944 712static inline bool is_machine_check(u32 intr_info)
a0861c02
AK		 713{
714 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
715 INTR_INFO_VALID_MASK)) ==
716 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
717}
718
31299944 719static inline bool cpu_has_vmx_msr_bitmap(void)
25c5f225 720{
04547156 721 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
25c5f225
SY		 722}
723
31299944 724static inline bool cpu_has_vmx_tpr_shadow(void)
6e5d865c 725{
04547156 726 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
6e5d865c
YS		 727}
728
31299944 729static inline bool vm_need_tpr_shadow(struct kvm *kvm)
6e5d865c 730{
04547156 731 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
6e5d865c
YS		 732}
733
31299944 734static inline bool cpu_has_secondary_exec_ctrls(void)
f78e0e2e 735{
04547156
SY		 736 return vmcs_config.cpu_based_exec_ctrl &
737 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
f78e0e2e
SY		 738}
739
774ead3a 740static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
f78e0e2e 741{
04547156
SY		 742 return vmcs_config.cpu_based_2nd_exec_ctrl &
743 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
744}
745
746static inline bool cpu_has_vmx_flexpriority(void)
747{
748 return cpu_has_vmx_tpr_shadow() &&
749 cpu_has_vmx_virtualize_apic_accesses();
f78e0e2e
SY		 750}
751
e799794e
MT		 752static inline bool cpu_has_vmx_ept_execute_only(void)
753{
31299944 754 return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
e799794e
MT		 755}
756
757static inline bool cpu_has_vmx_eptp_uncacheable(void)
758{
31299944 759 return vmx_capability.ept & VMX_EPTP_UC_BIT;
e799794e
MT		 760}
761
762static inline bool cpu_has_vmx_eptp_writeback(void)
763{
31299944 764 return vmx_capability.ept & VMX_EPTP_WB_BIT;
e799794e
MT		 765}
766
767static inline bool cpu_has_vmx_ept_2m_page(void)
768{
31299944 769 return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
e799794e
MT		 770}
771
878403b7
SY		 772static inline bool cpu_has_vmx_ept_1g_page(void)
773{
31299944 774 return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
878403b7
SY		 775}
776
4bc9b982
SY		 777static inline bool cpu_has_vmx_ept_4levels(void)
778{
779 return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
780}
781
31299944 782static inline bool cpu_has_vmx_invept_individual_addr(void)
d56f546d 783{
31299944 784 return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
d56f546d
SY		 785}
786
31299944 787static inline bool cpu_has_vmx_invept_context(void)
d56f546d 788{
31299944 789 return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
d56f546d
SY		 790}
791
31299944 792static inline bool cpu_has_vmx_invept_global(void)
d56f546d 793{
31299944 794 return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
d56f546d
SY		 795}
796
518c8aee
GJ		 797static inline bool cpu_has_vmx_invvpid_single(void)
798{
799 return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
800}
801
b9d762fa
GJ		 802static inline bool cpu_has_vmx_invvpid_global(void)
803{
804 return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
805}
806
31299944 807static inline bool cpu_has_vmx_ept(void)
d56f546d 808{
04547156
SY		 809 return vmcs_config.cpu_based_2nd_exec_ctrl &
810 SECONDARY_EXEC_ENABLE_EPT;
d56f546d
SY		 811}
812
31299944 813static inline bool cpu_has_vmx_unrestricted_guest(void)
3a624e29
NK		 814{
815 return vmcs_config.cpu_based_2nd_exec_ctrl &
816 SECONDARY_EXEC_UNRESTRICTED_GUEST;
817}
818
31299944 819static inline bool cpu_has_vmx_ple(void)
4b8d54f9
ZE		 820{
821 return vmcs_config.cpu_based_2nd_exec_ctrl &
822 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
823}
824
31299944 825static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
f78e0e2e 826{
6d3e435e 827 return flexpriority_enabled && irqchip_in_kernel(kvm);
f78e0e2e
SY		 828}
829
31299944 830static inline bool cpu_has_vmx_vpid(void)
2384d2b3 831{
04547156
SY		 832 return vmcs_config.cpu_based_2nd_exec_ctrl &
833 SECONDARY_EXEC_ENABLE_VPID;
2384d2b3
SY		 834}
835
31299944 836static inline bool cpu_has_vmx_rdtscp(void)
4e47c7a6
SY		 837{
838 return vmcs_config.cpu_based_2nd_exec_ctrl &
839 SECONDARY_EXEC_RDTSCP;
840}
841
31299944 842static inline bool cpu_has_virtual_nmis(void)
f08864b4
SY		 843{
844 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
845}
846
f5f48ee1
SY		 847static inline bool cpu_has_vmx_wbinvd_exit(void)
848{
849 return vmcs_config.cpu_based_2nd_exec_ctrl &
850 SECONDARY_EXEC_WBINVD_EXITING;
851}
852
04547156
SY		 853static inline bool report_flexpriority(void)
854{
855 return flexpriority_enabled;
856}
857
fe3ef05c
NHE		 858static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
859{
860 return vmcs12->cpu_based_vm_exec_control & bit;
861}
862
863static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
864{
865 return (vmcs12->cpu_based_vm_exec_control &
866 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
867 (vmcs12->secondary_vm_exec_control & bit);
868}
869
644d711a
NHE		 870static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
871 struct kvm_vcpu *vcpu)
872{
873 return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
874}
875
876static inline bool is_exception(u32 intr_info)
877{
878 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
879 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
880}
881
882static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
7c177938
NHE		 883static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
884 struct vmcs12 *vmcs12,
885 u32 reason, unsigned long qualification);
886
8b9cf98c 887static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 888{
889 int i;
890
a2fa3e9f 891 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 892 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 893 return i;
894 return -1;
895}
896
2384d2b3
SY		 897static inline void __invvpid(int ext, u16 vpid, gva_t gva)
898{
899 struct {
900 u64 vpid : 16;
901 u64 rsvd : 48;
902 u64 gva;
903 } operand = { vpid, 0, gva };
904
4ecac3fd 905 asm volatile (__ex(ASM_VMX_INVVPID)
2384d2b3
SY		 906 /* CF==1 or ZF==1 --> rc = -1 */
907 "; ja 1f ; ud2 ; 1:"
908 : : "a"(&operand), "c"(ext) : "cc", "memory");
909}
910
1439442c
SY		 911static inline void __invept(int ext, u64 eptp, gpa_t gpa)
912{
913 struct {
914 u64 eptp, gpa;
915 } operand = {eptp, gpa};
916
4ecac3fd 917 asm volatile (__ex(ASM_VMX_INVEPT)
1439442c
SY		 918 /* CF==1 or ZF==1 --> rc = -1 */
919 "; ja 1f ; ud2 ; 1:\n"
920 : : "a" (&operand), "c" (ext) : "cc", "memory");
921}
922
26bb0981 923static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 924{
925 int i;
926
8b9cf98c 927 i = __find_msr_index(vmx, msr);
a75beee6 928 if (i >= 0)
a2fa3e9f 929 return &vmx->guest_msrs[i];
8b6d44c7 930 return NULL;
7725f0ba
AK		 931}
932
6aa8b732
AK		 933static void vmcs_clear(struct vmcs *vmcs)
934{
935 u64 phys_addr = __pa(vmcs);
936 u8 error;
937
4ecac3fd 938 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
16d8f72f 939 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
6aa8b732
AK		 940 : "cc", "memory");
941 if (error)
942 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
943 vmcs, phys_addr);
944}
945
d462b819
NHE		 946static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
947{
948 vmcs_clear(loaded_vmcs->vmcs);
949 loaded_vmcs->cpu = -1;
950 loaded_vmcs->launched = 0;
951}
952
7725b894
DX		 953static void vmcs_load(struct vmcs *vmcs)
954{
955 u64 phys_addr = __pa(vmcs);
956 u8 error;
957
958 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
16d8f72f 959 : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
7725b894
DX		 960 : "cc", "memory");
961 if (error)
962 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
963 vmcs, phys_addr);
964}
965
d462b819 966static void __loaded_vmcs_clear(void *arg)
6aa8b732 967{
d462b819 968 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 969 int cpu = raw_smp_processor_id();
6aa8b732 970
d462b819
NHE		 971 if (loaded_vmcs->cpu != cpu)
972 return; /* vcpu migration can race with cpu offline */
973 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 974 per_cpu(current_vmcs, cpu) = NULL;
d462b819
NHE		 975 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
976 loaded_vmcs_init(loaded_vmcs);
6aa8b732
AK		 977}
978
d462b819 979static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 980{
d462b819
NHE		 981 if (loaded_vmcs->cpu != -1)
982 smp_call_function_single(
983 loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 984}
985
1760dd49 986static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
2384d2b3
SY		 987{
988 if (vmx->vpid == 0)
989 return;
990
518c8aee
GJ		 991 if (cpu_has_vmx_invvpid_single())
992 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
2384d2b3
SY		 993}
994
b9d762fa
GJ		 995static inline void vpid_sync_vcpu_global(void)
996{
997 if (cpu_has_vmx_invvpid_global())
998 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
999}
1000
1001static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1002{
1003 if (cpu_has_vmx_invvpid_single())
1760dd49 1004 vpid_sync_vcpu_single(vmx);
b9d762fa
GJ		 1005 else
1006 vpid_sync_vcpu_global();
1007}
1008
1439442c
SY		 1009static inline void ept_sync_global(void)
1010{
1011 if (cpu_has_vmx_invept_global())
1012 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1013}
1014
1015static inline void ept_sync_context(u64 eptp)
1016{
089d034e 1017 if (enable_ept) {
1439442c
SY		 1018 if (cpu_has_vmx_invept_context())
1019 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1020 else
1021 ept_sync_global();
1022 }
1023}
1024
1025static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1026{
089d034e 1027 if (enable_ept) {
1439442c
SY		 1028 if (cpu_has_vmx_invept_individual_addr())
1029 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1030 eptp, gpa);
1031 else
1032 ept_sync_context(eptp);
1033 }
1034}
1035
96304217 1036static __always_inline unsigned long vmcs_readl(unsigned long field)
6aa8b732 1037{
5e520e62 1038 unsigned long value;
6aa8b732 1039
5e520e62
AK		 1040 asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1041 : "=a"(value) : "d"(field) : "cc");
6aa8b732
AK		 1042 return value;
1043}
1044
96304217 1045static __always_inline u16 vmcs_read16(unsigned long field)
6aa8b732
AK		 1046{
1047 return vmcs_readl(field);
1048}
1049
96304217 1050static __always_inline u32 vmcs_read32(unsigned long field)
6aa8b732
AK		 1051{
1052 return vmcs_readl(field);
1053}
1054
96304217 1055static __always_inline u64 vmcs_read64(unsigned long field)
6aa8b732 1056{
05b3e0c2 1057#ifdef CONFIG_X86_64
6aa8b732
AK		 1058 return vmcs_readl(field);
1059#else
1060 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1061#endif
1062}
1063
e52de1b8
AK		 1064static noinline void vmwrite_error(unsigned long field, unsigned long value)
1065{
1066 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1067 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1068 dump_stack();
1069}
1070
6aa8b732
AK		 1071static void vmcs_writel(unsigned long field, unsigned long value)
1072{
1073 u8 error;
1074
4ecac3fd 1075 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
d77c26fc 1076 : "=q"(error) : "a"(value), "d"(field) : "cc");
e52de1b8
AK		 1077 if (unlikely(error))
1078 vmwrite_error(field, value);
6aa8b732
AK		 1079}
1080
1081static void vmcs_write16(unsigned long field, u16 value)
1082{
1083 vmcs_writel(field, value);
1084}
1085
1086static void vmcs_write32(unsigned long field, u32 value)
1087{
1088 vmcs_writel(field, value);
1089}
1090
1091static void vmcs_write64(unsigned long field, u64 value)
1092{
6aa8b732 1093 vmcs_writel(field, value);
7682f2d0 1094#ifndef CONFIG_X86_64
6aa8b732
AK		 1095 asm volatile ("");
1096 vmcs_writel(field+1, value >> 32);
1097#endif
1098}
1099
2ab455cc
AL		 1100static void vmcs_clear_bits(unsigned long field, u32 mask)
1101{
1102 vmcs_writel(field, vmcs_readl(field) & ~mask);
1103}
1104
1105static void vmcs_set_bits(unsigned long field, u32 mask)
1106{
1107 vmcs_writel(field, vmcs_readl(field) | mask);
1108}
1109
2fb92db1
AK		 1110static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1111{
1112 vmx->segment_cache.bitmask = 0;
1113}
1114
1115static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1116 unsigned field)
1117{
1118 bool ret;
1119 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1120
1121 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1122 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1123 vmx->segment_cache.bitmask = 0;
1124 }
1125 ret = vmx->segment_cache.bitmask & mask;
1126 vmx->segment_cache.bitmask |= mask;
1127 return ret;
1128}
1129
1130static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1131{
1132 u16 *p = &vmx->segment_cache.seg[seg].selector;
1133
1134 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1135 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1136 return *p;
1137}
1138
1139static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1140{
1141 ulong *p = &vmx->segment_cache.seg[seg].base;
1142
1143 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1144 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1145 return *p;
1146}
1147
1148static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1149{
1150 u32 *p = &vmx->segment_cache.seg[seg].limit;
1151
1152 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1153 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1154 return *p;
1155}
1156
1157static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1158{
1159 u32 *p = &vmx->segment_cache.seg[seg].ar;
1160
1161 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1162 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1163 return *p;
1164}
1165
abd3f2d6
AK		 1166static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1167{
1168 u32 eb;
1169
fd7373cc
JK		 1170 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1171 (1u << NM_VECTOR) | (1u << DB_VECTOR);
1172 if ((vcpu->guest_debug &
1173 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1174 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1175 eb |= 1u << BP_VECTOR;
7ffd92c5 1176 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 1177 eb = ~0;
089d034e 1178 if (enable_ept)
1439442c 1179 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
02daab21
AK		 1180 if (vcpu->fpu_active)
1181 eb &= ~(1u << NM_VECTOR);
abd3f2d6
AK		 1182 vmcs_write32(EXCEPTION_BITMAP, eb);
1183}
1184
61d2ef2c
AK		 1185static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1186{
1187 unsigned i;
1188 struct msr_autoload *m = &vmx->msr_autoload;
1189
110312c8
AK		 1190 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1191 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1192 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1193 return;
1194 }
1195
61d2ef2c
AK		 1196 for (i = 0; i < m->nr; ++i)
1197 if (m->guest[i].index == msr)
1198 break;
1199
1200 if (i == m->nr)
1201 return;
1202 --m->nr;
1203 m->guest[i] = m->guest[m->nr];
1204 m->host[i] = m->host[m->nr];
1205 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1206 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1207}
1208
1209static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1210 u64 guest_val, u64 host_val)
1211{
1212 unsigned i;
1213 struct msr_autoload *m = &vmx->msr_autoload;
1214
110312c8
AK		 1215 if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1216 vmcs_write64(GUEST_IA32_EFER, guest_val);
1217 vmcs_write64(HOST_IA32_EFER, host_val);
1218 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1219 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1220 return;
1221 }
1222
61d2ef2c
AK		 1223 for (i = 0; i < m->nr; ++i)
1224 if (m->guest[i].index == msr)
1225 break;
1226
1227 if (i == m->nr) {
1228 ++m->nr;
1229 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1230 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1231 }
1232
1233 m->guest[i].index = msr;
1234 m->guest[i].value = guest_val;
1235 m->host[i].index = msr;
1236 m->host[i].value = host_val;
1237}
1238
33ed6329
AK		 1239static void reload_tss(void)
1240{
33ed6329
AK		 1241 /*
1242 * VT restores TR but not its size. Useless.
1243 */
d359192f 1244 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
a5f61300 1245 struct desc_struct *descs;
33ed6329 1246
d359192f 1247 descs = (void *)gdt->address;
33ed6329
AK		 1248 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1249 load_TR_desc();
33ed6329
AK		 1250}
1251
92c0d900 1252static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 1253{
3a34a881 1254 u64 guest_efer;
51c6cf66
AK		 1255 u64 ignore_bits;
1256
f6801dff 1257 guest_efer = vmx->vcpu.arch.efer;
3a34a881 1258
51c6cf66
AK		 1259 /*
1260 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1261 * outside long mode
1262 */
1263 ignore_bits = EFER_NX | EFER_SCE;
1264#ifdef CONFIG_X86_64
1265 ignore_bits |= EFER_LMA | EFER_LME;
1266 /* SCE is meaningful only in long mode on Intel */
1267 if (guest_efer & EFER_LMA)
1268 ignore_bits &= ~(u64)EFER_SCE;
1269#endif
51c6cf66
AK		 1270 guest_efer &= ~ignore_bits;
1271 guest_efer |= host_efer & ignore_bits;
26bb0981 1272 vmx->guest_msrs[efer_offset].data = guest_efer;
d5696725 1273 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef
AK		 1274
1275 clear_atomic_switch_msr(vmx, MSR_EFER);
1276 /* On ept, can't emulate nx, and must switch nx atomically */
1277 if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1278 guest_efer = vmx->vcpu.arch.efer;
1279 if (!(guest_efer & EFER_LMA))
1280 guest_efer &= ~EFER_LME;
1281 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1282 return false;
1283 }
1284
26bb0981 1285 return true;
51c6cf66
AK		 1286}
1287
2d49ec72
GN		 1288static unsigned long segment_base(u16 selector)
1289{
d359192f 1290 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
2d49ec72
GN		 1291 struct desc_struct *d;
1292 unsigned long table_base;
1293 unsigned long v;
1294
1295 if (!(selector & ~3))
1296 return 0;
1297
d359192f 1298 table_base = gdt->address;
2d49ec72
GN		 1299
1300 if (selector & 4) { /* from ldt */
1301 u16 ldt_selector = kvm_read_ldt();
1302
1303 if (!(ldt_selector & ~3))
1304 return 0;
1305
1306 table_base = segment_base(ldt_selector);
1307 }
1308 d = (struct desc_struct *)(table_base + (selector & ~7));
1309 v = get_desc_base(d);
1310#ifdef CONFIG_X86_64
1311 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1312 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1313#endif
1314 return v;
1315}
1316
1317static inline unsigned long kvm_read_tr_base(void)
1318{
1319 u16 tr;
1320 asm("str %0" : "=g"(tr));
1321 return segment_base(tr);
1322}
1323
04d2cc77 1324static void vmx_save_host_state(struct kvm_vcpu *vcpu)
33ed6329 1325{
04d2cc77 1326 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1327 int i;
04d2cc77 1328
a2fa3e9f 1329 if (vmx->host_state.loaded)
33ed6329
AK		 1330 return;
1331
a2fa3e9f 1332 vmx->host_state.loaded = 1;
33ed6329
AK		 1333 /*
1334 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
1335 * allow segment selectors with cpl > 0 or ti == 1.
1336 */
d6e88aec 1337 vmx->host_state.ldt_sel = kvm_read_ldt();
152d3f2f 1338 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
9581d442 1339 savesegment(fs, vmx->host_state.fs_sel);
152d3f2f 1340 if (!(vmx->host_state.fs_sel & 7)) {
a2fa3e9f 1341 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
152d3f2f
LV		 1342 vmx->host_state.fs_reload_needed = 0;
1343 } else {
33ed6329 1344 vmcs_write16(HOST_FS_SELECTOR, 0);
152d3f2f 1345 vmx->host_state.fs_reload_needed = 1;
33ed6329 1346 }
9581d442 1347 savesegment(gs, vmx->host_state.gs_sel);
a2fa3e9f
GH		 1348 if (!(vmx->host_state.gs_sel & 7))
1349 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
33ed6329
AK		 1350 else {
1351 vmcs_write16(HOST_GS_SELECTOR, 0);
152d3f2f 1352 vmx->host_state.gs_ldt_reload_needed = 1;
33ed6329
AK		 1353 }
1354
1355#ifdef CONFIG_X86_64
1356 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1357 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1358#else
a2fa3e9f
GH		 1359 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1360 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
33ed6329 1361#endif
707c0874
AK		 1362
1363#ifdef CONFIG_X86_64
c8770e7b
AK		 1364 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1365 if (is_long_mode(&vmx->vcpu))
44ea2b17 1366 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
707c0874 1367#endif
26bb0981
AK		 1368 for (i = 0; i < vmx->save_nmsrs; ++i)
1369 kvm_set_shared_msr(vmx->guest_msrs[i].index,
d5696725
AK		 1370 vmx->guest_msrs[i].data,
1371 vmx->guest_msrs[i].mask);
33ed6329
AK		 1372}
1373
a9b21b62 1374static void __vmx_load_host_state(struct vcpu_vmx *vmx)
33ed6329 1375{
a2fa3e9f 1376 if (!vmx->host_state.loaded)
33ed6329
AK		 1377 return;
1378
e1beb1d3 1379 ++vmx->vcpu.stat.host_state_reload;
a2fa3e9f 1380 vmx->host_state.loaded = 0;
c8770e7b
AK		 1381#ifdef CONFIG_X86_64
1382 if (is_long_mode(&vmx->vcpu))
1383 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1384#endif
152d3f2f 1385 if (vmx->host_state.gs_ldt_reload_needed) {
d6e88aec 1386 kvm_load_ldt(vmx->host_state.ldt_sel);
33ed6329 1387#ifdef CONFIG_X86_64
9581d442 1388 load_gs_index(vmx->host_state.gs_sel);
9581d442
AK		 1389#else
1390 loadsegment(gs, vmx->host_state.gs_sel);
33ed6329 1391#endif
33ed6329 1392 }
0a77fe4c
AK		 1393 if (vmx->host_state.fs_reload_needed)
1394 loadsegment(fs, vmx->host_state.fs_sel);
152d3f2f 1395 reload_tss();
44ea2b17 1396#ifdef CONFIG_X86_64
c8770e7b 1397 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1398#endif
1c11e713
AK		 1399 if (current_thread_info()->status & TS_USEDFPU)
1400 clts();
3444d7da 1401 load_gdt(&__get_cpu_var(host_gdt));
33ed6329
AK		 1402}
1403
a9b21b62
AK		 1404static void vmx_load_host_state(struct vcpu_vmx *vmx)
1405{
1406 preempt_disable();
1407 __vmx_load_host_state(vmx);
1408 preempt_enable();
1409}
1410
6aa8b732
AK		 1411/*
1412 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1413 * vcpu mutex is already taken.
1414 */
15ad7146 1415static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1416{
a2fa3e9f 1417 struct vcpu_vmx *vmx = to_vmx(vcpu);
4610c9cc 1418 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
6aa8b732 1419
4610c9cc
DX		 1420 if (!vmm_exclusive)
1421 kvm_cpu_vmxon(phys_addr);
d462b819
NHE		 1422 else if (vmx->loaded_vmcs->cpu != cpu)
1423 loaded_vmcs_clear(vmx->loaded_vmcs);
6aa8b732 1424
d462b819
NHE		 1425 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1426 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1427 vmcs_load(vmx->loaded_vmcs->vmcs);
6aa8b732
AK		 1428 }
1429
d462b819 1430 if (vmx->loaded_vmcs->cpu != cpu) {
d359192f 1431 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
6aa8b732
AK		 1432 unsigned long sysenter_esp;
1433
a8eeb04a 1434 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1435 local_irq_disable();
d462b819
NHE		 1436 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1437 &per_cpu(loaded_vmcss_on_cpu, cpu));
92fe13be
DX		 1438 local_irq_enable();
1439
6aa8b732
AK		 1440 /*
1441 * Linux uses per-cpu TSS and GDT, so set these when switching
1442 * processors.
1443 */
d6e88aec 1444 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
d359192f 1445 vmcs_writel(HOST_GDTR_BASE, gdt->address); /* 22.2.4 */
6aa8b732
AK		 1446
1447 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1448 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
d462b819 1449 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1450 }
6aa8b732
AK		 1451}
1452
1453static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1454{
a9b21b62 1455 __vmx_load_host_state(to_vmx(vcpu));
4610c9cc 1456 if (!vmm_exclusive) {
d462b819
NHE		 1457 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1458 vcpu->cpu = -1;
4610c9cc
DX		 1459 kvm_cpu_vmxoff();
1460 }
6aa8b732
AK		 1461}
1462
5fd86fcf
AK		 1463static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1464{
81231c69
AK		 1465 ulong cr0;
1466
5fd86fcf
AK		 1467 if (vcpu->fpu_active)
1468 return;
1469 vcpu->fpu_active = 1;
81231c69
AK		 1470 cr0 = vmcs_readl(GUEST_CR0);
1471 cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1472 cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1473 vmcs_writel(GUEST_CR0, cr0);
5fd86fcf 1474 update_exception_bitmap(vcpu);
edcafe3c
AK		 1475 vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1476 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
5fd86fcf
AK		 1477}
1478
edcafe3c
AK		 1479static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1480
fe3ef05c
NHE		 1481/*
1482 * Return the cr0 value that a nested guest would read. This is a combination
1483 * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1484 * its hypervisor (cr0_read_shadow).
1485 */
1486static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1487{
1488 return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1489 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1490}
1491static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1492{
1493 return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1494 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1495}
1496
5fd86fcf
AK		 1497static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1498{
edcafe3c 1499 vmx_decache_cr0_guest_bits(vcpu);
81231c69 1500 vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
5fd86fcf 1501 update_exception_bitmap(vcpu);
edcafe3c
AK		 1502 vcpu->arch.cr0_guest_owned_bits = 0;
1503 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1504 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
5fd86fcf
AK		 1505}
1506
6aa8b732
AK		 1507static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1508{
78ac8b47 1509 unsigned long rflags, save_rflags;
345dcaa8 1510
6de12732
AK		 1511 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1512 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1513 rflags = vmcs_readl(GUEST_RFLAGS);
1514 if (to_vmx(vcpu)->rmode.vm86_active) {
1515 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1516 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1517 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1518 }
1519 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1520 }
6de12732 1521 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1522}
1523
1524static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1525{
6de12732 1526 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
69c73028 1527 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6de12732 1528 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1529 if (to_vmx(vcpu)->rmode.vm86_active) {
1530 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1531 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1532 }
6aa8b732
AK		 1533 vmcs_writel(GUEST_RFLAGS, rflags);
1534}
1535
2809f5d2
GC		 1536static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1537{
1538 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1539 int ret = 0;
1540
1541 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1542 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1543 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1544 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2
GC		 1545
1546 return ret & mask;
1547}
1548
1549static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1550{
1551 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1552 u32 interruptibility = interruptibility_old;
1553
1554 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1555
48005f64 1556 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1557 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1558 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1559 interruptibility |= GUEST_INTR_STATE_STI;
1560
1561 if ((interruptibility != interruptibility_old))
1562 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1563}
1564
6aa8b732
AK		 1565static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1566{
1567 unsigned long rip;
6aa8b732 1568
5fdbf976 1569 rip = kvm_rip_read(vcpu);
6aa8b732 1570 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1571 kvm_rip_write(vcpu, rip);
6aa8b732 1572
2809f5d2
GC		 1573 /* skipping an emulated instruction also counts */
1574 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1575}
1576
443381a8
AL		 1577static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1578{
1579 /* Ensure that we clear the HLT state in the VMCS. We don't need to
1580 * explicitly skip the instruction because if the HLT state is set, then
1581 * the instruction is already executing and RIP has already been
1582 * advanced. */
1583 if (!yield_on_hlt &&
1584 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1585 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1586}
1587
0b6ac343
NHE		 1588/*
1589 * KVM wants to inject page-faults which it got to the guest. This function
1590 * checks whether in a nested guest, we need to inject them to L1 or L2.
1591 * This function assumes it is called with the exit reason in vmcs02 being
1592 * a #PF exception (this is the only case in which KVM injects a #PF when L2
1593 * is running).
1594 */
1595static int nested_pf_handled(struct kvm_vcpu *vcpu)
1596{
1597 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1598
1599 /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1600 if (!(vmcs12->exception_bitmap & PF_VECTOR))
1601 return 0;
1602
1603 nested_vmx_vmexit(vcpu);
1604 return 1;
1605}
1606
298101da 1607static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
ce7ddec4
JR		 1608 bool has_error_code, u32 error_code,
1609 bool reinject)
298101da 1610{
77ab6db0 1611 struct vcpu_vmx *vmx = to_vmx(vcpu);
8ab2d2e2 1612 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1613
0b6ac343
NHE		 1614 if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1615 nested_pf_handled(vcpu))
1616 return;
1617
8ab2d2e2 1618 if (has_error_code) {
77ab6db0 1619 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1620 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1621 }
77ab6db0 1622
7ffd92c5 1623 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1624 int inc_eip = 0;
1625 if (kvm_exception_is_soft(nr))
1626 inc_eip = vcpu->arch.event_exit_inst_len;
1627 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1628 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1629 return;
1630 }
1631
66fd3f7f
GN		 1632 if (kvm_exception_is_soft(nr)) {
1633 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1634 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1635 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1636 } else
1637 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1638
1639 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
443381a8 1640 vmx_clear_hlt(vcpu);
298101da
AK		 1641}
1642
4e47c7a6
SY		 1643static bool vmx_rdtscp_supported(void)
1644{
1645 return cpu_has_vmx_rdtscp();
1646}
1647
a75beee6
ED		 1648/*
1649 * Swap MSR entry in host/guest MSR entry array.
1650 */
8b9cf98c 1651static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1652{
26bb0981 1653 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1654
1655 tmp = vmx->guest_msrs[to];
1656 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1657 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1658}
1659
e38aea3e
AK		 1660/*
1661 * Set up the vmcs to automatically save and restore system
1662 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1663 * mode, as fiddling with msrs is very expensive.
1664 */
8b9cf98c 1665static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1666{
26bb0981 1667 int save_nmsrs, index;
5897297b 1668 unsigned long *msr_bitmap;
e38aea3e 1669
33f9c505 1670 vmx_load_host_state(vmx);
a75beee6
ED		 1671 save_nmsrs = 0;
1672#ifdef CONFIG_X86_64
8b9cf98c 1673 if (is_long_mode(&vmx->vcpu)) {
8b9cf98c 1674 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
a75beee6 1675 if (index >= 0)
8b9cf98c
RR		 1676 move_msr_up(vmx, index, save_nmsrs++);
1677 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1678 if (index >= 0)
8b9cf98c
RR		 1679 move_msr_up(vmx, index, save_nmsrs++);
1680 index = __find_msr_index(vmx, MSR_CSTAR);
a75beee6 1681 if (index >= 0)
8b9cf98c 1682 move_msr_up(vmx, index, save_nmsrs++);
4e47c7a6
SY		 1683 index = __find_msr_index(vmx, MSR_TSC_AUX);
1684 if (index >= 0 && vmx->rdtscp_enabled)
1685 move_msr_up(vmx, index, save_nmsrs++);
a75beee6 1686 /*
8c06585d 1687 * MSR_STAR is only needed on long mode guests, and only
a75beee6
ED		 1688 * if efer.sce is enabled.
1689 */
8c06585d 1690 index = __find_msr_index(vmx, MSR_STAR);
f6801dff 1691 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
8b9cf98c 1692 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1693 }
1694#endif
92c0d900
AK		 1695 index = __find_msr_index(vmx, MSR_EFER);
1696 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1697 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1698
26bb0981 1699 vmx->save_nmsrs = save_nmsrs;
5897297b
AK		 1700
1701 if (cpu_has_vmx_msr_bitmap()) {
1702 if (is_long_mode(&vmx->vcpu))
1703 msr_bitmap = vmx_msr_bitmap_longmode;
1704 else
1705 msr_bitmap = vmx_msr_bitmap_legacy;
1706
1707 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1708 }
e38aea3e
AK		 1709}
1710
6aa8b732
AK		 1711/*
1712 * reads and returns guest's timestamp counter "register"
1713 * guest_tsc = host_tsc + tsc_offset -- 21.3
1714 */
1715static u64 guest_read_tsc(void)
1716{
1717 u64 host_tsc, tsc_offset;
1718
1719 rdtscll(host_tsc);
1720 tsc_offset = vmcs_read64(TSC_OFFSET);
1721 return host_tsc + tsc_offset;
1722}
1723
4051b188
JR		 1724/*
1725 * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1726 * ioctl. In this case the call-back should update internal vmx state to make
1727 * the changes effective.
1728 */
1729static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1730{
1731 /* Nothing to do here */
1732}
1733
6aa8b732 1734/*
99e3e30a 1735 * writes 'offset' into guest's timestamp counter offset register
6aa8b732 1736 */
99e3e30a 1737static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1738{
f4e1b3c8 1739 vmcs_write64(TSC_OFFSET, offset);
6aa8b732
AK		 1740}
1741
e48672fa
ZA		 1742static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1743{
1744 u64 offset = vmcs_read64(TSC_OFFSET);
1745 vmcs_write64(TSC_OFFSET, offset + adjustment);
1746}
1747
857e4099
JR		 1748static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1749{
1750 return target_tsc - native_read_tsc();
1751}
1752
801d3424
NHE		 1753static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1754{
1755 struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1756 return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1757}
1758
1759/*
1760 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1761 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1762 * all guests if the "nested" module option is off, and can also be disabled
1763 * for a single guest by disabling its VMX cpuid bit.
1764 */
1765static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1766{
1767 return nested && guest_cpuid_has_vmx(vcpu);
1768}
1769
b87a51ae
NHE		 1770/*
1771 * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1772 * returned for the various VMX controls MSRs when nested VMX is enabled.
1773 * The same values should also be used to verify that vmcs12 control fields are
1774 * valid during nested entry from L1 to L2.
1775 * Each of these control msrs has a low and high 32-bit half: A low bit is on
1776 * if the corresponding bit in the (32-bit) control field *must* be on, and a
1777 * bit in the high half is on if the corresponding bit in the control field
1778 * may be on. See also vmx_control_verify().
1779 * TODO: allow these variables to be modified (downgraded) by module options
1780 * or other means.
1781 */
1782static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1783static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1784static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1785static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1786static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1787static __init void nested_vmx_setup_ctls_msrs(void)
1788{
1789 /*
1790 * Note that as a general rule, the high half of the MSRs (bits in
1791 * the control fields which may be 1) should be initialized by the
1792 * intersection of the underlying hardware's MSR (i.e., features which
1793 * can be supported) and the list of features we want to expose -
1794 * because they are known to be properly supported in our code.
1795 * Also, usually, the low half of the MSRs (bits which must be 1) can
1796 * be set to 0, meaning that L1 may turn off any of these bits. The
1797 * reason is that if one of these bits is necessary, it will appear
1798 * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1799 * fields of vmcs01 and vmcs02, will turn these bits off - and
1800 * nested_vmx_exit_handled() will not pass related exits to L1.
1801 * These rules have exceptions below.
1802 */
1803
1804 /* pin-based controls */
1805 /*
1806 * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1807 * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1808 */
1809 nested_vmx_pinbased_ctls_low = 0x16 ;
1810 nested_vmx_pinbased_ctls_high = 0x16 |
1811 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1812 PIN_BASED_VIRTUAL_NMIS;
1813
1814 /* exit controls */
1815 nested_vmx_exit_ctls_low = 0;
b6f1250e 1816 /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
b87a51ae
NHE		 1817#ifdef CONFIG_X86_64
1818 nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1819#else
1820 nested_vmx_exit_ctls_high = 0;
1821#endif
1822
1823 /* entry controls */
1824 rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1825 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1826 nested_vmx_entry_ctls_low = 0;
1827 nested_vmx_entry_ctls_high &=
1828 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1829
1830 /* cpu-based controls */
1831 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1832 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1833 nested_vmx_procbased_ctls_low = 0;
1834 nested_vmx_procbased_ctls_high &=
1835 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1836 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1837 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1838 CPU_BASED_CR3_STORE_EXITING |
1839#ifdef CONFIG_X86_64
1840 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1841#endif
1842 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1843 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1844 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1845 /*
1846 * We can allow some features even when not supported by the
1847 * hardware. For example, L1 can specify an MSR bitmap - and we
1848 * can use it to avoid exits to L1 - even when L0 runs L2
1849 * without MSR bitmaps.
1850 */
1851 nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1852
1853 /* secondary cpu-based controls */
1854 rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1855 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1856 nested_vmx_secondary_ctls_low = 0;
1857 nested_vmx_secondary_ctls_high &=
1858 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1859}
1860
1861static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1862{
1863 /*
1864 * Bits 0 in high must be 0, and bits 1 in low must be 1.
1865 */
1866 return ((control & high) | low) == control;
1867}
1868
1869static inline u64 vmx_control_msr(u32 low, u32 high)
1870{
1871 return low | ((u64)high << 32);
1872}
1873
1874/*
1875 * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1876 * also let it use VMX-specific MSRs.
1877 * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1878 * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1879 * like all other MSRs).
1880 */
1881static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1882{
1883 if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
1884 msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
1885 /*
1886 * According to the spec, processors which do not support VMX
1887 * should throw a #GP(0) when VMX capability MSRs are read.
1888 */
1889 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
1890 return 1;
1891 }
1892
1893 switch (msr_index) {
1894 case MSR_IA32_FEATURE_CONTROL:
1895 *pdata = 0;
1896 break;
1897 case MSR_IA32_VMX_BASIC:
1898 /*
1899 * This MSR reports some information about VMX support. We
1900 * should return information about the VMX we emulate for the
1901 * guest, and the VMCS structure we give it - not about the
1902 * VMX support of the underlying hardware.
1903 */
1904 *pdata = VMCS12_REVISION |
1905 ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
1906 (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
1907 break;
1908 case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
1909 case MSR_IA32_VMX_PINBASED_CTLS:
1910 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
1911 nested_vmx_pinbased_ctls_high);
1912 break;
1913 case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
1914 case MSR_IA32_VMX_PROCBASED_CTLS:
1915 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
1916 nested_vmx_procbased_ctls_high);
1917 break;
1918 case MSR_IA32_VMX_TRUE_EXIT_CTLS:
1919 case MSR_IA32_VMX_EXIT_CTLS:
1920 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
1921 nested_vmx_exit_ctls_high);
1922 break;
1923 case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
1924 case MSR_IA32_VMX_ENTRY_CTLS:
1925 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
1926 nested_vmx_entry_ctls_high);
1927 break;
1928 case MSR_IA32_VMX_MISC:
1929 *pdata = 0;
1930 break;
1931 /*
1932 * These MSRs specify bits which the guest must keep fixed (on or off)
1933 * while L1 is in VMXON mode (in L1's root mode, or running an L2).
1934 * We picked the standard core2 setting.
1935 */
1936#define VMXON_CR0_ALWAYSON (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
1937#define VMXON_CR4_ALWAYSON X86_CR4_VMXE
1938 case MSR_IA32_VMX_CR0_FIXED0:
1939 *pdata = VMXON_CR0_ALWAYSON;
1940 break;
1941 case MSR_IA32_VMX_CR0_FIXED1:
1942 *pdata = -1ULL;
1943 break;
1944 case MSR_IA32_VMX_CR4_FIXED0:
1945 *pdata = VMXON_CR4_ALWAYSON;
1946 break;
1947 case MSR_IA32_VMX_CR4_FIXED1:
1948 *pdata = -1ULL;
1949 break;
1950 case MSR_IA32_VMX_VMCS_ENUM:
1951 *pdata = 0x1f;
1952 break;
1953 case MSR_IA32_VMX_PROCBASED_CTLS2:
1954 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
1955 nested_vmx_secondary_ctls_high);
1956 break;
1957 case MSR_IA32_VMX_EPT_VPID_CAP:
1958 /* Currently, no nested ept or nested vpid */
1959 *pdata = 0;
1960 break;
1961 default:
1962 return 0;
1963 }
1964
1965 return 1;
1966}
1967
1968static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1969{
1970 if (!nested_vmx_allowed(vcpu))
1971 return 0;
1972
1973 if (msr_index == MSR_IA32_FEATURE_CONTROL)
1974 /* TODO: the right thing. */
1975 return 1;
1976 /*
1977 * No need to treat VMX capability MSRs specially: If we don't handle
1978 * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
1979 */
1980 return 0;
1981}
1982
6aa8b732
AK		 1983/*
1984 * Reads an msr value (of 'msr_index') into 'pdata'.
1985 * Returns 0 on success, non-0 otherwise.
1986 * Assumes vcpu_load() was already called.
1987 */
1988static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1989{
1990 u64 data;
26bb0981 1991 struct shared_msr_entry *msr;
6aa8b732
AK		 1992
1993 if (!pdata) {
1994 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1995 return -EINVAL;
1996 }
1997
1998 switch (msr_index) {
05b3e0c2 1999#ifdef CONFIG_X86_64
6aa8b732
AK		 2000 case MSR_FS_BASE:
2001 data = vmcs_readl(GUEST_FS_BASE);
2002 break;
2003 case MSR_GS_BASE:
2004 data = vmcs_readl(GUEST_GS_BASE);
2005 break;
44ea2b17
AK		 2006 case MSR_KERNEL_GS_BASE:
2007 vmx_load_host_state(to_vmx(vcpu));
2008 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2009 break;
26bb0981 2010#endif
6aa8b732 2011 case MSR_EFER:
3bab1f5d 2012 return kvm_get_msr_common(vcpu, msr_index, pdata);
af24a4e4 2013 case MSR_IA32_TSC:
6aa8b732
AK		 2014 data = guest_read_tsc();
2015 break;
2016 case MSR_IA32_SYSENTER_CS:
2017 data = vmcs_read32(GUEST_SYSENTER_CS);
2018 break;
2019 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2020 data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 2021 break;
2022 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2023 data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 2024 break;
4e47c7a6
SY		 2025 case MSR_TSC_AUX:
2026 if (!to_vmx(vcpu)->rdtscp_enabled)
2027 return 1;
2028 /* Otherwise falls through */
6aa8b732 2029 default:
26bb0981 2030 vmx_load_host_state(to_vmx(vcpu));
b87a51ae
NHE		 2031 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2032 return 0;
8b9cf98c 2033 msr = find_msr_entry(to_vmx(vcpu), msr_index);
3bab1f5d 2034 if (msr) {
542423b0 2035 vmx_load_host_state(to_vmx(vcpu));
3bab1f5d
AK		 2036 data = msr->data;
2037 break;
6aa8b732 2038 }
3bab1f5d 2039 return kvm_get_msr_common(vcpu, msr_index, pdata);
6aa8b732
AK		 2040 }
2041
2042 *pdata = data;
2043 return 0;
2044}
2045
2046/*
2047 * Writes msr value into into the appropriate "register".
2048 * Returns 0 on success, non-0 otherwise.
2049 * Assumes vcpu_load() was already called.
2050 */
2051static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2052{
a2fa3e9f 2053 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 2054 struct shared_msr_entry *msr;
2cc51560
ED		 2055 int ret = 0;
2056
6aa8b732 2057 switch (msr_index) {
3bab1f5d 2058 case MSR_EFER:
a9b21b62 2059 vmx_load_host_state(vmx);
2cc51560 2060 ret = kvm_set_msr_common(vcpu, msr_index, data);
2cc51560 2061 break;
16175a79 2062#ifdef CONFIG_X86_64
6aa8b732 2063 case MSR_FS_BASE:
2fb92db1 2064 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2065 vmcs_writel(GUEST_FS_BASE, data);
2066 break;
2067 case MSR_GS_BASE:
2fb92db1 2068 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 2069 vmcs_writel(GUEST_GS_BASE, data);
2070 break;
44ea2b17
AK		 2071 case MSR_KERNEL_GS_BASE:
2072 vmx_load_host_state(vmx);
2073 vmx->msr_guest_kernel_gs_base = data;
2074 break;
6aa8b732
AK		 2075#endif
2076 case MSR_IA32_SYSENTER_CS:
2077 vmcs_write32(GUEST_SYSENTER_CS, data);
2078 break;
2079 case MSR_IA32_SYSENTER_EIP:
f5b42c33 2080 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 2081 break;
2082 case MSR_IA32_SYSENTER_ESP:
f5b42c33 2083 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 2084 break;
af24a4e4 2085 case MSR_IA32_TSC:
99e3e30a 2086 kvm_write_tsc(vcpu, data);
6aa8b732 2087 break;
468d472f
SY		 2088 case MSR_IA32_CR_PAT:
2089 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2090 vmcs_write64(GUEST_IA32_PAT, data);
2091 vcpu->arch.pat = data;
2092 break;
2093 }
4e47c7a6
SY		 2094 ret = kvm_set_msr_common(vcpu, msr_index, data);
2095 break;
2096 case MSR_TSC_AUX:
2097 if (!vmx->rdtscp_enabled)
2098 return 1;
2099 /* Check reserved bit, higher 32 bits should be zero */
2100 if ((data >> 32) != 0)
2101 return 1;
2102 /* Otherwise falls through */
6aa8b732 2103 default:
b87a51ae
NHE		 2104 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2105 break;
8b9cf98c 2106 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 2107 if (msr) {
542423b0 2108 vmx_load_host_state(vmx);
3bab1f5d
AK		 2109 msr->data = data;
2110 break;
6aa8b732 2111 }
2cc51560 2112 ret = kvm_set_msr_common(vcpu, msr_index, data);
6aa8b732
AK		 2113 }
2114
2cc51560 2115 return ret;
6aa8b732
AK		 2116}
2117
5fdbf976 2118static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 2119{
5fdbf976
MT		 2120 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2121 switch (reg) {
2122 case VCPU_REGS_RSP:
2123 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2124 break;
2125 case VCPU_REGS_RIP:
2126 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2127 break;
6de4f3ad
AK		 2128 case VCPU_EXREG_PDPTR:
2129 if (enable_ept)
2130 ept_save_pdptrs(vcpu);
2131 break;
5fdbf976
MT		 2132 default:
2133 break;
2134 }
6aa8b732
AK		 2135}
2136
355be0b9 2137static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
6aa8b732 2138{
ae675ef0
JK		 2139 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2140 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2141 else
2142 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2143
abd3f2d6 2144 update_exception_bitmap(vcpu);
6aa8b732
AK		 2145}
2146
2147static __init int cpu_has_kvm_support(void)
2148{
6210e37b 2149 return cpu_has_vmx();
6aa8b732
AK		 2150}
2151
2152static __init int vmx_disabled_by_bios(void)
2153{
2154 u64 msr;
2155
2156 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 2157 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 2158 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 2159 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2160 && tboot_enabled())
2161 return 1;
23f3e991 2162 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 2163 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 2164 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 2165 && !tboot_enabled()) {
2166 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 2167 "activate TXT before enabling KVM\n");
cafd6659 2168 return 1;
f9335afe 2169 }
23f3e991
JC		 2170 /* launched w/o TXT and VMX disabled */
2171 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2172 && !tboot_enabled())
2173 return 1;
cafd6659
SW		 2174 }
2175
2176 return 0;
6aa8b732
AK		 2177}
2178
7725b894
DX		 2179static void kvm_cpu_vmxon(u64 addr)
2180{
2181 asm volatile (ASM_VMX_VMXON_RAX
2182 : : "a"(&addr), "m"(addr)
2183 : "memory", "cc");
2184}
2185
10474ae8 2186static int hardware_enable(void *garbage)
6aa8b732
AK		 2187{
2188 int cpu = raw_smp_processor_id();
2189 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 2190 u64 old, test_bits;
6aa8b732 2191
10474ae8
AG		 2192 if (read_cr4() & X86_CR4_VMXE)
2193 return -EBUSY;
2194
d462b819 2195 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
6aa8b732 2196 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 2197
2198 test_bits = FEATURE_CONTROL_LOCKED;
2199 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2200 if (tboot_enabled())
2201 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2202
2203 if ((old & test_bits) != test_bits) {
6aa8b732 2204 /* enable and lock */
cafd6659
SW		 2205 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2206 }
66aee91a 2207 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
10474ae8 2208
4610c9cc
DX		 2209 if (vmm_exclusive) {
2210 kvm_cpu_vmxon(phys_addr);
2211 ept_sync_global();
2212 }
10474ae8 2213
3444d7da
AK		 2214 store_gdt(&__get_cpu_var(host_gdt));
2215
10474ae8 2216 return 0;
6aa8b732
AK		 2217}
2218
d462b819 2219static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 2220{
2221 int cpu = raw_smp_processor_id();
d462b819 2222 struct loaded_vmcs *v, *n;
543e4243 2223
d462b819
NHE		 2224 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2225 loaded_vmcss_on_cpu_link)
2226 __loaded_vmcs_clear(v);
543e4243
AK		 2227}
2228
710ff4a8
EH		 2229
2230/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2231 * tricks.
2232 */
2233static void kvm_cpu_vmxoff(void)
6aa8b732 2234{
4ecac3fd 2235 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
6aa8b732
AK		 2236}
2237
710ff4a8
EH		 2238static void hardware_disable(void *garbage)
2239{
4610c9cc 2240 if (vmm_exclusive) {
d462b819 2241 vmclear_local_loaded_vmcss();
4610c9cc
DX		 2242 kvm_cpu_vmxoff();
2243 }
7725b894 2244 write_cr4(read_cr4() & ~X86_CR4_VMXE);
710ff4a8
EH		 2245}
2246
1c3d14fe 2247static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 2248 u32 msr, u32 *result)
1c3d14fe
YS		 2249{
2250 u32 vmx_msr_low, vmx_msr_high;
2251 u32 ctl = ctl_min | ctl_opt;
2252
2253 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2254
2255 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2256 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
2257
2258 /* Ensure minimum (required) set of control bits are supported. */
2259 if (ctl_min & ~ctl)
002c7f7c 2260 return -EIO;
1c3d14fe
YS		 2261
2262 *result = ctl;
2263 return 0;
2264}
2265
110312c8
AK		 2266static __init bool allow_1_setting(u32 msr, u32 ctl)
2267{
2268 u32 vmx_msr_low, vmx_msr_high;
2269
2270 rdmsr(msr, vmx_msr_low, vmx_msr_high);
2271 return vmx_msr_high & ctl;
2272}
2273
002c7f7c 2274static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
6aa8b732
AK		 2275{
2276 u32 vmx_msr_low, vmx_msr_high;
d56f546d 2277 u32 min, opt, min2, opt2;
1c3d14fe
YS		 2278 u32 _pin_based_exec_control = 0;
2279 u32 _cpu_based_exec_control = 0;
f78e0e2e 2280 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 2281 u32 _vmexit_control = 0;
2282 u32 _vmentry_control = 0;
2283
2284 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
f08864b4 2285 opt = PIN_BASED_VIRTUAL_NMIS;
1c3d14fe
YS		 2286 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2287 &_pin_based_exec_control) < 0)
002c7f7c 2288 return -EIO;
1c3d14fe 2289
443381a8 2290 min =
1c3d14fe
YS		 2291#ifdef CONFIG_X86_64
2292 CPU_BASED_CR8_LOAD_EXITING |
2293 CPU_BASED_CR8_STORE_EXITING |
2294#endif
d56f546d
SY		 2295 CPU_BASED_CR3_LOAD_EXITING |
2296 CPU_BASED_CR3_STORE_EXITING |
1c3d14fe
YS		 2297 CPU_BASED_USE_IO_BITMAPS |
2298 CPU_BASED_MOV_DR_EXITING |
a7052897 2299 CPU_BASED_USE_TSC_OFFSETING |
59708670
SY		 2300 CPU_BASED_MWAIT_EXITING |
2301 CPU_BASED_MONITOR_EXITING |
a7052897 2302 CPU_BASED_INVLPG_EXITING;
443381a8
AL		 2303
2304 if (yield_on_hlt)
2305 min |= CPU_BASED_HLT_EXITING;
2306
f78e0e2e 2307 opt = CPU_BASED_TPR_SHADOW |
25c5f225 2308 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 2309 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 2310 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2311 &_cpu_based_exec_control) < 0)
002c7f7c 2312 return -EIO;
6e5d865c
YS		 2313#ifdef CONFIG_X86_64
2314 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2315 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2316 ~CPU_BASED_CR8_STORE_EXITING;
2317#endif
f78e0e2e 2318 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 2319 min2 = 0;
2320 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2384d2b3 2321 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 2322 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 2323 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 2324 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6
SY		 2325 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2326 SECONDARY_EXEC_RDTSCP;
d56f546d
SY		 2327 if (adjust_vmx_controls(min2, opt2,
2328 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 2329 &_cpu_based_2nd_exec_control) < 0)
2330 return -EIO;
2331 }
2332#ifndef CONFIG_X86_64
2333 if (!(_cpu_based_2nd_exec_control &
2334 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2335 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2336#endif
d56f546d 2337 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2338 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2339 enabled */
5fff7d27
GN		 2340 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2341 CPU_BASED_CR3_STORE_EXITING |
2342 CPU_BASED_INVLPG_EXITING);
d56f546d
SY		 2343 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2344 vmx_capability.ept, vmx_capability.vpid);
2345 }
1c3d14fe
YS		 2346
2347 min = 0;
2348#ifdef CONFIG_X86_64
2349 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2350#endif
468d472f 2351 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1c3d14fe
YS		 2352 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2353 &_vmexit_control) < 0)
002c7f7c 2354 return -EIO;
1c3d14fe 2355
468d472f
SY		 2356 min = 0;
2357 opt = VM_ENTRY_LOAD_IA32_PAT;
1c3d14fe
YS		 2358 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2359 &_vmentry_control) < 0)
002c7f7c 2360 return -EIO;
6aa8b732 2361
c68876fd 2362 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2363
2364 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2365 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2366 return -EIO;
1c3d14fe
YS		 2367
2368#ifdef CONFIG_X86_64
2369 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2370 if (vmx_msr_high & (1u<<16))
002c7f7c 2371 return -EIO;
1c3d14fe
YS		 2372#endif
2373
2374 /* Require Write-Back (WB) memory type for VMCS accesses. */
2375 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2376 return -EIO;
1c3d14fe 2377
002c7f7c
YS		 2378 vmcs_conf->size = vmx_msr_high & 0x1fff;
2379 vmcs_conf->order = get_order(vmcs_config.size);
2380 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2381
002c7f7c
YS		 2382 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2383 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2384 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2385 vmcs_conf->vmexit_ctrl = _vmexit_control;
2386 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2387
110312c8
AK		 2388 cpu_has_load_ia32_efer =
2389 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2390 VM_ENTRY_LOAD_IA32_EFER)
2391 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2392 VM_EXIT_LOAD_IA32_EFER);
2393
1c3d14fe 2394 return 0;
c68876fd 2395}
6aa8b732
AK		 2396
2397static struct vmcs *alloc_vmcs_cpu(int cpu)
2398{
2399 int node = cpu_to_node(cpu);
2400 struct page *pages;
2401 struct vmcs *vmcs;
2402
6484eb3e 2403 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2404 if (!pages)
2405 return NULL;
2406 vmcs = page_address(pages);
1c3d14fe
YS		 2407 memset(vmcs, 0, vmcs_config.size);
2408 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
6aa8b732
AK		 2409 return vmcs;
2410}
2411
2412static struct vmcs *alloc_vmcs(void)
2413{
d3b2c338 2414 return alloc_vmcs_cpu(raw_smp_processor_id());
6aa8b732
AK		 2415}
2416
2417static void free_vmcs(struct vmcs *vmcs)
2418{
1c3d14fe 2419 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2420}
2421
d462b819
NHE		 2422/*
2423 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2424 */
2425static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2426{
2427 if (!loaded_vmcs->vmcs)
2428 return;
2429 loaded_vmcs_clear(loaded_vmcs);
2430 free_vmcs(loaded_vmcs->vmcs);
2431 loaded_vmcs->vmcs = NULL;
2432}
2433
39959588 2434static void free_kvm_area(void)
6aa8b732
AK		 2435{
2436 int cpu;
2437
3230bb47 2438 for_each_possible_cpu(cpu) {
6aa8b732 2439 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2440 per_cpu(vmxarea, cpu) = NULL;
2441 }
6aa8b732
AK		 2442}
2443
6aa8b732
AK		 2444static __init int alloc_kvm_area(void)
2445{
2446 int cpu;
2447
3230bb47 2448 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2449 struct vmcs *vmcs;
2450
2451 vmcs = alloc_vmcs_cpu(cpu);
2452 if (!vmcs) {
2453 free_kvm_area();
2454 return -ENOMEM;
2455 }
2456
2457 per_cpu(vmxarea, cpu) = vmcs;
2458 }
2459 return 0;
2460}
2461
2462static __init int hardware_setup(void)
2463{
002c7f7c
YS		 2464 if (setup_vmcs_config(&vmcs_config) < 0)
2465 return -EIO;
50a37eb4
JR		 2466
2467 if (boot_cpu_has(X86_FEATURE_NX))
2468 kvm_enable_efer_bits(EFER_NX);
2469
93ba03c2
SY		 2470 if (!cpu_has_vmx_vpid())
2471 enable_vpid = 0;
2472
4bc9b982
SY		 2473 if (!cpu_has_vmx_ept() ||
2474 !cpu_has_vmx_ept_4levels()) {
93ba03c2 2475 enable_ept = 0;
3a624e29
NK		 2476 enable_unrestricted_guest = 0;
2477 }
2478
2479 if (!cpu_has_vmx_unrestricted_guest())
2480 enable_unrestricted_guest = 0;
93ba03c2
SY		 2481
2482 if (!cpu_has_vmx_flexpriority())
2483 flexpriority_enabled = 0;
2484
95ba8273
GN		 2485 if (!cpu_has_vmx_tpr_shadow())
2486 kvm_x86_ops->update_cr8_intercept = NULL;
2487
54dee993
MT		 2488 if (enable_ept && !cpu_has_vmx_ept_2m_page())
2489 kvm_disable_largepages();
2490
4b8d54f9
ZE		 2491 if (!cpu_has_vmx_ple())
2492 ple_gap = 0;
2493
b87a51ae
NHE		 2494 if (nested)
2495 nested_vmx_setup_ctls_msrs();
2496
6aa8b732
AK		 2497 return alloc_kvm_area();
2498}
2499
2500static __exit void hardware_unsetup(void)
2501{
2502 free_kvm_area();
2503}
2504
6aa8b732
AK		 2505static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2506{
2507 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2508
6af11b9e 2509 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
6aa8b732
AK		 2510 vmcs_write16(sf->selector, save->selector);
2511 vmcs_writel(sf->base, save->base);
2512 vmcs_write32(sf->limit, save->limit);
2513 vmcs_write32(sf->ar_bytes, save->ar);
2514 } else {
2515 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2516 << AR_DPL_SHIFT;
2517 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2518 }
2519}
2520
2521static void enter_pmode(struct kvm_vcpu *vcpu)
2522{
2523 unsigned long flags;
a89a8fb9 2524 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2525
a89a8fb9 2526 vmx->emulation_required = 1;
7ffd92c5 2527 vmx->rmode.vm86_active = 0;
6aa8b732 2528
2fb92db1
AK		 2529 vmx_segment_cache_clear(vmx);
2530
d0ba64f9 2531 vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
7ffd92c5
AK		 2532 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2533 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2534 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
6aa8b732
AK		 2535
2536 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2537 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2538 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2539 vmcs_writel(GUEST_RFLAGS, flags);
2540
66aee91a
RR		 2541 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2542 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2543
2544 update_exception_bitmap(vcpu);
2545
a89a8fb9
MG		 2546 if (emulate_invalid_guest_state)
2547 return;
2548
7ffd92c5
AK		 2549 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2550 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2551 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2552 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
6aa8b732 2553
2fb92db1
AK		 2554 vmx_segment_cache_clear(vmx);
2555
6aa8b732
AK		 2556 vmcs_write16(GUEST_SS_SELECTOR, 0);
2557 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2558
2559 vmcs_write16(GUEST_CS_SELECTOR,
2560 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2561 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2562}
2563
d77c26fc 2564static gva_t rmode_tss_base(struct kvm *kvm)
6aa8b732 2565{
bfc6d222 2566 if (!kvm->arch.tss_addr) {
bc6678a3
MT		 2567 struct kvm_memslots *slots;
2568 gfn_t base_gfn;
2569
90d83dc3 2570 slots = kvm_memslots(kvm);
f495c6e5 2571 base_gfn = slots->memslots[0].base_gfn +
46a26bf5 2572 kvm->memslots->memslots[0].npages - 3;
cbc94022
IE		 2573 return base_gfn << PAGE_SHIFT;
2574 }
bfc6d222 2575 return kvm->arch.tss_addr;
6aa8b732
AK		 2576}
2577
2578static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2579{
2580 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2581
2582 save->selector = vmcs_read16(sf->selector);
2583 save->base = vmcs_readl(sf->base);
2584 save->limit = vmcs_read32(sf->limit);
2585 save->ar = vmcs_read32(sf->ar_bytes);
15b00f32 2586 vmcs_write16(sf->selector, save->base >> 4);
444e863d 2587 vmcs_write32(sf->base, save->base & 0xffff0);
6aa8b732
AK		 2588 vmcs_write32(sf->limit, 0xffff);
2589 vmcs_write32(sf->ar_bytes, 0xf3);
444e863d
GN		 2590 if (save->base & 0xf)
2591 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2592 " aligned when entering protected mode (seg=%d)",
2593 seg);
6aa8b732
AK		 2594}
2595
2596static void enter_rmode(struct kvm_vcpu *vcpu)
2597{
2598 unsigned long flags;
a89a8fb9 2599 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2600
3a624e29
NK		 2601 if (enable_unrestricted_guest)
2602 return;
2603
a89a8fb9 2604 vmx->emulation_required = 1;
7ffd92c5 2605 vmx->rmode.vm86_active = 1;
6aa8b732 2606
776e58ea
GN		 2607 /*
2608 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2609 * vcpu. Call it here with phys address pointing 16M below 4G.
2610 */
2611 if (!vcpu->kvm->arch.tss_addr) {
2612 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2613 "called before entering vcpu\n");
2614 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2615 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2616 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2617 }
2618
2fb92db1
AK		 2619 vmx_segment_cache_clear(vmx);
2620
d0ba64f9 2621 vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
7ffd92c5 2622 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
6aa8b732
AK		 2623 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2624
7ffd92c5 2625 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
6aa8b732
AK		 2626 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2627
7ffd92c5 2628 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
6aa8b732
AK		 2629 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2630
2631 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2632 vmx->rmode.save_rflags = flags;
6aa8b732 2633
053de044 2634 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2635
2636 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2637 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2638 update_exception_bitmap(vcpu);
2639
a89a8fb9
MG		 2640 if (emulate_invalid_guest_state)
2641 goto continue_rmode;
2642
6aa8b732
AK		 2643 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2644 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2645 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2646
2647 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
abacf8df 2648 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
8cb5b033
AK		 2649 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2650 vmcs_writel(GUEST_CS_BASE, 0xf0000);
6aa8b732
AK		 2651 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2652
7ffd92c5
AK		 2653 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2654 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2655 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2656 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
75880a01 2657
a89a8fb9 2658continue_rmode:
8668a3c4 2659 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2660}
2661
401d10de
AS		 2662static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2663{
2664 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2665 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2666
2667 if (!msr)
2668 return;
401d10de 2669
44ea2b17
AK		 2670 /*
2671 * Force kernel_gs_base reloading before EFER changes, as control
2672 * of this msr depends on is_long_mode().
2673 */
2674 vmx_load_host_state(to_vmx(vcpu));
f6801dff 2675 vcpu->arch.efer = efer;
401d10de
AS		 2676 if (efer & EFER_LMA) {
2677 vmcs_write32(VM_ENTRY_CONTROLS,
2678 vmcs_read32(VM_ENTRY_CONTROLS) |
2679 VM_ENTRY_IA32E_MODE);
2680 msr->data = efer;
2681 } else {
2682 vmcs_write32(VM_ENTRY_CONTROLS,
2683 vmcs_read32(VM_ENTRY_CONTROLS) &
2684 ~VM_ENTRY_IA32E_MODE);
2685
2686 msr->data = efer & ~EFER_LME;
2687 }
2688 setup_msrs(vmx);
2689}
2690
05b3e0c2 2691#ifdef CONFIG_X86_64
6aa8b732
AK		 2692
2693static void enter_lmode(struct kvm_vcpu *vcpu)
2694{
2695 u32 guest_tr_ar;
2696
2fb92db1
AK		 2697 vmx_segment_cache_clear(to_vmx(vcpu));
2698
6aa8b732
AK		 2699 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2700 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2701 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
b8688d51 2702 __func__);
6aa8b732
AK		 2703 vmcs_write32(GUEST_TR_AR_BYTES,
2704 (guest_tr_ar & ~AR_TYPE_MASK)
2705 | AR_TYPE_BUSY_64_TSS);
2706 }
da38f438 2707 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2708}
2709
2710static void exit_lmode(struct kvm_vcpu *vcpu)
2711{
6aa8b732
AK		 2712 vmcs_write32(VM_ENTRY_CONTROLS,
2713 vmcs_read32(VM_ENTRY_CONTROLS)
1e4e6e00 2714 & ~VM_ENTRY_IA32E_MODE);
da38f438 2715 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2716}
2717
2718#endif
2719
2384d2b3
SY		 2720static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2721{
b9d762fa 2722 vpid_sync_context(to_vmx(vcpu));
dd180b3e
XG		 2723 if (enable_ept) {
2724 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2725 return;
4e1096d2 2726 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
dd180b3e 2727 }
2384d2b3
SY		 2728}
2729
e8467fda
AK		 2730static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2731{
2732 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2733
2734 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2735 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2736}
2737
aff48baa
AK		 2738static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2739{
2740 if (enable_ept && is_paging(vcpu))
2741 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2742 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2743}
2744
25c4c276 2745static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 2746{
fc78f519
AK		 2747 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2748
2749 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2750 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 2751}
2752
1439442c
SY		 2753static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2754{
6de4f3ad
AK		 2755 if (!test_bit(VCPU_EXREG_PDPTR,
2756 (unsigned long *)&vcpu->arch.regs_dirty))
2757 return;
2758
1439442c 2759 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2760 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2761 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2762 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2763 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
1439442c
SY		 2764 }
2765}
2766
8f5d549f
AK		 2767static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2768{
2769 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
ff03a073
JR		 2770 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2771 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2772 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2773 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 2774 }
6de4f3ad
AK		 2775
2776 __set_bit(VCPU_EXREG_PDPTR,
2777 (unsigned long *)&vcpu->arch.regs_avail);
2778 __set_bit(VCPU_EXREG_PDPTR,
2779 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 2780}
2781
5e1746d6 2782static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1439442c
SY		 2783
2784static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2785 unsigned long cr0,
2786 struct kvm_vcpu *vcpu)
2787{
5233dd51
MT		 2788 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2789 vmx_decache_cr3(vcpu);
1439442c
SY		 2790 if (!(cr0 & X86_CR0_PG)) {
2791 /* From paging/starting to nonpaging */
2792 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2793 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 2794 (CPU_BASED_CR3_LOAD_EXITING |
2795 CPU_BASED_CR3_STORE_EXITING));
2796 vcpu->arch.cr0 = cr0;
fc78f519 2797 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 2798 } else if (!is_paging(vcpu)) {
2799 /* From nonpaging to paging */
2800 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2801 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 2802 ~(CPU_BASED_CR3_LOAD_EXITING |
2803 CPU_BASED_CR3_STORE_EXITING));
2804 vcpu->arch.cr0 = cr0;
fc78f519 2805 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 2806 }
95eb84a7
SY		 2807
2808 if (!(cr0 & X86_CR0_WP))
2809 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 2810}
2811
6aa8b732
AK		 2812static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2813{
7ffd92c5 2814 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 2815 unsigned long hw_cr0;
2816
2817 if (enable_unrestricted_guest)
2818 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2819 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2820 else
2821 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1439442c 2822
7ffd92c5 2823 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
6aa8b732
AK		 2824 enter_pmode(vcpu);
2825
7ffd92c5 2826 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
6aa8b732
AK		 2827 enter_rmode(vcpu);
2828
05b3e0c2 2829#ifdef CONFIG_X86_64
f6801dff 2830 if (vcpu->arch.efer & EFER_LME) {
707d92fa 2831 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 2832 enter_lmode(vcpu);
707d92fa 2833 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 2834 exit_lmode(vcpu);
2835 }
2836#endif
2837
089d034e 2838 if (enable_ept)
1439442c
SY		 2839 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2840
02daab21 2841 if (!vcpu->fpu_active)
81231c69 2842 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
02daab21 2843
6aa8b732 2844 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 2845 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 2846 vcpu->arch.cr0 = cr0;
69c73028 2847 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 2848}
2849
1439442c
SY		 2850static u64 construct_eptp(unsigned long root_hpa)
2851{
2852 u64 eptp;
2853
2854 /* TODO write the value reading from MSR */
2855 eptp = VMX_EPT_DEFAULT_MT |
2856 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
2857 eptp |= (root_hpa & PAGE_MASK);
2858
2859 return eptp;
2860}
2861
6aa8b732
AK		 2862static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2863{
1439442c
SY		 2864 unsigned long guest_cr3;
2865 u64 eptp;
2866
2867 guest_cr3 = cr3;
089d034e 2868 if (enable_ept) {
1439442c
SY		 2869 eptp = construct_eptp(cr3);
2870 vmcs_write64(EPT_POINTER, eptp);
9f8fe504 2871 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
b927a3ce 2872 vcpu->kvm->arch.ept_identity_map_addr;
7c93be44 2873 ept_load_pdptrs(vcpu);
1439442c
SY		 2874 }
2875
2384d2b3 2876 vmx_flush_tlb(vcpu);
1439442c 2877 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 2878}
2879
5e1746d6 2880static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 2881{
7ffd92c5 2882 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1439442c
SY		 2883 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2884
5e1746d6
NHE		 2885 if (cr4 & X86_CR4_VMXE) {
2886 /*
2887 * To use VMXON (and later other VMX instructions), a guest
2888 * must first be able to turn on cr4.VMXE (see handle_vmon()).
2889 * So basically the check on whether to allow nested VMX
2890 * is here.
2891 */
2892 if (!nested_vmx_allowed(vcpu))
2893 return 1;
2894 } else if (to_vmx(vcpu)->nested.vmxon)
2895 return 1;
2896
ad312c7c 2897 vcpu->arch.cr4 = cr4;
bc23008b
AK		 2898 if (enable_ept) {
2899 if (!is_paging(vcpu)) {
2900 hw_cr4 &= ~X86_CR4_PAE;
2901 hw_cr4 |= X86_CR4_PSE;
2902 } else if (!(cr4 & X86_CR4_PAE)) {
2903 hw_cr4 &= ~X86_CR4_PAE;
2904 }
2905 }
1439442c
SY		 2906
2907 vmcs_writel(CR4_READ_SHADOW, cr4);
2908 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 2909 return 0;
6aa8b732
AK		 2910}
2911
6aa8b732
AK		 2912static void vmx_get_segment(struct kvm_vcpu *vcpu,
2913 struct kvm_segment *var, int seg)
2914{
a9179499 2915 struct vcpu_vmx *vmx = to_vmx(vcpu);
a9179499 2916 struct kvm_save_segment *save;
6aa8b732
AK		 2917 u32 ar;
2918
a9179499
AK		 2919 if (vmx->rmode.vm86_active
2920 && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
2921 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
2922 || seg == VCPU_SREG_GS)
2923 && !emulate_invalid_guest_state) {
2924 switch (seg) {
2925 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
2926 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
2927 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
2928 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
2929 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
2930 default: BUG();
2931 }
2932 var->selector = save->selector;
2933 var->base = save->base;
2934 var->limit = save->limit;
2935 ar = save->ar;
2936 if (seg == VCPU_SREG_TR
2fb92db1 2937 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
a9179499
AK		 2938 goto use_saved_rmode_seg;
2939 }
2fb92db1
AK		 2940 var->base = vmx_read_guest_seg_base(vmx, seg);
2941 var->limit = vmx_read_guest_seg_limit(vmx, seg);
2942 var->selector = vmx_read_guest_seg_selector(vmx, seg);
2943 ar = vmx_read_guest_seg_ar(vmx, seg);
a9179499 2944use_saved_rmode_seg:
9fd4a3b7 2945 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
6aa8b732
AK		 2946 ar = 0;
2947 var->type = ar & 15;
2948 var->s = (ar >> 4) & 1;
2949 var->dpl = (ar >> 5) & 3;
2950 var->present = (ar >> 7) & 1;
2951 var->avl = (ar >> 12) & 1;
2952 var->l = (ar >> 13) & 1;
2953 var->db = (ar >> 14) & 1;
2954 var->g = (ar >> 15) & 1;
2955 var->unusable = (ar >> 16) & 1;
2956}
2957
a9179499
AK		 2958static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2959{
a9179499
AK		 2960 struct kvm_segment s;
2961
2962 if (to_vmx(vcpu)->rmode.vm86_active) {
2963 vmx_get_segment(vcpu, &s, seg);
2964 return s.base;
2965 }
2fb92db1 2966 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 2967}
2968
69c73028 2969static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 2970{
3eeb3288 2971 if (!is_protmode(vcpu))
2e4d2653
IE		 2972 return 0;
2973
f4c63e5d
AK		 2974 if (!is_long_mode(vcpu)
2975 && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
2e4d2653
IE		 2976 return 3;
2977
2fb92db1 2978 return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
2e4d2653
IE		 2979}
2980
69c73028
AK		 2981static int vmx_get_cpl(struct kvm_vcpu *vcpu)
2982{
2983 if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
2984 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2985 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
2986 }
2987 return to_vmx(vcpu)->cpl;
2988}
2989
2990
653e3108 2991static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 2992{
6aa8b732
AK		 2993 u32 ar;
2994
653e3108 2995 if (var->unusable)
6aa8b732
AK		 2996 ar = 1 << 16;
2997 else {
2998 ar = var->type & 15;
2999 ar |= (var->s & 1) << 4;
3000 ar |= (var->dpl & 3) << 5;
3001 ar |= (var->present & 1) << 7;
3002 ar |= (var->avl & 1) << 12;
3003 ar |= (var->l & 1) << 13;
3004 ar |= (var->db & 1) << 14;
3005 ar |= (var->g & 1) << 15;
3006 }
f7fbf1fd
UL		 3007 if (ar == 0) /* a 0 value means unusable */
3008 ar = AR_UNUSABLE_MASK;
653e3108
AK		 3009
3010 return ar;
3011}
3012
3013static void vmx_set_segment(struct kvm_vcpu *vcpu,
3014 struct kvm_segment *var, int seg)
3015{
7ffd92c5 3016 struct vcpu_vmx *vmx = to_vmx(vcpu);
653e3108
AK		 3017 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3018 u32 ar;
3019
2fb92db1
AK		 3020 vmx_segment_cache_clear(vmx);
3021
7ffd92c5 3022 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
a8ba6c26 3023 vmcs_write16(sf->selector, var->selector);
7ffd92c5
AK		 3024 vmx->rmode.tr.selector = var->selector;
3025 vmx->rmode.tr.base = var->base;
3026 vmx->rmode.tr.limit = var->limit;
3027 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
653e3108
AK		 3028 return;
3029 }
3030 vmcs_writel(sf->base, var->base);
3031 vmcs_write32(sf->limit, var->limit);
3032 vmcs_write16(sf->selector, var->selector);
7ffd92c5 3033 if (vmx->rmode.vm86_active && var->s) {
653e3108
AK		 3034 /*
3035 * Hack real-mode segments into vm86 compatibility.
3036 */
3037 if (var->base == 0xffff0000 && var->selector == 0xf000)
3038 vmcs_writel(sf->base, 0xf0000);
3039 ar = 0xf3;
3040 } else
3041 ar = vmx_segment_access_rights(var);
3a624e29
NK		 3042
3043 /*
3044 * Fix the "Accessed" bit in AR field of segment registers for older
3045 * qemu binaries.
3046 * IA32 arch specifies that at the time of processor reset the
3047 * "Accessed" bit in the AR field of segment registers is 1. And qemu
3048 * is setting it to 0 in the usedland code. This causes invalid guest
3049 * state vmexit when "unrestricted guest" mode is turned on.
3050 * Fix for this setup issue in cpu_reset is being pushed in the qemu
3051 * tree. Newer qemu binaries with that qemu fix would not need this
3052 * kvm hack.
3053 */
3054 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3055 ar |= 0x1; /* Accessed */
3056
6aa8b732 3057 vmcs_write32(sf->ar_bytes, ar);
69c73028 3058 __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
6aa8b732
AK		 3059}
3060
6aa8b732
AK		 3061static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3062{
2fb92db1 3063 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 3064
3065 *db = (ar >> 14) & 1;
3066 *l = (ar >> 13) & 1;
3067}
3068
89a27f4d 3069static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3070{
89a27f4d
GN		 3071 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3072 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 3073}
3074
89a27f4d 3075static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3076{
89a27f4d
GN		 3077 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3078 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 3079}
3080
89a27f4d 3081static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3082{
89a27f4d
GN		 3083 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3084 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 3085}
3086
89a27f4d 3087static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 3088{
89a27f4d
GN		 3089 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3090 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 3091}
3092
648dfaa7
MG		 3093static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3094{
3095 struct kvm_segment var;
3096 u32 ar;
3097
3098 vmx_get_segment(vcpu, &var, seg);
3099 ar = vmx_segment_access_rights(&var);
3100
3101 if (var.base != (var.selector << 4))
3102 return false;
3103 if (var.limit != 0xffff)
3104 return false;
3105 if (ar != 0xf3)
3106 return false;
3107
3108 return true;
3109}
3110
3111static bool code_segment_valid(struct kvm_vcpu *vcpu)
3112{
3113 struct kvm_segment cs;
3114 unsigned int cs_rpl;
3115
3116 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3117 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3118
1872a3f4
AK		 3119 if (cs.unusable)
3120 return false;
648dfaa7
MG		 3121 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3122 return false;
3123 if (!cs.s)
3124 return false;
1872a3f4 3125 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 3126 if (cs.dpl > cs_rpl)
3127 return false;
1872a3f4 3128 } else {
648dfaa7
MG		 3129 if (cs.dpl != cs_rpl)
3130 return false;
3131 }
3132 if (!cs.present)
3133 return false;
3134
3135 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3136 return true;
3137}
3138
3139static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3140{
3141 struct kvm_segment ss;
3142 unsigned int ss_rpl;
3143
3144 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3145 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3146
1872a3f4
AK		 3147 if (ss.unusable)
3148 return true;
3149 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 3150 return false;
3151 if (!ss.s)
3152 return false;
3153 if (ss.dpl != ss_rpl) /* DPL != RPL */
3154 return false;
3155 if (!ss.present)
3156 return false;
3157
3158 return true;
3159}
3160
3161static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3162{
3163 struct kvm_segment var;
3164 unsigned int rpl;
3165
3166 vmx_get_segment(vcpu, &var, seg);
3167 rpl = var.selector & SELECTOR_RPL_MASK;
3168
1872a3f4
AK		 3169 if (var.unusable)
3170 return true;
648dfaa7
MG		 3171 if (!var.s)
3172 return false;
3173 if (!var.present)
3174 return false;
3175 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3176 if (var.dpl < rpl) /* DPL < RPL */
3177 return false;
3178 }
3179
3180 /* TODO: Add other members to kvm_segment_field to allow checking for other access
3181 * rights flags
3182 */
3183 return true;
3184}
3185
3186static bool tr_valid(struct kvm_vcpu *vcpu)
3187{
3188 struct kvm_segment tr;
3189
3190 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3191
1872a3f4
AK		 3192 if (tr.unusable)
3193 return false;
648dfaa7
MG		 3194 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3195 return false;
1872a3f4 3196 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 3197 return false;
3198 if (!tr.present)
3199 return false;
3200
3201 return true;
3202}
3203
3204static bool ldtr_valid(struct kvm_vcpu *vcpu)
3205{
3206 struct kvm_segment ldtr;
3207
3208 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3209
1872a3f4
AK		 3210 if (ldtr.unusable)
3211 return true;
648dfaa7
MG		 3212 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
3213 return false;
3214 if (ldtr.type != 2)
3215 return false;
3216 if (!ldtr.present)
3217 return false;
3218
3219 return true;
3220}
3221
3222static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3223{
3224 struct kvm_segment cs, ss;
3225
3226 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3227 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3228
3229 return ((cs.selector & SELECTOR_RPL_MASK) ==
3230 (ss.selector & SELECTOR_RPL_MASK));
3231}
3232
3233/*
3234 * Check if guest state is valid. Returns true if valid, false if
3235 * not.
3236 * We assume that registers are always usable
3237 */
3238static bool guest_state_valid(struct kvm_vcpu *vcpu)
3239{
3240 /* real mode guest state checks */
3eeb3288 3241 if (!is_protmode(vcpu)) {
648dfaa7
MG		 3242 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3243 return false;
3244 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3245 return false;
3246 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3247 return false;
3248 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3249 return false;
3250 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3251 return false;
3252 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3253 return false;
3254 } else {
3255 /* protected mode guest state checks */
3256 if (!cs_ss_rpl_check(vcpu))
3257 return false;
3258 if (!code_segment_valid(vcpu))
3259 return false;
3260 if (!stack_segment_valid(vcpu))
3261 return false;
3262 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3263 return false;
3264 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3265 return false;
3266 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3267 return false;
3268 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3269 return false;
3270 if (!tr_valid(vcpu))
3271 return false;
3272 if (!ldtr_valid(vcpu))
3273 return false;
3274 }
3275 /* TODO:
3276 * - Add checks on RIP
3277 * - Add checks on RFLAGS
3278 */
3279
3280 return true;
3281}
3282
d77c26fc 3283static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3284{
40dcaa9f 3285 gfn_t fn;
195aefde 3286 u16 data = 0;
40dcaa9f 3287 int r, idx, ret = 0;
6aa8b732 3288
40dcaa9f
XG		 3289 idx = srcu_read_lock(&kvm->srcu);
3290 fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
195aefde
IE		 3291 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3292 if (r < 0)
10589a46 3293 goto out;
195aefde 3294 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3295 r = kvm_write_guest_page(kvm, fn++, &data,
3296 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3297 if (r < 0)
10589a46 3298 goto out;
195aefde
IE		 3299 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3300 if (r < 0)
10589a46 3301 goto out;
195aefde
IE		 3302 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3303 if (r < 0)
10589a46 3304 goto out;
195aefde 3305 data = ~0;
10589a46
MT		 3306 r = kvm_write_guest_page(kvm, fn, &data,
3307 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3308 sizeof(u8));
195aefde 3309 if (r < 0)
10589a46
MT		 3310 goto out;
3311
3312 ret = 1;
3313out:
40dcaa9f 3314 srcu_read_unlock(&kvm->srcu, idx);
10589a46 3315 return ret;
6aa8b732
AK		 3316}
3317
b7ebfb05
SY		 3318static int init_rmode_identity_map(struct kvm *kvm)
3319{
40dcaa9f 3320 int i, idx, r, ret;
b7ebfb05
SY		 3321 pfn_t identity_map_pfn;
3322 u32 tmp;
3323
089d034e 3324 if (!enable_ept)
b7ebfb05
SY		 3325 return 1;
3326 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3327 printk(KERN_ERR "EPT: identity-mapping pagetable "
3328 "haven't been allocated!\n");
3329 return 0;
3330 }
3331 if (likely(kvm->arch.ept_identity_pagetable_done))
3332 return 1;
3333 ret = 0;
b927a3ce 3334 identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
40dcaa9f 3335 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3336 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3337 if (r < 0)
3338 goto out;
3339 /* Set up identity-mapping pagetable for EPT in real mode */
3340 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3341 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3342 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3343 r = kvm_write_guest_page(kvm, identity_map_pfn,
3344 &tmp, i * sizeof(tmp), sizeof(tmp));
3345 if (r < 0)
3346 goto out;
3347 }
3348 kvm->arch.ept_identity_pagetable_done = true;
3349 ret = 1;
3350out:
40dcaa9f 3351 srcu_read_unlock(&kvm->srcu, idx);
b7ebfb05
SY		 3352 return ret;
3353}
3354
6aa8b732
AK		 3355static void seg_setup(int seg)
3356{
3357 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3358 unsigned int ar;
6aa8b732
AK		 3359
3360 vmcs_write16(sf->selector, 0);
3361 vmcs_writel(sf->base, 0);
3362 vmcs_write32(sf->limit, 0xffff);
3a624e29
NK		 3363 if (enable_unrestricted_guest) {
3364 ar = 0x93;
3365 if (seg == VCPU_SREG_CS)
3366 ar |= 0x08; /* code segment */
3367 } else
3368 ar = 0xf3;
3369
3370 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3371}
3372
f78e0e2e
SY		 3373static int alloc_apic_access_page(struct kvm *kvm)
3374{
3375 struct kvm_userspace_memory_region kvm_userspace_mem;
3376 int r = 0;
3377
79fac95e 3378 mutex_lock(&kvm->slots_lock);
bfc6d222 3379 if (kvm->arch.apic_access_page)
f78e0e2e
SY		 3380 goto out;
3381 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3382 kvm_userspace_mem.flags = 0;
3383 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3384 kvm_userspace_mem.memory_size = PAGE_SIZE;
3385 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3386 if (r)
3387 goto out;
72dc67a6 3388
bfc6d222 3389 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
f78e0e2e 3390out:
79fac95e 3391 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3392 return r;
3393}
3394
b7ebfb05
SY		 3395static int alloc_identity_pagetable(struct kvm *kvm)
3396{
3397 struct kvm_userspace_memory_region kvm_userspace_mem;
3398 int r = 0;
3399
79fac95e 3400 mutex_lock(&kvm->slots_lock);
b7ebfb05
SY		 3401 if (kvm->arch.ept_identity_pagetable)
3402 goto out;
3403 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3404 kvm_userspace_mem.flags = 0;
b927a3ce
SY		 3405 kvm_userspace_mem.guest_phys_addr =
3406 kvm->arch.ept_identity_map_addr;
b7ebfb05
SY		 3407 kvm_userspace_mem.memory_size = PAGE_SIZE;
3408 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3409 if (r)
3410 goto out;
3411
b7ebfb05 3412 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
b927a3ce 3413 kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
b7ebfb05 3414out:
79fac95e 3415 mutex_unlock(&kvm->slots_lock);
b7ebfb05
SY		 3416 return r;
3417}
3418
2384d2b3
SY		 3419static void allocate_vpid(struct vcpu_vmx *vmx)
3420{
3421 int vpid;
3422
3423 vmx->vpid = 0;
919818ab 3424 if (!enable_vpid)
2384d2b3
SY		 3425 return;
3426 spin_lock(&vmx_vpid_lock);
3427 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3428 if (vpid < VMX_NR_VPIDS) {
3429 vmx->vpid = vpid;
3430 __set_bit(vpid, vmx_vpid_bitmap);
3431 }
3432 spin_unlock(&vmx_vpid_lock);
3433}
3434
cdbecfc3
LJ		 3435static void free_vpid(struct vcpu_vmx *vmx)
3436{
3437 if (!enable_vpid)
3438 return;
3439 spin_lock(&vmx_vpid_lock);
3440 if (vmx->vpid != 0)
3441 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3442 spin_unlock(&vmx_vpid_lock);
3443}
3444
5897297b 3445static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
25c5f225 3446{
3e7c73e9 3447 int f = sizeof(unsigned long);
25c5f225
SY		 3448
3449 if (!cpu_has_vmx_msr_bitmap())
3450 return;
3451
3452 /*
3453 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3454 * have the write-low and read-high bitmap offsets the wrong way round.
3455 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3456 */
25c5f225 3457 if (msr <= 0x1fff) {
3e7c73e9
AK		 3458 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3459 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
25c5f225
SY		 3460 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3461 msr &= 0x1fff;
3e7c73e9
AK		 3462 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3463 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
25c5f225 3464 }
25c5f225
SY		 3465}
3466
5897297b
AK		 3467static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3468{
3469 if (!longmode_only)
3470 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3471 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3472}
3473
a3a8ff8e
NHE		 3474/*
3475 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3476 * will not change in the lifetime of the guest.
3477 * Note that host-state that does change is set elsewhere. E.g., host-state
3478 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3479 */
3480static void vmx_set_constant_host_state(void)
3481{
3482 u32 low32, high32;
3483 unsigned long tmpl;
3484 struct desc_ptr dt;
3485
3486 vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS); /* 22.2.3 */
3487 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
3488 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
3489
3490 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
3491 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3492 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3493 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3494 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3495
3496 native_store_idt(&dt);
3497 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
3498
3499 asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3500 vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3501
3502 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3503 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3504 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3505 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3506
3507 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3508 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3509 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3510 }
3511}
3512
bf8179a0
NHE		 3513static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3514{
3515 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3516 if (enable_ept)
3517 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3518 if (is_guest_mode(&vmx->vcpu))
3519 vmx->vcpu.arch.cr4_guest_owned_bits &=
3520 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3521 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3522}
3523
3524static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3525{
3526 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3527 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3528 exec_control &= ~CPU_BASED_TPR_SHADOW;
3529#ifdef CONFIG_X86_64
3530 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3531 CPU_BASED_CR8_LOAD_EXITING;
3532#endif
3533 }
3534 if (!enable_ept)
3535 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3536 CPU_BASED_CR3_LOAD_EXITING |
3537 CPU_BASED_INVLPG_EXITING;
3538 return exec_control;
3539}
3540
3541static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3542{
3543 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3544 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3545 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3546 if (vmx->vpid == 0)
3547 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3548 if (!enable_ept) {
3549 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3550 enable_unrestricted_guest = 0;
3551 }
3552 if (!enable_unrestricted_guest)
3553 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3554 if (!ple_gap)
3555 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3556 return exec_control;
3557}
3558
6aa8b732
AK		 3559/*
3560 * Sets up the vmcs for emulated real mode.
3561 */
8b9cf98c 3562static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
6aa8b732 3563{
6aa8b732 3564 unsigned long a;
6aa8b732 3565 int i;
6aa8b732 3566
6aa8b732 3567 /* I/O */
3e7c73e9
AK		 3568 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3569 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
6aa8b732 3570
25c5f225 3571 if (cpu_has_vmx_msr_bitmap())
5897297b 3572 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
25c5f225 3573
6aa8b732
AK		 3574 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3575
6aa8b732 3576 /* Control */
1c3d14fe
YS		 3577 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3578 vmcs_config.pin_based_exec_ctrl);
6e5d865c 3579
bf8179a0 3580 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 3581
83ff3b9d 3582 if (cpu_has_secondary_exec_ctrls()) {
bf8179a0
NHE		 3583 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3584 vmx_secondary_exec_control(vmx));
83ff3b9d 3585 }
f78e0e2e 3586
4b8d54f9
ZE		 3587 if (ple_gap) {
3588 vmcs_write32(PLE_GAP, ple_gap);
3589 vmcs_write32(PLE_WINDOW, ple_window);
3590 }
3591
c7addb90
AK		 3592 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
3593 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
6aa8b732
AK		 3594 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3595
9581d442
AK		 3596 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3597 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a3a8ff8e 3598 vmx_set_constant_host_state();
05b3e0c2 3599#ifdef CONFIG_X86_64
6aa8b732
AK		 3600 rdmsrl(MSR_FS_BASE, a);
3601 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3602 rdmsrl(MSR_GS_BASE, a);
3603 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3604#else
3605 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3606 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3607#endif
3608
2cc51560
ED		 3609 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3610 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
61d2ef2c 3611 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2cc51560 3612 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
61d2ef2c 3613 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
6aa8b732 3614
468d472f 3615 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
a3a8ff8e
NHE		 3616 u32 msr_low, msr_high;
3617 u64 host_pat;
468d472f
SY		 3618 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3619 host_pat = msr_low | ((u64) msr_high << 32);
3620 /* Write the default value follow host pat */
3621 vmcs_write64(GUEST_IA32_PAT, host_pat);
3622 /* Keep arch.pat sync with GUEST_IA32_PAT */
3623 vmx->vcpu.arch.pat = host_pat;
3624 }
3625
6aa8b732
AK		 3626 for (i = 0; i < NR_VMX_MSR; ++i) {
3627 u32 index = vmx_msr_index[i];
3628 u32 data_low, data_high;
a2fa3e9f 3629 int j = vmx->nmsrs;
6aa8b732
AK		 3630
3631 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3632 continue;
432bd6cb
AK		 3633 if (wrmsr_safe(index, data_low, data_high) < 0)
3634 continue;
26bb0981
AK		 3635 vmx->guest_msrs[j].index = i;
3636 vmx->guest_msrs[j].data = 0;
d5696725 3637 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 3638 ++vmx->nmsrs;
6aa8b732 3639 }
6aa8b732 3640
1c3d14fe 3641 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
6aa8b732
AK		 3642
3643 /* 22.2.1, 20.8.1 */
1c3d14fe
YS		 3644 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3645
e00c8cf2 3646 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
bf8179a0 3647 set_cr4_guest_host_mask(vmx);
e00c8cf2 3648
99e3e30a 3649 kvm_write_tsc(&vmx->vcpu, 0);
f78e0e2e 3650
e00c8cf2
AK		 3651 return 0;
3652}
3653
3654static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3655{
3656 struct vcpu_vmx *vmx = to_vmx(vcpu);
3657 u64 msr;
4b9d3a04 3658 int ret;
e00c8cf2 3659
5fdbf976 3660 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
e00c8cf2 3661
7ffd92c5 3662 vmx->rmode.vm86_active = 0;
e00c8cf2 3663
3b86cd99
JK		 3664 vmx->soft_vnmi_blocked = 0;
3665
ad312c7c 3666 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2d3ad1f4 3667 kvm_set_cr8(&vmx->vcpu, 0);
e00c8cf2 3668 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
c5af89b6 3669 if (kvm_vcpu_is_bsp(&vmx->vcpu))
e00c8cf2
AK		 3670 msr |= MSR_IA32_APICBASE_BSP;
3671 kvm_set_apic_base(&vmx->vcpu, msr);
3672
10ab25cd
JK		 3673 ret = fx_init(&vmx->vcpu);
3674 if (ret != 0)
3675 goto out;
e00c8cf2 3676
2fb92db1
AK		 3677 vmx_segment_cache_clear(vmx);
3678
5706be0d 3679 seg_setup(VCPU_SREG_CS);
e00c8cf2
AK		 3680 /*
3681 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3682 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
3683 */
c5af89b6 3684 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
e00c8cf2
AK		 3685 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3686 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3687 } else {
ad312c7c
ZX		 3688 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3689 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
e00c8cf2 3690 }
e00c8cf2
AK		 3691
3692 seg_setup(VCPU_SREG_DS);
3693 seg_setup(VCPU_SREG_ES);
3694 seg_setup(VCPU_SREG_FS);
3695 seg_setup(VCPU_SREG_GS);
3696 seg_setup(VCPU_SREG_SS);
3697
3698 vmcs_write16(GUEST_TR_SELECTOR, 0);
3699 vmcs_writel(GUEST_TR_BASE, 0);
3700 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3701 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3702
3703 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3704 vmcs_writel(GUEST_LDTR_BASE, 0);
3705 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3706 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3707
3708 vmcs_write32(GUEST_SYSENTER_CS, 0);
3709 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3710 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3711
3712 vmcs_writel(GUEST_RFLAGS, 0x02);
c5af89b6 3713 if (kvm_vcpu_is_bsp(&vmx->vcpu))
5fdbf976 3714 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 3715 else
5fdbf976
MT		 3716 kvm_rip_write(vcpu, 0);
3717 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
e00c8cf2 3718
e00c8cf2
AK		 3719 vmcs_writel(GUEST_DR7, 0x400);
3720
3721 vmcs_writel(GUEST_GDTR_BASE, 0);
3722 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3723
3724 vmcs_writel(GUEST_IDTR_BASE, 0);
3725 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3726
443381a8 3727 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2
AK		 3728 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3729 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3730
e00c8cf2
AK		 3731 /* Special registers */
3732 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3733
3734 setup_msrs(vmx);
3735
6aa8b732
AK		 3736 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
3737
f78e0e2e
SY		 3738 if (cpu_has_vmx_tpr_shadow()) {
3739 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3740 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3741 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
afc20184 3742 __pa(vmx->vcpu.arch.apic->regs));
f78e0e2e
SY		 3743 vmcs_write32(TPR_THRESHOLD, 0);
3744 }
3745
3746 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3747 vmcs_write64(APIC_ACCESS_ADDR,
bfc6d222 3748 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
6aa8b732 3749
2384d2b3
SY		 3750 if (vmx->vpid != 0)
3751 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3752
fa40052c 3753 vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
4d4ec087 3754 vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
8b9cf98c 3755 vmx_set_cr4(&vmx->vcpu, 0);
8b9cf98c 3756 vmx_set_efer(&vmx->vcpu, 0);
8b9cf98c
RR		 3757 vmx_fpu_activate(&vmx->vcpu);
3758 update_exception_bitmap(&vmx->vcpu);
6aa8b732 3759
b9d762fa 3760 vpid_sync_context(vmx);
2384d2b3 3761
3200f405 3762 ret = 0;
6aa8b732 3763
a89a8fb9
MG		 3764 /* HACK: Don't enable emulation on guest boot/reset */
3765 vmx->emulation_required = 0;
3766
6aa8b732
AK		 3767out:
3768 return ret;
3769}
3770
b6f1250e
NHE		 3771/*
3772 * In nested virtualization, check if L1 asked to exit on external interrupts.
3773 * For most existing hypervisors, this will always return true.
3774 */
3775static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
3776{
3777 return get_vmcs12(vcpu)->pin_based_vm_exec_control &
3778 PIN_BASED_EXT_INTR_MASK;
3779}
3780
3b86cd99
JK		 3781static void enable_irq_window(struct kvm_vcpu *vcpu)
3782{
3783 u32 cpu_based_vm_exec_control;
b6f1250e
NHE		 3784 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
3785 /* We can get here when nested_run_pending caused
3786 * vmx_interrupt_allowed() to return false. In this case, do
3787 * nothing - the interrupt will be injected later.
3788 */
3789 return;
3b86cd99
JK		 3790
3791 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3792 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3793 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3794}
3795
3796static void enable_nmi_window(struct kvm_vcpu *vcpu)
3797{
3798 u32 cpu_based_vm_exec_control;
3799
3800 if (!cpu_has_virtual_nmis()) {
3801 enable_irq_window(vcpu);
3802 return;
3803 }
3804
30bd0c4c
AK		 3805 if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3806 enable_irq_window(vcpu);
3807 return;
3808 }
3b86cd99
JK		 3809 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3810 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3811 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3812}
3813
66fd3f7f 3814static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 3815{
9c8cba37 3816 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 3817 uint32_t intr;
3818 int irq = vcpu->arch.interrupt.nr;
9c8cba37 3819
229456fc 3820 trace_kvm_inj_virq(irq);
2714d1d3 3821
fa89a817 3822 ++vcpu->stat.irq_injections;
7ffd92c5 3823 if (vmx->rmode.vm86_active) {
71f9833b
SH		 3824 int inc_eip = 0;
3825 if (vcpu->arch.interrupt.soft)
3826 inc_eip = vcpu->arch.event_exit_inst_len;
3827 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 3828 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 3829 return;
3830 }
66fd3f7f
GN		 3831 intr = irq | INTR_INFO_VALID_MASK;
3832 if (vcpu->arch.interrupt.soft) {
3833 intr |= INTR_TYPE_SOFT_INTR;
3834 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3835 vmx->vcpu.arch.event_exit_inst_len);
3836 } else
3837 intr |= INTR_TYPE_EXT_INTR;
3838 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
443381a8 3839 vmx_clear_hlt(vcpu);
85f455f7
ED		 3840}
3841
f08864b4
SY		 3842static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
3843{
66a5a347
JK		 3844 struct vcpu_vmx *vmx = to_vmx(vcpu);
3845
0b6ac343
NHE		 3846 if (is_guest_mode(vcpu))
3847 return;
3848
3b86cd99
JK		 3849 if (!cpu_has_virtual_nmis()) {
3850 /*
3851 * Tracking the NMI-blocked state in software is built upon
3852 * finding the next open IRQ window. This, in turn, depends on
3853 * well-behaving guests: They have to keep IRQs disabled at
3854 * least as long as the NMI handler runs. Otherwise we may
3855 * cause NMI nesting, maybe breaking the guest. But as this is
3856 * highly unlikely, we can live with the residual risk.
3857 */
3858 vmx->soft_vnmi_blocked = 1;
3859 vmx->vnmi_blocked_time = 0;
3860 }
3861
487b391d 3862 ++vcpu->stat.nmi_injections;
9d58b931 3863 vmx->nmi_known_unmasked = false;
7ffd92c5 3864 if (vmx->rmode.vm86_active) {
71f9833b 3865 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 3866 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 3867 return;
3868 }
f08864b4
SY		 3869 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
3870 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
443381a8 3871 vmx_clear_hlt(vcpu);
f08864b4
SY		 3872}
3873
c4282df9 3874static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
33f089ca 3875{
3b86cd99 3876 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
c4282df9 3877 return 0;
33f089ca 3878
c4282df9 3879 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
30bd0c4c
AK		 3880 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
3881 | GUEST_INTR_STATE_NMI));
33f089ca
JK		 3882}
3883
3cfc3092
JK		 3884static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
3885{
3886 if (!cpu_has_virtual_nmis())
3887 return to_vmx(vcpu)->soft_vnmi_blocked;
9d58b931
AK		 3888 if (to_vmx(vcpu)->nmi_known_unmasked)
3889 return false;
c332c83a 3890 return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3cfc3092
JK		 3891}
3892
3893static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3894{
3895 struct vcpu_vmx *vmx = to_vmx(vcpu);
3896
3897 if (!cpu_has_virtual_nmis()) {
3898 if (vmx->soft_vnmi_blocked != masked) {
3899 vmx->soft_vnmi_blocked = masked;
3900 vmx->vnmi_blocked_time = 0;
3901 }
3902 } else {
9d58b931 3903 vmx->nmi_known_unmasked = !masked;
3cfc3092
JK		 3904 if (masked)
3905 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3906 GUEST_INTR_STATE_NMI);
3907 else
3908 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3909 GUEST_INTR_STATE_NMI);
3910 }
3911}
3912
78646121
GN		 3913static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
3914{
b6f1250e
NHE		 3915 if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
3916 struct vmcs12 *vmcs12;
3917 if (to_vmx(vcpu)->nested.nested_run_pending)
3918 return 0;
3919 nested_vmx_vmexit(vcpu);
3920 vmcs12 = get_vmcs12(vcpu);
3921 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
3922 vmcs12->vm_exit_intr_info = 0;
3923 /* fall through to normal code, but now in L1, not L2 */
3924 }
3925
c4282df9
GN		 3926 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
3927 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3928 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 3929}
3930
cbc94022
IE		 3931static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
3932{
3933 int ret;
3934 struct kvm_userspace_memory_region tss_mem = {
6fe63979 3935 .slot = TSS_PRIVATE_MEMSLOT,
cbc94022
IE		 3936 .guest_phys_addr = addr,
3937 .memory_size = PAGE_SIZE * 3,
3938 .flags = 0,
3939 };
3940
3941 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
3942 if (ret)
3943 return ret;
bfc6d222 3944 kvm->arch.tss_addr = addr;
93ea5388
GN		 3945 if (!init_rmode_tss(kvm))
3946 return -ENOMEM;
3947
cbc94022
IE		 3948 return 0;
3949}
3950
6aa8b732
AK		 3951static int handle_rmode_exception(struct kvm_vcpu *vcpu,
3952 int vec, u32 err_code)
3953{
b3f37707
NK		 3954 /*
3955 * Instruction with address size override prefix opcode 0x67
3956 * Cause the #SS fault with 0 error code in VM86 mode.
3957 */
3958 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
51d8b661 3959 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
6aa8b732 3960 return 1;
77ab6db0
JK		 3961 /*
3962 * Forward all other exceptions that are valid in real mode.
3963 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
3964 * the required debugging infrastructure rework.
3965 */
3966 switch (vec) {
77ab6db0 3967 case DB_VECTOR:
d0bfb940
JK		 3968 if (vcpu->guest_debug &
3969 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
3970 return 0;
3971 kvm_queue_exception(vcpu, vec);
3972 return 1;
77ab6db0 3973 case BP_VECTOR:
c573cd22
JK		 3974 /*
3975 * Update instruction length as we may reinject the exception
3976 * from user space while in guest debugging mode.
3977 */
3978 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
3979 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940
JK		 3980 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
3981 return 0;
3982 /* fall through */
3983 case DE_VECTOR:
77ab6db0
JK		 3984 case OF_VECTOR:
3985 case BR_VECTOR:
3986 case UD_VECTOR:
3987 case DF_VECTOR:
3988 case SS_VECTOR:
3989 case GP_VECTOR:
3990 case MF_VECTOR:
3991 kvm_queue_exception(vcpu, vec);
3992 return 1;
3993 }
6aa8b732
AK		 3994 return 0;
3995}
3996
a0861c02
AK		 3997/*
3998 * Trigger machine check on the host. We assume all the MSRs are already set up
3999 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4000 * We pass a fake environment to the machine check handler because we want
4001 * the guest to be always treated like user space, no matter what context
4002 * it used internally.
4003 */
4004static void kvm_machine_check(void)
4005{
4006#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4007 struct pt_regs regs = {
4008 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4009 .flags = X86_EFLAGS_IF,
4010 };
4011
4012 do_machine_check(&regs, 0);
4013#endif
4014}
4015
851ba692 4016static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4017{
4018 /* already handled by vcpu_run */
4019 return 1;
4020}
4021
851ba692 4022static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4023{
1155f76a 4024 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4025 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4026 u32 intr_info, ex_no, error_code;
42dbaa5a 4027 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4028 u32 vect_info;
4029 enum emulation_result er;
4030
1155f76a 4031 vect_info = vmx->idt_vectoring_info;
88786475 4032 intr_info = vmx->exit_intr_info;
6aa8b732 4033
a0861c02 4034 if (is_machine_check(intr_info))
851ba692 4035 return handle_machine_check(vcpu);
a0861c02 4036
6aa8b732 4037 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
65ac7264
AK		 4038 !is_page_fault(intr_info)) {
4039 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4040 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4041 vcpu->run->internal.ndata = 2;
4042 vcpu->run->internal.data[0] = vect_info;
4043 vcpu->run->internal.data[1] = intr_info;
4044 return 0;
4045 }
6aa8b732 4046
e4a41889 4047 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
1b6269db 4048 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc
AL		 4049
4050 if (is_no_device(intr_info)) {
5fd86fcf 4051 vmx_fpu_activate(vcpu);
2ab455cc
AL		 4052 return 1;
4053 }
4054
7aa81cc0 4055 if (is_invalid_opcode(intr_info)) {
51d8b661 4056 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
7aa81cc0 4057 if (er != EMULATE_DONE)
7ee5d940 4058 kvm_queue_exception(vcpu, UD_VECTOR);
7aa81cc0
AL		 4059 return 1;
4060 }
4061
6aa8b732 4062 error_code = 0;
2e11384c 4063 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732
AK		 4064 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4065 if (is_page_fault(intr_info)) {
1439442c 4066 /* EPT won't cause page fault directly */
089d034e 4067 if (enable_ept)
1439442c 4068 BUG();
6aa8b732 4069 cr2 = vmcs_readl(EXIT_QUALIFICATION);
229456fc
MT		 4070 trace_kvm_page_fault(cr2, error_code);
4071
3298b75c 4072 if (kvm_event_needs_reinjection(vcpu))
577bdc49 4073 kvm_mmu_unprotect_page_virt(vcpu, cr2);
dc25e89e 4074 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
6aa8b732
AK		 4075 }
4076
7ffd92c5 4077 if (vmx->rmode.vm86_active &&
6aa8b732 4078 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
72d6e5a0 4079 error_code)) {
ad312c7c
ZX		 4080 if (vcpu->arch.halt_request) {
4081 vcpu->arch.halt_request = 0;
72d6e5a0
AK		 4082 return kvm_emulate_halt(vcpu);
4083 }
6aa8b732 4084 return 1;
72d6e5a0 4085 }
6aa8b732 4086
d0bfb940 4087 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
42dbaa5a
JK		 4088 switch (ex_no) {
4089 case DB_VECTOR:
4090 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4091 if (!(vcpu->guest_debug &
4092 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4093 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4094 kvm_queue_exception(vcpu, DB_VECTOR);
4095 return 1;
4096 }
4097 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4098 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4099 /* fall through */
4100 case BP_VECTOR:
c573cd22
JK		 4101 /*
4102 * Update instruction length as we may reinject #BP from
4103 * user space while in guest debugging mode. Reading it for
4104 * #DB as well causes no harm, it is not used in that case.
4105 */
4106 vmx->vcpu.arch.event_exit_inst_len =
4107 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4108 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4109 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4110 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4111 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4112 break;
4113 default:
d0bfb940
JK		 4114 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4115 kvm_run->ex.exception = ex_no;
4116 kvm_run->ex.error_code = error_code;
42dbaa5a 4117 break;
6aa8b732 4118 }
6aa8b732
AK		 4119 return 0;
4120}
4121
851ba692 4122static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4123{
1165f5fe 4124 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4125 return 1;
4126}
4127
851ba692 4128static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4129{
851ba692 4130 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
988ad74f
AK		 4131 return 0;
4132}
6aa8b732 4133
851ba692 4134static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4135{
bfdaab09 4136 unsigned long exit_qualification;
34c33d16 4137 int size, in, string;
039576c0 4138 unsigned port;
6aa8b732 4139
bfdaab09 4140 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4141 string = (exit_qualification & 16) != 0;
cf8f70bf 4142 in = (exit_qualification & 8) != 0;
e70669ab 4143
cf8f70bf 4144 ++vcpu->stat.io_exits;
e70669ab 4145
cf8f70bf 4146 if (string || in)
51d8b661 4147 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4148
cf8f70bf
GN		 4149 port = exit_qualification >> 16;
4150 size = (exit_qualification & 7) + 1;
e93f36bc 4151 skip_emulated_instruction(vcpu);
cf8f70bf
GN		 4152
4153 return kvm_fast_pio_out(vcpu, size, port);
6aa8b732
AK		 4154}
4155
102d8325
IM		 4156static void
4157vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4158{
4159 /*
4160 * Patch in the VMCALL instruction:
4161 */
4162 hypercall[0] = 0x0f;
4163 hypercall[1] = 0x01;
4164 hypercall[2] = 0xc1;
102d8325
IM		 4165}
4166
eeadf9e7
NHE		 4167/* called to set cr0 as approriate for a mov-to-cr0 exit. */
4168static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4169{
4170 if (to_vmx(vcpu)->nested.vmxon &&
4171 ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4172 return 1;
4173
4174 if (is_guest_mode(vcpu)) {
4175 /*
4176 * We get here when L2 changed cr0 in a way that did not change
4177 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4178 * but did change L0 shadowed bits. This can currently happen
4179 * with the TS bit: L0 may want to leave TS on (for lazy fpu
4180 * loading) while pretending to allow the guest to change it.
4181 */
4182 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4183 (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4184 return 1;
4185 vmcs_writel(CR0_READ_SHADOW, val);
4186 return 0;
4187 } else
4188 return kvm_set_cr0(vcpu, val);
4189}
4190
4191static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4192{
4193 if (is_guest_mode(vcpu)) {
4194 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4195 (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4196 return 1;
4197 vmcs_writel(CR4_READ_SHADOW, val);
4198 return 0;
4199 } else
4200 return kvm_set_cr4(vcpu, val);
4201}
4202
4203/* called to set cr0 as approriate for clts instruction exit. */
4204static void handle_clts(struct kvm_vcpu *vcpu)
4205{
4206 if (is_guest_mode(vcpu)) {
4207 /*
4208 * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4209 * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4210 * just pretend it's off (also in arch.cr0 for fpu_activate).
4211 */
4212 vmcs_writel(CR0_READ_SHADOW,
4213 vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4214 vcpu->arch.cr0 &= ~X86_CR0_TS;
4215 } else
4216 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4217}
4218
851ba692 4219static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4220{
229456fc 4221 unsigned long exit_qualification, val;
6aa8b732
AK		 4222 int cr;
4223 int reg;
49a9b07e 4224 int err;
6aa8b732 4225
bfdaab09 4226 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4227 cr = exit_qualification & 15;
4228 reg = (exit_qualification >> 8) & 15;
4229 switch ((exit_qualification >> 4) & 3) {
4230 case 0: /* mov to cr */
229456fc
MT		 4231 val = kvm_register_read(vcpu, reg);
4232 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4233 switch (cr) {
4234 case 0:
eeadf9e7 4235 err = handle_set_cr0(vcpu, val);
db8fcefa 4236 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4237 return 1;
4238 case 3:
2390218b 4239 err = kvm_set_cr3(vcpu, val);
db8fcefa 4240 kvm_complete_insn_gp(vcpu, err);
6aa8b732
AK		 4241 return 1;
4242 case 4:
eeadf9e7 4243 err = handle_set_cr4(vcpu, val);
db8fcefa 4244 kvm_complete_insn_gp(vcpu, err);
6aa8b732 4245 return 1;
0a5fff19
GN		 4246 case 8: {
4247 u8 cr8_prev = kvm_get_cr8(vcpu);
4248 u8 cr8 = kvm_register_read(vcpu, reg);
eea1cff9 4249 err = kvm_set_cr8(vcpu, cr8);
db8fcefa 4250 kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4251 if (irqchip_in_kernel(vcpu->kvm))
4252 return 1;
4253 if (cr8_prev <= cr8)
4254 return 1;
851ba692 4255 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4256 return 0;
4257 }
6aa8b732
AK		 4258 };
4259 break;
25c4c276 4260 case 2: /* clts */
eeadf9e7 4261 handle_clts(vcpu);
4d4ec087 4262 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
25c4c276 4263 skip_emulated_instruction(vcpu);
6b52d186 4264 vmx_fpu_activate(vcpu);
25c4c276 4265 return 1;
6aa8b732
AK		 4266 case 1: /*mov from cr*/
4267 switch (cr) {
4268 case 3:
9f8fe504
AK		 4269 val = kvm_read_cr3(vcpu);
4270 kvm_register_write(vcpu, reg, val);
4271 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4272 skip_emulated_instruction(vcpu);
4273 return 1;
4274 case 8:
229456fc
MT		 4275 val = kvm_get_cr8(vcpu);
4276 kvm_register_write(vcpu, reg, val);
4277 trace_kvm_cr_read(cr, val);
6aa8b732
AK		 4278 skip_emulated_instruction(vcpu);
4279 return 1;
4280 }
4281 break;
4282 case 3: /* lmsw */
a1f83a74 4283 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4284 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4285 kvm_lmsw(vcpu, val);
6aa8b732
AK		 4286
4287 skip_emulated_instruction(vcpu);
4288 return 1;
4289 default:
4290 break;
4291 }
851ba692 4292 vcpu->run->exit_reason = 0;
f0242478 4293 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4294 (int)(exit_qualification >> 4) & 3, cr);
4295 return 0;
4296}
4297
851ba692 4298static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4299{
bfdaab09 4300 unsigned long exit_qualification;
6aa8b732
AK		 4301 int dr, reg;
4302
f2483415 4303 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4304 if (!kvm_require_cpl(vcpu, 0))
4305 return 1;
42dbaa5a
JK		 4306 dr = vmcs_readl(GUEST_DR7);
4307 if (dr & DR7_GD) {
4308 /*
4309 * As the vm-exit takes precedence over the debug trap, we
4310 * need to emulate the latter, either for the host or the
4311 * guest debugging itself.
4312 */
4313 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692
AK		 4314 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4315 vcpu->run->debug.arch.dr7 = dr;
4316 vcpu->run->debug.arch.pc =
42dbaa5a
JK		 4317 vmcs_readl(GUEST_CS_BASE) +
4318 vmcs_readl(GUEST_RIP);
851ba692
AK		 4319 vcpu->run->debug.arch.exception = DB_VECTOR;
4320 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4321 return 0;
4322 } else {
4323 vcpu->arch.dr7 &= ~DR7_GD;
4324 vcpu->arch.dr6 |= DR6_BD;
4325 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4326 kvm_queue_exception(vcpu, DB_VECTOR);
4327 return 1;
4328 }
4329 }
4330
bfdaab09 4331 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
42dbaa5a
JK		 4332 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4333 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4334 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079
GN		 4335 unsigned long val;
4336 if (!kvm_get_dr(vcpu, dr, &val))
4337 kvm_register_write(vcpu, reg, val);
4338 } else
4339 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
6aa8b732
AK		 4340 skip_emulated_instruction(vcpu);
4341 return 1;
4342}
4343
020df079
GN		 4344static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4345{
4346 vmcs_writel(GUEST_DR7, val);
4347}
4348
851ba692 4349static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4350{
06465c5a
AK		 4351 kvm_emulate_cpuid(vcpu);
4352 return 1;
6aa8b732
AK		 4353}
4354
851ba692 4355static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4356{
ad312c7c 4357 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
6aa8b732
AK		 4358 u64 data;
4359
4360 if (vmx_get_msr(vcpu, ecx, &data)) {
59200273 4361 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 4362 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4363 return 1;
4364 }
4365
229456fc 4366 trace_kvm_msr_read(ecx, data);
2714d1d3 4367
6aa8b732 4368 /* FIXME: handling of bits 32:63 of rax, rdx */
ad312c7c
ZX		 4369 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4370 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
6aa8b732
AK		 4371 skip_emulated_instruction(vcpu);
4372 return 1;
4373}
4374
851ba692 4375static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4376{
ad312c7c
ZX		 4377 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4378 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4379 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732
AK		 4380
4381 if (vmx_set_msr(vcpu, ecx, data) != 0) {
59200273 4382 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 4383 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4384 return 1;
4385 }
4386
59200273 4387 trace_kvm_msr_write(ecx, data);
6aa8b732
AK		 4388 skip_emulated_instruction(vcpu);
4389 return 1;
4390}
4391
851ba692 4392static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4393{
3842d135 4394 kvm_make_request(KVM_REQ_EVENT, vcpu);
6e5d865c
YS		 4395 return 1;
4396}
4397
851ba692 4398static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4399{
85f455f7
ED		 4400 u32 cpu_based_vm_exec_control;
4401
4402 /* clear pending irq */
4403 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4404 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4405 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2714d1d3 4406
3842d135
AK		 4407 kvm_make_request(KVM_REQ_EVENT, vcpu);
4408
a26bf12a 4409 ++vcpu->stat.irq_window_exits;
2714d1d3 4410
c1150d8c
DL		 4411 /*
4412 * If the user space waits to inject interrupts, exit as soon as
4413 * possible
4414 */
8061823a 4415 if (!irqchip_in_kernel(vcpu->kvm) &&
851ba692 4416 vcpu->run->request_interrupt_window &&
8061823a 4417 !kvm_cpu_has_interrupt(vcpu)) {
851ba692 4418 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
c1150d8c
DL		 4419 return 0;
4420 }
6aa8b732
AK		 4421 return 1;
4422}
4423
851ba692 4424static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732
AK		 4425{
4426 skip_emulated_instruction(vcpu);
d3bef15f 4427 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 4428}
4429
851ba692 4430static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4431{
510043da 4432 skip_emulated_instruction(vcpu);
7aa81cc0
AL		 4433 kvm_emulate_hypercall(vcpu);
4434 return 1;
c21415e8
IM		 4435}
4436
ec25d5e6
GN		 4437static int handle_invd(struct kvm_vcpu *vcpu)
4438{
51d8b661 4439 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 4440}
4441
851ba692 4442static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4443{
f9c617f6 4444 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4445
4446 kvm_mmu_invlpg(vcpu, exit_qualification);
4447 skip_emulated_instruction(vcpu);
4448 return 1;
4449}
4450
851ba692 4451static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01
ED		 4452{
4453 skip_emulated_instruction(vcpu);
f5f48ee1 4454 kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 4455 return 1;
4456}
4457
2acf923e
DC		 4458static int handle_xsetbv(struct kvm_vcpu *vcpu)
4459{
4460 u64 new_bv = kvm_read_edx_eax(vcpu);
4461 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4462
4463 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4464 skip_emulated_instruction(vcpu);
4465 return 1;
4466}
4467
851ba692 4468static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 4469{
51d8b661 4470 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 4471}
4472
851ba692 4473static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 4474{
60637aac 4475 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 4476 unsigned long exit_qualification;
e269fb21
JK		 4477 bool has_error_code = false;
4478 u32 error_code = 0;
37817f29 4479 u16 tss_selector;
64a7ec06
GN		 4480 int reason, type, idt_v;
4481
4482 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4483 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 4484
4485 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4486
4487 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 4488 if (reason == TASK_SWITCH_GATE && idt_v) {
4489 switch (type) {
4490 case INTR_TYPE_NMI_INTR:
4491 vcpu->arch.nmi_injected = false;
654f06fc 4492 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 4493 break;
4494 case INTR_TYPE_EXT_INTR:
66fd3f7f 4495 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 4496 kvm_clear_interrupt_queue(vcpu);
4497 break;
4498 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 4499 if (vmx->idt_vectoring_info &
4500 VECTORING_INFO_DELIVER_CODE_MASK) {
4501 has_error_code = true;
4502 error_code =
4503 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4504 }
4505 /* fall through */
64a7ec06
GN		 4506 case INTR_TYPE_SOFT_EXCEPTION:
4507 kvm_clear_exception_queue(vcpu);
4508 break;
4509 default:
4510 break;
4511 }
60637aac 4512 }
37817f29
IE		 4513 tss_selector = exit_qualification;
4514
64a7ec06
GN		 4515 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4516 type != INTR_TYPE_EXT_INTR &&
4517 type != INTR_TYPE_NMI_INTR))
4518 skip_emulated_instruction(vcpu);
4519
acb54517
GN		 4520 if (kvm_task_switch(vcpu, tss_selector, reason,
4521 has_error_code, error_code) == EMULATE_FAIL) {
4522 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4523 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4524 vcpu->run->internal.ndata = 0;
42dbaa5a 4525 return 0;
acb54517 4526 }
42dbaa5a
JK		 4527
4528 /* clear all local breakpoint enable flags */
4529 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4530
4531 /*
4532 * TODO: What about debug traps on tss switch?
4533 * Are we supposed to inject them and update dr6?
4534 */
4535
4536 return 1;
37817f29
IE		 4537}
4538
851ba692 4539static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 4540{
f9c617f6 4541 unsigned long exit_qualification;
1439442c 4542 gpa_t gpa;
1439442c 4543 int gla_validity;
1439442c 4544
f9c617f6 4545 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c
SY		 4546
4547 if (exit_qualification & (1 << 6)) {
4548 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
7f582ab6 4549 return -EINVAL;
1439442c
SY		 4550 }
4551
4552 gla_validity = (exit_qualification >> 7) & 0x3;
4553 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4554 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4555 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4556 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
f9c617f6 4557 vmcs_readl(GUEST_LINEAR_ADDRESS));
1439442c
SY		 4558 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4559 (long unsigned int)exit_qualification);
851ba692
AK		 4560 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4561 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
596ae895 4562 return 0;
1439442c
SY		 4563 }
4564
4565 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 4566 trace_kvm_page_fault(gpa, exit_qualification);
dc25e89e 4567 return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
1439442c
SY		 4568}
4569
68f89400
MT		 4570static u64 ept_rsvd_mask(u64 spte, int level)
4571{
4572 int i;
4573 u64 mask = 0;
4574
4575 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4576 mask |= (1ULL << i);
4577
4578 if (level > 2)
4579 /* bits 7:3 reserved */
4580 mask |= 0xf8;
4581 else if (level == 2) {
4582 if (spte & (1ULL << 7))
4583 /* 2MB ref, bits 20:12 reserved */
4584 mask |= 0x1ff000;
4585 else
4586 /* bits 6:3 reserved */
4587 mask |= 0x78;
4588 }
4589
4590 return mask;
4591}
4592
4593static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4594 int level)
4595{
4596 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4597
4598 /* 010b (write-only) */
4599 WARN_ON((spte & 0x7) == 0x2);
4600
4601 /* 110b (write/execute) */
4602 WARN_ON((spte & 0x7) == 0x6);
4603
4604 /* 100b (execute-only) and value not supported by logical processor */
4605 if (!cpu_has_vmx_ept_execute_only())
4606 WARN_ON((spte & 0x7) == 0x4);
4607
4608 /* not 000b */
4609 if ((spte & 0x7)) {
4610 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4611
4612 if (rsvd_bits != 0) {
4613 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4614 __func__, rsvd_bits);
4615 WARN_ON(1);
4616 }
4617
4618 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4619 u64 ept_mem_type = (spte & 0x38) >> 3;
4620
4621 if (ept_mem_type == 2 || ept_mem_type == 3 ||
4622 ept_mem_type == 7) {
4623 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4624 __func__, ept_mem_type);
4625 WARN_ON(1);
4626 }
4627 }
4628 }
4629}
4630
851ba692 4631static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400
MT		 4632{
4633 u64 sptes[4];
4634 int nr_sptes, i;
4635 gpa_t gpa;
4636
4637 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4638
4639 printk(KERN_ERR "EPT: Misconfiguration.\n");
4640 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4641
4642 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4643
4644 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4645 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4646
851ba692
AK		 4647 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4648 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
68f89400
MT		 4649
4650 return 0;
4651}
4652
851ba692 4653static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4
SY		 4654{
4655 u32 cpu_based_vm_exec_control;
4656
4657 /* clear pending NMI */
4658 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4659 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4660 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4661 ++vcpu->stat.nmi_window_exits;
3842d135 4662 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 4663
4664 return 1;
4665}
4666
80ced186 4667static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 4668{
8b3079a5
AK		 4669 struct vcpu_vmx *vmx = to_vmx(vcpu);
4670 enum emulation_result err = EMULATE_DONE;
80ced186 4671 int ret = 1;
49e9d557
AK		 4672 u32 cpu_exec_ctrl;
4673 bool intr_window_requested;
4674
4675 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4676 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0
MG		 4677
4678 while (!guest_state_valid(vcpu)) {
49e9d557
AK		 4679 if (intr_window_requested
4680 && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4681 return handle_interrupt_window(&vmx->vcpu);
4682
51d8b661 4683 err = emulate_instruction(vcpu, 0);
ea953ef0 4684
80ced186
MG		 4685 if (err == EMULATE_DO_MMIO) {
4686 ret = 0;
4687 goto out;
4688 }
1d5a4d9b 4689
6d77dbfc
GN		 4690 if (err != EMULATE_DONE)
4691 return 0;
ea953ef0
MG		 4692
4693 if (signal_pending(current))
80ced186 4694 goto out;
ea953ef0
MG		 4695 if (need_resched())
4696 schedule();
4697 }
4698
80ced186
MG		 4699 vmx->emulation_required = 0;
4700out:
4701 return ret;
ea953ef0
MG		 4702}
4703
4b8d54f9
ZE		 4704/*
4705 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4706 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4707 */
9fb41ba8 4708static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9
ZE		 4709{
4710 skip_emulated_instruction(vcpu);
4711 kvm_vcpu_on_spin(vcpu);
4712
4713 return 1;
4714}
4715
59708670
SY		 4716static int handle_invalid_op(struct kvm_vcpu *vcpu)
4717{
4718 kvm_queue_exception(vcpu, UD_VECTOR);
4719 return 1;
4720}
4721
ff2f6fe9
NHE		 4722/*
4723 * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4724 * We could reuse a single VMCS for all the L2 guests, but we also want the
4725 * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4726 * allows keeping them loaded on the processor, and in the future will allow
4727 * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4728 * every entry if they never change.
4729 * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4730 * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4731 *
4732 * The following functions allocate and free a vmcs02 in this pool.
4733 */
4734
4735/* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4736static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
4737{
4738 struct vmcs02_list *item;
4739 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4740 if (item->vmptr == vmx->nested.current_vmptr) {
4741 list_move(&item->list, &vmx->nested.vmcs02_pool);
4742 return &item->vmcs02;
4743 }
4744
4745 if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
4746 /* Recycle the least recently used VMCS. */
4747 item = list_entry(vmx->nested.vmcs02_pool.prev,
4748 struct vmcs02_list, list);
4749 item->vmptr = vmx->nested.current_vmptr;
4750 list_move(&item->list, &vmx->nested.vmcs02_pool);
4751 return &item->vmcs02;
4752 }
4753
4754 /* Create a new VMCS */
4755 item = (struct vmcs02_list *)
4756 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
4757 if (!item)
4758 return NULL;
4759 item->vmcs02.vmcs = alloc_vmcs();
4760 if (!item->vmcs02.vmcs) {
4761 kfree(item);
4762 return NULL;
4763 }
4764 loaded_vmcs_init(&item->vmcs02);
4765 item->vmptr = vmx->nested.current_vmptr;
4766 list_add(&(item->list), &(vmx->nested.vmcs02_pool));
4767 vmx->nested.vmcs02_num++;
4768 return &item->vmcs02;
4769}
4770
4771/* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4772static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
4773{
4774 struct vmcs02_list *item;
4775 list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4776 if (item->vmptr == vmptr) {
4777 free_loaded_vmcs(&item->vmcs02);
4778 list_del(&item->list);
4779 kfree(item);
4780 vmx->nested.vmcs02_num--;
4781 return;
4782 }
4783}
4784
4785/*
4786 * Free all VMCSs saved for this vcpu, except the one pointed by
4787 * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4788 * currently used, if running L2), and vmcs01 when running L2.
4789 */
4790static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
4791{
4792 struct vmcs02_list *item, *n;
4793 list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4794 if (vmx->loaded_vmcs != &item->vmcs02)
4795 free_loaded_vmcs(&item->vmcs02);
4796 list_del(&item->list);
4797 kfree(item);
4798 }
4799 vmx->nested.vmcs02_num = 0;
4800
4801 if (vmx->loaded_vmcs != &vmx->vmcs01)
4802 free_loaded_vmcs(&vmx->vmcs01);
4803}
4804
ec378aee
NHE		 4805/*
4806 * Emulate the VMXON instruction.
4807 * Currently, we just remember that VMX is active, and do not save or even
4808 * inspect the argument to VMXON (the so-called "VMXON pointer") because we
4809 * do not currently need to store anything in that guest-allocated memory
4810 * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
4811 * argument is different from the VMXON pointer (which the spec says they do).
4812 */
4813static int handle_vmon(struct kvm_vcpu *vcpu)
4814{
4815 struct kvm_segment cs;
4816 struct vcpu_vmx *vmx = to_vmx(vcpu);
4817
4818 /* The Intel VMX Instruction Reference lists a bunch of bits that
4819 * are prerequisite to running VMXON, most notably cr4.VMXE must be
4820 * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
4821 * Otherwise, we should fail with #UD. We test these now:
4822 */
4823 if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
4824 !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
4825 (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4826 kvm_queue_exception(vcpu, UD_VECTOR);
4827 return 1;
4828 }
4829
4830 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4831 if (is_long_mode(vcpu) && !cs.l) {
4832 kvm_queue_exception(vcpu, UD_VECTOR);
4833 return 1;
4834 }
4835
4836 if (vmx_get_cpl(vcpu)) {
4837 kvm_inject_gp(vcpu, 0);
4838 return 1;
4839 }
4840
ff2f6fe9
NHE		 4841 INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
4842 vmx->nested.vmcs02_num = 0;
4843
ec378aee
NHE		 4844 vmx->nested.vmxon = true;
4845
4846 skip_emulated_instruction(vcpu);
4847 return 1;
4848}
4849
4850/*
4851 * Intel's VMX Instruction Reference specifies a common set of prerequisites
4852 * for running VMX instructions (except VMXON, whose prerequisites are
4853 * slightly different). It also specifies what exception to inject otherwise.
4854 */
4855static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
4856{
4857 struct kvm_segment cs;
4858 struct vcpu_vmx *vmx = to_vmx(vcpu);
4859
4860 if (!vmx->nested.vmxon) {
4861 kvm_queue_exception(vcpu, UD_VECTOR);
4862 return 0;
4863 }
4864
4865 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4866 if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
4867 (is_long_mode(vcpu) && !cs.l)) {
4868 kvm_queue_exception(vcpu, UD_VECTOR);
4869 return 0;
4870 }
4871
4872 if (vmx_get_cpl(vcpu)) {
4873 kvm_inject_gp(vcpu, 0);
4874 return 0;
4875 }
4876
4877 return 1;
4878}
4879
4880/*
4881 * Free whatever needs to be freed from vmx->nested when L1 goes down, or
4882 * just stops using VMX.
4883 */
4884static void free_nested(struct vcpu_vmx *vmx)
4885{
4886 if (!vmx->nested.vmxon)
4887 return;
4888 vmx->nested.vmxon = false;
a9d30f33
NHE		 4889 if (vmx->nested.current_vmptr != -1ull) {
4890 kunmap(vmx->nested.current_vmcs12_page);
4891 nested_release_page(vmx->nested.current_vmcs12_page);
4892 vmx->nested.current_vmptr = -1ull;
4893 vmx->nested.current_vmcs12 = NULL;
4894 }
fe3ef05c
NHE		 4895 /* Unpin physical memory we referred to in current vmcs02 */
4896 if (vmx->nested.apic_access_page) {
4897 nested_release_page(vmx->nested.apic_access_page);
4898 vmx->nested.apic_access_page = 0;
4899 }
ff2f6fe9
NHE		 4900
4901 nested_free_all_saved_vmcss(vmx);
ec378aee
NHE		 4902}
4903
4904/* Emulate the VMXOFF instruction */
4905static int handle_vmoff(struct kvm_vcpu *vcpu)
4906{
4907 if (!nested_vmx_check_permission(vcpu))
4908 return 1;
4909 free_nested(to_vmx(vcpu));
4910 skip_emulated_instruction(vcpu);
4911 return 1;
4912}
4913
064aea77
NHE		 4914/*
4915 * Decode the memory-address operand of a vmx instruction, as recorded on an
4916 * exit caused by such an instruction (run by a guest hypervisor).
4917 * On success, returns 0. When the operand is invalid, returns 1 and throws
4918 * #UD or #GP.
4919 */
4920static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
4921 unsigned long exit_qualification,
4922 u32 vmx_instruction_info, gva_t *ret)
4923{
4924 /*
4925 * According to Vol. 3B, "Information for VM Exits Due to Instruction
4926 * Execution", on an exit, vmx_instruction_info holds most of the
4927 * addressing components of the operand. Only the displacement part
4928 * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
4929 * For how an actual address is calculated from all these components,
4930 * refer to Vol. 1, "Operand Addressing".
4931 */
4932 int scaling = vmx_instruction_info & 3;
4933 int addr_size = (vmx_instruction_info >> 7) & 7;
4934 bool is_reg = vmx_instruction_info & (1u << 10);
4935 int seg_reg = (vmx_instruction_info >> 15) & 7;
4936 int index_reg = (vmx_instruction_info >> 18) & 0xf;
4937 bool index_is_valid = !(vmx_instruction_info & (1u << 22));
4938 int base_reg = (vmx_instruction_info >> 23) & 0xf;
4939 bool base_is_valid = !(vmx_instruction_info & (1u << 27));
4940
4941 if (is_reg) {
4942 kvm_queue_exception(vcpu, UD_VECTOR);
4943 return 1;
4944 }
4945
4946 /* Addr = segment_base + offset */
4947 /* offset = base + [index * scale] + displacement */
4948 *ret = vmx_get_segment_base(vcpu, seg_reg);
4949 if (base_is_valid)
4950 *ret += kvm_register_read(vcpu, base_reg);
4951 if (index_is_valid)
4952 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
4953 *ret += exit_qualification; /* holds the displacement */
4954
4955 if (addr_size == 1) /* 32 bit */
4956 *ret &= 0xffffffff;
4957
4958 /*
4959 * TODO: throw #GP (and return 1) in various cases that the VM*
4960 * instructions require it - e.g., offset beyond segment limit,
4961 * unusable or unreadable/unwritable segment, non-canonical 64-bit
4962 * address, and so on. Currently these are not checked.
4963 */
4964 return 0;
4965}
4966
0140caea
NHE		 4967/*
4968 * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
4969 * set the success or error code of an emulated VMX instruction, as specified
4970 * by Vol 2B, VMX Instruction Reference, "Conventions".
4971 */
4972static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
4973{
4974 vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
4975 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
4976 X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
4977}
4978
4979static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
4980{
4981 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
4982 & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
4983 X86_EFLAGS_SF | X86_EFLAGS_OF))
4984 | X86_EFLAGS_CF);
4985}
4986
4987static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
4988 u32 vm_instruction_error)
4989{
4990 if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
4991 /*
4992 * failValid writes the error number to the current VMCS, which
4993 * can't be done there isn't a current VMCS.
4994 */
4995 nested_vmx_failInvalid(vcpu);
4996 return;
4997 }
4998 vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
4999 & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5000 X86_EFLAGS_SF | X86_EFLAGS_OF))
5001 | X86_EFLAGS_ZF);
5002 get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5003}
5004
27d6c865
NHE		 5005/* Emulate the VMCLEAR instruction */
5006static int handle_vmclear(struct kvm_vcpu *vcpu)
5007{
5008 struct vcpu_vmx *vmx = to_vmx(vcpu);
5009 gva_t gva;
5010 gpa_t vmptr;
5011 struct vmcs12 *vmcs12;
5012 struct page *page;
5013 struct x86_exception e;
5014
5015 if (!nested_vmx_check_permission(vcpu))
5016 return 1;
5017
5018 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5019 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5020 return 1;
5021
5022 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5023 sizeof(vmptr), &e)) {
5024 kvm_inject_page_fault(vcpu, &e);
5025 return 1;
5026 }
5027
5028 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5029 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5030 skip_emulated_instruction(vcpu);
5031 return 1;
5032 }
5033
5034 if (vmptr == vmx->nested.current_vmptr) {
5035 kunmap(vmx->nested.current_vmcs12_page);
5036 nested_release_page(vmx->nested.current_vmcs12_page);
5037 vmx->nested.current_vmptr = -1ull;
5038 vmx->nested.current_vmcs12 = NULL;
5039 }
5040
5041 page = nested_get_page(vcpu, vmptr);
5042 if (page == NULL) {
5043 /*
5044 * For accurate processor emulation, VMCLEAR beyond available
5045 * physical memory should do nothing at all. However, it is
5046 * possible that a nested vmx bug, not a guest hypervisor bug,
5047 * resulted in this case, so let's shut down before doing any
5048 * more damage:
5049 */
5050 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5051 return 1;
5052 }
5053 vmcs12 = kmap(page);
5054 vmcs12->launch_state = 0;
5055 kunmap(page);
5056 nested_release_page(page);
5057
5058 nested_free_vmcs02(vmx, vmptr);
5059
5060 skip_emulated_instruction(vcpu);
5061 nested_vmx_succeed(vcpu);
5062 return 1;
5063}
5064
cd232ad0
NHE		 5065static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5066
5067/* Emulate the VMLAUNCH instruction */
5068static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5069{
5070 return nested_vmx_run(vcpu, true);
5071}
5072
5073/* Emulate the VMRESUME instruction */
5074static int handle_vmresume(struct kvm_vcpu *vcpu)
5075{
5076
5077 return nested_vmx_run(vcpu, false);
5078}
5079
49f705c5
NHE		 5080enum vmcs_field_type {
5081 VMCS_FIELD_TYPE_U16 = 0,
5082 VMCS_FIELD_TYPE_U64 = 1,
5083 VMCS_FIELD_TYPE_U32 = 2,
5084 VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5085};
5086
5087static inline int vmcs_field_type(unsigned long field)
5088{
5089 if (0x1 & field) /* the *_HIGH fields are all 32 bit */
5090 return VMCS_FIELD_TYPE_U32;
5091 return (field >> 13) & 0x3 ;
5092}
5093
5094static inline int vmcs_field_readonly(unsigned long field)
5095{
5096 return (((field >> 10) & 0x3) == 1);
5097}
5098
5099/*
5100 * Read a vmcs12 field. Since these can have varying lengths and we return
5101 * one type, we chose the biggest type (u64) and zero-extend the return value
5102 * to that size. Note that the caller, handle_vmread, might need to use only
5103 * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5104 * 64-bit fields are to be returned).
5105 */
5106static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5107 unsigned long field, u64 *ret)
5108{
5109 short offset = vmcs_field_to_offset(field);
5110 char *p;
5111
5112 if (offset < 0)
5113 return 0;
5114
5115 p = ((char *)(get_vmcs12(vcpu))) + offset;
5116
5117 switch (vmcs_field_type(field)) {
5118 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5119 *ret = *((natural_width *)p);
5120 return 1;
5121 case VMCS_FIELD_TYPE_U16:
5122 *ret = *((u16 *)p);
5123 return 1;
5124 case VMCS_FIELD_TYPE_U32:
5125 *ret = *((u32 *)p);
5126 return 1;
5127 case VMCS_FIELD_TYPE_U64:
5128 *ret = *((u64 *)p);
5129 return 1;
5130 default:
5131 return 0; /* can never happen. */
5132 }
5133}
5134
5135/*
5136 * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5137 * used before) all generate the same failure when it is missing.
5138 */
5139static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5140{
5141 struct vcpu_vmx *vmx = to_vmx(vcpu);
5142 if (vmx->nested.current_vmptr == -1ull) {
5143 nested_vmx_failInvalid(vcpu);
5144 skip_emulated_instruction(vcpu);
5145 return 0;
5146 }
5147 return 1;
5148}
5149
5150static int handle_vmread(struct kvm_vcpu *vcpu)
5151{
5152 unsigned long field;
5153 u64 field_value;
5154 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5155 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5156 gva_t gva = 0;
5157
5158 if (!nested_vmx_check_permission(vcpu) ||
5159 !nested_vmx_check_vmcs12(vcpu))
5160 return 1;
5161
5162 /* Decode instruction info and find the field to read */
5163 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5164 /* Read the field, zero-extended to a u64 field_value */
5165 if (!vmcs12_read_any(vcpu, field, &field_value)) {
5166 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5167 skip_emulated_instruction(vcpu);
5168 return 1;
5169 }
5170 /*
5171 * Now copy part of this value to register or memory, as requested.
5172 * Note that the number of bits actually copied is 32 or 64 depending
5173 * on the guest's mode (32 or 64 bit), not on the given field's length.
5174 */
5175 if (vmx_instruction_info & (1u << 10)) {
5176 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5177 field_value);
5178 } else {
5179 if (get_vmx_mem_address(vcpu, exit_qualification,
5180 vmx_instruction_info, &gva))
5181 return 1;
5182 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5183 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5184 &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5185 }
5186
5187 nested_vmx_succeed(vcpu);
5188 skip_emulated_instruction(vcpu);
5189 return 1;
5190}
5191
5192
5193static int handle_vmwrite(struct kvm_vcpu *vcpu)
5194{
5195 unsigned long field;
5196 gva_t gva;
5197 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5198 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5199 char *p;
5200 short offset;
5201 /* The value to write might be 32 or 64 bits, depending on L1's long
5202 * mode, and eventually we need to write that into a field of several
5203 * possible lengths. The code below first zero-extends the value to 64
5204 * bit (field_value), and then copies only the approriate number of
5205 * bits into the vmcs12 field.
5206 */
5207 u64 field_value = 0;
5208 struct x86_exception e;
5209
5210 if (!nested_vmx_check_permission(vcpu) ||
5211 !nested_vmx_check_vmcs12(vcpu))
5212 return 1;
5213
5214 if (vmx_instruction_info & (1u << 10))
5215 field_value = kvm_register_read(vcpu,
5216 (((vmx_instruction_info) >> 3) & 0xf));
5217 else {
5218 if (get_vmx_mem_address(vcpu, exit_qualification,
5219 vmx_instruction_info, &gva))
5220 return 1;
5221 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5222 &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5223 kvm_inject_page_fault(vcpu, &e);
5224 return 1;
5225 }
5226 }
5227
5228
5229 field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5230 if (vmcs_field_readonly(field)) {
5231 nested_vmx_failValid(vcpu,
5232 VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5233 skip_emulated_instruction(vcpu);
5234 return 1;
5235 }
5236
5237 offset = vmcs_field_to_offset(field);
5238 if (offset < 0) {
5239 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5240 skip_emulated_instruction(vcpu);
5241 return 1;
5242 }
5243 p = ((char *) get_vmcs12(vcpu)) + offset;
5244
5245 switch (vmcs_field_type(field)) {
5246 case VMCS_FIELD_TYPE_U16:
5247 *(u16 *)p = field_value;
5248 break;
5249 case VMCS_FIELD_TYPE_U32:
5250 *(u32 *)p = field_value;
5251 break;
5252 case VMCS_FIELD_TYPE_U64:
5253 *(u64 *)p = field_value;
5254 break;
5255 case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5256 *(natural_width *)p = field_value;
5257 break;
5258 default:
5259 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5260 skip_emulated_instruction(vcpu);
5261 return 1;
5262 }
5263
5264 nested_vmx_succeed(vcpu);
5265 skip_emulated_instruction(vcpu);
5266 return 1;
5267}
5268
63846663
NHE		 5269/* Emulate the VMPTRLD instruction */
5270static int handle_vmptrld(struct kvm_vcpu *vcpu)
5271{
5272 struct vcpu_vmx *vmx = to_vmx(vcpu);
5273 gva_t gva;
5274 gpa_t vmptr;
5275 struct x86_exception e;
5276
5277 if (!nested_vmx_check_permission(vcpu))
5278 return 1;
5279
5280 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5281 vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5282 return 1;
5283
5284 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5285 sizeof(vmptr), &e)) {
5286 kvm_inject_page_fault(vcpu, &e);
5287 return 1;
5288 }
5289
5290 if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5291 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5292 skip_emulated_instruction(vcpu);
5293 return 1;
5294 }
5295
5296 if (vmx->nested.current_vmptr != vmptr) {
5297 struct vmcs12 *new_vmcs12;
5298 struct page *page;
5299 page = nested_get_page(vcpu, vmptr);
5300 if (page == NULL) {
5301 nested_vmx_failInvalid(vcpu);
5302 skip_emulated_instruction(vcpu);
5303 return 1;
5304 }
5305 new_vmcs12 = kmap(page);
5306 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5307 kunmap(page);
5308 nested_release_page_clean(page);
5309 nested_vmx_failValid(vcpu,
5310 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5311 skip_emulated_instruction(vcpu);
5312 return 1;
5313 }
5314 if (vmx->nested.current_vmptr != -1ull) {
5315 kunmap(vmx->nested.current_vmcs12_page);
5316 nested_release_page(vmx->nested.current_vmcs12_page);
5317 }
5318
5319 vmx->nested.current_vmptr = vmptr;
5320 vmx->nested.current_vmcs12 = new_vmcs12;
5321 vmx->nested.current_vmcs12_page = page;
5322 }
5323
5324 nested_vmx_succeed(vcpu);
5325 skip_emulated_instruction(vcpu);
5326 return 1;
5327}
5328
6a4d7550
NHE		 5329/* Emulate the VMPTRST instruction */
5330static int handle_vmptrst(struct kvm_vcpu *vcpu)
5331{
5332 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5333 u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5334 gva_t vmcs_gva;
5335 struct x86_exception e;
5336
5337 if (!nested_vmx_check_permission(vcpu))
5338 return 1;
5339
5340 if (get_vmx_mem_address(vcpu, exit_qualification,
5341 vmx_instruction_info, &vmcs_gva))
5342 return 1;
5343 /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5344 if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5345 (void *)&to_vmx(vcpu)->nested.current_vmptr,
5346 sizeof(u64), &e)) {
5347 kvm_inject_page_fault(vcpu, &e);
5348 return 1;
5349 }
5350 nested_vmx_succeed(vcpu);
5351 skip_emulated_instruction(vcpu);
5352 return 1;
5353}
5354
6aa8b732
AK		 5355/*
5356 * The exit handlers return 1 if the exit was handled fully and guest execution
5357 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5358 * to be done to userspace and return 0.
5359 */
851ba692 5360static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
6aa8b732
AK		 5361 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5362 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
988ad74f 5363 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
f08864b4 5364 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
6aa8b732 5365 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
6aa8b732
AK		 5366 [EXIT_REASON_CR_ACCESS] = handle_cr,
5367 [EXIT_REASON_DR_ACCESS] = handle_dr,
5368 [EXIT_REASON_CPUID] = handle_cpuid,
5369 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5370 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5371 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5372 [EXIT_REASON_HLT] = handle_halt,
ec25d5e6 5373 [EXIT_REASON_INVD] = handle_invd,
a7052897 5374 [EXIT_REASON_INVLPG] = handle_invlpg,
c21415e8 5375 [EXIT_REASON_VMCALL] = handle_vmcall,
27d6c865 5376 [EXIT_REASON_VMCLEAR] = handle_vmclear,
cd232ad0 5377 [EXIT_REASON_VMLAUNCH] = handle_vmlaunch,
63846663 5378 [EXIT_REASON_VMPTRLD] = handle_vmptrld,
6a4d7550 5379 [EXIT_REASON_VMPTRST] = handle_vmptrst,
49f705c5 5380 [EXIT_REASON_VMREAD] = handle_vmread,
cd232ad0 5381 [EXIT_REASON_VMRESUME] = handle_vmresume,
49f705c5 5382 [EXIT_REASON_VMWRITE] = handle_vmwrite,
ec378aee
NHE		 5383 [EXIT_REASON_VMOFF] = handle_vmoff,
5384 [EXIT_REASON_VMON] = handle_vmon,
f78e0e2e
SY		 5385 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5386 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
e5edaa01 5387 [EXIT_REASON_WBINVD] = handle_wbinvd,
2acf923e 5388 [EXIT_REASON_XSETBV] = handle_xsetbv,
37817f29 5389 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
a0861c02 5390 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
68f89400
MT		 5391 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5392 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
4b8d54f9 5393 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
59708670
SY		 5394 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_invalid_op,
5395 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_invalid_op,
6aa8b732
AK		 5396};
5397
5398static const int kvm_vmx_max_exit_handlers =
50a3485c 5399 ARRAY_SIZE(kvm_vmx_exit_handlers);
6aa8b732 5400
644d711a
NHE		 5401/*
5402 * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5403 * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5404 * disinterest in the current event (read or write a specific MSR) by using an
5405 * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5406 */
5407static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5408 struct vmcs12 *vmcs12, u32 exit_reason)
5409{
5410 u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5411 gpa_t bitmap;
5412
5413 if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5414 return 1;
5415
5416 /*
5417 * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5418 * for the four combinations of read/write and low/high MSR numbers.
5419 * First we need to figure out which of the four to use:
5420 */
5421 bitmap = vmcs12->msr_bitmap;
5422 if (exit_reason == EXIT_REASON_MSR_WRITE)
5423 bitmap += 2048;
5424 if (msr_index >= 0xc0000000) {
5425 msr_index -= 0xc0000000;
5426 bitmap += 1024;
5427 }
5428
5429 /* Then read the msr_index'th bit from this bitmap: */
5430 if (msr_index < 1024*8) {
5431 unsigned char b;
5432 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5433 return 1 & (b >> (msr_index & 7));
5434 } else
5435 return 1; /* let L1 handle the wrong parameter */
5436}
5437
5438/*
5439 * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5440 * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5441 * intercept (via guest_host_mask etc.) the current event.
5442 */
5443static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5444 struct vmcs12 *vmcs12)
5445{
5446 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5447 int cr = exit_qualification & 15;
5448 int reg = (exit_qualification >> 8) & 15;
5449 unsigned long val = kvm_register_read(vcpu, reg);
5450
5451 switch ((exit_qualification >> 4) & 3) {
5452 case 0: /* mov to cr */
5453 switch (cr) {
5454 case 0:
5455 if (vmcs12->cr0_guest_host_mask &
5456 (val ^ vmcs12->cr0_read_shadow))
5457 return 1;
5458 break;
5459 case 3:
5460 if ((vmcs12->cr3_target_count >= 1 &&
5461 vmcs12->cr3_target_value0 == val) ||
5462 (vmcs12->cr3_target_count >= 2 &&
5463 vmcs12->cr3_target_value1 == val) ||
5464 (vmcs12->cr3_target_count >= 3 &&
5465 vmcs12->cr3_target_value2 == val) ||
5466 (vmcs12->cr3_target_count >= 4 &&
5467 vmcs12->cr3_target_value3 == val))
5468 return 0;
5469 if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5470 return 1;
5471 break;
5472 case 4:
5473 if (vmcs12->cr4_guest_host_mask &
5474 (vmcs12->cr4_read_shadow ^ val))
5475 return 1;
5476 break;
5477 case 8:
5478 if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5479 return 1;
5480 break;
5481 }
5482 break;
5483 case 2: /* clts */
5484 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5485 (vmcs12->cr0_read_shadow & X86_CR0_TS))
5486 return 1;
5487 break;
5488 case 1: /* mov from cr */
5489 switch (cr) {
5490 case 3:
5491 if (vmcs12->cpu_based_vm_exec_control &
5492 CPU_BASED_CR3_STORE_EXITING)
5493 return 1;
5494 break;
5495 case 8:
5496 if (vmcs12->cpu_based_vm_exec_control &
5497 CPU_BASED_CR8_STORE_EXITING)
5498 return 1;
5499 break;
5500 }
5501 break;
5502 case 3: /* lmsw */
5503 /*
5504 * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5505 * cr0. Other attempted changes are ignored, with no exit.
5506 */
5507 if (vmcs12->cr0_guest_host_mask & 0xe &
5508 (val ^ vmcs12->cr0_read_shadow))
5509 return 1;
5510 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5511 !(vmcs12->cr0_read_shadow & 0x1) &&
5512 (val & 0x1))
5513 return 1;
5514 break;
5515 }
5516 return 0;
5517}
5518
5519/*
5520 * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5521 * should handle it ourselves in L0 (and then continue L2). Only call this
5522 * when in is_guest_mode (L2).
5523 */
5524static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5525{
5526 u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5527 u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5528 struct vcpu_vmx *vmx = to_vmx(vcpu);
5529 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5530
5531 if (vmx->nested.nested_run_pending)
5532 return 0;
5533
5534 if (unlikely(vmx->fail)) {
5535 printk(KERN_INFO "%s failed vm entry %x\n",
5536 __func__, vmcs_read32(VM_INSTRUCTION_ERROR));
5537 return 1;
5538 }
5539
5540 switch (exit_reason) {
5541 case EXIT_REASON_EXCEPTION_NMI:
5542 if (!is_exception(intr_info))
5543 return 0;
5544 else if (is_page_fault(intr_info))
5545 return enable_ept;
5546 return vmcs12->exception_bitmap &
5547 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5548 case EXIT_REASON_EXTERNAL_INTERRUPT:
5549 return 0;
5550 case EXIT_REASON_TRIPLE_FAULT:
5551 return 1;
5552 case EXIT_REASON_PENDING_INTERRUPT:
5553 case EXIT_REASON_NMI_WINDOW:
5554 /*
5555 * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5556 * (aka Interrupt Window Exiting) only when L1 turned it on,
5557 * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5558 * Same for NMI Window Exiting.
5559 */
5560 return 1;
5561 case EXIT_REASON_TASK_SWITCH:
5562 return 1;
5563 case EXIT_REASON_CPUID:
5564 return 1;
5565 case EXIT_REASON_HLT:
5566 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5567 case EXIT_REASON_INVD:
5568 return 1;
5569 case EXIT_REASON_INVLPG:
5570 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5571 case EXIT_REASON_RDPMC:
5572 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5573 case EXIT_REASON_RDTSC:
5574 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5575 case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5576 case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5577 case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5578 case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5579 case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5580 /*
5581 * VMX instructions trap unconditionally. This allows L1 to
5582 * emulate them for its L2 guest, i.e., allows 3-level nesting!
5583 */
5584 return 1;
5585 case EXIT_REASON_CR_ACCESS:
5586 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5587 case EXIT_REASON_DR_ACCESS:
5588 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5589 case EXIT_REASON_IO_INSTRUCTION:
5590 /* TODO: support IO bitmaps */
5591 return 1;
5592 case EXIT_REASON_MSR_READ:
5593 case EXIT_REASON_MSR_WRITE:
5594 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5595 case EXIT_REASON_INVALID_STATE:
5596 return 1;
5597 case EXIT_REASON_MWAIT_INSTRUCTION:
5598 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5599 case EXIT_REASON_MONITOR_INSTRUCTION:
5600 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5601 case EXIT_REASON_PAUSE_INSTRUCTION:
5602 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5603 nested_cpu_has2(vmcs12,
5604 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5605 case EXIT_REASON_MCE_DURING_VMENTRY:
5606 return 0;
5607 case EXIT_REASON_TPR_BELOW_THRESHOLD:
5608 return 1;
5609 case EXIT_REASON_APIC_ACCESS:
5610 return nested_cpu_has2(vmcs12,
5611 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5612 case EXIT_REASON_EPT_VIOLATION:
5613 case EXIT_REASON_EPT_MISCONFIG:
5614 return 0;
5615 case EXIT_REASON_WBINVD:
5616 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5617 case EXIT_REASON_XSETBV:
5618 return 1;
5619 default:
5620 return 1;
5621 }
5622}
5623
586f9607
AK		 5624static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5625{
5626 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5627 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5628}
5629
6aa8b732
AK		 5630/*
5631 * The guest has exited. See if we can fix it or if we need userspace
5632 * assistance.
5633 */
851ba692 5634static int vmx_handle_exit(struct kvm_vcpu *vcpu)
6aa8b732 5635{
29bd8a78 5636 struct vcpu_vmx *vmx = to_vmx(vcpu);
a0861c02 5637 u32 exit_reason = vmx->exit_reason;
1155f76a 5638 u32 vectoring_info = vmx->idt_vectoring_info;
29bd8a78 5639
aa17911e 5640 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
2714d1d3 5641
80ced186
MG		 5642 /* If guest state is invalid, start emulating */
5643 if (vmx->emulation_required && emulate_invalid_guest_state)
5644 return handle_invalid_guest_state(vcpu);
1d5a4d9b 5645
b6f1250e
NHE		 5646 /*
5647 * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5648 * we did not inject a still-pending event to L1 now because of
5649 * nested_run_pending, we need to re-enable this bit.
5650 */
5651 if (vmx->nested.nested_run_pending)
5652 kvm_make_request(KVM_REQ_EVENT, vcpu);
5653
644d711a
NHE		 5654 if (exit_reason == EXIT_REASON_VMLAUNCH ||
5655 exit_reason == EXIT_REASON_VMRESUME)
5656 vmx->nested.nested_run_pending = 1;
5657 else
5658 vmx->nested.nested_run_pending = 0;
5659
5660 if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5661 nested_vmx_vmexit(vcpu);
5662 return 1;
5663 }
5664
5120702e
MG		 5665 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5666 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5667 vcpu->run->fail_entry.hardware_entry_failure_reason
5668 = exit_reason;
5669 return 0;
5670 }
5671
29bd8a78 5672 if (unlikely(vmx->fail)) {
851ba692
AK		 5673 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5674 vcpu->run->fail_entry.hardware_entry_failure_reason
29bd8a78
AK		 5675 = vmcs_read32(VM_INSTRUCTION_ERROR);
5676 return 0;
5677 }
6aa8b732 5678
d77c26fc 5679 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
1439442c 5680 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
60637aac
JK		 5681 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5682 exit_reason != EXIT_REASON_TASK_SWITCH))
5683 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5684 "(0x%x) and exit reason is 0x%x\n",
5685 __func__, vectoring_info, exit_reason);
3b86cd99 5686
644d711a
NHE		 5687 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5688 !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5689 get_vmcs12(vcpu), vcpu)))) {
c4282df9 5690 if (vmx_interrupt_allowed(vcpu)) {
3b86cd99 5691 vmx->soft_vnmi_blocked = 0;
3b86cd99 5692 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
4531220b 5693 vcpu->arch.nmi_pending) {
3b86cd99
JK		 5694 /*
5695 * This CPU don't support us in finding the end of an
5696 * NMI-blocked window if the guest runs with IRQs
5697 * disabled. So we pull the trigger after 1 s of
5698 * futile waiting, but inform the user about this.
5699 */
5700 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5701 "state on VCPU %d after 1 s timeout\n",
5702 __func__, vcpu->vcpu_id);
5703 vmx->soft_vnmi_blocked = 0;
3b86cd99 5704 }
3b86cd99
JK		 5705 }
5706
6aa8b732
AK		 5707 if (exit_reason < kvm_vmx_max_exit_handlers
5708 && kvm_vmx_exit_handlers[exit_reason])
851ba692 5709 return kvm_vmx_exit_handlers[exit_reason](vcpu);
6aa8b732 5710 else {
851ba692
AK		 5711 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5712 vcpu->run->hw.hardware_exit_reason = exit_reason;
6aa8b732
AK		 5713 }
5714 return 0;
5715}
5716
95ba8273 5717static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
6e5d865c 5718{
95ba8273 5719 if (irr == -1 || tpr < irr) {
6e5d865c
YS		 5720 vmcs_write32(TPR_THRESHOLD, 0);
5721 return;
5722 }
5723
95ba8273 5724 vmcs_write32(TPR_THRESHOLD, irr);
6e5d865c
YS		 5725}
5726
51aa01d1 5727static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
cf393f75 5728{
00eba012
AK		 5729 u32 exit_intr_info;
5730
5731 if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
5732 || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
5733 return;
5734
c5ca8e57 5735 vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
00eba012 5736 exit_intr_info = vmx->exit_intr_info;
a0861c02
AK		 5737
5738 /* Handle machine checks before interrupts are enabled */
00eba012 5739 if (is_machine_check(exit_intr_info))
a0861c02
AK		 5740 kvm_machine_check();
5741
20f65983 5742 /* We need to handle NMIs before interrupts are enabled */
00eba012 5743 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
ff9d07a0
ZY		 5744 (exit_intr_info & INTR_INFO_VALID_MASK)) {
5745 kvm_before_handle_nmi(&vmx->vcpu);
20f65983 5746 asm("int $2");
ff9d07a0
ZY		 5747 kvm_after_handle_nmi(&vmx->vcpu);
5748 }
51aa01d1 5749}
20f65983 5750
51aa01d1
AK		 5751static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
5752{
c5ca8e57 5753 u32 exit_intr_info;
51aa01d1
AK		 5754 bool unblock_nmi;
5755 u8 vector;
5756 bool idtv_info_valid;
5757
5758 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
20f65983 5759
cf393f75 5760 if (cpu_has_virtual_nmis()) {
9d58b931
AK		 5761 if (vmx->nmi_known_unmasked)
5762 return;
c5ca8e57
AK		 5763 /*
5764 * Can't use vmx->exit_intr_info since we're not sure what
5765 * the exit reason is.
5766 */
5767 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
cf393f75
AK		 5768 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
5769 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
5770 /*
7b4a25cb 5771 * SDM 3: 27.7.1.2 (September 2008)
cf393f75
AK		 5772 * Re-set bit "block by NMI" before VM entry if vmexit caused by
5773 * a guest IRET fault.
7b4a25cb
GN		 5774 * SDM 3: 23.2.2 (September 2008)
5775 * Bit 12 is undefined in any of the following cases:
5776 * If the VM exit sets the valid bit in the IDT-vectoring
5777 * information field.
5778 * If the VM exit is due to a double fault.
cf393f75 5779 */
7b4a25cb
GN		 5780 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
5781 vector != DF_VECTOR && !idtv_info_valid)
cf393f75
AK		 5782 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5783 GUEST_INTR_STATE_NMI);
9d58b931
AK		 5784 else
5785 vmx->nmi_known_unmasked =
5786 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
5787 & GUEST_INTR_STATE_NMI);
3b86cd99
JK		 5788 } else if (unlikely(vmx->soft_vnmi_blocked))
5789 vmx->vnmi_blocked_time +=
5790 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
51aa01d1
AK		 5791}
5792
83422e17
AK		 5793static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
5794 u32 idt_vectoring_info,
5795 int instr_len_field,
5796 int error_code_field)
51aa01d1 5797{
51aa01d1
AK		 5798 u8 vector;
5799 int type;
5800 bool idtv_info_valid;
5801
5802 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
668f612f 5803
37b96e98
GN		 5804 vmx->vcpu.arch.nmi_injected = false;
5805 kvm_clear_exception_queue(&vmx->vcpu);
5806 kvm_clear_interrupt_queue(&vmx->vcpu);
5807
5808 if (!idtv_info_valid)
5809 return;
5810
3842d135
AK		 5811 kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5812
668f612f
AK		 5813 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
5814 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
37b96e98 5815
64a7ec06 5816 switch (type) {
37b96e98
GN		 5817 case INTR_TYPE_NMI_INTR:
5818 vmx->vcpu.arch.nmi_injected = true;
668f612f 5819 /*
7b4a25cb 5820 * SDM 3: 27.7.1.2 (September 2008)
37b96e98
GN		 5821 * Clear bit "block by NMI" before VM entry if a NMI
5822 * delivery faulted.
668f612f 5823 */
654f06fc 5824 vmx_set_nmi_mask(&vmx->vcpu, false);
37b96e98 5825 break;
37b96e98 5826 case INTR_TYPE_SOFT_EXCEPTION:
66fd3f7f 5827 vmx->vcpu.arch.event_exit_inst_len =
83422e17 5828 vmcs_read32(instr_len_field);
66fd3f7f
GN		 5829 /* fall through */
5830 case INTR_TYPE_HARD_EXCEPTION:
35920a35 5831 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
83422e17 5832 u32 err = vmcs_read32(error_code_field);
37b96e98 5833 kvm_queue_exception_e(&vmx->vcpu, vector, err);
35920a35
AK		 5834 } else
5835 kvm_queue_exception(&vmx->vcpu, vector);
37b96e98 5836 break;
66fd3f7f
GN		 5837 case INTR_TYPE_SOFT_INTR:
5838 vmx->vcpu.arch.event_exit_inst_len =
83422e17 5839 vmcs_read32(instr_len_field);
66fd3f7f 5840 /* fall through */
37b96e98 5841 case INTR_TYPE_EXT_INTR:
66fd3f7f
GN		 5842 kvm_queue_interrupt(&vmx->vcpu, vector,
5843 type == INTR_TYPE_SOFT_INTR);
37b96e98
GN		 5844 break;
5845 default:
5846 break;
f7d9238f 5847 }
cf393f75
AK		 5848}
5849
83422e17
AK		 5850static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
5851{
66c78ae4
NHE		 5852 if (is_guest_mode(&vmx->vcpu))
5853 return;
83422e17
AK		 5854 __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
5855 VM_EXIT_INSTRUCTION_LEN,
5856 IDT_VECTORING_ERROR_CODE);
5857}
5858
b463a6f7
AK		 5859static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
5860{
66c78ae4
NHE		 5861 if (is_guest_mode(vcpu))
5862 return;
b463a6f7
AK		 5863 __vmx_complete_interrupts(to_vmx(vcpu),
5864 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5865 VM_ENTRY_INSTRUCTION_LEN,
5866 VM_ENTRY_EXCEPTION_ERROR_CODE);
5867
5868 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
5869}
5870
c801949d
AK		 5871#ifdef CONFIG_X86_64
5872#define R "r"
5873#define Q "q"
5874#else
5875#define R "e"
5876#define Q "l"
5877#endif
5878
a3b5ba49 5879static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6aa8b732 5880{
a2fa3e9f 5881 struct vcpu_vmx *vmx = to_vmx(vcpu);
104f226b 5882
66c78ae4
NHE		 5883 if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
5884 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5885 if (vmcs12->idt_vectoring_info_field &
5886 VECTORING_INFO_VALID_MASK) {
5887 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5888 vmcs12->idt_vectoring_info_field);
5889 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5890 vmcs12->vm_exit_instruction_len);
5891 if (vmcs12->idt_vectoring_info_field &
5892 VECTORING_INFO_DELIVER_CODE_MASK)
5893 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
5894 vmcs12->idt_vectoring_error_code);
5895 }
5896 }
5897
104f226b
AK		 5898 /* Record the guest's net vcpu time for enforced NMI injections. */
5899 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
5900 vmx->entry_time = ktime_get();
5901
5902 /* Don't enter VMX if guest state is invalid, let the exit handler
5903 start emulation until we arrive back to a valid state */
5904 if (vmx->emulation_required && emulate_invalid_guest_state)
5905 return;
5906
5907 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
5908 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
5909 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
5910 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
5911
5912 /* When single-stepping over STI and MOV SS, we must clear the
5913 * corresponding interruptibility bits in the guest state. Otherwise
5914 * vmentry fails as it then expects bit 14 (BS) in pending debug
5915 * exceptions being set, but that's not correct for the guest debugging
5916 * case. */
5917 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
5918 vmx_set_interrupt_shadow(vcpu, 0);
5919
d462b819 5920 vmx->__launched = vmx->loaded_vmcs->launched;
104f226b 5921 asm(
6aa8b732 5922 /* Store host registers */
c801949d 5923 "push %%"R"dx; push %%"R"bp;"
40712fae 5924 "push %%"R"cx \n\t" /* placeholder for guest rcx */
c801949d 5925 "push %%"R"cx \n\t"
313dbd49
AK		 5926 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
5927 "je 1f \n\t"
5928 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
4ecac3fd 5929 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
313dbd49 5930 "1: \n\t"
d3edefc0
AK		 5931 /* Reload cr2 if changed */
5932 "mov %c[cr2](%0), %%"R"ax \n\t"
5933 "mov %%cr2, %%"R"dx \n\t"
5934 "cmp %%"R"ax, %%"R"dx \n\t"
5935 "je 2f \n\t"
5936 "mov %%"R"ax, %%cr2 \n\t"
5937 "2: \n\t"
6aa8b732 5938 /* Check if vmlaunch of vmresume is needed */
e08aa78a 5939 "cmpl $0, %c[launched](%0) \n\t"
6aa8b732 5940 /* Load guest registers. Don't clobber flags. */
c801949d
AK		 5941 "mov %c[rax](%0), %%"R"ax \n\t"
5942 "mov %c[rbx](%0), %%"R"bx \n\t"
5943 "mov %c[rdx](%0), %%"R"dx \n\t"
5944 "mov %c[rsi](%0), %%"R"si \n\t"
5945 "mov %c[rdi](%0), %%"R"di \n\t"
5946 "mov %c[rbp](%0), %%"R"bp \n\t"
05b3e0c2 5947#ifdef CONFIG_X86_64
e08aa78a
AK		 5948 "mov %c[r8](%0), %%r8 \n\t"
5949 "mov %c[r9](%0), %%r9 \n\t"
5950 "mov %c[r10](%0), %%r10 \n\t"
5951 "mov %c[r11](%0), %%r11 \n\t"
5952 "mov %c[r12](%0), %%r12 \n\t"
5953 "mov %c[r13](%0), %%r13 \n\t"
5954 "mov %c[r14](%0), %%r14 \n\t"
5955 "mov %c[r15](%0), %%r15 \n\t"
6aa8b732 5956#endif
c801949d
AK		 5957 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
5958
6aa8b732 5959 /* Enter guest mode */
cd2276a7 5960 "jne .Llaunched \n\t"
4ecac3fd 5961 __ex(ASM_VMX_VMLAUNCH) "\n\t"
cd2276a7 5962 "jmp .Lkvm_vmx_return \n\t"
4ecac3fd 5963 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
cd2276a7 5964 ".Lkvm_vmx_return: "
6aa8b732 5965 /* Save guest registers, load host registers, keep flags */
40712fae
AK		 5966 "mov %0, %c[wordsize](%%"R"sp) \n\t"
5967 "pop %0 \n\t"
c801949d
AK		 5968 "mov %%"R"ax, %c[rax](%0) \n\t"
5969 "mov %%"R"bx, %c[rbx](%0) \n\t"
1c696d0e 5970 "pop"Q" %c[rcx](%0) \n\t"
c801949d
AK		 5971 "mov %%"R"dx, %c[rdx](%0) \n\t"
5972 "mov %%"R"si, %c[rsi](%0) \n\t"
5973 "mov %%"R"di, %c[rdi](%0) \n\t"
5974 "mov %%"R"bp, %c[rbp](%0) \n\t"
05b3e0c2 5975#ifdef CONFIG_X86_64
e08aa78a
AK		 5976 "mov %%r8, %c[r8](%0) \n\t"
5977 "mov %%r9, %c[r9](%0) \n\t"
5978 "mov %%r10, %c[r10](%0) \n\t"
5979 "mov %%r11, %c[r11](%0) \n\t"
5980 "mov %%r12, %c[r12](%0) \n\t"
5981 "mov %%r13, %c[r13](%0) \n\t"
5982 "mov %%r14, %c[r14](%0) \n\t"
5983 "mov %%r15, %c[r15](%0) \n\t"
6aa8b732 5984#endif
c801949d
AK		 5985 "mov %%cr2, %%"R"ax \n\t"
5986 "mov %%"R"ax, %c[cr2](%0) \n\t"
5987
1c696d0e 5988 "pop %%"R"bp; pop %%"R"dx \n\t"
e08aa78a
AK		 5989 "setbe %c[fail](%0) \n\t"
5990 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
d462b819 5991 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
e08aa78a 5992 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
313dbd49 5993 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
ad312c7c
ZX		 5994 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
5995 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
5996 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
5997 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
5998 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
5999 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6000 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
05b3e0c2 6001#ifdef CONFIG_X86_64
ad312c7c
ZX		 6002 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6003 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6004 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6005 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6006 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6007 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6008 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6009 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6aa8b732 6010#endif
40712fae
AK		 6011 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6012 [wordsize]"i"(sizeof(ulong))
c2036300 6013 : "cc", "memory"
07d6f555 6014 , R"ax", R"bx", R"di", R"si"
c2036300 6015#ifdef CONFIG_X86_64
c2036300
LV		 6016 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6017#endif
6018 );
6aa8b732 6019
6de4f3ad 6020 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6de12732 6021 | (1 << VCPU_EXREG_RFLAGS)
69c73028 6022 | (1 << VCPU_EXREG_CPL)
aff48baa 6023 | (1 << VCPU_EXREG_PDPTR)
2fb92db1 6024 | (1 << VCPU_EXREG_SEGMENTS)
aff48baa 6025 | (1 << VCPU_EXREG_CR3));
5fdbf976
MT		 6026 vcpu->arch.regs_dirty = 0;
6027
1155f76a
AK		 6028 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6029
66c78ae4
NHE		 6030 if (is_guest_mode(vcpu)) {
6031 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6032 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6033 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6034 vmcs12->idt_vectoring_error_code =
6035 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6036 vmcs12->vm_exit_instruction_len =
6037 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6038 }
6039 }
6040
d77c26fc 6041 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
d462b819 6042 vmx->loaded_vmcs->launched = 1;
1b6269db 6043
51aa01d1 6044 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
51aa01d1
AK		 6045
6046 vmx_complete_atomic_exit(vmx);
6047 vmx_recover_nmi_blocking(vmx);
cf393f75 6048 vmx_complete_interrupts(vmx);
6aa8b732
AK		 6049}
6050
c801949d
AK		 6051#undef R
6052#undef Q
6053
6aa8b732
AK		 6054static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6055{
fb3f0f51
RR		 6056 struct vcpu_vmx *vmx = to_vmx(vcpu);
6057
cdbecfc3 6058 free_vpid(vmx);
ec378aee 6059 free_nested(vmx);
d462b819 6060 free_loaded_vmcs(vmx->loaded_vmcs);
fb3f0f51
RR		 6061 kfree(vmx->guest_msrs);
6062 kvm_vcpu_uninit(vcpu);
a4770347 6063 kmem_cache_free(kvm_vcpu_cache, vmx);
6aa8b732
AK		 6064}
6065
fb3f0f51 6066static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6aa8b732 6067{
fb3f0f51 6068 int err;
c16f862d 6069 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
15ad7146 6070 int cpu;
6aa8b732 6071
a2fa3e9f 6072 if (!vmx)
fb3f0f51
RR		 6073 return ERR_PTR(-ENOMEM);
6074
2384d2b3
SY		 6075 allocate_vpid(vmx);
6076
fb3f0f51
RR		 6077 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6078 if (err)
6079 goto free_vcpu;
965b58a5 6080
a2fa3e9f 6081 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
be6d05cf 6082 err = -ENOMEM;
fb3f0f51 6083 if (!vmx->guest_msrs) {
fb3f0f51
RR		 6084 goto uninit_vcpu;
6085 }
965b58a5 6086
d462b819
NHE		 6087 vmx->loaded_vmcs = &vmx->vmcs01;
6088 vmx->loaded_vmcs->vmcs = alloc_vmcs();
6089 if (!vmx->loaded_vmcs->vmcs)
fb3f0f51 6090 goto free_msrs;
d462b819
NHE		 6091 if (!vmm_exclusive)
6092 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6093 loaded_vmcs_init(vmx->loaded_vmcs);
6094 if (!vmm_exclusive)
6095 kvm_cpu_vmxoff();
a2fa3e9f 6096
15ad7146
AK		 6097 cpu = get_cpu();
6098 vmx_vcpu_load(&vmx->vcpu, cpu);
e48672fa 6099 vmx->vcpu.cpu = cpu;
8b9cf98c 6100 err = vmx_vcpu_setup(vmx);
fb3f0f51 6101 vmx_vcpu_put(&vmx->vcpu);
15ad7146 6102 put_cpu();
fb3f0f51
RR		 6103 if (err)
6104 goto free_vmcs;
5e4a0b3c 6105 if (vm_need_virtualize_apic_accesses(kvm))
be6d05cf
JK		 6106 err = alloc_apic_access_page(kvm);
6107 if (err)
5e4a0b3c 6108 goto free_vmcs;
fb3f0f51 6109
b927a3ce
SY		 6110 if (enable_ept) {
6111 if (!kvm->arch.ept_identity_map_addr)
6112 kvm->arch.ept_identity_map_addr =
6113 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
93ea5388 6114 err = -ENOMEM;
b7ebfb05
SY		 6115 if (alloc_identity_pagetable(kvm) != 0)
6116 goto free_vmcs;
93ea5388
GN		 6117 if (!init_rmode_identity_map(kvm))
6118 goto free_vmcs;
b927a3ce 6119 }
b7ebfb05 6120
a9d30f33
NHE		 6121 vmx->nested.current_vmptr = -1ull;
6122 vmx->nested.current_vmcs12 = NULL;
6123
fb3f0f51
RR		 6124 return &vmx->vcpu;
6125
6126free_vmcs:
d462b819 6127 free_vmcs(vmx->loaded_vmcs->vmcs);
fb3f0f51 6128free_msrs:
fb3f0f51
RR		 6129 kfree(vmx->guest_msrs);
6130uninit_vcpu:
6131 kvm_vcpu_uninit(&vmx->vcpu);
6132free_vcpu:
cdbecfc3 6133 free_vpid(vmx);
a4770347 6134 kmem_cache_free(kvm_vcpu_cache, vmx);
fb3f0f51 6135 return ERR_PTR(err);
6aa8b732
AK		 6136}
6137
002c7f7c
YS		 6138static void __init vmx_check_processor_compat(void *rtn)
6139{
6140 struct vmcs_config vmcs_conf;
6141
6142 *(int *)rtn = 0;
6143 if (setup_vmcs_config(&vmcs_conf) < 0)
6144 *(int *)rtn = -EIO;
6145 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6146 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6147 smp_processor_id());
6148 *(int *)rtn = -EIO;
6149 }
6150}
6151
67253af5
SY		 6152static int get_ept_level(void)
6153{
6154 return VMX_EPT_DEFAULT_GAW + 1;
6155}
6156
4b12f0de 6157static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
64d4d521 6158{
4b12f0de
SY		 6159 u64 ret;
6160
522c68c4
SY		 6161 /* For VT-d and EPT combination
6162 * 1. MMIO: always map as UC
6163 * 2. EPT with VT-d:
6164 * a. VT-d without snooping control feature: can't guarantee the
6165 * result, try to trust guest.
6166 * b. VT-d with snooping control feature: snooping control feature of
6167 * VT-d engine can guarantee the cache correctness. Just set it
6168 * to WB to keep consistent with host. So the same as item 3.
a19a6d11 6169 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
522c68c4
SY		 6170 * consistent with host MTRR
6171 */
4b12f0de
SY		 6172 if (is_mmio)
6173 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
522c68c4
SY		 6174 else if (vcpu->kvm->arch.iommu_domain &&
6175 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6176 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6177 VMX_EPT_MT_EPTE_SHIFT;
4b12f0de 6178 else
522c68c4 6179 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
a19a6d11 6180 | VMX_EPT_IPAT_BIT;
4b12f0de
SY		 6181
6182 return ret;
64d4d521
SY		 6183}
6184
f4c9e87c
AK		 6185#define _ER(x) { EXIT_REASON_##x, #x }
6186
229456fc 6187static const struct trace_print_flags vmx_exit_reasons_str[] = {
f4c9e87c
AK		 6188 _ER(EXCEPTION_NMI),
6189 _ER(EXTERNAL_INTERRUPT),
6190 _ER(TRIPLE_FAULT),
6191 _ER(PENDING_INTERRUPT),
6192 _ER(NMI_WINDOW),
6193 _ER(TASK_SWITCH),
6194 _ER(CPUID),
6195 _ER(HLT),
6196 _ER(INVLPG),
6197 _ER(RDPMC),
6198 _ER(RDTSC),
6199 _ER(VMCALL),
6200 _ER(VMCLEAR),
6201 _ER(VMLAUNCH),
6202 _ER(VMPTRLD),
6203 _ER(VMPTRST),
6204 _ER(VMREAD),
6205 _ER(VMRESUME),
6206 _ER(VMWRITE),
6207 _ER(VMOFF),
6208 _ER(VMON),
6209 _ER(CR_ACCESS),
6210 _ER(DR_ACCESS),
6211 _ER(IO_INSTRUCTION),
6212 _ER(MSR_READ),
6213 _ER(MSR_WRITE),
6214 _ER(MWAIT_INSTRUCTION),
6215 _ER(MONITOR_INSTRUCTION),
6216 _ER(PAUSE_INSTRUCTION),
6217 _ER(MCE_DURING_VMENTRY),
6218 _ER(TPR_BELOW_THRESHOLD),
6219 _ER(APIC_ACCESS),
6220 _ER(EPT_VIOLATION),
6221 _ER(EPT_MISCONFIG),
6222 _ER(WBINVD),
229456fc
MT		 6223 { -1, NULL }
6224};
6225
f4c9e87c
AK		 6226#undef _ER
6227
17cc3935 6228static int vmx_get_lpage_level(void)
344f414f 6229{
878403b7
SY		 6230 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6231 return PT_DIRECTORY_LEVEL;
6232 else
6233 /* For shadow and EPT supported 1GB page */
6234 return PT_PDPE_LEVEL;
344f414f
JR		 6235}
6236
0e851880
SY		 6237static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6238{
4e47c7a6
SY		 6239 struct kvm_cpuid_entry2 *best;
6240 struct vcpu_vmx *vmx = to_vmx(vcpu);
6241 u32 exec_control;
6242
6243 vmx->rdtscp_enabled = false;
6244 if (vmx_rdtscp_supported()) {
6245 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6246 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6247 best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6248 if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6249 vmx->rdtscp_enabled = true;
6250 else {
6251 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6252 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6253 exec_control);
6254 }
6255 }
6256 }
0e851880
SY		 6257}
6258
d4330ef2
JR		 6259static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6260{
6261}
6262
fe3ef05c
NHE		 6263/*
6264 * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6265 * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6266 * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6267 * guest in a way that will both be appropriate to L1's requests, and our
6268 * needs. In addition to modifying the active vmcs (which is vmcs02), this
6269 * function also has additional necessary side-effects, like setting various
6270 * vcpu->arch fields.
6271 */
6272static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6273{
6274 struct vcpu_vmx *vmx = to_vmx(vcpu);
6275 u32 exec_control;
6276
6277 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6278 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6279 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6280 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6281 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6282 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6283 vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6284 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6285 vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6286 vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6287 vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6288 vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6289 vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6290 vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6291 vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6292 vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6293 vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6294 vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6295 vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6296 vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6297 vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6298 vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6299 vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6300 vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6301 vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6302 vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6303 vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6304 vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6305 vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6306 vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6307 vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6308 vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6309 vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6310 vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6311 vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6312 vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6313
6314 vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6315 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6316 vmcs12->vm_entry_intr_info_field);
6317 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6318 vmcs12->vm_entry_exception_error_code);
6319 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6320 vmcs12->vm_entry_instruction_len);
6321 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6322 vmcs12->guest_interruptibility_info);
6323 vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6324 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6325 vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6326 vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6327 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6328 vmcs12->guest_pending_dbg_exceptions);
6329 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6330 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6331
6332 vmcs_write64(VMCS_LINK_POINTER, -1ull);
6333
6334 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6335 (vmcs_config.pin_based_exec_ctrl |
6336 vmcs12->pin_based_vm_exec_control));
6337
6338 /*
6339 * Whether page-faults are trapped is determined by a combination of
6340 * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6341 * If enable_ept, L0 doesn't care about page faults and we should
6342 * set all of these to L1's desires. However, if !enable_ept, L0 does
6343 * care about (at least some) page faults, and because it is not easy
6344 * (if at all possible?) to merge L0 and L1's desires, we simply ask
6345 * to exit on each and every L2 page fault. This is done by setting
6346 * MASK=MATCH=0 and (see below) EB.PF=1.
6347 * Note that below we don't need special code to set EB.PF beyond the
6348 * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6349 * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6350 * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6351 *
6352 * A problem with this approach (when !enable_ept) is that L1 may be
6353 * injected with more page faults than it asked for. This could have
6354 * caused problems, but in practice existing hypervisors don't care.
6355 * To fix this, we will need to emulate the PFEC checking (on the L1
6356 * page tables), using walk_addr(), when injecting PFs to L1.
6357 */
6358 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6359 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6360 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6361 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6362
6363 if (cpu_has_secondary_exec_ctrls()) {
6364 u32 exec_control = vmx_secondary_exec_control(vmx);
6365 if (!vmx->rdtscp_enabled)
6366 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6367 /* Take the following fields only from vmcs12 */
6368 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6369 if (nested_cpu_has(vmcs12,
6370 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6371 exec_control |= vmcs12->secondary_vm_exec_control;
6372
6373 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6374 /*
6375 * Translate L1 physical address to host physical
6376 * address for vmcs02. Keep the page pinned, so this
6377 * physical address remains valid. We keep a reference
6378 * to it so we can release it later.
6379 */
6380 if (vmx->nested.apic_access_page) /* shouldn't happen */
6381 nested_release_page(vmx->nested.apic_access_page);
6382 vmx->nested.apic_access_page =
6383 nested_get_page(vcpu, vmcs12->apic_access_addr);
6384 /*
6385 * If translation failed, no matter: This feature asks
6386 * to exit when accessing the given address, and if it
6387 * can never be accessed, this feature won't do
6388 * anything anyway.
6389 */
6390 if (!vmx->nested.apic_access_page)
6391 exec_control &=
6392 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6393 else
6394 vmcs_write64(APIC_ACCESS_ADDR,
6395 page_to_phys(vmx->nested.apic_access_page));
6396 }
6397
6398 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6399 }
6400
6401
6402 /*
6403 * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6404 * Some constant fields are set here by vmx_set_constant_host_state().
6405 * Other fields are different per CPU, and will be set later when
6406 * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6407 */
6408 vmx_set_constant_host_state();
6409
6410 /*
6411 * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6412 * entry, but only if the current (host) sp changed from the value
6413 * we wrote last (vmx->host_rsp). This cache is no longer relevant
6414 * if we switch vmcs, and rather than hold a separate cache per vmcs,
6415 * here we just force the write to happen on entry.
6416 */
6417 vmx->host_rsp = 0;
6418
6419 exec_control = vmx_exec_control(vmx); /* L0's desires */
6420 exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6421 exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6422 exec_control &= ~CPU_BASED_TPR_SHADOW;
6423 exec_control |= vmcs12->cpu_based_vm_exec_control;
6424 /*
6425 * Merging of IO and MSR bitmaps not currently supported.
6426 * Rather, exit every time.
6427 */
6428 exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6429 exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6430 exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6431
6432 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6433
6434 /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6435 * bitwise-or of what L1 wants to trap for L2, and what we want to
6436 * trap. Note that CR0.TS also needs updating - we do this later.
6437 */
6438 update_exception_bitmap(vcpu);
6439 vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6440 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6441
6442 /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6443 vmcs_write32(VM_EXIT_CONTROLS,
6444 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6445 vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6446 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6447
6448 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6449 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6450 else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6451 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6452
6453
6454 set_cr4_guest_host_mask(vmx);
6455
6456 vmcs_write64(TSC_OFFSET,
6457 vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6458
6459 if (enable_vpid) {
6460 /*
6461 * Trivially support vpid by letting L2s share their parent
6462 * L1's vpid. TODO: move to a more elaborate solution, giving
6463 * each L2 its own vpid and exposing the vpid feature to L1.
6464 */
6465 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6466 vmx_flush_tlb(vcpu);
6467 }
6468
6469 if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6470 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6471 if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6472 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6473 else
6474 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6475 /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6476 vmx_set_efer(vcpu, vcpu->arch.efer);
6477
6478 /*
6479 * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6480 * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6481 * The CR0_READ_SHADOW is what L2 should have expected to read given
6482 * the specifications by L1; It's not enough to take
6483 * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6484 * have more bits than L1 expected.
6485 */
6486 vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6487 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6488
6489 vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6490 vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6491
6492 /* shadow page tables on either EPT or shadow page tables */
6493 kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6494 kvm_mmu_reset_context(vcpu);
6495
6496 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6497 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6498}
6499
cd232ad0
NHE		 6500/*
6501 * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6502 * for running an L2 nested guest.
6503 */
6504static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6505{
6506 struct vmcs12 *vmcs12;
6507 struct vcpu_vmx *vmx = to_vmx(vcpu);
6508 int cpu;
6509 struct loaded_vmcs *vmcs02;
6510
6511 if (!nested_vmx_check_permission(vcpu) ||
6512 !nested_vmx_check_vmcs12(vcpu))
6513 return 1;
6514
6515 skip_emulated_instruction(vcpu);
6516 vmcs12 = get_vmcs12(vcpu);
6517
7c177938
NHE		 6518 /*
6519 * The nested entry process starts with enforcing various prerequisites
6520 * on vmcs12 as required by the Intel SDM, and act appropriately when
6521 * they fail: As the SDM explains, some conditions should cause the
6522 * instruction to fail, while others will cause the instruction to seem
6523 * to succeed, but return an EXIT_REASON_INVALID_STATE.
6524 * To speed up the normal (success) code path, we should avoid checking
6525 * for misconfigurations which will anyway be caught by the processor
6526 * when using the merged vmcs02.
6527 */
6528 if (vmcs12->launch_state == launch) {
6529 nested_vmx_failValid(vcpu,
6530 launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6531 : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6532 return 1;
6533 }
6534
6535 if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6536 !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6537 /*TODO: Also verify bits beyond physical address width are 0*/
6538 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6539 return 1;
6540 }
6541
6542 if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6543 !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6544 /*TODO: Also verify bits beyond physical address width are 0*/
6545 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6546 return 1;
6547 }
6548
6549 if (vmcs12->vm_entry_msr_load_count > 0 ||
6550 vmcs12->vm_exit_msr_load_count > 0 ||
6551 vmcs12->vm_exit_msr_store_count > 0) {
6552 if (printk_ratelimit())
6553 printk(KERN_WARNING
6554 "%s: VMCS MSR_{LOAD,STORE} unsupported\n", __func__);
6555 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6556 return 1;
6557 }
6558
6559 if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6560 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6561 !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6562 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6563 !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6564 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6565 !vmx_control_verify(vmcs12->vm_exit_controls,
6566 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6567 !vmx_control_verify(vmcs12->vm_entry_controls,
6568 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6569 {
6570 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6571 return 1;
6572 }
6573
6574 if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6575 ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6576 nested_vmx_failValid(vcpu,
6577 VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6578 return 1;
6579 }
6580
6581 if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6582 ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6583 nested_vmx_entry_failure(vcpu, vmcs12,
6584 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6585 return 1;
6586 }
6587 if (vmcs12->vmcs_link_pointer != -1ull) {
6588 nested_vmx_entry_failure(vcpu, vmcs12,
6589 EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6590 return 1;
6591 }
6592
6593 /*
6594 * We're finally done with prerequisite checking, and can start with
6595 * the nested entry.
6596 */
6597
cd232ad0
NHE		 6598 vmcs02 = nested_get_current_vmcs02(vmx);
6599 if (!vmcs02)
6600 return -ENOMEM;
6601
6602 enter_guest_mode(vcpu);
6603
6604 vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6605
6606 cpu = get_cpu();
6607 vmx->loaded_vmcs = vmcs02;
6608 vmx_vcpu_put(vcpu);
6609 vmx_vcpu_load(vcpu, cpu);
6610 vcpu->cpu = cpu;
6611 put_cpu();
6612
6613 vmcs12->launch_state = 1;
6614
6615 prepare_vmcs02(vcpu, vmcs12);
6616
6617 /*
6618 * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6619 * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6620 * returned as far as L1 is concerned. It will only return (and set
6621 * the success flag) when L2 exits (see nested_vmx_vmexit()).
6622 */
6623 return 1;
6624}
6625
4704d0be
NHE		 6626/*
6627 * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6628 * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6629 * This function returns the new value we should put in vmcs12.guest_cr0.
6630 * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6631 * 1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6632 * available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6633 * didn't trap the bit, because if L1 did, so would L0).
6634 * 2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6635 * been modified by L2, and L1 knows it. So just leave the old value of
6636 * the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6637 * isn't relevant, because if L0 traps this bit it can set it to anything.
6638 * 3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6639 * changed these bits, and therefore they need to be updated, but L0
6640 * didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6641 * put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6642 */
6643static inline unsigned long
6644vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6645{
6646 return
6647 /*1*/ (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6648 /*2*/ (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6649 /*3*/ (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6650 vcpu->arch.cr0_guest_owned_bits));
6651}
6652
6653static inline unsigned long
6654vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6655{
6656 return
6657 /*1*/ (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6658 /*2*/ (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6659 /*3*/ (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6660 vcpu->arch.cr4_guest_owned_bits));
6661}
6662
6663/*
6664 * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6665 * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6666 * and this function updates it to reflect the changes to the guest state while
6667 * L2 was running (and perhaps made some exits which were handled directly by L0
6668 * without going back to L1), and to reflect the exit reason.
6669 * Note that we do not have to copy here all VMCS fields, just those that
6670 * could have changed by the L2 guest or the exit - i.e., the guest-state and
6671 * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6672 * which already writes to vmcs12 directly.
6673 */
6674void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6675{
6676 /* update guest state fields: */
6677 vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
6678 vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
6679
6680 kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
6681 vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6682 vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
6683 vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
6684
6685 vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
6686 vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
6687 vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
6688 vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
6689 vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
6690 vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
6691 vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
6692 vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
6693 vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
6694 vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
6695 vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
6696 vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
6697 vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
6698 vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
6699 vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
6700 vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
6701 vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
6702 vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
6703 vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
6704 vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
6705 vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
6706 vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
6707 vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
6708 vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
6709 vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
6710 vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
6711 vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
6712 vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
6713 vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
6714 vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
6715 vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
6716 vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
6717 vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
6718 vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
6719 vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
6720 vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
6721
6722 vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
6723 vmcs12->guest_interruptibility_info =
6724 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
6725 vmcs12->guest_pending_dbg_exceptions =
6726 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
6727
6728 /* TODO: These cannot have changed unless we have MSR bitmaps and
6729 * the relevant bit asks not to trap the change */
6730 vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
6731 if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
6732 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
6733 vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
6734 vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
6735 vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
6736
6737 /* update exit information fields: */
6738
6739 vmcs12->vm_exit_reason = vmcs_read32(VM_EXIT_REASON);
6740 vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6741
6742 vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6743 vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6744 vmcs12->idt_vectoring_info_field =
6745 vmcs_read32(IDT_VECTORING_INFO_FIELD);
6746 vmcs12->idt_vectoring_error_code =
6747 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6748 vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6749 vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6750
6751 /* clear vm-entry fields which are to be cleared on exit */
6752 if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6753 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
6754}
6755
6756/*
6757 * A part of what we need to when the nested L2 guest exits and we want to
6758 * run its L1 parent, is to reset L1's guest state to the host state specified
6759 * in vmcs12.
6760 * This function is to be called not only on normal nested exit, but also on
6761 * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
6762 * Failures During or After Loading Guest State").
6763 * This function should be called when the active VMCS is L1's (vmcs01).
6764 */
6765void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6766{
6767 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
6768 vcpu->arch.efer = vmcs12->host_ia32_efer;
6769 if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
6770 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6771 else
6772 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6773 vmx_set_efer(vcpu, vcpu->arch.efer);
6774
6775 kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
6776 kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
6777 /*
6778 * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
6779 * actually changed, because it depends on the current state of
6780 * fpu_active (which may have changed).
6781 * Note that vmx_set_cr0 refers to efer set above.
6782 */
6783 kvm_set_cr0(vcpu, vmcs12->host_cr0);
6784 /*
6785 * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
6786 * to apply the same changes to L1's vmcs. We just set cr0 correctly,
6787 * but we also need to update cr0_guest_host_mask and exception_bitmap.
6788 */
6789 update_exception_bitmap(vcpu);
6790 vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
6791 vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6792
6793 /*
6794 * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
6795 * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
6796 */
6797 vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
6798 kvm_set_cr4(vcpu, vmcs12->host_cr4);
6799
6800 /* shadow page tables on either EPT or shadow page tables */
6801 kvm_set_cr3(vcpu, vmcs12->host_cr3);
6802 kvm_mmu_reset_context(vcpu);
6803
6804 if (enable_vpid) {
6805 /*
6806 * Trivially support vpid by letting L2s share their parent
6807 * L1's vpid. TODO: move to a more elaborate solution, giving
6808 * each L2 its own vpid and exposing the vpid feature to L1.
6809 */
6810 vmx_flush_tlb(vcpu);
6811 }
6812
6813
6814 vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
6815 vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
6816 vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
6817 vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
6818 vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
6819 vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
6820 vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
6821 vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
6822 vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
6823 vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
6824 vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
6825 vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
6826 vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
6827 vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
6828 vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
6829
6830 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
6831 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
6832 if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
6833 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
6834 vmcs12->host_ia32_perf_global_ctrl);
6835}
6836
6837/*
6838 * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
6839 * and modify vmcs12 to make it see what it would expect to see there if
6840 * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
6841 */
6842static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
6843{
6844 struct vcpu_vmx *vmx = to_vmx(vcpu);
6845 int cpu;
6846 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6847
6848 leave_guest_mode(vcpu);
6849 prepare_vmcs12(vcpu, vmcs12);
6850
6851 cpu = get_cpu();
6852 vmx->loaded_vmcs = &vmx->vmcs01;
6853 vmx_vcpu_put(vcpu);
6854 vmx_vcpu_load(vcpu, cpu);
6855 vcpu->cpu = cpu;
6856 put_cpu();
6857
6858 /* if no vmcs02 cache requested, remove the one we used */
6859 if (VMCS02_POOL_SIZE == 0)
6860 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
6861
6862 load_vmcs12_host_state(vcpu, vmcs12);
6863
6864 /* Update TSC_OFFSET if vmx_adjust_tsc_offset() was used while L2 ran */
6865 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
6866
6867 /* This is needed for same reason as it was needed in prepare_vmcs02 */
6868 vmx->host_rsp = 0;
6869
6870 /* Unpin physical memory we referred to in vmcs02 */
6871 if (vmx->nested.apic_access_page) {
6872 nested_release_page(vmx->nested.apic_access_page);
6873 vmx->nested.apic_access_page = 0;
6874 }
6875
6876 /*
6877 * Exiting from L2 to L1, we're now back to L1 which thinks it just
6878 * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
6879 * success or failure flag accordingly.
6880 */
6881 if (unlikely(vmx->fail)) {
6882 vmx->fail = 0;
6883 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
6884 } else
6885 nested_vmx_succeed(vcpu);
6886}
6887
7c177938
NHE		 6888/*
6889 * L1's failure to enter L2 is a subset of a normal exit, as explained in
6890 * 23.7 "VM-entry failures during or after loading guest state" (this also
6891 * lists the acceptable exit-reason and exit-qualification parameters).
6892 * It should only be called before L2 actually succeeded to run, and when
6893 * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
6894 */
6895static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
6896 struct vmcs12 *vmcs12,
6897 u32 reason, unsigned long qualification)
6898{
6899 load_vmcs12_host_state(vcpu, vmcs12);
6900 vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
6901 vmcs12->exit_qualification = qualification;
6902 nested_vmx_succeed(vcpu);
6903}
6904
8a76d7f2
JR		 6905static int vmx_check_intercept(struct kvm_vcpu *vcpu,
6906 struct x86_instruction_info *info,
6907 enum x86_intercept_stage stage)
6908{
6909 return X86EMUL_CONTINUE;
6910}
6911
cbdd1bea 6912static struct kvm_x86_ops vmx_x86_ops = {
6aa8b732
AK		 6913 .cpu_has_kvm_support = cpu_has_kvm_support,
6914 .disabled_by_bios = vmx_disabled_by_bios,
6915 .hardware_setup = hardware_setup,
6916 .hardware_unsetup = hardware_unsetup,
002c7f7c 6917 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 6918 .hardware_enable = hardware_enable,
6919 .hardware_disable = hardware_disable,
04547156 6920 .cpu_has_accelerated_tpr = report_flexpriority,
6aa8b732
AK		 6921
6922 .vcpu_create = vmx_create_vcpu,
6923 .vcpu_free = vmx_free_vcpu,
04d2cc77 6924 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 6925
04d2cc77 6926 .prepare_guest_switch = vmx_save_host_state,
6aa8b732
AK		 6927 .vcpu_load = vmx_vcpu_load,
6928 .vcpu_put = vmx_vcpu_put,
6929
6930 .set_guest_debug = set_guest_debug,
6931 .get_msr = vmx_get_msr,
6932 .set_msr = vmx_set_msr,
6933 .get_segment_base = vmx_get_segment_base,
6934 .get_segment = vmx_get_segment,
6935 .set_segment = vmx_set_segment,
2e4d2653 6936 .get_cpl = vmx_get_cpl,
6aa8b732 6937 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 6938 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 6939 .decache_cr3 = vmx_decache_cr3,
25c4c276 6940 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 6941 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 6942 .set_cr3 = vmx_set_cr3,
6943 .set_cr4 = vmx_set_cr4,
6aa8b732 6944 .set_efer = vmx_set_efer,
6aa8b732
AK		 6945 .get_idt = vmx_get_idt,
6946 .set_idt = vmx_set_idt,
6947 .get_gdt = vmx_get_gdt,
6948 .set_gdt = vmx_set_gdt,
020df079 6949 .set_dr7 = vmx_set_dr7,
5fdbf976 6950 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 6951 .get_rflags = vmx_get_rflags,
6952 .set_rflags = vmx_set_rflags,
ebcbab4c 6953 .fpu_activate = vmx_fpu_activate,
02daab21 6954 .fpu_deactivate = vmx_fpu_deactivate,
6aa8b732
AK		 6955
6956 .tlb_flush = vmx_flush_tlb,
6aa8b732 6957
6aa8b732 6958 .run = vmx_vcpu_run,
6062d012 6959 .handle_exit = vmx_handle_exit,
6aa8b732 6960 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 6961 .set_interrupt_shadow = vmx_set_interrupt_shadow,
6962 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 6963 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 6964 .set_irq = vmx_inject_irq,
95ba8273 6965 .set_nmi = vmx_inject_nmi,
298101da 6966 .queue_exception = vmx_queue_exception,
b463a6f7 6967 .cancel_injection = vmx_cancel_injection,
78646121 6968 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 6969 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 6970 .get_nmi_mask = vmx_get_nmi_mask,
6971 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 6972 .enable_nmi_window = enable_nmi_window,
6973 .enable_irq_window = enable_irq_window,
6974 .update_cr8_intercept = update_cr8_intercept,
95ba8273 6975
cbc94022 6976 .set_tss_addr = vmx_set_tss_addr,
67253af5 6977 .get_tdp_level = get_ept_level,
4b12f0de 6978 .get_mt_mask = vmx_get_mt_mask,
229456fc 6979
586f9607 6980 .get_exit_info = vmx_get_exit_info,
229456fc 6981 .exit_reasons_str = vmx_exit_reasons_str,
586f9607 6982
17cc3935 6983 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 6984
6985 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 6986
6987 .rdtscp_supported = vmx_rdtscp_supported,
d4330ef2
JR		 6988
6989 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 6990
6991 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 6992
4051b188 6993 .set_tsc_khz = vmx_set_tsc_khz,
99e3e30a 6994 .write_tsc_offset = vmx_write_tsc_offset,
e48672fa 6995 .adjust_tsc_offset = vmx_adjust_tsc_offset,
857e4099 6996 .compute_tsc_offset = vmx_compute_tsc_offset,
1c97f0a0
JR		 6997
6998 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 6999
7000 .check_intercept = vmx_check_intercept,
6aa8b732
AK		 7001};
7002
7003static int __init vmx_init(void)
7004{
26bb0981
AK		 7005 int r, i;
7006
7007 rdmsrl_safe(MSR_EFER, &host_efer);
7008
7009 for (i = 0; i < NR_VMX_MSR; ++i)
7010 kvm_define_shared_msr(i, vmx_msr_index[i]);
fdef3ad1 7011
3e7c73e9 7012 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7013 if (!vmx_io_bitmap_a)
7014 return -ENOMEM;
7015
3e7c73e9 7016 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
fdef3ad1
HQ		 7017 if (!vmx_io_bitmap_b) {
7018 r = -ENOMEM;
7019 goto out;
7020 }
7021
5897297b
AK		 7022 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7023 if (!vmx_msr_bitmap_legacy) {
25c5f225
SY		 7024 r = -ENOMEM;
7025 goto out1;
7026 }
7027
5897297b
AK		 7028 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7029 if (!vmx_msr_bitmap_longmode) {
7030 r = -ENOMEM;
7031 goto out2;
7032 }
7033
fdef3ad1
HQ		 7034 /*
7035 * Allow direct access to the PC debug port (it is often used for I/O
7036 * delays, but the vmexits simply slow things down).
7037 */
3e7c73e9
AK		 7038 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7039 clear_bit(0x80, vmx_io_bitmap_a);
fdef3ad1 7040
3e7c73e9 7041 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
fdef3ad1 7042
5897297b
AK		 7043 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7044 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
25c5f225 7045
2384d2b3
SY		 7046 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7047
0ee75bea
AK		 7048 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7049 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 7050 if (r)
5897297b 7051 goto out3;
25c5f225 7052
5897297b
AK		 7053 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7054 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7055 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7056 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7057 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7058 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
fdef3ad1 7059
089d034e 7060 if (enable_ept) {
1439442c 7061 bypass_guest_pf = 0;
534e38b4 7062 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4b12f0de 7063 VMX_EPT_EXECUTABLE_MASK);
5fdbcb9d
SY		 7064 kvm_enable_tdp();
7065 } else
7066 kvm_disable_tdp();
1439442c 7067
c7addb90
AK		 7068 if (bypass_guest_pf)
7069 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
7070
fdef3ad1
HQ		 7071 return 0;
7072
5897297b
AK		 7073out3:
7074 free_page((unsigned long)vmx_msr_bitmap_longmode);
25c5f225 7075out2:
5897297b 7076 free_page((unsigned long)vmx_msr_bitmap_legacy);
fdef3ad1 7077out1:
3e7c73e9 7078 free_page((unsigned long)vmx_io_bitmap_b);
fdef3ad1 7079out:
3e7c73e9 7080 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7081 return r;
6aa8b732
AK		 7082}
7083
7084static void __exit vmx_exit(void)
7085{
5897297b
AK		 7086 free_page((unsigned long)vmx_msr_bitmap_legacy);
7087 free_page((unsigned long)vmx_msr_bitmap_longmode);
3e7c73e9
AK		 7088 free_page((unsigned long)vmx_io_bitmap_b);
7089 free_page((unsigned long)vmx_io_bitmap_a);
fdef3ad1 7090
cb498ea2 7091 kvm_exit();
6aa8b732
AK		 7092}
7093
7094module_init(vmx_init)
7095module_exit(vmx_exit)
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