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KVM: x86: add MSR_IA32_BNDCFGS to msrs_to_save
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 90
97896d04 91struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 92EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 93
476bc001
RR		 94static bool ignore_msrs = 0;
95module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 96
9ed96e87
MT		 97unsigned int min_timer_period_us = 500;
98module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
99
92a1f12d
JR		 100bool kvm_has_tsc_control;
101EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
102u32 kvm_max_guest_tsc_khz;
103EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
104
cc578287
ZA		 105/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
106static u32 tsc_tolerance_ppm = 250;
107module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
108
18863bdd
AK		 109#define KVM_NR_SHARED_MSRS 16
110
111struct kvm_shared_msrs_global {
112 int nr;
2bf78fa7 113 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 114};
115
116struct kvm_shared_msrs {
117 struct user_return_notifier urn;
118 bool registered;
2bf78fa7
SY		 119 struct kvm_shared_msr_values {
120 u64 host;
121 u64 curr;
122 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 123};
124
125static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 126static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 127
417bc304 128struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 129 { "pf_fixed", VCPU_STAT(pf_fixed) },
130 { "pf_guest", VCPU_STAT(pf_guest) },
131 { "tlb_flush", VCPU_STAT(tlb_flush) },
132 { "invlpg", VCPU_STAT(invlpg) },
133 { "exits", VCPU_STAT(exits) },
134 { "io_exits", VCPU_STAT(io_exits) },
135 { "mmio_exits", VCPU_STAT(mmio_exits) },
136 { "signal_exits", VCPU_STAT(signal_exits) },
137 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 138 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 139 { "halt_exits", VCPU_STAT(halt_exits) },
140 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 141 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 142 { "request_irq", VCPU_STAT(request_irq_exits) },
143 { "irq_exits", VCPU_STAT(irq_exits) },
144 { "host_state_reload", VCPU_STAT(host_state_reload) },
145 { "efer_reload", VCPU_STAT(efer_reload) },
146 { "fpu_reload", VCPU_STAT(fpu_reload) },
147 { "insn_emulation", VCPU_STAT(insn_emulation) },
148 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 149 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 150 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 151 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
152 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
153 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
154 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
155 { "mmu_flooded", VM_STAT(mmu_flooded) },
156 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 157 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 158 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 159 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 160 { "largepages", VM_STAT(lpages) },
417bc304
HB		 161 { NULL }
162};
163
2acf923e
DC		 164u64 __read_mostly host_xcr0;
165
b6785def 166static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 167
af585b92
GN		 168static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
169{
170 int i;
171 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
172 vcpu->arch.apf.gfns[i] = ~0;
173}
174
18863bdd
AK		 175static void kvm_on_user_return(struct user_return_notifier *urn)
176{
177 unsigned slot;
18863bdd
AK		 178 struct kvm_shared_msrs *locals
179 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 180 struct kvm_shared_msr_values *values;
18863bdd
AK		 181
182 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 183 values = &locals->values[slot];
184 if (values->host != values->curr) {
185 wrmsrl(shared_msrs_global.msrs[slot], values->host);
186 values->curr = values->host;
18863bdd
AK		 187 }
188 }
189 locals->registered = false;
190 user_return_notifier_unregister(urn);
191}
192
2bf78fa7 193static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 194{
18863bdd 195 u64 value;
013f6a5d
MT		 196 unsigned int cpu = smp_processor_id();
197 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 198
2bf78fa7
SY		 199 /* only read, and nobody should modify it at this time,
200 * so don't need lock */
201 if (slot >= shared_msrs_global.nr) {
202 printk(KERN_ERR "kvm: invalid MSR slot!");
203 return;
204 }
205 rdmsrl_safe(msr, &value);
206 smsr->values[slot].host = value;
207 smsr->values[slot].curr = value;
208}
209
210void kvm_define_shared_msr(unsigned slot, u32 msr)
211{
18863bdd
AK		 212 if (slot >= shared_msrs_global.nr)
213 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 214 shared_msrs_global.msrs[slot] = msr;
215 /* we need ensured the shared_msr_global have been updated */
216 smp_wmb();
18863bdd
AK		 217}
218EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
219
220static void kvm_shared_msr_cpu_online(void)
221{
222 unsigned i;
18863bdd
AK		 223
224 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 225 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 226}
227
d5696725 228void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 229{
013f6a5d
MT		 230 unsigned int cpu = smp_processor_id();
231 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 232
2bf78fa7 233 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 234 return;
2bf78fa7
SY		 235 smsr->values[slot].curr = value;
236 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 237 if (!smsr->registered) {
238 smsr->urn.on_user_return = kvm_on_user_return;
239 user_return_notifier_register(&smsr->urn);
240 smsr->registered = true;
241 }
242}
243EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
244
3548bab5
AK		 245static void drop_user_return_notifiers(void *ignore)
246{
013f6a5d
MT		 247 unsigned int cpu = smp_processor_id();
248 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 249
250 if (smsr->registered)
251 kvm_on_user_return(&smsr->urn);
252}
253
6866b83e
CO		 254u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
255{
8a5a87d9 256 return vcpu->arch.apic_base;
6866b83e
CO		 257}
258EXPORT_SYMBOL_GPL(kvm_get_apic_base);
259
58cb628d
JK		 260int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
261{
262 u64 old_state = vcpu->arch.apic_base &
263 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
264 u64 new_state = msr_info->data &
265 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
266 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
267 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
268
269 if (!msr_info->host_initiated &&
270 ((msr_info->data & reserved_bits) != 0 ||
271 new_state == X2APIC_ENABLE ||
272 (new_state == MSR_IA32_APICBASE_ENABLE &&
273 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
274 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
275 old_state == 0)))
276 return 1;
277
278 kvm_lapic_set_base(vcpu, msr_info->data);
279 return 0;
6866b83e
CO		 280}
281EXPORT_SYMBOL_GPL(kvm_set_apic_base);
282
e3ba45b8
GL		 283asmlinkage void kvm_spurious_fault(void)
284{
285 /* Fault while not rebooting. We want the trace. */
286 BUG();
287}
288EXPORT_SYMBOL_GPL(kvm_spurious_fault);
289
3fd28fce
ED		 290#define EXCPT_BENIGN 0
291#define EXCPT_CONTRIBUTORY 1
292#define EXCPT_PF 2
293
294static int exception_class(int vector)
295{
296 switch (vector) {
297 case PF_VECTOR:
298 return EXCPT_PF;
299 case DE_VECTOR:
300 case TS_VECTOR:
301 case NP_VECTOR:
302 case SS_VECTOR:
303 case GP_VECTOR:
304 return EXCPT_CONTRIBUTORY;
305 default:
306 break;
307 }
308 return EXCPT_BENIGN;
309}
310
311static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 312 unsigned nr, bool has_error, u32 error_code,
313 bool reinject)
3fd28fce
ED		 314{
315 u32 prev_nr;
316 int class1, class2;
317
3842d135
AK		 318 kvm_make_request(KVM_REQ_EVENT, vcpu);
319
3fd28fce
ED		 320 if (!vcpu->arch.exception.pending) {
321 queue:
322 vcpu->arch.exception.pending = true;
323 vcpu->arch.exception.has_error_code = has_error;
324 vcpu->arch.exception.nr = nr;
325 vcpu->arch.exception.error_code = error_code;
3f0fd292 326 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 327 return;
328 }
329
330 /* to check exception */
331 prev_nr = vcpu->arch.exception.nr;
332 if (prev_nr == DF_VECTOR) {
333 /* triple fault -> shutdown */
a8eeb04a 334 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 335 return;
336 }
337 class1 = exception_class(prev_nr);
338 class2 = exception_class(nr);
339 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
340 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
341 /* generate double fault per SDM Table 5-5 */
342 vcpu->arch.exception.pending = true;
343 vcpu->arch.exception.has_error_code = true;
344 vcpu->arch.exception.nr = DF_VECTOR;
345 vcpu->arch.exception.error_code = 0;
346 } else
347 /* replace previous exception with a new one in a hope
348 that instruction re-execution will regenerate lost
349 exception */
350 goto queue;
351}
352
298101da
AK		 353void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
354{
ce7ddec4 355 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 356}
357EXPORT_SYMBOL_GPL(kvm_queue_exception);
358
ce7ddec4
JR		 359void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
360{
361 kvm_multiple_exception(vcpu, nr, false, 0, true);
362}
363EXPORT_SYMBOL_GPL(kvm_requeue_exception);
364
db8fcefa 365void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 366{
db8fcefa
AP		 367 if (err)
368 kvm_inject_gp(vcpu, 0);
369 else
370 kvm_x86_ops->skip_emulated_instruction(vcpu);
371}
372EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 373
6389ee94 374void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 375{
376 ++vcpu->stat.pf_guest;
6389ee94
AK		 377 vcpu->arch.cr2 = fault->address;
378 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 379}
27d6c865 380EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 381
6389ee94 382void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 383{
6389ee94
AK		 384 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
385 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 386 else
6389ee94 387 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 388}
389
3419ffc8
SY		 390void kvm_inject_nmi(struct kvm_vcpu *vcpu)
391{
7460fb4a
AK		 392 atomic_inc(&vcpu->arch.nmi_queued);
393 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 394}
395EXPORT_SYMBOL_GPL(kvm_inject_nmi);
396
298101da
AK		 397void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
398{
ce7ddec4 399 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 400}
401EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
402
ce7ddec4
JR		 403void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
404{
405 kvm_multiple_exception(vcpu, nr, true, error_code, true);
406}
407EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
408
0a79b009
AK		 409/*
410 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
411 * a #GP and return false.
412 */
413bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 414{
0a79b009
AK		 415 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
416 return true;
417 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
418 return false;
298101da 419}
0a79b009 420EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 421
ec92fe44
JR		 422/*
423 * This function will be used to read from the physical memory of the currently
424 * running guest. The difference to kvm_read_guest_page is that this function
425 * can read from guest physical or from the guest's guest physical memory.
426 */
427int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
428 gfn_t ngfn, void *data, int offset, int len,
429 u32 access)
430{
431 gfn_t real_gfn;
432 gpa_t ngpa;
433
434 ngpa = gfn_to_gpa(ngfn);
435 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
436 if (real_gfn == UNMAPPED_GVA)
437 return -EFAULT;
438
439 real_gfn = gpa_to_gfn(real_gfn);
440
441 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
442}
443EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
444
3d06b8bf
JR		 445int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
446 void *data, int offset, int len, u32 access)
447{
448 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
449 data, offset, len, access);
450}
451
a03490ed
CO		 452/*
453 * Load the pae pdptrs. Return true is they are all valid.
454 */
ff03a073 455int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 456{
457 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
458 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
459 int i;
460 int ret;
ff03a073 461 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 462
ff03a073
JR		 463 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
464 offset * sizeof(u64), sizeof(pdpte),
465 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 466 if (ret < 0) {
467 ret = 0;
468 goto out;
469 }
470 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 471 if (is_present_gpte(pdpte[i]) &&
20c466b5 472 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 473 ret = 0;
474 goto out;
475 }
476 }
477 ret = 1;
478
ff03a073 479 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 480 __set_bit(VCPU_EXREG_PDPTR,
481 (unsigned long *)&vcpu->arch.regs_avail);
482 __set_bit(VCPU_EXREG_PDPTR,
483 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 484out:
a03490ed
CO		 485
486 return ret;
487}
cc4b6871 488EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 489
d835dfec
AK		 490static bool pdptrs_changed(struct kvm_vcpu *vcpu)
491{
ff03a073 492 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 493 bool changed = true;
3d06b8bf
JR		 494 int offset;
495 gfn_t gfn;
d835dfec
AK		 496 int r;
497
498 if (is_long_mode(vcpu) || !is_pae(vcpu))
499 return false;
500
6de4f3ad
AK		 501 if (!test_bit(VCPU_EXREG_PDPTR,
502 (unsigned long *)&vcpu->arch.regs_avail))
503 return true;
504
9f8fe504
AK		 505 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
506 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 507 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
508 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 509 if (r < 0)
510 goto out;
ff03a073 511 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 512out:
d835dfec
AK		 513
514 return changed;
515}
516
49a9b07e 517int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 518{
aad82703
SY		 519 unsigned long old_cr0 = kvm_read_cr0(vcpu);
520 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
521 X86_CR0_CD | X86_CR0_NW;
522
f9a48e6a
AK		 523 cr0 |= X86_CR0_ET;
524
ab344828 525#ifdef CONFIG_X86_64
0f12244f
GN		 526 if (cr0 & 0xffffffff00000000UL)
527 return 1;
ab344828
GN		 528#endif
529
530 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 531
0f12244f
GN		 532 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
533 return 1;
a03490ed 534
0f12244f
GN		 535 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
536 return 1;
a03490ed
CO		 537
538 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
539#ifdef CONFIG_X86_64
f6801dff 540 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 541 int cs_db, cs_l;
542
0f12244f
GN		 543 if (!is_pae(vcpu))
544 return 1;
a03490ed 545 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 546 if (cs_l)
547 return 1;
a03490ed
CO		 548 } else
549#endif
ff03a073 550 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 551 kvm_read_cr3(vcpu)))
0f12244f 552 return 1;
a03490ed
CO		 553 }
554
ad756a16
MJ		 555 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
556 return 1;
557
a03490ed 558 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 559
d170c419 560 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 561 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 562 kvm_async_pf_hash_reset(vcpu);
563 }
e5f3f027 564
aad82703
SY		 565 if ((cr0 ^ old_cr0) & update_bits)
566 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 567 return 0;
568}
2d3ad1f4 569EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 570
2d3ad1f4 571void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 572{
49a9b07e 573 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 574}
2d3ad1f4 575EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 576
42bdf991
MT		 577static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
578{
579 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
580 !vcpu->guest_xcr0_loaded) {
581 /* kvm_set_xcr() also depends on this */
582 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
583 vcpu->guest_xcr0_loaded = 1;
584 }
585}
586
587static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
588{
589 if (vcpu->guest_xcr0_loaded) {
590 if (vcpu->arch.xcr0 != host_xcr0)
591 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
592 vcpu->guest_xcr0_loaded = 0;
593 }
594}
595
2acf923e
DC		 596int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
597{
56c103ec
LJ		 598 u64 xcr0 = xcr;
599 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 600 u64 valid_bits;
2acf923e
DC		 601
602 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
603 if (index != XCR_XFEATURE_ENABLED_MASK)
604 return 1;
2acf923e
DC		 605 if (!(xcr0 & XSTATE_FP))
606 return 1;
607 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
608 return 1;
46c34cb0
PB		 609
610 /*
611 * Do not allow the guest to set bits that we do not support
612 * saving. However, xcr0 bit 0 is always set, even if the
613 * emulated CPU does not support XSAVE (see fx_init).
614 */
615 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
616 if (xcr0 & ~valid_bits)
2acf923e 617 return 1;
46c34cb0 618
42bdf991 619 kvm_put_guest_xcr0(vcpu);
2acf923e 620 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 621
622 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
623 kvm_update_cpuid(vcpu);
2acf923e
DC		 624 return 0;
625}
626
627int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
628{
764bcbc5
Z		 629 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
630 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 631 kvm_inject_gp(vcpu, 0);
632 return 1;
633 }
634 return 0;
635}
636EXPORT_SYMBOL_GPL(kvm_set_xcr);
637
a83b29c6 638int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 639{
fc78f519 640 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 641 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
642 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 643 if (cr4 & CR4_RESERVED_BITS)
644 return 1;
a03490ed 645
2acf923e
DC		 646 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
647 return 1;
648
c68b734f
YW		 649 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
650 return 1;
651
afcbf13f 652 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 653 return 1;
654
a03490ed 655 if (is_long_mode(vcpu)) {
0f12244f
GN		 656 if (!(cr4 & X86_CR4_PAE))
657 return 1;
a2edf57f
AK		 658 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
659 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 660 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
661 kvm_read_cr3(vcpu)))
0f12244f
GN		 662 return 1;
663
ad756a16
MJ		 664 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
665 if (!guest_cpuid_has_pcid(vcpu))
666 return 1;
667
668 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
669 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
670 return 1;
671 }
672
5e1746d6 673 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 674 return 1;
a03490ed 675
ad756a16
MJ		 676 if (((cr4 ^ old_cr4) & pdptr_bits) ||
677 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 678 kvm_mmu_reset_context(vcpu);
0f12244f 679
2acf923e 680 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 681 kvm_update_cpuid(vcpu);
2acf923e 682
0f12244f
GN		 683 return 0;
684}
2d3ad1f4 685EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 686
2390218b 687int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 688{
9f8fe504 689 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 690 kvm_mmu_sync_roots(vcpu);
d835dfec 691 kvm_mmu_flush_tlb(vcpu);
0f12244f 692 return 0;
d835dfec
AK		 693 }
694
a03490ed 695 if (is_long_mode(vcpu)) {
471842ec 696 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
ad756a16
MJ		 697 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
698 return 1;
699 } else
700 if (cr3 & CR3_L_MODE_RESERVED_BITS)
701 return 1;
a03490ed
CO		 702 } else {
703 if (is_pae(vcpu)) {
0f12244f
GN		 704 if (cr3 & CR3_PAE_RESERVED_BITS)
705 return 1;
ff03a073
JR		 706 if (is_paging(vcpu) &&
707 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 708 return 1;
a03490ed
CO		 709 }
710 /*
711 * We don't check reserved bits in nonpae mode, because
712 * this isn't enforced, and VMware depends on this.
713 */
714 }
715
0f12244f 716 vcpu->arch.cr3 = cr3;
aff48baa 717 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 718 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 719 return 0;
720}
2d3ad1f4 721EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 722
eea1cff9 723int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 724{
0f12244f
GN		 725 if (cr8 & CR8_RESERVED_BITS)
726 return 1;
a03490ed
CO		 727 if (irqchip_in_kernel(vcpu->kvm))
728 kvm_lapic_set_tpr(vcpu, cr8);
729 else
ad312c7c 730 vcpu->arch.cr8 = cr8;
0f12244f
GN		 731 return 0;
732}
2d3ad1f4 733EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 734
2d3ad1f4 735unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 736{
737 if (irqchip_in_kernel(vcpu->kvm))
738 return kvm_lapic_get_cr8(vcpu);
739 else
ad312c7c 740 return vcpu->arch.cr8;
a03490ed 741}
2d3ad1f4 742EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 743
73aaf249
JK		 744static void kvm_update_dr6(struct kvm_vcpu *vcpu)
745{
746 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
747 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
748}
749
c8639010
JK		 750static void kvm_update_dr7(struct kvm_vcpu *vcpu)
751{
752 unsigned long dr7;
753
754 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
755 dr7 = vcpu->arch.guest_debug_dr7;
756 else
757 dr7 = vcpu->arch.dr7;
758 kvm_x86_ops->set_dr7(vcpu, dr7);
759 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
760}
761
338dbc97 762static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 763{
764 switch (dr) {
765 case 0 ... 3:
766 vcpu->arch.db[dr] = val;
767 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
768 vcpu->arch.eff_db[dr] = val;
769 break;
770 case 4:
338dbc97
GN		 771 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
772 return 1; /* #UD */
020df079
GN		 773 /* fall through */
774 case 6:
338dbc97
GN		 775 if (val & 0xffffffff00000000ULL)
776 return -1; /* #GP */
020df079 777 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
73aaf249 778 kvm_update_dr6(vcpu);
020df079
GN		 779 break;
780 case 5:
338dbc97
GN		 781 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
782 return 1; /* #UD */
020df079
GN		 783 /* fall through */
784 default: /* 7 */
338dbc97
GN		 785 if (val & 0xffffffff00000000ULL)
786 return -1; /* #GP */
020df079 787 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 788 kvm_update_dr7(vcpu);
020df079
GN		 789 break;
790 }
791
792 return 0;
793}
338dbc97
GN		 794
795int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
796{
797 int res;
798
799 res = __kvm_set_dr(vcpu, dr, val);
800 if (res > 0)
801 kvm_queue_exception(vcpu, UD_VECTOR);
802 else if (res < 0)
803 kvm_inject_gp(vcpu, 0);
804
805 return res;
806}
020df079
GN		 807EXPORT_SYMBOL_GPL(kvm_set_dr);
808
338dbc97 809static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 810{
811 switch (dr) {
812 case 0 ... 3:
813 *val = vcpu->arch.db[dr];
814 break;
815 case 4:
338dbc97 816 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 817 return 1;
020df079
GN		 818 /* fall through */
819 case 6:
73aaf249
JK		 820 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
821 *val = vcpu->arch.dr6;
822 else
823 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 824 break;
825 case 5:
338dbc97 826 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 827 return 1;
020df079
GN		 828 /* fall through */
829 default: /* 7 */
830 *val = vcpu->arch.dr7;
831 break;
832 }
833
834 return 0;
835}
338dbc97
GN		 836
837int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
838{
839 if (_kvm_get_dr(vcpu, dr, val)) {
840 kvm_queue_exception(vcpu, UD_VECTOR);
841 return 1;
842 }
843 return 0;
844}
020df079
GN		 845EXPORT_SYMBOL_GPL(kvm_get_dr);
846
022cd0e8
AK		 847bool kvm_rdpmc(struct kvm_vcpu *vcpu)
848{
849 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
850 u64 data;
851 int err;
852
853 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
854 if (err)
855 return err;
856 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
857 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
858 return err;
859}
860EXPORT_SYMBOL_GPL(kvm_rdpmc);
861
043405e1
CO		 862/*
863 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
864 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
865 *
866 * This list is modified at module load time to reflect the
e3267cbb
GC		 867 * capabilities of the host cpu. This capabilities test skips MSRs that are
868 * kvm-specific. Those are put in the beginning of the list.
043405e1 869 */
e3267cbb 870
e984097b 871#define KVM_SAVE_MSRS_BEGIN 12
043405e1 872static u32 msrs_to_save[] = {
e3267cbb 873 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 874 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 875 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 876 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 877 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 878 MSR_KVM_PV_EOI_EN,
043405e1 879 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 880 MSR_STAR,
043405e1
CO		 881#ifdef CONFIG_X86_64
882 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
883#endif
b3897a49 884 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 885 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 886};
887
888static unsigned num_msrs_to_save;
889
f1d24831 890static const u32 emulated_msrs[] = {
ba904635 891 MSR_IA32_TSC_ADJUST,
a3e06bbe 892 MSR_IA32_TSCDEADLINE,
043405e1 893 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 894 MSR_IA32_MCG_STATUS,
895 MSR_IA32_MCG_CTL,
043405e1
CO		 896};
897
384bb783 898bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 899{
b69e8cae 900 if (efer & efer_reserved_bits)
384bb783 901 return false;
15c4a640 902
1b2fd70c
AG		 903 if (efer & EFER_FFXSR) {
904 struct kvm_cpuid_entry2 *feat;
905
906 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 907 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 908 return false;
1b2fd70c
AG		 909 }
910
d8017474
AG		 911 if (efer & EFER_SVME) {
912 struct kvm_cpuid_entry2 *feat;
913
914 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 915 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 916 return false;
d8017474
AG		 917 }
918
384bb783
JK		 919 return true;
920}
921EXPORT_SYMBOL_GPL(kvm_valid_efer);
922
923static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
924{
925 u64 old_efer = vcpu->arch.efer;
926
927 if (!kvm_valid_efer(vcpu, efer))
928 return 1;
929
930 if (is_paging(vcpu)
931 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
932 return 1;
933
15c4a640 934 efer &= ~EFER_LMA;
f6801dff 935 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 936
a3d204e2
SY		 937 kvm_x86_ops->set_efer(vcpu, efer);
938
aad82703
SY		 939 /* Update reserved bits */
940 if ((efer ^ old_efer) & EFER_NX)
941 kvm_mmu_reset_context(vcpu);
942
b69e8cae 943 return 0;
15c4a640
CO		 944}
945
f2b4b7dd
JR		 946void kvm_enable_efer_bits(u64 mask)
947{
948 efer_reserved_bits &= ~mask;
949}
950EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
951
952
15c4a640
CO		 953/*
954 * Writes msr value into into the appropriate "register".
955 * Returns 0 on success, non-0 otherwise.
956 * Assumes vcpu_load() was already called.
957 */
8fe8ab46 958int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 959{
8fe8ab46 960 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 961}
962
313a3dc7
CO		 963/*
964 * Adapt set_msr() to msr_io()'s calling convention
965 */
966static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
967{
8fe8ab46
WA		 968 struct msr_data msr;
969
970 msr.data = *data;
971 msr.index = index;
972 msr.host_initiated = true;
973 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 974}
975
16e8d74d
MT		 976#ifdef CONFIG_X86_64
977struct pvclock_gtod_data {
978 seqcount_t seq;
979
980 struct { /* extract of a clocksource struct */
981 int vclock_mode;
982 cycle_t cycle_last;
983 cycle_t mask;
984 u32 mult;
985 u32 shift;
986 } clock;
987
988 /* open coded 'struct timespec' */
989 u64 monotonic_time_snsec;
990 time_t monotonic_time_sec;
991};
992
993static struct pvclock_gtod_data pvclock_gtod_data;
994
995static void update_pvclock_gtod(struct timekeeper *tk)
996{
997 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
998
999 write_seqcount_begin(&vdata->seq);
1000
1001 /* copy pvclock gtod data */
1002 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
1003 vdata->clock.cycle_last = tk->clock->cycle_last;
1004 vdata->clock.mask = tk->clock->mask;
1005 vdata->clock.mult = tk->mult;
1006 vdata->clock.shift = tk->shift;
1007
1008 vdata->monotonic_time_sec = tk->xtime_sec
1009 + tk->wall_to_monotonic.tv_sec;
1010 vdata->monotonic_time_snsec = tk->xtime_nsec
1011 + (tk->wall_to_monotonic.tv_nsec
1012 << tk->shift);
1013 while (vdata->monotonic_time_snsec >=
1014 (((u64)NSEC_PER_SEC) << tk->shift)) {
1015 vdata->monotonic_time_snsec -=
1016 ((u64)NSEC_PER_SEC) << tk->shift;
1017 vdata->monotonic_time_sec++;
1018 }
1019
1020 write_seqcount_end(&vdata->seq);
1021}
1022#endif
1023
1024
18068523
GOC		 1025static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1026{
9ed3c444
AK		 1027 int version;
1028 int r;
50d0a0f9 1029 struct pvclock_wall_clock wc;
923de3cf 1030 struct timespec boot;
18068523
GOC		 1031
1032 if (!wall_clock)
1033 return;
1034
9ed3c444
AK		 1035 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1036 if (r)
1037 return;
1038
1039 if (version & 1)
1040 ++version; /* first time write, random junk */
1041
1042 ++version;
18068523 1043
18068523
GOC		 1044 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1045
50d0a0f9
GH		 1046 /*
1047 * The guest calculates current wall clock time by adding
34c238a1 1048 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1049 * wall clock specified here. guest system time equals host
1050 * system time for us, thus we must fill in host boot time here.
1051 */
923de3cf 1052 getboottime(&boot);
50d0a0f9 1053
4b648665
BR		 1054 if (kvm->arch.kvmclock_offset) {
1055 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1056 boot = timespec_sub(boot, ts);
1057 }
50d0a0f9
GH		 1058 wc.sec = boot.tv_sec;
1059 wc.nsec = boot.tv_nsec;
1060 wc.version = version;
18068523
GOC		 1061
1062 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1063
1064 version++;
1065 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1066}
1067
50d0a0f9
GH		 1068static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1069{
1070 uint32_t quotient, remainder;
1071
1072 /* Don't try to replace with do_div(), this one calculates
1073 * "(dividend << 32) / divisor" */
1074 __asm__ ( "divl %4"
1075 : "=a" (quotient), "=d" (remainder)
1076 : "0" (0), "1" (dividend), "r" (divisor) );
1077 return quotient;
1078}
1079
5f4e3f88
ZA		 1080static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1081 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1082{
5f4e3f88 1083 uint64_t scaled64;
50d0a0f9
GH		 1084 int32_t shift = 0;
1085 uint64_t tps64;
1086 uint32_t tps32;
1087
5f4e3f88
ZA		 1088 tps64 = base_khz * 1000LL;
1089 scaled64 = scaled_khz * 1000LL;
50933623 1090 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1091 tps64 >>= 1;
1092 shift--;
1093 }
1094
1095 tps32 = (uint32_t)tps64;
50933623
JK		 1096 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1097 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1098 scaled64 >>= 1;
1099 else
1100 tps32 <<= 1;
50d0a0f9
GH		 1101 shift++;
1102 }
1103
5f4e3f88
ZA		 1104 *pshift = shift;
1105 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1106
5f4e3f88
ZA		 1107 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1108 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1109}
1110
759379dd
ZA		 1111static inline u64 get_kernel_ns(void)
1112{
1113 struct timespec ts;
1114
1115 WARN_ON(preemptible());
1116 ktime_get_ts(&ts);
1117 monotonic_to_bootbased(&ts);
1118 return timespec_to_ns(&ts);
50d0a0f9
GH		 1119}
1120
d828199e 1121#ifdef CONFIG_X86_64
16e8d74d 1122static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1123#endif
16e8d74d 1124
c8076604 1125static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1126unsigned long max_tsc_khz;
c8076604 1127
cc578287 1128static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1129{
cc578287
ZA		 1130 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1131 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1132}
1133
cc578287 1134static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1135{
cc578287
ZA		 1136 u64 v = (u64)khz * (1000000 + ppm);
1137 do_div(v, 1000000);
1138 return v;
1e993611
JR		 1139}
1140
cc578287 1141static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1142{
cc578287
ZA		 1143 u32 thresh_lo, thresh_hi;
1144 int use_scaling = 0;
217fc9cf 1145
03ba32ca
MT		 1146 /* tsc_khz can be zero if TSC calibration fails */
1147 if (this_tsc_khz == 0)
1148 return;
1149
c285545f
ZA		 1150 /* Compute a scale to convert nanoseconds in TSC cycles */
1151 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1152 &vcpu->arch.virtual_tsc_shift,
1153 &vcpu->arch.virtual_tsc_mult);
1154 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1155
1156 /*
1157 * Compute the variation in TSC rate which is acceptable
1158 * within the range of tolerance and decide if the
1159 * rate being applied is within that bounds of the hardware
1160 * rate. If so, no scaling or compensation need be done.
1161 */
1162 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1163 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1164 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1165 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1166 use_scaling = 1;
1167 }
1168 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1169}
1170
1171static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1172{
e26101b1 1173 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1174 vcpu->arch.virtual_tsc_mult,
1175 vcpu->arch.virtual_tsc_shift);
e26101b1 1176 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1177 return tsc;
1178}
1179
b48aa97e
MT		 1180void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1181{
1182#ifdef CONFIG_X86_64
1183 bool vcpus_matched;
1184 bool do_request = false;
1185 struct kvm_arch *ka = &vcpu->kvm->arch;
1186 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1187
1188 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1189 atomic_read(&vcpu->kvm->online_vcpus));
1190
1191 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1192 if (!ka->use_master_clock)
1193 do_request = 1;
1194
1195 if (!vcpus_matched && ka->use_master_clock)
1196 do_request = 1;
1197
1198 if (do_request)
1199 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1200
1201 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1202 atomic_read(&vcpu->kvm->online_vcpus),
1203 ka->use_master_clock, gtod->clock.vclock_mode);
1204#endif
1205}
1206
ba904635
WA		 1207static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1208{
1209 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1210 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1211}
1212
8fe8ab46 1213void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1214{
1215 struct kvm *kvm = vcpu->kvm;
f38e098f 1216 u64 offset, ns, elapsed;
99e3e30a 1217 unsigned long flags;
02626b6a 1218 s64 usdiff;
b48aa97e 1219 bool matched;
8fe8ab46 1220 u64 data = msr->data;
99e3e30a 1221
038f8c11 1222 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1223 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1224 ns = get_kernel_ns();
f38e098f 1225 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1226
03ba32ca 1227 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1228 int faulted = 0;
1229
03ba32ca
MT		 1230 /* n.b - signed multiplication and division required */
1231 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1232#ifdef CONFIG_X86_64
03ba32ca 1233 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1234#else
03ba32ca 1235 /* do_div() only does unsigned */
8915aa27
MT		 1236 asm("1: idivl %[divisor]\n"
1237 "2: xor %%edx, %%edx\n"
1238 " movl $0, %[faulted]\n"
1239 "3:\n"
1240 ".section .fixup,\"ax\"\n"
1241 "4: movl $1, %[faulted]\n"
1242 " jmp 3b\n"
1243 ".previous\n"
1244
1245 _ASM_EXTABLE(1b, 4b)
1246
1247 : "=A"(usdiff), [faulted] "=r" (faulted)
1248 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1249
5d3cb0f6 1250#endif
03ba32ca
MT		 1251 do_div(elapsed, 1000);
1252 usdiff -= elapsed;
1253 if (usdiff < 0)
1254 usdiff = -usdiff;
8915aa27
MT		 1255
1256 /* idivl overflow => difference is larger than USEC_PER_SEC */
1257 if (faulted)
1258 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1259 } else
1260 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1261
1262 /*
5d3cb0f6
ZA		 1263 * Special case: TSC write with a small delta (1 second) of virtual
1264 * cycle time against real time is interpreted as an attempt to
1265 * synchronize the CPU.
1266 *
1267 * For a reliable TSC, we can match TSC offsets, and for an unstable
1268 * TSC, we add elapsed time in this computation. We could let the
1269 * compensation code attempt to catch up if we fall behind, but
1270 * it's better to try to match offsets from the beginning.
1271 */
02626b6a 1272 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1273 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1274 if (!check_tsc_unstable()) {
e26101b1 1275 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1276 pr_debug("kvm: matched tsc offset for %llu\n", data);
1277 } else {
857e4099 1278 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1279 data += delta;
1280 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1281 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1282 }
b48aa97e 1283 matched = true;
e26101b1
ZA		 1284 } else {
1285 /*
1286 * We split periods of matched TSC writes into generations.
1287 * For each generation, we track the original measured
1288 * nanosecond time, offset, and write, so if TSCs are in
1289 * sync, we can match exact offset, and if not, we can match
4a969980 1290 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1291 *
1292 * These values are tracked in kvm->arch.cur_xxx variables.
1293 */
1294 kvm->arch.cur_tsc_generation++;
1295 kvm->arch.cur_tsc_nsec = ns;
1296 kvm->arch.cur_tsc_write = data;
1297 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1298 matched = false;
e26101b1
ZA		 1299 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1300 kvm->arch.cur_tsc_generation, data);
f38e098f 1301 }
e26101b1
ZA		 1302
1303 /*
1304 * We also track th most recent recorded KHZ, write and time to
1305 * allow the matching interval to be extended at each write.
1306 */
f38e098f
ZA		 1307 kvm->arch.last_tsc_nsec = ns;
1308 kvm->arch.last_tsc_write = data;
5d3cb0f6 1309 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1310
b183aa58 1311 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1312
1313 /* Keep track of which generation this VCPU has synchronized to */
1314 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1315 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1316 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1317
ba904635
WA		 1318 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1319 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1320 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1321 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1322
1323 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1324 if (matched)
1325 kvm->arch.nr_vcpus_matched_tsc++;
1326 else
1327 kvm->arch.nr_vcpus_matched_tsc = 0;
1328
1329 kvm_track_tsc_matching(vcpu);
1330 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1331}
e26101b1 1332
99e3e30a
ZA		 1333EXPORT_SYMBOL_GPL(kvm_write_tsc);
1334
d828199e
MT		 1335#ifdef CONFIG_X86_64
1336
1337static cycle_t read_tsc(void)
1338{
1339 cycle_t ret;
1340 u64 last;
1341
1342 /*
1343 * Empirically, a fence (of type that depends on the CPU)
1344 * before rdtsc is enough to ensure that rdtsc is ordered
1345 * with respect to loads. The various CPU manuals are unclear
1346 * as to whether rdtsc can be reordered with later loads,
1347 * but no one has ever seen it happen.
1348 */
1349 rdtsc_barrier();
1350 ret = (cycle_t)vget_cycles();
1351
1352 last = pvclock_gtod_data.clock.cycle_last;
1353
1354 if (likely(ret >= last))
1355 return ret;
1356
1357 /*
1358 * GCC likes to generate cmov here, but this branch is extremely
1359 * predictable (it's just a funciton of time and the likely is
1360 * very likely) and there's a data dependence, so force GCC
1361 * to generate a branch instead. I don't barrier() because
1362 * we don't actually need a barrier, and if this function
1363 * ever gets inlined it will generate worse code.
1364 */
1365 asm volatile ("");
1366 return last;
1367}
1368
1369static inline u64 vgettsc(cycle_t *cycle_now)
1370{
1371 long v;
1372 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1373
1374 *cycle_now = read_tsc();
1375
1376 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1377 return v * gtod->clock.mult;
1378}
1379
1380static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1381{
1382 unsigned long seq;
1383 u64 ns;
1384 int mode;
1385 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1386
1387 ts->tv_nsec = 0;
1388 do {
1389 seq = read_seqcount_begin(&gtod->seq);
1390 mode = gtod->clock.vclock_mode;
1391 ts->tv_sec = gtod->monotonic_time_sec;
1392 ns = gtod->monotonic_time_snsec;
1393 ns += vgettsc(cycle_now);
1394 ns >>= gtod->clock.shift;
1395 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1396 timespec_add_ns(ts, ns);
1397
1398 return mode;
1399}
1400
1401/* returns true if host is using tsc clocksource */
1402static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1403{
1404 struct timespec ts;
1405
1406 /* checked again under seqlock below */
1407 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1408 return false;
1409
1410 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1411 return false;
1412
1413 monotonic_to_bootbased(&ts);
1414 *kernel_ns = timespec_to_ns(&ts);
1415
1416 return true;
1417}
1418#endif
1419
1420/*
1421 *
b48aa97e
MT		 1422 * Assuming a stable TSC across physical CPUS, and a stable TSC
1423 * across virtual CPUs, the following condition is possible.
1424 * Each numbered line represents an event visible to both
d828199e
MT		 1425 * CPUs at the next numbered event.
1426 *
1427 * "timespecX" represents host monotonic time. "tscX" represents
1428 * RDTSC value.
1429 *
1430 * VCPU0 on CPU0 | VCPU1 on CPU1
1431 *
1432 * 1. read timespec0,tsc0
1433 * 2. | timespec1 = timespec0 + N
1434 * | tsc1 = tsc0 + M
1435 * 3. transition to guest | transition to guest
1436 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1437 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1438 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1439 *
1440 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1441 *
1442 * - ret0 < ret1
1443 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1444 * ...
1445 * - 0 < N - M => M < N
1446 *
1447 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1448 * always the case (the difference between two distinct xtime instances
1449 * might be smaller then the difference between corresponding TSC reads,
1450 * when updating guest vcpus pvclock areas).
1451 *
1452 * To avoid that problem, do not allow visibility of distinct
1453 * system_timestamp/tsc_timestamp values simultaneously: use a master
1454 * copy of host monotonic time values. Update that master copy
1455 * in lockstep.
1456 *
b48aa97e 1457 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1458 *
1459 */
1460
1461static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1462{
1463#ifdef CONFIG_X86_64
1464 struct kvm_arch *ka = &kvm->arch;
1465 int vclock_mode;
b48aa97e
MT		 1466 bool host_tsc_clocksource, vcpus_matched;
1467
1468 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1469 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1470
1471 /*
1472 * If the host uses TSC clock, then passthrough TSC as stable
1473 * to the guest.
1474 */
b48aa97e 1475 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1476 &ka->master_kernel_ns,
1477 &ka->master_cycle_now);
1478
b48aa97e
MT		 1479 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1480
d828199e
MT		 1481 if (ka->use_master_clock)
1482 atomic_set(&kvm_guest_has_master_clock, 1);
1483
1484 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1485 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1486 vcpus_matched);
d828199e
MT		 1487#endif
1488}
1489
2e762ff7
MT		 1490static void kvm_gen_update_masterclock(struct kvm *kvm)
1491{
1492#ifdef CONFIG_X86_64
1493 int i;
1494 struct kvm_vcpu *vcpu;
1495 struct kvm_arch *ka = &kvm->arch;
1496
1497 spin_lock(&ka->pvclock_gtod_sync_lock);
1498 kvm_make_mclock_inprogress_request(kvm);
1499 /* no guest entries from this point */
1500 pvclock_update_vm_gtod_copy(kvm);
1501
1502 kvm_for_each_vcpu(i, vcpu, kvm)
1503 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1504
1505 /* guest entries allowed */
1506 kvm_for_each_vcpu(i, vcpu, kvm)
1507 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1508
1509 spin_unlock(&ka->pvclock_gtod_sync_lock);
1510#endif
1511}
1512
34c238a1 1513static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1514{
d828199e 1515 unsigned long flags, this_tsc_khz;
18068523 1516 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1517 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1518 s64 kernel_ns;
d828199e 1519 u64 tsc_timestamp, host_tsc;
0b79459b 1520 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1521 u8 pvclock_flags;
d828199e
MT		 1522 bool use_master_clock;
1523
1524 kernel_ns = 0;
1525 host_tsc = 0;
18068523 1526
d828199e
MT		 1527 /*
1528 * If the host uses TSC clock, then passthrough TSC as stable
1529 * to the guest.
1530 */
1531 spin_lock(&ka->pvclock_gtod_sync_lock);
1532 use_master_clock = ka->use_master_clock;
1533 if (use_master_clock) {
1534 host_tsc = ka->master_cycle_now;
1535 kernel_ns = ka->master_kernel_ns;
1536 }
1537 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1538
1539 /* Keep irq disabled to prevent changes to the clock */
1540 local_irq_save(flags);
1541 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1542 if (unlikely(this_tsc_khz == 0)) {
1543 local_irq_restore(flags);
1544 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1545 return 1;
1546 }
d828199e
MT		 1547 if (!use_master_clock) {
1548 host_tsc = native_read_tsc();
1549 kernel_ns = get_kernel_ns();
1550 }
1551
1552 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1553
c285545f
ZA		 1554 /*
1555 * We may have to catch up the TSC to match elapsed wall clock
1556 * time for two reasons, even if kvmclock is used.
1557 * 1) CPU could have been running below the maximum TSC rate
1558 * 2) Broken TSC compensation resets the base at each VCPU
1559 * entry to avoid unknown leaps of TSC even when running
1560 * again on the same CPU. This may cause apparent elapsed
1561 * time to disappear, and the guest to stand still or run
1562 * very slowly.
1563 */
1564 if (vcpu->tsc_catchup) {
1565 u64 tsc = compute_guest_tsc(v, kernel_ns);
1566 if (tsc > tsc_timestamp) {
f1e2b260 1567 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1568 tsc_timestamp = tsc;
1569 }
50d0a0f9
GH		 1570 }
1571
18068523
GOC		 1572 local_irq_restore(flags);
1573
0b79459b 1574 if (!vcpu->pv_time_enabled)
c285545f 1575 return 0;
18068523 1576
e48672fa 1577 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1578 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1579 &vcpu->hv_clock.tsc_shift,
1580 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1581 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1582 }
1583
1584 /* With all the info we got, fill in the values */
1d5f066e 1585 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1586 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1587 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1588
18068523
GOC		 1589 /*
1590 * The interface expects us to write an even number signaling that the
1591 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1592 * state, we just increase by 2 at the end.
18068523 1593 */
50d0a0f9 1594 vcpu->hv_clock.version += 2;
18068523 1595
0b79459b
AH		 1596 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1597 &guest_hv_clock, sizeof(guest_hv_clock))))
1598 return 0;
78c0337a
MT		 1599
1600 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1601 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1602
1603 if (vcpu->pvclock_set_guest_stopped_request) {
1604 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1605 vcpu->pvclock_set_guest_stopped_request = false;
1606 }
1607
d828199e
MT		 1608 /* If the host uses TSC clocksource, then it is stable */
1609 if (use_master_clock)
1610 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1611
78c0337a
MT		 1612 vcpu->hv_clock.flags = pvclock_flags;
1613
0b79459b
AH		 1614 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1615 &vcpu->hv_clock,
1616 sizeof(vcpu->hv_clock));
8cfdc000 1617 return 0;
c8076604
GH		 1618}
1619
0061d53d
MT		 1620/*
1621 * kvmclock updates which are isolated to a given vcpu, such as
1622 * vcpu->cpu migration, should not allow system_timestamp from
1623 * the rest of the vcpus to remain static. Otherwise ntp frequency
1624 * correction applies to one vcpu's system_timestamp but not
1625 * the others.
1626 *
1627 * So in those cases, request a kvmclock update for all vcpus.
1628 * The worst case for a remote vcpu to update its kvmclock
1629 * is then bounded by maximum nohz sleep latency.
1630 */
1631
1632static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1633{
1634 int i;
1635 struct kvm *kvm = v->kvm;
1636 struct kvm_vcpu *vcpu;
1637
1638 kvm_for_each_vcpu(i, vcpu, kvm) {
1639 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1640 kvm_vcpu_kick(vcpu);
1641 }
1642}
1643
9ba075a6
AK		 1644static bool msr_mtrr_valid(unsigned msr)
1645{
1646 switch (msr) {
1647 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1648 case MSR_MTRRfix64K_00000:
1649 case MSR_MTRRfix16K_80000:
1650 case MSR_MTRRfix16K_A0000:
1651 case MSR_MTRRfix4K_C0000:
1652 case MSR_MTRRfix4K_C8000:
1653 case MSR_MTRRfix4K_D0000:
1654 case MSR_MTRRfix4K_D8000:
1655 case MSR_MTRRfix4K_E0000:
1656 case MSR_MTRRfix4K_E8000:
1657 case MSR_MTRRfix4K_F0000:
1658 case MSR_MTRRfix4K_F8000:
1659 case MSR_MTRRdefType:
1660 case MSR_IA32_CR_PAT:
1661 return true;
1662 case 0x2f8:
1663 return true;
1664 }
1665 return false;
1666}
1667
d6289b93
MT		 1668static bool valid_pat_type(unsigned t)
1669{
1670 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1671}
1672
1673static bool valid_mtrr_type(unsigned t)
1674{
1675 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1676}
1677
1678static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1679{
1680 int i;
1681
1682 if (!msr_mtrr_valid(msr))
1683 return false;
1684
1685 if (msr == MSR_IA32_CR_PAT) {
1686 for (i = 0; i < 8; i++)
1687 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1688 return false;
1689 return true;
1690 } else if (msr == MSR_MTRRdefType) {
1691 if (data & ~0xcff)
1692 return false;
1693 return valid_mtrr_type(data & 0xff);
1694 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1695 for (i = 0; i < 8 ; i++)
1696 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1697 return false;
1698 return true;
1699 }
1700
1701 /* variable MTRRs */
1702 return valid_mtrr_type(data & 0xff);
1703}
1704
9ba075a6
AK		 1705static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1706{
0bed3b56
SY		 1707 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1708
d6289b93 1709 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1710 return 1;
1711
0bed3b56
SY		 1712 if (msr == MSR_MTRRdefType) {
1713 vcpu->arch.mtrr_state.def_type = data;
1714 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1715 } else if (msr == MSR_MTRRfix64K_00000)
1716 p[0] = data;
1717 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1718 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1719 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1720 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1721 else if (msr == MSR_IA32_CR_PAT)
1722 vcpu->arch.pat = data;
1723 else { /* Variable MTRRs */
1724 int idx, is_mtrr_mask;
1725 u64 *pt;
1726
1727 idx = (msr - 0x200) / 2;
1728 is_mtrr_mask = msr - 0x200 - 2 * idx;
1729 if (!is_mtrr_mask)
1730 pt =
1731 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1732 else
1733 pt =
1734 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1735 *pt = data;
1736 }
1737
1738 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1739 return 0;
1740}
15c4a640 1741
890ca9ae 1742static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1743{
890ca9ae
HY		 1744 u64 mcg_cap = vcpu->arch.mcg_cap;
1745 unsigned bank_num = mcg_cap & 0xff;
1746
15c4a640 1747 switch (msr) {
15c4a640 1748 case MSR_IA32_MCG_STATUS:
890ca9ae 1749 vcpu->arch.mcg_status = data;
15c4a640 1750 break;
c7ac679c 1751 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1752 if (!(mcg_cap & MCG_CTL_P))
1753 return 1;
1754 if (data != 0 && data != ~(u64)0)
1755 return -1;
1756 vcpu->arch.mcg_ctl = data;
1757 break;
1758 default:
1759 if (msr >= MSR_IA32_MC0_CTL &&
1760 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1761 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1762 /* only 0 or all 1s can be written to IA32_MCi_CTL
1763 * some Linux kernels though clear bit 10 in bank 4 to
1764 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1765 * this to avoid an uncatched #GP in the guest
1766 */
890ca9ae 1767 if ((offset & 0x3) == 0 &&
114be429 1768 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1769 return -1;
1770 vcpu->arch.mce_banks[offset] = data;
1771 break;
1772 }
1773 return 1;
1774 }
1775 return 0;
1776}
1777
ffde22ac
ES		 1778static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1779{
1780 struct kvm *kvm = vcpu->kvm;
1781 int lm = is_long_mode(vcpu);
1782 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1783 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1784 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1785 : kvm->arch.xen_hvm_config.blob_size_32;
1786 u32 page_num = data & ~PAGE_MASK;
1787 u64 page_addr = data & PAGE_MASK;
1788 u8 *page;
1789 int r;
1790
1791 r = -E2BIG;
1792 if (page_num >= blob_size)
1793 goto out;
1794 r = -ENOMEM;
ff5c2c03
SL		 1795 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1796 if (IS_ERR(page)) {
1797 r = PTR_ERR(page);
ffde22ac 1798 goto out;
ff5c2c03 1799 }
ffde22ac
ES		 1800 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1801 goto out_free;
1802 r = 0;
1803out_free:
1804 kfree(page);
1805out:
1806 return r;
1807}
1808
55cd8e5a
GN		 1809static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1810{
1811 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1812}
1813
1814static bool kvm_hv_msr_partition_wide(u32 msr)
1815{
1816 bool r = false;
1817 switch (msr) {
1818 case HV_X64_MSR_GUEST_OS_ID:
1819 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1820 case HV_X64_MSR_REFERENCE_TSC:
1821 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1822 r = true;
1823 break;
1824 }
1825
1826 return r;
1827}
1828
1829static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1830{
1831 struct kvm *kvm = vcpu->kvm;
1832
1833 switch (msr) {
1834 case HV_X64_MSR_GUEST_OS_ID:
1835 kvm->arch.hv_guest_os_id = data;
1836 /* setting guest os id to zero disables hypercall page */
1837 if (!kvm->arch.hv_guest_os_id)
1838 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1839 break;
1840 case HV_X64_MSR_HYPERCALL: {
1841 u64 gfn;
1842 unsigned long addr;
1843 u8 instructions[4];
1844
1845 /* if guest os id is not set hypercall should remain disabled */
1846 if (!kvm->arch.hv_guest_os_id)
1847 break;
1848 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1849 kvm->arch.hv_hypercall = data;
1850 break;
1851 }
1852 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1853 addr = gfn_to_hva(kvm, gfn);
1854 if (kvm_is_error_hva(addr))
1855 return 1;
1856 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1857 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1858 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1859 return 1;
1860 kvm->arch.hv_hypercall = data;
b94b64c9 1861 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 1862 break;
1863 }
e984097b
VR		 1864 case HV_X64_MSR_REFERENCE_TSC: {
1865 u64 gfn;
1866 HV_REFERENCE_TSC_PAGE tsc_ref;
1867 memset(&tsc_ref, 0, sizeof(tsc_ref));
1868 kvm->arch.hv_tsc_page = data;
1869 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1870 break;
1871 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1872 if (kvm_write_guest(kvm, data,
1873 &tsc_ref, sizeof(tsc_ref)))
1874 return 1;
1875 mark_page_dirty(kvm, gfn);
1876 break;
1877 }
55cd8e5a 1878 default:
a737f256
CD		 1879 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1880 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1881 return 1;
1882 }
1883 return 0;
1884}
1885
1886static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1887{
10388a07
GN		 1888 switch (msr) {
1889 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 1890 u64 gfn;
10388a07 1891 unsigned long addr;
55cd8e5a 1892
10388a07
GN		 1893 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1894 vcpu->arch.hv_vapic = data;
1895 break;
1896 }
b3af1e88
VR		 1897 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1898 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 1899 if (kvm_is_error_hva(addr))
1900 return 1;
8b0cedff 1901 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1902 return 1;
1903 vcpu->arch.hv_vapic = data;
b3af1e88 1904 mark_page_dirty(vcpu->kvm, gfn);
10388a07
GN		 1905 break;
1906 }
1907 case HV_X64_MSR_EOI:
1908 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1909 case HV_X64_MSR_ICR:
1910 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1911 case HV_X64_MSR_TPR:
1912 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1913 default:
a737f256
CD		 1914 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1915 "data 0x%llx\n", msr, data);
10388a07
GN		 1916 return 1;
1917 }
1918
1919 return 0;
55cd8e5a
GN		 1920}
1921
344d9588
GN		 1922static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1923{
1924 gpa_t gpa = data & ~0x3f;
1925
4a969980 1926 /* Bits 2:5 are reserved, Should be zero */
6adba527 1927 if (data & 0x3c)
344d9588
GN		 1928 return 1;
1929
1930 vcpu->arch.apf.msr_val = data;
1931
1932 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1933 kvm_clear_async_pf_completion_queue(vcpu);
1934 kvm_async_pf_hash_reset(vcpu);
1935 return 0;
1936 }
1937
8f964525
AH		 1938 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1939 sizeof(u32)))
344d9588
GN		 1940 return 1;
1941
6adba527 1942 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1943 kvm_async_pf_wakeup_all(vcpu);
1944 return 0;
1945}
1946
12f9a48f
GC		 1947static void kvmclock_reset(struct kvm_vcpu *vcpu)
1948{
0b79459b 1949 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1950}
1951
c9aaa895
GC		 1952static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1953{
1954 u64 delta;
1955
1956 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1957 return;
1958
1959 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1960 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1961 vcpu->arch.st.accum_steal = delta;
1962}
1963
1964static void record_steal_time(struct kvm_vcpu *vcpu)
1965{
1966 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1967 return;
1968
1969 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1970 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1971 return;
1972
1973 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1974 vcpu->arch.st.steal.version += 2;
1975 vcpu->arch.st.accum_steal = 0;
1976
1977 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1978 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1979}
1980
8fe8ab46 1981int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 1982{
5753785f 1983 bool pr = false;
8fe8ab46
WA		 1984 u32 msr = msr_info->index;
1985 u64 data = msr_info->data;
5753785f 1986
15c4a640 1987 switch (msr) {
2e32b719
BP		 1988 case MSR_AMD64_NB_CFG:
1989 case MSR_IA32_UCODE_REV:
1990 case MSR_IA32_UCODE_WRITE:
1991 case MSR_VM_HSAVE_PA:
1992 case MSR_AMD64_PATCH_LOADER:
1993 case MSR_AMD64_BU_CFG2:
1994 break;
1995
15c4a640 1996 case MSR_EFER:
b69e8cae 1997 return set_efer(vcpu, data);
8f1589d9
AP		 1998 case MSR_K7_HWCR:
1999 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2000 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2001 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 2002 if (data != 0) {
a737f256
CD		 2003 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2004 data);
8f1589d9
AP		 2005 return 1;
2006 }
15c4a640 2007 break;
f7c6d140
AP		 2008 case MSR_FAM10H_MMIO_CONF_BASE:
2009 if (data != 0) {
a737f256
CD		 2010 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2011 "0x%llx\n", data);
f7c6d140
AP		 2012 return 1;
2013 }
15c4a640 2014 break;
b5e2fec0
AG		 2015 case MSR_IA32_DEBUGCTLMSR:
2016 if (!data) {
2017 /* We support the non-activated case already */
2018 break;
2019 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2020 /* Values other than LBR and BTF are vendor-specific,
2021 thus reserved and should throw a #GP */
2022 return 1;
2023 }
a737f256
CD		 2024 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2025 __func__, data);
b5e2fec0 2026 break;
9ba075a6
AK		 2027 case 0x200 ... 0x2ff:
2028 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2029 case MSR_IA32_APICBASE:
58cb628d 2030 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2031 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2032 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2033 case MSR_IA32_TSCDEADLINE:
2034 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2035 break;
ba904635
WA		 2036 case MSR_IA32_TSC_ADJUST:
2037 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2038 if (!msr_info->host_initiated) {
2039 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2040 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2041 }
2042 vcpu->arch.ia32_tsc_adjust_msr = data;
2043 }
2044 break;
15c4a640 2045 case MSR_IA32_MISC_ENABLE:
ad312c7c 2046 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2047 break;
11c6bffa 2048 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2049 case MSR_KVM_WALL_CLOCK:
2050 vcpu->kvm->arch.wall_clock = data;
2051 kvm_write_wall_clock(vcpu->kvm, data);
2052 break;
11c6bffa 2053 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2054 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2055 u64 gpa_offset;
12f9a48f 2056 kvmclock_reset(vcpu);
18068523
GOC		 2057
2058 vcpu->arch.time = data;
0061d53d 2059 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2060
2061 /* we verify if the enable bit is set... */
2062 if (!(data & 1))
2063 break;
2064
0b79459b 2065 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2066
0b79459b 2067 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2068 &vcpu->arch.pv_time, data & ~1ULL,
2069 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2070 vcpu->arch.pv_time_enabled = false;
2071 else
2072 vcpu->arch.pv_time_enabled = true;
32cad84f 2073
18068523
GOC		 2074 break;
2075 }
344d9588
GN		 2076 case MSR_KVM_ASYNC_PF_EN:
2077 if (kvm_pv_enable_async_pf(vcpu, data))
2078 return 1;
2079 break;
c9aaa895
GC		 2080 case MSR_KVM_STEAL_TIME:
2081
2082 if (unlikely(!sched_info_on()))
2083 return 1;
2084
2085 if (data & KVM_STEAL_RESERVED_MASK)
2086 return 1;
2087
2088 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2089 data & KVM_STEAL_VALID_BITS,
2090 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2091 return 1;
2092
2093 vcpu->arch.st.msr_val = data;
2094
2095 if (!(data & KVM_MSR_ENABLED))
2096 break;
2097
2098 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2099
2100 preempt_disable();
2101 accumulate_steal_time(vcpu);
2102 preempt_enable();
2103
2104 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2105
2106 break;
ae7a2a3f
MT		 2107 case MSR_KVM_PV_EOI_EN:
2108 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2109 return 1;
2110 break;
c9aaa895 2111
890ca9ae
HY		 2112 case MSR_IA32_MCG_CTL:
2113 case MSR_IA32_MCG_STATUS:
2114 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2115 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2116
2117 /* Performance counters are not protected by a CPUID bit,
2118 * so we should check all of them in the generic path for the sake of
2119 * cross vendor migration.
2120 * Writing a zero into the event select MSRs disables them,
2121 * which we perfectly emulate ;-). Any other value should be at least
2122 * reported, some guests depend on them.
2123 */
71db6023
AP		 2124 case MSR_K7_EVNTSEL0:
2125 case MSR_K7_EVNTSEL1:
2126 case MSR_K7_EVNTSEL2:
2127 case MSR_K7_EVNTSEL3:
2128 if (data != 0)
a737f256
CD		 2129 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2130 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2131 break;
2132 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2133 * so we ignore writes to make it happy.
2134 */
71db6023
AP		 2135 case MSR_K7_PERFCTR0:
2136 case MSR_K7_PERFCTR1:
2137 case MSR_K7_PERFCTR2:
2138 case MSR_K7_PERFCTR3:
a737f256
CD		 2139 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2140 "0x%x data 0x%llx\n", msr, data);
71db6023 2141 break;
5753785f
GN		 2142 case MSR_P6_PERFCTR0:
2143 case MSR_P6_PERFCTR1:
2144 pr = true;
2145 case MSR_P6_EVNTSEL0:
2146 case MSR_P6_EVNTSEL1:
2147 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2148 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2149
2150 if (pr || data != 0)
a737f256
CD		 2151 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2152 "0x%x data 0x%llx\n", msr, data);
5753785f 2153 break;
84e0cefa
JS		 2154 case MSR_K7_CLK_CTL:
2155 /*
2156 * Ignore all writes to this no longer documented MSR.
2157 * Writes are only relevant for old K7 processors,
2158 * all pre-dating SVM, but a recommended workaround from
4a969980 2159 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2160 * affected processor models on the command line, hence
2161 * the need to ignore the workaround.
2162 */
2163 break;
55cd8e5a
GN		 2164 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2165 if (kvm_hv_msr_partition_wide(msr)) {
2166 int r;
2167 mutex_lock(&vcpu->kvm->lock);
2168 r = set_msr_hyperv_pw(vcpu, msr, data);
2169 mutex_unlock(&vcpu->kvm->lock);
2170 return r;
2171 } else
2172 return set_msr_hyperv(vcpu, msr, data);
2173 break;
91c9c3ed 2174 case MSR_IA32_BBL_CR_CTL3:
2175 /* Drop writes to this legacy MSR -- see rdmsr
2176 * counterpart for further detail.
2177 */
a737f256 2178 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2179 break;
2b036c6b
BO		 2180 case MSR_AMD64_OSVW_ID_LENGTH:
2181 if (!guest_cpuid_has_osvw(vcpu))
2182 return 1;
2183 vcpu->arch.osvw.length = data;
2184 break;
2185 case MSR_AMD64_OSVW_STATUS:
2186 if (!guest_cpuid_has_osvw(vcpu))
2187 return 1;
2188 vcpu->arch.osvw.status = data;
2189 break;
15c4a640 2190 default:
ffde22ac
ES		 2191 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2192 return xen_hvm_config(vcpu, data);
f5132b01 2193 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2194 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2195 if (!ignore_msrs) {
a737f256
CD		 2196 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2197 msr, data);
ed85c068
AP		 2198 return 1;
2199 } else {
a737f256
CD		 2200 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2201 msr, data);
ed85c068
AP		 2202 break;
2203 }
15c4a640
CO		 2204 }
2205 return 0;
2206}
2207EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2208
2209
2210/*
2211 * Reads an msr value (of 'msr_index') into 'pdata'.
2212 * Returns 0 on success, non-0 otherwise.
2213 * Assumes vcpu_load() was already called.
2214 */
2215int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2216{
2217 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2218}
2219
9ba075a6
AK		 2220static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2221{
0bed3b56
SY		 2222 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2223
9ba075a6
AK		 2224 if (!msr_mtrr_valid(msr))
2225 return 1;
2226
0bed3b56
SY		 2227 if (msr == MSR_MTRRdefType)
2228 *pdata = vcpu->arch.mtrr_state.def_type +
2229 (vcpu->arch.mtrr_state.enabled << 10);
2230 else if (msr == MSR_MTRRfix64K_00000)
2231 *pdata = p[0];
2232 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2233 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2234 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2235 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2236 else if (msr == MSR_IA32_CR_PAT)
2237 *pdata = vcpu->arch.pat;
2238 else { /* Variable MTRRs */
2239 int idx, is_mtrr_mask;
2240 u64 *pt;
2241
2242 idx = (msr - 0x200) / 2;
2243 is_mtrr_mask = msr - 0x200 - 2 * idx;
2244 if (!is_mtrr_mask)
2245 pt =
2246 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2247 else
2248 pt =
2249 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2250 *pdata = *pt;
2251 }
2252
9ba075a6
AK		 2253 return 0;
2254}
2255
890ca9ae 2256static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2257{
2258 u64 data;
890ca9ae
HY		 2259 u64 mcg_cap = vcpu->arch.mcg_cap;
2260 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2261
2262 switch (msr) {
15c4a640
CO		 2263 case MSR_IA32_P5_MC_ADDR:
2264 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2265 data = 0;
2266 break;
15c4a640 2267 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2268 data = vcpu->arch.mcg_cap;
2269 break;
c7ac679c 2270 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2271 if (!(mcg_cap & MCG_CTL_P))
2272 return 1;
2273 data = vcpu->arch.mcg_ctl;
2274 break;
2275 case MSR_IA32_MCG_STATUS:
2276 data = vcpu->arch.mcg_status;
2277 break;
2278 default:
2279 if (msr >= MSR_IA32_MC0_CTL &&
2280 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2281 u32 offset = msr - MSR_IA32_MC0_CTL;
2282 data = vcpu->arch.mce_banks[offset];
2283 break;
2284 }
2285 return 1;
2286 }
2287 *pdata = data;
2288 return 0;
2289}
2290
55cd8e5a
GN		 2291static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2292{
2293 u64 data = 0;
2294 struct kvm *kvm = vcpu->kvm;
2295
2296 switch (msr) {
2297 case HV_X64_MSR_GUEST_OS_ID:
2298 data = kvm->arch.hv_guest_os_id;
2299 break;
2300 case HV_X64_MSR_HYPERCALL:
2301 data = kvm->arch.hv_hypercall;
2302 break;
e984097b
VR		 2303 case HV_X64_MSR_TIME_REF_COUNT: {
2304 data =
2305 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2306 break;
2307 }
2308 case HV_X64_MSR_REFERENCE_TSC:
2309 data = kvm->arch.hv_tsc_page;
2310 break;
55cd8e5a 2311 default:
a737f256 2312 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2313 return 1;
2314 }
2315
2316 *pdata = data;
2317 return 0;
2318}
2319
2320static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2321{
2322 u64 data = 0;
2323
2324 switch (msr) {
2325 case HV_X64_MSR_VP_INDEX: {
2326 int r;
2327 struct kvm_vcpu *v;
2328 kvm_for_each_vcpu(r, v, vcpu->kvm)
2329 if (v == vcpu)
2330 data = r;
2331 break;
2332 }
10388a07
GN		 2333 case HV_X64_MSR_EOI:
2334 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2335 case HV_X64_MSR_ICR:
2336 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2337 case HV_X64_MSR_TPR:
2338 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2339 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2340 data = vcpu->arch.hv_vapic;
2341 break;
55cd8e5a 2342 default:
a737f256 2343 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2344 return 1;
2345 }
2346 *pdata = data;
2347 return 0;
2348}
2349
890ca9ae
HY		 2350int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2351{
2352 u64 data;
2353
2354 switch (msr) {
890ca9ae 2355 case MSR_IA32_PLATFORM_ID:
15c4a640 2356 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2357 case MSR_IA32_DEBUGCTLMSR:
2358 case MSR_IA32_LASTBRANCHFROMIP:
2359 case MSR_IA32_LASTBRANCHTOIP:
2360 case MSR_IA32_LASTINTFROMIP:
2361 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2362 case MSR_K8_SYSCFG:
2363 case MSR_K7_HWCR:
61a6bd67 2364 case MSR_VM_HSAVE_PA:
9e699624 2365 case MSR_K7_EVNTSEL0:
1f3ee616 2366 case MSR_K7_PERFCTR0:
1fdbd48c 2367 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2368 case MSR_AMD64_NB_CFG:
f7c6d140 2369 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2370 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2371 data = 0;
2372 break;
5753785f
GN		 2373 case MSR_P6_PERFCTR0:
2374 case MSR_P6_PERFCTR1:
2375 case MSR_P6_EVNTSEL0:
2376 case MSR_P6_EVNTSEL1:
2377 if (kvm_pmu_msr(vcpu, msr))
2378 return kvm_pmu_get_msr(vcpu, msr, pdata);
2379 data = 0;
2380 break;
742bc670
MT		 2381 case MSR_IA32_UCODE_REV:
2382 data = 0x100000000ULL;
2383 break;
9ba075a6
AK		 2384 case MSR_MTRRcap:
2385 data = 0x500 | KVM_NR_VAR_MTRR;
2386 break;
2387 case 0x200 ... 0x2ff:
2388 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2389 case 0xcd: /* fsb frequency */
2390 data = 3;
2391 break;
7b914098
JS		 2392 /*
2393 * MSR_EBC_FREQUENCY_ID
2394 * Conservative value valid for even the basic CPU models.
2395 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2396 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2397 * and 266MHz for model 3, or 4. Set Core Clock
2398 * Frequency to System Bus Frequency Ratio to 1 (bits
2399 * 31:24) even though these are only valid for CPU
2400 * models > 2, however guests may end up dividing or
2401 * multiplying by zero otherwise.
2402 */
2403 case MSR_EBC_FREQUENCY_ID:
2404 data = 1 << 24;
2405 break;
15c4a640
CO		 2406 case MSR_IA32_APICBASE:
2407 data = kvm_get_apic_base(vcpu);
2408 break;
0105d1a5
GN		 2409 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2410 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2411 break;
a3e06bbe
LJ		 2412 case MSR_IA32_TSCDEADLINE:
2413 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2414 break;
ba904635
WA		 2415 case MSR_IA32_TSC_ADJUST:
2416 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2417 break;
15c4a640 2418 case MSR_IA32_MISC_ENABLE:
ad312c7c 2419 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2420 break;
847f0ad8
AG		 2421 case MSR_IA32_PERF_STATUS:
2422 /* TSC increment by tick */
2423 data = 1000ULL;
2424 /* CPU multiplier */
2425 data |= (((uint64_t)4ULL) << 40);
2426 break;
15c4a640 2427 case MSR_EFER:
f6801dff 2428 data = vcpu->arch.efer;
15c4a640 2429 break;
18068523 2430 case MSR_KVM_WALL_CLOCK:
11c6bffa 2431 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2432 data = vcpu->kvm->arch.wall_clock;
2433 break;
2434 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2435 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2436 data = vcpu->arch.time;
2437 break;
344d9588
GN		 2438 case MSR_KVM_ASYNC_PF_EN:
2439 data = vcpu->arch.apf.msr_val;
2440 break;
c9aaa895
GC		 2441 case MSR_KVM_STEAL_TIME:
2442 data = vcpu->arch.st.msr_val;
2443 break;
1d92128f
MT		 2444 case MSR_KVM_PV_EOI_EN:
2445 data = vcpu->arch.pv_eoi.msr_val;
2446 break;
890ca9ae
HY		 2447 case MSR_IA32_P5_MC_ADDR:
2448 case MSR_IA32_P5_MC_TYPE:
2449 case MSR_IA32_MCG_CAP:
2450 case MSR_IA32_MCG_CTL:
2451 case MSR_IA32_MCG_STATUS:
2452 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2453 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2454 case MSR_K7_CLK_CTL:
2455 /*
2456 * Provide expected ramp-up count for K7. All other
2457 * are set to zero, indicating minimum divisors for
2458 * every field.
2459 *
2460 * This prevents guest kernels on AMD host with CPU
2461 * type 6, model 8 and higher from exploding due to
2462 * the rdmsr failing.
2463 */
2464 data = 0x20000000;
2465 break;
55cd8e5a
GN		 2466 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2467 if (kvm_hv_msr_partition_wide(msr)) {
2468 int r;
2469 mutex_lock(&vcpu->kvm->lock);
2470 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2471 mutex_unlock(&vcpu->kvm->lock);
2472 return r;
2473 } else
2474 return get_msr_hyperv(vcpu, msr, pdata);
2475 break;
91c9c3ed 2476 case MSR_IA32_BBL_CR_CTL3:
2477 /* This legacy MSR exists but isn't fully documented in current
2478 * silicon. It is however accessed by winxp in very narrow
2479 * scenarios where it sets bit #19, itself documented as
2480 * a "reserved" bit. Best effort attempt to source coherent
2481 * read data here should the balance of the register be
2482 * interpreted by the guest:
2483 *
2484 * L2 cache control register 3: 64GB range, 256KB size,
2485 * enabled, latency 0x1, configured
2486 */
2487 data = 0xbe702111;
2488 break;
2b036c6b
BO		 2489 case MSR_AMD64_OSVW_ID_LENGTH:
2490 if (!guest_cpuid_has_osvw(vcpu))
2491 return 1;
2492 data = vcpu->arch.osvw.length;
2493 break;
2494 case MSR_AMD64_OSVW_STATUS:
2495 if (!guest_cpuid_has_osvw(vcpu))
2496 return 1;
2497 data = vcpu->arch.osvw.status;
2498 break;
15c4a640 2499 default:
f5132b01
GN		 2500 if (kvm_pmu_msr(vcpu, msr))
2501 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2502 if (!ignore_msrs) {
a737f256 2503 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2504 return 1;
2505 } else {
a737f256 2506 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2507 data = 0;
2508 }
2509 break;
15c4a640
CO		 2510 }
2511 *pdata = data;
2512 return 0;
2513}
2514EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2515
313a3dc7
CO		 2516/*
2517 * Read or write a bunch of msrs. All parameters are kernel addresses.
2518 *
2519 * @return number of msrs set successfully.
2520 */
2521static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2522 struct kvm_msr_entry *entries,
2523 int (*do_msr)(struct kvm_vcpu *vcpu,
2524 unsigned index, u64 *data))
2525{
f656ce01 2526 int i, idx;
313a3dc7 2527
f656ce01 2528 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2529 for (i = 0; i < msrs->nmsrs; ++i)
2530 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2531 break;
f656ce01 2532 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2533
313a3dc7
CO		 2534 return i;
2535}
2536
2537/*
2538 * Read or write a bunch of msrs. Parameters are user addresses.
2539 *
2540 * @return number of msrs set successfully.
2541 */
2542static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2543 int (*do_msr)(struct kvm_vcpu *vcpu,
2544 unsigned index, u64 *data),
2545 int writeback)
2546{
2547 struct kvm_msrs msrs;
2548 struct kvm_msr_entry *entries;
2549 int r, n;
2550 unsigned size;
2551
2552 r = -EFAULT;
2553 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2554 goto out;
2555
2556 r = -E2BIG;
2557 if (msrs.nmsrs >= MAX_IO_MSRS)
2558 goto out;
2559
313a3dc7 2560 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2561 entries = memdup_user(user_msrs->entries, size);
2562 if (IS_ERR(entries)) {
2563 r = PTR_ERR(entries);
313a3dc7 2564 goto out;
ff5c2c03 2565 }
313a3dc7
CO		 2566
2567 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2568 if (r < 0)
2569 goto out_free;
2570
2571 r = -EFAULT;
2572 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2573 goto out_free;
2574
2575 r = n;
2576
2577out_free:
7a73c028 2578 kfree(entries);
313a3dc7
CO		 2579out:
2580 return r;
2581}
2582
018d00d2
ZX		 2583int kvm_dev_ioctl_check_extension(long ext)
2584{
2585 int r;
2586
2587 switch (ext) {
2588 case KVM_CAP_IRQCHIP:
2589 case KVM_CAP_HLT:
2590 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2591 case KVM_CAP_SET_TSS_ADDR:
07716717 2592 case KVM_CAP_EXT_CPUID:
9c15bb1d 2593 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2594 case KVM_CAP_CLOCKSOURCE:
7837699f 2595 case KVM_CAP_PIT:
a28e4f5a 2596 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2597 case KVM_CAP_MP_STATE:
ed848624 2598 case KVM_CAP_SYNC_MMU:
a355c85c 2599 case KVM_CAP_USER_NMI:
52d939a0 2600 case KVM_CAP_REINJECT_CONTROL:
4925663a 2601 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2602 case KVM_CAP_IRQFD:
d34e6b17 2603 case KVM_CAP_IOEVENTFD:
c5ff41ce 2604 case KVM_CAP_PIT2:
e9f42757 2605 case KVM_CAP_PIT_STATE2:
b927a3ce 2606 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2607 case KVM_CAP_XEN_HVM:
afbcf7ab 2608 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2609 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2610 case KVM_CAP_HYPERV:
10388a07 2611 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2612 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2613 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2614 case KVM_CAP_DEBUGREGS:
d2be1651 2615 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2616 case KVM_CAP_XSAVE:
344d9588 2617 case KVM_CAP_ASYNC_PF:
92a1f12d 2618 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2619 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2620 case KVM_CAP_READONLY_MEM:
5f66b620 2621 case KVM_CAP_HYPERV_TIME:
2a5bab10
AW		 2622#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2623 case KVM_CAP_ASSIGN_DEV_IRQ:
2624 case KVM_CAP_PCI_2_3:
2625#endif
018d00d2
ZX		 2626 r = 1;
2627 break;
542472b5
LV		 2628 case KVM_CAP_COALESCED_MMIO:
2629 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2630 break;
774ead3a
AK		 2631 case KVM_CAP_VAPIC:
2632 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2633 break;
f725230a 2634 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2635 r = KVM_SOFT_MAX_VCPUS;
2636 break;
2637 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2638 r = KVM_MAX_VCPUS;
2639 break;
a988b910 2640 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2641 r = KVM_USER_MEM_SLOTS;
a988b910 2642 break;
a68a6a72
MT		 2643 case KVM_CAP_PV_MMU: /* obsolete */
2644 r = 0;
2f333bcb 2645 break;
4cee4b72 2646#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2647 case KVM_CAP_IOMMU:
a1b60c1c 2648 r = iommu_present(&pci_bus_type);
62c476c7 2649 break;
4cee4b72 2650#endif
890ca9ae
HY		 2651 case KVM_CAP_MCE:
2652 r = KVM_MAX_MCE_BANKS;
2653 break;
2d5b5a66
SY		 2654 case KVM_CAP_XCRS:
2655 r = cpu_has_xsave;
2656 break;
92a1f12d
JR		 2657 case KVM_CAP_TSC_CONTROL:
2658 r = kvm_has_tsc_control;
2659 break;
4d25a066
JK		 2660 case KVM_CAP_TSC_DEADLINE_TIMER:
2661 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2662 break;
018d00d2
ZX		 2663 default:
2664 r = 0;
2665 break;
2666 }
2667 return r;
2668
2669}
2670
043405e1
CO		 2671long kvm_arch_dev_ioctl(struct file *filp,
2672 unsigned int ioctl, unsigned long arg)
2673{
2674 void __user *argp = (void __user *)arg;
2675 long r;
2676
2677 switch (ioctl) {
2678 case KVM_GET_MSR_INDEX_LIST: {
2679 struct kvm_msr_list __user *user_msr_list = argp;
2680 struct kvm_msr_list msr_list;
2681 unsigned n;
2682
2683 r = -EFAULT;
2684 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2685 goto out;
2686 n = msr_list.nmsrs;
2687 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2688 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2689 goto out;
2690 r = -E2BIG;
e125e7b6 2691 if (n < msr_list.nmsrs)
043405e1
CO		 2692 goto out;
2693 r = -EFAULT;
2694 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2695 num_msrs_to_save * sizeof(u32)))
2696 goto out;
e125e7b6 2697 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2698 &emulated_msrs,
2699 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2700 goto out;
2701 r = 0;
2702 break;
2703 }
9c15bb1d
BP		 2704 case KVM_GET_SUPPORTED_CPUID:
2705 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2706 struct kvm_cpuid2 __user *cpuid_arg = argp;
2707 struct kvm_cpuid2 cpuid;
2708
2709 r = -EFAULT;
2710 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2711 goto out;
9c15bb1d
BP		 2712
2713 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2714 ioctl);
674eea0f
AK		 2715 if (r)
2716 goto out;
2717
2718 r = -EFAULT;
2719 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2720 goto out;
2721 r = 0;
2722 break;
2723 }
890ca9ae
HY		 2724 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2725 u64 mce_cap;
2726
2727 mce_cap = KVM_MCE_CAP_SUPPORTED;
2728 r = -EFAULT;
2729 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2730 goto out;
2731 r = 0;
2732 break;
2733 }
043405e1
CO		 2734 default:
2735 r = -EINVAL;
2736 }
2737out:
2738 return r;
2739}
2740
f5f48ee1
SY		 2741static void wbinvd_ipi(void *garbage)
2742{
2743 wbinvd();
2744}
2745
2746static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2747{
e0f0bbc5 2748 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2749}
2750
313a3dc7
CO		 2751void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2752{
f5f48ee1
SY		 2753 /* Address WBINVD may be executed by guest */
2754 if (need_emulate_wbinvd(vcpu)) {
2755 if (kvm_x86_ops->has_wbinvd_exit())
2756 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2757 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2758 smp_call_function_single(vcpu->cpu,
2759 wbinvd_ipi, NULL, 1);
2760 }
2761
313a3dc7 2762 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2763
0dd6a6ed
ZA		 2764 /* Apply any externally detected TSC adjustments (due to suspend) */
2765 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2766 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2767 vcpu->arch.tsc_offset_adjustment = 0;
2768 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2769 }
8f6055cb 2770
48434c20 2771 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2772 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2773 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2774 if (tsc_delta < 0)
2775 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2776 if (check_tsc_unstable()) {
b183aa58
ZA		 2777 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2778 vcpu->arch.last_guest_tsc);
2779 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2780 vcpu->arch.tsc_catchup = 1;
c285545f 2781 }
d98d07ca
MT		 2782 /*
2783 * On a host with synchronized TSC, there is no need to update
2784 * kvmclock on vcpu->cpu migration
2785 */
2786 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2787 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2788 if (vcpu->cpu != cpu)
2789 kvm_migrate_timers(vcpu);
e48672fa 2790 vcpu->cpu = cpu;
6b7d7e76 2791 }
c9aaa895
GC		 2792
2793 accumulate_steal_time(vcpu);
2794 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2795}
2796
2797void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2798{
02daab21 2799 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2800 kvm_put_guest_fpu(vcpu);
6f526ec5 2801 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2802}
2803
313a3dc7
CO		 2804static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2805 struct kvm_lapic_state *s)
2806{
5a71785d 2807 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2808 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2809
2810 return 0;
2811}
2812
2813static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2814 struct kvm_lapic_state *s)
2815{
64eb0620 2816 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2817 update_cr8_intercept(vcpu);
313a3dc7
CO		 2818
2819 return 0;
2820}
2821
f77bc6a4
ZX		 2822static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2823 struct kvm_interrupt *irq)
2824{
02cdb50f 2825 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2826 return -EINVAL;
2827 if (irqchip_in_kernel(vcpu->kvm))
2828 return -ENXIO;
f77bc6a4 2829
66fd3f7f 2830 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2831 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2832
f77bc6a4
ZX		 2833 return 0;
2834}
2835
c4abb7c9
JK		 2836static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2837{
c4abb7c9 2838 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2839
2840 return 0;
2841}
2842
b209749f
AK		 2843static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2844 struct kvm_tpr_access_ctl *tac)
2845{
2846 if (tac->flags)
2847 return -EINVAL;
2848 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2849 return 0;
2850}
2851
890ca9ae
HY		 2852static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2853 u64 mcg_cap)
2854{
2855 int r;
2856 unsigned bank_num = mcg_cap & 0xff, bank;
2857
2858 r = -EINVAL;
a9e38c3e 2859 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2860 goto out;
2861 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2862 goto out;
2863 r = 0;
2864 vcpu->arch.mcg_cap = mcg_cap;
2865 /* Init IA32_MCG_CTL to all 1s */
2866 if (mcg_cap & MCG_CTL_P)
2867 vcpu->arch.mcg_ctl = ~(u64)0;
2868 /* Init IA32_MCi_CTL to all 1s */
2869 for (bank = 0; bank < bank_num; bank++)
2870 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2871out:
2872 return r;
2873}
2874
2875static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2876 struct kvm_x86_mce *mce)
2877{
2878 u64 mcg_cap = vcpu->arch.mcg_cap;
2879 unsigned bank_num = mcg_cap & 0xff;
2880 u64 *banks = vcpu->arch.mce_banks;
2881
2882 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2883 return -EINVAL;
2884 /*
2885 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2886 * reporting is disabled
2887 */
2888 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2889 vcpu->arch.mcg_ctl != ~(u64)0)
2890 return 0;
2891 banks += 4 * mce->bank;
2892 /*
2893 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2894 * reporting is disabled for the bank
2895 */
2896 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2897 return 0;
2898 if (mce->status & MCI_STATUS_UC) {
2899 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2900 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2901 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2902 return 0;
2903 }
2904 if (banks[1] & MCI_STATUS_VAL)
2905 mce->status |= MCI_STATUS_OVER;
2906 banks[2] = mce->addr;
2907 banks[3] = mce->misc;
2908 vcpu->arch.mcg_status = mce->mcg_status;
2909 banks[1] = mce->status;
2910 kvm_queue_exception(vcpu, MC_VECTOR);
2911 } else if (!(banks[1] & MCI_STATUS_VAL)
2912 || !(banks[1] & MCI_STATUS_UC)) {
2913 if (banks[1] & MCI_STATUS_VAL)
2914 mce->status |= MCI_STATUS_OVER;
2915 banks[2] = mce->addr;
2916 banks[3] = mce->misc;
2917 banks[1] = mce->status;
2918 } else
2919 banks[1] |= MCI_STATUS_OVER;
2920 return 0;
2921}
2922
3cfc3092
JK		 2923static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2924 struct kvm_vcpu_events *events)
2925{
7460fb4a 2926 process_nmi(vcpu);
03b82a30
JK		 2927 events->exception.injected =
2928 vcpu->arch.exception.pending &&
2929 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2930 events->exception.nr = vcpu->arch.exception.nr;
2931 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2932 events->exception.pad = 0;
3cfc3092
JK		 2933 events->exception.error_code = vcpu->arch.exception.error_code;
2934
03b82a30
JK		 2935 events->interrupt.injected =
2936 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2937 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2938 events->interrupt.soft = 0;
48005f64
JK		 2939 events->interrupt.shadow =
2940 kvm_x86_ops->get_interrupt_shadow(vcpu,
2941 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2942
2943 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2944 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2945 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2946 events->nmi.pad = 0;
3cfc3092 2947
66450a21 2948 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2949
dab4b911 2950 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2951 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2952 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2953}
2954
2955static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2956 struct kvm_vcpu_events *events)
2957{
dab4b911 2958 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2959 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2960 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2961 return -EINVAL;
2962
7460fb4a 2963 process_nmi(vcpu);
3cfc3092
JK		 2964 vcpu->arch.exception.pending = events->exception.injected;
2965 vcpu->arch.exception.nr = events->exception.nr;
2966 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2967 vcpu->arch.exception.error_code = events->exception.error_code;
2968
2969 vcpu->arch.interrupt.pending = events->interrupt.injected;
2970 vcpu->arch.interrupt.nr = events->interrupt.nr;
2971 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2972 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2973 kvm_x86_ops->set_interrupt_shadow(vcpu,
2974 events->interrupt.shadow);
3cfc3092
JK		 2975
2976 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2977 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2978 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2979 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2980
66450a21
JK		 2981 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2982 kvm_vcpu_has_lapic(vcpu))
2983 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2984
3842d135
AK		 2985 kvm_make_request(KVM_REQ_EVENT, vcpu);
2986
3cfc3092
JK		 2987 return 0;
2988}
2989
a1efbe77
JK		 2990static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2991 struct kvm_debugregs *dbgregs)
2992{
73aaf249
JK		 2993 unsigned long val;
2994
a1efbe77 2995 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
73aaf249
JK		 2996 _kvm_get_dr(vcpu, 6, &val);
2997 dbgregs->dr6 = val;
a1efbe77
JK		 2998 dbgregs->dr7 = vcpu->arch.dr7;
2999 dbgregs->flags = 0;
97e69aa6 3000 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3001}
3002
3003static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3004 struct kvm_debugregs *dbgregs)
3005{
3006 if (dbgregs->flags)
3007 return -EINVAL;
3008
a1efbe77
JK		 3009 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3010 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3011 kvm_update_dr6(vcpu);
a1efbe77 3012 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3013 kvm_update_dr7(vcpu);
a1efbe77 3014
a1efbe77
JK		 3015 return 0;
3016}
3017
2d5b5a66
SY		 3018static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3019 struct kvm_xsave *guest_xsave)
3020{
4344ee98 3021 if (cpu_has_xsave) {
2d5b5a66
SY		 3022 memcpy(guest_xsave->region,
3023 &vcpu->arch.guest_fpu.state->xsave,
4344ee98
PB		 3024 vcpu->arch.guest_xstate_size);
3025 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3026 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3027 } else {
2d5b5a66
SY		 3028 memcpy(guest_xsave->region,
3029 &vcpu->arch.guest_fpu.state->fxsave,
3030 sizeof(struct i387_fxsave_struct));
3031 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3032 XSTATE_FPSSE;
3033 }
3034}
3035
3036static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3037 struct kvm_xsave *guest_xsave)
3038{
3039 u64 xstate_bv =
3040 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3041
d7876f1b
PB		 3042 if (cpu_has_xsave) {
3043 /*
3044 * Here we allow setting states that are not present in
3045 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3046 * with old userspace.
3047 */
3048 if (xstate_bv & ~KVM_SUPPORTED_XCR0)
3049 return -EINVAL;
3050 if (xstate_bv & ~host_xcr0)
3051 return -EINVAL;
2d5b5a66 3052 memcpy(&vcpu->arch.guest_fpu.state->xsave,
4344ee98 3053 guest_xsave->region, vcpu->arch.guest_xstate_size);
d7876f1b 3054 } else {
2d5b5a66
SY		 3055 if (xstate_bv & ~XSTATE_FPSSE)
3056 return -EINVAL;
3057 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3058 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3059 }
3060 return 0;
3061}
3062
3063static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3064 struct kvm_xcrs *guest_xcrs)
3065{
3066 if (!cpu_has_xsave) {
3067 guest_xcrs->nr_xcrs = 0;
3068 return;
3069 }
3070
3071 guest_xcrs->nr_xcrs = 1;
3072 guest_xcrs->flags = 0;
3073 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3074 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3075}
3076
3077static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3078 struct kvm_xcrs *guest_xcrs)
3079{
3080 int i, r = 0;
3081
3082 if (!cpu_has_xsave)
3083 return -EINVAL;
3084
3085 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3086 return -EINVAL;
3087
3088 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3089 /* Only support XCR0 currently */
c67a04cb 3090 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3091 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3092 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3093 break;
3094 }
3095 if (r)
3096 r = -EINVAL;
3097 return r;
3098}
3099
1c0b28c2
EM		 3100/*
3101 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3102 * stopped by the hypervisor. This function will be called from the host only.
3103 * EINVAL is returned when the host attempts to set the flag for a guest that
3104 * does not support pv clocks.
3105 */
3106static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3107{
0b79459b 3108 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3109 return -EINVAL;
51d59c6b 3110 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3111 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3112 return 0;
3113}
3114
313a3dc7
CO		 3115long kvm_arch_vcpu_ioctl(struct file *filp,
3116 unsigned int ioctl, unsigned long arg)
3117{
3118 struct kvm_vcpu *vcpu = filp->private_data;
3119 void __user *argp = (void __user *)arg;
3120 int r;
d1ac91d8
AK		 3121 union {
3122 struct kvm_lapic_state *lapic;
3123 struct kvm_xsave *xsave;
3124 struct kvm_xcrs *xcrs;
3125 void *buffer;
3126 } u;
3127
3128 u.buffer = NULL;
313a3dc7
CO		 3129 switch (ioctl) {
3130 case KVM_GET_LAPIC: {
2204ae3c
MT		 3131 r = -EINVAL;
3132 if (!vcpu->arch.apic)
3133 goto out;
d1ac91d8 3134 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3135
b772ff36 3136 r = -ENOMEM;
d1ac91d8 3137 if (!u.lapic)
b772ff36 3138 goto out;
d1ac91d8 3139 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3140 if (r)
3141 goto out;
3142 r = -EFAULT;
d1ac91d8 3143 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3144 goto out;
3145 r = 0;
3146 break;
3147 }
3148 case KVM_SET_LAPIC: {
2204ae3c
MT		 3149 r = -EINVAL;
3150 if (!vcpu->arch.apic)
3151 goto out;
ff5c2c03 3152 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3153 if (IS_ERR(u.lapic))
3154 return PTR_ERR(u.lapic);
ff5c2c03 3155
d1ac91d8 3156 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3157 break;
3158 }
f77bc6a4
ZX		 3159 case KVM_INTERRUPT: {
3160 struct kvm_interrupt irq;
3161
3162 r = -EFAULT;
3163 if (copy_from_user(&irq, argp, sizeof irq))
3164 goto out;
3165 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3166 break;
3167 }
c4abb7c9
JK		 3168 case KVM_NMI: {
3169 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3170 break;
3171 }
313a3dc7
CO		 3172 case KVM_SET_CPUID: {
3173 struct kvm_cpuid __user *cpuid_arg = argp;
3174 struct kvm_cpuid cpuid;
3175
3176 r = -EFAULT;
3177 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3178 goto out;
3179 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3180 break;
3181 }
07716717
DK		 3182 case KVM_SET_CPUID2: {
3183 struct kvm_cpuid2 __user *cpuid_arg = argp;
3184 struct kvm_cpuid2 cpuid;
3185
3186 r = -EFAULT;
3187 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3188 goto out;
3189 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3190 cpuid_arg->entries);
07716717
DK		 3191 break;
3192 }
3193 case KVM_GET_CPUID2: {
3194 struct kvm_cpuid2 __user *cpuid_arg = argp;
3195 struct kvm_cpuid2 cpuid;
3196
3197 r = -EFAULT;
3198 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3199 goto out;
3200 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3201 cpuid_arg->entries);
07716717
DK		 3202 if (r)
3203 goto out;
3204 r = -EFAULT;
3205 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3206 goto out;
3207 r = 0;
3208 break;
3209 }
313a3dc7
CO		 3210 case KVM_GET_MSRS:
3211 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3212 break;
3213 case KVM_SET_MSRS:
3214 r = msr_io(vcpu, argp, do_set_msr, 0);
3215 break;
b209749f
AK		 3216 case KVM_TPR_ACCESS_REPORTING: {
3217 struct kvm_tpr_access_ctl tac;
3218
3219 r = -EFAULT;
3220 if (copy_from_user(&tac, argp, sizeof tac))
3221 goto out;
3222 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3223 if (r)
3224 goto out;
3225 r = -EFAULT;
3226 if (copy_to_user(argp, &tac, sizeof tac))
3227 goto out;
3228 r = 0;
3229 break;
3230 };
b93463aa
AK		 3231 case KVM_SET_VAPIC_ADDR: {
3232 struct kvm_vapic_addr va;
3233
3234 r = -EINVAL;
3235 if (!irqchip_in_kernel(vcpu->kvm))
3236 goto out;
3237 r = -EFAULT;
3238 if (copy_from_user(&va, argp, sizeof va))
3239 goto out;
fda4e2e8 3240 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3241 break;
3242 }
890ca9ae
HY		 3243 case KVM_X86_SETUP_MCE: {
3244 u64 mcg_cap;
3245
3246 r = -EFAULT;
3247 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3248 goto out;
3249 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3250 break;
3251 }
3252 case KVM_X86_SET_MCE: {
3253 struct kvm_x86_mce mce;
3254
3255 r = -EFAULT;
3256 if (copy_from_user(&mce, argp, sizeof mce))
3257 goto out;
3258 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3259 break;
3260 }
3cfc3092
JK		 3261 case KVM_GET_VCPU_EVENTS: {
3262 struct kvm_vcpu_events events;
3263
3264 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3265
3266 r = -EFAULT;
3267 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3268 break;
3269 r = 0;
3270 break;
3271 }
3272 case KVM_SET_VCPU_EVENTS: {
3273 struct kvm_vcpu_events events;
3274
3275 r = -EFAULT;
3276 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3277 break;
3278
3279 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3280 break;
3281 }
a1efbe77
JK		 3282 case KVM_GET_DEBUGREGS: {
3283 struct kvm_debugregs dbgregs;
3284
3285 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3286
3287 r = -EFAULT;
3288 if (copy_to_user(argp, &dbgregs,
3289 sizeof(struct kvm_debugregs)))
3290 break;
3291 r = 0;
3292 break;
3293 }
3294 case KVM_SET_DEBUGREGS: {
3295 struct kvm_debugregs dbgregs;
3296
3297 r = -EFAULT;
3298 if (copy_from_user(&dbgregs, argp,
3299 sizeof(struct kvm_debugregs)))
3300 break;
3301
3302 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3303 break;
3304 }
2d5b5a66 3305 case KVM_GET_XSAVE: {
d1ac91d8 3306 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3307 r = -ENOMEM;
d1ac91d8 3308 if (!u.xsave)
2d5b5a66
SY		 3309 break;
3310
d1ac91d8 3311 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3312
3313 r = -EFAULT;
d1ac91d8 3314 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3315 break;
3316 r = 0;
3317 break;
3318 }
3319 case KVM_SET_XSAVE: {
ff5c2c03 3320 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3321 if (IS_ERR(u.xsave))
3322 return PTR_ERR(u.xsave);
2d5b5a66 3323
d1ac91d8 3324 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3325 break;
3326 }
3327 case KVM_GET_XCRS: {
d1ac91d8 3328 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3329 r = -ENOMEM;
d1ac91d8 3330 if (!u.xcrs)
2d5b5a66
SY		 3331 break;
3332
d1ac91d8 3333 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3334
3335 r = -EFAULT;
d1ac91d8 3336 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3337 sizeof(struct kvm_xcrs)))
3338 break;
3339 r = 0;
3340 break;
3341 }
3342 case KVM_SET_XCRS: {
ff5c2c03 3343 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3344 if (IS_ERR(u.xcrs))
3345 return PTR_ERR(u.xcrs);
2d5b5a66 3346
d1ac91d8 3347 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3348 break;
3349 }
92a1f12d
JR		 3350 case KVM_SET_TSC_KHZ: {
3351 u32 user_tsc_khz;
3352
3353 r = -EINVAL;
92a1f12d
JR		 3354 user_tsc_khz = (u32)arg;
3355
3356 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3357 goto out;
3358
cc578287
ZA		 3359 if (user_tsc_khz == 0)
3360 user_tsc_khz = tsc_khz;
3361
3362 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3363
3364 r = 0;
3365 goto out;
3366 }
3367 case KVM_GET_TSC_KHZ: {
cc578287 3368 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3369 goto out;
3370 }
1c0b28c2
EM		 3371 case KVM_KVMCLOCK_CTRL: {
3372 r = kvm_set_guest_paused(vcpu);
3373 goto out;
3374 }
313a3dc7
CO		 3375 default:
3376 r = -EINVAL;
3377 }
3378out:
d1ac91d8 3379 kfree(u.buffer);
313a3dc7
CO		 3380 return r;
3381}
3382
5b1c1493
CO		 3383int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3384{
3385 return VM_FAULT_SIGBUS;
3386}
3387
1fe779f8
CO		 3388static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3389{
3390 int ret;
3391
3392 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3393 return -EINVAL;
1fe779f8
CO		 3394 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3395 return ret;
3396}
3397
b927a3ce
SY		 3398static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3399 u64 ident_addr)
3400{
3401 kvm->arch.ept_identity_map_addr = ident_addr;
3402 return 0;
3403}
3404
1fe779f8
CO		 3405static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3406 u32 kvm_nr_mmu_pages)
3407{
3408 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3409 return -EINVAL;
3410
79fac95e 3411 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3412
3413 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3414 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3415
79fac95e 3416 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3417 return 0;
3418}
3419
3420static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3421{
39de71ec 3422 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3423}
3424
1fe779f8
CO		 3425static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3426{
3427 int r;
3428
3429 r = 0;
3430 switch (chip->chip_id) {
3431 case KVM_IRQCHIP_PIC_MASTER:
3432 memcpy(&chip->chip.pic,
3433 &pic_irqchip(kvm)->pics[0],
3434 sizeof(struct kvm_pic_state));
3435 break;
3436 case KVM_IRQCHIP_PIC_SLAVE:
3437 memcpy(&chip->chip.pic,
3438 &pic_irqchip(kvm)->pics[1],
3439 sizeof(struct kvm_pic_state));
3440 break;
3441 case KVM_IRQCHIP_IOAPIC:
eba0226b 3442 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3443 break;
3444 default:
3445 r = -EINVAL;
3446 break;
3447 }
3448 return r;
3449}
3450
3451static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3452{
3453 int r;
3454
3455 r = 0;
3456 switch (chip->chip_id) {
3457 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3458 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3459 memcpy(&pic_irqchip(kvm)->pics[0],
3460 &chip->chip.pic,
3461 sizeof(struct kvm_pic_state));
f4f51050 3462 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3463 break;
3464 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3465 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3466 memcpy(&pic_irqchip(kvm)->pics[1],
3467 &chip->chip.pic,
3468 sizeof(struct kvm_pic_state));
f4f51050 3469 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3470 break;
3471 case KVM_IRQCHIP_IOAPIC:
eba0226b 3472 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3473 break;
3474 default:
3475 r = -EINVAL;
3476 break;
3477 }
3478 kvm_pic_update_irq(pic_irqchip(kvm));
3479 return r;
3480}
3481
e0f63cb9
SY		 3482static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3483{
3484 int r = 0;
3485
894a9c55 3486 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3487 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3488 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3489 return r;
3490}
3491
3492static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3493{
3494 int r = 0;
3495
894a9c55 3496 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3497 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3498 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3499 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3500 return r;
3501}
3502
3503static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3504{
3505 int r = 0;
3506
3507 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3508 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3509 sizeof(ps->channels));
3510 ps->flags = kvm->arch.vpit->pit_state.flags;
3511 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3512 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3513 return r;
3514}
3515
3516static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3517{
3518 int r = 0, start = 0;
3519 u32 prev_legacy, cur_legacy;
3520 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3521 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3522 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3523 if (!prev_legacy && cur_legacy)
3524 start = 1;
3525 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3526 sizeof(kvm->arch.vpit->pit_state.channels));
3527 kvm->arch.vpit->pit_state.flags = ps->flags;
3528 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3529 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3530 return r;
3531}
3532
52d939a0
MT		 3533static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3534 struct kvm_reinject_control *control)
3535{
3536 if (!kvm->arch.vpit)
3537 return -ENXIO;
894a9c55 3538 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3539 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3540 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3541 return 0;
3542}
3543
95d4c16c 3544/**
60c34612
TY		 3545 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3546 * @kvm: kvm instance
3547 * @log: slot id and address to which we copy the log
95d4c16c 3548 *
60c34612
TY		 3549 * We need to keep it in mind that VCPU threads can write to the bitmap
3550 * concurrently. So, to avoid losing data, we keep the following order for
3551 * each bit:
95d4c16c 3552 *
60c34612
TY		 3553 * 1. Take a snapshot of the bit and clear it if needed.
3554 * 2. Write protect the corresponding page.
3555 * 3. Flush TLB's if needed.
3556 * 4. Copy the snapshot to the userspace.
95d4c16c 3557 *
60c34612
TY		 3558 * Between 2 and 3, the guest may write to the page using the remaining TLB
3559 * entry. This is not a problem because the page will be reported dirty at
3560 * step 4 using the snapshot taken before and step 3 ensures that successive
3561 * writes will be logged for the next call.
5bb064dc 3562 */
60c34612 3563int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3564{
7850ac54 3565 int r;
5bb064dc 3566 struct kvm_memory_slot *memslot;
60c34612
TY		 3567 unsigned long n, i;
3568 unsigned long *dirty_bitmap;
3569 unsigned long *dirty_bitmap_buffer;
3570 bool is_dirty = false;
5bb064dc 3571
79fac95e 3572 mutex_lock(&kvm->slots_lock);
5bb064dc 3573
b050b015 3574 r = -EINVAL;
bbacc0c1 3575 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3576 goto out;
3577
28a37544 3578 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3579
3580 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3581 r = -ENOENT;
60c34612 3582 if (!dirty_bitmap)
b050b015
MT		 3583 goto out;
3584
87bf6e7d 3585 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3586
60c34612
TY		 3587 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3588 memset(dirty_bitmap_buffer, 0, n);
b050b015 3589
60c34612 3590 spin_lock(&kvm->mmu_lock);
b050b015 3591
60c34612
TY		 3592 for (i = 0; i < n / sizeof(long); i++) {
3593 unsigned long mask;
3594 gfn_t offset;
cdfca7b3 3595
60c34612
TY		 3596 if (!dirty_bitmap[i])
3597 continue;
b050b015 3598
60c34612 3599 is_dirty = true;
914ebccd 3600
60c34612
TY		 3601 mask = xchg(&dirty_bitmap[i], 0);
3602 dirty_bitmap_buffer[i] = mask;
edde99ce 3603
60c34612
TY		 3604 offset = i * BITS_PER_LONG;
3605 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3606 }
60c34612
TY		 3607 if (is_dirty)
3608 kvm_flush_remote_tlbs(kvm);
3609
3610 spin_unlock(&kvm->mmu_lock);
3611
3612 r = -EFAULT;
3613 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3614 goto out;
b050b015 3615
5bb064dc
ZX		 3616 r = 0;
3617out:
79fac95e 3618 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3619 return r;
3620}
3621
aa2fbe6d
YZ		 3622int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3623 bool line_status)
23d43cf9
CD		 3624{
3625 if (!irqchip_in_kernel(kvm))
3626 return -ENXIO;
3627
3628 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3629 irq_event->irq, irq_event->level,
3630 line_status);
23d43cf9
CD		 3631 return 0;
3632}
3633
1fe779f8
CO		 3634long kvm_arch_vm_ioctl(struct file *filp,
3635 unsigned int ioctl, unsigned long arg)
3636{
3637 struct kvm *kvm = filp->private_data;
3638 void __user *argp = (void __user *)arg;
367e1319 3639 int r = -ENOTTY;
f0d66275
DH		 3640 /*
3641 * This union makes it completely explicit to gcc-3.x
3642 * that these two variables' stack usage should be
3643 * combined, not added together.
3644 */
3645 union {
3646 struct kvm_pit_state ps;
e9f42757 3647 struct kvm_pit_state2 ps2;
c5ff41ce 3648 struct kvm_pit_config pit_config;
f0d66275 3649 } u;
1fe779f8
CO		 3650
3651 switch (ioctl) {
3652 case KVM_SET_TSS_ADDR:
3653 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3654 break;
b927a3ce
SY		 3655 case KVM_SET_IDENTITY_MAP_ADDR: {
3656 u64 ident_addr;
3657
3658 r = -EFAULT;
3659 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3660 goto out;
3661 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3662 break;
3663 }
1fe779f8
CO		 3664 case KVM_SET_NR_MMU_PAGES:
3665 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3666 break;
3667 case KVM_GET_NR_MMU_PAGES:
3668 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3669 break;
3ddea128
MT		 3670 case KVM_CREATE_IRQCHIP: {
3671 struct kvm_pic *vpic;
3672
3673 mutex_lock(&kvm->lock);
3674 r = -EEXIST;
3675 if (kvm->arch.vpic)
3676 goto create_irqchip_unlock;
3e515705
AK		 3677 r = -EINVAL;
3678 if (atomic_read(&kvm->online_vcpus))
3679 goto create_irqchip_unlock;
1fe779f8 3680 r = -ENOMEM;
3ddea128
MT		 3681 vpic = kvm_create_pic(kvm);
3682 if (vpic) {
1fe779f8
CO		 3683 r = kvm_ioapic_init(kvm);
3684 if (r) {
175504cd 3685 mutex_lock(&kvm->slots_lock);
72bb2fcd 3686 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3687 &vpic->dev_master);
3688 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3689 &vpic->dev_slave);
3690 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3691 &vpic->dev_eclr);
175504cd 3692 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3693 kfree(vpic);
3694 goto create_irqchip_unlock;
1fe779f8
CO		 3695 }
3696 } else
3ddea128
MT		 3697 goto create_irqchip_unlock;
3698 smp_wmb();
3699 kvm->arch.vpic = vpic;
3700 smp_wmb();
399ec807
AK		 3701 r = kvm_setup_default_irq_routing(kvm);
3702 if (r) {
175504cd 3703 mutex_lock(&kvm->slots_lock);
3ddea128 3704 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3705 kvm_ioapic_destroy(kvm);
3706 kvm_destroy_pic(kvm);
3ddea128 3707 mutex_unlock(&kvm->irq_lock);
175504cd 3708 mutex_unlock(&kvm->slots_lock);
399ec807 3709 }
3ddea128
MT		 3710 create_irqchip_unlock:
3711 mutex_unlock(&kvm->lock);
1fe779f8 3712 break;
3ddea128 3713 }
7837699f 3714 case KVM_CREATE_PIT:
c5ff41ce
JK		 3715 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3716 goto create_pit;
3717 case KVM_CREATE_PIT2:
3718 r = -EFAULT;
3719 if (copy_from_user(&u.pit_config, argp,
3720 sizeof(struct kvm_pit_config)))
3721 goto out;
3722 create_pit:
79fac95e 3723 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3724 r = -EEXIST;
3725 if (kvm->arch.vpit)
3726 goto create_pit_unlock;
7837699f 3727 r = -ENOMEM;
c5ff41ce 3728 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3729 if (kvm->arch.vpit)
3730 r = 0;
269e05e4 3731 create_pit_unlock:
79fac95e 3732 mutex_unlock(&kvm->slots_lock);
7837699f 3733 break;
1fe779f8
CO		 3734 case KVM_GET_IRQCHIP: {
3735 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3736 struct kvm_irqchip *chip;
1fe779f8 3737
ff5c2c03
SL		 3738 chip = memdup_user(argp, sizeof(*chip));
3739 if (IS_ERR(chip)) {
3740 r = PTR_ERR(chip);
1fe779f8 3741 goto out;
ff5c2c03
SL		 3742 }
3743
1fe779f8
CO		 3744 r = -ENXIO;
3745 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3746 goto get_irqchip_out;
3747 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3748 if (r)
f0d66275 3749 goto get_irqchip_out;
1fe779f8 3750 r = -EFAULT;
f0d66275
DH		 3751 if (copy_to_user(argp, chip, sizeof *chip))
3752 goto get_irqchip_out;
1fe779f8 3753 r = 0;
f0d66275
DH		 3754 get_irqchip_out:
3755 kfree(chip);
1fe779f8
CO		 3756 break;
3757 }
3758 case KVM_SET_IRQCHIP: {
3759 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3760 struct kvm_irqchip *chip;
1fe779f8 3761
ff5c2c03
SL		 3762 chip = memdup_user(argp, sizeof(*chip));
3763 if (IS_ERR(chip)) {
3764 r = PTR_ERR(chip);
1fe779f8 3765 goto out;
ff5c2c03
SL		 3766 }
3767
1fe779f8
CO		 3768 r = -ENXIO;
3769 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3770 goto set_irqchip_out;
3771 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3772 if (r)
f0d66275 3773 goto set_irqchip_out;
1fe779f8 3774 r = 0;
f0d66275
DH		 3775 set_irqchip_out:
3776 kfree(chip);
1fe779f8
CO		 3777 break;
3778 }
e0f63cb9 3779 case KVM_GET_PIT: {
e0f63cb9 3780 r = -EFAULT;
f0d66275 3781 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3782 goto out;
3783 r = -ENXIO;
3784 if (!kvm->arch.vpit)
3785 goto out;
f0d66275 3786 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3787 if (r)
3788 goto out;
3789 r = -EFAULT;
f0d66275 3790 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3791 goto out;
3792 r = 0;
3793 break;
3794 }
3795 case KVM_SET_PIT: {
e0f63cb9 3796 r = -EFAULT;
f0d66275 3797 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3798 goto out;
3799 r = -ENXIO;
3800 if (!kvm->arch.vpit)
3801 goto out;
f0d66275 3802 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3803 break;
3804 }
e9f42757
BK		 3805 case KVM_GET_PIT2: {
3806 r = -ENXIO;
3807 if (!kvm->arch.vpit)
3808 goto out;
3809 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3810 if (r)
3811 goto out;
3812 r = -EFAULT;
3813 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3814 goto out;
3815 r = 0;
3816 break;
3817 }
3818 case KVM_SET_PIT2: {
3819 r = -EFAULT;
3820 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3821 goto out;
3822 r = -ENXIO;
3823 if (!kvm->arch.vpit)
3824 goto out;
3825 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3826 break;
3827 }
52d939a0
MT		 3828 case KVM_REINJECT_CONTROL: {
3829 struct kvm_reinject_control control;
3830 r = -EFAULT;
3831 if (copy_from_user(&control, argp, sizeof(control)))
3832 goto out;
3833 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3834 break;
3835 }
ffde22ac
ES		 3836 case KVM_XEN_HVM_CONFIG: {
3837 r = -EFAULT;
3838 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3839 sizeof(struct kvm_xen_hvm_config)))
3840 goto out;
3841 r = -EINVAL;
3842 if (kvm->arch.xen_hvm_config.flags)
3843 goto out;
3844 r = 0;
3845 break;
3846 }
afbcf7ab 3847 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3848 struct kvm_clock_data user_ns;
3849 u64 now_ns;
3850 s64 delta;
3851
3852 r = -EFAULT;
3853 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3854 goto out;
3855
3856 r = -EINVAL;
3857 if (user_ns.flags)
3858 goto out;
3859
3860 r = 0;
395c6b0a 3861 local_irq_disable();
759379dd 3862 now_ns = get_kernel_ns();
afbcf7ab 3863 delta = user_ns.clock - now_ns;
395c6b0a 3864 local_irq_enable();
afbcf7ab 3865 kvm->arch.kvmclock_offset = delta;
2e762ff7 3866 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3867 break;
3868 }
3869 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3870 struct kvm_clock_data user_ns;
3871 u64 now_ns;
3872
395c6b0a 3873 local_irq_disable();
759379dd 3874 now_ns = get_kernel_ns();
afbcf7ab 3875 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3876 local_irq_enable();
afbcf7ab 3877 user_ns.flags = 0;
97e69aa6 3878 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3879
3880 r = -EFAULT;
3881 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3882 goto out;
3883 r = 0;
3884 break;
3885 }
3886
1fe779f8
CO		 3887 default:
3888 ;
3889 }
3890out:
3891 return r;
3892}
3893
a16b043c 3894static void kvm_init_msr_list(void)
043405e1
CO		 3895{
3896 u32 dummy[2];
3897 unsigned i, j;
3898
e3267cbb
GC		 3899 /* skip the first msrs in the list. KVM-specific */
3900 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3901 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3902 continue;
3903 if (j < i)
3904 msrs_to_save[j] = msrs_to_save[i];
3905 j++;
3906 }
3907 num_msrs_to_save = j;
3908}
3909
bda9020e
MT		 3910static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3911 const void *v)
bbd9b64e 3912{
70252a10
AK		 3913 int handled = 0;
3914 int n;
3915
3916 do {
3917 n = min(len, 8);
3918 if (!(vcpu->arch.apic &&
3919 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3920 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3921 break;
3922 handled += n;
3923 addr += n;
3924 len -= n;
3925 v += n;
3926 } while (len);
bbd9b64e 3927
70252a10 3928 return handled;
bbd9b64e
CO		 3929}
3930
bda9020e 3931static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3932{
70252a10
AK		 3933 int handled = 0;
3934 int n;
3935
3936 do {
3937 n = min(len, 8);
3938 if (!(vcpu->arch.apic &&
3939 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3940 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3941 break;
3942 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3943 handled += n;
3944 addr += n;
3945 len -= n;
3946 v += n;
3947 } while (len);
bbd9b64e 3948
70252a10 3949 return handled;
bbd9b64e
CO		 3950}
3951
2dafc6c2
GN		 3952static void kvm_set_segment(struct kvm_vcpu *vcpu,
3953 struct kvm_segment *var, int seg)
3954{
3955 kvm_x86_ops->set_segment(vcpu, var, seg);
3956}
3957
3958void kvm_get_segment(struct kvm_vcpu *vcpu,
3959 struct kvm_segment *var, int seg)
3960{
3961 kvm_x86_ops->get_segment(vcpu, var, seg);
3962}
3963
e459e322 3964gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3965{
3966 gpa_t t_gpa;
ab9ae313 3967 struct x86_exception exception;
02f59dc9
JR		 3968
3969 BUG_ON(!mmu_is_nested(vcpu));
3970
3971 /* NPT walks are always user-walks */
3972 access |= PFERR_USER_MASK;
ab9ae313 3973 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3974
3975 return t_gpa;
3976}
3977
ab9ae313
AK		 3978gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3979 struct x86_exception *exception)
1871c602
GN		 3980{
3981 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3982 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3983}
3984
ab9ae313
AK		 3985 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3986 struct x86_exception *exception)
1871c602
GN		 3987{
3988 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3989 access |= PFERR_FETCH_MASK;
ab9ae313 3990 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3991}
3992
ab9ae313
AK		 3993gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3994 struct x86_exception *exception)
1871c602
GN		 3995{
3996 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3997 access |= PFERR_WRITE_MASK;
ab9ae313 3998 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3999}
4000
4001/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4002gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4003 struct x86_exception *exception)
1871c602 4004{
ab9ae313 4005 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4006}
4007
4008static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4009 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4010 struct x86_exception *exception)
bbd9b64e
CO		 4011{
4012 void *data = val;
10589a46 4013 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4014
4015 while (bytes) {
14dfe855 4016 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4017 exception);
bbd9b64e 4018 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4019 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4020 int ret;
4021
bcc55cba 4022 if (gpa == UNMAPPED_GVA)
ab9ae313 4023 return X86EMUL_PROPAGATE_FAULT;
77c2002e 4024 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 4025 if (ret < 0) {
c3cd7ffa 4026 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4027 goto out;
4028 }
bbd9b64e 4029
77c2002e
IE		 4030 bytes -= toread;
4031 data += toread;
4032 addr += toread;
bbd9b64e 4033 }
10589a46 4034out:
10589a46 4035 return r;
bbd9b64e 4036}
77c2002e 4037
1871c602 4038/* used for instruction fetching */
0f65dd70
AK		 4039static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4040 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4041 struct x86_exception *exception)
1871c602 4042{
0f65dd70 4043 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4044 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4045
1871c602 4046 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 4047 access | PFERR_FETCH_MASK,
4048 exception);
1871c602
GN		 4049}
4050
064aea77 4051int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4052 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4053 struct x86_exception *exception)
1871c602 4054{
0f65dd70 4055 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4056 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4057
1871c602 4058 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4059 exception);
1871c602 4060}
064aea77 4061EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4062
0f65dd70
AK		 4063static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4064 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4065 struct x86_exception *exception)
1871c602 4066{
0f65dd70 4067 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4068 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4069}
4070
6a4d7550 4071int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4072 gva_t addr, void *val,
2dafc6c2 4073 unsigned int bytes,
bcc55cba 4074 struct x86_exception *exception)
77c2002e 4075{
0f65dd70 4076 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4077 void *data = val;
4078 int r = X86EMUL_CONTINUE;
4079
4080 while (bytes) {
14dfe855
JR		 4081 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4082 PFERR_WRITE_MASK,
ab9ae313 4083 exception);
77c2002e
IE		 4084 unsigned offset = addr & (PAGE_SIZE-1);
4085 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4086 int ret;
4087
bcc55cba 4088 if (gpa == UNMAPPED_GVA)
ab9ae313 4089 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4090 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4091 if (ret < 0) {
c3cd7ffa 4092 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4093 goto out;
4094 }
4095
4096 bytes -= towrite;
4097 data += towrite;
4098 addr += towrite;
4099 }
4100out:
4101 return r;
4102}
6a4d7550 4103EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4104
af7cc7d1
XG		 4105static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4106 gpa_t *gpa, struct x86_exception *exception,
4107 bool write)
4108{
97d64b78
AK		 4109 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4110 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4111
97d64b78
AK		 4112 if (vcpu_match_mmio_gva(vcpu, gva)
4113 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
bebb106a
XG		 4114 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4115 (gva & (PAGE_SIZE - 1));
4f022648 4116 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4117 return 1;
4118 }
4119
af7cc7d1
XG		 4120 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4121
4122 if (*gpa == UNMAPPED_GVA)
4123 return -1;
4124
4125 /* For APIC access vmexit */
4126 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4127 return 1;
4128
4f022648
XG		 4129 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4130 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4131 return 1;
4f022648 4132 }
bebb106a 4133
af7cc7d1
XG		 4134 return 0;
4135}
4136
3200f405 4137int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4138 const void *val, int bytes)
bbd9b64e
CO		 4139{
4140 int ret;
4141
4142 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4143 if (ret < 0)
bbd9b64e 4144 return 0;
f57f2ef5 4145 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4146 return 1;
4147}
4148
77d197b2
XG		 4149struct read_write_emulator_ops {
4150 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4151 int bytes);
4152 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4153 void *val, int bytes);
4154 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4155 int bytes, void *val);
4156 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4157 void *val, int bytes);
4158 bool write;
4159};
4160
4161static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4162{
4163 if (vcpu->mmio_read_completed) {
77d197b2 4164 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4165 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4166 vcpu->mmio_read_completed = 0;
4167 return 1;
4168 }
4169
4170 return 0;
4171}
4172
4173static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4174 void *val, int bytes)
4175{
4176 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4177}
4178
4179static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4180 void *val, int bytes)
4181{
4182 return emulator_write_phys(vcpu, gpa, val, bytes);
4183}
4184
4185static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4186{
4187 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4188 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4189}
4190
4191static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4192 void *val, int bytes)
4193{
4194 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4195 return X86EMUL_IO_NEEDED;
4196}
4197
4198static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4199 void *val, int bytes)
4200{
f78146b0
AK		 4201 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4202
87da7e66 4203 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4204 return X86EMUL_CONTINUE;
4205}
4206
0fbe9b0b 4207static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4208 .read_write_prepare = read_prepare,
4209 .read_write_emulate = read_emulate,
4210 .read_write_mmio = vcpu_mmio_read,
4211 .read_write_exit_mmio = read_exit_mmio,
4212};
4213
0fbe9b0b 4214static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4215 .read_write_emulate = write_emulate,
4216 .read_write_mmio = write_mmio,
4217 .read_write_exit_mmio = write_exit_mmio,
4218 .write = true,
4219};
4220
22388a3c
XG		 4221static int emulator_read_write_onepage(unsigned long addr, void *val,
4222 unsigned int bytes,
4223 struct x86_exception *exception,
4224 struct kvm_vcpu *vcpu,
0fbe9b0b 4225 const struct read_write_emulator_ops *ops)
bbd9b64e 4226{
af7cc7d1
XG		 4227 gpa_t gpa;
4228 int handled, ret;
22388a3c 4229 bool write = ops->write;
f78146b0 4230 struct kvm_mmio_fragment *frag;
10589a46 4231
22388a3c 4232 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4233
af7cc7d1 4234 if (ret < 0)
bbd9b64e 4235 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4236
4237 /* For APIC access vmexit */
af7cc7d1 4238 if (ret)
bbd9b64e
CO		 4239 goto mmio;
4240
22388a3c 4241 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4242 return X86EMUL_CONTINUE;
4243
4244mmio:
4245 /*
4246 * Is this MMIO handled locally?
4247 */
22388a3c 4248 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4249 if (handled == bytes)
bbd9b64e 4250 return X86EMUL_CONTINUE;
bbd9b64e 4251
70252a10
AK		 4252 gpa += handled;
4253 bytes -= handled;
4254 val += handled;
4255
87da7e66
XG		 4256 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4257 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4258 frag->gpa = gpa;
4259 frag->data = val;
4260 frag->len = bytes;
f78146b0 4261 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4262}
4263
22388a3c
XG		 4264int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4265 void *val, unsigned int bytes,
4266 struct x86_exception *exception,
0fbe9b0b 4267 const struct read_write_emulator_ops *ops)
bbd9b64e 4268{
0f65dd70 4269 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4270 gpa_t gpa;
4271 int rc;
4272
4273 if (ops->read_write_prepare &&
4274 ops->read_write_prepare(vcpu, val, bytes))
4275 return X86EMUL_CONTINUE;
4276
4277 vcpu->mmio_nr_fragments = 0;
0f65dd70 4278
bbd9b64e
CO		 4279 /* Crossing a page boundary? */
4280 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4281 int now;
bbd9b64e
CO		 4282
4283 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4284 rc = emulator_read_write_onepage(addr, val, now, exception,
4285 vcpu, ops);
4286
bbd9b64e
CO		 4287 if (rc != X86EMUL_CONTINUE)
4288 return rc;
4289 addr += now;
4290 val += now;
4291 bytes -= now;
4292 }
22388a3c 4293
f78146b0
AK		 4294 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4295 vcpu, ops);
4296 if (rc != X86EMUL_CONTINUE)
4297 return rc;
4298
4299 if (!vcpu->mmio_nr_fragments)
4300 return rc;
4301
4302 gpa = vcpu->mmio_fragments[0].gpa;
4303
4304 vcpu->mmio_needed = 1;
4305 vcpu->mmio_cur_fragment = 0;
4306
87da7e66 4307 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4308 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4309 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4310 vcpu->run->mmio.phys_addr = gpa;
4311
4312 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4313}
4314
4315static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4316 unsigned long addr,
4317 void *val,
4318 unsigned int bytes,
4319 struct x86_exception *exception)
4320{
4321 return emulator_read_write(ctxt, addr, val, bytes,
4322 exception, &read_emultor);
4323}
4324
4325int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4326 unsigned long addr,
4327 const void *val,
4328 unsigned int bytes,
4329 struct x86_exception *exception)
4330{
4331 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4332 exception, &write_emultor);
bbd9b64e 4333}
bbd9b64e 4334
daea3e73
AK		 4335#define CMPXCHG_TYPE(t, ptr, old, new) \
4336 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4337
4338#ifdef CONFIG_X86_64
4339# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4340#else
4341# define CMPXCHG64(ptr, old, new) \
9749a6c0 4342 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4343#endif
4344
0f65dd70
AK		 4345static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4346 unsigned long addr,
bbd9b64e
CO		 4347 const void *old,
4348 const void *new,
4349 unsigned int bytes,
0f65dd70 4350 struct x86_exception *exception)
bbd9b64e 4351{
0f65dd70 4352 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4353 gpa_t gpa;
4354 struct page *page;
4355 char *kaddr;
4356 bool exchanged;
2bacc55c 4357
daea3e73
AK		 4358 /* guests cmpxchg8b have to be emulated atomically */
4359 if (bytes > 8 || (bytes & (bytes - 1)))
4360 goto emul_write;
10589a46 4361
daea3e73 4362 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4363
daea3e73
AK		 4364 if (gpa == UNMAPPED_GVA ||
4365 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4366 goto emul_write;
2bacc55c 4367
daea3e73
AK		 4368 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4369 goto emul_write;
72dc67a6 4370
daea3e73 4371 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4372 if (is_error_page(page))
c19b8bd6 4373 goto emul_write;
72dc67a6 4374
8fd75e12 4375 kaddr = kmap_atomic(page);
daea3e73
AK		 4376 kaddr += offset_in_page(gpa);
4377 switch (bytes) {
4378 case 1:
4379 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4380 break;
4381 case 2:
4382 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4383 break;
4384 case 4:
4385 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4386 break;
4387 case 8:
4388 exchanged = CMPXCHG64(kaddr, old, new);
4389 break;
4390 default:
4391 BUG();
2bacc55c 4392 }
8fd75e12 4393 kunmap_atomic(kaddr);
daea3e73
AK		 4394 kvm_release_page_dirty(page);
4395
4396 if (!exchanged)
4397 return X86EMUL_CMPXCHG_FAILED;
4398
f57f2ef5 4399 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4400
4401 return X86EMUL_CONTINUE;
4a5f48f6 4402
3200f405 4403emul_write:
daea3e73 4404 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4405
0f65dd70 4406 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4407}
4408
cf8f70bf
GN		 4409static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4410{
4411 /* TODO: String I/O for in kernel device */
4412 int r;
4413
4414 if (vcpu->arch.pio.in)
4415 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4416 vcpu->arch.pio.size, pd);
4417 else
4418 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4419 vcpu->arch.pio.port, vcpu->arch.pio.size,
4420 pd);
4421 return r;
4422}
4423
6f6fbe98
XG		 4424static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4425 unsigned short port, void *val,
4426 unsigned int count, bool in)
cf8f70bf 4427{
6f6fbe98 4428 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 4429
4430 vcpu->arch.pio.port = port;
6f6fbe98 4431 vcpu->arch.pio.in = in;
7972995b 4432 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4433 vcpu->arch.pio.size = size;
4434
4435 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4436 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4437 return 1;
4438 }
4439
4440 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4441 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4442 vcpu->run->io.size = size;
4443 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4444 vcpu->run->io.count = count;
4445 vcpu->run->io.port = port;
4446
4447 return 0;
4448}
4449
6f6fbe98
XG		 4450static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4451 int size, unsigned short port, void *val,
4452 unsigned int count)
cf8f70bf 4453{
ca1d4a9e 4454 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4455 int ret;
ca1d4a9e 4456
6f6fbe98
XG		 4457 if (vcpu->arch.pio.count)
4458 goto data_avail;
cf8f70bf 4459
6f6fbe98
XG		 4460 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4461 if (ret) {
4462data_avail:
4463 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4464 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4465 return 1;
4466 }
4467
cf8f70bf
GN		 4468 return 0;
4469}
4470
6f6fbe98
XG		 4471static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4472 int size, unsigned short port,
4473 const void *val, unsigned int count)
4474{
4475 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4476
4477 memcpy(vcpu->arch.pio_data, val, size * count);
4478 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4479}
4480
bbd9b64e
CO		 4481static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4482{
4483 return kvm_x86_ops->get_segment_base(vcpu, seg);
4484}
4485
3cb16fe7 4486static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4487{
3cb16fe7 4488 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4489}
4490
f5f48ee1
SY		 4491int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4492{
4493 if (!need_emulate_wbinvd(vcpu))
4494 return X86EMUL_CONTINUE;
4495
4496 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4497 int cpu = get_cpu();
4498
4499 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4500 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4501 wbinvd_ipi, NULL, 1);
2eec7343 4502 put_cpu();
f5f48ee1 4503 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4504 } else
4505 wbinvd();
f5f48ee1
SY		 4506 return X86EMUL_CONTINUE;
4507}
4508EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4509
bcaf5cc5
AK		 4510static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4511{
4512 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4513}
4514
717746e3 4515int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4516{
717746e3 4517 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4518}
4519
717746e3 4520int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4521{
338dbc97 4522
717746e3 4523 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4524}
4525
52a46617 4526static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4527{
52a46617 4528 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4529}
4530
717746e3 4531static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4532{
717746e3 4533 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4534 unsigned long value;
4535
4536 switch (cr) {
4537 case 0:
4538 value = kvm_read_cr0(vcpu);
4539 break;
4540 case 2:
4541 value = vcpu->arch.cr2;
4542 break;
4543 case 3:
9f8fe504 4544 value = kvm_read_cr3(vcpu);
52a46617
GN		 4545 break;
4546 case 4:
4547 value = kvm_read_cr4(vcpu);
4548 break;
4549 case 8:
4550 value = kvm_get_cr8(vcpu);
4551 break;
4552 default:
a737f256 4553 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4554 return 0;
4555 }
4556
4557 return value;
4558}
4559
717746e3 4560static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4561{
717746e3 4562 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4563 int res = 0;
4564
52a46617
GN		 4565 switch (cr) {
4566 case 0:
49a9b07e 4567 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4568 break;
4569 case 2:
4570 vcpu->arch.cr2 = val;
4571 break;
4572 case 3:
2390218b 4573 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4574 break;
4575 case 4:
a83b29c6 4576 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4577 break;
4578 case 8:
eea1cff9 4579 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4580 break;
4581 default:
a737f256 4582 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4583 res = -1;
52a46617 4584 }
0f12244f
GN		 4585
4586 return res;
52a46617
GN		 4587}
4588
4cee4798
KW		 4589static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4590{
4591 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4592}
4593
717746e3 4594static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4595{
717746e3 4596 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4597}
4598
4bff1e86 4599static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4600{
4bff1e86 4601 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4602}
4603
4bff1e86 4604static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4605{
4bff1e86 4606 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4607}
4608
1ac9d0cf
AK		 4609static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4610{
4611 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4612}
4613
4614static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4615{
4616 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4617}
4618
4bff1e86
AK		 4619static unsigned long emulator_get_cached_segment_base(
4620 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4621{
4bff1e86 4622 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4623}
4624
1aa36616
AK		 4625static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4626 struct desc_struct *desc, u32 *base3,
4627 int seg)
2dafc6c2
GN		 4628{
4629 struct kvm_segment var;
4630
4bff1e86 4631 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4632 *selector = var.selector;
2dafc6c2 4633
378a8b09
GN		 4634 if (var.unusable) {
4635 memset(desc, 0, sizeof(*desc));
2dafc6c2 4636 return false;
378a8b09 4637 }
2dafc6c2
GN		 4638
4639 if (var.g)
4640 var.limit >>= 12;
4641 set_desc_limit(desc, var.limit);
4642 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4643#ifdef CONFIG_X86_64
4644 if (base3)
4645 *base3 = var.base >> 32;
4646#endif
2dafc6c2
GN		 4647 desc->type = var.type;
4648 desc->s = var.s;
4649 desc->dpl = var.dpl;
4650 desc->p = var.present;
4651 desc->avl = var.avl;
4652 desc->l = var.l;
4653 desc->d = var.db;
4654 desc->g = var.g;
4655
4656 return true;
4657}
4658
1aa36616
AK		 4659static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4660 struct desc_struct *desc, u32 base3,
4661 int seg)
2dafc6c2 4662{
4bff1e86 4663 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4664 struct kvm_segment var;
4665
1aa36616 4666 var.selector = selector;
2dafc6c2 4667 var.base = get_desc_base(desc);
5601d05b
GN		 4668#ifdef CONFIG_X86_64
4669 var.base |= ((u64)base3) << 32;
4670#endif
2dafc6c2
GN		 4671 var.limit = get_desc_limit(desc);
4672 if (desc->g)
4673 var.limit = (var.limit << 12) | 0xfff;
4674 var.type = desc->type;
4675 var.present = desc->p;
4676 var.dpl = desc->dpl;
4677 var.db = desc->d;
4678 var.s = desc->s;
4679 var.l = desc->l;
4680 var.g = desc->g;
4681 var.avl = desc->avl;
4682 var.present = desc->p;
4683 var.unusable = !var.present;
4684 var.padding = 0;
4685
4686 kvm_set_segment(vcpu, &var, seg);
4687 return;
4688}
4689
717746e3
AK		 4690static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4691 u32 msr_index, u64 *pdata)
4692{
4693 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4694}
4695
4696static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4697 u32 msr_index, u64 data)
4698{
8fe8ab46
WA		 4699 struct msr_data msr;
4700
4701 msr.data = data;
4702 msr.index = msr_index;
4703 msr.host_initiated = false;
4704 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4705}
4706
222d21aa
AK		 4707static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4708 u32 pmc, u64 *pdata)
4709{
4710 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4711}
4712
6c3287f7
AK		 4713static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4714{
4715 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4716}
4717
5037f6f3
AK		 4718static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4719{
4720 preempt_disable();
5197b808 4721 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4722 /*
4723 * CR0.TS may reference the host fpu state, not the guest fpu state,
4724 * so it may be clear at this point.
4725 */
4726 clts();
4727}
4728
4729static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4730{
4731 preempt_enable();
4732}
4733
2953538e 4734static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4735 struct x86_instruction_info *info,
c4f035c6
AK		 4736 enum x86_intercept_stage stage)
4737{
2953538e 4738 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4739}
4740
0017f93a 4741static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4742 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4743{
0017f93a 4744 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4745}
4746
dd856efa
AK		 4747static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4748{
4749 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4750}
4751
4752static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4753{
4754 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4755}
4756
0225fb50 4757static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4758 .read_gpr = emulator_read_gpr,
4759 .write_gpr = emulator_write_gpr,
1871c602 4760 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4761 .write_std = kvm_write_guest_virt_system,
1871c602 4762 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4763 .read_emulated = emulator_read_emulated,
4764 .write_emulated = emulator_write_emulated,
4765 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4766 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4767 .pio_in_emulated = emulator_pio_in_emulated,
4768 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4769 .get_segment = emulator_get_segment,
4770 .set_segment = emulator_set_segment,
5951c442 4771 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4772 .get_gdt = emulator_get_gdt,
160ce1f1 4773 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4774 .set_gdt = emulator_set_gdt,
4775 .set_idt = emulator_set_idt,
52a46617
GN		 4776 .get_cr = emulator_get_cr,
4777 .set_cr = emulator_set_cr,
4cee4798 4778 .set_rflags = emulator_set_rflags,
9c537244 4779 .cpl = emulator_get_cpl,
35aa5375
GN		 4780 .get_dr = emulator_get_dr,
4781 .set_dr = emulator_set_dr,
717746e3
AK		 4782 .set_msr = emulator_set_msr,
4783 .get_msr = emulator_get_msr,
222d21aa 4784 .read_pmc = emulator_read_pmc,
6c3287f7 4785 .halt = emulator_halt,
bcaf5cc5 4786 .wbinvd = emulator_wbinvd,
d6aa1000 4787 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4788 .get_fpu = emulator_get_fpu,
4789 .put_fpu = emulator_put_fpu,
c4f035c6 4790 .intercept = emulator_intercept,
bdb42f5a 4791 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4792};
4793
95cb2295
GN		 4794static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4795{
4796 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4797 /*
4798 * an sti; sti; sequence only disable interrupts for the first
4799 * instruction. So, if the last instruction, be it emulated or
4800 * not, left the system with the INT_STI flag enabled, it
4801 * means that the last instruction is an sti. We should not
4802 * leave the flag on in this case. The same goes for mov ss
4803 */
4804 if (!(int_shadow & mask))
4805 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4806}
4807
54b8486f
GN		 4808static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4809{
4810 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4811 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4812 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4813 else if (ctxt->exception.error_code_valid)
4814 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4815 ctxt->exception.error_code);
54b8486f 4816 else
da9cb575 4817 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4818}
4819
dd856efa 4820static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
b5c9ff73 4821{
1ce19dc1
BP		 4822 memset(&ctxt->opcode_len, 0,
4823 (void *)&ctxt->_regs - (void *)&ctxt->opcode_len);
b5c9ff73 4824
9dac77fa
AK		 4825 ctxt->fetch.start = 0;
4826 ctxt->fetch.end = 0;
4827 ctxt->io_read.pos = 0;
4828 ctxt->io_read.end = 0;
4829 ctxt->mem_read.pos = 0;
4830 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4831}
4832
8ec4722d
MG		 4833static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4834{
adf52235 4835 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4836 int cs_db, cs_l;
4837
8ec4722d
MG		 4838 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4839
adf52235
TY		 4840 ctxt->eflags = kvm_get_rflags(vcpu);
4841 ctxt->eip = kvm_rip_read(vcpu);
4842 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4843 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4844 cs_l ? X86EMUL_MODE_PROT64 :
4845 cs_db ? X86EMUL_MODE_PROT32 :
4846 X86EMUL_MODE_PROT16;
4847 ctxt->guest_mode = is_guest_mode(vcpu);
4848
dd856efa 4849 init_decode_cache(ctxt);
7ae441ea 4850 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4851}
4852
71f9833b 4853int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4854{
9d74191a 4855 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4856 int ret;
4857
4858 init_emulate_ctxt(vcpu);
4859
9dac77fa
AK		 4860 ctxt->op_bytes = 2;
4861 ctxt->ad_bytes = 2;
4862 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4863 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4864
4865 if (ret != X86EMUL_CONTINUE)
4866 return EMULATE_FAIL;
4867
9dac77fa 4868 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4869 kvm_rip_write(vcpu, ctxt->eip);
4870 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4871
4872 if (irq == NMI_VECTOR)
7460fb4a 4873 vcpu->arch.nmi_pending = 0;
63995653
MG		 4874 else
4875 vcpu->arch.interrupt.pending = false;
4876
4877 return EMULATE_DONE;
4878}
4879EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4880
6d77dbfc
GN		 4881static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4882{
fc3a9157
JR		 4883 int r = EMULATE_DONE;
4884
6d77dbfc
GN		 4885 ++vcpu->stat.insn_emulation_fail;
4886 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4887 if (!is_guest_mode(vcpu)) {
4888 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4889 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4890 vcpu->run->internal.ndata = 0;
4891 r = EMULATE_FAIL;
4892 }
6d77dbfc 4893 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4894
4895 return r;
6d77dbfc
GN		 4896}
4897
93c05d3e 4898static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4899 bool write_fault_to_shadow_pgtable,
4900 int emulation_type)
a6f177ef 4901{
95b3cf69 4902 gpa_t gpa = cr2;
8e3d9d06 4903 pfn_t pfn;
a6f177ef 4904
991eebf9
GN		 4905 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4906 return false;
4907
95b3cf69
XG		 4908 if (!vcpu->arch.mmu.direct_map) {
4909 /*
4910 * Write permission should be allowed since only
4911 * write access need to be emulated.
4912 */
4913 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 4914
95b3cf69
XG		 4915 /*
4916 * If the mapping is invalid in guest, let cpu retry
4917 * it to generate fault.
4918 */
4919 if (gpa == UNMAPPED_GVA)
4920 return true;
4921 }
a6f177ef 4922
8e3d9d06
XG		 4923 /*
4924 * Do not retry the unhandleable instruction if it faults on the
4925 * readonly host memory, otherwise it will goto a infinite loop:
4926 * retry instruction -> write #PF -> emulation fail -> retry
4927 * instruction -> ...
4928 */
4929 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 4930
4931 /*
4932 * If the instruction failed on the error pfn, it can not be fixed,
4933 * report the error to userspace.
4934 */
4935 if (is_error_noslot_pfn(pfn))
4936 return false;
4937
4938 kvm_release_pfn_clean(pfn);
4939
4940 /* The instructions are well-emulated on direct mmu. */
4941 if (vcpu->arch.mmu.direct_map) {
4942 unsigned int indirect_shadow_pages;
4943
4944 spin_lock(&vcpu->kvm->mmu_lock);
4945 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4946 spin_unlock(&vcpu->kvm->mmu_lock);
4947
4948 if (indirect_shadow_pages)
4949 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4950
a6f177ef 4951 return true;
8e3d9d06 4952 }
a6f177ef 4953
95b3cf69
XG		 4954 /*
4955 * if emulation was due to access to shadowed page table
4956 * and it failed try to unshadow page and re-enter the
4957 * guest to let CPU execute the instruction.
4958 */
4959 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 4960
4961 /*
4962 * If the access faults on its page table, it can not
4963 * be fixed by unprotecting shadow page and it should
4964 * be reported to userspace.
4965 */
4966 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 4967}
4968
1cb3f3ae
XG		 4969static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4970 unsigned long cr2, int emulation_type)
4971{
4972 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4973 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4974
4975 last_retry_eip = vcpu->arch.last_retry_eip;
4976 last_retry_addr = vcpu->arch.last_retry_addr;
4977
4978 /*
4979 * If the emulation is caused by #PF and it is non-page_table
4980 * writing instruction, it means the VM-EXIT is caused by shadow
4981 * page protected, we can zap the shadow page and retry this
4982 * instruction directly.
4983 *
4984 * Note: if the guest uses a non-page-table modifying instruction
4985 * on the PDE that points to the instruction, then we will unmap
4986 * the instruction and go to an infinite loop. So, we cache the
4987 * last retried eip and the last fault address, if we meet the eip
4988 * and the address again, we can break out of the potential infinite
4989 * loop.
4990 */
4991 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4992
4993 if (!(emulation_type & EMULTYPE_RETRY))
4994 return false;
4995
4996 if (x86_page_table_writing_insn(ctxt))
4997 return false;
4998
4999 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5000 return false;
5001
5002 vcpu->arch.last_retry_eip = ctxt->eip;
5003 vcpu->arch.last_retry_addr = cr2;
5004
5005 if (!vcpu->arch.mmu.direct_map)
5006 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5007
22368028 5008 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5009
5010 return true;
5011}
5012
716d51ab
GN		 5013static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5014static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5015
4a1e10d5
PB		 5016static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5017 unsigned long *db)
5018{
5019 u32 dr6 = 0;
5020 int i;
5021 u32 enable, rwlen;
5022
5023 enable = dr7;
5024 rwlen = dr7 >> 16;
5025 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5026 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5027 dr6 |= (1 << i);
5028 return dr6;
5029}
5030
663f4c61
PB		 5031static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, int *r)
5032{
5033 struct kvm_run *kvm_run = vcpu->run;
5034
5035 /*
5036 * Use the "raw" value to see if TF was passed to the processor.
5037 * Note that the new value of the flags has not been saved yet.
5038 *
5039 * This is correct even for TF set by the guest, because "the
5040 * processor will not generate this exception after the instruction
5041 * that sets the TF flag".
5042 */
5043 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5044
5045 if (unlikely(rflags & X86_EFLAGS_TF)) {
5046 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5047 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1;
5048 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5049 kvm_run->debug.arch.exception = DB_VECTOR;
5050 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5051 *r = EMULATE_USER_EXIT;
5052 } else {
5053 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5054 /*
5055 * "Certain debug exceptions may clear bit 0-3. The
5056 * remaining contents of the DR6 register are never
5057 * cleared by the processor".
5058 */
5059 vcpu->arch.dr6 &= ~15;
5060 vcpu->arch.dr6 |= DR6_BS;
5061 kvm_queue_exception(vcpu, DB_VECTOR);
5062 }
5063 }
5064}
5065
4a1e10d5
PB		 5066static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5067{
5068 struct kvm_run *kvm_run = vcpu->run;
5069 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5070 u32 dr6 = 0;
5071
5072 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5073 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5074 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5075 vcpu->arch.guest_debug_dr7,
5076 vcpu->arch.eff_db);
5077
5078 if (dr6 != 0) {
5079 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5080 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5081 get_segment_base(vcpu, VCPU_SREG_CS);
5082
5083 kvm_run->debug.arch.exception = DB_VECTOR;
5084 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5085 *r = EMULATE_USER_EXIT;
5086 return true;
5087 }
5088 }
5089
5090 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) {
5091 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5092 vcpu->arch.dr7,
5093 vcpu->arch.db);
5094
5095 if (dr6 != 0) {
5096 vcpu->arch.dr6 &= ~15;
5097 vcpu->arch.dr6 |= dr6;
5098 kvm_queue_exception(vcpu, DB_VECTOR);
5099 *r = EMULATE_DONE;
5100 return true;
5101 }
5102 }
5103
5104 return false;
5105}
5106
51d8b661
AP		 5107int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5108 unsigned long cr2,
dc25e89e
AP		 5109 int emulation_type,
5110 void *insn,
5111 int insn_len)
bbd9b64e 5112{
95cb2295 5113 int r;
9d74191a 5114 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5115 bool writeback = true;
93c05d3e 5116 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5117
93c05d3e
XG		 5118 /*
5119 * Clear write_fault_to_shadow_pgtable here to ensure it is
5120 * never reused.
5121 */
5122 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5123 kvm_clear_exception_queue(vcpu);
8d7d8102 5124
571008da 5125 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5126 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5127
5128 /*
5129 * We will reenter on the same instruction since
5130 * we do not set complete_userspace_io. This does not
5131 * handle watchpoints yet, those would be handled in
5132 * the emulate_ops.
5133 */
5134 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5135 return r;
5136
9d74191a
TY		 5137 ctxt->interruptibility = 0;
5138 ctxt->have_exception = false;
5139 ctxt->perm_ok = false;
bbd9b64e 5140
b51e974f 5141 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5142
9d74191a 5143 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5144
e46479f8 5145 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5146 ++vcpu->stat.insn_emulation;
1d2887e2 5147 if (r != EMULATION_OK) {
4005996e
AK		 5148 if (emulation_type & EMULTYPE_TRAP_UD)
5149 return EMULATE_FAIL;
991eebf9
GN		 5150 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5151 emulation_type))
bbd9b64e 5152 return EMULATE_DONE;
6d77dbfc
GN		 5153 if (emulation_type & EMULTYPE_SKIP)
5154 return EMULATE_FAIL;
5155 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5156 }
5157 }
5158
ba8afb6b 5159 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5160 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 5161 return EMULATE_DONE;
5162 }
5163
1cb3f3ae
XG		 5164 if (retry_instruction(ctxt, cr2, emulation_type))
5165 return EMULATE_DONE;
5166
7ae441ea 5167 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5168 changes registers values during IO operation */
7ae441ea
GN		 5169 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5170 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5171 emulator_invalidate_register_cache(ctxt);
7ae441ea 5172 }
4d2179e1 5173
5cd21917 5174restart:
9d74191a 5175 r = x86_emulate_insn(ctxt);
bbd9b64e 5176
775fde86
JR		 5177 if (r == EMULATION_INTERCEPTED)
5178 return EMULATE_DONE;
5179
d2ddd1c4 5180 if (r == EMULATION_FAILED) {
991eebf9
GN		 5181 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5182 emulation_type))
c3cd7ffa
GN		 5183 return EMULATE_DONE;
5184
6d77dbfc 5185 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5186 }
5187
9d74191a 5188 if (ctxt->have_exception) {
54b8486f 5189 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 5190 r = EMULATE_DONE;
5191 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5192 if (!vcpu->arch.pio.in) {
5193 /* FIXME: return into emulator if single-stepping. */
3457e419 5194 vcpu->arch.pio.count = 0;
0912c977 5195 } else {
7ae441ea 5196 writeback = false;
716d51ab
GN		 5197 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5198 }
ac0a48c3 5199 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5200 } else if (vcpu->mmio_needed) {
5201 if (!vcpu->mmio_is_write)
5202 writeback = false;
ac0a48c3 5203 r = EMULATE_USER_EXIT;
716d51ab 5204 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5205 } else if (r == EMULATION_RESTART)
5cd21917 5206 goto restart;
d2ddd1c4
GN		 5207 else
5208 r = EMULATE_DONE;
f850e2e6 5209
7ae441ea 5210 if (writeback) {
9d74191a 5211 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5212 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea 5213 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5214 kvm_rip_write(vcpu, ctxt->eip);
663f4c61
PB		 5215 if (r == EMULATE_DONE)
5216 kvm_vcpu_check_singlestep(vcpu, &r);
5217 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea
GN		 5218 } else
5219 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5220
5221 return r;
de7d789a 5222}
51d8b661 5223EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5224
cf8f70bf 5225int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5226{
cf8f70bf 5227 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5228 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5229 size, port, &val, 1);
cf8f70bf 5230 /* do not return to emulator after return from userspace */
7972995b 5231 vcpu->arch.pio.count = 0;
de7d789a
CO		 5232 return ret;
5233}
cf8f70bf 5234EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5235
8cfdc000
ZA		 5236static void tsc_bad(void *info)
5237{
0a3aee0d 5238 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5239}
5240
5241static void tsc_khz_changed(void *data)
c8076604 5242{
8cfdc000
ZA		 5243 struct cpufreq_freqs *freq = data;
5244 unsigned long khz = 0;
5245
5246 if (data)
5247 khz = freq->new;
5248 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5249 khz = cpufreq_quick_get(raw_smp_processor_id());
5250 if (!khz)
5251 khz = tsc_khz;
0a3aee0d 5252 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5253}
5254
c8076604
GH		 5255static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5256 void *data)
5257{
5258 struct cpufreq_freqs *freq = data;
5259 struct kvm *kvm;
5260 struct kvm_vcpu *vcpu;
5261 int i, send_ipi = 0;
5262
8cfdc000
ZA		 5263 /*
5264 * We allow guests to temporarily run on slowing clocks,
5265 * provided we notify them after, or to run on accelerating
5266 * clocks, provided we notify them before. Thus time never
5267 * goes backwards.
5268 *
5269 * However, we have a problem. We can't atomically update
5270 * the frequency of a given CPU from this function; it is
5271 * merely a notifier, which can be called from any CPU.
5272 * Changing the TSC frequency at arbitrary points in time
5273 * requires a recomputation of local variables related to
5274 * the TSC for each VCPU. We must flag these local variables
5275 * to be updated and be sure the update takes place with the
5276 * new frequency before any guests proceed.
5277 *
5278 * Unfortunately, the combination of hotplug CPU and frequency
5279 * change creates an intractable locking scenario; the order
5280 * of when these callouts happen is undefined with respect to
5281 * CPU hotplug, and they can race with each other. As such,
5282 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5283 * undefined; you can actually have a CPU frequency change take
5284 * place in between the computation of X and the setting of the
5285 * variable. To protect against this problem, all updates of
5286 * the per_cpu tsc_khz variable are done in an interrupt
5287 * protected IPI, and all callers wishing to update the value
5288 * must wait for a synchronous IPI to complete (which is trivial
5289 * if the caller is on the CPU already). This establishes the
5290 * necessary total order on variable updates.
5291 *
5292 * Note that because a guest time update may take place
5293 * anytime after the setting of the VCPU's request bit, the
5294 * correct TSC value must be set before the request. However,
5295 * to ensure the update actually makes it to any guest which
5296 * starts running in hardware virtualization between the set
5297 * and the acquisition of the spinlock, we must also ping the
5298 * CPU after setting the request bit.
5299 *
5300 */
5301
c8076604
GH		 5302 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5303 return 0;
5304 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5305 return 0;
8cfdc000
ZA		 5306
5307 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5308
2f303b74 5309 spin_lock(&kvm_lock);
c8076604 5310 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5311 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5312 if (vcpu->cpu != freq->cpu)
5313 continue;
c285545f 5314 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5315 if (vcpu->cpu != smp_processor_id())
8cfdc000 5316 send_ipi = 1;
c8076604
GH		 5317 }
5318 }
2f303b74 5319 spin_unlock(&kvm_lock);
c8076604
GH		 5320
5321 if (freq->old < freq->new && send_ipi) {
5322 /*
5323 * We upscale the frequency. Must make the guest
5324 * doesn't see old kvmclock values while running with
5325 * the new frequency, otherwise we risk the guest sees
5326 * time go backwards.
5327 *
5328 * In case we update the frequency for another cpu
5329 * (which might be in guest context) send an interrupt
5330 * to kick the cpu out of guest context. Next time
5331 * guest context is entered kvmclock will be updated,
5332 * so the guest will not see stale values.
5333 */
8cfdc000 5334 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5335 }
5336 return 0;
5337}
5338
5339static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5340 .notifier_call = kvmclock_cpufreq_notifier
5341};
5342
5343static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5344 unsigned long action, void *hcpu)
5345{
5346 unsigned int cpu = (unsigned long)hcpu;
5347
5348 switch (action) {
5349 case CPU_ONLINE:
5350 case CPU_DOWN_FAILED:
5351 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5352 break;
5353 case CPU_DOWN_PREPARE:
5354 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5355 break;
5356 }
5357 return NOTIFY_OK;
5358}
5359
5360static struct notifier_block kvmclock_cpu_notifier_block = {
5361 .notifier_call = kvmclock_cpu_notifier,
5362 .priority = -INT_MAX
c8076604
GH		 5363};
5364
b820cc0c
ZA		 5365static void kvm_timer_init(void)
5366{
5367 int cpu;
5368
c285545f 5369 max_tsc_khz = tsc_khz;
8cfdc000 5370 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 5371 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5372#ifdef CONFIG_CPU_FREQ
5373 struct cpufreq_policy policy;
5374 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5375 cpu = get_cpu();
5376 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5377 if (policy.cpuinfo.max_freq)
5378 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5379 put_cpu();
c285545f 5380#endif
b820cc0c
ZA		 5381 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5382 CPUFREQ_TRANSITION_NOTIFIER);
5383 }
c285545f 5384 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5385 for_each_online_cpu(cpu)
5386 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 5387}
5388
ff9d07a0
ZY		 5389static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5390
f5132b01 5391int kvm_is_in_guest(void)
ff9d07a0 5392{
086c9855 5393 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5394}
5395
5396static int kvm_is_user_mode(void)
5397{
5398 int user_mode = 3;
dcf46b94 5399
086c9855
AS		 5400 if (__this_cpu_read(current_vcpu))
5401 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5402
ff9d07a0
ZY		 5403 return user_mode != 0;
5404}
5405
5406static unsigned long kvm_get_guest_ip(void)
5407{
5408 unsigned long ip = 0;
dcf46b94 5409
086c9855
AS		 5410 if (__this_cpu_read(current_vcpu))
5411 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5412
ff9d07a0
ZY		 5413 return ip;
5414}
5415
5416static struct perf_guest_info_callbacks kvm_guest_cbs = {
5417 .is_in_guest = kvm_is_in_guest,
5418 .is_user_mode = kvm_is_user_mode,
5419 .get_guest_ip = kvm_get_guest_ip,
5420};
5421
5422void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5423{
086c9855 5424 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5425}
5426EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5427
5428void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5429{
086c9855 5430 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5431}
5432EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5433
ce88decf
XG		 5434static void kvm_set_mmio_spte_mask(void)
5435{
5436 u64 mask;
5437 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5438
5439 /*
5440 * Set the reserved bits and the present bit of an paging-structure
5441 * entry to generate page fault with PFER.RSV = 1.
5442 */
885032b9
XG		 5443 /* Mask the reserved physical address bits. */
5444 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5445
5446 /* Bit 62 is always reserved for 32bit host. */
5447 mask |= 0x3ull << 62;
5448
5449 /* Set the present bit. */
ce88decf
XG		 5450 mask |= 1ull;
5451
5452#ifdef CONFIG_X86_64
5453 /*
5454 * If reserved bit is not supported, clear the present bit to disable
5455 * mmio page fault.
5456 */
5457 if (maxphyaddr == 52)
5458 mask &= ~1ull;
5459#endif
5460
5461 kvm_mmu_set_mmio_spte_mask(mask);
5462}
5463
16e8d74d
MT		 5464#ifdef CONFIG_X86_64
5465static void pvclock_gtod_update_fn(struct work_struct *work)
5466{
d828199e
MT		 5467 struct kvm *kvm;
5468
5469 struct kvm_vcpu *vcpu;
5470 int i;
5471
2f303b74 5472 spin_lock(&kvm_lock);
d828199e
MT		 5473 list_for_each_entry(kvm, &vm_list, vm_list)
5474 kvm_for_each_vcpu(i, vcpu, kvm)
5475 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5476 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5477 spin_unlock(&kvm_lock);
16e8d74d
MT		 5478}
5479
5480static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5481
5482/*
5483 * Notification about pvclock gtod data update.
5484 */
5485static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5486 void *priv)
5487{
5488 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5489 struct timekeeper *tk = priv;
5490
5491 update_pvclock_gtod(tk);
5492
5493 /* disable master clock if host does not trust, or does not
5494 * use, TSC clocksource
5495 */
5496 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5497 atomic_read(&kvm_guest_has_master_clock) != 0)
5498 queue_work(system_long_wq, &pvclock_gtod_work);
5499
5500 return 0;
5501}
5502
5503static struct notifier_block pvclock_gtod_notifier = {
5504 .notifier_call = pvclock_gtod_notify,
5505};
5506#endif
5507
f8c16bba 5508int kvm_arch_init(void *opaque)
043405e1 5509{
b820cc0c 5510 int r;
6b61edf7 5511 struct kvm_x86_ops *ops = opaque;
f8c16bba 5512
f8c16bba
ZX		 5513 if (kvm_x86_ops) {
5514 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5515 r = -EEXIST;
5516 goto out;
f8c16bba
ZX		 5517 }
5518
5519 if (!ops->cpu_has_kvm_support()) {
5520 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5521 r = -EOPNOTSUPP;
5522 goto out;
f8c16bba
ZX		 5523 }
5524 if (ops->disabled_by_bios()) {
5525 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5526 r = -EOPNOTSUPP;
5527 goto out;
f8c16bba
ZX		 5528 }
5529
013f6a5d
MT		 5530 r = -ENOMEM;
5531 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5532 if (!shared_msrs) {
5533 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5534 goto out;
5535 }
5536
97db56ce
AK		 5537 r = kvm_mmu_module_init();
5538 if (r)
013f6a5d 5539 goto out_free_percpu;
97db56ce 5540
ce88decf 5541 kvm_set_mmio_spte_mask();
97db56ce
AK		 5542 kvm_init_msr_list();
5543
f8c16bba 5544 kvm_x86_ops = ops;
7b52345e 5545 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5546 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5547
b820cc0c 5548 kvm_timer_init();
c8076604 5549
ff9d07a0
ZY		 5550 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5551
2acf923e
DC		 5552 if (cpu_has_xsave)
5553 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5554
c5cc421b 5555 kvm_lapic_init();
16e8d74d
MT		 5556#ifdef CONFIG_X86_64
5557 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5558#endif
5559
f8c16bba 5560 return 0;
56c6d28a 5561
013f6a5d
MT		 5562out_free_percpu:
5563 free_percpu(shared_msrs);
56c6d28a 5564out:
56c6d28a 5565 return r;
043405e1 5566}
8776e519 5567
f8c16bba
ZX		 5568void kvm_arch_exit(void)
5569{
ff9d07a0
ZY		 5570 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5571
888d256e
JK		 5572 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5573 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5574 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5575 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5576#ifdef CONFIG_X86_64
5577 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5578#endif
f8c16bba 5579 kvm_x86_ops = NULL;
56c6d28a 5580 kvm_mmu_module_exit();
013f6a5d 5581 free_percpu(shared_msrs);
56c6d28a 5582}
f8c16bba 5583
8776e519
HB		 5584int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5585{
5586 ++vcpu->stat.halt_exits;
5587 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5588 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5589 return 1;
5590 } else {
5591 vcpu->run->exit_reason = KVM_EXIT_HLT;
5592 return 0;
5593 }
5594}
5595EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5596
55cd8e5a
GN		 5597int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5598{
5599 u64 param, ingpa, outgpa, ret;
5600 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5601 bool fast, longmode;
5602 int cs_db, cs_l;
5603
5604 /*
5605 * hypercall generates UD from non zero cpl and real mode
5606 * per HYPER-V spec
5607 */
3eeb3288 5608 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5609 kvm_queue_exception(vcpu, UD_VECTOR);
5610 return 0;
5611 }
5612
5613 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5614 longmode = is_long_mode(vcpu) && cs_l == 1;
5615
5616 if (!longmode) {
ccd46936
GN		 5617 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5618 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5619 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5620 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5621 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5622 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5623 }
5624#ifdef CONFIG_X86_64
5625 else {
5626 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5627 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5628 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5629 }
5630#endif
5631
5632 code = param & 0xffff;
5633 fast = (param >> 16) & 0x1;
5634 rep_cnt = (param >> 32) & 0xfff;
5635 rep_idx = (param >> 48) & 0xfff;
5636
5637 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5638
c25bc163
GN		 5639 switch (code) {
5640 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5641 kvm_vcpu_on_spin(vcpu);
5642 break;
5643 default:
5644 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5645 break;
5646 }
55cd8e5a
GN		 5647
5648 ret = res | (((u64)rep_done & 0xfff) << 32);
5649 if (longmode) {
5650 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5651 } else {
5652 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5653 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5654 }
5655
5656 return 1;
5657}
5658
6aef266c
SV		 5659/*
5660 * kvm_pv_kick_cpu_op: Kick a vcpu.
5661 *
5662 * @apicid - apicid of vcpu to be kicked.
5663 */
5664static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5665{
24d2166b 5666 struct kvm_lapic_irq lapic_irq;
6aef266c 5667
24d2166b
R		 5668 lapic_irq.shorthand = 0;
5669 lapic_irq.dest_mode = 0;
5670 lapic_irq.dest_id = apicid;
6aef266c 5671
24d2166b
R		 5672 lapic_irq.delivery_mode = APIC_DM_REMRD;
5673 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
6aef266c
SV		 5674}
5675
8776e519
HB		 5676int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5677{
5678 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5679 int r = 1;
8776e519 5680
55cd8e5a
GN		 5681 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5682 return kvm_hv_hypercall(vcpu);
5683
5fdbf976
MT		 5684 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5685 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5686 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5687 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5688 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5689
229456fc 5690 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5691
8776e519
HB		 5692 if (!is_long_mode(vcpu)) {
5693 nr &= 0xFFFFFFFF;
5694 a0 &= 0xFFFFFFFF;
5695 a1 &= 0xFFFFFFFF;
5696 a2 &= 0xFFFFFFFF;
5697 a3 &= 0xFFFFFFFF;
5698 }
5699
07708c4a
JK		 5700 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5701 ret = -KVM_EPERM;
5702 goto out;
5703 }
5704
8776e519 5705 switch (nr) {
b93463aa
AK		 5706 case KVM_HC_VAPIC_POLL_IRQ:
5707 ret = 0;
5708 break;
6aef266c
SV		 5709 case KVM_HC_KICK_CPU:
5710 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5711 ret = 0;
5712 break;
8776e519
HB		 5713 default:
5714 ret = -KVM_ENOSYS;
5715 break;
5716 }
07708c4a 5717out:
5fdbf976 5718 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5719 ++vcpu->stat.hypercalls;
2f333bcb 5720 return r;
8776e519
HB		 5721}
5722EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5723
b6785def 5724static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5725{
d6aa1000 5726 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5727 char instruction[3];
5fdbf976 5728 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5729
8776e519 5730 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5731
9d74191a 5732 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5733}
5734
b6c7a5dc
HB		 5735/*
5736 * Check if userspace requested an interrupt window, and that the
5737 * interrupt window is open.
5738 *
5739 * No need to exit to userspace if we already have an interrupt queued.
5740 */
851ba692 5741static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5742{
8061823a 5743 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5744 vcpu->run->request_interrupt_window &&
5df56646 5745 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5746}
5747
851ba692 5748static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5749{
851ba692
AK		 5750 struct kvm_run *kvm_run = vcpu->run;
5751
91586a3b 5752 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5753 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5754 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5755 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5756 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5757 else
b6c7a5dc 5758 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5759 kvm_arch_interrupt_allowed(vcpu) &&
5760 !kvm_cpu_has_interrupt(vcpu) &&
5761 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5762}
5763
95ba8273
GN		 5764static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5765{
5766 int max_irr, tpr;
5767
5768 if (!kvm_x86_ops->update_cr8_intercept)
5769 return;
5770
88c808fd
AK		 5771 if (!vcpu->arch.apic)
5772 return;
5773
8db3baa2
GN		 5774 if (!vcpu->arch.apic->vapic_addr)
5775 max_irr = kvm_lapic_find_highest_irr(vcpu);
5776 else
5777 max_irr = -1;
95ba8273
GN		 5778
5779 if (max_irr != -1)
5780 max_irr >>= 4;
5781
5782 tpr = kvm_lapic_get_cr8(vcpu);
5783
5784 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5785}
5786
851ba692 5787static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5788{
5789 /* try to reinject previous events if any */
b59bb7bd 5790 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5791 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5792 vcpu->arch.exception.has_error_code,
5793 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5794 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5795 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5796 vcpu->arch.exception.error_code,
5797 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5798 return;
5799 }
5800
95ba8273
GN		 5801 if (vcpu->arch.nmi_injected) {
5802 kvm_x86_ops->set_nmi(vcpu);
5803 return;
5804 }
5805
5806 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5807 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5808 return;
5809 }
5810
5811 /* try to inject new event if pending */
5812 if (vcpu->arch.nmi_pending) {
5813 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5814 --vcpu->arch.nmi_pending;
95ba8273
GN		 5815 vcpu->arch.nmi_injected = true;
5816 kvm_x86_ops->set_nmi(vcpu);
5817 }
c7c9c56c 5818 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
95ba8273 5819 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5820 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5821 false);
5822 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5823 }
5824 }
5825}
5826
7460fb4a
AK		 5827static void process_nmi(struct kvm_vcpu *vcpu)
5828{
5829 unsigned limit = 2;
5830
5831 /*
5832 * x86 is limited to one NMI running, and one NMI pending after it.
5833 * If an NMI is already in progress, limit further NMIs to just one.
5834 * Otherwise, allow two (and we'll inject the first one immediately).
5835 */
5836 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5837 limit = 1;
5838
5839 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5840 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5841 kvm_make_request(KVM_REQ_EVENT, vcpu);
5842}
5843
3d81bc7e 5844static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 5845{
5846 u64 eoi_exit_bitmap[4];
cf9e65b7 5847 u32 tmr[8];
c7c9c56c 5848
3d81bc7e
YZ		 5849 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5850 return;
c7c9c56c
YZ		 5851
5852 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 5853 memset(tmr, 0, 32);
c7c9c56c 5854
cf9e65b7 5855 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 5856 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 5857 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 5858}
5859
9357d939
TY		 5860/*
5861 * Returns 1 to let __vcpu_run() continue the guest execution loop without
5862 * exiting to the userspace. Otherwise, the value will be returned to the
5863 * userspace.
5864 */
851ba692 5865static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5866{
5867 int r;
6a8b1d13 5868 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5869 vcpu->run->request_interrupt_window;
730dca42 5870 bool req_immediate_exit = false;
b6c7a5dc 5871
3e007509 5872 if (vcpu->requests) {
a8eeb04a 5873 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5874 kvm_mmu_unload(vcpu);
a8eeb04a 5875 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5876 __kvm_migrate_timers(vcpu);
d828199e
MT		 5877 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5878 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 5879 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5880 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 5881 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5882 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5883 if (unlikely(r))
5884 goto out;
5885 }
a8eeb04a 5886 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5887 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5888 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5889 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5890 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5891 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5892 r = 0;
5893 goto out;
5894 }
a8eeb04a 5895 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5896 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5897 r = 0;
5898 goto out;
5899 }
a8eeb04a 5900 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5901 vcpu->fpu_active = 0;
5902 kvm_x86_ops->fpu_deactivate(vcpu);
5903 }
af585b92
GN		 5904 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5905 /* Page is swapped out. Do synthetic halt */
5906 vcpu->arch.apf.halted = true;
5907 r = 1;
5908 goto out;
5909 }
c9aaa895
GC		 5910 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5911 record_steal_time(vcpu);
7460fb4a
AK		 5912 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5913 process_nmi(vcpu);
f5132b01
GN		 5914 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5915 kvm_handle_pmu_event(vcpu);
5916 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5917 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 5918 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5919 vcpu_scan_ioapic(vcpu);
2f52d58c 5920 }
b93463aa 5921
b463a6f7 5922 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 5923 kvm_apic_accept_events(vcpu);
5924 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5925 r = 1;
5926 goto out;
5927 }
5928
b463a6f7
AK		 5929 inject_pending_event(vcpu);
5930
5931 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5932 if (vcpu->arch.nmi_pending)
03b28f81
JK		 5933 req_immediate_exit =
5934 kvm_x86_ops->enable_nmi_window(vcpu) != 0;
c7c9c56c 5935 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
730dca42
JK		 5936 req_immediate_exit =
5937 kvm_x86_ops->enable_irq_window(vcpu) != 0;
b463a6f7
AK		 5938
5939 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 5940 /*
5941 * Update architecture specific hints for APIC
5942 * virtual interrupt delivery.
5943 */
5944 if (kvm_x86_ops->hwapic_irr_update)
5945 kvm_x86_ops->hwapic_irr_update(vcpu,
5946 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 5947 update_cr8_intercept(vcpu);
5948 kvm_lapic_sync_to_vapic(vcpu);
5949 }
5950 }
5951
d8368af8
AK		 5952 r = kvm_mmu_reload(vcpu);
5953 if (unlikely(r)) {
d905c069 5954 goto cancel_injection;
d8368af8
AK		 5955 }
5956
b6c7a5dc
HB		 5957 preempt_disable();
5958
5959 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5960 if (vcpu->fpu_active)
5961 kvm_load_guest_fpu(vcpu);
2acf923e 5962 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5963
6b7e2d09
XG		 5964 vcpu->mode = IN_GUEST_MODE;
5965
01b71917
MT		 5966 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5967
6b7e2d09
XG		 5968 /* We should set ->mode before check ->requests,
5969 * see the comment in make_all_cpus_request.
5970 */
01b71917 5971 smp_mb__after_srcu_read_unlock();
b6c7a5dc 5972
d94e1dc9 5973 local_irq_disable();
32f88400 5974
6b7e2d09 5975 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5976 || need_resched() || signal_pending(current)) {
6b7e2d09 5977 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5978 smp_wmb();
6c142801
AK		 5979 local_irq_enable();
5980 preempt_enable();
01b71917 5981 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 5982 r = 1;
d905c069 5983 goto cancel_injection;
6c142801
AK		 5984 }
5985
d6185f20
NHE		 5986 if (req_immediate_exit)
5987 smp_send_reschedule(vcpu->cpu);
5988
b6c7a5dc
HB		 5989 kvm_guest_enter();
5990
42dbaa5a 5991 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5992 set_debugreg(0, 7);
5993 set_debugreg(vcpu->arch.eff_db[0], 0);
5994 set_debugreg(vcpu->arch.eff_db[1], 1);
5995 set_debugreg(vcpu->arch.eff_db[2], 2);
5996 set_debugreg(vcpu->arch.eff_db[3], 3);
5997 }
b6c7a5dc 5998
229456fc 5999 trace_kvm_entry(vcpu->vcpu_id);
851ba692 6000 kvm_x86_ops->run(vcpu);
b6c7a5dc 6001
24f1e32c
FW		 6002 /*
6003 * If the guest has used debug registers, at least dr7
6004 * will be disabled while returning to the host.
6005 * If we don't have active breakpoints in the host, we don't
6006 * care about the messed up debug address registers. But if
6007 * we have some of them active, restore the old state.
6008 */
59d8eb53 6009 if (hw_breakpoint_active())
24f1e32c 6010 hw_breakpoint_restore();
42dbaa5a 6011
886b470c
MT		 6012 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6013 native_read_tsc());
1d5f066e 6014
6b7e2d09 6015 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6016 smp_wmb();
a547c6db
YZ		 6017
6018 /* Interrupt is enabled by handle_external_intr() */
6019 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6020
6021 ++vcpu->stat.exits;
6022
6023 /*
6024 * We must have an instruction between local_irq_enable() and
6025 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6026 * the interrupt shadow. The stat.exits increment will do nicely.
6027 * But we need to prevent reordering, hence this barrier():
6028 */
6029 barrier();
6030
6031 kvm_guest_exit();
6032
6033 preempt_enable();
6034
f656ce01 6035 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6036
b6c7a5dc
HB		 6037 /*
6038 * Profile KVM exit RIPs:
6039 */
6040 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6041 unsigned long rip = kvm_rip_read(vcpu);
6042 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6043 }
6044
cc578287
ZA		 6045 if (unlikely(vcpu->arch.tsc_always_catchup))
6046 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6047
5cfb1d5a
MT		 6048 if (vcpu->arch.apic_attention)
6049 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6050
851ba692 6051 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6052 return r;
6053
6054cancel_injection:
6055 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6056 if (unlikely(vcpu->arch.apic_attention))
6057 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6058out:
6059 return r;
6060}
b6c7a5dc 6061
09cec754 6062
851ba692 6063static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6064{
6065 int r;
f656ce01 6066 struct kvm *kvm = vcpu->kvm;
d7690175 6067
f656ce01 6068 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 6069
6070 r = 1;
6071 while (r > 0) {
af585b92
GN		 6072 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6073 !vcpu->arch.apf.halted)
851ba692 6074 r = vcpu_enter_guest(vcpu);
d7690175 6075 else {
f656ce01 6076 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6077 kvm_vcpu_block(vcpu);
f656ce01 6078 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6079 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6080 kvm_apic_accept_events(vcpu);
09cec754
GN		 6081 switch(vcpu->arch.mp_state) {
6082 case KVM_MP_STATE_HALTED:
6aef266c 6083 vcpu->arch.pv.pv_unhalted = false;
d7690175 6084 vcpu->arch.mp_state =
09cec754
GN		 6085 KVM_MP_STATE_RUNNABLE;
6086 case KVM_MP_STATE_RUNNABLE:
af585b92 6087 vcpu->arch.apf.halted = false;
09cec754 6088 break;
66450a21
JK		 6089 case KVM_MP_STATE_INIT_RECEIVED:
6090 break;
09cec754
GN		 6091 default:
6092 r = -EINTR;
6093 break;
6094 }
6095 }
d7690175
MT		 6096 }
6097
09cec754
GN		 6098 if (r <= 0)
6099 break;
6100
6101 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6102 if (kvm_cpu_has_pending_timer(vcpu))
6103 kvm_inject_pending_timer_irqs(vcpu);
6104
851ba692 6105 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6106 r = -EINTR;
851ba692 6107 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6108 ++vcpu->stat.request_irq_exits;
6109 }
af585b92
GN		 6110
6111 kvm_check_async_pf_completion(vcpu);
6112
09cec754
GN		 6113 if (signal_pending(current)) {
6114 r = -EINTR;
851ba692 6115 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6116 ++vcpu->stat.signal_exits;
6117 }
6118 if (need_resched()) {
f656ce01 6119 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6120 cond_resched();
f656ce01 6121 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6122 }
b6c7a5dc
HB		 6123 }
6124
f656ce01 6125 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6126
6127 return r;
6128}
6129
716d51ab
GN		 6130static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6131{
6132 int r;
6133 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6134 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6135 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6136 if (r != EMULATE_DONE)
6137 return 0;
6138 return 1;
6139}
6140
6141static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6142{
6143 BUG_ON(!vcpu->arch.pio.count);
6144
6145 return complete_emulated_io(vcpu);
6146}
6147
f78146b0
AK		 6148/*
6149 * Implements the following, as a state machine:
6150 *
6151 * read:
6152 * for each fragment
87da7e66
XG		 6153 * for each mmio piece in the fragment
6154 * write gpa, len
6155 * exit
6156 * copy data
f78146b0
AK		 6157 * execute insn
6158 *
6159 * write:
6160 * for each fragment
87da7e66
XG		 6161 * for each mmio piece in the fragment
6162 * write gpa, len
6163 * copy data
6164 * exit
f78146b0 6165 */
716d51ab 6166static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6167{
6168 struct kvm_run *run = vcpu->run;
f78146b0 6169 struct kvm_mmio_fragment *frag;
87da7e66 6170 unsigned len;
5287f194 6171
716d51ab 6172 BUG_ON(!vcpu->mmio_needed);
5287f194 6173
716d51ab 6174 /* Complete previous fragment */
87da7e66
XG		 6175 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6176 len = min(8u, frag->len);
716d51ab 6177 if (!vcpu->mmio_is_write)
87da7e66
XG		 6178 memcpy(frag->data, run->mmio.data, len);
6179
6180 if (frag->len <= 8) {
6181 /* Switch to the next fragment. */
6182 frag++;
6183 vcpu->mmio_cur_fragment++;
6184 } else {
6185 /* Go forward to the next mmio piece. */
6186 frag->data += len;
6187 frag->gpa += len;
6188 frag->len -= len;
6189 }
6190
716d51ab
GN		 6191 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
6192 vcpu->mmio_needed = 0;
0912c977
PB		 6193
6194 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6195 if (vcpu->mmio_is_write)
716d51ab
GN		 6196 return 1;
6197 vcpu->mmio_read_completed = 1;
6198 return complete_emulated_io(vcpu);
6199 }
87da7e66 6200
716d51ab
GN		 6201 run->exit_reason = KVM_EXIT_MMIO;
6202 run->mmio.phys_addr = frag->gpa;
6203 if (vcpu->mmio_is_write)
87da7e66
XG		 6204 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6205 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6206 run->mmio.is_write = vcpu->mmio_is_write;
6207 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6208 return 0;
5287f194
AK		 6209}
6210
716d51ab 6211
b6c7a5dc
HB		 6212int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6213{
6214 int r;
6215 sigset_t sigsaved;
6216
e5c30142
AK		 6217 if (!tsk_used_math(current) && init_fpu(current))
6218 return -ENOMEM;
6219
ac9f6dc0
AK		 6220 if (vcpu->sigset_active)
6221 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6222
a4535290 6223 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6224 kvm_vcpu_block(vcpu);
66450a21 6225 kvm_apic_accept_events(vcpu);
d7690175 6226 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6227 r = -EAGAIN;
6228 goto out;
b6c7a5dc
HB		 6229 }
6230
b6c7a5dc 6231 /* re-sync apic's tpr */
eea1cff9
AP		 6232 if (!irqchip_in_kernel(vcpu->kvm)) {
6233 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6234 r = -EINVAL;
6235 goto out;
6236 }
6237 }
b6c7a5dc 6238
716d51ab
GN		 6239 if (unlikely(vcpu->arch.complete_userspace_io)) {
6240 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6241 vcpu->arch.complete_userspace_io = NULL;
6242 r = cui(vcpu);
6243 if (r <= 0)
6244 goto out;
6245 } else
6246 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6247
851ba692 6248 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6249
6250out:
f1d86e46 6251 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6252 if (vcpu->sigset_active)
6253 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6254
b6c7a5dc
HB		 6255 return r;
6256}
6257
6258int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6259{
7ae441ea
GN		 6260 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6261 /*
6262 * We are here if userspace calls get_regs() in the middle of
6263 * instruction emulation. Registers state needs to be copied
4a969980 6264 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6265 * that usually, but some bad designed PV devices (vmware
6266 * backdoor interface) need this to work
6267 */
dd856efa 6268 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6269 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6270 }
5fdbf976
MT		 6271 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6272 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6273 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6274 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6275 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6276 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6277 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6278 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6279#ifdef CONFIG_X86_64
5fdbf976
MT		 6280 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6281 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6282 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6283 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6284 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6285 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6286 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6287 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6288#endif
6289
5fdbf976 6290 regs->rip = kvm_rip_read(vcpu);
91586a3b 6291 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6292
b6c7a5dc
HB		 6293 return 0;
6294}
6295
6296int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6297{
7ae441ea
GN		 6298 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6299 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6300
5fdbf976
MT		 6301 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6302 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6303 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6304 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6305 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6306 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6307 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6308 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6309#ifdef CONFIG_X86_64
5fdbf976
MT		 6310 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6311 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6312 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6313 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6314 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6315 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6316 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6317 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6318#endif
6319
5fdbf976 6320 kvm_rip_write(vcpu, regs->rip);
91586a3b 6321 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6322
b4f14abd
JK		 6323 vcpu->arch.exception.pending = false;
6324
3842d135
AK		 6325 kvm_make_request(KVM_REQ_EVENT, vcpu);
6326
b6c7a5dc
HB		 6327 return 0;
6328}
6329
b6c7a5dc
HB		 6330void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6331{
6332 struct kvm_segment cs;
6333
3e6e0aab 6334 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6335 *db = cs.db;
6336 *l = cs.l;
6337}
6338EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6339
6340int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6341 struct kvm_sregs *sregs)
6342{
89a27f4d 6343 struct desc_ptr dt;
b6c7a5dc 6344
3e6e0aab
GT		 6345 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6346 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6347 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6348 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6349 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6350 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6351
3e6e0aab
GT		 6352 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6353 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6354
6355 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6356 sregs->idt.limit = dt.size;
6357 sregs->idt.base = dt.address;
b6c7a5dc 6358 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6359 sregs->gdt.limit = dt.size;
6360 sregs->gdt.base = dt.address;
b6c7a5dc 6361
4d4ec087 6362 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6363 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6364 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6365 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6366 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6367 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6368 sregs->apic_base = kvm_get_apic_base(vcpu);
6369
923c61bb 6370 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6371
36752c9b 6372 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6373 set_bit(vcpu->arch.interrupt.nr,
6374 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6375
b6c7a5dc
HB		 6376 return 0;
6377}
6378
62d9f0db
MT		 6379int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6380 struct kvm_mp_state *mp_state)
6381{
66450a21 6382 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6383 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6384 vcpu->arch.pv.pv_unhalted)
6385 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6386 else
6387 mp_state->mp_state = vcpu->arch.mp_state;
6388
62d9f0db
MT		 6389 return 0;
6390}
6391
6392int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6393 struct kvm_mp_state *mp_state)
6394{
66450a21
JK		 6395 if (!kvm_vcpu_has_lapic(vcpu) &&
6396 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6397 return -EINVAL;
6398
6399 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6400 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6401 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6402 } else
6403 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6404 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6405 return 0;
6406}
6407
7f3d35fd
KW		 6408int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6409 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6410{
9d74191a 6411 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6412 int ret;
e01c2426 6413
8ec4722d 6414 init_emulate_ctxt(vcpu);
c697518a 6415
7f3d35fd 6416 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6417 has_error_code, error_code);
c697518a 6418
c697518a 6419 if (ret)
19d04437 6420 return EMULATE_FAIL;
37817f29 6421
9d74191a
TY		 6422 kvm_rip_write(vcpu, ctxt->eip);
6423 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6424 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6425 return EMULATE_DONE;
37817f29
IE		 6426}
6427EXPORT_SYMBOL_GPL(kvm_task_switch);
6428
b6c7a5dc
HB		 6429int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6430 struct kvm_sregs *sregs)
6431{
58cb628d 6432 struct msr_data apic_base_msr;
b6c7a5dc 6433 int mmu_reset_needed = 0;
63f42e02 6434 int pending_vec, max_bits, idx;
89a27f4d 6435 struct desc_ptr dt;
b6c7a5dc 6436
6d1068b3
PM		 6437 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6438 return -EINVAL;
6439
89a27f4d
GN		 6440 dt.size = sregs->idt.limit;
6441 dt.address = sregs->idt.base;
b6c7a5dc 6442 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6443 dt.size = sregs->gdt.limit;
6444 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6445 kvm_x86_ops->set_gdt(vcpu, &dt);
6446
ad312c7c 6447 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6448 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6449 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6450 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6451
2d3ad1f4 6452 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6453
f6801dff 6454 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6455 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6456 apic_base_msr.data = sregs->apic_base;
6457 apic_base_msr.host_initiated = true;
6458 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6459
4d4ec087 6460 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6461 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6462 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6463
fc78f519 6464 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6465 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6466 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6467 kvm_update_cpuid(vcpu);
63f42e02
XG		 6468
6469 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6470 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6471 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6472 mmu_reset_needed = 1;
6473 }
63f42e02 6474 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6475
6476 if (mmu_reset_needed)
6477 kvm_mmu_reset_context(vcpu);
6478
a50abc3b 6479 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6480 pending_vec = find_first_bit(
6481 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6482 if (pending_vec < max_bits) {
66fd3f7f 6483 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6484 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6485 }
6486
3e6e0aab
GT		 6487 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6488 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6489 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6490 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6491 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6492 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6493
3e6e0aab
GT		 6494 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6495 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6496
5f0269f5
ME		 6497 update_cr8_intercept(vcpu);
6498
9c3e4aab 6499 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6500 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6501 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6502 !is_protmode(vcpu))
9c3e4aab
MT		 6503 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6504
3842d135
AK		 6505 kvm_make_request(KVM_REQ_EVENT, vcpu);
6506
b6c7a5dc
HB		 6507 return 0;
6508}
6509
d0bfb940
JK		 6510int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6511 struct kvm_guest_debug *dbg)
b6c7a5dc 6512{
355be0b9 6513 unsigned long rflags;
ae675ef0 6514 int i, r;
b6c7a5dc 6515
4f926bf2
JK		 6516 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6517 r = -EBUSY;
6518 if (vcpu->arch.exception.pending)
2122ff5e 6519 goto out;
4f926bf2
JK		 6520 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6521 kvm_queue_exception(vcpu, DB_VECTOR);
6522 else
6523 kvm_queue_exception(vcpu, BP_VECTOR);
6524 }
6525
91586a3b
JK		 6526 /*
6527 * Read rflags as long as potentially injected trace flags are still
6528 * filtered out.
6529 */
6530 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6531
6532 vcpu->guest_debug = dbg->control;
6533 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6534 vcpu->guest_debug = 0;
6535
6536 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6537 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6538 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6539 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6540 } else {
6541 for (i = 0; i < KVM_NR_DB_REGS; i++)
6542 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6543 }
c8639010 6544 kvm_update_dr7(vcpu);
ae675ef0 6545
f92653ee
JK		 6546 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6547 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6548 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6549
91586a3b
JK		 6550 /*
6551 * Trigger an rflags update that will inject or remove the trace
6552 * flags.
6553 */
6554 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6555
c8639010 6556 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6557
4f926bf2 6558 r = 0;
d0bfb940 6559
2122ff5e 6560out:
b6c7a5dc
HB		 6561
6562 return r;
6563}
6564
8b006791
ZX		 6565/*
6566 * Translate a guest virtual address to a guest physical address.
6567 */
6568int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6569 struct kvm_translation *tr)
6570{
6571 unsigned long vaddr = tr->linear_address;
6572 gpa_t gpa;
f656ce01 6573 int idx;
8b006791 6574
f656ce01 6575 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6576 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6577 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6578 tr->physical_address = gpa;
6579 tr->valid = gpa != UNMAPPED_GVA;
6580 tr->writeable = 1;
6581 tr->usermode = 0;
8b006791
ZX		 6582
6583 return 0;
6584}
6585
d0752060
HB		 6586int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6587{
98918833
SY		 6588 struct i387_fxsave_struct *fxsave =
6589 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6590
d0752060
HB		 6591 memcpy(fpu->fpr, fxsave->st_space, 128);
6592 fpu->fcw = fxsave->cwd;
6593 fpu->fsw = fxsave->swd;
6594 fpu->ftwx = fxsave->twd;
6595 fpu->last_opcode = fxsave->fop;
6596 fpu->last_ip = fxsave->rip;
6597 fpu->last_dp = fxsave->rdp;
6598 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6599
d0752060
HB		 6600 return 0;
6601}
6602
6603int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6604{
98918833
SY		 6605 struct i387_fxsave_struct *fxsave =
6606 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6607
d0752060
HB		 6608 memcpy(fxsave->st_space, fpu->fpr, 128);
6609 fxsave->cwd = fpu->fcw;
6610 fxsave->swd = fpu->fsw;
6611 fxsave->twd = fpu->ftwx;
6612 fxsave->fop = fpu->last_opcode;
6613 fxsave->rip = fpu->last_ip;
6614 fxsave->rdp = fpu->last_dp;
6615 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6616
d0752060
HB		 6617 return 0;
6618}
6619
10ab25cd 6620int fx_init(struct kvm_vcpu *vcpu)
d0752060 6621{
10ab25cd
JK		 6622 int err;
6623
6624 err = fpu_alloc(&vcpu->arch.guest_fpu);
6625 if (err)
6626 return err;
6627
98918833 6628 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6629
2acf923e
DC		 6630 /*
6631 * Ensure guest xcr0 is valid for loading
6632 */
6633 vcpu->arch.xcr0 = XSTATE_FP;
6634
ad312c7c 6635 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6636
6637 return 0;
d0752060
HB		 6638}
6639EXPORT_SYMBOL_GPL(fx_init);
6640
98918833
SY		 6641static void fx_free(struct kvm_vcpu *vcpu)
6642{
6643 fpu_free(&vcpu->arch.guest_fpu);
6644}
6645
d0752060
HB		 6646void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6647{
2608d7a1 6648 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6649 return;
6650
2acf923e
DC		 6651 /*
6652 * Restore all possible states in the guest,
6653 * and assume host would use all available bits.
6654 * Guest xcr0 would be loaded later.
6655 */
6656 kvm_put_guest_xcr0(vcpu);
d0752060 6657 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6658 __kernel_fpu_begin();
98918833 6659 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6660 trace_kvm_fpu(1);
d0752060 6661}
d0752060
HB		 6662
6663void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6664{
2acf923e
DC		 6665 kvm_put_guest_xcr0(vcpu);
6666
d0752060
HB		 6667 if (!vcpu->guest_fpu_loaded)
6668 return;
6669
6670 vcpu->guest_fpu_loaded = 0;
98918833 6671 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6672 __kernel_fpu_end();
f096ed85 6673 ++vcpu->stat.fpu_reload;
a8eeb04a 6674 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6675 trace_kvm_fpu(0);
d0752060 6676}
e9b11c17
ZX		 6677
6678void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6679{
12f9a48f 6680 kvmclock_reset(vcpu);
7f1ea208 6681
f5f48ee1 6682 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6683 fx_free(vcpu);
e9b11c17
ZX		 6684 kvm_x86_ops->vcpu_free(vcpu);
6685}
6686
6687struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6688 unsigned int id)
6689{
6755bae8
ZA		 6690 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6691 printk_once(KERN_WARNING
6692 "kvm: SMP vm created on host with unstable TSC; "
6693 "guest TSC will not be reliable\n");
26e5215f
AK		 6694 return kvm_x86_ops->vcpu_create(kvm, id);
6695}
e9b11c17 6696
26e5215f
AK		 6697int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6698{
6699 int r;
e9b11c17 6700
0bed3b56 6701 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6702 r = vcpu_load(vcpu);
6703 if (r)
6704 return r;
57f252f2 6705 kvm_vcpu_reset(vcpu);
8a3c1a33 6706 kvm_mmu_setup(vcpu);
e9b11c17 6707 vcpu_put(vcpu);
e9b11c17 6708
26e5215f 6709 return r;
e9b11c17
ZX		 6710}
6711
42897d86
MT		 6712int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6713{
6714 int r;
8fe8ab46 6715 struct msr_data msr;
42897d86
MT		 6716
6717 r = vcpu_load(vcpu);
6718 if (r)
6719 return r;
8fe8ab46
WA		 6720 msr.data = 0x0;
6721 msr.index = MSR_IA32_TSC;
6722 msr.host_initiated = true;
6723 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6724 vcpu_put(vcpu);
6725
6726 return r;
6727}
6728
d40ccc62 6729void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6730{
9fc77441 6731 int r;
344d9588
GN		 6732 vcpu->arch.apf.msr_val = 0;
6733
9fc77441
MT		 6734 r = vcpu_load(vcpu);
6735 BUG_ON(r);
e9b11c17
ZX		 6736 kvm_mmu_unload(vcpu);
6737 vcpu_put(vcpu);
6738
98918833 6739 fx_free(vcpu);
e9b11c17
ZX		 6740 kvm_x86_ops->vcpu_free(vcpu);
6741}
6742
66450a21 6743void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6744{
7460fb4a
AK		 6745 atomic_set(&vcpu->arch.nmi_queued, 0);
6746 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6747 vcpu->arch.nmi_injected = false;
6748
42dbaa5a
JK		 6749 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6750 vcpu->arch.dr6 = DR6_FIXED_1;
73aaf249 6751 kvm_update_dr6(vcpu);
42dbaa5a 6752 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6753 kvm_update_dr7(vcpu);
42dbaa5a 6754
3842d135 6755 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6756 vcpu->arch.apf.msr_val = 0;
c9aaa895 6757 vcpu->arch.st.msr_val = 0;
3842d135 6758
12f9a48f
GC		 6759 kvmclock_reset(vcpu);
6760
af585b92
GN		 6761 kvm_clear_async_pf_completion_queue(vcpu);
6762 kvm_async_pf_hash_reset(vcpu);
6763 vcpu->arch.apf.halted = false;
3842d135 6764
f5132b01
GN		 6765 kvm_pmu_reset(vcpu);
6766
66f7b72e
JS		 6767 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6768 vcpu->arch.regs_avail = ~0;
6769 vcpu->arch.regs_dirty = ~0;
6770
57f252f2 6771 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 6772}
6773
66450a21
JK		 6774void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6775{
6776 struct kvm_segment cs;
6777
6778 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6779 cs.selector = vector << 8;
6780 cs.base = vector << 12;
6781 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6782 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 6783}
6784
10474ae8 6785int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6786{
ca84d1a2
ZA		 6787 struct kvm *kvm;
6788 struct kvm_vcpu *vcpu;
6789 int i;
0dd6a6ed
ZA		 6790 int ret;
6791 u64 local_tsc;
6792 u64 max_tsc = 0;
6793 bool stable, backwards_tsc = false;
18863bdd
AK		 6794
6795 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6796 ret = kvm_x86_ops->hardware_enable(garbage);
6797 if (ret != 0)
6798 return ret;
6799
6800 local_tsc = native_read_tsc();
6801 stable = !check_tsc_unstable();
6802 list_for_each_entry(kvm, &vm_list, vm_list) {
6803 kvm_for_each_vcpu(i, vcpu, kvm) {
6804 if (!stable && vcpu->cpu == smp_processor_id())
6805 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6806 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6807 backwards_tsc = true;
6808 if (vcpu->arch.last_host_tsc > max_tsc)
6809 max_tsc = vcpu->arch.last_host_tsc;
6810 }
6811 }
6812 }
6813
6814 /*
6815 * Sometimes, even reliable TSCs go backwards. This happens on
6816 * platforms that reset TSC during suspend or hibernate actions, but
6817 * maintain synchronization. We must compensate. Fortunately, we can
6818 * detect that condition here, which happens early in CPU bringup,
6819 * before any KVM threads can be running. Unfortunately, we can't
6820 * bring the TSCs fully up to date with real time, as we aren't yet far
6821 * enough into CPU bringup that we know how much real time has actually
6822 * elapsed; our helper function, get_kernel_ns() will be using boot
6823 * variables that haven't been updated yet.
6824 *
6825 * So we simply find the maximum observed TSC above, then record the
6826 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6827 * the adjustment will be applied. Note that we accumulate
6828 * adjustments, in case multiple suspend cycles happen before some VCPU
6829 * gets a chance to run again. In the event that no KVM threads get a
6830 * chance to run, we will miss the entire elapsed period, as we'll have
6831 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6832 * loose cycle time. This isn't too big a deal, since the loss will be
6833 * uniform across all VCPUs (not to mention the scenario is extremely
6834 * unlikely). It is possible that a second hibernate recovery happens
6835 * much faster than a first, causing the observed TSC here to be
6836 * smaller; this would require additional padding adjustment, which is
6837 * why we set last_host_tsc to the local tsc observed here.
6838 *
6839 * N.B. - this code below runs only on platforms with reliable TSC,
6840 * as that is the only way backwards_tsc is set above. Also note
6841 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6842 * have the same delta_cyc adjustment applied if backwards_tsc
6843 * is detected. Note further, this adjustment is only done once,
6844 * as we reset last_host_tsc on all VCPUs to stop this from being
6845 * called multiple times (one for each physical CPU bringup).
6846 *
4a969980 6847 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6848 * will be compensated by the logic in vcpu_load, which sets the TSC to
6849 * catchup mode. This will catchup all VCPUs to real time, but cannot
6850 * guarantee that they stay in perfect synchronization.
6851 */
6852 if (backwards_tsc) {
6853 u64 delta_cyc = max_tsc - local_tsc;
6854 list_for_each_entry(kvm, &vm_list, vm_list) {
6855 kvm_for_each_vcpu(i, vcpu, kvm) {
6856 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6857 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 6858 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6859 &vcpu->requests);
0dd6a6ed
ZA		 6860 }
6861
6862 /*
6863 * We have to disable TSC offset matching.. if you were
6864 * booting a VM while issuing an S4 host suspend....
6865 * you may have some problem. Solving this issue is
6866 * left as an exercise to the reader.
6867 */
6868 kvm->arch.last_tsc_nsec = 0;
6869 kvm->arch.last_tsc_write = 0;
6870 }
6871
6872 }
6873 return 0;
e9b11c17
ZX		 6874}
6875
6876void kvm_arch_hardware_disable(void *garbage)
6877{
6878 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6879 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6880}
6881
6882int kvm_arch_hardware_setup(void)
6883{
6884 return kvm_x86_ops->hardware_setup();
6885}
6886
6887void kvm_arch_hardware_unsetup(void)
6888{
6889 kvm_x86_ops->hardware_unsetup();
6890}
6891
6892void kvm_arch_check_processor_compat(void *rtn)
6893{
6894 kvm_x86_ops->check_processor_compatibility(rtn);
6895}
6896
3e515705
AK		 6897bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6898{
6899 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6900}
6901
54e9818f
GN		 6902struct static_key kvm_no_apic_vcpu __read_mostly;
6903
e9b11c17
ZX		 6904int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6905{
6906 struct page *page;
6907 struct kvm *kvm;
6908 int r;
6909
6910 BUG_ON(vcpu->kvm == NULL);
6911 kvm = vcpu->kvm;
6912
6aef266c 6913 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 6914 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6915 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6916 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6917 else
a4535290 6918 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6919
6920 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6921 if (!page) {
6922 r = -ENOMEM;
6923 goto fail;
6924 }
ad312c7c 6925 vcpu->arch.pio_data = page_address(page);
e9b11c17 6926
cc578287 6927 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6928
e9b11c17
ZX		 6929 r = kvm_mmu_create(vcpu);
6930 if (r < 0)
6931 goto fail_free_pio_data;
6932
6933 if (irqchip_in_kernel(kvm)) {
6934 r = kvm_create_lapic(vcpu);
6935 if (r < 0)
6936 goto fail_mmu_destroy;
54e9818f
GN		 6937 } else
6938 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 6939
890ca9ae
HY		 6940 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6941 GFP_KERNEL);
6942 if (!vcpu->arch.mce_banks) {
6943 r = -ENOMEM;
443c39bc 6944 goto fail_free_lapic;
890ca9ae
HY		 6945 }
6946 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6947
f1797359
WY		 6948 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
6949 r = -ENOMEM;
f5f48ee1 6950 goto fail_free_mce_banks;
f1797359 6951 }
f5f48ee1 6952
66f7b72e
JS		 6953 r = fx_init(vcpu);
6954 if (r)
6955 goto fail_free_wbinvd_dirty_mask;
6956
ba904635 6957 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 6958 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 6959
6960 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 6961 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 6962
af585b92 6963 kvm_async_pf_hash_reset(vcpu);
f5132b01 6964 kvm_pmu_init(vcpu);
af585b92 6965
e9b11c17 6966 return 0;
66f7b72e
JS		 6967fail_free_wbinvd_dirty_mask:
6968 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 6969fail_free_mce_banks:
6970 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6971fail_free_lapic:
6972 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6973fail_mmu_destroy:
6974 kvm_mmu_destroy(vcpu);
6975fail_free_pio_data:
ad312c7c 6976 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6977fail:
6978 return r;
6979}
6980
6981void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6982{
f656ce01
MT		 6983 int idx;
6984
f5132b01 6985 kvm_pmu_destroy(vcpu);
36cb93fd 6986 kfree(vcpu->arch.mce_banks);
e9b11c17 6987 kvm_free_lapic(vcpu);
f656ce01 6988 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6989 kvm_mmu_destroy(vcpu);
f656ce01 6990 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6991 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 6992 if (!irqchip_in_kernel(vcpu->kvm))
6993 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 6994}
d19a9cd2 6995
e08b9637 6996int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 6997{
e08b9637
CO		 6998 if (type)
6999 return -EINVAL;
7000
f05e70ac 7001 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7002 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7003 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7004 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7005
5550af4d
SY		 7006 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7007 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7008 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7009 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7010 &kvm->arch.irq_sources_bitmap);
5550af4d 7011
038f8c11 7012 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7013 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7014 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7015
7016 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7017
d89f5eff 7018 return 0;
d19a9cd2
ZX		 7019}
7020
7021static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7022{
9fc77441
MT		 7023 int r;
7024 r = vcpu_load(vcpu);
7025 BUG_ON(r);
d19a9cd2
ZX		 7026 kvm_mmu_unload(vcpu);
7027 vcpu_put(vcpu);
7028}
7029
7030static void kvm_free_vcpus(struct kvm *kvm)
7031{
7032 unsigned int i;
988a2cae 7033 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7034
7035 /*
7036 * Unpin any mmu pages first.
7037 */
af585b92
GN		 7038 kvm_for_each_vcpu(i, vcpu, kvm) {
7039 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7040 kvm_unload_vcpu_mmu(vcpu);
af585b92 7041 }
988a2cae
GN		 7042 kvm_for_each_vcpu(i, vcpu, kvm)
7043 kvm_arch_vcpu_free(vcpu);
7044
7045 mutex_lock(&kvm->lock);
7046 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7047 kvm->vcpus[i] = NULL;
d19a9cd2 7048
988a2cae
GN		 7049 atomic_set(&kvm->online_vcpus, 0);
7050 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7051}
7052
ad8ba2cd
SY		 7053void kvm_arch_sync_events(struct kvm *kvm)
7054{
ba4cef31 7055 kvm_free_all_assigned_devices(kvm);
aea924f6 7056 kvm_free_pit(kvm);
ad8ba2cd
SY		 7057}
7058
d19a9cd2
ZX		 7059void kvm_arch_destroy_vm(struct kvm *kvm)
7060{
27469d29
AH		 7061 if (current->mm == kvm->mm) {
7062 /*
7063 * Free memory regions allocated on behalf of userspace,
7064 * unless the the memory map has changed due to process exit
7065 * or fd copying.
7066 */
7067 struct kvm_userspace_memory_region mem;
7068 memset(&mem, 0, sizeof(mem));
7069 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7070 kvm_set_memory_region(kvm, &mem);
7071
7072 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7073 kvm_set_memory_region(kvm, &mem);
7074
7075 mem.slot = TSS_PRIVATE_MEMSLOT;
7076 kvm_set_memory_region(kvm, &mem);
7077 }
6eb55818 7078 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7079 kfree(kvm->arch.vpic);
7080 kfree(kvm->arch.vioapic);
d19a9cd2 7081 kvm_free_vcpus(kvm);
3d45830c
AK		 7082 if (kvm->arch.apic_access_page)
7083 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 7084 if (kvm->arch.ept_identity_pagetable)
7085 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 7086 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7087}
0de10343 7088
5587027c 7089void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7090 struct kvm_memory_slot *dont)
7091{
7092 int i;
7093
d89cc617
TY		 7094 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7095 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7096 kvm_kvfree(free->arch.rmap[i]);
7097 free->arch.rmap[i] = NULL;
77d11309 7098 }
d89cc617
TY		 7099 if (i == 0)
7100 continue;
7101
7102 if (!dont || free->arch.lpage_info[i - 1] !=
7103 dont->arch.lpage_info[i - 1]) {
7104 kvm_kvfree(free->arch.lpage_info[i - 1]);
7105 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7106 }
7107 }
7108}
7109
5587027c
AK		 7110int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7111 unsigned long npages)
db3fe4eb
TY		 7112{
7113 int i;
7114
d89cc617 7115 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7116 unsigned long ugfn;
7117 int lpages;
d89cc617 7118 int level = i + 1;
db3fe4eb
TY		 7119
7120 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7121 slot->base_gfn, level) + 1;
7122
d89cc617
TY		 7123 slot->arch.rmap[i] =
7124 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7125 if (!slot->arch.rmap[i])
77d11309 7126 goto out_free;
d89cc617
TY		 7127 if (i == 0)
7128 continue;
77d11309 7129
d89cc617
TY		 7130 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7131 sizeof(*slot->arch.lpage_info[i - 1]));
7132 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7133 goto out_free;
7134
7135 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7136 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7137 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7138 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7139 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7140 /*
7141 * If the gfn and userspace address are not aligned wrt each
7142 * other, or if explicitly asked to, disable large page
7143 * support for this slot
7144 */
7145 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7146 !kvm_largepages_enabled()) {
7147 unsigned long j;
7148
7149 for (j = 0; j < lpages; ++j)
d89cc617 7150 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7151 }
7152 }
7153
7154 return 0;
7155
7156out_free:
d89cc617
TY		 7157 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7158 kvm_kvfree(slot->arch.rmap[i]);
7159 slot->arch.rmap[i] = NULL;
7160 if (i == 0)
7161 continue;
7162
7163 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7164 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7165 }
7166 return -ENOMEM;
7167}
7168
e59dbe09
TY		 7169void kvm_arch_memslots_updated(struct kvm *kvm)
7170{
e6dff7d1
TY		 7171 /*
7172 * memslots->generation has been incremented.
7173 * mmio generation may have reached its maximum value.
7174 */
7175 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7176}
7177
f7784b8e
MT		 7178int kvm_arch_prepare_memory_region(struct kvm *kvm,
7179 struct kvm_memory_slot *memslot,
f7784b8e 7180 struct kvm_userspace_memory_region *mem,
7b6195a9 7181 enum kvm_mr_change change)
0de10343 7182{
7a905b14
TY		 7183 /*
7184 * Only private memory slots need to be mapped here since
7185 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7186 */
7b6195a9 7187 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7188 unsigned long userspace_addr;
604b38ac 7189
7a905b14
TY		 7190 /*
7191 * MAP_SHARED to prevent internal slot pages from being moved
7192 * by fork()/COW.
7193 */
7b6195a9 7194 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7195 PROT_READ | PROT_WRITE,
7196 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7197
7a905b14
TY		 7198 if (IS_ERR((void *)userspace_addr))
7199 return PTR_ERR((void *)userspace_addr);
604b38ac 7200
7a905b14 7201 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7202 }
7203
f7784b8e
MT		 7204 return 0;
7205}
7206
7207void kvm_arch_commit_memory_region(struct kvm *kvm,
7208 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7209 const struct kvm_memory_slot *old,
7210 enum kvm_mr_change change)
f7784b8e
MT		 7211{
7212
8482644a 7213 int nr_mmu_pages = 0;
f7784b8e 7214
8482644a 7215 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7216 int ret;
7217
8482644a
TY		 7218 ret = vm_munmap(old->userspace_addr,
7219 old->npages * PAGE_SIZE);
f7784b8e
MT		 7220 if (ret < 0)
7221 printk(KERN_WARNING
7222 "kvm_vm_ioctl_set_memory_region: "
7223 "failed to munmap memory\n");
7224 }
7225
48c0e4e9
XG		 7226 if (!kvm->arch.n_requested_mmu_pages)
7227 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7228
48c0e4e9 7229 if (nr_mmu_pages)
0de10343 7230 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7231 /*
7232 * Write protect all pages for dirty logging.
7233 * Existing largepage mappings are destroyed here and new ones will
7234 * not be created until the end of the logging.
7235 */
8482644a 7236 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7237 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7238}
1d737c8a 7239
2df72e9b 7240void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7241{
6ca18b69 7242 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7243}
7244
2df72e9b
MT		 7245void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7246 struct kvm_memory_slot *slot)
7247{
6ca18b69 7248 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7249}
7250
1d737c8a
ZX		 7251int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7252{
af585b92
GN		 7253 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7254 !vcpu->arch.apf.halted)
7255 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7256 || kvm_apic_has_events(vcpu)
6aef266c 7257 || vcpu->arch.pv.pv_unhalted
7460fb4a 7258 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7259 (kvm_arch_interrupt_allowed(vcpu) &&
7260 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7261}
5736199a 7262
b6d33834 7263int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7264{
b6d33834 7265 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7266}
78646121
GN		 7267
7268int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7269{
7270 return kvm_x86_ops->interrupt_allowed(vcpu);
7271}
229456fc 7272
f92653ee
JK		 7273bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7274{
7275 unsigned long current_rip = kvm_rip_read(vcpu) +
7276 get_segment_base(vcpu, VCPU_SREG_CS);
7277
7278 return current_rip == linear_rip;
7279}
7280EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7281
94fe45da
JK		 7282unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7283{
7284 unsigned long rflags;
7285
7286 rflags = kvm_x86_ops->get_rflags(vcpu);
7287 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7288 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7289 return rflags;
7290}
7291EXPORT_SYMBOL_GPL(kvm_get_rflags);
7292
7293void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7294{
7295 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7296 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7297 rflags |= X86_EFLAGS_TF;
94fe45da 7298 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 7299 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7300}
7301EXPORT_SYMBOL_GPL(kvm_set_rflags);
7302
56028d08
GN		 7303void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7304{
7305 int r;
7306
fb67e14f 7307 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7308 work->wakeup_all)
56028d08
GN		 7309 return;
7310
7311 r = kvm_mmu_reload(vcpu);
7312 if (unlikely(r))
7313 return;
7314
fb67e14f
XG		 7315 if (!vcpu->arch.mmu.direct_map &&
7316 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7317 return;
7318
56028d08
GN		 7319 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7320}
7321
af585b92
GN		 7322static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7323{
7324 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7325}
7326
7327static inline u32 kvm_async_pf_next_probe(u32 key)
7328{
7329 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7330}
7331
7332static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7333{
7334 u32 key = kvm_async_pf_hash_fn(gfn);
7335
7336 while (vcpu->arch.apf.gfns[key] != ~0)
7337 key = kvm_async_pf_next_probe(key);
7338
7339 vcpu->arch.apf.gfns[key] = gfn;
7340}
7341
7342static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7343{
7344 int i;
7345 u32 key = kvm_async_pf_hash_fn(gfn);
7346
7347 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7348 (vcpu->arch.apf.gfns[key] != gfn &&
7349 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7350 key = kvm_async_pf_next_probe(key);
7351
7352 return key;
7353}
7354
7355bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7356{
7357 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7358}
7359
7360static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7361{
7362 u32 i, j, k;
7363
7364 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7365 while (true) {
7366 vcpu->arch.apf.gfns[i] = ~0;
7367 do {
7368 j = kvm_async_pf_next_probe(j);
7369 if (vcpu->arch.apf.gfns[j] == ~0)
7370 return;
7371 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7372 /*
7373 * k lies cyclically in ]i,j]
7374 * | i.k.j |
7375 * |....j i.k.| or |.k..j i...|
7376 */
7377 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7378 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7379 i = j;
7380 }
7381}
7382
7c90705b
GN		 7383static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7384{
7385
7386 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7387 sizeof(val));
7388}
7389
af585b92
GN		 7390void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7391 struct kvm_async_pf *work)
7392{
6389ee94
AK		 7393 struct x86_exception fault;
7394
7c90705b 7395 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7396 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7397
7398 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7399 (vcpu->arch.apf.send_user_only &&
7400 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7401 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7402 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7403 fault.vector = PF_VECTOR;
7404 fault.error_code_valid = true;
7405 fault.error_code = 0;
7406 fault.nested_page_fault = false;
7407 fault.address = work->arch.token;
7408 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7409 }
af585b92
GN		 7410}
7411
7412void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7413 struct kvm_async_pf *work)
7414{
6389ee94
AK		 7415 struct x86_exception fault;
7416
7c90705b 7417 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7418 if (work->wakeup_all)
7c90705b
GN		 7419 work->arch.token = ~0; /* broadcast wakeup */
7420 else
7421 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7422
7423 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7424 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7425 fault.vector = PF_VECTOR;
7426 fault.error_code_valid = true;
7427 fault.error_code = 0;
7428 fault.nested_page_fault = false;
7429 fault.address = work->arch.token;
7430 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7431 }
e6d53e3b 7432 vcpu->arch.apf.halted = false;
a4fa1635 7433 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7434}
7435
7436bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7437{
7438 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7439 return true;
7440 else
7441 return !kvm_event_needs_reinjection(vcpu) &&
7442 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7443}
7444
e0f0bbc5
AW		 7445void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7446{
7447 atomic_inc(&kvm->arch.noncoherent_dma_count);
7448}
7449EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7450
7451void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7452{
7453 atomic_dec(&kvm->arch.noncoherent_dma_count);
7454}
7455EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7456
7457bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7458{
7459 return atomic_read(&kvm->arch.noncoherent_dma_count);
7460}
7461EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7462
229456fc
MT		 7463EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7464EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7465EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7466EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7467EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7468EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7469EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7470EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7471EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7472EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7473EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7474EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7475EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
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