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KVM: MMU: make kvm_mmu_available_pages robust against n_used_mmu_pages > n_max_mmu_pages
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 90
97896d04 91struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 92EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 93
476bc001
RR		 94static bool ignore_msrs = 0;
95module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 96
92a1f12d
JR		 97bool kvm_has_tsc_control;
98EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
99u32 kvm_max_guest_tsc_khz;
100EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
101
cc578287
ZA		 102/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
103static u32 tsc_tolerance_ppm = 250;
104module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
105
18863bdd
AK		 106#define KVM_NR_SHARED_MSRS 16
107
108struct kvm_shared_msrs_global {
109 int nr;
2bf78fa7 110 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 111};
112
113struct kvm_shared_msrs {
114 struct user_return_notifier urn;
115 bool registered;
2bf78fa7
SY		 116 struct kvm_shared_msr_values {
117 u64 host;
118 u64 curr;
119 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 120};
121
122static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 123static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 124
417bc304 125struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 126 { "pf_fixed", VCPU_STAT(pf_fixed) },
127 { "pf_guest", VCPU_STAT(pf_guest) },
128 { "tlb_flush", VCPU_STAT(tlb_flush) },
129 { "invlpg", VCPU_STAT(invlpg) },
130 { "exits", VCPU_STAT(exits) },
131 { "io_exits", VCPU_STAT(io_exits) },
132 { "mmio_exits", VCPU_STAT(mmio_exits) },
133 { "signal_exits", VCPU_STAT(signal_exits) },
134 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 135 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 136 { "halt_exits", VCPU_STAT(halt_exits) },
137 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 138 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 139 { "request_irq", VCPU_STAT(request_irq_exits) },
140 { "irq_exits", VCPU_STAT(irq_exits) },
141 { "host_state_reload", VCPU_STAT(host_state_reload) },
142 { "efer_reload", VCPU_STAT(efer_reload) },
143 { "fpu_reload", VCPU_STAT(fpu_reload) },
144 { "insn_emulation", VCPU_STAT(insn_emulation) },
145 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 146 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 147 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 148 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
149 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
150 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
151 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
152 { "mmu_flooded", VM_STAT(mmu_flooded) },
153 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 154 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 155 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 156 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 157 { "largepages", VM_STAT(lpages) },
417bc304
HB		 158 { NULL }
159};
160
2acf923e
DC		 161u64 __read_mostly host_xcr0;
162
b6785def 163static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 164
57f252f2 165static void kvm_vcpu_reset(struct kvm_vcpu *vcpu);
d6aa1000 166
af585b92
GN		 167static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
168{
169 int i;
170 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
171 vcpu->arch.apf.gfns[i] = ~0;
172}
173
18863bdd
AK		 174static void kvm_on_user_return(struct user_return_notifier *urn)
175{
176 unsigned slot;
18863bdd
AK		 177 struct kvm_shared_msrs *locals
178 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 179 struct kvm_shared_msr_values *values;
18863bdd
AK		 180
181 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 182 values = &locals->values[slot];
183 if (values->host != values->curr) {
184 wrmsrl(shared_msrs_global.msrs[slot], values->host);
185 values->curr = values->host;
18863bdd
AK		 186 }
187 }
188 locals->registered = false;
189 user_return_notifier_unregister(urn);
190}
191
2bf78fa7 192static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 193{
18863bdd 194 u64 value;
013f6a5d
MT		 195 unsigned int cpu = smp_processor_id();
196 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 197
2bf78fa7
SY		 198 /* only read, and nobody should modify it at this time,
199 * so don't need lock */
200 if (slot >= shared_msrs_global.nr) {
201 printk(KERN_ERR "kvm: invalid MSR slot!");
202 return;
203 }
204 rdmsrl_safe(msr, &value);
205 smsr->values[slot].host = value;
206 smsr->values[slot].curr = value;
207}
208
209void kvm_define_shared_msr(unsigned slot, u32 msr)
210{
18863bdd
AK		 211 if (slot >= shared_msrs_global.nr)
212 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 213 shared_msrs_global.msrs[slot] = msr;
214 /* we need ensured the shared_msr_global have been updated */
215 smp_wmb();
18863bdd
AK		 216}
217EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
218
219static void kvm_shared_msr_cpu_online(void)
220{
221 unsigned i;
18863bdd
AK		 222
223 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 224 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 225}
226
d5696725 227void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 228{
013f6a5d
MT		 229 unsigned int cpu = smp_processor_id();
230 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 231
2bf78fa7 232 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 233 return;
2bf78fa7
SY		 234 smsr->values[slot].curr = value;
235 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 236 if (!smsr->registered) {
237 smsr->urn.on_user_return = kvm_on_user_return;
238 user_return_notifier_register(&smsr->urn);
239 smsr->registered = true;
240 }
241}
242EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
243
3548bab5
AK		 244static void drop_user_return_notifiers(void *ignore)
245{
013f6a5d
MT		 246 unsigned int cpu = smp_processor_id();
247 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 248
249 if (smsr->registered)
250 kvm_on_user_return(&smsr->urn);
251}
252
6866b83e
CO		 253u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
254{
8a5a87d9 255 return vcpu->arch.apic_base;
6866b83e
CO		 256}
257EXPORT_SYMBOL_GPL(kvm_get_apic_base);
258
259void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
260{
261 /* TODO: reserve bits check */
8a5a87d9 262 kvm_lapic_set_base(vcpu, data);
6866b83e
CO		 263}
264EXPORT_SYMBOL_GPL(kvm_set_apic_base);
265
3fd28fce
ED		 266#define EXCPT_BENIGN 0
267#define EXCPT_CONTRIBUTORY 1
268#define EXCPT_PF 2
269
270static int exception_class(int vector)
271{
272 switch (vector) {
273 case PF_VECTOR:
274 return EXCPT_PF;
275 case DE_VECTOR:
276 case TS_VECTOR:
277 case NP_VECTOR:
278 case SS_VECTOR:
279 case GP_VECTOR:
280 return EXCPT_CONTRIBUTORY;
281 default:
282 break;
283 }
284 return EXCPT_BENIGN;
285}
286
287static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 288 unsigned nr, bool has_error, u32 error_code,
289 bool reinject)
3fd28fce
ED		 290{
291 u32 prev_nr;
292 int class1, class2;
293
3842d135
AK		 294 kvm_make_request(KVM_REQ_EVENT, vcpu);
295
3fd28fce
ED		 296 if (!vcpu->arch.exception.pending) {
297 queue:
298 vcpu->arch.exception.pending = true;
299 vcpu->arch.exception.has_error_code = has_error;
300 vcpu->arch.exception.nr = nr;
301 vcpu->arch.exception.error_code = error_code;
3f0fd292 302 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 303 return;
304 }
305
306 /* to check exception */
307 prev_nr = vcpu->arch.exception.nr;
308 if (prev_nr == DF_VECTOR) {
309 /* triple fault -> shutdown */
a8eeb04a 310 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 311 return;
312 }
313 class1 = exception_class(prev_nr);
314 class2 = exception_class(nr);
315 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
316 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
317 /* generate double fault per SDM Table 5-5 */
318 vcpu->arch.exception.pending = true;
319 vcpu->arch.exception.has_error_code = true;
320 vcpu->arch.exception.nr = DF_VECTOR;
321 vcpu->arch.exception.error_code = 0;
322 } else
323 /* replace previous exception with a new one in a hope
324 that instruction re-execution will regenerate lost
325 exception */
326 goto queue;
327}
328
298101da
AK		 329void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
330{
ce7ddec4 331 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 332}
333EXPORT_SYMBOL_GPL(kvm_queue_exception);
334
ce7ddec4
JR		 335void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
336{
337 kvm_multiple_exception(vcpu, nr, false, 0, true);
338}
339EXPORT_SYMBOL_GPL(kvm_requeue_exception);
340
db8fcefa 341void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 342{
db8fcefa
AP		 343 if (err)
344 kvm_inject_gp(vcpu, 0);
345 else
346 kvm_x86_ops->skip_emulated_instruction(vcpu);
347}
348EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 349
6389ee94 350void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 351{
352 ++vcpu->stat.pf_guest;
6389ee94
AK		 353 vcpu->arch.cr2 = fault->address;
354 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 355}
27d6c865 356EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 357
6389ee94 358void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 359{
6389ee94
AK		 360 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
361 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 362 else
6389ee94 363 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 364}
365
3419ffc8
SY		 366void kvm_inject_nmi(struct kvm_vcpu *vcpu)
367{
7460fb4a
AK		 368 atomic_inc(&vcpu->arch.nmi_queued);
369 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 370}
371EXPORT_SYMBOL_GPL(kvm_inject_nmi);
372
298101da
AK		 373void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
374{
ce7ddec4 375 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 376}
377EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
378
ce7ddec4
JR		 379void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
380{
381 kvm_multiple_exception(vcpu, nr, true, error_code, true);
382}
383EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
384
0a79b009
AK		 385/*
386 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
387 * a #GP and return false.
388 */
389bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 390{
0a79b009
AK		 391 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
392 return true;
393 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
394 return false;
298101da 395}
0a79b009 396EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 397
ec92fe44
JR		 398/*
399 * This function will be used to read from the physical memory of the currently
400 * running guest. The difference to kvm_read_guest_page is that this function
401 * can read from guest physical or from the guest's guest physical memory.
402 */
403int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
404 gfn_t ngfn, void *data, int offset, int len,
405 u32 access)
406{
407 gfn_t real_gfn;
408 gpa_t ngpa;
409
410 ngpa = gfn_to_gpa(ngfn);
411 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
412 if (real_gfn == UNMAPPED_GVA)
413 return -EFAULT;
414
415 real_gfn = gpa_to_gfn(real_gfn);
416
417 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
418}
419EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
420
3d06b8bf
JR		 421int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
422 void *data, int offset, int len, u32 access)
423{
424 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
425 data, offset, len, access);
426}
427
a03490ed
CO		 428/*
429 * Load the pae pdptrs. Return true is they are all valid.
430 */
ff03a073 431int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 432{
433 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
434 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
435 int i;
436 int ret;
ff03a073 437 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 438
ff03a073
JR		 439 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
440 offset * sizeof(u64), sizeof(pdpte),
441 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 442 if (ret < 0) {
443 ret = 0;
444 goto out;
445 }
446 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 447 if (is_present_gpte(pdpte[i]) &&
20c466b5 448 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 449 ret = 0;
450 goto out;
451 }
452 }
453 ret = 1;
454
ff03a073 455 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 456 __set_bit(VCPU_EXREG_PDPTR,
457 (unsigned long *)&vcpu->arch.regs_avail);
458 __set_bit(VCPU_EXREG_PDPTR,
459 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 460out:
a03490ed
CO		 461
462 return ret;
463}
cc4b6871 464EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 465
d835dfec
AK		 466static bool pdptrs_changed(struct kvm_vcpu *vcpu)
467{
ff03a073 468 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 469 bool changed = true;
3d06b8bf
JR		 470 int offset;
471 gfn_t gfn;
d835dfec
AK		 472 int r;
473
474 if (is_long_mode(vcpu) || !is_pae(vcpu))
475 return false;
476
6de4f3ad
AK		 477 if (!test_bit(VCPU_EXREG_PDPTR,
478 (unsigned long *)&vcpu->arch.regs_avail))
479 return true;
480
9f8fe504
AK		 481 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
482 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 483 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
484 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 485 if (r < 0)
486 goto out;
ff03a073 487 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 488out:
d835dfec
AK		 489
490 return changed;
491}
492
49a9b07e 493int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 494{
aad82703
SY		 495 unsigned long old_cr0 = kvm_read_cr0(vcpu);
496 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
497 X86_CR0_CD | X86_CR0_NW;
498
f9a48e6a
AK		 499 cr0 |= X86_CR0_ET;
500
ab344828 501#ifdef CONFIG_X86_64
0f12244f
GN		 502 if (cr0 & 0xffffffff00000000UL)
503 return 1;
ab344828
GN		 504#endif
505
506 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 507
0f12244f
GN		 508 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
509 return 1;
a03490ed 510
0f12244f
GN		 511 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
512 return 1;
a03490ed
CO		 513
514 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
515#ifdef CONFIG_X86_64
f6801dff 516 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 517 int cs_db, cs_l;
518
0f12244f
GN		 519 if (!is_pae(vcpu))
520 return 1;
a03490ed 521 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 522 if (cs_l)
523 return 1;
a03490ed
CO		 524 } else
525#endif
ff03a073 526 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 527 kvm_read_cr3(vcpu)))
0f12244f 528 return 1;
a03490ed
CO		 529 }
530
ad756a16
MJ		 531 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
532 return 1;
533
a03490ed 534 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 535
d170c419 536 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 537 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 538 kvm_async_pf_hash_reset(vcpu);
539 }
e5f3f027 540
aad82703
SY		 541 if ((cr0 ^ old_cr0) & update_bits)
542 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 543 return 0;
544}
2d3ad1f4 545EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 546
2d3ad1f4 547void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 548{
49a9b07e 549 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 550}
2d3ad1f4 551EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 552
2acf923e
DC		 553int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
554{
555 u64 xcr0;
556
557 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
558 if (index != XCR_XFEATURE_ENABLED_MASK)
559 return 1;
560 xcr0 = xcr;
561 if (kvm_x86_ops->get_cpl(vcpu) != 0)
562 return 1;
563 if (!(xcr0 & XSTATE_FP))
564 return 1;
565 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
566 return 1;
567 if (xcr0 & ~host_xcr0)
568 return 1;
569 vcpu->arch.xcr0 = xcr0;
570 vcpu->guest_xcr0_loaded = 0;
571 return 0;
572}
573
574int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
575{
576 if (__kvm_set_xcr(vcpu, index, xcr)) {
577 kvm_inject_gp(vcpu, 0);
578 return 1;
579 }
580 return 0;
581}
582EXPORT_SYMBOL_GPL(kvm_set_xcr);
583
a83b29c6 584int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 585{
fc78f519 586 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 587 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
588 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 589 if (cr4 & CR4_RESERVED_BITS)
590 return 1;
a03490ed 591
2acf923e
DC		 592 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
593 return 1;
594
c68b734f
YW		 595 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
596 return 1;
597
74dc2b4f
YW		 598 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_RDWRGSFS))
599 return 1;
600
a03490ed 601 if (is_long_mode(vcpu)) {
0f12244f
GN		 602 if (!(cr4 & X86_CR4_PAE))
603 return 1;
a2edf57f
AK		 604 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
605 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 606 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
607 kvm_read_cr3(vcpu)))
0f12244f
GN		 608 return 1;
609
ad756a16
MJ		 610 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
611 if (!guest_cpuid_has_pcid(vcpu))
612 return 1;
613
614 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
615 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
616 return 1;
617 }
618
5e1746d6 619 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 620 return 1;
a03490ed 621
ad756a16
MJ		 622 if (((cr4 ^ old_cr4) & pdptr_bits) ||
623 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 624 kvm_mmu_reset_context(vcpu);
0f12244f 625
2acf923e 626 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 627 kvm_update_cpuid(vcpu);
2acf923e 628
0f12244f
GN		 629 return 0;
630}
2d3ad1f4 631EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 632
2390218b 633int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 634{
9f8fe504 635 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 636 kvm_mmu_sync_roots(vcpu);
d835dfec 637 kvm_mmu_flush_tlb(vcpu);
0f12244f 638 return 0;
d835dfec
AK		 639 }
640
a03490ed 641 if (is_long_mode(vcpu)) {
471842ec 642 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
ad756a16
MJ		 643 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
644 return 1;
645 } else
646 if (cr3 & CR3_L_MODE_RESERVED_BITS)
647 return 1;
a03490ed
CO		 648 } else {
649 if (is_pae(vcpu)) {
0f12244f
GN		 650 if (cr3 & CR3_PAE_RESERVED_BITS)
651 return 1;
ff03a073
JR		 652 if (is_paging(vcpu) &&
653 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 654 return 1;
a03490ed
CO		 655 }
656 /*
657 * We don't check reserved bits in nonpae mode, because
658 * this isn't enforced, and VMware depends on this.
659 */
660 }
661
a03490ed
CO		 662 /*
663 * Does the new cr3 value map to physical memory? (Note, we
664 * catch an invalid cr3 even in real-mode, because it would
665 * cause trouble later on when we turn on paging anyway.)
666 *
667 * A real CPU would silently accept an invalid cr3 and would
668 * attempt to use it - with largely undefined (and often hard
669 * to debug) behavior on the guest side.
670 */
671 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
0f12244f
GN		 672 return 1;
673 vcpu->arch.cr3 = cr3;
aff48baa 674 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
0f12244f
GN		 675 vcpu->arch.mmu.new_cr3(vcpu);
676 return 0;
677}
2d3ad1f4 678EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 679
eea1cff9 680int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 681{
0f12244f
GN		 682 if (cr8 & CR8_RESERVED_BITS)
683 return 1;
a03490ed
CO		 684 if (irqchip_in_kernel(vcpu->kvm))
685 kvm_lapic_set_tpr(vcpu, cr8);
686 else
ad312c7c 687 vcpu->arch.cr8 = cr8;
0f12244f
GN		 688 return 0;
689}
2d3ad1f4 690EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 691
2d3ad1f4 692unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 693{
694 if (irqchip_in_kernel(vcpu->kvm))
695 return kvm_lapic_get_cr8(vcpu);
696 else
ad312c7c 697 return vcpu->arch.cr8;
a03490ed 698}
2d3ad1f4 699EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 700
c8639010
JK		 701static void kvm_update_dr7(struct kvm_vcpu *vcpu)
702{
703 unsigned long dr7;
704
705 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
706 dr7 = vcpu->arch.guest_debug_dr7;
707 else
708 dr7 = vcpu->arch.dr7;
709 kvm_x86_ops->set_dr7(vcpu, dr7);
710 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
711}
712
338dbc97 713static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 714{
715 switch (dr) {
716 case 0 ... 3:
717 vcpu->arch.db[dr] = val;
718 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
719 vcpu->arch.eff_db[dr] = val;
720 break;
721 case 4:
338dbc97
GN		 722 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
723 return 1; /* #UD */
020df079
GN		 724 /* fall through */
725 case 6:
338dbc97
GN		 726 if (val & 0xffffffff00000000ULL)
727 return -1; /* #GP */
020df079
GN		 728 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
729 break;
730 case 5:
338dbc97
GN		 731 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
732 return 1; /* #UD */
020df079
GN		 733 /* fall through */
734 default: /* 7 */
338dbc97
GN		 735 if (val & 0xffffffff00000000ULL)
736 return -1; /* #GP */
020df079 737 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 738 kvm_update_dr7(vcpu);
020df079
GN		 739 break;
740 }
741
742 return 0;
743}
338dbc97
GN		 744
745int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
746{
747 int res;
748
749 res = __kvm_set_dr(vcpu, dr, val);
750 if (res > 0)
751 kvm_queue_exception(vcpu, UD_VECTOR);
752 else if (res < 0)
753 kvm_inject_gp(vcpu, 0);
754
755 return res;
756}
020df079
GN		 757EXPORT_SYMBOL_GPL(kvm_set_dr);
758
338dbc97 759static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 760{
761 switch (dr) {
762 case 0 ... 3:
763 *val = vcpu->arch.db[dr];
764 break;
765 case 4:
338dbc97 766 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 767 return 1;
020df079
GN		 768 /* fall through */
769 case 6:
770 *val = vcpu->arch.dr6;
771 break;
772 case 5:
338dbc97 773 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 774 return 1;
020df079
GN		 775 /* fall through */
776 default: /* 7 */
777 *val = vcpu->arch.dr7;
778 break;
779 }
780
781 return 0;
782}
338dbc97
GN		 783
784int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
785{
786 if (_kvm_get_dr(vcpu, dr, val)) {
787 kvm_queue_exception(vcpu, UD_VECTOR);
788 return 1;
789 }
790 return 0;
791}
020df079
GN		 792EXPORT_SYMBOL_GPL(kvm_get_dr);
793
022cd0e8
AK		 794bool kvm_rdpmc(struct kvm_vcpu *vcpu)
795{
796 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
797 u64 data;
798 int err;
799
800 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
801 if (err)
802 return err;
803 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
804 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
805 return err;
806}
807EXPORT_SYMBOL_GPL(kvm_rdpmc);
808
043405e1
CO		 809/*
810 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
811 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
812 *
813 * This list is modified at module load time to reflect the
e3267cbb
GC		 814 * capabilities of the host cpu. This capabilities test skips MSRs that are
815 * kvm-specific. Those are put in the beginning of the list.
043405e1 816 */
e3267cbb 817
439793d4 818#define KVM_SAVE_MSRS_BEGIN 10
043405e1 819static u32 msrs_to_save[] = {
e3267cbb 820 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 821 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 822 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 823 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 824 MSR_KVM_PV_EOI_EN,
043405e1 825 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 826 MSR_STAR,
043405e1
CO		 827#ifdef CONFIG_X86_64
828 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
829#endif
e90aa41e 830 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 831};
832
833static unsigned num_msrs_to_save;
834
f1d24831 835static const u32 emulated_msrs[] = {
ba904635 836 MSR_IA32_TSC_ADJUST,
a3e06bbe 837 MSR_IA32_TSCDEADLINE,
043405e1 838 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 839 MSR_IA32_MCG_STATUS,
840 MSR_IA32_MCG_CTL,
043405e1
CO		 841};
842
b69e8cae 843static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 844{
aad82703
SY		 845 u64 old_efer = vcpu->arch.efer;
846
b69e8cae
RJ		 847 if (efer & efer_reserved_bits)
848 return 1;
15c4a640
CO		 849
850 if (is_paging(vcpu)
b69e8cae
RJ		 851 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
852 return 1;
15c4a640 853
1b2fd70c
AG		 854 if (efer & EFER_FFXSR) {
855 struct kvm_cpuid_entry2 *feat;
856
857 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 858 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
859 return 1;
1b2fd70c
AG		 860 }
861
d8017474
AG		 862 if (efer & EFER_SVME) {
863 struct kvm_cpuid_entry2 *feat;
864
865 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae
RJ		 866 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
867 return 1;
d8017474
AG		 868 }
869
15c4a640 870 efer &= ~EFER_LMA;
f6801dff 871 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 872
a3d204e2
SY		 873 kvm_x86_ops->set_efer(vcpu, efer);
874
aad82703
SY		 875 /* Update reserved bits */
876 if ((efer ^ old_efer) & EFER_NX)
877 kvm_mmu_reset_context(vcpu);
878
b69e8cae 879 return 0;
15c4a640
CO		 880}
881
f2b4b7dd
JR		 882void kvm_enable_efer_bits(u64 mask)
883{
884 efer_reserved_bits &= ~mask;
885}
886EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
887
888
15c4a640
CO		 889/*
890 * Writes msr value into into the appropriate "register".
891 * Returns 0 on success, non-0 otherwise.
892 * Assumes vcpu_load() was already called.
893 */
8fe8ab46 894int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 895{
8fe8ab46 896 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 897}
898
313a3dc7
CO		 899/*
900 * Adapt set_msr() to msr_io()'s calling convention
901 */
902static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
903{
8fe8ab46
WA		 904 struct msr_data msr;
905
906 msr.data = *data;
907 msr.index = index;
908 msr.host_initiated = true;
909 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 910}
911
16e8d74d
MT		 912#ifdef CONFIG_X86_64
913struct pvclock_gtod_data {
914 seqcount_t seq;
915
916 struct { /* extract of a clocksource struct */
917 int vclock_mode;
918 cycle_t cycle_last;
919 cycle_t mask;
920 u32 mult;
921 u32 shift;
922 } clock;
923
924 /* open coded 'struct timespec' */
925 u64 monotonic_time_snsec;
926 time_t monotonic_time_sec;
927};
928
929static struct pvclock_gtod_data pvclock_gtod_data;
930
931static void update_pvclock_gtod(struct timekeeper *tk)
932{
933 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
934
935 write_seqcount_begin(&vdata->seq);
936
937 /* copy pvclock gtod data */
938 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
939 vdata->clock.cycle_last = tk->clock->cycle_last;
940 vdata->clock.mask = tk->clock->mask;
941 vdata->clock.mult = tk->mult;
942 vdata->clock.shift = tk->shift;
943
944 vdata->monotonic_time_sec = tk->xtime_sec
945 + tk->wall_to_monotonic.tv_sec;
946 vdata->monotonic_time_snsec = tk->xtime_nsec
947 + (tk->wall_to_monotonic.tv_nsec
948 << tk->shift);
949 while (vdata->monotonic_time_snsec >=
950 (((u64)NSEC_PER_SEC) << tk->shift)) {
951 vdata->monotonic_time_snsec -=
952 ((u64)NSEC_PER_SEC) << tk->shift;
953 vdata->monotonic_time_sec++;
954 }
955
956 write_seqcount_end(&vdata->seq);
957}
958#endif
959
960
18068523
GOC		 961static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
962{
9ed3c444
AK		 963 int version;
964 int r;
50d0a0f9 965 struct pvclock_wall_clock wc;
923de3cf 966 struct timespec boot;
18068523
GOC		 967
968 if (!wall_clock)
969 return;
970
9ed3c444
AK		 971 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
972 if (r)
973 return;
974
975 if (version & 1)
976 ++version; /* first time write, random junk */
977
978 ++version;
18068523 979
18068523
GOC		 980 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
981
50d0a0f9
GH		 982 /*
983 * The guest calculates current wall clock time by adding
34c238a1 984 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 985 * wall clock specified here. guest system time equals host
986 * system time for us, thus we must fill in host boot time here.
987 */
923de3cf 988 getboottime(&boot);
50d0a0f9 989
4b648665
BR		 990 if (kvm->arch.kvmclock_offset) {
991 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
992 boot = timespec_sub(boot, ts);
993 }
50d0a0f9
GH		 994 wc.sec = boot.tv_sec;
995 wc.nsec = boot.tv_nsec;
996 wc.version = version;
18068523
GOC		 997
998 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
999
1000 version++;
1001 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1002}
1003
50d0a0f9
GH		 1004static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1005{
1006 uint32_t quotient, remainder;
1007
1008 /* Don't try to replace with do_div(), this one calculates
1009 * "(dividend << 32) / divisor" */
1010 __asm__ ( "divl %4"
1011 : "=a" (quotient), "=d" (remainder)
1012 : "0" (0), "1" (dividend), "r" (divisor) );
1013 return quotient;
1014}
1015
5f4e3f88
ZA		 1016static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1017 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1018{
5f4e3f88 1019 uint64_t scaled64;
50d0a0f9
GH		 1020 int32_t shift = 0;
1021 uint64_t tps64;
1022 uint32_t tps32;
1023
5f4e3f88
ZA		 1024 tps64 = base_khz * 1000LL;
1025 scaled64 = scaled_khz * 1000LL;
50933623 1026 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1027 tps64 >>= 1;
1028 shift--;
1029 }
1030
1031 tps32 = (uint32_t)tps64;
50933623
JK		 1032 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1033 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1034 scaled64 >>= 1;
1035 else
1036 tps32 <<= 1;
50d0a0f9
GH		 1037 shift++;
1038 }
1039
5f4e3f88
ZA		 1040 *pshift = shift;
1041 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1042
5f4e3f88
ZA		 1043 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1044 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1045}
1046
759379dd
ZA		 1047static inline u64 get_kernel_ns(void)
1048{
1049 struct timespec ts;
1050
1051 WARN_ON(preemptible());
1052 ktime_get_ts(&ts);
1053 monotonic_to_bootbased(&ts);
1054 return timespec_to_ns(&ts);
50d0a0f9
GH		 1055}
1056
d828199e 1057#ifdef CONFIG_X86_64
16e8d74d 1058static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1059#endif
16e8d74d 1060
c8076604 1061static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1062unsigned long max_tsc_khz;
c8076604 1063
cc578287 1064static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1065{
cc578287
ZA		 1066 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1067 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1068}
1069
cc578287 1070static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1071{
cc578287
ZA		 1072 u64 v = (u64)khz * (1000000 + ppm);
1073 do_div(v, 1000000);
1074 return v;
1e993611
JR		 1075}
1076
cc578287 1077static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1078{
cc578287
ZA		 1079 u32 thresh_lo, thresh_hi;
1080 int use_scaling = 0;
217fc9cf 1081
03ba32ca
MT		 1082 /* tsc_khz can be zero if TSC calibration fails */
1083 if (this_tsc_khz == 0)
1084 return;
1085
c285545f
ZA		 1086 /* Compute a scale to convert nanoseconds in TSC cycles */
1087 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1088 &vcpu->arch.virtual_tsc_shift,
1089 &vcpu->arch.virtual_tsc_mult);
1090 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1091
1092 /*
1093 * Compute the variation in TSC rate which is acceptable
1094 * within the range of tolerance and decide if the
1095 * rate being applied is within that bounds of the hardware
1096 * rate. If so, no scaling or compensation need be done.
1097 */
1098 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1099 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1100 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1101 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1102 use_scaling = 1;
1103 }
1104 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1105}
1106
1107static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1108{
e26101b1 1109 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1110 vcpu->arch.virtual_tsc_mult,
1111 vcpu->arch.virtual_tsc_shift);
e26101b1 1112 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1113 return tsc;
1114}
1115
b48aa97e
MT		 1116void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1117{
1118#ifdef CONFIG_X86_64
1119 bool vcpus_matched;
1120 bool do_request = false;
1121 struct kvm_arch *ka = &vcpu->kvm->arch;
1122 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1123
1124 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1125 atomic_read(&vcpu->kvm->online_vcpus));
1126
1127 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1128 if (!ka->use_master_clock)
1129 do_request = 1;
1130
1131 if (!vcpus_matched && ka->use_master_clock)
1132 do_request = 1;
1133
1134 if (do_request)
1135 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1136
1137 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1138 atomic_read(&vcpu->kvm->online_vcpus),
1139 ka->use_master_clock, gtod->clock.vclock_mode);
1140#endif
1141}
1142
ba904635
WA		 1143static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1144{
1145 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1146 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1147}
1148
8fe8ab46 1149void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1150{
1151 struct kvm *kvm = vcpu->kvm;
f38e098f 1152 u64 offset, ns, elapsed;
99e3e30a 1153 unsigned long flags;
02626b6a 1154 s64 usdiff;
b48aa97e 1155 bool matched;
8fe8ab46 1156 u64 data = msr->data;
99e3e30a 1157
038f8c11 1158 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1159 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1160 ns = get_kernel_ns();
f38e098f 1161 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1162
03ba32ca
MT		 1163 if (vcpu->arch.virtual_tsc_khz) {
1164 /* n.b - signed multiplication and division required */
1165 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1166#ifdef CONFIG_X86_64
03ba32ca 1167 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1168#else
03ba32ca
MT		 1169 /* do_div() only does unsigned */
1170 asm("idivl %2; xor %%edx, %%edx"
1171 : "=A"(usdiff)
1172 : "A"(usdiff * 1000), "rm"(vcpu->arch.virtual_tsc_khz));
5d3cb0f6 1173#endif
03ba32ca
MT		 1174 do_div(elapsed, 1000);
1175 usdiff -= elapsed;
1176 if (usdiff < 0)
1177 usdiff = -usdiff;
1178 } else
1179 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1180
1181 /*
5d3cb0f6
ZA		 1182 * Special case: TSC write with a small delta (1 second) of virtual
1183 * cycle time against real time is interpreted as an attempt to
1184 * synchronize the CPU.
1185 *
1186 * For a reliable TSC, we can match TSC offsets, and for an unstable
1187 * TSC, we add elapsed time in this computation. We could let the
1188 * compensation code attempt to catch up if we fall behind, but
1189 * it's better to try to match offsets from the beginning.
1190 */
02626b6a 1191 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1192 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1193 if (!check_tsc_unstable()) {
e26101b1 1194 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1195 pr_debug("kvm: matched tsc offset for %llu\n", data);
1196 } else {
857e4099 1197 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1198 data += delta;
1199 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1200 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1201 }
b48aa97e 1202 matched = true;
e26101b1
ZA		 1203 } else {
1204 /*
1205 * We split periods of matched TSC writes into generations.
1206 * For each generation, we track the original measured
1207 * nanosecond time, offset, and write, so if TSCs are in
1208 * sync, we can match exact offset, and if not, we can match
4a969980 1209 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1210 *
1211 * These values are tracked in kvm->arch.cur_xxx variables.
1212 */
1213 kvm->arch.cur_tsc_generation++;
1214 kvm->arch.cur_tsc_nsec = ns;
1215 kvm->arch.cur_tsc_write = data;
1216 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1217 matched = false;
e26101b1
ZA		 1218 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1219 kvm->arch.cur_tsc_generation, data);
f38e098f 1220 }
e26101b1
ZA		 1221
1222 /*
1223 * We also track th most recent recorded KHZ, write and time to
1224 * allow the matching interval to be extended at each write.
1225 */
f38e098f
ZA		 1226 kvm->arch.last_tsc_nsec = ns;
1227 kvm->arch.last_tsc_write = data;
5d3cb0f6 1228 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a
ZA		 1229
1230 /* Reset of TSC must disable overshoot protection below */
1231 vcpu->arch.hv_clock.tsc_timestamp = 0;
b183aa58 1232 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1233
1234 /* Keep track of which generation this VCPU has synchronized to */
1235 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1236 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1237 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1238
ba904635
WA		 1239 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1240 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1241 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1242 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1243
1244 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1245 if (matched)
1246 kvm->arch.nr_vcpus_matched_tsc++;
1247 else
1248 kvm->arch.nr_vcpus_matched_tsc = 0;
1249
1250 kvm_track_tsc_matching(vcpu);
1251 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1252}
e26101b1 1253
99e3e30a
ZA		 1254EXPORT_SYMBOL_GPL(kvm_write_tsc);
1255
d828199e
MT		 1256#ifdef CONFIG_X86_64
1257
1258static cycle_t read_tsc(void)
1259{
1260 cycle_t ret;
1261 u64 last;
1262
1263 /*
1264 * Empirically, a fence (of type that depends on the CPU)
1265 * before rdtsc is enough to ensure that rdtsc is ordered
1266 * with respect to loads. The various CPU manuals are unclear
1267 * as to whether rdtsc can be reordered with later loads,
1268 * but no one has ever seen it happen.
1269 */
1270 rdtsc_barrier();
1271 ret = (cycle_t)vget_cycles();
1272
1273 last = pvclock_gtod_data.clock.cycle_last;
1274
1275 if (likely(ret >= last))
1276 return ret;
1277
1278 /*
1279 * GCC likes to generate cmov here, but this branch is extremely
1280 * predictable (it's just a funciton of time and the likely is
1281 * very likely) and there's a data dependence, so force GCC
1282 * to generate a branch instead. I don't barrier() because
1283 * we don't actually need a barrier, and if this function
1284 * ever gets inlined it will generate worse code.
1285 */
1286 asm volatile ("");
1287 return last;
1288}
1289
1290static inline u64 vgettsc(cycle_t *cycle_now)
1291{
1292 long v;
1293 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1294
1295 *cycle_now = read_tsc();
1296
1297 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1298 return v * gtod->clock.mult;
1299}
1300
1301static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1302{
1303 unsigned long seq;
1304 u64 ns;
1305 int mode;
1306 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1307
1308 ts->tv_nsec = 0;
1309 do {
1310 seq = read_seqcount_begin(&gtod->seq);
1311 mode = gtod->clock.vclock_mode;
1312 ts->tv_sec = gtod->monotonic_time_sec;
1313 ns = gtod->monotonic_time_snsec;
1314 ns += vgettsc(cycle_now);
1315 ns >>= gtod->clock.shift;
1316 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1317 timespec_add_ns(ts, ns);
1318
1319 return mode;
1320}
1321
1322/* returns true if host is using tsc clocksource */
1323static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1324{
1325 struct timespec ts;
1326
1327 /* checked again under seqlock below */
1328 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1329 return false;
1330
1331 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1332 return false;
1333
1334 monotonic_to_bootbased(&ts);
1335 *kernel_ns = timespec_to_ns(&ts);
1336
1337 return true;
1338}
1339#endif
1340
1341/*
1342 *
b48aa97e
MT		 1343 * Assuming a stable TSC across physical CPUS, and a stable TSC
1344 * across virtual CPUs, the following condition is possible.
1345 * Each numbered line represents an event visible to both
d828199e
MT		 1346 * CPUs at the next numbered event.
1347 *
1348 * "timespecX" represents host monotonic time. "tscX" represents
1349 * RDTSC value.
1350 *
1351 * VCPU0 on CPU0 | VCPU1 on CPU1
1352 *
1353 * 1. read timespec0,tsc0
1354 * 2. | timespec1 = timespec0 + N
1355 * | tsc1 = tsc0 + M
1356 * 3. transition to guest | transition to guest
1357 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1358 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1359 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1360 *
1361 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1362 *
1363 * - ret0 < ret1
1364 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1365 * ...
1366 * - 0 < N - M => M < N
1367 *
1368 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1369 * always the case (the difference between two distinct xtime instances
1370 * might be smaller then the difference between corresponding TSC reads,
1371 * when updating guest vcpus pvclock areas).
1372 *
1373 * To avoid that problem, do not allow visibility of distinct
1374 * system_timestamp/tsc_timestamp values simultaneously: use a master
1375 * copy of host monotonic time values. Update that master copy
1376 * in lockstep.
1377 *
b48aa97e 1378 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1379 *
1380 */
1381
1382static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1383{
1384#ifdef CONFIG_X86_64
1385 struct kvm_arch *ka = &kvm->arch;
1386 int vclock_mode;
b48aa97e
MT		 1387 bool host_tsc_clocksource, vcpus_matched;
1388
1389 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1390 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1391
1392 /*
1393 * If the host uses TSC clock, then passthrough TSC as stable
1394 * to the guest.
1395 */
b48aa97e 1396 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1397 &ka->master_kernel_ns,
1398 &ka->master_cycle_now);
1399
b48aa97e
MT		 1400 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1401
d828199e
MT		 1402 if (ka->use_master_clock)
1403 atomic_set(&kvm_guest_has_master_clock, 1);
1404
1405 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1406 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1407 vcpus_matched);
d828199e
MT		 1408#endif
1409}
1410
34c238a1 1411static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1412{
d828199e 1413 unsigned long flags, this_tsc_khz;
18068523 1414 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1415 struct kvm_arch *ka = &v->kvm->arch;
18068523 1416 void *shared_kaddr;
1d5f066e 1417 s64 kernel_ns, max_kernel_ns;
d828199e 1418 u64 tsc_timestamp, host_tsc;
78c0337a 1419 struct pvclock_vcpu_time_info *guest_hv_clock;
51d59c6b 1420 u8 pvclock_flags;
d828199e
MT		 1421 bool use_master_clock;
1422
1423 kernel_ns = 0;
1424 host_tsc = 0;
18068523 1425
18068523
GOC		 1426 /* Keep irq disabled to prevent changes to the clock */
1427 local_irq_save(flags);
cc578287 1428 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
8cfdc000 1429 if (unlikely(this_tsc_khz == 0)) {
c285545f 1430 local_irq_restore(flags);
34c238a1 1431 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
8cfdc000
ZA		 1432 return 1;
1433 }
18068523 1434
d828199e
MT		 1435 /*
1436 * If the host uses TSC clock, then passthrough TSC as stable
1437 * to the guest.
1438 */
1439 spin_lock(&ka->pvclock_gtod_sync_lock);
1440 use_master_clock = ka->use_master_clock;
1441 if (use_master_clock) {
1442 host_tsc = ka->master_cycle_now;
1443 kernel_ns = ka->master_kernel_ns;
1444 }
1445 spin_unlock(&ka->pvclock_gtod_sync_lock);
1446 if (!use_master_clock) {
1447 host_tsc = native_read_tsc();
1448 kernel_ns = get_kernel_ns();
1449 }
1450
1451 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1452
c285545f
ZA		 1453 /*
1454 * We may have to catch up the TSC to match elapsed wall clock
1455 * time for two reasons, even if kvmclock is used.
1456 * 1) CPU could have been running below the maximum TSC rate
1457 * 2) Broken TSC compensation resets the base at each VCPU
1458 * entry to avoid unknown leaps of TSC even when running
1459 * again on the same CPU. This may cause apparent elapsed
1460 * time to disappear, and the guest to stand still or run
1461 * very slowly.
1462 */
1463 if (vcpu->tsc_catchup) {
1464 u64 tsc = compute_guest_tsc(v, kernel_ns);
1465 if (tsc > tsc_timestamp) {
f1e2b260 1466 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1467 tsc_timestamp = tsc;
1468 }
50d0a0f9
GH		 1469 }
1470
18068523
GOC		 1471 local_irq_restore(flags);
1472
c285545f
ZA		 1473 if (!vcpu->time_page)
1474 return 0;
18068523 1475
1d5f066e
ZA		 1476 /*
1477 * Time as measured by the TSC may go backwards when resetting the base
1478 * tsc_timestamp. The reason for this is that the TSC resolution is
1479 * higher than the resolution of the other clock scales. Thus, many
1480 * possible measurments of the TSC correspond to one measurement of any
1481 * other clock, and so a spread of values is possible. This is not a
1482 * problem for the computation of the nanosecond clock; with TSC rates
1483 * around 1GHZ, there can only be a few cycles which correspond to one
1484 * nanosecond value, and any path through this code will inevitably
1485 * take longer than that. However, with the kernel_ns value itself,
1486 * the precision may be much lower, down to HZ granularity. If the
1487 * first sampling of TSC against kernel_ns ends in the low part of the
1488 * range, and the second in the high end of the range, we can get:
1489 *
1490 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1491 *
1492 * As the sampling errors potentially range in the thousands of cycles,
1493 * it is possible such a time value has already been observed by the
1494 * guest. To protect against this, we must compute the system time as
1495 * observed by the guest and ensure the new system time is greater.
1496 */
1497 max_kernel_ns = 0;
b183aa58 1498 if (vcpu->hv_clock.tsc_timestamp) {
1d5f066e
ZA		 1499 max_kernel_ns = vcpu->last_guest_tsc -
1500 vcpu->hv_clock.tsc_timestamp;
1501 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1502 vcpu->hv_clock.tsc_to_system_mul,
1503 vcpu->hv_clock.tsc_shift);
1504 max_kernel_ns += vcpu->last_kernel_ns;
1505 }
afbcf7ab 1506
e48672fa 1507 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1508 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1509 &vcpu->hv_clock.tsc_shift,
1510 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1511 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1512 }
1513
d828199e
MT		 1514 /* with a master <monotonic time, tsc value> tuple,
1515 * pvclock clock reads always increase at the (scaled) rate
1516 * of guest TSC - no need to deal with sampling errors.
1517 */
1518 if (!use_master_clock) {
1519 if (max_kernel_ns > kernel_ns)
1520 kernel_ns = max_kernel_ns;
1521 }
8cfdc000 1522 /* With all the info we got, fill in the values */
1d5f066e 1523 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1524 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1525 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1526 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1527
18068523
GOC		 1528 /*
1529 * The interface expects us to write an even number signaling that the
1530 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1531 * state, we just increase by 2 at the end.
18068523 1532 */
50d0a0f9 1533 vcpu->hv_clock.version += 2;
18068523 1534
8fd75e12 1535 shared_kaddr = kmap_atomic(vcpu->time_page);
18068523 1536
78c0337a
MT		 1537 guest_hv_clock = shared_kaddr + vcpu->time_offset;
1538
1539 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
1540 pvclock_flags = (guest_hv_clock->flags & PVCLOCK_GUEST_STOPPED);
1541
1542 if (vcpu->pvclock_set_guest_stopped_request) {
1543 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1544 vcpu->pvclock_set_guest_stopped_request = false;
1545 }
1546
d828199e
MT		 1547 /* If the host uses TSC clocksource, then it is stable */
1548 if (use_master_clock)
1549 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1550
78c0337a
MT		 1551 vcpu->hv_clock.flags = pvclock_flags;
1552
18068523 1553 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 1554 sizeof(vcpu->hv_clock));
18068523 1555
8fd75e12 1556 kunmap_atomic(shared_kaddr);
18068523
GOC		 1557
1558 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
8cfdc000 1559 return 0;
c8076604
GH		 1560}
1561
9ba075a6
AK		 1562static bool msr_mtrr_valid(unsigned msr)
1563{
1564 switch (msr) {
1565 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1566 case MSR_MTRRfix64K_00000:
1567 case MSR_MTRRfix16K_80000:
1568 case MSR_MTRRfix16K_A0000:
1569 case MSR_MTRRfix4K_C0000:
1570 case MSR_MTRRfix4K_C8000:
1571 case MSR_MTRRfix4K_D0000:
1572 case MSR_MTRRfix4K_D8000:
1573 case MSR_MTRRfix4K_E0000:
1574 case MSR_MTRRfix4K_E8000:
1575 case MSR_MTRRfix4K_F0000:
1576 case MSR_MTRRfix4K_F8000:
1577 case MSR_MTRRdefType:
1578 case MSR_IA32_CR_PAT:
1579 return true;
1580 case 0x2f8:
1581 return true;
1582 }
1583 return false;
1584}
1585
d6289b93
MT		 1586static bool valid_pat_type(unsigned t)
1587{
1588 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1589}
1590
1591static bool valid_mtrr_type(unsigned t)
1592{
1593 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1594}
1595
1596static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1597{
1598 int i;
1599
1600 if (!msr_mtrr_valid(msr))
1601 return false;
1602
1603 if (msr == MSR_IA32_CR_PAT) {
1604 for (i = 0; i < 8; i++)
1605 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1606 return false;
1607 return true;
1608 } else if (msr == MSR_MTRRdefType) {
1609 if (data & ~0xcff)
1610 return false;
1611 return valid_mtrr_type(data & 0xff);
1612 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1613 for (i = 0; i < 8 ; i++)
1614 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1615 return false;
1616 return true;
1617 }
1618
1619 /* variable MTRRs */
1620 return valid_mtrr_type(data & 0xff);
1621}
1622
9ba075a6
AK		 1623static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1624{
0bed3b56
SY		 1625 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1626
d6289b93 1627 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1628 return 1;
1629
0bed3b56
SY		 1630 if (msr == MSR_MTRRdefType) {
1631 vcpu->arch.mtrr_state.def_type = data;
1632 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1633 } else if (msr == MSR_MTRRfix64K_00000)
1634 p[0] = data;
1635 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1636 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1637 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1638 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1639 else if (msr == MSR_IA32_CR_PAT)
1640 vcpu->arch.pat = data;
1641 else { /* Variable MTRRs */
1642 int idx, is_mtrr_mask;
1643 u64 *pt;
1644
1645 idx = (msr - 0x200) / 2;
1646 is_mtrr_mask = msr - 0x200 - 2 * idx;
1647 if (!is_mtrr_mask)
1648 pt =
1649 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1650 else
1651 pt =
1652 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1653 *pt = data;
1654 }
1655
1656 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1657 return 0;
1658}
15c4a640 1659
890ca9ae 1660static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1661{
890ca9ae
HY		 1662 u64 mcg_cap = vcpu->arch.mcg_cap;
1663 unsigned bank_num = mcg_cap & 0xff;
1664
15c4a640 1665 switch (msr) {
15c4a640 1666 case MSR_IA32_MCG_STATUS:
890ca9ae 1667 vcpu->arch.mcg_status = data;
15c4a640 1668 break;
c7ac679c 1669 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1670 if (!(mcg_cap & MCG_CTL_P))
1671 return 1;
1672 if (data != 0 && data != ~(u64)0)
1673 return -1;
1674 vcpu->arch.mcg_ctl = data;
1675 break;
1676 default:
1677 if (msr >= MSR_IA32_MC0_CTL &&
1678 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1679 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1680 /* only 0 or all 1s can be written to IA32_MCi_CTL
1681 * some Linux kernels though clear bit 10 in bank 4 to
1682 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1683 * this to avoid an uncatched #GP in the guest
1684 */
890ca9ae 1685 if ((offset & 0x3) == 0 &&
114be429 1686 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1687 return -1;
1688 vcpu->arch.mce_banks[offset] = data;
1689 break;
1690 }
1691 return 1;
1692 }
1693 return 0;
1694}
1695
ffde22ac
ES		 1696static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1697{
1698 struct kvm *kvm = vcpu->kvm;
1699 int lm = is_long_mode(vcpu);
1700 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1701 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1702 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1703 : kvm->arch.xen_hvm_config.blob_size_32;
1704 u32 page_num = data & ~PAGE_MASK;
1705 u64 page_addr = data & PAGE_MASK;
1706 u8 *page;
1707 int r;
1708
1709 r = -E2BIG;
1710 if (page_num >= blob_size)
1711 goto out;
1712 r = -ENOMEM;
ff5c2c03
SL		 1713 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1714 if (IS_ERR(page)) {
1715 r = PTR_ERR(page);
ffde22ac 1716 goto out;
ff5c2c03 1717 }
ffde22ac
ES		 1718 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1719 goto out_free;
1720 r = 0;
1721out_free:
1722 kfree(page);
1723out:
1724 return r;
1725}
1726
55cd8e5a
GN		 1727static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1728{
1729 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1730}
1731
1732static bool kvm_hv_msr_partition_wide(u32 msr)
1733{
1734 bool r = false;
1735 switch (msr) {
1736 case HV_X64_MSR_GUEST_OS_ID:
1737 case HV_X64_MSR_HYPERCALL:
1738 r = true;
1739 break;
1740 }
1741
1742 return r;
1743}
1744
1745static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1746{
1747 struct kvm *kvm = vcpu->kvm;
1748
1749 switch (msr) {
1750 case HV_X64_MSR_GUEST_OS_ID:
1751 kvm->arch.hv_guest_os_id = data;
1752 /* setting guest os id to zero disables hypercall page */
1753 if (!kvm->arch.hv_guest_os_id)
1754 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1755 break;
1756 case HV_X64_MSR_HYPERCALL: {
1757 u64 gfn;
1758 unsigned long addr;
1759 u8 instructions[4];
1760
1761 /* if guest os id is not set hypercall should remain disabled */
1762 if (!kvm->arch.hv_guest_os_id)
1763 break;
1764 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1765 kvm->arch.hv_hypercall = data;
1766 break;
1767 }
1768 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1769 addr = gfn_to_hva(kvm, gfn);
1770 if (kvm_is_error_hva(addr))
1771 return 1;
1772 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1773 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1774 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1775 return 1;
1776 kvm->arch.hv_hypercall = data;
1777 break;
1778 }
1779 default:
a737f256
CD		 1780 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1781 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1782 return 1;
1783 }
1784 return 0;
1785}
1786
1787static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1788{
10388a07
GN		 1789 switch (msr) {
1790 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1791 unsigned long addr;
55cd8e5a 1792
10388a07
GN		 1793 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1794 vcpu->arch.hv_vapic = data;
1795 break;
1796 }
1797 addr = gfn_to_hva(vcpu->kvm, data >>
1798 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1799 if (kvm_is_error_hva(addr))
1800 return 1;
8b0cedff 1801 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1802 return 1;
1803 vcpu->arch.hv_vapic = data;
1804 break;
1805 }
1806 case HV_X64_MSR_EOI:
1807 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1808 case HV_X64_MSR_ICR:
1809 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1810 case HV_X64_MSR_TPR:
1811 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1812 default:
a737f256
CD		 1813 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1814 "data 0x%llx\n", msr, data);
10388a07
GN		 1815 return 1;
1816 }
1817
1818 return 0;
55cd8e5a
GN		 1819}
1820
344d9588
GN		 1821static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1822{
1823 gpa_t gpa = data & ~0x3f;
1824
4a969980 1825 /* Bits 2:5 are reserved, Should be zero */
6adba527 1826 if (data & 0x3c)
344d9588
GN		 1827 return 1;
1828
1829 vcpu->arch.apf.msr_val = data;
1830
1831 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1832 kvm_clear_async_pf_completion_queue(vcpu);
1833 kvm_async_pf_hash_reset(vcpu);
1834 return 0;
1835 }
1836
1837 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa))
1838 return 1;
1839
6adba527 1840 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1841 kvm_async_pf_wakeup_all(vcpu);
1842 return 0;
1843}
1844
12f9a48f
GC		 1845static void kvmclock_reset(struct kvm_vcpu *vcpu)
1846{
1847 if (vcpu->arch.time_page) {
1848 kvm_release_page_dirty(vcpu->arch.time_page);
1849 vcpu->arch.time_page = NULL;
1850 }
1851}
1852
c9aaa895
GC		 1853static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1854{
1855 u64 delta;
1856
1857 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1858 return;
1859
1860 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1861 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1862 vcpu->arch.st.accum_steal = delta;
1863}
1864
1865static void record_steal_time(struct kvm_vcpu *vcpu)
1866{
1867 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1868 return;
1869
1870 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1871 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1872 return;
1873
1874 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1875 vcpu->arch.st.steal.version += 2;
1876 vcpu->arch.st.accum_steal = 0;
1877
1878 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1879 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1880}
1881
8fe8ab46 1882int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 1883{
5753785f 1884 bool pr = false;
8fe8ab46
WA		 1885 u32 msr = msr_info->index;
1886 u64 data = msr_info->data;
5753785f 1887
15c4a640 1888 switch (msr) {
2e32b719
BP		 1889 case MSR_AMD64_NB_CFG:
1890 case MSR_IA32_UCODE_REV:
1891 case MSR_IA32_UCODE_WRITE:
1892 case MSR_VM_HSAVE_PA:
1893 case MSR_AMD64_PATCH_LOADER:
1894 case MSR_AMD64_BU_CFG2:
1895 break;
1896
15c4a640 1897 case MSR_EFER:
b69e8cae 1898 return set_efer(vcpu, data);
8f1589d9
AP		 1899 case MSR_K7_HWCR:
1900 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1901 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1902 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 1903 if (data != 0) {
a737f256
CD		 1904 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1905 data);
8f1589d9
AP		 1906 return 1;
1907 }
15c4a640 1908 break;
f7c6d140
AP		 1909 case MSR_FAM10H_MMIO_CONF_BASE:
1910 if (data != 0) {
a737f256
CD		 1911 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1912 "0x%llx\n", data);
f7c6d140
AP		 1913 return 1;
1914 }
15c4a640 1915 break;
b5e2fec0
AG		 1916 case MSR_IA32_DEBUGCTLMSR:
1917 if (!data) {
1918 /* We support the non-activated case already */
1919 break;
1920 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
1921 /* Values other than LBR and BTF are vendor-specific,
1922 thus reserved and should throw a #GP */
1923 return 1;
1924 }
a737f256
CD		 1925 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
1926 __func__, data);
b5e2fec0 1927 break;
9ba075a6
AK		 1928 case 0x200 ... 0x2ff:
1929 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 1930 case MSR_IA32_APICBASE:
1931 kvm_set_apic_base(vcpu, data);
1932 break;
0105d1a5
GN		 1933 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
1934 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 1935 case MSR_IA32_TSCDEADLINE:
1936 kvm_set_lapic_tscdeadline_msr(vcpu, data);
1937 break;
ba904635
WA		 1938 case MSR_IA32_TSC_ADJUST:
1939 if (guest_cpuid_has_tsc_adjust(vcpu)) {
1940 if (!msr_info->host_initiated) {
1941 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
1942 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
1943 }
1944 vcpu->arch.ia32_tsc_adjust_msr = data;
1945 }
1946 break;
15c4a640 1947 case MSR_IA32_MISC_ENABLE:
ad312c7c 1948 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 1949 break;
11c6bffa 1950 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 1951 case MSR_KVM_WALL_CLOCK:
1952 vcpu->kvm->arch.wall_clock = data;
1953 kvm_write_wall_clock(vcpu->kvm, data);
1954 break;
11c6bffa 1955 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 1956 case MSR_KVM_SYSTEM_TIME: {
12f9a48f 1957 kvmclock_reset(vcpu);
18068523
GOC		 1958
1959 vcpu->arch.time = data;
c285545f 1960 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
18068523
GOC		 1961
1962 /* we verify if the enable bit is set... */
1963 if (!(data & 1))
1964 break;
1965
1966 /* ...but clean it before doing the actual write */
1967 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
1968
18068523
GOC		 1969 vcpu->arch.time_page =
1970 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523 1971
32cad84f 1972 if (is_error_page(vcpu->arch.time_page))
18068523 1973 vcpu->arch.time_page = NULL;
32cad84f 1974
18068523
GOC		 1975 break;
1976 }
344d9588
GN		 1977 case MSR_KVM_ASYNC_PF_EN:
1978 if (kvm_pv_enable_async_pf(vcpu, data))
1979 return 1;
1980 break;
c9aaa895
GC		 1981 case MSR_KVM_STEAL_TIME:
1982
1983 if (unlikely(!sched_info_on()))
1984 return 1;
1985
1986 if (data & KVM_STEAL_RESERVED_MASK)
1987 return 1;
1988
1989 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
1990 data & KVM_STEAL_VALID_BITS))
1991 return 1;
1992
1993 vcpu->arch.st.msr_val = data;
1994
1995 if (!(data & KVM_MSR_ENABLED))
1996 break;
1997
1998 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1999
2000 preempt_disable();
2001 accumulate_steal_time(vcpu);
2002 preempt_enable();
2003
2004 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2005
2006 break;
ae7a2a3f
MT		 2007 case MSR_KVM_PV_EOI_EN:
2008 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2009 return 1;
2010 break;
c9aaa895 2011
890ca9ae
HY		 2012 case MSR_IA32_MCG_CTL:
2013 case MSR_IA32_MCG_STATUS:
2014 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2015 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2016
2017 /* Performance counters are not protected by a CPUID bit,
2018 * so we should check all of them in the generic path for the sake of
2019 * cross vendor migration.
2020 * Writing a zero into the event select MSRs disables them,
2021 * which we perfectly emulate ;-). Any other value should be at least
2022 * reported, some guests depend on them.
2023 */
71db6023
AP		 2024 case MSR_K7_EVNTSEL0:
2025 case MSR_K7_EVNTSEL1:
2026 case MSR_K7_EVNTSEL2:
2027 case MSR_K7_EVNTSEL3:
2028 if (data != 0)
a737f256
CD		 2029 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2030 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2031 break;
2032 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2033 * so we ignore writes to make it happy.
2034 */
71db6023
AP		 2035 case MSR_K7_PERFCTR0:
2036 case MSR_K7_PERFCTR1:
2037 case MSR_K7_PERFCTR2:
2038 case MSR_K7_PERFCTR3:
a737f256
CD		 2039 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2040 "0x%x data 0x%llx\n", msr, data);
71db6023 2041 break;
5753785f
GN		 2042 case MSR_P6_PERFCTR0:
2043 case MSR_P6_PERFCTR1:
2044 pr = true;
2045 case MSR_P6_EVNTSEL0:
2046 case MSR_P6_EVNTSEL1:
2047 if (kvm_pmu_msr(vcpu, msr))
2048 return kvm_pmu_set_msr(vcpu, msr, data);
2049
2050 if (pr || data != 0)
a737f256
CD		 2051 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2052 "0x%x data 0x%llx\n", msr, data);
5753785f 2053 break;
84e0cefa
JS		 2054 case MSR_K7_CLK_CTL:
2055 /*
2056 * Ignore all writes to this no longer documented MSR.
2057 * Writes are only relevant for old K7 processors,
2058 * all pre-dating SVM, but a recommended workaround from
4a969980 2059 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2060 * affected processor models on the command line, hence
2061 * the need to ignore the workaround.
2062 */
2063 break;
55cd8e5a
GN		 2064 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2065 if (kvm_hv_msr_partition_wide(msr)) {
2066 int r;
2067 mutex_lock(&vcpu->kvm->lock);
2068 r = set_msr_hyperv_pw(vcpu, msr, data);
2069 mutex_unlock(&vcpu->kvm->lock);
2070 return r;
2071 } else
2072 return set_msr_hyperv(vcpu, msr, data);
2073 break;
91c9c3ed 2074 case MSR_IA32_BBL_CR_CTL3:
2075 /* Drop writes to this legacy MSR -- see rdmsr
2076 * counterpart for further detail.
2077 */
a737f256 2078 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2079 break;
2b036c6b
BO		 2080 case MSR_AMD64_OSVW_ID_LENGTH:
2081 if (!guest_cpuid_has_osvw(vcpu))
2082 return 1;
2083 vcpu->arch.osvw.length = data;
2084 break;
2085 case MSR_AMD64_OSVW_STATUS:
2086 if (!guest_cpuid_has_osvw(vcpu))
2087 return 1;
2088 vcpu->arch.osvw.status = data;
2089 break;
15c4a640 2090 default:
ffde22ac
ES		 2091 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2092 return xen_hvm_config(vcpu, data);
f5132b01
GN		 2093 if (kvm_pmu_msr(vcpu, msr))
2094 return kvm_pmu_set_msr(vcpu, msr, data);
ed85c068 2095 if (!ignore_msrs) {
a737f256
CD		 2096 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2097 msr, data);
ed85c068
AP		 2098 return 1;
2099 } else {
a737f256
CD		 2100 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2101 msr, data);
ed85c068
AP		 2102 break;
2103 }
15c4a640
CO		 2104 }
2105 return 0;
2106}
2107EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2108
2109
2110/*
2111 * Reads an msr value (of 'msr_index') into 'pdata'.
2112 * Returns 0 on success, non-0 otherwise.
2113 * Assumes vcpu_load() was already called.
2114 */
2115int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2116{
2117 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2118}
2119
9ba075a6
AK		 2120static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2121{
0bed3b56
SY		 2122 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2123
9ba075a6
AK		 2124 if (!msr_mtrr_valid(msr))
2125 return 1;
2126
0bed3b56
SY		 2127 if (msr == MSR_MTRRdefType)
2128 *pdata = vcpu->arch.mtrr_state.def_type +
2129 (vcpu->arch.mtrr_state.enabled << 10);
2130 else if (msr == MSR_MTRRfix64K_00000)
2131 *pdata = p[0];
2132 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2133 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2134 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2135 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2136 else if (msr == MSR_IA32_CR_PAT)
2137 *pdata = vcpu->arch.pat;
2138 else { /* Variable MTRRs */
2139 int idx, is_mtrr_mask;
2140 u64 *pt;
2141
2142 idx = (msr - 0x200) / 2;
2143 is_mtrr_mask = msr - 0x200 - 2 * idx;
2144 if (!is_mtrr_mask)
2145 pt =
2146 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2147 else
2148 pt =
2149 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2150 *pdata = *pt;
2151 }
2152
9ba075a6
AK		 2153 return 0;
2154}
2155
890ca9ae 2156static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2157{
2158 u64 data;
890ca9ae
HY		 2159 u64 mcg_cap = vcpu->arch.mcg_cap;
2160 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2161
2162 switch (msr) {
15c4a640
CO		 2163 case MSR_IA32_P5_MC_ADDR:
2164 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2165 data = 0;
2166 break;
15c4a640 2167 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2168 data = vcpu->arch.mcg_cap;
2169 break;
c7ac679c 2170 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2171 if (!(mcg_cap & MCG_CTL_P))
2172 return 1;
2173 data = vcpu->arch.mcg_ctl;
2174 break;
2175 case MSR_IA32_MCG_STATUS:
2176 data = vcpu->arch.mcg_status;
2177 break;
2178 default:
2179 if (msr >= MSR_IA32_MC0_CTL &&
2180 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2181 u32 offset = msr - MSR_IA32_MC0_CTL;
2182 data = vcpu->arch.mce_banks[offset];
2183 break;
2184 }
2185 return 1;
2186 }
2187 *pdata = data;
2188 return 0;
2189}
2190
55cd8e5a
GN		 2191static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2192{
2193 u64 data = 0;
2194 struct kvm *kvm = vcpu->kvm;
2195
2196 switch (msr) {
2197 case HV_X64_MSR_GUEST_OS_ID:
2198 data = kvm->arch.hv_guest_os_id;
2199 break;
2200 case HV_X64_MSR_HYPERCALL:
2201 data = kvm->arch.hv_hypercall;
2202 break;
2203 default:
a737f256 2204 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2205 return 1;
2206 }
2207
2208 *pdata = data;
2209 return 0;
2210}
2211
2212static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2213{
2214 u64 data = 0;
2215
2216 switch (msr) {
2217 case HV_X64_MSR_VP_INDEX: {
2218 int r;
2219 struct kvm_vcpu *v;
2220 kvm_for_each_vcpu(r, v, vcpu->kvm)
2221 if (v == vcpu)
2222 data = r;
2223 break;
2224 }
10388a07
GN		 2225 case HV_X64_MSR_EOI:
2226 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2227 case HV_X64_MSR_ICR:
2228 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2229 case HV_X64_MSR_TPR:
2230 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2231 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2232 data = vcpu->arch.hv_vapic;
2233 break;
55cd8e5a 2234 default:
a737f256 2235 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2236 return 1;
2237 }
2238 *pdata = data;
2239 return 0;
2240}
2241
890ca9ae
HY		 2242int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2243{
2244 u64 data;
2245
2246 switch (msr) {
890ca9ae 2247 case MSR_IA32_PLATFORM_ID:
15c4a640 2248 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2249 case MSR_IA32_DEBUGCTLMSR:
2250 case MSR_IA32_LASTBRANCHFROMIP:
2251 case MSR_IA32_LASTBRANCHTOIP:
2252 case MSR_IA32_LASTINTFROMIP:
2253 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2254 case MSR_K8_SYSCFG:
2255 case MSR_K7_HWCR:
61a6bd67 2256 case MSR_VM_HSAVE_PA:
9e699624 2257 case MSR_K7_EVNTSEL0:
1f3ee616 2258 case MSR_K7_PERFCTR0:
1fdbd48c 2259 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2260 case MSR_AMD64_NB_CFG:
f7c6d140 2261 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2262 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2263 data = 0;
2264 break;
5753785f
GN		 2265 case MSR_P6_PERFCTR0:
2266 case MSR_P6_PERFCTR1:
2267 case MSR_P6_EVNTSEL0:
2268 case MSR_P6_EVNTSEL1:
2269 if (kvm_pmu_msr(vcpu, msr))
2270 return kvm_pmu_get_msr(vcpu, msr, pdata);
2271 data = 0;
2272 break;
742bc670
MT		 2273 case MSR_IA32_UCODE_REV:
2274 data = 0x100000000ULL;
2275 break;
9ba075a6
AK		 2276 case MSR_MTRRcap:
2277 data = 0x500 | KVM_NR_VAR_MTRR;
2278 break;
2279 case 0x200 ... 0x2ff:
2280 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2281 case 0xcd: /* fsb frequency */
2282 data = 3;
2283 break;
7b914098
JS		 2284 /*
2285 * MSR_EBC_FREQUENCY_ID
2286 * Conservative value valid for even the basic CPU models.
2287 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2288 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2289 * and 266MHz for model 3, or 4. Set Core Clock
2290 * Frequency to System Bus Frequency Ratio to 1 (bits
2291 * 31:24) even though these are only valid for CPU
2292 * models > 2, however guests may end up dividing or
2293 * multiplying by zero otherwise.
2294 */
2295 case MSR_EBC_FREQUENCY_ID:
2296 data = 1 << 24;
2297 break;
15c4a640
CO		 2298 case MSR_IA32_APICBASE:
2299 data = kvm_get_apic_base(vcpu);
2300 break;
0105d1a5
GN		 2301 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2302 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2303 break;
a3e06bbe
LJ		 2304 case MSR_IA32_TSCDEADLINE:
2305 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2306 break;
ba904635
WA		 2307 case MSR_IA32_TSC_ADJUST:
2308 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2309 break;
15c4a640 2310 case MSR_IA32_MISC_ENABLE:
ad312c7c 2311 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2312 break;
847f0ad8
AG		 2313 case MSR_IA32_PERF_STATUS:
2314 /* TSC increment by tick */
2315 data = 1000ULL;
2316 /* CPU multiplier */
2317 data |= (((uint64_t)4ULL) << 40);
2318 break;
15c4a640 2319 case MSR_EFER:
f6801dff 2320 data = vcpu->arch.efer;
15c4a640 2321 break;
18068523 2322 case MSR_KVM_WALL_CLOCK:
11c6bffa 2323 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2324 data = vcpu->kvm->arch.wall_clock;
2325 break;
2326 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2327 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2328 data = vcpu->arch.time;
2329 break;
344d9588
GN		 2330 case MSR_KVM_ASYNC_PF_EN:
2331 data = vcpu->arch.apf.msr_val;
2332 break;
c9aaa895
GC		 2333 case MSR_KVM_STEAL_TIME:
2334 data = vcpu->arch.st.msr_val;
2335 break;
1d92128f
MT		 2336 case MSR_KVM_PV_EOI_EN:
2337 data = vcpu->arch.pv_eoi.msr_val;
2338 break;
890ca9ae
HY		 2339 case MSR_IA32_P5_MC_ADDR:
2340 case MSR_IA32_P5_MC_TYPE:
2341 case MSR_IA32_MCG_CAP:
2342 case MSR_IA32_MCG_CTL:
2343 case MSR_IA32_MCG_STATUS:
2344 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2345 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2346 case MSR_K7_CLK_CTL:
2347 /*
2348 * Provide expected ramp-up count for K7. All other
2349 * are set to zero, indicating minimum divisors for
2350 * every field.
2351 *
2352 * This prevents guest kernels on AMD host with CPU
2353 * type 6, model 8 and higher from exploding due to
2354 * the rdmsr failing.
2355 */
2356 data = 0x20000000;
2357 break;
55cd8e5a
GN		 2358 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2359 if (kvm_hv_msr_partition_wide(msr)) {
2360 int r;
2361 mutex_lock(&vcpu->kvm->lock);
2362 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2363 mutex_unlock(&vcpu->kvm->lock);
2364 return r;
2365 } else
2366 return get_msr_hyperv(vcpu, msr, pdata);
2367 break;
91c9c3ed 2368 case MSR_IA32_BBL_CR_CTL3:
2369 /* This legacy MSR exists but isn't fully documented in current
2370 * silicon. It is however accessed by winxp in very narrow
2371 * scenarios where it sets bit #19, itself documented as
2372 * a "reserved" bit. Best effort attempt to source coherent
2373 * read data here should the balance of the register be
2374 * interpreted by the guest:
2375 *
2376 * L2 cache control register 3: 64GB range, 256KB size,
2377 * enabled, latency 0x1, configured
2378 */
2379 data = 0xbe702111;
2380 break;
2b036c6b
BO		 2381 case MSR_AMD64_OSVW_ID_LENGTH:
2382 if (!guest_cpuid_has_osvw(vcpu))
2383 return 1;
2384 data = vcpu->arch.osvw.length;
2385 break;
2386 case MSR_AMD64_OSVW_STATUS:
2387 if (!guest_cpuid_has_osvw(vcpu))
2388 return 1;
2389 data = vcpu->arch.osvw.status;
2390 break;
15c4a640 2391 default:
f5132b01
GN		 2392 if (kvm_pmu_msr(vcpu, msr))
2393 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2394 if (!ignore_msrs) {
a737f256 2395 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2396 return 1;
2397 } else {
a737f256 2398 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2399 data = 0;
2400 }
2401 break;
15c4a640
CO		 2402 }
2403 *pdata = data;
2404 return 0;
2405}
2406EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2407
313a3dc7
CO		 2408/*
2409 * Read or write a bunch of msrs. All parameters are kernel addresses.
2410 *
2411 * @return number of msrs set successfully.
2412 */
2413static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2414 struct kvm_msr_entry *entries,
2415 int (*do_msr)(struct kvm_vcpu *vcpu,
2416 unsigned index, u64 *data))
2417{
f656ce01 2418 int i, idx;
313a3dc7 2419
f656ce01 2420 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2421 for (i = 0; i < msrs->nmsrs; ++i)
2422 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2423 break;
f656ce01 2424 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2425
313a3dc7
CO		 2426 return i;
2427}
2428
2429/*
2430 * Read or write a bunch of msrs. Parameters are user addresses.
2431 *
2432 * @return number of msrs set successfully.
2433 */
2434static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2435 int (*do_msr)(struct kvm_vcpu *vcpu,
2436 unsigned index, u64 *data),
2437 int writeback)
2438{
2439 struct kvm_msrs msrs;
2440 struct kvm_msr_entry *entries;
2441 int r, n;
2442 unsigned size;
2443
2444 r = -EFAULT;
2445 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2446 goto out;
2447
2448 r = -E2BIG;
2449 if (msrs.nmsrs >= MAX_IO_MSRS)
2450 goto out;
2451
313a3dc7 2452 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2453 entries = memdup_user(user_msrs->entries, size);
2454 if (IS_ERR(entries)) {
2455 r = PTR_ERR(entries);
313a3dc7 2456 goto out;
ff5c2c03 2457 }
313a3dc7
CO		 2458
2459 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2460 if (r < 0)
2461 goto out_free;
2462
2463 r = -EFAULT;
2464 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2465 goto out_free;
2466
2467 r = n;
2468
2469out_free:
7a73c028 2470 kfree(entries);
313a3dc7
CO		 2471out:
2472 return r;
2473}
2474
018d00d2
ZX		 2475int kvm_dev_ioctl_check_extension(long ext)
2476{
2477 int r;
2478
2479 switch (ext) {
2480 case KVM_CAP_IRQCHIP:
2481 case KVM_CAP_HLT:
2482 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2483 case KVM_CAP_SET_TSS_ADDR:
07716717 2484 case KVM_CAP_EXT_CPUID:
c8076604 2485 case KVM_CAP_CLOCKSOURCE:
7837699f 2486 case KVM_CAP_PIT:
a28e4f5a 2487 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2488 case KVM_CAP_MP_STATE:
ed848624 2489 case KVM_CAP_SYNC_MMU:
a355c85c 2490 case KVM_CAP_USER_NMI:
52d939a0 2491 case KVM_CAP_REINJECT_CONTROL:
4925663a 2492 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 2493 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 2494 case KVM_CAP_IRQFD:
d34e6b17 2495 case KVM_CAP_IOEVENTFD:
c5ff41ce 2496 case KVM_CAP_PIT2:
e9f42757 2497 case KVM_CAP_PIT_STATE2:
b927a3ce 2498 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2499 case KVM_CAP_XEN_HVM:
afbcf7ab 2500 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2501 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2502 case KVM_CAP_HYPERV:
10388a07 2503 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2504 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2505 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2506 case KVM_CAP_DEBUGREGS:
d2be1651 2507 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2508 case KVM_CAP_XSAVE:
344d9588 2509 case KVM_CAP_ASYNC_PF:
92a1f12d 2510 case KVM_CAP_GET_TSC_KHZ:
07700a94 2511 case KVM_CAP_PCI_2_3:
1c0b28c2 2512 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2513 case KVM_CAP_READONLY_MEM:
7a84428a 2514 case KVM_CAP_IRQFD_RESAMPLE:
018d00d2
ZX		 2515 r = 1;
2516 break;
542472b5
LV		 2517 case KVM_CAP_COALESCED_MMIO:
2518 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2519 break;
774ead3a
AK		 2520 case KVM_CAP_VAPIC:
2521 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2522 break;
f725230a 2523 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2524 r = KVM_SOFT_MAX_VCPUS;
2525 break;
2526 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2527 r = KVM_MAX_VCPUS;
2528 break;
a988b910 2529 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2530 r = KVM_USER_MEM_SLOTS;
a988b910 2531 break;
a68a6a72
MT		 2532 case KVM_CAP_PV_MMU: /* obsolete */
2533 r = 0;
2f333bcb 2534 break;
62c476c7 2535 case KVM_CAP_IOMMU:
a1b60c1c 2536 r = iommu_present(&pci_bus_type);
62c476c7 2537 break;
890ca9ae
HY		 2538 case KVM_CAP_MCE:
2539 r = KVM_MAX_MCE_BANKS;
2540 break;
2d5b5a66
SY		 2541 case KVM_CAP_XCRS:
2542 r = cpu_has_xsave;
2543 break;
92a1f12d
JR		 2544 case KVM_CAP_TSC_CONTROL:
2545 r = kvm_has_tsc_control;
2546 break;
4d25a066
JK		 2547 case KVM_CAP_TSC_DEADLINE_TIMER:
2548 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2549 break;
018d00d2
ZX		 2550 default:
2551 r = 0;
2552 break;
2553 }
2554 return r;
2555
2556}
2557
043405e1
CO		 2558long kvm_arch_dev_ioctl(struct file *filp,
2559 unsigned int ioctl, unsigned long arg)
2560{
2561 void __user *argp = (void __user *)arg;
2562 long r;
2563
2564 switch (ioctl) {
2565 case KVM_GET_MSR_INDEX_LIST: {
2566 struct kvm_msr_list __user *user_msr_list = argp;
2567 struct kvm_msr_list msr_list;
2568 unsigned n;
2569
2570 r = -EFAULT;
2571 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2572 goto out;
2573 n = msr_list.nmsrs;
2574 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2575 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2576 goto out;
2577 r = -E2BIG;
e125e7b6 2578 if (n < msr_list.nmsrs)
043405e1
CO		 2579 goto out;
2580 r = -EFAULT;
2581 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2582 num_msrs_to_save * sizeof(u32)))
2583 goto out;
e125e7b6 2584 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2585 &emulated_msrs,
2586 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2587 goto out;
2588 r = 0;
2589 break;
2590 }
674eea0f
AK		 2591 case KVM_GET_SUPPORTED_CPUID: {
2592 struct kvm_cpuid2 __user *cpuid_arg = argp;
2593 struct kvm_cpuid2 cpuid;
2594
2595 r = -EFAULT;
2596 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2597 goto out;
2598 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2599 cpuid_arg->entries);
674eea0f
AK		 2600 if (r)
2601 goto out;
2602
2603 r = -EFAULT;
2604 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2605 goto out;
2606 r = 0;
2607 break;
2608 }
890ca9ae
HY		 2609 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2610 u64 mce_cap;
2611
2612 mce_cap = KVM_MCE_CAP_SUPPORTED;
2613 r = -EFAULT;
2614 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2615 goto out;
2616 r = 0;
2617 break;
2618 }
043405e1
CO		 2619 default:
2620 r = -EINVAL;
2621 }
2622out:
2623 return r;
2624}
2625
f5f48ee1
SY		 2626static void wbinvd_ipi(void *garbage)
2627{
2628 wbinvd();
2629}
2630
2631static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2632{
2633 return vcpu->kvm->arch.iommu_domain &&
2634 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2635}
2636
313a3dc7
CO		 2637void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2638{
f5f48ee1
SY		 2639 /* Address WBINVD may be executed by guest */
2640 if (need_emulate_wbinvd(vcpu)) {
2641 if (kvm_x86_ops->has_wbinvd_exit())
2642 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2643 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2644 smp_call_function_single(vcpu->cpu,
2645 wbinvd_ipi, NULL, 1);
2646 }
2647
313a3dc7 2648 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2649
0dd6a6ed
ZA		 2650 /* Apply any externally detected TSC adjustments (due to suspend) */
2651 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2652 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2653 vcpu->arch.tsc_offset_adjustment = 0;
2654 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2655 }
8f6055cb 2656
48434c20 2657 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2658 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2659 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2660 if (tsc_delta < 0)
2661 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2662 if (check_tsc_unstable()) {
b183aa58
ZA		 2663 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2664 vcpu->arch.last_guest_tsc);
2665 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2666 vcpu->arch.tsc_catchup = 1;
c285545f 2667 }
d98d07ca
MT		 2668 /*
2669 * On a host with synchronized TSC, there is no need to update
2670 * kvmclock on vcpu->cpu migration
2671 */
2672 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
2673 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2674 if (vcpu->cpu != cpu)
2675 kvm_migrate_timers(vcpu);
e48672fa 2676 vcpu->cpu = cpu;
6b7d7e76 2677 }
c9aaa895
GC		 2678
2679 accumulate_steal_time(vcpu);
2680 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2681}
2682
2683void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2684{
02daab21 2685 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2686 kvm_put_guest_fpu(vcpu);
6f526ec5 2687 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2688}
2689
313a3dc7
CO		 2690static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2691 struct kvm_lapic_state *s)
2692{
ad312c7c 2693 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2694
2695 return 0;
2696}
2697
2698static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2699 struct kvm_lapic_state *s)
2700{
64eb0620 2701 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2702 update_cr8_intercept(vcpu);
313a3dc7
CO		 2703
2704 return 0;
2705}
2706
f77bc6a4
ZX		 2707static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2708 struct kvm_interrupt *irq)
2709{
02cdb50f 2710 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2711 return -EINVAL;
2712 if (irqchip_in_kernel(vcpu->kvm))
2713 return -ENXIO;
f77bc6a4 2714
66fd3f7f 2715 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2716 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2717
f77bc6a4
ZX		 2718 return 0;
2719}
2720
c4abb7c9
JK		 2721static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2722{
c4abb7c9 2723 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2724
2725 return 0;
2726}
2727
b209749f
AK		 2728static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2729 struct kvm_tpr_access_ctl *tac)
2730{
2731 if (tac->flags)
2732 return -EINVAL;
2733 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2734 return 0;
2735}
2736
890ca9ae
HY		 2737static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2738 u64 mcg_cap)
2739{
2740 int r;
2741 unsigned bank_num = mcg_cap & 0xff, bank;
2742
2743 r = -EINVAL;
a9e38c3e 2744 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2745 goto out;
2746 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2747 goto out;
2748 r = 0;
2749 vcpu->arch.mcg_cap = mcg_cap;
2750 /* Init IA32_MCG_CTL to all 1s */
2751 if (mcg_cap & MCG_CTL_P)
2752 vcpu->arch.mcg_ctl = ~(u64)0;
2753 /* Init IA32_MCi_CTL to all 1s */
2754 for (bank = 0; bank < bank_num; bank++)
2755 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2756out:
2757 return r;
2758}
2759
2760static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2761 struct kvm_x86_mce *mce)
2762{
2763 u64 mcg_cap = vcpu->arch.mcg_cap;
2764 unsigned bank_num = mcg_cap & 0xff;
2765 u64 *banks = vcpu->arch.mce_banks;
2766
2767 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2768 return -EINVAL;
2769 /*
2770 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2771 * reporting is disabled
2772 */
2773 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2774 vcpu->arch.mcg_ctl != ~(u64)0)
2775 return 0;
2776 banks += 4 * mce->bank;
2777 /*
2778 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2779 * reporting is disabled for the bank
2780 */
2781 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2782 return 0;
2783 if (mce->status & MCI_STATUS_UC) {
2784 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2785 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2786 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2787 return 0;
2788 }
2789 if (banks[1] & MCI_STATUS_VAL)
2790 mce->status |= MCI_STATUS_OVER;
2791 banks[2] = mce->addr;
2792 banks[3] = mce->misc;
2793 vcpu->arch.mcg_status = mce->mcg_status;
2794 banks[1] = mce->status;
2795 kvm_queue_exception(vcpu, MC_VECTOR);
2796 } else if (!(banks[1] & MCI_STATUS_VAL)
2797 || !(banks[1] & MCI_STATUS_UC)) {
2798 if (banks[1] & MCI_STATUS_VAL)
2799 mce->status |= MCI_STATUS_OVER;
2800 banks[2] = mce->addr;
2801 banks[3] = mce->misc;
2802 banks[1] = mce->status;
2803 } else
2804 banks[1] |= MCI_STATUS_OVER;
2805 return 0;
2806}
2807
3cfc3092
JK		 2808static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2809 struct kvm_vcpu_events *events)
2810{
7460fb4a 2811 process_nmi(vcpu);
03b82a30
JK		 2812 events->exception.injected =
2813 vcpu->arch.exception.pending &&
2814 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2815 events->exception.nr = vcpu->arch.exception.nr;
2816 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2817 events->exception.pad = 0;
3cfc3092
JK		 2818 events->exception.error_code = vcpu->arch.exception.error_code;
2819
03b82a30
JK		 2820 events->interrupt.injected =
2821 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2822 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2823 events->interrupt.soft = 0;
48005f64
JK		 2824 events->interrupt.shadow =
2825 kvm_x86_ops->get_interrupt_shadow(vcpu,
2826 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2827
2828 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2829 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2830 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2831 events->nmi.pad = 0;
3cfc3092
JK		 2832
2833 events->sipi_vector = vcpu->arch.sipi_vector;
2834
dab4b911 2835 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2836 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2837 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2838 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2839}
2840
2841static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2842 struct kvm_vcpu_events *events)
2843{
dab4b911 2844 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2845 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2846 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2847 return -EINVAL;
2848
7460fb4a 2849 process_nmi(vcpu);
3cfc3092
JK		 2850 vcpu->arch.exception.pending = events->exception.injected;
2851 vcpu->arch.exception.nr = events->exception.nr;
2852 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2853 vcpu->arch.exception.error_code = events->exception.error_code;
2854
2855 vcpu->arch.interrupt.pending = events->interrupt.injected;
2856 vcpu->arch.interrupt.nr = events->interrupt.nr;
2857 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2858 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2859 kvm_x86_ops->set_interrupt_shadow(vcpu,
2860 events->interrupt.shadow);
3cfc3092
JK		 2861
2862 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2863 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2864 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2865 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2866
dab4b911
JK		 2867 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR)
2868 vcpu->arch.sipi_vector = events->sipi_vector;
3cfc3092 2869
3842d135
AK		 2870 kvm_make_request(KVM_REQ_EVENT, vcpu);
2871
3cfc3092
JK		 2872 return 0;
2873}
2874
a1efbe77
JK		 2875static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2876 struct kvm_debugregs *dbgregs)
2877{
a1efbe77
JK		 2878 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2879 dbgregs->dr6 = vcpu->arch.dr6;
2880 dbgregs->dr7 = vcpu->arch.dr7;
2881 dbgregs->flags = 0;
97e69aa6 2882 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2883}
2884
2885static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2886 struct kvm_debugregs *dbgregs)
2887{
2888 if (dbgregs->flags)
2889 return -EINVAL;
2890
a1efbe77
JK		 2891 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2892 vcpu->arch.dr6 = dbgregs->dr6;
2893 vcpu->arch.dr7 = dbgregs->dr7;
2894
a1efbe77
JK		 2895 return 0;
2896}
2897
2d5b5a66
SY		 2898static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2899 struct kvm_xsave *guest_xsave)
2900{
2901 if (cpu_has_xsave)
2902 memcpy(guest_xsave->region,
2903 &vcpu->arch.guest_fpu.state->xsave,
f45755b8 2904 xstate_size);
2d5b5a66
SY		 2905 else {
2906 memcpy(guest_xsave->region,
2907 &vcpu->arch.guest_fpu.state->fxsave,
2908 sizeof(struct i387_fxsave_struct));
2909 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2910 XSTATE_FPSSE;
2911 }
2912}
2913
2914static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
2915 struct kvm_xsave *guest_xsave)
2916{
2917 u64 xstate_bv =
2918 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
2919
2920 if (cpu_has_xsave)
2921 memcpy(&vcpu->arch.guest_fpu.state->xsave,
f45755b8 2922 guest_xsave->region, xstate_size);
2d5b5a66
SY		 2923 else {
2924 if (xstate_bv & ~XSTATE_FPSSE)
2925 return -EINVAL;
2926 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
2927 guest_xsave->region, sizeof(struct i387_fxsave_struct));
2928 }
2929 return 0;
2930}
2931
2932static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
2933 struct kvm_xcrs *guest_xcrs)
2934{
2935 if (!cpu_has_xsave) {
2936 guest_xcrs->nr_xcrs = 0;
2937 return;
2938 }
2939
2940 guest_xcrs->nr_xcrs = 1;
2941 guest_xcrs->flags = 0;
2942 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
2943 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
2944}
2945
2946static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
2947 struct kvm_xcrs *guest_xcrs)
2948{
2949 int i, r = 0;
2950
2951 if (!cpu_has_xsave)
2952 return -EINVAL;
2953
2954 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
2955 return -EINVAL;
2956
2957 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
2958 /* Only support XCR0 currently */
2959 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
2960 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
2961 guest_xcrs->xcrs[0].value);
2962 break;
2963 }
2964 if (r)
2965 r = -EINVAL;
2966 return r;
2967}
2968
1c0b28c2
EM		 2969/*
2970 * kvm_set_guest_paused() indicates to the guest kernel that it has been
2971 * stopped by the hypervisor. This function will be called from the host only.
2972 * EINVAL is returned when the host attempts to set the flag for a guest that
2973 * does not support pv clocks.
2974 */
2975static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
2976{
1c0b28c2
EM		 2977 if (!vcpu->arch.time_page)
2978 return -EINVAL;
51d59c6b 2979 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 2980 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
2981 return 0;
2982}
2983
313a3dc7
CO		 2984long kvm_arch_vcpu_ioctl(struct file *filp,
2985 unsigned int ioctl, unsigned long arg)
2986{
2987 struct kvm_vcpu *vcpu = filp->private_data;
2988 void __user *argp = (void __user *)arg;
2989 int r;
d1ac91d8
AK		 2990 union {
2991 struct kvm_lapic_state *lapic;
2992 struct kvm_xsave *xsave;
2993 struct kvm_xcrs *xcrs;
2994 void *buffer;
2995 } u;
2996
2997 u.buffer = NULL;
313a3dc7
CO		 2998 switch (ioctl) {
2999 case KVM_GET_LAPIC: {
2204ae3c
MT		 3000 r = -EINVAL;
3001 if (!vcpu->arch.apic)
3002 goto out;
d1ac91d8 3003 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3004
b772ff36 3005 r = -ENOMEM;
d1ac91d8 3006 if (!u.lapic)
b772ff36 3007 goto out;
d1ac91d8 3008 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3009 if (r)
3010 goto out;
3011 r = -EFAULT;
d1ac91d8 3012 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3013 goto out;
3014 r = 0;
3015 break;
3016 }
3017 case KVM_SET_LAPIC: {
2204ae3c
MT		 3018 r = -EINVAL;
3019 if (!vcpu->arch.apic)
3020 goto out;
ff5c2c03 3021 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3022 if (IS_ERR(u.lapic))
3023 return PTR_ERR(u.lapic);
ff5c2c03 3024
d1ac91d8 3025 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3026 break;
3027 }
f77bc6a4
ZX		 3028 case KVM_INTERRUPT: {
3029 struct kvm_interrupt irq;
3030
3031 r = -EFAULT;
3032 if (copy_from_user(&irq, argp, sizeof irq))
3033 goto out;
3034 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3035 break;
3036 }
c4abb7c9
JK		 3037 case KVM_NMI: {
3038 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3039 break;
3040 }
313a3dc7
CO		 3041 case KVM_SET_CPUID: {
3042 struct kvm_cpuid __user *cpuid_arg = argp;
3043 struct kvm_cpuid cpuid;
3044
3045 r = -EFAULT;
3046 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3047 goto out;
3048 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3049 break;
3050 }
07716717
DK		 3051 case KVM_SET_CPUID2: {
3052 struct kvm_cpuid2 __user *cpuid_arg = argp;
3053 struct kvm_cpuid2 cpuid;
3054
3055 r = -EFAULT;
3056 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3057 goto out;
3058 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3059 cpuid_arg->entries);
07716717
DK		 3060 break;
3061 }
3062 case KVM_GET_CPUID2: {
3063 struct kvm_cpuid2 __user *cpuid_arg = argp;
3064 struct kvm_cpuid2 cpuid;
3065
3066 r = -EFAULT;
3067 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3068 goto out;
3069 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3070 cpuid_arg->entries);
07716717
DK		 3071 if (r)
3072 goto out;
3073 r = -EFAULT;
3074 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3075 goto out;
3076 r = 0;
3077 break;
3078 }
313a3dc7
CO		 3079 case KVM_GET_MSRS:
3080 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3081 break;
3082 case KVM_SET_MSRS:
3083 r = msr_io(vcpu, argp, do_set_msr, 0);
3084 break;
b209749f
AK		 3085 case KVM_TPR_ACCESS_REPORTING: {
3086 struct kvm_tpr_access_ctl tac;
3087
3088 r = -EFAULT;
3089 if (copy_from_user(&tac, argp, sizeof tac))
3090 goto out;
3091 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3092 if (r)
3093 goto out;
3094 r = -EFAULT;
3095 if (copy_to_user(argp, &tac, sizeof tac))
3096 goto out;
3097 r = 0;
3098 break;
3099 };
b93463aa
AK		 3100 case KVM_SET_VAPIC_ADDR: {
3101 struct kvm_vapic_addr va;
3102
3103 r = -EINVAL;
3104 if (!irqchip_in_kernel(vcpu->kvm))
3105 goto out;
3106 r = -EFAULT;
3107 if (copy_from_user(&va, argp, sizeof va))
3108 goto out;
3109 r = 0;
3110 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3111 break;
3112 }
890ca9ae
HY		 3113 case KVM_X86_SETUP_MCE: {
3114 u64 mcg_cap;
3115
3116 r = -EFAULT;
3117 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3118 goto out;
3119 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3120 break;
3121 }
3122 case KVM_X86_SET_MCE: {
3123 struct kvm_x86_mce mce;
3124
3125 r = -EFAULT;
3126 if (copy_from_user(&mce, argp, sizeof mce))
3127 goto out;
3128 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3129 break;
3130 }
3cfc3092
JK		 3131 case KVM_GET_VCPU_EVENTS: {
3132 struct kvm_vcpu_events events;
3133
3134 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3135
3136 r = -EFAULT;
3137 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3138 break;
3139 r = 0;
3140 break;
3141 }
3142 case KVM_SET_VCPU_EVENTS: {
3143 struct kvm_vcpu_events events;
3144
3145 r = -EFAULT;
3146 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3147 break;
3148
3149 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3150 break;
3151 }
a1efbe77
JK		 3152 case KVM_GET_DEBUGREGS: {
3153 struct kvm_debugregs dbgregs;
3154
3155 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3156
3157 r = -EFAULT;
3158 if (copy_to_user(argp, &dbgregs,
3159 sizeof(struct kvm_debugregs)))
3160 break;
3161 r = 0;
3162 break;
3163 }
3164 case KVM_SET_DEBUGREGS: {
3165 struct kvm_debugregs dbgregs;
3166
3167 r = -EFAULT;
3168 if (copy_from_user(&dbgregs, argp,
3169 sizeof(struct kvm_debugregs)))
3170 break;
3171
3172 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3173 break;
3174 }
2d5b5a66 3175 case KVM_GET_XSAVE: {
d1ac91d8 3176 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3177 r = -ENOMEM;
d1ac91d8 3178 if (!u.xsave)
2d5b5a66
SY		 3179 break;
3180
d1ac91d8 3181 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3182
3183 r = -EFAULT;
d1ac91d8 3184 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3185 break;
3186 r = 0;
3187 break;
3188 }
3189 case KVM_SET_XSAVE: {
ff5c2c03 3190 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3191 if (IS_ERR(u.xsave))
3192 return PTR_ERR(u.xsave);
2d5b5a66 3193
d1ac91d8 3194 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3195 break;
3196 }
3197 case KVM_GET_XCRS: {
d1ac91d8 3198 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3199 r = -ENOMEM;
d1ac91d8 3200 if (!u.xcrs)
2d5b5a66
SY		 3201 break;
3202
d1ac91d8 3203 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3204
3205 r = -EFAULT;
d1ac91d8 3206 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3207 sizeof(struct kvm_xcrs)))
3208 break;
3209 r = 0;
3210 break;
3211 }
3212 case KVM_SET_XCRS: {
ff5c2c03 3213 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3214 if (IS_ERR(u.xcrs))
3215 return PTR_ERR(u.xcrs);
2d5b5a66 3216
d1ac91d8 3217 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3218 break;
3219 }
92a1f12d
JR		 3220 case KVM_SET_TSC_KHZ: {
3221 u32 user_tsc_khz;
3222
3223 r = -EINVAL;
92a1f12d
JR		 3224 user_tsc_khz = (u32)arg;
3225
3226 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3227 goto out;
3228
cc578287
ZA		 3229 if (user_tsc_khz == 0)
3230 user_tsc_khz = tsc_khz;
3231
3232 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3233
3234 r = 0;
3235 goto out;
3236 }
3237 case KVM_GET_TSC_KHZ: {
cc578287 3238 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3239 goto out;
3240 }
1c0b28c2
EM		 3241 case KVM_KVMCLOCK_CTRL: {
3242 r = kvm_set_guest_paused(vcpu);
3243 goto out;
3244 }
313a3dc7
CO		 3245 default:
3246 r = -EINVAL;
3247 }
3248out:
d1ac91d8 3249 kfree(u.buffer);
313a3dc7
CO		 3250 return r;
3251}
3252
5b1c1493
CO		 3253int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3254{
3255 return VM_FAULT_SIGBUS;
3256}
3257
1fe779f8
CO		 3258static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3259{
3260 int ret;
3261
3262 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3263 return -EINVAL;
1fe779f8
CO		 3264 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3265 return ret;
3266}
3267
b927a3ce
SY		 3268static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3269 u64 ident_addr)
3270{
3271 kvm->arch.ept_identity_map_addr = ident_addr;
3272 return 0;
3273}
3274
1fe779f8
CO		 3275static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3276 u32 kvm_nr_mmu_pages)
3277{
3278 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3279 return -EINVAL;
3280
79fac95e 3281 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3282
3283 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3284 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3285
79fac95e 3286 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3287 return 0;
3288}
3289
3290static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3291{
39de71ec 3292 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3293}
3294
1fe779f8
CO		 3295static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3296{
3297 int r;
3298
3299 r = 0;
3300 switch (chip->chip_id) {
3301 case KVM_IRQCHIP_PIC_MASTER:
3302 memcpy(&chip->chip.pic,
3303 &pic_irqchip(kvm)->pics[0],
3304 sizeof(struct kvm_pic_state));
3305 break;
3306 case KVM_IRQCHIP_PIC_SLAVE:
3307 memcpy(&chip->chip.pic,
3308 &pic_irqchip(kvm)->pics[1],
3309 sizeof(struct kvm_pic_state));
3310 break;
3311 case KVM_IRQCHIP_IOAPIC:
eba0226b 3312 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3313 break;
3314 default:
3315 r = -EINVAL;
3316 break;
3317 }
3318 return r;
3319}
3320
3321static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3322{
3323 int r;
3324
3325 r = 0;
3326 switch (chip->chip_id) {
3327 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3328 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3329 memcpy(&pic_irqchip(kvm)->pics[0],
3330 &chip->chip.pic,
3331 sizeof(struct kvm_pic_state));
f4f51050 3332 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3333 break;
3334 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3335 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3336 memcpy(&pic_irqchip(kvm)->pics[1],
3337 &chip->chip.pic,
3338 sizeof(struct kvm_pic_state));
f4f51050 3339 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3340 break;
3341 case KVM_IRQCHIP_IOAPIC:
eba0226b 3342 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3343 break;
3344 default:
3345 r = -EINVAL;
3346 break;
3347 }
3348 kvm_pic_update_irq(pic_irqchip(kvm));
3349 return r;
3350}
3351
e0f63cb9
SY		 3352static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3353{
3354 int r = 0;
3355
894a9c55 3356 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3357 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3358 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3359 return r;
3360}
3361
3362static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3363{
3364 int r = 0;
3365
894a9c55 3366 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3367 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3368 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3369 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3370 return r;
3371}
3372
3373static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3374{
3375 int r = 0;
3376
3377 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3378 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3379 sizeof(ps->channels));
3380 ps->flags = kvm->arch.vpit->pit_state.flags;
3381 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3382 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3383 return r;
3384}
3385
3386static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3387{
3388 int r = 0, start = 0;
3389 u32 prev_legacy, cur_legacy;
3390 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3391 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3392 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3393 if (!prev_legacy && cur_legacy)
3394 start = 1;
3395 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3396 sizeof(kvm->arch.vpit->pit_state.channels));
3397 kvm->arch.vpit->pit_state.flags = ps->flags;
3398 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3399 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3400 return r;
3401}
3402
52d939a0
MT		 3403static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3404 struct kvm_reinject_control *control)
3405{
3406 if (!kvm->arch.vpit)
3407 return -ENXIO;
894a9c55 3408 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3409 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3410 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3411 return 0;
3412}
3413
95d4c16c 3414/**
60c34612
TY		 3415 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3416 * @kvm: kvm instance
3417 * @log: slot id and address to which we copy the log
95d4c16c 3418 *
60c34612
TY		 3419 * We need to keep it in mind that VCPU threads can write to the bitmap
3420 * concurrently. So, to avoid losing data, we keep the following order for
3421 * each bit:
95d4c16c 3422 *
60c34612
TY		 3423 * 1. Take a snapshot of the bit and clear it if needed.
3424 * 2. Write protect the corresponding page.
3425 * 3. Flush TLB's if needed.
3426 * 4. Copy the snapshot to the userspace.
95d4c16c 3427 *
60c34612
TY		 3428 * Between 2 and 3, the guest may write to the page using the remaining TLB
3429 * entry. This is not a problem because the page will be reported dirty at
3430 * step 4 using the snapshot taken before and step 3 ensures that successive
3431 * writes will be logged for the next call.
5bb064dc 3432 */
60c34612 3433int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3434{
7850ac54 3435 int r;
5bb064dc 3436 struct kvm_memory_slot *memslot;
60c34612
TY		 3437 unsigned long n, i;
3438 unsigned long *dirty_bitmap;
3439 unsigned long *dirty_bitmap_buffer;
3440 bool is_dirty = false;
5bb064dc 3441
79fac95e 3442 mutex_lock(&kvm->slots_lock);
5bb064dc 3443
b050b015 3444 r = -EINVAL;
bbacc0c1 3445 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3446 goto out;
3447
28a37544 3448 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3449
3450 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3451 r = -ENOENT;
60c34612 3452 if (!dirty_bitmap)
b050b015
MT		 3453 goto out;
3454
87bf6e7d 3455 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3456
60c34612
TY		 3457 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3458 memset(dirty_bitmap_buffer, 0, n);
b050b015 3459
60c34612 3460 spin_lock(&kvm->mmu_lock);
b050b015 3461
60c34612
TY		 3462 for (i = 0; i < n / sizeof(long); i++) {
3463 unsigned long mask;
3464 gfn_t offset;
cdfca7b3 3465
60c34612
TY		 3466 if (!dirty_bitmap[i])
3467 continue;
b050b015 3468
60c34612 3469 is_dirty = true;
914ebccd 3470
60c34612
TY		 3471 mask = xchg(&dirty_bitmap[i], 0);
3472 dirty_bitmap_buffer[i] = mask;
edde99ce 3473
60c34612
TY		 3474 offset = i * BITS_PER_LONG;
3475 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3476 }
60c34612
TY		 3477 if (is_dirty)
3478 kvm_flush_remote_tlbs(kvm);
3479
3480 spin_unlock(&kvm->mmu_lock);
3481
3482 r = -EFAULT;
3483 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3484 goto out;
b050b015 3485
5bb064dc
ZX		 3486 r = 0;
3487out:
79fac95e 3488 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3489 return r;
3490}
3491
23d43cf9
CD		 3492int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event)
3493{
3494 if (!irqchip_in_kernel(kvm))
3495 return -ENXIO;
3496
3497 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
3498 irq_event->irq, irq_event->level);
3499 return 0;
3500}
3501
1fe779f8
CO		 3502long kvm_arch_vm_ioctl(struct file *filp,
3503 unsigned int ioctl, unsigned long arg)
3504{
3505 struct kvm *kvm = filp->private_data;
3506 void __user *argp = (void __user *)arg;
367e1319 3507 int r = -ENOTTY;
f0d66275
DH		 3508 /*
3509 * This union makes it completely explicit to gcc-3.x
3510 * that these two variables' stack usage should be
3511 * combined, not added together.
3512 */
3513 union {
3514 struct kvm_pit_state ps;
e9f42757 3515 struct kvm_pit_state2 ps2;
c5ff41ce 3516 struct kvm_pit_config pit_config;
f0d66275 3517 } u;
1fe779f8
CO		 3518
3519 switch (ioctl) {
3520 case KVM_SET_TSS_ADDR:
3521 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3522 break;
b927a3ce
SY		 3523 case KVM_SET_IDENTITY_MAP_ADDR: {
3524 u64 ident_addr;
3525
3526 r = -EFAULT;
3527 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3528 goto out;
3529 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3530 break;
3531 }
1fe779f8
CO		 3532 case KVM_SET_NR_MMU_PAGES:
3533 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3534 break;
3535 case KVM_GET_NR_MMU_PAGES:
3536 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3537 break;
3ddea128
MT		 3538 case KVM_CREATE_IRQCHIP: {
3539 struct kvm_pic *vpic;
3540
3541 mutex_lock(&kvm->lock);
3542 r = -EEXIST;
3543 if (kvm->arch.vpic)
3544 goto create_irqchip_unlock;
3e515705
AK		 3545 r = -EINVAL;
3546 if (atomic_read(&kvm->online_vcpus))
3547 goto create_irqchip_unlock;
1fe779f8 3548 r = -ENOMEM;
3ddea128
MT		 3549 vpic = kvm_create_pic(kvm);
3550 if (vpic) {
1fe779f8
CO		 3551 r = kvm_ioapic_init(kvm);
3552 if (r) {
175504cd 3553 mutex_lock(&kvm->slots_lock);
72bb2fcd 3554 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3555 &vpic->dev_master);
3556 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3557 &vpic->dev_slave);
3558 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3559 &vpic->dev_eclr);
175504cd 3560 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3561 kfree(vpic);
3562 goto create_irqchip_unlock;
1fe779f8
CO		 3563 }
3564 } else
3ddea128
MT		 3565 goto create_irqchip_unlock;
3566 smp_wmb();
3567 kvm->arch.vpic = vpic;
3568 smp_wmb();
399ec807
AK		 3569 r = kvm_setup_default_irq_routing(kvm);
3570 if (r) {
175504cd 3571 mutex_lock(&kvm->slots_lock);
3ddea128 3572 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3573 kvm_ioapic_destroy(kvm);
3574 kvm_destroy_pic(kvm);
3ddea128 3575 mutex_unlock(&kvm->irq_lock);
175504cd 3576 mutex_unlock(&kvm->slots_lock);
399ec807 3577 }
3ddea128
MT		 3578 create_irqchip_unlock:
3579 mutex_unlock(&kvm->lock);
1fe779f8 3580 break;
3ddea128 3581 }
7837699f 3582 case KVM_CREATE_PIT:
c5ff41ce
JK		 3583 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3584 goto create_pit;
3585 case KVM_CREATE_PIT2:
3586 r = -EFAULT;
3587 if (copy_from_user(&u.pit_config, argp,
3588 sizeof(struct kvm_pit_config)))
3589 goto out;
3590 create_pit:
79fac95e 3591 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3592 r = -EEXIST;
3593 if (kvm->arch.vpit)
3594 goto create_pit_unlock;
7837699f 3595 r = -ENOMEM;
c5ff41ce 3596 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3597 if (kvm->arch.vpit)
3598 r = 0;
269e05e4 3599 create_pit_unlock:
79fac95e 3600 mutex_unlock(&kvm->slots_lock);
7837699f 3601 break;
1fe779f8
CO		 3602 case KVM_GET_IRQCHIP: {
3603 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3604 struct kvm_irqchip *chip;
1fe779f8 3605
ff5c2c03
SL		 3606 chip = memdup_user(argp, sizeof(*chip));
3607 if (IS_ERR(chip)) {
3608 r = PTR_ERR(chip);
1fe779f8 3609 goto out;
ff5c2c03
SL		 3610 }
3611
1fe779f8
CO		 3612 r = -ENXIO;
3613 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3614 goto get_irqchip_out;
3615 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3616 if (r)
f0d66275 3617 goto get_irqchip_out;
1fe779f8 3618 r = -EFAULT;
f0d66275
DH		 3619 if (copy_to_user(argp, chip, sizeof *chip))
3620 goto get_irqchip_out;
1fe779f8 3621 r = 0;
f0d66275
DH		 3622 get_irqchip_out:
3623 kfree(chip);
1fe779f8
CO		 3624 break;
3625 }
3626 case KVM_SET_IRQCHIP: {
3627 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3628 struct kvm_irqchip *chip;
1fe779f8 3629
ff5c2c03
SL		 3630 chip = memdup_user(argp, sizeof(*chip));
3631 if (IS_ERR(chip)) {
3632 r = PTR_ERR(chip);
1fe779f8 3633 goto out;
ff5c2c03
SL		 3634 }
3635
1fe779f8
CO		 3636 r = -ENXIO;
3637 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3638 goto set_irqchip_out;
3639 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3640 if (r)
f0d66275 3641 goto set_irqchip_out;
1fe779f8 3642 r = 0;
f0d66275
DH		 3643 set_irqchip_out:
3644 kfree(chip);
1fe779f8
CO		 3645 break;
3646 }
e0f63cb9 3647 case KVM_GET_PIT: {
e0f63cb9 3648 r = -EFAULT;
f0d66275 3649 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3650 goto out;
3651 r = -ENXIO;
3652 if (!kvm->arch.vpit)
3653 goto out;
f0d66275 3654 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3655 if (r)
3656 goto out;
3657 r = -EFAULT;
f0d66275 3658 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3659 goto out;
3660 r = 0;
3661 break;
3662 }
3663 case KVM_SET_PIT: {
e0f63cb9 3664 r = -EFAULT;
f0d66275 3665 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3666 goto out;
3667 r = -ENXIO;
3668 if (!kvm->arch.vpit)
3669 goto out;
f0d66275 3670 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3671 break;
3672 }
e9f42757
BK		 3673 case KVM_GET_PIT2: {
3674 r = -ENXIO;
3675 if (!kvm->arch.vpit)
3676 goto out;
3677 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3678 if (r)
3679 goto out;
3680 r = -EFAULT;
3681 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3682 goto out;
3683 r = 0;
3684 break;
3685 }
3686 case KVM_SET_PIT2: {
3687 r = -EFAULT;
3688 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3689 goto out;
3690 r = -ENXIO;
3691 if (!kvm->arch.vpit)
3692 goto out;
3693 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3694 break;
3695 }
52d939a0
MT		 3696 case KVM_REINJECT_CONTROL: {
3697 struct kvm_reinject_control control;
3698 r = -EFAULT;
3699 if (copy_from_user(&control, argp, sizeof(control)))
3700 goto out;
3701 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3702 break;
3703 }
ffde22ac
ES		 3704 case KVM_XEN_HVM_CONFIG: {
3705 r = -EFAULT;
3706 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3707 sizeof(struct kvm_xen_hvm_config)))
3708 goto out;
3709 r = -EINVAL;
3710 if (kvm->arch.xen_hvm_config.flags)
3711 goto out;
3712 r = 0;
3713 break;
3714 }
afbcf7ab 3715 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3716 struct kvm_clock_data user_ns;
3717 u64 now_ns;
3718 s64 delta;
3719
3720 r = -EFAULT;
3721 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3722 goto out;
3723
3724 r = -EINVAL;
3725 if (user_ns.flags)
3726 goto out;
3727
3728 r = 0;
395c6b0a 3729 local_irq_disable();
759379dd 3730 now_ns = get_kernel_ns();
afbcf7ab 3731 delta = user_ns.clock - now_ns;
395c6b0a 3732 local_irq_enable();
afbcf7ab
GC		 3733 kvm->arch.kvmclock_offset = delta;
3734 break;
3735 }
3736 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3737 struct kvm_clock_data user_ns;
3738 u64 now_ns;
3739
395c6b0a 3740 local_irq_disable();
759379dd 3741 now_ns = get_kernel_ns();
afbcf7ab 3742 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3743 local_irq_enable();
afbcf7ab 3744 user_ns.flags = 0;
97e69aa6 3745 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3746
3747 r = -EFAULT;
3748 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3749 goto out;
3750 r = 0;
3751 break;
3752 }
3753
1fe779f8
CO		 3754 default:
3755 ;
3756 }
3757out:
3758 return r;
3759}
3760
a16b043c 3761static void kvm_init_msr_list(void)
043405e1
CO		 3762{
3763 u32 dummy[2];
3764 unsigned i, j;
3765
e3267cbb
GC		 3766 /* skip the first msrs in the list. KVM-specific */
3767 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3768 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3769 continue;
3770 if (j < i)
3771 msrs_to_save[j] = msrs_to_save[i];
3772 j++;
3773 }
3774 num_msrs_to_save = j;
3775}
3776
bda9020e
MT		 3777static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3778 const void *v)
bbd9b64e 3779{
70252a10
AK		 3780 int handled = 0;
3781 int n;
3782
3783 do {
3784 n = min(len, 8);
3785 if (!(vcpu->arch.apic &&
3786 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3787 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3788 break;
3789 handled += n;
3790 addr += n;
3791 len -= n;
3792 v += n;
3793 } while (len);
bbd9b64e 3794
70252a10 3795 return handled;
bbd9b64e
CO		 3796}
3797
bda9020e 3798static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3799{
70252a10
AK		 3800 int handled = 0;
3801 int n;
3802
3803 do {
3804 n = min(len, 8);
3805 if (!(vcpu->arch.apic &&
3806 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3807 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3808 break;
3809 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3810 handled += n;
3811 addr += n;
3812 len -= n;
3813 v += n;
3814 } while (len);
bbd9b64e 3815
70252a10 3816 return handled;
bbd9b64e
CO		 3817}
3818
2dafc6c2
GN		 3819static void kvm_set_segment(struct kvm_vcpu *vcpu,
3820 struct kvm_segment *var, int seg)
3821{
3822 kvm_x86_ops->set_segment(vcpu, var, seg);
3823}
3824
3825void kvm_get_segment(struct kvm_vcpu *vcpu,
3826 struct kvm_segment *var, int seg)
3827{
3828 kvm_x86_ops->get_segment(vcpu, var, seg);
3829}
3830
e459e322 3831gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3832{
3833 gpa_t t_gpa;
ab9ae313 3834 struct x86_exception exception;
02f59dc9
JR		 3835
3836 BUG_ON(!mmu_is_nested(vcpu));
3837
3838 /* NPT walks are always user-walks */
3839 access |= PFERR_USER_MASK;
ab9ae313 3840 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3841
3842 return t_gpa;
3843}
3844
ab9ae313
AK		 3845gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3846 struct x86_exception *exception)
1871c602
GN		 3847{
3848 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3849 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3850}
3851
ab9ae313
AK		 3852 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3853 struct x86_exception *exception)
1871c602
GN		 3854{
3855 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3856 access |= PFERR_FETCH_MASK;
ab9ae313 3857 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3858}
3859
ab9ae313
AK		 3860gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3861 struct x86_exception *exception)
1871c602
GN		 3862{
3863 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3864 access |= PFERR_WRITE_MASK;
ab9ae313 3865 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3866}
3867
3868/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3869gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3870 struct x86_exception *exception)
1871c602 3871{
ab9ae313 3872 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3873}
3874
3875static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3876 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3877 struct x86_exception *exception)
bbd9b64e
CO		 3878{
3879 void *data = val;
10589a46 3880 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3881
3882 while (bytes) {
14dfe855 3883 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3884 exception);
bbd9b64e 3885 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3886 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3887 int ret;
3888
bcc55cba 3889 if (gpa == UNMAPPED_GVA)
ab9ae313 3890 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3891 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3892 if (ret < 0) {
c3cd7ffa 3893 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3894 goto out;
3895 }
bbd9b64e 3896
77c2002e
IE		 3897 bytes -= toread;
3898 data += toread;
3899 addr += toread;
bbd9b64e 3900 }
10589a46 3901out:
10589a46 3902 return r;
bbd9b64e 3903}
77c2002e 3904
1871c602 3905/* used for instruction fetching */
0f65dd70
AK		 3906static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
3907 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3908 struct x86_exception *exception)
1871c602 3909{
0f65dd70 3910 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3911 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3912
1871c602 3913 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 3914 access | PFERR_FETCH_MASK,
3915 exception);
1871c602
GN		 3916}
3917
064aea77 3918int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 3919 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3920 struct x86_exception *exception)
1871c602 3921{
0f65dd70 3922 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 3923 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 3924
1871c602 3925 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 3926 exception);
1871c602 3927}
064aea77 3928EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 3929
0f65dd70
AK		 3930static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
3931 gva_t addr, void *val, unsigned int bytes,
bcc55cba 3932 struct x86_exception *exception)
1871c602 3933{
0f65dd70 3934 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 3935 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 3936}
3937
6a4d7550 3938int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 3939 gva_t addr, void *val,
2dafc6c2 3940 unsigned int bytes,
bcc55cba 3941 struct x86_exception *exception)
77c2002e 3942{
0f65dd70 3943 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 3944 void *data = val;
3945 int r = X86EMUL_CONTINUE;
3946
3947 while (bytes) {
14dfe855
JR		 3948 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
3949 PFERR_WRITE_MASK,
ab9ae313 3950 exception);
77c2002e
IE		 3951 unsigned offset = addr & (PAGE_SIZE-1);
3952 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
3953 int ret;
3954
bcc55cba 3955 if (gpa == UNMAPPED_GVA)
ab9ae313 3956 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 3957 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
3958 if (ret < 0) {
c3cd7ffa 3959 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 3960 goto out;
3961 }
3962
3963 bytes -= towrite;
3964 data += towrite;
3965 addr += towrite;
3966 }
3967out:
3968 return r;
3969}
6a4d7550 3970EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 3971
af7cc7d1
XG		 3972static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
3973 gpa_t *gpa, struct x86_exception *exception,
3974 bool write)
3975{
97d64b78
AK		 3976 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
3977 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 3978
97d64b78
AK		 3979 if (vcpu_match_mmio_gva(vcpu, gva)
3980 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
bebb106a
XG		 3981 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
3982 (gva & (PAGE_SIZE - 1));
4f022648 3983 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 3984 return 1;
3985 }
3986
af7cc7d1
XG		 3987 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
3988
3989 if (*gpa == UNMAPPED_GVA)
3990 return -1;
3991
3992 /* For APIC access vmexit */
3993 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
3994 return 1;
3995
4f022648
XG		 3996 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
3997 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 3998 return 1;
4f022648 3999 }
bebb106a 4000
af7cc7d1
XG		 4001 return 0;
4002}
4003
3200f405 4004int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4005 const void *val, int bytes)
bbd9b64e
CO		 4006{
4007 int ret;
4008
4009 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4010 if (ret < 0)
bbd9b64e 4011 return 0;
f57f2ef5 4012 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4013 return 1;
4014}
4015
77d197b2
XG		 4016struct read_write_emulator_ops {
4017 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4018 int bytes);
4019 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4020 void *val, int bytes);
4021 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4022 int bytes, void *val);
4023 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4024 void *val, int bytes);
4025 bool write;
4026};
4027
4028static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4029{
4030 if (vcpu->mmio_read_completed) {
77d197b2 4031 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4032 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4033 vcpu->mmio_read_completed = 0;
4034 return 1;
4035 }
4036
4037 return 0;
4038}
4039
4040static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4041 void *val, int bytes)
4042{
4043 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4044}
4045
4046static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4047 void *val, int bytes)
4048{
4049 return emulator_write_phys(vcpu, gpa, val, bytes);
4050}
4051
4052static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4053{
4054 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4055 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4056}
4057
4058static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4059 void *val, int bytes)
4060{
4061 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4062 return X86EMUL_IO_NEEDED;
4063}
4064
4065static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4066 void *val, int bytes)
4067{
f78146b0
AK		 4068 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4069
87da7e66 4070 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4071 return X86EMUL_CONTINUE;
4072}
4073
0fbe9b0b 4074static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4075 .read_write_prepare = read_prepare,
4076 .read_write_emulate = read_emulate,
4077 .read_write_mmio = vcpu_mmio_read,
4078 .read_write_exit_mmio = read_exit_mmio,
4079};
4080
0fbe9b0b 4081static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4082 .read_write_emulate = write_emulate,
4083 .read_write_mmio = write_mmio,
4084 .read_write_exit_mmio = write_exit_mmio,
4085 .write = true,
4086};
4087
22388a3c
XG		 4088static int emulator_read_write_onepage(unsigned long addr, void *val,
4089 unsigned int bytes,
4090 struct x86_exception *exception,
4091 struct kvm_vcpu *vcpu,
0fbe9b0b 4092 const struct read_write_emulator_ops *ops)
bbd9b64e 4093{
af7cc7d1
XG		 4094 gpa_t gpa;
4095 int handled, ret;
22388a3c 4096 bool write = ops->write;
f78146b0 4097 struct kvm_mmio_fragment *frag;
10589a46 4098
22388a3c 4099 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4100
af7cc7d1 4101 if (ret < 0)
bbd9b64e 4102 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4103
4104 /* For APIC access vmexit */
af7cc7d1 4105 if (ret)
bbd9b64e
CO		 4106 goto mmio;
4107
22388a3c 4108 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4109 return X86EMUL_CONTINUE;
4110
4111mmio:
4112 /*
4113 * Is this MMIO handled locally?
4114 */
22388a3c 4115 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4116 if (handled == bytes)
bbd9b64e 4117 return X86EMUL_CONTINUE;
bbd9b64e 4118
70252a10
AK		 4119 gpa += handled;
4120 bytes -= handled;
4121 val += handled;
4122
87da7e66
XG		 4123 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4124 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4125 frag->gpa = gpa;
4126 frag->data = val;
4127 frag->len = bytes;
f78146b0 4128 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4129}
4130
22388a3c
XG		 4131int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4132 void *val, unsigned int bytes,
4133 struct x86_exception *exception,
0fbe9b0b 4134 const struct read_write_emulator_ops *ops)
bbd9b64e 4135{
0f65dd70 4136 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4137 gpa_t gpa;
4138 int rc;
4139
4140 if (ops->read_write_prepare &&
4141 ops->read_write_prepare(vcpu, val, bytes))
4142 return X86EMUL_CONTINUE;
4143
4144 vcpu->mmio_nr_fragments = 0;
0f65dd70 4145
bbd9b64e
CO		 4146 /* Crossing a page boundary? */
4147 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4148 int now;
bbd9b64e
CO		 4149
4150 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4151 rc = emulator_read_write_onepage(addr, val, now, exception,
4152 vcpu, ops);
4153
bbd9b64e
CO		 4154 if (rc != X86EMUL_CONTINUE)
4155 return rc;
4156 addr += now;
4157 val += now;
4158 bytes -= now;
4159 }
22388a3c 4160
f78146b0
AK		 4161 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4162 vcpu, ops);
4163 if (rc != X86EMUL_CONTINUE)
4164 return rc;
4165
4166 if (!vcpu->mmio_nr_fragments)
4167 return rc;
4168
4169 gpa = vcpu->mmio_fragments[0].gpa;
4170
4171 vcpu->mmio_needed = 1;
4172 vcpu->mmio_cur_fragment = 0;
4173
87da7e66 4174 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4175 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4176 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4177 vcpu->run->mmio.phys_addr = gpa;
4178
4179 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4180}
4181
4182static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4183 unsigned long addr,
4184 void *val,
4185 unsigned int bytes,
4186 struct x86_exception *exception)
4187{
4188 return emulator_read_write(ctxt, addr, val, bytes,
4189 exception, &read_emultor);
4190}
4191
4192int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4193 unsigned long addr,
4194 const void *val,
4195 unsigned int bytes,
4196 struct x86_exception *exception)
4197{
4198 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4199 exception, &write_emultor);
bbd9b64e 4200}
bbd9b64e 4201
daea3e73
AK		 4202#define CMPXCHG_TYPE(t, ptr, old, new) \
4203 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4204
4205#ifdef CONFIG_X86_64
4206# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4207#else
4208# define CMPXCHG64(ptr, old, new) \
9749a6c0 4209 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4210#endif
4211
0f65dd70
AK		 4212static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4213 unsigned long addr,
bbd9b64e
CO		 4214 const void *old,
4215 const void *new,
4216 unsigned int bytes,
0f65dd70 4217 struct x86_exception *exception)
bbd9b64e 4218{
0f65dd70 4219 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4220 gpa_t gpa;
4221 struct page *page;
4222 char *kaddr;
4223 bool exchanged;
2bacc55c 4224
daea3e73
AK		 4225 /* guests cmpxchg8b have to be emulated atomically */
4226 if (bytes > 8 || (bytes & (bytes - 1)))
4227 goto emul_write;
10589a46 4228
daea3e73 4229 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4230
daea3e73
AK		 4231 if (gpa == UNMAPPED_GVA ||
4232 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4233 goto emul_write;
2bacc55c 4234
daea3e73
AK		 4235 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4236 goto emul_write;
72dc67a6 4237
daea3e73 4238 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4239 if (is_error_page(page))
c19b8bd6 4240 goto emul_write;
72dc67a6 4241
8fd75e12 4242 kaddr = kmap_atomic(page);
daea3e73
AK		 4243 kaddr += offset_in_page(gpa);
4244 switch (bytes) {
4245 case 1:
4246 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4247 break;
4248 case 2:
4249 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4250 break;
4251 case 4:
4252 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4253 break;
4254 case 8:
4255 exchanged = CMPXCHG64(kaddr, old, new);
4256 break;
4257 default:
4258 BUG();
2bacc55c 4259 }
8fd75e12 4260 kunmap_atomic(kaddr);
daea3e73
AK		 4261 kvm_release_page_dirty(page);
4262
4263 if (!exchanged)
4264 return X86EMUL_CMPXCHG_FAILED;
4265
f57f2ef5 4266 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4267
4268 return X86EMUL_CONTINUE;
4a5f48f6 4269
3200f405 4270emul_write:
daea3e73 4271 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4272
0f65dd70 4273 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4274}
4275
cf8f70bf
GN		 4276static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4277{
4278 /* TODO: String I/O for in kernel device */
4279 int r;
4280
4281 if (vcpu->arch.pio.in)
4282 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4283 vcpu->arch.pio.size, pd);
4284 else
4285 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4286 vcpu->arch.pio.port, vcpu->arch.pio.size,
4287 pd);
4288 return r;
4289}
4290
6f6fbe98
XG		 4291static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4292 unsigned short port, void *val,
4293 unsigned int count, bool in)
cf8f70bf 4294{
6f6fbe98 4295 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 4296
4297 vcpu->arch.pio.port = port;
6f6fbe98 4298 vcpu->arch.pio.in = in;
7972995b 4299 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4300 vcpu->arch.pio.size = size;
4301
4302 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4303 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4304 return 1;
4305 }
4306
4307 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4308 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4309 vcpu->run->io.size = size;
4310 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4311 vcpu->run->io.count = count;
4312 vcpu->run->io.port = port;
4313
4314 return 0;
4315}
4316
6f6fbe98
XG		 4317static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4318 int size, unsigned short port, void *val,
4319 unsigned int count)
cf8f70bf 4320{
ca1d4a9e 4321 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4322 int ret;
ca1d4a9e 4323
6f6fbe98
XG		 4324 if (vcpu->arch.pio.count)
4325 goto data_avail;
cf8f70bf 4326
6f6fbe98
XG		 4327 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4328 if (ret) {
4329data_avail:
4330 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4331 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4332 return 1;
4333 }
4334
cf8f70bf
GN		 4335 return 0;
4336}
4337
6f6fbe98
XG		 4338static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4339 int size, unsigned short port,
4340 const void *val, unsigned int count)
4341{
4342 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4343
4344 memcpy(vcpu->arch.pio_data, val, size * count);
4345 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4346}
4347
bbd9b64e
CO		 4348static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4349{
4350 return kvm_x86_ops->get_segment_base(vcpu, seg);
4351}
4352
3cb16fe7 4353static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4354{
3cb16fe7 4355 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4356}
4357
f5f48ee1
SY		 4358int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4359{
4360 if (!need_emulate_wbinvd(vcpu))
4361 return X86EMUL_CONTINUE;
4362
4363 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4364 int cpu = get_cpu();
4365
4366 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4367 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4368 wbinvd_ipi, NULL, 1);
2eec7343 4369 put_cpu();
f5f48ee1 4370 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4371 } else
4372 wbinvd();
f5f48ee1
SY		 4373 return X86EMUL_CONTINUE;
4374}
4375EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4376
bcaf5cc5
AK		 4377static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4378{
4379 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4380}
4381
717746e3 4382int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4383{
717746e3 4384 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4385}
4386
717746e3 4387int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4388{
338dbc97 4389
717746e3 4390 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4391}
4392
52a46617 4393static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4394{
52a46617 4395 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4396}
4397
717746e3 4398static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4399{
717746e3 4400 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4401 unsigned long value;
4402
4403 switch (cr) {
4404 case 0:
4405 value = kvm_read_cr0(vcpu);
4406 break;
4407 case 2:
4408 value = vcpu->arch.cr2;
4409 break;
4410 case 3:
9f8fe504 4411 value = kvm_read_cr3(vcpu);
52a46617
GN		 4412 break;
4413 case 4:
4414 value = kvm_read_cr4(vcpu);
4415 break;
4416 case 8:
4417 value = kvm_get_cr8(vcpu);
4418 break;
4419 default:
a737f256 4420 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4421 return 0;
4422 }
4423
4424 return value;
4425}
4426
717746e3 4427static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4428{
717746e3 4429 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4430 int res = 0;
4431
52a46617
GN		 4432 switch (cr) {
4433 case 0:
49a9b07e 4434 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4435 break;
4436 case 2:
4437 vcpu->arch.cr2 = val;
4438 break;
4439 case 3:
2390218b 4440 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4441 break;
4442 case 4:
a83b29c6 4443 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4444 break;
4445 case 8:
eea1cff9 4446 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4447 break;
4448 default:
a737f256 4449 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4450 res = -1;
52a46617 4451 }
0f12244f
GN		 4452
4453 return res;
52a46617
GN		 4454}
4455
4cee4798
KW		 4456static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4457{
4458 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4459}
4460
717746e3 4461static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4462{
717746e3 4463 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4464}
4465
4bff1e86 4466static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4467{
4bff1e86 4468 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4469}
4470
4bff1e86 4471static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4472{
4bff1e86 4473 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4474}
4475
1ac9d0cf
AK		 4476static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4477{
4478 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4479}
4480
4481static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4482{
4483 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4484}
4485
4bff1e86
AK		 4486static unsigned long emulator_get_cached_segment_base(
4487 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4488{
4bff1e86 4489 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4490}
4491
1aa36616
AK		 4492static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4493 struct desc_struct *desc, u32 *base3,
4494 int seg)
2dafc6c2
GN		 4495{
4496 struct kvm_segment var;
4497
4bff1e86 4498 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4499 *selector = var.selector;
2dafc6c2 4500
378a8b09
GN		 4501 if (var.unusable) {
4502 memset(desc, 0, sizeof(*desc));
2dafc6c2 4503 return false;
378a8b09 4504 }
2dafc6c2
GN		 4505
4506 if (var.g)
4507 var.limit >>= 12;
4508 set_desc_limit(desc, var.limit);
4509 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4510#ifdef CONFIG_X86_64
4511 if (base3)
4512 *base3 = var.base >> 32;
4513#endif
2dafc6c2
GN		 4514 desc->type = var.type;
4515 desc->s = var.s;
4516 desc->dpl = var.dpl;
4517 desc->p = var.present;
4518 desc->avl = var.avl;
4519 desc->l = var.l;
4520 desc->d = var.db;
4521 desc->g = var.g;
4522
4523 return true;
4524}
4525
1aa36616
AK		 4526static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4527 struct desc_struct *desc, u32 base3,
4528 int seg)
2dafc6c2 4529{
4bff1e86 4530 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4531 struct kvm_segment var;
4532
1aa36616 4533 var.selector = selector;
2dafc6c2 4534 var.base = get_desc_base(desc);
5601d05b
GN		 4535#ifdef CONFIG_X86_64
4536 var.base |= ((u64)base3) << 32;
4537#endif
2dafc6c2
GN		 4538 var.limit = get_desc_limit(desc);
4539 if (desc->g)
4540 var.limit = (var.limit << 12) | 0xfff;
4541 var.type = desc->type;
4542 var.present = desc->p;
4543 var.dpl = desc->dpl;
4544 var.db = desc->d;
4545 var.s = desc->s;
4546 var.l = desc->l;
4547 var.g = desc->g;
4548 var.avl = desc->avl;
4549 var.present = desc->p;
4550 var.unusable = !var.present;
4551 var.padding = 0;
4552
4553 kvm_set_segment(vcpu, &var, seg);
4554 return;
4555}
4556
717746e3
AK		 4557static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4558 u32 msr_index, u64 *pdata)
4559{
4560 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4561}
4562
4563static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4564 u32 msr_index, u64 data)
4565{
8fe8ab46
WA		 4566 struct msr_data msr;
4567
4568 msr.data = data;
4569 msr.index = msr_index;
4570 msr.host_initiated = false;
4571 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4572}
4573
222d21aa
AK		 4574static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4575 u32 pmc, u64 *pdata)
4576{
4577 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4578}
4579
6c3287f7
AK		 4580static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4581{
4582 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4583}
4584
5037f6f3
AK		 4585static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4586{
4587 preempt_disable();
5197b808 4588 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4589 /*
4590 * CR0.TS may reference the host fpu state, not the guest fpu state,
4591 * so it may be clear at this point.
4592 */
4593 clts();
4594}
4595
4596static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4597{
4598 preempt_enable();
4599}
4600
2953538e 4601static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4602 struct x86_instruction_info *info,
c4f035c6
AK		 4603 enum x86_intercept_stage stage)
4604{
2953538e 4605 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4606}
4607
0017f93a 4608static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4609 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4610{
0017f93a 4611 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4612}
4613
dd856efa
AK		 4614static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4615{
4616 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4617}
4618
4619static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4620{
4621 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4622}
4623
0225fb50 4624static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4625 .read_gpr = emulator_read_gpr,
4626 .write_gpr = emulator_write_gpr,
1871c602 4627 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4628 .write_std = kvm_write_guest_virt_system,
1871c602 4629 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4630 .read_emulated = emulator_read_emulated,
4631 .write_emulated = emulator_write_emulated,
4632 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4633 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4634 .pio_in_emulated = emulator_pio_in_emulated,
4635 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4636 .get_segment = emulator_get_segment,
4637 .set_segment = emulator_set_segment,
5951c442 4638 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4639 .get_gdt = emulator_get_gdt,
160ce1f1 4640 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4641 .set_gdt = emulator_set_gdt,
4642 .set_idt = emulator_set_idt,
52a46617
GN		 4643 .get_cr = emulator_get_cr,
4644 .set_cr = emulator_set_cr,
4cee4798 4645 .set_rflags = emulator_set_rflags,
9c537244 4646 .cpl = emulator_get_cpl,
35aa5375
GN		 4647 .get_dr = emulator_get_dr,
4648 .set_dr = emulator_set_dr,
717746e3
AK		 4649 .set_msr = emulator_set_msr,
4650 .get_msr = emulator_get_msr,
222d21aa 4651 .read_pmc = emulator_read_pmc,
6c3287f7 4652 .halt = emulator_halt,
bcaf5cc5 4653 .wbinvd = emulator_wbinvd,
d6aa1000 4654 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4655 .get_fpu = emulator_get_fpu,
4656 .put_fpu = emulator_put_fpu,
c4f035c6 4657 .intercept = emulator_intercept,
bdb42f5a 4658 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4659};
4660
95cb2295
GN		 4661static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4662{
4663 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4664 /*
4665 * an sti; sti; sequence only disable interrupts for the first
4666 * instruction. So, if the last instruction, be it emulated or
4667 * not, left the system with the INT_STI flag enabled, it
4668 * means that the last instruction is an sti. We should not
4669 * leave the flag on in this case. The same goes for mov ss
4670 */
4671 if (!(int_shadow & mask))
4672 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4673}
4674
54b8486f
GN		 4675static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4676{
4677 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4678 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4679 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4680 else if (ctxt->exception.error_code_valid)
4681 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4682 ctxt->exception.error_code);
54b8486f 4683 else
da9cb575 4684 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4685}
4686
dd856efa 4687static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
b5c9ff73 4688{
9dac77fa 4689 memset(&ctxt->twobyte, 0,
dd856efa 4690 (void *)&ctxt->_regs - (void *)&ctxt->twobyte);
b5c9ff73 4691
9dac77fa
AK		 4692 ctxt->fetch.start = 0;
4693 ctxt->fetch.end = 0;
4694 ctxt->io_read.pos = 0;
4695 ctxt->io_read.end = 0;
4696 ctxt->mem_read.pos = 0;
4697 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4698}
4699
8ec4722d
MG		 4700static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4701{
adf52235 4702 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4703 int cs_db, cs_l;
4704
8ec4722d
MG		 4705 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4706
adf52235
TY		 4707 ctxt->eflags = kvm_get_rflags(vcpu);
4708 ctxt->eip = kvm_rip_read(vcpu);
4709 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4710 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4711 cs_l ? X86EMUL_MODE_PROT64 :
4712 cs_db ? X86EMUL_MODE_PROT32 :
4713 X86EMUL_MODE_PROT16;
4714 ctxt->guest_mode = is_guest_mode(vcpu);
4715
dd856efa 4716 init_decode_cache(ctxt);
7ae441ea 4717 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4718}
4719
71f9833b 4720int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4721{
9d74191a 4722 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4723 int ret;
4724
4725 init_emulate_ctxt(vcpu);
4726
9dac77fa
AK		 4727 ctxt->op_bytes = 2;
4728 ctxt->ad_bytes = 2;
4729 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4730 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4731
4732 if (ret != X86EMUL_CONTINUE)
4733 return EMULATE_FAIL;
4734
9dac77fa 4735 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4736 kvm_rip_write(vcpu, ctxt->eip);
4737 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4738
4739 if (irq == NMI_VECTOR)
7460fb4a 4740 vcpu->arch.nmi_pending = 0;
63995653
MG		 4741 else
4742 vcpu->arch.interrupt.pending = false;
4743
4744 return EMULATE_DONE;
4745}
4746EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4747
6d77dbfc
GN		 4748static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4749{
fc3a9157
JR		 4750 int r = EMULATE_DONE;
4751
6d77dbfc
GN		 4752 ++vcpu->stat.insn_emulation_fail;
4753 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4754 if (!is_guest_mode(vcpu)) {
4755 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4756 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4757 vcpu->run->internal.ndata = 0;
4758 r = EMULATE_FAIL;
4759 }
6d77dbfc 4760 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4761
4762 return r;
6d77dbfc
GN		 4763}
4764
93c05d3e
XG		 4765static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
4766 bool write_fault_to_shadow_pgtable)
a6f177ef 4767{
95b3cf69 4768 gpa_t gpa = cr2;
8e3d9d06 4769 pfn_t pfn;
a6f177ef 4770
95b3cf69
XG		 4771 if (!vcpu->arch.mmu.direct_map) {
4772 /*
4773 * Write permission should be allowed since only
4774 * write access need to be emulated.
4775 */
4776 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
22368028 4777
95b3cf69
XG		 4778 /*
4779 * If the mapping is invalid in guest, let cpu retry
4780 * it to generate fault.
4781 */
4782 if (gpa == UNMAPPED_GVA)
4783 return true;
4784 }
a6f177ef 4785
8e3d9d06
XG		 4786 /*
4787 * Do not retry the unhandleable instruction if it faults on the
4788 * readonly host memory, otherwise it will goto a infinite loop:
4789 * retry instruction -> write #PF -> emulation fail -> retry
4790 * instruction -> ...
4791 */
4792 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 4793
4794 /*
4795 * If the instruction failed on the error pfn, it can not be fixed,
4796 * report the error to userspace.
4797 */
4798 if (is_error_noslot_pfn(pfn))
4799 return false;
4800
4801 kvm_release_pfn_clean(pfn);
4802
4803 /* The instructions are well-emulated on direct mmu. */
4804 if (vcpu->arch.mmu.direct_map) {
4805 unsigned int indirect_shadow_pages;
4806
4807 spin_lock(&vcpu->kvm->mmu_lock);
4808 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4809 spin_unlock(&vcpu->kvm->mmu_lock);
4810
4811 if (indirect_shadow_pages)
4812 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4813
a6f177ef 4814 return true;
8e3d9d06 4815 }
a6f177ef 4816
95b3cf69
XG		 4817 /*
4818 * if emulation was due to access to shadowed page table
4819 * and it failed try to unshadow page and re-enter the
4820 * guest to let CPU execute the instruction.
4821 */
4822 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 4823
4824 /*
4825 * If the access faults on its page table, it can not
4826 * be fixed by unprotecting shadow page and it should
4827 * be reported to userspace.
4828 */
4829 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 4830}
4831
1cb3f3ae
XG		 4832static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4833 unsigned long cr2, int emulation_type)
4834{
4835 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4836 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4837
4838 last_retry_eip = vcpu->arch.last_retry_eip;
4839 last_retry_addr = vcpu->arch.last_retry_addr;
4840
4841 /*
4842 * If the emulation is caused by #PF and it is non-page_table
4843 * writing instruction, it means the VM-EXIT is caused by shadow
4844 * page protected, we can zap the shadow page and retry this
4845 * instruction directly.
4846 *
4847 * Note: if the guest uses a non-page-table modifying instruction
4848 * on the PDE that points to the instruction, then we will unmap
4849 * the instruction and go to an infinite loop. So, we cache the
4850 * last retried eip and the last fault address, if we meet the eip
4851 * and the address again, we can break out of the potential infinite
4852 * loop.
4853 */
4854 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4855
4856 if (!(emulation_type & EMULTYPE_RETRY))
4857 return false;
4858
4859 if (x86_page_table_writing_insn(ctxt))
4860 return false;
4861
4862 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4863 return false;
4864
4865 vcpu->arch.last_retry_eip = ctxt->eip;
4866 vcpu->arch.last_retry_addr = cr2;
4867
4868 if (!vcpu->arch.mmu.direct_map)
4869 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4870
22368028 4871 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 4872
4873 return true;
4874}
4875
716d51ab
GN		 4876static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4877static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4878
51d8b661
AP		 4879int x86_emulate_instruction(struct kvm_vcpu *vcpu,
4880 unsigned long cr2,
dc25e89e
AP		 4881 int emulation_type,
4882 void *insn,
4883 int insn_len)
bbd9b64e 4884{
95cb2295 4885 int r;
9d74191a 4886 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 4887 bool writeback = true;
93c05d3e 4888 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 4889
93c05d3e
XG		 4890 /*
4891 * Clear write_fault_to_shadow_pgtable here to ensure it is
4892 * never reused.
4893 */
4894 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 4895 kvm_clear_exception_queue(vcpu);
8d7d8102 4896
571008da 4897 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 4898 init_emulate_ctxt(vcpu);
9d74191a
TY		 4899 ctxt->interruptibility = 0;
4900 ctxt->have_exception = false;
4901 ctxt->perm_ok = false;
bbd9b64e 4902
9d74191a 4903 ctxt->only_vendor_specific_insn
4005996e
AK		 4904 = emulation_type & EMULTYPE_TRAP_UD;
4905
9d74191a 4906 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 4907
e46479f8 4908 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 4909 ++vcpu->stat.insn_emulation;
1d2887e2 4910 if (r != EMULATION_OK) {
4005996e
AK		 4911 if (emulation_type & EMULTYPE_TRAP_UD)
4912 return EMULATE_FAIL;
93c05d3e
XG		 4913 if (reexecute_instruction(vcpu, cr2,
4914 write_fault_to_spt))
bbd9b64e 4915 return EMULATE_DONE;
6d77dbfc
GN		 4916 if (emulation_type & EMULTYPE_SKIP)
4917 return EMULATE_FAIL;
4918 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4919 }
4920 }
4921
ba8afb6b 4922 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 4923 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 4924 return EMULATE_DONE;
4925 }
4926
1cb3f3ae
XG		 4927 if (retry_instruction(ctxt, cr2, emulation_type))
4928 return EMULATE_DONE;
4929
7ae441ea 4930 /* this is needed for vmware backdoor interface to work since it
4d2179e1 4931 changes registers values during IO operation */
7ae441ea
GN		 4932 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
4933 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 4934 emulator_invalidate_register_cache(ctxt);
7ae441ea 4935 }
4d2179e1 4936
5cd21917 4937restart:
9d74191a 4938 r = x86_emulate_insn(ctxt);
bbd9b64e 4939
775fde86
JR		 4940 if (r == EMULATION_INTERCEPTED)
4941 return EMULATE_DONE;
4942
d2ddd1c4 4943 if (r == EMULATION_FAILED) {
93c05d3e 4944 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt))
c3cd7ffa
GN		 4945 return EMULATE_DONE;
4946
6d77dbfc 4947 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 4948 }
4949
9d74191a 4950 if (ctxt->have_exception) {
54b8486f 4951 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 4952 r = EMULATE_DONE;
4953 } else if (vcpu->arch.pio.count) {
3457e419
GN		 4954 if (!vcpu->arch.pio.in)
4955 vcpu->arch.pio.count = 0;
716d51ab 4956 else {
7ae441ea 4957 writeback = false;
716d51ab
GN		 4958 vcpu->arch.complete_userspace_io = complete_emulated_pio;
4959 }
e85d28f8 4960 r = EMULATE_DO_MMIO;
7ae441ea
GN		 4961 } else if (vcpu->mmio_needed) {
4962 if (!vcpu->mmio_is_write)
4963 writeback = false;
e85d28f8 4964 r = EMULATE_DO_MMIO;
716d51ab 4965 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 4966 } else if (r == EMULATION_RESTART)
5cd21917 4967 goto restart;
d2ddd1c4
GN		 4968 else
4969 r = EMULATE_DONE;
f850e2e6 4970
7ae441ea 4971 if (writeback) {
9d74191a
TY		 4972 toggle_interruptibility(vcpu, ctxt->interruptibility);
4973 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea 4974 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea 4975 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 4976 kvm_rip_write(vcpu, ctxt->eip);
7ae441ea
GN		 4977 } else
4978 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 4979
4980 return r;
de7d789a 4981}
51d8b661 4982EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 4983
cf8f70bf 4984int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 4985{
cf8f70bf 4986 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 4987 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
4988 size, port, &val, 1);
cf8f70bf 4989 /* do not return to emulator after return from userspace */
7972995b 4990 vcpu->arch.pio.count = 0;
de7d789a
CO		 4991 return ret;
4992}
cf8f70bf 4993EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 4994
8cfdc000
ZA		 4995static void tsc_bad(void *info)
4996{
0a3aee0d 4997 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 4998}
4999
5000static void tsc_khz_changed(void *data)
c8076604 5001{
8cfdc000
ZA		 5002 struct cpufreq_freqs *freq = data;
5003 unsigned long khz = 0;
5004
5005 if (data)
5006 khz = freq->new;
5007 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5008 khz = cpufreq_quick_get(raw_smp_processor_id());
5009 if (!khz)
5010 khz = tsc_khz;
0a3aee0d 5011 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5012}
5013
c8076604
GH		 5014static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5015 void *data)
5016{
5017 struct cpufreq_freqs *freq = data;
5018 struct kvm *kvm;
5019 struct kvm_vcpu *vcpu;
5020 int i, send_ipi = 0;
5021
8cfdc000
ZA		 5022 /*
5023 * We allow guests to temporarily run on slowing clocks,
5024 * provided we notify them after, or to run on accelerating
5025 * clocks, provided we notify them before. Thus time never
5026 * goes backwards.
5027 *
5028 * However, we have a problem. We can't atomically update
5029 * the frequency of a given CPU from this function; it is
5030 * merely a notifier, which can be called from any CPU.
5031 * Changing the TSC frequency at arbitrary points in time
5032 * requires a recomputation of local variables related to
5033 * the TSC for each VCPU. We must flag these local variables
5034 * to be updated and be sure the update takes place with the
5035 * new frequency before any guests proceed.
5036 *
5037 * Unfortunately, the combination of hotplug CPU and frequency
5038 * change creates an intractable locking scenario; the order
5039 * of when these callouts happen is undefined with respect to
5040 * CPU hotplug, and they can race with each other. As such,
5041 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5042 * undefined; you can actually have a CPU frequency change take
5043 * place in between the computation of X and the setting of the
5044 * variable. To protect against this problem, all updates of
5045 * the per_cpu tsc_khz variable are done in an interrupt
5046 * protected IPI, and all callers wishing to update the value
5047 * must wait for a synchronous IPI to complete (which is trivial
5048 * if the caller is on the CPU already). This establishes the
5049 * necessary total order on variable updates.
5050 *
5051 * Note that because a guest time update may take place
5052 * anytime after the setting of the VCPU's request bit, the
5053 * correct TSC value must be set before the request. However,
5054 * to ensure the update actually makes it to any guest which
5055 * starts running in hardware virtualization between the set
5056 * and the acquisition of the spinlock, we must also ping the
5057 * CPU after setting the request bit.
5058 *
5059 */
5060
c8076604
GH		 5061 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5062 return 0;
5063 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5064 return 0;
8cfdc000
ZA		 5065
5066 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5067
e935b837 5068 raw_spin_lock(&kvm_lock);
c8076604 5069 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5070 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5071 if (vcpu->cpu != freq->cpu)
5072 continue;
c285545f 5073 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5074 if (vcpu->cpu != smp_processor_id())
8cfdc000 5075 send_ipi = 1;
c8076604
GH		 5076 }
5077 }
e935b837 5078 raw_spin_unlock(&kvm_lock);
c8076604
GH		 5079
5080 if (freq->old < freq->new && send_ipi) {
5081 /*
5082 * We upscale the frequency. Must make the guest
5083 * doesn't see old kvmclock values while running with
5084 * the new frequency, otherwise we risk the guest sees
5085 * time go backwards.
5086 *
5087 * In case we update the frequency for another cpu
5088 * (which might be in guest context) send an interrupt
5089 * to kick the cpu out of guest context. Next time
5090 * guest context is entered kvmclock will be updated,
5091 * so the guest will not see stale values.
5092 */
8cfdc000 5093 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5094 }
5095 return 0;
5096}
5097
5098static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5099 .notifier_call = kvmclock_cpufreq_notifier
5100};
5101
5102static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5103 unsigned long action, void *hcpu)
5104{
5105 unsigned int cpu = (unsigned long)hcpu;
5106
5107 switch (action) {
5108 case CPU_ONLINE:
5109 case CPU_DOWN_FAILED:
5110 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5111 break;
5112 case CPU_DOWN_PREPARE:
5113 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5114 break;
5115 }
5116 return NOTIFY_OK;
5117}
5118
5119static struct notifier_block kvmclock_cpu_notifier_block = {
5120 .notifier_call = kvmclock_cpu_notifier,
5121 .priority = -INT_MAX
c8076604
GH		 5122};
5123
b820cc0c
ZA		 5124static void kvm_timer_init(void)
5125{
5126 int cpu;
5127
c285545f 5128 max_tsc_khz = tsc_khz;
8cfdc000 5129 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 5130 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5131#ifdef CONFIG_CPU_FREQ
5132 struct cpufreq_policy policy;
5133 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5134 cpu = get_cpu();
5135 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5136 if (policy.cpuinfo.max_freq)
5137 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5138 put_cpu();
c285545f 5139#endif
b820cc0c
ZA		 5140 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5141 CPUFREQ_TRANSITION_NOTIFIER);
5142 }
c285545f 5143 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5144 for_each_online_cpu(cpu)
5145 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 5146}
5147
ff9d07a0
ZY		 5148static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5149
f5132b01 5150int kvm_is_in_guest(void)
ff9d07a0 5151{
086c9855 5152 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5153}
5154
5155static int kvm_is_user_mode(void)
5156{
5157 int user_mode = 3;
dcf46b94 5158
086c9855
AS		 5159 if (__this_cpu_read(current_vcpu))
5160 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5161
ff9d07a0
ZY		 5162 return user_mode != 0;
5163}
5164
5165static unsigned long kvm_get_guest_ip(void)
5166{
5167 unsigned long ip = 0;
dcf46b94 5168
086c9855
AS		 5169 if (__this_cpu_read(current_vcpu))
5170 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5171
ff9d07a0
ZY		 5172 return ip;
5173}
5174
5175static struct perf_guest_info_callbacks kvm_guest_cbs = {
5176 .is_in_guest = kvm_is_in_guest,
5177 .is_user_mode = kvm_is_user_mode,
5178 .get_guest_ip = kvm_get_guest_ip,
5179};
5180
5181void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5182{
086c9855 5183 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5184}
5185EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5186
5187void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5188{
086c9855 5189 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5190}
5191EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5192
ce88decf
XG		 5193static void kvm_set_mmio_spte_mask(void)
5194{
5195 u64 mask;
5196 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5197
5198 /*
5199 * Set the reserved bits and the present bit of an paging-structure
5200 * entry to generate page fault with PFER.RSV = 1.
5201 */
5202 mask = ((1ull << (62 - maxphyaddr + 1)) - 1) << maxphyaddr;
5203 mask |= 1ull;
5204
5205#ifdef CONFIG_X86_64
5206 /*
5207 * If reserved bit is not supported, clear the present bit to disable
5208 * mmio page fault.
5209 */
5210 if (maxphyaddr == 52)
5211 mask &= ~1ull;
5212#endif
5213
5214 kvm_mmu_set_mmio_spte_mask(mask);
5215}
5216
16e8d74d
MT		 5217#ifdef CONFIG_X86_64
5218static void pvclock_gtod_update_fn(struct work_struct *work)
5219{
d828199e
MT		 5220 struct kvm *kvm;
5221
5222 struct kvm_vcpu *vcpu;
5223 int i;
5224
5225 raw_spin_lock(&kvm_lock);
5226 list_for_each_entry(kvm, &vm_list, vm_list)
5227 kvm_for_each_vcpu(i, vcpu, kvm)
5228 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5229 atomic_set(&kvm_guest_has_master_clock, 0);
5230 raw_spin_unlock(&kvm_lock);
16e8d74d
MT		 5231}
5232
5233static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5234
5235/*
5236 * Notification about pvclock gtod data update.
5237 */
5238static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5239 void *priv)
5240{
5241 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5242 struct timekeeper *tk = priv;
5243
5244 update_pvclock_gtod(tk);
5245
5246 /* disable master clock if host does not trust, or does not
5247 * use, TSC clocksource
5248 */
5249 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5250 atomic_read(&kvm_guest_has_master_clock) != 0)
5251 queue_work(system_long_wq, &pvclock_gtod_work);
5252
5253 return 0;
5254}
5255
5256static struct notifier_block pvclock_gtod_notifier = {
5257 .notifier_call = pvclock_gtod_notify,
5258};
5259#endif
5260
f8c16bba 5261int kvm_arch_init(void *opaque)
043405e1 5262{
b820cc0c 5263 int r;
f8c16bba
ZX		 5264 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
5265
f8c16bba
ZX		 5266 if (kvm_x86_ops) {
5267 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5268 r = -EEXIST;
5269 goto out;
f8c16bba
ZX		 5270 }
5271
5272 if (!ops->cpu_has_kvm_support()) {
5273 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5274 r = -EOPNOTSUPP;
5275 goto out;
f8c16bba
ZX		 5276 }
5277 if (ops->disabled_by_bios()) {
5278 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5279 r = -EOPNOTSUPP;
5280 goto out;
f8c16bba
ZX		 5281 }
5282
013f6a5d
MT		 5283 r = -ENOMEM;
5284 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5285 if (!shared_msrs) {
5286 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5287 goto out;
5288 }
5289
97db56ce
AK		 5290 r = kvm_mmu_module_init();
5291 if (r)
013f6a5d 5292 goto out_free_percpu;
97db56ce 5293
ce88decf 5294 kvm_set_mmio_spte_mask();
97db56ce
AK		 5295 kvm_init_msr_list();
5296
f8c16bba 5297 kvm_x86_ops = ops;
7b52345e 5298 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5299 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5300
b820cc0c 5301 kvm_timer_init();
c8076604 5302
ff9d07a0
ZY		 5303 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5304
2acf923e
DC		 5305 if (cpu_has_xsave)
5306 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5307
c5cc421b 5308 kvm_lapic_init();
16e8d74d
MT		 5309#ifdef CONFIG_X86_64
5310 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5311#endif
5312
f8c16bba 5313 return 0;
56c6d28a 5314
013f6a5d
MT		 5315out_free_percpu:
5316 free_percpu(shared_msrs);
56c6d28a 5317out:
56c6d28a 5318 return r;
043405e1 5319}
8776e519 5320
f8c16bba
ZX		 5321void kvm_arch_exit(void)
5322{
ff9d07a0
ZY		 5323 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5324
888d256e
JK		 5325 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5326 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5327 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5328 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5329#ifdef CONFIG_X86_64
5330 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5331#endif
f8c16bba 5332 kvm_x86_ops = NULL;
56c6d28a 5333 kvm_mmu_module_exit();
013f6a5d 5334 free_percpu(shared_msrs);
56c6d28a 5335}
f8c16bba 5336
8776e519
HB		 5337int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5338{
5339 ++vcpu->stat.halt_exits;
5340 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5341 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5342 return 1;
5343 } else {
5344 vcpu->run->exit_reason = KVM_EXIT_HLT;
5345 return 0;
5346 }
5347}
5348EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5349
55cd8e5a
GN		 5350int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5351{
5352 u64 param, ingpa, outgpa, ret;
5353 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5354 bool fast, longmode;
5355 int cs_db, cs_l;
5356
5357 /*
5358 * hypercall generates UD from non zero cpl and real mode
5359 * per HYPER-V spec
5360 */
3eeb3288 5361 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5362 kvm_queue_exception(vcpu, UD_VECTOR);
5363 return 0;
5364 }
5365
5366 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5367 longmode = is_long_mode(vcpu) && cs_l == 1;
5368
5369 if (!longmode) {
ccd46936
GN		 5370 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5371 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5372 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5373 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5374 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5375 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5376 }
5377#ifdef CONFIG_X86_64
5378 else {
5379 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5380 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5381 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5382 }
5383#endif
5384
5385 code = param & 0xffff;
5386 fast = (param >> 16) & 0x1;
5387 rep_cnt = (param >> 32) & 0xfff;
5388 rep_idx = (param >> 48) & 0xfff;
5389
5390 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5391
c25bc163
GN		 5392 switch (code) {
5393 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5394 kvm_vcpu_on_spin(vcpu);
5395 break;
5396 default:
5397 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5398 break;
5399 }
55cd8e5a
GN		 5400
5401 ret = res | (((u64)rep_done & 0xfff) << 32);
5402 if (longmode) {
5403 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5404 } else {
5405 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5406 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5407 }
5408
5409 return 1;
5410}
5411
8776e519
HB		 5412int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5413{
5414 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5415 int r = 1;
8776e519 5416
55cd8e5a
GN		 5417 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5418 return kvm_hv_hypercall(vcpu);
5419
5fdbf976
MT		 5420 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5421 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5422 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5423 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5424 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5425
229456fc 5426 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5427
8776e519
HB		 5428 if (!is_long_mode(vcpu)) {
5429 nr &= 0xFFFFFFFF;
5430 a0 &= 0xFFFFFFFF;
5431 a1 &= 0xFFFFFFFF;
5432 a2 &= 0xFFFFFFFF;
5433 a3 &= 0xFFFFFFFF;
5434 }
5435
07708c4a
JK		 5436 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5437 ret = -KVM_EPERM;
5438 goto out;
5439 }
5440
8776e519 5441 switch (nr) {
b93463aa
AK		 5442 case KVM_HC_VAPIC_POLL_IRQ:
5443 ret = 0;
5444 break;
8776e519
HB		 5445 default:
5446 ret = -KVM_ENOSYS;
5447 break;
5448 }
07708c4a 5449out:
5fdbf976 5450 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5451 ++vcpu->stat.hypercalls;
2f333bcb 5452 return r;
8776e519
HB		 5453}
5454EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5455
b6785def 5456static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5457{
d6aa1000 5458 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5459 char instruction[3];
5fdbf976 5460 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5461
8776e519
HB		 5462 /*
5463 * Blow out the MMU to ensure that no other VCPU has an active mapping
5464 * to ensure that the updated hypercall appears atomically across all
5465 * VCPUs.
5466 */
5467 kvm_mmu_zap_all(vcpu->kvm);
5468
8776e519 5469 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5470
9d74191a 5471 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5472}
5473
b6c7a5dc
HB		 5474/*
5475 * Check if userspace requested an interrupt window, and that the
5476 * interrupt window is open.
5477 *
5478 * No need to exit to userspace if we already have an interrupt queued.
5479 */
851ba692 5480static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5481{
8061823a 5482 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5483 vcpu->run->request_interrupt_window &&
5df56646 5484 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5485}
5486
851ba692 5487static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5488{
851ba692
AK		 5489 struct kvm_run *kvm_run = vcpu->run;
5490
91586a3b 5491 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5492 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5493 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5494 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5495 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5496 else
b6c7a5dc 5497 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5498 kvm_arch_interrupt_allowed(vcpu) &&
5499 !kvm_cpu_has_interrupt(vcpu) &&
5500 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5501}
5502
4484141a 5503static int vapic_enter(struct kvm_vcpu *vcpu)
b93463aa
AK		 5504{
5505 struct kvm_lapic *apic = vcpu->arch.apic;
5506 struct page *page;
5507
5508 if (!apic || !apic->vapic_addr)
4484141a 5509 return 0;
b93463aa
AK		 5510
5511 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
4484141a
XG		 5512 if (is_error_page(page))
5513 return -EFAULT;
72dc67a6
IE		 5514
5515 vcpu->arch.apic->vapic_page = page;
4484141a 5516 return 0;
b93463aa
AK		 5517}
5518
5519static void vapic_exit(struct kvm_vcpu *vcpu)
5520{
5521 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5522 int idx;
b93463aa
AK		 5523
5524 if (!apic || !apic->vapic_addr)
5525 return;
5526
f656ce01 5527 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5528 kvm_release_page_dirty(apic->vapic_page);
5529 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5530 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5531}
5532
95ba8273
GN		 5533static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5534{
5535 int max_irr, tpr;
5536
5537 if (!kvm_x86_ops->update_cr8_intercept)
5538 return;
5539
88c808fd
AK		 5540 if (!vcpu->arch.apic)
5541 return;
5542
8db3baa2
GN		 5543 if (!vcpu->arch.apic->vapic_addr)
5544 max_irr = kvm_lapic_find_highest_irr(vcpu);
5545 else
5546 max_irr = -1;
95ba8273
GN		 5547
5548 if (max_irr != -1)
5549 max_irr >>= 4;
5550
5551 tpr = kvm_lapic_get_cr8(vcpu);
5552
5553 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5554}
5555
851ba692 5556static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5557{
5558 /* try to reinject previous events if any */
b59bb7bd 5559 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5560 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5561 vcpu->arch.exception.has_error_code,
5562 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5563 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5564 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5565 vcpu->arch.exception.error_code,
5566 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5567 return;
5568 }
5569
95ba8273
GN		 5570 if (vcpu->arch.nmi_injected) {
5571 kvm_x86_ops->set_nmi(vcpu);
5572 return;
5573 }
5574
5575 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5576 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5577 return;
5578 }
5579
5580 /* try to inject new event if pending */
5581 if (vcpu->arch.nmi_pending) {
5582 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5583 --vcpu->arch.nmi_pending;
95ba8273
GN		 5584 vcpu->arch.nmi_injected = true;
5585 kvm_x86_ops->set_nmi(vcpu);
5586 }
c7c9c56c 5587 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
95ba8273 5588 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5589 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5590 false);
5591 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5592 }
5593 }
5594}
5595
2acf923e
DC		 5596static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
5597{
5598 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
5599 !vcpu->guest_xcr0_loaded) {
5600 /* kvm_set_xcr() also depends on this */
5601 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
5602 vcpu->guest_xcr0_loaded = 1;
5603 }
5604}
5605
5606static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
5607{
5608 if (vcpu->guest_xcr0_loaded) {
5609 if (vcpu->arch.xcr0 != host_xcr0)
5610 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
5611 vcpu->guest_xcr0_loaded = 0;
5612 }
5613}
5614
7460fb4a
AK		 5615static void process_nmi(struct kvm_vcpu *vcpu)
5616{
5617 unsigned limit = 2;
5618
5619 /*
5620 * x86 is limited to one NMI running, and one NMI pending after it.
5621 * If an NMI is already in progress, limit further NMIs to just one.
5622 * Otherwise, allow two (and we'll inject the first one immediately).
5623 */
5624 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5625 limit = 1;
5626
5627 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5628 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5629 kvm_make_request(KVM_REQ_EVENT, vcpu);
5630}
5631
d828199e
MT		 5632static void kvm_gen_update_masterclock(struct kvm *kvm)
5633{
5634#ifdef CONFIG_X86_64
5635 int i;
5636 struct kvm_vcpu *vcpu;
5637 struct kvm_arch *ka = &kvm->arch;
5638
5639 spin_lock(&ka->pvclock_gtod_sync_lock);
5640 kvm_make_mclock_inprogress_request(kvm);
5641 /* no guest entries from this point */
5642 pvclock_update_vm_gtod_copy(kvm);
5643
5644 kvm_for_each_vcpu(i, vcpu, kvm)
5645 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
5646
5647 /* guest entries allowed */
5648 kvm_for_each_vcpu(i, vcpu, kvm)
5649 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
5650
5651 spin_unlock(&ka->pvclock_gtod_sync_lock);
5652#endif
5653}
5654
c7c9c56c
YZ		 5655static void update_eoi_exitmap(struct kvm_vcpu *vcpu)
5656{
5657 u64 eoi_exit_bitmap[4];
5658
5659 memset(eoi_exit_bitmap, 0, 32);
5660
5661 kvm_ioapic_calculate_eoi_exitmap(vcpu, eoi_exit_bitmap);
5662 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
5663}
5664
851ba692 5665static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5666{
5667 int r;
6a8b1d13 5668 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5669 vcpu->run->request_interrupt_window;
d6185f20 5670 bool req_immediate_exit = 0;
b6c7a5dc 5671
3e007509 5672 if (vcpu->requests) {
a8eeb04a 5673 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5674 kvm_mmu_unload(vcpu);
a8eeb04a 5675 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5676 __kvm_migrate_timers(vcpu);
d828199e
MT		 5677 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5678 kvm_gen_update_masterclock(vcpu->kvm);
34c238a1
ZA		 5679 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5680 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5681 if (unlikely(r))
5682 goto out;
5683 }
a8eeb04a 5684 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5685 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5686 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5687 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5688 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5689 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5690 r = 0;
5691 goto out;
5692 }
a8eeb04a 5693 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5694 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5695 r = 0;
5696 goto out;
5697 }
a8eeb04a 5698 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5699 vcpu->fpu_active = 0;
5700 kvm_x86_ops->fpu_deactivate(vcpu);
5701 }
af585b92
GN		 5702 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5703 /* Page is swapped out. Do synthetic halt */
5704 vcpu->arch.apf.halted = true;
5705 r = 1;
5706 goto out;
5707 }
c9aaa895
GC		 5708 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5709 record_steal_time(vcpu);
7460fb4a
AK		 5710 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5711 process_nmi(vcpu);
d6185f20
NHE		 5712 req_immediate_exit =
5713 kvm_check_request(KVM_REQ_IMMEDIATE_EXIT, vcpu);
f5132b01
GN		 5714 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5715 kvm_handle_pmu_event(vcpu);
5716 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5717 kvm_deliver_pmi(vcpu);
c7c9c56c
YZ		 5718 if (kvm_check_request(KVM_REQ_EOIBITMAP, vcpu))
5719 update_eoi_exitmap(vcpu);
2f52d58c 5720 }
b93463aa 5721
b463a6f7
AK		 5722 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
5723 inject_pending_event(vcpu);
5724
5725 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5726 if (vcpu->arch.nmi_pending)
b463a6f7 5727 kvm_x86_ops->enable_nmi_window(vcpu);
c7c9c56c 5728 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
b463a6f7
AK		 5729 kvm_x86_ops->enable_irq_window(vcpu);
5730
5731 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 5732 /*
5733 * Update architecture specific hints for APIC
5734 * virtual interrupt delivery.
5735 */
5736 if (kvm_x86_ops->hwapic_irr_update)
5737 kvm_x86_ops->hwapic_irr_update(vcpu,
5738 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 5739 update_cr8_intercept(vcpu);
5740 kvm_lapic_sync_to_vapic(vcpu);
5741 }
5742 }
5743
d8368af8
AK		 5744 r = kvm_mmu_reload(vcpu);
5745 if (unlikely(r)) {
d905c069 5746 goto cancel_injection;
d8368af8
AK		 5747 }
5748
b6c7a5dc
HB		 5749 preempt_disable();
5750
5751 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5752 if (vcpu->fpu_active)
5753 kvm_load_guest_fpu(vcpu);
2acf923e 5754 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5755
6b7e2d09
XG		 5756 vcpu->mode = IN_GUEST_MODE;
5757
5758 /* We should set ->mode before check ->requests,
5759 * see the comment in make_all_cpus_request.
5760 */
5761 smp_mb();
b6c7a5dc 5762
d94e1dc9 5763 local_irq_disable();
32f88400 5764
6b7e2d09 5765 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5766 || need_resched() || signal_pending(current)) {
6b7e2d09 5767 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5768 smp_wmb();
6c142801
AK		 5769 local_irq_enable();
5770 preempt_enable();
5771 r = 1;
d905c069 5772 goto cancel_injection;
6c142801
AK		 5773 }
5774
f656ce01 5775 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5776
d6185f20
NHE		 5777 if (req_immediate_exit)
5778 smp_send_reschedule(vcpu->cpu);
5779
b6c7a5dc
HB		 5780 kvm_guest_enter();
5781
42dbaa5a 5782 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5783 set_debugreg(0, 7);
5784 set_debugreg(vcpu->arch.eff_db[0], 0);
5785 set_debugreg(vcpu->arch.eff_db[1], 1);
5786 set_debugreg(vcpu->arch.eff_db[2], 2);
5787 set_debugreg(vcpu->arch.eff_db[3], 3);
5788 }
b6c7a5dc 5789
229456fc 5790 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5791 kvm_x86_ops->run(vcpu);
b6c7a5dc 5792
24f1e32c
FW		 5793 /*
5794 * If the guest has used debug registers, at least dr7
5795 * will be disabled while returning to the host.
5796 * If we don't have active breakpoints in the host, we don't
5797 * care about the messed up debug address registers. But if
5798 * we have some of them active, restore the old state.
5799 */
59d8eb53 5800 if (hw_breakpoint_active())
24f1e32c 5801 hw_breakpoint_restore();
42dbaa5a 5802
886b470c
MT		 5803 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
5804 native_read_tsc());
1d5f066e 5805
6b7e2d09 5806 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5807 smp_wmb();
b6c7a5dc
HB		 5808 local_irq_enable();
5809
5810 ++vcpu->stat.exits;
5811
5812 /*
5813 * We must have an instruction between local_irq_enable() and
5814 * kvm_guest_exit(), so the timer interrupt isn't delayed by
5815 * the interrupt shadow. The stat.exits increment will do nicely.
5816 * But we need to prevent reordering, hence this barrier():
5817 */
5818 barrier();
5819
5820 kvm_guest_exit();
5821
5822 preempt_enable();
5823
f656ce01 5824 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 5825
b6c7a5dc
HB		 5826 /*
5827 * Profile KVM exit RIPs:
5828 */
5829 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 5830 unsigned long rip = kvm_rip_read(vcpu);
5831 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 5832 }
5833
cc578287
ZA		 5834 if (unlikely(vcpu->arch.tsc_always_catchup))
5835 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 5836
5cfb1d5a
MT		 5837 if (vcpu->arch.apic_attention)
5838 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 5839
851ba692 5840 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 5841 return r;
5842
5843cancel_injection:
5844 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 5845 if (unlikely(vcpu->arch.apic_attention))
5846 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 5847out:
5848 return r;
5849}
b6c7a5dc 5850
09cec754 5851
851ba692 5852static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 5853{
5854 int r;
f656ce01 5855 struct kvm *kvm = vcpu->kvm;
d7690175
MT		 5856
5857 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 5858 pr_debug("vcpu %d received sipi with vector # %x\n",
5859 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 5860 kvm_lapic_reset(vcpu);
57f252f2 5861 kvm_vcpu_reset(vcpu);
d7690175 5862 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 5863 }
5864
f656ce01 5865 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
4484141a
XG		 5866 r = vapic_enter(vcpu);
5867 if (r) {
5868 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
5869 return r;
5870 }
d7690175
MT		 5871
5872 r = 1;
5873 while (r > 0) {
af585b92
GN		 5874 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
5875 !vcpu->arch.apf.halted)
851ba692 5876 r = vcpu_enter_guest(vcpu);
d7690175 5877 else {
f656ce01 5878 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 5879 kvm_vcpu_block(vcpu);
f656ce01 5880 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
a8eeb04a 5881 if (kvm_check_request(KVM_REQ_UNHALT, vcpu))
09cec754
GN		 5882 {
5883 switch(vcpu->arch.mp_state) {
5884 case KVM_MP_STATE_HALTED:
d7690175 5885 vcpu->arch.mp_state =
09cec754
GN		 5886 KVM_MP_STATE_RUNNABLE;
5887 case KVM_MP_STATE_RUNNABLE:
af585b92 5888 vcpu->arch.apf.halted = false;
09cec754
GN		 5889 break;
5890 case KVM_MP_STATE_SIPI_RECEIVED:
5891 default:
5892 r = -EINTR;
5893 break;
5894 }
5895 }
d7690175
MT		 5896 }
5897
09cec754
GN		 5898 if (r <= 0)
5899 break;
5900
5901 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
5902 if (kvm_cpu_has_pending_timer(vcpu))
5903 kvm_inject_pending_timer_irqs(vcpu);
5904
851ba692 5905 if (dm_request_for_irq_injection(vcpu)) {
09cec754 5906 r = -EINTR;
851ba692 5907 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5908 ++vcpu->stat.request_irq_exits;
5909 }
af585b92
GN		 5910
5911 kvm_check_async_pf_completion(vcpu);
5912
09cec754
GN		 5913 if (signal_pending(current)) {
5914 r = -EINTR;
851ba692 5915 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 5916 ++vcpu->stat.signal_exits;
5917 }
5918 if (need_resched()) {
f656ce01 5919 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 5920 kvm_resched(vcpu);
f656ce01 5921 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 5922 }
b6c7a5dc
HB		 5923 }
5924
f656ce01 5925 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 5926
b93463aa
AK		 5927 vapic_exit(vcpu);
5928
b6c7a5dc
HB		 5929 return r;
5930}
5931
716d51ab
GN		 5932static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
5933{
5934 int r;
5935 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
5936 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
5937 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5938 if (r != EMULATE_DONE)
5939 return 0;
5940 return 1;
5941}
5942
5943static int complete_emulated_pio(struct kvm_vcpu *vcpu)
5944{
5945 BUG_ON(!vcpu->arch.pio.count);
5946
5947 return complete_emulated_io(vcpu);
5948}
5949
f78146b0
AK		 5950/*
5951 * Implements the following, as a state machine:
5952 *
5953 * read:
5954 * for each fragment
87da7e66
XG		 5955 * for each mmio piece in the fragment
5956 * write gpa, len
5957 * exit
5958 * copy data
f78146b0
AK		 5959 * execute insn
5960 *
5961 * write:
5962 * for each fragment
87da7e66
XG		 5963 * for each mmio piece in the fragment
5964 * write gpa, len
5965 * copy data
5966 * exit
f78146b0 5967 */
716d51ab 5968static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 5969{
5970 struct kvm_run *run = vcpu->run;
f78146b0 5971 struct kvm_mmio_fragment *frag;
87da7e66 5972 unsigned len;
5287f194 5973
716d51ab 5974 BUG_ON(!vcpu->mmio_needed);
5287f194 5975
716d51ab 5976 /* Complete previous fragment */
87da7e66
XG		 5977 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
5978 len = min(8u, frag->len);
716d51ab 5979 if (!vcpu->mmio_is_write)
87da7e66
XG		 5980 memcpy(frag->data, run->mmio.data, len);
5981
5982 if (frag->len <= 8) {
5983 /* Switch to the next fragment. */
5984 frag++;
5985 vcpu->mmio_cur_fragment++;
5986 } else {
5987 /* Go forward to the next mmio piece. */
5988 frag->data += len;
5989 frag->gpa += len;
5990 frag->len -= len;
5991 }
5992
716d51ab
GN		 5993 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
5994 vcpu->mmio_needed = 0;
cef4dea0 5995 if (vcpu->mmio_is_write)
716d51ab
GN		 5996 return 1;
5997 vcpu->mmio_read_completed = 1;
5998 return complete_emulated_io(vcpu);
5999 }
87da7e66 6000
716d51ab
GN		 6001 run->exit_reason = KVM_EXIT_MMIO;
6002 run->mmio.phys_addr = frag->gpa;
6003 if (vcpu->mmio_is_write)
87da7e66
XG		 6004 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6005 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6006 run->mmio.is_write = vcpu->mmio_is_write;
6007 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6008 return 0;
5287f194
AK		 6009}
6010
716d51ab 6011
b6c7a5dc
HB		 6012int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6013{
6014 int r;
6015 sigset_t sigsaved;
6016
e5c30142
AK		 6017 if (!tsk_used_math(current) && init_fpu(current))
6018 return -ENOMEM;
6019
ac9f6dc0
AK		 6020 if (vcpu->sigset_active)
6021 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6022
a4535290 6023 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6024 kvm_vcpu_block(vcpu);
d7690175 6025 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6026 r = -EAGAIN;
6027 goto out;
b6c7a5dc
HB		 6028 }
6029
b6c7a5dc 6030 /* re-sync apic's tpr */
eea1cff9
AP		 6031 if (!irqchip_in_kernel(vcpu->kvm)) {
6032 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6033 r = -EINVAL;
6034 goto out;
6035 }
6036 }
b6c7a5dc 6037
716d51ab
GN		 6038 if (unlikely(vcpu->arch.complete_userspace_io)) {
6039 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6040 vcpu->arch.complete_userspace_io = NULL;
6041 r = cui(vcpu);
6042 if (r <= 0)
6043 goto out;
6044 } else
6045 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6046
851ba692 6047 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6048
6049out:
f1d86e46 6050 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6051 if (vcpu->sigset_active)
6052 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6053
b6c7a5dc
HB		 6054 return r;
6055}
6056
6057int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6058{
7ae441ea
GN		 6059 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6060 /*
6061 * We are here if userspace calls get_regs() in the middle of
6062 * instruction emulation. Registers state needs to be copied
4a969980 6063 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6064 * that usually, but some bad designed PV devices (vmware
6065 * backdoor interface) need this to work
6066 */
dd856efa 6067 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6068 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6069 }
5fdbf976
MT		 6070 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6071 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6072 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6073 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6074 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6075 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6076 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6077 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6078#ifdef CONFIG_X86_64
5fdbf976
MT		 6079 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6080 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6081 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6082 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6083 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6084 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6085 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6086 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6087#endif
6088
5fdbf976 6089 regs->rip = kvm_rip_read(vcpu);
91586a3b 6090 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6091
b6c7a5dc
HB		 6092 return 0;
6093}
6094
6095int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6096{
7ae441ea
GN		 6097 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6098 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6099
5fdbf976
MT		 6100 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6101 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6102 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6103 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6104 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6105 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6106 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6107 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6108#ifdef CONFIG_X86_64
5fdbf976
MT		 6109 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6110 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6111 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6112 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6113 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6114 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6115 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6116 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6117#endif
6118
5fdbf976 6119 kvm_rip_write(vcpu, regs->rip);
91586a3b 6120 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6121
b4f14abd
JK		 6122 vcpu->arch.exception.pending = false;
6123
3842d135
AK		 6124 kvm_make_request(KVM_REQ_EVENT, vcpu);
6125
b6c7a5dc
HB		 6126 return 0;
6127}
6128
b6c7a5dc
HB		 6129void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6130{
6131 struct kvm_segment cs;
6132
3e6e0aab 6133 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6134 *db = cs.db;
6135 *l = cs.l;
6136}
6137EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6138
6139int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6140 struct kvm_sregs *sregs)
6141{
89a27f4d 6142 struct desc_ptr dt;
b6c7a5dc 6143
3e6e0aab
GT		 6144 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6145 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6146 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6147 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6148 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6149 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6150
3e6e0aab
GT		 6151 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6152 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6153
6154 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6155 sregs->idt.limit = dt.size;
6156 sregs->idt.base = dt.address;
b6c7a5dc 6157 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6158 sregs->gdt.limit = dt.size;
6159 sregs->gdt.base = dt.address;
b6c7a5dc 6160
4d4ec087 6161 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6162 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6163 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6164 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6165 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6166 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6167 sregs->apic_base = kvm_get_apic_base(vcpu);
6168
923c61bb 6169 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6170
36752c9b 6171 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6172 set_bit(vcpu->arch.interrupt.nr,
6173 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6174
b6c7a5dc
HB		 6175 return 0;
6176}
6177
62d9f0db
MT		 6178int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6179 struct kvm_mp_state *mp_state)
6180{
62d9f0db 6181 mp_state->mp_state = vcpu->arch.mp_state;
62d9f0db
MT		 6182 return 0;
6183}
6184
6185int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6186 struct kvm_mp_state *mp_state)
6187{
62d9f0db 6188 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6189 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6190 return 0;
6191}
6192
7f3d35fd
KW		 6193int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6194 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6195{
9d74191a 6196 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6197 int ret;
e01c2426 6198
8ec4722d 6199 init_emulate_ctxt(vcpu);
c697518a 6200
7f3d35fd 6201 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6202 has_error_code, error_code);
c697518a 6203
c697518a 6204 if (ret)
19d04437 6205 return EMULATE_FAIL;
37817f29 6206
9d74191a
TY		 6207 kvm_rip_write(vcpu, ctxt->eip);
6208 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6209 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6210 return EMULATE_DONE;
37817f29
IE		 6211}
6212EXPORT_SYMBOL_GPL(kvm_task_switch);
6213
b6c7a5dc
HB		 6214int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6215 struct kvm_sregs *sregs)
6216{
6217 int mmu_reset_needed = 0;
63f42e02 6218 int pending_vec, max_bits, idx;
89a27f4d 6219 struct desc_ptr dt;
b6c7a5dc 6220
6d1068b3
PM		 6221 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6222 return -EINVAL;
6223
89a27f4d
GN		 6224 dt.size = sregs->idt.limit;
6225 dt.address = sregs->idt.base;
b6c7a5dc 6226 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6227 dt.size = sregs->gdt.limit;
6228 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6229 kvm_x86_ops->set_gdt(vcpu, &dt);
6230
ad312c7c 6231 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6232 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6233 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6234 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6235
2d3ad1f4 6236 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6237
f6801dff 6238 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6239 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 6240 kvm_set_apic_base(vcpu, sregs->apic_base);
6241
4d4ec087 6242 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6243 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6244 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6245
fc78f519 6246 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6247 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6248 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6249 kvm_update_cpuid(vcpu);
63f42e02
XG		 6250
6251 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6252 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6253 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6254 mmu_reset_needed = 1;
6255 }
63f42e02 6256 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6257
6258 if (mmu_reset_needed)
6259 kvm_mmu_reset_context(vcpu);
6260
a50abc3b 6261 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6262 pending_vec = find_first_bit(
6263 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6264 if (pending_vec < max_bits) {
66fd3f7f 6265 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6266 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6267 }
6268
3e6e0aab
GT		 6269 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6270 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6271 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6272 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6273 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6274 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6275
3e6e0aab
GT		 6276 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6277 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6278
5f0269f5
ME		 6279 update_cr8_intercept(vcpu);
6280
9c3e4aab 6281 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6282 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6283 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6284 !is_protmode(vcpu))
9c3e4aab
MT		 6285 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6286
3842d135
AK		 6287 kvm_make_request(KVM_REQ_EVENT, vcpu);
6288
b6c7a5dc
HB		 6289 return 0;
6290}
6291
d0bfb940
JK		 6292int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6293 struct kvm_guest_debug *dbg)
b6c7a5dc 6294{
355be0b9 6295 unsigned long rflags;
ae675ef0 6296 int i, r;
b6c7a5dc 6297
4f926bf2
JK		 6298 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6299 r = -EBUSY;
6300 if (vcpu->arch.exception.pending)
2122ff5e 6301 goto out;
4f926bf2
JK		 6302 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6303 kvm_queue_exception(vcpu, DB_VECTOR);
6304 else
6305 kvm_queue_exception(vcpu, BP_VECTOR);
6306 }
6307
91586a3b
JK		 6308 /*
6309 * Read rflags as long as potentially injected trace flags are still
6310 * filtered out.
6311 */
6312 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6313
6314 vcpu->guest_debug = dbg->control;
6315 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6316 vcpu->guest_debug = 0;
6317
6318 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6319 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6320 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6321 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6322 } else {
6323 for (i = 0; i < KVM_NR_DB_REGS; i++)
6324 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6325 }
c8639010 6326 kvm_update_dr7(vcpu);
ae675ef0 6327
f92653ee
JK		 6328 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6329 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6330 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6331
91586a3b
JK		 6332 /*
6333 * Trigger an rflags update that will inject or remove the trace
6334 * flags.
6335 */
6336 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6337
c8639010 6338 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6339
4f926bf2 6340 r = 0;
d0bfb940 6341
2122ff5e 6342out:
b6c7a5dc
HB		 6343
6344 return r;
6345}
6346
8b006791
ZX		 6347/*
6348 * Translate a guest virtual address to a guest physical address.
6349 */
6350int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6351 struct kvm_translation *tr)
6352{
6353 unsigned long vaddr = tr->linear_address;
6354 gpa_t gpa;
f656ce01 6355 int idx;
8b006791 6356
f656ce01 6357 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6358 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6359 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6360 tr->physical_address = gpa;
6361 tr->valid = gpa != UNMAPPED_GVA;
6362 tr->writeable = 1;
6363 tr->usermode = 0;
8b006791
ZX		 6364
6365 return 0;
6366}
6367
d0752060
HB		 6368int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6369{
98918833
SY		 6370 struct i387_fxsave_struct *fxsave =
6371 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6372
d0752060
HB		 6373 memcpy(fpu->fpr, fxsave->st_space, 128);
6374 fpu->fcw = fxsave->cwd;
6375 fpu->fsw = fxsave->swd;
6376 fpu->ftwx = fxsave->twd;
6377 fpu->last_opcode = fxsave->fop;
6378 fpu->last_ip = fxsave->rip;
6379 fpu->last_dp = fxsave->rdp;
6380 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6381
d0752060
HB		 6382 return 0;
6383}
6384
6385int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6386{
98918833
SY		 6387 struct i387_fxsave_struct *fxsave =
6388 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6389
d0752060
HB		 6390 memcpy(fxsave->st_space, fpu->fpr, 128);
6391 fxsave->cwd = fpu->fcw;
6392 fxsave->swd = fpu->fsw;
6393 fxsave->twd = fpu->ftwx;
6394 fxsave->fop = fpu->last_opcode;
6395 fxsave->rip = fpu->last_ip;
6396 fxsave->rdp = fpu->last_dp;
6397 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6398
d0752060
HB		 6399 return 0;
6400}
6401
10ab25cd 6402int fx_init(struct kvm_vcpu *vcpu)
d0752060 6403{
10ab25cd
JK		 6404 int err;
6405
6406 err = fpu_alloc(&vcpu->arch.guest_fpu);
6407 if (err)
6408 return err;
6409
98918833 6410 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6411
2acf923e
DC		 6412 /*
6413 * Ensure guest xcr0 is valid for loading
6414 */
6415 vcpu->arch.xcr0 = XSTATE_FP;
6416
ad312c7c 6417 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6418
6419 return 0;
d0752060
HB		 6420}
6421EXPORT_SYMBOL_GPL(fx_init);
6422
98918833
SY		 6423static void fx_free(struct kvm_vcpu *vcpu)
6424{
6425 fpu_free(&vcpu->arch.guest_fpu);
6426}
6427
d0752060
HB		 6428void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6429{
2608d7a1 6430 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6431 return;
6432
2acf923e
DC		 6433 /*
6434 * Restore all possible states in the guest,
6435 * and assume host would use all available bits.
6436 * Guest xcr0 would be loaded later.
6437 */
6438 kvm_put_guest_xcr0(vcpu);
d0752060 6439 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6440 __kernel_fpu_begin();
98918833 6441 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6442 trace_kvm_fpu(1);
d0752060 6443}
d0752060
HB		 6444
6445void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6446{
2acf923e
DC		 6447 kvm_put_guest_xcr0(vcpu);
6448
d0752060
HB		 6449 if (!vcpu->guest_fpu_loaded)
6450 return;
6451
6452 vcpu->guest_fpu_loaded = 0;
98918833 6453 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6454 __kernel_fpu_end();
f096ed85 6455 ++vcpu->stat.fpu_reload;
a8eeb04a 6456 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6457 trace_kvm_fpu(0);
d0752060 6458}
e9b11c17
ZX		 6459
6460void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6461{
12f9a48f 6462 kvmclock_reset(vcpu);
7f1ea208 6463
f5f48ee1 6464 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6465 fx_free(vcpu);
e9b11c17
ZX		 6466 kvm_x86_ops->vcpu_free(vcpu);
6467}
6468
6469struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6470 unsigned int id)
6471{
6755bae8
ZA		 6472 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6473 printk_once(KERN_WARNING
6474 "kvm: SMP vm created on host with unstable TSC; "
6475 "guest TSC will not be reliable\n");
26e5215f
AK		 6476 return kvm_x86_ops->vcpu_create(kvm, id);
6477}
e9b11c17 6478
26e5215f
AK		 6479int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6480{
6481 int r;
e9b11c17 6482
0bed3b56 6483 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6484 r = vcpu_load(vcpu);
6485 if (r)
6486 return r;
57f252f2
JK		 6487 kvm_vcpu_reset(vcpu);
6488 r = kvm_mmu_setup(vcpu);
e9b11c17 6489 vcpu_put(vcpu);
e9b11c17 6490
26e5215f 6491 return r;
e9b11c17
ZX		 6492}
6493
42897d86
MT		 6494int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6495{
6496 int r;
8fe8ab46 6497 struct msr_data msr;
42897d86
MT		 6498
6499 r = vcpu_load(vcpu);
6500 if (r)
6501 return r;
8fe8ab46
WA		 6502 msr.data = 0x0;
6503 msr.index = MSR_IA32_TSC;
6504 msr.host_initiated = true;
6505 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6506 vcpu_put(vcpu);
6507
6508 return r;
6509}
6510
d40ccc62 6511void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6512{
9fc77441 6513 int r;
344d9588
GN		 6514 vcpu->arch.apf.msr_val = 0;
6515
9fc77441
MT		 6516 r = vcpu_load(vcpu);
6517 BUG_ON(r);
e9b11c17
ZX		 6518 kvm_mmu_unload(vcpu);
6519 vcpu_put(vcpu);
6520
98918833 6521 fx_free(vcpu);
e9b11c17
ZX		 6522 kvm_x86_ops->vcpu_free(vcpu);
6523}
6524
57f252f2 6525static void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6526{
7460fb4a
AK		 6527 atomic_set(&vcpu->arch.nmi_queued, 0);
6528 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6529 vcpu->arch.nmi_injected = false;
6530
42dbaa5a
JK		 6531 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6532 vcpu->arch.dr6 = DR6_FIXED_1;
6533 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6534 kvm_update_dr7(vcpu);
42dbaa5a 6535
3842d135 6536 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6537 vcpu->arch.apf.msr_val = 0;
c9aaa895 6538 vcpu->arch.st.msr_val = 0;
3842d135 6539
12f9a48f
GC		 6540 kvmclock_reset(vcpu);
6541
af585b92
GN		 6542 kvm_clear_async_pf_completion_queue(vcpu);
6543 kvm_async_pf_hash_reset(vcpu);
6544 vcpu->arch.apf.halted = false;
3842d135 6545
f5132b01
GN		 6546 kvm_pmu_reset(vcpu);
6547
66f7b72e
JS		 6548 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6549 vcpu->arch.regs_avail = ~0;
6550 vcpu->arch.regs_dirty = ~0;
6551
57f252f2 6552 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 6553}
6554
10474ae8 6555int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6556{
ca84d1a2
ZA		 6557 struct kvm *kvm;
6558 struct kvm_vcpu *vcpu;
6559 int i;
0dd6a6ed
ZA		 6560 int ret;
6561 u64 local_tsc;
6562 u64 max_tsc = 0;
6563 bool stable, backwards_tsc = false;
18863bdd
AK		 6564
6565 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6566 ret = kvm_x86_ops->hardware_enable(garbage);
6567 if (ret != 0)
6568 return ret;
6569
6570 local_tsc = native_read_tsc();
6571 stable = !check_tsc_unstable();
6572 list_for_each_entry(kvm, &vm_list, vm_list) {
6573 kvm_for_each_vcpu(i, vcpu, kvm) {
6574 if (!stable && vcpu->cpu == smp_processor_id())
6575 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6576 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6577 backwards_tsc = true;
6578 if (vcpu->arch.last_host_tsc > max_tsc)
6579 max_tsc = vcpu->arch.last_host_tsc;
6580 }
6581 }
6582 }
6583
6584 /*
6585 * Sometimes, even reliable TSCs go backwards. This happens on
6586 * platforms that reset TSC during suspend or hibernate actions, but
6587 * maintain synchronization. We must compensate. Fortunately, we can
6588 * detect that condition here, which happens early in CPU bringup,
6589 * before any KVM threads can be running. Unfortunately, we can't
6590 * bring the TSCs fully up to date with real time, as we aren't yet far
6591 * enough into CPU bringup that we know how much real time has actually
6592 * elapsed; our helper function, get_kernel_ns() will be using boot
6593 * variables that haven't been updated yet.
6594 *
6595 * So we simply find the maximum observed TSC above, then record the
6596 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6597 * the adjustment will be applied. Note that we accumulate
6598 * adjustments, in case multiple suspend cycles happen before some VCPU
6599 * gets a chance to run again. In the event that no KVM threads get a
6600 * chance to run, we will miss the entire elapsed period, as we'll have
6601 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6602 * loose cycle time. This isn't too big a deal, since the loss will be
6603 * uniform across all VCPUs (not to mention the scenario is extremely
6604 * unlikely). It is possible that a second hibernate recovery happens
6605 * much faster than a first, causing the observed TSC here to be
6606 * smaller; this would require additional padding adjustment, which is
6607 * why we set last_host_tsc to the local tsc observed here.
6608 *
6609 * N.B. - this code below runs only on platforms with reliable TSC,
6610 * as that is the only way backwards_tsc is set above. Also note
6611 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6612 * have the same delta_cyc adjustment applied if backwards_tsc
6613 * is detected. Note further, this adjustment is only done once,
6614 * as we reset last_host_tsc on all VCPUs to stop this from being
6615 * called multiple times (one for each physical CPU bringup).
6616 *
4a969980 6617 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6618 * will be compensated by the logic in vcpu_load, which sets the TSC to
6619 * catchup mode. This will catchup all VCPUs to real time, but cannot
6620 * guarantee that they stay in perfect synchronization.
6621 */
6622 if (backwards_tsc) {
6623 u64 delta_cyc = max_tsc - local_tsc;
6624 list_for_each_entry(kvm, &vm_list, vm_list) {
6625 kvm_for_each_vcpu(i, vcpu, kvm) {
6626 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6627 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 6628 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6629 &vcpu->requests);
0dd6a6ed
ZA		 6630 }
6631
6632 /*
6633 * We have to disable TSC offset matching.. if you were
6634 * booting a VM while issuing an S4 host suspend....
6635 * you may have some problem. Solving this issue is
6636 * left as an exercise to the reader.
6637 */
6638 kvm->arch.last_tsc_nsec = 0;
6639 kvm->arch.last_tsc_write = 0;
6640 }
6641
6642 }
6643 return 0;
e9b11c17
ZX		 6644}
6645
6646void kvm_arch_hardware_disable(void *garbage)
6647{
6648 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6649 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6650}
6651
6652int kvm_arch_hardware_setup(void)
6653{
6654 return kvm_x86_ops->hardware_setup();
6655}
6656
6657void kvm_arch_hardware_unsetup(void)
6658{
6659 kvm_x86_ops->hardware_unsetup();
6660}
6661
6662void kvm_arch_check_processor_compat(void *rtn)
6663{
6664 kvm_x86_ops->check_processor_compatibility(rtn);
6665}
6666
3e515705
AK		 6667bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6668{
6669 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6670}
6671
54e9818f
GN		 6672struct static_key kvm_no_apic_vcpu __read_mostly;
6673
e9b11c17
ZX		 6674int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6675{
6676 struct page *page;
6677 struct kvm *kvm;
6678 int r;
6679
6680 BUG_ON(vcpu->kvm == NULL);
6681 kvm = vcpu->kvm;
6682
9aabc88f 6683 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6684 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6685 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6686 else
a4535290 6687 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6688
6689 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6690 if (!page) {
6691 r = -ENOMEM;
6692 goto fail;
6693 }
ad312c7c 6694 vcpu->arch.pio_data = page_address(page);
e9b11c17 6695
cc578287 6696 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6697
e9b11c17
ZX		 6698 r = kvm_mmu_create(vcpu);
6699 if (r < 0)
6700 goto fail_free_pio_data;
6701
6702 if (irqchip_in_kernel(kvm)) {
6703 r = kvm_create_lapic(vcpu);
6704 if (r < 0)
6705 goto fail_mmu_destroy;
54e9818f
GN		 6706 } else
6707 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 6708
890ca9ae
HY		 6709 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6710 GFP_KERNEL);
6711 if (!vcpu->arch.mce_banks) {
6712 r = -ENOMEM;
443c39bc 6713 goto fail_free_lapic;
890ca9ae
HY		 6714 }
6715 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6716
f5f48ee1
SY		 6717 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL))
6718 goto fail_free_mce_banks;
6719
66f7b72e
JS		 6720 r = fx_init(vcpu);
6721 if (r)
6722 goto fail_free_wbinvd_dirty_mask;
6723
ba904635 6724 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
af585b92 6725 kvm_async_pf_hash_reset(vcpu);
f5132b01 6726 kvm_pmu_init(vcpu);
af585b92 6727
e9b11c17 6728 return 0;
66f7b72e
JS		 6729fail_free_wbinvd_dirty_mask:
6730 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 6731fail_free_mce_banks:
6732 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6733fail_free_lapic:
6734 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6735fail_mmu_destroy:
6736 kvm_mmu_destroy(vcpu);
6737fail_free_pio_data:
ad312c7c 6738 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6739fail:
6740 return r;
6741}
6742
6743void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6744{
f656ce01
MT		 6745 int idx;
6746
f5132b01 6747 kvm_pmu_destroy(vcpu);
36cb93fd 6748 kfree(vcpu->arch.mce_banks);
e9b11c17 6749 kvm_free_lapic(vcpu);
f656ce01 6750 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6751 kvm_mmu_destroy(vcpu);
f656ce01 6752 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6753 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 6754 if (!irqchip_in_kernel(vcpu->kvm))
6755 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 6756}
d19a9cd2 6757
e08b9637 6758int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 6759{
e08b9637
CO		 6760 if (type)
6761 return -EINVAL;
6762
f05e70ac 6763 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 6764 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6765
5550af4d
SY		 6766 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
6767 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 6768 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
6769 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
6770 &kvm->arch.irq_sources_bitmap);
5550af4d 6771
038f8c11 6772 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 6773 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 6774 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
6775
6776 pvclock_update_vm_gtod_copy(kvm);
53f658b3 6777
d89f5eff 6778 return 0;
d19a9cd2
ZX		 6779}
6780
6781static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
6782{
9fc77441
MT		 6783 int r;
6784 r = vcpu_load(vcpu);
6785 BUG_ON(r);
d19a9cd2
ZX		 6786 kvm_mmu_unload(vcpu);
6787 vcpu_put(vcpu);
6788}
6789
6790static void kvm_free_vcpus(struct kvm *kvm)
6791{
6792 unsigned int i;
988a2cae 6793 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 6794
6795 /*
6796 * Unpin any mmu pages first.
6797 */
af585b92
GN		 6798 kvm_for_each_vcpu(i, vcpu, kvm) {
6799 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 6800 kvm_unload_vcpu_mmu(vcpu);
af585b92 6801 }
988a2cae
GN		 6802 kvm_for_each_vcpu(i, vcpu, kvm)
6803 kvm_arch_vcpu_free(vcpu);
6804
6805 mutex_lock(&kvm->lock);
6806 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
6807 kvm->vcpus[i] = NULL;
d19a9cd2 6808
988a2cae
GN		 6809 atomic_set(&kvm->online_vcpus, 0);
6810 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 6811}
6812
ad8ba2cd
SY		 6813void kvm_arch_sync_events(struct kvm *kvm)
6814{
ba4cef31 6815 kvm_free_all_assigned_devices(kvm);
aea924f6 6816 kvm_free_pit(kvm);
ad8ba2cd
SY		 6817}
6818
d19a9cd2
ZX		 6819void kvm_arch_destroy_vm(struct kvm *kvm)
6820{
6eb55818 6821 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 6822 kfree(kvm->arch.vpic);
6823 kfree(kvm->arch.vioapic);
d19a9cd2 6824 kvm_free_vcpus(kvm);
3d45830c
AK		 6825 if (kvm->arch.apic_access_page)
6826 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 6827 if (kvm->arch.ept_identity_pagetable)
6828 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 6829 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 6830}
0de10343 6831
db3fe4eb
TY		 6832void kvm_arch_free_memslot(struct kvm_memory_slot *free,
6833 struct kvm_memory_slot *dont)
6834{
6835 int i;
6836
d89cc617
TY		 6837 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6838 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
6839 kvm_kvfree(free->arch.rmap[i]);
6840 free->arch.rmap[i] = NULL;
77d11309 6841 }
d89cc617
TY		 6842 if (i == 0)
6843 continue;
6844
6845 if (!dont || free->arch.lpage_info[i - 1] !=
6846 dont->arch.lpage_info[i - 1]) {
6847 kvm_kvfree(free->arch.lpage_info[i - 1]);
6848 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 6849 }
6850 }
6851}
6852
6853int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
6854{
6855 int i;
6856
d89cc617 6857 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 6858 unsigned long ugfn;
6859 int lpages;
d89cc617 6860 int level = i + 1;
db3fe4eb
TY		 6861
6862 lpages = gfn_to_index(slot->base_gfn + npages - 1,
6863 slot->base_gfn, level) + 1;
6864
d89cc617
TY		 6865 slot->arch.rmap[i] =
6866 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
6867 if (!slot->arch.rmap[i])
77d11309 6868 goto out_free;
d89cc617
TY		 6869 if (i == 0)
6870 continue;
77d11309 6871
d89cc617
TY		 6872 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
6873 sizeof(*slot->arch.lpage_info[i - 1]));
6874 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 6875 goto out_free;
6876
6877 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 6878 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 6879 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 6880 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 6881 ugfn = slot->userspace_addr >> PAGE_SHIFT;
6882 /*
6883 * If the gfn and userspace address are not aligned wrt each
6884 * other, or if explicitly asked to, disable large page
6885 * support for this slot
6886 */
6887 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
6888 !kvm_largepages_enabled()) {
6889 unsigned long j;
6890
6891 for (j = 0; j < lpages; ++j)
d89cc617 6892 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 6893 }
6894 }
6895
6896 return 0;
6897
6898out_free:
d89cc617
TY		 6899 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
6900 kvm_kvfree(slot->arch.rmap[i]);
6901 slot->arch.rmap[i] = NULL;
6902 if (i == 0)
6903 continue;
6904
6905 kvm_kvfree(slot->arch.lpage_info[i - 1]);
6906 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 6907 }
6908 return -ENOMEM;
6909}
6910
f7784b8e
MT		 6911int kvm_arch_prepare_memory_region(struct kvm *kvm,
6912 struct kvm_memory_slot *memslot,
7b6195a9
TY		 6913 struct kvm_userspace_memory_region *mem,
6914 enum kvm_mr_change change)
0de10343 6915{
7a905b14
TY		 6916 /*
6917 * Only private memory slots need to be mapped here since
6918 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 6919 */
7b6195a9 6920 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 6921 unsigned long userspace_addr;
604b38ac 6922
7a905b14
TY		 6923 /*
6924 * MAP_SHARED to prevent internal slot pages from being moved
6925 * by fork()/COW.
6926 */
7b6195a9 6927 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 6928 PROT_READ | PROT_WRITE,
6929 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 6930
7a905b14
TY		 6931 if (IS_ERR((void *)userspace_addr))
6932 return PTR_ERR((void *)userspace_addr);
604b38ac 6933
7a905b14 6934 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 6935 }
6936
f7784b8e
MT		 6937 return 0;
6938}
6939
6940void kvm_arch_commit_memory_region(struct kvm *kvm,
6941 struct kvm_userspace_memory_region *mem,
8482644a
TY		 6942 const struct kvm_memory_slot *old,
6943 enum kvm_mr_change change)
f7784b8e
MT		 6944{
6945
8482644a 6946 int nr_mmu_pages = 0;
f7784b8e 6947
8482644a 6948 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 6949 int ret;
6950
8482644a
TY		 6951 ret = vm_munmap(old->userspace_addr,
6952 old->npages * PAGE_SIZE);
f7784b8e
MT		 6953 if (ret < 0)
6954 printk(KERN_WARNING
6955 "kvm_vm_ioctl_set_memory_region: "
6956 "failed to munmap memory\n");
6957 }
6958
48c0e4e9
XG		 6959 if (!kvm->arch.n_requested_mmu_pages)
6960 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
6961
48c0e4e9 6962 if (nr_mmu_pages)
0de10343 6963 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 6964 /*
6965 * Write protect all pages for dirty logging.
6966 * Existing largepage mappings are destroyed here and new ones will
6967 * not be created until the end of the logging.
6968 */
8482644a 6969 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 6970 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
3b4dc3a0
MT		 6971 /*
6972 * If memory slot is created, or moved, we need to clear all
6973 * mmio sptes.
6974 */
8482644a 6975 if ((change == KVM_MR_CREATE) || (change == KVM_MR_MOVE)) {
3b4dc3a0
MT		 6976 kvm_mmu_zap_all(kvm);
6977 kvm_reload_remote_mmus(kvm);
6978 }
0de10343 6979}
1d737c8a 6980
2df72e9b 6981void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f
MT		 6982{
6983 kvm_mmu_zap_all(kvm);
8986ecc0 6984 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 6985}
6986
2df72e9b
MT		 6987void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
6988 struct kvm_memory_slot *slot)
6989{
6990 kvm_arch_flush_shadow_all(kvm);
6991}
6992
1d737c8a
ZX		 6993int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
6994{
af585b92
GN		 6995 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6996 !vcpu->arch.apf.halted)
6997 || !list_empty_careful(&vcpu->async_pf.done)
a1b37100 6998 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
7460fb4a 6999 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7000 (kvm_arch_interrupt_allowed(vcpu) &&
7001 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7002}
5736199a 7003
b6d33834 7004int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7005{
b6d33834 7006 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7007}
78646121
GN		 7008
7009int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7010{
7011 return kvm_x86_ops->interrupt_allowed(vcpu);
7012}
229456fc 7013
f92653ee
JK		 7014bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7015{
7016 unsigned long current_rip = kvm_rip_read(vcpu) +
7017 get_segment_base(vcpu, VCPU_SREG_CS);
7018
7019 return current_rip == linear_rip;
7020}
7021EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7022
94fe45da
JK		 7023unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7024{
7025 unsigned long rflags;
7026
7027 rflags = kvm_x86_ops->get_rflags(vcpu);
7028 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7029 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7030 return rflags;
7031}
7032EXPORT_SYMBOL_GPL(kvm_get_rflags);
7033
7034void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7035{
7036 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7037 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7038 rflags |= X86_EFLAGS_TF;
94fe45da 7039 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 7040 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7041}
7042EXPORT_SYMBOL_GPL(kvm_set_rflags);
7043
56028d08
GN		 7044void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7045{
7046 int r;
7047
fb67e14f 7048 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 7049 is_error_page(work->page))
56028d08
GN		 7050 return;
7051
7052 r = kvm_mmu_reload(vcpu);
7053 if (unlikely(r))
7054 return;
7055
fb67e14f
XG		 7056 if (!vcpu->arch.mmu.direct_map &&
7057 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7058 return;
7059
56028d08
GN		 7060 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7061}
7062
af585b92
GN		 7063static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7064{
7065 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7066}
7067
7068static inline u32 kvm_async_pf_next_probe(u32 key)
7069{
7070 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7071}
7072
7073static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7074{
7075 u32 key = kvm_async_pf_hash_fn(gfn);
7076
7077 while (vcpu->arch.apf.gfns[key] != ~0)
7078 key = kvm_async_pf_next_probe(key);
7079
7080 vcpu->arch.apf.gfns[key] = gfn;
7081}
7082
7083static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7084{
7085 int i;
7086 u32 key = kvm_async_pf_hash_fn(gfn);
7087
7088 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7089 (vcpu->arch.apf.gfns[key] != gfn &&
7090 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7091 key = kvm_async_pf_next_probe(key);
7092
7093 return key;
7094}
7095
7096bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7097{
7098 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7099}
7100
7101static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7102{
7103 u32 i, j, k;
7104
7105 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7106 while (true) {
7107 vcpu->arch.apf.gfns[i] = ~0;
7108 do {
7109 j = kvm_async_pf_next_probe(j);
7110 if (vcpu->arch.apf.gfns[j] == ~0)
7111 return;
7112 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7113 /*
7114 * k lies cyclically in ]i,j]
7115 * | i.k.j |
7116 * |....j i.k.| or |.k..j i...|
7117 */
7118 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7119 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7120 i = j;
7121 }
7122}
7123
7c90705b
GN		 7124static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7125{
7126
7127 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7128 sizeof(val));
7129}
7130
af585b92
GN		 7131void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7132 struct kvm_async_pf *work)
7133{
6389ee94
AK		 7134 struct x86_exception fault;
7135
7c90705b 7136 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7137 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7138
7139 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7140 (vcpu->arch.apf.send_user_only &&
7141 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7142 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7143 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7144 fault.vector = PF_VECTOR;
7145 fault.error_code_valid = true;
7146 fault.error_code = 0;
7147 fault.nested_page_fault = false;
7148 fault.address = work->arch.token;
7149 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7150 }
af585b92
GN		 7151}
7152
7153void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7154 struct kvm_async_pf *work)
7155{
6389ee94
AK		 7156 struct x86_exception fault;
7157
7c90705b
GN		 7158 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7159 if (is_error_page(work->page))
7160 work->arch.token = ~0; /* broadcast wakeup */
7161 else
7162 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7163
7164 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7165 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7166 fault.vector = PF_VECTOR;
7167 fault.error_code_valid = true;
7168 fault.error_code = 0;
7169 fault.nested_page_fault = false;
7170 fault.address = work->arch.token;
7171 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7172 }
e6d53e3b 7173 vcpu->arch.apf.halted = false;
a4fa1635 7174 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7175}
7176
7177bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7178{
7179 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7180 return true;
7181 else
7182 return !kvm_event_needs_reinjection(vcpu) &&
7183 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7184}
7185
229456fc
MT		 7186EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7187EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7188EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7189EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7190EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7191EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7192EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7193EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7194EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7195EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7196EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7197EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
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