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KVM/s390: Set preempted flag during vcpu wakeup and interrupt delivery
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 90
97896d04 91struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 92EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 93
476bc001
RR		 94static bool ignore_msrs = 0;
95module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 96
9ed96e87
MT		 97unsigned int min_timer_period_us = 500;
98module_param(min_timer_period_us, uint, S_IRUGO | S_IWUSR);
99
92a1f12d
JR		 100bool kvm_has_tsc_control;
101EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
102u32 kvm_max_guest_tsc_khz;
103EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
104
cc578287
ZA		 105/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
106static u32 tsc_tolerance_ppm = 250;
107module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
108
18863bdd
AK		 109#define KVM_NR_SHARED_MSRS 16
110
111struct kvm_shared_msrs_global {
112 int nr;
2bf78fa7 113 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 114};
115
116struct kvm_shared_msrs {
117 struct user_return_notifier urn;
118 bool registered;
2bf78fa7
SY		 119 struct kvm_shared_msr_values {
120 u64 host;
121 u64 curr;
122 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 123};
124
125static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 126static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 127
417bc304 128struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 129 { "pf_fixed", VCPU_STAT(pf_fixed) },
130 { "pf_guest", VCPU_STAT(pf_guest) },
131 { "tlb_flush", VCPU_STAT(tlb_flush) },
132 { "invlpg", VCPU_STAT(invlpg) },
133 { "exits", VCPU_STAT(exits) },
134 { "io_exits", VCPU_STAT(io_exits) },
135 { "mmio_exits", VCPU_STAT(mmio_exits) },
136 { "signal_exits", VCPU_STAT(signal_exits) },
137 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 138 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 139 { "halt_exits", VCPU_STAT(halt_exits) },
140 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 141 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 142 { "request_irq", VCPU_STAT(request_irq_exits) },
143 { "irq_exits", VCPU_STAT(irq_exits) },
144 { "host_state_reload", VCPU_STAT(host_state_reload) },
145 { "efer_reload", VCPU_STAT(efer_reload) },
146 { "fpu_reload", VCPU_STAT(fpu_reload) },
147 { "insn_emulation", VCPU_STAT(insn_emulation) },
148 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 149 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 150 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 151 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
152 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
153 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
154 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
155 { "mmu_flooded", VM_STAT(mmu_flooded) },
156 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 157 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 158 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 159 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 160 { "largepages", VM_STAT(lpages) },
417bc304
HB		 161 { NULL }
162};
163
2acf923e
DC		 164u64 __read_mostly host_xcr0;
165
b6785def 166static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 167
af585b92
GN		 168static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
169{
170 int i;
171 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
172 vcpu->arch.apf.gfns[i] = ~0;
173}
174
18863bdd
AK		 175static void kvm_on_user_return(struct user_return_notifier *urn)
176{
177 unsigned slot;
18863bdd
AK		 178 struct kvm_shared_msrs *locals
179 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 180 struct kvm_shared_msr_values *values;
18863bdd
AK		 181
182 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 183 values = &locals->values[slot];
184 if (values->host != values->curr) {
185 wrmsrl(shared_msrs_global.msrs[slot], values->host);
186 values->curr = values->host;
18863bdd
AK		 187 }
188 }
189 locals->registered = false;
190 user_return_notifier_unregister(urn);
191}
192
2bf78fa7 193static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 194{
18863bdd 195 u64 value;
013f6a5d
MT		 196 unsigned int cpu = smp_processor_id();
197 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 198
2bf78fa7
SY		 199 /* only read, and nobody should modify it at this time,
200 * so don't need lock */
201 if (slot >= shared_msrs_global.nr) {
202 printk(KERN_ERR "kvm: invalid MSR slot!");
203 return;
204 }
205 rdmsrl_safe(msr, &value);
206 smsr->values[slot].host = value;
207 smsr->values[slot].curr = value;
208}
209
210void kvm_define_shared_msr(unsigned slot, u32 msr)
211{
18863bdd
AK		 212 if (slot >= shared_msrs_global.nr)
213 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 214 shared_msrs_global.msrs[slot] = msr;
215 /* we need ensured the shared_msr_global have been updated */
216 smp_wmb();
18863bdd
AK		 217}
218EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
219
220static void kvm_shared_msr_cpu_online(void)
221{
222 unsigned i;
18863bdd
AK		 223
224 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 225 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 226}
227
d5696725 228void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 229{
013f6a5d
MT		 230 unsigned int cpu = smp_processor_id();
231 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 232
2bf78fa7 233 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 234 return;
2bf78fa7
SY		 235 smsr->values[slot].curr = value;
236 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 237 if (!smsr->registered) {
238 smsr->urn.on_user_return = kvm_on_user_return;
239 user_return_notifier_register(&smsr->urn);
240 smsr->registered = true;
241 }
242}
243EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
244
3548bab5
AK		 245static void drop_user_return_notifiers(void *ignore)
246{
013f6a5d
MT		 247 unsigned int cpu = smp_processor_id();
248 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 249
250 if (smsr->registered)
251 kvm_on_user_return(&smsr->urn);
252}
253
6866b83e
CO		 254u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
255{
8a5a87d9 256 return vcpu->arch.apic_base;
6866b83e
CO		 257}
258EXPORT_SYMBOL_GPL(kvm_get_apic_base);
259
58cb628d
JK		 260int kvm_set_apic_base(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
261{
262 u64 old_state = vcpu->arch.apic_base &
263 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
264 u64 new_state = msr_info->data &
265 (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE);
266 u64 reserved_bits = ((~0ULL) << cpuid_maxphyaddr(vcpu)) |
267 0x2ff | (guest_cpuid_has_x2apic(vcpu) ? 0 : X2APIC_ENABLE);
268
269 if (!msr_info->host_initiated &&
270 ((msr_info->data & reserved_bits) != 0 ||
271 new_state == X2APIC_ENABLE ||
272 (new_state == MSR_IA32_APICBASE_ENABLE &&
273 old_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE)) ||
274 (new_state == (MSR_IA32_APICBASE_ENABLE | X2APIC_ENABLE) &&
275 old_state == 0)))
276 return 1;
277
278 kvm_lapic_set_base(vcpu, msr_info->data);
279 return 0;
6866b83e
CO		 280}
281EXPORT_SYMBOL_GPL(kvm_set_apic_base);
282
e3ba45b8
GL		 283asmlinkage void kvm_spurious_fault(void)
284{
285 /* Fault while not rebooting. We want the trace. */
286 BUG();
287}
288EXPORT_SYMBOL_GPL(kvm_spurious_fault);
289
3fd28fce
ED		 290#define EXCPT_BENIGN 0
291#define EXCPT_CONTRIBUTORY 1
292#define EXCPT_PF 2
293
294static int exception_class(int vector)
295{
296 switch (vector) {
297 case PF_VECTOR:
298 return EXCPT_PF;
299 case DE_VECTOR:
300 case TS_VECTOR:
301 case NP_VECTOR:
302 case SS_VECTOR:
303 case GP_VECTOR:
304 return EXCPT_CONTRIBUTORY;
305 default:
306 break;
307 }
308 return EXCPT_BENIGN;
309}
310
311static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 312 unsigned nr, bool has_error, u32 error_code,
313 bool reinject)
3fd28fce
ED		 314{
315 u32 prev_nr;
316 int class1, class2;
317
3842d135
AK		 318 kvm_make_request(KVM_REQ_EVENT, vcpu);
319
3fd28fce
ED		 320 if (!vcpu->arch.exception.pending) {
321 queue:
322 vcpu->arch.exception.pending = true;
323 vcpu->arch.exception.has_error_code = has_error;
324 vcpu->arch.exception.nr = nr;
325 vcpu->arch.exception.error_code = error_code;
3f0fd292 326 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 327 return;
328 }
329
330 /* to check exception */
331 prev_nr = vcpu->arch.exception.nr;
332 if (prev_nr == DF_VECTOR) {
333 /* triple fault -> shutdown */
a8eeb04a 334 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 335 return;
336 }
337 class1 = exception_class(prev_nr);
338 class2 = exception_class(nr);
339 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
340 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
341 /* generate double fault per SDM Table 5-5 */
342 vcpu->arch.exception.pending = true;
343 vcpu->arch.exception.has_error_code = true;
344 vcpu->arch.exception.nr = DF_VECTOR;
345 vcpu->arch.exception.error_code = 0;
346 } else
347 /* replace previous exception with a new one in a hope
348 that instruction re-execution will regenerate lost
349 exception */
350 goto queue;
351}
352
298101da
AK		 353void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
354{
ce7ddec4 355 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 356}
357EXPORT_SYMBOL_GPL(kvm_queue_exception);
358
ce7ddec4
JR		 359void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
360{
361 kvm_multiple_exception(vcpu, nr, false, 0, true);
362}
363EXPORT_SYMBOL_GPL(kvm_requeue_exception);
364
db8fcefa 365void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 366{
db8fcefa
AP		 367 if (err)
368 kvm_inject_gp(vcpu, 0);
369 else
370 kvm_x86_ops->skip_emulated_instruction(vcpu);
371}
372EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 373
6389ee94 374void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 375{
376 ++vcpu->stat.pf_guest;
6389ee94
AK		 377 vcpu->arch.cr2 = fault->address;
378 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 379}
27d6c865 380EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 381
6389ee94 382void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 383{
6389ee94
AK		 384 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
385 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 386 else
6389ee94 387 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 388}
389
3419ffc8
SY		 390void kvm_inject_nmi(struct kvm_vcpu *vcpu)
391{
7460fb4a
AK		 392 atomic_inc(&vcpu->arch.nmi_queued);
393 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 394}
395EXPORT_SYMBOL_GPL(kvm_inject_nmi);
396
298101da
AK		 397void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
398{
ce7ddec4 399 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 400}
401EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
402
ce7ddec4
JR		 403void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
404{
405 kvm_multiple_exception(vcpu, nr, true, error_code, true);
406}
407EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
408
0a79b009
AK		 409/*
410 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
411 * a #GP and return false.
412 */
413bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 414{
0a79b009
AK		 415 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
416 return true;
417 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
418 return false;
298101da 419}
0a79b009 420EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 421
ec92fe44
JR		 422/*
423 * This function will be used to read from the physical memory of the currently
424 * running guest. The difference to kvm_read_guest_page is that this function
425 * can read from guest physical or from the guest's guest physical memory.
426 */
427int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
428 gfn_t ngfn, void *data, int offset, int len,
429 u32 access)
430{
431 gfn_t real_gfn;
432 gpa_t ngpa;
433
434 ngpa = gfn_to_gpa(ngfn);
435 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
436 if (real_gfn == UNMAPPED_GVA)
437 return -EFAULT;
438
439 real_gfn = gpa_to_gfn(real_gfn);
440
441 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
442}
443EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
444
3d06b8bf
JR		 445int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
446 void *data, int offset, int len, u32 access)
447{
448 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
449 data, offset, len, access);
450}
451
a03490ed
CO		 452/*
453 * Load the pae pdptrs. Return true is they are all valid.
454 */
ff03a073 455int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 456{
457 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
458 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
459 int i;
460 int ret;
ff03a073 461 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 462
ff03a073
JR		 463 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
464 offset * sizeof(u64), sizeof(pdpte),
465 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 466 if (ret < 0) {
467 ret = 0;
468 goto out;
469 }
470 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 471 if (is_present_gpte(pdpte[i]) &&
20c466b5 472 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 473 ret = 0;
474 goto out;
475 }
476 }
477 ret = 1;
478
ff03a073 479 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 480 __set_bit(VCPU_EXREG_PDPTR,
481 (unsigned long *)&vcpu->arch.regs_avail);
482 __set_bit(VCPU_EXREG_PDPTR,
483 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 484out:
a03490ed
CO		 485
486 return ret;
487}
cc4b6871 488EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 489
d835dfec
AK		 490static bool pdptrs_changed(struct kvm_vcpu *vcpu)
491{
ff03a073 492 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 493 bool changed = true;
3d06b8bf
JR		 494 int offset;
495 gfn_t gfn;
d835dfec
AK		 496 int r;
497
498 if (is_long_mode(vcpu) || !is_pae(vcpu))
499 return false;
500
6de4f3ad
AK		 501 if (!test_bit(VCPU_EXREG_PDPTR,
502 (unsigned long *)&vcpu->arch.regs_avail))
503 return true;
504
9f8fe504
AK		 505 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
506 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 507 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
508 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 509 if (r < 0)
510 goto out;
ff03a073 511 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 512out:
d835dfec
AK		 513
514 return changed;
515}
516
49a9b07e 517int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 518{
aad82703
SY		 519 unsigned long old_cr0 = kvm_read_cr0(vcpu);
520 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
521 X86_CR0_CD | X86_CR0_NW;
522
f9a48e6a
AK		 523 cr0 |= X86_CR0_ET;
524
ab344828 525#ifdef CONFIG_X86_64
0f12244f
GN		 526 if (cr0 & 0xffffffff00000000UL)
527 return 1;
ab344828
GN		 528#endif
529
530 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 531
0f12244f
GN		 532 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
533 return 1;
a03490ed 534
0f12244f
GN		 535 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
536 return 1;
a03490ed
CO		 537
538 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
539#ifdef CONFIG_X86_64
f6801dff 540 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 541 int cs_db, cs_l;
542
0f12244f
GN		 543 if (!is_pae(vcpu))
544 return 1;
a03490ed 545 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 546 if (cs_l)
547 return 1;
a03490ed
CO		 548 } else
549#endif
ff03a073 550 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 551 kvm_read_cr3(vcpu)))
0f12244f 552 return 1;
a03490ed
CO		 553 }
554
ad756a16
MJ		 555 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
556 return 1;
557
a03490ed 558 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 559
d170c419 560 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 561 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 562 kvm_async_pf_hash_reset(vcpu);
563 }
e5f3f027 564
aad82703
SY		 565 if ((cr0 ^ old_cr0) & update_bits)
566 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 567 return 0;
568}
2d3ad1f4 569EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 570
2d3ad1f4 571void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 572{
49a9b07e 573 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 574}
2d3ad1f4 575EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 576
42bdf991
MT		 577static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
578{
579 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
580 !vcpu->guest_xcr0_loaded) {
581 /* kvm_set_xcr() also depends on this */
582 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
583 vcpu->guest_xcr0_loaded = 1;
584 }
585}
586
587static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
588{
589 if (vcpu->guest_xcr0_loaded) {
590 if (vcpu->arch.xcr0 != host_xcr0)
591 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
592 vcpu->guest_xcr0_loaded = 0;
593 }
594}
595
2acf923e
DC		 596int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
597{
56c103ec
LJ		 598 u64 xcr0 = xcr;
599 u64 old_xcr0 = vcpu->arch.xcr0;
46c34cb0 600 u64 valid_bits;
2acf923e
DC		 601
602 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
603 if (index != XCR_XFEATURE_ENABLED_MASK)
604 return 1;
2acf923e
DC		 605 if (!(xcr0 & XSTATE_FP))
606 return 1;
607 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
608 return 1;
46c34cb0
PB		 609
610 /*
611 * Do not allow the guest to set bits that we do not support
612 * saving. However, xcr0 bit 0 is always set, even if the
613 * emulated CPU does not support XSAVE (see fx_init).
614 */
615 valid_bits = vcpu->arch.guest_supported_xcr0 | XSTATE_FP;
616 if (xcr0 & ~valid_bits)
2acf923e 617 return 1;
46c34cb0 618
390bd528
LJ		 619 if ((!(xcr0 & XSTATE_BNDREGS)) != (!(xcr0 & XSTATE_BNDCSR)))
620 return 1;
621
42bdf991 622 kvm_put_guest_xcr0(vcpu);
2acf923e 623 vcpu->arch.xcr0 = xcr0;
56c103ec
LJ		 624
625 if ((xcr0 ^ old_xcr0) & XSTATE_EXTEND_MASK)
626 kvm_update_cpuid(vcpu);
2acf923e
DC		 627 return 0;
628}
629
630int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
631{
764bcbc5
Z		 632 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
633 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 634 kvm_inject_gp(vcpu, 0);
635 return 1;
636 }
637 return 0;
638}
639EXPORT_SYMBOL_GPL(kvm_set_xcr);
640
a83b29c6 641int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 642{
fc78f519 643 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 644 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
645 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 646 if (cr4 & CR4_RESERVED_BITS)
647 return 1;
a03490ed 648
2acf923e
DC		 649 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
650 return 1;
651
c68b734f
YW		 652 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
653 return 1;
654
afcbf13f 655 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 656 return 1;
657
a03490ed 658 if (is_long_mode(vcpu)) {
0f12244f
GN		 659 if (!(cr4 & X86_CR4_PAE))
660 return 1;
a2edf57f
AK		 661 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
662 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 663 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
664 kvm_read_cr3(vcpu)))
0f12244f
GN		 665 return 1;
666
ad756a16
MJ		 667 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
668 if (!guest_cpuid_has_pcid(vcpu))
669 return 1;
670
671 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
672 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
673 return 1;
674 }
675
5e1746d6 676 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 677 return 1;
a03490ed 678
ad756a16
MJ		 679 if (((cr4 ^ old_cr4) & pdptr_bits) ||
680 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 681 kvm_mmu_reset_context(vcpu);
0f12244f 682
2acf923e 683 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 684 kvm_update_cpuid(vcpu);
2acf923e 685
0f12244f
GN		 686 return 0;
687}
2d3ad1f4 688EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 689
2390218b 690int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 691{
9f8fe504 692 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 693 kvm_mmu_sync_roots(vcpu);
d835dfec 694 kvm_mmu_flush_tlb(vcpu);
0f12244f 695 return 0;
d835dfec
AK		 696 }
697
a03490ed 698 if (is_long_mode(vcpu)) {
471842ec 699 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
ad756a16
MJ		 700 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
701 return 1;
702 } else
703 if (cr3 & CR3_L_MODE_RESERVED_BITS)
704 return 1;
a03490ed
CO		 705 } else {
706 if (is_pae(vcpu)) {
0f12244f
GN		 707 if (cr3 & CR3_PAE_RESERVED_BITS)
708 return 1;
ff03a073
JR		 709 if (is_paging(vcpu) &&
710 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 711 return 1;
a03490ed
CO		 712 }
713 /*
714 * We don't check reserved bits in nonpae mode, because
715 * this isn't enforced, and VMware depends on this.
716 */
717 }
718
0f12244f 719 vcpu->arch.cr3 = cr3;
aff48baa 720 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 721 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 722 return 0;
723}
2d3ad1f4 724EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 725
eea1cff9 726int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 727{
0f12244f
GN		 728 if (cr8 & CR8_RESERVED_BITS)
729 return 1;
a03490ed
CO		 730 if (irqchip_in_kernel(vcpu->kvm))
731 kvm_lapic_set_tpr(vcpu, cr8);
732 else
ad312c7c 733 vcpu->arch.cr8 = cr8;
0f12244f
GN		 734 return 0;
735}
2d3ad1f4 736EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 737
2d3ad1f4 738unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 739{
740 if (irqchip_in_kernel(vcpu->kvm))
741 return kvm_lapic_get_cr8(vcpu);
742 else
ad312c7c 743 return vcpu->arch.cr8;
a03490ed 744}
2d3ad1f4 745EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 746
73aaf249
JK		 747static void kvm_update_dr6(struct kvm_vcpu *vcpu)
748{
749 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
750 kvm_x86_ops->set_dr6(vcpu, vcpu->arch.dr6);
751}
752
c8639010
JK		 753static void kvm_update_dr7(struct kvm_vcpu *vcpu)
754{
755 unsigned long dr7;
756
757 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
758 dr7 = vcpu->arch.guest_debug_dr7;
759 else
760 dr7 = vcpu->arch.dr7;
761 kvm_x86_ops->set_dr7(vcpu, dr7);
762 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
763}
764
338dbc97 765static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 766{
767 switch (dr) {
768 case 0 ... 3:
769 vcpu->arch.db[dr] = val;
770 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
771 vcpu->arch.eff_db[dr] = val;
772 break;
773 case 4:
338dbc97
GN		 774 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
775 return 1; /* #UD */
020df079
GN		 776 /* fall through */
777 case 6:
338dbc97
GN		 778 if (val & 0xffffffff00000000ULL)
779 return -1; /* #GP */
020df079 780 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
73aaf249 781 kvm_update_dr6(vcpu);
020df079
GN		 782 break;
783 case 5:
338dbc97
GN		 784 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
785 return 1; /* #UD */
020df079
GN		 786 /* fall through */
787 default: /* 7 */
338dbc97
GN		 788 if (val & 0xffffffff00000000ULL)
789 return -1; /* #GP */
020df079 790 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 791 kvm_update_dr7(vcpu);
020df079
GN		 792 break;
793 }
794
795 return 0;
796}
338dbc97
GN		 797
798int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
799{
800 int res;
801
802 res = __kvm_set_dr(vcpu, dr, val);
803 if (res > 0)
804 kvm_queue_exception(vcpu, UD_VECTOR);
805 else if (res < 0)
806 kvm_inject_gp(vcpu, 0);
807
808 return res;
809}
020df079
GN		 810EXPORT_SYMBOL_GPL(kvm_set_dr);
811
338dbc97 812static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 813{
814 switch (dr) {
815 case 0 ... 3:
816 *val = vcpu->arch.db[dr];
817 break;
818 case 4:
338dbc97 819 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 820 return 1;
020df079
GN		 821 /* fall through */
822 case 6:
73aaf249
JK		 823 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
824 *val = vcpu->arch.dr6;
825 else
826 *val = kvm_x86_ops->get_dr6(vcpu);
020df079
GN		 827 break;
828 case 5:
338dbc97 829 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 830 return 1;
020df079
GN		 831 /* fall through */
832 default: /* 7 */
833 *val = vcpu->arch.dr7;
834 break;
835 }
836
837 return 0;
838}
338dbc97
GN		 839
840int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
841{
842 if (_kvm_get_dr(vcpu, dr, val)) {
843 kvm_queue_exception(vcpu, UD_VECTOR);
844 return 1;
845 }
846 return 0;
847}
020df079
GN		 848EXPORT_SYMBOL_GPL(kvm_get_dr);
849
022cd0e8
AK		 850bool kvm_rdpmc(struct kvm_vcpu *vcpu)
851{
852 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
853 u64 data;
854 int err;
855
856 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
857 if (err)
858 return err;
859 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
860 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
861 return err;
862}
863EXPORT_SYMBOL_GPL(kvm_rdpmc);
864
043405e1
CO		 865/*
866 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
867 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
868 *
869 * This list is modified at module load time to reflect the
e3267cbb
GC		 870 * capabilities of the host cpu. This capabilities test skips MSRs that are
871 * kvm-specific. Those are put in the beginning of the list.
043405e1 872 */
e3267cbb 873
e984097b 874#define KVM_SAVE_MSRS_BEGIN 12
043405e1 875static u32 msrs_to_save[] = {
e3267cbb 876 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 877 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 878 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
e984097b 879 HV_X64_MSR_TIME_REF_COUNT, HV_X64_MSR_REFERENCE_TSC,
c9aaa895 880 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 881 MSR_KVM_PV_EOI_EN,
043405e1 882 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 883 MSR_STAR,
043405e1
CO		 884#ifdef CONFIG_X86_64
885 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
886#endif
b3897a49 887 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
0dd376e7 888 MSR_IA32_FEATURE_CONTROL, MSR_IA32_BNDCFGS
043405e1
CO		 889};
890
891static unsigned num_msrs_to_save;
892
f1d24831 893static const u32 emulated_msrs[] = {
ba904635 894 MSR_IA32_TSC_ADJUST,
a3e06bbe 895 MSR_IA32_TSCDEADLINE,
043405e1 896 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 897 MSR_IA32_MCG_STATUS,
898 MSR_IA32_MCG_CTL,
043405e1
CO		 899};
900
384bb783 901bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 902{
b69e8cae 903 if (efer & efer_reserved_bits)
384bb783 904 return false;
15c4a640 905
1b2fd70c
AG		 906 if (efer & EFER_FFXSR) {
907 struct kvm_cpuid_entry2 *feat;
908
909 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 910 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 911 return false;
1b2fd70c
AG		 912 }
913
d8017474
AG		 914 if (efer & EFER_SVME) {
915 struct kvm_cpuid_entry2 *feat;
916
917 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 918 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 919 return false;
d8017474
AG		 920 }
921
384bb783
JK		 922 return true;
923}
924EXPORT_SYMBOL_GPL(kvm_valid_efer);
925
926static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
927{
928 u64 old_efer = vcpu->arch.efer;
929
930 if (!kvm_valid_efer(vcpu, efer))
931 return 1;
932
933 if (is_paging(vcpu)
934 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
935 return 1;
936
15c4a640 937 efer &= ~EFER_LMA;
f6801dff 938 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 939
a3d204e2
SY		 940 kvm_x86_ops->set_efer(vcpu, efer);
941
aad82703
SY		 942 /* Update reserved bits */
943 if ((efer ^ old_efer) & EFER_NX)
944 kvm_mmu_reset_context(vcpu);
945
b69e8cae 946 return 0;
15c4a640
CO		 947}
948
f2b4b7dd
JR		 949void kvm_enable_efer_bits(u64 mask)
950{
951 efer_reserved_bits &= ~mask;
952}
953EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
954
955
15c4a640
CO		 956/*
957 * Writes msr value into into the appropriate "register".
958 * Returns 0 on success, non-0 otherwise.
959 * Assumes vcpu_load() was already called.
960 */
8fe8ab46 961int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 962{
8fe8ab46 963 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 964}
965
313a3dc7
CO		 966/*
967 * Adapt set_msr() to msr_io()'s calling convention
968 */
969static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
970{
8fe8ab46
WA		 971 struct msr_data msr;
972
973 msr.data = *data;
974 msr.index = index;
975 msr.host_initiated = true;
976 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 977}
978
16e8d74d
MT		 979#ifdef CONFIG_X86_64
980struct pvclock_gtod_data {
981 seqcount_t seq;
982
983 struct { /* extract of a clocksource struct */
984 int vclock_mode;
985 cycle_t cycle_last;
986 cycle_t mask;
987 u32 mult;
988 u32 shift;
989 } clock;
990
991 /* open coded 'struct timespec' */
992 u64 monotonic_time_snsec;
993 time_t monotonic_time_sec;
994};
995
996static struct pvclock_gtod_data pvclock_gtod_data;
997
998static void update_pvclock_gtod(struct timekeeper *tk)
999{
1000 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
1001
1002 write_seqcount_begin(&vdata->seq);
1003
1004 /* copy pvclock gtod data */
1005 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
1006 vdata->clock.cycle_last = tk->clock->cycle_last;
1007 vdata->clock.mask = tk->clock->mask;
1008 vdata->clock.mult = tk->mult;
1009 vdata->clock.shift = tk->shift;
1010
1011 vdata->monotonic_time_sec = tk->xtime_sec
1012 + tk->wall_to_monotonic.tv_sec;
1013 vdata->monotonic_time_snsec = tk->xtime_nsec
1014 + (tk->wall_to_monotonic.tv_nsec
1015 << tk->shift);
1016 while (vdata->monotonic_time_snsec >=
1017 (((u64)NSEC_PER_SEC) << tk->shift)) {
1018 vdata->monotonic_time_snsec -=
1019 ((u64)NSEC_PER_SEC) << tk->shift;
1020 vdata->monotonic_time_sec++;
1021 }
1022
1023 write_seqcount_end(&vdata->seq);
1024}
1025#endif
1026
1027
18068523
GOC		 1028static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
1029{
9ed3c444
AK		 1030 int version;
1031 int r;
50d0a0f9 1032 struct pvclock_wall_clock wc;
923de3cf 1033 struct timespec boot;
18068523
GOC		 1034
1035 if (!wall_clock)
1036 return;
1037
9ed3c444
AK		 1038 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
1039 if (r)
1040 return;
1041
1042 if (version & 1)
1043 ++version; /* first time write, random junk */
1044
1045 ++version;
18068523 1046
18068523
GOC		 1047 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1048
50d0a0f9
GH		 1049 /*
1050 * The guest calculates current wall clock time by adding
34c238a1 1051 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1052 * wall clock specified here. guest system time equals host
1053 * system time for us, thus we must fill in host boot time here.
1054 */
923de3cf 1055 getboottime(&boot);
50d0a0f9 1056
4b648665
BR		 1057 if (kvm->arch.kvmclock_offset) {
1058 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1059 boot = timespec_sub(boot, ts);
1060 }
50d0a0f9
GH		 1061 wc.sec = boot.tv_sec;
1062 wc.nsec = boot.tv_nsec;
1063 wc.version = version;
18068523
GOC		 1064
1065 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1066
1067 version++;
1068 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1069}
1070
50d0a0f9
GH		 1071static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1072{
1073 uint32_t quotient, remainder;
1074
1075 /* Don't try to replace with do_div(), this one calculates
1076 * "(dividend << 32) / divisor" */
1077 __asm__ ( "divl %4"
1078 : "=a" (quotient), "=d" (remainder)
1079 : "0" (0), "1" (dividend), "r" (divisor) );
1080 return quotient;
1081}
1082
5f4e3f88
ZA		 1083static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1084 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1085{
5f4e3f88 1086 uint64_t scaled64;
50d0a0f9
GH		 1087 int32_t shift = 0;
1088 uint64_t tps64;
1089 uint32_t tps32;
1090
5f4e3f88
ZA		 1091 tps64 = base_khz * 1000LL;
1092 scaled64 = scaled_khz * 1000LL;
50933623 1093 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1094 tps64 >>= 1;
1095 shift--;
1096 }
1097
1098 tps32 = (uint32_t)tps64;
50933623
JK		 1099 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1100 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1101 scaled64 >>= 1;
1102 else
1103 tps32 <<= 1;
50d0a0f9
GH		 1104 shift++;
1105 }
1106
5f4e3f88
ZA		 1107 *pshift = shift;
1108 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1109
5f4e3f88
ZA		 1110 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1111 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1112}
1113
759379dd
ZA		 1114static inline u64 get_kernel_ns(void)
1115{
1116 struct timespec ts;
1117
1118 WARN_ON(preemptible());
1119 ktime_get_ts(&ts);
1120 monotonic_to_bootbased(&ts);
1121 return timespec_to_ns(&ts);
50d0a0f9
GH		 1122}
1123
d828199e 1124#ifdef CONFIG_X86_64
16e8d74d 1125static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1126#endif
16e8d74d 1127
c8076604 1128static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1129unsigned long max_tsc_khz;
c8076604 1130
cc578287 1131static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1132{
cc578287
ZA		 1133 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1134 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1135}
1136
cc578287 1137static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1138{
cc578287
ZA		 1139 u64 v = (u64)khz * (1000000 + ppm);
1140 do_div(v, 1000000);
1141 return v;
1e993611
JR		 1142}
1143
cc578287 1144static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1145{
cc578287
ZA		 1146 u32 thresh_lo, thresh_hi;
1147 int use_scaling = 0;
217fc9cf 1148
03ba32ca
MT		 1149 /* tsc_khz can be zero if TSC calibration fails */
1150 if (this_tsc_khz == 0)
1151 return;
1152
c285545f
ZA		 1153 /* Compute a scale to convert nanoseconds in TSC cycles */
1154 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1155 &vcpu->arch.virtual_tsc_shift,
1156 &vcpu->arch.virtual_tsc_mult);
1157 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1158
1159 /*
1160 * Compute the variation in TSC rate which is acceptable
1161 * within the range of tolerance and decide if the
1162 * rate being applied is within that bounds of the hardware
1163 * rate. If so, no scaling or compensation need be done.
1164 */
1165 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1166 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1167 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1168 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1169 use_scaling = 1;
1170 }
1171 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1172}
1173
1174static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1175{
e26101b1 1176 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1177 vcpu->arch.virtual_tsc_mult,
1178 vcpu->arch.virtual_tsc_shift);
e26101b1 1179 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1180 return tsc;
1181}
1182
b48aa97e
MT		 1183void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1184{
1185#ifdef CONFIG_X86_64
1186 bool vcpus_matched;
1187 bool do_request = false;
1188 struct kvm_arch *ka = &vcpu->kvm->arch;
1189 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1190
1191 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1192 atomic_read(&vcpu->kvm->online_vcpus));
1193
1194 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1195 if (!ka->use_master_clock)
1196 do_request = 1;
1197
1198 if (!vcpus_matched && ka->use_master_clock)
1199 do_request = 1;
1200
1201 if (do_request)
1202 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1203
1204 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1205 atomic_read(&vcpu->kvm->online_vcpus),
1206 ka->use_master_clock, gtod->clock.vclock_mode);
1207#endif
1208}
1209
ba904635
WA		 1210static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1211{
1212 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1213 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1214}
1215
8fe8ab46 1216void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1217{
1218 struct kvm *kvm = vcpu->kvm;
f38e098f 1219 u64 offset, ns, elapsed;
99e3e30a 1220 unsigned long flags;
02626b6a 1221 s64 usdiff;
b48aa97e 1222 bool matched;
8fe8ab46 1223 u64 data = msr->data;
99e3e30a 1224
038f8c11 1225 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1226 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1227 ns = get_kernel_ns();
f38e098f 1228 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1229
03ba32ca 1230 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1231 int faulted = 0;
1232
03ba32ca
MT		 1233 /* n.b - signed multiplication and division required */
1234 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1235#ifdef CONFIG_X86_64
03ba32ca 1236 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1237#else
03ba32ca 1238 /* do_div() only does unsigned */
8915aa27
MT		 1239 asm("1: idivl %[divisor]\n"
1240 "2: xor %%edx, %%edx\n"
1241 " movl $0, %[faulted]\n"
1242 "3:\n"
1243 ".section .fixup,\"ax\"\n"
1244 "4: movl $1, %[faulted]\n"
1245 " jmp 3b\n"
1246 ".previous\n"
1247
1248 _ASM_EXTABLE(1b, 4b)
1249
1250 : "=A"(usdiff), [faulted] "=r" (faulted)
1251 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1252
5d3cb0f6 1253#endif
03ba32ca
MT		 1254 do_div(elapsed, 1000);
1255 usdiff -= elapsed;
1256 if (usdiff < 0)
1257 usdiff = -usdiff;
8915aa27
MT		 1258
1259 /* idivl overflow => difference is larger than USEC_PER_SEC */
1260 if (faulted)
1261 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1262 } else
1263 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1264
1265 /*
5d3cb0f6
ZA		 1266 * Special case: TSC write with a small delta (1 second) of virtual
1267 * cycle time against real time is interpreted as an attempt to
1268 * synchronize the CPU.
1269 *
1270 * For a reliable TSC, we can match TSC offsets, and for an unstable
1271 * TSC, we add elapsed time in this computation. We could let the
1272 * compensation code attempt to catch up if we fall behind, but
1273 * it's better to try to match offsets from the beginning.
1274 */
02626b6a 1275 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1276 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1277 if (!check_tsc_unstable()) {
e26101b1 1278 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1279 pr_debug("kvm: matched tsc offset for %llu\n", data);
1280 } else {
857e4099 1281 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1282 data += delta;
1283 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1284 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1285 }
b48aa97e 1286 matched = true;
e26101b1
ZA		 1287 } else {
1288 /*
1289 * We split periods of matched TSC writes into generations.
1290 * For each generation, we track the original measured
1291 * nanosecond time, offset, and write, so if TSCs are in
1292 * sync, we can match exact offset, and if not, we can match
4a969980 1293 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1294 *
1295 * These values are tracked in kvm->arch.cur_xxx variables.
1296 */
1297 kvm->arch.cur_tsc_generation++;
1298 kvm->arch.cur_tsc_nsec = ns;
1299 kvm->arch.cur_tsc_write = data;
1300 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1301 matched = false;
e26101b1
ZA		 1302 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1303 kvm->arch.cur_tsc_generation, data);
f38e098f 1304 }
e26101b1
ZA		 1305
1306 /*
1307 * We also track th most recent recorded KHZ, write and time to
1308 * allow the matching interval to be extended at each write.
1309 */
f38e098f
ZA		 1310 kvm->arch.last_tsc_nsec = ns;
1311 kvm->arch.last_tsc_write = data;
5d3cb0f6 1312 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a 1313
b183aa58 1314 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1315
1316 /* Keep track of which generation this VCPU has synchronized to */
1317 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1318 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1319 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1320
ba904635
WA		 1321 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1322 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1323 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1324 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1325
1326 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1327 if (matched)
1328 kvm->arch.nr_vcpus_matched_tsc++;
1329 else
1330 kvm->arch.nr_vcpus_matched_tsc = 0;
1331
1332 kvm_track_tsc_matching(vcpu);
1333 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1334}
e26101b1 1335
99e3e30a
ZA		 1336EXPORT_SYMBOL_GPL(kvm_write_tsc);
1337
d828199e
MT		 1338#ifdef CONFIG_X86_64
1339
1340static cycle_t read_tsc(void)
1341{
1342 cycle_t ret;
1343 u64 last;
1344
1345 /*
1346 * Empirically, a fence (of type that depends on the CPU)
1347 * before rdtsc is enough to ensure that rdtsc is ordered
1348 * with respect to loads. The various CPU manuals are unclear
1349 * as to whether rdtsc can be reordered with later loads,
1350 * but no one has ever seen it happen.
1351 */
1352 rdtsc_barrier();
1353 ret = (cycle_t)vget_cycles();
1354
1355 last = pvclock_gtod_data.clock.cycle_last;
1356
1357 if (likely(ret >= last))
1358 return ret;
1359
1360 /*
1361 * GCC likes to generate cmov here, but this branch is extremely
1362 * predictable (it's just a funciton of time and the likely is
1363 * very likely) and there's a data dependence, so force GCC
1364 * to generate a branch instead. I don't barrier() because
1365 * we don't actually need a barrier, and if this function
1366 * ever gets inlined it will generate worse code.
1367 */
1368 asm volatile ("");
1369 return last;
1370}
1371
1372static inline u64 vgettsc(cycle_t *cycle_now)
1373{
1374 long v;
1375 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1376
1377 *cycle_now = read_tsc();
1378
1379 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1380 return v * gtod->clock.mult;
1381}
1382
1383static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1384{
1385 unsigned long seq;
1386 u64 ns;
1387 int mode;
1388 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1389
1390 ts->tv_nsec = 0;
1391 do {
1392 seq = read_seqcount_begin(&gtod->seq);
1393 mode = gtod->clock.vclock_mode;
1394 ts->tv_sec = gtod->monotonic_time_sec;
1395 ns = gtod->monotonic_time_snsec;
1396 ns += vgettsc(cycle_now);
1397 ns >>= gtod->clock.shift;
1398 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1399 timespec_add_ns(ts, ns);
1400
1401 return mode;
1402}
1403
1404/* returns true if host is using tsc clocksource */
1405static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1406{
1407 struct timespec ts;
1408
1409 /* checked again under seqlock below */
1410 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1411 return false;
1412
1413 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1414 return false;
1415
1416 monotonic_to_bootbased(&ts);
1417 *kernel_ns = timespec_to_ns(&ts);
1418
1419 return true;
1420}
1421#endif
1422
1423/*
1424 *
b48aa97e
MT		 1425 * Assuming a stable TSC across physical CPUS, and a stable TSC
1426 * across virtual CPUs, the following condition is possible.
1427 * Each numbered line represents an event visible to both
d828199e
MT		 1428 * CPUs at the next numbered event.
1429 *
1430 * "timespecX" represents host monotonic time. "tscX" represents
1431 * RDTSC value.
1432 *
1433 * VCPU0 on CPU0 | VCPU1 on CPU1
1434 *
1435 * 1. read timespec0,tsc0
1436 * 2. | timespec1 = timespec0 + N
1437 * | tsc1 = tsc0 + M
1438 * 3. transition to guest | transition to guest
1439 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1440 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1441 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1442 *
1443 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1444 *
1445 * - ret0 < ret1
1446 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1447 * ...
1448 * - 0 < N - M => M < N
1449 *
1450 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1451 * always the case (the difference between two distinct xtime instances
1452 * might be smaller then the difference between corresponding TSC reads,
1453 * when updating guest vcpus pvclock areas).
1454 *
1455 * To avoid that problem, do not allow visibility of distinct
1456 * system_timestamp/tsc_timestamp values simultaneously: use a master
1457 * copy of host monotonic time values. Update that master copy
1458 * in lockstep.
1459 *
b48aa97e 1460 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1461 *
1462 */
1463
1464static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1465{
1466#ifdef CONFIG_X86_64
1467 struct kvm_arch *ka = &kvm->arch;
1468 int vclock_mode;
b48aa97e
MT		 1469 bool host_tsc_clocksource, vcpus_matched;
1470
1471 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1472 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1473
1474 /*
1475 * If the host uses TSC clock, then passthrough TSC as stable
1476 * to the guest.
1477 */
b48aa97e 1478 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1479 &ka->master_kernel_ns,
1480 &ka->master_cycle_now);
1481
b48aa97e
MT		 1482 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1483
d828199e
MT		 1484 if (ka->use_master_clock)
1485 atomic_set(&kvm_guest_has_master_clock, 1);
1486
1487 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1488 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1489 vcpus_matched);
d828199e
MT		 1490#endif
1491}
1492
2e762ff7
MT		 1493static void kvm_gen_update_masterclock(struct kvm *kvm)
1494{
1495#ifdef CONFIG_X86_64
1496 int i;
1497 struct kvm_vcpu *vcpu;
1498 struct kvm_arch *ka = &kvm->arch;
1499
1500 spin_lock(&ka->pvclock_gtod_sync_lock);
1501 kvm_make_mclock_inprogress_request(kvm);
1502 /* no guest entries from this point */
1503 pvclock_update_vm_gtod_copy(kvm);
1504
1505 kvm_for_each_vcpu(i, vcpu, kvm)
1506 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1507
1508 /* guest entries allowed */
1509 kvm_for_each_vcpu(i, vcpu, kvm)
1510 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1511
1512 spin_unlock(&ka->pvclock_gtod_sync_lock);
1513#endif
1514}
1515
34c238a1 1516static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1517{
d828199e 1518 unsigned long flags, this_tsc_khz;
18068523 1519 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1520 struct kvm_arch *ka = &v->kvm->arch;
f25e656d 1521 s64 kernel_ns;
d828199e 1522 u64 tsc_timestamp, host_tsc;
0b79459b 1523 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1524 u8 pvclock_flags;
d828199e
MT		 1525 bool use_master_clock;
1526
1527 kernel_ns = 0;
1528 host_tsc = 0;
18068523 1529
d828199e
MT		 1530 /*
1531 * If the host uses TSC clock, then passthrough TSC as stable
1532 * to the guest.
1533 */
1534 spin_lock(&ka->pvclock_gtod_sync_lock);
1535 use_master_clock = ka->use_master_clock;
1536 if (use_master_clock) {
1537 host_tsc = ka->master_cycle_now;
1538 kernel_ns = ka->master_kernel_ns;
1539 }
1540 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1541
1542 /* Keep irq disabled to prevent changes to the clock */
1543 local_irq_save(flags);
1544 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1545 if (unlikely(this_tsc_khz == 0)) {
1546 local_irq_restore(flags);
1547 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1548 return 1;
1549 }
d828199e
MT		 1550 if (!use_master_clock) {
1551 host_tsc = native_read_tsc();
1552 kernel_ns = get_kernel_ns();
1553 }
1554
1555 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1556
c285545f
ZA		 1557 /*
1558 * We may have to catch up the TSC to match elapsed wall clock
1559 * time for two reasons, even if kvmclock is used.
1560 * 1) CPU could have been running below the maximum TSC rate
1561 * 2) Broken TSC compensation resets the base at each VCPU
1562 * entry to avoid unknown leaps of TSC even when running
1563 * again on the same CPU. This may cause apparent elapsed
1564 * time to disappear, and the guest to stand still or run
1565 * very slowly.
1566 */
1567 if (vcpu->tsc_catchup) {
1568 u64 tsc = compute_guest_tsc(v, kernel_ns);
1569 if (tsc > tsc_timestamp) {
f1e2b260 1570 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1571 tsc_timestamp = tsc;
1572 }
50d0a0f9
GH		 1573 }
1574
18068523
GOC		 1575 local_irq_restore(flags);
1576
0b79459b 1577 if (!vcpu->pv_time_enabled)
c285545f 1578 return 0;
18068523 1579
e48672fa 1580 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1581 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1582 &vcpu->hv_clock.tsc_shift,
1583 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1584 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1585 }
1586
1587 /* With all the info we got, fill in the values */
1d5f066e 1588 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1589 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
28e4639a 1590 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1591
18068523
GOC		 1592 /*
1593 * The interface expects us to write an even number signaling that the
1594 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1595 * state, we just increase by 2 at the end.
18068523 1596 */
50d0a0f9 1597 vcpu->hv_clock.version += 2;
18068523 1598
0b79459b
AH		 1599 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1600 &guest_hv_clock, sizeof(guest_hv_clock))))
1601 return 0;
78c0337a
MT		 1602
1603 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1604 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1605
1606 if (vcpu->pvclock_set_guest_stopped_request) {
1607 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1608 vcpu->pvclock_set_guest_stopped_request = false;
1609 }
1610
d828199e
MT		 1611 /* If the host uses TSC clocksource, then it is stable */
1612 if (use_master_clock)
1613 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1614
78c0337a
MT		 1615 vcpu->hv_clock.flags = pvclock_flags;
1616
0b79459b
AH		 1617 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1618 &vcpu->hv_clock,
1619 sizeof(vcpu->hv_clock));
8cfdc000 1620 return 0;
c8076604
GH		 1621}
1622
0061d53d
MT		 1623/*
1624 * kvmclock updates which are isolated to a given vcpu, such as
1625 * vcpu->cpu migration, should not allow system_timestamp from
1626 * the rest of the vcpus to remain static. Otherwise ntp frequency
1627 * correction applies to one vcpu's system_timestamp but not
1628 * the others.
1629 *
1630 * So in those cases, request a kvmclock update for all vcpus.
1631 * The worst case for a remote vcpu to update its kvmclock
1632 * is then bounded by maximum nohz sleep latency.
1633 */
1634
1635static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1636{
1637 int i;
1638 struct kvm *kvm = v->kvm;
1639 struct kvm_vcpu *vcpu;
1640
1641 kvm_for_each_vcpu(i, vcpu, kvm) {
1642 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1643 kvm_vcpu_kick(vcpu);
1644 }
1645}
1646
9ba075a6
AK		 1647static bool msr_mtrr_valid(unsigned msr)
1648{
1649 switch (msr) {
1650 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1651 case MSR_MTRRfix64K_00000:
1652 case MSR_MTRRfix16K_80000:
1653 case MSR_MTRRfix16K_A0000:
1654 case MSR_MTRRfix4K_C0000:
1655 case MSR_MTRRfix4K_C8000:
1656 case MSR_MTRRfix4K_D0000:
1657 case MSR_MTRRfix4K_D8000:
1658 case MSR_MTRRfix4K_E0000:
1659 case MSR_MTRRfix4K_E8000:
1660 case MSR_MTRRfix4K_F0000:
1661 case MSR_MTRRfix4K_F8000:
1662 case MSR_MTRRdefType:
1663 case MSR_IA32_CR_PAT:
1664 return true;
1665 case 0x2f8:
1666 return true;
1667 }
1668 return false;
1669}
1670
d6289b93
MT		 1671static bool valid_pat_type(unsigned t)
1672{
1673 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1674}
1675
1676static bool valid_mtrr_type(unsigned t)
1677{
1678 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1679}
1680
1681static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1682{
1683 int i;
1684
1685 if (!msr_mtrr_valid(msr))
1686 return false;
1687
1688 if (msr == MSR_IA32_CR_PAT) {
1689 for (i = 0; i < 8; i++)
1690 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1691 return false;
1692 return true;
1693 } else if (msr == MSR_MTRRdefType) {
1694 if (data & ~0xcff)
1695 return false;
1696 return valid_mtrr_type(data & 0xff);
1697 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1698 for (i = 0; i < 8 ; i++)
1699 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1700 return false;
1701 return true;
1702 }
1703
1704 /* variable MTRRs */
1705 return valid_mtrr_type(data & 0xff);
1706}
1707
9ba075a6
AK		 1708static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1709{
0bed3b56
SY		 1710 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1711
d6289b93 1712 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1713 return 1;
1714
0bed3b56
SY		 1715 if (msr == MSR_MTRRdefType) {
1716 vcpu->arch.mtrr_state.def_type = data;
1717 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1718 } else if (msr == MSR_MTRRfix64K_00000)
1719 p[0] = data;
1720 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1721 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1722 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1723 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1724 else if (msr == MSR_IA32_CR_PAT)
1725 vcpu->arch.pat = data;
1726 else { /* Variable MTRRs */
1727 int idx, is_mtrr_mask;
1728 u64 *pt;
1729
1730 idx = (msr - 0x200) / 2;
1731 is_mtrr_mask = msr - 0x200 - 2 * idx;
1732 if (!is_mtrr_mask)
1733 pt =
1734 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1735 else
1736 pt =
1737 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1738 *pt = data;
1739 }
1740
1741 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1742 return 0;
1743}
15c4a640 1744
890ca9ae 1745static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1746{
890ca9ae
HY		 1747 u64 mcg_cap = vcpu->arch.mcg_cap;
1748 unsigned bank_num = mcg_cap & 0xff;
1749
15c4a640 1750 switch (msr) {
15c4a640 1751 case MSR_IA32_MCG_STATUS:
890ca9ae 1752 vcpu->arch.mcg_status = data;
15c4a640 1753 break;
c7ac679c 1754 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1755 if (!(mcg_cap & MCG_CTL_P))
1756 return 1;
1757 if (data != 0 && data != ~(u64)0)
1758 return -1;
1759 vcpu->arch.mcg_ctl = data;
1760 break;
1761 default:
1762 if (msr >= MSR_IA32_MC0_CTL &&
1763 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1764 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1765 /* only 0 or all 1s can be written to IA32_MCi_CTL
1766 * some Linux kernels though clear bit 10 in bank 4 to
1767 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1768 * this to avoid an uncatched #GP in the guest
1769 */
890ca9ae 1770 if ((offset & 0x3) == 0 &&
114be429 1771 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1772 return -1;
1773 vcpu->arch.mce_banks[offset] = data;
1774 break;
1775 }
1776 return 1;
1777 }
1778 return 0;
1779}
1780
ffde22ac
ES		 1781static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1782{
1783 struct kvm *kvm = vcpu->kvm;
1784 int lm = is_long_mode(vcpu);
1785 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1786 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1787 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1788 : kvm->arch.xen_hvm_config.blob_size_32;
1789 u32 page_num = data & ~PAGE_MASK;
1790 u64 page_addr = data & PAGE_MASK;
1791 u8 *page;
1792 int r;
1793
1794 r = -E2BIG;
1795 if (page_num >= blob_size)
1796 goto out;
1797 r = -ENOMEM;
ff5c2c03
SL		 1798 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1799 if (IS_ERR(page)) {
1800 r = PTR_ERR(page);
ffde22ac 1801 goto out;
ff5c2c03 1802 }
ffde22ac
ES		 1803 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1804 goto out_free;
1805 r = 0;
1806out_free:
1807 kfree(page);
1808out:
1809 return r;
1810}
1811
55cd8e5a
GN		 1812static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1813{
1814 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1815}
1816
1817static bool kvm_hv_msr_partition_wide(u32 msr)
1818{
1819 bool r = false;
1820 switch (msr) {
1821 case HV_X64_MSR_GUEST_OS_ID:
1822 case HV_X64_MSR_HYPERCALL:
e984097b
VR		 1823 case HV_X64_MSR_REFERENCE_TSC:
1824 case HV_X64_MSR_TIME_REF_COUNT:
55cd8e5a
GN		 1825 r = true;
1826 break;
1827 }
1828
1829 return r;
1830}
1831
1832static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1833{
1834 struct kvm *kvm = vcpu->kvm;
1835
1836 switch (msr) {
1837 case HV_X64_MSR_GUEST_OS_ID:
1838 kvm->arch.hv_guest_os_id = data;
1839 /* setting guest os id to zero disables hypercall page */
1840 if (!kvm->arch.hv_guest_os_id)
1841 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1842 break;
1843 case HV_X64_MSR_HYPERCALL: {
1844 u64 gfn;
1845 unsigned long addr;
1846 u8 instructions[4];
1847
1848 /* if guest os id is not set hypercall should remain disabled */
1849 if (!kvm->arch.hv_guest_os_id)
1850 break;
1851 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1852 kvm->arch.hv_hypercall = data;
1853 break;
1854 }
1855 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1856 addr = gfn_to_hva(kvm, gfn);
1857 if (kvm_is_error_hva(addr))
1858 return 1;
1859 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1860 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1861 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1862 return 1;
1863 kvm->arch.hv_hypercall = data;
b94b64c9 1864 mark_page_dirty(kvm, gfn);
55cd8e5a
GN		 1865 break;
1866 }
e984097b
VR		 1867 case HV_X64_MSR_REFERENCE_TSC: {
1868 u64 gfn;
1869 HV_REFERENCE_TSC_PAGE tsc_ref;
1870 memset(&tsc_ref, 0, sizeof(tsc_ref));
1871 kvm->arch.hv_tsc_page = data;
1872 if (!(data & HV_X64_MSR_TSC_REFERENCE_ENABLE))
1873 break;
1874 gfn = data >> HV_X64_MSR_TSC_REFERENCE_ADDRESS_SHIFT;
1875 if (kvm_write_guest(kvm, data,
1876 &tsc_ref, sizeof(tsc_ref)))
1877 return 1;
1878 mark_page_dirty(kvm, gfn);
1879 break;
1880 }
55cd8e5a 1881 default:
a737f256
CD		 1882 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1883 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1884 return 1;
1885 }
1886 return 0;
1887}
1888
1889static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1890{
10388a07
GN		 1891 switch (msr) {
1892 case HV_X64_MSR_APIC_ASSIST_PAGE: {
b3af1e88 1893 u64 gfn;
10388a07 1894 unsigned long addr;
55cd8e5a 1895
10388a07
GN		 1896 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1897 vcpu->arch.hv_vapic = data;
1898 break;
1899 }
b3af1e88
VR		 1900 gfn = data >> HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT;
1901 addr = gfn_to_hva(vcpu->kvm, gfn);
10388a07
GN		 1902 if (kvm_is_error_hva(addr))
1903 return 1;
8b0cedff 1904 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1905 return 1;
1906 vcpu->arch.hv_vapic = data;
b3af1e88 1907 mark_page_dirty(vcpu->kvm, gfn);
10388a07
GN		 1908 break;
1909 }
1910 case HV_X64_MSR_EOI:
1911 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1912 case HV_X64_MSR_ICR:
1913 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1914 case HV_X64_MSR_TPR:
1915 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1916 default:
a737f256
CD		 1917 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1918 "data 0x%llx\n", msr, data);
10388a07
GN		 1919 return 1;
1920 }
1921
1922 return 0;
55cd8e5a
GN		 1923}
1924
344d9588
GN		 1925static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1926{
1927 gpa_t gpa = data & ~0x3f;
1928
4a969980 1929 /* Bits 2:5 are reserved, Should be zero */
6adba527 1930 if (data & 0x3c)
344d9588
GN		 1931 return 1;
1932
1933 vcpu->arch.apf.msr_val = data;
1934
1935 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1936 kvm_clear_async_pf_completion_queue(vcpu);
1937 kvm_async_pf_hash_reset(vcpu);
1938 return 0;
1939 }
1940
8f964525
AH		 1941 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1942 sizeof(u32)))
344d9588
GN		 1943 return 1;
1944
6adba527 1945 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1946 kvm_async_pf_wakeup_all(vcpu);
1947 return 0;
1948}
1949
12f9a48f
GC		 1950static void kvmclock_reset(struct kvm_vcpu *vcpu)
1951{
0b79459b 1952 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1953}
1954
c9aaa895
GC		 1955static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1956{
1957 u64 delta;
1958
1959 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1960 return;
1961
1962 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1963 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1964 vcpu->arch.st.accum_steal = delta;
1965}
1966
1967static void record_steal_time(struct kvm_vcpu *vcpu)
1968{
1969 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1970 return;
1971
1972 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1973 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1974 return;
1975
1976 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1977 vcpu->arch.st.steal.version += 2;
1978 vcpu->arch.st.accum_steal = 0;
1979
1980 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1981 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1982}
1983
8fe8ab46 1984int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 1985{
5753785f 1986 bool pr = false;
8fe8ab46
WA		 1987 u32 msr = msr_info->index;
1988 u64 data = msr_info->data;
5753785f 1989
15c4a640 1990 switch (msr) {
2e32b719
BP		 1991 case MSR_AMD64_NB_CFG:
1992 case MSR_IA32_UCODE_REV:
1993 case MSR_IA32_UCODE_WRITE:
1994 case MSR_VM_HSAVE_PA:
1995 case MSR_AMD64_PATCH_LOADER:
1996 case MSR_AMD64_BU_CFG2:
1997 break;
1998
15c4a640 1999 case MSR_EFER:
b69e8cae 2000 return set_efer(vcpu, data);
8f1589d9
AP		 2001 case MSR_K7_HWCR:
2002 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 2003 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 2004 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 2005 if (data != 0) {
a737f256
CD		 2006 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
2007 data);
8f1589d9
AP		 2008 return 1;
2009 }
15c4a640 2010 break;
f7c6d140
AP		 2011 case MSR_FAM10H_MMIO_CONF_BASE:
2012 if (data != 0) {
a737f256
CD		 2013 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
2014 "0x%llx\n", data);
f7c6d140
AP		 2015 return 1;
2016 }
15c4a640 2017 break;
b5e2fec0
AG		 2018 case MSR_IA32_DEBUGCTLMSR:
2019 if (!data) {
2020 /* We support the non-activated case already */
2021 break;
2022 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2023 /* Values other than LBR and BTF are vendor-specific,
2024 thus reserved and should throw a #GP */
2025 return 1;
2026 }
a737f256
CD		 2027 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2028 __func__, data);
b5e2fec0 2029 break;
9ba075a6
AK		 2030 case 0x200 ... 0x2ff:
2031 return set_msr_mtrr(vcpu, msr, data);
15c4a640 2032 case MSR_IA32_APICBASE:
58cb628d 2033 return kvm_set_apic_base(vcpu, msr_info);
0105d1a5
GN		 2034 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2035 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2036 case MSR_IA32_TSCDEADLINE:
2037 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2038 break;
ba904635
WA		 2039 case MSR_IA32_TSC_ADJUST:
2040 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2041 if (!msr_info->host_initiated) {
2042 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2043 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2044 }
2045 vcpu->arch.ia32_tsc_adjust_msr = data;
2046 }
2047 break;
15c4a640 2048 case MSR_IA32_MISC_ENABLE:
ad312c7c 2049 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2050 break;
11c6bffa 2051 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2052 case MSR_KVM_WALL_CLOCK:
2053 vcpu->kvm->arch.wall_clock = data;
2054 kvm_write_wall_clock(vcpu->kvm, data);
2055 break;
11c6bffa 2056 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2057 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2058 u64 gpa_offset;
12f9a48f 2059 kvmclock_reset(vcpu);
18068523
GOC		 2060
2061 vcpu->arch.time = data;
0061d53d 2062 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2063
2064 /* we verify if the enable bit is set... */
2065 if (!(data & 1))
2066 break;
2067
0b79459b 2068 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2069
0b79459b 2070 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2071 &vcpu->arch.pv_time, data & ~1ULL,
2072 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2073 vcpu->arch.pv_time_enabled = false;
2074 else
2075 vcpu->arch.pv_time_enabled = true;
32cad84f 2076
18068523
GOC		 2077 break;
2078 }
344d9588
GN		 2079 case MSR_KVM_ASYNC_PF_EN:
2080 if (kvm_pv_enable_async_pf(vcpu, data))
2081 return 1;
2082 break;
c9aaa895
GC		 2083 case MSR_KVM_STEAL_TIME:
2084
2085 if (unlikely(!sched_info_on()))
2086 return 1;
2087
2088 if (data & KVM_STEAL_RESERVED_MASK)
2089 return 1;
2090
2091 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2092 data & KVM_STEAL_VALID_BITS,
2093 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2094 return 1;
2095
2096 vcpu->arch.st.msr_val = data;
2097
2098 if (!(data & KVM_MSR_ENABLED))
2099 break;
2100
2101 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2102
2103 preempt_disable();
2104 accumulate_steal_time(vcpu);
2105 preempt_enable();
2106
2107 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2108
2109 break;
ae7a2a3f
MT		 2110 case MSR_KVM_PV_EOI_EN:
2111 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2112 return 1;
2113 break;
c9aaa895 2114
890ca9ae
HY		 2115 case MSR_IA32_MCG_CTL:
2116 case MSR_IA32_MCG_STATUS:
2117 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2118 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2119
2120 /* Performance counters are not protected by a CPUID bit,
2121 * so we should check all of them in the generic path for the sake of
2122 * cross vendor migration.
2123 * Writing a zero into the event select MSRs disables them,
2124 * which we perfectly emulate ;-). Any other value should be at least
2125 * reported, some guests depend on them.
2126 */
71db6023
AP		 2127 case MSR_K7_EVNTSEL0:
2128 case MSR_K7_EVNTSEL1:
2129 case MSR_K7_EVNTSEL2:
2130 case MSR_K7_EVNTSEL3:
2131 if (data != 0)
a737f256
CD		 2132 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2133 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2134 break;
2135 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2136 * so we ignore writes to make it happy.
2137 */
71db6023
AP		 2138 case MSR_K7_PERFCTR0:
2139 case MSR_K7_PERFCTR1:
2140 case MSR_K7_PERFCTR2:
2141 case MSR_K7_PERFCTR3:
a737f256
CD		 2142 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2143 "0x%x data 0x%llx\n", msr, data);
71db6023 2144 break;
5753785f
GN		 2145 case MSR_P6_PERFCTR0:
2146 case MSR_P6_PERFCTR1:
2147 pr = true;
2148 case MSR_P6_EVNTSEL0:
2149 case MSR_P6_EVNTSEL1:
2150 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2151 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2152
2153 if (pr || data != 0)
a737f256
CD		 2154 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2155 "0x%x data 0x%llx\n", msr, data);
5753785f 2156 break;
84e0cefa
JS		 2157 case MSR_K7_CLK_CTL:
2158 /*
2159 * Ignore all writes to this no longer documented MSR.
2160 * Writes are only relevant for old K7 processors,
2161 * all pre-dating SVM, but a recommended workaround from
4a969980 2162 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2163 * affected processor models on the command line, hence
2164 * the need to ignore the workaround.
2165 */
2166 break;
55cd8e5a
GN		 2167 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2168 if (kvm_hv_msr_partition_wide(msr)) {
2169 int r;
2170 mutex_lock(&vcpu->kvm->lock);
2171 r = set_msr_hyperv_pw(vcpu, msr, data);
2172 mutex_unlock(&vcpu->kvm->lock);
2173 return r;
2174 } else
2175 return set_msr_hyperv(vcpu, msr, data);
2176 break;
91c9c3ed 2177 case MSR_IA32_BBL_CR_CTL3:
2178 /* Drop writes to this legacy MSR -- see rdmsr
2179 * counterpart for further detail.
2180 */
a737f256 2181 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2182 break;
2b036c6b
BO		 2183 case MSR_AMD64_OSVW_ID_LENGTH:
2184 if (!guest_cpuid_has_osvw(vcpu))
2185 return 1;
2186 vcpu->arch.osvw.length = data;
2187 break;
2188 case MSR_AMD64_OSVW_STATUS:
2189 if (!guest_cpuid_has_osvw(vcpu))
2190 return 1;
2191 vcpu->arch.osvw.status = data;
2192 break;
15c4a640 2193 default:
ffde22ac
ES		 2194 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2195 return xen_hvm_config(vcpu, data);
f5132b01 2196 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2197 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2198 if (!ignore_msrs) {
a737f256
CD		 2199 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2200 msr, data);
ed85c068
AP		 2201 return 1;
2202 } else {
a737f256
CD		 2203 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2204 msr, data);
ed85c068
AP		 2205 break;
2206 }
15c4a640
CO		 2207 }
2208 return 0;
2209}
2210EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2211
2212
2213/*
2214 * Reads an msr value (of 'msr_index') into 'pdata'.
2215 * Returns 0 on success, non-0 otherwise.
2216 * Assumes vcpu_load() was already called.
2217 */
2218int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2219{
2220 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2221}
2222
9ba075a6
AK		 2223static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2224{
0bed3b56
SY		 2225 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2226
9ba075a6
AK		 2227 if (!msr_mtrr_valid(msr))
2228 return 1;
2229
0bed3b56
SY		 2230 if (msr == MSR_MTRRdefType)
2231 *pdata = vcpu->arch.mtrr_state.def_type +
2232 (vcpu->arch.mtrr_state.enabled << 10);
2233 else if (msr == MSR_MTRRfix64K_00000)
2234 *pdata = p[0];
2235 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2236 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2237 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2238 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2239 else if (msr == MSR_IA32_CR_PAT)
2240 *pdata = vcpu->arch.pat;
2241 else { /* Variable MTRRs */
2242 int idx, is_mtrr_mask;
2243 u64 *pt;
2244
2245 idx = (msr - 0x200) / 2;
2246 is_mtrr_mask = msr - 0x200 - 2 * idx;
2247 if (!is_mtrr_mask)
2248 pt =
2249 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2250 else
2251 pt =
2252 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2253 *pdata = *pt;
2254 }
2255
9ba075a6
AK		 2256 return 0;
2257}
2258
890ca9ae 2259static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2260{
2261 u64 data;
890ca9ae
HY		 2262 u64 mcg_cap = vcpu->arch.mcg_cap;
2263 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2264
2265 switch (msr) {
15c4a640
CO		 2266 case MSR_IA32_P5_MC_ADDR:
2267 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2268 data = 0;
2269 break;
15c4a640 2270 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2271 data = vcpu->arch.mcg_cap;
2272 break;
c7ac679c 2273 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2274 if (!(mcg_cap & MCG_CTL_P))
2275 return 1;
2276 data = vcpu->arch.mcg_ctl;
2277 break;
2278 case MSR_IA32_MCG_STATUS:
2279 data = vcpu->arch.mcg_status;
2280 break;
2281 default:
2282 if (msr >= MSR_IA32_MC0_CTL &&
2283 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2284 u32 offset = msr - MSR_IA32_MC0_CTL;
2285 data = vcpu->arch.mce_banks[offset];
2286 break;
2287 }
2288 return 1;
2289 }
2290 *pdata = data;
2291 return 0;
2292}
2293
55cd8e5a
GN		 2294static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2295{
2296 u64 data = 0;
2297 struct kvm *kvm = vcpu->kvm;
2298
2299 switch (msr) {
2300 case HV_X64_MSR_GUEST_OS_ID:
2301 data = kvm->arch.hv_guest_os_id;
2302 break;
2303 case HV_X64_MSR_HYPERCALL:
2304 data = kvm->arch.hv_hypercall;
2305 break;
e984097b
VR		 2306 case HV_X64_MSR_TIME_REF_COUNT: {
2307 data =
2308 div_u64(get_kernel_ns() + kvm->arch.kvmclock_offset, 100);
2309 break;
2310 }
2311 case HV_X64_MSR_REFERENCE_TSC:
2312 data = kvm->arch.hv_tsc_page;
2313 break;
55cd8e5a 2314 default:
a737f256 2315 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2316 return 1;
2317 }
2318
2319 *pdata = data;
2320 return 0;
2321}
2322
2323static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2324{
2325 u64 data = 0;
2326
2327 switch (msr) {
2328 case HV_X64_MSR_VP_INDEX: {
2329 int r;
2330 struct kvm_vcpu *v;
2331 kvm_for_each_vcpu(r, v, vcpu->kvm)
2332 if (v == vcpu)
2333 data = r;
2334 break;
2335 }
10388a07
GN		 2336 case HV_X64_MSR_EOI:
2337 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2338 case HV_X64_MSR_ICR:
2339 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2340 case HV_X64_MSR_TPR:
2341 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2342 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2343 data = vcpu->arch.hv_vapic;
2344 break;
55cd8e5a 2345 default:
a737f256 2346 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2347 return 1;
2348 }
2349 *pdata = data;
2350 return 0;
2351}
2352
890ca9ae
HY		 2353int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2354{
2355 u64 data;
2356
2357 switch (msr) {
890ca9ae 2358 case MSR_IA32_PLATFORM_ID:
15c4a640 2359 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2360 case MSR_IA32_DEBUGCTLMSR:
2361 case MSR_IA32_LASTBRANCHFROMIP:
2362 case MSR_IA32_LASTBRANCHTOIP:
2363 case MSR_IA32_LASTINTFROMIP:
2364 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2365 case MSR_K8_SYSCFG:
2366 case MSR_K7_HWCR:
61a6bd67 2367 case MSR_VM_HSAVE_PA:
9e699624 2368 case MSR_K7_EVNTSEL0:
1f3ee616 2369 case MSR_K7_PERFCTR0:
1fdbd48c 2370 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2371 case MSR_AMD64_NB_CFG:
f7c6d140 2372 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2373 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2374 data = 0;
2375 break;
5753785f
GN		 2376 case MSR_P6_PERFCTR0:
2377 case MSR_P6_PERFCTR1:
2378 case MSR_P6_EVNTSEL0:
2379 case MSR_P6_EVNTSEL1:
2380 if (kvm_pmu_msr(vcpu, msr))
2381 return kvm_pmu_get_msr(vcpu, msr, pdata);
2382 data = 0;
2383 break;
742bc670
MT		 2384 case MSR_IA32_UCODE_REV:
2385 data = 0x100000000ULL;
2386 break;
9ba075a6
AK		 2387 case MSR_MTRRcap:
2388 data = 0x500 | KVM_NR_VAR_MTRR;
2389 break;
2390 case 0x200 ... 0x2ff:
2391 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2392 case 0xcd: /* fsb frequency */
2393 data = 3;
2394 break;
7b914098
JS		 2395 /*
2396 * MSR_EBC_FREQUENCY_ID
2397 * Conservative value valid for even the basic CPU models.
2398 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2399 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2400 * and 266MHz for model 3, or 4. Set Core Clock
2401 * Frequency to System Bus Frequency Ratio to 1 (bits
2402 * 31:24) even though these are only valid for CPU
2403 * models > 2, however guests may end up dividing or
2404 * multiplying by zero otherwise.
2405 */
2406 case MSR_EBC_FREQUENCY_ID:
2407 data = 1 << 24;
2408 break;
15c4a640
CO		 2409 case MSR_IA32_APICBASE:
2410 data = kvm_get_apic_base(vcpu);
2411 break;
0105d1a5
GN		 2412 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2413 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2414 break;
a3e06bbe
LJ		 2415 case MSR_IA32_TSCDEADLINE:
2416 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2417 break;
ba904635
WA		 2418 case MSR_IA32_TSC_ADJUST:
2419 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2420 break;
15c4a640 2421 case MSR_IA32_MISC_ENABLE:
ad312c7c 2422 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2423 break;
847f0ad8
AG		 2424 case MSR_IA32_PERF_STATUS:
2425 /* TSC increment by tick */
2426 data = 1000ULL;
2427 /* CPU multiplier */
2428 data |= (((uint64_t)4ULL) << 40);
2429 break;
15c4a640 2430 case MSR_EFER:
f6801dff 2431 data = vcpu->arch.efer;
15c4a640 2432 break;
18068523 2433 case MSR_KVM_WALL_CLOCK:
11c6bffa 2434 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2435 data = vcpu->kvm->arch.wall_clock;
2436 break;
2437 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2438 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2439 data = vcpu->arch.time;
2440 break;
344d9588
GN		 2441 case MSR_KVM_ASYNC_PF_EN:
2442 data = vcpu->arch.apf.msr_val;
2443 break;
c9aaa895
GC		 2444 case MSR_KVM_STEAL_TIME:
2445 data = vcpu->arch.st.msr_val;
2446 break;
1d92128f
MT		 2447 case MSR_KVM_PV_EOI_EN:
2448 data = vcpu->arch.pv_eoi.msr_val;
2449 break;
890ca9ae
HY		 2450 case MSR_IA32_P5_MC_ADDR:
2451 case MSR_IA32_P5_MC_TYPE:
2452 case MSR_IA32_MCG_CAP:
2453 case MSR_IA32_MCG_CTL:
2454 case MSR_IA32_MCG_STATUS:
2455 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2456 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2457 case MSR_K7_CLK_CTL:
2458 /*
2459 * Provide expected ramp-up count for K7. All other
2460 * are set to zero, indicating minimum divisors for
2461 * every field.
2462 *
2463 * This prevents guest kernels on AMD host with CPU
2464 * type 6, model 8 and higher from exploding due to
2465 * the rdmsr failing.
2466 */
2467 data = 0x20000000;
2468 break;
55cd8e5a
GN		 2469 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2470 if (kvm_hv_msr_partition_wide(msr)) {
2471 int r;
2472 mutex_lock(&vcpu->kvm->lock);
2473 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2474 mutex_unlock(&vcpu->kvm->lock);
2475 return r;
2476 } else
2477 return get_msr_hyperv(vcpu, msr, pdata);
2478 break;
91c9c3ed 2479 case MSR_IA32_BBL_CR_CTL3:
2480 /* This legacy MSR exists but isn't fully documented in current
2481 * silicon. It is however accessed by winxp in very narrow
2482 * scenarios where it sets bit #19, itself documented as
2483 * a "reserved" bit. Best effort attempt to source coherent
2484 * read data here should the balance of the register be
2485 * interpreted by the guest:
2486 *
2487 * L2 cache control register 3: 64GB range, 256KB size,
2488 * enabled, latency 0x1, configured
2489 */
2490 data = 0xbe702111;
2491 break;
2b036c6b
BO		 2492 case MSR_AMD64_OSVW_ID_LENGTH:
2493 if (!guest_cpuid_has_osvw(vcpu))
2494 return 1;
2495 data = vcpu->arch.osvw.length;
2496 break;
2497 case MSR_AMD64_OSVW_STATUS:
2498 if (!guest_cpuid_has_osvw(vcpu))
2499 return 1;
2500 data = vcpu->arch.osvw.status;
2501 break;
15c4a640 2502 default:
f5132b01
GN		 2503 if (kvm_pmu_msr(vcpu, msr))
2504 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2505 if (!ignore_msrs) {
a737f256 2506 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2507 return 1;
2508 } else {
a737f256 2509 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2510 data = 0;
2511 }
2512 break;
15c4a640
CO		 2513 }
2514 *pdata = data;
2515 return 0;
2516}
2517EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2518
313a3dc7
CO		 2519/*
2520 * Read or write a bunch of msrs. All parameters are kernel addresses.
2521 *
2522 * @return number of msrs set successfully.
2523 */
2524static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2525 struct kvm_msr_entry *entries,
2526 int (*do_msr)(struct kvm_vcpu *vcpu,
2527 unsigned index, u64 *data))
2528{
f656ce01 2529 int i, idx;
313a3dc7 2530
f656ce01 2531 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2532 for (i = 0; i < msrs->nmsrs; ++i)
2533 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2534 break;
f656ce01 2535 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2536
313a3dc7
CO		 2537 return i;
2538}
2539
2540/*
2541 * Read or write a bunch of msrs. Parameters are user addresses.
2542 *
2543 * @return number of msrs set successfully.
2544 */
2545static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2546 int (*do_msr)(struct kvm_vcpu *vcpu,
2547 unsigned index, u64 *data),
2548 int writeback)
2549{
2550 struct kvm_msrs msrs;
2551 struct kvm_msr_entry *entries;
2552 int r, n;
2553 unsigned size;
2554
2555 r = -EFAULT;
2556 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2557 goto out;
2558
2559 r = -E2BIG;
2560 if (msrs.nmsrs >= MAX_IO_MSRS)
2561 goto out;
2562
313a3dc7 2563 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2564 entries = memdup_user(user_msrs->entries, size);
2565 if (IS_ERR(entries)) {
2566 r = PTR_ERR(entries);
313a3dc7 2567 goto out;
ff5c2c03 2568 }
313a3dc7
CO		 2569
2570 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2571 if (r < 0)
2572 goto out_free;
2573
2574 r = -EFAULT;
2575 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2576 goto out_free;
2577
2578 r = n;
2579
2580out_free:
7a73c028 2581 kfree(entries);
313a3dc7
CO		 2582out:
2583 return r;
2584}
2585
018d00d2
ZX		 2586int kvm_dev_ioctl_check_extension(long ext)
2587{
2588 int r;
2589
2590 switch (ext) {
2591 case KVM_CAP_IRQCHIP:
2592 case KVM_CAP_HLT:
2593 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2594 case KVM_CAP_SET_TSS_ADDR:
07716717 2595 case KVM_CAP_EXT_CPUID:
9c15bb1d 2596 case KVM_CAP_EXT_EMUL_CPUID:
c8076604 2597 case KVM_CAP_CLOCKSOURCE:
7837699f 2598 case KVM_CAP_PIT:
a28e4f5a 2599 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2600 case KVM_CAP_MP_STATE:
ed848624 2601 case KVM_CAP_SYNC_MMU:
a355c85c 2602 case KVM_CAP_USER_NMI:
52d939a0 2603 case KVM_CAP_REINJECT_CONTROL:
4925663a 2604 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2605 case KVM_CAP_IRQFD:
d34e6b17 2606 case KVM_CAP_IOEVENTFD:
c5ff41ce 2607 case KVM_CAP_PIT2:
e9f42757 2608 case KVM_CAP_PIT_STATE2:
b927a3ce 2609 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2610 case KVM_CAP_XEN_HVM:
afbcf7ab 2611 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2612 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2613 case KVM_CAP_HYPERV:
10388a07 2614 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2615 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2616 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2617 case KVM_CAP_DEBUGREGS:
d2be1651 2618 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2619 case KVM_CAP_XSAVE:
344d9588 2620 case KVM_CAP_ASYNC_PF:
92a1f12d 2621 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2622 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2623 case KVM_CAP_READONLY_MEM:
5f66b620 2624 case KVM_CAP_HYPERV_TIME:
2a5bab10
AW		 2625#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2626 case KVM_CAP_ASSIGN_DEV_IRQ:
2627 case KVM_CAP_PCI_2_3:
2628#endif
018d00d2
ZX		 2629 r = 1;
2630 break;
542472b5
LV		 2631 case KVM_CAP_COALESCED_MMIO:
2632 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2633 break;
774ead3a
AK		 2634 case KVM_CAP_VAPIC:
2635 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2636 break;
f725230a 2637 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2638 r = KVM_SOFT_MAX_VCPUS;
2639 break;
2640 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2641 r = KVM_MAX_VCPUS;
2642 break;
a988b910 2643 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2644 r = KVM_USER_MEM_SLOTS;
a988b910 2645 break;
a68a6a72
MT		 2646 case KVM_CAP_PV_MMU: /* obsolete */
2647 r = 0;
2f333bcb 2648 break;
4cee4b72 2649#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2650 case KVM_CAP_IOMMU:
a1b60c1c 2651 r = iommu_present(&pci_bus_type);
62c476c7 2652 break;
4cee4b72 2653#endif
890ca9ae
HY		 2654 case KVM_CAP_MCE:
2655 r = KVM_MAX_MCE_BANKS;
2656 break;
2d5b5a66
SY		 2657 case KVM_CAP_XCRS:
2658 r = cpu_has_xsave;
2659 break;
92a1f12d
JR		 2660 case KVM_CAP_TSC_CONTROL:
2661 r = kvm_has_tsc_control;
2662 break;
4d25a066
JK		 2663 case KVM_CAP_TSC_DEADLINE_TIMER:
2664 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2665 break;
018d00d2
ZX		 2666 default:
2667 r = 0;
2668 break;
2669 }
2670 return r;
2671
2672}
2673
043405e1
CO		 2674long kvm_arch_dev_ioctl(struct file *filp,
2675 unsigned int ioctl, unsigned long arg)
2676{
2677 void __user *argp = (void __user *)arg;
2678 long r;
2679
2680 switch (ioctl) {
2681 case KVM_GET_MSR_INDEX_LIST: {
2682 struct kvm_msr_list __user *user_msr_list = argp;
2683 struct kvm_msr_list msr_list;
2684 unsigned n;
2685
2686 r = -EFAULT;
2687 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2688 goto out;
2689 n = msr_list.nmsrs;
2690 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2691 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2692 goto out;
2693 r = -E2BIG;
e125e7b6 2694 if (n < msr_list.nmsrs)
043405e1
CO		 2695 goto out;
2696 r = -EFAULT;
2697 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2698 num_msrs_to_save * sizeof(u32)))
2699 goto out;
e125e7b6 2700 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2701 &emulated_msrs,
2702 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2703 goto out;
2704 r = 0;
2705 break;
2706 }
9c15bb1d
BP		 2707 case KVM_GET_SUPPORTED_CPUID:
2708 case KVM_GET_EMULATED_CPUID: {
674eea0f
AK		 2709 struct kvm_cpuid2 __user *cpuid_arg = argp;
2710 struct kvm_cpuid2 cpuid;
2711
2712 r = -EFAULT;
2713 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2714 goto out;
9c15bb1d
BP		 2715
2716 r = kvm_dev_ioctl_get_cpuid(&cpuid, cpuid_arg->entries,
2717 ioctl);
674eea0f
AK		 2718 if (r)
2719 goto out;
2720
2721 r = -EFAULT;
2722 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2723 goto out;
2724 r = 0;
2725 break;
2726 }
890ca9ae
HY		 2727 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2728 u64 mce_cap;
2729
2730 mce_cap = KVM_MCE_CAP_SUPPORTED;
2731 r = -EFAULT;
2732 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2733 goto out;
2734 r = 0;
2735 break;
2736 }
043405e1
CO		 2737 default:
2738 r = -EINVAL;
2739 }
2740out:
2741 return r;
2742}
2743
f5f48ee1
SY		 2744static void wbinvd_ipi(void *garbage)
2745{
2746 wbinvd();
2747}
2748
2749static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2750{
e0f0bbc5 2751 return kvm_arch_has_noncoherent_dma(vcpu->kvm);
f5f48ee1
SY		 2752}
2753
313a3dc7
CO		 2754void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2755{
f5f48ee1
SY		 2756 /* Address WBINVD may be executed by guest */
2757 if (need_emulate_wbinvd(vcpu)) {
2758 if (kvm_x86_ops->has_wbinvd_exit())
2759 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2760 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2761 smp_call_function_single(vcpu->cpu,
2762 wbinvd_ipi, NULL, 1);
2763 }
2764
313a3dc7 2765 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2766
0dd6a6ed
ZA		 2767 /* Apply any externally detected TSC adjustments (due to suspend) */
2768 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2769 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2770 vcpu->arch.tsc_offset_adjustment = 0;
2771 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2772 }
8f6055cb 2773
48434c20 2774 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2775 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2776 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2777 if (tsc_delta < 0)
2778 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2779 if (check_tsc_unstable()) {
b183aa58
ZA		 2780 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2781 vcpu->arch.last_guest_tsc);
2782 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2783 vcpu->arch.tsc_catchup = 1;
c285545f 2784 }
d98d07ca
MT		 2785 /*
2786 * On a host with synchronized TSC, there is no need to update
2787 * kvmclock on vcpu->cpu migration
2788 */
2789 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2790 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2791 if (vcpu->cpu != cpu)
2792 kvm_migrate_timers(vcpu);
e48672fa 2793 vcpu->cpu = cpu;
6b7d7e76 2794 }
c9aaa895
GC		 2795
2796 accumulate_steal_time(vcpu);
2797 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2798}
2799
2800void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2801{
02daab21 2802 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2803 kvm_put_guest_fpu(vcpu);
6f526ec5 2804 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2805}
2806
313a3dc7
CO		 2807static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2808 struct kvm_lapic_state *s)
2809{
5a71785d 2810 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2811 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2812
2813 return 0;
2814}
2815
2816static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2817 struct kvm_lapic_state *s)
2818{
64eb0620 2819 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2820 update_cr8_intercept(vcpu);
313a3dc7
CO		 2821
2822 return 0;
2823}
2824
f77bc6a4
ZX		 2825static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2826 struct kvm_interrupt *irq)
2827{
02cdb50f 2828 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2829 return -EINVAL;
2830 if (irqchip_in_kernel(vcpu->kvm))
2831 return -ENXIO;
f77bc6a4 2832
66fd3f7f 2833 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2834 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2835
f77bc6a4
ZX		 2836 return 0;
2837}
2838
c4abb7c9
JK		 2839static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2840{
c4abb7c9 2841 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2842
2843 return 0;
2844}
2845
b209749f
AK		 2846static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2847 struct kvm_tpr_access_ctl *tac)
2848{
2849 if (tac->flags)
2850 return -EINVAL;
2851 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2852 return 0;
2853}
2854
890ca9ae
HY		 2855static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2856 u64 mcg_cap)
2857{
2858 int r;
2859 unsigned bank_num = mcg_cap & 0xff, bank;
2860
2861 r = -EINVAL;
a9e38c3e 2862 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2863 goto out;
2864 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2865 goto out;
2866 r = 0;
2867 vcpu->arch.mcg_cap = mcg_cap;
2868 /* Init IA32_MCG_CTL to all 1s */
2869 if (mcg_cap & MCG_CTL_P)
2870 vcpu->arch.mcg_ctl = ~(u64)0;
2871 /* Init IA32_MCi_CTL to all 1s */
2872 for (bank = 0; bank < bank_num; bank++)
2873 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2874out:
2875 return r;
2876}
2877
2878static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2879 struct kvm_x86_mce *mce)
2880{
2881 u64 mcg_cap = vcpu->arch.mcg_cap;
2882 unsigned bank_num = mcg_cap & 0xff;
2883 u64 *banks = vcpu->arch.mce_banks;
2884
2885 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2886 return -EINVAL;
2887 /*
2888 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2889 * reporting is disabled
2890 */
2891 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2892 vcpu->arch.mcg_ctl != ~(u64)0)
2893 return 0;
2894 banks += 4 * mce->bank;
2895 /*
2896 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2897 * reporting is disabled for the bank
2898 */
2899 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2900 return 0;
2901 if (mce->status & MCI_STATUS_UC) {
2902 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2903 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2904 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2905 return 0;
2906 }
2907 if (banks[1] & MCI_STATUS_VAL)
2908 mce->status |= MCI_STATUS_OVER;
2909 banks[2] = mce->addr;
2910 banks[3] = mce->misc;
2911 vcpu->arch.mcg_status = mce->mcg_status;
2912 banks[1] = mce->status;
2913 kvm_queue_exception(vcpu, MC_VECTOR);
2914 } else if (!(banks[1] & MCI_STATUS_VAL)
2915 || !(banks[1] & MCI_STATUS_UC)) {
2916 if (banks[1] & MCI_STATUS_VAL)
2917 mce->status |= MCI_STATUS_OVER;
2918 banks[2] = mce->addr;
2919 banks[3] = mce->misc;
2920 banks[1] = mce->status;
2921 } else
2922 banks[1] |= MCI_STATUS_OVER;
2923 return 0;
2924}
2925
3cfc3092
JK		 2926static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2927 struct kvm_vcpu_events *events)
2928{
7460fb4a 2929 process_nmi(vcpu);
03b82a30
JK		 2930 events->exception.injected =
2931 vcpu->arch.exception.pending &&
2932 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2933 events->exception.nr = vcpu->arch.exception.nr;
2934 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2935 events->exception.pad = 0;
3cfc3092
JK		 2936 events->exception.error_code = vcpu->arch.exception.error_code;
2937
03b82a30
JK		 2938 events->interrupt.injected =
2939 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2940 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2941 events->interrupt.soft = 0;
48005f64
JK		 2942 events->interrupt.shadow =
2943 kvm_x86_ops->get_interrupt_shadow(vcpu,
2944 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2945
2946 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2947 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2948 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2949 events->nmi.pad = 0;
3cfc3092 2950
66450a21 2951 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2952
dab4b911 2953 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2954 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2955 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2956}
2957
2958static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2959 struct kvm_vcpu_events *events)
2960{
dab4b911 2961 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2962 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2963 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2964 return -EINVAL;
2965
7460fb4a 2966 process_nmi(vcpu);
3cfc3092
JK		 2967 vcpu->arch.exception.pending = events->exception.injected;
2968 vcpu->arch.exception.nr = events->exception.nr;
2969 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2970 vcpu->arch.exception.error_code = events->exception.error_code;
2971
2972 vcpu->arch.interrupt.pending = events->interrupt.injected;
2973 vcpu->arch.interrupt.nr = events->interrupt.nr;
2974 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2975 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2976 kvm_x86_ops->set_interrupt_shadow(vcpu,
2977 events->interrupt.shadow);
3cfc3092
JK		 2978
2979 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2980 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2981 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2982 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2983
66450a21
JK		 2984 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2985 kvm_vcpu_has_lapic(vcpu))
2986 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2987
3842d135
AK		 2988 kvm_make_request(KVM_REQ_EVENT, vcpu);
2989
3cfc3092
JK		 2990 return 0;
2991}
2992
a1efbe77
JK		 2993static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2994 struct kvm_debugregs *dbgregs)
2995{
73aaf249
JK		 2996 unsigned long val;
2997
a1efbe77 2998 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
73aaf249
JK		 2999 _kvm_get_dr(vcpu, 6, &val);
3000 dbgregs->dr6 = val;
a1efbe77
JK		 3001 dbgregs->dr7 = vcpu->arch.dr7;
3002 dbgregs->flags = 0;
97e69aa6 3003 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 3004}
3005
3006static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
3007 struct kvm_debugregs *dbgregs)
3008{
3009 if (dbgregs->flags)
3010 return -EINVAL;
3011
a1efbe77
JK		 3012 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
3013 vcpu->arch.dr6 = dbgregs->dr6;
73aaf249 3014 kvm_update_dr6(vcpu);
a1efbe77 3015 vcpu->arch.dr7 = dbgregs->dr7;
9926c9fd 3016 kvm_update_dr7(vcpu);
a1efbe77 3017
a1efbe77
JK		 3018 return 0;
3019}
3020
2d5b5a66
SY		 3021static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
3022 struct kvm_xsave *guest_xsave)
3023{
4344ee98 3024 if (cpu_has_xsave) {
2d5b5a66
SY		 3025 memcpy(guest_xsave->region,
3026 &vcpu->arch.guest_fpu.state->xsave,
4344ee98
PB		 3027 vcpu->arch.guest_xstate_size);
3028 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
3029 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
3030 } else {
2d5b5a66
SY		 3031 memcpy(guest_xsave->region,
3032 &vcpu->arch.guest_fpu.state->fxsave,
3033 sizeof(struct i387_fxsave_struct));
3034 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
3035 XSTATE_FPSSE;
3036 }
3037}
3038
3039static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3040 struct kvm_xsave *guest_xsave)
3041{
3042 u64 xstate_bv =
3043 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3044
d7876f1b
PB		 3045 if (cpu_has_xsave) {
3046 /*
3047 * Here we allow setting states that are not present in
3048 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3049 * with old userspace.
3050 */
3051 if (xstate_bv & ~KVM_SUPPORTED_XCR0)
3052 return -EINVAL;
3053 if (xstate_bv & ~host_xcr0)
3054 return -EINVAL;
2d5b5a66 3055 memcpy(&vcpu->arch.guest_fpu.state->xsave,
4344ee98 3056 guest_xsave->region, vcpu->arch.guest_xstate_size);
d7876f1b 3057 } else {
2d5b5a66
SY		 3058 if (xstate_bv & ~XSTATE_FPSSE)
3059 return -EINVAL;
3060 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3061 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3062 }
3063 return 0;
3064}
3065
3066static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3067 struct kvm_xcrs *guest_xcrs)
3068{
3069 if (!cpu_has_xsave) {
3070 guest_xcrs->nr_xcrs = 0;
3071 return;
3072 }
3073
3074 guest_xcrs->nr_xcrs = 1;
3075 guest_xcrs->flags = 0;
3076 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3077 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3078}
3079
3080static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3081 struct kvm_xcrs *guest_xcrs)
3082{
3083 int i, r = 0;
3084
3085 if (!cpu_has_xsave)
3086 return -EINVAL;
3087
3088 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3089 return -EINVAL;
3090
3091 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3092 /* Only support XCR0 currently */
c67a04cb 3093 if (guest_xcrs->xcrs[i].xcr == XCR_XFEATURE_ENABLED_MASK) {
2d5b5a66 3094 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
c67a04cb 3095 guest_xcrs->xcrs[i].value);
2d5b5a66
SY		 3096 break;
3097 }
3098 if (r)
3099 r = -EINVAL;
3100 return r;
3101}
3102
1c0b28c2
EM		 3103/*
3104 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3105 * stopped by the hypervisor. This function will be called from the host only.
3106 * EINVAL is returned when the host attempts to set the flag for a guest that
3107 * does not support pv clocks.
3108 */
3109static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3110{
0b79459b 3111 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3112 return -EINVAL;
51d59c6b 3113 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3114 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3115 return 0;
3116}
3117
313a3dc7
CO		 3118long kvm_arch_vcpu_ioctl(struct file *filp,
3119 unsigned int ioctl, unsigned long arg)
3120{
3121 struct kvm_vcpu *vcpu = filp->private_data;
3122 void __user *argp = (void __user *)arg;
3123 int r;
d1ac91d8
AK		 3124 union {
3125 struct kvm_lapic_state *lapic;
3126 struct kvm_xsave *xsave;
3127 struct kvm_xcrs *xcrs;
3128 void *buffer;
3129 } u;
3130
3131 u.buffer = NULL;
313a3dc7
CO		 3132 switch (ioctl) {
3133 case KVM_GET_LAPIC: {
2204ae3c
MT		 3134 r = -EINVAL;
3135 if (!vcpu->arch.apic)
3136 goto out;
d1ac91d8 3137 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3138
b772ff36 3139 r = -ENOMEM;
d1ac91d8 3140 if (!u.lapic)
b772ff36 3141 goto out;
d1ac91d8 3142 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3143 if (r)
3144 goto out;
3145 r = -EFAULT;
d1ac91d8 3146 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3147 goto out;
3148 r = 0;
3149 break;
3150 }
3151 case KVM_SET_LAPIC: {
2204ae3c
MT		 3152 r = -EINVAL;
3153 if (!vcpu->arch.apic)
3154 goto out;
ff5c2c03 3155 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3156 if (IS_ERR(u.lapic))
3157 return PTR_ERR(u.lapic);
ff5c2c03 3158
d1ac91d8 3159 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3160 break;
3161 }
f77bc6a4
ZX		 3162 case KVM_INTERRUPT: {
3163 struct kvm_interrupt irq;
3164
3165 r = -EFAULT;
3166 if (copy_from_user(&irq, argp, sizeof irq))
3167 goto out;
3168 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3169 break;
3170 }
c4abb7c9
JK		 3171 case KVM_NMI: {
3172 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3173 break;
3174 }
313a3dc7
CO		 3175 case KVM_SET_CPUID: {
3176 struct kvm_cpuid __user *cpuid_arg = argp;
3177 struct kvm_cpuid cpuid;
3178
3179 r = -EFAULT;
3180 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3181 goto out;
3182 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3183 break;
3184 }
07716717
DK		 3185 case KVM_SET_CPUID2: {
3186 struct kvm_cpuid2 __user *cpuid_arg = argp;
3187 struct kvm_cpuid2 cpuid;
3188
3189 r = -EFAULT;
3190 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3191 goto out;
3192 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3193 cpuid_arg->entries);
07716717
DK		 3194 break;
3195 }
3196 case KVM_GET_CPUID2: {
3197 struct kvm_cpuid2 __user *cpuid_arg = argp;
3198 struct kvm_cpuid2 cpuid;
3199
3200 r = -EFAULT;
3201 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3202 goto out;
3203 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3204 cpuid_arg->entries);
07716717
DK		 3205 if (r)
3206 goto out;
3207 r = -EFAULT;
3208 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3209 goto out;
3210 r = 0;
3211 break;
3212 }
313a3dc7
CO		 3213 case KVM_GET_MSRS:
3214 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3215 break;
3216 case KVM_SET_MSRS:
3217 r = msr_io(vcpu, argp, do_set_msr, 0);
3218 break;
b209749f
AK		 3219 case KVM_TPR_ACCESS_REPORTING: {
3220 struct kvm_tpr_access_ctl tac;
3221
3222 r = -EFAULT;
3223 if (copy_from_user(&tac, argp, sizeof tac))
3224 goto out;
3225 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3226 if (r)
3227 goto out;
3228 r = -EFAULT;
3229 if (copy_to_user(argp, &tac, sizeof tac))
3230 goto out;
3231 r = 0;
3232 break;
3233 };
b93463aa
AK		 3234 case KVM_SET_VAPIC_ADDR: {
3235 struct kvm_vapic_addr va;
3236
3237 r = -EINVAL;
3238 if (!irqchip_in_kernel(vcpu->kvm))
3239 goto out;
3240 r = -EFAULT;
3241 if (copy_from_user(&va, argp, sizeof va))
3242 goto out;
fda4e2e8 3243 r = kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
b93463aa
AK		 3244 break;
3245 }
890ca9ae
HY		 3246 case KVM_X86_SETUP_MCE: {
3247 u64 mcg_cap;
3248
3249 r = -EFAULT;
3250 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3251 goto out;
3252 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3253 break;
3254 }
3255 case KVM_X86_SET_MCE: {
3256 struct kvm_x86_mce mce;
3257
3258 r = -EFAULT;
3259 if (copy_from_user(&mce, argp, sizeof mce))
3260 goto out;
3261 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3262 break;
3263 }
3cfc3092
JK		 3264 case KVM_GET_VCPU_EVENTS: {
3265 struct kvm_vcpu_events events;
3266
3267 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3268
3269 r = -EFAULT;
3270 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3271 break;
3272 r = 0;
3273 break;
3274 }
3275 case KVM_SET_VCPU_EVENTS: {
3276 struct kvm_vcpu_events events;
3277
3278 r = -EFAULT;
3279 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3280 break;
3281
3282 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3283 break;
3284 }
a1efbe77
JK		 3285 case KVM_GET_DEBUGREGS: {
3286 struct kvm_debugregs dbgregs;
3287
3288 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3289
3290 r = -EFAULT;
3291 if (copy_to_user(argp, &dbgregs,
3292 sizeof(struct kvm_debugregs)))
3293 break;
3294 r = 0;
3295 break;
3296 }
3297 case KVM_SET_DEBUGREGS: {
3298 struct kvm_debugregs dbgregs;
3299
3300 r = -EFAULT;
3301 if (copy_from_user(&dbgregs, argp,
3302 sizeof(struct kvm_debugregs)))
3303 break;
3304
3305 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3306 break;
3307 }
2d5b5a66 3308 case KVM_GET_XSAVE: {
d1ac91d8 3309 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3310 r = -ENOMEM;
d1ac91d8 3311 if (!u.xsave)
2d5b5a66
SY		 3312 break;
3313
d1ac91d8 3314 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3315
3316 r = -EFAULT;
d1ac91d8 3317 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3318 break;
3319 r = 0;
3320 break;
3321 }
3322 case KVM_SET_XSAVE: {
ff5c2c03 3323 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3324 if (IS_ERR(u.xsave))
3325 return PTR_ERR(u.xsave);
2d5b5a66 3326
d1ac91d8 3327 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3328 break;
3329 }
3330 case KVM_GET_XCRS: {
d1ac91d8 3331 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3332 r = -ENOMEM;
d1ac91d8 3333 if (!u.xcrs)
2d5b5a66
SY		 3334 break;
3335
d1ac91d8 3336 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3337
3338 r = -EFAULT;
d1ac91d8 3339 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3340 sizeof(struct kvm_xcrs)))
3341 break;
3342 r = 0;
3343 break;
3344 }
3345 case KVM_SET_XCRS: {
ff5c2c03 3346 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3347 if (IS_ERR(u.xcrs))
3348 return PTR_ERR(u.xcrs);
2d5b5a66 3349
d1ac91d8 3350 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3351 break;
3352 }
92a1f12d
JR		 3353 case KVM_SET_TSC_KHZ: {
3354 u32 user_tsc_khz;
3355
3356 r = -EINVAL;
92a1f12d
JR		 3357 user_tsc_khz = (u32)arg;
3358
3359 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3360 goto out;
3361
cc578287
ZA		 3362 if (user_tsc_khz == 0)
3363 user_tsc_khz = tsc_khz;
3364
3365 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3366
3367 r = 0;
3368 goto out;
3369 }
3370 case KVM_GET_TSC_KHZ: {
cc578287 3371 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3372 goto out;
3373 }
1c0b28c2
EM		 3374 case KVM_KVMCLOCK_CTRL: {
3375 r = kvm_set_guest_paused(vcpu);
3376 goto out;
3377 }
313a3dc7
CO		 3378 default:
3379 r = -EINVAL;
3380 }
3381out:
d1ac91d8 3382 kfree(u.buffer);
313a3dc7
CO		 3383 return r;
3384}
3385
5b1c1493
CO		 3386int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3387{
3388 return VM_FAULT_SIGBUS;
3389}
3390
1fe779f8
CO		 3391static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3392{
3393 int ret;
3394
3395 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3396 return -EINVAL;
1fe779f8
CO		 3397 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3398 return ret;
3399}
3400
b927a3ce
SY		 3401static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3402 u64 ident_addr)
3403{
3404 kvm->arch.ept_identity_map_addr = ident_addr;
3405 return 0;
3406}
3407
1fe779f8
CO		 3408static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3409 u32 kvm_nr_mmu_pages)
3410{
3411 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3412 return -EINVAL;
3413
79fac95e 3414 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3415
3416 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3417 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3418
79fac95e 3419 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3420 return 0;
3421}
3422
3423static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3424{
39de71ec 3425 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3426}
3427
1fe779f8
CO		 3428static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3429{
3430 int r;
3431
3432 r = 0;
3433 switch (chip->chip_id) {
3434 case KVM_IRQCHIP_PIC_MASTER:
3435 memcpy(&chip->chip.pic,
3436 &pic_irqchip(kvm)->pics[0],
3437 sizeof(struct kvm_pic_state));
3438 break;
3439 case KVM_IRQCHIP_PIC_SLAVE:
3440 memcpy(&chip->chip.pic,
3441 &pic_irqchip(kvm)->pics[1],
3442 sizeof(struct kvm_pic_state));
3443 break;
3444 case KVM_IRQCHIP_IOAPIC:
eba0226b 3445 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3446 break;
3447 default:
3448 r = -EINVAL;
3449 break;
3450 }
3451 return r;
3452}
3453
3454static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3455{
3456 int r;
3457
3458 r = 0;
3459 switch (chip->chip_id) {
3460 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3461 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3462 memcpy(&pic_irqchip(kvm)->pics[0],
3463 &chip->chip.pic,
3464 sizeof(struct kvm_pic_state));
f4f51050 3465 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3466 break;
3467 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3468 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3469 memcpy(&pic_irqchip(kvm)->pics[1],
3470 &chip->chip.pic,
3471 sizeof(struct kvm_pic_state));
f4f51050 3472 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3473 break;
3474 case KVM_IRQCHIP_IOAPIC:
eba0226b 3475 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3476 break;
3477 default:
3478 r = -EINVAL;
3479 break;
3480 }
3481 kvm_pic_update_irq(pic_irqchip(kvm));
3482 return r;
3483}
3484
e0f63cb9
SY		 3485static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3486{
3487 int r = 0;
3488
894a9c55 3489 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3490 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3491 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3492 return r;
3493}
3494
3495static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3496{
3497 int r = 0;
3498
894a9c55 3499 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3500 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3501 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3502 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3503 return r;
3504}
3505
3506static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3507{
3508 int r = 0;
3509
3510 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3511 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3512 sizeof(ps->channels));
3513 ps->flags = kvm->arch.vpit->pit_state.flags;
3514 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3515 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3516 return r;
3517}
3518
3519static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3520{
3521 int r = 0, start = 0;
3522 u32 prev_legacy, cur_legacy;
3523 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3524 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3525 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3526 if (!prev_legacy && cur_legacy)
3527 start = 1;
3528 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3529 sizeof(kvm->arch.vpit->pit_state.channels));
3530 kvm->arch.vpit->pit_state.flags = ps->flags;
3531 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3532 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3533 return r;
3534}
3535
52d939a0
MT		 3536static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3537 struct kvm_reinject_control *control)
3538{
3539 if (!kvm->arch.vpit)
3540 return -ENXIO;
894a9c55 3541 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3542 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3543 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3544 return 0;
3545}
3546
95d4c16c 3547/**
60c34612
TY		 3548 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3549 * @kvm: kvm instance
3550 * @log: slot id and address to which we copy the log
95d4c16c 3551 *
60c34612
TY		 3552 * We need to keep it in mind that VCPU threads can write to the bitmap
3553 * concurrently. So, to avoid losing data, we keep the following order for
3554 * each bit:
95d4c16c 3555 *
60c34612
TY		 3556 * 1. Take a snapshot of the bit and clear it if needed.
3557 * 2. Write protect the corresponding page.
3558 * 3. Flush TLB's if needed.
3559 * 4. Copy the snapshot to the userspace.
95d4c16c 3560 *
60c34612
TY		 3561 * Between 2 and 3, the guest may write to the page using the remaining TLB
3562 * entry. This is not a problem because the page will be reported dirty at
3563 * step 4 using the snapshot taken before and step 3 ensures that successive
3564 * writes will be logged for the next call.
5bb064dc 3565 */
60c34612 3566int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3567{
7850ac54 3568 int r;
5bb064dc 3569 struct kvm_memory_slot *memslot;
60c34612
TY		 3570 unsigned long n, i;
3571 unsigned long *dirty_bitmap;
3572 unsigned long *dirty_bitmap_buffer;
3573 bool is_dirty = false;
5bb064dc 3574
79fac95e 3575 mutex_lock(&kvm->slots_lock);
5bb064dc 3576
b050b015 3577 r = -EINVAL;
bbacc0c1 3578 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3579 goto out;
3580
28a37544 3581 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3582
3583 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3584 r = -ENOENT;
60c34612 3585 if (!dirty_bitmap)
b050b015
MT		 3586 goto out;
3587
87bf6e7d 3588 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3589
60c34612
TY		 3590 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3591 memset(dirty_bitmap_buffer, 0, n);
b050b015 3592
60c34612 3593 spin_lock(&kvm->mmu_lock);
b050b015 3594
60c34612
TY		 3595 for (i = 0; i < n / sizeof(long); i++) {
3596 unsigned long mask;
3597 gfn_t offset;
cdfca7b3 3598
60c34612
TY		 3599 if (!dirty_bitmap[i])
3600 continue;
b050b015 3601
60c34612 3602 is_dirty = true;
914ebccd 3603
60c34612
TY		 3604 mask = xchg(&dirty_bitmap[i], 0);
3605 dirty_bitmap_buffer[i] = mask;
edde99ce 3606
60c34612
TY		 3607 offset = i * BITS_PER_LONG;
3608 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3609 }
60c34612
TY		 3610 if (is_dirty)
3611 kvm_flush_remote_tlbs(kvm);
3612
3613 spin_unlock(&kvm->mmu_lock);
3614
3615 r = -EFAULT;
3616 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3617 goto out;
b050b015 3618
5bb064dc
ZX		 3619 r = 0;
3620out:
79fac95e 3621 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3622 return r;
3623}
3624
aa2fbe6d
YZ		 3625int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3626 bool line_status)
23d43cf9
CD		 3627{
3628 if (!irqchip_in_kernel(kvm))
3629 return -ENXIO;
3630
3631 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3632 irq_event->irq, irq_event->level,
3633 line_status);
23d43cf9
CD		 3634 return 0;
3635}
3636
1fe779f8
CO		 3637long kvm_arch_vm_ioctl(struct file *filp,
3638 unsigned int ioctl, unsigned long arg)
3639{
3640 struct kvm *kvm = filp->private_data;
3641 void __user *argp = (void __user *)arg;
367e1319 3642 int r = -ENOTTY;
f0d66275
DH		 3643 /*
3644 * This union makes it completely explicit to gcc-3.x
3645 * that these two variables' stack usage should be
3646 * combined, not added together.
3647 */
3648 union {
3649 struct kvm_pit_state ps;
e9f42757 3650 struct kvm_pit_state2 ps2;
c5ff41ce 3651 struct kvm_pit_config pit_config;
f0d66275 3652 } u;
1fe779f8
CO		 3653
3654 switch (ioctl) {
3655 case KVM_SET_TSS_ADDR:
3656 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3657 break;
b927a3ce
SY		 3658 case KVM_SET_IDENTITY_MAP_ADDR: {
3659 u64 ident_addr;
3660
3661 r = -EFAULT;
3662 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3663 goto out;
3664 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3665 break;
3666 }
1fe779f8
CO		 3667 case KVM_SET_NR_MMU_PAGES:
3668 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3669 break;
3670 case KVM_GET_NR_MMU_PAGES:
3671 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3672 break;
3ddea128
MT		 3673 case KVM_CREATE_IRQCHIP: {
3674 struct kvm_pic *vpic;
3675
3676 mutex_lock(&kvm->lock);
3677 r = -EEXIST;
3678 if (kvm->arch.vpic)
3679 goto create_irqchip_unlock;
3e515705
AK		 3680 r = -EINVAL;
3681 if (atomic_read(&kvm->online_vcpus))
3682 goto create_irqchip_unlock;
1fe779f8 3683 r = -ENOMEM;
3ddea128
MT		 3684 vpic = kvm_create_pic(kvm);
3685 if (vpic) {
1fe779f8
CO		 3686 r = kvm_ioapic_init(kvm);
3687 if (r) {
175504cd 3688 mutex_lock(&kvm->slots_lock);
72bb2fcd 3689 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3690 &vpic->dev_master);
3691 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3692 &vpic->dev_slave);
3693 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3694 &vpic->dev_eclr);
175504cd 3695 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3696 kfree(vpic);
3697 goto create_irqchip_unlock;
1fe779f8
CO		 3698 }
3699 } else
3ddea128
MT		 3700 goto create_irqchip_unlock;
3701 smp_wmb();
3702 kvm->arch.vpic = vpic;
3703 smp_wmb();
399ec807
AK		 3704 r = kvm_setup_default_irq_routing(kvm);
3705 if (r) {
175504cd 3706 mutex_lock(&kvm->slots_lock);
3ddea128 3707 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3708 kvm_ioapic_destroy(kvm);
3709 kvm_destroy_pic(kvm);
3ddea128 3710 mutex_unlock(&kvm->irq_lock);
175504cd 3711 mutex_unlock(&kvm->slots_lock);
399ec807 3712 }
3ddea128
MT		 3713 create_irqchip_unlock:
3714 mutex_unlock(&kvm->lock);
1fe779f8 3715 break;
3ddea128 3716 }
7837699f 3717 case KVM_CREATE_PIT:
c5ff41ce
JK		 3718 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3719 goto create_pit;
3720 case KVM_CREATE_PIT2:
3721 r = -EFAULT;
3722 if (copy_from_user(&u.pit_config, argp,
3723 sizeof(struct kvm_pit_config)))
3724 goto out;
3725 create_pit:
79fac95e 3726 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3727 r = -EEXIST;
3728 if (kvm->arch.vpit)
3729 goto create_pit_unlock;
7837699f 3730 r = -ENOMEM;
c5ff41ce 3731 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3732 if (kvm->arch.vpit)
3733 r = 0;
269e05e4 3734 create_pit_unlock:
79fac95e 3735 mutex_unlock(&kvm->slots_lock);
7837699f 3736 break;
1fe779f8
CO		 3737 case KVM_GET_IRQCHIP: {
3738 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3739 struct kvm_irqchip *chip;
1fe779f8 3740
ff5c2c03
SL		 3741 chip = memdup_user(argp, sizeof(*chip));
3742 if (IS_ERR(chip)) {
3743 r = PTR_ERR(chip);
1fe779f8 3744 goto out;
ff5c2c03
SL		 3745 }
3746
1fe779f8
CO		 3747 r = -ENXIO;
3748 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3749 goto get_irqchip_out;
3750 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3751 if (r)
f0d66275 3752 goto get_irqchip_out;
1fe779f8 3753 r = -EFAULT;
f0d66275
DH		 3754 if (copy_to_user(argp, chip, sizeof *chip))
3755 goto get_irqchip_out;
1fe779f8 3756 r = 0;
f0d66275
DH		 3757 get_irqchip_out:
3758 kfree(chip);
1fe779f8
CO		 3759 break;
3760 }
3761 case KVM_SET_IRQCHIP: {
3762 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3763 struct kvm_irqchip *chip;
1fe779f8 3764
ff5c2c03
SL		 3765 chip = memdup_user(argp, sizeof(*chip));
3766 if (IS_ERR(chip)) {
3767 r = PTR_ERR(chip);
1fe779f8 3768 goto out;
ff5c2c03
SL		 3769 }
3770
1fe779f8
CO		 3771 r = -ENXIO;
3772 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3773 goto set_irqchip_out;
3774 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3775 if (r)
f0d66275 3776 goto set_irqchip_out;
1fe779f8 3777 r = 0;
f0d66275
DH		 3778 set_irqchip_out:
3779 kfree(chip);
1fe779f8
CO		 3780 break;
3781 }
e0f63cb9 3782 case KVM_GET_PIT: {
e0f63cb9 3783 r = -EFAULT;
f0d66275 3784 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3785 goto out;
3786 r = -ENXIO;
3787 if (!kvm->arch.vpit)
3788 goto out;
f0d66275 3789 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3790 if (r)
3791 goto out;
3792 r = -EFAULT;
f0d66275 3793 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3794 goto out;
3795 r = 0;
3796 break;
3797 }
3798 case KVM_SET_PIT: {
e0f63cb9 3799 r = -EFAULT;
f0d66275 3800 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3801 goto out;
3802 r = -ENXIO;
3803 if (!kvm->arch.vpit)
3804 goto out;
f0d66275 3805 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3806 break;
3807 }
e9f42757
BK		 3808 case KVM_GET_PIT2: {
3809 r = -ENXIO;
3810 if (!kvm->arch.vpit)
3811 goto out;
3812 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3813 if (r)
3814 goto out;
3815 r = -EFAULT;
3816 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3817 goto out;
3818 r = 0;
3819 break;
3820 }
3821 case KVM_SET_PIT2: {
3822 r = -EFAULT;
3823 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3824 goto out;
3825 r = -ENXIO;
3826 if (!kvm->arch.vpit)
3827 goto out;
3828 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3829 break;
3830 }
52d939a0
MT		 3831 case KVM_REINJECT_CONTROL: {
3832 struct kvm_reinject_control control;
3833 r = -EFAULT;
3834 if (copy_from_user(&control, argp, sizeof(control)))
3835 goto out;
3836 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3837 break;
3838 }
ffde22ac
ES		 3839 case KVM_XEN_HVM_CONFIG: {
3840 r = -EFAULT;
3841 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3842 sizeof(struct kvm_xen_hvm_config)))
3843 goto out;
3844 r = -EINVAL;
3845 if (kvm->arch.xen_hvm_config.flags)
3846 goto out;
3847 r = 0;
3848 break;
3849 }
afbcf7ab 3850 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3851 struct kvm_clock_data user_ns;
3852 u64 now_ns;
3853 s64 delta;
3854
3855 r = -EFAULT;
3856 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3857 goto out;
3858
3859 r = -EINVAL;
3860 if (user_ns.flags)
3861 goto out;
3862
3863 r = 0;
395c6b0a 3864 local_irq_disable();
759379dd 3865 now_ns = get_kernel_ns();
afbcf7ab 3866 delta = user_ns.clock - now_ns;
395c6b0a 3867 local_irq_enable();
afbcf7ab 3868 kvm->arch.kvmclock_offset = delta;
2e762ff7 3869 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3870 break;
3871 }
3872 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3873 struct kvm_clock_data user_ns;
3874 u64 now_ns;
3875
395c6b0a 3876 local_irq_disable();
759379dd 3877 now_ns = get_kernel_ns();
afbcf7ab 3878 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3879 local_irq_enable();
afbcf7ab 3880 user_ns.flags = 0;
97e69aa6 3881 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3882
3883 r = -EFAULT;
3884 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3885 goto out;
3886 r = 0;
3887 break;
3888 }
3889
1fe779f8
CO		 3890 default:
3891 ;
3892 }
3893out:
3894 return r;
3895}
3896
a16b043c 3897static void kvm_init_msr_list(void)
043405e1
CO		 3898{
3899 u32 dummy[2];
3900 unsigned i, j;
3901
e3267cbb
GC		 3902 /* skip the first msrs in the list. KVM-specific */
3903 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3904 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3905 continue;
3906 if (j < i)
3907 msrs_to_save[j] = msrs_to_save[i];
3908 j++;
3909 }
3910 num_msrs_to_save = j;
3911}
3912
bda9020e
MT		 3913static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3914 const void *v)
bbd9b64e 3915{
70252a10
AK		 3916 int handled = 0;
3917 int n;
3918
3919 do {
3920 n = min(len, 8);
3921 if (!(vcpu->arch.apic &&
3922 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3923 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3924 break;
3925 handled += n;
3926 addr += n;
3927 len -= n;
3928 v += n;
3929 } while (len);
bbd9b64e 3930
70252a10 3931 return handled;
bbd9b64e
CO		 3932}
3933
bda9020e 3934static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3935{
70252a10
AK		 3936 int handled = 0;
3937 int n;
3938
3939 do {
3940 n = min(len, 8);
3941 if (!(vcpu->arch.apic &&
3942 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3943 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3944 break;
3945 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3946 handled += n;
3947 addr += n;
3948 len -= n;
3949 v += n;
3950 } while (len);
bbd9b64e 3951
70252a10 3952 return handled;
bbd9b64e
CO		 3953}
3954
2dafc6c2
GN		 3955static void kvm_set_segment(struct kvm_vcpu *vcpu,
3956 struct kvm_segment *var, int seg)
3957{
3958 kvm_x86_ops->set_segment(vcpu, var, seg);
3959}
3960
3961void kvm_get_segment(struct kvm_vcpu *vcpu,
3962 struct kvm_segment *var, int seg)
3963{
3964 kvm_x86_ops->get_segment(vcpu, var, seg);
3965}
3966
e459e322 3967gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3968{
3969 gpa_t t_gpa;
ab9ae313 3970 struct x86_exception exception;
02f59dc9
JR		 3971
3972 BUG_ON(!mmu_is_nested(vcpu));
3973
3974 /* NPT walks are always user-walks */
3975 access |= PFERR_USER_MASK;
ab9ae313 3976 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3977
3978 return t_gpa;
3979}
3980
ab9ae313
AK		 3981gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3982 struct x86_exception *exception)
1871c602
GN		 3983{
3984 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3985 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3986}
3987
ab9ae313
AK		 3988 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3989 struct x86_exception *exception)
1871c602
GN		 3990{
3991 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3992 access |= PFERR_FETCH_MASK;
ab9ae313 3993 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3994}
3995
ab9ae313
AK		 3996gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3997 struct x86_exception *exception)
1871c602
GN		 3998{
3999 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
4000 access |= PFERR_WRITE_MASK;
ab9ae313 4001 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 4002}
4003
4004/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 4005gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
4006 struct x86_exception *exception)
1871c602 4007{
ab9ae313 4008 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 4009}
4010
4011static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
4012 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 4013 struct x86_exception *exception)
bbd9b64e
CO		 4014{
4015 void *data = val;
10589a46 4016 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 4017
4018 while (bytes) {
14dfe855 4019 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 4020 exception);
bbd9b64e 4021 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 4022 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 4023 int ret;
4024
bcc55cba 4025 if (gpa == UNMAPPED_GVA)
ab9ae313 4026 return X86EMUL_PROPAGATE_FAULT;
77c2002e 4027 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 4028 if (ret < 0) {
c3cd7ffa 4029 r = X86EMUL_IO_NEEDED;
10589a46
MT		 4030 goto out;
4031 }
bbd9b64e 4032
77c2002e
IE		 4033 bytes -= toread;
4034 data += toread;
4035 addr += toread;
bbd9b64e 4036 }
10589a46 4037out:
10589a46 4038 return r;
bbd9b64e 4039}
77c2002e 4040
1871c602 4041/* used for instruction fetching */
0f65dd70
AK		 4042static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4043 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4044 struct x86_exception *exception)
1871c602 4045{
0f65dd70 4046 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4047 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4048
1871c602 4049 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 4050 access | PFERR_FETCH_MASK,
4051 exception);
1871c602
GN		 4052}
4053
064aea77 4054int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4055 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4056 struct x86_exception *exception)
1871c602 4057{
0f65dd70 4058 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4059 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4060
1871c602 4061 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4062 exception);
1871c602 4063}
064aea77 4064EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4065
0f65dd70
AK		 4066static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4067 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4068 struct x86_exception *exception)
1871c602 4069{
0f65dd70 4070 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4071 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4072}
4073
6a4d7550 4074int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4075 gva_t addr, void *val,
2dafc6c2 4076 unsigned int bytes,
bcc55cba 4077 struct x86_exception *exception)
77c2002e 4078{
0f65dd70 4079 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4080 void *data = val;
4081 int r = X86EMUL_CONTINUE;
4082
4083 while (bytes) {
14dfe855
JR		 4084 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4085 PFERR_WRITE_MASK,
ab9ae313 4086 exception);
77c2002e
IE		 4087 unsigned offset = addr & (PAGE_SIZE-1);
4088 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4089 int ret;
4090
bcc55cba 4091 if (gpa == UNMAPPED_GVA)
ab9ae313 4092 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4093 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4094 if (ret < 0) {
c3cd7ffa 4095 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4096 goto out;
4097 }
4098
4099 bytes -= towrite;
4100 data += towrite;
4101 addr += towrite;
4102 }
4103out:
4104 return r;
4105}
6a4d7550 4106EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4107
af7cc7d1
XG		 4108static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4109 gpa_t *gpa, struct x86_exception *exception,
4110 bool write)
4111{
97d64b78
AK		 4112 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4113 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4114
97d64b78
AK		 4115 if (vcpu_match_mmio_gva(vcpu, gva)
4116 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
bebb106a
XG		 4117 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4118 (gva & (PAGE_SIZE - 1));
4f022648 4119 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4120 return 1;
4121 }
4122
af7cc7d1
XG		 4123 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4124
4125 if (*gpa == UNMAPPED_GVA)
4126 return -1;
4127
4128 /* For APIC access vmexit */
4129 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4130 return 1;
4131
4f022648
XG		 4132 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4133 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4134 return 1;
4f022648 4135 }
bebb106a 4136
af7cc7d1
XG		 4137 return 0;
4138}
4139
3200f405 4140int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4141 const void *val, int bytes)
bbd9b64e
CO		 4142{
4143 int ret;
4144
4145 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4146 if (ret < 0)
bbd9b64e 4147 return 0;
f57f2ef5 4148 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4149 return 1;
4150}
4151
77d197b2
XG		 4152struct read_write_emulator_ops {
4153 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4154 int bytes);
4155 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4156 void *val, int bytes);
4157 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4158 int bytes, void *val);
4159 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4160 void *val, int bytes);
4161 bool write;
4162};
4163
4164static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4165{
4166 if (vcpu->mmio_read_completed) {
77d197b2 4167 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4168 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4169 vcpu->mmio_read_completed = 0;
4170 return 1;
4171 }
4172
4173 return 0;
4174}
4175
4176static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4177 void *val, int bytes)
4178{
4179 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4180}
4181
4182static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4183 void *val, int bytes)
4184{
4185 return emulator_write_phys(vcpu, gpa, val, bytes);
4186}
4187
4188static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4189{
4190 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4191 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4192}
4193
4194static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4195 void *val, int bytes)
4196{
4197 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4198 return X86EMUL_IO_NEEDED;
4199}
4200
4201static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4202 void *val, int bytes)
4203{
f78146b0
AK		 4204 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4205
87da7e66 4206 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4207 return X86EMUL_CONTINUE;
4208}
4209
0fbe9b0b 4210static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4211 .read_write_prepare = read_prepare,
4212 .read_write_emulate = read_emulate,
4213 .read_write_mmio = vcpu_mmio_read,
4214 .read_write_exit_mmio = read_exit_mmio,
4215};
4216
0fbe9b0b 4217static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4218 .read_write_emulate = write_emulate,
4219 .read_write_mmio = write_mmio,
4220 .read_write_exit_mmio = write_exit_mmio,
4221 .write = true,
4222};
4223
22388a3c
XG		 4224static int emulator_read_write_onepage(unsigned long addr, void *val,
4225 unsigned int bytes,
4226 struct x86_exception *exception,
4227 struct kvm_vcpu *vcpu,
0fbe9b0b 4228 const struct read_write_emulator_ops *ops)
bbd9b64e 4229{
af7cc7d1
XG		 4230 gpa_t gpa;
4231 int handled, ret;
22388a3c 4232 bool write = ops->write;
f78146b0 4233 struct kvm_mmio_fragment *frag;
10589a46 4234
22388a3c 4235 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4236
af7cc7d1 4237 if (ret < 0)
bbd9b64e 4238 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4239
4240 /* For APIC access vmexit */
af7cc7d1 4241 if (ret)
bbd9b64e
CO		 4242 goto mmio;
4243
22388a3c 4244 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4245 return X86EMUL_CONTINUE;
4246
4247mmio:
4248 /*
4249 * Is this MMIO handled locally?
4250 */
22388a3c 4251 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4252 if (handled == bytes)
bbd9b64e 4253 return X86EMUL_CONTINUE;
bbd9b64e 4254
70252a10
AK		 4255 gpa += handled;
4256 bytes -= handled;
4257 val += handled;
4258
87da7e66
XG		 4259 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4260 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4261 frag->gpa = gpa;
4262 frag->data = val;
4263 frag->len = bytes;
f78146b0 4264 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4265}
4266
22388a3c
XG		 4267int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4268 void *val, unsigned int bytes,
4269 struct x86_exception *exception,
0fbe9b0b 4270 const struct read_write_emulator_ops *ops)
bbd9b64e 4271{
0f65dd70 4272 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4273 gpa_t gpa;
4274 int rc;
4275
4276 if (ops->read_write_prepare &&
4277 ops->read_write_prepare(vcpu, val, bytes))
4278 return X86EMUL_CONTINUE;
4279
4280 vcpu->mmio_nr_fragments = 0;
0f65dd70 4281
bbd9b64e
CO		 4282 /* Crossing a page boundary? */
4283 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4284 int now;
bbd9b64e
CO		 4285
4286 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4287 rc = emulator_read_write_onepage(addr, val, now, exception,
4288 vcpu, ops);
4289
bbd9b64e
CO		 4290 if (rc != X86EMUL_CONTINUE)
4291 return rc;
4292 addr += now;
4293 val += now;
4294 bytes -= now;
4295 }
22388a3c 4296
f78146b0
AK		 4297 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4298 vcpu, ops);
4299 if (rc != X86EMUL_CONTINUE)
4300 return rc;
4301
4302 if (!vcpu->mmio_nr_fragments)
4303 return rc;
4304
4305 gpa = vcpu->mmio_fragments[0].gpa;
4306
4307 vcpu->mmio_needed = 1;
4308 vcpu->mmio_cur_fragment = 0;
4309
87da7e66 4310 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4311 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4312 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4313 vcpu->run->mmio.phys_addr = gpa;
4314
4315 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4316}
4317
4318static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4319 unsigned long addr,
4320 void *val,
4321 unsigned int bytes,
4322 struct x86_exception *exception)
4323{
4324 return emulator_read_write(ctxt, addr, val, bytes,
4325 exception, &read_emultor);
4326}
4327
4328int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4329 unsigned long addr,
4330 const void *val,
4331 unsigned int bytes,
4332 struct x86_exception *exception)
4333{
4334 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4335 exception, &write_emultor);
bbd9b64e 4336}
bbd9b64e 4337
daea3e73
AK		 4338#define CMPXCHG_TYPE(t, ptr, old, new) \
4339 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4340
4341#ifdef CONFIG_X86_64
4342# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4343#else
4344# define CMPXCHG64(ptr, old, new) \
9749a6c0 4345 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4346#endif
4347
0f65dd70
AK		 4348static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4349 unsigned long addr,
bbd9b64e
CO		 4350 const void *old,
4351 const void *new,
4352 unsigned int bytes,
0f65dd70 4353 struct x86_exception *exception)
bbd9b64e 4354{
0f65dd70 4355 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4356 gpa_t gpa;
4357 struct page *page;
4358 char *kaddr;
4359 bool exchanged;
2bacc55c 4360
daea3e73
AK		 4361 /* guests cmpxchg8b have to be emulated atomically */
4362 if (bytes > 8 || (bytes & (bytes - 1)))
4363 goto emul_write;
10589a46 4364
daea3e73 4365 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4366
daea3e73
AK		 4367 if (gpa == UNMAPPED_GVA ||
4368 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4369 goto emul_write;
2bacc55c 4370
daea3e73
AK		 4371 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4372 goto emul_write;
72dc67a6 4373
daea3e73 4374 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4375 if (is_error_page(page))
c19b8bd6 4376 goto emul_write;
72dc67a6 4377
8fd75e12 4378 kaddr = kmap_atomic(page);
daea3e73
AK		 4379 kaddr += offset_in_page(gpa);
4380 switch (bytes) {
4381 case 1:
4382 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4383 break;
4384 case 2:
4385 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4386 break;
4387 case 4:
4388 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4389 break;
4390 case 8:
4391 exchanged = CMPXCHG64(kaddr, old, new);
4392 break;
4393 default:
4394 BUG();
2bacc55c 4395 }
8fd75e12 4396 kunmap_atomic(kaddr);
daea3e73
AK		 4397 kvm_release_page_dirty(page);
4398
4399 if (!exchanged)
4400 return X86EMUL_CMPXCHG_FAILED;
4401
d3714010 4402 mark_page_dirty(vcpu->kvm, gpa >> PAGE_SHIFT);
f57f2ef5 4403 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4404
4405 return X86EMUL_CONTINUE;
4a5f48f6 4406
3200f405 4407emul_write:
daea3e73 4408 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4409
0f65dd70 4410 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4411}
4412
cf8f70bf
GN		 4413static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4414{
4415 /* TODO: String I/O for in kernel device */
4416 int r;
4417
4418 if (vcpu->arch.pio.in)
4419 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4420 vcpu->arch.pio.size, pd);
4421 else
4422 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4423 vcpu->arch.pio.port, vcpu->arch.pio.size,
4424 pd);
4425 return r;
4426}
4427
6f6fbe98
XG		 4428static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4429 unsigned short port, void *val,
4430 unsigned int count, bool in)
cf8f70bf 4431{
6f6fbe98 4432 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 4433
4434 vcpu->arch.pio.port = port;
6f6fbe98 4435 vcpu->arch.pio.in = in;
7972995b 4436 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4437 vcpu->arch.pio.size = size;
4438
4439 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4440 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4441 return 1;
4442 }
4443
4444 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4445 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4446 vcpu->run->io.size = size;
4447 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4448 vcpu->run->io.count = count;
4449 vcpu->run->io.port = port;
4450
4451 return 0;
4452}
4453
6f6fbe98
XG		 4454static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4455 int size, unsigned short port, void *val,
4456 unsigned int count)
cf8f70bf 4457{
ca1d4a9e 4458 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4459 int ret;
ca1d4a9e 4460
6f6fbe98
XG		 4461 if (vcpu->arch.pio.count)
4462 goto data_avail;
cf8f70bf 4463
6f6fbe98
XG		 4464 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4465 if (ret) {
4466data_avail:
4467 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4468 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4469 return 1;
4470 }
4471
cf8f70bf
GN		 4472 return 0;
4473}
4474
6f6fbe98
XG		 4475static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4476 int size, unsigned short port,
4477 const void *val, unsigned int count)
4478{
4479 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4480
4481 memcpy(vcpu->arch.pio_data, val, size * count);
4482 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4483}
4484
bbd9b64e
CO		 4485static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4486{
4487 return kvm_x86_ops->get_segment_base(vcpu, seg);
4488}
4489
3cb16fe7 4490static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4491{
3cb16fe7 4492 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4493}
4494
f5f48ee1
SY		 4495int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4496{
4497 if (!need_emulate_wbinvd(vcpu))
4498 return X86EMUL_CONTINUE;
4499
4500 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4501 int cpu = get_cpu();
4502
4503 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4504 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4505 wbinvd_ipi, NULL, 1);
2eec7343 4506 put_cpu();
f5f48ee1 4507 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4508 } else
4509 wbinvd();
f5f48ee1
SY		 4510 return X86EMUL_CONTINUE;
4511}
4512EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4513
bcaf5cc5
AK		 4514static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4515{
4516 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4517}
4518
717746e3 4519int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4520{
717746e3 4521 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4522}
4523
717746e3 4524int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4525{
338dbc97 4526
717746e3 4527 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4528}
4529
52a46617 4530static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4531{
52a46617 4532 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4533}
4534
717746e3 4535static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4536{
717746e3 4537 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4538 unsigned long value;
4539
4540 switch (cr) {
4541 case 0:
4542 value = kvm_read_cr0(vcpu);
4543 break;
4544 case 2:
4545 value = vcpu->arch.cr2;
4546 break;
4547 case 3:
9f8fe504 4548 value = kvm_read_cr3(vcpu);
52a46617
GN		 4549 break;
4550 case 4:
4551 value = kvm_read_cr4(vcpu);
4552 break;
4553 case 8:
4554 value = kvm_get_cr8(vcpu);
4555 break;
4556 default:
a737f256 4557 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4558 return 0;
4559 }
4560
4561 return value;
4562}
4563
717746e3 4564static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4565{
717746e3 4566 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4567 int res = 0;
4568
52a46617
GN		 4569 switch (cr) {
4570 case 0:
49a9b07e 4571 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4572 break;
4573 case 2:
4574 vcpu->arch.cr2 = val;
4575 break;
4576 case 3:
2390218b 4577 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4578 break;
4579 case 4:
a83b29c6 4580 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4581 break;
4582 case 8:
eea1cff9 4583 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4584 break;
4585 default:
a737f256 4586 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4587 res = -1;
52a46617 4588 }
0f12244f
GN		 4589
4590 return res;
52a46617
GN		 4591}
4592
4cee4798
KW		 4593static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4594{
4595 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4596}
4597
717746e3 4598static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4599{
717746e3 4600 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4601}
4602
4bff1e86 4603static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4604{
4bff1e86 4605 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4606}
4607
4bff1e86 4608static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4609{
4bff1e86 4610 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4611}
4612
1ac9d0cf
AK		 4613static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4614{
4615 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4616}
4617
4618static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4619{
4620 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4621}
4622
4bff1e86
AK		 4623static unsigned long emulator_get_cached_segment_base(
4624 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4625{
4bff1e86 4626 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4627}
4628
1aa36616
AK		 4629static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4630 struct desc_struct *desc, u32 *base3,
4631 int seg)
2dafc6c2
GN		 4632{
4633 struct kvm_segment var;
4634
4bff1e86 4635 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4636 *selector = var.selector;
2dafc6c2 4637
378a8b09
GN		 4638 if (var.unusable) {
4639 memset(desc, 0, sizeof(*desc));
2dafc6c2 4640 return false;
378a8b09 4641 }
2dafc6c2
GN		 4642
4643 if (var.g)
4644 var.limit >>= 12;
4645 set_desc_limit(desc, var.limit);
4646 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4647#ifdef CONFIG_X86_64
4648 if (base3)
4649 *base3 = var.base >> 32;
4650#endif
2dafc6c2
GN		 4651 desc->type = var.type;
4652 desc->s = var.s;
4653 desc->dpl = var.dpl;
4654 desc->p = var.present;
4655 desc->avl = var.avl;
4656 desc->l = var.l;
4657 desc->d = var.db;
4658 desc->g = var.g;
4659
4660 return true;
4661}
4662
1aa36616
AK		 4663static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4664 struct desc_struct *desc, u32 base3,
4665 int seg)
2dafc6c2 4666{
4bff1e86 4667 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4668 struct kvm_segment var;
4669
1aa36616 4670 var.selector = selector;
2dafc6c2 4671 var.base = get_desc_base(desc);
5601d05b
GN		 4672#ifdef CONFIG_X86_64
4673 var.base |= ((u64)base3) << 32;
4674#endif
2dafc6c2
GN		 4675 var.limit = get_desc_limit(desc);
4676 if (desc->g)
4677 var.limit = (var.limit << 12) | 0xfff;
4678 var.type = desc->type;
4679 var.present = desc->p;
4680 var.dpl = desc->dpl;
4681 var.db = desc->d;
4682 var.s = desc->s;
4683 var.l = desc->l;
4684 var.g = desc->g;
4685 var.avl = desc->avl;
4686 var.present = desc->p;
4687 var.unusable = !var.present;
4688 var.padding = 0;
4689
4690 kvm_set_segment(vcpu, &var, seg);
4691 return;
4692}
4693
717746e3
AK		 4694static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4695 u32 msr_index, u64 *pdata)
4696{
4697 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4698}
4699
4700static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4701 u32 msr_index, u64 data)
4702{
8fe8ab46
WA		 4703 struct msr_data msr;
4704
4705 msr.data = data;
4706 msr.index = msr_index;
4707 msr.host_initiated = false;
4708 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4709}
4710
222d21aa
AK		 4711static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4712 u32 pmc, u64 *pdata)
4713{
4714 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4715}
4716
6c3287f7
AK		 4717static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4718{
4719 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4720}
4721
5037f6f3
AK		 4722static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4723{
4724 preempt_disable();
5197b808 4725 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4726 /*
4727 * CR0.TS may reference the host fpu state, not the guest fpu state,
4728 * so it may be clear at this point.
4729 */
4730 clts();
4731}
4732
4733static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4734{
4735 preempt_enable();
4736}
4737
2953538e 4738static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4739 struct x86_instruction_info *info,
c4f035c6
AK		 4740 enum x86_intercept_stage stage)
4741{
2953538e 4742 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4743}
4744
0017f93a 4745static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4746 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4747{
0017f93a 4748 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4749}
4750
dd856efa
AK		 4751static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4752{
4753 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4754}
4755
4756static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4757{
4758 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4759}
4760
0225fb50 4761static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4762 .read_gpr = emulator_read_gpr,
4763 .write_gpr = emulator_write_gpr,
1871c602 4764 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4765 .write_std = kvm_write_guest_virt_system,
1871c602 4766 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4767 .read_emulated = emulator_read_emulated,
4768 .write_emulated = emulator_write_emulated,
4769 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4770 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4771 .pio_in_emulated = emulator_pio_in_emulated,
4772 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4773 .get_segment = emulator_get_segment,
4774 .set_segment = emulator_set_segment,
5951c442 4775 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4776 .get_gdt = emulator_get_gdt,
160ce1f1 4777 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4778 .set_gdt = emulator_set_gdt,
4779 .set_idt = emulator_set_idt,
52a46617
GN		 4780 .get_cr = emulator_get_cr,
4781 .set_cr = emulator_set_cr,
4cee4798 4782 .set_rflags = emulator_set_rflags,
9c537244 4783 .cpl = emulator_get_cpl,
35aa5375
GN		 4784 .get_dr = emulator_get_dr,
4785 .set_dr = emulator_set_dr,
717746e3
AK		 4786 .set_msr = emulator_set_msr,
4787 .get_msr = emulator_get_msr,
222d21aa 4788 .read_pmc = emulator_read_pmc,
6c3287f7 4789 .halt = emulator_halt,
bcaf5cc5 4790 .wbinvd = emulator_wbinvd,
d6aa1000 4791 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4792 .get_fpu = emulator_get_fpu,
4793 .put_fpu = emulator_put_fpu,
c4f035c6 4794 .intercept = emulator_intercept,
bdb42f5a 4795 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4796};
4797
95cb2295
GN		 4798static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4799{
4800 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4801 /*
4802 * an sti; sti; sequence only disable interrupts for the first
4803 * instruction. So, if the last instruction, be it emulated or
4804 * not, left the system with the INT_STI flag enabled, it
4805 * means that the last instruction is an sti. We should not
4806 * leave the flag on in this case. The same goes for mov ss
4807 */
4808 if (!(int_shadow & mask))
4809 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4810}
4811
54b8486f
GN		 4812static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4813{
4814 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4815 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4816 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4817 else if (ctxt->exception.error_code_valid)
4818 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4819 ctxt->exception.error_code);
54b8486f 4820 else
da9cb575 4821 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4822}
4823
dd856efa 4824static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
b5c9ff73 4825{
1ce19dc1
BP		 4826 memset(&ctxt->opcode_len, 0,
4827 (void *)&ctxt->_regs - (void *)&ctxt->opcode_len);
b5c9ff73 4828
9dac77fa
AK		 4829 ctxt->fetch.start = 0;
4830 ctxt->fetch.end = 0;
4831 ctxt->io_read.pos = 0;
4832 ctxt->io_read.end = 0;
4833 ctxt->mem_read.pos = 0;
4834 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4835}
4836
8ec4722d
MG		 4837static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4838{
adf52235 4839 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4840 int cs_db, cs_l;
4841
8ec4722d
MG		 4842 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4843
adf52235
TY		 4844 ctxt->eflags = kvm_get_rflags(vcpu);
4845 ctxt->eip = kvm_rip_read(vcpu);
4846 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4847 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4848 cs_l ? X86EMUL_MODE_PROT64 :
4849 cs_db ? X86EMUL_MODE_PROT32 :
4850 X86EMUL_MODE_PROT16;
4851 ctxt->guest_mode = is_guest_mode(vcpu);
4852
dd856efa 4853 init_decode_cache(ctxt);
7ae441ea 4854 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4855}
4856
71f9833b 4857int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4858{
9d74191a 4859 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4860 int ret;
4861
4862 init_emulate_ctxt(vcpu);
4863
9dac77fa
AK		 4864 ctxt->op_bytes = 2;
4865 ctxt->ad_bytes = 2;
4866 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4867 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4868
4869 if (ret != X86EMUL_CONTINUE)
4870 return EMULATE_FAIL;
4871
9dac77fa 4872 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4873 kvm_rip_write(vcpu, ctxt->eip);
4874 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4875
4876 if (irq == NMI_VECTOR)
7460fb4a 4877 vcpu->arch.nmi_pending = 0;
63995653
MG		 4878 else
4879 vcpu->arch.interrupt.pending = false;
4880
4881 return EMULATE_DONE;
4882}
4883EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4884
6d77dbfc
GN		 4885static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4886{
fc3a9157
JR		 4887 int r = EMULATE_DONE;
4888
6d77dbfc
GN		 4889 ++vcpu->stat.insn_emulation_fail;
4890 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4891 if (!is_guest_mode(vcpu)) {
4892 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4893 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4894 vcpu->run->internal.ndata = 0;
4895 r = EMULATE_FAIL;
4896 }
6d77dbfc 4897 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4898
4899 return r;
6d77dbfc
GN		 4900}
4901
93c05d3e 4902static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4903 bool write_fault_to_shadow_pgtable,
4904 int emulation_type)
a6f177ef 4905{
95b3cf69 4906 gpa_t gpa = cr2;
8e3d9d06 4907 pfn_t pfn;
a6f177ef 4908
991eebf9
GN		 4909 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4910 return false;
4911
95b3cf69
XG		 4912 if (!vcpu->arch.mmu.direct_map) {
4913 /*
4914 * Write permission should be allowed since only
4915 * write access need to be emulated.
4916 */
4917 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 4918
95b3cf69
XG		 4919 /*
4920 * If the mapping is invalid in guest, let cpu retry
4921 * it to generate fault.
4922 */
4923 if (gpa == UNMAPPED_GVA)
4924 return true;
4925 }
a6f177ef 4926
8e3d9d06
XG		 4927 /*
4928 * Do not retry the unhandleable instruction if it faults on the
4929 * readonly host memory, otherwise it will goto a infinite loop:
4930 * retry instruction -> write #PF -> emulation fail -> retry
4931 * instruction -> ...
4932 */
4933 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 4934
4935 /*
4936 * If the instruction failed on the error pfn, it can not be fixed,
4937 * report the error to userspace.
4938 */
4939 if (is_error_noslot_pfn(pfn))
4940 return false;
4941
4942 kvm_release_pfn_clean(pfn);
4943
4944 /* The instructions are well-emulated on direct mmu. */
4945 if (vcpu->arch.mmu.direct_map) {
4946 unsigned int indirect_shadow_pages;
4947
4948 spin_lock(&vcpu->kvm->mmu_lock);
4949 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4950 spin_unlock(&vcpu->kvm->mmu_lock);
4951
4952 if (indirect_shadow_pages)
4953 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4954
a6f177ef 4955 return true;
8e3d9d06 4956 }
a6f177ef 4957
95b3cf69
XG		 4958 /*
4959 * if emulation was due to access to shadowed page table
4960 * and it failed try to unshadow page and re-enter the
4961 * guest to let CPU execute the instruction.
4962 */
4963 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 4964
4965 /*
4966 * If the access faults on its page table, it can not
4967 * be fixed by unprotecting shadow page and it should
4968 * be reported to userspace.
4969 */
4970 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 4971}
4972
1cb3f3ae
XG		 4973static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4974 unsigned long cr2, int emulation_type)
4975{
4976 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4977 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4978
4979 last_retry_eip = vcpu->arch.last_retry_eip;
4980 last_retry_addr = vcpu->arch.last_retry_addr;
4981
4982 /*
4983 * If the emulation is caused by #PF and it is non-page_table
4984 * writing instruction, it means the VM-EXIT is caused by shadow
4985 * page protected, we can zap the shadow page and retry this
4986 * instruction directly.
4987 *
4988 * Note: if the guest uses a non-page-table modifying instruction
4989 * on the PDE that points to the instruction, then we will unmap
4990 * the instruction and go to an infinite loop. So, we cache the
4991 * last retried eip and the last fault address, if we meet the eip
4992 * and the address again, we can break out of the potential infinite
4993 * loop.
4994 */
4995 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4996
4997 if (!(emulation_type & EMULTYPE_RETRY))
4998 return false;
4999
5000 if (x86_page_table_writing_insn(ctxt))
5001 return false;
5002
5003 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
5004 return false;
5005
5006 vcpu->arch.last_retry_eip = ctxt->eip;
5007 vcpu->arch.last_retry_addr = cr2;
5008
5009 if (!vcpu->arch.mmu.direct_map)
5010 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
5011
22368028 5012 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 5013
5014 return true;
5015}
5016
716d51ab
GN		 5017static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
5018static int complete_emulated_pio(struct kvm_vcpu *vcpu);
5019
4a1e10d5
PB		 5020static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
5021 unsigned long *db)
5022{
5023 u32 dr6 = 0;
5024 int i;
5025 u32 enable, rwlen;
5026
5027 enable = dr7;
5028 rwlen = dr7 >> 16;
5029 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
5030 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
5031 dr6 |= (1 << i);
5032 return dr6;
5033}
5034
663f4c61
PB		 5035static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, int *r)
5036{
5037 struct kvm_run *kvm_run = vcpu->run;
5038
5039 /*
5040 * Use the "raw" value to see if TF was passed to the processor.
5041 * Note that the new value of the flags has not been saved yet.
5042 *
5043 * This is correct even for TF set by the guest, because "the
5044 * processor will not generate this exception after the instruction
5045 * that sets the TF flag".
5046 */
5047 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5048
5049 if (unlikely(rflags & X86_EFLAGS_TF)) {
5050 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5051 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1;
5052 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5053 kvm_run->debug.arch.exception = DB_VECTOR;
5054 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5055 *r = EMULATE_USER_EXIT;
5056 } else {
5057 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5058 /*
5059 * "Certain debug exceptions may clear bit 0-3. The
5060 * remaining contents of the DR6 register are never
5061 * cleared by the processor".
5062 */
5063 vcpu->arch.dr6 &= ~15;
5064 vcpu->arch.dr6 |= DR6_BS;
5065 kvm_queue_exception(vcpu, DB_VECTOR);
5066 }
5067 }
5068}
5069
4a1e10d5
PB		 5070static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5071{
5072 struct kvm_run *kvm_run = vcpu->run;
5073 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5074 u32 dr6 = 0;
5075
5076 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5077 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5078 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5079 vcpu->arch.guest_debug_dr7,
5080 vcpu->arch.eff_db);
5081
5082 if (dr6 != 0) {
5083 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5084 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5085 get_segment_base(vcpu, VCPU_SREG_CS);
5086
5087 kvm_run->debug.arch.exception = DB_VECTOR;
5088 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5089 *r = EMULATE_USER_EXIT;
5090 return true;
5091 }
5092 }
5093
5094 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) {
5095 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5096 vcpu->arch.dr7,
5097 vcpu->arch.db);
5098
5099 if (dr6 != 0) {
5100 vcpu->arch.dr6 &= ~15;
5101 vcpu->arch.dr6 |= dr6;
5102 kvm_queue_exception(vcpu, DB_VECTOR);
5103 *r = EMULATE_DONE;
5104 return true;
5105 }
5106 }
5107
5108 return false;
5109}
5110
51d8b661
AP		 5111int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5112 unsigned long cr2,
dc25e89e
AP		 5113 int emulation_type,
5114 void *insn,
5115 int insn_len)
bbd9b64e 5116{
95cb2295 5117 int r;
9d74191a 5118 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5119 bool writeback = true;
93c05d3e 5120 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5121
93c05d3e
XG		 5122 /*
5123 * Clear write_fault_to_shadow_pgtable here to ensure it is
5124 * never reused.
5125 */
5126 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5127 kvm_clear_exception_queue(vcpu);
8d7d8102 5128
571008da 5129 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5130 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5131
5132 /*
5133 * We will reenter on the same instruction since
5134 * we do not set complete_userspace_io. This does not
5135 * handle watchpoints yet, those would be handled in
5136 * the emulate_ops.
5137 */
5138 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5139 return r;
5140
9d74191a
TY		 5141 ctxt->interruptibility = 0;
5142 ctxt->have_exception = false;
5143 ctxt->perm_ok = false;
bbd9b64e 5144
b51e974f 5145 ctxt->ud = emulation_type & EMULTYPE_TRAP_UD;
4005996e 5146
9d74191a 5147 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5148
e46479f8 5149 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5150 ++vcpu->stat.insn_emulation;
1d2887e2 5151 if (r != EMULATION_OK) {
4005996e
AK		 5152 if (emulation_type & EMULTYPE_TRAP_UD)
5153 return EMULATE_FAIL;
991eebf9
GN		 5154 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5155 emulation_type))
bbd9b64e 5156 return EMULATE_DONE;
6d77dbfc
GN		 5157 if (emulation_type & EMULTYPE_SKIP)
5158 return EMULATE_FAIL;
5159 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5160 }
5161 }
5162
ba8afb6b 5163 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5164 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 5165 return EMULATE_DONE;
5166 }
5167
1cb3f3ae
XG		 5168 if (retry_instruction(ctxt, cr2, emulation_type))
5169 return EMULATE_DONE;
5170
7ae441ea 5171 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5172 changes registers values during IO operation */
7ae441ea
GN		 5173 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5174 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5175 emulator_invalidate_register_cache(ctxt);
7ae441ea 5176 }
4d2179e1 5177
5cd21917 5178restart:
9d74191a 5179 r = x86_emulate_insn(ctxt);
bbd9b64e 5180
775fde86
JR		 5181 if (r == EMULATION_INTERCEPTED)
5182 return EMULATE_DONE;
5183
d2ddd1c4 5184 if (r == EMULATION_FAILED) {
991eebf9
GN		 5185 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5186 emulation_type))
c3cd7ffa
GN		 5187 return EMULATE_DONE;
5188
6d77dbfc 5189 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5190 }
5191
9d74191a 5192 if (ctxt->have_exception) {
54b8486f 5193 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 5194 r = EMULATE_DONE;
5195 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5196 if (!vcpu->arch.pio.in) {
5197 /* FIXME: return into emulator if single-stepping. */
3457e419 5198 vcpu->arch.pio.count = 0;
0912c977 5199 } else {
7ae441ea 5200 writeback = false;
716d51ab
GN		 5201 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5202 }
ac0a48c3 5203 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5204 } else if (vcpu->mmio_needed) {
5205 if (!vcpu->mmio_is_write)
5206 writeback = false;
ac0a48c3 5207 r = EMULATE_USER_EXIT;
716d51ab 5208 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5209 } else if (r == EMULATION_RESTART)
5cd21917 5210 goto restart;
d2ddd1c4
GN		 5211 else
5212 r = EMULATE_DONE;
f850e2e6 5213
7ae441ea 5214 if (writeback) {
9d74191a 5215 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5216 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea 5217 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5218 kvm_rip_write(vcpu, ctxt->eip);
663f4c61
PB		 5219 if (r == EMULATE_DONE)
5220 kvm_vcpu_check_singlestep(vcpu, &r);
5221 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea
GN		 5222 } else
5223 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5224
5225 return r;
de7d789a 5226}
51d8b661 5227EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5228
cf8f70bf 5229int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5230{
cf8f70bf 5231 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5232 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5233 size, port, &val, 1);
cf8f70bf 5234 /* do not return to emulator after return from userspace */
7972995b 5235 vcpu->arch.pio.count = 0;
de7d789a
CO		 5236 return ret;
5237}
cf8f70bf 5238EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5239
8cfdc000
ZA		 5240static void tsc_bad(void *info)
5241{
0a3aee0d 5242 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5243}
5244
5245static void tsc_khz_changed(void *data)
c8076604 5246{
8cfdc000
ZA		 5247 struct cpufreq_freqs *freq = data;
5248 unsigned long khz = 0;
5249
5250 if (data)
5251 khz = freq->new;
5252 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5253 khz = cpufreq_quick_get(raw_smp_processor_id());
5254 if (!khz)
5255 khz = tsc_khz;
0a3aee0d 5256 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5257}
5258
c8076604
GH		 5259static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5260 void *data)
5261{
5262 struct cpufreq_freqs *freq = data;
5263 struct kvm *kvm;
5264 struct kvm_vcpu *vcpu;
5265 int i, send_ipi = 0;
5266
8cfdc000
ZA		 5267 /*
5268 * We allow guests to temporarily run on slowing clocks,
5269 * provided we notify them after, or to run on accelerating
5270 * clocks, provided we notify them before. Thus time never
5271 * goes backwards.
5272 *
5273 * However, we have a problem. We can't atomically update
5274 * the frequency of a given CPU from this function; it is
5275 * merely a notifier, which can be called from any CPU.
5276 * Changing the TSC frequency at arbitrary points in time
5277 * requires a recomputation of local variables related to
5278 * the TSC for each VCPU. We must flag these local variables
5279 * to be updated and be sure the update takes place with the
5280 * new frequency before any guests proceed.
5281 *
5282 * Unfortunately, the combination of hotplug CPU and frequency
5283 * change creates an intractable locking scenario; the order
5284 * of when these callouts happen is undefined with respect to
5285 * CPU hotplug, and they can race with each other. As such,
5286 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5287 * undefined; you can actually have a CPU frequency change take
5288 * place in between the computation of X and the setting of the
5289 * variable. To protect against this problem, all updates of
5290 * the per_cpu tsc_khz variable are done in an interrupt
5291 * protected IPI, and all callers wishing to update the value
5292 * must wait for a synchronous IPI to complete (which is trivial
5293 * if the caller is on the CPU already). This establishes the
5294 * necessary total order on variable updates.
5295 *
5296 * Note that because a guest time update may take place
5297 * anytime after the setting of the VCPU's request bit, the
5298 * correct TSC value must be set before the request. However,
5299 * to ensure the update actually makes it to any guest which
5300 * starts running in hardware virtualization between the set
5301 * and the acquisition of the spinlock, we must also ping the
5302 * CPU after setting the request bit.
5303 *
5304 */
5305
c8076604
GH		 5306 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5307 return 0;
5308 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5309 return 0;
8cfdc000
ZA		 5310
5311 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5312
2f303b74 5313 spin_lock(&kvm_lock);
c8076604 5314 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5315 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5316 if (vcpu->cpu != freq->cpu)
5317 continue;
c285545f 5318 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5319 if (vcpu->cpu != smp_processor_id())
8cfdc000 5320 send_ipi = 1;
c8076604
GH		 5321 }
5322 }
2f303b74 5323 spin_unlock(&kvm_lock);
c8076604
GH		 5324
5325 if (freq->old < freq->new && send_ipi) {
5326 /*
5327 * We upscale the frequency. Must make the guest
5328 * doesn't see old kvmclock values while running with
5329 * the new frequency, otherwise we risk the guest sees
5330 * time go backwards.
5331 *
5332 * In case we update the frequency for another cpu
5333 * (which might be in guest context) send an interrupt
5334 * to kick the cpu out of guest context. Next time
5335 * guest context is entered kvmclock will be updated,
5336 * so the guest will not see stale values.
5337 */
8cfdc000 5338 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5339 }
5340 return 0;
5341}
5342
5343static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5344 .notifier_call = kvmclock_cpufreq_notifier
5345};
5346
5347static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5348 unsigned long action, void *hcpu)
5349{
5350 unsigned int cpu = (unsigned long)hcpu;
5351
5352 switch (action) {
5353 case CPU_ONLINE:
5354 case CPU_DOWN_FAILED:
5355 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5356 break;
5357 case CPU_DOWN_PREPARE:
5358 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5359 break;
5360 }
5361 return NOTIFY_OK;
5362}
5363
5364static struct notifier_block kvmclock_cpu_notifier_block = {
5365 .notifier_call = kvmclock_cpu_notifier,
5366 .priority = -INT_MAX
c8076604
GH		 5367};
5368
b820cc0c
ZA		 5369static void kvm_timer_init(void)
5370{
5371 int cpu;
5372
c285545f 5373 max_tsc_khz = tsc_khz;
8cfdc000 5374 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 5375 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5376#ifdef CONFIG_CPU_FREQ
5377 struct cpufreq_policy policy;
5378 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5379 cpu = get_cpu();
5380 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5381 if (policy.cpuinfo.max_freq)
5382 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5383 put_cpu();
c285545f 5384#endif
b820cc0c
ZA		 5385 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5386 CPUFREQ_TRANSITION_NOTIFIER);
5387 }
c285545f 5388 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5389 for_each_online_cpu(cpu)
5390 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 5391}
5392
ff9d07a0
ZY		 5393static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5394
f5132b01 5395int kvm_is_in_guest(void)
ff9d07a0 5396{
086c9855 5397 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5398}
5399
5400static int kvm_is_user_mode(void)
5401{
5402 int user_mode = 3;
dcf46b94 5403
086c9855
AS		 5404 if (__this_cpu_read(current_vcpu))
5405 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5406
ff9d07a0
ZY		 5407 return user_mode != 0;
5408}
5409
5410static unsigned long kvm_get_guest_ip(void)
5411{
5412 unsigned long ip = 0;
dcf46b94 5413
086c9855
AS		 5414 if (__this_cpu_read(current_vcpu))
5415 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5416
ff9d07a0
ZY		 5417 return ip;
5418}
5419
5420static struct perf_guest_info_callbacks kvm_guest_cbs = {
5421 .is_in_guest = kvm_is_in_guest,
5422 .is_user_mode = kvm_is_user_mode,
5423 .get_guest_ip = kvm_get_guest_ip,
5424};
5425
5426void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5427{
086c9855 5428 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5429}
5430EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5431
5432void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5433{
086c9855 5434 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5435}
5436EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5437
ce88decf
XG		 5438static void kvm_set_mmio_spte_mask(void)
5439{
5440 u64 mask;
5441 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5442
5443 /*
5444 * Set the reserved bits and the present bit of an paging-structure
5445 * entry to generate page fault with PFER.RSV = 1.
5446 */
885032b9
XG		 5447 /* Mask the reserved physical address bits. */
5448 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5449
5450 /* Bit 62 is always reserved for 32bit host. */
5451 mask |= 0x3ull << 62;
5452
5453 /* Set the present bit. */
ce88decf
XG		 5454 mask |= 1ull;
5455
5456#ifdef CONFIG_X86_64
5457 /*
5458 * If reserved bit is not supported, clear the present bit to disable
5459 * mmio page fault.
5460 */
5461 if (maxphyaddr == 52)
5462 mask &= ~1ull;
5463#endif
5464
5465 kvm_mmu_set_mmio_spte_mask(mask);
5466}
5467
16e8d74d
MT		 5468#ifdef CONFIG_X86_64
5469static void pvclock_gtod_update_fn(struct work_struct *work)
5470{
d828199e
MT		 5471 struct kvm *kvm;
5472
5473 struct kvm_vcpu *vcpu;
5474 int i;
5475
2f303b74 5476 spin_lock(&kvm_lock);
d828199e
MT		 5477 list_for_each_entry(kvm, &vm_list, vm_list)
5478 kvm_for_each_vcpu(i, vcpu, kvm)
5479 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5480 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5481 spin_unlock(&kvm_lock);
16e8d74d
MT		 5482}
5483
5484static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5485
5486/*
5487 * Notification about pvclock gtod data update.
5488 */
5489static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5490 void *priv)
5491{
5492 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5493 struct timekeeper *tk = priv;
5494
5495 update_pvclock_gtod(tk);
5496
5497 /* disable master clock if host does not trust, or does not
5498 * use, TSC clocksource
5499 */
5500 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5501 atomic_read(&kvm_guest_has_master_clock) != 0)
5502 queue_work(system_long_wq, &pvclock_gtod_work);
5503
5504 return 0;
5505}
5506
5507static struct notifier_block pvclock_gtod_notifier = {
5508 .notifier_call = pvclock_gtod_notify,
5509};
5510#endif
5511
f8c16bba 5512int kvm_arch_init(void *opaque)
043405e1 5513{
b820cc0c 5514 int r;
6b61edf7 5515 struct kvm_x86_ops *ops = opaque;
f8c16bba 5516
f8c16bba
ZX		 5517 if (kvm_x86_ops) {
5518 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5519 r = -EEXIST;
5520 goto out;
f8c16bba
ZX		 5521 }
5522
5523 if (!ops->cpu_has_kvm_support()) {
5524 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5525 r = -EOPNOTSUPP;
5526 goto out;
f8c16bba
ZX		 5527 }
5528 if (ops->disabled_by_bios()) {
5529 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5530 r = -EOPNOTSUPP;
5531 goto out;
f8c16bba
ZX		 5532 }
5533
013f6a5d
MT		 5534 r = -ENOMEM;
5535 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5536 if (!shared_msrs) {
5537 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5538 goto out;
5539 }
5540
97db56ce
AK		 5541 r = kvm_mmu_module_init();
5542 if (r)
013f6a5d 5543 goto out_free_percpu;
97db56ce 5544
ce88decf 5545 kvm_set_mmio_spte_mask();
97db56ce
AK		 5546 kvm_init_msr_list();
5547
f8c16bba 5548 kvm_x86_ops = ops;
7b52345e 5549 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5550 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5551
b820cc0c 5552 kvm_timer_init();
c8076604 5553
ff9d07a0
ZY		 5554 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5555
2acf923e
DC		 5556 if (cpu_has_xsave)
5557 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5558
c5cc421b 5559 kvm_lapic_init();
16e8d74d
MT		 5560#ifdef CONFIG_X86_64
5561 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5562#endif
5563
f8c16bba 5564 return 0;
56c6d28a 5565
013f6a5d
MT		 5566out_free_percpu:
5567 free_percpu(shared_msrs);
56c6d28a 5568out:
56c6d28a 5569 return r;
043405e1 5570}
8776e519 5571
f8c16bba
ZX		 5572void kvm_arch_exit(void)
5573{
ff9d07a0
ZY		 5574 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5575
888d256e
JK		 5576 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5577 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5578 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5579 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5580#ifdef CONFIG_X86_64
5581 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5582#endif
f8c16bba 5583 kvm_x86_ops = NULL;
56c6d28a 5584 kvm_mmu_module_exit();
013f6a5d 5585 free_percpu(shared_msrs);
56c6d28a 5586}
f8c16bba 5587
8776e519
HB		 5588int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5589{
5590 ++vcpu->stat.halt_exits;
5591 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5592 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5593 return 1;
5594 } else {
5595 vcpu->run->exit_reason = KVM_EXIT_HLT;
5596 return 0;
5597 }
5598}
5599EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5600
55cd8e5a
GN		 5601int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5602{
5603 u64 param, ingpa, outgpa, ret;
5604 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5605 bool fast, longmode;
5606 int cs_db, cs_l;
5607
5608 /*
5609 * hypercall generates UD from non zero cpl and real mode
5610 * per HYPER-V spec
5611 */
3eeb3288 5612 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5613 kvm_queue_exception(vcpu, UD_VECTOR);
5614 return 0;
5615 }
5616
5617 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5618 longmode = is_long_mode(vcpu) && cs_l == 1;
5619
5620 if (!longmode) {
ccd46936
GN		 5621 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5622 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5623 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5624 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5625 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5626 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5627 }
5628#ifdef CONFIG_X86_64
5629 else {
5630 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5631 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5632 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5633 }
5634#endif
5635
5636 code = param & 0xffff;
5637 fast = (param >> 16) & 0x1;
5638 rep_cnt = (param >> 32) & 0xfff;
5639 rep_idx = (param >> 48) & 0xfff;
5640
5641 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5642
c25bc163
GN		 5643 switch (code) {
5644 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5645 kvm_vcpu_on_spin(vcpu);
5646 break;
5647 default:
5648 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5649 break;
5650 }
55cd8e5a
GN		 5651
5652 ret = res | (((u64)rep_done & 0xfff) << 32);
5653 if (longmode) {
5654 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5655 } else {
5656 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5657 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5658 }
5659
5660 return 1;
5661}
5662
6aef266c
SV		 5663/*
5664 * kvm_pv_kick_cpu_op: Kick a vcpu.
5665 *
5666 * @apicid - apicid of vcpu to be kicked.
5667 */
5668static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5669{
24d2166b 5670 struct kvm_lapic_irq lapic_irq;
6aef266c 5671
24d2166b
R		 5672 lapic_irq.shorthand = 0;
5673 lapic_irq.dest_mode = 0;
5674 lapic_irq.dest_id = apicid;
6aef266c 5675
24d2166b
R		 5676 lapic_irq.delivery_mode = APIC_DM_REMRD;
5677 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
6aef266c
SV		 5678}
5679
8776e519
HB		 5680int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5681{
5682 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5683 int r = 1;
8776e519 5684
55cd8e5a
GN		 5685 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5686 return kvm_hv_hypercall(vcpu);
5687
5fdbf976
MT		 5688 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5689 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5690 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5691 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5692 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5693
229456fc 5694 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5695
8776e519
HB		 5696 if (!is_long_mode(vcpu)) {
5697 nr &= 0xFFFFFFFF;
5698 a0 &= 0xFFFFFFFF;
5699 a1 &= 0xFFFFFFFF;
5700 a2 &= 0xFFFFFFFF;
5701 a3 &= 0xFFFFFFFF;
5702 }
5703
07708c4a
JK		 5704 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5705 ret = -KVM_EPERM;
5706 goto out;
5707 }
5708
8776e519 5709 switch (nr) {
b93463aa
AK		 5710 case KVM_HC_VAPIC_POLL_IRQ:
5711 ret = 0;
5712 break;
6aef266c
SV		 5713 case KVM_HC_KICK_CPU:
5714 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5715 ret = 0;
5716 break;
8776e519
HB		 5717 default:
5718 ret = -KVM_ENOSYS;
5719 break;
5720 }
07708c4a 5721out:
5fdbf976 5722 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5723 ++vcpu->stat.hypercalls;
2f333bcb 5724 return r;
8776e519
HB		 5725}
5726EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5727
b6785def 5728static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5729{
d6aa1000 5730 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5731 char instruction[3];
5fdbf976 5732 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5733
8776e519 5734 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5735
9d74191a 5736 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5737}
5738
b6c7a5dc
HB		 5739/*
5740 * Check if userspace requested an interrupt window, and that the
5741 * interrupt window is open.
5742 *
5743 * No need to exit to userspace if we already have an interrupt queued.
5744 */
851ba692 5745static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5746{
8061823a 5747 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5748 vcpu->run->request_interrupt_window &&
5df56646 5749 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5750}
5751
851ba692 5752static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5753{
851ba692
AK		 5754 struct kvm_run *kvm_run = vcpu->run;
5755
91586a3b 5756 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5757 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5758 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5759 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5760 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5761 else
b6c7a5dc 5762 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5763 kvm_arch_interrupt_allowed(vcpu) &&
5764 !kvm_cpu_has_interrupt(vcpu) &&
5765 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5766}
5767
95ba8273
GN		 5768static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5769{
5770 int max_irr, tpr;
5771
5772 if (!kvm_x86_ops->update_cr8_intercept)
5773 return;
5774
88c808fd
AK		 5775 if (!vcpu->arch.apic)
5776 return;
5777
8db3baa2
GN		 5778 if (!vcpu->arch.apic->vapic_addr)
5779 max_irr = kvm_lapic_find_highest_irr(vcpu);
5780 else
5781 max_irr = -1;
95ba8273
GN		 5782
5783 if (max_irr != -1)
5784 max_irr >>= 4;
5785
5786 tpr = kvm_lapic_get_cr8(vcpu);
5787
5788 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5789}
5790
851ba692 5791static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5792{
5793 /* try to reinject previous events if any */
b59bb7bd 5794 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5795 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5796 vcpu->arch.exception.has_error_code,
5797 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5798 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5799 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5800 vcpu->arch.exception.error_code,
5801 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5802 return;
5803 }
5804
95ba8273
GN		 5805 if (vcpu->arch.nmi_injected) {
5806 kvm_x86_ops->set_nmi(vcpu);
5807 return;
5808 }
5809
5810 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5811 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5812 return;
5813 }
5814
5815 /* try to inject new event if pending */
5816 if (vcpu->arch.nmi_pending) {
5817 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5818 --vcpu->arch.nmi_pending;
95ba8273
GN		 5819 vcpu->arch.nmi_injected = true;
5820 kvm_x86_ops->set_nmi(vcpu);
5821 }
c7c9c56c 5822 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
95ba8273 5823 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5824 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5825 false);
5826 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5827 }
5828 }
5829}
5830
7460fb4a
AK		 5831static void process_nmi(struct kvm_vcpu *vcpu)
5832{
5833 unsigned limit = 2;
5834
5835 /*
5836 * x86 is limited to one NMI running, and one NMI pending after it.
5837 * If an NMI is already in progress, limit further NMIs to just one.
5838 * Otherwise, allow two (and we'll inject the first one immediately).
5839 */
5840 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5841 limit = 1;
5842
5843 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5844 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5845 kvm_make_request(KVM_REQ_EVENT, vcpu);
5846}
5847
3d81bc7e 5848static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 5849{
5850 u64 eoi_exit_bitmap[4];
cf9e65b7 5851 u32 tmr[8];
c7c9c56c 5852
3d81bc7e
YZ		 5853 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5854 return;
c7c9c56c
YZ		 5855
5856 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 5857 memset(tmr, 0, 32);
c7c9c56c 5858
cf9e65b7 5859 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 5860 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 5861 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 5862}
5863
9357d939
TY		 5864/*
5865 * Returns 1 to let __vcpu_run() continue the guest execution loop without
5866 * exiting to the userspace. Otherwise, the value will be returned to the
5867 * userspace.
5868 */
851ba692 5869static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5870{
5871 int r;
6a8b1d13 5872 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5873 vcpu->run->request_interrupt_window;
730dca42 5874 bool req_immediate_exit = false;
b6c7a5dc 5875
3e007509 5876 if (vcpu->requests) {
a8eeb04a 5877 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5878 kvm_mmu_unload(vcpu);
a8eeb04a 5879 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5880 __kvm_migrate_timers(vcpu);
d828199e
MT		 5881 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5882 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 5883 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5884 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 5885 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5886 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5887 if (unlikely(r))
5888 goto out;
5889 }
a8eeb04a 5890 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5891 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5892 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5893 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5894 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5895 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5896 r = 0;
5897 goto out;
5898 }
a8eeb04a 5899 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5900 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5901 r = 0;
5902 goto out;
5903 }
a8eeb04a 5904 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5905 vcpu->fpu_active = 0;
5906 kvm_x86_ops->fpu_deactivate(vcpu);
5907 }
af585b92
GN		 5908 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5909 /* Page is swapped out. Do synthetic halt */
5910 vcpu->arch.apf.halted = true;
5911 r = 1;
5912 goto out;
5913 }
c9aaa895
GC		 5914 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5915 record_steal_time(vcpu);
7460fb4a
AK		 5916 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5917 process_nmi(vcpu);
f5132b01
GN		 5918 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5919 kvm_handle_pmu_event(vcpu);
5920 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5921 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 5922 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5923 vcpu_scan_ioapic(vcpu);
2f52d58c 5924 }
b93463aa 5925
b463a6f7 5926 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 5927 kvm_apic_accept_events(vcpu);
5928 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5929 r = 1;
5930 goto out;
5931 }
5932
b463a6f7
AK		 5933 inject_pending_event(vcpu);
5934
5935 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5936 if (vcpu->arch.nmi_pending)
03b28f81
JK		 5937 req_immediate_exit =
5938 kvm_x86_ops->enable_nmi_window(vcpu) != 0;
c7c9c56c 5939 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
730dca42
JK		 5940 req_immediate_exit =
5941 kvm_x86_ops->enable_irq_window(vcpu) != 0;
b463a6f7
AK		 5942
5943 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 5944 /*
5945 * Update architecture specific hints for APIC
5946 * virtual interrupt delivery.
5947 */
5948 if (kvm_x86_ops->hwapic_irr_update)
5949 kvm_x86_ops->hwapic_irr_update(vcpu,
5950 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 5951 update_cr8_intercept(vcpu);
5952 kvm_lapic_sync_to_vapic(vcpu);
5953 }
5954 }
5955
d8368af8
AK		 5956 r = kvm_mmu_reload(vcpu);
5957 if (unlikely(r)) {
d905c069 5958 goto cancel_injection;
d8368af8
AK		 5959 }
5960
b6c7a5dc
HB		 5961 preempt_disable();
5962
5963 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5964 if (vcpu->fpu_active)
5965 kvm_load_guest_fpu(vcpu);
2acf923e 5966 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5967
6b7e2d09
XG		 5968 vcpu->mode = IN_GUEST_MODE;
5969
01b71917
MT		 5970 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
5971
6b7e2d09
XG		 5972 /* We should set ->mode before check ->requests,
5973 * see the comment in make_all_cpus_request.
5974 */
01b71917 5975 smp_mb__after_srcu_read_unlock();
b6c7a5dc 5976
d94e1dc9 5977 local_irq_disable();
32f88400 5978
6b7e2d09 5979 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5980 || need_resched() || signal_pending(current)) {
6b7e2d09 5981 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5982 smp_wmb();
6c142801
AK		 5983 local_irq_enable();
5984 preempt_enable();
01b71917 5985 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6c142801 5986 r = 1;
d905c069 5987 goto cancel_injection;
6c142801
AK		 5988 }
5989
d6185f20
NHE		 5990 if (req_immediate_exit)
5991 smp_send_reschedule(vcpu->cpu);
5992
b6c7a5dc
HB		 5993 kvm_guest_enter();
5994
42dbaa5a 5995 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5996 set_debugreg(0, 7);
5997 set_debugreg(vcpu->arch.eff_db[0], 0);
5998 set_debugreg(vcpu->arch.eff_db[1], 1);
5999 set_debugreg(vcpu->arch.eff_db[2], 2);
6000 set_debugreg(vcpu->arch.eff_db[3], 3);
6001 }
b6c7a5dc 6002
229456fc 6003 trace_kvm_entry(vcpu->vcpu_id);
851ba692 6004 kvm_x86_ops->run(vcpu);
b6c7a5dc 6005
24f1e32c
FW		 6006 /*
6007 * If the guest has used debug registers, at least dr7
6008 * will be disabled while returning to the host.
6009 * If we don't have active breakpoints in the host, we don't
6010 * care about the messed up debug address registers. But if
6011 * we have some of them active, restore the old state.
6012 */
59d8eb53 6013 if (hw_breakpoint_active())
24f1e32c 6014 hw_breakpoint_restore();
42dbaa5a 6015
886b470c
MT		 6016 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6017 native_read_tsc());
1d5f066e 6018
6b7e2d09 6019 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6020 smp_wmb();
a547c6db
YZ		 6021
6022 /* Interrupt is enabled by handle_external_intr() */
6023 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6024
6025 ++vcpu->stat.exits;
6026
6027 /*
6028 * We must have an instruction between local_irq_enable() and
6029 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6030 * the interrupt shadow. The stat.exits increment will do nicely.
6031 * But we need to prevent reordering, hence this barrier():
6032 */
6033 barrier();
6034
6035 kvm_guest_exit();
6036
6037 preempt_enable();
6038
f656ce01 6039 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6040
b6c7a5dc
HB		 6041 /*
6042 * Profile KVM exit RIPs:
6043 */
6044 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6045 unsigned long rip = kvm_rip_read(vcpu);
6046 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6047 }
6048
cc578287
ZA		 6049 if (unlikely(vcpu->arch.tsc_always_catchup))
6050 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6051
5cfb1d5a
MT		 6052 if (vcpu->arch.apic_attention)
6053 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6054
851ba692 6055 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6056 return r;
6057
6058cancel_injection:
6059 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6060 if (unlikely(vcpu->arch.apic_attention))
6061 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6062out:
6063 return r;
6064}
b6c7a5dc 6065
09cec754 6066
851ba692 6067static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6068{
6069 int r;
f656ce01 6070 struct kvm *kvm = vcpu->kvm;
d7690175 6071
f656ce01 6072 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175
MT		 6073
6074 r = 1;
6075 while (r > 0) {
af585b92
GN		 6076 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6077 !vcpu->arch.apf.halted)
851ba692 6078 r = vcpu_enter_guest(vcpu);
d7690175 6079 else {
f656ce01 6080 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6081 kvm_vcpu_block(vcpu);
f656ce01 6082 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6083 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6084 kvm_apic_accept_events(vcpu);
09cec754
GN		 6085 switch(vcpu->arch.mp_state) {
6086 case KVM_MP_STATE_HALTED:
6aef266c 6087 vcpu->arch.pv.pv_unhalted = false;
d7690175 6088 vcpu->arch.mp_state =
09cec754
GN		 6089 KVM_MP_STATE_RUNNABLE;
6090 case KVM_MP_STATE_RUNNABLE:
af585b92 6091 vcpu->arch.apf.halted = false;
09cec754 6092 break;
66450a21
JK		 6093 case KVM_MP_STATE_INIT_RECEIVED:
6094 break;
09cec754
GN		 6095 default:
6096 r = -EINTR;
6097 break;
6098 }
6099 }
d7690175
MT		 6100 }
6101
09cec754
GN		 6102 if (r <= 0)
6103 break;
6104
6105 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6106 if (kvm_cpu_has_pending_timer(vcpu))
6107 kvm_inject_pending_timer_irqs(vcpu);
6108
851ba692 6109 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6110 r = -EINTR;
851ba692 6111 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6112 ++vcpu->stat.request_irq_exits;
6113 }
af585b92
GN		 6114
6115 kvm_check_async_pf_completion(vcpu);
6116
09cec754
GN		 6117 if (signal_pending(current)) {
6118 r = -EINTR;
851ba692 6119 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6120 ++vcpu->stat.signal_exits;
6121 }
6122 if (need_resched()) {
f656ce01 6123 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
c08ac06a 6124 cond_resched();
f656ce01 6125 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6126 }
b6c7a5dc
HB		 6127 }
6128
f656ce01 6129 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc
HB		 6130
6131 return r;
6132}
6133
716d51ab
GN		 6134static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6135{
6136 int r;
6137 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6138 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6139 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6140 if (r != EMULATE_DONE)
6141 return 0;
6142 return 1;
6143}
6144
6145static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6146{
6147 BUG_ON(!vcpu->arch.pio.count);
6148
6149 return complete_emulated_io(vcpu);
6150}
6151
f78146b0
AK		 6152/*
6153 * Implements the following, as a state machine:
6154 *
6155 * read:
6156 * for each fragment
87da7e66
XG		 6157 * for each mmio piece in the fragment
6158 * write gpa, len
6159 * exit
6160 * copy data
f78146b0
AK		 6161 * execute insn
6162 *
6163 * write:
6164 * for each fragment
87da7e66
XG		 6165 * for each mmio piece in the fragment
6166 * write gpa, len
6167 * copy data
6168 * exit
f78146b0 6169 */
716d51ab 6170static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6171{
6172 struct kvm_run *run = vcpu->run;
f78146b0 6173 struct kvm_mmio_fragment *frag;
87da7e66 6174 unsigned len;
5287f194 6175
716d51ab 6176 BUG_ON(!vcpu->mmio_needed);
5287f194 6177
716d51ab 6178 /* Complete previous fragment */
87da7e66
XG		 6179 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6180 len = min(8u, frag->len);
716d51ab 6181 if (!vcpu->mmio_is_write)
87da7e66
XG		 6182 memcpy(frag->data, run->mmio.data, len);
6183
6184 if (frag->len <= 8) {
6185 /* Switch to the next fragment. */
6186 frag++;
6187 vcpu->mmio_cur_fragment++;
6188 } else {
6189 /* Go forward to the next mmio piece. */
6190 frag->data += len;
6191 frag->gpa += len;
6192 frag->len -= len;
6193 }
6194
716d51ab
GN		 6195 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
6196 vcpu->mmio_needed = 0;
0912c977
PB		 6197
6198 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6199 if (vcpu->mmio_is_write)
716d51ab
GN		 6200 return 1;
6201 vcpu->mmio_read_completed = 1;
6202 return complete_emulated_io(vcpu);
6203 }
87da7e66 6204
716d51ab
GN		 6205 run->exit_reason = KVM_EXIT_MMIO;
6206 run->mmio.phys_addr = frag->gpa;
6207 if (vcpu->mmio_is_write)
87da7e66
XG		 6208 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6209 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6210 run->mmio.is_write = vcpu->mmio_is_write;
6211 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6212 return 0;
5287f194
AK		 6213}
6214
716d51ab 6215
b6c7a5dc
HB		 6216int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6217{
6218 int r;
6219 sigset_t sigsaved;
6220
e5c30142
AK		 6221 if (!tsk_used_math(current) && init_fpu(current))
6222 return -ENOMEM;
6223
ac9f6dc0
AK		 6224 if (vcpu->sigset_active)
6225 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6226
a4535290 6227 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6228 kvm_vcpu_block(vcpu);
66450a21 6229 kvm_apic_accept_events(vcpu);
d7690175 6230 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6231 r = -EAGAIN;
6232 goto out;
b6c7a5dc
HB		 6233 }
6234
b6c7a5dc 6235 /* re-sync apic's tpr */
eea1cff9
AP		 6236 if (!irqchip_in_kernel(vcpu->kvm)) {
6237 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6238 r = -EINVAL;
6239 goto out;
6240 }
6241 }
b6c7a5dc 6242
716d51ab
GN		 6243 if (unlikely(vcpu->arch.complete_userspace_io)) {
6244 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6245 vcpu->arch.complete_userspace_io = NULL;
6246 r = cui(vcpu);
6247 if (r <= 0)
6248 goto out;
6249 } else
6250 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6251
851ba692 6252 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6253
6254out:
f1d86e46 6255 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6256 if (vcpu->sigset_active)
6257 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6258
b6c7a5dc
HB		 6259 return r;
6260}
6261
6262int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6263{
7ae441ea
GN		 6264 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6265 /*
6266 * We are here if userspace calls get_regs() in the middle of
6267 * instruction emulation. Registers state needs to be copied
4a969980 6268 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6269 * that usually, but some bad designed PV devices (vmware
6270 * backdoor interface) need this to work
6271 */
dd856efa 6272 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6273 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6274 }
5fdbf976
MT		 6275 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6276 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6277 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6278 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6279 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6280 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6281 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6282 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6283#ifdef CONFIG_X86_64
5fdbf976
MT		 6284 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6285 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6286 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6287 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6288 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6289 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6290 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6291 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6292#endif
6293
5fdbf976 6294 regs->rip = kvm_rip_read(vcpu);
91586a3b 6295 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6296
b6c7a5dc
HB		 6297 return 0;
6298}
6299
6300int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6301{
7ae441ea
GN		 6302 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6303 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6304
5fdbf976
MT		 6305 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6306 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6307 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6308 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6309 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6310 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6311 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6312 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6313#ifdef CONFIG_X86_64
5fdbf976
MT		 6314 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6315 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6316 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6317 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6318 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6319 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6320 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6321 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6322#endif
6323
5fdbf976 6324 kvm_rip_write(vcpu, regs->rip);
91586a3b 6325 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6326
b4f14abd
JK		 6327 vcpu->arch.exception.pending = false;
6328
3842d135
AK		 6329 kvm_make_request(KVM_REQ_EVENT, vcpu);
6330
b6c7a5dc
HB		 6331 return 0;
6332}
6333
b6c7a5dc
HB		 6334void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6335{
6336 struct kvm_segment cs;
6337
3e6e0aab 6338 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6339 *db = cs.db;
6340 *l = cs.l;
6341}
6342EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6343
6344int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6345 struct kvm_sregs *sregs)
6346{
89a27f4d 6347 struct desc_ptr dt;
b6c7a5dc 6348
3e6e0aab
GT		 6349 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6350 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6351 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6352 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6353 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6354 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6355
3e6e0aab
GT		 6356 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6357 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6358
6359 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6360 sregs->idt.limit = dt.size;
6361 sregs->idt.base = dt.address;
b6c7a5dc 6362 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6363 sregs->gdt.limit = dt.size;
6364 sregs->gdt.base = dt.address;
b6c7a5dc 6365
4d4ec087 6366 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6367 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6368 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6369 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6370 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6371 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6372 sregs->apic_base = kvm_get_apic_base(vcpu);
6373
923c61bb 6374 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6375
36752c9b 6376 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6377 set_bit(vcpu->arch.interrupt.nr,
6378 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6379
b6c7a5dc
HB		 6380 return 0;
6381}
6382
62d9f0db
MT		 6383int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6384 struct kvm_mp_state *mp_state)
6385{
66450a21 6386 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6387 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6388 vcpu->arch.pv.pv_unhalted)
6389 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6390 else
6391 mp_state->mp_state = vcpu->arch.mp_state;
6392
62d9f0db
MT		 6393 return 0;
6394}
6395
6396int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6397 struct kvm_mp_state *mp_state)
6398{
66450a21
JK		 6399 if (!kvm_vcpu_has_lapic(vcpu) &&
6400 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6401 return -EINVAL;
6402
6403 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6404 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6405 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6406 } else
6407 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6408 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6409 return 0;
6410}
6411
7f3d35fd
KW		 6412int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6413 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6414{
9d74191a 6415 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6416 int ret;
e01c2426 6417
8ec4722d 6418 init_emulate_ctxt(vcpu);
c697518a 6419
7f3d35fd 6420 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6421 has_error_code, error_code);
c697518a 6422
c697518a 6423 if (ret)
19d04437 6424 return EMULATE_FAIL;
37817f29 6425
9d74191a
TY		 6426 kvm_rip_write(vcpu, ctxt->eip);
6427 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6428 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6429 return EMULATE_DONE;
37817f29
IE		 6430}
6431EXPORT_SYMBOL_GPL(kvm_task_switch);
6432
b6c7a5dc
HB		 6433int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6434 struct kvm_sregs *sregs)
6435{
58cb628d 6436 struct msr_data apic_base_msr;
b6c7a5dc 6437 int mmu_reset_needed = 0;
63f42e02 6438 int pending_vec, max_bits, idx;
89a27f4d 6439 struct desc_ptr dt;
b6c7a5dc 6440
6d1068b3
PM		 6441 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6442 return -EINVAL;
6443
89a27f4d
GN		 6444 dt.size = sregs->idt.limit;
6445 dt.address = sregs->idt.base;
b6c7a5dc 6446 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6447 dt.size = sregs->gdt.limit;
6448 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6449 kvm_x86_ops->set_gdt(vcpu, &dt);
6450
ad312c7c 6451 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6452 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6453 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6454 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6455
2d3ad1f4 6456 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6457
f6801dff 6458 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6459 kvm_x86_ops->set_efer(vcpu, sregs->efer);
58cb628d
JK		 6460 apic_base_msr.data = sregs->apic_base;
6461 apic_base_msr.host_initiated = true;
6462 kvm_set_apic_base(vcpu, &apic_base_msr);
b6c7a5dc 6463
4d4ec087 6464 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6465 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6466 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6467
fc78f519 6468 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6469 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6470 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6471 kvm_update_cpuid(vcpu);
63f42e02
XG		 6472
6473 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6474 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6475 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6476 mmu_reset_needed = 1;
6477 }
63f42e02 6478 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6479
6480 if (mmu_reset_needed)
6481 kvm_mmu_reset_context(vcpu);
6482
a50abc3b 6483 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6484 pending_vec = find_first_bit(
6485 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6486 if (pending_vec < max_bits) {
66fd3f7f 6487 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6488 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6489 }
6490
3e6e0aab
GT		 6491 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6492 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6493 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6494 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6495 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6496 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6497
3e6e0aab
GT		 6498 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6499 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6500
5f0269f5
ME		 6501 update_cr8_intercept(vcpu);
6502
9c3e4aab 6503 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6504 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6505 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6506 !is_protmode(vcpu))
9c3e4aab
MT		 6507 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6508
3842d135
AK		 6509 kvm_make_request(KVM_REQ_EVENT, vcpu);
6510
b6c7a5dc
HB		 6511 return 0;
6512}
6513
d0bfb940
JK		 6514int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6515 struct kvm_guest_debug *dbg)
b6c7a5dc 6516{
355be0b9 6517 unsigned long rflags;
ae675ef0 6518 int i, r;
b6c7a5dc 6519
4f926bf2
JK		 6520 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6521 r = -EBUSY;
6522 if (vcpu->arch.exception.pending)
2122ff5e 6523 goto out;
4f926bf2
JK		 6524 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6525 kvm_queue_exception(vcpu, DB_VECTOR);
6526 else
6527 kvm_queue_exception(vcpu, BP_VECTOR);
6528 }
6529
91586a3b
JK		 6530 /*
6531 * Read rflags as long as potentially injected trace flags are still
6532 * filtered out.
6533 */
6534 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6535
6536 vcpu->guest_debug = dbg->control;
6537 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6538 vcpu->guest_debug = 0;
6539
6540 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6541 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6542 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6543 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6544 } else {
6545 for (i = 0; i < KVM_NR_DB_REGS; i++)
6546 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6547 }
c8639010 6548 kvm_update_dr7(vcpu);
ae675ef0 6549
f92653ee
JK		 6550 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6551 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6552 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6553
91586a3b
JK		 6554 /*
6555 * Trigger an rflags update that will inject or remove the trace
6556 * flags.
6557 */
6558 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6559
c8639010 6560 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6561
4f926bf2 6562 r = 0;
d0bfb940 6563
2122ff5e 6564out:
b6c7a5dc
HB		 6565
6566 return r;
6567}
6568
8b006791
ZX		 6569/*
6570 * Translate a guest virtual address to a guest physical address.
6571 */
6572int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6573 struct kvm_translation *tr)
6574{
6575 unsigned long vaddr = tr->linear_address;
6576 gpa_t gpa;
f656ce01 6577 int idx;
8b006791 6578
f656ce01 6579 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6580 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6581 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6582 tr->physical_address = gpa;
6583 tr->valid = gpa != UNMAPPED_GVA;
6584 tr->writeable = 1;
6585 tr->usermode = 0;
8b006791
ZX		 6586
6587 return 0;
6588}
6589
d0752060
HB		 6590int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6591{
98918833
SY		 6592 struct i387_fxsave_struct *fxsave =
6593 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6594
d0752060
HB		 6595 memcpy(fpu->fpr, fxsave->st_space, 128);
6596 fpu->fcw = fxsave->cwd;
6597 fpu->fsw = fxsave->swd;
6598 fpu->ftwx = fxsave->twd;
6599 fpu->last_opcode = fxsave->fop;
6600 fpu->last_ip = fxsave->rip;
6601 fpu->last_dp = fxsave->rdp;
6602 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6603
d0752060
HB		 6604 return 0;
6605}
6606
6607int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6608{
98918833
SY		 6609 struct i387_fxsave_struct *fxsave =
6610 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6611
d0752060
HB		 6612 memcpy(fxsave->st_space, fpu->fpr, 128);
6613 fxsave->cwd = fpu->fcw;
6614 fxsave->swd = fpu->fsw;
6615 fxsave->twd = fpu->ftwx;
6616 fxsave->fop = fpu->last_opcode;
6617 fxsave->rip = fpu->last_ip;
6618 fxsave->rdp = fpu->last_dp;
6619 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6620
d0752060
HB		 6621 return 0;
6622}
6623
10ab25cd 6624int fx_init(struct kvm_vcpu *vcpu)
d0752060 6625{
10ab25cd
JK		 6626 int err;
6627
6628 err = fpu_alloc(&vcpu->arch.guest_fpu);
6629 if (err)
6630 return err;
6631
98918833 6632 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6633
2acf923e
DC		 6634 /*
6635 * Ensure guest xcr0 is valid for loading
6636 */
6637 vcpu->arch.xcr0 = XSTATE_FP;
6638
ad312c7c 6639 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6640
6641 return 0;
d0752060
HB		 6642}
6643EXPORT_SYMBOL_GPL(fx_init);
6644
98918833
SY		 6645static void fx_free(struct kvm_vcpu *vcpu)
6646{
6647 fpu_free(&vcpu->arch.guest_fpu);
6648}
6649
d0752060
HB		 6650void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6651{
2608d7a1 6652 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6653 return;
6654
2acf923e
DC		 6655 /*
6656 * Restore all possible states in the guest,
6657 * and assume host would use all available bits.
6658 * Guest xcr0 would be loaded later.
6659 */
6660 kvm_put_guest_xcr0(vcpu);
d0752060 6661 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6662 __kernel_fpu_begin();
98918833 6663 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6664 trace_kvm_fpu(1);
d0752060 6665}
d0752060
HB		 6666
6667void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6668{
2acf923e
DC		 6669 kvm_put_guest_xcr0(vcpu);
6670
d0752060
HB		 6671 if (!vcpu->guest_fpu_loaded)
6672 return;
6673
6674 vcpu->guest_fpu_loaded = 0;
98918833 6675 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6676 __kernel_fpu_end();
f096ed85 6677 ++vcpu->stat.fpu_reload;
a8eeb04a 6678 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6679 trace_kvm_fpu(0);
d0752060 6680}
e9b11c17
ZX		 6681
6682void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6683{
12f9a48f 6684 kvmclock_reset(vcpu);
7f1ea208 6685
f5f48ee1 6686 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6687 fx_free(vcpu);
e9b11c17
ZX		 6688 kvm_x86_ops->vcpu_free(vcpu);
6689}
6690
6691struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6692 unsigned int id)
6693{
6755bae8
ZA		 6694 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6695 printk_once(KERN_WARNING
6696 "kvm: SMP vm created on host with unstable TSC; "
6697 "guest TSC will not be reliable\n");
26e5215f
AK		 6698 return kvm_x86_ops->vcpu_create(kvm, id);
6699}
e9b11c17 6700
26e5215f
AK		 6701int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6702{
6703 int r;
e9b11c17 6704
0bed3b56 6705 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6706 r = vcpu_load(vcpu);
6707 if (r)
6708 return r;
57f252f2 6709 kvm_vcpu_reset(vcpu);
8a3c1a33 6710 kvm_mmu_setup(vcpu);
e9b11c17 6711 vcpu_put(vcpu);
e9b11c17 6712
26e5215f 6713 return r;
e9b11c17
ZX		 6714}
6715
42897d86
MT		 6716int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6717{
6718 int r;
8fe8ab46 6719 struct msr_data msr;
42897d86
MT		 6720
6721 r = vcpu_load(vcpu);
6722 if (r)
6723 return r;
8fe8ab46
WA		 6724 msr.data = 0x0;
6725 msr.index = MSR_IA32_TSC;
6726 msr.host_initiated = true;
6727 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6728 vcpu_put(vcpu);
6729
6730 return r;
6731}
6732
d40ccc62 6733void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6734{
9fc77441 6735 int r;
344d9588
GN		 6736 vcpu->arch.apf.msr_val = 0;
6737
9fc77441
MT		 6738 r = vcpu_load(vcpu);
6739 BUG_ON(r);
e9b11c17
ZX		 6740 kvm_mmu_unload(vcpu);
6741 vcpu_put(vcpu);
6742
98918833 6743 fx_free(vcpu);
e9b11c17
ZX		 6744 kvm_x86_ops->vcpu_free(vcpu);
6745}
6746
66450a21 6747void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6748{
7460fb4a
AK		 6749 atomic_set(&vcpu->arch.nmi_queued, 0);
6750 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6751 vcpu->arch.nmi_injected = false;
6752
42dbaa5a
JK		 6753 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6754 vcpu->arch.dr6 = DR6_FIXED_1;
73aaf249 6755 kvm_update_dr6(vcpu);
42dbaa5a 6756 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6757 kvm_update_dr7(vcpu);
42dbaa5a 6758
3842d135 6759 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6760 vcpu->arch.apf.msr_val = 0;
c9aaa895 6761 vcpu->arch.st.msr_val = 0;
3842d135 6762
12f9a48f
GC		 6763 kvmclock_reset(vcpu);
6764
af585b92
GN		 6765 kvm_clear_async_pf_completion_queue(vcpu);
6766 kvm_async_pf_hash_reset(vcpu);
6767 vcpu->arch.apf.halted = false;
3842d135 6768
f5132b01
GN		 6769 kvm_pmu_reset(vcpu);
6770
66f7b72e
JS		 6771 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6772 vcpu->arch.regs_avail = ~0;
6773 vcpu->arch.regs_dirty = ~0;
6774
57f252f2 6775 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 6776}
6777
66450a21
JK		 6778void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6779{
6780 struct kvm_segment cs;
6781
6782 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6783 cs.selector = vector << 8;
6784 cs.base = vector << 12;
6785 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6786 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 6787}
6788
10474ae8 6789int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6790{
ca84d1a2
ZA		 6791 struct kvm *kvm;
6792 struct kvm_vcpu *vcpu;
6793 int i;
0dd6a6ed
ZA		 6794 int ret;
6795 u64 local_tsc;
6796 u64 max_tsc = 0;
6797 bool stable, backwards_tsc = false;
18863bdd
AK		 6798
6799 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6800 ret = kvm_x86_ops->hardware_enable(garbage);
6801 if (ret != 0)
6802 return ret;
6803
6804 local_tsc = native_read_tsc();
6805 stable = !check_tsc_unstable();
6806 list_for_each_entry(kvm, &vm_list, vm_list) {
6807 kvm_for_each_vcpu(i, vcpu, kvm) {
6808 if (!stable && vcpu->cpu == smp_processor_id())
6809 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6810 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6811 backwards_tsc = true;
6812 if (vcpu->arch.last_host_tsc > max_tsc)
6813 max_tsc = vcpu->arch.last_host_tsc;
6814 }
6815 }
6816 }
6817
6818 /*
6819 * Sometimes, even reliable TSCs go backwards. This happens on
6820 * platforms that reset TSC during suspend or hibernate actions, but
6821 * maintain synchronization. We must compensate. Fortunately, we can
6822 * detect that condition here, which happens early in CPU bringup,
6823 * before any KVM threads can be running. Unfortunately, we can't
6824 * bring the TSCs fully up to date with real time, as we aren't yet far
6825 * enough into CPU bringup that we know how much real time has actually
6826 * elapsed; our helper function, get_kernel_ns() will be using boot
6827 * variables that haven't been updated yet.
6828 *
6829 * So we simply find the maximum observed TSC above, then record the
6830 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6831 * the adjustment will be applied. Note that we accumulate
6832 * adjustments, in case multiple suspend cycles happen before some VCPU
6833 * gets a chance to run again. In the event that no KVM threads get a
6834 * chance to run, we will miss the entire elapsed period, as we'll have
6835 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6836 * loose cycle time. This isn't too big a deal, since the loss will be
6837 * uniform across all VCPUs (not to mention the scenario is extremely
6838 * unlikely). It is possible that a second hibernate recovery happens
6839 * much faster than a first, causing the observed TSC here to be
6840 * smaller; this would require additional padding adjustment, which is
6841 * why we set last_host_tsc to the local tsc observed here.
6842 *
6843 * N.B. - this code below runs only on platforms with reliable TSC,
6844 * as that is the only way backwards_tsc is set above. Also note
6845 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6846 * have the same delta_cyc adjustment applied if backwards_tsc
6847 * is detected. Note further, this adjustment is only done once,
6848 * as we reset last_host_tsc on all VCPUs to stop this from being
6849 * called multiple times (one for each physical CPU bringup).
6850 *
4a969980 6851 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6852 * will be compensated by the logic in vcpu_load, which sets the TSC to
6853 * catchup mode. This will catchup all VCPUs to real time, but cannot
6854 * guarantee that they stay in perfect synchronization.
6855 */
6856 if (backwards_tsc) {
6857 u64 delta_cyc = max_tsc - local_tsc;
6858 list_for_each_entry(kvm, &vm_list, vm_list) {
6859 kvm_for_each_vcpu(i, vcpu, kvm) {
6860 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6861 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 6862 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6863 &vcpu->requests);
0dd6a6ed
ZA		 6864 }
6865
6866 /*
6867 * We have to disable TSC offset matching.. if you were
6868 * booting a VM while issuing an S4 host suspend....
6869 * you may have some problem. Solving this issue is
6870 * left as an exercise to the reader.
6871 */
6872 kvm->arch.last_tsc_nsec = 0;
6873 kvm->arch.last_tsc_write = 0;
6874 }
6875
6876 }
6877 return 0;
e9b11c17
ZX		 6878}
6879
6880void kvm_arch_hardware_disable(void *garbage)
6881{
6882 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6883 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6884}
6885
6886int kvm_arch_hardware_setup(void)
6887{
6888 return kvm_x86_ops->hardware_setup();
6889}
6890
6891void kvm_arch_hardware_unsetup(void)
6892{
6893 kvm_x86_ops->hardware_unsetup();
6894}
6895
6896void kvm_arch_check_processor_compat(void *rtn)
6897{
6898 kvm_x86_ops->check_processor_compatibility(rtn);
6899}
6900
3e515705
AK		 6901bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6902{
6903 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6904}
6905
54e9818f
GN		 6906struct static_key kvm_no_apic_vcpu __read_mostly;
6907
e9b11c17
ZX		 6908int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6909{
6910 struct page *page;
6911 struct kvm *kvm;
6912 int r;
6913
6914 BUG_ON(vcpu->kvm == NULL);
6915 kvm = vcpu->kvm;
6916
6aef266c 6917 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 6918 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6919 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6920 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6921 else
a4535290 6922 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6923
6924 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6925 if (!page) {
6926 r = -ENOMEM;
6927 goto fail;
6928 }
ad312c7c 6929 vcpu->arch.pio_data = page_address(page);
e9b11c17 6930
cc578287 6931 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6932
e9b11c17
ZX		 6933 r = kvm_mmu_create(vcpu);
6934 if (r < 0)
6935 goto fail_free_pio_data;
6936
6937 if (irqchip_in_kernel(kvm)) {
6938 r = kvm_create_lapic(vcpu);
6939 if (r < 0)
6940 goto fail_mmu_destroy;
54e9818f
GN		 6941 } else
6942 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 6943
890ca9ae
HY		 6944 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6945 GFP_KERNEL);
6946 if (!vcpu->arch.mce_banks) {
6947 r = -ENOMEM;
443c39bc 6948 goto fail_free_lapic;
890ca9ae
HY		 6949 }
6950 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6951
f1797359
WY		 6952 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
6953 r = -ENOMEM;
f5f48ee1 6954 goto fail_free_mce_banks;
f1797359 6955 }
f5f48ee1 6956
66f7b72e
JS		 6957 r = fx_init(vcpu);
6958 if (r)
6959 goto fail_free_wbinvd_dirty_mask;
6960
ba904635 6961 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 6962 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 6963
6964 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 6965 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 6966
af585b92 6967 kvm_async_pf_hash_reset(vcpu);
f5132b01 6968 kvm_pmu_init(vcpu);
af585b92 6969
e9b11c17 6970 return 0;
66f7b72e
JS		 6971fail_free_wbinvd_dirty_mask:
6972 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 6973fail_free_mce_banks:
6974 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6975fail_free_lapic:
6976 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6977fail_mmu_destroy:
6978 kvm_mmu_destroy(vcpu);
6979fail_free_pio_data:
ad312c7c 6980 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6981fail:
6982 return r;
6983}
6984
6985void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6986{
f656ce01
MT		 6987 int idx;
6988
f5132b01 6989 kvm_pmu_destroy(vcpu);
36cb93fd 6990 kfree(vcpu->arch.mce_banks);
e9b11c17 6991 kvm_free_lapic(vcpu);
f656ce01 6992 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6993 kvm_mmu_destroy(vcpu);
f656ce01 6994 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6995 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 6996 if (!irqchip_in_kernel(vcpu->kvm))
6997 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 6998}
d19a9cd2 6999
e08b9637 7000int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 7001{
e08b9637
CO		 7002 if (type)
7003 return -EINVAL;
7004
f05e70ac 7005 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 7006 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 7007 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
e0f0bbc5 7008 atomic_set(&kvm->arch.noncoherent_dma_count, 0);
d19a9cd2 7009
5550af4d
SY		 7010 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7011 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7012 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7013 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7014 &kvm->arch.irq_sources_bitmap);
5550af4d 7015
038f8c11 7016 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7017 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7018 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7019
7020 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7021
d89f5eff 7022 return 0;
d19a9cd2
ZX		 7023}
7024
7025static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7026{
9fc77441
MT		 7027 int r;
7028 r = vcpu_load(vcpu);
7029 BUG_ON(r);
d19a9cd2
ZX		 7030 kvm_mmu_unload(vcpu);
7031 vcpu_put(vcpu);
7032}
7033
7034static void kvm_free_vcpus(struct kvm *kvm)
7035{
7036 unsigned int i;
988a2cae 7037 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7038
7039 /*
7040 * Unpin any mmu pages first.
7041 */
af585b92
GN		 7042 kvm_for_each_vcpu(i, vcpu, kvm) {
7043 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7044 kvm_unload_vcpu_mmu(vcpu);
af585b92 7045 }
988a2cae
GN		 7046 kvm_for_each_vcpu(i, vcpu, kvm)
7047 kvm_arch_vcpu_free(vcpu);
7048
7049 mutex_lock(&kvm->lock);
7050 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7051 kvm->vcpus[i] = NULL;
d19a9cd2 7052
988a2cae
GN		 7053 atomic_set(&kvm->online_vcpus, 0);
7054 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7055}
7056
ad8ba2cd
SY		 7057void kvm_arch_sync_events(struct kvm *kvm)
7058{
ba4cef31 7059 kvm_free_all_assigned_devices(kvm);
aea924f6 7060 kvm_free_pit(kvm);
ad8ba2cd
SY		 7061}
7062
d19a9cd2
ZX		 7063void kvm_arch_destroy_vm(struct kvm *kvm)
7064{
27469d29
AH		 7065 if (current->mm == kvm->mm) {
7066 /*
7067 * Free memory regions allocated on behalf of userspace,
7068 * unless the the memory map has changed due to process exit
7069 * or fd copying.
7070 */
7071 struct kvm_userspace_memory_region mem;
7072 memset(&mem, 0, sizeof(mem));
7073 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7074 kvm_set_memory_region(kvm, &mem);
7075
7076 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7077 kvm_set_memory_region(kvm, &mem);
7078
7079 mem.slot = TSS_PRIVATE_MEMSLOT;
7080 kvm_set_memory_region(kvm, &mem);
7081 }
6eb55818 7082 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7083 kfree(kvm->arch.vpic);
7084 kfree(kvm->arch.vioapic);
d19a9cd2 7085 kvm_free_vcpus(kvm);
3d45830c
AK		 7086 if (kvm->arch.apic_access_page)
7087 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 7088 if (kvm->arch.ept_identity_pagetable)
7089 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 7090 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7091}
0de10343 7092
5587027c 7093void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free,
db3fe4eb
TY		 7094 struct kvm_memory_slot *dont)
7095{
7096 int i;
7097
d89cc617
TY		 7098 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7099 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7100 kvm_kvfree(free->arch.rmap[i]);
7101 free->arch.rmap[i] = NULL;
77d11309 7102 }
d89cc617
TY		 7103 if (i == 0)
7104 continue;
7105
7106 if (!dont || free->arch.lpage_info[i - 1] !=
7107 dont->arch.lpage_info[i - 1]) {
7108 kvm_kvfree(free->arch.lpage_info[i - 1]);
7109 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7110 }
7111 }
7112}
7113
5587027c
AK		 7114int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
7115 unsigned long npages)
db3fe4eb
TY		 7116{
7117 int i;
7118
d89cc617 7119 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7120 unsigned long ugfn;
7121 int lpages;
d89cc617 7122 int level = i + 1;
db3fe4eb
TY		 7123
7124 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7125 slot->base_gfn, level) + 1;
7126
d89cc617
TY		 7127 slot->arch.rmap[i] =
7128 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7129 if (!slot->arch.rmap[i])
77d11309 7130 goto out_free;
d89cc617
TY		 7131 if (i == 0)
7132 continue;
77d11309 7133
d89cc617
TY		 7134 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7135 sizeof(*slot->arch.lpage_info[i - 1]));
7136 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7137 goto out_free;
7138
7139 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7140 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7141 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7142 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7143 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7144 /*
7145 * If the gfn and userspace address are not aligned wrt each
7146 * other, or if explicitly asked to, disable large page
7147 * support for this slot
7148 */
7149 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7150 !kvm_largepages_enabled()) {
7151 unsigned long j;
7152
7153 for (j = 0; j < lpages; ++j)
d89cc617 7154 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7155 }
7156 }
7157
7158 return 0;
7159
7160out_free:
d89cc617
TY		 7161 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7162 kvm_kvfree(slot->arch.rmap[i]);
7163 slot->arch.rmap[i] = NULL;
7164 if (i == 0)
7165 continue;
7166
7167 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7168 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7169 }
7170 return -ENOMEM;
7171}
7172
e59dbe09
TY		 7173void kvm_arch_memslots_updated(struct kvm *kvm)
7174{
e6dff7d1
TY		 7175 /*
7176 * memslots->generation has been incremented.
7177 * mmio generation may have reached its maximum value.
7178 */
7179 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7180}
7181
f7784b8e
MT		 7182int kvm_arch_prepare_memory_region(struct kvm *kvm,
7183 struct kvm_memory_slot *memslot,
f7784b8e 7184 struct kvm_userspace_memory_region *mem,
7b6195a9 7185 enum kvm_mr_change change)
0de10343 7186{
7a905b14
TY		 7187 /*
7188 * Only private memory slots need to be mapped here since
7189 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7190 */
7b6195a9 7191 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7192 unsigned long userspace_addr;
604b38ac 7193
7a905b14
TY		 7194 /*
7195 * MAP_SHARED to prevent internal slot pages from being moved
7196 * by fork()/COW.
7197 */
7b6195a9 7198 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7199 PROT_READ | PROT_WRITE,
7200 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7201
7a905b14
TY		 7202 if (IS_ERR((void *)userspace_addr))
7203 return PTR_ERR((void *)userspace_addr);
604b38ac 7204
7a905b14 7205 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7206 }
7207
f7784b8e
MT		 7208 return 0;
7209}
7210
7211void kvm_arch_commit_memory_region(struct kvm *kvm,
7212 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7213 const struct kvm_memory_slot *old,
7214 enum kvm_mr_change change)
f7784b8e
MT		 7215{
7216
8482644a 7217 int nr_mmu_pages = 0;
f7784b8e 7218
8482644a 7219 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7220 int ret;
7221
8482644a
TY		 7222 ret = vm_munmap(old->userspace_addr,
7223 old->npages * PAGE_SIZE);
f7784b8e
MT		 7224 if (ret < 0)
7225 printk(KERN_WARNING
7226 "kvm_vm_ioctl_set_memory_region: "
7227 "failed to munmap memory\n");
7228 }
7229
48c0e4e9
XG		 7230 if (!kvm->arch.n_requested_mmu_pages)
7231 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7232
48c0e4e9 7233 if (nr_mmu_pages)
0de10343 7234 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7235 /*
7236 * Write protect all pages for dirty logging.
7237 * Existing largepage mappings are destroyed here and new ones will
7238 * not be created until the end of the logging.
7239 */
8482644a 7240 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7241 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7242}
1d737c8a 7243
2df72e9b 7244void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7245{
6ca18b69 7246 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7247}
7248
2df72e9b
MT		 7249void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7250 struct kvm_memory_slot *slot)
7251{
6ca18b69 7252 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7253}
7254
1d737c8a
ZX		 7255int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7256{
af585b92
GN		 7257 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7258 !vcpu->arch.apf.halted)
7259 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7260 || kvm_apic_has_events(vcpu)
6aef266c 7261 || vcpu->arch.pv.pv_unhalted
7460fb4a 7262 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7263 (kvm_arch_interrupt_allowed(vcpu) &&
7264 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7265}
5736199a 7266
b6d33834 7267int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7268{
b6d33834 7269 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7270}
78646121
GN		 7271
7272int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7273{
7274 return kvm_x86_ops->interrupt_allowed(vcpu);
7275}
229456fc 7276
f92653ee
JK		 7277bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7278{
7279 unsigned long current_rip = kvm_rip_read(vcpu) +
7280 get_segment_base(vcpu, VCPU_SREG_CS);
7281
7282 return current_rip == linear_rip;
7283}
7284EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7285
94fe45da
JK		 7286unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7287{
7288 unsigned long rflags;
7289
7290 rflags = kvm_x86_ops->get_rflags(vcpu);
7291 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7292 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7293 return rflags;
7294}
7295EXPORT_SYMBOL_GPL(kvm_get_rflags);
7296
7297void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7298{
7299 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7300 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7301 rflags |= X86_EFLAGS_TF;
94fe45da 7302 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 7303 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7304}
7305EXPORT_SYMBOL_GPL(kvm_set_rflags);
7306
56028d08
GN		 7307void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7308{
7309 int r;
7310
fb67e14f 7311 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
f2e10669 7312 work->wakeup_all)
56028d08
GN		 7313 return;
7314
7315 r = kvm_mmu_reload(vcpu);
7316 if (unlikely(r))
7317 return;
7318
fb67e14f
XG		 7319 if (!vcpu->arch.mmu.direct_map &&
7320 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7321 return;
7322
56028d08
GN		 7323 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7324}
7325
af585b92
GN		 7326static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7327{
7328 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7329}
7330
7331static inline u32 kvm_async_pf_next_probe(u32 key)
7332{
7333 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7334}
7335
7336static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7337{
7338 u32 key = kvm_async_pf_hash_fn(gfn);
7339
7340 while (vcpu->arch.apf.gfns[key] != ~0)
7341 key = kvm_async_pf_next_probe(key);
7342
7343 vcpu->arch.apf.gfns[key] = gfn;
7344}
7345
7346static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7347{
7348 int i;
7349 u32 key = kvm_async_pf_hash_fn(gfn);
7350
7351 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7352 (vcpu->arch.apf.gfns[key] != gfn &&
7353 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7354 key = kvm_async_pf_next_probe(key);
7355
7356 return key;
7357}
7358
7359bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7360{
7361 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7362}
7363
7364static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7365{
7366 u32 i, j, k;
7367
7368 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7369 while (true) {
7370 vcpu->arch.apf.gfns[i] = ~0;
7371 do {
7372 j = kvm_async_pf_next_probe(j);
7373 if (vcpu->arch.apf.gfns[j] == ~0)
7374 return;
7375 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7376 /*
7377 * k lies cyclically in ]i,j]
7378 * | i.k.j |
7379 * |....j i.k.| or |.k..j i...|
7380 */
7381 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7382 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7383 i = j;
7384 }
7385}
7386
7c90705b
GN		 7387static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7388{
7389
7390 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7391 sizeof(val));
7392}
7393
af585b92
GN		 7394void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7395 struct kvm_async_pf *work)
7396{
6389ee94
AK		 7397 struct x86_exception fault;
7398
7c90705b 7399 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7400 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7401
7402 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7403 (vcpu->arch.apf.send_user_only &&
7404 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7405 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7406 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7407 fault.vector = PF_VECTOR;
7408 fault.error_code_valid = true;
7409 fault.error_code = 0;
7410 fault.nested_page_fault = false;
7411 fault.address = work->arch.token;
7412 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7413 }
af585b92
GN		 7414}
7415
7416void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7417 struct kvm_async_pf *work)
7418{
6389ee94
AK		 7419 struct x86_exception fault;
7420
7c90705b 7421 trace_kvm_async_pf_ready(work->arch.token, work->gva);
f2e10669 7422 if (work->wakeup_all)
7c90705b
GN		 7423 work->arch.token = ~0; /* broadcast wakeup */
7424 else
7425 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7426
7427 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7428 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7429 fault.vector = PF_VECTOR;
7430 fault.error_code_valid = true;
7431 fault.error_code = 0;
7432 fault.nested_page_fault = false;
7433 fault.address = work->arch.token;
7434 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7435 }
e6d53e3b 7436 vcpu->arch.apf.halted = false;
a4fa1635 7437 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7438}
7439
7440bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7441{
7442 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7443 return true;
7444 else
7445 return !kvm_event_needs_reinjection(vcpu) &&
7446 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7447}
7448
e0f0bbc5
AW		 7449void kvm_arch_register_noncoherent_dma(struct kvm *kvm)
7450{
7451 atomic_inc(&kvm->arch.noncoherent_dma_count);
7452}
7453EXPORT_SYMBOL_GPL(kvm_arch_register_noncoherent_dma);
7454
7455void kvm_arch_unregister_noncoherent_dma(struct kvm *kvm)
7456{
7457 atomic_dec(&kvm->arch.noncoherent_dma_count);
7458}
7459EXPORT_SYMBOL_GPL(kvm_arch_unregister_noncoherent_dma);
7460
7461bool kvm_arch_has_noncoherent_dma(struct kvm *kvm)
7462{
7463 return atomic_read(&kvm->arch.noncoherent_dma_count);
7464}
7465EXPORT_SYMBOL_GPL(kvm_arch_has_noncoherent_dma);
7466
229456fc
MT		 7467EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7468EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7469EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7470EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7471EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7472EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7473EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7474EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7475EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7476EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7477EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7478EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7479EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
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