]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - arch/x86/kvm/x86.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
KVM: s390: Get rid of KVM_HPAGE defines
[mirror_ubuntu-bionic-kernel.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
9611c187 9 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
043405e1
CO		 10 *
11 * Authors:
12 * Avi Kivity <avi@qumranet.com>
13 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 14 * Amit Shah <amit.shah@qumranet.com>
15 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 */
21
edf88417 22#include <linux/kvm_host.h>
313a3dc7 23#include "irq.h"
1d737c8a 24#include "mmu.h"
7837699f 25#include "i8254.h"
37817f29 26#include "tss.h"
5fdbf976 27#include "kvm_cache_regs.h"
26eef70c 28#include "x86.h"
00b27a3e 29#include "cpuid.h"
313a3dc7 30
18068523 31#include <linux/clocksource.h>
4d5c5d0f 32#include <linux/interrupt.h>
313a3dc7
CO		 33#include <linux/kvm.h>
34#include <linux/fs.h>
35#include <linux/vmalloc.h>
5fb76f9b 36#include <linux/module.h>
0de10343 37#include <linux/mman.h>
2bacc55c 38#include <linux/highmem.h>
19de40a8 39#include <linux/iommu.h>
62c476c7 40#include <linux/intel-iommu.h>
c8076604 41#include <linux/cpufreq.h>
18863bdd 42#include <linux/user-return-notifier.h>
a983fb23 43#include <linux/srcu.h>
5a0e3ad6 44#include <linux/slab.h>
ff9d07a0 45#include <linux/perf_event.h>
7bee342a 46#include <linux/uaccess.h>
af585b92 47#include <linux/hash.h>
a1b60c1c 48#include <linux/pci.h>
16e8d74d
MT		 49#include <linux/timekeeper_internal.h>
50#include <linux/pvclock_gtod.h>
aec51dc4 51#include <trace/events/kvm.h>
2ed152af 52
229456fc
MT		 53#define CREATE_TRACE_POINTS
54#include "trace.h"
043405e1 55
24f1e32c 56#include <asm/debugreg.h>
d825ed0a 57#include <asm/msr.h>
a5f61300 58#include <asm/desc.h>
0bed3b56 59#include <asm/mtrr.h>
890ca9ae 60#include <asm/mce.h>
7cf30855 61#include <asm/i387.h>
1361b83a 62#include <asm/fpu-internal.h> /* Ugh! */
98918833 63#include <asm/xcr.h>
1d5f066e 64#include <asm/pvclock.h>
217fc9cf 65#include <asm/div64.h>
043405e1 66
313a3dc7 67#define MAX_IO_MSRS 256
890ca9ae 68#define KVM_MAX_MCE_BANKS 32
5854dbca 69#define KVM_MCE_CAP_SUPPORTED (MCG_CTL_P | MCG_SER_P)
890ca9ae 70
0f65dd70
AK		 71#define emul_to_vcpu(ctxt) \
72 container_of(ctxt, struct kvm_vcpu, arch.emulate_ctxt)
73
50a37eb4
JR		 74/* EFER defaults:
75 * - enable syscall per default because its emulated by KVM
76 * - enable LME and LMA per default on 64 bit KVM
77 */
78#ifdef CONFIG_X86_64
1260edbe
LJ		 79static
80u64 __read_mostly efer_reserved_bits = ~((u64)(EFER_SCE | EFER_LME | EFER_LMA));
50a37eb4 81#else
1260edbe 82static u64 __read_mostly efer_reserved_bits = ~((u64)EFER_SCE);
50a37eb4 83#endif
313a3dc7 84
ba1389b7
AK		 85#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
86#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 87
cb142eb7 88static void update_cr8_intercept(struct kvm_vcpu *vcpu);
7460fb4a 89static void process_nmi(struct kvm_vcpu *vcpu);
674eea0f 90
97896d04 91struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 92EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 93
476bc001
RR		 94static bool ignore_msrs = 0;
95module_param(ignore_msrs, bool, S_IRUGO | S_IWUSR);
ed85c068 96
92a1f12d
JR		 97bool kvm_has_tsc_control;
98EXPORT_SYMBOL_GPL(kvm_has_tsc_control);
99u32 kvm_max_guest_tsc_khz;
100EXPORT_SYMBOL_GPL(kvm_max_guest_tsc_khz);
101
cc578287
ZA		 102/* tsc tolerance in parts per million - default to 1/2 of the NTP threshold */
103static u32 tsc_tolerance_ppm = 250;
104module_param(tsc_tolerance_ppm, uint, S_IRUGO | S_IWUSR);
105
18863bdd
AK		 106#define KVM_NR_SHARED_MSRS 16
107
108struct kvm_shared_msrs_global {
109 int nr;
2bf78fa7 110 u32 msrs[KVM_NR_SHARED_MSRS];
18863bdd
AK		 111};
112
113struct kvm_shared_msrs {
114 struct user_return_notifier urn;
115 bool registered;
2bf78fa7
SY		 116 struct kvm_shared_msr_values {
117 u64 host;
118 u64 curr;
119 } values[KVM_NR_SHARED_MSRS];
18863bdd
AK		 120};
121
122static struct kvm_shared_msrs_global __read_mostly shared_msrs_global;
013f6a5d 123static struct kvm_shared_msrs __percpu *shared_msrs;
18863bdd 124
417bc304 125struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 126 { "pf_fixed", VCPU_STAT(pf_fixed) },
127 { "pf_guest", VCPU_STAT(pf_guest) },
128 { "tlb_flush", VCPU_STAT(tlb_flush) },
129 { "invlpg", VCPU_STAT(invlpg) },
130 { "exits", VCPU_STAT(exits) },
131 { "io_exits", VCPU_STAT(io_exits) },
132 { "mmio_exits", VCPU_STAT(mmio_exits) },
133 { "signal_exits", VCPU_STAT(signal_exits) },
134 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 135 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 136 { "halt_exits", VCPU_STAT(halt_exits) },
137 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 138 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 139 { "request_irq", VCPU_STAT(request_irq_exits) },
140 { "irq_exits", VCPU_STAT(irq_exits) },
141 { "host_state_reload", VCPU_STAT(host_state_reload) },
142 { "efer_reload", VCPU_STAT(efer_reload) },
143 { "fpu_reload", VCPU_STAT(fpu_reload) },
144 { "insn_emulation", VCPU_STAT(insn_emulation) },
145 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 146 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 147 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 148 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
149 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
150 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
151 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
152 { "mmu_flooded", VM_STAT(mmu_flooded) },
153 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 154 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 155 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 156 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 157 { "largepages", VM_STAT(lpages) },
417bc304
HB		 158 { NULL }
159};
160
2acf923e
DC		 161u64 __read_mostly host_xcr0;
162
b6785def 163static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt);
d6aa1000 164
af585b92
GN		 165static inline void kvm_async_pf_hash_reset(struct kvm_vcpu *vcpu)
166{
167 int i;
168 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU); i++)
169 vcpu->arch.apf.gfns[i] = ~0;
170}
171
18863bdd
AK		 172static void kvm_on_user_return(struct user_return_notifier *urn)
173{
174 unsigned slot;
18863bdd
AK		 175 struct kvm_shared_msrs *locals
176 = container_of(urn, struct kvm_shared_msrs, urn);
2bf78fa7 177 struct kvm_shared_msr_values *values;
18863bdd
AK		 178
179 for (slot = 0; slot < shared_msrs_global.nr; ++slot) {
2bf78fa7
SY		 180 values = &locals->values[slot];
181 if (values->host != values->curr) {
182 wrmsrl(shared_msrs_global.msrs[slot], values->host);
183 values->curr = values->host;
18863bdd
AK		 184 }
185 }
186 locals->registered = false;
187 user_return_notifier_unregister(urn);
188}
189
2bf78fa7 190static void shared_msr_update(unsigned slot, u32 msr)
18863bdd 191{
18863bdd 192 u64 value;
013f6a5d
MT		 193 unsigned int cpu = smp_processor_id();
194 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 195
2bf78fa7
SY		 196 /* only read, and nobody should modify it at this time,
197 * so don't need lock */
198 if (slot >= shared_msrs_global.nr) {
199 printk(KERN_ERR "kvm: invalid MSR slot!");
200 return;
201 }
202 rdmsrl_safe(msr, &value);
203 smsr->values[slot].host = value;
204 smsr->values[slot].curr = value;
205}
206
207void kvm_define_shared_msr(unsigned slot, u32 msr)
208{
18863bdd
AK		 209 if (slot >= shared_msrs_global.nr)
210 shared_msrs_global.nr = slot + 1;
2bf78fa7
SY		 211 shared_msrs_global.msrs[slot] = msr;
212 /* we need ensured the shared_msr_global have been updated */
213 smp_wmb();
18863bdd
AK		 214}
215EXPORT_SYMBOL_GPL(kvm_define_shared_msr);
216
217static void kvm_shared_msr_cpu_online(void)
218{
219 unsigned i;
18863bdd
AK		 220
221 for (i = 0; i < shared_msrs_global.nr; ++i)
2bf78fa7 222 shared_msr_update(i, shared_msrs_global.msrs[i]);
18863bdd
AK		 223}
224
d5696725 225void kvm_set_shared_msr(unsigned slot, u64 value, u64 mask)
18863bdd 226{
013f6a5d
MT		 227 unsigned int cpu = smp_processor_id();
228 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
18863bdd 229
2bf78fa7 230 if (((value ^ smsr->values[slot].curr) & mask) == 0)
18863bdd 231 return;
2bf78fa7
SY		 232 smsr->values[slot].curr = value;
233 wrmsrl(shared_msrs_global.msrs[slot], value);
18863bdd
AK		 234 if (!smsr->registered) {
235 smsr->urn.on_user_return = kvm_on_user_return;
236 user_return_notifier_register(&smsr->urn);
237 smsr->registered = true;
238 }
239}
240EXPORT_SYMBOL_GPL(kvm_set_shared_msr);
241
3548bab5
AK		 242static void drop_user_return_notifiers(void *ignore)
243{
013f6a5d
MT		 244 unsigned int cpu = smp_processor_id();
245 struct kvm_shared_msrs *smsr = per_cpu_ptr(shared_msrs, cpu);
3548bab5
AK		 246
247 if (smsr->registered)
248 kvm_on_user_return(&smsr->urn);
249}
250
6866b83e
CO		 251u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
252{
8a5a87d9 253 return vcpu->arch.apic_base;
6866b83e
CO		 254}
255EXPORT_SYMBOL_GPL(kvm_get_apic_base);
256
257void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
258{
259 /* TODO: reserve bits check */
8a5a87d9 260 kvm_lapic_set_base(vcpu, data);
6866b83e
CO		 261}
262EXPORT_SYMBOL_GPL(kvm_set_apic_base);
263
e3ba45b8
GL		 264asmlinkage void kvm_spurious_fault(void)
265{
266 /* Fault while not rebooting. We want the trace. */
267 BUG();
268}
269EXPORT_SYMBOL_GPL(kvm_spurious_fault);
270
3fd28fce
ED		 271#define EXCPT_BENIGN 0
272#define EXCPT_CONTRIBUTORY 1
273#define EXCPT_PF 2
274
275static int exception_class(int vector)
276{
277 switch (vector) {
278 case PF_VECTOR:
279 return EXCPT_PF;
280 case DE_VECTOR:
281 case TS_VECTOR:
282 case NP_VECTOR:
283 case SS_VECTOR:
284 case GP_VECTOR:
285 return EXCPT_CONTRIBUTORY;
286 default:
287 break;
288 }
289 return EXCPT_BENIGN;
290}
291
292static void kvm_multiple_exception(struct kvm_vcpu *vcpu,
ce7ddec4
JR		 293 unsigned nr, bool has_error, u32 error_code,
294 bool reinject)
3fd28fce
ED		 295{
296 u32 prev_nr;
297 int class1, class2;
298
3842d135
AK		 299 kvm_make_request(KVM_REQ_EVENT, vcpu);
300
3fd28fce
ED		 301 if (!vcpu->arch.exception.pending) {
302 queue:
303 vcpu->arch.exception.pending = true;
304 vcpu->arch.exception.has_error_code = has_error;
305 vcpu->arch.exception.nr = nr;
306 vcpu->arch.exception.error_code = error_code;
3f0fd292 307 vcpu->arch.exception.reinject = reinject;
3fd28fce
ED		 308 return;
309 }
310
311 /* to check exception */
312 prev_nr = vcpu->arch.exception.nr;
313 if (prev_nr == DF_VECTOR) {
314 /* triple fault -> shutdown */
a8eeb04a 315 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3fd28fce
ED		 316 return;
317 }
318 class1 = exception_class(prev_nr);
319 class2 = exception_class(nr);
320 if ((class1 == EXCPT_CONTRIBUTORY && class2 == EXCPT_CONTRIBUTORY)
321 || (class1 == EXCPT_PF && class2 != EXCPT_BENIGN)) {
322 /* generate double fault per SDM Table 5-5 */
323 vcpu->arch.exception.pending = true;
324 vcpu->arch.exception.has_error_code = true;
325 vcpu->arch.exception.nr = DF_VECTOR;
326 vcpu->arch.exception.error_code = 0;
327 } else
328 /* replace previous exception with a new one in a hope
329 that instruction re-execution will regenerate lost
330 exception */
331 goto queue;
332}
333
298101da
AK		 334void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
335{
ce7ddec4 336 kvm_multiple_exception(vcpu, nr, false, 0, false);
298101da
AK		 337}
338EXPORT_SYMBOL_GPL(kvm_queue_exception);
339
ce7ddec4
JR		 340void kvm_requeue_exception(struct kvm_vcpu *vcpu, unsigned nr)
341{
342 kvm_multiple_exception(vcpu, nr, false, 0, true);
343}
344EXPORT_SYMBOL_GPL(kvm_requeue_exception);
345
db8fcefa 346void kvm_complete_insn_gp(struct kvm_vcpu *vcpu, int err)
c3c91fee 347{
db8fcefa
AP		 348 if (err)
349 kvm_inject_gp(vcpu, 0);
350 else
351 kvm_x86_ops->skip_emulated_instruction(vcpu);
352}
353EXPORT_SYMBOL_GPL(kvm_complete_insn_gp);
8df25a32 354
6389ee94 355void kvm_inject_page_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
c3c91fee
AK		 356{
357 ++vcpu->stat.pf_guest;
6389ee94
AK		 358 vcpu->arch.cr2 = fault->address;
359 kvm_queue_exception_e(vcpu, PF_VECTOR, fault->error_code);
c3c91fee 360}
27d6c865 361EXPORT_SYMBOL_GPL(kvm_inject_page_fault);
c3c91fee 362
6389ee94 363void kvm_propagate_fault(struct kvm_vcpu *vcpu, struct x86_exception *fault)
d4f8cf66 364{
6389ee94
AK		 365 if (mmu_is_nested(vcpu) && !fault->nested_page_fault)
366 vcpu->arch.nested_mmu.inject_page_fault(vcpu, fault);
d4f8cf66 367 else
6389ee94 368 vcpu->arch.mmu.inject_page_fault(vcpu, fault);
d4f8cf66
JR		 369}
370
3419ffc8
SY		 371void kvm_inject_nmi(struct kvm_vcpu *vcpu)
372{
7460fb4a
AK		 373 atomic_inc(&vcpu->arch.nmi_queued);
374 kvm_make_request(KVM_REQ_NMI, vcpu);
3419ffc8
SY		 375}
376EXPORT_SYMBOL_GPL(kvm_inject_nmi);
377
298101da
AK		 378void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
379{
ce7ddec4 380 kvm_multiple_exception(vcpu, nr, true, error_code, false);
298101da
AK		 381}
382EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
383
ce7ddec4
JR		 384void kvm_requeue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
385{
386 kvm_multiple_exception(vcpu, nr, true, error_code, true);
387}
388EXPORT_SYMBOL_GPL(kvm_requeue_exception_e);
389
0a79b009
AK		 390/*
391 * Checks if cpl <= required_cpl; if true, return true. Otherwise queue
392 * a #GP and return false.
393 */
394bool kvm_require_cpl(struct kvm_vcpu *vcpu, int required_cpl)
298101da 395{
0a79b009
AK		 396 if (kvm_x86_ops->get_cpl(vcpu) <= required_cpl)
397 return true;
398 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
399 return false;
298101da 400}
0a79b009 401EXPORT_SYMBOL_GPL(kvm_require_cpl);
298101da 402
ec92fe44
JR		 403/*
404 * This function will be used to read from the physical memory of the currently
405 * running guest. The difference to kvm_read_guest_page is that this function
406 * can read from guest physical or from the guest's guest physical memory.
407 */
408int kvm_read_guest_page_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
409 gfn_t ngfn, void *data, int offset, int len,
410 u32 access)
411{
412 gfn_t real_gfn;
413 gpa_t ngpa;
414
415 ngpa = gfn_to_gpa(ngfn);
416 real_gfn = mmu->translate_gpa(vcpu, ngpa, access);
417 if (real_gfn == UNMAPPED_GVA)
418 return -EFAULT;
419
420 real_gfn = gpa_to_gfn(real_gfn);
421
422 return kvm_read_guest_page(vcpu->kvm, real_gfn, data, offset, len);
423}
424EXPORT_SYMBOL_GPL(kvm_read_guest_page_mmu);
425
3d06b8bf
JR		 426int kvm_read_nested_guest_page(struct kvm_vcpu *vcpu, gfn_t gfn,
427 void *data, int offset, int len, u32 access)
428{
429 return kvm_read_guest_page_mmu(vcpu, vcpu->arch.walk_mmu, gfn,
430 data, offset, len, access);
431}
432
a03490ed
CO		 433/*
434 * Load the pae pdptrs. Return true is they are all valid.
435 */
ff03a073 436int load_pdptrs(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, unsigned long cr3)
a03490ed
CO		 437{
438 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
439 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
440 int i;
441 int ret;
ff03a073 442 u64 pdpte[ARRAY_SIZE(mmu->pdptrs)];
a03490ed 443
ff03a073
JR		 444 ret = kvm_read_guest_page_mmu(vcpu, mmu, pdpt_gfn, pdpte,
445 offset * sizeof(u64), sizeof(pdpte),
446 PFERR_USER_MASK|PFERR_WRITE_MASK);
a03490ed
CO		 447 if (ret < 0) {
448 ret = 0;
449 goto out;
450 }
451 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 452 if (is_present_gpte(pdpte[i]) &&
20c466b5 453 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 454 ret = 0;
455 goto out;
456 }
457 }
458 ret = 1;
459
ff03a073 460 memcpy(mmu->pdptrs, pdpte, sizeof(mmu->pdptrs));
6de4f3ad
AK		 461 __set_bit(VCPU_EXREG_PDPTR,
462 (unsigned long *)&vcpu->arch.regs_avail);
463 __set_bit(VCPU_EXREG_PDPTR,
464 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 465out:
a03490ed
CO		 466
467 return ret;
468}
cc4b6871 469EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 470
d835dfec
AK		 471static bool pdptrs_changed(struct kvm_vcpu *vcpu)
472{
ff03a073 473 u64 pdpte[ARRAY_SIZE(vcpu->arch.walk_mmu->pdptrs)];
d835dfec 474 bool changed = true;
3d06b8bf
JR		 475 int offset;
476 gfn_t gfn;
d835dfec
AK		 477 int r;
478
479 if (is_long_mode(vcpu) || !is_pae(vcpu))
480 return false;
481
6de4f3ad
AK		 482 if (!test_bit(VCPU_EXREG_PDPTR,
483 (unsigned long *)&vcpu->arch.regs_avail))
484 return true;
485
9f8fe504
AK		 486 gfn = (kvm_read_cr3(vcpu) & ~31u) >> PAGE_SHIFT;
487 offset = (kvm_read_cr3(vcpu) & ~31u) & (PAGE_SIZE - 1);
3d06b8bf
JR		 488 r = kvm_read_nested_guest_page(vcpu, gfn, pdpte, offset, sizeof(pdpte),
489 PFERR_USER_MASK | PFERR_WRITE_MASK);
d835dfec
AK		 490 if (r < 0)
491 goto out;
ff03a073 492 changed = memcmp(pdpte, vcpu->arch.walk_mmu->pdptrs, sizeof(pdpte)) != 0;
d835dfec 493out:
d835dfec
AK		 494
495 return changed;
496}
497
49a9b07e 498int kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed 499{
aad82703
SY		 500 unsigned long old_cr0 = kvm_read_cr0(vcpu);
501 unsigned long update_bits = X86_CR0_PG | X86_CR0_WP |
502 X86_CR0_CD | X86_CR0_NW;
503
f9a48e6a
AK		 504 cr0 |= X86_CR0_ET;
505
ab344828 506#ifdef CONFIG_X86_64
0f12244f
GN		 507 if (cr0 & 0xffffffff00000000UL)
508 return 1;
ab344828
GN		 509#endif
510
511 cr0 &= ~CR0_RESERVED_BITS;
a03490ed 512
0f12244f
GN		 513 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD))
514 return 1;
a03490ed 515
0f12244f
GN		 516 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE))
517 return 1;
a03490ed
CO		 518
519 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
520#ifdef CONFIG_X86_64
f6801dff 521 if ((vcpu->arch.efer & EFER_LME)) {
a03490ed
CO		 522 int cs_db, cs_l;
523
0f12244f
GN		 524 if (!is_pae(vcpu))
525 return 1;
a03490ed 526 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
0f12244f
GN		 527 if (cs_l)
528 return 1;
a03490ed
CO		 529 } else
530#endif
ff03a073 531 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
9f8fe504 532 kvm_read_cr3(vcpu)))
0f12244f 533 return 1;
a03490ed
CO		 534 }
535
ad756a16
MJ		 536 if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE))
537 return 1;
538
a03490ed 539 kvm_x86_ops->set_cr0(vcpu, cr0);
a03490ed 540
d170c419 541 if ((cr0 ^ old_cr0) & X86_CR0_PG) {
e5f3f027 542 kvm_clear_async_pf_completion_queue(vcpu);
d170c419
LJ		 543 kvm_async_pf_hash_reset(vcpu);
544 }
e5f3f027 545
aad82703
SY		 546 if ((cr0 ^ old_cr0) & update_bits)
547 kvm_mmu_reset_context(vcpu);
0f12244f
GN		 548 return 0;
549}
2d3ad1f4 550EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 551
2d3ad1f4 552void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 553{
49a9b07e 554 (void)kvm_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~0x0eul) | (msw & 0x0f));
a03490ed 555}
2d3ad1f4 556EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 557
42bdf991
MT		 558static void kvm_load_guest_xcr0(struct kvm_vcpu *vcpu)
559{
560 if (kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE) &&
561 !vcpu->guest_xcr0_loaded) {
562 /* kvm_set_xcr() also depends on this */
563 xsetbv(XCR_XFEATURE_ENABLED_MASK, vcpu->arch.xcr0);
564 vcpu->guest_xcr0_loaded = 1;
565 }
566}
567
568static void kvm_put_guest_xcr0(struct kvm_vcpu *vcpu)
569{
570 if (vcpu->guest_xcr0_loaded) {
571 if (vcpu->arch.xcr0 != host_xcr0)
572 xsetbv(XCR_XFEATURE_ENABLED_MASK, host_xcr0);
573 vcpu->guest_xcr0_loaded = 0;
574 }
575}
576
2acf923e
DC		 577int __kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
578{
579 u64 xcr0;
580
581 /* Only support XCR_XFEATURE_ENABLED_MASK(xcr0) now */
582 if (index != XCR_XFEATURE_ENABLED_MASK)
583 return 1;
584 xcr0 = xcr;
2acf923e
DC		 585 if (!(xcr0 & XSTATE_FP))
586 return 1;
587 if ((xcr0 & XSTATE_YMM) && !(xcr0 & XSTATE_SSE))
588 return 1;
d7876f1b 589 if (xcr0 & ~vcpu->arch.guest_supported_xcr0)
2acf923e 590 return 1;
42bdf991 591 kvm_put_guest_xcr0(vcpu);
2acf923e 592 vcpu->arch.xcr0 = xcr0;
2acf923e
DC		 593 return 0;
594}
595
596int kvm_set_xcr(struct kvm_vcpu *vcpu, u32 index, u64 xcr)
597{
764bcbc5
Z		 598 if (kvm_x86_ops->get_cpl(vcpu) != 0 ||
599 __kvm_set_xcr(vcpu, index, xcr)) {
2acf923e
DC		 600 kvm_inject_gp(vcpu, 0);
601 return 1;
602 }
603 return 0;
604}
605EXPORT_SYMBOL_GPL(kvm_set_xcr);
606
a83b29c6 607int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 608{
fc78f519 609 unsigned long old_cr4 = kvm_read_cr4(vcpu);
c68b734f
YW		 610 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE |
611 X86_CR4_PAE | X86_CR4_SMEP;
0f12244f
GN		 612 if (cr4 & CR4_RESERVED_BITS)
613 return 1;
a03490ed 614
2acf923e
DC		 615 if (!guest_cpuid_has_xsave(vcpu) && (cr4 & X86_CR4_OSXSAVE))
616 return 1;
617
c68b734f
YW		 618 if (!guest_cpuid_has_smep(vcpu) && (cr4 & X86_CR4_SMEP))
619 return 1;
620
afcbf13f 621 if (!guest_cpuid_has_fsgsbase(vcpu) && (cr4 & X86_CR4_FSGSBASE))
74dc2b4f
YW		 622 return 1;
623
a03490ed 624 if (is_long_mode(vcpu)) {
0f12244f
GN		 625 if (!(cr4 & X86_CR4_PAE))
626 return 1;
a2edf57f
AK		 627 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
628 && ((cr4 ^ old_cr4) & pdptr_bits)
9f8fe504
AK		 629 && !load_pdptrs(vcpu, vcpu->arch.walk_mmu,
630 kvm_read_cr3(vcpu)))
0f12244f
GN		 631 return 1;
632
ad756a16
MJ		 633 if ((cr4 & X86_CR4_PCIDE) && !(old_cr4 & X86_CR4_PCIDE)) {
634 if (!guest_cpuid_has_pcid(vcpu))
635 return 1;
636
637 /* PCID can not be enabled when cr3[11:0]!=000H or EFER.LMA=0 */
638 if ((kvm_read_cr3(vcpu) & X86_CR3_PCID_MASK) || !is_long_mode(vcpu))
639 return 1;
640 }
641
5e1746d6 642 if (kvm_x86_ops->set_cr4(vcpu, cr4))
0f12244f 643 return 1;
a03490ed 644
ad756a16
MJ		 645 if (((cr4 ^ old_cr4) & pdptr_bits) ||
646 (!(cr4 & X86_CR4_PCIDE) && (old_cr4 & X86_CR4_PCIDE)))
aad82703 647 kvm_mmu_reset_context(vcpu);
0f12244f 648
2acf923e 649 if ((cr4 ^ old_cr4) & X86_CR4_OSXSAVE)
00b27a3e 650 kvm_update_cpuid(vcpu);
2acf923e 651
0f12244f
GN		 652 return 0;
653}
2d3ad1f4 654EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 655
2390218b 656int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 657{
9f8fe504 658 if (cr3 == kvm_read_cr3(vcpu) && !pdptrs_changed(vcpu)) {
0ba73cda 659 kvm_mmu_sync_roots(vcpu);
d835dfec 660 kvm_mmu_flush_tlb(vcpu);
0f12244f 661 return 0;
d835dfec
AK		 662 }
663
a03490ed 664 if (is_long_mode(vcpu)) {
471842ec 665 if (kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) {
ad756a16
MJ		 666 if (cr3 & CR3_PCID_ENABLED_RESERVED_BITS)
667 return 1;
668 } else
669 if (cr3 & CR3_L_MODE_RESERVED_BITS)
670 return 1;
a03490ed
CO		 671 } else {
672 if (is_pae(vcpu)) {
0f12244f
GN		 673 if (cr3 & CR3_PAE_RESERVED_BITS)
674 return 1;
ff03a073
JR		 675 if (is_paging(vcpu) &&
676 !load_pdptrs(vcpu, vcpu->arch.walk_mmu, cr3))
0f12244f 677 return 1;
a03490ed
CO		 678 }
679 /*
680 * We don't check reserved bits in nonpae mode, because
681 * this isn't enforced, and VMware depends on this.
682 */
683 }
684
0f12244f 685 vcpu->arch.cr3 = cr3;
aff48baa 686 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
d8d173da 687 kvm_mmu_new_cr3(vcpu);
0f12244f
GN		 688 return 0;
689}
2d3ad1f4 690EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 691
eea1cff9 692int kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed 693{
0f12244f
GN		 694 if (cr8 & CR8_RESERVED_BITS)
695 return 1;
a03490ed
CO		 696 if (irqchip_in_kernel(vcpu->kvm))
697 kvm_lapic_set_tpr(vcpu, cr8);
698 else
ad312c7c 699 vcpu->arch.cr8 = cr8;
0f12244f
GN		 700 return 0;
701}
2d3ad1f4 702EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 703
2d3ad1f4 704unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 705{
706 if (irqchip_in_kernel(vcpu->kvm))
707 return kvm_lapic_get_cr8(vcpu);
708 else
ad312c7c 709 return vcpu->arch.cr8;
a03490ed 710}
2d3ad1f4 711EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 712
c8639010
JK		 713static void kvm_update_dr7(struct kvm_vcpu *vcpu)
714{
715 unsigned long dr7;
716
717 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
718 dr7 = vcpu->arch.guest_debug_dr7;
719 else
720 dr7 = vcpu->arch.dr7;
721 kvm_x86_ops->set_dr7(vcpu, dr7);
722 vcpu->arch.switch_db_regs = (dr7 & DR7_BP_EN_MASK);
723}
724
338dbc97 725static int __kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
020df079
GN		 726{
727 switch (dr) {
728 case 0 ... 3:
729 vcpu->arch.db[dr] = val;
730 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
731 vcpu->arch.eff_db[dr] = val;
732 break;
733 case 4:
338dbc97
GN		 734 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
735 return 1; /* #UD */
020df079
GN		 736 /* fall through */
737 case 6:
338dbc97
GN		 738 if (val & 0xffffffff00000000ULL)
739 return -1; /* #GP */
020df079
GN		 740 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
741 break;
742 case 5:
338dbc97
GN		 743 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
744 return 1; /* #UD */
020df079
GN		 745 /* fall through */
746 default: /* 7 */
338dbc97
GN		 747 if (val & 0xffffffff00000000ULL)
748 return -1; /* #GP */
020df079 749 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
c8639010 750 kvm_update_dr7(vcpu);
020df079
GN		 751 break;
752 }
753
754 return 0;
755}
338dbc97
GN		 756
757int kvm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long val)
758{
759 int res;
760
761 res = __kvm_set_dr(vcpu, dr, val);
762 if (res > 0)
763 kvm_queue_exception(vcpu, UD_VECTOR);
764 else if (res < 0)
765 kvm_inject_gp(vcpu, 0);
766
767 return res;
768}
020df079
GN		 769EXPORT_SYMBOL_GPL(kvm_set_dr);
770
338dbc97 771static int _kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
020df079
GN		 772{
773 switch (dr) {
774 case 0 ... 3:
775 *val = vcpu->arch.db[dr];
776 break;
777 case 4:
338dbc97 778 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 779 return 1;
020df079
GN		 780 /* fall through */
781 case 6:
782 *val = vcpu->arch.dr6;
783 break;
784 case 5:
338dbc97 785 if (kvm_read_cr4_bits(vcpu, X86_CR4_DE))
020df079 786 return 1;
020df079
GN		 787 /* fall through */
788 default: /* 7 */
789 *val = vcpu->arch.dr7;
790 break;
791 }
792
793 return 0;
794}
338dbc97
GN		 795
796int kvm_get_dr(struct kvm_vcpu *vcpu, int dr, unsigned long *val)
797{
798 if (_kvm_get_dr(vcpu, dr, val)) {
799 kvm_queue_exception(vcpu, UD_VECTOR);
800 return 1;
801 }
802 return 0;
803}
020df079
GN		 804EXPORT_SYMBOL_GPL(kvm_get_dr);
805
022cd0e8
AK		 806bool kvm_rdpmc(struct kvm_vcpu *vcpu)
807{
808 u32 ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
809 u64 data;
810 int err;
811
812 err = kvm_pmu_read_pmc(vcpu, ecx, &data);
813 if (err)
814 return err;
815 kvm_register_write(vcpu, VCPU_REGS_RAX, (u32)data);
816 kvm_register_write(vcpu, VCPU_REGS_RDX, data >> 32);
817 return err;
818}
819EXPORT_SYMBOL_GPL(kvm_rdpmc);
820
043405e1
CO		 821/*
822 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
823 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
824 *
825 * This list is modified at module load time to reflect the
e3267cbb
GC		 826 * capabilities of the host cpu. This capabilities test skips MSRs that are
827 * kvm-specific. Those are put in the beginning of the list.
043405e1 828 */
e3267cbb 829
439793d4 830#define KVM_SAVE_MSRS_BEGIN 10
043405e1 831static u32 msrs_to_save[] = {
e3267cbb 832 MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
11c6bffa 833 MSR_KVM_SYSTEM_TIME_NEW, MSR_KVM_WALL_CLOCK_NEW,
55cd8e5a 834 HV_X64_MSR_GUEST_OS_ID, HV_X64_MSR_HYPERCALL,
c9aaa895 835 HV_X64_MSR_APIC_ASSIST_PAGE, MSR_KVM_ASYNC_PF_EN, MSR_KVM_STEAL_TIME,
ae7a2a3f 836 MSR_KVM_PV_EOI_EN,
043405e1 837 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
8c06585d 838 MSR_STAR,
043405e1
CO		 839#ifdef CONFIG_X86_64
840 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
841#endif
b3897a49
NHE		 842 MSR_IA32_TSC, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA,
843 MSR_IA32_FEATURE_CONTROL
043405e1
CO		 844};
845
846static unsigned num_msrs_to_save;
847
f1d24831 848static const u32 emulated_msrs[] = {
ba904635 849 MSR_IA32_TSC_ADJUST,
a3e06bbe 850 MSR_IA32_TSCDEADLINE,
043405e1 851 MSR_IA32_MISC_ENABLE,
908e75f3
AK		 852 MSR_IA32_MCG_STATUS,
853 MSR_IA32_MCG_CTL,
043405e1
CO		 854};
855
384bb783 856bool kvm_valid_efer(struct kvm_vcpu *vcpu, u64 efer)
15c4a640 857{
b69e8cae 858 if (efer & efer_reserved_bits)
384bb783 859 return false;
15c4a640 860
1b2fd70c
AG		 861 if (efer & EFER_FFXSR) {
862 struct kvm_cpuid_entry2 *feat;
863
864 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 865 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT)))
384bb783 866 return false;
1b2fd70c
AG		 867 }
868
d8017474
AG		 869 if (efer & EFER_SVME) {
870 struct kvm_cpuid_entry2 *feat;
871
872 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
b69e8cae 873 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM)))
384bb783 874 return false;
d8017474
AG		 875 }
876
384bb783
JK		 877 return true;
878}
879EXPORT_SYMBOL_GPL(kvm_valid_efer);
880
881static int set_efer(struct kvm_vcpu *vcpu, u64 efer)
882{
883 u64 old_efer = vcpu->arch.efer;
884
885 if (!kvm_valid_efer(vcpu, efer))
886 return 1;
887
888 if (is_paging(vcpu)
889 && (vcpu->arch.efer & EFER_LME) != (efer & EFER_LME))
890 return 1;
891
15c4a640 892 efer &= ~EFER_LMA;
f6801dff 893 efer |= vcpu->arch.efer & EFER_LMA;
15c4a640 894
a3d204e2
SY		 895 kvm_x86_ops->set_efer(vcpu, efer);
896
aad82703
SY		 897 /* Update reserved bits */
898 if ((efer ^ old_efer) & EFER_NX)
899 kvm_mmu_reset_context(vcpu);
900
b69e8cae 901 return 0;
15c4a640
CO		 902}
903
f2b4b7dd
JR		 904void kvm_enable_efer_bits(u64 mask)
905{
906 efer_reserved_bits &= ~mask;
907}
908EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
909
910
15c4a640
CO		 911/*
912 * Writes msr value into into the appropriate "register".
913 * Returns 0 on success, non-0 otherwise.
914 * Assumes vcpu_load() was already called.
915 */
8fe8ab46 916int kvm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
15c4a640 917{
8fe8ab46 918 return kvm_x86_ops->set_msr(vcpu, msr);
15c4a640
CO		 919}
920
313a3dc7
CO		 921/*
922 * Adapt set_msr() to msr_io()'s calling convention
923 */
924static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
925{
8fe8ab46
WA		 926 struct msr_data msr;
927
928 msr.data = *data;
929 msr.index = index;
930 msr.host_initiated = true;
931 return kvm_set_msr(vcpu, &msr);
313a3dc7
CO		 932}
933
16e8d74d
MT		 934#ifdef CONFIG_X86_64
935struct pvclock_gtod_data {
936 seqcount_t seq;
937
938 struct { /* extract of a clocksource struct */
939 int vclock_mode;
940 cycle_t cycle_last;
941 cycle_t mask;
942 u32 mult;
943 u32 shift;
944 } clock;
945
946 /* open coded 'struct timespec' */
947 u64 monotonic_time_snsec;
948 time_t monotonic_time_sec;
949};
950
951static struct pvclock_gtod_data pvclock_gtod_data;
952
953static void update_pvclock_gtod(struct timekeeper *tk)
954{
955 struct pvclock_gtod_data *vdata = &pvclock_gtod_data;
956
957 write_seqcount_begin(&vdata->seq);
958
959 /* copy pvclock gtod data */
960 vdata->clock.vclock_mode = tk->clock->archdata.vclock_mode;
961 vdata->clock.cycle_last = tk->clock->cycle_last;
962 vdata->clock.mask = tk->clock->mask;
963 vdata->clock.mult = tk->mult;
964 vdata->clock.shift = tk->shift;
965
966 vdata->monotonic_time_sec = tk->xtime_sec
967 + tk->wall_to_monotonic.tv_sec;
968 vdata->monotonic_time_snsec = tk->xtime_nsec
969 + (tk->wall_to_monotonic.tv_nsec
970 << tk->shift);
971 while (vdata->monotonic_time_snsec >=
972 (((u64)NSEC_PER_SEC) << tk->shift)) {
973 vdata->monotonic_time_snsec -=
974 ((u64)NSEC_PER_SEC) << tk->shift;
975 vdata->monotonic_time_sec++;
976 }
977
978 write_seqcount_end(&vdata->seq);
979}
980#endif
981
982
18068523
GOC		 983static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
984{
9ed3c444
AK		 985 int version;
986 int r;
50d0a0f9 987 struct pvclock_wall_clock wc;
923de3cf 988 struct timespec boot;
18068523
GOC		 989
990 if (!wall_clock)
991 return;
992
9ed3c444
AK		 993 r = kvm_read_guest(kvm, wall_clock, &version, sizeof(version));
994 if (r)
995 return;
996
997 if (version & 1)
998 ++version; /* first time write, random junk */
999
1000 ++version;
18068523 1001
18068523
GOC		 1002 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
1003
50d0a0f9
GH		 1004 /*
1005 * The guest calculates current wall clock time by adding
34c238a1 1006 * system time (updated by kvm_guest_time_update below) to the
50d0a0f9
GH		 1007 * wall clock specified here. guest system time equals host
1008 * system time for us, thus we must fill in host boot time here.
1009 */
923de3cf 1010 getboottime(&boot);
50d0a0f9 1011
4b648665
BR		 1012 if (kvm->arch.kvmclock_offset) {
1013 struct timespec ts = ns_to_timespec(kvm->arch.kvmclock_offset);
1014 boot = timespec_sub(boot, ts);
1015 }
50d0a0f9
GH		 1016 wc.sec = boot.tv_sec;
1017 wc.nsec = boot.tv_nsec;
1018 wc.version = version;
18068523
GOC		 1019
1020 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
1021
1022 version++;
1023 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 1024}
1025
50d0a0f9
GH		 1026static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
1027{
1028 uint32_t quotient, remainder;
1029
1030 /* Don't try to replace with do_div(), this one calculates
1031 * "(dividend << 32) / divisor" */
1032 __asm__ ( "divl %4"
1033 : "=a" (quotient), "=d" (remainder)
1034 : "0" (0), "1" (dividend), "r" (divisor) );
1035 return quotient;
1036}
1037
5f4e3f88
ZA		 1038static void kvm_get_time_scale(uint32_t scaled_khz, uint32_t base_khz,
1039 s8 *pshift, u32 *pmultiplier)
50d0a0f9 1040{
5f4e3f88 1041 uint64_t scaled64;
50d0a0f9
GH		 1042 int32_t shift = 0;
1043 uint64_t tps64;
1044 uint32_t tps32;
1045
5f4e3f88
ZA		 1046 tps64 = base_khz * 1000LL;
1047 scaled64 = scaled_khz * 1000LL;
50933623 1048 while (tps64 > scaled64*2 || tps64 & 0xffffffff00000000ULL) {
50d0a0f9
GH		 1049 tps64 >>= 1;
1050 shift--;
1051 }
1052
1053 tps32 = (uint32_t)tps64;
50933623
JK		 1054 while (tps32 <= scaled64 || scaled64 & 0xffffffff00000000ULL) {
1055 if (scaled64 & 0xffffffff00000000ULL || tps32 & 0x80000000)
5f4e3f88
ZA		 1056 scaled64 >>= 1;
1057 else
1058 tps32 <<= 1;
50d0a0f9
GH		 1059 shift++;
1060 }
1061
5f4e3f88
ZA		 1062 *pshift = shift;
1063 *pmultiplier = div_frac(scaled64, tps32);
50d0a0f9 1064
5f4e3f88
ZA		 1065 pr_debug("%s: base_khz %u => %u, shift %d, mul %u\n",
1066 __func__, base_khz, scaled_khz, shift, *pmultiplier);
50d0a0f9
GH		 1067}
1068
759379dd
ZA		 1069static inline u64 get_kernel_ns(void)
1070{
1071 struct timespec ts;
1072
1073 WARN_ON(preemptible());
1074 ktime_get_ts(&ts);
1075 monotonic_to_bootbased(&ts);
1076 return timespec_to_ns(&ts);
50d0a0f9
GH		 1077}
1078
d828199e 1079#ifdef CONFIG_X86_64
16e8d74d 1080static atomic_t kvm_guest_has_master_clock = ATOMIC_INIT(0);
d828199e 1081#endif
16e8d74d 1082
c8076604 1083static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
c285545f 1084unsigned long max_tsc_khz;
c8076604 1085
cc578287 1086static inline u64 nsec_to_cycles(struct kvm_vcpu *vcpu, u64 nsec)
8cfdc000 1087{
cc578287
ZA		 1088 return pvclock_scale_delta(nsec, vcpu->arch.virtual_tsc_mult,
1089 vcpu->arch.virtual_tsc_shift);
8cfdc000
ZA		 1090}
1091
cc578287 1092static u32 adjust_tsc_khz(u32 khz, s32 ppm)
1e993611 1093{
cc578287
ZA		 1094 u64 v = (u64)khz * (1000000 + ppm);
1095 do_div(v, 1000000);
1096 return v;
1e993611
JR		 1097}
1098
cc578287 1099static void kvm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 this_tsc_khz)
759379dd 1100{
cc578287
ZA		 1101 u32 thresh_lo, thresh_hi;
1102 int use_scaling = 0;
217fc9cf 1103
03ba32ca
MT		 1104 /* tsc_khz can be zero if TSC calibration fails */
1105 if (this_tsc_khz == 0)
1106 return;
1107
c285545f
ZA		 1108 /* Compute a scale to convert nanoseconds in TSC cycles */
1109 kvm_get_time_scale(this_tsc_khz, NSEC_PER_SEC / 1000,
cc578287
ZA		 1110 &vcpu->arch.virtual_tsc_shift,
1111 &vcpu->arch.virtual_tsc_mult);
1112 vcpu->arch.virtual_tsc_khz = this_tsc_khz;
1113
1114 /*
1115 * Compute the variation in TSC rate which is acceptable
1116 * within the range of tolerance and decide if the
1117 * rate being applied is within that bounds of the hardware
1118 * rate. If so, no scaling or compensation need be done.
1119 */
1120 thresh_lo = adjust_tsc_khz(tsc_khz, -tsc_tolerance_ppm);
1121 thresh_hi = adjust_tsc_khz(tsc_khz, tsc_tolerance_ppm);
1122 if (this_tsc_khz < thresh_lo || this_tsc_khz > thresh_hi) {
1123 pr_debug("kvm: requested TSC rate %u falls outside tolerance [%u,%u]\n", this_tsc_khz, thresh_lo, thresh_hi);
1124 use_scaling = 1;
1125 }
1126 kvm_x86_ops->set_tsc_khz(vcpu, this_tsc_khz, use_scaling);
c285545f
ZA		 1127}
1128
1129static u64 compute_guest_tsc(struct kvm_vcpu *vcpu, s64 kernel_ns)
1130{
e26101b1 1131 u64 tsc = pvclock_scale_delta(kernel_ns-vcpu->arch.this_tsc_nsec,
cc578287
ZA		 1132 vcpu->arch.virtual_tsc_mult,
1133 vcpu->arch.virtual_tsc_shift);
e26101b1 1134 tsc += vcpu->arch.this_tsc_write;
c285545f
ZA		 1135 return tsc;
1136}
1137
b48aa97e
MT		 1138void kvm_track_tsc_matching(struct kvm_vcpu *vcpu)
1139{
1140#ifdef CONFIG_X86_64
1141 bool vcpus_matched;
1142 bool do_request = false;
1143 struct kvm_arch *ka = &vcpu->kvm->arch;
1144 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1145
1146 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1147 atomic_read(&vcpu->kvm->online_vcpus));
1148
1149 if (vcpus_matched && gtod->clock.vclock_mode == VCLOCK_TSC)
1150 if (!ka->use_master_clock)
1151 do_request = 1;
1152
1153 if (!vcpus_matched && ka->use_master_clock)
1154 do_request = 1;
1155
1156 if (do_request)
1157 kvm_make_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu);
1158
1159 trace_kvm_track_tsc(vcpu->vcpu_id, ka->nr_vcpus_matched_tsc,
1160 atomic_read(&vcpu->kvm->online_vcpus),
1161 ka->use_master_clock, gtod->clock.vclock_mode);
1162#endif
1163}
1164
ba904635
WA		 1165static void update_ia32_tsc_adjust_msr(struct kvm_vcpu *vcpu, s64 offset)
1166{
1167 u64 curr_offset = kvm_x86_ops->read_tsc_offset(vcpu);
1168 vcpu->arch.ia32_tsc_adjust_msr += offset - curr_offset;
1169}
1170
8fe8ab46 1171void kvm_write_tsc(struct kvm_vcpu *vcpu, struct msr_data *msr)
99e3e30a
ZA		 1172{
1173 struct kvm *kvm = vcpu->kvm;
f38e098f 1174 u64 offset, ns, elapsed;
99e3e30a 1175 unsigned long flags;
02626b6a 1176 s64 usdiff;
b48aa97e 1177 bool matched;
8fe8ab46 1178 u64 data = msr->data;
99e3e30a 1179
038f8c11 1180 raw_spin_lock_irqsave(&kvm->arch.tsc_write_lock, flags);
857e4099 1181 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1182 ns = get_kernel_ns();
f38e098f 1183 elapsed = ns - kvm->arch.last_tsc_nsec;
5d3cb0f6 1184
03ba32ca 1185 if (vcpu->arch.virtual_tsc_khz) {
8915aa27
MT		 1186 int faulted = 0;
1187
03ba32ca
MT		 1188 /* n.b - signed multiplication and division required */
1189 usdiff = data - kvm->arch.last_tsc_write;
5d3cb0f6 1190#ifdef CONFIG_X86_64
03ba32ca 1191 usdiff = (usdiff * 1000) / vcpu->arch.virtual_tsc_khz;
5d3cb0f6 1192#else
03ba32ca 1193 /* do_div() only does unsigned */
8915aa27
MT		 1194 asm("1: idivl %[divisor]\n"
1195 "2: xor %%edx, %%edx\n"
1196 " movl $0, %[faulted]\n"
1197 "3:\n"
1198 ".section .fixup,\"ax\"\n"
1199 "4: movl $1, %[faulted]\n"
1200 " jmp 3b\n"
1201 ".previous\n"
1202
1203 _ASM_EXTABLE(1b, 4b)
1204
1205 : "=A"(usdiff), [faulted] "=r" (faulted)
1206 : "A"(usdiff * 1000), [divisor] "rm"(vcpu->arch.virtual_tsc_khz));
1207
5d3cb0f6 1208#endif
03ba32ca
MT		 1209 do_div(elapsed, 1000);
1210 usdiff -= elapsed;
1211 if (usdiff < 0)
1212 usdiff = -usdiff;
8915aa27
MT		 1213
1214 /* idivl overflow => difference is larger than USEC_PER_SEC */
1215 if (faulted)
1216 usdiff = USEC_PER_SEC;
03ba32ca
MT		 1217 } else
1218 usdiff = USEC_PER_SEC; /* disable TSC match window below */
f38e098f
ZA		 1219
1220 /*
5d3cb0f6
ZA		 1221 * Special case: TSC write with a small delta (1 second) of virtual
1222 * cycle time against real time is interpreted as an attempt to
1223 * synchronize the CPU.
1224 *
1225 * For a reliable TSC, we can match TSC offsets, and for an unstable
1226 * TSC, we add elapsed time in this computation. We could let the
1227 * compensation code attempt to catch up if we fall behind, but
1228 * it's better to try to match offsets from the beginning.
1229 */
02626b6a 1230 if (usdiff < USEC_PER_SEC &&
5d3cb0f6 1231 vcpu->arch.virtual_tsc_khz == kvm->arch.last_tsc_khz) {
f38e098f 1232 if (!check_tsc_unstable()) {
e26101b1 1233 offset = kvm->arch.cur_tsc_offset;
f38e098f
ZA		 1234 pr_debug("kvm: matched tsc offset for %llu\n", data);
1235 } else {
857e4099 1236 u64 delta = nsec_to_cycles(vcpu, elapsed);
5d3cb0f6
ZA		 1237 data += delta;
1238 offset = kvm_x86_ops->compute_tsc_offset(vcpu, data);
759379dd 1239 pr_debug("kvm: adjusted tsc offset by %llu\n", delta);
f38e098f 1240 }
b48aa97e 1241 matched = true;
e26101b1
ZA		 1242 } else {
1243 /*
1244 * We split periods of matched TSC writes into generations.
1245 * For each generation, we track the original measured
1246 * nanosecond time, offset, and write, so if TSCs are in
1247 * sync, we can match exact offset, and if not, we can match
4a969980 1248 * exact software computation in compute_guest_tsc()
e26101b1
ZA		 1249 *
1250 * These values are tracked in kvm->arch.cur_xxx variables.
1251 */
1252 kvm->arch.cur_tsc_generation++;
1253 kvm->arch.cur_tsc_nsec = ns;
1254 kvm->arch.cur_tsc_write = data;
1255 kvm->arch.cur_tsc_offset = offset;
b48aa97e 1256 matched = false;
e26101b1
ZA		 1257 pr_debug("kvm: new tsc generation %u, clock %llu\n",
1258 kvm->arch.cur_tsc_generation, data);
f38e098f 1259 }
e26101b1
ZA		 1260
1261 /*
1262 * We also track th most recent recorded KHZ, write and time to
1263 * allow the matching interval to be extended at each write.
1264 */
f38e098f
ZA		 1265 kvm->arch.last_tsc_nsec = ns;
1266 kvm->arch.last_tsc_write = data;
5d3cb0f6 1267 kvm->arch.last_tsc_khz = vcpu->arch.virtual_tsc_khz;
99e3e30a
ZA		 1268
1269 /* Reset of TSC must disable overshoot protection below */
1270 vcpu->arch.hv_clock.tsc_timestamp = 0;
b183aa58 1271 vcpu->arch.last_guest_tsc = data;
e26101b1
ZA		 1272
1273 /* Keep track of which generation this VCPU has synchronized to */
1274 vcpu->arch.this_tsc_generation = kvm->arch.cur_tsc_generation;
1275 vcpu->arch.this_tsc_nsec = kvm->arch.cur_tsc_nsec;
1276 vcpu->arch.this_tsc_write = kvm->arch.cur_tsc_write;
1277
ba904635
WA		 1278 if (guest_cpuid_has_tsc_adjust(vcpu) && !msr->host_initiated)
1279 update_ia32_tsc_adjust_msr(vcpu, offset);
e26101b1
ZA		 1280 kvm_x86_ops->write_tsc_offset(vcpu, offset);
1281 raw_spin_unlock_irqrestore(&kvm->arch.tsc_write_lock, flags);
b48aa97e
MT		 1282
1283 spin_lock(&kvm->arch.pvclock_gtod_sync_lock);
1284 if (matched)
1285 kvm->arch.nr_vcpus_matched_tsc++;
1286 else
1287 kvm->arch.nr_vcpus_matched_tsc = 0;
1288
1289 kvm_track_tsc_matching(vcpu);
1290 spin_unlock(&kvm->arch.pvclock_gtod_sync_lock);
99e3e30a 1291}
e26101b1 1292
99e3e30a
ZA		 1293EXPORT_SYMBOL_GPL(kvm_write_tsc);
1294
d828199e
MT		 1295#ifdef CONFIG_X86_64
1296
1297static cycle_t read_tsc(void)
1298{
1299 cycle_t ret;
1300 u64 last;
1301
1302 /*
1303 * Empirically, a fence (of type that depends on the CPU)
1304 * before rdtsc is enough to ensure that rdtsc is ordered
1305 * with respect to loads. The various CPU manuals are unclear
1306 * as to whether rdtsc can be reordered with later loads,
1307 * but no one has ever seen it happen.
1308 */
1309 rdtsc_barrier();
1310 ret = (cycle_t)vget_cycles();
1311
1312 last = pvclock_gtod_data.clock.cycle_last;
1313
1314 if (likely(ret >= last))
1315 return ret;
1316
1317 /*
1318 * GCC likes to generate cmov here, but this branch is extremely
1319 * predictable (it's just a funciton of time and the likely is
1320 * very likely) and there's a data dependence, so force GCC
1321 * to generate a branch instead. I don't barrier() because
1322 * we don't actually need a barrier, and if this function
1323 * ever gets inlined it will generate worse code.
1324 */
1325 asm volatile ("");
1326 return last;
1327}
1328
1329static inline u64 vgettsc(cycle_t *cycle_now)
1330{
1331 long v;
1332 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1333
1334 *cycle_now = read_tsc();
1335
1336 v = (*cycle_now - gtod->clock.cycle_last) & gtod->clock.mask;
1337 return v * gtod->clock.mult;
1338}
1339
1340static int do_monotonic(struct timespec *ts, cycle_t *cycle_now)
1341{
1342 unsigned long seq;
1343 u64 ns;
1344 int mode;
1345 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
1346
1347 ts->tv_nsec = 0;
1348 do {
1349 seq = read_seqcount_begin(&gtod->seq);
1350 mode = gtod->clock.vclock_mode;
1351 ts->tv_sec = gtod->monotonic_time_sec;
1352 ns = gtod->monotonic_time_snsec;
1353 ns += vgettsc(cycle_now);
1354 ns >>= gtod->clock.shift;
1355 } while (unlikely(read_seqcount_retry(&gtod->seq, seq)));
1356 timespec_add_ns(ts, ns);
1357
1358 return mode;
1359}
1360
1361/* returns true if host is using tsc clocksource */
1362static bool kvm_get_time_and_clockread(s64 *kernel_ns, cycle_t *cycle_now)
1363{
1364 struct timespec ts;
1365
1366 /* checked again under seqlock below */
1367 if (pvclock_gtod_data.clock.vclock_mode != VCLOCK_TSC)
1368 return false;
1369
1370 if (do_monotonic(&ts, cycle_now) != VCLOCK_TSC)
1371 return false;
1372
1373 monotonic_to_bootbased(&ts);
1374 *kernel_ns = timespec_to_ns(&ts);
1375
1376 return true;
1377}
1378#endif
1379
1380/*
1381 *
b48aa97e
MT		 1382 * Assuming a stable TSC across physical CPUS, and a stable TSC
1383 * across virtual CPUs, the following condition is possible.
1384 * Each numbered line represents an event visible to both
d828199e
MT		 1385 * CPUs at the next numbered event.
1386 *
1387 * "timespecX" represents host monotonic time. "tscX" represents
1388 * RDTSC value.
1389 *
1390 * VCPU0 on CPU0 | VCPU1 on CPU1
1391 *
1392 * 1. read timespec0,tsc0
1393 * 2. | timespec1 = timespec0 + N
1394 * | tsc1 = tsc0 + M
1395 * 3. transition to guest | transition to guest
1396 * 4. ret0 = timespec0 + (rdtsc - tsc0) |
1397 * 5. | ret1 = timespec1 + (rdtsc - tsc1)
1398 * | ret1 = timespec0 + N + (rdtsc - (tsc0 + M))
1399 *
1400 * Since ret0 update is visible to VCPU1 at time 5, to obey monotonicity:
1401 *
1402 * - ret0 < ret1
1403 * - timespec0 + (rdtsc - tsc0) < timespec0 + N + (rdtsc - (tsc0 + M))
1404 * ...
1405 * - 0 < N - M => M < N
1406 *
1407 * That is, when timespec0 != timespec1, M < N. Unfortunately that is not
1408 * always the case (the difference between two distinct xtime instances
1409 * might be smaller then the difference between corresponding TSC reads,
1410 * when updating guest vcpus pvclock areas).
1411 *
1412 * To avoid that problem, do not allow visibility of distinct
1413 * system_timestamp/tsc_timestamp values simultaneously: use a master
1414 * copy of host monotonic time values. Update that master copy
1415 * in lockstep.
1416 *
b48aa97e 1417 * Rely on synchronization of host TSCs and guest TSCs for monotonicity.
d828199e
MT		 1418 *
1419 */
1420
1421static void pvclock_update_vm_gtod_copy(struct kvm *kvm)
1422{
1423#ifdef CONFIG_X86_64
1424 struct kvm_arch *ka = &kvm->arch;
1425 int vclock_mode;
b48aa97e
MT		 1426 bool host_tsc_clocksource, vcpus_matched;
1427
1428 vcpus_matched = (ka->nr_vcpus_matched_tsc + 1 ==
1429 atomic_read(&kvm->online_vcpus));
d828199e
MT		 1430
1431 /*
1432 * If the host uses TSC clock, then passthrough TSC as stable
1433 * to the guest.
1434 */
b48aa97e 1435 host_tsc_clocksource = kvm_get_time_and_clockread(
d828199e
MT		 1436 &ka->master_kernel_ns,
1437 &ka->master_cycle_now);
1438
b48aa97e
MT		 1439 ka->use_master_clock = host_tsc_clocksource & vcpus_matched;
1440
d828199e
MT		 1441 if (ka->use_master_clock)
1442 atomic_set(&kvm_guest_has_master_clock, 1);
1443
1444 vclock_mode = pvclock_gtod_data.clock.vclock_mode;
b48aa97e
MT		 1445 trace_kvm_update_master_clock(ka->use_master_clock, vclock_mode,
1446 vcpus_matched);
d828199e
MT		 1447#endif
1448}
1449
2e762ff7
MT		 1450static void kvm_gen_update_masterclock(struct kvm *kvm)
1451{
1452#ifdef CONFIG_X86_64
1453 int i;
1454 struct kvm_vcpu *vcpu;
1455 struct kvm_arch *ka = &kvm->arch;
1456
1457 spin_lock(&ka->pvclock_gtod_sync_lock);
1458 kvm_make_mclock_inprogress_request(kvm);
1459 /* no guest entries from this point */
1460 pvclock_update_vm_gtod_copy(kvm);
1461
1462 kvm_for_each_vcpu(i, vcpu, kvm)
1463 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1464
1465 /* guest entries allowed */
1466 kvm_for_each_vcpu(i, vcpu, kvm)
1467 clear_bit(KVM_REQ_MCLOCK_INPROGRESS, &vcpu->requests);
1468
1469 spin_unlock(&ka->pvclock_gtod_sync_lock);
1470#endif
1471}
1472
34c238a1 1473static int kvm_guest_time_update(struct kvm_vcpu *v)
18068523 1474{
d828199e 1475 unsigned long flags, this_tsc_khz;
18068523 1476 struct kvm_vcpu_arch *vcpu = &v->arch;
d828199e 1477 struct kvm_arch *ka = &v->kvm->arch;
1d5f066e 1478 s64 kernel_ns, max_kernel_ns;
d828199e 1479 u64 tsc_timestamp, host_tsc;
0b79459b 1480 struct pvclock_vcpu_time_info guest_hv_clock;
51d59c6b 1481 u8 pvclock_flags;
d828199e
MT		 1482 bool use_master_clock;
1483
1484 kernel_ns = 0;
1485 host_tsc = 0;
18068523 1486
d828199e
MT		 1487 /*
1488 * If the host uses TSC clock, then passthrough TSC as stable
1489 * to the guest.
1490 */
1491 spin_lock(&ka->pvclock_gtod_sync_lock);
1492 use_master_clock = ka->use_master_clock;
1493 if (use_master_clock) {
1494 host_tsc = ka->master_cycle_now;
1495 kernel_ns = ka->master_kernel_ns;
1496 }
1497 spin_unlock(&ka->pvclock_gtod_sync_lock);
c09664bb
MT		 1498
1499 /* Keep irq disabled to prevent changes to the clock */
1500 local_irq_save(flags);
1501 this_tsc_khz = __get_cpu_var(cpu_tsc_khz);
1502 if (unlikely(this_tsc_khz == 0)) {
1503 local_irq_restore(flags);
1504 kvm_make_request(KVM_REQ_CLOCK_UPDATE, v);
1505 return 1;
1506 }
d828199e
MT		 1507 if (!use_master_clock) {
1508 host_tsc = native_read_tsc();
1509 kernel_ns = get_kernel_ns();
1510 }
1511
1512 tsc_timestamp = kvm_x86_ops->read_l1_tsc(v, host_tsc);
1513
c285545f
ZA		 1514 /*
1515 * We may have to catch up the TSC to match elapsed wall clock
1516 * time for two reasons, even if kvmclock is used.
1517 * 1) CPU could have been running below the maximum TSC rate
1518 * 2) Broken TSC compensation resets the base at each VCPU
1519 * entry to avoid unknown leaps of TSC even when running
1520 * again on the same CPU. This may cause apparent elapsed
1521 * time to disappear, and the guest to stand still or run
1522 * very slowly.
1523 */
1524 if (vcpu->tsc_catchup) {
1525 u64 tsc = compute_guest_tsc(v, kernel_ns);
1526 if (tsc > tsc_timestamp) {
f1e2b260 1527 adjust_tsc_offset_guest(v, tsc - tsc_timestamp);
c285545f
ZA		 1528 tsc_timestamp = tsc;
1529 }
50d0a0f9
GH		 1530 }
1531
18068523
GOC		 1532 local_irq_restore(flags);
1533
0b79459b 1534 if (!vcpu->pv_time_enabled)
c285545f 1535 return 0;
18068523 1536
1d5f066e
ZA		 1537 /*
1538 * Time as measured by the TSC may go backwards when resetting the base
1539 * tsc_timestamp. The reason for this is that the TSC resolution is
1540 * higher than the resolution of the other clock scales. Thus, many
1541 * possible measurments of the TSC correspond to one measurement of any
1542 * other clock, and so a spread of values is possible. This is not a
1543 * problem for the computation of the nanosecond clock; with TSC rates
1544 * around 1GHZ, there can only be a few cycles which correspond to one
1545 * nanosecond value, and any path through this code will inevitably
1546 * take longer than that. However, with the kernel_ns value itself,
1547 * the precision may be much lower, down to HZ granularity. If the
1548 * first sampling of TSC against kernel_ns ends in the low part of the
1549 * range, and the second in the high end of the range, we can get:
1550 *
1551 * (TSC - offset_low) * S + kns_old > (TSC - offset_high) * S + kns_new
1552 *
1553 * As the sampling errors potentially range in the thousands of cycles,
1554 * it is possible such a time value has already been observed by the
1555 * guest. To protect against this, we must compute the system time as
1556 * observed by the guest and ensure the new system time is greater.
1557 */
1558 max_kernel_ns = 0;
b183aa58 1559 if (vcpu->hv_clock.tsc_timestamp) {
1d5f066e
ZA		 1560 max_kernel_ns = vcpu->last_guest_tsc -
1561 vcpu->hv_clock.tsc_timestamp;
1562 max_kernel_ns = pvclock_scale_delta(max_kernel_ns,
1563 vcpu->hv_clock.tsc_to_system_mul,
1564 vcpu->hv_clock.tsc_shift);
1565 max_kernel_ns += vcpu->last_kernel_ns;
1566 }
afbcf7ab 1567
e48672fa 1568 if (unlikely(vcpu->hw_tsc_khz != this_tsc_khz)) {
5f4e3f88
ZA		 1569 kvm_get_time_scale(NSEC_PER_SEC / 1000, this_tsc_khz,
1570 &vcpu->hv_clock.tsc_shift,
1571 &vcpu->hv_clock.tsc_to_system_mul);
e48672fa 1572 vcpu->hw_tsc_khz = this_tsc_khz;
8cfdc000
ZA		 1573 }
1574
d828199e
MT		 1575 /* with a master <monotonic time, tsc value> tuple,
1576 * pvclock clock reads always increase at the (scaled) rate
1577 * of guest TSC - no need to deal with sampling errors.
1578 */
1579 if (!use_master_clock) {
1580 if (max_kernel_ns > kernel_ns)
1581 kernel_ns = max_kernel_ns;
1582 }
8cfdc000 1583 /* With all the info we got, fill in the values */
1d5f066e 1584 vcpu->hv_clock.tsc_timestamp = tsc_timestamp;
759379dd 1585 vcpu->hv_clock.system_time = kernel_ns + v->kvm->arch.kvmclock_offset;
1d5f066e 1586 vcpu->last_kernel_ns = kernel_ns;
28e4639a 1587 vcpu->last_guest_tsc = tsc_timestamp;
51d59c6b 1588
18068523
GOC		 1589 /*
1590 * The interface expects us to write an even number signaling that the
1591 * update is finished. Since the guest won't see the intermediate
50d0a0f9 1592 * state, we just increase by 2 at the end.
18068523 1593 */
50d0a0f9 1594 vcpu->hv_clock.version += 2;
18068523 1595
0b79459b
AH		 1596 if (unlikely(kvm_read_guest_cached(v->kvm, &vcpu->pv_time,
1597 &guest_hv_clock, sizeof(guest_hv_clock))))
1598 return 0;
78c0337a
MT		 1599
1600 /* retain PVCLOCK_GUEST_STOPPED if set in guest copy */
0b79459b 1601 pvclock_flags = (guest_hv_clock.flags & PVCLOCK_GUEST_STOPPED);
78c0337a
MT		 1602
1603 if (vcpu->pvclock_set_guest_stopped_request) {
1604 pvclock_flags |= PVCLOCK_GUEST_STOPPED;
1605 vcpu->pvclock_set_guest_stopped_request = false;
1606 }
1607
d828199e
MT		 1608 /* If the host uses TSC clocksource, then it is stable */
1609 if (use_master_clock)
1610 pvclock_flags |= PVCLOCK_TSC_STABLE_BIT;
1611
78c0337a
MT		 1612 vcpu->hv_clock.flags = pvclock_flags;
1613
0b79459b
AH		 1614 kvm_write_guest_cached(v->kvm, &vcpu->pv_time,
1615 &vcpu->hv_clock,
1616 sizeof(vcpu->hv_clock));
8cfdc000 1617 return 0;
c8076604
GH		 1618}
1619
0061d53d
MT		 1620/*
1621 * kvmclock updates which are isolated to a given vcpu, such as
1622 * vcpu->cpu migration, should not allow system_timestamp from
1623 * the rest of the vcpus to remain static. Otherwise ntp frequency
1624 * correction applies to one vcpu's system_timestamp but not
1625 * the others.
1626 *
1627 * So in those cases, request a kvmclock update for all vcpus.
1628 * The worst case for a remote vcpu to update its kvmclock
1629 * is then bounded by maximum nohz sleep latency.
1630 */
1631
1632static void kvm_gen_kvmclock_update(struct kvm_vcpu *v)
1633{
1634 int i;
1635 struct kvm *kvm = v->kvm;
1636 struct kvm_vcpu *vcpu;
1637
1638 kvm_for_each_vcpu(i, vcpu, kvm) {
1639 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
1640 kvm_vcpu_kick(vcpu);
1641 }
1642}
1643
9ba075a6
AK		 1644static bool msr_mtrr_valid(unsigned msr)
1645{
1646 switch (msr) {
1647 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
1648 case MSR_MTRRfix64K_00000:
1649 case MSR_MTRRfix16K_80000:
1650 case MSR_MTRRfix16K_A0000:
1651 case MSR_MTRRfix4K_C0000:
1652 case MSR_MTRRfix4K_C8000:
1653 case MSR_MTRRfix4K_D0000:
1654 case MSR_MTRRfix4K_D8000:
1655 case MSR_MTRRfix4K_E0000:
1656 case MSR_MTRRfix4K_E8000:
1657 case MSR_MTRRfix4K_F0000:
1658 case MSR_MTRRfix4K_F8000:
1659 case MSR_MTRRdefType:
1660 case MSR_IA32_CR_PAT:
1661 return true;
1662 case 0x2f8:
1663 return true;
1664 }
1665 return false;
1666}
1667
d6289b93
MT		 1668static bool valid_pat_type(unsigned t)
1669{
1670 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
1671}
1672
1673static bool valid_mtrr_type(unsigned t)
1674{
1675 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
1676}
1677
1678static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1679{
1680 int i;
1681
1682 if (!msr_mtrr_valid(msr))
1683 return false;
1684
1685 if (msr == MSR_IA32_CR_PAT) {
1686 for (i = 0; i < 8; i++)
1687 if (!valid_pat_type((data >> (i * 8)) & 0xff))
1688 return false;
1689 return true;
1690 } else if (msr == MSR_MTRRdefType) {
1691 if (data & ~0xcff)
1692 return false;
1693 return valid_mtrr_type(data & 0xff);
1694 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
1695 for (i = 0; i < 8 ; i++)
1696 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
1697 return false;
1698 return true;
1699 }
1700
1701 /* variable MTRRs */
1702 return valid_mtrr_type(data & 0xff);
1703}
1704
9ba075a6
AK		 1705static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1706{
0bed3b56
SY		 1707 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
1708
d6289b93 1709 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 1710 return 1;
1711
0bed3b56
SY		 1712 if (msr == MSR_MTRRdefType) {
1713 vcpu->arch.mtrr_state.def_type = data;
1714 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
1715 } else if (msr == MSR_MTRRfix64K_00000)
1716 p[0] = data;
1717 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
1718 p[1 + msr - MSR_MTRRfix16K_80000] = data;
1719 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
1720 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
1721 else if (msr == MSR_IA32_CR_PAT)
1722 vcpu->arch.pat = data;
1723 else { /* Variable MTRRs */
1724 int idx, is_mtrr_mask;
1725 u64 *pt;
1726
1727 idx = (msr - 0x200) / 2;
1728 is_mtrr_mask = msr - 0x200 - 2 * idx;
1729 if (!is_mtrr_mask)
1730 pt =
1731 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
1732 else
1733 pt =
1734 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
1735 *pt = data;
1736 }
1737
1738 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 1739 return 0;
1740}
15c4a640 1741
890ca9ae 1742static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 1743{
890ca9ae
HY		 1744 u64 mcg_cap = vcpu->arch.mcg_cap;
1745 unsigned bank_num = mcg_cap & 0xff;
1746
15c4a640 1747 switch (msr) {
15c4a640 1748 case MSR_IA32_MCG_STATUS:
890ca9ae 1749 vcpu->arch.mcg_status = data;
15c4a640 1750 break;
c7ac679c 1751 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1752 if (!(mcg_cap & MCG_CTL_P))
1753 return 1;
1754 if (data != 0 && data != ~(u64)0)
1755 return -1;
1756 vcpu->arch.mcg_ctl = data;
1757 break;
1758 default:
1759 if (msr >= MSR_IA32_MC0_CTL &&
1760 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1761 u32 offset = msr - MSR_IA32_MC0_CTL;
114be429
AP		 1762 /* only 0 or all 1s can be written to IA32_MCi_CTL
1763 * some Linux kernels though clear bit 10 in bank 4 to
1764 * workaround a BIOS/GART TBL issue on AMD K8s, ignore
1765 * this to avoid an uncatched #GP in the guest
1766 */
890ca9ae 1767 if ((offset & 0x3) == 0 &&
114be429 1768 data != 0 && (data | (1 << 10)) != ~(u64)0)
890ca9ae
HY		 1769 return -1;
1770 vcpu->arch.mce_banks[offset] = data;
1771 break;
1772 }
1773 return 1;
1774 }
1775 return 0;
1776}
1777
ffde22ac
ES		 1778static int xen_hvm_config(struct kvm_vcpu *vcpu, u64 data)
1779{
1780 struct kvm *kvm = vcpu->kvm;
1781 int lm = is_long_mode(vcpu);
1782 u8 *blob_addr = lm ? (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_64
1783 : (u8 *)(long)kvm->arch.xen_hvm_config.blob_addr_32;
1784 u8 blob_size = lm ? kvm->arch.xen_hvm_config.blob_size_64
1785 : kvm->arch.xen_hvm_config.blob_size_32;
1786 u32 page_num = data & ~PAGE_MASK;
1787 u64 page_addr = data & PAGE_MASK;
1788 u8 *page;
1789 int r;
1790
1791 r = -E2BIG;
1792 if (page_num >= blob_size)
1793 goto out;
1794 r = -ENOMEM;
ff5c2c03
SL		 1795 page = memdup_user(blob_addr + (page_num * PAGE_SIZE), PAGE_SIZE);
1796 if (IS_ERR(page)) {
1797 r = PTR_ERR(page);
ffde22ac 1798 goto out;
ff5c2c03 1799 }
ffde22ac
ES		 1800 if (kvm_write_guest(kvm, page_addr, page, PAGE_SIZE))
1801 goto out_free;
1802 r = 0;
1803out_free:
1804 kfree(page);
1805out:
1806 return r;
1807}
1808
55cd8e5a
GN		 1809static bool kvm_hv_hypercall_enabled(struct kvm *kvm)
1810{
1811 return kvm->arch.hv_hypercall & HV_X64_MSR_HYPERCALL_ENABLE;
1812}
1813
1814static bool kvm_hv_msr_partition_wide(u32 msr)
1815{
1816 bool r = false;
1817 switch (msr) {
1818 case HV_X64_MSR_GUEST_OS_ID:
1819 case HV_X64_MSR_HYPERCALL:
1820 r = true;
1821 break;
1822 }
1823
1824 return r;
1825}
1826
1827static int set_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1828{
1829 struct kvm *kvm = vcpu->kvm;
1830
1831 switch (msr) {
1832 case HV_X64_MSR_GUEST_OS_ID:
1833 kvm->arch.hv_guest_os_id = data;
1834 /* setting guest os id to zero disables hypercall page */
1835 if (!kvm->arch.hv_guest_os_id)
1836 kvm->arch.hv_hypercall &= ~HV_X64_MSR_HYPERCALL_ENABLE;
1837 break;
1838 case HV_X64_MSR_HYPERCALL: {
1839 u64 gfn;
1840 unsigned long addr;
1841 u8 instructions[4];
1842
1843 /* if guest os id is not set hypercall should remain disabled */
1844 if (!kvm->arch.hv_guest_os_id)
1845 break;
1846 if (!(data & HV_X64_MSR_HYPERCALL_ENABLE)) {
1847 kvm->arch.hv_hypercall = data;
1848 break;
1849 }
1850 gfn = data >> HV_X64_MSR_HYPERCALL_PAGE_ADDRESS_SHIFT;
1851 addr = gfn_to_hva(kvm, gfn);
1852 if (kvm_is_error_hva(addr))
1853 return 1;
1854 kvm_x86_ops->patch_hypercall(vcpu, instructions);
1855 ((unsigned char *)instructions)[3] = 0xc3; /* ret */
8b0cedff 1856 if (__copy_to_user((void __user *)addr, instructions, 4))
55cd8e5a
GN		 1857 return 1;
1858 kvm->arch.hv_hypercall = data;
1859 break;
1860 }
1861 default:
a737f256
CD		 1862 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1863 "data 0x%llx\n", msr, data);
55cd8e5a
GN		 1864 return 1;
1865 }
1866 return 0;
1867}
1868
1869static int set_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1870{
10388a07
GN		 1871 switch (msr) {
1872 case HV_X64_MSR_APIC_ASSIST_PAGE: {
1873 unsigned long addr;
55cd8e5a 1874
10388a07
GN		 1875 if (!(data & HV_X64_MSR_APIC_ASSIST_PAGE_ENABLE)) {
1876 vcpu->arch.hv_vapic = data;
1877 break;
1878 }
1879 addr = gfn_to_hva(vcpu->kvm, data >>
1880 HV_X64_MSR_APIC_ASSIST_PAGE_ADDRESS_SHIFT);
1881 if (kvm_is_error_hva(addr))
1882 return 1;
8b0cedff 1883 if (__clear_user((void __user *)addr, PAGE_SIZE))
10388a07
GN		 1884 return 1;
1885 vcpu->arch.hv_vapic = data;
1886 break;
1887 }
1888 case HV_X64_MSR_EOI:
1889 return kvm_hv_vapic_msr_write(vcpu, APIC_EOI, data);
1890 case HV_X64_MSR_ICR:
1891 return kvm_hv_vapic_msr_write(vcpu, APIC_ICR, data);
1892 case HV_X64_MSR_TPR:
1893 return kvm_hv_vapic_msr_write(vcpu, APIC_TASKPRI, data);
1894 default:
a737f256
CD		 1895 vcpu_unimpl(vcpu, "HYPER-V unimplemented wrmsr: 0x%x "
1896 "data 0x%llx\n", msr, data);
10388a07
GN		 1897 return 1;
1898 }
1899
1900 return 0;
55cd8e5a
GN		 1901}
1902
344d9588
GN		 1903static int kvm_pv_enable_async_pf(struct kvm_vcpu *vcpu, u64 data)
1904{
1905 gpa_t gpa = data & ~0x3f;
1906
4a969980 1907 /* Bits 2:5 are reserved, Should be zero */
6adba527 1908 if (data & 0x3c)
344d9588
GN		 1909 return 1;
1910
1911 vcpu->arch.apf.msr_val = data;
1912
1913 if (!(data & KVM_ASYNC_PF_ENABLED)) {
1914 kvm_clear_async_pf_completion_queue(vcpu);
1915 kvm_async_pf_hash_reset(vcpu);
1916 return 0;
1917 }
1918
8f964525
AH		 1919 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.apf.data, gpa,
1920 sizeof(u32)))
344d9588
GN		 1921 return 1;
1922
6adba527 1923 vcpu->arch.apf.send_user_only = !(data & KVM_ASYNC_PF_SEND_ALWAYS);
344d9588
GN		 1924 kvm_async_pf_wakeup_all(vcpu);
1925 return 0;
1926}
1927
12f9a48f
GC		 1928static void kvmclock_reset(struct kvm_vcpu *vcpu)
1929{
0b79459b 1930 vcpu->arch.pv_time_enabled = false;
12f9a48f
GC		 1931}
1932
c9aaa895
GC		 1933static void accumulate_steal_time(struct kvm_vcpu *vcpu)
1934{
1935 u64 delta;
1936
1937 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1938 return;
1939
1940 delta = current->sched_info.run_delay - vcpu->arch.st.last_steal;
1941 vcpu->arch.st.last_steal = current->sched_info.run_delay;
1942 vcpu->arch.st.accum_steal = delta;
1943}
1944
1945static void record_steal_time(struct kvm_vcpu *vcpu)
1946{
1947 if (!(vcpu->arch.st.msr_val & KVM_MSR_ENABLED))
1948 return;
1949
1950 if (unlikely(kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1951 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time))))
1952 return;
1953
1954 vcpu->arch.st.steal.steal += vcpu->arch.st.accum_steal;
1955 vcpu->arch.st.steal.version += 2;
1956 vcpu->arch.st.accum_steal = 0;
1957
1958 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.st.stime,
1959 &vcpu->arch.st.steal, sizeof(struct kvm_steal_time));
1960}
1961
8fe8ab46 1962int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
15c4a640 1963{
5753785f 1964 bool pr = false;
8fe8ab46
WA		 1965 u32 msr = msr_info->index;
1966 u64 data = msr_info->data;
5753785f 1967
15c4a640 1968 switch (msr) {
2e32b719
BP		 1969 case MSR_AMD64_NB_CFG:
1970 case MSR_IA32_UCODE_REV:
1971 case MSR_IA32_UCODE_WRITE:
1972 case MSR_VM_HSAVE_PA:
1973 case MSR_AMD64_PATCH_LOADER:
1974 case MSR_AMD64_BU_CFG2:
1975 break;
1976
15c4a640 1977 case MSR_EFER:
b69e8cae 1978 return set_efer(vcpu, data);
8f1589d9
AP		 1979 case MSR_K7_HWCR:
1980 data &= ~(u64)0x40; /* ignore flush filter disable */
82494028 1981 data &= ~(u64)0x100; /* ignore ignne emulation enable */
a223c313 1982 data &= ~(u64)0x8; /* ignore TLB cache disable */
8f1589d9 1983 if (data != 0) {
a737f256
CD		 1984 vcpu_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
1985 data);
8f1589d9
AP		 1986 return 1;
1987 }
15c4a640 1988 break;
f7c6d140
AP		 1989 case MSR_FAM10H_MMIO_CONF_BASE:
1990 if (data != 0) {
a737f256
CD		 1991 vcpu_unimpl(vcpu, "unimplemented MMIO_CONF_BASE wrmsr: "
1992 "0x%llx\n", data);
f7c6d140
AP		 1993 return 1;
1994 }
15c4a640 1995 break;
b5e2fec0
AG		 1996 case MSR_IA32_DEBUGCTLMSR:
1997 if (!data) {
1998 /* We support the non-activated case already */
1999 break;
2000 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
2001 /* Values other than LBR and BTF are vendor-specific,
2002 thus reserved and should throw a #GP */
2003 return 1;
2004 }
a737f256
CD		 2005 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
2006 __func__, data);
b5e2fec0 2007 break;
9ba075a6
AK		 2008 case 0x200 ... 0x2ff:
2009 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 2010 case MSR_IA32_APICBASE:
2011 kvm_set_apic_base(vcpu, data);
2012 break;
0105d1a5
GN		 2013 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2014 return kvm_x2apic_msr_write(vcpu, msr, data);
a3e06bbe
LJ		 2015 case MSR_IA32_TSCDEADLINE:
2016 kvm_set_lapic_tscdeadline_msr(vcpu, data);
2017 break;
ba904635
WA		 2018 case MSR_IA32_TSC_ADJUST:
2019 if (guest_cpuid_has_tsc_adjust(vcpu)) {
2020 if (!msr_info->host_initiated) {
2021 u64 adj = data - vcpu->arch.ia32_tsc_adjust_msr;
2022 kvm_x86_ops->adjust_tsc_offset(vcpu, adj, true);
2023 }
2024 vcpu->arch.ia32_tsc_adjust_msr = data;
2025 }
2026 break;
15c4a640 2027 case MSR_IA32_MISC_ENABLE:
ad312c7c 2028 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 2029 break;
11c6bffa 2030 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2031 case MSR_KVM_WALL_CLOCK:
2032 vcpu->kvm->arch.wall_clock = data;
2033 kvm_write_wall_clock(vcpu->kvm, data);
2034 break;
11c6bffa 2035 case MSR_KVM_SYSTEM_TIME_NEW:
18068523 2036 case MSR_KVM_SYSTEM_TIME: {
0b79459b 2037 u64 gpa_offset;
12f9a48f 2038 kvmclock_reset(vcpu);
18068523
GOC		 2039
2040 vcpu->arch.time = data;
0061d53d 2041 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
18068523
GOC		 2042
2043 /* we verify if the enable bit is set... */
2044 if (!(data & 1))
2045 break;
2046
0b79459b 2047 gpa_offset = data & ~(PAGE_MASK | 1);
18068523 2048
0b79459b 2049 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
8f964525
AH		 2050 &vcpu->arch.pv_time, data & ~1ULL,
2051 sizeof(struct pvclock_vcpu_time_info)))
0b79459b
AH		 2052 vcpu->arch.pv_time_enabled = false;
2053 else
2054 vcpu->arch.pv_time_enabled = true;
32cad84f 2055
18068523
GOC		 2056 break;
2057 }
344d9588
GN		 2058 case MSR_KVM_ASYNC_PF_EN:
2059 if (kvm_pv_enable_async_pf(vcpu, data))
2060 return 1;
2061 break;
c9aaa895
GC		 2062 case MSR_KVM_STEAL_TIME:
2063
2064 if (unlikely(!sched_info_on()))
2065 return 1;
2066
2067 if (data & KVM_STEAL_RESERVED_MASK)
2068 return 1;
2069
2070 if (kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.st.stime,
8f964525
AH		 2071 data & KVM_STEAL_VALID_BITS,
2072 sizeof(struct kvm_steal_time)))
c9aaa895
GC		 2073 return 1;
2074
2075 vcpu->arch.st.msr_val = data;
2076
2077 if (!(data & KVM_MSR_ENABLED))
2078 break;
2079
2080 vcpu->arch.st.last_steal = current->sched_info.run_delay;
2081
2082 preempt_disable();
2083 accumulate_steal_time(vcpu);
2084 preempt_enable();
2085
2086 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
2087
2088 break;
ae7a2a3f
MT		 2089 case MSR_KVM_PV_EOI_EN:
2090 if (kvm_lapic_enable_pv_eoi(vcpu, data))
2091 return 1;
2092 break;
c9aaa895 2093
890ca9ae
HY		 2094 case MSR_IA32_MCG_CTL:
2095 case MSR_IA32_MCG_STATUS:
2096 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2097 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 2098
2099 /* Performance counters are not protected by a CPUID bit,
2100 * so we should check all of them in the generic path for the sake of
2101 * cross vendor migration.
2102 * Writing a zero into the event select MSRs disables them,
2103 * which we perfectly emulate ;-). Any other value should be at least
2104 * reported, some guests depend on them.
2105 */
71db6023
AP		 2106 case MSR_K7_EVNTSEL0:
2107 case MSR_K7_EVNTSEL1:
2108 case MSR_K7_EVNTSEL2:
2109 case MSR_K7_EVNTSEL3:
2110 if (data != 0)
a737f256
CD		 2111 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2112 "0x%x data 0x%llx\n", msr, data);
71db6023
AP		 2113 break;
2114 /* at least RHEL 4 unconditionally writes to the perfctr registers,
2115 * so we ignore writes to make it happy.
2116 */
71db6023
AP		 2117 case MSR_K7_PERFCTR0:
2118 case MSR_K7_PERFCTR1:
2119 case MSR_K7_PERFCTR2:
2120 case MSR_K7_PERFCTR3:
a737f256
CD		 2121 vcpu_unimpl(vcpu, "unimplemented perfctr wrmsr: "
2122 "0x%x data 0x%llx\n", msr, data);
71db6023 2123 break;
5753785f
GN		 2124 case MSR_P6_PERFCTR0:
2125 case MSR_P6_PERFCTR1:
2126 pr = true;
2127 case MSR_P6_EVNTSEL0:
2128 case MSR_P6_EVNTSEL1:
2129 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2130 return kvm_pmu_set_msr(vcpu, msr_info);
5753785f
GN		 2131
2132 if (pr || data != 0)
a737f256
CD		 2133 vcpu_unimpl(vcpu, "disabled perfctr wrmsr: "
2134 "0x%x data 0x%llx\n", msr, data);
5753785f 2135 break;
84e0cefa
JS		 2136 case MSR_K7_CLK_CTL:
2137 /*
2138 * Ignore all writes to this no longer documented MSR.
2139 * Writes are only relevant for old K7 processors,
2140 * all pre-dating SVM, but a recommended workaround from
4a969980 2141 * AMD for these chips. It is possible to specify the
84e0cefa
JS		 2142 * affected processor models on the command line, hence
2143 * the need to ignore the workaround.
2144 */
2145 break;
55cd8e5a
GN		 2146 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2147 if (kvm_hv_msr_partition_wide(msr)) {
2148 int r;
2149 mutex_lock(&vcpu->kvm->lock);
2150 r = set_msr_hyperv_pw(vcpu, msr, data);
2151 mutex_unlock(&vcpu->kvm->lock);
2152 return r;
2153 } else
2154 return set_msr_hyperv(vcpu, msr, data);
2155 break;
91c9c3ed 2156 case MSR_IA32_BBL_CR_CTL3:
2157 /* Drop writes to this legacy MSR -- see rdmsr
2158 * counterpart for further detail.
2159 */
a737f256 2160 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n", msr, data);
91c9c3ed 2161 break;
2b036c6b
BO		 2162 case MSR_AMD64_OSVW_ID_LENGTH:
2163 if (!guest_cpuid_has_osvw(vcpu))
2164 return 1;
2165 vcpu->arch.osvw.length = data;
2166 break;
2167 case MSR_AMD64_OSVW_STATUS:
2168 if (!guest_cpuid_has_osvw(vcpu))
2169 return 1;
2170 vcpu->arch.osvw.status = data;
2171 break;
15c4a640 2172 default:
ffde22ac
ES		 2173 if (msr && (msr == vcpu->kvm->arch.xen_hvm_config.msr))
2174 return xen_hvm_config(vcpu, data);
f5132b01 2175 if (kvm_pmu_msr(vcpu, msr))
afd80d85 2176 return kvm_pmu_set_msr(vcpu, msr_info);
ed85c068 2177 if (!ignore_msrs) {
a737f256
CD		 2178 vcpu_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
2179 msr, data);
ed85c068
AP		 2180 return 1;
2181 } else {
a737f256
CD		 2182 vcpu_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
2183 msr, data);
ed85c068
AP		 2184 break;
2185 }
15c4a640
CO		 2186 }
2187 return 0;
2188}
2189EXPORT_SYMBOL_GPL(kvm_set_msr_common);
2190
2191
2192/*
2193 * Reads an msr value (of 'msr_index') into 'pdata'.
2194 * Returns 0 on success, non-0 otherwise.
2195 * Assumes vcpu_load() was already called.
2196 */
2197int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2198{
2199 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
2200}
2201
9ba075a6
AK		 2202static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2203{
0bed3b56
SY		 2204 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
2205
9ba075a6
AK		 2206 if (!msr_mtrr_valid(msr))
2207 return 1;
2208
0bed3b56
SY		 2209 if (msr == MSR_MTRRdefType)
2210 *pdata = vcpu->arch.mtrr_state.def_type +
2211 (vcpu->arch.mtrr_state.enabled << 10);
2212 else if (msr == MSR_MTRRfix64K_00000)
2213 *pdata = p[0];
2214 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
2215 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
2216 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
2217 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
2218 else if (msr == MSR_IA32_CR_PAT)
2219 *pdata = vcpu->arch.pat;
2220 else { /* Variable MTRRs */
2221 int idx, is_mtrr_mask;
2222 u64 *pt;
2223
2224 idx = (msr - 0x200) / 2;
2225 is_mtrr_mask = msr - 0x200 - 2 * idx;
2226 if (!is_mtrr_mask)
2227 pt =
2228 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
2229 else
2230 pt =
2231 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
2232 *pdata = *pt;
2233 }
2234
9ba075a6
AK		 2235 return 0;
2236}
2237
890ca9ae 2238static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 2239{
2240 u64 data;
890ca9ae
HY		 2241 u64 mcg_cap = vcpu->arch.mcg_cap;
2242 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 2243
2244 switch (msr) {
15c4a640
CO		 2245 case MSR_IA32_P5_MC_ADDR:
2246 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 2247 data = 0;
2248 break;
15c4a640 2249 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 2250 data = vcpu->arch.mcg_cap;
2251 break;
c7ac679c 2252 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 2253 if (!(mcg_cap & MCG_CTL_P))
2254 return 1;
2255 data = vcpu->arch.mcg_ctl;
2256 break;
2257 case MSR_IA32_MCG_STATUS:
2258 data = vcpu->arch.mcg_status;
2259 break;
2260 default:
2261 if (msr >= MSR_IA32_MC0_CTL &&
2262 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
2263 u32 offset = msr - MSR_IA32_MC0_CTL;
2264 data = vcpu->arch.mce_banks[offset];
2265 break;
2266 }
2267 return 1;
2268 }
2269 *pdata = data;
2270 return 0;
2271}
2272
55cd8e5a
GN		 2273static int get_msr_hyperv_pw(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2274{
2275 u64 data = 0;
2276 struct kvm *kvm = vcpu->kvm;
2277
2278 switch (msr) {
2279 case HV_X64_MSR_GUEST_OS_ID:
2280 data = kvm->arch.hv_guest_os_id;
2281 break;
2282 case HV_X64_MSR_HYPERCALL:
2283 data = kvm->arch.hv_hypercall;
2284 break;
2285 default:
a737f256 2286 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2287 return 1;
2288 }
2289
2290 *pdata = data;
2291 return 0;
2292}
2293
2294static int get_msr_hyperv(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2295{
2296 u64 data = 0;
2297
2298 switch (msr) {
2299 case HV_X64_MSR_VP_INDEX: {
2300 int r;
2301 struct kvm_vcpu *v;
2302 kvm_for_each_vcpu(r, v, vcpu->kvm)
2303 if (v == vcpu)
2304 data = r;
2305 break;
2306 }
10388a07
GN		 2307 case HV_X64_MSR_EOI:
2308 return kvm_hv_vapic_msr_read(vcpu, APIC_EOI, pdata);
2309 case HV_X64_MSR_ICR:
2310 return kvm_hv_vapic_msr_read(vcpu, APIC_ICR, pdata);
2311 case HV_X64_MSR_TPR:
2312 return kvm_hv_vapic_msr_read(vcpu, APIC_TASKPRI, pdata);
14fa67ee 2313 case HV_X64_MSR_APIC_ASSIST_PAGE:
d1613ad5
MW		 2314 data = vcpu->arch.hv_vapic;
2315 break;
55cd8e5a 2316 default:
a737f256 2317 vcpu_unimpl(vcpu, "Hyper-V unhandled rdmsr: 0x%x\n", msr);
55cd8e5a
GN		 2318 return 1;
2319 }
2320 *pdata = data;
2321 return 0;
2322}
2323
890ca9ae
HY		 2324int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
2325{
2326 u64 data;
2327
2328 switch (msr) {
890ca9ae 2329 case MSR_IA32_PLATFORM_ID:
15c4a640 2330 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 2331 case MSR_IA32_DEBUGCTLMSR:
2332 case MSR_IA32_LASTBRANCHFROMIP:
2333 case MSR_IA32_LASTBRANCHTOIP:
2334 case MSR_IA32_LASTINTFROMIP:
2335 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 2336 case MSR_K8_SYSCFG:
2337 case MSR_K7_HWCR:
61a6bd67 2338 case MSR_VM_HSAVE_PA:
9e699624 2339 case MSR_K7_EVNTSEL0:
1f3ee616 2340 case MSR_K7_PERFCTR0:
1fdbd48c 2341 case MSR_K8_INT_PENDING_MSG:
c323c0e5 2342 case MSR_AMD64_NB_CFG:
f7c6d140 2343 case MSR_FAM10H_MMIO_CONF_BASE:
2e32b719 2344 case MSR_AMD64_BU_CFG2:
15c4a640
CO		 2345 data = 0;
2346 break;
5753785f
GN		 2347 case MSR_P6_PERFCTR0:
2348 case MSR_P6_PERFCTR1:
2349 case MSR_P6_EVNTSEL0:
2350 case MSR_P6_EVNTSEL1:
2351 if (kvm_pmu_msr(vcpu, msr))
2352 return kvm_pmu_get_msr(vcpu, msr, pdata);
2353 data = 0;
2354 break;
742bc670
MT		 2355 case MSR_IA32_UCODE_REV:
2356 data = 0x100000000ULL;
2357 break;
9ba075a6
AK		 2358 case MSR_MTRRcap:
2359 data = 0x500 | KVM_NR_VAR_MTRR;
2360 break;
2361 case 0x200 ... 0x2ff:
2362 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 2363 case 0xcd: /* fsb frequency */
2364 data = 3;
2365 break;
7b914098
JS		 2366 /*
2367 * MSR_EBC_FREQUENCY_ID
2368 * Conservative value valid for even the basic CPU models.
2369 * Models 0,1: 000 in bits 23:21 indicating a bus speed of
2370 * 100MHz, model 2 000 in bits 18:16 indicating 100MHz,
2371 * and 266MHz for model 3, or 4. Set Core Clock
2372 * Frequency to System Bus Frequency Ratio to 1 (bits
2373 * 31:24) even though these are only valid for CPU
2374 * models > 2, however guests may end up dividing or
2375 * multiplying by zero otherwise.
2376 */
2377 case MSR_EBC_FREQUENCY_ID:
2378 data = 1 << 24;
2379 break;
15c4a640
CO		 2380 case MSR_IA32_APICBASE:
2381 data = kvm_get_apic_base(vcpu);
2382 break;
0105d1a5
GN		 2383 case APIC_BASE_MSR ... APIC_BASE_MSR + 0x3ff:
2384 return kvm_x2apic_msr_read(vcpu, msr, pdata);
2385 break;
a3e06bbe
LJ		 2386 case MSR_IA32_TSCDEADLINE:
2387 data = kvm_get_lapic_tscdeadline_msr(vcpu);
2388 break;
ba904635
WA		 2389 case MSR_IA32_TSC_ADJUST:
2390 data = (u64)vcpu->arch.ia32_tsc_adjust_msr;
2391 break;
15c4a640 2392 case MSR_IA32_MISC_ENABLE:
ad312c7c 2393 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 2394 break;
847f0ad8
AG		 2395 case MSR_IA32_PERF_STATUS:
2396 /* TSC increment by tick */
2397 data = 1000ULL;
2398 /* CPU multiplier */
2399 data |= (((uint64_t)4ULL) << 40);
2400 break;
15c4a640 2401 case MSR_EFER:
f6801dff 2402 data = vcpu->arch.efer;
15c4a640 2403 break;
18068523 2404 case MSR_KVM_WALL_CLOCK:
11c6bffa 2405 case MSR_KVM_WALL_CLOCK_NEW:
18068523
GOC		 2406 data = vcpu->kvm->arch.wall_clock;
2407 break;
2408 case MSR_KVM_SYSTEM_TIME:
11c6bffa 2409 case MSR_KVM_SYSTEM_TIME_NEW:
18068523
GOC		 2410 data = vcpu->arch.time;
2411 break;
344d9588
GN		 2412 case MSR_KVM_ASYNC_PF_EN:
2413 data = vcpu->arch.apf.msr_val;
2414 break;
c9aaa895
GC		 2415 case MSR_KVM_STEAL_TIME:
2416 data = vcpu->arch.st.msr_val;
2417 break;
1d92128f
MT		 2418 case MSR_KVM_PV_EOI_EN:
2419 data = vcpu->arch.pv_eoi.msr_val;
2420 break;
890ca9ae
HY		 2421 case MSR_IA32_P5_MC_ADDR:
2422 case MSR_IA32_P5_MC_TYPE:
2423 case MSR_IA32_MCG_CAP:
2424 case MSR_IA32_MCG_CTL:
2425 case MSR_IA32_MCG_STATUS:
2426 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
2427 return get_msr_mce(vcpu, msr, pdata);
84e0cefa
JS		 2428 case MSR_K7_CLK_CTL:
2429 /*
2430 * Provide expected ramp-up count for K7. All other
2431 * are set to zero, indicating minimum divisors for
2432 * every field.
2433 *
2434 * This prevents guest kernels on AMD host with CPU
2435 * type 6, model 8 and higher from exploding due to
2436 * the rdmsr failing.
2437 */
2438 data = 0x20000000;
2439 break;
55cd8e5a
GN		 2440 case HV_X64_MSR_GUEST_OS_ID ... HV_X64_MSR_SINT15:
2441 if (kvm_hv_msr_partition_wide(msr)) {
2442 int r;
2443 mutex_lock(&vcpu->kvm->lock);
2444 r = get_msr_hyperv_pw(vcpu, msr, pdata);
2445 mutex_unlock(&vcpu->kvm->lock);
2446 return r;
2447 } else
2448 return get_msr_hyperv(vcpu, msr, pdata);
2449 break;
91c9c3ed 2450 case MSR_IA32_BBL_CR_CTL3:
2451 /* This legacy MSR exists but isn't fully documented in current
2452 * silicon. It is however accessed by winxp in very narrow
2453 * scenarios where it sets bit #19, itself documented as
2454 * a "reserved" bit. Best effort attempt to source coherent
2455 * read data here should the balance of the register be
2456 * interpreted by the guest:
2457 *
2458 * L2 cache control register 3: 64GB range, 256KB size,
2459 * enabled, latency 0x1, configured
2460 */
2461 data = 0xbe702111;
2462 break;
2b036c6b
BO		 2463 case MSR_AMD64_OSVW_ID_LENGTH:
2464 if (!guest_cpuid_has_osvw(vcpu))
2465 return 1;
2466 data = vcpu->arch.osvw.length;
2467 break;
2468 case MSR_AMD64_OSVW_STATUS:
2469 if (!guest_cpuid_has_osvw(vcpu))
2470 return 1;
2471 data = vcpu->arch.osvw.status;
2472 break;
15c4a640 2473 default:
f5132b01
GN		 2474 if (kvm_pmu_msr(vcpu, msr))
2475 return kvm_pmu_get_msr(vcpu, msr, pdata);
ed85c068 2476 if (!ignore_msrs) {
a737f256 2477 vcpu_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
ed85c068
AP		 2478 return 1;
2479 } else {
a737f256 2480 vcpu_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
ed85c068
AP		 2481 data = 0;
2482 }
2483 break;
15c4a640
CO		 2484 }
2485 *pdata = data;
2486 return 0;
2487}
2488EXPORT_SYMBOL_GPL(kvm_get_msr_common);
2489
313a3dc7
CO		 2490/*
2491 * Read or write a bunch of msrs. All parameters are kernel addresses.
2492 *
2493 * @return number of msrs set successfully.
2494 */
2495static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
2496 struct kvm_msr_entry *entries,
2497 int (*do_msr)(struct kvm_vcpu *vcpu,
2498 unsigned index, u64 *data))
2499{
f656ce01 2500 int i, idx;
313a3dc7 2501
f656ce01 2502 idx = srcu_read_lock(&vcpu->kvm->srcu);
313a3dc7
CO		 2503 for (i = 0; i < msrs->nmsrs; ++i)
2504 if (do_msr(vcpu, entries[i].index, &entries[i].data))
2505 break;
f656ce01 2506 srcu_read_unlock(&vcpu->kvm->srcu, idx);
313a3dc7 2507
313a3dc7
CO		 2508 return i;
2509}
2510
2511/*
2512 * Read or write a bunch of msrs. Parameters are user addresses.
2513 *
2514 * @return number of msrs set successfully.
2515 */
2516static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
2517 int (*do_msr)(struct kvm_vcpu *vcpu,
2518 unsigned index, u64 *data),
2519 int writeback)
2520{
2521 struct kvm_msrs msrs;
2522 struct kvm_msr_entry *entries;
2523 int r, n;
2524 unsigned size;
2525
2526 r = -EFAULT;
2527 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
2528 goto out;
2529
2530 r = -E2BIG;
2531 if (msrs.nmsrs >= MAX_IO_MSRS)
2532 goto out;
2533
313a3dc7 2534 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
ff5c2c03
SL		 2535 entries = memdup_user(user_msrs->entries, size);
2536 if (IS_ERR(entries)) {
2537 r = PTR_ERR(entries);
313a3dc7 2538 goto out;
ff5c2c03 2539 }
313a3dc7
CO		 2540
2541 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
2542 if (r < 0)
2543 goto out_free;
2544
2545 r = -EFAULT;
2546 if (writeback && copy_to_user(user_msrs->entries, entries, size))
2547 goto out_free;
2548
2549 r = n;
2550
2551out_free:
7a73c028 2552 kfree(entries);
313a3dc7
CO		 2553out:
2554 return r;
2555}
2556
018d00d2
ZX		 2557int kvm_dev_ioctl_check_extension(long ext)
2558{
2559 int r;
2560
2561 switch (ext) {
2562 case KVM_CAP_IRQCHIP:
2563 case KVM_CAP_HLT:
2564 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 2565 case KVM_CAP_SET_TSS_ADDR:
07716717 2566 case KVM_CAP_EXT_CPUID:
c8076604 2567 case KVM_CAP_CLOCKSOURCE:
7837699f 2568 case KVM_CAP_PIT:
a28e4f5a 2569 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 2570 case KVM_CAP_MP_STATE:
ed848624 2571 case KVM_CAP_SYNC_MMU:
a355c85c 2572 case KVM_CAP_USER_NMI:
52d939a0 2573 case KVM_CAP_REINJECT_CONTROL:
4925663a 2574 case KVM_CAP_IRQ_INJECT_STATUS:
721eecbf 2575 case KVM_CAP_IRQFD:
d34e6b17 2576 case KVM_CAP_IOEVENTFD:
c5ff41ce 2577 case KVM_CAP_PIT2:
e9f42757 2578 case KVM_CAP_PIT_STATE2:
b927a3ce 2579 case KVM_CAP_SET_IDENTITY_MAP_ADDR:
ffde22ac 2580 case KVM_CAP_XEN_HVM:
afbcf7ab 2581 case KVM_CAP_ADJUST_CLOCK:
3cfc3092 2582 case KVM_CAP_VCPU_EVENTS:
55cd8e5a 2583 case KVM_CAP_HYPERV:
10388a07 2584 case KVM_CAP_HYPERV_VAPIC:
c25bc163 2585 case KVM_CAP_HYPERV_SPIN:
ab9f4ecb 2586 case KVM_CAP_PCI_SEGMENT:
a1efbe77 2587 case KVM_CAP_DEBUGREGS:
d2be1651 2588 case KVM_CAP_X86_ROBUST_SINGLESTEP:
2d5b5a66 2589 case KVM_CAP_XSAVE:
344d9588 2590 case KVM_CAP_ASYNC_PF:
92a1f12d 2591 case KVM_CAP_GET_TSC_KHZ:
1c0b28c2 2592 case KVM_CAP_KVMCLOCK_CTRL:
4d8b81ab 2593 case KVM_CAP_READONLY_MEM:
2a5bab10
AW		 2594#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
2595 case KVM_CAP_ASSIGN_DEV_IRQ:
2596 case KVM_CAP_PCI_2_3:
2597#endif
018d00d2
ZX		 2598 r = 1;
2599 break;
542472b5
LV		 2600 case KVM_CAP_COALESCED_MMIO:
2601 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
2602 break;
774ead3a
AK		 2603 case KVM_CAP_VAPIC:
2604 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
2605 break;
f725230a 2606 case KVM_CAP_NR_VCPUS:
8c3ba334
SL		 2607 r = KVM_SOFT_MAX_VCPUS;
2608 break;
2609 case KVM_CAP_MAX_VCPUS:
f725230a
AK		 2610 r = KVM_MAX_VCPUS;
2611 break;
a988b910 2612 case KVM_CAP_NR_MEMSLOTS:
bbacc0c1 2613 r = KVM_USER_MEM_SLOTS;
a988b910 2614 break;
a68a6a72
MT		 2615 case KVM_CAP_PV_MMU: /* obsolete */
2616 r = 0;
2f333bcb 2617 break;
4cee4b72 2618#ifdef CONFIG_KVM_DEVICE_ASSIGNMENT
62c476c7 2619 case KVM_CAP_IOMMU:
a1b60c1c 2620 r = iommu_present(&pci_bus_type);
62c476c7 2621 break;
4cee4b72 2622#endif
890ca9ae
HY		 2623 case KVM_CAP_MCE:
2624 r = KVM_MAX_MCE_BANKS;
2625 break;
2d5b5a66
SY		 2626 case KVM_CAP_XCRS:
2627 r = cpu_has_xsave;
2628 break;
92a1f12d
JR		 2629 case KVM_CAP_TSC_CONTROL:
2630 r = kvm_has_tsc_control;
2631 break;
4d25a066
JK		 2632 case KVM_CAP_TSC_DEADLINE_TIMER:
2633 r = boot_cpu_has(X86_FEATURE_TSC_DEADLINE_TIMER);
2634 break;
018d00d2
ZX		 2635 default:
2636 r = 0;
2637 break;
2638 }
2639 return r;
2640
2641}
2642
043405e1
CO		 2643long kvm_arch_dev_ioctl(struct file *filp,
2644 unsigned int ioctl, unsigned long arg)
2645{
2646 void __user *argp = (void __user *)arg;
2647 long r;
2648
2649 switch (ioctl) {
2650 case KVM_GET_MSR_INDEX_LIST: {
2651 struct kvm_msr_list __user *user_msr_list = argp;
2652 struct kvm_msr_list msr_list;
2653 unsigned n;
2654
2655 r = -EFAULT;
2656 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
2657 goto out;
2658 n = msr_list.nmsrs;
2659 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
2660 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
2661 goto out;
2662 r = -E2BIG;
e125e7b6 2663 if (n < msr_list.nmsrs)
043405e1
CO		 2664 goto out;
2665 r = -EFAULT;
2666 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
2667 num_msrs_to_save * sizeof(u32)))
2668 goto out;
e125e7b6 2669 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 2670 &emulated_msrs,
2671 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
2672 goto out;
2673 r = 0;
2674 break;
2675 }
674eea0f
AK		 2676 case KVM_GET_SUPPORTED_CPUID: {
2677 struct kvm_cpuid2 __user *cpuid_arg = argp;
2678 struct kvm_cpuid2 cpuid;
2679
2680 r = -EFAULT;
2681 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
2682 goto out;
2683 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 2684 cpuid_arg->entries);
674eea0f
AK		 2685 if (r)
2686 goto out;
2687
2688 r = -EFAULT;
2689 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
2690 goto out;
2691 r = 0;
2692 break;
2693 }
890ca9ae
HY		 2694 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
2695 u64 mce_cap;
2696
2697 mce_cap = KVM_MCE_CAP_SUPPORTED;
2698 r = -EFAULT;
2699 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
2700 goto out;
2701 r = 0;
2702 break;
2703 }
043405e1
CO		 2704 default:
2705 r = -EINVAL;
2706 }
2707out:
2708 return r;
2709}
2710
f5f48ee1
SY		 2711static void wbinvd_ipi(void *garbage)
2712{
2713 wbinvd();
2714}
2715
2716static bool need_emulate_wbinvd(struct kvm_vcpu *vcpu)
2717{
2718 return vcpu->kvm->arch.iommu_domain &&
2719 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY);
2720}
2721
313a3dc7
CO		 2722void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
2723{
f5f48ee1
SY		 2724 /* Address WBINVD may be executed by guest */
2725 if (need_emulate_wbinvd(vcpu)) {
2726 if (kvm_x86_ops->has_wbinvd_exit())
2727 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
2728 else if (vcpu->cpu != -1 && vcpu->cpu != cpu)
2729 smp_call_function_single(vcpu->cpu,
2730 wbinvd_ipi, NULL, 1);
2731 }
2732
313a3dc7 2733 kvm_x86_ops->vcpu_load(vcpu, cpu);
8f6055cb 2734
0dd6a6ed
ZA		 2735 /* Apply any externally detected TSC adjustments (due to suspend) */
2736 if (unlikely(vcpu->arch.tsc_offset_adjustment)) {
2737 adjust_tsc_offset_host(vcpu, vcpu->arch.tsc_offset_adjustment);
2738 vcpu->arch.tsc_offset_adjustment = 0;
2739 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
2740 }
8f6055cb 2741
48434c20 2742 if (unlikely(vcpu->cpu != cpu) || check_tsc_unstable()) {
6f526ec5
ZA		 2743 s64 tsc_delta = !vcpu->arch.last_host_tsc ? 0 :
2744 native_read_tsc() - vcpu->arch.last_host_tsc;
e48672fa
ZA		 2745 if (tsc_delta < 0)
2746 mark_tsc_unstable("KVM discovered backwards TSC");
c285545f 2747 if (check_tsc_unstable()) {
b183aa58
ZA		 2748 u64 offset = kvm_x86_ops->compute_tsc_offset(vcpu,
2749 vcpu->arch.last_guest_tsc);
2750 kvm_x86_ops->write_tsc_offset(vcpu, offset);
c285545f 2751 vcpu->arch.tsc_catchup = 1;
c285545f 2752 }
d98d07ca
MT		 2753 /*
2754 * On a host with synchronized TSC, there is no need to update
2755 * kvmclock on vcpu->cpu migration
2756 */
2757 if (!vcpu->kvm->arch.use_master_clock || vcpu->cpu == -1)
0061d53d 2758 kvm_make_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu);
c285545f
ZA		 2759 if (vcpu->cpu != cpu)
2760 kvm_migrate_timers(vcpu);
e48672fa 2761 vcpu->cpu = cpu;
6b7d7e76 2762 }
c9aaa895
GC		 2763
2764 accumulate_steal_time(vcpu);
2765 kvm_make_request(KVM_REQ_STEAL_UPDATE, vcpu);
313a3dc7
CO		 2766}
2767
2768void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
2769{
02daab21 2770 kvm_x86_ops->vcpu_put(vcpu);
1c11e713 2771 kvm_put_guest_fpu(vcpu);
6f526ec5 2772 vcpu->arch.last_host_tsc = native_read_tsc();
313a3dc7
CO		 2773}
2774
313a3dc7
CO		 2775static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
2776 struct kvm_lapic_state *s)
2777{
5a71785d 2778 kvm_x86_ops->sync_pir_to_irr(vcpu);
ad312c7c 2779 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 2780
2781 return 0;
2782}
2783
2784static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
2785 struct kvm_lapic_state *s)
2786{
64eb0620 2787 kvm_apic_post_state_restore(vcpu, s);
cb142eb7 2788 update_cr8_intercept(vcpu);
313a3dc7
CO		 2789
2790 return 0;
2791}
2792
f77bc6a4
ZX		 2793static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
2794 struct kvm_interrupt *irq)
2795{
02cdb50f 2796 if (irq->irq >= KVM_NR_INTERRUPTS)
f77bc6a4
ZX		 2797 return -EINVAL;
2798 if (irqchip_in_kernel(vcpu->kvm))
2799 return -ENXIO;
f77bc6a4 2800
66fd3f7f 2801 kvm_queue_interrupt(vcpu, irq->irq, false);
3842d135 2802 kvm_make_request(KVM_REQ_EVENT, vcpu);
f77bc6a4 2803
f77bc6a4
ZX		 2804 return 0;
2805}
2806
c4abb7c9
JK		 2807static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
2808{
c4abb7c9 2809 kvm_inject_nmi(vcpu);
c4abb7c9
JK		 2810
2811 return 0;
2812}
2813
b209749f
AK		 2814static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
2815 struct kvm_tpr_access_ctl *tac)
2816{
2817 if (tac->flags)
2818 return -EINVAL;
2819 vcpu->arch.tpr_access_reporting = !!tac->enabled;
2820 return 0;
2821}
2822
890ca9ae
HY		 2823static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
2824 u64 mcg_cap)
2825{
2826 int r;
2827 unsigned bank_num = mcg_cap & 0xff, bank;
2828
2829 r = -EINVAL;
a9e38c3e 2830 if (!bank_num || bank_num >= KVM_MAX_MCE_BANKS)
890ca9ae
HY		 2831 goto out;
2832 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
2833 goto out;
2834 r = 0;
2835 vcpu->arch.mcg_cap = mcg_cap;
2836 /* Init IA32_MCG_CTL to all 1s */
2837 if (mcg_cap & MCG_CTL_P)
2838 vcpu->arch.mcg_ctl = ~(u64)0;
2839 /* Init IA32_MCi_CTL to all 1s */
2840 for (bank = 0; bank < bank_num; bank++)
2841 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
2842out:
2843 return r;
2844}
2845
2846static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
2847 struct kvm_x86_mce *mce)
2848{
2849 u64 mcg_cap = vcpu->arch.mcg_cap;
2850 unsigned bank_num = mcg_cap & 0xff;
2851 u64 *banks = vcpu->arch.mce_banks;
2852
2853 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
2854 return -EINVAL;
2855 /*
2856 * if IA32_MCG_CTL is not all 1s, the uncorrected error
2857 * reporting is disabled
2858 */
2859 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
2860 vcpu->arch.mcg_ctl != ~(u64)0)
2861 return 0;
2862 banks += 4 * mce->bank;
2863 /*
2864 * if IA32_MCi_CTL is not all 1s, the uncorrected error
2865 * reporting is disabled for the bank
2866 */
2867 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
2868 return 0;
2869 if (mce->status & MCI_STATUS_UC) {
2870 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
fc78f519 2871 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
a8eeb04a 2872 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
890ca9ae
HY		 2873 return 0;
2874 }
2875 if (banks[1] & MCI_STATUS_VAL)
2876 mce->status |= MCI_STATUS_OVER;
2877 banks[2] = mce->addr;
2878 banks[3] = mce->misc;
2879 vcpu->arch.mcg_status = mce->mcg_status;
2880 banks[1] = mce->status;
2881 kvm_queue_exception(vcpu, MC_VECTOR);
2882 } else if (!(banks[1] & MCI_STATUS_VAL)
2883 || !(banks[1] & MCI_STATUS_UC)) {
2884 if (banks[1] & MCI_STATUS_VAL)
2885 mce->status |= MCI_STATUS_OVER;
2886 banks[2] = mce->addr;
2887 banks[3] = mce->misc;
2888 banks[1] = mce->status;
2889 } else
2890 banks[1] |= MCI_STATUS_OVER;
2891 return 0;
2892}
2893
3cfc3092
JK		 2894static void kvm_vcpu_ioctl_x86_get_vcpu_events(struct kvm_vcpu *vcpu,
2895 struct kvm_vcpu_events *events)
2896{
7460fb4a 2897 process_nmi(vcpu);
03b82a30
JK		 2898 events->exception.injected =
2899 vcpu->arch.exception.pending &&
2900 !kvm_exception_is_soft(vcpu->arch.exception.nr);
3cfc3092
JK		 2901 events->exception.nr = vcpu->arch.exception.nr;
2902 events->exception.has_error_code = vcpu->arch.exception.has_error_code;
97e69aa6 2903 events->exception.pad = 0;
3cfc3092
JK		 2904 events->exception.error_code = vcpu->arch.exception.error_code;
2905
03b82a30
JK		 2906 events->interrupt.injected =
2907 vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft;
3cfc3092 2908 events->interrupt.nr = vcpu->arch.interrupt.nr;
03b82a30 2909 events->interrupt.soft = 0;
48005f64
JK		 2910 events->interrupt.shadow =
2911 kvm_x86_ops->get_interrupt_shadow(vcpu,
2912 KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI);
3cfc3092
JK		 2913
2914 events->nmi.injected = vcpu->arch.nmi_injected;
7460fb4a 2915 events->nmi.pending = vcpu->arch.nmi_pending != 0;
3cfc3092 2916 events->nmi.masked = kvm_x86_ops->get_nmi_mask(vcpu);
97e69aa6 2917 events->nmi.pad = 0;
3cfc3092 2918
66450a21 2919 events->sipi_vector = 0; /* never valid when reporting to user space */
3cfc3092 2920
dab4b911 2921 events->flags = (KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64 2922 | KVM_VCPUEVENT_VALID_SHADOW);
97e69aa6 2923 memset(&events->reserved, 0, sizeof(events->reserved));
3cfc3092
JK		 2924}
2925
2926static int kvm_vcpu_ioctl_x86_set_vcpu_events(struct kvm_vcpu *vcpu,
2927 struct kvm_vcpu_events *events)
2928{
dab4b911 2929 if (events->flags & ~(KVM_VCPUEVENT_VALID_NMI_PENDING
48005f64
JK		 2930 | KVM_VCPUEVENT_VALID_SIPI_VECTOR
2931 | KVM_VCPUEVENT_VALID_SHADOW))
3cfc3092
JK		 2932 return -EINVAL;
2933
7460fb4a 2934 process_nmi(vcpu);
3cfc3092
JK		 2935 vcpu->arch.exception.pending = events->exception.injected;
2936 vcpu->arch.exception.nr = events->exception.nr;
2937 vcpu->arch.exception.has_error_code = events->exception.has_error_code;
2938 vcpu->arch.exception.error_code = events->exception.error_code;
2939
2940 vcpu->arch.interrupt.pending = events->interrupt.injected;
2941 vcpu->arch.interrupt.nr = events->interrupt.nr;
2942 vcpu->arch.interrupt.soft = events->interrupt.soft;
48005f64
JK		 2943 if (events->flags & KVM_VCPUEVENT_VALID_SHADOW)
2944 kvm_x86_ops->set_interrupt_shadow(vcpu,
2945 events->interrupt.shadow);
3cfc3092
JK		 2946
2947 vcpu->arch.nmi_injected = events->nmi.injected;
dab4b911
JK		 2948 if (events->flags & KVM_VCPUEVENT_VALID_NMI_PENDING)
2949 vcpu->arch.nmi_pending = events->nmi.pending;
3cfc3092
JK		 2950 kvm_x86_ops->set_nmi_mask(vcpu, events->nmi.masked);
2951
66450a21
JK		 2952 if (events->flags & KVM_VCPUEVENT_VALID_SIPI_VECTOR &&
2953 kvm_vcpu_has_lapic(vcpu))
2954 vcpu->arch.apic->sipi_vector = events->sipi_vector;
3cfc3092 2955
3842d135
AK		 2956 kvm_make_request(KVM_REQ_EVENT, vcpu);
2957
3cfc3092
JK		 2958 return 0;
2959}
2960
a1efbe77
JK		 2961static void kvm_vcpu_ioctl_x86_get_debugregs(struct kvm_vcpu *vcpu,
2962 struct kvm_debugregs *dbgregs)
2963{
a1efbe77
JK		 2964 memcpy(dbgregs->db, vcpu->arch.db, sizeof(vcpu->arch.db));
2965 dbgregs->dr6 = vcpu->arch.dr6;
2966 dbgregs->dr7 = vcpu->arch.dr7;
2967 dbgregs->flags = 0;
97e69aa6 2968 memset(&dbgregs->reserved, 0, sizeof(dbgregs->reserved));
a1efbe77
JK		 2969}
2970
2971static int kvm_vcpu_ioctl_x86_set_debugregs(struct kvm_vcpu *vcpu,
2972 struct kvm_debugregs *dbgregs)
2973{
2974 if (dbgregs->flags)
2975 return -EINVAL;
2976
a1efbe77
JK		 2977 memcpy(vcpu->arch.db, dbgregs->db, sizeof(vcpu->arch.db));
2978 vcpu->arch.dr6 = dbgregs->dr6;
2979 vcpu->arch.dr7 = dbgregs->dr7;
2980
a1efbe77
JK		 2981 return 0;
2982}
2983
2d5b5a66
SY		 2984static void kvm_vcpu_ioctl_x86_get_xsave(struct kvm_vcpu *vcpu,
2985 struct kvm_xsave *guest_xsave)
2986{
4344ee98 2987 if (cpu_has_xsave) {
2d5b5a66
SY		 2988 memcpy(guest_xsave->region,
2989 &vcpu->arch.guest_fpu.state->xsave,
4344ee98
PB		 2990 vcpu->arch.guest_xstate_size);
2991 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] &=
2992 vcpu->arch.guest_supported_xcr0 | XSTATE_FPSSE;
2993 } else {
2d5b5a66
SY		 2994 memcpy(guest_xsave->region,
2995 &vcpu->arch.guest_fpu.state->fxsave,
2996 sizeof(struct i387_fxsave_struct));
2997 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)] =
2998 XSTATE_FPSSE;
2999 }
3000}
3001
3002static int kvm_vcpu_ioctl_x86_set_xsave(struct kvm_vcpu *vcpu,
3003 struct kvm_xsave *guest_xsave)
3004{
3005 u64 xstate_bv =
3006 *(u64 *)&guest_xsave->region[XSAVE_HDR_OFFSET / sizeof(u32)];
3007
d7876f1b
PB		 3008 if (cpu_has_xsave) {
3009 /*
3010 * Here we allow setting states that are not present in
3011 * CPUID leaf 0xD, index 0, EDX:EAX. This is for compatibility
3012 * with old userspace.
3013 */
3014 if (xstate_bv & ~KVM_SUPPORTED_XCR0)
3015 return -EINVAL;
3016 if (xstate_bv & ~host_xcr0)
3017 return -EINVAL;
2d5b5a66 3018 memcpy(&vcpu->arch.guest_fpu.state->xsave,
4344ee98 3019 guest_xsave->region, vcpu->arch.guest_xstate_size);
d7876f1b 3020 } else {
2d5b5a66
SY		 3021 if (xstate_bv & ~XSTATE_FPSSE)
3022 return -EINVAL;
3023 memcpy(&vcpu->arch.guest_fpu.state->fxsave,
3024 guest_xsave->region, sizeof(struct i387_fxsave_struct));
3025 }
3026 return 0;
3027}
3028
3029static void kvm_vcpu_ioctl_x86_get_xcrs(struct kvm_vcpu *vcpu,
3030 struct kvm_xcrs *guest_xcrs)
3031{
3032 if (!cpu_has_xsave) {
3033 guest_xcrs->nr_xcrs = 0;
3034 return;
3035 }
3036
3037 guest_xcrs->nr_xcrs = 1;
3038 guest_xcrs->flags = 0;
3039 guest_xcrs->xcrs[0].xcr = XCR_XFEATURE_ENABLED_MASK;
3040 guest_xcrs->xcrs[0].value = vcpu->arch.xcr0;
3041}
3042
3043static int kvm_vcpu_ioctl_x86_set_xcrs(struct kvm_vcpu *vcpu,
3044 struct kvm_xcrs *guest_xcrs)
3045{
3046 int i, r = 0;
3047
3048 if (!cpu_has_xsave)
3049 return -EINVAL;
3050
3051 if (guest_xcrs->nr_xcrs > KVM_MAX_XCRS || guest_xcrs->flags)
3052 return -EINVAL;
3053
3054 for (i = 0; i < guest_xcrs->nr_xcrs; i++)
3055 /* Only support XCR0 currently */
3056 if (guest_xcrs->xcrs[0].xcr == XCR_XFEATURE_ENABLED_MASK) {
3057 r = __kvm_set_xcr(vcpu, XCR_XFEATURE_ENABLED_MASK,
3058 guest_xcrs->xcrs[0].value);
3059 break;
3060 }
3061 if (r)
3062 r = -EINVAL;
3063 return r;
3064}
3065
1c0b28c2
EM		 3066/*
3067 * kvm_set_guest_paused() indicates to the guest kernel that it has been
3068 * stopped by the hypervisor. This function will be called from the host only.
3069 * EINVAL is returned when the host attempts to set the flag for a guest that
3070 * does not support pv clocks.
3071 */
3072static int kvm_set_guest_paused(struct kvm_vcpu *vcpu)
3073{
0b79459b 3074 if (!vcpu->arch.pv_time_enabled)
1c0b28c2 3075 return -EINVAL;
51d59c6b 3076 vcpu->arch.pvclock_set_guest_stopped_request = true;
1c0b28c2
EM		 3077 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
3078 return 0;
3079}
3080
313a3dc7
CO		 3081long kvm_arch_vcpu_ioctl(struct file *filp,
3082 unsigned int ioctl, unsigned long arg)
3083{
3084 struct kvm_vcpu *vcpu = filp->private_data;
3085 void __user *argp = (void __user *)arg;
3086 int r;
d1ac91d8
AK		 3087 union {
3088 struct kvm_lapic_state *lapic;
3089 struct kvm_xsave *xsave;
3090 struct kvm_xcrs *xcrs;
3091 void *buffer;
3092 } u;
3093
3094 u.buffer = NULL;
313a3dc7
CO		 3095 switch (ioctl) {
3096 case KVM_GET_LAPIC: {
2204ae3c
MT		 3097 r = -EINVAL;
3098 if (!vcpu->arch.apic)
3099 goto out;
d1ac91d8 3100 u.lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 3101
b772ff36 3102 r = -ENOMEM;
d1ac91d8 3103 if (!u.lapic)
b772ff36 3104 goto out;
d1ac91d8 3105 r = kvm_vcpu_ioctl_get_lapic(vcpu, u.lapic);
313a3dc7
CO		 3106 if (r)
3107 goto out;
3108 r = -EFAULT;
d1ac91d8 3109 if (copy_to_user(argp, u.lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 3110 goto out;
3111 r = 0;
3112 break;
3113 }
3114 case KVM_SET_LAPIC: {
2204ae3c
MT		 3115 r = -EINVAL;
3116 if (!vcpu->arch.apic)
3117 goto out;
ff5c2c03 3118 u.lapic = memdup_user(argp, sizeof(*u.lapic));
18595411
GC		 3119 if (IS_ERR(u.lapic))
3120 return PTR_ERR(u.lapic);
ff5c2c03 3121
d1ac91d8 3122 r = kvm_vcpu_ioctl_set_lapic(vcpu, u.lapic);
313a3dc7
CO		 3123 break;
3124 }
f77bc6a4
ZX		 3125 case KVM_INTERRUPT: {
3126 struct kvm_interrupt irq;
3127
3128 r = -EFAULT;
3129 if (copy_from_user(&irq, argp, sizeof irq))
3130 goto out;
3131 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
f77bc6a4
ZX		 3132 break;
3133 }
c4abb7c9
JK		 3134 case KVM_NMI: {
3135 r = kvm_vcpu_ioctl_nmi(vcpu);
c4abb7c9
JK		 3136 break;
3137 }
313a3dc7
CO		 3138 case KVM_SET_CPUID: {
3139 struct kvm_cpuid __user *cpuid_arg = argp;
3140 struct kvm_cpuid cpuid;
3141
3142 r = -EFAULT;
3143 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3144 goto out;
3145 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
313a3dc7
CO		 3146 break;
3147 }
07716717
DK		 3148 case KVM_SET_CPUID2: {
3149 struct kvm_cpuid2 __user *cpuid_arg = argp;
3150 struct kvm_cpuid2 cpuid;
3151
3152 r = -EFAULT;
3153 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3154 goto out;
3155 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 3156 cpuid_arg->entries);
07716717
DK		 3157 break;
3158 }
3159 case KVM_GET_CPUID2: {
3160 struct kvm_cpuid2 __user *cpuid_arg = argp;
3161 struct kvm_cpuid2 cpuid;
3162
3163 r = -EFAULT;
3164 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
3165 goto out;
3166 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 3167 cpuid_arg->entries);
07716717
DK		 3168 if (r)
3169 goto out;
3170 r = -EFAULT;
3171 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
3172 goto out;
3173 r = 0;
3174 break;
3175 }
313a3dc7
CO		 3176 case KVM_GET_MSRS:
3177 r = msr_io(vcpu, argp, kvm_get_msr, 1);
3178 break;
3179 case KVM_SET_MSRS:
3180 r = msr_io(vcpu, argp, do_set_msr, 0);
3181 break;
b209749f
AK		 3182 case KVM_TPR_ACCESS_REPORTING: {
3183 struct kvm_tpr_access_ctl tac;
3184
3185 r = -EFAULT;
3186 if (copy_from_user(&tac, argp, sizeof tac))
3187 goto out;
3188 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
3189 if (r)
3190 goto out;
3191 r = -EFAULT;
3192 if (copy_to_user(argp, &tac, sizeof tac))
3193 goto out;
3194 r = 0;
3195 break;
3196 };
b93463aa
AK		 3197 case KVM_SET_VAPIC_ADDR: {
3198 struct kvm_vapic_addr va;
3199
3200 r = -EINVAL;
3201 if (!irqchip_in_kernel(vcpu->kvm))
3202 goto out;
3203 r = -EFAULT;
3204 if (copy_from_user(&va, argp, sizeof va))
3205 goto out;
3206 r = 0;
3207 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
3208 break;
3209 }
890ca9ae
HY		 3210 case KVM_X86_SETUP_MCE: {
3211 u64 mcg_cap;
3212
3213 r = -EFAULT;
3214 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
3215 goto out;
3216 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
3217 break;
3218 }
3219 case KVM_X86_SET_MCE: {
3220 struct kvm_x86_mce mce;
3221
3222 r = -EFAULT;
3223 if (copy_from_user(&mce, argp, sizeof mce))
3224 goto out;
3225 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
3226 break;
3227 }
3cfc3092
JK		 3228 case KVM_GET_VCPU_EVENTS: {
3229 struct kvm_vcpu_events events;
3230
3231 kvm_vcpu_ioctl_x86_get_vcpu_events(vcpu, &events);
3232
3233 r = -EFAULT;
3234 if (copy_to_user(argp, &events, sizeof(struct kvm_vcpu_events)))
3235 break;
3236 r = 0;
3237 break;
3238 }
3239 case KVM_SET_VCPU_EVENTS: {
3240 struct kvm_vcpu_events events;
3241
3242 r = -EFAULT;
3243 if (copy_from_user(&events, argp, sizeof(struct kvm_vcpu_events)))
3244 break;
3245
3246 r = kvm_vcpu_ioctl_x86_set_vcpu_events(vcpu, &events);
3247 break;
3248 }
a1efbe77
JK		 3249 case KVM_GET_DEBUGREGS: {
3250 struct kvm_debugregs dbgregs;
3251
3252 kvm_vcpu_ioctl_x86_get_debugregs(vcpu, &dbgregs);
3253
3254 r = -EFAULT;
3255 if (copy_to_user(argp, &dbgregs,
3256 sizeof(struct kvm_debugregs)))
3257 break;
3258 r = 0;
3259 break;
3260 }
3261 case KVM_SET_DEBUGREGS: {
3262 struct kvm_debugregs dbgregs;
3263
3264 r = -EFAULT;
3265 if (copy_from_user(&dbgregs, argp,
3266 sizeof(struct kvm_debugregs)))
3267 break;
3268
3269 r = kvm_vcpu_ioctl_x86_set_debugregs(vcpu, &dbgregs);
3270 break;
3271 }
2d5b5a66 3272 case KVM_GET_XSAVE: {
d1ac91d8 3273 u.xsave = kzalloc(sizeof(struct kvm_xsave), GFP_KERNEL);
2d5b5a66 3274 r = -ENOMEM;
d1ac91d8 3275 if (!u.xsave)
2d5b5a66
SY		 3276 break;
3277
d1ac91d8 3278 kvm_vcpu_ioctl_x86_get_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3279
3280 r = -EFAULT;
d1ac91d8 3281 if (copy_to_user(argp, u.xsave, sizeof(struct kvm_xsave)))
2d5b5a66
SY		 3282 break;
3283 r = 0;
3284 break;
3285 }
3286 case KVM_SET_XSAVE: {
ff5c2c03 3287 u.xsave = memdup_user(argp, sizeof(*u.xsave));
18595411
GC		 3288 if (IS_ERR(u.xsave))
3289 return PTR_ERR(u.xsave);
2d5b5a66 3290
d1ac91d8 3291 r = kvm_vcpu_ioctl_x86_set_xsave(vcpu, u.xsave);
2d5b5a66
SY		 3292 break;
3293 }
3294 case KVM_GET_XCRS: {
d1ac91d8 3295 u.xcrs = kzalloc(sizeof(struct kvm_xcrs), GFP_KERNEL);
2d5b5a66 3296 r = -ENOMEM;
d1ac91d8 3297 if (!u.xcrs)
2d5b5a66
SY		 3298 break;
3299
d1ac91d8 3300 kvm_vcpu_ioctl_x86_get_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3301
3302 r = -EFAULT;
d1ac91d8 3303 if (copy_to_user(argp, u.xcrs,
2d5b5a66
SY		 3304 sizeof(struct kvm_xcrs)))
3305 break;
3306 r = 0;
3307 break;
3308 }
3309 case KVM_SET_XCRS: {
ff5c2c03 3310 u.xcrs = memdup_user(argp, sizeof(*u.xcrs));
18595411
GC		 3311 if (IS_ERR(u.xcrs))
3312 return PTR_ERR(u.xcrs);
2d5b5a66 3313
d1ac91d8 3314 r = kvm_vcpu_ioctl_x86_set_xcrs(vcpu, u.xcrs);
2d5b5a66
SY		 3315 break;
3316 }
92a1f12d
JR		 3317 case KVM_SET_TSC_KHZ: {
3318 u32 user_tsc_khz;
3319
3320 r = -EINVAL;
92a1f12d
JR		 3321 user_tsc_khz = (u32)arg;
3322
3323 if (user_tsc_khz >= kvm_max_guest_tsc_khz)
3324 goto out;
3325
cc578287
ZA		 3326 if (user_tsc_khz == 0)
3327 user_tsc_khz = tsc_khz;
3328
3329 kvm_set_tsc_khz(vcpu, user_tsc_khz);
92a1f12d
JR		 3330
3331 r = 0;
3332 goto out;
3333 }
3334 case KVM_GET_TSC_KHZ: {
cc578287 3335 r = vcpu->arch.virtual_tsc_khz;
92a1f12d
JR		 3336 goto out;
3337 }
1c0b28c2
EM		 3338 case KVM_KVMCLOCK_CTRL: {
3339 r = kvm_set_guest_paused(vcpu);
3340 goto out;
3341 }
313a3dc7
CO		 3342 default:
3343 r = -EINVAL;
3344 }
3345out:
d1ac91d8 3346 kfree(u.buffer);
313a3dc7
CO		 3347 return r;
3348}
3349
5b1c1493
CO		 3350int kvm_arch_vcpu_fault(struct kvm_vcpu *vcpu, struct vm_fault *vmf)
3351{
3352 return VM_FAULT_SIGBUS;
3353}
3354
1fe779f8
CO		 3355static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
3356{
3357 int ret;
3358
3359 if (addr > (unsigned int)(-3 * PAGE_SIZE))
951179ce 3360 return -EINVAL;
1fe779f8
CO		 3361 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
3362 return ret;
3363}
3364
b927a3ce
SY		 3365static int kvm_vm_ioctl_set_identity_map_addr(struct kvm *kvm,
3366 u64 ident_addr)
3367{
3368 kvm->arch.ept_identity_map_addr = ident_addr;
3369 return 0;
3370}
3371
1fe779f8
CO		 3372static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
3373 u32 kvm_nr_mmu_pages)
3374{
3375 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
3376 return -EINVAL;
3377
79fac95e 3378 mutex_lock(&kvm->slots_lock);
1fe779f8
CO		 3379
3380 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 3381 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 3382
79fac95e 3383 mutex_unlock(&kvm->slots_lock);
1fe779f8
CO		 3384 return 0;
3385}
3386
3387static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
3388{
39de71ec 3389 return kvm->arch.n_max_mmu_pages;
1fe779f8
CO		 3390}
3391
1fe779f8
CO		 3392static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3393{
3394 int r;
3395
3396 r = 0;
3397 switch (chip->chip_id) {
3398 case KVM_IRQCHIP_PIC_MASTER:
3399 memcpy(&chip->chip.pic,
3400 &pic_irqchip(kvm)->pics[0],
3401 sizeof(struct kvm_pic_state));
3402 break;
3403 case KVM_IRQCHIP_PIC_SLAVE:
3404 memcpy(&chip->chip.pic,
3405 &pic_irqchip(kvm)->pics[1],
3406 sizeof(struct kvm_pic_state));
3407 break;
3408 case KVM_IRQCHIP_IOAPIC:
eba0226b 3409 r = kvm_get_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3410 break;
3411 default:
3412 r = -EINVAL;
3413 break;
3414 }
3415 return r;
3416}
3417
3418static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
3419{
3420 int r;
3421
3422 r = 0;
3423 switch (chip->chip_id) {
3424 case KVM_IRQCHIP_PIC_MASTER:
f4f51050 3425 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3426 memcpy(&pic_irqchip(kvm)->pics[0],
3427 &chip->chip.pic,
3428 sizeof(struct kvm_pic_state));
f4f51050 3429 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3430 break;
3431 case KVM_IRQCHIP_PIC_SLAVE:
f4f51050 3432 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3433 memcpy(&pic_irqchip(kvm)->pics[1],
3434 &chip->chip.pic,
3435 sizeof(struct kvm_pic_state));
f4f51050 3436 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 3437 break;
3438 case KVM_IRQCHIP_IOAPIC:
eba0226b 3439 r = kvm_set_ioapic(kvm, &chip->chip.ioapic);
1fe779f8
CO		 3440 break;
3441 default:
3442 r = -EINVAL;
3443 break;
3444 }
3445 kvm_pic_update_irq(pic_irqchip(kvm));
3446 return r;
3447}
3448
e0f63cb9
SY		 3449static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3450{
3451 int r = 0;
3452
894a9c55 3453 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3454 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 3455 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3456 return r;
3457}
3458
3459static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
3460{
3461 int r = 0;
3462
894a9c55 3463 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 3464 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
e9f42757
BK		 3465 kvm_pit_load_count(kvm, 0, ps->channels[0].count, 0);
3466 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
3467 return r;
3468}
3469
3470static int kvm_vm_ioctl_get_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3471{
3472 int r = 0;
3473
3474 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3475 memcpy(ps->channels, &kvm->arch.vpit->pit_state.channels,
3476 sizeof(ps->channels));
3477 ps->flags = kvm->arch.vpit->pit_state.flags;
3478 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
97e69aa6 3479 memset(&ps->reserved, 0, sizeof(ps->reserved));
e9f42757
BK		 3480 return r;
3481}
3482
3483static int kvm_vm_ioctl_set_pit2(struct kvm *kvm, struct kvm_pit_state2 *ps)
3484{
3485 int r = 0, start = 0;
3486 u32 prev_legacy, cur_legacy;
3487 mutex_lock(&kvm->arch.vpit->pit_state.lock);
3488 prev_legacy = kvm->arch.vpit->pit_state.flags & KVM_PIT_FLAGS_HPET_LEGACY;
3489 cur_legacy = ps->flags & KVM_PIT_FLAGS_HPET_LEGACY;
3490 if (!prev_legacy && cur_legacy)
3491 start = 1;
3492 memcpy(&kvm->arch.vpit->pit_state.channels, &ps->channels,
3493 sizeof(kvm->arch.vpit->pit_state.channels));
3494 kvm->arch.vpit->pit_state.flags = ps->flags;
3495 kvm_pit_load_count(kvm, 0, kvm->arch.vpit->pit_state.channels[0].count, start);
894a9c55 3496 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 3497 return r;
3498}
3499
52d939a0
MT		 3500static int kvm_vm_ioctl_reinject(struct kvm *kvm,
3501 struct kvm_reinject_control *control)
3502{
3503 if (!kvm->arch.vpit)
3504 return -ENXIO;
894a9c55 3505 mutex_lock(&kvm->arch.vpit->pit_state.lock);
26ef1924 3506 kvm->arch.vpit->pit_state.reinject = control->pit_reinject;
894a9c55 3507 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 3508 return 0;
3509}
3510
95d4c16c 3511/**
60c34612
TY		 3512 * kvm_vm_ioctl_get_dirty_log - get and clear the log of dirty pages in a slot
3513 * @kvm: kvm instance
3514 * @log: slot id and address to which we copy the log
95d4c16c 3515 *
60c34612
TY		 3516 * We need to keep it in mind that VCPU threads can write to the bitmap
3517 * concurrently. So, to avoid losing data, we keep the following order for
3518 * each bit:
95d4c16c 3519 *
60c34612
TY		 3520 * 1. Take a snapshot of the bit and clear it if needed.
3521 * 2. Write protect the corresponding page.
3522 * 3. Flush TLB's if needed.
3523 * 4. Copy the snapshot to the userspace.
95d4c16c 3524 *
60c34612
TY		 3525 * Between 2 and 3, the guest may write to the page using the remaining TLB
3526 * entry. This is not a problem because the page will be reported dirty at
3527 * step 4 using the snapshot taken before and step 3 ensures that successive
3528 * writes will be logged for the next call.
5bb064dc 3529 */
60c34612 3530int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm, struct kvm_dirty_log *log)
5bb064dc 3531{
7850ac54 3532 int r;
5bb064dc 3533 struct kvm_memory_slot *memslot;
60c34612
TY		 3534 unsigned long n, i;
3535 unsigned long *dirty_bitmap;
3536 unsigned long *dirty_bitmap_buffer;
3537 bool is_dirty = false;
5bb064dc 3538
79fac95e 3539 mutex_lock(&kvm->slots_lock);
5bb064dc 3540
b050b015 3541 r = -EINVAL;
bbacc0c1 3542 if (log->slot >= KVM_USER_MEM_SLOTS)
b050b015
MT		 3543 goto out;
3544
28a37544 3545 memslot = id_to_memslot(kvm->memslots, log->slot);
60c34612
TY		 3546
3547 dirty_bitmap = memslot->dirty_bitmap;
b050b015 3548 r = -ENOENT;
60c34612 3549 if (!dirty_bitmap)
b050b015
MT		 3550 goto out;
3551
87bf6e7d 3552 n = kvm_dirty_bitmap_bytes(memslot);
b050b015 3553
60c34612
TY		 3554 dirty_bitmap_buffer = dirty_bitmap + n / sizeof(long);
3555 memset(dirty_bitmap_buffer, 0, n);
b050b015 3556
60c34612 3557 spin_lock(&kvm->mmu_lock);
b050b015 3558
60c34612
TY		 3559 for (i = 0; i < n / sizeof(long); i++) {
3560 unsigned long mask;
3561 gfn_t offset;
cdfca7b3 3562
60c34612
TY		 3563 if (!dirty_bitmap[i])
3564 continue;
b050b015 3565
60c34612 3566 is_dirty = true;
914ebccd 3567
60c34612
TY		 3568 mask = xchg(&dirty_bitmap[i], 0);
3569 dirty_bitmap_buffer[i] = mask;
edde99ce 3570
60c34612
TY		 3571 offset = i * BITS_PER_LONG;
3572 kvm_mmu_write_protect_pt_masked(kvm, memslot, offset, mask);
5bb064dc 3573 }
60c34612
TY		 3574 if (is_dirty)
3575 kvm_flush_remote_tlbs(kvm);
3576
3577 spin_unlock(&kvm->mmu_lock);
3578
3579 r = -EFAULT;
3580 if (copy_to_user(log->dirty_bitmap, dirty_bitmap_buffer, n))
3581 goto out;
b050b015 3582
5bb064dc
ZX		 3583 r = 0;
3584out:
79fac95e 3585 mutex_unlock(&kvm->slots_lock);
5bb064dc
ZX		 3586 return r;
3587}
3588
aa2fbe6d
YZ		 3589int kvm_vm_ioctl_irq_line(struct kvm *kvm, struct kvm_irq_level *irq_event,
3590 bool line_status)
23d43cf9
CD		 3591{
3592 if (!irqchip_in_kernel(kvm))
3593 return -ENXIO;
3594
3595 irq_event->status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
aa2fbe6d
YZ		 3596 irq_event->irq, irq_event->level,
3597 line_status);
23d43cf9
CD		 3598 return 0;
3599}
3600
1fe779f8
CO		 3601long kvm_arch_vm_ioctl(struct file *filp,
3602 unsigned int ioctl, unsigned long arg)
3603{
3604 struct kvm *kvm = filp->private_data;
3605 void __user *argp = (void __user *)arg;
367e1319 3606 int r = -ENOTTY;
f0d66275
DH		 3607 /*
3608 * This union makes it completely explicit to gcc-3.x
3609 * that these two variables' stack usage should be
3610 * combined, not added together.
3611 */
3612 union {
3613 struct kvm_pit_state ps;
e9f42757 3614 struct kvm_pit_state2 ps2;
c5ff41ce 3615 struct kvm_pit_config pit_config;
f0d66275 3616 } u;
1fe779f8
CO		 3617
3618 switch (ioctl) {
3619 case KVM_SET_TSS_ADDR:
3620 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
1fe779f8 3621 break;
b927a3ce
SY		 3622 case KVM_SET_IDENTITY_MAP_ADDR: {
3623 u64 ident_addr;
3624
3625 r = -EFAULT;
3626 if (copy_from_user(&ident_addr, argp, sizeof ident_addr))
3627 goto out;
3628 r = kvm_vm_ioctl_set_identity_map_addr(kvm, ident_addr);
b927a3ce
SY		 3629 break;
3630 }
1fe779f8
CO		 3631 case KVM_SET_NR_MMU_PAGES:
3632 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
1fe779f8
CO		 3633 break;
3634 case KVM_GET_NR_MMU_PAGES:
3635 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
3636 break;
3ddea128
MT		 3637 case KVM_CREATE_IRQCHIP: {
3638 struct kvm_pic *vpic;
3639
3640 mutex_lock(&kvm->lock);
3641 r = -EEXIST;
3642 if (kvm->arch.vpic)
3643 goto create_irqchip_unlock;
3e515705
AK		 3644 r = -EINVAL;
3645 if (atomic_read(&kvm->online_vcpus))
3646 goto create_irqchip_unlock;
1fe779f8 3647 r = -ENOMEM;
3ddea128
MT		 3648 vpic = kvm_create_pic(kvm);
3649 if (vpic) {
1fe779f8
CO		 3650 r = kvm_ioapic_init(kvm);
3651 if (r) {
175504cd 3652 mutex_lock(&kvm->slots_lock);
72bb2fcd 3653 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
743eeb0b
SL		 3654 &vpic->dev_master);
3655 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3656 &vpic->dev_slave);
3657 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS,
3658 &vpic->dev_eclr);
175504cd 3659 mutex_unlock(&kvm->slots_lock);
3ddea128
MT		 3660 kfree(vpic);
3661 goto create_irqchip_unlock;
1fe779f8
CO		 3662 }
3663 } else
3ddea128
MT		 3664 goto create_irqchip_unlock;
3665 smp_wmb();
3666 kvm->arch.vpic = vpic;
3667 smp_wmb();
399ec807
AK		 3668 r = kvm_setup_default_irq_routing(kvm);
3669 if (r) {
175504cd 3670 mutex_lock(&kvm->slots_lock);
3ddea128 3671 mutex_lock(&kvm->irq_lock);
72bb2fcd
WY		 3672 kvm_ioapic_destroy(kvm);
3673 kvm_destroy_pic(kvm);
3ddea128 3674 mutex_unlock(&kvm->irq_lock);
175504cd 3675 mutex_unlock(&kvm->slots_lock);
399ec807 3676 }
3ddea128
MT		 3677 create_irqchip_unlock:
3678 mutex_unlock(&kvm->lock);
1fe779f8 3679 break;
3ddea128 3680 }
7837699f 3681 case KVM_CREATE_PIT:
c5ff41ce
JK		 3682 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
3683 goto create_pit;
3684 case KVM_CREATE_PIT2:
3685 r = -EFAULT;
3686 if (copy_from_user(&u.pit_config, argp,
3687 sizeof(struct kvm_pit_config)))
3688 goto out;
3689 create_pit:
79fac95e 3690 mutex_lock(&kvm->slots_lock);
269e05e4
AK		 3691 r = -EEXIST;
3692 if (kvm->arch.vpit)
3693 goto create_pit_unlock;
7837699f 3694 r = -ENOMEM;
c5ff41ce 3695 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 3696 if (kvm->arch.vpit)
3697 r = 0;
269e05e4 3698 create_pit_unlock:
79fac95e 3699 mutex_unlock(&kvm->slots_lock);
7837699f 3700 break;
1fe779f8
CO		 3701 case KVM_GET_IRQCHIP: {
3702 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3703 struct kvm_irqchip *chip;
1fe779f8 3704
ff5c2c03
SL		 3705 chip = memdup_user(argp, sizeof(*chip));
3706 if (IS_ERR(chip)) {
3707 r = PTR_ERR(chip);
1fe779f8 3708 goto out;
ff5c2c03
SL		 3709 }
3710
1fe779f8
CO		 3711 r = -ENXIO;
3712 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3713 goto get_irqchip_out;
3714 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 3715 if (r)
f0d66275 3716 goto get_irqchip_out;
1fe779f8 3717 r = -EFAULT;
f0d66275
DH		 3718 if (copy_to_user(argp, chip, sizeof *chip))
3719 goto get_irqchip_out;
1fe779f8 3720 r = 0;
f0d66275
DH		 3721 get_irqchip_out:
3722 kfree(chip);
1fe779f8
CO		 3723 break;
3724 }
3725 case KVM_SET_IRQCHIP: {
3726 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
ff5c2c03 3727 struct kvm_irqchip *chip;
1fe779f8 3728
ff5c2c03
SL		 3729 chip = memdup_user(argp, sizeof(*chip));
3730 if (IS_ERR(chip)) {
3731 r = PTR_ERR(chip);
1fe779f8 3732 goto out;
ff5c2c03
SL		 3733 }
3734
1fe779f8
CO		 3735 r = -ENXIO;
3736 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 3737 goto set_irqchip_out;
3738 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 3739 if (r)
f0d66275 3740 goto set_irqchip_out;
1fe779f8 3741 r = 0;
f0d66275
DH		 3742 set_irqchip_out:
3743 kfree(chip);
1fe779f8
CO		 3744 break;
3745 }
e0f63cb9 3746 case KVM_GET_PIT: {
e0f63cb9 3747 r = -EFAULT;
f0d66275 3748 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3749 goto out;
3750 r = -ENXIO;
3751 if (!kvm->arch.vpit)
3752 goto out;
f0d66275 3753 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 3754 if (r)
3755 goto out;
3756 r = -EFAULT;
f0d66275 3757 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 3758 goto out;
3759 r = 0;
3760 break;
3761 }
3762 case KVM_SET_PIT: {
e0f63cb9 3763 r = -EFAULT;
f0d66275 3764 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 3765 goto out;
3766 r = -ENXIO;
3767 if (!kvm->arch.vpit)
3768 goto out;
f0d66275 3769 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 3770 break;
3771 }
e9f42757
BK		 3772 case KVM_GET_PIT2: {
3773 r = -ENXIO;
3774 if (!kvm->arch.vpit)
3775 goto out;
3776 r = kvm_vm_ioctl_get_pit2(kvm, &u.ps2);
3777 if (r)
3778 goto out;
3779 r = -EFAULT;
3780 if (copy_to_user(argp, &u.ps2, sizeof(u.ps2)))
3781 goto out;
3782 r = 0;
3783 break;
3784 }
3785 case KVM_SET_PIT2: {
3786 r = -EFAULT;
3787 if (copy_from_user(&u.ps2, argp, sizeof(u.ps2)))
3788 goto out;
3789 r = -ENXIO;
3790 if (!kvm->arch.vpit)
3791 goto out;
3792 r = kvm_vm_ioctl_set_pit2(kvm, &u.ps2);
e9f42757
BK		 3793 break;
3794 }
52d939a0
MT		 3795 case KVM_REINJECT_CONTROL: {
3796 struct kvm_reinject_control control;
3797 r = -EFAULT;
3798 if (copy_from_user(&control, argp, sizeof(control)))
3799 goto out;
3800 r = kvm_vm_ioctl_reinject(kvm, &control);
52d939a0
MT		 3801 break;
3802 }
ffde22ac
ES		 3803 case KVM_XEN_HVM_CONFIG: {
3804 r = -EFAULT;
3805 if (copy_from_user(&kvm->arch.xen_hvm_config, argp,
3806 sizeof(struct kvm_xen_hvm_config)))
3807 goto out;
3808 r = -EINVAL;
3809 if (kvm->arch.xen_hvm_config.flags)
3810 goto out;
3811 r = 0;
3812 break;
3813 }
afbcf7ab 3814 case KVM_SET_CLOCK: {
afbcf7ab
GC		 3815 struct kvm_clock_data user_ns;
3816 u64 now_ns;
3817 s64 delta;
3818
3819 r = -EFAULT;
3820 if (copy_from_user(&user_ns, argp, sizeof(user_ns)))
3821 goto out;
3822
3823 r = -EINVAL;
3824 if (user_ns.flags)
3825 goto out;
3826
3827 r = 0;
395c6b0a 3828 local_irq_disable();
759379dd 3829 now_ns = get_kernel_ns();
afbcf7ab 3830 delta = user_ns.clock - now_ns;
395c6b0a 3831 local_irq_enable();
afbcf7ab 3832 kvm->arch.kvmclock_offset = delta;
2e762ff7 3833 kvm_gen_update_masterclock(kvm);
afbcf7ab
GC		 3834 break;
3835 }
3836 case KVM_GET_CLOCK: {
afbcf7ab
GC		 3837 struct kvm_clock_data user_ns;
3838 u64 now_ns;
3839
395c6b0a 3840 local_irq_disable();
759379dd 3841 now_ns = get_kernel_ns();
afbcf7ab 3842 user_ns.clock = kvm->arch.kvmclock_offset + now_ns;
395c6b0a 3843 local_irq_enable();
afbcf7ab 3844 user_ns.flags = 0;
97e69aa6 3845 memset(&user_ns.pad, 0, sizeof(user_ns.pad));
afbcf7ab
GC		 3846
3847 r = -EFAULT;
3848 if (copy_to_user(argp, &user_ns, sizeof(user_ns)))
3849 goto out;
3850 r = 0;
3851 break;
3852 }
3853
1fe779f8
CO		 3854 default:
3855 ;
3856 }
3857out:
3858 return r;
3859}
3860
a16b043c 3861static void kvm_init_msr_list(void)
043405e1
CO		 3862{
3863 u32 dummy[2];
3864 unsigned i, j;
3865
e3267cbb
GC		 3866 /* skip the first msrs in the list. KVM-specific */
3867 for (i = j = KVM_SAVE_MSRS_BEGIN; i < ARRAY_SIZE(msrs_to_save); i++) {
043405e1
CO		 3868 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
3869 continue;
3870 if (j < i)
3871 msrs_to_save[j] = msrs_to_save[i];
3872 j++;
3873 }
3874 num_msrs_to_save = j;
3875}
3876
bda9020e
MT		 3877static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
3878 const void *v)
bbd9b64e 3879{
70252a10
AK		 3880 int handled = 0;
3881 int n;
3882
3883 do {
3884 n = min(len, 8);
3885 if (!(vcpu->arch.apic &&
3886 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, n, v))
3887 && kvm_io_bus_write(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3888 break;
3889 handled += n;
3890 addr += n;
3891 len -= n;
3892 v += n;
3893 } while (len);
bbd9b64e 3894
70252a10 3895 return handled;
bbd9b64e
CO		 3896}
3897
bda9020e 3898static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 3899{
70252a10
AK		 3900 int handled = 0;
3901 int n;
3902
3903 do {
3904 n = min(len, 8);
3905 if (!(vcpu->arch.apic &&
3906 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, n, v))
3907 && kvm_io_bus_read(vcpu->kvm, KVM_MMIO_BUS, addr, n, v))
3908 break;
3909 trace_kvm_mmio(KVM_TRACE_MMIO_READ, n, addr, *(u64 *)v);
3910 handled += n;
3911 addr += n;
3912 len -= n;
3913 v += n;
3914 } while (len);
bbd9b64e 3915
70252a10 3916 return handled;
bbd9b64e
CO		 3917}
3918
2dafc6c2
GN		 3919static void kvm_set_segment(struct kvm_vcpu *vcpu,
3920 struct kvm_segment *var, int seg)
3921{
3922 kvm_x86_ops->set_segment(vcpu, var, seg);
3923}
3924
3925void kvm_get_segment(struct kvm_vcpu *vcpu,
3926 struct kvm_segment *var, int seg)
3927{
3928 kvm_x86_ops->get_segment(vcpu, var, seg);
3929}
3930
e459e322 3931gpa_t translate_nested_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access)
02f59dc9
JR		 3932{
3933 gpa_t t_gpa;
ab9ae313 3934 struct x86_exception exception;
02f59dc9
JR		 3935
3936 BUG_ON(!mmu_is_nested(vcpu));
3937
3938 /* NPT walks are always user-walks */
3939 access |= PFERR_USER_MASK;
ab9ae313 3940 t_gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, gpa, access, &exception);
02f59dc9
JR		 3941
3942 return t_gpa;
3943}
3944
ab9ae313
AK		 3945gpa_t kvm_mmu_gva_to_gpa_read(struct kvm_vcpu *vcpu, gva_t gva,
3946 struct x86_exception *exception)
1871c602
GN		 3947{
3948 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
ab9ae313 3949 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3950}
3951
ab9ae313
AK		 3952 gpa_t kvm_mmu_gva_to_gpa_fetch(struct kvm_vcpu *vcpu, gva_t gva,
3953 struct x86_exception *exception)
1871c602
GN		 3954{
3955 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3956 access |= PFERR_FETCH_MASK;
ab9ae313 3957 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3958}
3959
ab9ae313
AK		 3960gpa_t kvm_mmu_gva_to_gpa_write(struct kvm_vcpu *vcpu, gva_t gva,
3961 struct x86_exception *exception)
1871c602
GN		 3962{
3963 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
3964 access |= PFERR_WRITE_MASK;
ab9ae313 3965 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
1871c602
GN		 3966}
3967
3968/* uses this to access any guest's mapped memory without checking CPL */
ab9ae313
AK		 3969gpa_t kvm_mmu_gva_to_gpa_system(struct kvm_vcpu *vcpu, gva_t gva,
3970 struct x86_exception *exception)
1871c602 3971{
ab9ae313 3972 return vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, 0, exception);
1871c602
GN		 3973}
3974
3975static int kvm_read_guest_virt_helper(gva_t addr, void *val, unsigned int bytes,
3976 struct kvm_vcpu *vcpu, u32 access,
bcc55cba 3977 struct x86_exception *exception)
bbd9b64e
CO		 3978{
3979 void *data = val;
10589a46 3980 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 3981
3982 while (bytes) {
14dfe855 3983 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr, access,
ab9ae313 3984 exception);
bbd9b64e 3985 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 3986 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 3987 int ret;
3988
bcc55cba 3989 if (gpa == UNMAPPED_GVA)
ab9ae313 3990 return X86EMUL_PROPAGATE_FAULT;
77c2002e 3991 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46 3992 if (ret < 0) {
c3cd7ffa 3993 r = X86EMUL_IO_NEEDED;
10589a46
MT		 3994 goto out;
3995 }
bbd9b64e 3996
77c2002e
IE		 3997 bytes -= toread;
3998 data += toread;
3999 addr += toread;
bbd9b64e 4000 }
10589a46 4001out:
10589a46 4002 return r;
bbd9b64e 4003}
77c2002e 4004
1871c602 4005/* used for instruction fetching */
0f65dd70
AK		 4006static int kvm_fetch_guest_virt(struct x86_emulate_ctxt *ctxt,
4007 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4008 struct x86_exception *exception)
1871c602 4009{
0f65dd70 4010 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4011 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4012
1871c602 4013 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu,
bcc55cba
AK		 4014 access | PFERR_FETCH_MASK,
4015 exception);
1871c602
GN		 4016}
4017
064aea77 4018int kvm_read_guest_virt(struct x86_emulate_ctxt *ctxt,
0f65dd70 4019 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4020 struct x86_exception *exception)
1871c602 4021{
0f65dd70 4022 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
1871c602 4023 u32 access = (kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0;
0f65dd70 4024
1871c602 4025 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, access,
bcc55cba 4026 exception);
1871c602 4027}
064aea77 4028EXPORT_SYMBOL_GPL(kvm_read_guest_virt);
1871c602 4029
0f65dd70
AK		 4030static int kvm_read_guest_virt_system(struct x86_emulate_ctxt *ctxt,
4031 gva_t addr, void *val, unsigned int bytes,
bcc55cba 4032 struct x86_exception *exception)
1871c602 4033{
0f65dd70 4034 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
bcc55cba 4035 return kvm_read_guest_virt_helper(addr, val, bytes, vcpu, 0, exception);
1871c602
GN		 4036}
4037
6a4d7550 4038int kvm_write_guest_virt_system(struct x86_emulate_ctxt *ctxt,
0f65dd70 4039 gva_t addr, void *val,
2dafc6c2 4040 unsigned int bytes,
bcc55cba 4041 struct x86_exception *exception)
77c2002e 4042{
0f65dd70 4043 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
77c2002e
IE		 4044 void *data = val;
4045 int r = X86EMUL_CONTINUE;
4046
4047 while (bytes) {
14dfe855
JR		 4048 gpa_t gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, addr,
4049 PFERR_WRITE_MASK,
ab9ae313 4050 exception);
77c2002e
IE		 4051 unsigned offset = addr & (PAGE_SIZE-1);
4052 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
4053 int ret;
4054
bcc55cba 4055 if (gpa == UNMAPPED_GVA)
ab9ae313 4056 return X86EMUL_PROPAGATE_FAULT;
77c2002e
IE		 4057 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
4058 if (ret < 0) {
c3cd7ffa 4059 r = X86EMUL_IO_NEEDED;
77c2002e
IE		 4060 goto out;
4061 }
4062
4063 bytes -= towrite;
4064 data += towrite;
4065 addr += towrite;
4066 }
4067out:
4068 return r;
4069}
6a4d7550 4070EXPORT_SYMBOL_GPL(kvm_write_guest_virt_system);
77c2002e 4071
af7cc7d1
XG		 4072static int vcpu_mmio_gva_to_gpa(struct kvm_vcpu *vcpu, unsigned long gva,
4073 gpa_t *gpa, struct x86_exception *exception,
4074 bool write)
4075{
97d64b78
AK		 4076 u32 access = ((kvm_x86_ops->get_cpl(vcpu) == 3) ? PFERR_USER_MASK : 0)
4077 | (write ? PFERR_WRITE_MASK : 0);
af7cc7d1 4078
97d64b78
AK		 4079 if (vcpu_match_mmio_gva(vcpu, gva)
4080 && !permission_fault(vcpu->arch.walk_mmu, vcpu->arch.access, access)) {
bebb106a
XG		 4081 *gpa = vcpu->arch.mmio_gfn << PAGE_SHIFT |
4082 (gva & (PAGE_SIZE - 1));
4f022648 4083 trace_vcpu_match_mmio(gva, *gpa, write, false);
bebb106a
XG		 4084 return 1;
4085 }
4086
af7cc7d1
XG		 4087 *gpa = vcpu->arch.walk_mmu->gva_to_gpa(vcpu, gva, access, exception);
4088
4089 if (*gpa == UNMAPPED_GVA)
4090 return -1;
4091
4092 /* For APIC access vmexit */
4093 if ((*gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4094 return 1;
4095
4f022648
XG		 4096 if (vcpu_match_mmio_gpa(vcpu, *gpa)) {
4097 trace_vcpu_match_mmio(gva, *gpa, write, true);
bebb106a 4098 return 1;
4f022648 4099 }
bebb106a 4100
af7cc7d1
XG		 4101 return 0;
4102}
4103
3200f405 4104int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
bcc55cba 4105 const void *val, int bytes)
bbd9b64e
CO		 4106{
4107 int ret;
4108
4109 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 4110 if (ret < 0)
bbd9b64e 4111 return 0;
f57f2ef5 4112 kvm_mmu_pte_write(vcpu, gpa, val, bytes);
bbd9b64e
CO		 4113 return 1;
4114}
4115
77d197b2
XG		 4116struct read_write_emulator_ops {
4117 int (*read_write_prepare)(struct kvm_vcpu *vcpu, void *val,
4118 int bytes);
4119 int (*read_write_emulate)(struct kvm_vcpu *vcpu, gpa_t gpa,
4120 void *val, int bytes);
4121 int (*read_write_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4122 int bytes, void *val);
4123 int (*read_write_exit_mmio)(struct kvm_vcpu *vcpu, gpa_t gpa,
4124 void *val, int bytes);
4125 bool write;
4126};
4127
4128static int read_prepare(struct kvm_vcpu *vcpu, void *val, int bytes)
4129{
4130 if (vcpu->mmio_read_completed) {
77d197b2 4131 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
f78146b0 4132 vcpu->mmio_fragments[0].gpa, *(u64 *)val);
77d197b2
XG		 4133 vcpu->mmio_read_completed = 0;
4134 return 1;
4135 }
4136
4137 return 0;
4138}
4139
4140static int read_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4141 void *val, int bytes)
4142{
4143 return !kvm_read_guest(vcpu->kvm, gpa, val, bytes);
4144}
4145
4146static int write_emulate(struct kvm_vcpu *vcpu, gpa_t gpa,
4147 void *val, int bytes)
4148{
4149 return emulator_write_phys(vcpu, gpa, val, bytes);
4150}
4151
4152static int write_mmio(struct kvm_vcpu *vcpu, gpa_t gpa, int bytes, void *val)
4153{
4154 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
4155 return vcpu_mmio_write(vcpu, gpa, bytes, val);
4156}
4157
4158static int read_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4159 void *val, int bytes)
4160{
4161 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
4162 return X86EMUL_IO_NEEDED;
4163}
4164
4165static int write_exit_mmio(struct kvm_vcpu *vcpu, gpa_t gpa,
4166 void *val, int bytes)
4167{
f78146b0
AK		 4168 struct kvm_mmio_fragment *frag = &vcpu->mmio_fragments[0];
4169
87da7e66 4170 memcpy(vcpu->run->mmio.data, frag->data, min(8u, frag->len));
77d197b2
XG		 4171 return X86EMUL_CONTINUE;
4172}
4173
0fbe9b0b 4174static const struct read_write_emulator_ops read_emultor = {
77d197b2
XG		 4175 .read_write_prepare = read_prepare,
4176 .read_write_emulate = read_emulate,
4177 .read_write_mmio = vcpu_mmio_read,
4178 .read_write_exit_mmio = read_exit_mmio,
4179};
4180
0fbe9b0b 4181static const struct read_write_emulator_ops write_emultor = {
77d197b2
XG		 4182 .read_write_emulate = write_emulate,
4183 .read_write_mmio = write_mmio,
4184 .read_write_exit_mmio = write_exit_mmio,
4185 .write = true,
4186};
4187
22388a3c
XG		 4188static int emulator_read_write_onepage(unsigned long addr, void *val,
4189 unsigned int bytes,
4190 struct x86_exception *exception,
4191 struct kvm_vcpu *vcpu,
0fbe9b0b 4192 const struct read_write_emulator_ops *ops)
bbd9b64e 4193{
af7cc7d1
XG		 4194 gpa_t gpa;
4195 int handled, ret;
22388a3c 4196 bool write = ops->write;
f78146b0 4197 struct kvm_mmio_fragment *frag;
10589a46 4198
22388a3c 4199 ret = vcpu_mmio_gva_to_gpa(vcpu, addr, &gpa, exception, write);
bbd9b64e 4200
af7cc7d1 4201 if (ret < 0)
bbd9b64e 4202 return X86EMUL_PROPAGATE_FAULT;
bbd9b64e
CO		 4203
4204 /* For APIC access vmexit */
af7cc7d1 4205 if (ret)
bbd9b64e
CO		 4206 goto mmio;
4207
22388a3c 4208 if (ops->read_write_emulate(vcpu, gpa, val, bytes))
bbd9b64e
CO		 4209 return X86EMUL_CONTINUE;
4210
4211mmio:
4212 /*
4213 * Is this MMIO handled locally?
4214 */
22388a3c 4215 handled = ops->read_write_mmio(vcpu, gpa, bytes, val);
70252a10 4216 if (handled == bytes)
bbd9b64e 4217 return X86EMUL_CONTINUE;
bbd9b64e 4218
70252a10
AK		 4219 gpa += handled;
4220 bytes -= handled;
4221 val += handled;
4222
87da7e66
XG		 4223 WARN_ON(vcpu->mmio_nr_fragments >= KVM_MAX_MMIO_FRAGMENTS);
4224 frag = &vcpu->mmio_fragments[vcpu->mmio_nr_fragments++];
4225 frag->gpa = gpa;
4226 frag->data = val;
4227 frag->len = bytes;
f78146b0 4228 return X86EMUL_CONTINUE;
bbd9b64e
CO		 4229}
4230
22388a3c
XG		 4231int emulator_read_write(struct x86_emulate_ctxt *ctxt, unsigned long addr,
4232 void *val, unsigned int bytes,
4233 struct x86_exception *exception,
0fbe9b0b 4234 const struct read_write_emulator_ops *ops)
bbd9b64e 4235{
0f65dd70 4236 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
f78146b0
AK		 4237 gpa_t gpa;
4238 int rc;
4239
4240 if (ops->read_write_prepare &&
4241 ops->read_write_prepare(vcpu, val, bytes))
4242 return X86EMUL_CONTINUE;
4243
4244 vcpu->mmio_nr_fragments = 0;
0f65dd70 4245
bbd9b64e
CO		 4246 /* Crossing a page boundary? */
4247 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
f78146b0 4248 int now;
bbd9b64e
CO		 4249
4250 now = -addr & ~PAGE_MASK;
22388a3c
XG		 4251 rc = emulator_read_write_onepage(addr, val, now, exception,
4252 vcpu, ops);
4253
bbd9b64e
CO		 4254 if (rc != X86EMUL_CONTINUE)
4255 return rc;
4256 addr += now;
4257 val += now;
4258 bytes -= now;
4259 }
22388a3c 4260
f78146b0
AK		 4261 rc = emulator_read_write_onepage(addr, val, bytes, exception,
4262 vcpu, ops);
4263 if (rc != X86EMUL_CONTINUE)
4264 return rc;
4265
4266 if (!vcpu->mmio_nr_fragments)
4267 return rc;
4268
4269 gpa = vcpu->mmio_fragments[0].gpa;
4270
4271 vcpu->mmio_needed = 1;
4272 vcpu->mmio_cur_fragment = 0;
4273
87da7e66 4274 vcpu->run->mmio.len = min(8u, vcpu->mmio_fragments[0].len);
f78146b0
AK		 4275 vcpu->run->mmio.is_write = vcpu->mmio_is_write = ops->write;
4276 vcpu->run->exit_reason = KVM_EXIT_MMIO;
4277 vcpu->run->mmio.phys_addr = gpa;
4278
4279 return ops->read_write_exit_mmio(vcpu, gpa, val, bytes);
22388a3c
XG		 4280}
4281
4282static int emulator_read_emulated(struct x86_emulate_ctxt *ctxt,
4283 unsigned long addr,
4284 void *val,
4285 unsigned int bytes,
4286 struct x86_exception *exception)
4287{
4288 return emulator_read_write(ctxt, addr, val, bytes,
4289 exception, &read_emultor);
4290}
4291
4292int emulator_write_emulated(struct x86_emulate_ctxt *ctxt,
4293 unsigned long addr,
4294 const void *val,
4295 unsigned int bytes,
4296 struct x86_exception *exception)
4297{
4298 return emulator_read_write(ctxt, addr, (void *)val, bytes,
4299 exception, &write_emultor);
bbd9b64e 4300}
bbd9b64e 4301
daea3e73
AK		 4302#define CMPXCHG_TYPE(t, ptr, old, new) \
4303 (cmpxchg((t *)(ptr), *(t *)(old), *(t *)(new)) == *(t *)(old))
4304
4305#ifdef CONFIG_X86_64
4306# define CMPXCHG64(ptr, old, new) CMPXCHG_TYPE(u64, ptr, old, new)
4307#else
4308# define CMPXCHG64(ptr, old, new) \
9749a6c0 4309 (cmpxchg64((u64 *)(ptr), *(u64 *)(old), *(u64 *)(new)) == *(u64 *)(old))
daea3e73
AK		 4310#endif
4311
0f65dd70
AK		 4312static int emulator_cmpxchg_emulated(struct x86_emulate_ctxt *ctxt,
4313 unsigned long addr,
bbd9b64e
CO		 4314 const void *old,
4315 const void *new,
4316 unsigned int bytes,
0f65dd70 4317 struct x86_exception *exception)
bbd9b64e 4318{
0f65dd70 4319 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
daea3e73
AK		 4320 gpa_t gpa;
4321 struct page *page;
4322 char *kaddr;
4323 bool exchanged;
2bacc55c 4324
daea3e73
AK		 4325 /* guests cmpxchg8b have to be emulated atomically */
4326 if (bytes > 8 || (bytes & (bytes - 1)))
4327 goto emul_write;
10589a46 4328
daea3e73 4329 gpa = kvm_mmu_gva_to_gpa_write(vcpu, addr, NULL);
2bacc55c 4330
daea3e73
AK		 4331 if (gpa == UNMAPPED_GVA ||
4332 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
4333 goto emul_write;
2bacc55c 4334
daea3e73
AK		 4335 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
4336 goto emul_write;
72dc67a6 4337
daea3e73 4338 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
32cad84f 4339 if (is_error_page(page))
c19b8bd6 4340 goto emul_write;
72dc67a6 4341
8fd75e12 4342 kaddr = kmap_atomic(page);
daea3e73
AK		 4343 kaddr += offset_in_page(gpa);
4344 switch (bytes) {
4345 case 1:
4346 exchanged = CMPXCHG_TYPE(u8, kaddr, old, new);
4347 break;
4348 case 2:
4349 exchanged = CMPXCHG_TYPE(u16, kaddr, old, new);
4350 break;
4351 case 4:
4352 exchanged = CMPXCHG_TYPE(u32, kaddr, old, new);
4353 break;
4354 case 8:
4355 exchanged = CMPXCHG64(kaddr, old, new);
4356 break;
4357 default:
4358 BUG();
2bacc55c 4359 }
8fd75e12 4360 kunmap_atomic(kaddr);
daea3e73
AK		 4361 kvm_release_page_dirty(page);
4362
4363 if (!exchanged)
4364 return X86EMUL_CMPXCHG_FAILED;
4365
f57f2ef5 4366 kvm_mmu_pte_write(vcpu, gpa, new, bytes);
8f6abd06
GN		 4367
4368 return X86EMUL_CONTINUE;
4a5f48f6 4369
3200f405 4370emul_write:
daea3e73 4371 printk_once(KERN_WARNING "kvm: emulating exchange as write\n");
2bacc55c 4372
0f65dd70 4373 return emulator_write_emulated(ctxt, addr, new, bytes, exception);
bbd9b64e
CO		 4374}
4375
cf8f70bf
GN		 4376static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
4377{
4378 /* TODO: String I/O for in kernel device */
4379 int r;
4380
4381 if (vcpu->arch.pio.in)
4382 r = kvm_io_bus_read(vcpu->kvm, KVM_PIO_BUS, vcpu->arch.pio.port,
4383 vcpu->arch.pio.size, pd);
4384 else
4385 r = kvm_io_bus_write(vcpu->kvm, KVM_PIO_BUS,
4386 vcpu->arch.pio.port, vcpu->arch.pio.size,
4387 pd);
4388 return r;
4389}
4390
6f6fbe98
XG		 4391static int emulator_pio_in_out(struct kvm_vcpu *vcpu, int size,
4392 unsigned short port, void *val,
4393 unsigned int count, bool in)
cf8f70bf 4394{
6f6fbe98 4395 trace_kvm_pio(!in, port, size, count);
cf8f70bf
GN		 4396
4397 vcpu->arch.pio.port = port;
6f6fbe98 4398 vcpu->arch.pio.in = in;
7972995b 4399 vcpu->arch.pio.count = count;
cf8f70bf
GN		 4400 vcpu->arch.pio.size = size;
4401
4402 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
7972995b 4403 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4404 return 1;
4405 }
4406
4407 vcpu->run->exit_reason = KVM_EXIT_IO;
6f6fbe98 4408 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
cf8f70bf
GN		 4409 vcpu->run->io.size = size;
4410 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
4411 vcpu->run->io.count = count;
4412 vcpu->run->io.port = port;
4413
4414 return 0;
4415}
4416
6f6fbe98
XG		 4417static int emulator_pio_in_emulated(struct x86_emulate_ctxt *ctxt,
4418 int size, unsigned short port, void *val,
4419 unsigned int count)
cf8f70bf 4420{
ca1d4a9e 4421 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
6f6fbe98 4422 int ret;
ca1d4a9e 4423
6f6fbe98
XG		 4424 if (vcpu->arch.pio.count)
4425 goto data_avail;
cf8f70bf 4426
6f6fbe98
XG		 4427 ret = emulator_pio_in_out(vcpu, size, port, val, count, true);
4428 if (ret) {
4429data_avail:
4430 memcpy(val, vcpu->arch.pio_data, size * count);
7972995b 4431 vcpu->arch.pio.count = 0;
cf8f70bf
GN		 4432 return 1;
4433 }
4434
cf8f70bf
GN		 4435 return 0;
4436}
4437
6f6fbe98
XG		 4438static int emulator_pio_out_emulated(struct x86_emulate_ctxt *ctxt,
4439 int size, unsigned short port,
4440 const void *val, unsigned int count)
4441{
4442 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4443
4444 memcpy(vcpu->arch.pio_data, val, size * count);
4445 return emulator_pio_in_out(vcpu, size, port, (void *)val, count, false);
4446}
4447
bbd9b64e
CO		 4448static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
4449{
4450 return kvm_x86_ops->get_segment_base(vcpu, seg);
4451}
4452
3cb16fe7 4453static void emulator_invlpg(struct x86_emulate_ctxt *ctxt, ulong address)
bbd9b64e 4454{
3cb16fe7 4455 kvm_mmu_invlpg(emul_to_vcpu(ctxt), address);
bbd9b64e
CO		 4456}
4457
f5f48ee1
SY		 4458int kvm_emulate_wbinvd(struct kvm_vcpu *vcpu)
4459{
4460 if (!need_emulate_wbinvd(vcpu))
4461 return X86EMUL_CONTINUE;
4462
4463 if (kvm_x86_ops->has_wbinvd_exit()) {
2eec7343
JK		 4464 int cpu = get_cpu();
4465
4466 cpumask_set_cpu(cpu, vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 4467 smp_call_function_many(vcpu->arch.wbinvd_dirty_mask,
4468 wbinvd_ipi, NULL, 1);
2eec7343 4469 put_cpu();
f5f48ee1 4470 cpumask_clear(vcpu->arch.wbinvd_dirty_mask);
2eec7343
JK		 4471 } else
4472 wbinvd();
f5f48ee1
SY		 4473 return X86EMUL_CONTINUE;
4474}
4475EXPORT_SYMBOL_GPL(kvm_emulate_wbinvd);
4476
bcaf5cc5
AK		 4477static void emulator_wbinvd(struct x86_emulate_ctxt *ctxt)
4478{
4479 kvm_emulate_wbinvd(emul_to_vcpu(ctxt));
4480}
4481
717746e3 4482int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
bbd9b64e 4483{
717746e3 4484 return _kvm_get_dr(emul_to_vcpu(ctxt), dr, dest);
bbd9b64e
CO		 4485}
4486
717746e3 4487int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
bbd9b64e 4488{
338dbc97 4489
717746e3 4490 return __kvm_set_dr(emul_to_vcpu(ctxt), dr, value);
bbd9b64e
CO		 4491}
4492
52a46617 4493static u64 mk_cr_64(u64 curr_cr, u32 new_val)
5fdbf976 4494{
52a46617 4495 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
5fdbf976
MT		 4496}
4497
717746e3 4498static unsigned long emulator_get_cr(struct x86_emulate_ctxt *ctxt, int cr)
bbd9b64e 4499{
717746e3 4500 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
52a46617
GN		 4501 unsigned long value;
4502
4503 switch (cr) {
4504 case 0:
4505 value = kvm_read_cr0(vcpu);
4506 break;
4507 case 2:
4508 value = vcpu->arch.cr2;
4509 break;
4510 case 3:
9f8fe504 4511 value = kvm_read_cr3(vcpu);
52a46617
GN		 4512 break;
4513 case 4:
4514 value = kvm_read_cr4(vcpu);
4515 break;
4516 case 8:
4517 value = kvm_get_cr8(vcpu);
4518 break;
4519 default:
a737f256 4520 kvm_err("%s: unexpected cr %u\n", __func__, cr);
52a46617
GN		 4521 return 0;
4522 }
4523
4524 return value;
4525}
4526
717746e3 4527static int emulator_set_cr(struct x86_emulate_ctxt *ctxt, int cr, ulong val)
52a46617 4528{
717746e3 4529 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
0f12244f
GN		 4530 int res = 0;
4531
52a46617
GN		 4532 switch (cr) {
4533 case 0:
49a9b07e 4534 res = kvm_set_cr0(vcpu, mk_cr_64(kvm_read_cr0(vcpu), val));
52a46617
GN		 4535 break;
4536 case 2:
4537 vcpu->arch.cr2 = val;
4538 break;
4539 case 3:
2390218b 4540 res = kvm_set_cr3(vcpu, val);
52a46617
GN		 4541 break;
4542 case 4:
a83b29c6 4543 res = kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
52a46617
GN		 4544 break;
4545 case 8:
eea1cff9 4546 res = kvm_set_cr8(vcpu, val);
52a46617
GN		 4547 break;
4548 default:
a737f256 4549 kvm_err("%s: unexpected cr %u\n", __func__, cr);
0f12244f 4550 res = -1;
52a46617 4551 }
0f12244f
GN		 4552
4553 return res;
52a46617
GN		 4554}
4555
4cee4798
KW		 4556static void emulator_set_rflags(struct x86_emulate_ctxt *ctxt, ulong val)
4557{
4558 kvm_set_rflags(emul_to_vcpu(ctxt), val);
4559}
4560
717746e3 4561static int emulator_get_cpl(struct x86_emulate_ctxt *ctxt)
9c537244 4562{
717746e3 4563 return kvm_x86_ops->get_cpl(emul_to_vcpu(ctxt));
9c537244
GN		 4564}
4565
4bff1e86 4566static void emulator_get_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
2dafc6c2 4567{
4bff1e86 4568 kvm_x86_ops->get_gdt(emul_to_vcpu(ctxt), dt);
2dafc6c2
GN		 4569}
4570
4bff1e86 4571static void emulator_get_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
160ce1f1 4572{
4bff1e86 4573 kvm_x86_ops->get_idt(emul_to_vcpu(ctxt), dt);
160ce1f1
MG		 4574}
4575
1ac9d0cf
AK		 4576static void emulator_set_gdt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4577{
4578 kvm_x86_ops->set_gdt(emul_to_vcpu(ctxt), dt);
4579}
4580
4581static void emulator_set_idt(struct x86_emulate_ctxt *ctxt, struct desc_ptr *dt)
4582{
4583 kvm_x86_ops->set_idt(emul_to_vcpu(ctxt), dt);
4584}
4585
4bff1e86
AK		 4586static unsigned long emulator_get_cached_segment_base(
4587 struct x86_emulate_ctxt *ctxt, int seg)
5951c442 4588{
4bff1e86 4589 return get_segment_base(emul_to_vcpu(ctxt), seg);
5951c442
GN		 4590}
4591
1aa36616
AK		 4592static bool emulator_get_segment(struct x86_emulate_ctxt *ctxt, u16 *selector,
4593 struct desc_struct *desc, u32 *base3,
4594 int seg)
2dafc6c2
GN		 4595{
4596 struct kvm_segment var;
4597
4bff1e86 4598 kvm_get_segment(emul_to_vcpu(ctxt), &var, seg);
1aa36616 4599 *selector = var.selector;
2dafc6c2 4600
378a8b09
GN		 4601 if (var.unusable) {
4602 memset(desc, 0, sizeof(*desc));
2dafc6c2 4603 return false;
378a8b09 4604 }
2dafc6c2
GN		 4605
4606 if (var.g)
4607 var.limit >>= 12;
4608 set_desc_limit(desc, var.limit);
4609 set_desc_base(desc, (unsigned long)var.base);
5601d05b
GN		 4610#ifdef CONFIG_X86_64
4611 if (base3)
4612 *base3 = var.base >> 32;
4613#endif
2dafc6c2
GN		 4614 desc->type = var.type;
4615 desc->s = var.s;
4616 desc->dpl = var.dpl;
4617 desc->p = var.present;
4618 desc->avl = var.avl;
4619 desc->l = var.l;
4620 desc->d = var.db;
4621 desc->g = var.g;
4622
4623 return true;
4624}
4625
1aa36616
AK		 4626static void emulator_set_segment(struct x86_emulate_ctxt *ctxt, u16 selector,
4627 struct desc_struct *desc, u32 base3,
4628 int seg)
2dafc6c2 4629{
4bff1e86 4630 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
2dafc6c2
GN		 4631 struct kvm_segment var;
4632
1aa36616 4633 var.selector = selector;
2dafc6c2 4634 var.base = get_desc_base(desc);
5601d05b
GN		 4635#ifdef CONFIG_X86_64
4636 var.base |= ((u64)base3) << 32;
4637#endif
2dafc6c2
GN		 4638 var.limit = get_desc_limit(desc);
4639 if (desc->g)
4640 var.limit = (var.limit << 12) | 0xfff;
4641 var.type = desc->type;
4642 var.present = desc->p;
4643 var.dpl = desc->dpl;
4644 var.db = desc->d;
4645 var.s = desc->s;
4646 var.l = desc->l;
4647 var.g = desc->g;
4648 var.avl = desc->avl;
4649 var.present = desc->p;
4650 var.unusable = !var.present;
4651 var.padding = 0;
4652
4653 kvm_set_segment(vcpu, &var, seg);
4654 return;
4655}
4656
717746e3
AK		 4657static int emulator_get_msr(struct x86_emulate_ctxt *ctxt,
4658 u32 msr_index, u64 *pdata)
4659{
4660 return kvm_get_msr(emul_to_vcpu(ctxt), msr_index, pdata);
4661}
4662
4663static int emulator_set_msr(struct x86_emulate_ctxt *ctxt,
4664 u32 msr_index, u64 data)
4665{
8fe8ab46
WA		 4666 struct msr_data msr;
4667
4668 msr.data = data;
4669 msr.index = msr_index;
4670 msr.host_initiated = false;
4671 return kvm_set_msr(emul_to_vcpu(ctxt), &msr);
717746e3
AK		 4672}
4673
222d21aa
AK		 4674static int emulator_read_pmc(struct x86_emulate_ctxt *ctxt,
4675 u32 pmc, u64 *pdata)
4676{
4677 return kvm_pmu_read_pmc(emul_to_vcpu(ctxt), pmc, pdata);
4678}
4679
6c3287f7
AK		 4680static void emulator_halt(struct x86_emulate_ctxt *ctxt)
4681{
4682 emul_to_vcpu(ctxt)->arch.halt_request = 1;
4683}
4684
5037f6f3
AK		 4685static void emulator_get_fpu(struct x86_emulate_ctxt *ctxt)
4686{
4687 preempt_disable();
5197b808 4688 kvm_load_guest_fpu(emul_to_vcpu(ctxt));
5037f6f3
AK		 4689 /*
4690 * CR0.TS may reference the host fpu state, not the guest fpu state,
4691 * so it may be clear at this point.
4692 */
4693 clts();
4694}
4695
4696static void emulator_put_fpu(struct x86_emulate_ctxt *ctxt)
4697{
4698 preempt_enable();
4699}
4700
2953538e 4701static int emulator_intercept(struct x86_emulate_ctxt *ctxt,
8a76d7f2 4702 struct x86_instruction_info *info,
c4f035c6
AK		 4703 enum x86_intercept_stage stage)
4704{
2953538e 4705 return kvm_x86_ops->check_intercept(emul_to_vcpu(ctxt), info, stage);
c4f035c6
AK		 4706}
4707
0017f93a 4708static void emulator_get_cpuid(struct x86_emulate_ctxt *ctxt,
bdb42f5a
SB		 4709 u32 *eax, u32 *ebx, u32 *ecx, u32 *edx)
4710{
0017f93a 4711 kvm_cpuid(emul_to_vcpu(ctxt), eax, ebx, ecx, edx);
bdb42f5a
SB		 4712}
4713
dd856efa
AK		 4714static ulong emulator_read_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg)
4715{
4716 return kvm_register_read(emul_to_vcpu(ctxt), reg);
4717}
4718
4719static void emulator_write_gpr(struct x86_emulate_ctxt *ctxt, unsigned reg, ulong val)
4720{
4721 kvm_register_write(emul_to_vcpu(ctxt), reg, val);
4722}
4723
0225fb50 4724static const struct x86_emulate_ops emulate_ops = {
dd856efa
AK		 4725 .read_gpr = emulator_read_gpr,
4726 .write_gpr = emulator_write_gpr,
1871c602 4727 .read_std = kvm_read_guest_virt_system,
2dafc6c2 4728 .write_std = kvm_write_guest_virt_system,
1871c602 4729 .fetch = kvm_fetch_guest_virt,
bbd9b64e
CO		 4730 .read_emulated = emulator_read_emulated,
4731 .write_emulated = emulator_write_emulated,
4732 .cmpxchg_emulated = emulator_cmpxchg_emulated,
3cb16fe7 4733 .invlpg = emulator_invlpg,
cf8f70bf
GN		 4734 .pio_in_emulated = emulator_pio_in_emulated,
4735 .pio_out_emulated = emulator_pio_out_emulated,
1aa36616
AK		 4736 .get_segment = emulator_get_segment,
4737 .set_segment = emulator_set_segment,
5951c442 4738 .get_cached_segment_base = emulator_get_cached_segment_base,
2dafc6c2 4739 .get_gdt = emulator_get_gdt,
160ce1f1 4740 .get_idt = emulator_get_idt,
1ac9d0cf
AK		 4741 .set_gdt = emulator_set_gdt,
4742 .set_idt = emulator_set_idt,
52a46617
GN		 4743 .get_cr = emulator_get_cr,
4744 .set_cr = emulator_set_cr,
4cee4798 4745 .set_rflags = emulator_set_rflags,
9c537244 4746 .cpl = emulator_get_cpl,
35aa5375
GN		 4747 .get_dr = emulator_get_dr,
4748 .set_dr = emulator_set_dr,
717746e3
AK		 4749 .set_msr = emulator_set_msr,
4750 .get_msr = emulator_get_msr,
222d21aa 4751 .read_pmc = emulator_read_pmc,
6c3287f7 4752 .halt = emulator_halt,
bcaf5cc5 4753 .wbinvd = emulator_wbinvd,
d6aa1000 4754 .fix_hypercall = emulator_fix_hypercall,
5037f6f3
AK		 4755 .get_fpu = emulator_get_fpu,
4756 .put_fpu = emulator_put_fpu,
c4f035c6 4757 .intercept = emulator_intercept,
bdb42f5a 4758 .get_cpuid = emulator_get_cpuid,
bbd9b64e
CO		 4759};
4760
95cb2295
GN		 4761static void toggle_interruptibility(struct kvm_vcpu *vcpu, u32 mask)
4762{
4763 u32 int_shadow = kvm_x86_ops->get_interrupt_shadow(vcpu, mask);
4764 /*
4765 * an sti; sti; sequence only disable interrupts for the first
4766 * instruction. So, if the last instruction, be it emulated or
4767 * not, left the system with the INT_STI flag enabled, it
4768 * means that the last instruction is an sti. We should not
4769 * leave the flag on in this case. The same goes for mov ss
4770 */
4771 if (!(int_shadow & mask))
4772 kvm_x86_ops->set_interrupt_shadow(vcpu, mask);
4773}
4774
54b8486f
GN		 4775static void inject_emulated_exception(struct kvm_vcpu *vcpu)
4776{
4777 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
da9cb575 4778 if (ctxt->exception.vector == PF_VECTOR)
6389ee94 4779 kvm_propagate_fault(vcpu, &ctxt->exception);
da9cb575
AK		 4780 else if (ctxt->exception.error_code_valid)
4781 kvm_queue_exception_e(vcpu, ctxt->exception.vector,
4782 ctxt->exception.error_code);
54b8486f 4783 else
da9cb575 4784 kvm_queue_exception(vcpu, ctxt->exception.vector);
54b8486f
GN		 4785}
4786
dd856efa 4787static void init_decode_cache(struct x86_emulate_ctxt *ctxt)
b5c9ff73 4788{
9dac77fa 4789 memset(&ctxt->twobyte, 0,
dd856efa 4790 (void *)&ctxt->_regs - (void *)&ctxt->twobyte);
b5c9ff73 4791
9dac77fa
AK		 4792 ctxt->fetch.start = 0;
4793 ctxt->fetch.end = 0;
4794 ctxt->io_read.pos = 0;
4795 ctxt->io_read.end = 0;
4796 ctxt->mem_read.pos = 0;
4797 ctxt->mem_read.end = 0;
b5c9ff73
TY		 4798}
4799
8ec4722d
MG		 4800static void init_emulate_ctxt(struct kvm_vcpu *vcpu)
4801{
adf52235 4802 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d
MG		 4803 int cs_db, cs_l;
4804
8ec4722d
MG		 4805 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
4806
adf52235
TY		 4807 ctxt->eflags = kvm_get_rflags(vcpu);
4808 ctxt->eip = kvm_rip_read(vcpu);
4809 ctxt->mode = (!is_protmode(vcpu)) ? X86EMUL_MODE_REAL :
4810 (ctxt->eflags & X86_EFLAGS_VM) ? X86EMUL_MODE_VM86 :
4811 cs_l ? X86EMUL_MODE_PROT64 :
4812 cs_db ? X86EMUL_MODE_PROT32 :
4813 X86EMUL_MODE_PROT16;
4814 ctxt->guest_mode = is_guest_mode(vcpu);
4815
dd856efa 4816 init_decode_cache(ctxt);
7ae441ea 4817 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
8ec4722d
MG		 4818}
4819
71f9833b 4820int kvm_inject_realmode_interrupt(struct kvm_vcpu *vcpu, int irq, int inc_eip)
63995653 4821{
9d74191a 4822 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
63995653
MG		 4823 int ret;
4824
4825 init_emulate_ctxt(vcpu);
4826
9dac77fa
AK		 4827 ctxt->op_bytes = 2;
4828 ctxt->ad_bytes = 2;
4829 ctxt->_eip = ctxt->eip + inc_eip;
9d74191a 4830 ret = emulate_int_real(ctxt, irq);
63995653
MG		 4831
4832 if (ret != X86EMUL_CONTINUE)
4833 return EMULATE_FAIL;
4834
9dac77fa 4835 ctxt->eip = ctxt->_eip;
9d74191a
TY		 4836 kvm_rip_write(vcpu, ctxt->eip);
4837 kvm_set_rflags(vcpu, ctxt->eflags);
63995653
MG		 4838
4839 if (irq == NMI_VECTOR)
7460fb4a 4840 vcpu->arch.nmi_pending = 0;
63995653
MG		 4841 else
4842 vcpu->arch.interrupt.pending = false;
4843
4844 return EMULATE_DONE;
4845}
4846EXPORT_SYMBOL_GPL(kvm_inject_realmode_interrupt);
4847
6d77dbfc
GN		 4848static int handle_emulation_failure(struct kvm_vcpu *vcpu)
4849{
fc3a9157
JR		 4850 int r = EMULATE_DONE;
4851
6d77dbfc
GN		 4852 ++vcpu->stat.insn_emulation_fail;
4853 trace_kvm_emulate_insn_failed(vcpu);
fc3a9157
JR		 4854 if (!is_guest_mode(vcpu)) {
4855 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4856 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4857 vcpu->run->internal.ndata = 0;
4858 r = EMULATE_FAIL;
4859 }
6d77dbfc 4860 kvm_queue_exception(vcpu, UD_VECTOR);
fc3a9157
JR		 4861
4862 return r;
6d77dbfc
GN		 4863}
4864
93c05d3e 4865static bool reexecute_instruction(struct kvm_vcpu *vcpu, gva_t cr2,
991eebf9
GN		 4866 bool write_fault_to_shadow_pgtable,
4867 int emulation_type)
a6f177ef 4868{
95b3cf69 4869 gpa_t gpa = cr2;
8e3d9d06 4870 pfn_t pfn;
a6f177ef 4871
991eebf9
GN		 4872 if (emulation_type & EMULTYPE_NO_REEXECUTE)
4873 return false;
4874
95b3cf69
XG		 4875 if (!vcpu->arch.mmu.direct_map) {
4876 /*
4877 * Write permission should be allowed since only
4878 * write access need to be emulated.
4879 */
4880 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
a6f177ef 4881
95b3cf69
XG		 4882 /*
4883 * If the mapping is invalid in guest, let cpu retry
4884 * it to generate fault.
4885 */
4886 if (gpa == UNMAPPED_GVA)
4887 return true;
4888 }
a6f177ef 4889
8e3d9d06
XG		 4890 /*
4891 * Do not retry the unhandleable instruction if it faults on the
4892 * readonly host memory, otherwise it will goto a infinite loop:
4893 * retry instruction -> write #PF -> emulation fail -> retry
4894 * instruction -> ...
4895 */
4896 pfn = gfn_to_pfn(vcpu->kvm, gpa_to_gfn(gpa));
95b3cf69
XG		 4897
4898 /*
4899 * If the instruction failed on the error pfn, it can not be fixed,
4900 * report the error to userspace.
4901 */
4902 if (is_error_noslot_pfn(pfn))
4903 return false;
4904
4905 kvm_release_pfn_clean(pfn);
4906
4907 /* The instructions are well-emulated on direct mmu. */
4908 if (vcpu->arch.mmu.direct_map) {
4909 unsigned int indirect_shadow_pages;
4910
4911 spin_lock(&vcpu->kvm->mmu_lock);
4912 indirect_shadow_pages = vcpu->kvm->arch.indirect_shadow_pages;
4913 spin_unlock(&vcpu->kvm->mmu_lock);
4914
4915 if (indirect_shadow_pages)
4916 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
4917
a6f177ef 4918 return true;
8e3d9d06 4919 }
a6f177ef 4920
95b3cf69
XG		 4921 /*
4922 * if emulation was due to access to shadowed page table
4923 * and it failed try to unshadow page and re-enter the
4924 * guest to let CPU execute the instruction.
4925 */
4926 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
93c05d3e
XG		 4927
4928 /*
4929 * If the access faults on its page table, it can not
4930 * be fixed by unprotecting shadow page and it should
4931 * be reported to userspace.
4932 */
4933 return !write_fault_to_shadow_pgtable;
a6f177ef
GN		 4934}
4935
1cb3f3ae
XG		 4936static bool retry_instruction(struct x86_emulate_ctxt *ctxt,
4937 unsigned long cr2, int emulation_type)
4938{
4939 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
4940 unsigned long last_retry_eip, last_retry_addr, gpa = cr2;
4941
4942 last_retry_eip = vcpu->arch.last_retry_eip;
4943 last_retry_addr = vcpu->arch.last_retry_addr;
4944
4945 /*
4946 * If the emulation is caused by #PF and it is non-page_table
4947 * writing instruction, it means the VM-EXIT is caused by shadow
4948 * page protected, we can zap the shadow page and retry this
4949 * instruction directly.
4950 *
4951 * Note: if the guest uses a non-page-table modifying instruction
4952 * on the PDE that points to the instruction, then we will unmap
4953 * the instruction and go to an infinite loop. So, we cache the
4954 * last retried eip and the last fault address, if we meet the eip
4955 * and the address again, we can break out of the potential infinite
4956 * loop.
4957 */
4958 vcpu->arch.last_retry_eip = vcpu->arch.last_retry_addr = 0;
4959
4960 if (!(emulation_type & EMULTYPE_RETRY))
4961 return false;
4962
4963 if (x86_page_table_writing_insn(ctxt))
4964 return false;
4965
4966 if (ctxt->eip == last_retry_eip && last_retry_addr == cr2)
4967 return false;
4968
4969 vcpu->arch.last_retry_eip = ctxt->eip;
4970 vcpu->arch.last_retry_addr = cr2;
4971
4972 if (!vcpu->arch.mmu.direct_map)
4973 gpa = kvm_mmu_gva_to_gpa_write(vcpu, cr2, NULL);
4974
22368028 4975 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(gpa));
1cb3f3ae
XG		 4976
4977 return true;
4978}
4979
716d51ab
GN		 4980static int complete_emulated_mmio(struct kvm_vcpu *vcpu);
4981static int complete_emulated_pio(struct kvm_vcpu *vcpu);
4982
4a1e10d5
PB		 4983static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 dr7,
4984 unsigned long *db)
4985{
4986 u32 dr6 = 0;
4987 int i;
4988 u32 enable, rwlen;
4989
4990 enable = dr7;
4991 rwlen = dr7 >> 16;
4992 for (i = 0; i < 4; i++, enable >>= 2, rwlen >>= 4)
4993 if ((enable & 3) && (rwlen & 15) == type && db[i] == addr)
4994 dr6 |= (1 << i);
4995 return dr6;
4996}
4997
663f4c61
PB		 4998static void kvm_vcpu_check_singlestep(struct kvm_vcpu *vcpu, int *r)
4999{
5000 struct kvm_run *kvm_run = vcpu->run;
5001
5002 /*
5003 * Use the "raw" value to see if TF was passed to the processor.
5004 * Note that the new value of the flags has not been saved yet.
5005 *
5006 * This is correct even for TF set by the guest, because "the
5007 * processor will not generate this exception after the instruction
5008 * that sets the TF flag".
5009 */
5010 unsigned long rflags = kvm_x86_ops->get_rflags(vcpu);
5011
5012 if (unlikely(rflags & X86_EFLAGS_TF)) {
5013 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
5014 kvm_run->debug.arch.dr6 = DR6_BS | DR6_FIXED_1;
5015 kvm_run->debug.arch.pc = vcpu->arch.singlestep_rip;
5016 kvm_run->debug.arch.exception = DB_VECTOR;
5017 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5018 *r = EMULATE_USER_EXIT;
5019 } else {
5020 vcpu->arch.emulate_ctxt.eflags &= ~X86_EFLAGS_TF;
5021 /*
5022 * "Certain debug exceptions may clear bit 0-3. The
5023 * remaining contents of the DR6 register are never
5024 * cleared by the processor".
5025 */
5026 vcpu->arch.dr6 &= ~15;
5027 vcpu->arch.dr6 |= DR6_BS;
5028 kvm_queue_exception(vcpu, DB_VECTOR);
5029 }
5030 }
5031}
5032
4a1e10d5
PB		 5033static bool kvm_vcpu_check_breakpoint(struct kvm_vcpu *vcpu, int *r)
5034{
5035 struct kvm_run *kvm_run = vcpu->run;
5036 unsigned long eip = vcpu->arch.emulate_ctxt.eip;
5037 u32 dr6 = 0;
5038
5039 if (unlikely(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) &&
5040 (vcpu->arch.guest_debug_dr7 & DR7_BP_EN_MASK)) {
5041 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5042 vcpu->arch.guest_debug_dr7,
5043 vcpu->arch.eff_db);
5044
5045 if (dr6 != 0) {
5046 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
5047 kvm_run->debug.arch.pc = kvm_rip_read(vcpu) +
5048 get_segment_base(vcpu, VCPU_SREG_CS);
5049
5050 kvm_run->debug.arch.exception = DB_VECTOR;
5051 kvm_run->exit_reason = KVM_EXIT_DEBUG;
5052 *r = EMULATE_USER_EXIT;
5053 return true;
5054 }
5055 }
5056
5057 if (unlikely(vcpu->arch.dr7 & DR7_BP_EN_MASK)) {
5058 dr6 = kvm_vcpu_check_hw_bp(eip, 0,
5059 vcpu->arch.dr7,
5060 vcpu->arch.db);
5061
5062 if (dr6 != 0) {
5063 vcpu->arch.dr6 &= ~15;
5064 vcpu->arch.dr6 |= dr6;
5065 kvm_queue_exception(vcpu, DB_VECTOR);
5066 *r = EMULATE_DONE;
5067 return true;
5068 }
5069 }
5070
5071 return false;
5072}
5073
51d8b661
AP		 5074int x86_emulate_instruction(struct kvm_vcpu *vcpu,
5075 unsigned long cr2,
dc25e89e
AP		 5076 int emulation_type,
5077 void *insn,
5078 int insn_len)
bbd9b64e 5079{
95cb2295 5080 int r;
9d74191a 5081 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
7ae441ea 5082 bool writeback = true;
93c05d3e 5083 bool write_fault_to_spt = vcpu->arch.write_fault_to_shadow_pgtable;
bbd9b64e 5084
93c05d3e
XG		 5085 /*
5086 * Clear write_fault_to_shadow_pgtable here to ensure it is
5087 * never reused.
5088 */
5089 vcpu->arch.write_fault_to_shadow_pgtable = false;
26eef70c 5090 kvm_clear_exception_queue(vcpu);
8d7d8102 5091
571008da 5092 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
8ec4722d 5093 init_emulate_ctxt(vcpu);
4a1e10d5
PB		 5094
5095 /*
5096 * We will reenter on the same instruction since
5097 * we do not set complete_userspace_io. This does not
5098 * handle watchpoints yet, those would be handled in
5099 * the emulate_ops.
5100 */
5101 if (kvm_vcpu_check_breakpoint(vcpu, &r))
5102 return r;
5103
9d74191a
TY		 5104 ctxt->interruptibility = 0;
5105 ctxt->have_exception = false;
5106 ctxt->perm_ok = false;
bbd9b64e 5107
9d74191a 5108 ctxt->only_vendor_specific_insn
4005996e
AK		 5109 = emulation_type & EMULTYPE_TRAP_UD;
5110
9d74191a 5111 r = x86_decode_insn(ctxt, insn, insn_len);
bbd9b64e 5112
e46479f8 5113 trace_kvm_emulate_insn_start(vcpu);
f2b5756b 5114 ++vcpu->stat.insn_emulation;
1d2887e2 5115 if (r != EMULATION_OK) {
4005996e
AK		 5116 if (emulation_type & EMULTYPE_TRAP_UD)
5117 return EMULATE_FAIL;
991eebf9
GN		 5118 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5119 emulation_type))
bbd9b64e 5120 return EMULATE_DONE;
6d77dbfc
GN		 5121 if (emulation_type & EMULTYPE_SKIP)
5122 return EMULATE_FAIL;
5123 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5124 }
5125 }
5126
ba8afb6b 5127 if (emulation_type & EMULTYPE_SKIP) {
9dac77fa 5128 kvm_rip_write(vcpu, ctxt->_eip);
ba8afb6b
GN		 5129 return EMULATE_DONE;
5130 }
5131
1cb3f3ae
XG		 5132 if (retry_instruction(ctxt, cr2, emulation_type))
5133 return EMULATE_DONE;
5134
7ae441ea 5135 /* this is needed for vmware backdoor interface to work since it
4d2179e1 5136 changes registers values during IO operation */
7ae441ea
GN		 5137 if (vcpu->arch.emulate_regs_need_sync_from_vcpu) {
5138 vcpu->arch.emulate_regs_need_sync_from_vcpu = false;
dd856efa 5139 emulator_invalidate_register_cache(ctxt);
7ae441ea 5140 }
4d2179e1 5141
5cd21917 5142restart:
9d74191a 5143 r = x86_emulate_insn(ctxt);
bbd9b64e 5144
775fde86
JR		 5145 if (r == EMULATION_INTERCEPTED)
5146 return EMULATE_DONE;
5147
d2ddd1c4 5148 if (r == EMULATION_FAILED) {
991eebf9
GN		 5149 if (reexecute_instruction(vcpu, cr2, write_fault_to_spt,
5150 emulation_type))
c3cd7ffa
GN		 5151 return EMULATE_DONE;
5152
6d77dbfc 5153 return handle_emulation_failure(vcpu);
bbd9b64e
CO		 5154 }
5155
9d74191a 5156 if (ctxt->have_exception) {
54b8486f 5157 inject_emulated_exception(vcpu);
d2ddd1c4
GN		 5158 r = EMULATE_DONE;
5159 } else if (vcpu->arch.pio.count) {
0912c977
PB		 5160 if (!vcpu->arch.pio.in) {
5161 /* FIXME: return into emulator if single-stepping. */
3457e419 5162 vcpu->arch.pio.count = 0;
0912c977 5163 } else {
7ae441ea 5164 writeback = false;
716d51ab
GN		 5165 vcpu->arch.complete_userspace_io = complete_emulated_pio;
5166 }
ac0a48c3 5167 r = EMULATE_USER_EXIT;
7ae441ea
GN		 5168 } else if (vcpu->mmio_needed) {
5169 if (!vcpu->mmio_is_write)
5170 writeback = false;
ac0a48c3 5171 r = EMULATE_USER_EXIT;
716d51ab 5172 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
7ae441ea 5173 } else if (r == EMULATION_RESTART)
5cd21917 5174 goto restart;
d2ddd1c4
GN		 5175 else
5176 r = EMULATE_DONE;
f850e2e6 5177
7ae441ea 5178 if (writeback) {
9d74191a 5179 toggle_interruptibility(vcpu, ctxt->interruptibility);
7ae441ea 5180 kvm_make_request(KVM_REQ_EVENT, vcpu);
7ae441ea 5181 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
9d74191a 5182 kvm_rip_write(vcpu, ctxt->eip);
663f4c61
PB		 5183 if (r == EMULATE_DONE)
5184 kvm_vcpu_check_singlestep(vcpu, &r);
5185 kvm_set_rflags(vcpu, ctxt->eflags);
7ae441ea
GN		 5186 } else
5187 vcpu->arch.emulate_regs_need_sync_to_vcpu = true;
e85d28f8
GN		 5188
5189 return r;
de7d789a 5190}
51d8b661 5191EXPORT_SYMBOL_GPL(x86_emulate_instruction);
de7d789a 5192
cf8f70bf 5193int kvm_fast_pio_out(struct kvm_vcpu *vcpu, int size, unsigned short port)
de7d789a 5194{
cf8f70bf 5195 unsigned long val = kvm_register_read(vcpu, VCPU_REGS_RAX);
ca1d4a9e
AK		 5196 int ret = emulator_pio_out_emulated(&vcpu->arch.emulate_ctxt,
5197 size, port, &val, 1);
cf8f70bf 5198 /* do not return to emulator after return from userspace */
7972995b 5199 vcpu->arch.pio.count = 0;
de7d789a
CO		 5200 return ret;
5201}
cf8f70bf 5202EXPORT_SYMBOL_GPL(kvm_fast_pio_out);
de7d789a 5203
8cfdc000
ZA		 5204static void tsc_bad(void *info)
5205{
0a3aee0d 5206 __this_cpu_write(cpu_tsc_khz, 0);
8cfdc000
ZA		 5207}
5208
5209static void tsc_khz_changed(void *data)
c8076604 5210{
8cfdc000
ZA		 5211 struct cpufreq_freqs *freq = data;
5212 unsigned long khz = 0;
5213
5214 if (data)
5215 khz = freq->new;
5216 else if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5217 khz = cpufreq_quick_get(raw_smp_processor_id());
5218 if (!khz)
5219 khz = tsc_khz;
0a3aee0d 5220 __this_cpu_write(cpu_tsc_khz, khz);
c8076604
GH		 5221}
5222
c8076604
GH		 5223static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
5224 void *data)
5225{
5226 struct cpufreq_freqs *freq = data;
5227 struct kvm *kvm;
5228 struct kvm_vcpu *vcpu;
5229 int i, send_ipi = 0;
5230
8cfdc000
ZA		 5231 /*
5232 * We allow guests to temporarily run on slowing clocks,
5233 * provided we notify them after, or to run on accelerating
5234 * clocks, provided we notify them before. Thus time never
5235 * goes backwards.
5236 *
5237 * However, we have a problem. We can't atomically update
5238 * the frequency of a given CPU from this function; it is
5239 * merely a notifier, which can be called from any CPU.
5240 * Changing the TSC frequency at arbitrary points in time
5241 * requires a recomputation of local variables related to
5242 * the TSC for each VCPU. We must flag these local variables
5243 * to be updated and be sure the update takes place with the
5244 * new frequency before any guests proceed.
5245 *
5246 * Unfortunately, the combination of hotplug CPU and frequency
5247 * change creates an intractable locking scenario; the order
5248 * of when these callouts happen is undefined with respect to
5249 * CPU hotplug, and they can race with each other. As such,
5250 * merely setting per_cpu(cpu_tsc_khz) = X during a hotadd is
5251 * undefined; you can actually have a CPU frequency change take
5252 * place in between the computation of X and the setting of the
5253 * variable. To protect against this problem, all updates of
5254 * the per_cpu tsc_khz variable are done in an interrupt
5255 * protected IPI, and all callers wishing to update the value
5256 * must wait for a synchronous IPI to complete (which is trivial
5257 * if the caller is on the CPU already). This establishes the
5258 * necessary total order on variable updates.
5259 *
5260 * Note that because a guest time update may take place
5261 * anytime after the setting of the VCPU's request bit, the
5262 * correct TSC value must be set before the request. However,
5263 * to ensure the update actually makes it to any guest which
5264 * starts running in hardware virtualization between the set
5265 * and the acquisition of the spinlock, we must also ping the
5266 * CPU after setting the request bit.
5267 *
5268 */
5269
c8076604
GH		 5270 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
5271 return 0;
5272 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
5273 return 0;
8cfdc000
ZA		 5274
5275 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604 5276
2f303b74 5277 spin_lock(&kvm_lock);
c8076604 5278 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 5279 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 5280 if (vcpu->cpu != freq->cpu)
5281 continue;
c285545f 5282 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
c8076604 5283 if (vcpu->cpu != smp_processor_id())
8cfdc000 5284 send_ipi = 1;
c8076604
GH		 5285 }
5286 }
2f303b74 5287 spin_unlock(&kvm_lock);
c8076604
GH		 5288
5289 if (freq->old < freq->new && send_ipi) {
5290 /*
5291 * We upscale the frequency. Must make the guest
5292 * doesn't see old kvmclock values while running with
5293 * the new frequency, otherwise we risk the guest sees
5294 * time go backwards.
5295 *
5296 * In case we update the frequency for another cpu
5297 * (which might be in guest context) send an interrupt
5298 * to kick the cpu out of guest context. Next time
5299 * guest context is entered kvmclock will be updated,
5300 * so the guest will not see stale values.
5301 */
8cfdc000 5302 smp_call_function_single(freq->cpu, tsc_khz_changed, freq, 1);
c8076604
GH		 5303 }
5304 return 0;
5305}
5306
5307static struct notifier_block kvmclock_cpufreq_notifier_block = {
8cfdc000
ZA		 5308 .notifier_call = kvmclock_cpufreq_notifier
5309};
5310
5311static int kvmclock_cpu_notifier(struct notifier_block *nfb,
5312 unsigned long action, void *hcpu)
5313{
5314 unsigned int cpu = (unsigned long)hcpu;
5315
5316 switch (action) {
5317 case CPU_ONLINE:
5318 case CPU_DOWN_FAILED:
5319 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
5320 break;
5321 case CPU_DOWN_PREPARE:
5322 smp_call_function_single(cpu, tsc_bad, NULL, 1);
5323 break;
5324 }
5325 return NOTIFY_OK;
5326}
5327
5328static struct notifier_block kvmclock_cpu_notifier_block = {
5329 .notifier_call = kvmclock_cpu_notifier,
5330 .priority = -INT_MAX
c8076604
GH		 5331};
5332
b820cc0c
ZA		 5333static void kvm_timer_init(void)
5334{
5335 int cpu;
5336
c285545f 5337 max_tsc_khz = tsc_khz;
8cfdc000 5338 register_hotcpu_notifier(&kvmclock_cpu_notifier_block);
b820cc0c 5339 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
c285545f
ZA		 5340#ifdef CONFIG_CPU_FREQ
5341 struct cpufreq_policy policy;
5342 memset(&policy, 0, sizeof(policy));
3e26f230
AK		 5343 cpu = get_cpu();
5344 cpufreq_get_policy(&policy, cpu);
c285545f
ZA		 5345 if (policy.cpuinfo.max_freq)
5346 max_tsc_khz = policy.cpuinfo.max_freq;
3e26f230 5347 put_cpu();
c285545f 5348#endif
b820cc0c
ZA		 5349 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
5350 CPUFREQ_TRANSITION_NOTIFIER);
5351 }
c285545f 5352 pr_debug("kvm: max_tsc_khz = %ld\n", max_tsc_khz);
8cfdc000
ZA		 5353 for_each_online_cpu(cpu)
5354 smp_call_function_single(cpu, tsc_khz_changed, NULL, 1);
b820cc0c
ZA		 5355}
5356
ff9d07a0
ZY		 5357static DEFINE_PER_CPU(struct kvm_vcpu *, current_vcpu);
5358
f5132b01 5359int kvm_is_in_guest(void)
ff9d07a0 5360{
086c9855 5361 return __this_cpu_read(current_vcpu) != NULL;
ff9d07a0
ZY		 5362}
5363
5364static int kvm_is_user_mode(void)
5365{
5366 int user_mode = 3;
dcf46b94 5367
086c9855
AS		 5368 if (__this_cpu_read(current_vcpu))
5369 user_mode = kvm_x86_ops->get_cpl(__this_cpu_read(current_vcpu));
dcf46b94 5370
ff9d07a0
ZY		 5371 return user_mode != 0;
5372}
5373
5374static unsigned long kvm_get_guest_ip(void)
5375{
5376 unsigned long ip = 0;
dcf46b94 5377
086c9855
AS		 5378 if (__this_cpu_read(current_vcpu))
5379 ip = kvm_rip_read(__this_cpu_read(current_vcpu));
dcf46b94 5380
ff9d07a0
ZY		 5381 return ip;
5382}
5383
5384static struct perf_guest_info_callbacks kvm_guest_cbs = {
5385 .is_in_guest = kvm_is_in_guest,
5386 .is_user_mode = kvm_is_user_mode,
5387 .get_guest_ip = kvm_get_guest_ip,
5388};
5389
5390void kvm_before_handle_nmi(struct kvm_vcpu *vcpu)
5391{
086c9855 5392 __this_cpu_write(current_vcpu, vcpu);
ff9d07a0
ZY		 5393}
5394EXPORT_SYMBOL_GPL(kvm_before_handle_nmi);
5395
5396void kvm_after_handle_nmi(struct kvm_vcpu *vcpu)
5397{
086c9855 5398 __this_cpu_write(current_vcpu, NULL);
ff9d07a0
ZY		 5399}
5400EXPORT_SYMBOL_GPL(kvm_after_handle_nmi);
5401
ce88decf
XG		 5402static void kvm_set_mmio_spte_mask(void)
5403{
5404 u64 mask;
5405 int maxphyaddr = boot_cpu_data.x86_phys_bits;
5406
5407 /*
5408 * Set the reserved bits and the present bit of an paging-structure
5409 * entry to generate page fault with PFER.RSV = 1.
5410 */
885032b9
XG		 5411 /* Mask the reserved physical address bits. */
5412 mask = ((1ull << (51 - maxphyaddr + 1)) - 1) << maxphyaddr;
5413
5414 /* Bit 62 is always reserved for 32bit host. */
5415 mask |= 0x3ull << 62;
5416
5417 /* Set the present bit. */
ce88decf
XG		 5418 mask |= 1ull;
5419
5420#ifdef CONFIG_X86_64
5421 /*
5422 * If reserved bit is not supported, clear the present bit to disable
5423 * mmio page fault.
5424 */
5425 if (maxphyaddr == 52)
5426 mask &= ~1ull;
5427#endif
5428
5429 kvm_mmu_set_mmio_spte_mask(mask);
5430}
5431
16e8d74d
MT		 5432#ifdef CONFIG_X86_64
5433static void pvclock_gtod_update_fn(struct work_struct *work)
5434{
d828199e
MT		 5435 struct kvm *kvm;
5436
5437 struct kvm_vcpu *vcpu;
5438 int i;
5439
2f303b74 5440 spin_lock(&kvm_lock);
d828199e
MT		 5441 list_for_each_entry(kvm, &vm_list, vm_list)
5442 kvm_for_each_vcpu(i, vcpu, kvm)
5443 set_bit(KVM_REQ_MASTERCLOCK_UPDATE, &vcpu->requests);
5444 atomic_set(&kvm_guest_has_master_clock, 0);
2f303b74 5445 spin_unlock(&kvm_lock);
16e8d74d
MT		 5446}
5447
5448static DECLARE_WORK(pvclock_gtod_work, pvclock_gtod_update_fn);
5449
5450/*
5451 * Notification about pvclock gtod data update.
5452 */
5453static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
5454 void *priv)
5455{
5456 struct pvclock_gtod_data *gtod = &pvclock_gtod_data;
5457 struct timekeeper *tk = priv;
5458
5459 update_pvclock_gtod(tk);
5460
5461 /* disable master clock if host does not trust, or does not
5462 * use, TSC clocksource
5463 */
5464 if (gtod->clock.vclock_mode != VCLOCK_TSC &&
5465 atomic_read(&kvm_guest_has_master_clock) != 0)
5466 queue_work(system_long_wq, &pvclock_gtod_work);
5467
5468 return 0;
5469}
5470
5471static struct notifier_block pvclock_gtod_notifier = {
5472 .notifier_call = pvclock_gtod_notify,
5473};
5474#endif
5475
f8c16bba 5476int kvm_arch_init(void *opaque)
043405e1 5477{
b820cc0c 5478 int r;
6b61edf7 5479 struct kvm_x86_ops *ops = opaque;
f8c16bba 5480
f8c16bba
ZX		 5481 if (kvm_x86_ops) {
5482 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 5483 r = -EEXIST;
5484 goto out;
f8c16bba
ZX		 5485 }
5486
5487 if (!ops->cpu_has_kvm_support()) {
5488 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 5489 r = -EOPNOTSUPP;
5490 goto out;
f8c16bba
ZX		 5491 }
5492 if (ops->disabled_by_bios()) {
5493 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 5494 r = -EOPNOTSUPP;
5495 goto out;
f8c16bba
ZX		 5496 }
5497
013f6a5d
MT		 5498 r = -ENOMEM;
5499 shared_msrs = alloc_percpu(struct kvm_shared_msrs);
5500 if (!shared_msrs) {
5501 printk(KERN_ERR "kvm: failed to allocate percpu kvm_shared_msrs\n");
5502 goto out;
5503 }
5504
97db56ce
AK		 5505 r = kvm_mmu_module_init();
5506 if (r)
013f6a5d 5507 goto out_free_percpu;
97db56ce 5508
ce88decf 5509 kvm_set_mmio_spte_mask();
97db56ce
AK		 5510 kvm_init_msr_list();
5511
f8c16bba 5512 kvm_x86_ops = ops;
7b52345e 5513 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 5514 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604 5515
b820cc0c 5516 kvm_timer_init();
c8076604 5517
ff9d07a0
ZY		 5518 perf_register_guest_info_callbacks(&kvm_guest_cbs);
5519
2acf923e
DC		 5520 if (cpu_has_xsave)
5521 host_xcr0 = xgetbv(XCR_XFEATURE_ENABLED_MASK);
5522
c5cc421b 5523 kvm_lapic_init();
16e8d74d
MT		 5524#ifdef CONFIG_X86_64
5525 pvclock_gtod_register_notifier(&pvclock_gtod_notifier);
5526#endif
5527
f8c16bba 5528 return 0;
56c6d28a 5529
013f6a5d
MT		 5530out_free_percpu:
5531 free_percpu(shared_msrs);
56c6d28a 5532out:
56c6d28a 5533 return r;
043405e1 5534}
8776e519 5535
f8c16bba
ZX		 5536void kvm_arch_exit(void)
5537{
ff9d07a0
ZY		 5538 perf_unregister_guest_info_callbacks(&kvm_guest_cbs);
5539
888d256e
JK		 5540 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
5541 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
5542 CPUFREQ_TRANSITION_NOTIFIER);
8cfdc000 5543 unregister_hotcpu_notifier(&kvmclock_cpu_notifier_block);
16e8d74d
MT		 5544#ifdef CONFIG_X86_64
5545 pvclock_gtod_unregister_notifier(&pvclock_gtod_notifier);
5546#endif
f8c16bba 5547 kvm_x86_ops = NULL;
56c6d28a 5548 kvm_mmu_module_exit();
013f6a5d 5549 free_percpu(shared_msrs);
56c6d28a 5550}
f8c16bba 5551
8776e519
HB		 5552int kvm_emulate_halt(struct kvm_vcpu *vcpu)
5553{
5554 ++vcpu->stat.halt_exits;
5555 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 5556 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 5557 return 1;
5558 } else {
5559 vcpu->run->exit_reason = KVM_EXIT_HLT;
5560 return 0;
5561 }
5562}
5563EXPORT_SYMBOL_GPL(kvm_emulate_halt);
5564
55cd8e5a
GN		 5565int kvm_hv_hypercall(struct kvm_vcpu *vcpu)
5566{
5567 u64 param, ingpa, outgpa, ret;
5568 uint16_t code, rep_idx, rep_cnt, res = HV_STATUS_SUCCESS, rep_done = 0;
5569 bool fast, longmode;
5570 int cs_db, cs_l;
5571
5572 /*
5573 * hypercall generates UD from non zero cpl and real mode
5574 * per HYPER-V spec
5575 */
3eeb3288 5576 if (kvm_x86_ops->get_cpl(vcpu) != 0 || !is_protmode(vcpu)) {
55cd8e5a
GN		 5577 kvm_queue_exception(vcpu, UD_VECTOR);
5578 return 0;
5579 }
5580
5581 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
5582 longmode = is_long_mode(vcpu) && cs_l == 1;
5583
5584 if (!longmode) {
ccd46936
GN		 5585 param = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDX) << 32) |
5586 (kvm_register_read(vcpu, VCPU_REGS_RAX) & 0xffffffff);
5587 ingpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RBX) << 32) |
5588 (kvm_register_read(vcpu, VCPU_REGS_RCX) & 0xffffffff);
5589 outgpa = ((u64)kvm_register_read(vcpu, VCPU_REGS_RDI) << 32) |
5590 (kvm_register_read(vcpu, VCPU_REGS_RSI) & 0xffffffff);
55cd8e5a
GN		 5591 }
5592#ifdef CONFIG_X86_64
5593 else {
5594 param = kvm_register_read(vcpu, VCPU_REGS_RCX);
5595 ingpa = kvm_register_read(vcpu, VCPU_REGS_RDX);
5596 outgpa = kvm_register_read(vcpu, VCPU_REGS_R8);
5597 }
5598#endif
5599
5600 code = param & 0xffff;
5601 fast = (param >> 16) & 0x1;
5602 rep_cnt = (param >> 32) & 0xfff;
5603 rep_idx = (param >> 48) & 0xfff;
5604
5605 trace_kvm_hv_hypercall(code, fast, rep_cnt, rep_idx, ingpa, outgpa);
5606
c25bc163
GN		 5607 switch (code) {
5608 case HV_X64_HV_NOTIFY_LONG_SPIN_WAIT:
5609 kvm_vcpu_on_spin(vcpu);
5610 break;
5611 default:
5612 res = HV_STATUS_INVALID_HYPERCALL_CODE;
5613 break;
5614 }
55cd8e5a
GN		 5615
5616 ret = res | (((u64)rep_done & 0xfff) << 32);
5617 if (longmode) {
5618 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
5619 } else {
5620 kvm_register_write(vcpu, VCPU_REGS_RDX, ret >> 32);
5621 kvm_register_write(vcpu, VCPU_REGS_RAX, ret & 0xffffffff);
5622 }
5623
5624 return 1;
5625}
5626
6aef266c
SV		 5627/*
5628 * kvm_pv_kick_cpu_op: Kick a vcpu.
5629 *
5630 * @apicid - apicid of vcpu to be kicked.
5631 */
5632static void kvm_pv_kick_cpu_op(struct kvm *kvm, unsigned long flags, int apicid)
5633{
24d2166b 5634 struct kvm_lapic_irq lapic_irq;
6aef266c 5635
24d2166b
R		 5636 lapic_irq.shorthand = 0;
5637 lapic_irq.dest_mode = 0;
5638 lapic_irq.dest_id = apicid;
6aef266c 5639
24d2166b
R		 5640 lapic_irq.delivery_mode = APIC_DM_REMRD;
5641 kvm_irq_delivery_to_apic(kvm, 0, &lapic_irq, NULL);
6aef266c
SV		 5642}
5643
8776e519
HB		 5644int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
5645{
5646 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 5647 int r = 1;
8776e519 5648
55cd8e5a
GN		 5649 if (kvm_hv_hypercall_enabled(vcpu->kvm))
5650 return kvm_hv_hypercall(vcpu);
5651
5fdbf976
MT		 5652 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
5653 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
5654 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
5655 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
5656 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 5657
229456fc 5658 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 5659
8776e519
HB		 5660 if (!is_long_mode(vcpu)) {
5661 nr &= 0xFFFFFFFF;
5662 a0 &= 0xFFFFFFFF;
5663 a1 &= 0xFFFFFFFF;
5664 a2 &= 0xFFFFFFFF;
5665 a3 &= 0xFFFFFFFF;
5666 }
5667
07708c4a
JK		 5668 if (kvm_x86_ops->get_cpl(vcpu) != 0) {
5669 ret = -KVM_EPERM;
5670 goto out;
5671 }
5672
8776e519 5673 switch (nr) {
b93463aa
AK		 5674 case KVM_HC_VAPIC_POLL_IRQ:
5675 ret = 0;
5676 break;
6aef266c
SV		 5677 case KVM_HC_KICK_CPU:
5678 kvm_pv_kick_cpu_op(vcpu->kvm, a0, a1);
5679 ret = 0;
5680 break;
8776e519
HB		 5681 default:
5682 ret = -KVM_ENOSYS;
5683 break;
5684 }
07708c4a 5685out:
5fdbf976 5686 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 5687 ++vcpu->stat.hypercalls;
2f333bcb 5688 return r;
8776e519
HB		 5689}
5690EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
5691
b6785def 5692static int emulator_fix_hypercall(struct x86_emulate_ctxt *ctxt)
8776e519 5693{
d6aa1000 5694 struct kvm_vcpu *vcpu = emul_to_vcpu(ctxt);
8776e519 5695 char instruction[3];
5fdbf976 5696 unsigned long rip = kvm_rip_read(vcpu);
8776e519 5697
8776e519 5698 kvm_x86_ops->patch_hypercall(vcpu, instruction);
8776e519 5699
9d74191a 5700 return emulator_write_emulated(ctxt, rip, instruction, 3, NULL);
8776e519
HB		 5701}
5702
b6c7a5dc
HB		 5703/*
5704 * Check if userspace requested an interrupt window, and that the
5705 * interrupt window is open.
5706 *
5707 * No need to exit to userspace if we already have an interrupt queued.
5708 */
851ba692 5709static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu)
b6c7a5dc 5710{
8061823a 5711 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
851ba692 5712 vcpu->run->request_interrupt_window &&
5df56646 5713 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 5714}
5715
851ba692 5716static void post_kvm_run_save(struct kvm_vcpu *vcpu)
b6c7a5dc 5717{
851ba692
AK		 5718 struct kvm_run *kvm_run = vcpu->run;
5719
91586a3b 5720 kvm_run->if_flag = (kvm_get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 5721 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 5722 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 5723 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 5724 kvm_run->ready_for_interrupt_injection = 1;
4531220b 5725 else
b6c7a5dc 5726 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 5727 kvm_arch_interrupt_allowed(vcpu) &&
5728 !kvm_cpu_has_interrupt(vcpu) &&
5729 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 5730}
5731
4484141a 5732static int vapic_enter(struct kvm_vcpu *vcpu)
b93463aa
AK		 5733{
5734 struct kvm_lapic *apic = vcpu->arch.apic;
5735 struct page *page;
5736
5737 if (!apic || !apic->vapic_addr)
4484141a 5738 return 0;
b93463aa
AK		 5739
5740 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
4484141a
XG		 5741 if (is_error_page(page))
5742 return -EFAULT;
72dc67a6
IE		 5743
5744 vcpu->arch.apic->vapic_page = page;
4484141a 5745 return 0;
b93463aa
AK		 5746}
5747
5748static void vapic_exit(struct kvm_vcpu *vcpu)
5749{
5750 struct kvm_lapic *apic = vcpu->arch.apic;
f656ce01 5751 int idx;
b93463aa
AK		 5752
5753 if (!apic || !apic->vapic_addr)
5754 return;
5755
f656ce01 5756 idx = srcu_read_lock(&vcpu->kvm->srcu);
b93463aa
AK		 5757 kvm_release_page_dirty(apic->vapic_page);
5758 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f656ce01 5759 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b93463aa
AK		 5760}
5761
95ba8273
GN		 5762static void update_cr8_intercept(struct kvm_vcpu *vcpu)
5763{
5764 int max_irr, tpr;
5765
5766 if (!kvm_x86_ops->update_cr8_intercept)
5767 return;
5768
88c808fd
AK		 5769 if (!vcpu->arch.apic)
5770 return;
5771
8db3baa2
GN		 5772 if (!vcpu->arch.apic->vapic_addr)
5773 max_irr = kvm_lapic_find_highest_irr(vcpu);
5774 else
5775 max_irr = -1;
95ba8273
GN		 5776
5777 if (max_irr != -1)
5778 max_irr >>= 4;
5779
5780 tpr = kvm_lapic_get_cr8(vcpu);
5781
5782 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
5783}
5784
851ba692 5785static void inject_pending_event(struct kvm_vcpu *vcpu)
95ba8273
GN		 5786{
5787 /* try to reinject previous events if any */
b59bb7bd 5788 if (vcpu->arch.exception.pending) {
5c1c85d0
AK		 5789 trace_kvm_inj_exception(vcpu->arch.exception.nr,
5790 vcpu->arch.exception.has_error_code,
5791 vcpu->arch.exception.error_code);
b59bb7bd
GN		 5792 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
5793 vcpu->arch.exception.has_error_code,
ce7ddec4
JR		 5794 vcpu->arch.exception.error_code,
5795 vcpu->arch.exception.reinject);
b59bb7bd
GN		 5796 return;
5797 }
5798
95ba8273
GN		 5799 if (vcpu->arch.nmi_injected) {
5800 kvm_x86_ops->set_nmi(vcpu);
5801 return;
5802 }
5803
5804 if (vcpu->arch.interrupt.pending) {
66fd3f7f 5805 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5806 return;
5807 }
5808
5809 /* try to inject new event if pending */
5810 if (vcpu->arch.nmi_pending) {
5811 if (kvm_x86_ops->nmi_allowed(vcpu)) {
7460fb4a 5812 --vcpu->arch.nmi_pending;
95ba8273
GN		 5813 vcpu->arch.nmi_injected = true;
5814 kvm_x86_ops->set_nmi(vcpu);
5815 }
c7c9c56c 5816 } else if (kvm_cpu_has_injectable_intr(vcpu)) {
95ba8273 5817 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 5818 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
5819 false);
5820 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 5821 }
5822 }
5823}
5824
7460fb4a
AK		 5825static void process_nmi(struct kvm_vcpu *vcpu)
5826{
5827 unsigned limit = 2;
5828
5829 /*
5830 * x86 is limited to one NMI running, and one NMI pending after it.
5831 * If an NMI is already in progress, limit further NMIs to just one.
5832 * Otherwise, allow two (and we'll inject the first one immediately).
5833 */
5834 if (kvm_x86_ops->get_nmi_mask(vcpu) || vcpu->arch.nmi_injected)
5835 limit = 1;
5836
5837 vcpu->arch.nmi_pending += atomic_xchg(&vcpu->arch.nmi_queued, 0);
5838 vcpu->arch.nmi_pending = min(vcpu->arch.nmi_pending, limit);
5839 kvm_make_request(KVM_REQ_EVENT, vcpu);
5840}
5841
3d81bc7e 5842static void vcpu_scan_ioapic(struct kvm_vcpu *vcpu)
c7c9c56c
YZ		 5843{
5844 u64 eoi_exit_bitmap[4];
cf9e65b7 5845 u32 tmr[8];
c7c9c56c 5846
3d81bc7e
YZ		 5847 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
5848 return;
c7c9c56c
YZ		 5849
5850 memset(eoi_exit_bitmap, 0, 32);
cf9e65b7 5851 memset(tmr, 0, 32);
c7c9c56c 5852
cf9e65b7 5853 kvm_ioapic_scan_entry(vcpu, eoi_exit_bitmap, tmr);
c7c9c56c 5854 kvm_x86_ops->load_eoi_exitmap(vcpu, eoi_exit_bitmap);
cf9e65b7 5855 kvm_apic_update_tmr(vcpu, tmr);
c7c9c56c
YZ		 5856}
5857
851ba692 5858static int vcpu_enter_guest(struct kvm_vcpu *vcpu)
b6c7a5dc
HB		 5859{
5860 int r;
6a8b1d13 5861 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
851ba692 5862 vcpu->run->request_interrupt_window;
730dca42 5863 bool req_immediate_exit = false;
b6c7a5dc 5864
3e007509 5865 if (vcpu->requests) {
a8eeb04a 5866 if (kvm_check_request(KVM_REQ_MMU_RELOAD, vcpu))
2e53d63a 5867 kvm_mmu_unload(vcpu);
a8eeb04a 5868 if (kvm_check_request(KVM_REQ_MIGRATE_TIMER, vcpu))
2f599714 5869 __kvm_migrate_timers(vcpu);
d828199e
MT		 5870 if (kvm_check_request(KVM_REQ_MASTERCLOCK_UPDATE, vcpu))
5871 kvm_gen_update_masterclock(vcpu->kvm);
0061d53d
MT		 5872 if (kvm_check_request(KVM_REQ_GLOBAL_CLOCK_UPDATE, vcpu))
5873 kvm_gen_kvmclock_update(vcpu);
34c238a1
ZA		 5874 if (kvm_check_request(KVM_REQ_CLOCK_UPDATE, vcpu)) {
5875 r = kvm_guest_time_update(vcpu);
8cfdc000
ZA		 5876 if (unlikely(r))
5877 goto out;
5878 }
a8eeb04a 5879 if (kvm_check_request(KVM_REQ_MMU_SYNC, vcpu))
4731d4c7 5880 kvm_mmu_sync_roots(vcpu);
a8eeb04a 5881 if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
d4acf7e7 5882 kvm_x86_ops->tlb_flush(vcpu);
a8eeb04a 5883 if (kvm_check_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu)) {
851ba692 5884 vcpu->run->exit_reason = KVM_EXIT_TPR_ACCESS;
b93463aa
AK		 5885 r = 0;
5886 goto out;
5887 }
a8eeb04a 5888 if (kvm_check_request(KVM_REQ_TRIPLE_FAULT, vcpu)) {
851ba692 5889 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
71c4dfaf
JR		 5890 r = 0;
5891 goto out;
5892 }
a8eeb04a 5893 if (kvm_check_request(KVM_REQ_DEACTIVATE_FPU, vcpu)) {
02daab21
AK		 5894 vcpu->fpu_active = 0;
5895 kvm_x86_ops->fpu_deactivate(vcpu);
5896 }
af585b92
GN		 5897 if (kvm_check_request(KVM_REQ_APF_HALT, vcpu)) {
5898 /* Page is swapped out. Do synthetic halt */
5899 vcpu->arch.apf.halted = true;
5900 r = 1;
5901 goto out;
5902 }
c9aaa895
GC		 5903 if (kvm_check_request(KVM_REQ_STEAL_UPDATE, vcpu))
5904 record_steal_time(vcpu);
7460fb4a
AK		 5905 if (kvm_check_request(KVM_REQ_NMI, vcpu))
5906 process_nmi(vcpu);
f5132b01
GN		 5907 if (kvm_check_request(KVM_REQ_PMU, vcpu))
5908 kvm_handle_pmu_event(vcpu);
5909 if (kvm_check_request(KVM_REQ_PMI, vcpu))
5910 kvm_deliver_pmi(vcpu);
3d81bc7e
YZ		 5911 if (kvm_check_request(KVM_REQ_SCAN_IOAPIC, vcpu))
5912 vcpu_scan_ioapic(vcpu);
2f52d58c 5913 }
b93463aa 5914
b463a6f7 5915 if (kvm_check_request(KVM_REQ_EVENT, vcpu) || req_int_win) {
66450a21
JK		 5916 kvm_apic_accept_events(vcpu);
5917 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
5918 r = 1;
5919 goto out;
5920 }
5921
b463a6f7
AK		 5922 inject_pending_event(vcpu);
5923
5924 /* enable NMI/IRQ window open exits if needed */
7460fb4a 5925 if (vcpu->arch.nmi_pending)
03b28f81
JK		 5926 req_immediate_exit =
5927 kvm_x86_ops->enable_nmi_window(vcpu) != 0;
c7c9c56c 5928 else if (kvm_cpu_has_injectable_intr(vcpu) || req_int_win)
730dca42
JK		 5929 req_immediate_exit =
5930 kvm_x86_ops->enable_irq_window(vcpu) != 0;
b463a6f7
AK		 5931
5932 if (kvm_lapic_enabled(vcpu)) {
c7c9c56c
YZ		 5933 /*
5934 * Update architecture specific hints for APIC
5935 * virtual interrupt delivery.
5936 */
5937 if (kvm_x86_ops->hwapic_irr_update)
5938 kvm_x86_ops->hwapic_irr_update(vcpu,
5939 kvm_lapic_find_highest_irr(vcpu));
b463a6f7
AK		 5940 update_cr8_intercept(vcpu);
5941 kvm_lapic_sync_to_vapic(vcpu);
5942 }
5943 }
5944
d8368af8
AK		 5945 r = kvm_mmu_reload(vcpu);
5946 if (unlikely(r)) {
d905c069 5947 goto cancel_injection;
d8368af8
AK		 5948 }
5949
b6c7a5dc
HB		 5950 preempt_disable();
5951
5952 kvm_x86_ops->prepare_guest_switch(vcpu);
2608d7a1
AK		 5953 if (vcpu->fpu_active)
5954 kvm_load_guest_fpu(vcpu);
2acf923e 5955 kvm_load_guest_xcr0(vcpu);
b6c7a5dc 5956
6b7e2d09
XG		 5957 vcpu->mode = IN_GUEST_MODE;
5958
5959 /* We should set ->mode before check ->requests,
5960 * see the comment in make_all_cpus_request.
5961 */
5962 smp_mb();
b6c7a5dc 5963
d94e1dc9 5964 local_irq_disable();
32f88400 5965
6b7e2d09 5966 if (vcpu->mode == EXITING_GUEST_MODE || vcpu->requests
d94e1dc9 5967 || need_resched() || signal_pending(current)) {
6b7e2d09 5968 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 5969 smp_wmb();
6c142801
AK		 5970 local_irq_enable();
5971 preempt_enable();
5972 r = 1;
d905c069 5973 goto cancel_injection;
6c142801
AK		 5974 }
5975
f656ce01 5976 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3200f405 5977
d6185f20
NHE		 5978 if (req_immediate_exit)
5979 smp_send_reschedule(vcpu->cpu);
5980
b6c7a5dc
HB		 5981 kvm_guest_enter();
5982
42dbaa5a 5983 if (unlikely(vcpu->arch.switch_db_regs)) {
42dbaa5a
JK		 5984 set_debugreg(0, 7);
5985 set_debugreg(vcpu->arch.eff_db[0], 0);
5986 set_debugreg(vcpu->arch.eff_db[1], 1);
5987 set_debugreg(vcpu->arch.eff_db[2], 2);
5988 set_debugreg(vcpu->arch.eff_db[3], 3);
5989 }
b6c7a5dc 5990
229456fc 5991 trace_kvm_entry(vcpu->vcpu_id);
851ba692 5992 kvm_x86_ops->run(vcpu);
b6c7a5dc 5993
24f1e32c
FW		 5994 /*
5995 * If the guest has used debug registers, at least dr7
5996 * will be disabled while returning to the host.
5997 * If we don't have active breakpoints in the host, we don't
5998 * care about the messed up debug address registers. But if
5999 * we have some of them active, restore the old state.
6000 */
59d8eb53 6001 if (hw_breakpoint_active())
24f1e32c 6002 hw_breakpoint_restore();
42dbaa5a 6003
886b470c
MT		 6004 vcpu->arch.last_guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu,
6005 native_read_tsc());
1d5f066e 6006
6b7e2d09 6007 vcpu->mode = OUTSIDE_GUEST_MODE;
d94e1dc9 6008 smp_wmb();
a547c6db
YZ		 6009
6010 /* Interrupt is enabled by handle_external_intr() */
6011 kvm_x86_ops->handle_external_intr(vcpu);
b6c7a5dc
HB		 6012
6013 ++vcpu->stat.exits;
6014
6015 /*
6016 * We must have an instruction between local_irq_enable() and
6017 * kvm_guest_exit(), so the timer interrupt isn't delayed by
6018 * the interrupt shadow. The stat.exits increment will do nicely.
6019 * But we need to prevent reordering, hence this barrier():
6020 */
6021 barrier();
6022
6023 kvm_guest_exit();
6024
6025 preempt_enable();
6026
f656ce01 6027 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3200f405 6028
b6c7a5dc
HB		 6029 /*
6030 * Profile KVM exit RIPs:
6031 */
6032 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 6033 unsigned long rip = kvm_rip_read(vcpu);
6034 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 6035 }
6036
cc578287
ZA		 6037 if (unlikely(vcpu->arch.tsc_always_catchup))
6038 kvm_make_request(KVM_REQ_CLOCK_UPDATE, vcpu);
298101da 6039
5cfb1d5a
MT		 6040 if (vcpu->arch.apic_attention)
6041 kvm_lapic_sync_from_vapic(vcpu);
b93463aa 6042
851ba692 6043 r = kvm_x86_ops->handle_exit(vcpu);
d905c069
MT		 6044 return r;
6045
6046cancel_injection:
6047 kvm_x86_ops->cancel_injection(vcpu);
ae7a2a3f
MT		 6048 if (unlikely(vcpu->arch.apic_attention))
6049 kvm_lapic_sync_from_vapic(vcpu);
d7690175
MT		 6050out:
6051 return r;
6052}
b6c7a5dc 6053
09cec754 6054
851ba692 6055static int __vcpu_run(struct kvm_vcpu *vcpu)
d7690175
MT		 6056{
6057 int r;
f656ce01 6058 struct kvm *kvm = vcpu->kvm;
d7690175 6059
f656ce01 6060 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
4484141a
XG		 6061 r = vapic_enter(vcpu);
6062 if (r) {
6063 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
6064 return r;
6065 }
d7690175
MT		 6066
6067 r = 1;
6068 while (r > 0) {
af585b92
GN		 6069 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
6070 !vcpu->arch.apf.halted)
851ba692 6071 r = vcpu_enter_guest(vcpu);
d7690175 6072 else {
f656ce01 6073 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
d7690175 6074 kvm_vcpu_block(vcpu);
f656ce01 6075 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
66450a21
JK		 6076 if (kvm_check_request(KVM_REQ_UNHALT, vcpu)) {
6077 kvm_apic_accept_events(vcpu);
09cec754
GN		 6078 switch(vcpu->arch.mp_state) {
6079 case KVM_MP_STATE_HALTED:
6aef266c 6080 vcpu->arch.pv.pv_unhalted = false;
d7690175 6081 vcpu->arch.mp_state =
09cec754
GN		 6082 KVM_MP_STATE_RUNNABLE;
6083 case KVM_MP_STATE_RUNNABLE:
af585b92 6084 vcpu->arch.apf.halted = false;
09cec754 6085 break;
66450a21
JK		 6086 case KVM_MP_STATE_INIT_RECEIVED:
6087 break;
09cec754
GN		 6088 default:
6089 r = -EINTR;
6090 break;
6091 }
6092 }
d7690175
MT		 6093 }
6094
09cec754
GN		 6095 if (r <= 0)
6096 break;
6097
6098 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
6099 if (kvm_cpu_has_pending_timer(vcpu))
6100 kvm_inject_pending_timer_irqs(vcpu);
6101
851ba692 6102 if (dm_request_for_irq_injection(vcpu)) {
09cec754 6103 r = -EINTR;
851ba692 6104 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6105 ++vcpu->stat.request_irq_exits;
6106 }
af585b92
GN		 6107
6108 kvm_check_async_pf_completion(vcpu);
6109
09cec754
GN		 6110 if (signal_pending(current)) {
6111 r = -EINTR;
851ba692 6112 vcpu->run->exit_reason = KVM_EXIT_INTR;
09cec754
GN		 6113 ++vcpu->stat.signal_exits;
6114 }
6115 if (need_resched()) {
f656ce01 6116 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
09cec754 6117 kvm_resched(vcpu);
f656ce01 6118 vcpu->srcu_idx = srcu_read_lock(&kvm->srcu);
d7690175 6119 }
b6c7a5dc
HB		 6120 }
6121
f656ce01 6122 srcu_read_unlock(&kvm->srcu, vcpu->srcu_idx);
b6c7a5dc 6123
b93463aa
AK		 6124 vapic_exit(vcpu);
6125
b6c7a5dc
HB		 6126 return r;
6127}
6128
716d51ab
GN		 6129static inline int complete_emulated_io(struct kvm_vcpu *vcpu)
6130{
6131 int r;
6132 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
6133 r = emulate_instruction(vcpu, EMULTYPE_NO_DECODE);
6134 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
6135 if (r != EMULATE_DONE)
6136 return 0;
6137 return 1;
6138}
6139
6140static int complete_emulated_pio(struct kvm_vcpu *vcpu)
6141{
6142 BUG_ON(!vcpu->arch.pio.count);
6143
6144 return complete_emulated_io(vcpu);
6145}
6146
f78146b0
AK		 6147/*
6148 * Implements the following, as a state machine:
6149 *
6150 * read:
6151 * for each fragment
87da7e66
XG		 6152 * for each mmio piece in the fragment
6153 * write gpa, len
6154 * exit
6155 * copy data
f78146b0
AK		 6156 * execute insn
6157 *
6158 * write:
6159 * for each fragment
87da7e66
XG		 6160 * for each mmio piece in the fragment
6161 * write gpa, len
6162 * copy data
6163 * exit
f78146b0 6164 */
716d51ab 6165static int complete_emulated_mmio(struct kvm_vcpu *vcpu)
5287f194
AK		 6166{
6167 struct kvm_run *run = vcpu->run;
f78146b0 6168 struct kvm_mmio_fragment *frag;
87da7e66 6169 unsigned len;
5287f194 6170
716d51ab 6171 BUG_ON(!vcpu->mmio_needed);
5287f194 6172
716d51ab 6173 /* Complete previous fragment */
87da7e66
XG		 6174 frag = &vcpu->mmio_fragments[vcpu->mmio_cur_fragment];
6175 len = min(8u, frag->len);
716d51ab 6176 if (!vcpu->mmio_is_write)
87da7e66
XG		 6177 memcpy(frag->data, run->mmio.data, len);
6178
6179 if (frag->len <= 8) {
6180 /* Switch to the next fragment. */
6181 frag++;
6182 vcpu->mmio_cur_fragment++;
6183 } else {
6184 /* Go forward to the next mmio piece. */
6185 frag->data += len;
6186 frag->gpa += len;
6187 frag->len -= len;
6188 }
6189
716d51ab
GN		 6190 if (vcpu->mmio_cur_fragment == vcpu->mmio_nr_fragments) {
6191 vcpu->mmio_needed = 0;
0912c977
PB		 6192
6193 /* FIXME: return into emulator if single-stepping. */
cef4dea0 6194 if (vcpu->mmio_is_write)
716d51ab
GN		 6195 return 1;
6196 vcpu->mmio_read_completed = 1;
6197 return complete_emulated_io(vcpu);
6198 }
87da7e66 6199
716d51ab
GN		 6200 run->exit_reason = KVM_EXIT_MMIO;
6201 run->mmio.phys_addr = frag->gpa;
6202 if (vcpu->mmio_is_write)
87da7e66
XG		 6203 memcpy(run->mmio.data, frag->data, min(8u, frag->len));
6204 run->mmio.len = min(8u, frag->len);
716d51ab
GN		 6205 run->mmio.is_write = vcpu->mmio_is_write;
6206 vcpu->arch.complete_userspace_io = complete_emulated_mmio;
6207 return 0;
5287f194
AK		 6208}
6209
716d51ab 6210
b6c7a5dc
HB		 6211int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
6212{
6213 int r;
6214 sigset_t sigsaved;
6215
e5c30142
AK		 6216 if (!tsk_used_math(current) && init_fpu(current))
6217 return -ENOMEM;
6218
ac9f6dc0
AK		 6219 if (vcpu->sigset_active)
6220 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
6221
a4535290 6222 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 6223 kvm_vcpu_block(vcpu);
66450a21 6224 kvm_apic_accept_events(vcpu);
d7690175 6225 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 6226 r = -EAGAIN;
6227 goto out;
b6c7a5dc
HB		 6228 }
6229
b6c7a5dc 6230 /* re-sync apic's tpr */
eea1cff9
AP		 6231 if (!irqchip_in_kernel(vcpu->kvm)) {
6232 if (kvm_set_cr8(vcpu, kvm_run->cr8) != 0) {
6233 r = -EINVAL;
6234 goto out;
6235 }
6236 }
b6c7a5dc 6237
716d51ab
GN		 6238 if (unlikely(vcpu->arch.complete_userspace_io)) {
6239 int (*cui)(struct kvm_vcpu *) = vcpu->arch.complete_userspace_io;
6240 vcpu->arch.complete_userspace_io = NULL;
6241 r = cui(vcpu);
6242 if (r <= 0)
6243 goto out;
6244 } else
6245 WARN_ON(vcpu->arch.pio.count || vcpu->mmio_needed);
5287f194 6246
851ba692 6247 r = __vcpu_run(vcpu);
b6c7a5dc
HB		 6248
6249out:
f1d86e46 6250 post_kvm_run_save(vcpu);
b6c7a5dc
HB		 6251 if (vcpu->sigset_active)
6252 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
6253
b6c7a5dc
HB		 6254 return r;
6255}
6256
6257int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6258{
7ae441ea
GN		 6259 if (vcpu->arch.emulate_regs_need_sync_to_vcpu) {
6260 /*
6261 * We are here if userspace calls get_regs() in the middle of
6262 * instruction emulation. Registers state needs to be copied
4a969980 6263 * back from emulation context to vcpu. Userspace shouldn't do
7ae441ea
GN		 6264 * that usually, but some bad designed PV devices (vmware
6265 * backdoor interface) need this to work
6266 */
dd856efa 6267 emulator_writeback_register_cache(&vcpu->arch.emulate_ctxt);
7ae441ea
GN		 6268 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6269 }
5fdbf976
MT		 6270 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
6271 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
6272 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
6273 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
6274 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
6275 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
6276 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6277 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 6278#ifdef CONFIG_X86_64
5fdbf976
MT		 6279 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
6280 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
6281 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
6282 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
6283 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
6284 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
6285 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
6286 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 6287#endif
6288
5fdbf976 6289 regs->rip = kvm_rip_read(vcpu);
91586a3b 6290 regs->rflags = kvm_get_rflags(vcpu);
b6c7a5dc 6291
b6c7a5dc
HB		 6292 return 0;
6293}
6294
6295int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
6296{
7ae441ea
GN		 6297 vcpu->arch.emulate_regs_need_sync_from_vcpu = true;
6298 vcpu->arch.emulate_regs_need_sync_to_vcpu = false;
6299
5fdbf976
MT		 6300 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
6301 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
6302 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
6303 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
6304 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
6305 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
6306 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
6307 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 6308#ifdef CONFIG_X86_64
5fdbf976
MT		 6309 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
6310 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
6311 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
6312 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
6313 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
6314 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
6315 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
6316 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
b6c7a5dc
HB		 6317#endif
6318
5fdbf976 6319 kvm_rip_write(vcpu, regs->rip);
91586a3b 6320 kvm_set_rflags(vcpu, regs->rflags);
b6c7a5dc 6321
b4f14abd
JK		 6322 vcpu->arch.exception.pending = false;
6323
3842d135
AK		 6324 kvm_make_request(KVM_REQ_EVENT, vcpu);
6325
b6c7a5dc
HB		 6326 return 0;
6327}
6328
b6c7a5dc
HB		 6329void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
6330{
6331 struct kvm_segment cs;
6332
3e6e0aab 6333 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 6334 *db = cs.db;
6335 *l = cs.l;
6336}
6337EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
6338
6339int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
6340 struct kvm_sregs *sregs)
6341{
89a27f4d 6342 struct desc_ptr dt;
b6c7a5dc 6343
3e6e0aab
GT		 6344 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6345 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6346 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6347 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6348 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6349 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6350
3e6e0aab
GT		 6351 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6352 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 6353
6354 kvm_x86_ops->get_idt(vcpu, &dt);
89a27f4d
GN		 6355 sregs->idt.limit = dt.size;
6356 sregs->idt.base = dt.address;
b6c7a5dc 6357 kvm_x86_ops->get_gdt(vcpu, &dt);
89a27f4d
GN		 6358 sregs->gdt.limit = dt.size;
6359 sregs->gdt.base = dt.address;
b6c7a5dc 6360
4d4ec087 6361 sregs->cr0 = kvm_read_cr0(vcpu);
ad312c7c 6362 sregs->cr2 = vcpu->arch.cr2;
9f8fe504 6363 sregs->cr3 = kvm_read_cr3(vcpu);
fc78f519 6364 sregs->cr4 = kvm_read_cr4(vcpu);
2d3ad1f4 6365 sregs->cr8 = kvm_get_cr8(vcpu);
f6801dff 6366 sregs->efer = vcpu->arch.efer;
b6c7a5dc
HB		 6367 sregs->apic_base = kvm_get_apic_base(vcpu);
6368
923c61bb 6369 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 6370
36752c9b 6371 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 6372 set_bit(vcpu->arch.interrupt.nr,
6373 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 6374
b6c7a5dc
HB		 6375 return 0;
6376}
6377
62d9f0db
MT		 6378int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
6379 struct kvm_mp_state *mp_state)
6380{
66450a21 6381 kvm_apic_accept_events(vcpu);
6aef266c
SV		 6382 if (vcpu->arch.mp_state == KVM_MP_STATE_HALTED &&
6383 vcpu->arch.pv.pv_unhalted)
6384 mp_state->mp_state = KVM_MP_STATE_RUNNABLE;
6385 else
6386 mp_state->mp_state = vcpu->arch.mp_state;
6387
62d9f0db
MT		 6388 return 0;
6389}
6390
6391int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
6392 struct kvm_mp_state *mp_state)
6393{
66450a21
JK		 6394 if (!kvm_vcpu_has_lapic(vcpu) &&
6395 mp_state->mp_state != KVM_MP_STATE_RUNNABLE)
6396 return -EINVAL;
6397
6398 if (mp_state->mp_state == KVM_MP_STATE_SIPI_RECEIVED) {
6399 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
6400 set_bit(KVM_APIC_SIPI, &vcpu->arch.apic->pending_events);
6401 } else
6402 vcpu->arch.mp_state = mp_state->mp_state;
3842d135 6403 kvm_make_request(KVM_REQ_EVENT, vcpu);
62d9f0db
MT		 6404 return 0;
6405}
6406
7f3d35fd
KW		 6407int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int idt_index,
6408 int reason, bool has_error_code, u32 error_code)
b6c7a5dc 6409{
9d74191a 6410 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
8ec4722d 6411 int ret;
e01c2426 6412
8ec4722d 6413 init_emulate_ctxt(vcpu);
c697518a 6414
7f3d35fd 6415 ret = emulator_task_switch(ctxt, tss_selector, idt_index, reason,
9d74191a 6416 has_error_code, error_code);
c697518a 6417
c697518a 6418 if (ret)
19d04437 6419 return EMULATE_FAIL;
37817f29 6420
9d74191a
TY		 6421 kvm_rip_write(vcpu, ctxt->eip);
6422 kvm_set_rflags(vcpu, ctxt->eflags);
3842d135 6423 kvm_make_request(KVM_REQ_EVENT, vcpu);
19d04437 6424 return EMULATE_DONE;
37817f29
IE		 6425}
6426EXPORT_SYMBOL_GPL(kvm_task_switch);
6427
b6c7a5dc
HB		 6428int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
6429 struct kvm_sregs *sregs)
6430{
6431 int mmu_reset_needed = 0;
63f42e02 6432 int pending_vec, max_bits, idx;
89a27f4d 6433 struct desc_ptr dt;
b6c7a5dc 6434
6d1068b3
PM		 6435 if (!guest_cpuid_has_xsave(vcpu) && (sregs->cr4 & X86_CR4_OSXSAVE))
6436 return -EINVAL;
6437
89a27f4d
GN		 6438 dt.size = sregs->idt.limit;
6439 dt.address = sregs->idt.base;
b6c7a5dc 6440 kvm_x86_ops->set_idt(vcpu, &dt);
89a27f4d
GN		 6441 dt.size = sregs->gdt.limit;
6442 dt.address = sregs->gdt.base;
b6c7a5dc
HB		 6443 kvm_x86_ops->set_gdt(vcpu, &dt);
6444
ad312c7c 6445 vcpu->arch.cr2 = sregs->cr2;
9f8fe504 6446 mmu_reset_needed |= kvm_read_cr3(vcpu) != sregs->cr3;
dc7e795e 6447 vcpu->arch.cr3 = sregs->cr3;
aff48baa 6448 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
b6c7a5dc 6449
2d3ad1f4 6450 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 6451
f6801dff 6452 mmu_reset_needed |= vcpu->arch.efer != sregs->efer;
b6c7a5dc 6453 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 6454 kvm_set_apic_base(vcpu, sregs->apic_base);
6455
4d4ec087 6456 mmu_reset_needed |= kvm_read_cr0(vcpu) != sregs->cr0;
b6c7a5dc 6457 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 6458 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 6459
fc78f519 6460 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
b6c7a5dc 6461 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
3ea3aa8c 6462 if (sregs->cr4 & X86_CR4_OSXSAVE)
00b27a3e 6463 kvm_update_cpuid(vcpu);
63f42e02
XG		 6464
6465 idx = srcu_read_lock(&vcpu->kvm->srcu);
7c93be44 6466 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
9f8fe504 6467 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
7c93be44
MT		 6468 mmu_reset_needed = 1;
6469 }
63f42e02 6470 srcu_read_unlock(&vcpu->kvm->srcu, idx);
b6c7a5dc
HB		 6471
6472 if (mmu_reset_needed)
6473 kvm_mmu_reset_context(vcpu);
6474
a50abc3b 6475 max_bits = KVM_NR_INTERRUPTS;
923c61bb
GN		 6476 pending_vec = find_first_bit(
6477 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
6478 if (pending_vec < max_bits) {
66fd3f7f 6479 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb 6480 pr_debug("Set back pending irq %d\n", pending_vec);
b6c7a5dc
HB		 6481 }
6482
3e6e0aab
GT		 6483 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
6484 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
6485 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
6486 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
6487 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
6488 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 6489
3e6e0aab
GT		 6490 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
6491 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 6492
5f0269f5
ME		 6493 update_cr8_intercept(vcpu);
6494
9c3e4aab 6495 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 6496 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab 6497 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
3eeb3288 6498 !is_protmode(vcpu))
9c3e4aab
MT		 6499 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
6500
3842d135
AK		 6501 kvm_make_request(KVM_REQ_EVENT, vcpu);
6502
b6c7a5dc
HB		 6503 return 0;
6504}
6505
d0bfb940
JK		 6506int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
6507 struct kvm_guest_debug *dbg)
b6c7a5dc 6508{
355be0b9 6509 unsigned long rflags;
ae675ef0 6510 int i, r;
b6c7a5dc 6511
4f926bf2
JK		 6512 if (dbg->control & (KVM_GUESTDBG_INJECT_DB | KVM_GUESTDBG_INJECT_BP)) {
6513 r = -EBUSY;
6514 if (vcpu->arch.exception.pending)
2122ff5e 6515 goto out;
4f926bf2
JK		 6516 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
6517 kvm_queue_exception(vcpu, DB_VECTOR);
6518 else
6519 kvm_queue_exception(vcpu, BP_VECTOR);
6520 }
6521
91586a3b
JK		 6522 /*
6523 * Read rflags as long as potentially injected trace flags are still
6524 * filtered out.
6525 */
6526 rflags = kvm_get_rflags(vcpu);
355be0b9
JK		 6527
6528 vcpu->guest_debug = dbg->control;
6529 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
6530 vcpu->guest_debug = 0;
6531
6532 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
ae675ef0
JK		 6533 for (i = 0; i < KVM_NR_DB_REGS; ++i)
6534 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
c8639010 6535 vcpu->arch.guest_debug_dr7 = dbg->arch.debugreg[7];
ae675ef0
JK		 6536 } else {
6537 for (i = 0; i < KVM_NR_DB_REGS; i++)
6538 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
ae675ef0 6539 }
c8639010 6540 kvm_update_dr7(vcpu);
ae675ef0 6541
f92653ee
JK		 6542 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6543 vcpu->arch.singlestep_rip = kvm_rip_read(vcpu) +
6544 get_segment_base(vcpu, VCPU_SREG_CS);
94fe45da 6545
91586a3b
JK		 6546 /*
6547 * Trigger an rflags update that will inject or remove the trace
6548 * flags.
6549 */
6550 kvm_set_rflags(vcpu, rflags);
b6c7a5dc 6551
c8639010 6552 kvm_x86_ops->update_db_bp_intercept(vcpu);
b6c7a5dc 6553
4f926bf2 6554 r = 0;
d0bfb940 6555
2122ff5e 6556out:
b6c7a5dc
HB		 6557
6558 return r;
6559}
6560
8b006791
ZX		 6561/*
6562 * Translate a guest virtual address to a guest physical address.
6563 */
6564int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
6565 struct kvm_translation *tr)
6566{
6567 unsigned long vaddr = tr->linear_address;
6568 gpa_t gpa;
f656ce01 6569 int idx;
8b006791 6570
f656ce01 6571 idx = srcu_read_lock(&vcpu->kvm->srcu);
1871c602 6572 gpa = kvm_mmu_gva_to_gpa_system(vcpu, vaddr, NULL);
f656ce01 6573 srcu_read_unlock(&vcpu->kvm->srcu, idx);
8b006791
ZX		 6574 tr->physical_address = gpa;
6575 tr->valid = gpa != UNMAPPED_GVA;
6576 tr->writeable = 1;
6577 tr->usermode = 0;
8b006791
ZX		 6578
6579 return 0;
6580}
6581
d0752060
HB		 6582int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6583{
98918833
SY		 6584 struct i387_fxsave_struct *fxsave =
6585 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6586
d0752060
HB		 6587 memcpy(fpu->fpr, fxsave->st_space, 128);
6588 fpu->fcw = fxsave->cwd;
6589 fpu->fsw = fxsave->swd;
6590 fpu->ftwx = fxsave->twd;
6591 fpu->last_opcode = fxsave->fop;
6592 fpu->last_ip = fxsave->rip;
6593 fpu->last_dp = fxsave->rdp;
6594 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
6595
d0752060
HB		 6596 return 0;
6597}
6598
6599int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
6600{
98918833
SY		 6601 struct i387_fxsave_struct *fxsave =
6602 &vcpu->arch.guest_fpu.state->fxsave;
d0752060 6603
d0752060
HB		 6604 memcpy(fxsave->st_space, fpu->fpr, 128);
6605 fxsave->cwd = fpu->fcw;
6606 fxsave->swd = fpu->fsw;
6607 fxsave->twd = fpu->ftwx;
6608 fxsave->fop = fpu->last_opcode;
6609 fxsave->rip = fpu->last_ip;
6610 fxsave->rdp = fpu->last_dp;
6611 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
6612
d0752060
HB		 6613 return 0;
6614}
6615
10ab25cd 6616int fx_init(struct kvm_vcpu *vcpu)
d0752060 6617{
10ab25cd
JK		 6618 int err;
6619
6620 err = fpu_alloc(&vcpu->arch.guest_fpu);
6621 if (err)
6622 return err;
6623
98918833 6624 fpu_finit(&vcpu->arch.guest_fpu);
d0752060 6625
2acf923e
DC		 6626 /*
6627 * Ensure guest xcr0 is valid for loading
6628 */
6629 vcpu->arch.xcr0 = XSTATE_FP;
6630
ad312c7c 6631 vcpu->arch.cr0 |= X86_CR0_ET;
10ab25cd
JK		 6632
6633 return 0;
d0752060
HB		 6634}
6635EXPORT_SYMBOL_GPL(fx_init);
6636
98918833
SY		 6637static void fx_free(struct kvm_vcpu *vcpu)
6638{
6639 fpu_free(&vcpu->arch.guest_fpu);
6640}
6641
d0752060
HB		 6642void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
6643{
2608d7a1 6644 if (vcpu->guest_fpu_loaded)
d0752060
HB		 6645 return;
6646
2acf923e
DC		 6647 /*
6648 * Restore all possible states in the guest,
6649 * and assume host would use all available bits.
6650 * Guest xcr0 would be loaded later.
6651 */
6652 kvm_put_guest_xcr0(vcpu);
d0752060 6653 vcpu->guest_fpu_loaded = 1;
b1a74bf8 6654 __kernel_fpu_begin();
98918833 6655 fpu_restore_checking(&vcpu->arch.guest_fpu);
0c04851c 6656 trace_kvm_fpu(1);
d0752060 6657}
d0752060
HB		 6658
6659void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
6660{
2acf923e
DC		 6661 kvm_put_guest_xcr0(vcpu);
6662
d0752060
HB		 6663 if (!vcpu->guest_fpu_loaded)
6664 return;
6665
6666 vcpu->guest_fpu_loaded = 0;
98918833 6667 fpu_save_init(&vcpu->arch.guest_fpu);
b1a74bf8 6668 __kernel_fpu_end();
f096ed85 6669 ++vcpu->stat.fpu_reload;
a8eeb04a 6670 kvm_make_request(KVM_REQ_DEACTIVATE_FPU, vcpu);
0c04851c 6671 trace_kvm_fpu(0);
d0752060 6672}
e9b11c17
ZX		 6673
6674void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
6675{
12f9a48f 6676 kvmclock_reset(vcpu);
7f1ea208 6677
f5f48ee1 6678 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
98918833 6679 fx_free(vcpu);
e9b11c17
ZX		 6680 kvm_x86_ops->vcpu_free(vcpu);
6681}
6682
6683struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
6684 unsigned int id)
6685{
6755bae8
ZA		 6686 if (check_tsc_unstable() && atomic_read(&kvm->online_vcpus) != 0)
6687 printk_once(KERN_WARNING
6688 "kvm: SMP vm created on host with unstable TSC; "
6689 "guest TSC will not be reliable\n");
26e5215f
AK		 6690 return kvm_x86_ops->vcpu_create(kvm, id);
6691}
e9b11c17 6692
26e5215f
AK		 6693int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
6694{
6695 int r;
e9b11c17 6696
0bed3b56 6697 vcpu->arch.mtrr_state.have_fixed = 1;
9fc77441
MT		 6698 r = vcpu_load(vcpu);
6699 if (r)
6700 return r;
57f252f2 6701 kvm_vcpu_reset(vcpu);
8a3c1a33 6702 kvm_mmu_setup(vcpu);
e9b11c17 6703 vcpu_put(vcpu);
e9b11c17 6704
26e5215f 6705 return r;
e9b11c17
ZX		 6706}
6707
42897d86
MT		 6708int kvm_arch_vcpu_postcreate(struct kvm_vcpu *vcpu)
6709{
6710 int r;
8fe8ab46 6711 struct msr_data msr;
42897d86
MT		 6712
6713 r = vcpu_load(vcpu);
6714 if (r)
6715 return r;
8fe8ab46
WA		 6716 msr.data = 0x0;
6717 msr.index = MSR_IA32_TSC;
6718 msr.host_initiated = true;
6719 kvm_write_tsc(vcpu, &msr);
42897d86
MT		 6720 vcpu_put(vcpu);
6721
6722 return r;
6723}
6724
d40ccc62 6725void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17 6726{
9fc77441 6727 int r;
344d9588
GN		 6728 vcpu->arch.apf.msr_val = 0;
6729
9fc77441
MT		 6730 r = vcpu_load(vcpu);
6731 BUG_ON(r);
e9b11c17
ZX		 6732 kvm_mmu_unload(vcpu);
6733 vcpu_put(vcpu);
6734
98918833 6735 fx_free(vcpu);
e9b11c17
ZX		 6736 kvm_x86_ops->vcpu_free(vcpu);
6737}
6738
66450a21 6739void kvm_vcpu_reset(struct kvm_vcpu *vcpu)
e9b11c17 6740{
7460fb4a
AK		 6741 atomic_set(&vcpu->arch.nmi_queued, 0);
6742 vcpu->arch.nmi_pending = 0;
448fa4a9
JK		 6743 vcpu->arch.nmi_injected = false;
6744
42dbaa5a
JK		 6745 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
6746 vcpu->arch.dr6 = DR6_FIXED_1;
6747 vcpu->arch.dr7 = DR7_FIXED_1;
c8639010 6748 kvm_update_dr7(vcpu);
42dbaa5a 6749
3842d135 6750 kvm_make_request(KVM_REQ_EVENT, vcpu);
344d9588 6751 vcpu->arch.apf.msr_val = 0;
c9aaa895 6752 vcpu->arch.st.msr_val = 0;
3842d135 6753
12f9a48f
GC		 6754 kvmclock_reset(vcpu);
6755
af585b92
GN		 6756 kvm_clear_async_pf_completion_queue(vcpu);
6757 kvm_async_pf_hash_reset(vcpu);
6758 vcpu->arch.apf.halted = false;
3842d135 6759
f5132b01
GN		 6760 kvm_pmu_reset(vcpu);
6761
66f7b72e
JS		 6762 memset(vcpu->arch.regs, 0, sizeof(vcpu->arch.regs));
6763 vcpu->arch.regs_avail = ~0;
6764 vcpu->arch.regs_dirty = ~0;
6765
57f252f2 6766 kvm_x86_ops->vcpu_reset(vcpu);
e9b11c17
ZX		 6767}
6768
66450a21
JK		 6769void kvm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, unsigned int vector)
6770{
6771 struct kvm_segment cs;
6772
6773 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
6774 cs.selector = vector << 8;
6775 cs.base = vector << 12;
6776 kvm_set_segment(vcpu, &cs, VCPU_SREG_CS);
6777 kvm_rip_write(vcpu, 0);
e9b11c17
ZX		 6778}
6779
10474ae8 6780int kvm_arch_hardware_enable(void *garbage)
e9b11c17 6781{
ca84d1a2
ZA		 6782 struct kvm *kvm;
6783 struct kvm_vcpu *vcpu;
6784 int i;
0dd6a6ed
ZA		 6785 int ret;
6786 u64 local_tsc;
6787 u64 max_tsc = 0;
6788 bool stable, backwards_tsc = false;
18863bdd
AK		 6789
6790 kvm_shared_msr_cpu_online();
0dd6a6ed
ZA		 6791 ret = kvm_x86_ops->hardware_enable(garbage);
6792 if (ret != 0)
6793 return ret;
6794
6795 local_tsc = native_read_tsc();
6796 stable = !check_tsc_unstable();
6797 list_for_each_entry(kvm, &vm_list, vm_list) {
6798 kvm_for_each_vcpu(i, vcpu, kvm) {
6799 if (!stable && vcpu->cpu == smp_processor_id())
6800 set_bit(KVM_REQ_CLOCK_UPDATE, &vcpu->requests);
6801 if (stable && vcpu->arch.last_host_tsc > local_tsc) {
6802 backwards_tsc = true;
6803 if (vcpu->arch.last_host_tsc > max_tsc)
6804 max_tsc = vcpu->arch.last_host_tsc;
6805 }
6806 }
6807 }
6808
6809 /*
6810 * Sometimes, even reliable TSCs go backwards. This happens on
6811 * platforms that reset TSC during suspend or hibernate actions, but
6812 * maintain synchronization. We must compensate. Fortunately, we can
6813 * detect that condition here, which happens early in CPU bringup,
6814 * before any KVM threads can be running. Unfortunately, we can't
6815 * bring the TSCs fully up to date with real time, as we aren't yet far
6816 * enough into CPU bringup that we know how much real time has actually
6817 * elapsed; our helper function, get_kernel_ns() will be using boot
6818 * variables that haven't been updated yet.
6819 *
6820 * So we simply find the maximum observed TSC above, then record the
6821 * adjustment to TSC in each VCPU. When the VCPU later gets loaded,
6822 * the adjustment will be applied. Note that we accumulate
6823 * adjustments, in case multiple suspend cycles happen before some VCPU
6824 * gets a chance to run again. In the event that no KVM threads get a
6825 * chance to run, we will miss the entire elapsed period, as we'll have
6826 * reset last_host_tsc, so VCPUs will not have the TSC adjusted and may
6827 * loose cycle time. This isn't too big a deal, since the loss will be
6828 * uniform across all VCPUs (not to mention the scenario is extremely
6829 * unlikely). It is possible that a second hibernate recovery happens
6830 * much faster than a first, causing the observed TSC here to be
6831 * smaller; this would require additional padding adjustment, which is
6832 * why we set last_host_tsc to the local tsc observed here.
6833 *
6834 * N.B. - this code below runs only on platforms with reliable TSC,
6835 * as that is the only way backwards_tsc is set above. Also note
6836 * that this runs for ALL vcpus, which is not a bug; all VCPUs should
6837 * have the same delta_cyc adjustment applied if backwards_tsc
6838 * is detected. Note further, this adjustment is only done once,
6839 * as we reset last_host_tsc on all VCPUs to stop this from being
6840 * called multiple times (one for each physical CPU bringup).
6841 *
4a969980 6842 * Platforms with unreliable TSCs don't have to deal with this, they
0dd6a6ed
ZA		 6843 * will be compensated by the logic in vcpu_load, which sets the TSC to
6844 * catchup mode. This will catchup all VCPUs to real time, but cannot
6845 * guarantee that they stay in perfect synchronization.
6846 */
6847 if (backwards_tsc) {
6848 u64 delta_cyc = max_tsc - local_tsc;
6849 list_for_each_entry(kvm, &vm_list, vm_list) {
6850 kvm_for_each_vcpu(i, vcpu, kvm) {
6851 vcpu->arch.tsc_offset_adjustment += delta_cyc;
6852 vcpu->arch.last_host_tsc = local_tsc;
d828199e
MT		 6853 set_bit(KVM_REQ_MASTERCLOCK_UPDATE,
6854 &vcpu->requests);
0dd6a6ed
ZA		 6855 }
6856
6857 /*
6858 * We have to disable TSC offset matching.. if you were
6859 * booting a VM while issuing an S4 host suspend....
6860 * you may have some problem. Solving this issue is
6861 * left as an exercise to the reader.
6862 */
6863 kvm->arch.last_tsc_nsec = 0;
6864 kvm->arch.last_tsc_write = 0;
6865 }
6866
6867 }
6868 return 0;
e9b11c17
ZX		 6869}
6870
6871void kvm_arch_hardware_disable(void *garbage)
6872{
6873 kvm_x86_ops->hardware_disable(garbage);
3548bab5 6874 drop_user_return_notifiers(garbage);
e9b11c17
ZX		 6875}
6876
6877int kvm_arch_hardware_setup(void)
6878{
6879 return kvm_x86_ops->hardware_setup();
6880}
6881
6882void kvm_arch_hardware_unsetup(void)
6883{
6884 kvm_x86_ops->hardware_unsetup();
6885}
6886
6887void kvm_arch_check_processor_compat(void *rtn)
6888{
6889 kvm_x86_ops->check_processor_compatibility(rtn);
6890}
6891
3e515705
AK		 6892bool kvm_vcpu_compatible(struct kvm_vcpu *vcpu)
6893{
6894 return irqchip_in_kernel(vcpu->kvm) == (vcpu->arch.apic != NULL);
6895}
6896
54e9818f
GN		 6897struct static_key kvm_no_apic_vcpu __read_mostly;
6898
e9b11c17
ZX		 6899int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
6900{
6901 struct page *page;
6902 struct kvm *kvm;
6903 int r;
6904
6905 BUG_ON(vcpu->kvm == NULL);
6906 kvm = vcpu->kvm;
6907
6aef266c 6908 vcpu->arch.pv.pv_unhalted = false;
9aabc88f 6909 vcpu->arch.emulate_ctxt.ops = &emulate_ops;
c5af89b6 6910 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 6911 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 6912 else
a4535290 6913 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 6914
6915 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
6916 if (!page) {
6917 r = -ENOMEM;
6918 goto fail;
6919 }
ad312c7c 6920 vcpu->arch.pio_data = page_address(page);
e9b11c17 6921
cc578287 6922 kvm_set_tsc_khz(vcpu, max_tsc_khz);
c285545f 6923
e9b11c17
ZX		 6924 r = kvm_mmu_create(vcpu);
6925 if (r < 0)
6926 goto fail_free_pio_data;
6927
6928 if (irqchip_in_kernel(kvm)) {
6929 r = kvm_create_lapic(vcpu);
6930 if (r < 0)
6931 goto fail_mmu_destroy;
54e9818f
GN		 6932 } else
6933 static_key_slow_inc(&kvm_no_apic_vcpu);
e9b11c17 6934
890ca9ae
HY		 6935 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
6936 GFP_KERNEL);
6937 if (!vcpu->arch.mce_banks) {
6938 r = -ENOMEM;
443c39bc 6939 goto fail_free_lapic;
890ca9ae
HY		 6940 }
6941 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
6942
f1797359
WY		 6943 if (!zalloc_cpumask_var(&vcpu->arch.wbinvd_dirty_mask, GFP_KERNEL)) {
6944 r = -ENOMEM;
f5f48ee1 6945 goto fail_free_mce_banks;
f1797359 6946 }
f5f48ee1 6947
66f7b72e
JS		 6948 r = fx_init(vcpu);
6949 if (r)
6950 goto fail_free_wbinvd_dirty_mask;
6951
ba904635 6952 vcpu->arch.ia32_tsc_adjust_msr = 0x0;
0b79459b 6953 vcpu->arch.pv_time_enabled = false;
d7876f1b
PB		 6954
6955 vcpu->arch.guest_supported_xcr0 = 0;
4344ee98 6956 vcpu->arch.guest_xstate_size = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET;
d7876f1b 6957
af585b92 6958 kvm_async_pf_hash_reset(vcpu);
f5132b01 6959 kvm_pmu_init(vcpu);
af585b92 6960
e9b11c17 6961 return 0;
66f7b72e
JS		 6962fail_free_wbinvd_dirty_mask:
6963 free_cpumask_var(vcpu->arch.wbinvd_dirty_mask);
f5f48ee1
SY		 6964fail_free_mce_banks:
6965 kfree(vcpu->arch.mce_banks);
443c39bc
WY		 6966fail_free_lapic:
6967 kvm_free_lapic(vcpu);
e9b11c17
ZX		 6968fail_mmu_destroy:
6969 kvm_mmu_destroy(vcpu);
6970fail_free_pio_data:
ad312c7c 6971 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 6972fail:
6973 return r;
6974}
6975
6976void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
6977{
f656ce01
MT		 6978 int idx;
6979
f5132b01 6980 kvm_pmu_destroy(vcpu);
36cb93fd 6981 kfree(vcpu->arch.mce_banks);
e9b11c17 6982 kvm_free_lapic(vcpu);
f656ce01 6983 idx = srcu_read_lock(&vcpu->kvm->srcu);
e9b11c17 6984 kvm_mmu_destroy(vcpu);
f656ce01 6985 srcu_read_unlock(&vcpu->kvm->srcu, idx);
ad312c7c 6986 free_page((unsigned long)vcpu->arch.pio_data);
54e9818f
GN		 6987 if (!irqchip_in_kernel(vcpu->kvm))
6988 static_key_slow_dec(&kvm_no_apic_vcpu);
e9b11c17 6989}
d19a9cd2 6990
e08b9637 6991int kvm_arch_init_vm(struct kvm *kvm, unsigned long type)
d19a9cd2 6992{
e08b9637
CO		 6993 if (type)
6994 return -EINVAL;
6995
f05e70ac 6996 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
365c8868 6997 INIT_LIST_HEAD(&kvm->arch.zapped_obsolete_pages);
4d5c5d0f 6998 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 6999
5550af4d
SY		 7000 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
7001 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
7a84428a
AW		 7002 /* Reserve bit 1 of irq_sources_bitmap for irqfd-resampler */
7003 set_bit(KVM_IRQFD_RESAMPLE_IRQ_SOURCE_ID,
7004 &kvm->arch.irq_sources_bitmap);
5550af4d 7005
038f8c11 7006 raw_spin_lock_init(&kvm->arch.tsc_write_lock);
1e08ec4a 7007 mutex_init(&kvm->arch.apic_map_lock);
d828199e
MT		 7008 spin_lock_init(&kvm->arch.pvclock_gtod_sync_lock);
7009
7010 pvclock_update_vm_gtod_copy(kvm);
53f658b3 7011
d89f5eff 7012 return 0;
d19a9cd2
ZX		 7013}
7014
7015static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
7016{
9fc77441
MT		 7017 int r;
7018 r = vcpu_load(vcpu);
7019 BUG_ON(r);
d19a9cd2
ZX		 7020 kvm_mmu_unload(vcpu);
7021 vcpu_put(vcpu);
7022}
7023
7024static void kvm_free_vcpus(struct kvm *kvm)
7025{
7026 unsigned int i;
988a2cae 7027 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 7028
7029 /*
7030 * Unpin any mmu pages first.
7031 */
af585b92
GN		 7032 kvm_for_each_vcpu(i, vcpu, kvm) {
7033 kvm_clear_async_pf_completion_queue(vcpu);
988a2cae 7034 kvm_unload_vcpu_mmu(vcpu);
af585b92 7035 }
988a2cae
GN		 7036 kvm_for_each_vcpu(i, vcpu, kvm)
7037 kvm_arch_vcpu_free(vcpu);
7038
7039 mutex_lock(&kvm->lock);
7040 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
7041 kvm->vcpus[i] = NULL;
d19a9cd2 7042
988a2cae
GN		 7043 atomic_set(&kvm->online_vcpus, 0);
7044 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 7045}
7046
ad8ba2cd
SY		 7047void kvm_arch_sync_events(struct kvm *kvm)
7048{
ba4cef31 7049 kvm_free_all_assigned_devices(kvm);
aea924f6 7050 kvm_free_pit(kvm);
ad8ba2cd
SY		 7051}
7052
d19a9cd2
ZX		 7053void kvm_arch_destroy_vm(struct kvm *kvm)
7054{
27469d29
AH		 7055 if (current->mm == kvm->mm) {
7056 /*
7057 * Free memory regions allocated on behalf of userspace,
7058 * unless the the memory map has changed due to process exit
7059 * or fd copying.
7060 */
7061 struct kvm_userspace_memory_region mem;
7062 memset(&mem, 0, sizeof(mem));
7063 mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
7064 kvm_set_memory_region(kvm, &mem);
7065
7066 mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
7067 kvm_set_memory_region(kvm, &mem);
7068
7069 mem.slot = TSS_PRIVATE_MEMSLOT;
7070 kvm_set_memory_region(kvm, &mem);
7071 }
6eb55818 7072 kvm_iommu_unmap_guest(kvm);
d7deeeb0
ZX		 7073 kfree(kvm->arch.vpic);
7074 kfree(kvm->arch.vioapic);
d19a9cd2 7075 kvm_free_vcpus(kvm);
3d45830c
AK		 7076 if (kvm->arch.apic_access_page)
7077 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 7078 if (kvm->arch.ept_identity_pagetable)
7079 put_page(kvm->arch.ept_identity_pagetable);
1e08ec4a 7080 kfree(rcu_dereference_check(kvm->arch.apic_map, 1));
d19a9cd2 7081}
0de10343 7082
db3fe4eb
TY		 7083void kvm_arch_free_memslot(struct kvm_memory_slot *free,
7084 struct kvm_memory_slot *dont)
7085{
7086 int i;
7087
d89cc617
TY		 7088 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7089 if (!dont || free->arch.rmap[i] != dont->arch.rmap[i]) {
7090 kvm_kvfree(free->arch.rmap[i]);
7091 free->arch.rmap[i] = NULL;
77d11309 7092 }
d89cc617
TY		 7093 if (i == 0)
7094 continue;
7095
7096 if (!dont || free->arch.lpage_info[i - 1] !=
7097 dont->arch.lpage_info[i - 1]) {
7098 kvm_kvfree(free->arch.lpage_info[i - 1]);
7099 free->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7100 }
7101 }
7102}
7103
7104int kvm_arch_create_memslot(struct kvm_memory_slot *slot, unsigned long npages)
7105{
7106 int i;
7107
d89cc617 7108 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
db3fe4eb
TY		 7109 unsigned long ugfn;
7110 int lpages;
d89cc617 7111 int level = i + 1;
db3fe4eb
TY		 7112
7113 lpages = gfn_to_index(slot->base_gfn + npages - 1,
7114 slot->base_gfn, level) + 1;
7115
d89cc617
TY		 7116 slot->arch.rmap[i] =
7117 kvm_kvzalloc(lpages * sizeof(*slot->arch.rmap[i]));
7118 if (!slot->arch.rmap[i])
77d11309 7119 goto out_free;
d89cc617
TY		 7120 if (i == 0)
7121 continue;
77d11309 7122
d89cc617
TY		 7123 slot->arch.lpage_info[i - 1] = kvm_kvzalloc(lpages *
7124 sizeof(*slot->arch.lpage_info[i - 1]));
7125 if (!slot->arch.lpage_info[i - 1])
db3fe4eb
TY		 7126 goto out_free;
7127
7128 if (slot->base_gfn & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7129 slot->arch.lpage_info[i - 1][0].write_count = 1;
db3fe4eb 7130 if ((slot->base_gfn + npages) & (KVM_PAGES_PER_HPAGE(level) - 1))
d89cc617 7131 slot->arch.lpage_info[i - 1][lpages - 1].write_count = 1;
db3fe4eb
TY		 7132 ugfn = slot->userspace_addr >> PAGE_SHIFT;
7133 /*
7134 * If the gfn and userspace address are not aligned wrt each
7135 * other, or if explicitly asked to, disable large page
7136 * support for this slot
7137 */
7138 if ((slot->base_gfn ^ ugfn) & (KVM_PAGES_PER_HPAGE(level) - 1) ||
7139 !kvm_largepages_enabled()) {
7140 unsigned long j;
7141
7142 for (j = 0; j < lpages; ++j)
d89cc617 7143 slot->arch.lpage_info[i - 1][j].write_count = 1;
db3fe4eb
TY		 7144 }
7145 }
7146
7147 return 0;
7148
7149out_free:
d89cc617
TY		 7150 for (i = 0; i < KVM_NR_PAGE_SIZES; ++i) {
7151 kvm_kvfree(slot->arch.rmap[i]);
7152 slot->arch.rmap[i] = NULL;
7153 if (i == 0)
7154 continue;
7155
7156 kvm_kvfree(slot->arch.lpage_info[i - 1]);
7157 slot->arch.lpage_info[i - 1] = NULL;
db3fe4eb
TY		 7158 }
7159 return -ENOMEM;
7160}
7161
e59dbe09
TY		 7162void kvm_arch_memslots_updated(struct kvm *kvm)
7163{
e6dff7d1
TY		 7164 /*
7165 * memslots->generation has been incremented.
7166 * mmio generation may have reached its maximum value.
7167 */
7168 kvm_mmu_invalidate_mmio_sptes(kvm);
e59dbe09
TY		 7169}
7170
f7784b8e
MT		 7171int kvm_arch_prepare_memory_region(struct kvm *kvm,
7172 struct kvm_memory_slot *memslot,
f7784b8e 7173 struct kvm_userspace_memory_region *mem,
7b6195a9 7174 enum kvm_mr_change change)
0de10343 7175{
7a905b14
TY		 7176 /*
7177 * Only private memory slots need to be mapped here since
7178 * KVM_SET_MEMORY_REGION ioctl is no longer supported.
0de10343 7179 */
7b6195a9 7180 if ((memslot->id >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_CREATE)) {
7a905b14 7181 unsigned long userspace_addr;
604b38ac 7182
7a905b14
TY		 7183 /*
7184 * MAP_SHARED to prevent internal slot pages from being moved
7185 * by fork()/COW.
7186 */
7b6195a9 7187 userspace_addr = vm_mmap(NULL, 0, memslot->npages * PAGE_SIZE,
7a905b14
TY		 7188 PROT_READ | PROT_WRITE,
7189 MAP_SHARED | MAP_ANONYMOUS, 0);
0de10343 7190
7a905b14
TY		 7191 if (IS_ERR((void *)userspace_addr))
7192 return PTR_ERR((void *)userspace_addr);
604b38ac 7193
7a905b14 7194 memslot->userspace_addr = userspace_addr;
0de10343
ZX		 7195 }
7196
f7784b8e
MT		 7197 return 0;
7198}
7199
7200void kvm_arch_commit_memory_region(struct kvm *kvm,
7201 struct kvm_userspace_memory_region *mem,
8482644a
TY		 7202 const struct kvm_memory_slot *old,
7203 enum kvm_mr_change change)
f7784b8e
MT		 7204{
7205
8482644a 7206 int nr_mmu_pages = 0;
f7784b8e 7207
8482644a 7208 if ((mem->slot >= KVM_USER_MEM_SLOTS) && (change == KVM_MR_DELETE)) {
f7784b8e
MT		 7209 int ret;
7210
8482644a
TY		 7211 ret = vm_munmap(old->userspace_addr,
7212 old->npages * PAGE_SIZE);
f7784b8e
MT		 7213 if (ret < 0)
7214 printk(KERN_WARNING
7215 "kvm_vm_ioctl_set_memory_region: "
7216 "failed to munmap memory\n");
7217 }
7218
48c0e4e9
XG		 7219 if (!kvm->arch.n_requested_mmu_pages)
7220 nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
7221
48c0e4e9 7222 if (nr_mmu_pages)
0de10343 7223 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
c972f3b1
TY		 7224 /*
7225 * Write protect all pages for dirty logging.
7226 * Existing largepage mappings are destroyed here and new ones will
7227 * not be created until the end of the logging.
7228 */
8482644a 7229 if ((change != KVM_MR_DELETE) && (mem->flags & KVM_MEM_LOG_DIRTY_PAGES))
c972f3b1 7230 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
0de10343 7231}
1d737c8a 7232
2df72e9b 7233void kvm_arch_flush_shadow_all(struct kvm *kvm)
34d4cb8f 7234{
6ca18b69 7235 kvm_mmu_invalidate_zap_all_pages(kvm);
34d4cb8f
MT		 7236}
7237
2df72e9b
MT		 7238void kvm_arch_flush_shadow_memslot(struct kvm *kvm,
7239 struct kvm_memory_slot *slot)
7240{
6ca18b69 7241 kvm_mmu_invalidate_zap_all_pages(kvm);
2df72e9b
MT		 7242}
7243
1d737c8a
ZX		 7244int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
7245{
af585b92
GN		 7246 return (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE &&
7247 !vcpu->arch.apf.halted)
7248 || !list_empty_careful(&vcpu->async_pf.done)
66450a21 7249 || kvm_apic_has_events(vcpu)
6aef266c 7250 || vcpu->arch.pv.pv_unhalted
7460fb4a 7251 || atomic_read(&vcpu->arch.nmi_queued) ||
a1b37100
GN		 7252 (kvm_arch_interrupt_allowed(vcpu) &&
7253 kvm_cpu_has_interrupt(vcpu));
1d737c8a 7254}
5736199a 7255
b6d33834 7256int kvm_arch_vcpu_should_kick(struct kvm_vcpu *vcpu)
5736199a 7257{
b6d33834 7258 return kvm_vcpu_exiting_guest_mode(vcpu) == IN_GUEST_MODE;
5736199a 7259}
78646121
GN		 7260
7261int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
7262{
7263 return kvm_x86_ops->interrupt_allowed(vcpu);
7264}
229456fc 7265
f92653ee
JK		 7266bool kvm_is_linear_rip(struct kvm_vcpu *vcpu, unsigned long linear_rip)
7267{
7268 unsigned long current_rip = kvm_rip_read(vcpu) +
7269 get_segment_base(vcpu, VCPU_SREG_CS);
7270
7271 return current_rip == linear_rip;
7272}
7273EXPORT_SYMBOL_GPL(kvm_is_linear_rip);
7274
94fe45da
JK		 7275unsigned long kvm_get_rflags(struct kvm_vcpu *vcpu)
7276{
7277 unsigned long rflags;
7278
7279 rflags = kvm_x86_ops->get_rflags(vcpu);
7280 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
c310bac5 7281 rflags &= ~X86_EFLAGS_TF;
94fe45da
JK		 7282 return rflags;
7283}
7284EXPORT_SYMBOL_GPL(kvm_get_rflags);
7285
7286void kvm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
7287{
7288 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP &&
f92653ee 7289 kvm_is_linear_rip(vcpu, vcpu->arch.singlestep_rip))
c310bac5 7290 rflags |= X86_EFLAGS_TF;
94fe45da 7291 kvm_x86_ops->set_rflags(vcpu, rflags);
3842d135 7292 kvm_make_request(KVM_REQ_EVENT, vcpu);
94fe45da
JK		 7293}
7294EXPORT_SYMBOL_GPL(kvm_set_rflags);
7295
56028d08
GN		 7296void kvm_arch_async_page_ready(struct kvm_vcpu *vcpu, struct kvm_async_pf *work)
7297{
7298 int r;
7299
fb67e14f 7300 if ((vcpu->arch.mmu.direct_map != work->arch.direct_map) ||
c4806acd 7301 is_error_page(work->page))
56028d08
GN		 7302 return;
7303
7304 r = kvm_mmu_reload(vcpu);
7305 if (unlikely(r))
7306 return;
7307
fb67e14f
XG		 7308 if (!vcpu->arch.mmu.direct_map &&
7309 work->arch.cr3 != vcpu->arch.mmu.get_cr3(vcpu))
7310 return;
7311
56028d08
GN		 7312 vcpu->arch.mmu.page_fault(vcpu, work->gva, 0, true);
7313}
7314
af585b92
GN		 7315static inline u32 kvm_async_pf_hash_fn(gfn_t gfn)
7316{
7317 return hash_32(gfn & 0xffffffff, order_base_2(ASYNC_PF_PER_VCPU));
7318}
7319
7320static inline u32 kvm_async_pf_next_probe(u32 key)
7321{
7322 return (key + 1) & (roundup_pow_of_two(ASYNC_PF_PER_VCPU) - 1);
7323}
7324
7325static void kvm_add_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7326{
7327 u32 key = kvm_async_pf_hash_fn(gfn);
7328
7329 while (vcpu->arch.apf.gfns[key] != ~0)
7330 key = kvm_async_pf_next_probe(key);
7331
7332 vcpu->arch.apf.gfns[key] = gfn;
7333}
7334
7335static u32 kvm_async_pf_gfn_slot(struct kvm_vcpu *vcpu, gfn_t gfn)
7336{
7337 int i;
7338 u32 key = kvm_async_pf_hash_fn(gfn);
7339
7340 for (i = 0; i < roundup_pow_of_two(ASYNC_PF_PER_VCPU) &&
c7d28c24
XG		 7341 (vcpu->arch.apf.gfns[key] != gfn &&
7342 vcpu->arch.apf.gfns[key] != ~0); i++)
af585b92
GN		 7343 key = kvm_async_pf_next_probe(key);
7344
7345 return key;
7346}
7347
7348bool kvm_find_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7349{
7350 return vcpu->arch.apf.gfns[kvm_async_pf_gfn_slot(vcpu, gfn)] == gfn;
7351}
7352
7353static void kvm_del_async_pf_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
7354{
7355 u32 i, j, k;
7356
7357 i = j = kvm_async_pf_gfn_slot(vcpu, gfn);
7358 while (true) {
7359 vcpu->arch.apf.gfns[i] = ~0;
7360 do {
7361 j = kvm_async_pf_next_probe(j);
7362 if (vcpu->arch.apf.gfns[j] == ~0)
7363 return;
7364 k = kvm_async_pf_hash_fn(vcpu->arch.apf.gfns[j]);
7365 /*
7366 * k lies cyclically in ]i,j]
7367 * | i.k.j |
7368 * |....j i.k.| or |.k..j i...|
7369 */
7370 } while ((i <= j) ? (i < k && k <= j) : (i < k || k <= j));
7371 vcpu->arch.apf.gfns[i] = vcpu->arch.apf.gfns[j];
7372 i = j;
7373 }
7374}
7375
7c90705b
GN		 7376static int apf_put_user(struct kvm_vcpu *vcpu, u32 val)
7377{
7378
7379 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apf.data, &val,
7380 sizeof(val));
7381}
7382
af585b92
GN		 7383void kvm_arch_async_page_not_present(struct kvm_vcpu *vcpu,
7384 struct kvm_async_pf *work)
7385{
6389ee94
AK		 7386 struct x86_exception fault;
7387
7c90705b 7388 trace_kvm_async_pf_not_present(work->arch.token, work->gva);
af585b92 7389 kvm_add_async_pf_gfn(vcpu, work->arch.gfn);
7c90705b
GN		 7390
7391 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) ||
fc5f06fa
GN		 7392 (vcpu->arch.apf.send_user_only &&
7393 kvm_x86_ops->get_cpl(vcpu) == 0))
7c90705b
GN		 7394 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
7395 else if (!apf_put_user(vcpu, KVM_PV_REASON_PAGE_NOT_PRESENT)) {
6389ee94
AK		 7396 fault.vector = PF_VECTOR;
7397 fault.error_code_valid = true;
7398 fault.error_code = 0;
7399 fault.nested_page_fault = false;
7400 fault.address = work->arch.token;
7401 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7402 }
af585b92
GN		 7403}
7404
7405void kvm_arch_async_page_present(struct kvm_vcpu *vcpu,
7406 struct kvm_async_pf *work)
7407{
6389ee94
AK		 7408 struct x86_exception fault;
7409
7c90705b
GN		 7410 trace_kvm_async_pf_ready(work->arch.token, work->gva);
7411 if (is_error_page(work->page))
7412 work->arch.token = ~0; /* broadcast wakeup */
7413 else
7414 kvm_del_async_pf_gfn(vcpu, work->arch.gfn);
7415
7416 if ((vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED) &&
7417 !apf_put_user(vcpu, KVM_PV_REASON_PAGE_READY)) {
6389ee94
AK		 7418 fault.vector = PF_VECTOR;
7419 fault.error_code_valid = true;
7420 fault.error_code = 0;
7421 fault.nested_page_fault = false;
7422 fault.address = work->arch.token;
7423 kvm_inject_page_fault(vcpu, &fault);
7c90705b 7424 }
e6d53e3b 7425 vcpu->arch.apf.halted = false;
a4fa1635 7426 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
7c90705b
GN		 7427}
7428
7429bool kvm_arch_can_inject_async_page_present(struct kvm_vcpu *vcpu)
7430{
7431 if (!(vcpu->arch.apf.msr_val & KVM_ASYNC_PF_ENABLED))
7432 return true;
7433 else
7434 return !kvm_event_needs_reinjection(vcpu) &&
7435 kvm_x86_ops->interrupt_allowed(vcpu);
af585b92
GN		 7436}
7437
229456fc
MT		 7438EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
7439EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
7440EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
7441EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
7442EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
0ac406de 7443EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmrun);
d8cabddf 7444EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit);
17897f36 7445EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_vmexit_inject);
236649de 7446EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intr_vmexit);
ec1ff790 7447EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_invlpga);
532a46b9 7448EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_skinit);
2e554e8d 7449EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_nested_intercepts);
489223ed 7450EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_write_tsc_offset);
ubuntu-bionic-kernel mirror