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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
e9b73c67 CW |
33 | #include <uapi/drm/i915_drm.h> |
34 | ||
585fb111 | 35 | #include "i915_reg.h" |
79e53945 | 36 | #include "intel_bios.h" |
8187a2b7 | 37 | #include "intel_ringbuffer.h" |
0839ccb8 | 38 | #include <linux/io-mapping.h> |
f899fc64 | 39 | #include <linux/i2c.h> |
c167a6fc | 40 | #include <linux/i2c-algo-bit.h> |
0ade6386 | 41 | #include <drm/intel-gtt.h> |
aaa6fd2a | 42 | #include <linux/backlight.h> |
2911a35b | 43 | #include <linux/intel-iommu.h> |
742cbee8 | 44 | #include <linux/kref.h> |
9ee32fea | 45 | #include <linux/pm_qos.h> |
585fb111 | 46 | |
1da177e4 LT |
47 | /* General customization: |
48 | */ | |
49 | ||
50 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." | |
51 | ||
52 | #define DRIVER_NAME "i915" | |
53 | #define DRIVER_DESC "Intel Graphics" | |
673a394b | 54 | #define DRIVER_DATE "20080730" |
1da177e4 | 55 | |
317c35d1 | 56 | enum pipe { |
752aa88a | 57 | INVALID_PIPE = -1, |
317c35d1 JB |
58 | PIPE_A = 0, |
59 | PIPE_B, | |
9db4a9c7 JB |
60 | PIPE_C, |
61 | I915_MAX_PIPES | |
317c35d1 | 62 | }; |
9db4a9c7 | 63 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 64 | |
a5c961d1 PZ |
65 | enum transcoder { |
66 | TRANSCODER_A = 0, | |
67 | TRANSCODER_B, | |
68 | TRANSCODER_C, | |
69 | TRANSCODER_EDP = 0xF, | |
70 | }; | |
71 | #define transcoder_name(t) ((t) + 'A') | |
72 | ||
80824003 JB |
73 | enum plane { |
74 | PLANE_A = 0, | |
75 | PLANE_B, | |
9db4a9c7 | 76 | PLANE_C, |
80824003 | 77 | }; |
9db4a9c7 | 78 | #define plane_name(p) ((p) + 'A') |
52440211 | 79 | |
06da8da2 VS |
80 | #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A') |
81 | ||
2b139522 ED |
82 | enum port { |
83 | PORT_A = 0, | |
84 | PORT_B, | |
85 | PORT_C, | |
86 | PORT_D, | |
87 | PORT_E, | |
88 | I915_MAX_PORTS | |
89 | }; | |
90 | #define port_name(p) ((p) + 'A') | |
91 | ||
e4607fcf CML |
92 | #define I915_NUM_PHYS_VLV 1 |
93 | ||
94 | enum dpio_channel { | |
95 | DPIO_CH0, | |
96 | DPIO_CH1 | |
97 | }; | |
98 | ||
99 | enum dpio_phy { | |
100 | DPIO_PHY0, | |
101 | DPIO_PHY1 | |
102 | }; | |
103 | ||
b97186f0 PZ |
104 | enum intel_display_power_domain { |
105 | POWER_DOMAIN_PIPE_A, | |
106 | POWER_DOMAIN_PIPE_B, | |
107 | POWER_DOMAIN_PIPE_C, | |
108 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, | |
109 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, | |
110 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, | |
111 | POWER_DOMAIN_TRANSCODER_A, | |
112 | POWER_DOMAIN_TRANSCODER_B, | |
113 | POWER_DOMAIN_TRANSCODER_C, | |
f52e353e | 114 | POWER_DOMAIN_TRANSCODER_EDP, |
cdf8dd7f | 115 | POWER_DOMAIN_VGA, |
fbeeaa23 | 116 | POWER_DOMAIN_AUDIO, |
baa70707 | 117 | POWER_DOMAIN_INIT, |
bddc7645 ID |
118 | |
119 | POWER_DOMAIN_NUM, | |
b97186f0 PZ |
120 | }; |
121 | ||
bddc7645 ID |
122 | #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) |
123 | ||
b97186f0 PZ |
124 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) |
125 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ | |
126 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) | |
f52e353e ID |
127 | #define POWER_DOMAIN_TRANSCODER(tran) \ |
128 | ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ | |
129 | (tran) + POWER_DOMAIN_TRANSCODER_A) | |
b97186f0 | 130 | |
bddc7645 ID |
131 | #define HSW_ALWAYS_ON_POWER_DOMAINS ( \ |
132 | BIT(POWER_DOMAIN_PIPE_A) | \ | |
133 | BIT(POWER_DOMAIN_TRANSCODER_EDP)) | |
6745a2ce PZ |
134 | #define BDW_ALWAYS_ON_POWER_DOMAINS ( \ |
135 | BIT(POWER_DOMAIN_PIPE_A) | \ | |
136 | BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ | |
137 | BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER)) | |
bddc7645 | 138 | |
1d843f9d EE |
139 | enum hpd_pin { |
140 | HPD_NONE = 0, | |
141 | HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ | |
142 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ | |
143 | HPD_CRT, | |
144 | HPD_SDVO_B, | |
145 | HPD_SDVO_C, | |
146 | HPD_PORT_B, | |
147 | HPD_PORT_C, | |
148 | HPD_PORT_D, | |
149 | HPD_NUM_PINS | |
150 | }; | |
151 | ||
2a2d5482 CW |
152 | #define I915_GEM_GPU_DOMAINS \ |
153 | (I915_GEM_DOMAIN_RENDER | \ | |
154 | I915_GEM_DOMAIN_SAMPLER | \ | |
155 | I915_GEM_DOMAIN_COMMAND | \ | |
156 | I915_GEM_DOMAIN_INSTRUCTION | \ | |
157 | I915_GEM_DOMAIN_VERTEX) | |
62fdfeaf | 158 | |
7eb552ae | 159 | #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++) |
9db4a9c7 | 160 | |
6c2b7c12 DV |
161 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
162 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | |
163 | if ((intel_encoder)->base.crtc == (__crtc)) | |
164 | ||
e7b903d2 DV |
165 | struct drm_i915_private; |
166 | ||
46edb027 DV |
167 | enum intel_dpll_id { |
168 | DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ | |
169 | /* real shared dpll ids must be >= 0 */ | |
170 | DPLL_ID_PCH_PLL_A, | |
171 | DPLL_ID_PCH_PLL_B, | |
172 | }; | |
173 | #define I915_NUM_PLLS 2 | |
174 | ||
5358901f | 175 | struct intel_dpll_hw_state { |
66e985c0 | 176 | uint32_t dpll; |
8bcc2795 | 177 | uint32_t dpll_md; |
66e985c0 DV |
178 | uint32_t fp0; |
179 | uint32_t fp1; | |
5358901f DV |
180 | }; |
181 | ||
e72f9fbf | 182 | struct intel_shared_dpll { |
ee7b9f93 JB |
183 | int refcount; /* count of number of CRTCs sharing this PLL */ |
184 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ | |
185 | bool on; /* is the PLL actually active? Disabled during modeset */ | |
46edb027 DV |
186 | const char *name; |
187 | /* should match the index in the dev_priv->shared_dplls array */ | |
188 | enum intel_dpll_id id; | |
5358901f | 189 | struct intel_dpll_hw_state hw_state; |
15bdd4cf DV |
190 | void (*mode_set)(struct drm_i915_private *dev_priv, |
191 | struct intel_shared_dpll *pll); | |
e7b903d2 DV |
192 | void (*enable)(struct drm_i915_private *dev_priv, |
193 | struct intel_shared_dpll *pll); | |
194 | void (*disable)(struct drm_i915_private *dev_priv, | |
195 | struct intel_shared_dpll *pll); | |
5358901f DV |
196 | bool (*get_hw_state)(struct drm_i915_private *dev_priv, |
197 | struct intel_shared_dpll *pll, | |
198 | struct intel_dpll_hw_state *hw_state); | |
ee7b9f93 | 199 | }; |
ee7b9f93 | 200 | |
e69d0bc1 DV |
201 | /* Used by dp and fdi links */ |
202 | struct intel_link_m_n { | |
203 | uint32_t tu; | |
204 | uint32_t gmch_m; | |
205 | uint32_t gmch_n; | |
206 | uint32_t link_m; | |
207 | uint32_t link_n; | |
208 | }; | |
209 | ||
210 | void intel_link_compute_m_n(int bpp, int nlanes, | |
211 | int pixel_clock, int link_clock, | |
212 | struct intel_link_m_n *m_n); | |
213 | ||
6441ab5f PZ |
214 | struct intel_ddi_plls { |
215 | int spll_refcount; | |
216 | int wrpll1_refcount; | |
217 | int wrpll2_refcount; | |
218 | }; | |
219 | ||
1da177e4 LT |
220 | /* Interface history: |
221 | * | |
222 | * 1.1: Original. | |
0d6aa60b DA |
223 | * 1.2: Add Power Management |
224 | * 1.3: Add vblank support | |
de227f5f | 225 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 226 | * 1.5: Add vblank pipe configuration |
2228ed67 MD |
227 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
228 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
229 | */ |
230 | #define DRIVER_MAJOR 1 | |
2228ed67 | 231 | #define DRIVER_MINOR 6 |
1da177e4 LT |
232 | #define DRIVER_PATCHLEVEL 0 |
233 | ||
23bc5982 | 234 | #define WATCH_LISTS 0 |
42d6ab48 | 235 | #define WATCH_GTT 0 |
673a394b | 236 | |
71acb5eb DA |
237 | #define I915_GEM_PHYS_CURSOR_0 1 |
238 | #define I915_GEM_PHYS_CURSOR_1 2 | |
239 | #define I915_GEM_PHYS_OVERLAY_REGS 3 | |
240 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) | |
241 | ||
242 | struct drm_i915_gem_phys_object { | |
243 | int id; | |
244 | struct page **page_list; | |
245 | drm_dma_handle_t *handle; | |
05394f39 | 246 | struct drm_i915_gem_object *cur_obj; |
71acb5eb DA |
247 | }; |
248 | ||
0a3e67a4 JB |
249 | struct opregion_header; |
250 | struct opregion_acpi; | |
251 | struct opregion_swsci; | |
252 | struct opregion_asle; | |
253 | ||
8ee1c3db | 254 | struct intel_opregion { |
5bc4418b BW |
255 | struct opregion_header __iomem *header; |
256 | struct opregion_acpi __iomem *acpi; | |
257 | struct opregion_swsci __iomem *swsci; | |
ebde53c7 JN |
258 | u32 swsci_gbda_sub_functions; |
259 | u32 swsci_sbcb_sub_functions; | |
5bc4418b BW |
260 | struct opregion_asle __iomem *asle; |
261 | void __iomem *vbt; | |
01fe9dbd | 262 | u32 __iomem *lid_state; |
91a60f20 | 263 | struct work_struct asle_work; |
8ee1c3db | 264 | }; |
44834a67 | 265 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 266 | |
6ef3d427 CW |
267 | struct intel_overlay; |
268 | struct intel_overlay_error_state; | |
269 | ||
7c1c2871 DA |
270 | struct drm_i915_master_private { |
271 | drm_local_map_t *sarea; | |
272 | struct _drm_i915_sarea *sarea_priv; | |
273 | }; | |
de151cf6 | 274 | #define I915_FENCE_REG_NONE -1 |
42b5aeab VS |
275 | #define I915_MAX_NUM_FENCES 32 |
276 | /* 32 fences + sign bit for FENCE_REG_NONE */ | |
277 | #define I915_MAX_NUM_FENCE_BITS 6 | |
de151cf6 JB |
278 | |
279 | struct drm_i915_fence_reg { | |
007cc8ac | 280 | struct list_head lru_list; |
caea7476 | 281 | struct drm_i915_gem_object *obj; |
1690e1eb | 282 | int pin_count; |
de151cf6 | 283 | }; |
7c1c2871 | 284 | |
9b9d172d | 285 | struct sdvo_device_mapping { |
e957d772 | 286 | u8 initialized; |
9b9d172d | 287 | u8 dvo_port; |
288 | u8 slave_addr; | |
289 | u8 dvo_wiring; | |
e957d772 | 290 | u8 i2c_pin; |
b1083333 | 291 | u8 ddc_pin; |
9b9d172d | 292 | }; |
293 | ||
c4a1d9e4 CW |
294 | struct intel_display_error_state; |
295 | ||
63eeaf38 | 296 | struct drm_i915_error_state { |
742cbee8 | 297 | struct kref ref; |
63eeaf38 JB |
298 | u32 eir; |
299 | u32 pgtbl_er; | |
be998e2e | 300 | u32 ier; |
b9a3906b | 301 | u32 ccid; |
0f3b6849 CW |
302 | u32 derrmr; |
303 | u32 forcewake; | |
9574b3fe | 304 | bool waiting[I915_NUM_RINGS]; |
9db4a9c7 | 305 | u32 pipestat[I915_MAX_PIPES]; |
c1cd90ed DV |
306 | u32 tail[I915_NUM_RINGS]; |
307 | u32 head[I915_NUM_RINGS]; | |
0f3b6849 | 308 | u32 ctl[I915_NUM_RINGS]; |
d27b1e0e DV |
309 | u32 ipeir[I915_NUM_RINGS]; |
310 | u32 ipehr[I915_NUM_RINGS]; | |
311 | u32 instdone[I915_NUM_RINGS]; | |
312 | u32 acthd[I915_NUM_RINGS]; | |
7e3b8737 | 313 | u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1]; |
df2b23d9 | 314 | u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1]; |
12f55818 | 315 | u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */ |
7e3b8737 DV |
316 | /* our own tracking of ring head and tail */ |
317 | u32 cpu_ring_head[I915_NUM_RINGS]; | |
318 | u32 cpu_ring_tail[I915_NUM_RINGS]; | |
1d8f38f4 | 319 | u32 error; /* gen6+ */ |
71e172e8 | 320 | u32 err_int; /* gen7 */ |
94e39e28 | 321 | u32 bbstate[I915_NUM_RINGS]; |
c1cd90ed DV |
322 | u32 instpm[I915_NUM_RINGS]; |
323 | u32 instps[I915_NUM_RINGS]; | |
050ee91f | 324 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; |
d27b1e0e | 325 | u32 seqno[I915_NUM_RINGS]; |
9df30794 | 326 | u64 bbaddr; |
33f3f518 DV |
327 | u32 fault_reg[I915_NUM_RINGS]; |
328 | u32 done_reg; | |
c1cd90ed | 329 | u32 faddr[I915_NUM_RINGS]; |
4b9de737 | 330 | u64 fence[I915_MAX_NUM_FENCES]; |
63eeaf38 | 331 | struct timeval time; |
52d39a21 CW |
332 | struct drm_i915_error_ring { |
333 | struct drm_i915_error_object { | |
334 | int page_count; | |
335 | u32 gtt_offset; | |
336 | u32 *pages[0]; | |
8c123e54 | 337 | } *ringbuffer, *batchbuffer, *ctx; |
52d39a21 CW |
338 | struct drm_i915_error_request { |
339 | long jiffies; | |
340 | u32 seqno; | |
ee4f42b1 | 341 | u32 tail; |
52d39a21 CW |
342 | } *requests; |
343 | int num_requests; | |
344 | } ring[I915_NUM_RINGS]; | |
9df30794 | 345 | struct drm_i915_error_buffer { |
a779e5ab | 346 | u32 size; |
9df30794 | 347 | u32 name; |
0201f1ec | 348 | u32 rseqno, wseqno; |
9df30794 CW |
349 | u32 gtt_offset; |
350 | u32 read_domains; | |
351 | u32 write_domain; | |
4b9de737 | 352 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
9df30794 CW |
353 | s32 pinned:2; |
354 | u32 tiling:2; | |
355 | u32 dirty:1; | |
356 | u32 purgeable:1; | |
5d1333fc | 357 | s32 ring:4; |
f56383cb | 358 | u32 cache_level:3; |
95f5301d BW |
359 | } **active_bo, **pinned_bo; |
360 | u32 *active_bo_count, *pinned_bo_count; | |
6ef3d427 | 361 | struct intel_overlay_error_state *overlay; |
c4a1d9e4 | 362 | struct intel_display_error_state *display; |
da661464 MK |
363 | int hangcheck_score[I915_NUM_RINGS]; |
364 | enum intel_ring_hangcheck_action hangcheck_action[I915_NUM_RINGS]; | |
63eeaf38 JB |
365 | }; |
366 | ||
7bd688cd | 367 | struct intel_connector; |
b8cecdf5 | 368 | struct intel_crtc_config; |
0e8ffe1b | 369 | struct intel_crtc; |
ee9300bb DV |
370 | struct intel_limit; |
371 | struct dpll; | |
b8cecdf5 | 372 | |
e70236a8 | 373 | struct drm_i915_display_funcs { |
ee5382ae | 374 | bool (*fbc_enabled)(struct drm_device *dev); |
e70236a8 JB |
375 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
376 | void (*disable_fbc)(struct drm_device *dev); | |
377 | int (*get_display_clock_speed)(struct drm_device *dev); | |
378 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
ee9300bb DV |
379 | /** |
380 | * find_dpll() - Find the best values for the PLL | |
381 | * @limit: limits for the PLL | |
382 | * @crtc: current CRTC | |
383 | * @target: target frequency in kHz | |
384 | * @refclk: reference clock frequency in kHz | |
385 | * @match_clock: if provided, @best_clock P divider must | |
386 | * match the P divider from @match_clock | |
387 | * used for LVDS downclocking | |
388 | * @best_clock: best PLL values found | |
389 | * | |
390 | * Returns true on success, false on failure. | |
391 | */ | |
392 | bool (*find_dpll)(const struct intel_limit *limit, | |
393 | struct drm_crtc *crtc, | |
394 | int target, int refclk, | |
395 | struct dpll *match_clock, | |
396 | struct dpll *best_clock); | |
46ba614c | 397 | void (*update_wm)(struct drm_crtc *crtc); |
adf3d35e VS |
398 | void (*update_sprite_wm)(struct drm_plane *plane, |
399 | struct drm_crtc *crtc, | |
4c4ff43a | 400 | uint32_t sprite_width, int pixel_size, |
bdd57d03 | 401 | bool enable, bool scaled); |
47fab737 | 402 | void (*modeset_global_resources)(struct drm_device *dev); |
0e8ffe1b DV |
403 | /* Returns the active state of the crtc, and if the crtc is active, |
404 | * fills out the pipe-config with the hw state. */ | |
405 | bool (*get_pipe_config)(struct intel_crtc *, | |
406 | struct intel_crtc_config *); | |
f564048e | 407 | int (*crtc_mode_set)(struct drm_crtc *crtc, |
f564048e EA |
408 | int x, int y, |
409 | struct drm_framebuffer *old_fb); | |
76e5a89c DV |
410 | void (*crtc_enable)(struct drm_crtc *crtc); |
411 | void (*crtc_disable)(struct drm_crtc *crtc); | |
ee7b9f93 | 412 | void (*off)(struct drm_crtc *crtc); |
e0dac65e | 413 | void (*write_eld)(struct drm_connector *connector, |
34427052 JN |
414 | struct drm_crtc *crtc, |
415 | struct drm_display_mode *mode); | |
674cf967 | 416 | void (*fdi_link_train)(struct drm_crtc *crtc); |
6067aaea | 417 | void (*init_clock_gating)(struct drm_device *dev); |
8c9f3aaf JB |
418 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
419 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
420 | struct drm_i915_gem_object *obj, |
421 | uint32_t flags); | |
17638cd6 JB |
422 | int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
423 | int x, int y); | |
20afbda2 | 424 | void (*hpd_irq_setup)(struct drm_device *dev); |
e70236a8 JB |
425 | /* clock updates for mode set */ |
426 | /* cursor updates */ | |
427 | /* render clock increase/decrease */ | |
428 | /* display clock increase/decrease */ | |
429 | /* pll clock increase/decrease */ | |
7bd688cd JN |
430 | |
431 | int (*setup_backlight)(struct intel_connector *connector); | |
7bd688cd JN |
432 | uint32_t (*get_backlight)(struct intel_connector *connector); |
433 | void (*set_backlight)(struct intel_connector *connector, | |
434 | uint32_t level); | |
435 | void (*disable_backlight)(struct intel_connector *connector); | |
436 | void (*enable_backlight)(struct intel_connector *connector); | |
e70236a8 JB |
437 | }; |
438 | ||
907b28c5 | 439 | struct intel_uncore_funcs { |
990bbdad CW |
440 | void (*force_wake_get)(struct drm_i915_private *dev_priv); |
441 | void (*force_wake_put)(struct drm_i915_private *dev_priv); | |
0b274481 BW |
442 | |
443 | uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
444 | uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
445 | uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
446 | uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
447 | ||
448 | void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset, | |
449 | uint8_t val, bool trace); | |
450 | void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset, | |
451 | uint16_t val, bool trace); | |
452 | void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset, | |
453 | uint32_t val, bool trace); | |
454 | void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset, | |
455 | uint64_t val, bool trace); | |
990bbdad CW |
456 | }; |
457 | ||
907b28c5 CW |
458 | struct intel_uncore { |
459 | spinlock_t lock; /** lock is also taken in irq contexts. */ | |
460 | ||
461 | struct intel_uncore_funcs funcs; | |
462 | ||
463 | unsigned fifo_count; | |
464 | unsigned forcewake_count; | |
aec347ab CW |
465 | |
466 | struct delayed_work force_wake_work; | |
907b28c5 CW |
467 | }; |
468 | ||
79fc46df DL |
469 | #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ |
470 | func(is_mobile) sep \ | |
471 | func(is_i85x) sep \ | |
472 | func(is_i915g) sep \ | |
473 | func(is_i945gm) sep \ | |
474 | func(is_g33) sep \ | |
475 | func(need_gfx_hws) sep \ | |
476 | func(is_g4x) sep \ | |
477 | func(is_pineview) sep \ | |
478 | func(is_broadwater) sep \ | |
479 | func(is_crestline) sep \ | |
480 | func(is_ivybridge) sep \ | |
481 | func(is_valleyview) sep \ | |
482 | func(is_haswell) sep \ | |
b833d685 | 483 | func(is_preliminary) sep \ |
79fc46df DL |
484 | func(has_fbc) sep \ |
485 | func(has_pipe_cxsr) sep \ | |
486 | func(has_hotplug) sep \ | |
487 | func(cursor_needs_physical) sep \ | |
488 | func(has_overlay) sep \ | |
489 | func(overlay_needs_physical) sep \ | |
490 | func(supports_tv) sep \ | |
dd93be58 | 491 | func(has_llc) sep \ |
30568c45 DL |
492 | func(has_ddi) sep \ |
493 | func(has_fpga_dbg) | |
c96ea64e | 494 | |
a587f779 DL |
495 | #define DEFINE_FLAG(name) u8 name:1 |
496 | #define SEP_SEMICOLON ; | |
c96ea64e | 497 | |
cfdf1fa2 | 498 | struct intel_device_info { |
10fce67a | 499 | u32 display_mmio_offset; |
7eb552ae | 500 | u8 num_pipes:3; |
c96c3a8c | 501 | u8 gen; |
73ae478c | 502 | u8 ring_mask; /* Rings supported by the HW */ |
a587f779 | 503 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); |
cfdf1fa2 KH |
504 | }; |
505 | ||
a587f779 DL |
506 | #undef DEFINE_FLAG |
507 | #undef SEP_SEMICOLON | |
508 | ||
7faf1ab2 DV |
509 | enum i915_cache_level { |
510 | I915_CACHE_NONE = 0, | |
350ec881 CW |
511 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ |
512 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc | |
513 | caches, eg sampler/render caches, and the | |
514 | large Last-Level-Cache. LLC is coherent with | |
515 | the CPU, but L3 is only visible to the GPU. */ | |
651d794f | 516 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ |
7faf1ab2 DV |
517 | }; |
518 | ||
2d04befb KG |
519 | typedef uint32_t gen6_gtt_pte_t; |
520 | ||
853ba5d2 | 521 | struct i915_address_space { |
93bd8649 | 522 | struct drm_mm mm; |
853ba5d2 | 523 | struct drm_device *dev; |
a7bbbd63 | 524 | struct list_head global_link; |
853ba5d2 BW |
525 | unsigned long start; /* Start offset always 0 for dri2 */ |
526 | size_t total; /* size addr space maps (ex. 2GB for ggtt) */ | |
527 | ||
528 | struct { | |
529 | dma_addr_t addr; | |
530 | struct page *page; | |
531 | } scratch; | |
532 | ||
5cef07e1 BW |
533 | /** |
534 | * List of objects currently involved in rendering. | |
535 | * | |
536 | * Includes buffers having the contents of their GPU caches | |
537 | * flushed, not necessarily primitives. last_rendering_seqno | |
538 | * represents when the rendering involved will be completed. | |
539 | * | |
540 | * A reference is held on the buffer while on this list. | |
541 | */ | |
542 | struct list_head active_list; | |
543 | ||
544 | /** | |
545 | * LRU list of objects which are not in the ringbuffer and | |
546 | * are ready to unbind, but are still in the GTT. | |
547 | * | |
548 | * last_rendering_seqno is 0 while an object is in this list. | |
549 | * | |
550 | * A reference is not held on the buffer while on this list, | |
551 | * as merely being GTT-bound shouldn't prevent its being | |
552 | * freed, and we'll pull it off the list in the free path. | |
553 | */ | |
554 | struct list_head inactive_list; | |
555 | ||
853ba5d2 BW |
556 | /* FIXME: Need a more generic return type */ |
557 | gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr, | |
b35b380e BW |
558 | enum i915_cache_level level, |
559 | bool valid); /* Create a valid PTE */ | |
853ba5d2 BW |
560 | void (*clear_range)(struct i915_address_space *vm, |
561 | unsigned int first_entry, | |
828c7908 BW |
562 | unsigned int num_entries, |
563 | bool use_scratch); | |
853ba5d2 BW |
564 | void (*insert_entries)(struct i915_address_space *vm, |
565 | struct sg_table *st, | |
566 | unsigned int first_entry, | |
567 | enum i915_cache_level cache_level); | |
568 | void (*cleanup)(struct i915_address_space *vm); | |
569 | }; | |
570 | ||
5d4545ae BW |
571 | /* The Graphics Translation Table is the way in which GEN hardware translates a |
572 | * Graphics Virtual Address into a Physical Address. In addition to the normal | |
573 | * collateral associated with any va->pa translations GEN hardware also has a | |
574 | * portion of the GTT which can be mapped by the CPU and remain both coherent | |
575 | * and correct (in cases like swizzling). That region is referred to as GMADR in | |
576 | * the spec. | |
577 | */ | |
578 | struct i915_gtt { | |
853ba5d2 | 579 | struct i915_address_space base; |
baa09f5f | 580 | size_t stolen_size; /* Total size of stolen memory */ |
5d4545ae BW |
581 | |
582 | unsigned long mappable_end; /* End offset that we can CPU map */ | |
583 | struct io_mapping *mappable; /* Mapping to our CPU mappable region */ | |
584 | phys_addr_t mappable_base; /* PA of our GMADR */ | |
585 | ||
586 | /** "Graphics Stolen Memory" holds the global PTEs */ | |
587 | void __iomem *gsm; | |
a81cc00c BW |
588 | |
589 | bool do_idle_maps; | |
7faf1ab2 | 590 | |
911bdf0a | 591 | int mtrr; |
7faf1ab2 DV |
592 | |
593 | /* global gtt ops */ | |
baa09f5f | 594 | int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total, |
41907ddc BW |
595 | size_t *stolen, phys_addr_t *mappable_base, |
596 | unsigned long *mappable_end); | |
5d4545ae | 597 | }; |
853ba5d2 | 598 | #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT) |
5d4545ae | 599 | |
1d2a314c | 600 | struct i915_hw_ppgtt { |
853ba5d2 | 601 | struct i915_address_space base; |
1d2a314c | 602 | unsigned num_pd_entries; |
37aca44a BW |
603 | union { |
604 | struct page **pt_pages; | |
605 | struct page *gen8_pt_pages; | |
606 | }; | |
607 | struct page *pd_pages; | |
608 | int num_pd_pages; | |
609 | int num_pt_pages; | |
610 | union { | |
611 | uint32_t pd_offset; | |
612 | dma_addr_t pd_dma_addr[4]; | |
613 | }; | |
614 | union { | |
615 | dma_addr_t *pt_dma_addr; | |
616 | dma_addr_t *gen8_pt_dma_addr[4]; | |
617 | }; | |
b7c36d25 | 618 | int (*enable)(struct drm_device *dev); |
1d2a314c DV |
619 | }; |
620 | ||
0b02e798 BW |
621 | /** |
622 | * A VMA represents a GEM BO that is bound into an address space. Therefore, a | |
623 | * VMA's presence cannot be guaranteed before binding, or after unbinding the | |
624 | * object into/from the address space. | |
625 | * | |
626 | * To make things as simple as possible (ie. no refcounting), a VMA's lifetime | |
2f633156 BW |
627 | * will always be <= an objects lifetime. So object refcounting should cover us. |
628 | */ | |
629 | struct i915_vma { | |
630 | struct drm_mm_node node; | |
631 | struct drm_i915_gem_object *obj; | |
632 | struct i915_address_space *vm; | |
633 | ||
ca191b13 BW |
634 | /** This object's place on the active/inactive lists */ |
635 | struct list_head mm_list; | |
636 | ||
2f633156 | 637 | struct list_head vma_link; /* Link in the object's VMA list */ |
82a55ad1 BW |
638 | |
639 | /** This vma's place in the batchbuffer or on the eviction list */ | |
640 | struct list_head exec_list; | |
641 | ||
27173f1f BW |
642 | /** |
643 | * Used for performing relocations during execbuffer insertion. | |
644 | */ | |
645 | struct hlist_node exec_node; | |
646 | unsigned long exec_handle; | |
647 | struct drm_i915_gem_exec_object2 *exec_entry; | |
648 | ||
1d2a314c DV |
649 | }; |
650 | ||
e59ec13d MK |
651 | struct i915_ctx_hang_stats { |
652 | /* This context had batch pending when hang was declared */ | |
653 | unsigned batch_pending; | |
654 | ||
655 | /* This context had batch active when hang was declared */ | |
656 | unsigned batch_active; | |
be62acb4 MK |
657 | |
658 | /* Time when this context was last blamed for a GPU reset */ | |
659 | unsigned long guilty_ts; | |
660 | ||
661 | /* This context is banned to submit more work */ | |
662 | bool banned; | |
e59ec13d | 663 | }; |
40521054 BW |
664 | |
665 | /* This must match up with the value previously used for execbuf2.rsvd1. */ | |
666 | #define DEFAULT_CONTEXT_ID 0 | |
667 | struct i915_hw_context { | |
dce3271b | 668 | struct kref ref; |
40521054 | 669 | int id; |
e0556841 | 670 | bool is_initialized; |
3ccfd19d | 671 | uint8_t remap_slice; |
40521054 BW |
672 | struct drm_i915_file_private *file_priv; |
673 | struct intel_ring_buffer *ring; | |
674 | struct drm_i915_gem_object *obj; | |
e59ec13d | 675 | struct i915_ctx_hang_stats hang_stats; |
a33afea5 BW |
676 | |
677 | struct list_head link; | |
40521054 BW |
678 | }; |
679 | ||
5c3fe8b0 BW |
680 | struct i915_fbc { |
681 | unsigned long size; | |
682 | unsigned int fb_id; | |
683 | enum plane plane; | |
684 | int y; | |
685 | ||
686 | struct drm_mm_node *compressed_fb; | |
687 | struct drm_mm_node *compressed_llb; | |
688 | ||
689 | struct intel_fbc_work { | |
690 | struct delayed_work work; | |
691 | struct drm_crtc *crtc; | |
692 | struct drm_framebuffer *fb; | |
693 | int interval; | |
694 | } *fbc_work; | |
695 | ||
29ebf90f CW |
696 | enum no_fbc_reason { |
697 | FBC_OK, /* FBC is enabled */ | |
698 | FBC_UNSUPPORTED, /* FBC is not supported by this chipset */ | |
5c3fe8b0 BW |
699 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
700 | FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */ | |
701 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ | |
702 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ | |
703 | FBC_BAD_PLANE, /* fbc not supported on plane */ | |
704 | FBC_NOT_TILED, /* buffer not tiled */ | |
705 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ | |
706 | FBC_MODULE_PARAM, | |
707 | FBC_CHIP_DEFAULT, /* disabled by default on this chip */ | |
708 | } no_fbc_reason; | |
b5e50c3f JB |
709 | }; |
710 | ||
a031d709 RV |
711 | struct i915_psr { |
712 | bool sink_support; | |
713 | bool source_ok; | |
3f51e471 | 714 | }; |
5c3fe8b0 | 715 | |
3bad0781 | 716 | enum intel_pch { |
f0350830 | 717 | PCH_NONE = 0, /* No PCH present */ |
3bad0781 ZW |
718 | PCH_IBX, /* Ibexpeak PCH */ |
719 | PCH_CPT, /* Cougarpoint PCH */ | |
eb877ebf | 720 | PCH_LPT, /* Lynxpoint PCH */ |
40c7ead9 | 721 | PCH_NOP, |
3bad0781 ZW |
722 | }; |
723 | ||
988d6ee8 PZ |
724 | enum intel_sbi_destination { |
725 | SBI_ICLK, | |
726 | SBI_MPHY, | |
727 | }; | |
728 | ||
b690e96c | 729 | #define QUIRK_PIPEA_FORCE (1<<0) |
435793df | 730 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
4dca20ef | 731 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
b690e96c | 732 | |
8be48d92 | 733 | struct intel_fbdev; |
1630fe75 | 734 | struct intel_fbc_work; |
38651674 | 735 | |
c2b9152f DV |
736 | struct intel_gmbus { |
737 | struct i2c_adapter adapter; | |
f2ce9faf | 738 | u32 force_bit; |
c2b9152f | 739 | u32 reg0; |
36c785f0 | 740 | u32 gpio_reg; |
c167a6fc | 741 | struct i2c_algo_bit_data bit_algo; |
c2b9152f DV |
742 | struct drm_i915_private *dev_priv; |
743 | }; | |
744 | ||
f4c956ad | 745 | struct i915_suspend_saved_registers { |
ba8bbcf6 JB |
746 | u8 saveLBB; |
747 | u32 saveDSPACNTR; | |
748 | u32 saveDSPBCNTR; | |
e948e994 | 749 | u32 saveDSPARB; |
ba8bbcf6 JB |
750 | u32 savePIPEACONF; |
751 | u32 savePIPEBCONF; | |
752 | u32 savePIPEASRC; | |
753 | u32 savePIPEBSRC; | |
754 | u32 saveFPA0; | |
755 | u32 saveFPA1; | |
756 | u32 saveDPLL_A; | |
757 | u32 saveDPLL_A_MD; | |
758 | u32 saveHTOTAL_A; | |
759 | u32 saveHBLANK_A; | |
760 | u32 saveHSYNC_A; | |
761 | u32 saveVTOTAL_A; | |
762 | u32 saveVBLANK_A; | |
763 | u32 saveVSYNC_A; | |
764 | u32 saveBCLRPAT_A; | |
5586c8bc | 765 | u32 saveTRANSACONF; |
42048781 ZW |
766 | u32 saveTRANS_HTOTAL_A; |
767 | u32 saveTRANS_HBLANK_A; | |
768 | u32 saveTRANS_HSYNC_A; | |
769 | u32 saveTRANS_VTOTAL_A; | |
770 | u32 saveTRANS_VBLANK_A; | |
771 | u32 saveTRANS_VSYNC_A; | |
0da3ea12 | 772 | u32 savePIPEASTAT; |
ba8bbcf6 JB |
773 | u32 saveDSPASTRIDE; |
774 | u32 saveDSPASIZE; | |
775 | u32 saveDSPAPOS; | |
585fb111 | 776 | u32 saveDSPAADDR; |
ba8bbcf6 JB |
777 | u32 saveDSPASURF; |
778 | u32 saveDSPATILEOFF; | |
779 | u32 savePFIT_PGM_RATIOS; | |
0eb96d6e | 780 | u32 saveBLC_HIST_CTL; |
ba8bbcf6 JB |
781 | u32 saveBLC_PWM_CTL; |
782 | u32 saveBLC_PWM_CTL2; | |
07bf139b | 783 | u32 saveBLC_HIST_CTL_B; |
42048781 ZW |
784 | u32 saveBLC_CPU_PWM_CTL; |
785 | u32 saveBLC_CPU_PWM_CTL2; | |
ba8bbcf6 JB |
786 | u32 saveFPB0; |
787 | u32 saveFPB1; | |
788 | u32 saveDPLL_B; | |
789 | u32 saveDPLL_B_MD; | |
790 | u32 saveHTOTAL_B; | |
791 | u32 saveHBLANK_B; | |
792 | u32 saveHSYNC_B; | |
793 | u32 saveVTOTAL_B; | |
794 | u32 saveVBLANK_B; | |
795 | u32 saveVSYNC_B; | |
796 | u32 saveBCLRPAT_B; | |
5586c8bc | 797 | u32 saveTRANSBCONF; |
42048781 ZW |
798 | u32 saveTRANS_HTOTAL_B; |
799 | u32 saveTRANS_HBLANK_B; | |
800 | u32 saveTRANS_HSYNC_B; | |
801 | u32 saveTRANS_VTOTAL_B; | |
802 | u32 saveTRANS_VBLANK_B; | |
803 | u32 saveTRANS_VSYNC_B; | |
0da3ea12 | 804 | u32 savePIPEBSTAT; |
ba8bbcf6 JB |
805 | u32 saveDSPBSTRIDE; |
806 | u32 saveDSPBSIZE; | |
807 | u32 saveDSPBPOS; | |
585fb111 | 808 | u32 saveDSPBADDR; |
ba8bbcf6 JB |
809 | u32 saveDSPBSURF; |
810 | u32 saveDSPBTILEOFF; | |
585fb111 JB |
811 | u32 saveVGA0; |
812 | u32 saveVGA1; | |
813 | u32 saveVGA_PD; | |
ba8bbcf6 JB |
814 | u32 saveVGACNTRL; |
815 | u32 saveADPA; | |
816 | u32 saveLVDS; | |
585fb111 JB |
817 | u32 savePP_ON_DELAYS; |
818 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
819 | u32 saveDVOA; |
820 | u32 saveDVOB; | |
821 | u32 saveDVOC; | |
822 | u32 savePP_ON; | |
823 | u32 savePP_OFF; | |
824 | u32 savePP_CONTROL; | |
585fb111 | 825 | u32 savePP_DIVISOR; |
ba8bbcf6 JB |
826 | u32 savePFIT_CONTROL; |
827 | u32 save_palette_a[256]; | |
828 | u32 save_palette_b[256]; | |
06027f91 | 829 | u32 saveDPFC_CB_BASE; |
ba8bbcf6 JB |
830 | u32 saveFBC_CFB_BASE; |
831 | u32 saveFBC_LL_BASE; | |
832 | u32 saveFBC_CONTROL; | |
833 | u32 saveFBC_CONTROL2; | |
0da3ea12 JB |
834 | u32 saveIER; |
835 | u32 saveIIR; | |
836 | u32 saveIMR; | |
42048781 ZW |
837 | u32 saveDEIER; |
838 | u32 saveDEIMR; | |
839 | u32 saveGTIER; | |
840 | u32 saveGTIMR; | |
841 | u32 saveFDI_RXA_IMR; | |
842 | u32 saveFDI_RXB_IMR; | |
1f84e550 | 843 | u32 saveCACHE_MODE_0; |
1f84e550 | 844 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
845 | u32 saveSWF0[16]; |
846 | u32 saveSWF1[16]; | |
847 | u32 saveSWF2[3]; | |
848 | u8 saveMSR; | |
849 | u8 saveSR[8]; | |
123f794f | 850 | u8 saveGR[25]; |
ba8bbcf6 | 851 | u8 saveAR_INDEX; |
a59e122a | 852 | u8 saveAR[21]; |
ba8bbcf6 | 853 | u8 saveDACMASK; |
a59e122a | 854 | u8 saveCR[37]; |
4b9de737 | 855 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
1fd1c624 EA |
856 | u32 saveCURACNTR; |
857 | u32 saveCURAPOS; | |
858 | u32 saveCURABASE; | |
859 | u32 saveCURBCNTR; | |
860 | u32 saveCURBPOS; | |
861 | u32 saveCURBBASE; | |
862 | u32 saveCURSIZE; | |
a4fc5ed6 KP |
863 | u32 saveDP_B; |
864 | u32 saveDP_C; | |
865 | u32 saveDP_D; | |
866 | u32 savePIPEA_GMCH_DATA_M; | |
867 | u32 savePIPEB_GMCH_DATA_M; | |
868 | u32 savePIPEA_GMCH_DATA_N; | |
869 | u32 savePIPEB_GMCH_DATA_N; | |
870 | u32 savePIPEA_DP_LINK_M; | |
871 | u32 savePIPEB_DP_LINK_M; | |
872 | u32 savePIPEA_DP_LINK_N; | |
873 | u32 savePIPEB_DP_LINK_N; | |
42048781 ZW |
874 | u32 saveFDI_RXA_CTL; |
875 | u32 saveFDI_TXA_CTL; | |
876 | u32 saveFDI_RXB_CTL; | |
877 | u32 saveFDI_TXB_CTL; | |
878 | u32 savePFA_CTL_1; | |
879 | u32 savePFB_CTL_1; | |
880 | u32 savePFA_WIN_SZ; | |
881 | u32 savePFB_WIN_SZ; | |
882 | u32 savePFA_WIN_POS; | |
883 | u32 savePFB_WIN_POS; | |
5586c8bc ZW |
884 | u32 savePCH_DREF_CONTROL; |
885 | u32 saveDISP_ARB_CTL; | |
886 | u32 savePIPEA_DATA_M1; | |
887 | u32 savePIPEA_DATA_N1; | |
888 | u32 savePIPEA_LINK_M1; | |
889 | u32 savePIPEA_LINK_N1; | |
890 | u32 savePIPEB_DATA_M1; | |
891 | u32 savePIPEB_DATA_N1; | |
892 | u32 savePIPEB_LINK_M1; | |
893 | u32 savePIPEB_LINK_N1; | |
b5b72e89 | 894 | u32 saveMCHBAR_RENDER_STANDBY; |
cda2bb78 | 895 | u32 savePCH_PORT_HOTPLUG; |
f4c956ad | 896 | }; |
c85aa885 DV |
897 | |
898 | struct intel_gen6_power_mgmt { | |
59cdb63d | 899 | /* work and pm_iir are protected by dev_priv->irq_lock */ |
c85aa885 DV |
900 | struct work_struct work; |
901 | u32 pm_iir; | |
59cdb63d | 902 | |
c85aa885 DV |
903 | /* The below variables an all the rps hw state are protected by |
904 | * dev->struct mutext. */ | |
905 | u8 cur_delay; | |
906 | u8 min_delay; | |
907 | u8 max_delay; | |
52ceb908 | 908 | u8 rpe_delay; |
dd75fdc8 CW |
909 | u8 rp1_delay; |
910 | u8 rp0_delay; | |
31c77388 | 911 | u8 hw_max; |
1a01ab3b | 912 | |
dd75fdc8 CW |
913 | int last_adj; |
914 | enum { LOW_POWER, BETWEEN, HIGH_POWER } power; | |
915 | ||
c0951f0c | 916 | bool enabled; |
1a01ab3b | 917 | struct delayed_work delayed_resume_work; |
4fc688ce JB |
918 | |
919 | /* | |
920 | * Protects RPS/RC6 register access and PCU communication. | |
921 | * Must be taken after struct_mutex if nested. | |
922 | */ | |
923 | struct mutex hw_lock; | |
c85aa885 DV |
924 | }; |
925 | ||
1a240d4d DV |
926 | /* defined intel_pm.c */ |
927 | extern spinlock_t mchdev_lock; | |
928 | ||
c85aa885 DV |
929 | struct intel_ilk_power_mgmt { |
930 | u8 cur_delay; | |
931 | u8 min_delay; | |
932 | u8 max_delay; | |
933 | u8 fmax; | |
934 | u8 fstart; | |
935 | ||
936 | u64 last_count1; | |
937 | unsigned long last_time1; | |
938 | unsigned long chipset_power; | |
939 | u64 last_count2; | |
940 | struct timespec last_time2; | |
941 | unsigned long gfx_power; | |
942 | u8 corr; | |
943 | ||
944 | int c_m; | |
945 | int r_t; | |
3e373948 DV |
946 | |
947 | struct drm_i915_gem_object *pwrctx; | |
948 | struct drm_i915_gem_object *renderctx; | |
c85aa885 DV |
949 | }; |
950 | ||
a38911a3 WX |
951 | /* Power well structure for haswell */ |
952 | struct i915_power_well { | |
c1ca727f | 953 | const char *name; |
6f3ef5dd | 954 | bool always_on; |
a38911a3 WX |
955 | /* power well enable/disable usage count */ |
956 | int count; | |
c1ca727f ID |
957 | unsigned long domains; |
958 | void *data; | |
959 | void (*set)(struct drm_device *dev, struct i915_power_well *power_well, | |
960 | bool enable); | |
961 | bool (*is_enabled)(struct drm_device *dev, | |
962 | struct i915_power_well *power_well); | |
a38911a3 WX |
963 | }; |
964 | ||
83c00f55 | 965 | struct i915_power_domains { |
baa70707 ID |
966 | /* |
967 | * Power wells needed for initialization at driver init and suspend | |
968 | * time are on. They are kept on until after the first modeset. | |
969 | */ | |
970 | bool init_power_on; | |
c1ca727f | 971 | int power_well_count; |
baa70707 | 972 | |
83c00f55 | 973 | struct mutex lock; |
1da51581 ID |
974 | #if IS_ENABLED(CONFIG_DEBUG_FS) |
975 | int domain_use_count[POWER_DOMAIN_NUM]; | |
976 | #endif | |
c1ca727f | 977 | struct i915_power_well *power_wells; |
83c00f55 ID |
978 | }; |
979 | ||
231f42a4 DV |
980 | struct i915_dri1_state { |
981 | unsigned allow_batchbuffer : 1; | |
982 | u32 __iomem *gfx_hws_cpu_addr; | |
983 | ||
984 | unsigned int cpp; | |
985 | int back_offset; | |
986 | int front_offset; | |
987 | int current_page; | |
988 | int page_flipping; | |
989 | ||
990 | uint32_t counter; | |
991 | }; | |
992 | ||
db1b76ca DV |
993 | struct i915_ums_state { |
994 | /** | |
995 | * Flag if the X Server, and thus DRM, is not currently in | |
996 | * control of the device. | |
997 | * | |
998 | * This is set between LeaveVT and EnterVT. It needs to be | |
999 | * replaced with a semaphore. It also needs to be | |
1000 | * transitioned away from for kernel modesetting. | |
1001 | */ | |
1002 | int mm_suspended; | |
1003 | }; | |
1004 | ||
35a85ac6 | 1005 | #define MAX_L3_SLICES 2 |
a4da4fa4 | 1006 | struct intel_l3_parity { |
35a85ac6 | 1007 | u32 *remap_info[MAX_L3_SLICES]; |
a4da4fa4 | 1008 | struct work_struct error_work; |
35a85ac6 | 1009 | int which_slice; |
a4da4fa4 DV |
1010 | }; |
1011 | ||
4b5aed62 | 1012 | struct i915_gem_mm { |
4b5aed62 DV |
1013 | /** Memory allocator for GTT stolen memory */ |
1014 | struct drm_mm stolen; | |
4b5aed62 DV |
1015 | /** List of all objects in gtt_space. Used to restore gtt |
1016 | * mappings on resume */ | |
1017 | struct list_head bound_list; | |
1018 | /** | |
1019 | * List of objects which are not bound to the GTT (thus | |
1020 | * are idle and not used by the GPU) but still have | |
1021 | * (presumably uncached) pages still attached. | |
1022 | */ | |
1023 | struct list_head unbound_list; | |
1024 | ||
1025 | /** Usable portion of the GTT for GEM */ | |
1026 | unsigned long stolen_base; /* limited to low memory (32-bit) */ | |
1027 | ||
4b5aed62 DV |
1028 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
1029 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
1030 | ||
1031 | struct shrinker inactive_shrinker; | |
1032 | bool shrinker_no_lock_stealing; | |
1033 | ||
4b5aed62 DV |
1034 | /** LRU list of objects with fence regs on them. */ |
1035 | struct list_head fence_list; | |
1036 | ||
1037 | /** | |
1038 | * We leave the user IRQ off as much as possible, | |
1039 | * but this means that requests will finish and never | |
1040 | * be retired once the system goes idle. Set a timer to | |
1041 | * fire periodically while the ring is running. When it | |
1042 | * fires, go retire requests. | |
1043 | */ | |
1044 | struct delayed_work retire_work; | |
1045 | ||
b29c19b6 CW |
1046 | /** |
1047 | * When we detect an idle GPU, we want to turn on | |
1048 | * powersaving features. So once we see that there | |
1049 | * are no more requests outstanding and no more | |
1050 | * arrive within a small period of time, we fire | |
1051 | * off the idle_work. | |
1052 | */ | |
1053 | struct delayed_work idle_work; | |
1054 | ||
4b5aed62 DV |
1055 | /** |
1056 | * Are we in a non-interruptible section of code like | |
1057 | * modesetting? | |
1058 | */ | |
1059 | bool interruptible; | |
1060 | ||
4b5aed62 DV |
1061 | /** Bit 6 swizzling required for X tiling */ |
1062 | uint32_t bit_6_swizzle_x; | |
1063 | /** Bit 6 swizzling required for Y tiling */ | |
1064 | uint32_t bit_6_swizzle_y; | |
1065 | ||
1066 | /* storage for physical objects */ | |
1067 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; | |
1068 | ||
1069 | /* accounting, useful for userland debugging */ | |
c20e8355 | 1070 | spinlock_t object_stat_lock; |
4b5aed62 DV |
1071 | size_t object_memory; |
1072 | u32 object_count; | |
1073 | }; | |
1074 | ||
edc3d884 MK |
1075 | struct drm_i915_error_state_buf { |
1076 | unsigned bytes; | |
1077 | unsigned size; | |
1078 | int err; | |
1079 | u8 *buf; | |
1080 | loff_t start; | |
1081 | loff_t pos; | |
1082 | }; | |
1083 | ||
fc16b48b MK |
1084 | struct i915_error_state_file_priv { |
1085 | struct drm_device *dev; | |
1086 | struct drm_i915_error_state *error; | |
1087 | }; | |
1088 | ||
99584db3 DV |
1089 | struct i915_gpu_error { |
1090 | /* For hangcheck timer */ | |
1091 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ | |
1092 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) | |
be62acb4 MK |
1093 | /* Hang gpu twice in this window and your context gets banned */ |
1094 | #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) | |
1095 | ||
99584db3 | 1096 | struct timer_list hangcheck_timer; |
99584db3 DV |
1097 | |
1098 | /* For reset and error_state handling. */ | |
1099 | spinlock_t lock; | |
1100 | /* Protected by the above dev->gpu_error.lock. */ | |
1101 | struct drm_i915_error_state *first_error; | |
1102 | struct work_struct work; | |
99584db3 | 1103 | |
094f9a54 CW |
1104 | |
1105 | unsigned long missed_irq_rings; | |
1106 | ||
1f83fee0 | 1107 | /** |
2ac0f450 | 1108 | * State variable controlling the reset flow and count |
1f83fee0 | 1109 | * |
2ac0f450 MK |
1110 | * This is a counter which gets incremented when reset is triggered, |
1111 | * and again when reset has been handled. So odd values (lowest bit set) | |
1112 | * means that reset is in progress and even values that | |
1113 | * (reset_counter >> 1):th reset was successfully completed. | |
1114 | * | |
1115 | * If reset is not completed succesfully, the I915_WEDGE bit is | |
1116 | * set meaning that hardware is terminally sour and there is no | |
1117 | * recovery. All waiters on the reset_queue will be woken when | |
1118 | * that happens. | |
1119 | * | |
1120 | * This counter is used by the wait_seqno code to notice that reset | |
1121 | * event happened and it needs to restart the entire ioctl (since most | |
1122 | * likely the seqno it waited for won't ever signal anytime soon). | |
f69061be DV |
1123 | * |
1124 | * This is important for lock-free wait paths, where no contended lock | |
1125 | * naturally enforces the correct ordering between the bail-out of the | |
1126 | * waiter and the gpu reset work code. | |
1f83fee0 DV |
1127 | */ |
1128 | atomic_t reset_counter; | |
1129 | ||
1f83fee0 | 1130 | #define I915_RESET_IN_PROGRESS_FLAG 1 |
2ac0f450 | 1131 | #define I915_WEDGED (1 << 31) |
1f83fee0 DV |
1132 | |
1133 | /** | |
1134 | * Waitqueue to signal when the reset has completed. Used by clients | |
1135 | * that wait for dev_priv->mm.wedged to settle. | |
1136 | */ | |
1137 | wait_queue_head_t reset_queue; | |
33196ded | 1138 | |
99584db3 DV |
1139 | /* For gpu hang simulation. */ |
1140 | unsigned int stop_rings; | |
094f9a54 CW |
1141 | |
1142 | /* For missed irq/seqno simulation. */ | |
1143 | unsigned int test_irq_rings; | |
99584db3 DV |
1144 | }; |
1145 | ||
b8efb17b ZR |
1146 | enum modeset_restore { |
1147 | MODESET_ON_LID_OPEN, | |
1148 | MODESET_DONE, | |
1149 | MODESET_SUSPENDED, | |
1150 | }; | |
1151 | ||
6acab15a PZ |
1152 | struct ddi_vbt_port_info { |
1153 | uint8_t hdmi_level_shift; | |
311a2094 PZ |
1154 | |
1155 | uint8_t supports_dvi:1; | |
1156 | uint8_t supports_hdmi:1; | |
1157 | uint8_t supports_dp:1; | |
6acab15a PZ |
1158 | }; |
1159 | ||
41aa3448 RV |
1160 | struct intel_vbt_data { |
1161 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ | |
1162 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
1163 | ||
1164 | /* Feature bits */ | |
1165 | unsigned int int_tv_support:1; | |
1166 | unsigned int lvds_dither:1; | |
1167 | unsigned int lvds_vbt:1; | |
1168 | unsigned int int_crt_support:1; | |
1169 | unsigned int lvds_use_ssc:1; | |
1170 | unsigned int display_clock_mode:1; | |
1171 | unsigned int fdi_rx_polarity_inverted:1; | |
1172 | int lvds_ssc_freq; | |
1173 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ | |
1174 | ||
1175 | /* eDP */ | |
1176 | int edp_rate; | |
1177 | int edp_lanes; | |
1178 | int edp_preemphasis; | |
1179 | int edp_vswing; | |
1180 | bool edp_initialized; | |
1181 | bool edp_support; | |
1182 | int edp_bpp; | |
1183 | struct edp_power_seq edp_pps; | |
1184 | ||
d17c5443 SK |
1185 | /* MIPI DSI */ |
1186 | struct { | |
1187 | u16 panel_id; | |
1188 | } dsi; | |
1189 | ||
41aa3448 RV |
1190 | int crt_ddc_pin; |
1191 | ||
1192 | int child_dev_num; | |
768f69c9 | 1193 | union child_device_config *child_dev; |
6acab15a PZ |
1194 | |
1195 | struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; | |
41aa3448 RV |
1196 | }; |
1197 | ||
77c122bc VS |
1198 | enum intel_ddb_partitioning { |
1199 | INTEL_DDB_PART_1_2, | |
1200 | INTEL_DDB_PART_5_6, /* IVB+ */ | |
1201 | }; | |
1202 | ||
1fd527cc VS |
1203 | struct intel_wm_level { |
1204 | bool enable; | |
1205 | uint32_t pri_val; | |
1206 | uint32_t spr_val; | |
1207 | uint32_t cur_val; | |
1208 | uint32_t fbc_val; | |
1209 | }; | |
1210 | ||
609cedef VS |
1211 | struct hsw_wm_values { |
1212 | uint32_t wm_pipe[3]; | |
1213 | uint32_t wm_lp[3]; | |
1214 | uint32_t wm_lp_spr[3]; | |
1215 | uint32_t wm_linetime[3]; | |
1216 | bool enable_fbc_wm; | |
1217 | enum intel_ddb_partitioning partitioning; | |
1218 | }; | |
1219 | ||
c67a470b PZ |
1220 | /* |
1221 | * This struct tracks the state needed for the Package C8+ feature. | |
1222 | * | |
1223 | * Package states C8 and deeper are really deep PC states that can only be | |
1224 | * reached when all the devices on the system allow it, so even if the graphics | |
1225 | * device allows PC8+, it doesn't mean the system will actually get to these | |
1226 | * states. | |
1227 | * | |
1228 | * Our driver only allows PC8+ when all the outputs are disabled, the power well | |
1229 | * is disabled and the GPU is idle. When these conditions are met, we manually | |
1230 | * do the other conditions: disable the interrupts, clocks and switch LCPLL | |
1231 | * refclk to Fclk. | |
1232 | * | |
1233 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
1234 | * the state of some registers, so when we come back from PC8+ we need to | |
1235 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
1236 | * need to take care of the registers kept by RC6. | |
1237 | * | |
1238 | * The interrupt disabling is part of the requirements. We can only leave the | |
1239 | * PCH HPD interrupts enabled. If we're in PC8+ and we get another interrupt we | |
1240 | * can lock the machine. | |
1241 | * | |
1242 | * Ideally every piece of our code that needs PC8+ disabled would call | |
1243 | * hsw_disable_package_c8, which would increment disable_count and prevent the | |
1244 | * system from reaching PC8+. But we don't have a symmetric way to do this for | |
1245 | * everything, so we have the requirements_met and gpu_idle variables. When we | |
1246 | * switch requirements_met or gpu_idle to true we decrease disable_count, and | |
1247 | * increase it in the opposite case. The requirements_met variable is true when | |
1248 | * all the CRTCs, encoders and the power well are disabled. The gpu_idle | |
1249 | * variable is true when the GPU is idle. | |
1250 | * | |
1251 | * In addition to everything, we only actually enable PC8+ if disable_count | |
1252 | * stays at zero for at least some seconds. This is implemented with the | |
1253 | * enable_work variable. We do this so we don't enable/disable PC8 dozens of | |
1254 | * consecutive times when all screens are disabled and some background app | |
1255 | * queries the state of our connectors, or we have some application constantly | |
1256 | * waking up to use the GPU. Only after the enable_work function actually | |
1257 | * enables PC8+ the "enable" variable will become true, which means that it can | |
1258 | * be false even if disable_count is 0. | |
1259 | * | |
1260 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and | |
1261 | * goes back to false exactly before we reenable the IRQs. We use this variable | |
1262 | * to check if someone is trying to enable/disable IRQs while they're supposed | |
1263 | * to be disabled. This shouldn't happen and we'll print some error messages in | |
1264 | * case it happens, but if it actually happens we'll also update the variables | |
1265 | * inside struct regsave so when we restore the IRQs they will contain the | |
1266 | * latest expected values. | |
1267 | * | |
1268 | * For more, read "Display Sequences for Package C8" on our documentation. | |
1269 | */ | |
1270 | struct i915_package_c8 { | |
1271 | bool requirements_met; | |
1272 | bool gpu_idle; | |
1273 | bool irqs_disabled; | |
1274 | /* Only true after the delayed work task actually enables it. */ | |
1275 | bool enabled; | |
1276 | int disable_count; | |
1277 | struct mutex lock; | |
1278 | struct delayed_work enable_work; | |
1279 | ||
1280 | struct { | |
1281 | uint32_t deimr; | |
1282 | uint32_t sdeimr; | |
1283 | uint32_t gtimr; | |
1284 | uint32_t gtier; | |
1285 | uint32_t gen6_pmimr; | |
1286 | } regsave; | |
1287 | }; | |
1288 | ||
926321d5 DV |
1289 | enum intel_pipe_crc_source { |
1290 | INTEL_PIPE_CRC_SOURCE_NONE, | |
1291 | INTEL_PIPE_CRC_SOURCE_PLANE1, | |
1292 | INTEL_PIPE_CRC_SOURCE_PLANE2, | |
1293 | INTEL_PIPE_CRC_SOURCE_PF, | |
5b3a856b | 1294 | INTEL_PIPE_CRC_SOURCE_PIPE, |
3d099a05 DV |
1295 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ |
1296 | INTEL_PIPE_CRC_SOURCE_TV, | |
1297 | INTEL_PIPE_CRC_SOURCE_DP_B, | |
1298 | INTEL_PIPE_CRC_SOURCE_DP_C, | |
1299 | INTEL_PIPE_CRC_SOURCE_DP_D, | |
46a19188 | 1300 | INTEL_PIPE_CRC_SOURCE_AUTO, |
926321d5 DV |
1301 | INTEL_PIPE_CRC_SOURCE_MAX, |
1302 | }; | |
1303 | ||
8bf1e9f1 | 1304 | struct intel_pipe_crc_entry { |
ac2300d4 | 1305 | uint32_t frame; |
8bf1e9f1 SH |
1306 | uint32_t crc[5]; |
1307 | }; | |
1308 | ||
b2c88f5b | 1309 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 |
8bf1e9f1 | 1310 | struct intel_pipe_crc { |
d538bbdf DL |
1311 | spinlock_t lock; |
1312 | bool opened; /* exclusive access to the result file */ | |
e5f75aca | 1313 | struct intel_pipe_crc_entry *entries; |
926321d5 | 1314 | enum intel_pipe_crc_source source; |
d538bbdf | 1315 | int head, tail; |
07144428 | 1316 | wait_queue_head_t wq; |
8bf1e9f1 SH |
1317 | }; |
1318 | ||
f4c956ad DV |
1319 | typedef struct drm_i915_private { |
1320 | struct drm_device *dev; | |
42dcedd4 | 1321 | struct kmem_cache *slab; |
f4c956ad DV |
1322 | |
1323 | const struct intel_device_info *info; | |
1324 | ||
1325 | int relative_constants_mode; | |
1326 | ||
1327 | void __iomem *regs; | |
1328 | ||
907b28c5 | 1329 | struct intel_uncore uncore; |
f4c956ad DV |
1330 | |
1331 | struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; | |
1332 | ||
28c70f16 | 1333 | |
f4c956ad DV |
1334 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
1335 | * controller on different i2c buses. */ | |
1336 | struct mutex gmbus_mutex; | |
1337 | ||
1338 | /** | |
1339 | * Base address of the gmbus and gpio block. | |
1340 | */ | |
1341 | uint32_t gpio_mmio_base; | |
1342 | ||
28c70f16 DV |
1343 | wait_queue_head_t gmbus_wait_queue; |
1344 | ||
f4c956ad DV |
1345 | struct pci_dev *bridge_dev; |
1346 | struct intel_ring_buffer ring[I915_NUM_RINGS]; | |
f72b3435 | 1347 | uint32_t last_seqno, next_seqno; |
f4c956ad DV |
1348 | |
1349 | drm_dma_handle_t *status_page_dmah; | |
f4c956ad DV |
1350 | struct resource mch_res; |
1351 | ||
1352 | atomic_t irq_received; | |
1353 | ||
1354 | /* protects the irq masks */ | |
1355 | spinlock_t irq_lock; | |
1356 | ||
9ee32fea DV |
1357 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
1358 | struct pm_qos_request pm_qos; | |
1359 | ||
f4c956ad | 1360 | /* DPIO indirect register protection */ |
09153000 | 1361 | struct mutex dpio_lock; |
f4c956ad DV |
1362 | |
1363 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
abd58f01 BW |
1364 | union { |
1365 | u32 irq_mask; | |
1366 | u32 de_irq_mask[I915_MAX_PIPES]; | |
1367 | }; | |
f4c956ad | 1368 | u32 gt_irq_mask; |
605cd25b | 1369 | u32 pm_irq_mask; |
f4c956ad | 1370 | |
f4c956ad | 1371 | struct work_struct hotplug_work; |
52d7eced | 1372 | bool enable_hotplug_processing; |
b543fb04 EE |
1373 | struct { |
1374 | unsigned long hpd_last_jiffies; | |
1375 | int hpd_cnt; | |
1376 | enum { | |
1377 | HPD_ENABLED = 0, | |
1378 | HPD_DISABLED = 1, | |
1379 | HPD_MARK_DISABLED = 2 | |
1380 | } hpd_mark; | |
1381 | } hpd_stats[HPD_NUM_PINS]; | |
142e2398 | 1382 | u32 hpd_event_bits; |
ac4c16c5 | 1383 | struct timer_list hotplug_reenable_timer; |
f4c956ad | 1384 | |
7f1f3851 | 1385 | int num_plane; |
f4c956ad | 1386 | |
5c3fe8b0 | 1387 | struct i915_fbc fbc; |
f4c956ad | 1388 | struct intel_opregion opregion; |
41aa3448 | 1389 | struct intel_vbt_data vbt; |
f4c956ad DV |
1390 | |
1391 | /* overlay */ | |
1392 | struct intel_overlay *overlay; | |
2c6602df | 1393 | unsigned int sprite_scaling_enabled; |
f4c956ad | 1394 | |
58c68779 JN |
1395 | /* backlight registers and fields in struct intel_panel */ |
1396 | spinlock_t backlight_lock; | |
31ad8ec6 | 1397 | |
f4c956ad | 1398 | /* LVDS info */ |
f4c956ad DV |
1399 | bool no_aux_handshake; |
1400 | ||
f4c956ad DV |
1401 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
1402 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ | |
1403 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
1404 | ||
1405 | unsigned int fsb_freq, mem_freq, is_ddr3; | |
1406 | ||
645416f5 DV |
1407 | /** |
1408 | * wq - Driver workqueue for GEM. | |
1409 | * | |
1410 | * NOTE: Work items scheduled here are not allowed to grab any modeset | |
1411 | * locks, for otherwise the flushing done in the pageflip code will | |
1412 | * result in deadlocks. | |
1413 | */ | |
f4c956ad DV |
1414 | struct workqueue_struct *wq; |
1415 | ||
1416 | /* Display functions */ | |
1417 | struct drm_i915_display_funcs display; | |
1418 | ||
1419 | /* PCH chipset type */ | |
1420 | enum intel_pch pch_type; | |
17a303ec | 1421 | unsigned short pch_id; |
f4c956ad DV |
1422 | |
1423 | unsigned long quirks; | |
1424 | ||
b8efb17b ZR |
1425 | enum modeset_restore modeset_restore; |
1426 | struct mutex modeset_restore_lock; | |
673a394b | 1427 | |
a7bbbd63 | 1428 | struct list_head vm_list; /* Global list of all address spaces */ |
853ba5d2 | 1429 | struct i915_gtt gtt; /* VMA representing the global address space */ |
5d4545ae | 1430 | |
4b5aed62 | 1431 | struct i915_gem_mm mm; |
8781342d | 1432 | |
8781342d DV |
1433 | /* Kernel Modesetting */ |
1434 | ||
9b9d172d | 1435 | struct sdvo_device_mapping sdvo_mappings[2]; |
652c393a | 1436 | |
27f8227b JB |
1437 | struct drm_crtc *plane_to_crtc_mapping[3]; |
1438 | struct drm_crtc *pipe_to_crtc_mapping[3]; | |
6b95a207 KH |
1439 | wait_queue_head_t pending_flip_queue; |
1440 | ||
c4597872 DV |
1441 | #ifdef CONFIG_DEBUG_FS |
1442 | struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; | |
1443 | #endif | |
1444 | ||
e72f9fbf DV |
1445 | int num_shared_dpll; |
1446 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; | |
6441ab5f | 1447 | struct intel_ddi_plls ddi_plls; |
e4607fcf | 1448 | int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; |
ee7b9f93 | 1449 | |
652c393a JB |
1450 | /* Reclocking support */ |
1451 | bool render_reclock_avail; | |
1452 | bool lvds_downclock_avail; | |
18f9ed12 ZY |
1453 | /* indicates the reduced downclock for LVDS*/ |
1454 | int lvds_downclock; | |
652c393a | 1455 | u16 orig_clock; |
f97108d1 | 1456 | |
c4804411 | 1457 | bool mchbar_need_disable; |
f97108d1 | 1458 | |
a4da4fa4 DV |
1459 | struct intel_l3_parity l3_parity; |
1460 | ||
59124506 BW |
1461 | /* Cannot be determined by PCIID. You must always read a register. */ |
1462 | size_t ellc_size; | |
1463 | ||
c6a828d3 | 1464 | /* gen6+ rps state */ |
c85aa885 | 1465 | struct intel_gen6_power_mgmt rps; |
c6a828d3 | 1466 | |
20e4d407 DV |
1467 | /* ilk-only ips/rps state. Everything in here is protected by the global |
1468 | * mchdev_lock in intel_pm.c */ | |
c85aa885 | 1469 | struct intel_ilk_power_mgmt ips; |
b5e50c3f | 1470 | |
83c00f55 | 1471 | struct i915_power_domains power_domains; |
a38911a3 | 1472 | |
a031d709 | 1473 | struct i915_psr psr; |
3f51e471 | 1474 | |
99584db3 | 1475 | struct i915_gpu_error gpu_error; |
ae681d96 | 1476 | |
c9cddffc JB |
1477 | struct drm_i915_gem_object *vlv_pctx; |
1478 | ||
4520f53a | 1479 | #ifdef CONFIG_DRM_I915_FBDEV |
8be48d92 DA |
1480 | /* list of fbdev register on this device */ |
1481 | struct intel_fbdev *fbdev; | |
4520f53a | 1482 | #endif |
e953fd7b | 1483 | |
073f34d9 JB |
1484 | /* |
1485 | * The console may be contended at resume, but we don't | |
1486 | * want it to block on it. | |
1487 | */ | |
1488 | struct work_struct console_resume_work; | |
1489 | ||
e953fd7b | 1490 | struct drm_property *broadcast_rgb_property; |
3f43c48d | 1491 | struct drm_property *force_audio_property; |
e3689190 | 1492 | |
254f965c | 1493 | uint32_t hw_context_size; |
a33afea5 | 1494 | struct list_head context_list; |
f4c956ad | 1495 | |
3e68320e | 1496 | u32 fdi_rx_config; |
68d18ad7 | 1497 | |
f4c956ad | 1498 | struct i915_suspend_saved_registers regfile; |
231f42a4 | 1499 | |
53615a5e VS |
1500 | struct { |
1501 | /* | |
1502 | * Raw watermark latency values: | |
1503 | * in 0.1us units for WM0, | |
1504 | * in 0.5us units for WM1+. | |
1505 | */ | |
1506 | /* primary */ | |
1507 | uint16_t pri_latency[5]; | |
1508 | /* sprite */ | |
1509 | uint16_t spr_latency[5]; | |
1510 | /* cursor */ | |
1511 | uint16_t cur_latency[5]; | |
609cedef VS |
1512 | |
1513 | /* current hardware state */ | |
1514 | struct hsw_wm_values hw; | |
53615a5e VS |
1515 | } wm; |
1516 | ||
c67a470b PZ |
1517 | struct i915_package_c8 pc8; |
1518 | ||
231f42a4 DV |
1519 | /* Old dri1 support infrastructure, beware the dragons ya fools entering |
1520 | * here! */ | |
1521 | struct i915_dri1_state dri1; | |
db1b76ca DV |
1522 | /* Old ums support infrastructure, same warning applies. */ |
1523 | struct i915_ums_state ums; | |
1da177e4 LT |
1524 | } drm_i915_private_t; |
1525 | ||
2c1792a1 CW |
1526 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) |
1527 | { | |
1528 | return dev->dev_private; | |
1529 | } | |
1530 | ||
b4519513 CW |
1531 | /* Iterate over initialised rings */ |
1532 | #define for_each_ring(ring__, dev_priv__, i__) \ | |
1533 | for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ | |
1534 | if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) | |
1535 | ||
b1d7e4b4 WF |
1536 | enum hdmi_force_audio { |
1537 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
1538 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
1539 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
1540 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
1541 | }; | |
1542 | ||
190d6cd5 | 1543 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
ed2f3452 | 1544 | |
37e680a1 CW |
1545 | struct drm_i915_gem_object_ops { |
1546 | /* Interface between the GEM object and its backing storage. | |
1547 | * get_pages() is called once prior to the use of the associated set | |
1548 | * of pages before to binding them into the GTT, and put_pages() is | |
1549 | * called after we no longer need them. As we expect there to be | |
1550 | * associated cost with migrating pages between the backing storage | |
1551 | * and making them available for the GPU (e.g. clflush), we may hold | |
1552 | * onto the pages after they are no longer referenced by the GPU | |
1553 | * in case they may be used again shortly (for example migrating the | |
1554 | * pages to a different memory domain within the GTT). put_pages() | |
1555 | * will therefore most likely be called when the object itself is | |
1556 | * being released or under memory pressure (where we attempt to | |
1557 | * reap pages for the shrinker). | |
1558 | */ | |
1559 | int (*get_pages)(struct drm_i915_gem_object *); | |
1560 | void (*put_pages)(struct drm_i915_gem_object *); | |
1561 | }; | |
1562 | ||
673a394b | 1563 | struct drm_i915_gem_object { |
c397b908 | 1564 | struct drm_gem_object base; |
673a394b | 1565 | |
37e680a1 CW |
1566 | const struct drm_i915_gem_object_ops *ops; |
1567 | ||
2f633156 BW |
1568 | /** List of VMAs backed by this object */ |
1569 | struct list_head vma_list; | |
1570 | ||
c1ad11fc CW |
1571 | /** Stolen memory for this object, instead of being backed by shmem. */ |
1572 | struct drm_mm_node *stolen; | |
35c20a60 | 1573 | struct list_head global_list; |
673a394b | 1574 | |
69dc4987 | 1575 | struct list_head ring_list; |
b25cb2f8 BW |
1576 | /** Used in execbuf to temporarily hold a ref */ |
1577 | struct list_head obj_exec_link; | |
673a394b EA |
1578 | |
1579 | /** | |
65ce3027 CW |
1580 | * This is set if the object is on the active lists (has pending |
1581 | * rendering and so a non-zero seqno), and is not set if it i s on | |
1582 | * inactive (ready to be unbound) list. | |
673a394b | 1583 | */ |
0206e353 | 1584 | unsigned int active:1; |
673a394b EA |
1585 | |
1586 | /** | |
1587 | * This is set if the object has been written to since last bound | |
1588 | * to the GTT | |
1589 | */ | |
0206e353 | 1590 | unsigned int dirty:1; |
778c3544 DV |
1591 | |
1592 | /** | |
1593 | * Fence register bits (if any) for this object. Will be set | |
1594 | * as needed when mapped into the GTT. | |
1595 | * Protected by dev->struct_mutex. | |
778c3544 | 1596 | */ |
4b9de737 | 1597 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
778c3544 | 1598 | |
778c3544 DV |
1599 | /** |
1600 | * Advice: are the backing pages purgeable? | |
1601 | */ | |
0206e353 | 1602 | unsigned int madv:2; |
778c3544 | 1603 | |
778c3544 DV |
1604 | /** |
1605 | * Current tiling mode for the object. | |
1606 | */ | |
0206e353 | 1607 | unsigned int tiling_mode:2; |
5d82e3e6 CW |
1608 | /** |
1609 | * Whether the tiling parameters for the currently associated fence | |
1610 | * register have changed. Note that for the purposes of tracking | |
1611 | * tiling changes we also treat the unfenced register, the register | |
1612 | * slot that the object occupies whilst it executes a fenced | |
1613 | * command (such as BLT on gen2/3), as a "fence". | |
1614 | */ | |
1615 | unsigned int fence_dirty:1; | |
778c3544 DV |
1616 | |
1617 | /** How many users have pinned this object in GTT space. The following | |
1618 | * users can each hold at most one reference: pwrite/pread, pin_ioctl | |
1619 | * (via user_pin_count), execbuffer (objects are not allowed multiple | |
1620 | * times for the same batchbuffer), and the framebuffer code. When | |
1621 | * switching/pageflipping, the framebuffer code has at most two buffers | |
1622 | * pinned per crtc. | |
1623 | * | |
1624 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 | |
1625 | * bits with absolutely no headroom. So use 4 bits. */ | |
0206e353 | 1626 | unsigned int pin_count:4; |
778c3544 | 1627 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
673a394b | 1628 | |
75e9e915 DV |
1629 | /** |
1630 | * Is the object at the current location in the gtt mappable and | |
1631 | * fenceable? Used to avoid costly recalculations. | |
1632 | */ | |
0206e353 | 1633 | unsigned int map_and_fenceable:1; |
75e9e915 | 1634 | |
fb7d516a DV |
1635 | /** |
1636 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
1637 | * mappable by accident). Track pin and fault separate for a more | |
1638 | * accurate mappable working set. | |
1639 | */ | |
0206e353 AJ |
1640 | unsigned int fault_mappable:1; |
1641 | unsigned int pin_mappable:1; | |
cc98b413 | 1642 | unsigned int pin_display:1; |
fb7d516a | 1643 | |
caea7476 CW |
1644 | /* |
1645 | * Is the GPU currently using a fence to access this buffer, | |
1646 | */ | |
1647 | unsigned int pending_fenced_gpu_access:1; | |
1648 | unsigned int fenced_gpu_access:1; | |
1649 | ||
651d794f | 1650 | unsigned int cache_level:3; |
93dfb40c | 1651 | |
7bddb01f | 1652 | unsigned int has_aliasing_ppgtt_mapping:1; |
74898d7e | 1653 | unsigned int has_global_gtt_mapping:1; |
9da3da66 | 1654 | unsigned int has_dma_mapping:1; |
7bddb01f | 1655 | |
9da3da66 | 1656 | struct sg_table *pages; |
a5570178 | 1657 | int pages_pin_count; |
673a394b | 1658 | |
1286ff73 | 1659 | /* prime dma-buf support */ |
9a70cc2a DA |
1660 | void *dma_buf_vmapping; |
1661 | int vmapping_count; | |
1662 | ||
caea7476 CW |
1663 | struct intel_ring_buffer *ring; |
1664 | ||
1c293ea3 | 1665 | /** Breadcrumb of last rendering to the buffer. */ |
0201f1ec CW |
1666 | uint32_t last_read_seqno; |
1667 | uint32_t last_write_seqno; | |
caea7476 CW |
1668 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
1669 | uint32_t last_fenced_seqno; | |
673a394b | 1670 | |
778c3544 | 1671 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 1672 | uint32_t stride; |
673a394b | 1673 | |
80075d49 DV |
1674 | /** References from framebuffers, locks out tiling changes. */ |
1675 | unsigned long framebuffer_references; | |
1676 | ||
280b713b | 1677 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 1678 | unsigned long *bit_17; |
280b713b | 1679 | |
79e53945 | 1680 | /** User space pin count and filp owning the pin */ |
aa5f8021 | 1681 | unsigned long user_pin_count; |
79e53945 | 1682 | struct drm_file *pin_filp; |
71acb5eb DA |
1683 | |
1684 | /** for phy allocated objects */ | |
1685 | struct drm_i915_gem_phys_object *phys_obj; | |
673a394b | 1686 | }; |
b45305fc | 1687 | #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base) |
673a394b | 1688 | |
62b8b215 | 1689 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 1690 | |
673a394b EA |
1691 | /** |
1692 | * Request queue structure. | |
1693 | * | |
1694 | * The request queue allows us to note sequence numbers that have been emitted | |
1695 | * and may be associated with active buffers to be retired. | |
1696 | * | |
1697 | * By keeping this list, we can avoid having to do questionable | |
1698 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate | |
1699 | * an emission time with seqnos for tracking how far ahead of the GPU we are. | |
1700 | */ | |
1701 | struct drm_i915_gem_request { | |
852835f3 ZN |
1702 | /** On Which ring this request was generated */ |
1703 | struct intel_ring_buffer *ring; | |
1704 | ||
673a394b EA |
1705 | /** GEM sequence number associated with this request. */ |
1706 | uint32_t seqno; | |
1707 | ||
7d736f4f MK |
1708 | /** Position in the ringbuffer of the start of the request */ |
1709 | u32 head; | |
1710 | ||
1711 | /** Position in the ringbuffer of the end of the request */ | |
a71d8d94 CW |
1712 | u32 tail; |
1713 | ||
0e50e96b MK |
1714 | /** Context related to this request */ |
1715 | struct i915_hw_context *ctx; | |
1716 | ||
7d736f4f MK |
1717 | /** Batch buffer related to this request if any */ |
1718 | struct drm_i915_gem_object *batch_obj; | |
1719 | ||
673a394b EA |
1720 | /** Time at which this request was emitted, in jiffies. */ |
1721 | unsigned long emitted_jiffies; | |
1722 | ||
b962442e | 1723 | /** global list entry for this request */ |
673a394b | 1724 | struct list_head list; |
b962442e | 1725 | |
f787a5f5 | 1726 | struct drm_i915_file_private *file_priv; |
b962442e EA |
1727 | /** file_priv list entry for this request */ |
1728 | struct list_head client_list; | |
673a394b EA |
1729 | }; |
1730 | ||
1731 | struct drm_i915_file_private { | |
b29c19b6 CW |
1732 | struct drm_i915_private *dev_priv; |
1733 | ||
673a394b | 1734 | struct { |
99057c81 | 1735 | spinlock_t lock; |
b962442e | 1736 | struct list_head request_list; |
b29c19b6 | 1737 | struct delayed_work idle_work; |
673a394b | 1738 | } mm; |
40521054 | 1739 | struct idr context_idr; |
e59ec13d MK |
1740 | |
1741 | struct i915_ctx_hang_stats hang_stats; | |
b29c19b6 | 1742 | atomic_t rps_wait_boost; |
673a394b EA |
1743 | }; |
1744 | ||
2c1792a1 | 1745 | #define INTEL_INFO(dev) (to_i915(dev)->info) |
cae5852d | 1746 | |
ffbab09b VS |
1747 | #define IS_I830(dev) ((dev)->pdev->device == 0x3577) |
1748 | #define IS_845G(dev) ((dev)->pdev->device == 0x2562) | |
cae5852d | 1749 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
ffbab09b | 1750 | #define IS_I865G(dev) ((dev)->pdev->device == 0x2572) |
cae5852d | 1751 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
ffbab09b VS |
1752 | #define IS_I915GM(dev) ((dev)->pdev->device == 0x2592) |
1753 | #define IS_I945G(dev) ((dev)->pdev->device == 0x2772) | |
cae5852d ZN |
1754 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
1755 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
1756 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
ffbab09b | 1757 | #define IS_GM45(dev) ((dev)->pdev->device == 0x2A42) |
cae5852d | 1758 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
ffbab09b VS |
1759 | #define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001) |
1760 | #define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011) | |
cae5852d ZN |
1761 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
1762 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
ffbab09b | 1763 | #define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046) |
4b65177b | 1764 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
ffbab09b VS |
1765 | #define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \ |
1766 | (dev)->pdev->device == 0x0152 || \ | |
1767 | (dev)->pdev->device == 0x015a) | |
1768 | #define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \ | |
1769 | (dev)->pdev->device == 0x0106 || \ | |
1770 | (dev)->pdev->device == 0x010A) | |
70a3eb7a | 1771 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
4cae9ae0 | 1772 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
4e8058a2 | 1773 | #define IS_BROADWELL(dev) (INTEL_INFO(dev)->gen == 8) |
cae5852d | 1774 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
ed1c9e2c | 1775 | #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ |
ffbab09b | 1776 | ((dev)->pdev->device & 0xFF00) == 0x0C00) |
5dd8c4c3 BW |
1777 | #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ |
1778 | (((dev)->pdev->device & 0xf) == 0x2 || \ | |
1779 | ((dev)->pdev->device & 0xf) == 0x6 || \ | |
1780 | ((dev)->pdev->device & 0xf) == 0xe)) | |
1781 | #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ | |
ffbab09b | 1782 | ((dev)->pdev->device & 0xFF00) == 0x0A00) |
5dd8c4c3 | 1783 | #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
9435373e | 1784 | #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ |
ffbab09b | 1785 | ((dev)->pdev->device & 0x00F0) == 0x0020) |
b833d685 | 1786 | #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) |
cae5852d | 1787 | |
85436696 JB |
1788 | /* |
1789 | * The genX designation typically refers to the render engine, so render | |
1790 | * capability related checks should use IS_GEN, while display and other checks | |
1791 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
1792 | * chips, etc.). | |
1793 | */ | |
cae5852d ZN |
1794 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
1795 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) | |
1796 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) | |
1797 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) | |
1798 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) | |
85436696 | 1799 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
d2980845 | 1800 | #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8) |
cae5852d | 1801 | |
73ae478c BW |
1802 | #define RENDER_RING (1<<RCS) |
1803 | #define BSD_RING (1<<VCS) | |
1804 | #define BLT_RING (1<<BCS) | |
1805 | #define VEBOX_RING (1<<VECS) | |
1806 | #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) | |
1807 | #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) | |
1808 | #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) | |
3d29b842 | 1809 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) |
651d794f | 1810 | #define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size) |
cae5852d ZN |
1811 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
1812 | ||
254f965c | 1813 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
93553609 | 1814 | #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev)) |
1d2a314c | 1815 | |
05394f39 | 1816 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
cae5852d ZN |
1817 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
1818 | ||
b45305fc DV |
1819 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
1820 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) | |
1821 | ||
cae5852d ZN |
1822 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
1823 | * rows, which changed the alignment requirements and fence programming. | |
1824 | */ | |
1825 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
1826 | IS_I915GM(dev))) | |
1827 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) | |
1828 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
1829 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
cae5852d ZN |
1830 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
1831 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
cae5852d ZN |
1832 | |
1833 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
1834 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
1835 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) | |
cae5852d | 1836 | |
2a114cc1 | 1837 | #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev)) |
f5adf94e | 1838 | |
dd93be58 | 1839 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) |
30568c45 | 1840 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) |
ed8546ac | 1841 | #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
affa9354 | 1842 | |
17a303ec PZ |
1843 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
1844 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 | |
1845 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
1846 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 | |
1847 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 | |
1848 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 | |
1849 | ||
2c1792a1 | 1850 | #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type) |
eb877ebf | 1851 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
cae5852d ZN |
1852 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
1853 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
40c7ead9 | 1854 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
45e6e3a1 | 1855 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
cae5852d | 1856 | |
040d2baa BW |
1857 | /* DPF == dynamic parity feature */ |
1858 | #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
1859 | #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) | |
e1ef7cc2 | 1860 | |
c8735b0c BW |
1861 | #define GT_FREQUENCY_MULTIPLIER 50 |
1862 | ||
05394f39 CW |
1863 | #include "i915_trace.h" |
1864 | ||
baa70943 | 1865 | extern const struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 | 1866 | extern int i915_max_ioctl; |
a35d9d3c BW |
1867 | extern unsigned int i915_fbpercrtc __always_unused; |
1868 | extern int i915_panel_ignore_lid __read_mostly; | |
1869 | extern unsigned int i915_powersave __read_mostly; | |
f45b5557 | 1870 | extern int i915_semaphores __read_mostly; |
a35d9d3c | 1871 | extern unsigned int i915_lvds_downclock __read_mostly; |
121d527a | 1872 | extern int i915_lvds_channel_mode __read_mostly; |
4415e63b | 1873 | extern int i915_panel_use_ssc __read_mostly; |
a35d9d3c | 1874 | extern int i915_vbt_sdvo_panel_type __read_mostly; |
c0f372b3 | 1875 | extern int i915_enable_rc6 __read_mostly; |
4415e63b | 1876 | extern int i915_enable_fbc __read_mostly; |
a35d9d3c | 1877 | extern bool i915_enable_hangcheck __read_mostly; |
650dc07e | 1878 | extern int i915_enable_ppgtt __read_mostly; |
105b7c11 | 1879 | extern int i915_enable_psr __read_mostly; |
0a3af268 | 1880 | extern unsigned int i915_preliminary_hw_support __read_mostly; |
2124b72e | 1881 | extern int i915_disable_power_well __read_mostly; |
3c4ca58c | 1882 | extern int i915_enable_ips __read_mostly; |
2385bdf0 | 1883 | extern bool i915_fastboot __read_mostly; |
c67a470b | 1884 | extern int i915_enable_pc8 __read_mostly; |
90058745 | 1885 | extern int i915_pc8_timeout __read_mostly; |
0b74b508 | 1886 | extern bool i915_prefault_disable __read_mostly; |
b3a83639 | 1887 | |
6a9ee8af DA |
1888 | extern int i915_suspend(struct drm_device *dev, pm_message_t state); |
1889 | extern int i915_resume(struct drm_device *dev); | |
7c1c2871 DA |
1890 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
1891 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); | |
1892 | ||
1da177e4 | 1893 | /* i915_dma.c */ |
d05c617e | 1894 | void i915_update_dri1_breadcrumb(struct drm_device *dev); |
84b1fd10 | 1895 | extern void i915_kernel_lost_context(struct drm_device * dev); |
22eae947 | 1896 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 1897 | extern int i915_driver_unload(struct drm_device *); |
673a394b | 1898 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
84b1fd10 | 1899 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac EA |
1900 | extern void i915_driver_preclose(struct drm_device *dev, |
1901 | struct drm_file *file_priv); | |
673a394b EA |
1902 | extern void i915_driver_postclose(struct drm_device *dev, |
1903 | struct drm_file *file_priv); | |
84b1fd10 | 1904 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
c43b5634 | 1905 | #ifdef CONFIG_COMPAT |
0d6aa60b DA |
1906 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
1907 | unsigned long arg); | |
c43b5634 | 1908 | #endif |
673a394b | 1909 | extern int i915_emit_box(struct drm_device *dev, |
c4e7a414 CW |
1910 | struct drm_clip_rect *box, |
1911 | int DR1, int DR4); | |
8e96d9c4 | 1912 | extern int intel_gpu_reset(struct drm_device *dev); |
d4b8bb2a | 1913 | extern int i915_reset(struct drm_device *dev); |
7648fa99 JB |
1914 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
1915 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
1916 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
1917 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
1918 | ||
073f34d9 | 1919 | extern void intel_console_resume(struct work_struct *work); |
af6061af | 1920 | |
1da177e4 | 1921 | /* i915_irq.c */ |
10cd45b6 | 1922 | void i915_queue_hangcheck(struct drm_device *dev); |
527f9e90 | 1923 | void i915_handle_error(struct drm_device *dev, bool wedged); |
1da177e4 | 1924 | |
f71d4af4 | 1925 | extern void intel_irq_init(struct drm_device *dev); |
e1b4d303 | 1926 | extern void intel_pm_init(struct drm_device *dev); |
20afbda2 | 1927 | extern void intel_hpd_init(struct drm_device *dev); |
907b28c5 CW |
1928 | extern void intel_pm_init(struct drm_device *dev); |
1929 | ||
1930 | extern void intel_uncore_sanitize(struct drm_device *dev); | |
1931 | extern void intel_uncore_early_sanitize(struct drm_device *dev); | |
1932 | extern void intel_uncore_init(struct drm_device *dev); | |
907b28c5 | 1933 | extern void intel_uncore_check_errors(struct drm_device *dev); |
aec347ab | 1934 | extern void intel_uncore_fini(struct drm_device *dev); |
b1f14ad0 | 1935 | |
7c463586 | 1936 | void |
3b6c42e8 | 1937 | i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask); |
7c463586 KP |
1938 | |
1939 | void | |
3b6c42e8 | 1940 | i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, u32 mask); |
7c463586 | 1941 | |
673a394b EA |
1942 | /* i915_gem.c */ |
1943 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
1944 | struct drm_file *file_priv); | |
1945 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
1946 | struct drm_file *file_priv); | |
1947 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
1948 | struct drm_file *file_priv); | |
1949 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
1950 | struct drm_file *file_priv); | |
1951 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1952 | struct drm_file *file_priv); | |
de151cf6 JB |
1953 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
1954 | struct drm_file *file_priv); | |
673a394b EA |
1955 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
1956 | struct drm_file *file_priv); | |
1957 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1958 | struct drm_file *file_priv); | |
1959 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1960 | struct drm_file *file_priv); | |
76446cac JB |
1961 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
1962 | struct drm_file *file_priv); | |
673a394b EA |
1963 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
1964 | struct drm_file *file_priv); | |
1965 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
1966 | struct drm_file *file_priv); | |
1967 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
1968 | struct drm_file *file_priv); | |
199adf40 BW |
1969 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
1970 | struct drm_file *file); | |
1971 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, | |
1972 | struct drm_file *file); | |
673a394b EA |
1973 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
1974 | struct drm_file *file_priv); | |
3ef94daa CW |
1975 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
1976 | struct drm_file *file_priv); | |
673a394b EA |
1977 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
1978 | struct drm_file *file_priv); | |
1979 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
1980 | struct drm_file *file_priv); | |
1981 | int i915_gem_set_tiling(struct drm_device *dev, void *data, | |
1982 | struct drm_file *file_priv); | |
1983 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
1984 | struct drm_file *file_priv); | |
5a125c3c EA |
1985 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
1986 | struct drm_file *file_priv); | |
23ba4fd0 BW |
1987 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
1988 | struct drm_file *file_priv); | |
673a394b | 1989 | void i915_gem_load(struct drm_device *dev); |
42dcedd4 CW |
1990 | void *i915_gem_object_alloc(struct drm_device *dev); |
1991 | void i915_gem_object_free(struct drm_i915_gem_object *obj); | |
37e680a1 CW |
1992 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
1993 | const struct drm_i915_gem_object_ops *ops); | |
05394f39 CW |
1994 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
1995 | size_t size); | |
673a394b | 1996 | void i915_gem_free_object(struct drm_gem_object *obj); |
2f633156 | 1997 | void i915_gem_vma_destroy(struct i915_vma *vma); |
42dcedd4 | 1998 | |
2021746e | 1999 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, |
c37e2204 | 2000 | struct i915_address_space *vm, |
2021746e | 2001 | uint32_t alignment, |
86a1ee26 CW |
2002 | bool map_and_fenceable, |
2003 | bool nonblocking); | |
05394f39 | 2004 | void i915_gem_object_unpin(struct drm_i915_gem_object *obj); |
07fe0b12 BW |
2005 | int __must_check i915_vma_unbind(struct i915_vma *vma); |
2006 | int __must_check i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj); | |
dd624afd | 2007 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); |
05394f39 | 2008 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
673a394b | 2009 | void i915_gem_lastclose(struct drm_device *dev); |
f787a5f5 | 2010 | |
37e680a1 | 2011 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
9da3da66 CW |
2012 | static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) |
2013 | { | |
67d5a50c ID |
2014 | struct sg_page_iter sg_iter; |
2015 | ||
2016 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n) | |
2db76d7c | 2017 | return sg_page_iter_page(&sg_iter); |
67d5a50c ID |
2018 | |
2019 | return NULL; | |
9da3da66 | 2020 | } |
a5570178 CW |
2021 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
2022 | { | |
2023 | BUG_ON(obj->pages == NULL); | |
2024 | obj->pages_pin_count++; | |
2025 | } | |
2026 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) | |
2027 | { | |
2028 | BUG_ON(obj->pages_pin_count == 0); | |
2029 | obj->pages_pin_count--; | |
2030 | } | |
2031 | ||
54cf91dc | 2032 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
2911a35b BW |
2033 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
2034 | struct intel_ring_buffer *to); | |
e2d05a8b BW |
2035 | void i915_vma_move_to_active(struct i915_vma *vma, |
2036 | struct intel_ring_buffer *ring); | |
ff72145b DA |
2037 | int i915_gem_dumb_create(struct drm_file *file_priv, |
2038 | struct drm_device *dev, | |
2039 | struct drm_mode_create_dumb *args); | |
2040 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, | |
2041 | uint32_t handle, uint64_t *offset); | |
f787a5f5 CW |
2042 | /** |
2043 | * Returns true if seq1 is later than seq2. | |
2044 | */ | |
2045 | static inline bool | |
2046 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
2047 | { | |
2048 | return (int32_t)(seq1 - seq2) >= 0; | |
2049 | } | |
2050 | ||
fca26bb4 MK |
2051 | int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); |
2052 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); | |
06d98131 | 2053 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); |
d9e86c0e | 2054 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
2021746e | 2055 | |
9a5a53b3 | 2056 | static inline bool |
1690e1eb CW |
2057 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) |
2058 | { | |
2059 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
2060 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2061 | dev_priv->fence_regs[obj->fence_reg].pin_count++; | |
9a5a53b3 CW |
2062 | return true; |
2063 | } else | |
2064 | return false; | |
1690e1eb CW |
2065 | } |
2066 | ||
2067 | static inline void | |
2068 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) | |
2069 | { | |
2070 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
2071 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
b8c3af76 | 2072 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0); |
1690e1eb CW |
2073 | dev_priv->fence_regs[obj->fence_reg].pin_count--; |
2074 | } | |
2075 | } | |
2076 | ||
b29c19b6 | 2077 | bool i915_gem_retire_requests(struct drm_device *dev); |
a71d8d94 | 2078 | void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); |
33196ded | 2079 | int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, |
d6b2c790 | 2080 | bool interruptible); |
1f83fee0 DV |
2081 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
2082 | { | |
2083 | return unlikely(atomic_read(&error->reset_counter) | |
2ac0f450 | 2084 | & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); |
1f83fee0 DV |
2085 | } |
2086 | ||
2087 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) | |
2088 | { | |
2ac0f450 MK |
2089 | return atomic_read(&error->reset_counter) & I915_WEDGED; |
2090 | } | |
2091 | ||
2092 | static inline u32 i915_reset_count(struct i915_gpu_error *error) | |
2093 | { | |
2094 | return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2; | |
1f83fee0 | 2095 | } |
a71d8d94 | 2096 | |
069efc1d | 2097 | void i915_gem_reset(struct drm_device *dev); |
000433b6 | 2098 | bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); |
a8198eea | 2099 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); |
1070a42b | 2100 | int __must_check i915_gem_init(struct drm_device *dev); |
f691e2f4 | 2101 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
c3787e2e | 2102 | int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice); |
f691e2f4 | 2103 | void i915_gem_init_swizzling(struct drm_device *dev); |
79e53945 | 2104 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
b2da9fe5 | 2105 | int __must_check i915_gpu_idle(struct drm_device *dev); |
45c5f202 | 2106 | int __must_check i915_gem_suspend(struct drm_device *dev); |
0025c077 MK |
2107 | int __i915_add_request(struct intel_ring_buffer *ring, |
2108 | struct drm_file *file, | |
7d736f4f | 2109 | struct drm_i915_gem_object *batch_obj, |
0025c077 MK |
2110 | u32 *seqno); |
2111 | #define i915_add_request(ring, seqno) \ | |
854c94a7 | 2112 | __i915_add_request(ring, NULL, NULL, seqno) |
199b2bc2 BW |
2113 | int __must_check i915_wait_seqno(struct intel_ring_buffer *ring, |
2114 | uint32_t seqno); | |
de151cf6 | 2115 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
2021746e CW |
2116 | int __must_check |
2117 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, | |
2118 | bool write); | |
2119 | int __must_check | |
dabdfe02 CW |
2120 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
2121 | int __must_check | |
2da3b9b9 CW |
2122 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
2123 | u32 alignment, | |
2021746e | 2124 | struct intel_ring_buffer *pipelined); |
cc98b413 | 2125 | void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj); |
71acb5eb | 2126 | int i915_gem_attach_phys_object(struct drm_device *dev, |
05394f39 | 2127 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
2128 | int id, |
2129 | int align); | |
71acb5eb | 2130 | void i915_gem_detach_phys_object(struct drm_device *dev, |
05394f39 | 2131 | struct drm_i915_gem_object *obj); |
71acb5eb | 2132 | void i915_gem_free_all_phys_object(struct drm_device *dev); |
b29c19b6 | 2133 | int i915_gem_open(struct drm_device *dev, struct drm_file *file); |
05394f39 | 2134 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 2135 | |
0fa87796 ID |
2136 | uint32_t |
2137 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); | |
467cffba | 2138 | uint32_t |
d865110c ID |
2139 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
2140 | int tiling_mode, bool fenced); | |
467cffba | 2141 | |
e4ffd173 CW |
2142 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
2143 | enum i915_cache_level cache_level); | |
2144 | ||
1286ff73 DV |
2145 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
2146 | struct dma_buf *dma_buf); | |
2147 | ||
2148 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, | |
2149 | struct drm_gem_object *gem_obj, int flags); | |
2150 | ||
19b2dbde CW |
2151 | void i915_gem_restore_fences(struct drm_device *dev); |
2152 | ||
a70a3148 BW |
2153 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, |
2154 | struct i915_address_space *vm); | |
2155 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); | |
2156 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
2157 | struct i915_address_space *vm); | |
2158 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
2159 | struct i915_address_space *vm); | |
2160 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, | |
2161 | struct i915_address_space *vm); | |
accfef2e BW |
2162 | struct i915_vma * |
2163 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
2164 | struct i915_address_space *vm); | |
5c2abbea BW |
2165 | |
2166 | struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj); | |
2167 | ||
a70a3148 BW |
2168 | /* Some GGTT VM helpers */ |
2169 | #define obj_to_ggtt(obj) \ | |
2170 | (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) | |
2171 | static inline bool i915_is_ggtt(struct i915_address_space *vm) | |
2172 | { | |
2173 | struct i915_address_space *ggtt = | |
2174 | &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base; | |
2175 | return vm == ggtt; | |
2176 | } | |
2177 | ||
2178 | static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) | |
2179 | { | |
2180 | return i915_gem_obj_bound(obj, obj_to_ggtt(obj)); | |
2181 | } | |
2182 | ||
2183 | static inline unsigned long | |
2184 | i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj) | |
2185 | { | |
2186 | return i915_gem_obj_offset(obj, obj_to_ggtt(obj)); | |
2187 | } | |
2188 | ||
2189 | static inline unsigned long | |
2190 | i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) | |
2191 | { | |
2192 | return i915_gem_obj_size(obj, obj_to_ggtt(obj)); | |
2193 | } | |
c37e2204 BW |
2194 | |
2195 | static inline int __must_check | |
2196 | i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, | |
2197 | uint32_t alignment, | |
2198 | bool map_and_fenceable, | |
2199 | bool nonblocking) | |
2200 | { | |
2201 | return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, | |
2202 | map_and_fenceable, nonblocking); | |
2203 | } | |
a70a3148 | 2204 | |
254f965c | 2205 | /* i915_gem_context.c */ |
8245be31 | 2206 | int __must_check i915_gem_context_init(struct drm_device *dev); |
254f965c | 2207 | void i915_gem_context_fini(struct drm_device *dev); |
254f965c | 2208 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
e0556841 BW |
2209 | int i915_switch_context(struct intel_ring_buffer *ring, |
2210 | struct drm_file *file, int to_id); | |
dce3271b MK |
2211 | void i915_gem_context_free(struct kref *ctx_ref); |
2212 | static inline void i915_gem_context_reference(struct i915_hw_context *ctx) | |
2213 | { | |
2214 | kref_get(&ctx->ref); | |
2215 | } | |
2216 | ||
2217 | static inline void i915_gem_context_unreference(struct i915_hw_context *ctx) | |
2218 | { | |
2219 | kref_put(&ctx->ref, i915_gem_context_free); | |
2220 | } | |
2221 | ||
c0bb617a | 2222 | struct i915_ctx_hang_stats * __must_check |
11fa3384 | 2223 | i915_gem_context_get_hang_stats(struct drm_device *dev, |
c0bb617a MK |
2224 | struct drm_file *file, |
2225 | u32 id); | |
84624813 BW |
2226 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
2227 | struct drm_file *file); | |
2228 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
2229 | struct drm_file *file); | |
1286ff73 | 2230 | |
76aaf220 | 2231 | /* i915_gem_gtt.c */ |
1d2a314c | 2232 | void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev); |
7bddb01f DV |
2233 | void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt, |
2234 | struct drm_i915_gem_object *obj, | |
2235 | enum i915_cache_level cache_level); | |
2236 | void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt, | |
2237 | struct drm_i915_gem_object *obj); | |
1d2a314c | 2238 | |
828c7908 BW |
2239 | void i915_check_and_clear_faults(struct drm_device *dev); |
2240 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev); | |
76aaf220 | 2241 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); |
74163907 DV |
2242 | int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); |
2243 | void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj, | |
e4ffd173 | 2244 | enum i915_cache_level cache_level); |
05394f39 | 2245 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); |
74163907 | 2246 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); |
d7e5008f BW |
2247 | void i915_gem_init_global_gtt(struct drm_device *dev); |
2248 | void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start, | |
2249 | unsigned long mappable_end, unsigned long end); | |
e76e9aeb | 2250 | int i915_gem_gtt_init(struct drm_device *dev); |
d09105c6 | 2251 | static inline void i915_gem_chipset_flush(struct drm_device *dev) |
e76e9aeb BW |
2252 | { |
2253 | if (INTEL_INFO(dev)->gen < 6) | |
2254 | intel_gtt_chipset_flush(); | |
2255 | } | |
2256 | ||
76aaf220 | 2257 | |
b47eb4a2 | 2258 | /* i915_gem_evict.c */ |
f6cd1f15 BW |
2259 | int __must_check i915_gem_evict_something(struct drm_device *dev, |
2260 | struct i915_address_space *vm, | |
2261 | int min_size, | |
42d6ab48 CW |
2262 | unsigned alignment, |
2263 | unsigned cache_level, | |
86a1ee26 CW |
2264 | bool mappable, |
2265 | bool nonblock); | |
68c8c17f | 2266 | int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); |
6c085a72 | 2267 | int i915_gem_evict_everything(struct drm_device *dev); |
b47eb4a2 | 2268 | |
9797fbfb CW |
2269 | /* i915_gem_stolen.c */ |
2270 | int i915_gem_init_stolen(struct drm_device *dev); | |
11be49eb CW |
2271 | int i915_gem_stolen_setup_compression(struct drm_device *dev, int size); |
2272 | void i915_gem_stolen_cleanup_compression(struct drm_device *dev); | |
9797fbfb | 2273 | void i915_gem_cleanup_stolen(struct drm_device *dev); |
0104fdbb CW |
2274 | struct drm_i915_gem_object * |
2275 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); | |
866d12b4 CW |
2276 | struct drm_i915_gem_object * |
2277 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, | |
2278 | u32 stolen_offset, | |
2279 | u32 gtt_offset, | |
2280 | u32 size); | |
0104fdbb | 2281 | void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj); |
9797fbfb | 2282 | |
673a394b | 2283 | /* i915_gem_tiling.c */ |
2c1792a1 | 2284 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
e9b73c67 CW |
2285 | { |
2286 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; | |
2287 | ||
2288 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
2289 | obj->tiling_mode != I915_TILING_NONE; | |
2290 | } | |
2291 | ||
673a394b | 2292 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
05394f39 CW |
2293 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
2294 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
673a394b EA |
2295 | |
2296 | /* i915_gem_debug.c */ | |
23bc5982 CW |
2297 | #if WATCH_LISTS |
2298 | int i915_verify_lists(struct drm_device *dev); | |
673a394b | 2299 | #else |
23bc5982 | 2300 | #define i915_verify_lists(dev) 0 |
673a394b | 2301 | #endif |
1da177e4 | 2302 | |
2017263e | 2303 | /* i915_debugfs.c */ |
27c202ad BG |
2304 | int i915_debugfs_init(struct drm_minor *minor); |
2305 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
f8c168fa | 2306 | #ifdef CONFIG_DEBUG_FS |
07144428 DL |
2307 | void intel_display_crc_init(struct drm_device *dev); |
2308 | #else | |
f8c168fa | 2309 | static inline void intel_display_crc_init(struct drm_device *dev) {} |
07144428 | 2310 | #endif |
84734a04 MK |
2311 | |
2312 | /* i915_gpu_error.c */ | |
edc3d884 MK |
2313 | __printf(2, 3) |
2314 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); | |
fc16b48b MK |
2315 | int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, |
2316 | const struct i915_error_state_file_priv *error); | |
4dc955f7 MK |
2317 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, |
2318 | size_t count, loff_t pos); | |
2319 | static inline void i915_error_state_buf_release( | |
2320 | struct drm_i915_error_state_buf *eb) | |
2321 | { | |
2322 | kfree(eb->buf); | |
2323 | } | |
84734a04 MK |
2324 | void i915_capture_error_state(struct drm_device *dev); |
2325 | void i915_error_state_get(struct drm_device *dev, | |
2326 | struct i915_error_state_file_priv *error_priv); | |
2327 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv); | |
2328 | void i915_destroy_error_state(struct drm_device *dev); | |
2329 | ||
2330 | void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); | |
2331 | const char *i915_cache_level_str(int type); | |
2017263e | 2332 | |
317c35d1 JB |
2333 | /* i915_suspend.c */ |
2334 | extern int i915_save_state(struct drm_device *dev); | |
2335 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 | 2336 | |
d8157a36 DV |
2337 | /* i915_ums.c */ |
2338 | void i915_save_display_reg(struct drm_device *dev); | |
2339 | void i915_restore_display_reg(struct drm_device *dev); | |
317c35d1 | 2340 | |
0136db58 BW |
2341 | /* i915_sysfs.c */ |
2342 | void i915_setup_sysfs(struct drm_device *dev_priv); | |
2343 | void i915_teardown_sysfs(struct drm_device *dev_priv); | |
2344 | ||
f899fc64 CW |
2345 | /* intel_i2c.c */ |
2346 | extern int intel_setup_gmbus(struct drm_device *dev); | |
2347 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
8f375e10 | 2348 | static inline bool intel_gmbus_is_port_valid(unsigned port) |
3bd7d909 | 2349 | { |
2ed06c93 | 2350 | return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); |
3bd7d909 DK |
2351 | } |
2352 | ||
2353 | extern struct i2c_adapter *intel_gmbus_get_adapter( | |
2354 | struct drm_i915_private *dev_priv, unsigned port); | |
e957d772 CW |
2355 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
2356 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
8f375e10 | 2357 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
b8232e90 CW |
2358 | { |
2359 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
2360 | } | |
f899fc64 CW |
2361 | extern void intel_i2c_reset(struct drm_device *dev); |
2362 | ||
3b617967 | 2363 | /* intel_opregion.c */ |
9c4b0a68 | 2364 | struct intel_encoder; |
44834a67 CW |
2365 | extern int intel_opregion_setup(struct drm_device *dev); |
2366 | #ifdef CONFIG_ACPI | |
2367 | extern void intel_opregion_init(struct drm_device *dev); | |
2368 | extern void intel_opregion_fini(struct drm_device *dev); | |
3b617967 | 2369 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
9c4b0a68 JN |
2370 | extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, |
2371 | bool enable); | |
ecbc5cf3 JN |
2372 | extern int intel_opregion_notify_adapter(struct drm_device *dev, |
2373 | pci_power_t state); | |
65e082c9 | 2374 | #else |
44834a67 CW |
2375 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
2376 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } | |
3b617967 | 2377 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
9c4b0a68 JN |
2378 | static inline int |
2379 | intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) | |
2380 | { | |
2381 | return 0; | |
2382 | } | |
ecbc5cf3 JN |
2383 | static inline int |
2384 | intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state) | |
2385 | { | |
2386 | return 0; | |
2387 | } | |
65e082c9 | 2388 | #endif |
8ee1c3db | 2389 | |
723bfd70 JB |
2390 | /* intel_acpi.c */ |
2391 | #ifdef CONFIG_ACPI | |
2392 | extern void intel_register_dsm_handler(void); | |
2393 | extern void intel_unregister_dsm_handler(void); | |
2394 | #else | |
2395 | static inline void intel_register_dsm_handler(void) { return; } | |
2396 | static inline void intel_unregister_dsm_handler(void) { return; } | |
2397 | #endif /* CONFIG_ACPI */ | |
2398 | ||
79e53945 | 2399 | /* modesetting */ |
f817586c | 2400 | extern void intel_modeset_init_hw(struct drm_device *dev); |
7d708ee4 | 2401 | extern void intel_modeset_suspend_hw(struct drm_device *dev); |
79e53945 | 2402 | extern void intel_modeset_init(struct drm_device *dev); |
2c7111db | 2403 | extern void intel_modeset_gem_init(struct drm_device *dev); |
79e53945 | 2404 | extern void intel_modeset_cleanup(struct drm_device *dev); |
28d52043 | 2405 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
45e2b5f6 DV |
2406 | extern void intel_modeset_setup_hw_state(struct drm_device *dev, |
2407 | bool force_restore); | |
44cec740 | 2408 | extern void i915_redisable_vga(struct drm_device *dev); |
ee5382ae | 2409 | extern bool intel_fbc_enabled(struct drm_device *dev); |
43a9539f | 2410 | extern void intel_disable_fbc(struct drm_device *dev); |
7648fa99 | 2411 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
dde86e2d | 2412 | extern void intel_init_pch_refclk(struct drm_device *dev); |
3b8d8d91 | 2413 | extern void gen6_set_rps(struct drm_device *dev, u8 val); |
0a073b84 JB |
2414 | extern void valleyview_set_rps(struct drm_device *dev, u8 val); |
2415 | extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv); | |
2416 | extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv); | |
0206e353 AJ |
2417 | extern void intel_detect_pch(struct drm_device *dev); |
2418 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); | |
0136db58 | 2419 | extern int intel_enable_rc6(const struct drm_device *dev); |
3bad0781 | 2420 | |
2911a35b | 2421 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
c0c7babc BW |
2422 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
2423 | struct drm_file *file); | |
b6359918 MK |
2424 | int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, |
2425 | struct drm_file *file); | |
575155a9 | 2426 | |
6ef3d427 CW |
2427 | /* overlay */ |
2428 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); | |
edc3d884 MK |
2429 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
2430 | struct intel_overlay_error_state *error); | |
c4a1d9e4 CW |
2431 | |
2432 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); | |
edc3d884 | 2433 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
c4a1d9e4 CW |
2434 | struct drm_device *dev, |
2435 | struct intel_display_error_state *error); | |
6ef3d427 | 2436 | |
b7287d80 BW |
2437 | /* On SNB platform, before reading ring registers forcewake bit |
2438 | * must be set to prevent GT core from power down and stale values being | |
2439 | * returned. | |
2440 | */ | |
fcca7926 BW |
2441 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); |
2442 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); | |
b7287d80 | 2443 | |
42c0526c BW |
2444 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); |
2445 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); | |
59de0813 JN |
2446 | |
2447 | /* intel_sideband.c */ | |
64936258 JN |
2448 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr); |
2449 | void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); | |
2450 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); | |
e9f882a3 JN |
2451 | u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); |
2452 | void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
2453 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); | |
2454 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
2455 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); | |
2456 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
f3419158 JB |
2457 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); |
2458 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
e9f882a3 JN |
2459 | u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg); |
2460 | void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
5e69f97f CML |
2461 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); |
2462 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); | |
59de0813 JN |
2463 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
2464 | enum intel_sbi_destination destination); | |
2465 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, | |
2466 | enum intel_sbi_destination destination); | |
0a073b84 | 2467 | |
2ec3815f VS |
2468 | int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val); |
2469 | int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val); | |
42c0526c | 2470 | |
0b274481 BW |
2471 | #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) |
2472 | #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) | |
2473 | ||
2474 | #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) | |
2475 | #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) | |
2476 | #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) | |
2477 | #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) | |
2478 | ||
2479 | #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) | |
2480 | #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) | |
2481 | #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) | |
2482 | #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) | |
2483 | ||
2484 | #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) | |
2485 | #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) | |
cae5852d ZN |
2486 | |
2487 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) | |
2488 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
2489 | ||
55bc60db VS |
2490 | /* "Broadcast RGB" property */ |
2491 | #define INTEL_BROADCAST_RGB_AUTO 0 | |
2492 | #define INTEL_BROADCAST_RGB_FULL 1 | |
2493 | #define INTEL_BROADCAST_RGB_LIMITED 2 | |
ba4f01a3 | 2494 | |
766aa1c4 VS |
2495 | static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) |
2496 | { | |
2497 | if (HAS_PCH_SPLIT(dev)) | |
2498 | return CPU_VGACNTRL; | |
2499 | else if (IS_VALLEYVIEW(dev)) | |
2500 | return VLV_VGACNTRL; | |
2501 | else | |
2502 | return VGACNTRL; | |
2503 | } | |
2504 | ||
2bb4629a VS |
2505 | static inline void __user *to_user_ptr(u64 address) |
2506 | { | |
2507 | return (void __user *)(uintptr_t)address; | |
2508 | } | |
2509 | ||
df97729f ID |
2510 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
2511 | { | |
2512 | unsigned long j = msecs_to_jiffies(m); | |
2513 | ||
2514 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
2515 | } | |
2516 | ||
2517 | static inline unsigned long | |
2518 | timespec_to_jiffies_timeout(const struct timespec *value) | |
2519 | { | |
2520 | unsigned long j = timespec_to_jiffies(value); | |
2521 | ||
2522 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
2523 | } | |
2524 | ||
1da177e4 | 2525 | #endif |