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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
e9b73c67 CW |
33 | #include <uapi/drm/i915_drm.h> |
34 | ||
585fb111 | 35 | #include "i915_reg.h" |
79e53945 | 36 | #include "intel_bios.h" |
8187a2b7 | 37 | #include "intel_ringbuffer.h" |
b20385f1 | 38 | #include "intel_lrc.h" |
0260c420 | 39 | #include "i915_gem_gtt.h" |
564ddb2f | 40 | #include "i915_gem_render_state.h" |
0839ccb8 | 41 | #include <linux/io-mapping.h> |
f899fc64 | 42 | #include <linux/i2c.h> |
c167a6fc | 43 | #include <linux/i2c-algo-bit.h> |
0ade6386 | 44 | #include <drm/intel-gtt.h> |
ba8286fa | 45 | #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ |
d9fc9413 | 46 | #include <drm/drm_gem.h> |
aaa6fd2a | 47 | #include <linux/backlight.h> |
5cc9ed4b | 48 | #include <linux/hashtable.h> |
2911a35b | 49 | #include <linux/intel-iommu.h> |
742cbee8 | 50 | #include <linux/kref.h> |
9ee32fea | 51 | #include <linux/pm_qos.h> |
585fb111 | 52 | |
1da177e4 LT |
53 | /* General customization: |
54 | */ | |
55 | ||
1da177e4 LT |
56 | #define DRIVER_NAME "i915" |
57 | #define DRIVER_DESC "Intel Graphics" | |
e7f1d0b7 | 58 | #define DRIVER_DATE "20141121" |
1da177e4 | 59 | |
c883ef1b MK |
60 | #undef WARN_ON |
61 | #define WARN_ON(x) WARN(x, "WARN_ON(" #x ")") | |
62 | ||
317c35d1 | 63 | enum pipe { |
752aa88a | 64 | INVALID_PIPE = -1, |
317c35d1 JB |
65 | PIPE_A = 0, |
66 | PIPE_B, | |
9db4a9c7 | 67 | PIPE_C, |
a57c774a AK |
68 | _PIPE_EDP, |
69 | I915_MAX_PIPES = _PIPE_EDP | |
317c35d1 | 70 | }; |
9db4a9c7 | 71 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 72 | |
a5c961d1 PZ |
73 | enum transcoder { |
74 | TRANSCODER_A = 0, | |
75 | TRANSCODER_B, | |
76 | TRANSCODER_C, | |
a57c774a AK |
77 | TRANSCODER_EDP, |
78 | I915_MAX_TRANSCODERS | |
a5c961d1 PZ |
79 | }; |
80 | #define transcoder_name(t) ((t) + 'A') | |
81 | ||
84139d1e DL |
82 | /* |
83 | * This is the maximum (across all platforms) number of planes (primary + | |
84 | * sprites) that can be active at the same time on one pipe. | |
85 | * | |
86 | * This value doesn't count the cursor plane. | |
87 | */ | |
88 | #define I915_MAX_PLANES 3 | |
89 | ||
80824003 JB |
90 | enum plane { |
91 | PLANE_A = 0, | |
92 | PLANE_B, | |
9db4a9c7 | 93 | PLANE_C, |
80824003 | 94 | }; |
9db4a9c7 | 95 | #define plane_name(p) ((p) + 'A') |
52440211 | 96 | |
d615a166 | 97 | #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A') |
06da8da2 | 98 | |
2b139522 ED |
99 | enum port { |
100 | PORT_A = 0, | |
101 | PORT_B, | |
102 | PORT_C, | |
103 | PORT_D, | |
104 | PORT_E, | |
105 | I915_MAX_PORTS | |
106 | }; | |
107 | #define port_name(p) ((p) + 'A') | |
108 | ||
a09caddd | 109 | #define I915_NUM_PHYS_VLV 2 |
e4607fcf CML |
110 | |
111 | enum dpio_channel { | |
112 | DPIO_CH0, | |
113 | DPIO_CH1 | |
114 | }; | |
115 | ||
116 | enum dpio_phy { | |
117 | DPIO_PHY0, | |
118 | DPIO_PHY1 | |
119 | }; | |
120 | ||
b97186f0 PZ |
121 | enum intel_display_power_domain { |
122 | POWER_DOMAIN_PIPE_A, | |
123 | POWER_DOMAIN_PIPE_B, | |
124 | POWER_DOMAIN_PIPE_C, | |
125 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, | |
126 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, | |
127 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, | |
128 | POWER_DOMAIN_TRANSCODER_A, | |
129 | POWER_DOMAIN_TRANSCODER_B, | |
130 | POWER_DOMAIN_TRANSCODER_C, | |
f52e353e | 131 | POWER_DOMAIN_TRANSCODER_EDP, |
319be8ae ID |
132 | POWER_DOMAIN_PORT_DDI_A_2_LANES, |
133 | POWER_DOMAIN_PORT_DDI_A_4_LANES, | |
134 | POWER_DOMAIN_PORT_DDI_B_2_LANES, | |
135 | POWER_DOMAIN_PORT_DDI_B_4_LANES, | |
136 | POWER_DOMAIN_PORT_DDI_C_2_LANES, | |
137 | POWER_DOMAIN_PORT_DDI_C_4_LANES, | |
138 | POWER_DOMAIN_PORT_DDI_D_2_LANES, | |
139 | POWER_DOMAIN_PORT_DDI_D_4_LANES, | |
140 | POWER_DOMAIN_PORT_DSI, | |
141 | POWER_DOMAIN_PORT_CRT, | |
142 | POWER_DOMAIN_PORT_OTHER, | |
cdf8dd7f | 143 | POWER_DOMAIN_VGA, |
fbeeaa23 | 144 | POWER_DOMAIN_AUDIO, |
bd2bb1b9 | 145 | POWER_DOMAIN_PLLS, |
baa70707 | 146 | POWER_DOMAIN_INIT, |
bddc7645 ID |
147 | |
148 | POWER_DOMAIN_NUM, | |
b97186f0 PZ |
149 | }; |
150 | ||
151 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) | |
152 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ | |
153 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) | |
f52e353e ID |
154 | #define POWER_DOMAIN_TRANSCODER(tran) \ |
155 | ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ | |
156 | (tran) + POWER_DOMAIN_TRANSCODER_A) | |
b97186f0 | 157 | |
1d843f9d EE |
158 | enum hpd_pin { |
159 | HPD_NONE = 0, | |
160 | HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ | |
161 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ | |
162 | HPD_CRT, | |
163 | HPD_SDVO_B, | |
164 | HPD_SDVO_C, | |
165 | HPD_PORT_B, | |
166 | HPD_PORT_C, | |
167 | HPD_PORT_D, | |
168 | HPD_NUM_PINS | |
169 | }; | |
170 | ||
2a2d5482 CW |
171 | #define I915_GEM_GPU_DOMAINS \ |
172 | (I915_GEM_DOMAIN_RENDER | \ | |
173 | I915_GEM_DOMAIN_SAMPLER | \ | |
174 | I915_GEM_DOMAIN_COMMAND | \ | |
175 | I915_GEM_DOMAIN_INSTRUCTION | \ | |
176 | I915_GEM_DOMAIN_VERTEX) | |
62fdfeaf | 177 | |
055e393f DL |
178 | #define for_each_pipe(__dev_priv, __p) \ |
179 | for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) | |
2d025a5b DL |
180 | #define for_each_plane(pipe, p) \ |
181 | for ((p) = 0; (p) < INTEL_INFO(dev)->num_sprites[(pipe)] + 1; (p)++) | |
d615a166 | 182 | #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++) |
9db4a9c7 | 183 | |
d79b814d DL |
184 | #define for_each_crtc(dev, crtc) \ |
185 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | |
186 | ||
d063ae48 DL |
187 | #define for_each_intel_crtc(dev, intel_crtc) \ |
188 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) | |
189 | ||
b2784e15 DL |
190 | #define for_each_intel_encoder(dev, intel_encoder) \ |
191 | list_for_each_entry(intel_encoder, \ | |
192 | &(dev)->mode_config.encoder_list, \ | |
193 | base.head) | |
194 | ||
6c2b7c12 DV |
195 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
196 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | |
197 | if ((intel_encoder)->base.crtc == (__crtc)) | |
198 | ||
53f5e3ca JB |
199 | #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ |
200 | list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ | |
201 | if ((intel_connector)->base.encoder == (__encoder)) | |
202 | ||
b04c5bd6 BF |
203 | #define for_each_power_domain(domain, mask) \ |
204 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
205 | if ((1 << (domain)) & (mask)) | |
206 | ||
e7b903d2 | 207 | struct drm_i915_private; |
ad46cb53 | 208 | struct i915_mm_struct; |
5cc9ed4b | 209 | struct i915_mmu_object; |
e7b903d2 | 210 | |
46edb027 DV |
211 | enum intel_dpll_id { |
212 | DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ | |
213 | /* real shared dpll ids must be >= 0 */ | |
9cd86933 DV |
214 | DPLL_ID_PCH_PLL_A = 0, |
215 | DPLL_ID_PCH_PLL_B = 1, | |
429d47d5 | 216 | /* hsw/bdw */ |
9cd86933 DV |
217 | DPLL_ID_WRPLL1 = 0, |
218 | DPLL_ID_WRPLL2 = 1, | |
429d47d5 S |
219 | /* skl */ |
220 | DPLL_ID_SKL_DPLL1 = 0, | |
221 | DPLL_ID_SKL_DPLL2 = 1, | |
222 | DPLL_ID_SKL_DPLL3 = 2, | |
46edb027 | 223 | }; |
429d47d5 | 224 | #define I915_NUM_PLLS 3 |
46edb027 | 225 | |
5358901f | 226 | struct intel_dpll_hw_state { |
dcfc3552 | 227 | /* i9xx, pch plls */ |
66e985c0 | 228 | uint32_t dpll; |
8bcc2795 | 229 | uint32_t dpll_md; |
66e985c0 DV |
230 | uint32_t fp0; |
231 | uint32_t fp1; | |
dcfc3552 DL |
232 | |
233 | /* hsw, bdw */ | |
d452c5b6 | 234 | uint32_t wrpll; |
d1a2dc78 S |
235 | |
236 | /* skl */ | |
237 | /* | |
238 | * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in | |
239 | * lower part of crtl1 and they get shifted into position when writing | |
240 | * the register. This allows us to easily compare the state to share | |
241 | * the DPLL. | |
242 | */ | |
243 | uint32_t ctrl1; | |
244 | /* HDMI only, 0 when used for DP */ | |
245 | uint32_t cfgcr1, cfgcr2; | |
5358901f DV |
246 | }; |
247 | ||
3e369b76 | 248 | struct intel_shared_dpll_config { |
1e6f2ddc | 249 | unsigned crtc_mask; /* mask of CRTCs sharing this PLL */ |
3e369b76 ACO |
250 | struct intel_dpll_hw_state hw_state; |
251 | }; | |
252 | ||
253 | struct intel_shared_dpll { | |
254 | struct intel_shared_dpll_config config; | |
8bd31e67 ACO |
255 | struct intel_shared_dpll_config *new_config; |
256 | ||
ee7b9f93 JB |
257 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ |
258 | bool on; /* is the PLL actually active? Disabled during modeset */ | |
46edb027 DV |
259 | const char *name; |
260 | /* should match the index in the dev_priv->shared_dplls array */ | |
261 | enum intel_dpll_id id; | |
96f6128c DV |
262 | /* The mode_set hook is optional and should be used together with the |
263 | * intel_prepare_shared_dpll function. */ | |
15bdd4cf DV |
264 | void (*mode_set)(struct drm_i915_private *dev_priv, |
265 | struct intel_shared_dpll *pll); | |
e7b903d2 DV |
266 | void (*enable)(struct drm_i915_private *dev_priv, |
267 | struct intel_shared_dpll *pll); | |
268 | void (*disable)(struct drm_i915_private *dev_priv, | |
269 | struct intel_shared_dpll *pll); | |
5358901f DV |
270 | bool (*get_hw_state)(struct drm_i915_private *dev_priv, |
271 | struct intel_shared_dpll *pll, | |
272 | struct intel_dpll_hw_state *hw_state); | |
ee7b9f93 | 273 | }; |
ee7b9f93 | 274 | |
429d47d5 S |
275 | #define SKL_DPLL0 0 |
276 | #define SKL_DPLL1 1 | |
277 | #define SKL_DPLL2 2 | |
278 | #define SKL_DPLL3 3 | |
279 | ||
e69d0bc1 DV |
280 | /* Used by dp and fdi links */ |
281 | struct intel_link_m_n { | |
282 | uint32_t tu; | |
283 | uint32_t gmch_m; | |
284 | uint32_t gmch_n; | |
285 | uint32_t link_m; | |
286 | uint32_t link_n; | |
287 | }; | |
288 | ||
289 | void intel_link_compute_m_n(int bpp, int nlanes, | |
290 | int pixel_clock, int link_clock, | |
291 | struct intel_link_m_n *m_n); | |
292 | ||
1da177e4 LT |
293 | /* Interface history: |
294 | * | |
295 | * 1.1: Original. | |
0d6aa60b DA |
296 | * 1.2: Add Power Management |
297 | * 1.3: Add vblank support | |
de227f5f | 298 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 299 | * 1.5: Add vblank pipe configuration |
2228ed67 MD |
300 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
301 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
302 | */ |
303 | #define DRIVER_MAJOR 1 | |
2228ed67 | 304 | #define DRIVER_MINOR 6 |
1da177e4 LT |
305 | #define DRIVER_PATCHLEVEL 0 |
306 | ||
23bc5982 | 307 | #define WATCH_LISTS 0 |
673a394b | 308 | |
0a3e67a4 JB |
309 | struct opregion_header; |
310 | struct opregion_acpi; | |
311 | struct opregion_swsci; | |
312 | struct opregion_asle; | |
313 | ||
8ee1c3db | 314 | struct intel_opregion { |
5bc4418b BW |
315 | struct opregion_header __iomem *header; |
316 | struct opregion_acpi __iomem *acpi; | |
317 | struct opregion_swsci __iomem *swsci; | |
ebde53c7 JN |
318 | u32 swsci_gbda_sub_functions; |
319 | u32 swsci_sbcb_sub_functions; | |
5bc4418b BW |
320 | struct opregion_asle __iomem *asle; |
321 | void __iomem *vbt; | |
01fe9dbd | 322 | u32 __iomem *lid_state; |
91a60f20 | 323 | struct work_struct asle_work; |
8ee1c3db | 324 | }; |
44834a67 | 325 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 326 | |
6ef3d427 CW |
327 | struct intel_overlay; |
328 | struct intel_overlay_error_state; | |
329 | ||
de151cf6 | 330 | #define I915_FENCE_REG_NONE -1 |
42b5aeab VS |
331 | #define I915_MAX_NUM_FENCES 32 |
332 | /* 32 fences + sign bit for FENCE_REG_NONE */ | |
333 | #define I915_MAX_NUM_FENCE_BITS 6 | |
de151cf6 JB |
334 | |
335 | struct drm_i915_fence_reg { | |
007cc8ac | 336 | struct list_head lru_list; |
caea7476 | 337 | struct drm_i915_gem_object *obj; |
1690e1eb | 338 | int pin_count; |
de151cf6 | 339 | }; |
7c1c2871 | 340 | |
9b9d172d | 341 | struct sdvo_device_mapping { |
e957d772 | 342 | u8 initialized; |
9b9d172d | 343 | u8 dvo_port; |
344 | u8 slave_addr; | |
345 | u8 dvo_wiring; | |
e957d772 | 346 | u8 i2c_pin; |
b1083333 | 347 | u8 ddc_pin; |
9b9d172d | 348 | }; |
349 | ||
c4a1d9e4 CW |
350 | struct intel_display_error_state; |
351 | ||
63eeaf38 | 352 | struct drm_i915_error_state { |
742cbee8 | 353 | struct kref ref; |
585b0288 BW |
354 | struct timeval time; |
355 | ||
cb383002 | 356 | char error_msg[128]; |
48b031e3 | 357 | u32 reset_count; |
62d5d69b | 358 | u32 suspend_count; |
cb383002 | 359 | |
585b0288 | 360 | /* Generic register state */ |
63eeaf38 JB |
361 | u32 eir; |
362 | u32 pgtbl_er; | |
be998e2e | 363 | u32 ier; |
885ea5a8 | 364 | u32 gtier[4]; |
b9a3906b | 365 | u32 ccid; |
0f3b6849 CW |
366 | u32 derrmr; |
367 | u32 forcewake; | |
585b0288 BW |
368 | u32 error; /* gen6+ */ |
369 | u32 err_int; /* gen7 */ | |
370 | u32 done_reg; | |
91ec5d11 BW |
371 | u32 gac_eco; |
372 | u32 gam_ecochk; | |
373 | u32 gab_ctl; | |
374 | u32 gfx_mode; | |
585b0288 | 375 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; |
585b0288 BW |
376 | u64 fence[I915_MAX_NUM_FENCES]; |
377 | struct intel_overlay_error_state *overlay; | |
378 | struct intel_display_error_state *display; | |
0ca36d78 | 379 | struct drm_i915_error_object *semaphore_obj; |
585b0288 | 380 | |
52d39a21 | 381 | struct drm_i915_error_ring { |
372fbb8e | 382 | bool valid; |
362b8af7 BW |
383 | /* Software tracked state */ |
384 | bool waiting; | |
385 | int hangcheck_score; | |
386 | enum intel_ring_hangcheck_action hangcheck_action; | |
387 | int num_requests; | |
388 | ||
389 | /* our own tracking of ring head and tail */ | |
390 | u32 cpu_ring_head; | |
391 | u32 cpu_ring_tail; | |
392 | ||
393 | u32 semaphore_seqno[I915_NUM_RINGS - 1]; | |
394 | ||
395 | /* Register state */ | |
396 | u32 tail; | |
397 | u32 head; | |
398 | u32 ctl; | |
399 | u32 hws; | |
400 | u32 ipeir; | |
401 | u32 ipehr; | |
402 | u32 instdone; | |
362b8af7 BW |
403 | u32 bbstate; |
404 | u32 instpm; | |
405 | u32 instps; | |
406 | u32 seqno; | |
407 | u64 bbaddr; | |
50877445 | 408 | u64 acthd; |
362b8af7 | 409 | u32 fault_reg; |
13ffadd1 | 410 | u64 faddr; |
362b8af7 BW |
411 | u32 rc_psmi; /* sleep state */ |
412 | u32 semaphore_mboxes[I915_NUM_RINGS - 1]; | |
413 | ||
52d39a21 CW |
414 | struct drm_i915_error_object { |
415 | int page_count; | |
416 | u32 gtt_offset; | |
417 | u32 *pages[0]; | |
ab0e7ff9 | 418 | } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; |
362b8af7 | 419 | |
52d39a21 CW |
420 | struct drm_i915_error_request { |
421 | long jiffies; | |
422 | u32 seqno; | |
ee4f42b1 | 423 | u32 tail; |
52d39a21 | 424 | } *requests; |
6c7a01ec BW |
425 | |
426 | struct { | |
427 | u32 gfx_mode; | |
428 | union { | |
429 | u64 pdp[4]; | |
430 | u32 pp_dir_base; | |
431 | }; | |
432 | } vm_info; | |
ab0e7ff9 CW |
433 | |
434 | pid_t pid; | |
435 | char comm[TASK_COMM_LEN]; | |
52d39a21 | 436 | } ring[I915_NUM_RINGS]; |
3a448734 | 437 | |
9df30794 | 438 | struct drm_i915_error_buffer { |
a779e5ab | 439 | u32 size; |
9df30794 | 440 | u32 name; |
0201f1ec | 441 | u32 rseqno, wseqno; |
9df30794 CW |
442 | u32 gtt_offset; |
443 | u32 read_domains; | |
444 | u32 write_domain; | |
4b9de737 | 445 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
9df30794 CW |
446 | s32 pinned:2; |
447 | u32 tiling:2; | |
448 | u32 dirty:1; | |
449 | u32 purgeable:1; | |
5cc9ed4b | 450 | u32 userptr:1; |
5d1333fc | 451 | s32 ring:4; |
f56383cb | 452 | u32 cache_level:3; |
95f5301d | 453 | } **active_bo, **pinned_bo; |
6c7a01ec | 454 | |
95f5301d | 455 | u32 *active_bo_count, *pinned_bo_count; |
3a448734 | 456 | u32 vm_count; |
63eeaf38 JB |
457 | }; |
458 | ||
7bd688cd | 459 | struct intel_connector; |
820d2d77 | 460 | struct intel_encoder; |
b8cecdf5 | 461 | struct intel_crtc_config; |
46f297fb | 462 | struct intel_plane_config; |
0e8ffe1b | 463 | struct intel_crtc; |
ee9300bb DV |
464 | struct intel_limit; |
465 | struct dpll; | |
b8cecdf5 | 466 | |
e70236a8 | 467 | struct drm_i915_display_funcs { |
ee5382ae | 468 | bool (*fbc_enabled)(struct drm_device *dev); |
993495ae | 469 | void (*enable_fbc)(struct drm_crtc *crtc); |
e70236a8 JB |
470 | void (*disable_fbc)(struct drm_device *dev); |
471 | int (*get_display_clock_speed)(struct drm_device *dev); | |
472 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
ee9300bb DV |
473 | /** |
474 | * find_dpll() - Find the best values for the PLL | |
475 | * @limit: limits for the PLL | |
476 | * @crtc: current CRTC | |
477 | * @target: target frequency in kHz | |
478 | * @refclk: reference clock frequency in kHz | |
479 | * @match_clock: if provided, @best_clock P divider must | |
480 | * match the P divider from @match_clock | |
481 | * used for LVDS downclocking | |
482 | * @best_clock: best PLL values found | |
483 | * | |
484 | * Returns true on success, false on failure. | |
485 | */ | |
486 | bool (*find_dpll)(const struct intel_limit *limit, | |
a919ff14 | 487 | struct intel_crtc *crtc, |
ee9300bb DV |
488 | int target, int refclk, |
489 | struct dpll *match_clock, | |
490 | struct dpll *best_clock); | |
46ba614c | 491 | void (*update_wm)(struct drm_crtc *crtc); |
adf3d35e VS |
492 | void (*update_sprite_wm)(struct drm_plane *plane, |
493 | struct drm_crtc *crtc, | |
ed57cb8a DL |
494 | uint32_t sprite_width, uint32_t sprite_height, |
495 | int pixel_size, bool enable, bool scaled); | |
47fab737 | 496 | void (*modeset_global_resources)(struct drm_device *dev); |
0e8ffe1b DV |
497 | /* Returns the active state of the crtc, and if the crtc is active, |
498 | * fills out the pipe-config with the hw state. */ | |
499 | bool (*get_pipe_config)(struct intel_crtc *, | |
500 | struct intel_crtc_config *); | |
46f297fb JB |
501 | void (*get_plane_config)(struct intel_crtc *, |
502 | struct intel_plane_config *); | |
8bd31e67 | 503 | int (*crtc_compute_clock)(struct intel_crtc *crtc); |
76e5a89c DV |
504 | void (*crtc_enable)(struct drm_crtc *crtc); |
505 | void (*crtc_disable)(struct drm_crtc *crtc); | |
ee7b9f93 | 506 | void (*off)(struct drm_crtc *crtc); |
69bfe1a9 JN |
507 | void (*audio_codec_enable)(struct drm_connector *connector, |
508 | struct intel_encoder *encoder, | |
509 | struct drm_display_mode *mode); | |
510 | void (*audio_codec_disable)(struct intel_encoder *encoder); | |
674cf967 | 511 | void (*fdi_link_train)(struct drm_crtc *crtc); |
6067aaea | 512 | void (*init_clock_gating)(struct drm_device *dev); |
8c9f3aaf JB |
513 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
514 | struct drm_framebuffer *fb, | |
ed8d1975 | 515 | struct drm_i915_gem_object *obj, |
a4872ba6 | 516 | struct intel_engine_cs *ring, |
ed8d1975 | 517 | uint32_t flags); |
29b9bde6 DV |
518 | void (*update_primary_plane)(struct drm_crtc *crtc, |
519 | struct drm_framebuffer *fb, | |
520 | int x, int y); | |
20afbda2 | 521 | void (*hpd_irq_setup)(struct drm_device *dev); |
e70236a8 JB |
522 | /* clock updates for mode set */ |
523 | /* cursor updates */ | |
524 | /* render clock increase/decrease */ | |
525 | /* display clock increase/decrease */ | |
526 | /* pll clock increase/decrease */ | |
7bd688cd | 527 | |
6517d273 | 528 | int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe); |
7bd688cd JN |
529 | uint32_t (*get_backlight)(struct intel_connector *connector); |
530 | void (*set_backlight)(struct intel_connector *connector, | |
531 | uint32_t level); | |
532 | void (*disable_backlight)(struct intel_connector *connector); | |
533 | void (*enable_backlight)(struct intel_connector *connector); | |
e70236a8 JB |
534 | }; |
535 | ||
907b28c5 | 536 | struct intel_uncore_funcs { |
c8d9a590 D |
537 | void (*force_wake_get)(struct drm_i915_private *dev_priv, |
538 | int fw_engine); | |
539 | void (*force_wake_put)(struct drm_i915_private *dev_priv, | |
540 | int fw_engine); | |
0b274481 BW |
541 | |
542 | uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
543 | uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
544 | uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
545 | uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
546 | ||
547 | void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset, | |
548 | uint8_t val, bool trace); | |
549 | void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset, | |
550 | uint16_t val, bool trace); | |
551 | void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset, | |
552 | uint32_t val, bool trace); | |
553 | void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset, | |
554 | uint64_t val, bool trace); | |
990bbdad CW |
555 | }; |
556 | ||
907b28c5 CW |
557 | struct intel_uncore { |
558 | spinlock_t lock; /** lock is also taken in irq contexts. */ | |
559 | ||
560 | struct intel_uncore_funcs funcs; | |
561 | ||
562 | unsigned fifo_count; | |
563 | unsigned forcewake_count; | |
aec347ab | 564 | |
940aece4 D |
565 | unsigned fw_rendercount; |
566 | unsigned fw_mediacount; | |
38cff0b1 | 567 | unsigned fw_blittercount; |
940aece4 | 568 | |
8232644c | 569 | struct timer_list force_wake_timer; |
907b28c5 CW |
570 | }; |
571 | ||
79fc46df DL |
572 | #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ |
573 | func(is_mobile) sep \ | |
574 | func(is_i85x) sep \ | |
575 | func(is_i915g) sep \ | |
576 | func(is_i945gm) sep \ | |
577 | func(is_g33) sep \ | |
578 | func(need_gfx_hws) sep \ | |
579 | func(is_g4x) sep \ | |
580 | func(is_pineview) sep \ | |
581 | func(is_broadwater) sep \ | |
582 | func(is_crestline) sep \ | |
583 | func(is_ivybridge) sep \ | |
584 | func(is_valleyview) sep \ | |
585 | func(is_haswell) sep \ | |
7201c0b3 | 586 | func(is_skylake) sep \ |
b833d685 | 587 | func(is_preliminary) sep \ |
79fc46df DL |
588 | func(has_fbc) sep \ |
589 | func(has_pipe_cxsr) sep \ | |
590 | func(has_hotplug) sep \ | |
591 | func(cursor_needs_physical) sep \ | |
592 | func(has_overlay) sep \ | |
593 | func(overlay_needs_physical) sep \ | |
594 | func(supports_tv) sep \ | |
dd93be58 | 595 | func(has_llc) sep \ |
30568c45 DL |
596 | func(has_ddi) sep \ |
597 | func(has_fpga_dbg) | |
c96ea64e | 598 | |
a587f779 DL |
599 | #define DEFINE_FLAG(name) u8 name:1 |
600 | #define SEP_SEMICOLON ; | |
c96ea64e | 601 | |
cfdf1fa2 | 602 | struct intel_device_info { |
10fce67a | 603 | u32 display_mmio_offset; |
87f1f465 | 604 | u16 device_id; |
7eb552ae | 605 | u8 num_pipes:3; |
d615a166 | 606 | u8 num_sprites[I915_MAX_PIPES]; |
c96c3a8c | 607 | u8 gen; |
73ae478c | 608 | u8 ring_mask; /* Rings supported by the HW */ |
a587f779 | 609 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); |
a57c774a AK |
610 | /* Register offsets for the various display pipes and transcoders */ |
611 | int pipe_offsets[I915_MAX_TRANSCODERS]; | |
612 | int trans_offsets[I915_MAX_TRANSCODERS]; | |
a57c774a | 613 | int palette_offsets[I915_MAX_PIPES]; |
5efb3e28 | 614 | int cursor_offsets[I915_MAX_PIPES]; |
cfdf1fa2 KH |
615 | }; |
616 | ||
a587f779 DL |
617 | #undef DEFINE_FLAG |
618 | #undef SEP_SEMICOLON | |
619 | ||
7faf1ab2 DV |
620 | enum i915_cache_level { |
621 | I915_CACHE_NONE = 0, | |
350ec881 CW |
622 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ |
623 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc | |
624 | caches, eg sampler/render caches, and the | |
625 | large Last-Level-Cache. LLC is coherent with | |
626 | the CPU, but L3 is only visible to the GPU. */ | |
651d794f | 627 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ |
7faf1ab2 DV |
628 | }; |
629 | ||
e59ec13d MK |
630 | struct i915_ctx_hang_stats { |
631 | /* This context had batch pending when hang was declared */ | |
632 | unsigned batch_pending; | |
633 | ||
634 | /* This context had batch active when hang was declared */ | |
635 | unsigned batch_active; | |
be62acb4 MK |
636 | |
637 | /* Time when this context was last blamed for a GPU reset */ | |
638 | unsigned long guilty_ts; | |
639 | ||
640 | /* This context is banned to submit more work */ | |
641 | bool banned; | |
e59ec13d | 642 | }; |
40521054 BW |
643 | |
644 | /* This must match up with the value previously used for execbuf2.rsvd1. */ | |
821d66dd | 645 | #define DEFAULT_CONTEXT_HANDLE 0 |
31b7a88d OM |
646 | /** |
647 | * struct intel_context - as the name implies, represents a context. | |
648 | * @ref: reference count. | |
649 | * @user_handle: userspace tracking identity for this context. | |
650 | * @remap_slice: l3 row remapping information. | |
651 | * @file_priv: filp associated with this context (NULL for global default | |
652 | * context). | |
653 | * @hang_stats: information about the role of this context in possible GPU | |
654 | * hangs. | |
655 | * @vm: virtual memory space used by this context. | |
656 | * @legacy_hw_ctx: render context backing object and whether it is correctly | |
657 | * initialized (legacy ring submission mechanism only). | |
658 | * @link: link in the global list of contexts. | |
659 | * | |
660 | * Contexts are memory images used by the hardware to store copies of their | |
661 | * internal state. | |
662 | */ | |
273497e5 | 663 | struct intel_context { |
dce3271b | 664 | struct kref ref; |
821d66dd | 665 | int user_handle; |
3ccfd19d | 666 | uint8_t remap_slice; |
40521054 | 667 | struct drm_i915_file_private *file_priv; |
e59ec13d | 668 | struct i915_ctx_hang_stats hang_stats; |
ae6c4806 | 669 | struct i915_hw_ppgtt *ppgtt; |
a33afea5 | 670 | |
c9e003af | 671 | /* Legacy ring buffer submission */ |
ea0c76f8 OM |
672 | struct { |
673 | struct drm_i915_gem_object *rcs_state; | |
674 | bool initialized; | |
675 | } legacy_hw_ctx; | |
676 | ||
c9e003af | 677 | /* Execlists */ |
564ddb2f | 678 | bool rcs_initialized; |
c9e003af OM |
679 | struct { |
680 | struct drm_i915_gem_object *state; | |
84c2377f | 681 | struct intel_ringbuffer *ringbuf; |
dcb4c12a | 682 | int unpin_count; |
c9e003af OM |
683 | } engine[I915_NUM_RINGS]; |
684 | ||
a33afea5 | 685 | struct list_head link; |
40521054 BW |
686 | }; |
687 | ||
5c3fe8b0 BW |
688 | struct i915_fbc { |
689 | unsigned long size; | |
5e59f717 | 690 | unsigned threshold; |
5c3fe8b0 BW |
691 | unsigned int fb_id; |
692 | enum plane plane; | |
693 | int y; | |
694 | ||
c4213885 | 695 | struct drm_mm_node compressed_fb; |
5c3fe8b0 BW |
696 | struct drm_mm_node *compressed_llb; |
697 | ||
da46f936 RV |
698 | bool false_color; |
699 | ||
9adccc60 PZ |
700 | /* Tracks whether the HW is actually enabled, not whether the feature is |
701 | * possible. */ | |
702 | bool enabled; | |
703 | ||
1d73c2a8 RV |
704 | /* On gen8 some rings cannont perform fbc clean operation so for now |
705 | * we are doing this on SW with mmio. | |
706 | * This variable works in the opposite information direction | |
707 | * of ring->fbc_dirty telling software on frontbuffer tracking | |
708 | * to perform the cache clean on sw side. | |
709 | */ | |
710 | bool need_sw_cache_clean; | |
711 | ||
5c3fe8b0 BW |
712 | struct intel_fbc_work { |
713 | struct delayed_work work; | |
714 | struct drm_crtc *crtc; | |
715 | struct drm_framebuffer *fb; | |
5c3fe8b0 BW |
716 | } *fbc_work; |
717 | ||
29ebf90f CW |
718 | enum no_fbc_reason { |
719 | FBC_OK, /* FBC is enabled */ | |
720 | FBC_UNSUPPORTED, /* FBC is not supported by this chipset */ | |
5c3fe8b0 BW |
721 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
722 | FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */ | |
723 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ | |
724 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ | |
725 | FBC_BAD_PLANE, /* fbc not supported on plane */ | |
726 | FBC_NOT_TILED, /* buffer not tiled */ | |
727 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ | |
728 | FBC_MODULE_PARAM, | |
729 | FBC_CHIP_DEFAULT, /* disabled by default on this chip */ | |
730 | } no_fbc_reason; | |
b5e50c3f JB |
731 | }; |
732 | ||
439d7ac0 PB |
733 | struct i915_drrs { |
734 | struct intel_connector *connector; | |
735 | }; | |
736 | ||
2807cf69 | 737 | struct intel_dp; |
a031d709 | 738 | struct i915_psr { |
f0355c4a | 739 | struct mutex lock; |
a031d709 RV |
740 | bool sink_support; |
741 | bool source_ok; | |
2807cf69 | 742 | struct intel_dp *enabled; |
7c8f8a70 RV |
743 | bool active; |
744 | struct delayed_work work; | |
9ca15301 | 745 | unsigned busy_frontbuffer_bits; |
3f51e471 | 746 | }; |
5c3fe8b0 | 747 | |
3bad0781 | 748 | enum intel_pch { |
f0350830 | 749 | PCH_NONE = 0, /* No PCH present */ |
3bad0781 ZW |
750 | PCH_IBX, /* Ibexpeak PCH */ |
751 | PCH_CPT, /* Cougarpoint PCH */ | |
eb877ebf | 752 | PCH_LPT, /* Lynxpoint PCH */ |
e7e7ea20 | 753 | PCH_SPT, /* Sunrisepoint PCH */ |
40c7ead9 | 754 | PCH_NOP, |
3bad0781 ZW |
755 | }; |
756 | ||
988d6ee8 PZ |
757 | enum intel_sbi_destination { |
758 | SBI_ICLK, | |
759 | SBI_MPHY, | |
760 | }; | |
761 | ||
b690e96c | 762 | #define QUIRK_PIPEA_FORCE (1<<0) |
435793df | 763 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
4dca20ef | 764 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
9c72cc6f | 765 | #define QUIRK_BACKLIGHT_PRESENT (1<<3) |
b6b5d049 | 766 | #define QUIRK_PIPEB_FORCE (1<<4) |
656bfa3a | 767 | #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) |
b690e96c | 768 | |
8be48d92 | 769 | struct intel_fbdev; |
1630fe75 | 770 | struct intel_fbc_work; |
38651674 | 771 | |
c2b9152f DV |
772 | struct intel_gmbus { |
773 | struct i2c_adapter adapter; | |
f2ce9faf | 774 | u32 force_bit; |
c2b9152f | 775 | u32 reg0; |
36c785f0 | 776 | u32 gpio_reg; |
c167a6fc | 777 | struct i2c_algo_bit_data bit_algo; |
c2b9152f DV |
778 | struct drm_i915_private *dev_priv; |
779 | }; | |
780 | ||
f4c956ad | 781 | struct i915_suspend_saved_registers { |
ba8bbcf6 JB |
782 | u8 saveLBB; |
783 | u32 saveDSPACNTR; | |
784 | u32 saveDSPBCNTR; | |
e948e994 | 785 | u32 saveDSPARB; |
ba8bbcf6 JB |
786 | u32 savePIPEACONF; |
787 | u32 savePIPEBCONF; | |
788 | u32 savePIPEASRC; | |
789 | u32 savePIPEBSRC; | |
790 | u32 saveFPA0; | |
791 | u32 saveFPA1; | |
792 | u32 saveDPLL_A; | |
793 | u32 saveDPLL_A_MD; | |
794 | u32 saveHTOTAL_A; | |
795 | u32 saveHBLANK_A; | |
796 | u32 saveHSYNC_A; | |
797 | u32 saveVTOTAL_A; | |
798 | u32 saveVBLANK_A; | |
799 | u32 saveVSYNC_A; | |
800 | u32 saveBCLRPAT_A; | |
5586c8bc | 801 | u32 saveTRANSACONF; |
42048781 ZW |
802 | u32 saveTRANS_HTOTAL_A; |
803 | u32 saveTRANS_HBLANK_A; | |
804 | u32 saveTRANS_HSYNC_A; | |
805 | u32 saveTRANS_VTOTAL_A; | |
806 | u32 saveTRANS_VBLANK_A; | |
807 | u32 saveTRANS_VSYNC_A; | |
0da3ea12 | 808 | u32 savePIPEASTAT; |
ba8bbcf6 JB |
809 | u32 saveDSPASTRIDE; |
810 | u32 saveDSPASIZE; | |
811 | u32 saveDSPAPOS; | |
585fb111 | 812 | u32 saveDSPAADDR; |
ba8bbcf6 JB |
813 | u32 saveDSPASURF; |
814 | u32 saveDSPATILEOFF; | |
815 | u32 savePFIT_PGM_RATIOS; | |
0eb96d6e | 816 | u32 saveBLC_HIST_CTL; |
ba8bbcf6 JB |
817 | u32 saveBLC_PWM_CTL; |
818 | u32 saveBLC_PWM_CTL2; | |
42048781 ZW |
819 | u32 saveBLC_CPU_PWM_CTL; |
820 | u32 saveBLC_CPU_PWM_CTL2; | |
ba8bbcf6 JB |
821 | u32 saveFPB0; |
822 | u32 saveFPB1; | |
823 | u32 saveDPLL_B; | |
824 | u32 saveDPLL_B_MD; | |
825 | u32 saveHTOTAL_B; | |
826 | u32 saveHBLANK_B; | |
827 | u32 saveHSYNC_B; | |
828 | u32 saveVTOTAL_B; | |
829 | u32 saveVBLANK_B; | |
830 | u32 saveVSYNC_B; | |
831 | u32 saveBCLRPAT_B; | |
5586c8bc | 832 | u32 saveTRANSBCONF; |
42048781 ZW |
833 | u32 saveTRANS_HTOTAL_B; |
834 | u32 saveTRANS_HBLANK_B; | |
835 | u32 saveTRANS_HSYNC_B; | |
836 | u32 saveTRANS_VTOTAL_B; | |
837 | u32 saveTRANS_VBLANK_B; | |
838 | u32 saveTRANS_VSYNC_B; | |
0da3ea12 | 839 | u32 savePIPEBSTAT; |
ba8bbcf6 JB |
840 | u32 saveDSPBSTRIDE; |
841 | u32 saveDSPBSIZE; | |
842 | u32 saveDSPBPOS; | |
585fb111 | 843 | u32 saveDSPBADDR; |
ba8bbcf6 JB |
844 | u32 saveDSPBSURF; |
845 | u32 saveDSPBTILEOFF; | |
585fb111 JB |
846 | u32 saveVGA0; |
847 | u32 saveVGA1; | |
848 | u32 saveVGA_PD; | |
ba8bbcf6 JB |
849 | u32 saveVGACNTRL; |
850 | u32 saveADPA; | |
851 | u32 saveLVDS; | |
585fb111 JB |
852 | u32 savePP_ON_DELAYS; |
853 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
854 | u32 saveDVOA; |
855 | u32 saveDVOB; | |
856 | u32 saveDVOC; | |
857 | u32 savePP_ON; | |
858 | u32 savePP_OFF; | |
859 | u32 savePP_CONTROL; | |
585fb111 | 860 | u32 savePP_DIVISOR; |
ba8bbcf6 JB |
861 | u32 savePFIT_CONTROL; |
862 | u32 save_palette_a[256]; | |
863 | u32 save_palette_b[256]; | |
ba8bbcf6 | 864 | u32 saveFBC_CONTROL; |
0da3ea12 JB |
865 | u32 saveIER; |
866 | u32 saveIIR; | |
867 | u32 saveIMR; | |
42048781 ZW |
868 | u32 saveDEIER; |
869 | u32 saveDEIMR; | |
870 | u32 saveGTIER; | |
871 | u32 saveGTIMR; | |
872 | u32 saveFDI_RXA_IMR; | |
873 | u32 saveFDI_RXB_IMR; | |
1f84e550 | 874 | u32 saveCACHE_MODE_0; |
1f84e550 | 875 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
876 | u32 saveSWF0[16]; |
877 | u32 saveSWF1[16]; | |
878 | u32 saveSWF2[3]; | |
879 | u8 saveMSR; | |
880 | u8 saveSR[8]; | |
123f794f | 881 | u8 saveGR[25]; |
ba8bbcf6 | 882 | u8 saveAR_INDEX; |
a59e122a | 883 | u8 saveAR[21]; |
ba8bbcf6 | 884 | u8 saveDACMASK; |
a59e122a | 885 | u8 saveCR[37]; |
4b9de737 | 886 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
1fd1c624 EA |
887 | u32 saveCURACNTR; |
888 | u32 saveCURAPOS; | |
889 | u32 saveCURABASE; | |
890 | u32 saveCURBCNTR; | |
891 | u32 saveCURBPOS; | |
892 | u32 saveCURBBASE; | |
893 | u32 saveCURSIZE; | |
a4fc5ed6 KP |
894 | u32 saveDP_B; |
895 | u32 saveDP_C; | |
896 | u32 saveDP_D; | |
897 | u32 savePIPEA_GMCH_DATA_M; | |
898 | u32 savePIPEB_GMCH_DATA_M; | |
899 | u32 savePIPEA_GMCH_DATA_N; | |
900 | u32 savePIPEB_GMCH_DATA_N; | |
901 | u32 savePIPEA_DP_LINK_M; | |
902 | u32 savePIPEB_DP_LINK_M; | |
903 | u32 savePIPEA_DP_LINK_N; | |
904 | u32 savePIPEB_DP_LINK_N; | |
42048781 ZW |
905 | u32 saveFDI_RXA_CTL; |
906 | u32 saveFDI_TXA_CTL; | |
907 | u32 saveFDI_RXB_CTL; | |
908 | u32 saveFDI_TXB_CTL; | |
909 | u32 savePFA_CTL_1; | |
910 | u32 savePFB_CTL_1; | |
911 | u32 savePFA_WIN_SZ; | |
912 | u32 savePFB_WIN_SZ; | |
913 | u32 savePFA_WIN_POS; | |
914 | u32 savePFB_WIN_POS; | |
5586c8bc ZW |
915 | u32 savePCH_DREF_CONTROL; |
916 | u32 saveDISP_ARB_CTL; | |
917 | u32 savePIPEA_DATA_M1; | |
918 | u32 savePIPEA_DATA_N1; | |
919 | u32 savePIPEA_LINK_M1; | |
920 | u32 savePIPEA_LINK_N1; | |
921 | u32 savePIPEB_DATA_M1; | |
922 | u32 savePIPEB_DATA_N1; | |
923 | u32 savePIPEB_LINK_M1; | |
924 | u32 savePIPEB_LINK_N1; | |
b5b72e89 | 925 | u32 saveMCHBAR_RENDER_STANDBY; |
cda2bb78 | 926 | u32 savePCH_PORT_HOTPLUG; |
f4c956ad | 927 | }; |
c85aa885 | 928 | |
ddeea5b0 ID |
929 | struct vlv_s0ix_state { |
930 | /* GAM */ | |
931 | u32 wr_watermark; | |
932 | u32 gfx_prio_ctrl; | |
933 | u32 arb_mode; | |
934 | u32 gfx_pend_tlb0; | |
935 | u32 gfx_pend_tlb1; | |
936 | u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; | |
937 | u32 media_max_req_count; | |
938 | u32 gfx_max_req_count; | |
939 | u32 render_hwsp; | |
940 | u32 ecochk; | |
941 | u32 bsd_hwsp; | |
942 | u32 blt_hwsp; | |
943 | u32 tlb_rd_addr; | |
944 | ||
945 | /* MBC */ | |
946 | u32 g3dctl; | |
947 | u32 gsckgctl; | |
948 | u32 mbctl; | |
949 | ||
950 | /* GCP */ | |
951 | u32 ucgctl1; | |
952 | u32 ucgctl3; | |
953 | u32 rcgctl1; | |
954 | u32 rcgctl2; | |
955 | u32 rstctl; | |
956 | u32 misccpctl; | |
957 | ||
958 | /* GPM */ | |
959 | u32 gfxpause; | |
960 | u32 rpdeuhwtc; | |
961 | u32 rpdeuc; | |
962 | u32 ecobus; | |
963 | u32 pwrdwnupctl; | |
964 | u32 rp_down_timeout; | |
965 | u32 rp_deucsw; | |
966 | u32 rcubmabdtmr; | |
967 | u32 rcedata; | |
968 | u32 spare2gh; | |
969 | ||
970 | /* Display 1 CZ domain */ | |
971 | u32 gt_imr; | |
972 | u32 gt_ier; | |
973 | u32 pm_imr; | |
974 | u32 pm_ier; | |
975 | u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; | |
976 | ||
977 | /* GT SA CZ domain */ | |
978 | u32 tilectl; | |
979 | u32 gt_fifoctl; | |
980 | u32 gtlc_wake_ctrl; | |
981 | u32 gtlc_survive; | |
982 | u32 pmwgicz; | |
983 | ||
984 | /* Display 2 CZ domain */ | |
985 | u32 gu_ctl0; | |
986 | u32 gu_ctl1; | |
987 | u32 clock_gate_dis2; | |
988 | }; | |
989 | ||
bf225f20 CW |
990 | struct intel_rps_ei { |
991 | u32 cz_clock; | |
992 | u32 render_c0; | |
993 | u32 media_c0; | |
31685c25 D |
994 | }; |
995 | ||
c85aa885 | 996 | struct intel_gen6_power_mgmt { |
d4d70aa5 ID |
997 | /* |
998 | * work, interrupts_enabled and pm_iir are protected by | |
999 | * dev_priv->irq_lock | |
1000 | */ | |
c85aa885 | 1001 | struct work_struct work; |
d4d70aa5 | 1002 | bool interrupts_enabled; |
c85aa885 | 1003 | u32 pm_iir; |
59cdb63d | 1004 | |
b39fb297 BW |
1005 | /* Frequencies are stored in potentially platform dependent multiples. |
1006 | * In other words, *_freq needs to be multiplied by X to be interesting. | |
1007 | * Soft limits are those which are used for the dynamic reclocking done | |
1008 | * by the driver (raise frequencies under heavy loads, and lower for | |
1009 | * lighter loads). Hard limits are those imposed by the hardware. | |
1010 | * | |
1011 | * A distinction is made for overclocking, which is never enabled by | |
1012 | * default, and is considered to be above the hard limit if it's | |
1013 | * possible at all. | |
1014 | */ | |
1015 | u8 cur_freq; /* Current frequency (cached, may not == HW) */ | |
1016 | u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ | |
1017 | u8 max_freq_softlimit; /* Max frequency permitted by the driver */ | |
1018 | u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ | |
1019 | u8 min_freq; /* AKA RPn. Minimum frequency */ | |
1020 | u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ | |
1021 | u8 rp1_freq; /* "less than" RP0 power/freqency */ | |
1022 | u8 rp0_freq; /* Non-overclocked max frequency. */ | |
67c3bf6f | 1023 | u32 cz_freq; |
1a01ab3b | 1024 | |
31685c25 | 1025 | u32 ei_interrupt_count; |
1a01ab3b | 1026 | |
dd75fdc8 CW |
1027 | int last_adj; |
1028 | enum { LOW_POWER, BETWEEN, HIGH_POWER } power; | |
1029 | ||
c0951f0c | 1030 | bool enabled; |
1a01ab3b | 1031 | struct delayed_work delayed_resume_work; |
4fc688ce | 1032 | |
bf225f20 CW |
1033 | /* manual wa residency calculations */ |
1034 | struct intel_rps_ei up_ei, down_ei; | |
1035 | ||
4fc688ce JB |
1036 | /* |
1037 | * Protects RPS/RC6 register access and PCU communication. | |
1038 | * Must be taken after struct_mutex if nested. | |
1039 | */ | |
1040 | struct mutex hw_lock; | |
c85aa885 DV |
1041 | }; |
1042 | ||
1a240d4d DV |
1043 | /* defined intel_pm.c */ |
1044 | extern spinlock_t mchdev_lock; | |
1045 | ||
c85aa885 DV |
1046 | struct intel_ilk_power_mgmt { |
1047 | u8 cur_delay; | |
1048 | u8 min_delay; | |
1049 | u8 max_delay; | |
1050 | u8 fmax; | |
1051 | u8 fstart; | |
1052 | ||
1053 | u64 last_count1; | |
1054 | unsigned long last_time1; | |
1055 | unsigned long chipset_power; | |
1056 | u64 last_count2; | |
5ed0bdf2 | 1057 | u64 last_time2; |
c85aa885 DV |
1058 | unsigned long gfx_power; |
1059 | u8 corr; | |
1060 | ||
1061 | int c_m; | |
1062 | int r_t; | |
3e373948 DV |
1063 | |
1064 | struct drm_i915_gem_object *pwrctx; | |
1065 | struct drm_i915_gem_object *renderctx; | |
c85aa885 DV |
1066 | }; |
1067 | ||
c6cb582e ID |
1068 | struct drm_i915_private; |
1069 | struct i915_power_well; | |
1070 | ||
1071 | struct i915_power_well_ops { | |
1072 | /* | |
1073 | * Synchronize the well's hw state to match the current sw state, for | |
1074 | * example enable/disable it based on the current refcount. Called | |
1075 | * during driver init and resume time, possibly after first calling | |
1076 | * the enable/disable handlers. | |
1077 | */ | |
1078 | void (*sync_hw)(struct drm_i915_private *dev_priv, | |
1079 | struct i915_power_well *power_well); | |
1080 | /* | |
1081 | * Enable the well and resources that depend on it (for example | |
1082 | * interrupts located on the well). Called after the 0->1 refcount | |
1083 | * transition. | |
1084 | */ | |
1085 | void (*enable)(struct drm_i915_private *dev_priv, | |
1086 | struct i915_power_well *power_well); | |
1087 | /* | |
1088 | * Disable the well and resources that depend on it. Called after | |
1089 | * the 1->0 refcount transition. | |
1090 | */ | |
1091 | void (*disable)(struct drm_i915_private *dev_priv, | |
1092 | struct i915_power_well *power_well); | |
1093 | /* Returns the hw enabled state. */ | |
1094 | bool (*is_enabled)(struct drm_i915_private *dev_priv, | |
1095 | struct i915_power_well *power_well); | |
1096 | }; | |
1097 | ||
a38911a3 WX |
1098 | /* Power well structure for haswell */ |
1099 | struct i915_power_well { | |
c1ca727f | 1100 | const char *name; |
6f3ef5dd | 1101 | bool always_on; |
a38911a3 WX |
1102 | /* power well enable/disable usage count */ |
1103 | int count; | |
bfafe93a ID |
1104 | /* cached hw enabled state */ |
1105 | bool hw_enabled; | |
c1ca727f | 1106 | unsigned long domains; |
77961eb9 | 1107 | unsigned long data; |
c6cb582e | 1108 | const struct i915_power_well_ops *ops; |
a38911a3 WX |
1109 | }; |
1110 | ||
83c00f55 | 1111 | struct i915_power_domains { |
baa70707 ID |
1112 | /* |
1113 | * Power wells needed for initialization at driver init and suspend | |
1114 | * time are on. They are kept on until after the first modeset. | |
1115 | */ | |
1116 | bool init_power_on; | |
0d116a29 | 1117 | bool initializing; |
c1ca727f | 1118 | int power_well_count; |
baa70707 | 1119 | |
83c00f55 | 1120 | struct mutex lock; |
1da51581 | 1121 | int domain_use_count[POWER_DOMAIN_NUM]; |
c1ca727f | 1122 | struct i915_power_well *power_wells; |
83c00f55 ID |
1123 | }; |
1124 | ||
35a85ac6 | 1125 | #define MAX_L3_SLICES 2 |
a4da4fa4 | 1126 | struct intel_l3_parity { |
35a85ac6 | 1127 | u32 *remap_info[MAX_L3_SLICES]; |
a4da4fa4 | 1128 | struct work_struct error_work; |
35a85ac6 | 1129 | int which_slice; |
a4da4fa4 DV |
1130 | }; |
1131 | ||
4b5aed62 | 1132 | struct i915_gem_mm { |
4b5aed62 DV |
1133 | /** Memory allocator for GTT stolen memory */ |
1134 | struct drm_mm stolen; | |
4b5aed62 DV |
1135 | /** List of all objects in gtt_space. Used to restore gtt |
1136 | * mappings on resume */ | |
1137 | struct list_head bound_list; | |
1138 | /** | |
1139 | * List of objects which are not bound to the GTT (thus | |
1140 | * are idle and not used by the GPU) but still have | |
1141 | * (presumably uncached) pages still attached. | |
1142 | */ | |
1143 | struct list_head unbound_list; | |
1144 | ||
1145 | /** Usable portion of the GTT for GEM */ | |
1146 | unsigned long stolen_base; /* limited to low memory (32-bit) */ | |
1147 | ||
4b5aed62 DV |
1148 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
1149 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
1150 | ||
2cfcd32a | 1151 | struct notifier_block oom_notifier; |
ceabbba5 | 1152 | struct shrinker shrinker; |
4b5aed62 DV |
1153 | bool shrinker_no_lock_stealing; |
1154 | ||
4b5aed62 DV |
1155 | /** LRU list of objects with fence regs on them. */ |
1156 | struct list_head fence_list; | |
1157 | ||
1158 | /** | |
1159 | * We leave the user IRQ off as much as possible, | |
1160 | * but this means that requests will finish and never | |
1161 | * be retired once the system goes idle. Set a timer to | |
1162 | * fire periodically while the ring is running. When it | |
1163 | * fires, go retire requests. | |
1164 | */ | |
1165 | struct delayed_work retire_work; | |
1166 | ||
b29c19b6 CW |
1167 | /** |
1168 | * When we detect an idle GPU, we want to turn on | |
1169 | * powersaving features. So once we see that there | |
1170 | * are no more requests outstanding and no more | |
1171 | * arrive within a small period of time, we fire | |
1172 | * off the idle_work. | |
1173 | */ | |
1174 | struct delayed_work idle_work; | |
1175 | ||
4b5aed62 DV |
1176 | /** |
1177 | * Are we in a non-interruptible section of code like | |
1178 | * modesetting? | |
1179 | */ | |
1180 | bool interruptible; | |
1181 | ||
f62a0076 CW |
1182 | /** |
1183 | * Is the GPU currently considered idle, or busy executing userspace | |
1184 | * requests? Whilst idle, we attempt to power down the hardware and | |
1185 | * display clocks. In order to reduce the effect on performance, there | |
1186 | * is a slight delay before we do so. | |
1187 | */ | |
1188 | bool busy; | |
1189 | ||
bdf1e7e3 DV |
1190 | /* the indicator for dispatch video commands on two BSD rings */ |
1191 | int bsd_ring_dispatch_index; | |
1192 | ||
4b5aed62 DV |
1193 | /** Bit 6 swizzling required for X tiling */ |
1194 | uint32_t bit_6_swizzle_x; | |
1195 | /** Bit 6 swizzling required for Y tiling */ | |
1196 | uint32_t bit_6_swizzle_y; | |
1197 | ||
4b5aed62 | 1198 | /* accounting, useful for userland debugging */ |
c20e8355 | 1199 | spinlock_t object_stat_lock; |
4b5aed62 DV |
1200 | size_t object_memory; |
1201 | u32 object_count; | |
1202 | }; | |
1203 | ||
edc3d884 | 1204 | struct drm_i915_error_state_buf { |
0a4cd7c8 | 1205 | struct drm_i915_private *i915; |
edc3d884 MK |
1206 | unsigned bytes; |
1207 | unsigned size; | |
1208 | int err; | |
1209 | u8 *buf; | |
1210 | loff_t start; | |
1211 | loff_t pos; | |
1212 | }; | |
1213 | ||
fc16b48b MK |
1214 | struct i915_error_state_file_priv { |
1215 | struct drm_device *dev; | |
1216 | struct drm_i915_error_state *error; | |
1217 | }; | |
1218 | ||
99584db3 DV |
1219 | struct i915_gpu_error { |
1220 | /* For hangcheck timer */ | |
1221 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ | |
1222 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) | |
be62acb4 MK |
1223 | /* Hang gpu twice in this window and your context gets banned */ |
1224 | #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) | |
1225 | ||
99584db3 | 1226 | struct timer_list hangcheck_timer; |
99584db3 DV |
1227 | |
1228 | /* For reset and error_state handling. */ | |
1229 | spinlock_t lock; | |
1230 | /* Protected by the above dev->gpu_error.lock. */ | |
1231 | struct drm_i915_error_state *first_error; | |
1232 | struct work_struct work; | |
99584db3 | 1233 | |
094f9a54 CW |
1234 | |
1235 | unsigned long missed_irq_rings; | |
1236 | ||
1f83fee0 | 1237 | /** |
2ac0f450 | 1238 | * State variable controlling the reset flow and count |
1f83fee0 | 1239 | * |
2ac0f450 MK |
1240 | * This is a counter which gets incremented when reset is triggered, |
1241 | * and again when reset has been handled. So odd values (lowest bit set) | |
1242 | * means that reset is in progress and even values that | |
1243 | * (reset_counter >> 1):th reset was successfully completed. | |
1244 | * | |
1245 | * If reset is not completed succesfully, the I915_WEDGE bit is | |
1246 | * set meaning that hardware is terminally sour and there is no | |
1247 | * recovery. All waiters on the reset_queue will be woken when | |
1248 | * that happens. | |
1249 | * | |
1250 | * This counter is used by the wait_seqno code to notice that reset | |
1251 | * event happened and it needs to restart the entire ioctl (since most | |
1252 | * likely the seqno it waited for won't ever signal anytime soon). | |
f69061be DV |
1253 | * |
1254 | * This is important for lock-free wait paths, where no contended lock | |
1255 | * naturally enforces the correct ordering between the bail-out of the | |
1256 | * waiter and the gpu reset work code. | |
1f83fee0 DV |
1257 | */ |
1258 | atomic_t reset_counter; | |
1259 | ||
1f83fee0 | 1260 | #define I915_RESET_IN_PROGRESS_FLAG 1 |
2ac0f450 | 1261 | #define I915_WEDGED (1 << 31) |
1f83fee0 DV |
1262 | |
1263 | /** | |
1264 | * Waitqueue to signal when the reset has completed. Used by clients | |
1265 | * that wait for dev_priv->mm.wedged to settle. | |
1266 | */ | |
1267 | wait_queue_head_t reset_queue; | |
33196ded | 1268 | |
88b4aa87 MK |
1269 | /* Userspace knobs for gpu hang simulation; |
1270 | * combines both a ring mask, and extra flags | |
1271 | */ | |
1272 | u32 stop_rings; | |
1273 | #define I915_STOP_RING_ALLOW_BAN (1 << 31) | |
1274 | #define I915_STOP_RING_ALLOW_WARN (1 << 30) | |
094f9a54 CW |
1275 | |
1276 | /* For missed irq/seqno simulation. */ | |
1277 | unsigned int test_irq_rings; | |
6689c167 MA |
1278 | |
1279 | /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */ | |
1280 | bool reload_in_reset; | |
99584db3 DV |
1281 | }; |
1282 | ||
b8efb17b ZR |
1283 | enum modeset_restore { |
1284 | MODESET_ON_LID_OPEN, | |
1285 | MODESET_DONE, | |
1286 | MODESET_SUSPENDED, | |
1287 | }; | |
1288 | ||
6acab15a | 1289 | struct ddi_vbt_port_info { |
ce4dd49e DL |
1290 | /* |
1291 | * This is an index in the HDMI/DVI DDI buffer translation table. | |
1292 | * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't | |
1293 | * populate this field. | |
1294 | */ | |
1295 | #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff | |
6acab15a | 1296 | uint8_t hdmi_level_shift; |
311a2094 PZ |
1297 | |
1298 | uint8_t supports_dvi:1; | |
1299 | uint8_t supports_hdmi:1; | |
1300 | uint8_t supports_dp:1; | |
6acab15a PZ |
1301 | }; |
1302 | ||
83a7280e PB |
1303 | enum drrs_support_type { |
1304 | DRRS_NOT_SUPPORTED = 0, | |
1305 | STATIC_DRRS_SUPPORT = 1, | |
1306 | SEAMLESS_DRRS_SUPPORT = 2 | |
1307 | }; | |
1308 | ||
bfd7ebda RV |
1309 | enum psr_lines_to_wait { |
1310 | PSR_0_LINES_TO_WAIT = 0, | |
1311 | PSR_1_LINE_TO_WAIT, | |
1312 | PSR_4_LINES_TO_WAIT, | |
1313 | PSR_8_LINES_TO_WAIT | |
1314 | }; | |
1315 | ||
41aa3448 RV |
1316 | struct intel_vbt_data { |
1317 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ | |
1318 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
1319 | ||
1320 | /* Feature bits */ | |
1321 | unsigned int int_tv_support:1; | |
1322 | unsigned int lvds_dither:1; | |
1323 | unsigned int lvds_vbt:1; | |
1324 | unsigned int int_crt_support:1; | |
1325 | unsigned int lvds_use_ssc:1; | |
1326 | unsigned int display_clock_mode:1; | |
1327 | unsigned int fdi_rx_polarity_inverted:1; | |
3e6bd011 | 1328 | unsigned int has_mipi:1; |
41aa3448 RV |
1329 | int lvds_ssc_freq; |
1330 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ | |
1331 | ||
83a7280e PB |
1332 | enum drrs_support_type drrs_type; |
1333 | ||
41aa3448 RV |
1334 | /* eDP */ |
1335 | int edp_rate; | |
1336 | int edp_lanes; | |
1337 | int edp_preemphasis; | |
1338 | int edp_vswing; | |
1339 | bool edp_initialized; | |
1340 | bool edp_support; | |
1341 | int edp_bpp; | |
1342 | struct edp_power_seq edp_pps; | |
1343 | ||
bfd7ebda RV |
1344 | struct { |
1345 | bool full_link; | |
1346 | bool require_aux_wakeup; | |
1347 | int idle_frames; | |
1348 | enum psr_lines_to_wait lines_to_wait; | |
1349 | int tp1_wakeup_time; | |
1350 | int tp2_tp3_wakeup_time; | |
1351 | } psr; | |
1352 | ||
f00076d2 JN |
1353 | struct { |
1354 | u16 pwm_freq_hz; | |
39fbc9c8 | 1355 | bool present; |
f00076d2 | 1356 | bool active_low_pwm; |
1de6068e | 1357 | u8 min_brightness; /* min_brightness/255 of max */ |
f00076d2 JN |
1358 | } backlight; |
1359 | ||
d17c5443 SK |
1360 | /* MIPI DSI */ |
1361 | struct { | |
3e6bd011 | 1362 | u16 port; |
d17c5443 | 1363 | u16 panel_id; |
d3b542fc SK |
1364 | struct mipi_config *config; |
1365 | struct mipi_pps_data *pps; | |
1366 | u8 seq_version; | |
1367 | u32 size; | |
1368 | u8 *data; | |
1369 | u8 *sequence[MIPI_SEQ_MAX]; | |
d17c5443 SK |
1370 | } dsi; |
1371 | ||
41aa3448 RV |
1372 | int crt_ddc_pin; |
1373 | ||
1374 | int child_dev_num; | |
768f69c9 | 1375 | union child_device_config *child_dev; |
6acab15a PZ |
1376 | |
1377 | struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; | |
41aa3448 RV |
1378 | }; |
1379 | ||
77c122bc VS |
1380 | enum intel_ddb_partitioning { |
1381 | INTEL_DDB_PART_1_2, | |
1382 | INTEL_DDB_PART_5_6, /* IVB+ */ | |
1383 | }; | |
1384 | ||
1fd527cc VS |
1385 | struct intel_wm_level { |
1386 | bool enable; | |
1387 | uint32_t pri_val; | |
1388 | uint32_t spr_val; | |
1389 | uint32_t cur_val; | |
1390 | uint32_t fbc_val; | |
1391 | }; | |
1392 | ||
820c1980 | 1393 | struct ilk_wm_values { |
609cedef VS |
1394 | uint32_t wm_pipe[3]; |
1395 | uint32_t wm_lp[3]; | |
1396 | uint32_t wm_lp_spr[3]; | |
1397 | uint32_t wm_linetime[3]; | |
1398 | bool enable_fbc_wm; | |
1399 | enum intel_ddb_partitioning partitioning; | |
1400 | }; | |
1401 | ||
c193924e | 1402 | struct skl_ddb_entry { |
16160e3d | 1403 | uint16_t start, end; /* in number of blocks, 'end' is exclusive */ |
c193924e DL |
1404 | }; |
1405 | ||
1406 | static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry) | |
1407 | { | |
16160e3d | 1408 | return entry->end - entry->start; |
c193924e DL |
1409 | } |
1410 | ||
08db6652 DL |
1411 | static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, |
1412 | const struct skl_ddb_entry *e2) | |
1413 | { | |
1414 | if (e1->start == e2->start && e1->end == e2->end) | |
1415 | return true; | |
1416 | ||
1417 | return false; | |
1418 | } | |
1419 | ||
c193924e | 1420 | struct skl_ddb_allocation { |
34bb56af | 1421 | struct skl_ddb_entry pipe[I915_MAX_PIPES]; |
c193924e DL |
1422 | struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; |
1423 | struct skl_ddb_entry cursor[I915_MAX_PIPES]; | |
1424 | }; | |
1425 | ||
2ac96d2a PB |
1426 | struct skl_wm_values { |
1427 | bool dirty[I915_MAX_PIPES]; | |
c193924e | 1428 | struct skl_ddb_allocation ddb; |
2ac96d2a PB |
1429 | uint32_t wm_linetime[I915_MAX_PIPES]; |
1430 | uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8]; | |
1431 | uint32_t cursor[I915_MAX_PIPES][8]; | |
1432 | uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES]; | |
1433 | uint32_t cursor_trans[I915_MAX_PIPES]; | |
1434 | }; | |
1435 | ||
1436 | struct skl_wm_level { | |
1437 | bool plane_en[I915_MAX_PLANES]; | |
b99f58da | 1438 | bool cursor_en; |
2ac96d2a PB |
1439 | uint16_t plane_res_b[I915_MAX_PLANES]; |
1440 | uint8_t plane_res_l[I915_MAX_PLANES]; | |
2ac96d2a PB |
1441 | uint16_t cursor_res_b; |
1442 | uint8_t cursor_res_l; | |
1443 | }; | |
1444 | ||
c67a470b | 1445 | /* |
765dab67 PZ |
1446 | * This struct helps tracking the state needed for runtime PM, which puts the |
1447 | * device in PCI D3 state. Notice that when this happens, nothing on the | |
1448 | * graphics device works, even register access, so we don't get interrupts nor | |
1449 | * anything else. | |
c67a470b | 1450 | * |
765dab67 PZ |
1451 | * Every piece of our code that needs to actually touch the hardware needs to |
1452 | * either call intel_runtime_pm_get or call intel_display_power_get with the | |
1453 | * appropriate power domain. | |
a8a8bd54 | 1454 | * |
765dab67 PZ |
1455 | * Our driver uses the autosuspend delay feature, which means we'll only really |
1456 | * suspend if we stay with zero refcount for a certain amount of time. The | |
f458ebbc | 1457 | * default value is currently very conservative (see intel_runtime_pm_enable), but |
765dab67 | 1458 | * it can be changed with the standard runtime PM files from sysfs. |
c67a470b PZ |
1459 | * |
1460 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and | |
1461 | * goes back to false exactly before we reenable the IRQs. We use this variable | |
1462 | * to check if someone is trying to enable/disable IRQs while they're supposed | |
1463 | * to be disabled. This shouldn't happen and we'll print some error messages in | |
730488b2 | 1464 | * case it happens. |
c67a470b | 1465 | * |
765dab67 | 1466 | * For more, read the Documentation/power/runtime_pm.txt. |
c67a470b | 1467 | */ |
5d584b2e PZ |
1468 | struct i915_runtime_pm { |
1469 | bool suspended; | |
2aeb7d3a | 1470 | bool irqs_enabled; |
c67a470b PZ |
1471 | }; |
1472 | ||
926321d5 DV |
1473 | enum intel_pipe_crc_source { |
1474 | INTEL_PIPE_CRC_SOURCE_NONE, | |
1475 | INTEL_PIPE_CRC_SOURCE_PLANE1, | |
1476 | INTEL_PIPE_CRC_SOURCE_PLANE2, | |
1477 | INTEL_PIPE_CRC_SOURCE_PF, | |
5b3a856b | 1478 | INTEL_PIPE_CRC_SOURCE_PIPE, |
3d099a05 DV |
1479 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ |
1480 | INTEL_PIPE_CRC_SOURCE_TV, | |
1481 | INTEL_PIPE_CRC_SOURCE_DP_B, | |
1482 | INTEL_PIPE_CRC_SOURCE_DP_C, | |
1483 | INTEL_PIPE_CRC_SOURCE_DP_D, | |
46a19188 | 1484 | INTEL_PIPE_CRC_SOURCE_AUTO, |
926321d5 DV |
1485 | INTEL_PIPE_CRC_SOURCE_MAX, |
1486 | }; | |
1487 | ||
8bf1e9f1 | 1488 | struct intel_pipe_crc_entry { |
ac2300d4 | 1489 | uint32_t frame; |
8bf1e9f1 SH |
1490 | uint32_t crc[5]; |
1491 | }; | |
1492 | ||
b2c88f5b | 1493 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 |
8bf1e9f1 | 1494 | struct intel_pipe_crc { |
d538bbdf DL |
1495 | spinlock_t lock; |
1496 | bool opened; /* exclusive access to the result file */ | |
e5f75aca | 1497 | struct intel_pipe_crc_entry *entries; |
926321d5 | 1498 | enum intel_pipe_crc_source source; |
d538bbdf | 1499 | int head, tail; |
07144428 | 1500 | wait_queue_head_t wq; |
8bf1e9f1 SH |
1501 | }; |
1502 | ||
f99d7069 DV |
1503 | struct i915_frontbuffer_tracking { |
1504 | struct mutex lock; | |
1505 | ||
1506 | /* | |
1507 | * Tracking bits for delayed frontbuffer flushing du to gpu activity or | |
1508 | * scheduled flips. | |
1509 | */ | |
1510 | unsigned busy_bits; | |
1511 | unsigned flip_bits; | |
1512 | }; | |
1513 | ||
7225342a MK |
1514 | struct i915_wa_reg { |
1515 | u32 addr; | |
1516 | u32 value; | |
1517 | /* bitmask representing WA bits */ | |
1518 | u32 mask; | |
1519 | }; | |
1520 | ||
1521 | #define I915_MAX_WA_REGS 16 | |
1522 | ||
1523 | struct i915_workarounds { | |
1524 | struct i915_wa_reg reg[I915_MAX_WA_REGS]; | |
1525 | u32 count; | |
1526 | }; | |
1527 | ||
77fec556 | 1528 | struct drm_i915_private { |
f4c956ad | 1529 | struct drm_device *dev; |
42dcedd4 | 1530 | struct kmem_cache *slab; |
f4c956ad | 1531 | |
5c969aa7 | 1532 | const struct intel_device_info info; |
f4c956ad DV |
1533 | |
1534 | int relative_constants_mode; | |
1535 | ||
1536 | void __iomem *regs; | |
1537 | ||
907b28c5 | 1538 | struct intel_uncore uncore; |
f4c956ad DV |
1539 | |
1540 | struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; | |
1541 | ||
28c70f16 | 1542 | |
f4c956ad DV |
1543 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
1544 | * controller on different i2c buses. */ | |
1545 | struct mutex gmbus_mutex; | |
1546 | ||
1547 | /** | |
1548 | * Base address of the gmbus and gpio block. | |
1549 | */ | |
1550 | uint32_t gpio_mmio_base; | |
1551 | ||
b6fdd0f2 SS |
1552 | /* MMIO base address for MIPI regs */ |
1553 | uint32_t mipi_mmio_base; | |
1554 | ||
28c70f16 DV |
1555 | wait_queue_head_t gmbus_wait_queue; |
1556 | ||
f4c956ad | 1557 | struct pci_dev *bridge_dev; |
a4872ba6 | 1558 | struct intel_engine_cs ring[I915_NUM_RINGS]; |
3e78998a | 1559 | struct drm_i915_gem_object *semaphore_obj; |
f72b3435 | 1560 | uint32_t last_seqno, next_seqno; |
f4c956ad | 1561 | |
ba8286fa | 1562 | struct drm_dma_handle *status_page_dmah; |
f4c956ad DV |
1563 | struct resource mch_res; |
1564 | ||
f4c956ad DV |
1565 | /* protects the irq masks */ |
1566 | spinlock_t irq_lock; | |
1567 | ||
84c33a64 SG |
1568 | /* protects the mmio flip data */ |
1569 | spinlock_t mmio_flip_lock; | |
1570 | ||
f8b79e58 ID |
1571 | bool display_irqs_enabled; |
1572 | ||
9ee32fea DV |
1573 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
1574 | struct pm_qos_request pm_qos; | |
1575 | ||
f4c956ad | 1576 | /* DPIO indirect register protection */ |
09153000 | 1577 | struct mutex dpio_lock; |
f4c956ad DV |
1578 | |
1579 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
abd58f01 BW |
1580 | union { |
1581 | u32 irq_mask; | |
1582 | u32 de_irq_mask[I915_MAX_PIPES]; | |
1583 | }; | |
f4c956ad | 1584 | u32 gt_irq_mask; |
605cd25b | 1585 | u32 pm_irq_mask; |
a6706b45 | 1586 | u32 pm_rps_events; |
91d181dd | 1587 | u32 pipestat_irq_mask[I915_MAX_PIPES]; |
f4c956ad | 1588 | |
f4c956ad | 1589 | struct work_struct hotplug_work; |
b543fb04 EE |
1590 | struct { |
1591 | unsigned long hpd_last_jiffies; | |
1592 | int hpd_cnt; | |
1593 | enum { | |
1594 | HPD_ENABLED = 0, | |
1595 | HPD_DISABLED = 1, | |
1596 | HPD_MARK_DISABLED = 2 | |
1597 | } hpd_mark; | |
1598 | } hpd_stats[HPD_NUM_PINS]; | |
142e2398 | 1599 | u32 hpd_event_bits; |
6323751d | 1600 | struct delayed_work hotplug_reenable_work; |
f4c956ad | 1601 | |
5c3fe8b0 | 1602 | struct i915_fbc fbc; |
439d7ac0 | 1603 | struct i915_drrs drrs; |
f4c956ad | 1604 | struct intel_opregion opregion; |
41aa3448 | 1605 | struct intel_vbt_data vbt; |
f4c956ad | 1606 | |
d9ceb816 JB |
1607 | bool preserve_bios_swizzle; |
1608 | ||
f4c956ad DV |
1609 | /* overlay */ |
1610 | struct intel_overlay *overlay; | |
f4c956ad | 1611 | |
58c68779 | 1612 | /* backlight registers and fields in struct intel_panel */ |
07f11d49 | 1613 | struct mutex backlight_lock; |
31ad8ec6 | 1614 | |
f4c956ad | 1615 | /* LVDS info */ |
f4c956ad DV |
1616 | bool no_aux_handshake; |
1617 | ||
e39b999a VS |
1618 | /* protects panel power sequencer state */ |
1619 | struct mutex pps_mutex; | |
1620 | ||
f4c956ad DV |
1621 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
1622 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ | |
1623 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
1624 | ||
1625 | unsigned int fsb_freq, mem_freq, is_ddr3; | |
d60c4473 | 1626 | unsigned int vlv_cdclk_freq; |
6bcda4f0 | 1627 | unsigned int hpll_freq; |
f4c956ad | 1628 | |
645416f5 DV |
1629 | /** |
1630 | * wq - Driver workqueue for GEM. | |
1631 | * | |
1632 | * NOTE: Work items scheduled here are not allowed to grab any modeset | |
1633 | * locks, for otherwise the flushing done in the pageflip code will | |
1634 | * result in deadlocks. | |
1635 | */ | |
f4c956ad DV |
1636 | struct workqueue_struct *wq; |
1637 | ||
1638 | /* Display functions */ | |
1639 | struct drm_i915_display_funcs display; | |
1640 | ||
1641 | /* PCH chipset type */ | |
1642 | enum intel_pch pch_type; | |
17a303ec | 1643 | unsigned short pch_id; |
f4c956ad DV |
1644 | |
1645 | unsigned long quirks; | |
1646 | ||
b8efb17b ZR |
1647 | enum modeset_restore modeset_restore; |
1648 | struct mutex modeset_restore_lock; | |
673a394b | 1649 | |
a7bbbd63 | 1650 | struct list_head vm_list; /* Global list of all address spaces */ |
0260c420 | 1651 | struct i915_gtt gtt; /* VM representing the global address space */ |
5d4545ae | 1652 | |
4b5aed62 | 1653 | struct i915_gem_mm mm; |
ad46cb53 CW |
1654 | DECLARE_HASHTABLE(mm_structs, 7); |
1655 | struct mutex mm_lock; | |
8781342d | 1656 | |
8781342d DV |
1657 | /* Kernel Modesetting */ |
1658 | ||
9b9d172d | 1659 | struct sdvo_device_mapping sdvo_mappings[2]; |
652c393a | 1660 | |
76c4ac04 DL |
1661 | struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; |
1662 | struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; | |
6b95a207 KH |
1663 | wait_queue_head_t pending_flip_queue; |
1664 | ||
c4597872 DV |
1665 | #ifdef CONFIG_DEBUG_FS |
1666 | struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; | |
1667 | #endif | |
1668 | ||
e72f9fbf DV |
1669 | int num_shared_dpll; |
1670 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; | |
e4607fcf | 1671 | int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; |
ee7b9f93 | 1672 | |
7225342a | 1673 | struct i915_workarounds workarounds; |
888b5995 | 1674 | |
652c393a JB |
1675 | /* Reclocking support */ |
1676 | bool render_reclock_avail; | |
1677 | bool lvds_downclock_avail; | |
18f9ed12 ZY |
1678 | /* indicates the reduced downclock for LVDS*/ |
1679 | int lvds_downclock; | |
f99d7069 DV |
1680 | |
1681 | struct i915_frontbuffer_tracking fb_tracking; | |
1682 | ||
652c393a | 1683 | u16 orig_clock; |
f97108d1 | 1684 | |
c4804411 | 1685 | bool mchbar_need_disable; |
f97108d1 | 1686 | |
a4da4fa4 DV |
1687 | struct intel_l3_parity l3_parity; |
1688 | ||
59124506 BW |
1689 | /* Cannot be determined by PCIID. You must always read a register. */ |
1690 | size_t ellc_size; | |
1691 | ||
c6a828d3 | 1692 | /* gen6+ rps state */ |
c85aa885 | 1693 | struct intel_gen6_power_mgmt rps; |
c6a828d3 | 1694 | |
20e4d407 DV |
1695 | /* ilk-only ips/rps state. Everything in here is protected by the global |
1696 | * mchdev_lock in intel_pm.c */ | |
c85aa885 | 1697 | struct intel_ilk_power_mgmt ips; |
b5e50c3f | 1698 | |
83c00f55 | 1699 | struct i915_power_domains power_domains; |
a38911a3 | 1700 | |
a031d709 | 1701 | struct i915_psr psr; |
3f51e471 | 1702 | |
99584db3 | 1703 | struct i915_gpu_error gpu_error; |
ae681d96 | 1704 | |
c9cddffc JB |
1705 | struct drm_i915_gem_object *vlv_pctx; |
1706 | ||
4520f53a | 1707 | #ifdef CONFIG_DRM_I915_FBDEV |
8be48d92 DA |
1708 | /* list of fbdev register on this device */ |
1709 | struct intel_fbdev *fbdev; | |
82e3b8c1 | 1710 | struct work_struct fbdev_suspend_work; |
4520f53a | 1711 | #endif |
e953fd7b CW |
1712 | |
1713 | struct drm_property *broadcast_rgb_property; | |
3f43c48d | 1714 | struct drm_property *force_audio_property; |
e3689190 | 1715 | |
254f965c | 1716 | uint32_t hw_context_size; |
a33afea5 | 1717 | struct list_head context_list; |
f4c956ad | 1718 | |
3e68320e | 1719 | u32 fdi_rx_config; |
68d18ad7 | 1720 | |
842f1c8b | 1721 | u32 suspend_count; |
f4c956ad | 1722 | struct i915_suspend_saved_registers regfile; |
ddeea5b0 | 1723 | struct vlv_s0ix_state vlv_s0ix_state; |
231f42a4 | 1724 | |
53615a5e VS |
1725 | struct { |
1726 | /* | |
1727 | * Raw watermark latency values: | |
1728 | * in 0.1us units for WM0, | |
1729 | * in 0.5us units for WM1+. | |
1730 | */ | |
1731 | /* primary */ | |
1732 | uint16_t pri_latency[5]; | |
1733 | /* sprite */ | |
1734 | uint16_t spr_latency[5]; | |
1735 | /* cursor */ | |
1736 | uint16_t cur_latency[5]; | |
2af30a5c PB |
1737 | /* |
1738 | * Raw watermark memory latency values | |
1739 | * for SKL for all 8 levels | |
1740 | * in 1us units. | |
1741 | */ | |
1742 | uint16_t skl_latency[8]; | |
609cedef | 1743 | |
2d41c0b5 PB |
1744 | /* |
1745 | * The skl_wm_values structure is a bit too big for stack | |
1746 | * allocation, so we keep the staging struct where we store | |
1747 | * intermediate results here instead. | |
1748 | */ | |
1749 | struct skl_wm_values skl_results; | |
1750 | ||
609cedef | 1751 | /* current hardware state */ |
2d41c0b5 PB |
1752 | union { |
1753 | struct ilk_wm_values hw; | |
1754 | struct skl_wm_values skl_hw; | |
1755 | }; | |
53615a5e VS |
1756 | } wm; |
1757 | ||
8a187455 PZ |
1758 | struct i915_runtime_pm pm; |
1759 | ||
13cf5504 DA |
1760 | struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS]; |
1761 | u32 long_hpd_port_mask; | |
1762 | u32 short_hpd_port_mask; | |
1763 | struct work_struct dig_port_work; | |
1764 | ||
0e32b39c DA |
1765 | /* |
1766 | * if we get a HPD irq from DP and a HPD irq from non-DP | |
1767 | * the non-DP HPD could block the workqueue on a mode config | |
1768 | * mutex getting, that userspace may have taken. However | |
1769 | * userspace is waiting on the DP workqueue to run which is | |
1770 | * blocked behind the non-DP one. | |
1771 | */ | |
1772 | struct workqueue_struct *dp_wq; | |
1773 | ||
69769f9a VS |
1774 | uint32_t bios_vgacntr; |
1775 | ||
a83014d3 OM |
1776 | /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ |
1777 | struct { | |
1778 | int (*do_execbuf)(struct drm_device *dev, struct drm_file *file, | |
1779 | struct intel_engine_cs *ring, | |
1780 | struct intel_context *ctx, | |
1781 | struct drm_i915_gem_execbuffer2 *args, | |
1782 | struct list_head *vmas, | |
1783 | struct drm_i915_gem_object *batch_obj, | |
1784 | u64 exec_start, u32 flags); | |
1785 | int (*init_rings)(struct drm_device *dev); | |
1786 | void (*cleanup_ring)(struct intel_engine_cs *ring); | |
1787 | void (*stop_ring)(struct intel_engine_cs *ring); | |
1788 | } gt; | |
1789 | ||
bdf1e7e3 DV |
1790 | /* |
1791 | * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch | |
1792 | * will be rejected. Instead look for a better place. | |
1793 | */ | |
77fec556 | 1794 | }; |
1da177e4 | 1795 | |
2c1792a1 CW |
1796 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) |
1797 | { | |
1798 | return dev->dev_private; | |
1799 | } | |
1800 | ||
b4519513 CW |
1801 | /* Iterate over initialised rings */ |
1802 | #define for_each_ring(ring__, dev_priv__, i__) \ | |
1803 | for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ | |
1804 | if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) | |
1805 | ||
b1d7e4b4 WF |
1806 | enum hdmi_force_audio { |
1807 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
1808 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
1809 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
1810 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
1811 | }; | |
1812 | ||
190d6cd5 | 1813 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
ed2f3452 | 1814 | |
37e680a1 CW |
1815 | struct drm_i915_gem_object_ops { |
1816 | /* Interface between the GEM object and its backing storage. | |
1817 | * get_pages() is called once prior to the use of the associated set | |
1818 | * of pages before to binding them into the GTT, and put_pages() is | |
1819 | * called after we no longer need them. As we expect there to be | |
1820 | * associated cost with migrating pages between the backing storage | |
1821 | * and making them available for the GPU (e.g. clflush), we may hold | |
1822 | * onto the pages after they are no longer referenced by the GPU | |
1823 | * in case they may be used again shortly (for example migrating the | |
1824 | * pages to a different memory domain within the GTT). put_pages() | |
1825 | * will therefore most likely be called when the object itself is | |
1826 | * being released or under memory pressure (where we attempt to | |
1827 | * reap pages for the shrinker). | |
1828 | */ | |
1829 | int (*get_pages)(struct drm_i915_gem_object *); | |
1830 | void (*put_pages)(struct drm_i915_gem_object *); | |
5cc9ed4b CW |
1831 | int (*dmabuf_export)(struct drm_i915_gem_object *); |
1832 | void (*release)(struct drm_i915_gem_object *); | |
37e680a1 CW |
1833 | }; |
1834 | ||
a071fa00 DV |
1835 | /* |
1836 | * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is | |
1837 | * considered to be the frontbuffer for the given plane interface-vise. This | |
1838 | * doesn't mean that the hw necessarily already scans it out, but that any | |
1839 | * rendering (by the cpu or gpu) will land in the frontbuffer eventually. | |
1840 | * | |
1841 | * We have one bit per pipe and per scanout plane type. | |
1842 | */ | |
1843 | #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4 | |
1844 | #define INTEL_FRONTBUFFER_BITS \ | |
1845 | (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES) | |
1846 | #define INTEL_FRONTBUFFER_PRIMARY(pipe) \ | |
1847 | (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) | |
1848 | #define INTEL_FRONTBUFFER_CURSOR(pipe) \ | |
1849 | (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
1850 | #define INTEL_FRONTBUFFER_SPRITE(pipe) \ | |
1851 | (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
1852 | #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ | |
1853 | (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
cc36513c DV |
1854 | #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ |
1855 | (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) | |
a071fa00 | 1856 | |
673a394b | 1857 | struct drm_i915_gem_object { |
c397b908 | 1858 | struct drm_gem_object base; |
673a394b | 1859 | |
37e680a1 CW |
1860 | const struct drm_i915_gem_object_ops *ops; |
1861 | ||
2f633156 BW |
1862 | /** List of VMAs backed by this object */ |
1863 | struct list_head vma_list; | |
1864 | ||
c1ad11fc CW |
1865 | /** Stolen memory for this object, instead of being backed by shmem. */ |
1866 | struct drm_mm_node *stolen; | |
35c20a60 | 1867 | struct list_head global_list; |
673a394b | 1868 | |
69dc4987 | 1869 | struct list_head ring_list; |
b25cb2f8 BW |
1870 | /** Used in execbuf to temporarily hold a ref */ |
1871 | struct list_head obj_exec_link; | |
673a394b EA |
1872 | |
1873 | /** | |
65ce3027 CW |
1874 | * This is set if the object is on the active lists (has pending |
1875 | * rendering and so a non-zero seqno), and is not set if it i s on | |
1876 | * inactive (ready to be unbound) list. | |
673a394b | 1877 | */ |
0206e353 | 1878 | unsigned int active:1; |
673a394b EA |
1879 | |
1880 | /** | |
1881 | * This is set if the object has been written to since last bound | |
1882 | * to the GTT | |
1883 | */ | |
0206e353 | 1884 | unsigned int dirty:1; |
778c3544 DV |
1885 | |
1886 | /** | |
1887 | * Fence register bits (if any) for this object. Will be set | |
1888 | * as needed when mapped into the GTT. | |
1889 | * Protected by dev->struct_mutex. | |
778c3544 | 1890 | */ |
4b9de737 | 1891 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
778c3544 | 1892 | |
778c3544 DV |
1893 | /** |
1894 | * Advice: are the backing pages purgeable? | |
1895 | */ | |
0206e353 | 1896 | unsigned int madv:2; |
778c3544 | 1897 | |
778c3544 DV |
1898 | /** |
1899 | * Current tiling mode for the object. | |
1900 | */ | |
0206e353 | 1901 | unsigned int tiling_mode:2; |
5d82e3e6 CW |
1902 | /** |
1903 | * Whether the tiling parameters for the currently associated fence | |
1904 | * register have changed. Note that for the purposes of tracking | |
1905 | * tiling changes we also treat the unfenced register, the register | |
1906 | * slot that the object occupies whilst it executes a fenced | |
1907 | * command (such as BLT on gen2/3), as a "fence". | |
1908 | */ | |
1909 | unsigned int fence_dirty:1; | |
778c3544 | 1910 | |
75e9e915 DV |
1911 | /** |
1912 | * Is the object at the current location in the gtt mappable and | |
1913 | * fenceable? Used to avoid costly recalculations. | |
1914 | */ | |
0206e353 | 1915 | unsigned int map_and_fenceable:1; |
75e9e915 | 1916 | |
fb7d516a DV |
1917 | /** |
1918 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
1919 | * mappable by accident). Track pin and fault separate for a more | |
1920 | * accurate mappable working set. | |
1921 | */ | |
0206e353 AJ |
1922 | unsigned int fault_mappable:1; |
1923 | unsigned int pin_mappable:1; | |
cc98b413 | 1924 | unsigned int pin_display:1; |
fb7d516a | 1925 | |
24f3a8cf AG |
1926 | /* |
1927 | * Is the object to be mapped as read-only to the GPU | |
1928 | * Only honoured if hardware has relevant pte bit | |
1929 | */ | |
1930 | unsigned long gt_ro:1; | |
651d794f | 1931 | unsigned int cache_level:3; |
93dfb40c | 1932 | |
9da3da66 | 1933 | unsigned int has_dma_mapping:1; |
7bddb01f | 1934 | |
a071fa00 DV |
1935 | unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS; |
1936 | ||
9da3da66 | 1937 | struct sg_table *pages; |
a5570178 | 1938 | int pages_pin_count; |
673a394b | 1939 | |
1286ff73 | 1940 | /* prime dma-buf support */ |
9a70cc2a DA |
1941 | void *dma_buf_vmapping; |
1942 | int vmapping_count; | |
1943 | ||
a4872ba6 | 1944 | struct intel_engine_cs *ring; |
caea7476 | 1945 | |
1c293ea3 | 1946 | /** Breadcrumb of last rendering to the buffer. */ |
97b2a6a1 JH |
1947 | struct drm_i915_gem_request *last_read_req; |
1948 | struct drm_i915_gem_request *last_write_req; | |
caea7476 | 1949 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
97b2a6a1 | 1950 | struct drm_i915_gem_request *last_fenced_req; |
673a394b | 1951 | |
778c3544 | 1952 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 1953 | uint32_t stride; |
673a394b | 1954 | |
80075d49 DV |
1955 | /** References from framebuffers, locks out tiling changes. */ |
1956 | unsigned long framebuffer_references; | |
1957 | ||
280b713b | 1958 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 1959 | unsigned long *bit_17; |
280b713b | 1960 | |
5cc9ed4b | 1961 | union { |
6a2c4232 CW |
1962 | /** for phy allocated objects */ |
1963 | struct drm_dma_handle *phys_handle; | |
1964 | ||
5cc9ed4b CW |
1965 | struct i915_gem_userptr { |
1966 | uintptr_t ptr; | |
1967 | unsigned read_only :1; | |
1968 | unsigned workers :4; | |
1969 | #define I915_GEM_USERPTR_MAX_WORKERS 15 | |
1970 | ||
ad46cb53 CW |
1971 | struct i915_mm_struct *mm; |
1972 | struct i915_mmu_object *mmu_object; | |
5cc9ed4b CW |
1973 | struct work_struct *work; |
1974 | } userptr; | |
1975 | }; | |
1976 | }; | |
62b8b215 | 1977 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 1978 | |
a071fa00 DV |
1979 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
1980 | struct drm_i915_gem_object *new, | |
1981 | unsigned frontbuffer_bits); | |
1982 | ||
673a394b EA |
1983 | /** |
1984 | * Request queue structure. | |
1985 | * | |
1986 | * The request queue allows us to note sequence numbers that have been emitted | |
1987 | * and may be associated with active buffers to be retired. | |
1988 | * | |
97b2a6a1 JH |
1989 | * By keeping this list, we can avoid having to do questionable sequence |
1990 | * number comparisons on buffer last_read|write_seqno. It also allows an | |
1991 | * emission time to be associated with the request for tracking how far ahead | |
1992 | * of the GPU the submission is. | |
673a394b EA |
1993 | */ |
1994 | struct drm_i915_gem_request { | |
abfe262a JH |
1995 | struct kref ref; |
1996 | ||
852835f3 | 1997 | /** On Which ring this request was generated */ |
a4872ba6 | 1998 | struct intel_engine_cs *ring; |
852835f3 | 1999 | |
673a394b EA |
2000 | /** GEM sequence number associated with this request. */ |
2001 | uint32_t seqno; | |
2002 | ||
7d736f4f MK |
2003 | /** Position in the ringbuffer of the start of the request */ |
2004 | u32 head; | |
2005 | ||
2006 | /** Position in the ringbuffer of the end of the request */ | |
a71d8d94 CW |
2007 | u32 tail; |
2008 | ||
0e50e96b | 2009 | /** Context related to this request */ |
273497e5 | 2010 | struct intel_context *ctx; |
0e50e96b | 2011 | |
7d736f4f MK |
2012 | /** Batch buffer related to this request if any */ |
2013 | struct drm_i915_gem_object *batch_obj; | |
2014 | ||
673a394b EA |
2015 | /** Time at which this request was emitted, in jiffies. */ |
2016 | unsigned long emitted_jiffies; | |
2017 | ||
b962442e | 2018 | /** global list entry for this request */ |
673a394b | 2019 | struct list_head list; |
b962442e | 2020 | |
f787a5f5 | 2021 | struct drm_i915_file_private *file_priv; |
b962442e EA |
2022 | /** file_priv list entry for this request */ |
2023 | struct list_head client_list; | |
673a394b EA |
2024 | }; |
2025 | ||
abfe262a JH |
2026 | void i915_gem_request_free(struct kref *req_ref); |
2027 | ||
b793a00a JH |
2028 | static inline uint32_t |
2029 | i915_gem_request_get_seqno(struct drm_i915_gem_request *req) | |
2030 | { | |
2031 | return req ? req->seqno : 0; | |
2032 | } | |
2033 | ||
2034 | static inline struct intel_engine_cs * | |
2035 | i915_gem_request_get_ring(struct drm_i915_gem_request *req) | |
2036 | { | |
2037 | return req ? req->ring : NULL; | |
2038 | } | |
2039 | ||
abfe262a JH |
2040 | static inline void |
2041 | i915_gem_request_reference(struct drm_i915_gem_request *req) | |
2042 | { | |
2043 | kref_get(&req->ref); | |
2044 | } | |
2045 | ||
2046 | static inline void | |
2047 | i915_gem_request_unreference(struct drm_i915_gem_request *req) | |
2048 | { | |
2049 | kref_put(&req->ref, i915_gem_request_free); | |
2050 | } | |
2051 | ||
2052 | static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst, | |
2053 | struct drm_i915_gem_request *src) | |
2054 | { | |
2055 | if (src) | |
2056 | i915_gem_request_reference(src); | |
2057 | ||
2058 | if (*pdst) | |
2059 | i915_gem_request_unreference(*pdst); | |
2060 | ||
2061 | *pdst = src; | |
2062 | } | |
2063 | ||
673a394b | 2064 | struct drm_i915_file_private { |
b29c19b6 | 2065 | struct drm_i915_private *dev_priv; |
ab0e7ff9 | 2066 | struct drm_file *file; |
b29c19b6 | 2067 | |
673a394b | 2068 | struct { |
99057c81 | 2069 | spinlock_t lock; |
b962442e | 2070 | struct list_head request_list; |
b29c19b6 | 2071 | struct delayed_work idle_work; |
673a394b | 2072 | } mm; |
40521054 | 2073 | struct idr context_idr; |
e59ec13d | 2074 | |
b29c19b6 | 2075 | atomic_t rps_wait_boost; |
a4872ba6 | 2076 | struct intel_engine_cs *bsd_ring; |
673a394b EA |
2077 | }; |
2078 | ||
351e3db2 BV |
2079 | /* |
2080 | * A command that requires special handling by the command parser. | |
2081 | */ | |
2082 | struct drm_i915_cmd_descriptor { | |
2083 | /* | |
2084 | * Flags describing how the command parser processes the command. | |
2085 | * | |
2086 | * CMD_DESC_FIXED: The command has a fixed length if this is set, | |
2087 | * a length mask if not set | |
2088 | * CMD_DESC_SKIP: The command is allowed but does not follow the | |
2089 | * standard length encoding for the opcode range in | |
2090 | * which it falls | |
2091 | * CMD_DESC_REJECT: The command is never allowed | |
2092 | * CMD_DESC_REGISTER: The command should be checked against the | |
2093 | * register whitelist for the appropriate ring | |
2094 | * CMD_DESC_MASTER: The command is allowed if the submitting process | |
2095 | * is the DRM master | |
2096 | */ | |
2097 | u32 flags; | |
2098 | #define CMD_DESC_FIXED (1<<0) | |
2099 | #define CMD_DESC_SKIP (1<<1) | |
2100 | #define CMD_DESC_REJECT (1<<2) | |
2101 | #define CMD_DESC_REGISTER (1<<3) | |
2102 | #define CMD_DESC_BITMASK (1<<4) | |
2103 | #define CMD_DESC_MASTER (1<<5) | |
2104 | ||
2105 | /* | |
2106 | * The command's unique identification bits and the bitmask to get them. | |
2107 | * This isn't strictly the opcode field as defined in the spec and may | |
2108 | * also include type, subtype, and/or subop fields. | |
2109 | */ | |
2110 | struct { | |
2111 | u32 value; | |
2112 | u32 mask; | |
2113 | } cmd; | |
2114 | ||
2115 | /* | |
2116 | * The command's length. The command is either fixed length (i.e. does | |
2117 | * not include a length field) or has a length field mask. The flag | |
2118 | * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has | |
2119 | * a length mask. All command entries in a command table must include | |
2120 | * length information. | |
2121 | */ | |
2122 | union { | |
2123 | u32 fixed; | |
2124 | u32 mask; | |
2125 | } length; | |
2126 | ||
2127 | /* | |
2128 | * Describes where to find a register address in the command to check | |
2129 | * against the ring's register whitelist. Only valid if flags has the | |
2130 | * CMD_DESC_REGISTER bit set. | |
2131 | */ | |
2132 | struct { | |
2133 | u32 offset; | |
2134 | u32 mask; | |
2135 | } reg; | |
2136 | ||
2137 | #define MAX_CMD_DESC_BITMASKS 3 | |
2138 | /* | |
2139 | * Describes command checks where a particular dword is masked and | |
2140 | * compared against an expected value. If the command does not match | |
2141 | * the expected value, the parser rejects it. Only valid if flags has | |
2142 | * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero | |
2143 | * are valid. | |
d4d48035 BV |
2144 | * |
2145 | * If the check specifies a non-zero condition_mask then the parser | |
2146 | * only performs the check when the bits specified by condition_mask | |
2147 | * are non-zero. | |
351e3db2 BV |
2148 | */ |
2149 | struct { | |
2150 | u32 offset; | |
2151 | u32 mask; | |
2152 | u32 expected; | |
d4d48035 BV |
2153 | u32 condition_offset; |
2154 | u32 condition_mask; | |
351e3db2 BV |
2155 | } bits[MAX_CMD_DESC_BITMASKS]; |
2156 | }; | |
2157 | ||
2158 | /* | |
2159 | * A table of commands requiring special handling by the command parser. | |
2160 | * | |
2161 | * Each ring has an array of tables. Each table consists of an array of command | |
2162 | * descriptors, which must be sorted with command opcodes in ascending order. | |
2163 | */ | |
2164 | struct drm_i915_cmd_table { | |
2165 | const struct drm_i915_cmd_descriptor *table; | |
2166 | int count; | |
2167 | }; | |
2168 | ||
dbbe9127 | 2169 | /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */ |
7312e2dd CW |
2170 | #define __I915__(p) ({ \ |
2171 | struct drm_i915_private *__p; \ | |
2172 | if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \ | |
2173 | __p = (struct drm_i915_private *)p; \ | |
2174 | else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \ | |
2175 | __p = to_i915((struct drm_device *)p); \ | |
2176 | else \ | |
2177 | BUILD_BUG(); \ | |
2178 | __p; \ | |
2179 | }) | |
dbbe9127 | 2180 | #define INTEL_INFO(p) (&__I915__(p)->info) |
87f1f465 | 2181 | #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id) |
cae5852d | 2182 | |
87f1f465 CW |
2183 | #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577) |
2184 | #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562) | |
cae5852d | 2185 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
87f1f465 | 2186 | #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572) |
cae5852d | 2187 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
87f1f465 CW |
2188 | #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592) |
2189 | #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772) | |
cae5852d ZN |
2190 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
2191 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
2192 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
87f1f465 | 2193 | #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42) |
cae5852d | 2194 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
87f1f465 CW |
2195 | #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001) |
2196 | #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011) | |
cae5852d ZN |
2197 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
2198 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
87f1f465 | 2199 | #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046) |
4b65177b | 2200 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
87f1f465 CW |
2201 | #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \ |
2202 | INTEL_DEVID(dev) == 0x0152 || \ | |
2203 | INTEL_DEVID(dev) == 0x015a) | |
2204 | #define IS_SNB_GT1(dev) (INTEL_DEVID(dev) == 0x0102 || \ | |
2205 | INTEL_DEVID(dev) == 0x0106 || \ | |
2206 | INTEL_DEVID(dev) == 0x010A) | |
70a3eb7a | 2207 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
6df4027b | 2208 | #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) |
4cae9ae0 | 2209 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
8179f1f0 | 2210 | #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) |
7201c0b3 | 2211 | #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake) |
cae5852d | 2212 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
ed1c9e2c | 2213 | #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2214 | (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) |
5dd8c4c3 | 2215 | #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ |
87f1f465 CW |
2216 | ((INTEL_DEVID(dev) & 0xf) == 0x2 || \ |
2217 | (INTEL_DEVID(dev) & 0xf) == 0x6 || \ | |
2218 | (INTEL_DEVID(dev) & 0xf) == 0xe)) | |
a0fcbd95 RV |
2219 | #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \ |
2220 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) | |
5dd8c4c3 | 2221 | #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2222 | (INTEL_DEVID(dev) & 0xFF00) == 0x0A00) |
9435373e | 2223 | #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2224 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) |
9bbfd20a | 2225 | /* ULX machines are also considered ULT. */ |
87f1f465 CW |
2226 | #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \ |
2227 | INTEL_DEVID(dev) == 0x0A1E) | |
b833d685 | 2228 | #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) |
cae5852d | 2229 | |
85436696 JB |
2230 | /* |
2231 | * The genX designation typically refers to the render engine, so render | |
2232 | * capability related checks should use IS_GEN, while display and other checks | |
2233 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
2234 | * chips, etc.). | |
2235 | */ | |
cae5852d ZN |
2236 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
2237 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) | |
2238 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) | |
2239 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) | |
2240 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) | |
85436696 | 2241 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
d2980845 | 2242 | #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8) |
b71252dc | 2243 | #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9) |
cae5852d | 2244 | |
73ae478c BW |
2245 | #define RENDER_RING (1<<RCS) |
2246 | #define BSD_RING (1<<VCS) | |
2247 | #define BLT_RING (1<<BCS) | |
2248 | #define VEBOX_RING (1<<VECS) | |
845f74a7 | 2249 | #define BSD2_RING (1<<VCS2) |
63c42e56 | 2250 | #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) |
845f74a7 | 2251 | #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING) |
63c42e56 BW |
2252 | #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) |
2253 | #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) | |
2254 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) | |
2255 | #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ | |
f2fbc690 | 2256 | __I915__(dev)->ellc_size) |
cae5852d ZN |
2257 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
2258 | ||
254f965c | 2259 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
d7f621e5 | 2260 | #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8) |
692ef70c JB |
2261 | #define USES_PPGTT(dev) (i915.enable_ppgtt) |
2262 | #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2) | |
1d2a314c | 2263 | |
05394f39 | 2264 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
cae5852d ZN |
2265 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
2266 | ||
b45305fc DV |
2267 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
2268 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) | |
4e6b788c DV |
2269 | /* |
2270 | * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts | |
2271 | * even when in MSI mode. This results in spurious interrupt warnings if the | |
2272 | * legacy irq no. is shared with another device. The kernel then disables that | |
2273 | * interrupt source and so prevents the other device from working properly. | |
2274 | */ | |
2275 | #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
2276 | #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
b45305fc | 2277 | |
cae5852d ZN |
2278 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
2279 | * rows, which changed the alignment requirements and fence programming. | |
2280 | */ | |
2281 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
2282 | IS_I915GM(dev))) | |
2283 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) | |
2284 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
2285 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
cae5852d ZN |
2286 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
2287 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
cae5852d ZN |
2288 | |
2289 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
2290 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
3a77c4c4 | 2291 | #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
cae5852d | 2292 | |
dbf7786e | 2293 | #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev)) |
f5adf94e | 2294 | |
dd93be58 | 2295 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) |
30568c45 | 2296 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) |
b32c6f48 RV |
2297 | #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ |
2298 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) | |
6157d3c8 | 2299 | #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ |
fd7f8cce | 2300 | IS_BROADWELL(dev) || IS_VALLEYVIEW(dev)) |
58abf1da RV |
2301 | #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) |
2302 | #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev)) | |
affa9354 | 2303 | |
17a303ec PZ |
2304 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
2305 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 | |
2306 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
2307 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 | |
2308 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 | |
2309 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 | |
e7e7ea20 S |
2310 | #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 |
2311 | #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 | |
17a303ec | 2312 | |
f2fbc690 | 2313 | #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type) |
e7e7ea20 | 2314 | #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT) |
eb877ebf | 2315 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
cae5852d ZN |
2316 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
2317 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
40c7ead9 | 2318 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
45e6e3a1 | 2319 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
cae5852d | 2320 | |
5fafe292 SJ |
2321 | #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)) |
2322 | ||
040d2baa BW |
2323 | /* DPF == dynamic parity feature */ |
2324 | #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
2325 | #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) | |
e1ef7cc2 | 2326 | |
c8735b0c BW |
2327 | #define GT_FREQUENCY_MULTIPLIER 50 |
2328 | ||
05394f39 CW |
2329 | #include "i915_trace.h" |
2330 | ||
baa70943 | 2331 | extern const struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 DA |
2332 | extern int i915_max_ioctl; |
2333 | ||
fc49b3da ID |
2334 | extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state); |
2335 | extern int i915_resume_legacy(struct drm_device *dev); | |
7c1c2871 DA |
2336 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
2337 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); | |
2338 | ||
d330a953 JN |
2339 | /* i915_params.c */ |
2340 | struct i915_params { | |
2341 | int modeset; | |
2342 | int panel_ignore_lid; | |
2343 | unsigned int powersave; | |
2344 | int semaphores; | |
2345 | unsigned int lvds_downclock; | |
2346 | int lvds_channel_mode; | |
2347 | int panel_use_ssc; | |
2348 | int vbt_sdvo_panel_type; | |
2349 | int enable_rc6; | |
2350 | int enable_fbc; | |
d330a953 | 2351 | int enable_ppgtt; |
127f1003 | 2352 | int enable_execlists; |
d330a953 JN |
2353 | int enable_psr; |
2354 | unsigned int preliminary_hw_support; | |
2355 | int disable_power_well; | |
2356 | int enable_ips; | |
e5aa6541 | 2357 | int invert_brightness; |
351e3db2 | 2358 | int enable_cmd_parser; |
e5aa6541 DL |
2359 | /* leave bools at the end to not create holes */ |
2360 | bool enable_hangcheck; | |
2361 | bool fastboot; | |
d330a953 JN |
2362 | bool prefault_disable; |
2363 | bool reset; | |
a0bae57f | 2364 | bool disable_display; |
7a10dfa6 | 2365 | bool disable_vtd_wa; |
84c33a64 | 2366 | int use_mmio_flip; |
5978118c | 2367 | bool mmio_debug; |
d330a953 JN |
2368 | }; |
2369 | extern struct i915_params i915 __read_mostly; | |
2370 | ||
1da177e4 | 2371 | /* i915_dma.c */ |
22eae947 | 2372 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 2373 | extern int i915_driver_unload(struct drm_device *); |
2885f6ac | 2374 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file); |
84b1fd10 | 2375 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac | 2376 | extern void i915_driver_preclose(struct drm_device *dev, |
2885f6ac | 2377 | struct drm_file *file); |
673a394b | 2378 | extern void i915_driver_postclose(struct drm_device *dev, |
2885f6ac | 2379 | struct drm_file *file); |
84b1fd10 | 2380 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
c43b5634 | 2381 | #ifdef CONFIG_COMPAT |
0d6aa60b DA |
2382 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
2383 | unsigned long arg); | |
c43b5634 | 2384 | #endif |
8e96d9c4 | 2385 | extern int intel_gpu_reset(struct drm_device *dev); |
d4b8bb2a | 2386 | extern int i915_reset(struct drm_device *dev); |
7648fa99 JB |
2387 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
2388 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
2389 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
2390 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
650ad970 | 2391 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); |
1d0d343a | 2392 | void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); |
7648fa99 | 2393 | |
1da177e4 | 2394 | /* i915_irq.c */ |
10cd45b6 | 2395 | void i915_queue_hangcheck(struct drm_device *dev); |
58174462 MK |
2396 | __printf(3, 4) |
2397 | void i915_handle_error(struct drm_device *dev, bool wedged, | |
2398 | const char *fmt, ...); | |
1da177e4 | 2399 | |
b963291c DV |
2400 | extern void intel_irq_init(struct drm_i915_private *dev_priv); |
2401 | extern void intel_hpd_init(struct drm_i915_private *dev_priv); | |
2aeb7d3a DV |
2402 | int intel_irq_install(struct drm_i915_private *dev_priv); |
2403 | void intel_irq_uninstall(struct drm_i915_private *dev_priv); | |
907b28c5 CW |
2404 | |
2405 | extern void intel_uncore_sanitize(struct drm_device *dev); | |
10018603 ID |
2406 | extern void intel_uncore_early_sanitize(struct drm_device *dev, |
2407 | bool restore_forcewake); | |
907b28c5 | 2408 | extern void intel_uncore_init(struct drm_device *dev); |
907b28c5 | 2409 | extern void intel_uncore_check_errors(struct drm_device *dev); |
aec347ab | 2410 | extern void intel_uncore_fini(struct drm_device *dev); |
156c7ca0 | 2411 | extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore); |
b1f14ad0 | 2412 | |
7c463586 | 2413 | void |
50227e1c | 2414 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2415 | u32 status_mask); |
7c463586 KP |
2416 | |
2417 | void | |
50227e1c | 2418 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2419 | u32 status_mask); |
7c463586 | 2420 | |
f8b79e58 ID |
2421 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); |
2422 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); | |
47339cd9 DV |
2423 | void |
2424 | ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask); | |
2425 | void | |
2426 | ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask); | |
2427 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, | |
2428 | uint32_t interrupt_mask, | |
2429 | uint32_t enabled_irq_mask); | |
2430 | #define ibx_enable_display_interrupt(dev_priv, bits) \ | |
2431 | ibx_display_interrupt_update((dev_priv), (bits), (bits)) | |
2432 | #define ibx_disable_display_interrupt(dev_priv, bits) \ | |
2433 | ibx_display_interrupt_update((dev_priv), (bits), 0) | |
f8b79e58 | 2434 | |
673a394b | 2435 | /* i915_gem.c */ |
673a394b EA |
2436 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
2437 | struct drm_file *file_priv); | |
2438 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
2439 | struct drm_file *file_priv); | |
2440 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
2441 | struct drm_file *file_priv); | |
2442 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
2443 | struct drm_file *file_priv); | |
de151cf6 JB |
2444 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
2445 | struct drm_file *file_priv); | |
673a394b EA |
2446 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
2447 | struct drm_file *file_priv); | |
2448 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
2449 | struct drm_file *file_priv); | |
ba8b7ccb OM |
2450 | void i915_gem_execbuffer_move_to_active(struct list_head *vmas, |
2451 | struct intel_engine_cs *ring); | |
2452 | void i915_gem_execbuffer_retire_commands(struct drm_device *dev, | |
2453 | struct drm_file *file, | |
2454 | struct intel_engine_cs *ring, | |
2455 | struct drm_i915_gem_object *obj); | |
a83014d3 OM |
2456 | int i915_gem_ringbuffer_submission(struct drm_device *dev, |
2457 | struct drm_file *file, | |
2458 | struct intel_engine_cs *ring, | |
2459 | struct intel_context *ctx, | |
2460 | struct drm_i915_gem_execbuffer2 *args, | |
2461 | struct list_head *vmas, | |
2462 | struct drm_i915_gem_object *batch_obj, | |
2463 | u64 exec_start, u32 flags); | |
673a394b EA |
2464 | int i915_gem_execbuffer(struct drm_device *dev, void *data, |
2465 | struct drm_file *file_priv); | |
76446cac JB |
2466 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
2467 | struct drm_file *file_priv); | |
673a394b EA |
2468 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
2469 | struct drm_file *file_priv); | |
199adf40 BW |
2470 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
2471 | struct drm_file *file); | |
2472 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, | |
2473 | struct drm_file *file); | |
673a394b EA |
2474 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
2475 | struct drm_file *file_priv); | |
3ef94daa CW |
2476 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
2477 | struct drm_file *file_priv); | |
673a394b EA |
2478 | int i915_gem_set_tiling(struct drm_device *dev, void *data, |
2479 | struct drm_file *file_priv); | |
2480 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
2481 | struct drm_file *file_priv); | |
5cc9ed4b CW |
2482 | int i915_gem_init_userptr(struct drm_device *dev); |
2483 | int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, | |
2484 | struct drm_file *file); | |
5a125c3c EA |
2485 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
2486 | struct drm_file *file_priv); | |
23ba4fd0 BW |
2487 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
2488 | struct drm_file *file_priv); | |
673a394b | 2489 | void i915_gem_load(struct drm_device *dev); |
21ab4e74 CW |
2490 | unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, |
2491 | long target, | |
2492 | unsigned flags); | |
2493 | #define I915_SHRINK_PURGEABLE 0x1 | |
2494 | #define I915_SHRINK_UNBOUND 0x2 | |
2495 | #define I915_SHRINK_BOUND 0x4 | |
42dcedd4 CW |
2496 | void *i915_gem_object_alloc(struct drm_device *dev); |
2497 | void i915_gem_object_free(struct drm_i915_gem_object *obj); | |
37e680a1 CW |
2498 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
2499 | const struct drm_i915_gem_object_ops *ops); | |
05394f39 CW |
2500 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
2501 | size_t size); | |
7e0d96bc BW |
2502 | void i915_init_vm(struct drm_i915_private *dev_priv, |
2503 | struct i915_address_space *vm); | |
673a394b | 2504 | void i915_gem_free_object(struct drm_gem_object *obj); |
2f633156 | 2505 | void i915_gem_vma_destroy(struct i915_vma *vma); |
42dcedd4 | 2506 | |
1ec9e26d DV |
2507 | #define PIN_MAPPABLE 0x1 |
2508 | #define PIN_NONBLOCK 0x2 | |
bf3d149b | 2509 | #define PIN_GLOBAL 0x4 |
d23db88c CW |
2510 | #define PIN_OFFSET_BIAS 0x8 |
2511 | #define PIN_OFFSET_MASK (~4095) | |
2021746e | 2512 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, |
c37e2204 | 2513 | struct i915_address_space *vm, |
2021746e | 2514 | uint32_t alignment, |
d23db88c | 2515 | uint64_t flags); |
07fe0b12 | 2516 | int __must_check i915_vma_unbind(struct i915_vma *vma); |
dd624afd | 2517 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); |
48018a57 | 2518 | void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); |
05394f39 | 2519 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
f787a5f5 | 2520 | |
4c914c0c BV |
2521 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, |
2522 | int *needs_clflush); | |
2523 | ||
37e680a1 | 2524 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
9da3da66 CW |
2525 | static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) |
2526 | { | |
67d5a50c ID |
2527 | struct sg_page_iter sg_iter; |
2528 | ||
2529 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n) | |
2db76d7c | 2530 | return sg_page_iter_page(&sg_iter); |
67d5a50c ID |
2531 | |
2532 | return NULL; | |
9da3da66 | 2533 | } |
a5570178 CW |
2534 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
2535 | { | |
2536 | BUG_ON(obj->pages == NULL); | |
2537 | obj->pages_pin_count++; | |
2538 | } | |
2539 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) | |
2540 | { | |
2541 | BUG_ON(obj->pages_pin_count == 0); | |
2542 | obj->pages_pin_count--; | |
2543 | } | |
2544 | ||
54cf91dc | 2545 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
2911a35b | 2546 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
a4872ba6 | 2547 | struct intel_engine_cs *to); |
e2d05a8b | 2548 | void i915_vma_move_to_active(struct i915_vma *vma, |
a4872ba6 | 2549 | struct intel_engine_cs *ring); |
ff72145b DA |
2550 | int i915_gem_dumb_create(struct drm_file *file_priv, |
2551 | struct drm_device *dev, | |
2552 | struct drm_mode_create_dumb *args); | |
355a7018 TH |
2553 | int i915_gem_dumb_map_offset(struct drm_file *file_priv, |
2554 | struct drm_device *dev, uint32_t handle, | |
2555 | uint64_t *offset); | |
f787a5f5 CW |
2556 | /** |
2557 | * Returns true if seq1 is later than seq2. | |
2558 | */ | |
2559 | static inline bool | |
2560 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
2561 | { | |
2562 | return (int32_t)(seq1 - seq2) >= 0; | |
2563 | } | |
2564 | ||
fca26bb4 MK |
2565 | int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); |
2566 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); | |
06d98131 | 2567 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); |
d9e86c0e | 2568 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
2021746e | 2569 | |
d8ffa60b DV |
2570 | bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj); |
2571 | void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj); | |
1690e1eb | 2572 | |
8d9fc7fd | 2573 | struct drm_i915_gem_request * |
a4872ba6 | 2574 | i915_gem_find_active_request(struct intel_engine_cs *ring); |
8d9fc7fd | 2575 | |
b29c19b6 | 2576 | bool i915_gem_retire_requests(struct drm_device *dev); |
a4872ba6 | 2577 | void i915_gem_retire_requests_ring(struct intel_engine_cs *ring); |
33196ded | 2578 | int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, |
d6b2c790 | 2579 | bool interruptible); |
b6660d59 | 2580 | int __must_check i915_gem_check_olr(struct drm_i915_gem_request *req); |
84c33a64 | 2581 | |
1f83fee0 DV |
2582 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
2583 | { | |
2584 | return unlikely(atomic_read(&error->reset_counter) | |
2ac0f450 | 2585 | & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); |
1f83fee0 DV |
2586 | } |
2587 | ||
2588 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) | |
2589 | { | |
2ac0f450 MK |
2590 | return atomic_read(&error->reset_counter) & I915_WEDGED; |
2591 | } | |
2592 | ||
2593 | static inline u32 i915_reset_count(struct i915_gpu_error *error) | |
2594 | { | |
2595 | return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2; | |
1f83fee0 | 2596 | } |
a71d8d94 | 2597 | |
88b4aa87 MK |
2598 | static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv) |
2599 | { | |
2600 | return dev_priv->gpu_error.stop_rings == 0 || | |
2601 | dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN; | |
2602 | } | |
2603 | ||
2604 | static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv) | |
2605 | { | |
2606 | return dev_priv->gpu_error.stop_rings == 0 || | |
2607 | dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN; | |
2608 | } | |
2609 | ||
069efc1d | 2610 | void i915_gem_reset(struct drm_device *dev); |
000433b6 | 2611 | bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); |
a8198eea | 2612 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); |
1070a42b | 2613 | int __must_check i915_gem_init(struct drm_device *dev); |
a83014d3 | 2614 | int i915_gem_init_rings(struct drm_device *dev); |
f691e2f4 | 2615 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
a4872ba6 | 2616 | int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice); |
f691e2f4 | 2617 | void i915_gem_init_swizzling(struct drm_device *dev); |
79e53945 | 2618 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
b2da9fe5 | 2619 | int __must_check i915_gpu_idle(struct drm_device *dev); |
45c5f202 | 2620 | int __must_check i915_gem_suspend(struct drm_device *dev); |
a4872ba6 | 2621 | int __i915_add_request(struct intel_engine_cs *ring, |
0025c077 | 2622 | struct drm_file *file, |
7d736f4f | 2623 | struct drm_i915_gem_object *batch_obj, |
0025c077 MK |
2624 | u32 *seqno); |
2625 | #define i915_add_request(ring, seqno) \ | |
854c94a7 | 2626 | __i915_add_request(ring, NULL, NULL, seqno) |
16e9a21f ACO |
2627 | int __i915_wait_seqno(struct intel_engine_cs *ring, u32 seqno, |
2628 | unsigned reset_counter, | |
2629 | bool interruptible, | |
2630 | s64 *timeout, | |
2631 | struct drm_i915_file_private *file_priv); | |
a4b3a571 | 2632 | int __must_check i915_wait_request(struct drm_i915_gem_request *req); |
de151cf6 | 2633 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
2021746e CW |
2634 | int __must_check |
2635 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, | |
2636 | bool write); | |
2637 | int __must_check | |
dabdfe02 CW |
2638 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
2639 | int __must_check | |
2da3b9b9 CW |
2640 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
2641 | u32 alignment, | |
a4872ba6 | 2642 | struct intel_engine_cs *pipelined); |
cc98b413 | 2643 | void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj); |
00731155 | 2644 | int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, |
6eeefaf3 | 2645 | int align); |
b29c19b6 | 2646 | int i915_gem_open(struct drm_device *dev, struct drm_file *file); |
05394f39 | 2647 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 2648 | |
0fa87796 ID |
2649 | uint32_t |
2650 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); | |
467cffba | 2651 | uint32_t |
d865110c ID |
2652 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
2653 | int tiling_mode, bool fenced); | |
467cffba | 2654 | |
e4ffd173 CW |
2655 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
2656 | enum i915_cache_level cache_level); | |
2657 | ||
1286ff73 DV |
2658 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
2659 | struct dma_buf *dma_buf); | |
2660 | ||
2661 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, | |
2662 | struct drm_gem_object *gem_obj, int flags); | |
2663 | ||
19b2dbde CW |
2664 | void i915_gem_restore_fences(struct drm_device *dev); |
2665 | ||
a70a3148 BW |
2666 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, |
2667 | struct i915_address_space *vm); | |
2668 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); | |
2669 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
2670 | struct i915_address_space *vm); | |
2671 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
2672 | struct i915_address_space *vm); | |
2673 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, | |
2674 | struct i915_address_space *vm); | |
accfef2e BW |
2675 | struct i915_vma * |
2676 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
2677 | struct i915_address_space *vm); | |
5c2abbea BW |
2678 | |
2679 | struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj); | |
d7f46fc4 BW |
2680 | static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) { |
2681 | struct i915_vma *vma; | |
2682 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
2683 | if (vma->pin_count > 0) | |
2684 | return true; | |
2685 | return false; | |
2686 | } | |
5c2abbea | 2687 | |
a70a3148 | 2688 | /* Some GGTT VM helpers */ |
5dc383b0 | 2689 | #define i915_obj_to_ggtt(obj) \ |
a70a3148 BW |
2690 | (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) |
2691 | static inline bool i915_is_ggtt(struct i915_address_space *vm) | |
2692 | { | |
2693 | struct i915_address_space *ggtt = | |
2694 | &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base; | |
2695 | return vm == ggtt; | |
2696 | } | |
2697 | ||
841cd773 DV |
2698 | static inline struct i915_hw_ppgtt * |
2699 | i915_vm_to_ppgtt(struct i915_address_space *vm) | |
2700 | { | |
2701 | WARN_ON(i915_is_ggtt(vm)); | |
2702 | ||
2703 | return container_of(vm, struct i915_hw_ppgtt, base); | |
2704 | } | |
2705 | ||
2706 | ||
a70a3148 BW |
2707 | static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) |
2708 | { | |
5dc383b0 | 2709 | return i915_gem_obj_bound(obj, i915_obj_to_ggtt(obj)); |
a70a3148 BW |
2710 | } |
2711 | ||
2712 | static inline unsigned long | |
2713 | i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj) | |
2714 | { | |
5dc383b0 | 2715 | return i915_gem_obj_offset(obj, i915_obj_to_ggtt(obj)); |
a70a3148 BW |
2716 | } |
2717 | ||
2718 | static inline unsigned long | |
2719 | i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) | |
2720 | { | |
5dc383b0 | 2721 | return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj)); |
a70a3148 | 2722 | } |
c37e2204 BW |
2723 | |
2724 | static inline int __must_check | |
2725 | i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, | |
2726 | uint32_t alignment, | |
1ec9e26d | 2727 | unsigned flags) |
c37e2204 | 2728 | { |
5dc383b0 DV |
2729 | return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj), |
2730 | alignment, flags | PIN_GLOBAL); | |
c37e2204 | 2731 | } |
a70a3148 | 2732 | |
b287110e DV |
2733 | static inline int |
2734 | i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) | |
2735 | { | |
2736 | return i915_vma_unbind(i915_gem_obj_to_ggtt(obj)); | |
2737 | } | |
2738 | ||
2739 | void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj); | |
2740 | ||
254f965c | 2741 | /* i915_gem_context.c */ |
8245be31 | 2742 | int __must_check i915_gem_context_init(struct drm_device *dev); |
254f965c | 2743 | void i915_gem_context_fini(struct drm_device *dev); |
acce9ffa | 2744 | void i915_gem_context_reset(struct drm_device *dev); |
e422b888 | 2745 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); |
2fa48d8d | 2746 | int i915_gem_context_enable(struct drm_i915_private *dev_priv); |
254f965c | 2747 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
a4872ba6 | 2748 | int i915_switch_context(struct intel_engine_cs *ring, |
273497e5 OM |
2749 | struct intel_context *to); |
2750 | struct intel_context * | |
41bde553 | 2751 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); |
dce3271b | 2752 | void i915_gem_context_free(struct kref *ctx_ref); |
8c857917 OM |
2753 | struct drm_i915_gem_object * |
2754 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size); | |
273497e5 | 2755 | static inline void i915_gem_context_reference(struct intel_context *ctx) |
dce3271b | 2756 | { |
691e6415 | 2757 | kref_get(&ctx->ref); |
dce3271b MK |
2758 | } |
2759 | ||
273497e5 | 2760 | static inline void i915_gem_context_unreference(struct intel_context *ctx) |
dce3271b | 2761 | { |
691e6415 | 2762 | kref_put(&ctx->ref, i915_gem_context_free); |
dce3271b MK |
2763 | } |
2764 | ||
273497e5 | 2765 | static inline bool i915_gem_context_is_default(const struct intel_context *c) |
3fac8978 | 2766 | { |
821d66dd | 2767 | return c->user_handle == DEFAULT_CONTEXT_HANDLE; |
3fac8978 MK |
2768 | } |
2769 | ||
84624813 BW |
2770 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
2771 | struct drm_file *file); | |
2772 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
2773 | struct drm_file *file); | |
1286ff73 | 2774 | |
679845ed BW |
2775 | /* i915_gem_evict.c */ |
2776 | int __must_check i915_gem_evict_something(struct drm_device *dev, | |
2777 | struct i915_address_space *vm, | |
2778 | int min_size, | |
2779 | unsigned alignment, | |
2780 | unsigned cache_level, | |
d23db88c CW |
2781 | unsigned long start, |
2782 | unsigned long end, | |
1ec9e26d | 2783 | unsigned flags); |
679845ed BW |
2784 | int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); |
2785 | int i915_gem_evict_everything(struct drm_device *dev); | |
1d2a314c | 2786 | |
0260c420 | 2787 | /* belongs in i915_gem_gtt.h */ |
d09105c6 | 2788 | static inline void i915_gem_chipset_flush(struct drm_device *dev) |
e76e9aeb BW |
2789 | { |
2790 | if (INTEL_INFO(dev)->gen < 6) | |
2791 | intel_gtt_chipset_flush(); | |
2792 | } | |
246cbfb5 | 2793 | |
9797fbfb CW |
2794 | /* i915_gem_stolen.c */ |
2795 | int i915_gem_init_stolen(struct drm_device *dev); | |
5e59f717 | 2796 | int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp); |
11be49eb | 2797 | void i915_gem_stolen_cleanup_compression(struct drm_device *dev); |
9797fbfb | 2798 | void i915_gem_cleanup_stolen(struct drm_device *dev); |
0104fdbb CW |
2799 | struct drm_i915_gem_object * |
2800 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); | |
866d12b4 CW |
2801 | struct drm_i915_gem_object * |
2802 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, | |
2803 | u32 stolen_offset, | |
2804 | u32 gtt_offset, | |
2805 | u32 size); | |
9797fbfb | 2806 | |
673a394b | 2807 | /* i915_gem_tiling.c */ |
2c1792a1 | 2808 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
e9b73c67 | 2809 | { |
50227e1c | 2810 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e9b73c67 CW |
2811 | |
2812 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
2813 | obj->tiling_mode != I915_TILING_NONE; | |
2814 | } | |
2815 | ||
673a394b | 2816 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
05394f39 CW |
2817 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
2818 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
673a394b EA |
2819 | |
2820 | /* i915_gem_debug.c */ | |
23bc5982 CW |
2821 | #if WATCH_LISTS |
2822 | int i915_verify_lists(struct drm_device *dev); | |
673a394b | 2823 | #else |
23bc5982 | 2824 | #define i915_verify_lists(dev) 0 |
673a394b | 2825 | #endif |
1da177e4 | 2826 | |
2017263e | 2827 | /* i915_debugfs.c */ |
27c202ad BG |
2828 | int i915_debugfs_init(struct drm_minor *minor); |
2829 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
f8c168fa | 2830 | #ifdef CONFIG_DEBUG_FS |
07144428 DL |
2831 | void intel_display_crc_init(struct drm_device *dev); |
2832 | #else | |
f8c168fa | 2833 | static inline void intel_display_crc_init(struct drm_device *dev) {} |
07144428 | 2834 | #endif |
84734a04 MK |
2835 | |
2836 | /* i915_gpu_error.c */ | |
edc3d884 MK |
2837 | __printf(2, 3) |
2838 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); | |
fc16b48b MK |
2839 | int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, |
2840 | const struct i915_error_state_file_priv *error); | |
4dc955f7 | 2841 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, |
0a4cd7c8 | 2842 | struct drm_i915_private *i915, |
4dc955f7 MK |
2843 | size_t count, loff_t pos); |
2844 | static inline void i915_error_state_buf_release( | |
2845 | struct drm_i915_error_state_buf *eb) | |
2846 | { | |
2847 | kfree(eb->buf); | |
2848 | } | |
58174462 MK |
2849 | void i915_capture_error_state(struct drm_device *dev, bool wedge, |
2850 | const char *error_msg); | |
84734a04 MK |
2851 | void i915_error_state_get(struct drm_device *dev, |
2852 | struct i915_error_state_file_priv *error_priv); | |
2853 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv); | |
2854 | void i915_destroy_error_state(struct drm_device *dev); | |
2855 | ||
2856 | void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); | |
0a4cd7c8 | 2857 | const char *i915_cache_level_str(struct drm_i915_private *i915, int type); |
2017263e | 2858 | |
351e3db2 | 2859 | /* i915_cmd_parser.c */ |
d728c8ef | 2860 | int i915_cmd_parser_get_version(void); |
a4872ba6 OM |
2861 | int i915_cmd_parser_init_ring(struct intel_engine_cs *ring); |
2862 | void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring); | |
2863 | bool i915_needs_cmd_parser(struct intel_engine_cs *ring); | |
2864 | int i915_parse_cmds(struct intel_engine_cs *ring, | |
351e3db2 BV |
2865 | struct drm_i915_gem_object *batch_obj, |
2866 | u32 batch_start_offset, | |
2867 | bool is_master); | |
2868 | ||
317c35d1 JB |
2869 | /* i915_suspend.c */ |
2870 | extern int i915_save_state(struct drm_device *dev); | |
2871 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 | 2872 | |
d8157a36 DV |
2873 | /* i915_ums.c */ |
2874 | void i915_save_display_reg(struct drm_device *dev); | |
2875 | void i915_restore_display_reg(struct drm_device *dev); | |
317c35d1 | 2876 | |
0136db58 BW |
2877 | /* i915_sysfs.c */ |
2878 | void i915_setup_sysfs(struct drm_device *dev_priv); | |
2879 | void i915_teardown_sysfs(struct drm_device *dev_priv); | |
2880 | ||
f899fc64 CW |
2881 | /* intel_i2c.c */ |
2882 | extern int intel_setup_gmbus(struct drm_device *dev); | |
2883 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
8f375e10 | 2884 | static inline bool intel_gmbus_is_port_valid(unsigned port) |
3bd7d909 | 2885 | { |
2ed06c93 | 2886 | return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); |
3bd7d909 DK |
2887 | } |
2888 | ||
2889 | extern struct i2c_adapter *intel_gmbus_get_adapter( | |
2890 | struct drm_i915_private *dev_priv, unsigned port); | |
e957d772 CW |
2891 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
2892 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
8f375e10 | 2893 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
b8232e90 CW |
2894 | { |
2895 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
2896 | } | |
f899fc64 CW |
2897 | extern void intel_i2c_reset(struct drm_device *dev); |
2898 | ||
3b617967 | 2899 | /* intel_opregion.c */ |
44834a67 | 2900 | #ifdef CONFIG_ACPI |
27d50c82 | 2901 | extern int intel_opregion_setup(struct drm_device *dev); |
44834a67 CW |
2902 | extern void intel_opregion_init(struct drm_device *dev); |
2903 | extern void intel_opregion_fini(struct drm_device *dev); | |
3b617967 | 2904 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
9c4b0a68 JN |
2905 | extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, |
2906 | bool enable); | |
ecbc5cf3 JN |
2907 | extern int intel_opregion_notify_adapter(struct drm_device *dev, |
2908 | pci_power_t state); | |
65e082c9 | 2909 | #else |
27d50c82 | 2910 | static inline int intel_opregion_setup(struct drm_device *dev) { return 0; } |
44834a67 CW |
2911 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
2912 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } | |
3b617967 | 2913 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
9c4b0a68 JN |
2914 | static inline int |
2915 | intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) | |
2916 | { | |
2917 | return 0; | |
2918 | } | |
ecbc5cf3 JN |
2919 | static inline int |
2920 | intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state) | |
2921 | { | |
2922 | return 0; | |
2923 | } | |
65e082c9 | 2924 | #endif |
8ee1c3db | 2925 | |
723bfd70 JB |
2926 | /* intel_acpi.c */ |
2927 | #ifdef CONFIG_ACPI | |
2928 | extern void intel_register_dsm_handler(void); | |
2929 | extern void intel_unregister_dsm_handler(void); | |
2930 | #else | |
2931 | static inline void intel_register_dsm_handler(void) { return; } | |
2932 | static inline void intel_unregister_dsm_handler(void) { return; } | |
2933 | #endif /* CONFIG_ACPI */ | |
2934 | ||
79e53945 | 2935 | /* modesetting */ |
f817586c | 2936 | extern void intel_modeset_init_hw(struct drm_device *dev); |
79e53945 | 2937 | extern void intel_modeset_init(struct drm_device *dev); |
2c7111db | 2938 | extern void intel_modeset_gem_init(struct drm_device *dev); |
79e53945 | 2939 | extern void intel_modeset_cleanup(struct drm_device *dev); |
4932e2c3 | 2940 | extern void intel_connector_unregister(struct intel_connector *); |
28d52043 | 2941 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
45e2b5f6 DV |
2942 | extern void intel_modeset_setup_hw_state(struct drm_device *dev, |
2943 | bool force_restore); | |
44cec740 | 2944 | extern void i915_redisable_vga(struct drm_device *dev); |
04098753 | 2945 | extern void i915_redisable_vga_power_on(struct drm_device *dev); |
ee5382ae | 2946 | extern bool intel_fbc_enabled(struct drm_device *dev); |
1d73c2a8 | 2947 | extern void bdw_fbc_sw_flush(struct drm_device *dev, u32 value); |
43a9539f | 2948 | extern void intel_disable_fbc(struct drm_device *dev); |
7648fa99 | 2949 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
dde86e2d | 2950 | extern void intel_init_pch_refclk(struct drm_device *dev); |
3b8d8d91 | 2951 | extern void gen6_set_rps(struct drm_device *dev, u8 val); |
0a073b84 | 2952 | extern void valleyview_set_rps(struct drm_device *dev, u8 val); |
5209b1f4 ID |
2953 | extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, |
2954 | bool enable); | |
0206e353 AJ |
2955 | extern void intel_detect_pch(struct drm_device *dev); |
2956 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); | |
0136db58 | 2957 | extern int intel_enable_rc6(const struct drm_device *dev); |
3bad0781 | 2958 | |
2911a35b | 2959 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
c0c7babc BW |
2960 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
2961 | struct drm_file *file); | |
b6359918 MK |
2962 | int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, |
2963 | struct drm_file *file); | |
575155a9 | 2964 | |
84c33a64 SG |
2965 | void intel_notify_mmio_flip(struct intel_engine_cs *ring); |
2966 | ||
6ef3d427 CW |
2967 | /* overlay */ |
2968 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); | |
edc3d884 MK |
2969 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
2970 | struct intel_overlay_error_state *error); | |
c4a1d9e4 CW |
2971 | |
2972 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); | |
edc3d884 | 2973 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
c4a1d9e4 CW |
2974 | struct drm_device *dev, |
2975 | struct intel_display_error_state *error); | |
6ef3d427 | 2976 | |
b7287d80 BW |
2977 | /* On SNB platform, before reading ring registers forcewake bit |
2978 | * must be set to prevent GT core from power down and stale values being | |
2979 | * returned. | |
2980 | */ | |
c8d9a590 D |
2981 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine); |
2982 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine); | |
e998c40f | 2983 | void assert_force_wake_inactive(struct drm_i915_private *dev_priv); |
b7287d80 | 2984 | |
151a49d0 TR |
2985 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); |
2986 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val); | |
59de0813 JN |
2987 | |
2988 | /* intel_sideband.c */ | |
64936258 JN |
2989 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr); |
2990 | void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); | |
2991 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); | |
e9f882a3 JN |
2992 | u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); |
2993 | void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
2994 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); | |
2995 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
2996 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); | |
2997 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
f3419158 JB |
2998 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); |
2999 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
e9f882a3 JN |
3000 | u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg); |
3001 | void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
5e69f97f CML |
3002 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); |
3003 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); | |
59de0813 JN |
3004 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
3005 | enum intel_sbi_destination destination); | |
3006 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, | |
3007 | enum intel_sbi_destination destination); | |
e9fe51c6 SK |
3008 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); |
3009 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
0a073b84 | 3010 | |
2ec3815f VS |
3011 | int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val); |
3012 | int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val); | |
42c0526c | 3013 | |
c8d9a590 D |
3014 | #define FORCEWAKE_RENDER (1 << 0) |
3015 | #define FORCEWAKE_MEDIA (1 << 1) | |
38cff0b1 ZW |
3016 | #define FORCEWAKE_BLITTER (1 << 2) |
3017 | #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA | \ | |
3018 | FORCEWAKE_BLITTER) | |
c8d9a590 D |
3019 | |
3020 | ||
0b274481 BW |
3021 | #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) |
3022 | #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) | |
3023 | ||
3024 | #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) | |
3025 | #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) | |
3026 | #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) | |
3027 | #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) | |
3028 | ||
3029 | #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) | |
3030 | #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) | |
3031 | #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) | |
3032 | #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) | |
3033 | ||
698b3135 CW |
3034 | /* Be very careful with read/write 64-bit values. On 32-bit machines, they |
3035 | * will be implemented using 2 32-bit writes in an arbitrary order with | |
3036 | * an arbitrary delay between them. This can cause the hardware to | |
3037 | * act upon the intermediate value, possibly leading to corruption and | |
3038 | * machine death. You have been warned. | |
3039 | */ | |
0b274481 BW |
3040 | #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) |
3041 | #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) | |
cae5852d | 3042 | |
50877445 CW |
3043 | #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ |
3044 | u32 upper = I915_READ(upper_reg); \ | |
3045 | u32 lower = I915_READ(lower_reg); \ | |
3046 | u32 tmp = I915_READ(upper_reg); \ | |
3047 | if (upper != tmp) { \ | |
3048 | upper = tmp; \ | |
3049 | lower = I915_READ(lower_reg); \ | |
3050 | WARN_ON(I915_READ(upper_reg) != upper); \ | |
3051 | } \ | |
3052 | (u64)upper << 32 | lower; }) | |
3053 | ||
cae5852d ZN |
3054 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
3055 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
3056 | ||
55bc60db VS |
3057 | /* "Broadcast RGB" property */ |
3058 | #define INTEL_BROADCAST_RGB_AUTO 0 | |
3059 | #define INTEL_BROADCAST_RGB_FULL 1 | |
3060 | #define INTEL_BROADCAST_RGB_LIMITED 2 | |
ba4f01a3 | 3061 | |
766aa1c4 VS |
3062 | static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) |
3063 | { | |
92e23b99 | 3064 | if (IS_VALLEYVIEW(dev)) |
766aa1c4 | 3065 | return VLV_VGACNTRL; |
92e23b99 SJ |
3066 | else if (INTEL_INFO(dev)->gen >= 5) |
3067 | return CPU_VGACNTRL; | |
766aa1c4 VS |
3068 | else |
3069 | return VGACNTRL; | |
3070 | } | |
3071 | ||
2bb4629a VS |
3072 | static inline void __user *to_user_ptr(u64 address) |
3073 | { | |
3074 | return (void __user *)(uintptr_t)address; | |
3075 | } | |
3076 | ||
df97729f ID |
3077 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
3078 | { | |
3079 | unsigned long j = msecs_to_jiffies(m); | |
3080 | ||
3081 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3082 | } | |
3083 | ||
3084 | static inline unsigned long | |
3085 | timespec_to_jiffies_timeout(const struct timespec *value) | |
3086 | { | |
3087 | unsigned long j = timespec_to_jiffies(value); | |
3088 | ||
3089 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3090 | } | |
3091 | ||
dce56b3c PZ |
3092 | /* |
3093 | * If you need to wait X milliseconds between events A and B, but event B | |
3094 | * doesn't happen exactly after event A, you record the timestamp (jiffies) of | |
3095 | * when event A happened, then just before event B you call this function and | |
3096 | * pass the timestamp as the first argument, and X as the second argument. | |
3097 | */ | |
3098 | static inline void | |
3099 | wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) | |
3100 | { | |
ec5e0cfb | 3101 | unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; |
dce56b3c PZ |
3102 | |
3103 | /* | |
3104 | * Don't re-read the value of "jiffies" every time since it may change | |
3105 | * behind our back and break the math. | |
3106 | */ | |
3107 | tmp_jiffies = jiffies; | |
3108 | target_jiffies = timestamp_jiffies + | |
3109 | msecs_to_jiffies_timeout(to_wait_ms); | |
3110 | ||
3111 | if (time_after(target_jiffies, tmp_jiffies)) { | |
ec5e0cfb ID |
3112 | remaining_jiffies = target_jiffies - tmp_jiffies; |
3113 | while (remaining_jiffies) | |
3114 | remaining_jiffies = | |
3115 | schedule_timeout_uninterruptible(remaining_jiffies); | |
dce56b3c PZ |
3116 | } |
3117 | } | |
3118 | ||
1da177e4 | 3119 | #endif |