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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
e9b73c67 | 33 | #include <uapi/drm/i915_drm.h> |
93b81f51 | 34 | #include <uapi/drm/drm_fourcc.h> |
e9b73c67 | 35 | |
585fb111 | 36 | #include "i915_reg.h" |
79e53945 | 37 | #include "intel_bios.h" |
8187a2b7 | 38 | #include "intel_ringbuffer.h" |
b20385f1 | 39 | #include "intel_lrc.h" |
0260c420 | 40 | #include "i915_gem_gtt.h" |
564ddb2f | 41 | #include "i915_gem_render_state.h" |
0839ccb8 | 42 | #include <linux/io-mapping.h> |
f899fc64 | 43 | #include <linux/i2c.h> |
c167a6fc | 44 | #include <linux/i2c-algo-bit.h> |
0ade6386 | 45 | #include <drm/intel-gtt.h> |
ba8286fa | 46 | #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ |
d9fc9413 | 47 | #include <drm/drm_gem.h> |
aaa6fd2a | 48 | #include <linux/backlight.h> |
5cc9ed4b | 49 | #include <linux/hashtable.h> |
2911a35b | 50 | #include <linux/intel-iommu.h> |
742cbee8 | 51 | #include <linux/kref.h> |
9ee32fea | 52 | #include <linux/pm_qos.h> |
585fb111 | 53 | |
1da177e4 LT |
54 | /* General customization: |
55 | */ | |
56 | ||
1da177e4 LT |
57 | #define DRIVER_NAME "i915" |
58 | #define DRIVER_DESC "Intel Graphics" | |
214a2b7f | 59 | #define DRIVER_DATE "20150508" |
1da177e4 | 60 | |
c883ef1b | 61 | #undef WARN_ON |
5f77eeb0 DV |
62 | /* Many gcc seem to no see through this and fall over :( */ |
63 | #if 0 | |
64 | #define WARN_ON(x) ({ \ | |
65 | bool __i915_warn_cond = (x); \ | |
66 | if (__builtin_constant_p(__i915_warn_cond)) \ | |
67 | BUILD_BUG_ON(__i915_warn_cond); \ | |
68 | WARN(__i915_warn_cond, "WARN_ON(" #x ")"); }) | |
69 | #else | |
70 | #define WARN_ON(x) WARN((x), "WARN_ON(" #x ")") | |
71 | #endif | |
72 | ||
cd9bfacb JN |
73 | #undef WARN_ON_ONCE |
74 | #define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(" #x ")") | |
75 | ||
5f77eeb0 DV |
76 | #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \ |
77 | (long) (x), __func__); | |
c883ef1b | 78 | |
e2c719b7 RC |
79 | /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and |
80 | * WARN_ON()) for hw state sanity checks to check for unexpected conditions | |
81 | * which may not necessarily be a user visible problem. This will either | |
82 | * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to | |
83 | * enable distros and users to tailor their preferred amount of i915 abrt | |
84 | * spam. | |
85 | */ | |
86 | #define I915_STATE_WARN(condition, format...) ({ \ | |
87 | int __ret_warn_on = !!(condition); \ | |
88 | if (unlikely(__ret_warn_on)) { \ | |
89 | if (i915.verbose_state_checks) \ | |
2f3408c7 | 90 | WARN(1, format); \ |
e2c719b7 RC |
91 | else \ |
92 | DRM_ERROR(format); \ | |
93 | } \ | |
94 | unlikely(__ret_warn_on); \ | |
95 | }) | |
96 | ||
97 | #define I915_STATE_WARN_ON(condition) ({ \ | |
98 | int __ret_warn_on = !!(condition); \ | |
99 | if (unlikely(__ret_warn_on)) { \ | |
100 | if (i915.verbose_state_checks) \ | |
2f3408c7 | 101 | WARN(1, "WARN_ON(" #condition ")\n"); \ |
e2c719b7 RC |
102 | else \ |
103 | DRM_ERROR("WARN_ON(" #condition ")\n"); \ | |
104 | } \ | |
105 | unlikely(__ret_warn_on); \ | |
106 | }) | |
c883ef1b | 107 | |
317c35d1 | 108 | enum pipe { |
752aa88a | 109 | INVALID_PIPE = -1, |
317c35d1 JB |
110 | PIPE_A = 0, |
111 | PIPE_B, | |
9db4a9c7 | 112 | PIPE_C, |
a57c774a AK |
113 | _PIPE_EDP, |
114 | I915_MAX_PIPES = _PIPE_EDP | |
317c35d1 | 115 | }; |
9db4a9c7 | 116 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 117 | |
a5c961d1 PZ |
118 | enum transcoder { |
119 | TRANSCODER_A = 0, | |
120 | TRANSCODER_B, | |
121 | TRANSCODER_C, | |
a57c774a AK |
122 | TRANSCODER_EDP, |
123 | I915_MAX_TRANSCODERS | |
a5c961d1 PZ |
124 | }; |
125 | #define transcoder_name(t) ((t) + 'A') | |
126 | ||
84139d1e DL |
127 | /* |
128 | * This is the maximum (across all platforms) number of planes (primary + | |
129 | * sprites) that can be active at the same time on one pipe. | |
130 | * | |
131 | * This value doesn't count the cursor plane. | |
132 | */ | |
8232edb5 | 133 | #define I915_MAX_PLANES 4 |
84139d1e | 134 | |
80824003 JB |
135 | enum plane { |
136 | PLANE_A = 0, | |
137 | PLANE_B, | |
9db4a9c7 | 138 | PLANE_C, |
80824003 | 139 | }; |
9db4a9c7 | 140 | #define plane_name(p) ((p) + 'A') |
52440211 | 141 | |
d615a166 | 142 | #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A') |
06da8da2 | 143 | |
2b139522 ED |
144 | enum port { |
145 | PORT_A = 0, | |
146 | PORT_B, | |
147 | PORT_C, | |
148 | PORT_D, | |
149 | PORT_E, | |
150 | I915_MAX_PORTS | |
151 | }; | |
152 | #define port_name(p) ((p) + 'A') | |
153 | ||
a09caddd | 154 | #define I915_NUM_PHYS_VLV 2 |
e4607fcf CML |
155 | |
156 | enum dpio_channel { | |
157 | DPIO_CH0, | |
158 | DPIO_CH1 | |
159 | }; | |
160 | ||
161 | enum dpio_phy { | |
162 | DPIO_PHY0, | |
163 | DPIO_PHY1 | |
164 | }; | |
165 | ||
b97186f0 PZ |
166 | enum intel_display_power_domain { |
167 | POWER_DOMAIN_PIPE_A, | |
168 | POWER_DOMAIN_PIPE_B, | |
169 | POWER_DOMAIN_PIPE_C, | |
170 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, | |
171 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, | |
172 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, | |
173 | POWER_DOMAIN_TRANSCODER_A, | |
174 | POWER_DOMAIN_TRANSCODER_B, | |
175 | POWER_DOMAIN_TRANSCODER_C, | |
f52e353e | 176 | POWER_DOMAIN_TRANSCODER_EDP, |
319be8ae ID |
177 | POWER_DOMAIN_PORT_DDI_A_2_LANES, |
178 | POWER_DOMAIN_PORT_DDI_A_4_LANES, | |
179 | POWER_DOMAIN_PORT_DDI_B_2_LANES, | |
180 | POWER_DOMAIN_PORT_DDI_B_4_LANES, | |
181 | POWER_DOMAIN_PORT_DDI_C_2_LANES, | |
182 | POWER_DOMAIN_PORT_DDI_C_4_LANES, | |
183 | POWER_DOMAIN_PORT_DDI_D_2_LANES, | |
184 | POWER_DOMAIN_PORT_DDI_D_4_LANES, | |
185 | POWER_DOMAIN_PORT_DSI, | |
186 | POWER_DOMAIN_PORT_CRT, | |
187 | POWER_DOMAIN_PORT_OTHER, | |
cdf8dd7f | 188 | POWER_DOMAIN_VGA, |
fbeeaa23 | 189 | POWER_DOMAIN_AUDIO, |
bd2bb1b9 | 190 | POWER_DOMAIN_PLLS, |
1407121a S |
191 | POWER_DOMAIN_AUX_A, |
192 | POWER_DOMAIN_AUX_B, | |
193 | POWER_DOMAIN_AUX_C, | |
194 | POWER_DOMAIN_AUX_D, | |
baa70707 | 195 | POWER_DOMAIN_INIT, |
bddc7645 ID |
196 | |
197 | POWER_DOMAIN_NUM, | |
b97186f0 PZ |
198 | }; |
199 | ||
200 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) | |
201 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ | |
202 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) | |
f52e353e ID |
203 | #define POWER_DOMAIN_TRANSCODER(tran) \ |
204 | ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ | |
205 | (tran) + POWER_DOMAIN_TRANSCODER_A) | |
b97186f0 | 206 | |
1d843f9d EE |
207 | enum hpd_pin { |
208 | HPD_NONE = 0, | |
209 | HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ | |
210 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ | |
211 | HPD_CRT, | |
212 | HPD_SDVO_B, | |
213 | HPD_SDVO_C, | |
214 | HPD_PORT_B, | |
215 | HPD_PORT_C, | |
216 | HPD_PORT_D, | |
217 | HPD_NUM_PINS | |
218 | }; | |
219 | ||
2a2d5482 CW |
220 | #define I915_GEM_GPU_DOMAINS \ |
221 | (I915_GEM_DOMAIN_RENDER | \ | |
222 | I915_GEM_DOMAIN_SAMPLER | \ | |
223 | I915_GEM_DOMAIN_COMMAND | \ | |
224 | I915_GEM_DOMAIN_INSTRUCTION | \ | |
225 | I915_GEM_DOMAIN_VERTEX) | |
62fdfeaf | 226 | |
055e393f DL |
227 | #define for_each_pipe(__dev_priv, __p) \ |
228 | for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) | |
dd740780 DL |
229 | #define for_each_plane(__dev_priv, __pipe, __p) \ |
230 | for ((__p) = 0; \ | |
231 | (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ | |
232 | (__p)++) | |
3bdcfc0c DL |
233 | #define for_each_sprite(__dev_priv, __p, __s) \ |
234 | for ((__s) = 0; \ | |
235 | (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \ | |
236 | (__s)++) | |
9db4a9c7 | 237 | |
d79b814d DL |
238 | #define for_each_crtc(dev, crtc) \ |
239 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | |
240 | ||
27321ae8 ML |
241 | #define for_each_intel_plane(dev, intel_plane) \ |
242 | list_for_each_entry(intel_plane, \ | |
243 | &dev->mode_config.plane_list, \ | |
244 | base.head) | |
245 | ||
d063ae48 DL |
246 | #define for_each_intel_crtc(dev, intel_crtc) \ |
247 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) | |
248 | ||
b2784e15 DL |
249 | #define for_each_intel_encoder(dev, intel_encoder) \ |
250 | list_for_each_entry(intel_encoder, \ | |
251 | &(dev)->mode_config.encoder_list, \ | |
252 | base.head) | |
253 | ||
3a3371ff ACO |
254 | #define for_each_intel_connector(dev, intel_connector) \ |
255 | list_for_each_entry(intel_connector, \ | |
256 | &dev->mode_config.connector_list, \ | |
257 | base.head) | |
258 | ||
6c2b7c12 DV |
259 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
260 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | |
261 | if ((intel_encoder)->base.crtc == (__crtc)) | |
262 | ||
53f5e3ca JB |
263 | #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ |
264 | list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ | |
265 | if ((intel_connector)->base.encoder == (__encoder)) | |
266 | ||
b04c5bd6 BF |
267 | #define for_each_power_domain(domain, mask) \ |
268 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
269 | if ((1 << (domain)) & (mask)) | |
270 | ||
e7b903d2 | 271 | struct drm_i915_private; |
ad46cb53 | 272 | struct i915_mm_struct; |
5cc9ed4b | 273 | struct i915_mmu_object; |
e7b903d2 | 274 | |
a6f766f3 CW |
275 | struct drm_i915_file_private { |
276 | struct drm_i915_private *dev_priv; | |
277 | struct drm_file *file; | |
278 | ||
279 | struct { | |
280 | spinlock_t lock; | |
281 | struct list_head request_list; | |
282 | } mm; | |
283 | struct idr context_idr; | |
284 | ||
2e1b8730 CW |
285 | struct intel_rps_client { |
286 | struct list_head link; | |
287 | unsigned boosts; | |
288 | } rps; | |
a6f766f3 | 289 | |
2e1b8730 | 290 | struct intel_engine_cs *bsd_ring; |
a6f766f3 CW |
291 | }; |
292 | ||
46edb027 DV |
293 | enum intel_dpll_id { |
294 | DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ | |
295 | /* real shared dpll ids must be >= 0 */ | |
9cd86933 DV |
296 | DPLL_ID_PCH_PLL_A = 0, |
297 | DPLL_ID_PCH_PLL_B = 1, | |
429d47d5 | 298 | /* hsw/bdw */ |
9cd86933 DV |
299 | DPLL_ID_WRPLL1 = 0, |
300 | DPLL_ID_WRPLL2 = 1, | |
429d47d5 S |
301 | /* skl */ |
302 | DPLL_ID_SKL_DPLL1 = 0, | |
303 | DPLL_ID_SKL_DPLL2 = 1, | |
304 | DPLL_ID_SKL_DPLL3 = 2, | |
46edb027 | 305 | }; |
429d47d5 | 306 | #define I915_NUM_PLLS 3 |
46edb027 | 307 | |
5358901f | 308 | struct intel_dpll_hw_state { |
dcfc3552 | 309 | /* i9xx, pch plls */ |
66e985c0 | 310 | uint32_t dpll; |
8bcc2795 | 311 | uint32_t dpll_md; |
66e985c0 DV |
312 | uint32_t fp0; |
313 | uint32_t fp1; | |
dcfc3552 DL |
314 | |
315 | /* hsw, bdw */ | |
d452c5b6 | 316 | uint32_t wrpll; |
d1a2dc78 S |
317 | |
318 | /* skl */ | |
319 | /* | |
320 | * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in | |
71cd8423 | 321 | * lower part of ctrl1 and they get shifted into position when writing |
d1a2dc78 S |
322 | * the register. This allows us to easily compare the state to share |
323 | * the DPLL. | |
324 | */ | |
325 | uint32_t ctrl1; | |
326 | /* HDMI only, 0 when used for DP */ | |
327 | uint32_t cfgcr1, cfgcr2; | |
dfb82408 S |
328 | |
329 | /* bxt */ | |
b6dc71f3 | 330 | uint32_t ebb0, pll0, pll1, pll2, pll3, pll6, pll8, pll10, pcsdw12; |
5358901f DV |
331 | }; |
332 | ||
3e369b76 | 333 | struct intel_shared_dpll_config { |
1e6f2ddc | 334 | unsigned crtc_mask; /* mask of CRTCs sharing this PLL */ |
3e369b76 ACO |
335 | struct intel_dpll_hw_state hw_state; |
336 | }; | |
337 | ||
338 | struct intel_shared_dpll { | |
339 | struct intel_shared_dpll_config config; | |
8bd31e67 ACO |
340 | struct intel_shared_dpll_config *new_config; |
341 | ||
ee7b9f93 JB |
342 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ |
343 | bool on; /* is the PLL actually active? Disabled during modeset */ | |
46edb027 DV |
344 | const char *name; |
345 | /* should match the index in the dev_priv->shared_dplls array */ | |
346 | enum intel_dpll_id id; | |
96f6128c DV |
347 | /* The mode_set hook is optional and should be used together with the |
348 | * intel_prepare_shared_dpll function. */ | |
15bdd4cf DV |
349 | void (*mode_set)(struct drm_i915_private *dev_priv, |
350 | struct intel_shared_dpll *pll); | |
e7b903d2 DV |
351 | void (*enable)(struct drm_i915_private *dev_priv, |
352 | struct intel_shared_dpll *pll); | |
353 | void (*disable)(struct drm_i915_private *dev_priv, | |
354 | struct intel_shared_dpll *pll); | |
5358901f DV |
355 | bool (*get_hw_state)(struct drm_i915_private *dev_priv, |
356 | struct intel_shared_dpll *pll, | |
357 | struct intel_dpll_hw_state *hw_state); | |
ee7b9f93 | 358 | }; |
ee7b9f93 | 359 | |
429d47d5 S |
360 | #define SKL_DPLL0 0 |
361 | #define SKL_DPLL1 1 | |
362 | #define SKL_DPLL2 2 | |
363 | #define SKL_DPLL3 3 | |
364 | ||
e69d0bc1 DV |
365 | /* Used by dp and fdi links */ |
366 | struct intel_link_m_n { | |
367 | uint32_t tu; | |
368 | uint32_t gmch_m; | |
369 | uint32_t gmch_n; | |
370 | uint32_t link_m; | |
371 | uint32_t link_n; | |
372 | }; | |
373 | ||
374 | void intel_link_compute_m_n(int bpp, int nlanes, | |
375 | int pixel_clock, int link_clock, | |
376 | struct intel_link_m_n *m_n); | |
377 | ||
1da177e4 LT |
378 | /* Interface history: |
379 | * | |
380 | * 1.1: Original. | |
0d6aa60b DA |
381 | * 1.2: Add Power Management |
382 | * 1.3: Add vblank support | |
de227f5f | 383 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 384 | * 1.5: Add vblank pipe configuration |
2228ed67 MD |
385 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
386 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
387 | */ |
388 | #define DRIVER_MAJOR 1 | |
2228ed67 | 389 | #define DRIVER_MINOR 6 |
1da177e4 LT |
390 | #define DRIVER_PATCHLEVEL 0 |
391 | ||
23bc5982 | 392 | #define WATCH_LISTS 0 |
673a394b | 393 | |
0a3e67a4 JB |
394 | struct opregion_header; |
395 | struct opregion_acpi; | |
396 | struct opregion_swsci; | |
397 | struct opregion_asle; | |
398 | ||
8ee1c3db | 399 | struct intel_opregion { |
5bc4418b BW |
400 | struct opregion_header __iomem *header; |
401 | struct opregion_acpi __iomem *acpi; | |
402 | struct opregion_swsci __iomem *swsci; | |
ebde53c7 JN |
403 | u32 swsci_gbda_sub_functions; |
404 | u32 swsci_sbcb_sub_functions; | |
5bc4418b BW |
405 | struct opregion_asle __iomem *asle; |
406 | void __iomem *vbt; | |
01fe9dbd | 407 | u32 __iomem *lid_state; |
91a60f20 | 408 | struct work_struct asle_work; |
8ee1c3db | 409 | }; |
44834a67 | 410 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 411 | |
6ef3d427 CW |
412 | struct intel_overlay; |
413 | struct intel_overlay_error_state; | |
414 | ||
de151cf6 | 415 | #define I915_FENCE_REG_NONE -1 |
42b5aeab VS |
416 | #define I915_MAX_NUM_FENCES 32 |
417 | /* 32 fences + sign bit for FENCE_REG_NONE */ | |
418 | #define I915_MAX_NUM_FENCE_BITS 6 | |
de151cf6 JB |
419 | |
420 | struct drm_i915_fence_reg { | |
007cc8ac | 421 | struct list_head lru_list; |
caea7476 | 422 | struct drm_i915_gem_object *obj; |
1690e1eb | 423 | int pin_count; |
de151cf6 | 424 | }; |
7c1c2871 | 425 | |
9b9d172d | 426 | struct sdvo_device_mapping { |
e957d772 | 427 | u8 initialized; |
9b9d172d | 428 | u8 dvo_port; |
429 | u8 slave_addr; | |
430 | u8 dvo_wiring; | |
e957d772 | 431 | u8 i2c_pin; |
b1083333 | 432 | u8 ddc_pin; |
9b9d172d | 433 | }; |
434 | ||
c4a1d9e4 CW |
435 | struct intel_display_error_state; |
436 | ||
63eeaf38 | 437 | struct drm_i915_error_state { |
742cbee8 | 438 | struct kref ref; |
585b0288 BW |
439 | struct timeval time; |
440 | ||
cb383002 | 441 | char error_msg[128]; |
48b031e3 | 442 | u32 reset_count; |
62d5d69b | 443 | u32 suspend_count; |
cb383002 | 444 | |
585b0288 | 445 | /* Generic register state */ |
63eeaf38 JB |
446 | u32 eir; |
447 | u32 pgtbl_er; | |
be998e2e | 448 | u32 ier; |
885ea5a8 | 449 | u32 gtier[4]; |
b9a3906b | 450 | u32 ccid; |
0f3b6849 CW |
451 | u32 derrmr; |
452 | u32 forcewake; | |
585b0288 BW |
453 | u32 error; /* gen6+ */ |
454 | u32 err_int; /* gen7 */ | |
6c826f34 MK |
455 | u32 fault_data0; /* gen8, gen9 */ |
456 | u32 fault_data1; /* gen8, gen9 */ | |
585b0288 | 457 | u32 done_reg; |
91ec5d11 BW |
458 | u32 gac_eco; |
459 | u32 gam_ecochk; | |
460 | u32 gab_ctl; | |
461 | u32 gfx_mode; | |
585b0288 | 462 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; |
585b0288 BW |
463 | u64 fence[I915_MAX_NUM_FENCES]; |
464 | struct intel_overlay_error_state *overlay; | |
465 | struct intel_display_error_state *display; | |
0ca36d78 | 466 | struct drm_i915_error_object *semaphore_obj; |
585b0288 | 467 | |
52d39a21 | 468 | struct drm_i915_error_ring { |
372fbb8e | 469 | bool valid; |
362b8af7 BW |
470 | /* Software tracked state */ |
471 | bool waiting; | |
472 | int hangcheck_score; | |
473 | enum intel_ring_hangcheck_action hangcheck_action; | |
474 | int num_requests; | |
475 | ||
476 | /* our own tracking of ring head and tail */ | |
477 | u32 cpu_ring_head; | |
478 | u32 cpu_ring_tail; | |
479 | ||
480 | u32 semaphore_seqno[I915_NUM_RINGS - 1]; | |
481 | ||
482 | /* Register state */ | |
94f8cf10 | 483 | u32 start; |
362b8af7 BW |
484 | u32 tail; |
485 | u32 head; | |
486 | u32 ctl; | |
487 | u32 hws; | |
488 | u32 ipeir; | |
489 | u32 ipehr; | |
490 | u32 instdone; | |
362b8af7 BW |
491 | u32 bbstate; |
492 | u32 instpm; | |
493 | u32 instps; | |
494 | u32 seqno; | |
495 | u64 bbaddr; | |
50877445 | 496 | u64 acthd; |
362b8af7 | 497 | u32 fault_reg; |
13ffadd1 | 498 | u64 faddr; |
362b8af7 BW |
499 | u32 rc_psmi; /* sleep state */ |
500 | u32 semaphore_mboxes[I915_NUM_RINGS - 1]; | |
501 | ||
52d39a21 CW |
502 | struct drm_i915_error_object { |
503 | int page_count; | |
504 | u32 gtt_offset; | |
505 | u32 *pages[0]; | |
ab0e7ff9 | 506 | } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; |
362b8af7 | 507 | |
52d39a21 CW |
508 | struct drm_i915_error_request { |
509 | long jiffies; | |
510 | u32 seqno; | |
ee4f42b1 | 511 | u32 tail; |
52d39a21 | 512 | } *requests; |
6c7a01ec BW |
513 | |
514 | struct { | |
515 | u32 gfx_mode; | |
516 | union { | |
517 | u64 pdp[4]; | |
518 | u32 pp_dir_base; | |
519 | }; | |
520 | } vm_info; | |
ab0e7ff9 CW |
521 | |
522 | pid_t pid; | |
523 | char comm[TASK_COMM_LEN]; | |
52d39a21 | 524 | } ring[I915_NUM_RINGS]; |
3a448734 | 525 | |
9df30794 | 526 | struct drm_i915_error_buffer { |
a779e5ab | 527 | u32 size; |
9df30794 | 528 | u32 name; |
b4716185 | 529 | u32 rseqno[I915_NUM_RINGS], wseqno; |
9df30794 CW |
530 | u32 gtt_offset; |
531 | u32 read_domains; | |
532 | u32 write_domain; | |
4b9de737 | 533 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
9df30794 CW |
534 | s32 pinned:2; |
535 | u32 tiling:2; | |
536 | u32 dirty:1; | |
537 | u32 purgeable:1; | |
5cc9ed4b | 538 | u32 userptr:1; |
5d1333fc | 539 | s32 ring:4; |
f56383cb | 540 | u32 cache_level:3; |
95f5301d | 541 | } **active_bo, **pinned_bo; |
6c7a01ec | 542 | |
95f5301d | 543 | u32 *active_bo_count, *pinned_bo_count; |
3a448734 | 544 | u32 vm_count; |
63eeaf38 JB |
545 | }; |
546 | ||
7bd688cd | 547 | struct intel_connector; |
820d2d77 | 548 | struct intel_encoder; |
5cec258b | 549 | struct intel_crtc_state; |
5724dbd1 | 550 | struct intel_initial_plane_config; |
0e8ffe1b | 551 | struct intel_crtc; |
ee9300bb DV |
552 | struct intel_limit; |
553 | struct dpll; | |
b8cecdf5 | 554 | |
e70236a8 | 555 | struct drm_i915_display_funcs { |
ee5382ae | 556 | bool (*fbc_enabled)(struct drm_device *dev); |
993495ae | 557 | void (*enable_fbc)(struct drm_crtc *crtc); |
e70236a8 JB |
558 | void (*disable_fbc)(struct drm_device *dev); |
559 | int (*get_display_clock_speed)(struct drm_device *dev); | |
560 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
ee9300bb DV |
561 | /** |
562 | * find_dpll() - Find the best values for the PLL | |
563 | * @limit: limits for the PLL | |
564 | * @crtc: current CRTC | |
565 | * @target: target frequency in kHz | |
566 | * @refclk: reference clock frequency in kHz | |
567 | * @match_clock: if provided, @best_clock P divider must | |
568 | * match the P divider from @match_clock | |
569 | * used for LVDS downclocking | |
570 | * @best_clock: best PLL values found | |
571 | * | |
572 | * Returns true on success, false on failure. | |
573 | */ | |
574 | bool (*find_dpll)(const struct intel_limit *limit, | |
a93e255f | 575 | struct intel_crtc_state *crtc_state, |
ee9300bb DV |
576 | int target, int refclk, |
577 | struct dpll *match_clock, | |
578 | struct dpll *best_clock); | |
46ba614c | 579 | void (*update_wm)(struct drm_crtc *crtc); |
adf3d35e VS |
580 | void (*update_sprite_wm)(struct drm_plane *plane, |
581 | struct drm_crtc *crtc, | |
ed57cb8a DL |
582 | uint32_t sprite_width, uint32_t sprite_height, |
583 | int pixel_size, bool enable, bool scaled); | |
679dacd4 | 584 | void (*modeset_global_resources)(struct drm_atomic_state *state); |
0e8ffe1b DV |
585 | /* Returns the active state of the crtc, and if the crtc is active, |
586 | * fills out the pipe-config with the hw state. */ | |
587 | bool (*get_pipe_config)(struct intel_crtc *, | |
5cec258b | 588 | struct intel_crtc_state *); |
5724dbd1 DL |
589 | void (*get_initial_plane_config)(struct intel_crtc *, |
590 | struct intel_initial_plane_config *); | |
190f68c5 ACO |
591 | int (*crtc_compute_clock)(struct intel_crtc *crtc, |
592 | struct intel_crtc_state *crtc_state); | |
76e5a89c DV |
593 | void (*crtc_enable)(struct drm_crtc *crtc); |
594 | void (*crtc_disable)(struct drm_crtc *crtc); | |
ee7b9f93 | 595 | void (*off)(struct drm_crtc *crtc); |
69bfe1a9 JN |
596 | void (*audio_codec_enable)(struct drm_connector *connector, |
597 | struct intel_encoder *encoder, | |
598 | struct drm_display_mode *mode); | |
599 | void (*audio_codec_disable)(struct intel_encoder *encoder); | |
674cf967 | 600 | void (*fdi_link_train)(struct drm_crtc *crtc); |
6067aaea | 601 | void (*init_clock_gating)(struct drm_device *dev); |
8c9f3aaf JB |
602 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
603 | struct drm_framebuffer *fb, | |
ed8d1975 | 604 | struct drm_i915_gem_object *obj, |
a4872ba6 | 605 | struct intel_engine_cs *ring, |
ed8d1975 | 606 | uint32_t flags); |
29b9bde6 DV |
607 | void (*update_primary_plane)(struct drm_crtc *crtc, |
608 | struct drm_framebuffer *fb, | |
609 | int x, int y); | |
20afbda2 | 610 | void (*hpd_irq_setup)(struct drm_device *dev); |
e70236a8 JB |
611 | /* clock updates for mode set */ |
612 | /* cursor updates */ | |
613 | /* render clock increase/decrease */ | |
614 | /* display clock increase/decrease */ | |
615 | /* pll clock increase/decrease */ | |
7bd688cd | 616 | |
6517d273 | 617 | int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe); |
7bd688cd JN |
618 | uint32_t (*get_backlight)(struct intel_connector *connector); |
619 | void (*set_backlight)(struct intel_connector *connector, | |
620 | uint32_t level); | |
621 | void (*disable_backlight)(struct intel_connector *connector); | |
622 | void (*enable_backlight)(struct intel_connector *connector); | |
e70236a8 JB |
623 | }; |
624 | ||
48c1026a MK |
625 | enum forcewake_domain_id { |
626 | FW_DOMAIN_ID_RENDER = 0, | |
627 | FW_DOMAIN_ID_BLITTER, | |
628 | FW_DOMAIN_ID_MEDIA, | |
629 | ||
630 | FW_DOMAIN_ID_COUNT | |
631 | }; | |
632 | ||
633 | enum forcewake_domains { | |
634 | FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER), | |
635 | FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER), | |
636 | FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA), | |
637 | FORCEWAKE_ALL = (FORCEWAKE_RENDER | | |
638 | FORCEWAKE_BLITTER | | |
639 | FORCEWAKE_MEDIA) | |
640 | }; | |
641 | ||
907b28c5 | 642 | struct intel_uncore_funcs { |
c8d9a590 | 643 | void (*force_wake_get)(struct drm_i915_private *dev_priv, |
48c1026a | 644 | enum forcewake_domains domains); |
c8d9a590 | 645 | void (*force_wake_put)(struct drm_i915_private *dev_priv, |
48c1026a | 646 | enum forcewake_domains domains); |
0b274481 BW |
647 | |
648 | uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
649 | uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
650 | uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
651 | uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
652 | ||
653 | void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset, | |
654 | uint8_t val, bool trace); | |
655 | void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset, | |
656 | uint16_t val, bool trace); | |
657 | void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset, | |
658 | uint32_t val, bool trace); | |
659 | void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset, | |
660 | uint64_t val, bool trace); | |
990bbdad CW |
661 | }; |
662 | ||
907b28c5 CW |
663 | struct intel_uncore { |
664 | spinlock_t lock; /** lock is also taken in irq contexts. */ | |
665 | ||
666 | struct intel_uncore_funcs funcs; | |
667 | ||
668 | unsigned fifo_count; | |
48c1026a | 669 | enum forcewake_domains fw_domains; |
b2cff0db CW |
670 | |
671 | struct intel_uncore_forcewake_domain { | |
672 | struct drm_i915_private *i915; | |
48c1026a | 673 | enum forcewake_domain_id id; |
b2cff0db CW |
674 | unsigned wake_count; |
675 | struct timer_list timer; | |
05a2fb15 MK |
676 | u32 reg_set; |
677 | u32 val_set; | |
678 | u32 val_clear; | |
679 | u32 reg_ack; | |
680 | u32 reg_post; | |
681 | u32 val_reset; | |
b2cff0db | 682 | } fw_domain[FW_DOMAIN_ID_COUNT]; |
b2cff0db CW |
683 | }; |
684 | ||
685 | /* Iterate over initialised fw domains */ | |
686 | #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \ | |
687 | for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \ | |
688 | (i__) < FW_DOMAIN_ID_COUNT; \ | |
689 | (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \ | |
690 | if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__))) | |
691 | ||
692 | #define for_each_fw_domain(domain__, dev_priv__, i__) \ | |
693 | for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__) | |
907b28c5 | 694 | |
dc174300 SS |
695 | enum csr_state { |
696 | FW_UNINITIALIZED = 0, | |
697 | FW_LOADED, | |
698 | FW_FAILED | |
699 | }; | |
700 | ||
eb805623 DV |
701 | struct intel_csr { |
702 | const char *fw_path; | |
703 | __be32 *dmc_payload; | |
704 | uint32_t dmc_fw_size; | |
705 | uint32_t mmio_count; | |
706 | uint32_t mmioaddr[8]; | |
707 | uint32_t mmiodata[8]; | |
dc174300 | 708 | enum csr_state state; |
eb805623 DV |
709 | }; |
710 | ||
79fc46df DL |
711 | #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ |
712 | func(is_mobile) sep \ | |
713 | func(is_i85x) sep \ | |
714 | func(is_i915g) sep \ | |
715 | func(is_i945gm) sep \ | |
716 | func(is_g33) sep \ | |
717 | func(need_gfx_hws) sep \ | |
718 | func(is_g4x) sep \ | |
719 | func(is_pineview) sep \ | |
720 | func(is_broadwater) sep \ | |
721 | func(is_crestline) sep \ | |
722 | func(is_ivybridge) sep \ | |
723 | func(is_valleyview) sep \ | |
724 | func(is_haswell) sep \ | |
7201c0b3 | 725 | func(is_skylake) sep \ |
b833d685 | 726 | func(is_preliminary) sep \ |
79fc46df DL |
727 | func(has_fbc) sep \ |
728 | func(has_pipe_cxsr) sep \ | |
729 | func(has_hotplug) sep \ | |
730 | func(cursor_needs_physical) sep \ | |
731 | func(has_overlay) sep \ | |
732 | func(overlay_needs_physical) sep \ | |
733 | func(supports_tv) sep \ | |
dd93be58 | 734 | func(has_llc) sep \ |
30568c45 DL |
735 | func(has_ddi) sep \ |
736 | func(has_fpga_dbg) | |
c96ea64e | 737 | |
a587f779 DL |
738 | #define DEFINE_FLAG(name) u8 name:1 |
739 | #define SEP_SEMICOLON ; | |
c96ea64e | 740 | |
cfdf1fa2 | 741 | struct intel_device_info { |
10fce67a | 742 | u32 display_mmio_offset; |
87f1f465 | 743 | u16 device_id; |
7eb552ae | 744 | u8 num_pipes:3; |
d615a166 | 745 | u8 num_sprites[I915_MAX_PIPES]; |
c96c3a8c | 746 | u8 gen; |
73ae478c | 747 | u8 ring_mask; /* Rings supported by the HW */ |
a587f779 | 748 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); |
a57c774a AK |
749 | /* Register offsets for the various display pipes and transcoders */ |
750 | int pipe_offsets[I915_MAX_TRANSCODERS]; | |
751 | int trans_offsets[I915_MAX_TRANSCODERS]; | |
a57c774a | 752 | int palette_offsets[I915_MAX_PIPES]; |
5efb3e28 | 753 | int cursor_offsets[I915_MAX_PIPES]; |
3873218f JM |
754 | |
755 | /* Slice/subslice/EU info */ | |
756 | u8 slice_total; | |
757 | u8 subslice_total; | |
758 | u8 subslice_per_slice; | |
759 | u8 eu_total; | |
760 | u8 eu_per_subslice; | |
b7668791 DL |
761 | /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ |
762 | u8 subslice_7eu[3]; | |
3873218f JM |
763 | u8 has_slice_pg:1; |
764 | u8 has_subslice_pg:1; | |
765 | u8 has_eu_pg:1; | |
cfdf1fa2 KH |
766 | }; |
767 | ||
a587f779 DL |
768 | #undef DEFINE_FLAG |
769 | #undef SEP_SEMICOLON | |
770 | ||
7faf1ab2 DV |
771 | enum i915_cache_level { |
772 | I915_CACHE_NONE = 0, | |
350ec881 CW |
773 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ |
774 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc | |
775 | caches, eg sampler/render caches, and the | |
776 | large Last-Level-Cache. LLC is coherent with | |
777 | the CPU, but L3 is only visible to the GPU. */ | |
651d794f | 778 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ |
7faf1ab2 DV |
779 | }; |
780 | ||
e59ec13d MK |
781 | struct i915_ctx_hang_stats { |
782 | /* This context had batch pending when hang was declared */ | |
783 | unsigned batch_pending; | |
784 | ||
785 | /* This context had batch active when hang was declared */ | |
786 | unsigned batch_active; | |
be62acb4 MK |
787 | |
788 | /* Time when this context was last blamed for a GPU reset */ | |
789 | unsigned long guilty_ts; | |
790 | ||
676fa572 CW |
791 | /* If the contexts causes a second GPU hang within this time, |
792 | * it is permanently banned from submitting any more work. | |
793 | */ | |
794 | unsigned long ban_period_seconds; | |
795 | ||
be62acb4 MK |
796 | /* This context is banned to submit more work */ |
797 | bool banned; | |
e59ec13d | 798 | }; |
40521054 BW |
799 | |
800 | /* This must match up with the value previously used for execbuf2.rsvd1. */ | |
821d66dd | 801 | #define DEFAULT_CONTEXT_HANDLE 0 |
31b7a88d OM |
802 | /** |
803 | * struct intel_context - as the name implies, represents a context. | |
804 | * @ref: reference count. | |
805 | * @user_handle: userspace tracking identity for this context. | |
806 | * @remap_slice: l3 row remapping information. | |
807 | * @file_priv: filp associated with this context (NULL for global default | |
808 | * context). | |
809 | * @hang_stats: information about the role of this context in possible GPU | |
810 | * hangs. | |
7df113e4 | 811 | * @ppgtt: virtual memory space used by this context. |
31b7a88d OM |
812 | * @legacy_hw_ctx: render context backing object and whether it is correctly |
813 | * initialized (legacy ring submission mechanism only). | |
814 | * @link: link in the global list of contexts. | |
815 | * | |
816 | * Contexts are memory images used by the hardware to store copies of their | |
817 | * internal state. | |
818 | */ | |
273497e5 | 819 | struct intel_context { |
dce3271b | 820 | struct kref ref; |
821d66dd | 821 | int user_handle; |
3ccfd19d | 822 | uint8_t remap_slice; |
40521054 | 823 | struct drm_i915_file_private *file_priv; |
e59ec13d | 824 | struct i915_ctx_hang_stats hang_stats; |
ae6c4806 | 825 | struct i915_hw_ppgtt *ppgtt; |
a33afea5 | 826 | |
c9e003af | 827 | /* Legacy ring buffer submission */ |
ea0c76f8 OM |
828 | struct { |
829 | struct drm_i915_gem_object *rcs_state; | |
830 | bool initialized; | |
831 | } legacy_hw_ctx; | |
832 | ||
c9e003af | 833 | /* Execlists */ |
564ddb2f | 834 | bool rcs_initialized; |
c9e003af OM |
835 | struct { |
836 | struct drm_i915_gem_object *state; | |
84c2377f | 837 | struct intel_ringbuffer *ringbuf; |
a7cbedec | 838 | int pin_count; |
c9e003af OM |
839 | } engine[I915_NUM_RINGS]; |
840 | ||
a33afea5 | 841 | struct list_head link; |
40521054 BW |
842 | }; |
843 | ||
a4001f1b PZ |
844 | enum fb_op_origin { |
845 | ORIGIN_GTT, | |
846 | ORIGIN_CPU, | |
847 | ORIGIN_CS, | |
848 | ORIGIN_FLIP, | |
849 | }; | |
850 | ||
5c3fe8b0 | 851 | struct i915_fbc { |
60ee5cd2 | 852 | unsigned long uncompressed_size; |
5e59f717 | 853 | unsigned threshold; |
5c3fe8b0 | 854 | unsigned int fb_id; |
dbef0f15 PZ |
855 | unsigned int possible_framebuffer_bits; |
856 | unsigned int busy_bits; | |
e35fef21 | 857 | struct intel_crtc *crtc; |
5c3fe8b0 BW |
858 | int y; |
859 | ||
c4213885 | 860 | struct drm_mm_node compressed_fb; |
5c3fe8b0 BW |
861 | struct drm_mm_node *compressed_llb; |
862 | ||
da46f936 RV |
863 | bool false_color; |
864 | ||
9adccc60 PZ |
865 | /* Tracks whether the HW is actually enabled, not whether the feature is |
866 | * possible. */ | |
867 | bool enabled; | |
868 | ||
5c3fe8b0 BW |
869 | struct intel_fbc_work { |
870 | struct delayed_work work; | |
871 | struct drm_crtc *crtc; | |
872 | struct drm_framebuffer *fb; | |
5c3fe8b0 BW |
873 | } *fbc_work; |
874 | ||
29ebf90f CW |
875 | enum no_fbc_reason { |
876 | FBC_OK, /* FBC is enabled */ | |
877 | FBC_UNSUPPORTED, /* FBC is not supported by this chipset */ | |
5c3fe8b0 BW |
878 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
879 | FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */ | |
880 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ | |
881 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ | |
882 | FBC_BAD_PLANE, /* fbc not supported on plane */ | |
883 | FBC_NOT_TILED, /* buffer not tiled */ | |
884 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ | |
885 | FBC_MODULE_PARAM, | |
886 | FBC_CHIP_DEFAULT, /* disabled by default on this chip */ | |
887 | } no_fbc_reason; | |
b5e50c3f JB |
888 | }; |
889 | ||
96178eeb VK |
890 | /** |
891 | * HIGH_RR is the highest eDP panel refresh rate read from EDID | |
892 | * LOW_RR is the lowest eDP panel refresh rate found from EDID | |
893 | * parsing for same resolution. | |
894 | */ | |
895 | enum drrs_refresh_rate_type { | |
896 | DRRS_HIGH_RR, | |
897 | DRRS_LOW_RR, | |
898 | DRRS_MAX_RR, /* RR count */ | |
899 | }; | |
900 | ||
901 | enum drrs_support_type { | |
902 | DRRS_NOT_SUPPORTED = 0, | |
903 | STATIC_DRRS_SUPPORT = 1, | |
904 | SEAMLESS_DRRS_SUPPORT = 2 | |
439d7ac0 PB |
905 | }; |
906 | ||
2807cf69 | 907 | struct intel_dp; |
96178eeb VK |
908 | struct i915_drrs { |
909 | struct mutex mutex; | |
910 | struct delayed_work work; | |
911 | struct intel_dp *dp; | |
912 | unsigned busy_frontbuffer_bits; | |
913 | enum drrs_refresh_rate_type refresh_rate_type; | |
914 | enum drrs_support_type type; | |
915 | }; | |
916 | ||
a031d709 | 917 | struct i915_psr { |
f0355c4a | 918 | struct mutex lock; |
a031d709 RV |
919 | bool sink_support; |
920 | bool source_ok; | |
2807cf69 | 921 | struct intel_dp *enabled; |
7c8f8a70 RV |
922 | bool active; |
923 | struct delayed_work work; | |
9ca15301 | 924 | unsigned busy_frontbuffer_bits; |
474d1ec4 SJ |
925 | bool psr2_support; |
926 | bool aux_frame_sync; | |
3f51e471 | 927 | }; |
5c3fe8b0 | 928 | |
3bad0781 | 929 | enum intel_pch { |
f0350830 | 930 | PCH_NONE = 0, /* No PCH present */ |
3bad0781 ZW |
931 | PCH_IBX, /* Ibexpeak PCH */ |
932 | PCH_CPT, /* Cougarpoint PCH */ | |
eb877ebf | 933 | PCH_LPT, /* Lynxpoint PCH */ |
e7e7ea20 | 934 | PCH_SPT, /* Sunrisepoint PCH */ |
40c7ead9 | 935 | PCH_NOP, |
3bad0781 ZW |
936 | }; |
937 | ||
988d6ee8 PZ |
938 | enum intel_sbi_destination { |
939 | SBI_ICLK, | |
940 | SBI_MPHY, | |
941 | }; | |
942 | ||
b690e96c | 943 | #define QUIRK_PIPEA_FORCE (1<<0) |
435793df | 944 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
4dca20ef | 945 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
9c72cc6f | 946 | #define QUIRK_BACKLIGHT_PRESENT (1<<3) |
b6b5d049 | 947 | #define QUIRK_PIPEB_FORCE (1<<4) |
656bfa3a | 948 | #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) |
b690e96c | 949 | |
8be48d92 | 950 | struct intel_fbdev; |
1630fe75 | 951 | struct intel_fbc_work; |
38651674 | 952 | |
c2b9152f DV |
953 | struct intel_gmbus { |
954 | struct i2c_adapter adapter; | |
f2ce9faf | 955 | u32 force_bit; |
c2b9152f | 956 | u32 reg0; |
36c785f0 | 957 | u32 gpio_reg; |
c167a6fc | 958 | struct i2c_algo_bit_data bit_algo; |
c2b9152f DV |
959 | struct drm_i915_private *dev_priv; |
960 | }; | |
961 | ||
f4c956ad | 962 | struct i915_suspend_saved_registers { |
e948e994 | 963 | u32 saveDSPARB; |
ba8bbcf6 | 964 | u32 saveLVDS; |
585fb111 JB |
965 | u32 savePP_ON_DELAYS; |
966 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
967 | u32 savePP_ON; |
968 | u32 savePP_OFF; | |
969 | u32 savePP_CONTROL; | |
585fb111 | 970 | u32 savePP_DIVISOR; |
ba8bbcf6 | 971 | u32 saveFBC_CONTROL; |
1f84e550 | 972 | u32 saveCACHE_MODE_0; |
1f84e550 | 973 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
974 | u32 saveSWF0[16]; |
975 | u32 saveSWF1[16]; | |
976 | u32 saveSWF2[3]; | |
4b9de737 | 977 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
cda2bb78 | 978 | u32 savePCH_PORT_HOTPLUG; |
9f49c376 | 979 | u16 saveGCDGMBUS; |
f4c956ad | 980 | }; |
c85aa885 | 981 | |
ddeea5b0 ID |
982 | struct vlv_s0ix_state { |
983 | /* GAM */ | |
984 | u32 wr_watermark; | |
985 | u32 gfx_prio_ctrl; | |
986 | u32 arb_mode; | |
987 | u32 gfx_pend_tlb0; | |
988 | u32 gfx_pend_tlb1; | |
989 | u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; | |
990 | u32 media_max_req_count; | |
991 | u32 gfx_max_req_count; | |
992 | u32 render_hwsp; | |
993 | u32 ecochk; | |
994 | u32 bsd_hwsp; | |
995 | u32 blt_hwsp; | |
996 | u32 tlb_rd_addr; | |
997 | ||
998 | /* MBC */ | |
999 | u32 g3dctl; | |
1000 | u32 gsckgctl; | |
1001 | u32 mbctl; | |
1002 | ||
1003 | /* GCP */ | |
1004 | u32 ucgctl1; | |
1005 | u32 ucgctl3; | |
1006 | u32 rcgctl1; | |
1007 | u32 rcgctl2; | |
1008 | u32 rstctl; | |
1009 | u32 misccpctl; | |
1010 | ||
1011 | /* GPM */ | |
1012 | u32 gfxpause; | |
1013 | u32 rpdeuhwtc; | |
1014 | u32 rpdeuc; | |
1015 | u32 ecobus; | |
1016 | u32 pwrdwnupctl; | |
1017 | u32 rp_down_timeout; | |
1018 | u32 rp_deucsw; | |
1019 | u32 rcubmabdtmr; | |
1020 | u32 rcedata; | |
1021 | u32 spare2gh; | |
1022 | ||
1023 | /* Display 1 CZ domain */ | |
1024 | u32 gt_imr; | |
1025 | u32 gt_ier; | |
1026 | u32 pm_imr; | |
1027 | u32 pm_ier; | |
1028 | u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; | |
1029 | ||
1030 | /* GT SA CZ domain */ | |
1031 | u32 tilectl; | |
1032 | u32 gt_fifoctl; | |
1033 | u32 gtlc_wake_ctrl; | |
1034 | u32 gtlc_survive; | |
1035 | u32 pmwgicz; | |
1036 | ||
1037 | /* Display 2 CZ domain */ | |
1038 | u32 gu_ctl0; | |
1039 | u32 gu_ctl1; | |
9c25210f | 1040 | u32 pcbr; |
ddeea5b0 ID |
1041 | u32 clock_gate_dis2; |
1042 | }; | |
1043 | ||
bf225f20 CW |
1044 | struct intel_rps_ei { |
1045 | u32 cz_clock; | |
1046 | u32 render_c0; | |
1047 | u32 media_c0; | |
31685c25 D |
1048 | }; |
1049 | ||
c85aa885 | 1050 | struct intel_gen6_power_mgmt { |
d4d70aa5 ID |
1051 | /* |
1052 | * work, interrupts_enabled and pm_iir are protected by | |
1053 | * dev_priv->irq_lock | |
1054 | */ | |
c85aa885 | 1055 | struct work_struct work; |
d4d70aa5 | 1056 | bool interrupts_enabled; |
c85aa885 | 1057 | u32 pm_iir; |
59cdb63d | 1058 | |
b39fb297 BW |
1059 | /* Frequencies are stored in potentially platform dependent multiples. |
1060 | * In other words, *_freq needs to be multiplied by X to be interesting. | |
1061 | * Soft limits are those which are used for the dynamic reclocking done | |
1062 | * by the driver (raise frequencies under heavy loads, and lower for | |
1063 | * lighter loads). Hard limits are those imposed by the hardware. | |
1064 | * | |
1065 | * A distinction is made for overclocking, which is never enabled by | |
1066 | * default, and is considered to be above the hard limit if it's | |
1067 | * possible at all. | |
1068 | */ | |
1069 | u8 cur_freq; /* Current frequency (cached, may not == HW) */ | |
1070 | u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ | |
1071 | u8 max_freq_softlimit; /* Max frequency permitted by the driver */ | |
1072 | u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ | |
1073 | u8 min_freq; /* AKA RPn. Minimum frequency */ | |
aed242ff | 1074 | u8 idle_freq; /* Frequency to request when we are idle */ |
b39fb297 BW |
1075 | u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ |
1076 | u8 rp1_freq; /* "less than" RP0 power/freqency */ | |
1077 | u8 rp0_freq; /* Non-overclocked max frequency. */ | |
67c3bf6f | 1078 | u32 cz_freq; |
1a01ab3b | 1079 | |
8fb55197 CW |
1080 | u8 up_threshold; /* Current %busy required to uplock */ |
1081 | u8 down_threshold; /* Current %busy required to downclock */ | |
1082 | ||
dd75fdc8 CW |
1083 | int last_adj; |
1084 | enum { LOW_POWER, BETWEEN, HIGH_POWER } power; | |
1085 | ||
c0951f0c | 1086 | bool enabled; |
1a01ab3b | 1087 | struct delayed_work delayed_resume_work; |
1854d5ca CW |
1088 | struct list_head clients; |
1089 | unsigned boosts; | |
4fc688ce | 1090 | |
2e1b8730 | 1091 | struct intel_rps_client semaphores, mmioflips; |
a6f766f3 | 1092 | |
bf225f20 CW |
1093 | /* manual wa residency calculations */ |
1094 | struct intel_rps_ei up_ei, down_ei; | |
1095 | ||
4fc688ce JB |
1096 | /* |
1097 | * Protects RPS/RC6 register access and PCU communication. | |
1098 | * Must be taken after struct_mutex if nested. | |
1099 | */ | |
1100 | struct mutex hw_lock; | |
c85aa885 DV |
1101 | }; |
1102 | ||
1a240d4d DV |
1103 | /* defined intel_pm.c */ |
1104 | extern spinlock_t mchdev_lock; | |
1105 | ||
c85aa885 DV |
1106 | struct intel_ilk_power_mgmt { |
1107 | u8 cur_delay; | |
1108 | u8 min_delay; | |
1109 | u8 max_delay; | |
1110 | u8 fmax; | |
1111 | u8 fstart; | |
1112 | ||
1113 | u64 last_count1; | |
1114 | unsigned long last_time1; | |
1115 | unsigned long chipset_power; | |
1116 | u64 last_count2; | |
5ed0bdf2 | 1117 | u64 last_time2; |
c85aa885 DV |
1118 | unsigned long gfx_power; |
1119 | u8 corr; | |
1120 | ||
1121 | int c_m; | |
1122 | int r_t; | |
1123 | }; | |
1124 | ||
c6cb582e ID |
1125 | struct drm_i915_private; |
1126 | struct i915_power_well; | |
1127 | ||
1128 | struct i915_power_well_ops { | |
1129 | /* | |
1130 | * Synchronize the well's hw state to match the current sw state, for | |
1131 | * example enable/disable it based on the current refcount. Called | |
1132 | * during driver init and resume time, possibly after first calling | |
1133 | * the enable/disable handlers. | |
1134 | */ | |
1135 | void (*sync_hw)(struct drm_i915_private *dev_priv, | |
1136 | struct i915_power_well *power_well); | |
1137 | /* | |
1138 | * Enable the well and resources that depend on it (for example | |
1139 | * interrupts located on the well). Called after the 0->1 refcount | |
1140 | * transition. | |
1141 | */ | |
1142 | void (*enable)(struct drm_i915_private *dev_priv, | |
1143 | struct i915_power_well *power_well); | |
1144 | /* | |
1145 | * Disable the well and resources that depend on it. Called after | |
1146 | * the 1->0 refcount transition. | |
1147 | */ | |
1148 | void (*disable)(struct drm_i915_private *dev_priv, | |
1149 | struct i915_power_well *power_well); | |
1150 | /* Returns the hw enabled state. */ | |
1151 | bool (*is_enabled)(struct drm_i915_private *dev_priv, | |
1152 | struct i915_power_well *power_well); | |
1153 | }; | |
1154 | ||
a38911a3 WX |
1155 | /* Power well structure for haswell */ |
1156 | struct i915_power_well { | |
c1ca727f | 1157 | const char *name; |
6f3ef5dd | 1158 | bool always_on; |
a38911a3 WX |
1159 | /* power well enable/disable usage count */ |
1160 | int count; | |
bfafe93a ID |
1161 | /* cached hw enabled state */ |
1162 | bool hw_enabled; | |
c1ca727f | 1163 | unsigned long domains; |
77961eb9 | 1164 | unsigned long data; |
c6cb582e | 1165 | const struct i915_power_well_ops *ops; |
a38911a3 WX |
1166 | }; |
1167 | ||
83c00f55 | 1168 | struct i915_power_domains { |
baa70707 ID |
1169 | /* |
1170 | * Power wells needed for initialization at driver init and suspend | |
1171 | * time are on. They are kept on until after the first modeset. | |
1172 | */ | |
1173 | bool init_power_on; | |
0d116a29 | 1174 | bool initializing; |
c1ca727f | 1175 | int power_well_count; |
baa70707 | 1176 | |
83c00f55 | 1177 | struct mutex lock; |
1da51581 | 1178 | int domain_use_count[POWER_DOMAIN_NUM]; |
c1ca727f | 1179 | struct i915_power_well *power_wells; |
83c00f55 ID |
1180 | }; |
1181 | ||
35a85ac6 | 1182 | #define MAX_L3_SLICES 2 |
a4da4fa4 | 1183 | struct intel_l3_parity { |
35a85ac6 | 1184 | u32 *remap_info[MAX_L3_SLICES]; |
a4da4fa4 | 1185 | struct work_struct error_work; |
35a85ac6 | 1186 | int which_slice; |
a4da4fa4 DV |
1187 | }; |
1188 | ||
4b5aed62 | 1189 | struct i915_gem_mm { |
4b5aed62 DV |
1190 | /** Memory allocator for GTT stolen memory */ |
1191 | struct drm_mm stolen; | |
4b5aed62 DV |
1192 | /** List of all objects in gtt_space. Used to restore gtt |
1193 | * mappings on resume */ | |
1194 | struct list_head bound_list; | |
1195 | /** | |
1196 | * List of objects which are not bound to the GTT (thus | |
1197 | * are idle and not used by the GPU) but still have | |
1198 | * (presumably uncached) pages still attached. | |
1199 | */ | |
1200 | struct list_head unbound_list; | |
1201 | ||
1202 | /** Usable portion of the GTT for GEM */ | |
1203 | unsigned long stolen_base; /* limited to low memory (32-bit) */ | |
1204 | ||
4b5aed62 DV |
1205 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
1206 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
1207 | ||
2cfcd32a | 1208 | struct notifier_block oom_notifier; |
ceabbba5 | 1209 | struct shrinker shrinker; |
4b5aed62 DV |
1210 | bool shrinker_no_lock_stealing; |
1211 | ||
4b5aed62 DV |
1212 | /** LRU list of objects with fence regs on them. */ |
1213 | struct list_head fence_list; | |
1214 | ||
1215 | /** | |
1216 | * We leave the user IRQ off as much as possible, | |
1217 | * but this means that requests will finish and never | |
1218 | * be retired once the system goes idle. Set a timer to | |
1219 | * fire periodically while the ring is running. When it | |
1220 | * fires, go retire requests. | |
1221 | */ | |
1222 | struct delayed_work retire_work; | |
1223 | ||
b29c19b6 CW |
1224 | /** |
1225 | * When we detect an idle GPU, we want to turn on | |
1226 | * powersaving features. So once we see that there | |
1227 | * are no more requests outstanding and no more | |
1228 | * arrive within a small period of time, we fire | |
1229 | * off the idle_work. | |
1230 | */ | |
1231 | struct delayed_work idle_work; | |
1232 | ||
4b5aed62 DV |
1233 | /** |
1234 | * Are we in a non-interruptible section of code like | |
1235 | * modesetting? | |
1236 | */ | |
1237 | bool interruptible; | |
1238 | ||
f62a0076 CW |
1239 | /** |
1240 | * Is the GPU currently considered idle, or busy executing userspace | |
1241 | * requests? Whilst idle, we attempt to power down the hardware and | |
1242 | * display clocks. In order to reduce the effect on performance, there | |
1243 | * is a slight delay before we do so. | |
1244 | */ | |
1245 | bool busy; | |
1246 | ||
bdf1e7e3 DV |
1247 | /* the indicator for dispatch video commands on two BSD rings */ |
1248 | int bsd_ring_dispatch_index; | |
1249 | ||
4b5aed62 DV |
1250 | /** Bit 6 swizzling required for X tiling */ |
1251 | uint32_t bit_6_swizzle_x; | |
1252 | /** Bit 6 swizzling required for Y tiling */ | |
1253 | uint32_t bit_6_swizzle_y; | |
1254 | ||
4b5aed62 | 1255 | /* accounting, useful for userland debugging */ |
c20e8355 | 1256 | spinlock_t object_stat_lock; |
4b5aed62 DV |
1257 | size_t object_memory; |
1258 | u32 object_count; | |
1259 | }; | |
1260 | ||
edc3d884 | 1261 | struct drm_i915_error_state_buf { |
0a4cd7c8 | 1262 | struct drm_i915_private *i915; |
edc3d884 MK |
1263 | unsigned bytes; |
1264 | unsigned size; | |
1265 | int err; | |
1266 | u8 *buf; | |
1267 | loff_t start; | |
1268 | loff_t pos; | |
1269 | }; | |
1270 | ||
fc16b48b MK |
1271 | struct i915_error_state_file_priv { |
1272 | struct drm_device *dev; | |
1273 | struct drm_i915_error_state *error; | |
1274 | }; | |
1275 | ||
99584db3 DV |
1276 | struct i915_gpu_error { |
1277 | /* For hangcheck timer */ | |
1278 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ | |
1279 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) | |
be62acb4 MK |
1280 | /* Hang gpu twice in this window and your context gets banned */ |
1281 | #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) | |
1282 | ||
737b1506 CW |
1283 | struct workqueue_struct *hangcheck_wq; |
1284 | struct delayed_work hangcheck_work; | |
99584db3 DV |
1285 | |
1286 | /* For reset and error_state handling. */ | |
1287 | spinlock_t lock; | |
1288 | /* Protected by the above dev->gpu_error.lock. */ | |
1289 | struct drm_i915_error_state *first_error; | |
094f9a54 CW |
1290 | |
1291 | unsigned long missed_irq_rings; | |
1292 | ||
1f83fee0 | 1293 | /** |
2ac0f450 | 1294 | * State variable controlling the reset flow and count |
1f83fee0 | 1295 | * |
2ac0f450 MK |
1296 | * This is a counter which gets incremented when reset is triggered, |
1297 | * and again when reset has been handled. So odd values (lowest bit set) | |
1298 | * means that reset is in progress and even values that | |
1299 | * (reset_counter >> 1):th reset was successfully completed. | |
1300 | * | |
1301 | * If reset is not completed succesfully, the I915_WEDGE bit is | |
1302 | * set meaning that hardware is terminally sour and there is no | |
1303 | * recovery. All waiters on the reset_queue will be woken when | |
1304 | * that happens. | |
1305 | * | |
1306 | * This counter is used by the wait_seqno code to notice that reset | |
1307 | * event happened and it needs to restart the entire ioctl (since most | |
1308 | * likely the seqno it waited for won't ever signal anytime soon). | |
f69061be DV |
1309 | * |
1310 | * This is important for lock-free wait paths, where no contended lock | |
1311 | * naturally enforces the correct ordering between the bail-out of the | |
1312 | * waiter and the gpu reset work code. | |
1f83fee0 DV |
1313 | */ |
1314 | atomic_t reset_counter; | |
1315 | ||
1f83fee0 | 1316 | #define I915_RESET_IN_PROGRESS_FLAG 1 |
2ac0f450 | 1317 | #define I915_WEDGED (1 << 31) |
1f83fee0 DV |
1318 | |
1319 | /** | |
1320 | * Waitqueue to signal when the reset has completed. Used by clients | |
1321 | * that wait for dev_priv->mm.wedged to settle. | |
1322 | */ | |
1323 | wait_queue_head_t reset_queue; | |
33196ded | 1324 | |
88b4aa87 MK |
1325 | /* Userspace knobs for gpu hang simulation; |
1326 | * combines both a ring mask, and extra flags | |
1327 | */ | |
1328 | u32 stop_rings; | |
1329 | #define I915_STOP_RING_ALLOW_BAN (1 << 31) | |
1330 | #define I915_STOP_RING_ALLOW_WARN (1 << 30) | |
094f9a54 CW |
1331 | |
1332 | /* For missed irq/seqno simulation. */ | |
1333 | unsigned int test_irq_rings; | |
6689c167 MA |
1334 | |
1335 | /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */ | |
1336 | bool reload_in_reset; | |
99584db3 DV |
1337 | }; |
1338 | ||
b8efb17b ZR |
1339 | enum modeset_restore { |
1340 | MODESET_ON_LID_OPEN, | |
1341 | MODESET_DONE, | |
1342 | MODESET_SUSPENDED, | |
1343 | }; | |
1344 | ||
6acab15a | 1345 | struct ddi_vbt_port_info { |
ce4dd49e DL |
1346 | /* |
1347 | * This is an index in the HDMI/DVI DDI buffer translation table. | |
1348 | * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't | |
1349 | * populate this field. | |
1350 | */ | |
1351 | #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff | |
6acab15a | 1352 | uint8_t hdmi_level_shift; |
311a2094 PZ |
1353 | |
1354 | uint8_t supports_dvi:1; | |
1355 | uint8_t supports_hdmi:1; | |
1356 | uint8_t supports_dp:1; | |
6acab15a PZ |
1357 | }; |
1358 | ||
bfd7ebda RV |
1359 | enum psr_lines_to_wait { |
1360 | PSR_0_LINES_TO_WAIT = 0, | |
1361 | PSR_1_LINE_TO_WAIT, | |
1362 | PSR_4_LINES_TO_WAIT, | |
1363 | PSR_8_LINES_TO_WAIT | |
83a7280e PB |
1364 | }; |
1365 | ||
41aa3448 RV |
1366 | struct intel_vbt_data { |
1367 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ | |
1368 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
1369 | ||
1370 | /* Feature bits */ | |
1371 | unsigned int int_tv_support:1; | |
1372 | unsigned int lvds_dither:1; | |
1373 | unsigned int lvds_vbt:1; | |
1374 | unsigned int int_crt_support:1; | |
1375 | unsigned int lvds_use_ssc:1; | |
1376 | unsigned int display_clock_mode:1; | |
1377 | unsigned int fdi_rx_polarity_inverted:1; | |
3e6bd011 | 1378 | unsigned int has_mipi:1; |
41aa3448 RV |
1379 | int lvds_ssc_freq; |
1380 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ | |
1381 | ||
83a7280e PB |
1382 | enum drrs_support_type drrs_type; |
1383 | ||
41aa3448 RV |
1384 | /* eDP */ |
1385 | int edp_rate; | |
1386 | int edp_lanes; | |
1387 | int edp_preemphasis; | |
1388 | int edp_vswing; | |
1389 | bool edp_initialized; | |
1390 | bool edp_support; | |
1391 | int edp_bpp; | |
1392 | struct edp_power_seq edp_pps; | |
1393 | ||
bfd7ebda RV |
1394 | struct { |
1395 | bool full_link; | |
1396 | bool require_aux_wakeup; | |
1397 | int idle_frames; | |
1398 | enum psr_lines_to_wait lines_to_wait; | |
1399 | int tp1_wakeup_time; | |
1400 | int tp2_tp3_wakeup_time; | |
1401 | } psr; | |
1402 | ||
f00076d2 JN |
1403 | struct { |
1404 | u16 pwm_freq_hz; | |
39fbc9c8 | 1405 | bool present; |
f00076d2 | 1406 | bool active_low_pwm; |
1de6068e | 1407 | u8 min_brightness; /* min_brightness/255 of max */ |
f00076d2 JN |
1408 | } backlight; |
1409 | ||
d17c5443 SK |
1410 | /* MIPI DSI */ |
1411 | struct { | |
3e6bd011 | 1412 | u16 port; |
d17c5443 | 1413 | u16 panel_id; |
d3b542fc SK |
1414 | struct mipi_config *config; |
1415 | struct mipi_pps_data *pps; | |
1416 | u8 seq_version; | |
1417 | u32 size; | |
1418 | u8 *data; | |
1419 | u8 *sequence[MIPI_SEQ_MAX]; | |
d17c5443 SK |
1420 | } dsi; |
1421 | ||
41aa3448 RV |
1422 | int crt_ddc_pin; |
1423 | ||
1424 | int child_dev_num; | |
768f69c9 | 1425 | union child_device_config *child_dev; |
6acab15a PZ |
1426 | |
1427 | struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; | |
41aa3448 RV |
1428 | }; |
1429 | ||
77c122bc VS |
1430 | enum intel_ddb_partitioning { |
1431 | INTEL_DDB_PART_1_2, | |
1432 | INTEL_DDB_PART_5_6, /* IVB+ */ | |
1433 | }; | |
1434 | ||
1fd527cc VS |
1435 | struct intel_wm_level { |
1436 | bool enable; | |
1437 | uint32_t pri_val; | |
1438 | uint32_t spr_val; | |
1439 | uint32_t cur_val; | |
1440 | uint32_t fbc_val; | |
1441 | }; | |
1442 | ||
820c1980 | 1443 | struct ilk_wm_values { |
609cedef VS |
1444 | uint32_t wm_pipe[3]; |
1445 | uint32_t wm_lp[3]; | |
1446 | uint32_t wm_lp_spr[3]; | |
1447 | uint32_t wm_linetime[3]; | |
1448 | bool enable_fbc_wm; | |
1449 | enum intel_ddb_partitioning partitioning; | |
1450 | }; | |
1451 | ||
0018fda1 | 1452 | struct vlv_wm_values { |
ae80152d VS |
1453 | struct { |
1454 | uint16_t primary; | |
1455 | uint16_t sprite[2]; | |
1456 | uint8_t cursor; | |
1457 | } pipe[3]; | |
1458 | ||
1459 | struct { | |
1460 | uint16_t plane; | |
1461 | uint8_t cursor; | |
1462 | } sr; | |
1463 | ||
0018fda1 VS |
1464 | struct { |
1465 | uint8_t cursor; | |
1466 | uint8_t sprite[2]; | |
1467 | uint8_t primary; | |
1468 | } ddl[3]; | |
1469 | }; | |
1470 | ||
c193924e | 1471 | struct skl_ddb_entry { |
16160e3d | 1472 | uint16_t start, end; /* in number of blocks, 'end' is exclusive */ |
c193924e DL |
1473 | }; |
1474 | ||
1475 | static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry) | |
1476 | { | |
16160e3d | 1477 | return entry->end - entry->start; |
c193924e DL |
1478 | } |
1479 | ||
08db6652 DL |
1480 | static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, |
1481 | const struct skl_ddb_entry *e2) | |
1482 | { | |
1483 | if (e1->start == e2->start && e1->end == e2->end) | |
1484 | return true; | |
1485 | ||
1486 | return false; | |
1487 | } | |
1488 | ||
c193924e | 1489 | struct skl_ddb_allocation { |
34bb56af | 1490 | struct skl_ddb_entry pipe[I915_MAX_PIPES]; |
2cd601c6 CK |
1491 | struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */ |
1492 | struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* y-plane */ | |
c193924e DL |
1493 | struct skl_ddb_entry cursor[I915_MAX_PIPES]; |
1494 | }; | |
1495 | ||
2ac96d2a PB |
1496 | struct skl_wm_values { |
1497 | bool dirty[I915_MAX_PIPES]; | |
c193924e | 1498 | struct skl_ddb_allocation ddb; |
2ac96d2a PB |
1499 | uint32_t wm_linetime[I915_MAX_PIPES]; |
1500 | uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8]; | |
1501 | uint32_t cursor[I915_MAX_PIPES][8]; | |
1502 | uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES]; | |
1503 | uint32_t cursor_trans[I915_MAX_PIPES]; | |
1504 | }; | |
1505 | ||
1506 | struct skl_wm_level { | |
1507 | bool plane_en[I915_MAX_PLANES]; | |
b99f58da | 1508 | bool cursor_en; |
2ac96d2a PB |
1509 | uint16_t plane_res_b[I915_MAX_PLANES]; |
1510 | uint8_t plane_res_l[I915_MAX_PLANES]; | |
2ac96d2a PB |
1511 | uint16_t cursor_res_b; |
1512 | uint8_t cursor_res_l; | |
1513 | }; | |
1514 | ||
c67a470b | 1515 | /* |
765dab67 PZ |
1516 | * This struct helps tracking the state needed for runtime PM, which puts the |
1517 | * device in PCI D3 state. Notice that when this happens, nothing on the | |
1518 | * graphics device works, even register access, so we don't get interrupts nor | |
1519 | * anything else. | |
c67a470b | 1520 | * |
765dab67 PZ |
1521 | * Every piece of our code that needs to actually touch the hardware needs to |
1522 | * either call intel_runtime_pm_get or call intel_display_power_get with the | |
1523 | * appropriate power domain. | |
a8a8bd54 | 1524 | * |
765dab67 PZ |
1525 | * Our driver uses the autosuspend delay feature, which means we'll only really |
1526 | * suspend if we stay with zero refcount for a certain amount of time. The | |
f458ebbc | 1527 | * default value is currently very conservative (see intel_runtime_pm_enable), but |
765dab67 | 1528 | * it can be changed with the standard runtime PM files from sysfs. |
c67a470b PZ |
1529 | * |
1530 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and | |
1531 | * goes back to false exactly before we reenable the IRQs. We use this variable | |
1532 | * to check if someone is trying to enable/disable IRQs while they're supposed | |
1533 | * to be disabled. This shouldn't happen and we'll print some error messages in | |
730488b2 | 1534 | * case it happens. |
c67a470b | 1535 | * |
765dab67 | 1536 | * For more, read the Documentation/power/runtime_pm.txt. |
c67a470b | 1537 | */ |
5d584b2e PZ |
1538 | struct i915_runtime_pm { |
1539 | bool suspended; | |
2aeb7d3a | 1540 | bool irqs_enabled; |
c67a470b PZ |
1541 | }; |
1542 | ||
926321d5 DV |
1543 | enum intel_pipe_crc_source { |
1544 | INTEL_PIPE_CRC_SOURCE_NONE, | |
1545 | INTEL_PIPE_CRC_SOURCE_PLANE1, | |
1546 | INTEL_PIPE_CRC_SOURCE_PLANE2, | |
1547 | INTEL_PIPE_CRC_SOURCE_PF, | |
5b3a856b | 1548 | INTEL_PIPE_CRC_SOURCE_PIPE, |
3d099a05 DV |
1549 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ |
1550 | INTEL_PIPE_CRC_SOURCE_TV, | |
1551 | INTEL_PIPE_CRC_SOURCE_DP_B, | |
1552 | INTEL_PIPE_CRC_SOURCE_DP_C, | |
1553 | INTEL_PIPE_CRC_SOURCE_DP_D, | |
46a19188 | 1554 | INTEL_PIPE_CRC_SOURCE_AUTO, |
926321d5 DV |
1555 | INTEL_PIPE_CRC_SOURCE_MAX, |
1556 | }; | |
1557 | ||
8bf1e9f1 | 1558 | struct intel_pipe_crc_entry { |
ac2300d4 | 1559 | uint32_t frame; |
8bf1e9f1 SH |
1560 | uint32_t crc[5]; |
1561 | }; | |
1562 | ||
b2c88f5b | 1563 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 |
8bf1e9f1 | 1564 | struct intel_pipe_crc { |
d538bbdf DL |
1565 | spinlock_t lock; |
1566 | bool opened; /* exclusive access to the result file */ | |
e5f75aca | 1567 | struct intel_pipe_crc_entry *entries; |
926321d5 | 1568 | enum intel_pipe_crc_source source; |
d538bbdf | 1569 | int head, tail; |
07144428 | 1570 | wait_queue_head_t wq; |
8bf1e9f1 SH |
1571 | }; |
1572 | ||
f99d7069 DV |
1573 | struct i915_frontbuffer_tracking { |
1574 | struct mutex lock; | |
1575 | ||
1576 | /* | |
1577 | * Tracking bits for delayed frontbuffer flushing du to gpu activity or | |
1578 | * scheduled flips. | |
1579 | */ | |
1580 | unsigned busy_bits; | |
1581 | unsigned flip_bits; | |
1582 | }; | |
1583 | ||
7225342a MK |
1584 | struct i915_wa_reg { |
1585 | u32 addr; | |
1586 | u32 value; | |
1587 | /* bitmask representing WA bits */ | |
1588 | u32 mask; | |
1589 | }; | |
1590 | ||
1591 | #define I915_MAX_WA_REGS 16 | |
1592 | ||
1593 | struct i915_workarounds { | |
1594 | struct i915_wa_reg reg[I915_MAX_WA_REGS]; | |
1595 | u32 count; | |
1596 | }; | |
1597 | ||
cf9d2890 YZ |
1598 | struct i915_virtual_gpu { |
1599 | bool active; | |
1600 | }; | |
1601 | ||
77fec556 | 1602 | struct drm_i915_private { |
f4c956ad | 1603 | struct drm_device *dev; |
efab6d8d | 1604 | struct kmem_cache *objects; |
e20d2ab7 | 1605 | struct kmem_cache *vmas; |
efab6d8d | 1606 | struct kmem_cache *requests; |
f4c956ad | 1607 | |
5c969aa7 | 1608 | const struct intel_device_info info; |
f4c956ad DV |
1609 | |
1610 | int relative_constants_mode; | |
1611 | ||
1612 | void __iomem *regs; | |
1613 | ||
907b28c5 | 1614 | struct intel_uncore uncore; |
f4c956ad | 1615 | |
cf9d2890 YZ |
1616 | struct i915_virtual_gpu vgpu; |
1617 | ||
eb805623 DV |
1618 | struct intel_csr csr; |
1619 | ||
1620 | /* Display CSR-related protection */ | |
1621 | struct mutex csr_lock; | |
1622 | ||
5ea6e5e3 | 1623 | struct intel_gmbus gmbus[GMBUS_NUM_PINS]; |
28c70f16 | 1624 | |
f4c956ad DV |
1625 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
1626 | * controller on different i2c buses. */ | |
1627 | struct mutex gmbus_mutex; | |
1628 | ||
1629 | /** | |
1630 | * Base address of the gmbus and gpio block. | |
1631 | */ | |
1632 | uint32_t gpio_mmio_base; | |
1633 | ||
b6fdd0f2 SS |
1634 | /* MMIO base address for MIPI regs */ |
1635 | uint32_t mipi_mmio_base; | |
1636 | ||
28c70f16 DV |
1637 | wait_queue_head_t gmbus_wait_queue; |
1638 | ||
f4c956ad | 1639 | struct pci_dev *bridge_dev; |
a4872ba6 | 1640 | struct intel_engine_cs ring[I915_NUM_RINGS]; |
3e78998a | 1641 | struct drm_i915_gem_object *semaphore_obj; |
f72b3435 | 1642 | uint32_t last_seqno, next_seqno; |
f4c956ad | 1643 | |
ba8286fa | 1644 | struct drm_dma_handle *status_page_dmah; |
f4c956ad DV |
1645 | struct resource mch_res; |
1646 | ||
f4c956ad DV |
1647 | /* protects the irq masks */ |
1648 | spinlock_t irq_lock; | |
1649 | ||
84c33a64 SG |
1650 | /* protects the mmio flip data */ |
1651 | spinlock_t mmio_flip_lock; | |
1652 | ||
f8b79e58 ID |
1653 | bool display_irqs_enabled; |
1654 | ||
9ee32fea DV |
1655 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
1656 | struct pm_qos_request pm_qos; | |
1657 | ||
f4c956ad | 1658 | /* DPIO indirect register protection */ |
09153000 | 1659 | struct mutex dpio_lock; |
f4c956ad DV |
1660 | |
1661 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
abd58f01 BW |
1662 | union { |
1663 | u32 irq_mask; | |
1664 | u32 de_irq_mask[I915_MAX_PIPES]; | |
1665 | }; | |
f4c956ad | 1666 | u32 gt_irq_mask; |
605cd25b | 1667 | u32 pm_irq_mask; |
a6706b45 | 1668 | u32 pm_rps_events; |
91d181dd | 1669 | u32 pipestat_irq_mask[I915_MAX_PIPES]; |
f4c956ad | 1670 | |
f4c956ad | 1671 | struct work_struct hotplug_work; |
b543fb04 EE |
1672 | struct { |
1673 | unsigned long hpd_last_jiffies; | |
1674 | int hpd_cnt; | |
1675 | enum { | |
1676 | HPD_ENABLED = 0, | |
1677 | HPD_DISABLED = 1, | |
1678 | HPD_MARK_DISABLED = 2 | |
1679 | } hpd_mark; | |
1680 | } hpd_stats[HPD_NUM_PINS]; | |
142e2398 | 1681 | u32 hpd_event_bits; |
6323751d | 1682 | struct delayed_work hotplug_reenable_work; |
f4c956ad | 1683 | |
5c3fe8b0 | 1684 | struct i915_fbc fbc; |
439d7ac0 | 1685 | struct i915_drrs drrs; |
f4c956ad | 1686 | struct intel_opregion opregion; |
41aa3448 | 1687 | struct intel_vbt_data vbt; |
f4c956ad | 1688 | |
d9ceb816 JB |
1689 | bool preserve_bios_swizzle; |
1690 | ||
f4c956ad DV |
1691 | /* overlay */ |
1692 | struct intel_overlay *overlay; | |
f4c956ad | 1693 | |
58c68779 | 1694 | /* backlight registers and fields in struct intel_panel */ |
07f11d49 | 1695 | struct mutex backlight_lock; |
31ad8ec6 | 1696 | |
f4c956ad | 1697 | /* LVDS info */ |
f4c956ad DV |
1698 | bool no_aux_handshake; |
1699 | ||
e39b999a VS |
1700 | /* protects panel power sequencer state */ |
1701 | struct mutex pps_mutex; | |
1702 | ||
f4c956ad DV |
1703 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
1704 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ | |
1705 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
1706 | ||
1707 | unsigned int fsb_freq, mem_freq, is_ddr3; | |
164dfd28 | 1708 | unsigned int cdclk_freq; |
6bcda4f0 | 1709 | unsigned int hpll_freq; |
f4c956ad | 1710 | |
645416f5 DV |
1711 | /** |
1712 | * wq - Driver workqueue for GEM. | |
1713 | * | |
1714 | * NOTE: Work items scheduled here are not allowed to grab any modeset | |
1715 | * locks, for otherwise the flushing done in the pageflip code will | |
1716 | * result in deadlocks. | |
1717 | */ | |
f4c956ad DV |
1718 | struct workqueue_struct *wq; |
1719 | ||
1720 | /* Display functions */ | |
1721 | struct drm_i915_display_funcs display; | |
1722 | ||
1723 | /* PCH chipset type */ | |
1724 | enum intel_pch pch_type; | |
17a303ec | 1725 | unsigned short pch_id; |
f4c956ad DV |
1726 | |
1727 | unsigned long quirks; | |
1728 | ||
b8efb17b ZR |
1729 | enum modeset_restore modeset_restore; |
1730 | struct mutex modeset_restore_lock; | |
673a394b | 1731 | |
a7bbbd63 | 1732 | struct list_head vm_list; /* Global list of all address spaces */ |
0260c420 | 1733 | struct i915_gtt gtt; /* VM representing the global address space */ |
5d4545ae | 1734 | |
4b5aed62 | 1735 | struct i915_gem_mm mm; |
ad46cb53 CW |
1736 | DECLARE_HASHTABLE(mm_structs, 7); |
1737 | struct mutex mm_lock; | |
8781342d | 1738 | |
8781342d DV |
1739 | /* Kernel Modesetting */ |
1740 | ||
9b9d172d | 1741 | struct sdvo_device_mapping sdvo_mappings[2]; |
652c393a | 1742 | |
76c4ac04 DL |
1743 | struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; |
1744 | struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; | |
6b95a207 KH |
1745 | wait_queue_head_t pending_flip_queue; |
1746 | ||
c4597872 DV |
1747 | #ifdef CONFIG_DEBUG_FS |
1748 | struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; | |
1749 | #endif | |
1750 | ||
e72f9fbf DV |
1751 | int num_shared_dpll; |
1752 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; | |
e4607fcf | 1753 | int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; |
ee7b9f93 | 1754 | |
7225342a | 1755 | struct i915_workarounds workarounds; |
888b5995 | 1756 | |
652c393a JB |
1757 | /* Reclocking support */ |
1758 | bool render_reclock_avail; | |
1759 | bool lvds_downclock_avail; | |
18f9ed12 ZY |
1760 | /* indicates the reduced downclock for LVDS*/ |
1761 | int lvds_downclock; | |
f99d7069 DV |
1762 | |
1763 | struct i915_frontbuffer_tracking fb_tracking; | |
1764 | ||
652c393a | 1765 | u16 orig_clock; |
f97108d1 | 1766 | |
c4804411 | 1767 | bool mchbar_need_disable; |
f97108d1 | 1768 | |
a4da4fa4 DV |
1769 | struct intel_l3_parity l3_parity; |
1770 | ||
59124506 BW |
1771 | /* Cannot be determined by PCIID. You must always read a register. */ |
1772 | size_t ellc_size; | |
1773 | ||
c6a828d3 | 1774 | /* gen6+ rps state */ |
c85aa885 | 1775 | struct intel_gen6_power_mgmt rps; |
c6a828d3 | 1776 | |
20e4d407 DV |
1777 | /* ilk-only ips/rps state. Everything in here is protected by the global |
1778 | * mchdev_lock in intel_pm.c */ | |
c85aa885 | 1779 | struct intel_ilk_power_mgmt ips; |
b5e50c3f | 1780 | |
83c00f55 | 1781 | struct i915_power_domains power_domains; |
a38911a3 | 1782 | |
a031d709 | 1783 | struct i915_psr psr; |
3f51e471 | 1784 | |
99584db3 | 1785 | struct i915_gpu_error gpu_error; |
ae681d96 | 1786 | |
c9cddffc JB |
1787 | struct drm_i915_gem_object *vlv_pctx; |
1788 | ||
4520f53a | 1789 | #ifdef CONFIG_DRM_I915_FBDEV |
8be48d92 DA |
1790 | /* list of fbdev register on this device */ |
1791 | struct intel_fbdev *fbdev; | |
82e3b8c1 | 1792 | struct work_struct fbdev_suspend_work; |
4520f53a | 1793 | #endif |
e953fd7b CW |
1794 | |
1795 | struct drm_property *broadcast_rgb_property; | |
3f43c48d | 1796 | struct drm_property *force_audio_property; |
e3689190 | 1797 | |
58fddc28 ID |
1798 | /* hda/i915 audio component */ |
1799 | bool audio_component_registered; | |
1800 | ||
254f965c | 1801 | uint32_t hw_context_size; |
a33afea5 | 1802 | struct list_head context_list; |
f4c956ad | 1803 | |
3e68320e | 1804 | u32 fdi_rx_config; |
68d18ad7 | 1805 | |
70722468 VS |
1806 | u32 chv_phy_control; |
1807 | ||
842f1c8b | 1808 | u32 suspend_count; |
f4c956ad | 1809 | struct i915_suspend_saved_registers regfile; |
ddeea5b0 | 1810 | struct vlv_s0ix_state vlv_s0ix_state; |
231f42a4 | 1811 | |
53615a5e VS |
1812 | struct { |
1813 | /* | |
1814 | * Raw watermark latency values: | |
1815 | * in 0.1us units for WM0, | |
1816 | * in 0.5us units for WM1+. | |
1817 | */ | |
1818 | /* primary */ | |
1819 | uint16_t pri_latency[5]; | |
1820 | /* sprite */ | |
1821 | uint16_t spr_latency[5]; | |
1822 | /* cursor */ | |
1823 | uint16_t cur_latency[5]; | |
2af30a5c PB |
1824 | /* |
1825 | * Raw watermark memory latency values | |
1826 | * for SKL for all 8 levels | |
1827 | * in 1us units. | |
1828 | */ | |
1829 | uint16_t skl_latency[8]; | |
609cedef | 1830 | |
2d41c0b5 PB |
1831 | /* |
1832 | * The skl_wm_values structure is a bit too big for stack | |
1833 | * allocation, so we keep the staging struct where we store | |
1834 | * intermediate results here instead. | |
1835 | */ | |
1836 | struct skl_wm_values skl_results; | |
1837 | ||
609cedef | 1838 | /* current hardware state */ |
2d41c0b5 PB |
1839 | union { |
1840 | struct ilk_wm_values hw; | |
1841 | struct skl_wm_values skl_hw; | |
0018fda1 | 1842 | struct vlv_wm_values vlv; |
2d41c0b5 | 1843 | }; |
53615a5e VS |
1844 | } wm; |
1845 | ||
8a187455 PZ |
1846 | struct i915_runtime_pm pm; |
1847 | ||
13cf5504 DA |
1848 | struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS]; |
1849 | u32 long_hpd_port_mask; | |
1850 | u32 short_hpd_port_mask; | |
1851 | struct work_struct dig_port_work; | |
1852 | ||
0e32b39c DA |
1853 | /* |
1854 | * if we get a HPD irq from DP and a HPD irq from non-DP | |
1855 | * the non-DP HPD could block the workqueue on a mode config | |
1856 | * mutex getting, that userspace may have taken. However | |
1857 | * userspace is waiting on the DP workqueue to run which is | |
1858 | * blocked behind the non-DP one. | |
1859 | */ | |
1860 | struct workqueue_struct *dp_wq; | |
1861 | ||
a83014d3 OM |
1862 | /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ |
1863 | struct { | |
f3dc74c0 JH |
1864 | int (*execbuf_submit)(struct drm_device *dev, struct drm_file *file, |
1865 | struct intel_engine_cs *ring, | |
1866 | struct intel_context *ctx, | |
1867 | struct drm_i915_gem_execbuffer2 *args, | |
1868 | struct list_head *vmas, | |
1869 | struct drm_i915_gem_object *batch_obj, | |
1870 | u64 exec_start, u32 flags); | |
a83014d3 OM |
1871 | int (*init_rings)(struct drm_device *dev); |
1872 | void (*cleanup_ring)(struct intel_engine_cs *ring); | |
1873 | void (*stop_ring)(struct intel_engine_cs *ring); | |
1874 | } gt; | |
1875 | ||
9e458034 SJ |
1876 | bool edp_low_vswing; |
1877 | ||
bdf1e7e3 DV |
1878 | /* |
1879 | * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch | |
1880 | * will be rejected. Instead look for a better place. | |
1881 | */ | |
77fec556 | 1882 | }; |
1da177e4 | 1883 | |
2c1792a1 CW |
1884 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) |
1885 | { | |
1886 | return dev->dev_private; | |
1887 | } | |
1888 | ||
888d0d42 ID |
1889 | static inline struct drm_i915_private *dev_to_i915(struct device *dev) |
1890 | { | |
1891 | return to_i915(dev_get_drvdata(dev)); | |
1892 | } | |
1893 | ||
b4519513 CW |
1894 | /* Iterate over initialised rings */ |
1895 | #define for_each_ring(ring__, dev_priv__, i__) \ | |
1896 | for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ | |
1897 | if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) | |
1898 | ||
b1d7e4b4 WF |
1899 | enum hdmi_force_audio { |
1900 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
1901 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
1902 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
1903 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
1904 | }; | |
1905 | ||
190d6cd5 | 1906 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
ed2f3452 | 1907 | |
37e680a1 CW |
1908 | struct drm_i915_gem_object_ops { |
1909 | /* Interface between the GEM object and its backing storage. | |
1910 | * get_pages() is called once prior to the use of the associated set | |
1911 | * of pages before to binding them into the GTT, and put_pages() is | |
1912 | * called after we no longer need them. As we expect there to be | |
1913 | * associated cost with migrating pages between the backing storage | |
1914 | * and making them available for the GPU (e.g. clflush), we may hold | |
1915 | * onto the pages after they are no longer referenced by the GPU | |
1916 | * in case they may be used again shortly (for example migrating the | |
1917 | * pages to a different memory domain within the GTT). put_pages() | |
1918 | * will therefore most likely be called when the object itself is | |
1919 | * being released or under memory pressure (where we attempt to | |
1920 | * reap pages for the shrinker). | |
1921 | */ | |
1922 | int (*get_pages)(struct drm_i915_gem_object *); | |
1923 | void (*put_pages)(struct drm_i915_gem_object *); | |
5cc9ed4b CW |
1924 | int (*dmabuf_export)(struct drm_i915_gem_object *); |
1925 | void (*release)(struct drm_i915_gem_object *); | |
37e680a1 CW |
1926 | }; |
1927 | ||
a071fa00 DV |
1928 | /* |
1929 | * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is | |
1930 | * considered to be the frontbuffer for the given plane interface-vise. This | |
1931 | * doesn't mean that the hw necessarily already scans it out, but that any | |
1932 | * rendering (by the cpu or gpu) will land in the frontbuffer eventually. | |
1933 | * | |
1934 | * We have one bit per pipe and per scanout plane type. | |
1935 | */ | |
1936 | #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4 | |
1937 | #define INTEL_FRONTBUFFER_BITS \ | |
1938 | (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES) | |
1939 | #define INTEL_FRONTBUFFER_PRIMARY(pipe) \ | |
1940 | (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) | |
1941 | #define INTEL_FRONTBUFFER_CURSOR(pipe) \ | |
1942 | (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
1943 | #define INTEL_FRONTBUFFER_SPRITE(pipe) \ | |
1944 | (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
1945 | #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ | |
1946 | (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
cc36513c DV |
1947 | #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ |
1948 | (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) | |
a071fa00 | 1949 | |
673a394b | 1950 | struct drm_i915_gem_object { |
c397b908 | 1951 | struct drm_gem_object base; |
673a394b | 1952 | |
37e680a1 CW |
1953 | const struct drm_i915_gem_object_ops *ops; |
1954 | ||
2f633156 BW |
1955 | /** List of VMAs backed by this object */ |
1956 | struct list_head vma_list; | |
1957 | ||
c1ad11fc CW |
1958 | /** Stolen memory for this object, instead of being backed by shmem. */ |
1959 | struct drm_mm_node *stolen; | |
35c20a60 | 1960 | struct list_head global_list; |
673a394b | 1961 | |
b4716185 | 1962 | struct list_head ring_list[I915_NUM_RINGS]; |
b25cb2f8 BW |
1963 | /** Used in execbuf to temporarily hold a ref */ |
1964 | struct list_head obj_exec_link; | |
673a394b | 1965 | |
8d9d5744 | 1966 | struct list_head batch_pool_link; |
493018dc | 1967 | |
673a394b | 1968 | /** |
65ce3027 CW |
1969 | * This is set if the object is on the active lists (has pending |
1970 | * rendering and so a non-zero seqno), and is not set if it i s on | |
1971 | * inactive (ready to be unbound) list. | |
673a394b | 1972 | */ |
b4716185 | 1973 | unsigned int active:I915_NUM_RINGS; |
673a394b EA |
1974 | |
1975 | /** | |
1976 | * This is set if the object has been written to since last bound | |
1977 | * to the GTT | |
1978 | */ | |
0206e353 | 1979 | unsigned int dirty:1; |
778c3544 DV |
1980 | |
1981 | /** | |
1982 | * Fence register bits (if any) for this object. Will be set | |
1983 | * as needed when mapped into the GTT. | |
1984 | * Protected by dev->struct_mutex. | |
778c3544 | 1985 | */ |
4b9de737 | 1986 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
778c3544 | 1987 | |
778c3544 DV |
1988 | /** |
1989 | * Advice: are the backing pages purgeable? | |
1990 | */ | |
0206e353 | 1991 | unsigned int madv:2; |
778c3544 | 1992 | |
778c3544 DV |
1993 | /** |
1994 | * Current tiling mode for the object. | |
1995 | */ | |
0206e353 | 1996 | unsigned int tiling_mode:2; |
5d82e3e6 CW |
1997 | /** |
1998 | * Whether the tiling parameters for the currently associated fence | |
1999 | * register have changed. Note that for the purposes of tracking | |
2000 | * tiling changes we also treat the unfenced register, the register | |
2001 | * slot that the object occupies whilst it executes a fenced | |
2002 | * command (such as BLT on gen2/3), as a "fence". | |
2003 | */ | |
2004 | unsigned int fence_dirty:1; | |
778c3544 | 2005 | |
75e9e915 DV |
2006 | /** |
2007 | * Is the object at the current location in the gtt mappable and | |
2008 | * fenceable? Used to avoid costly recalculations. | |
2009 | */ | |
0206e353 | 2010 | unsigned int map_and_fenceable:1; |
75e9e915 | 2011 | |
fb7d516a DV |
2012 | /** |
2013 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
2014 | * mappable by accident). Track pin and fault separate for a more | |
2015 | * accurate mappable working set. | |
2016 | */ | |
0206e353 | 2017 | unsigned int fault_mappable:1; |
fb7d516a | 2018 | |
24f3a8cf AG |
2019 | /* |
2020 | * Is the object to be mapped as read-only to the GPU | |
2021 | * Only honoured if hardware has relevant pte bit | |
2022 | */ | |
2023 | unsigned long gt_ro:1; | |
651d794f | 2024 | unsigned int cache_level:3; |
0f71979a | 2025 | unsigned int cache_dirty:1; |
93dfb40c | 2026 | |
9da3da66 | 2027 | unsigned int has_dma_mapping:1; |
7bddb01f | 2028 | |
a071fa00 DV |
2029 | unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS; |
2030 | ||
8a0c39b1 TU |
2031 | unsigned int pin_display; |
2032 | ||
9da3da66 | 2033 | struct sg_table *pages; |
a5570178 | 2034 | int pages_pin_count; |
ee286370 CW |
2035 | struct get_page { |
2036 | struct scatterlist *sg; | |
2037 | int last; | |
2038 | } get_page; | |
673a394b | 2039 | |
1286ff73 | 2040 | /* prime dma-buf support */ |
9a70cc2a DA |
2041 | void *dma_buf_vmapping; |
2042 | int vmapping_count; | |
2043 | ||
b4716185 CW |
2044 | /** Breadcrumb of last rendering to the buffer. |
2045 | * There can only be one writer, but we allow for multiple readers. | |
2046 | * If there is a writer that necessarily implies that all other | |
2047 | * read requests are complete - but we may only be lazily clearing | |
2048 | * the read requests. A read request is naturally the most recent | |
2049 | * request on a ring, so we may have two different write and read | |
2050 | * requests on one ring where the write request is older than the | |
2051 | * read request. This allows for the CPU to read from an active | |
2052 | * buffer by only waiting for the write to complete. | |
2053 | * */ | |
2054 | struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS]; | |
97b2a6a1 | 2055 | struct drm_i915_gem_request *last_write_req; |
caea7476 | 2056 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
97b2a6a1 | 2057 | struct drm_i915_gem_request *last_fenced_req; |
673a394b | 2058 | |
778c3544 | 2059 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 2060 | uint32_t stride; |
673a394b | 2061 | |
80075d49 DV |
2062 | /** References from framebuffers, locks out tiling changes. */ |
2063 | unsigned long framebuffer_references; | |
2064 | ||
280b713b | 2065 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 2066 | unsigned long *bit_17; |
280b713b | 2067 | |
5cc9ed4b | 2068 | union { |
6a2c4232 CW |
2069 | /** for phy allocated objects */ |
2070 | struct drm_dma_handle *phys_handle; | |
2071 | ||
5cc9ed4b CW |
2072 | struct i915_gem_userptr { |
2073 | uintptr_t ptr; | |
2074 | unsigned read_only :1; | |
2075 | unsigned workers :4; | |
2076 | #define I915_GEM_USERPTR_MAX_WORKERS 15 | |
2077 | ||
ad46cb53 CW |
2078 | struct i915_mm_struct *mm; |
2079 | struct i915_mmu_object *mmu_object; | |
5cc9ed4b CW |
2080 | struct work_struct *work; |
2081 | } userptr; | |
2082 | }; | |
2083 | }; | |
62b8b215 | 2084 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 2085 | |
a071fa00 DV |
2086 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
2087 | struct drm_i915_gem_object *new, | |
2088 | unsigned frontbuffer_bits); | |
2089 | ||
673a394b EA |
2090 | /** |
2091 | * Request queue structure. | |
2092 | * | |
2093 | * The request queue allows us to note sequence numbers that have been emitted | |
2094 | * and may be associated with active buffers to be retired. | |
2095 | * | |
97b2a6a1 JH |
2096 | * By keeping this list, we can avoid having to do questionable sequence |
2097 | * number comparisons on buffer last_read|write_seqno. It also allows an | |
2098 | * emission time to be associated with the request for tracking how far ahead | |
2099 | * of the GPU the submission is. | |
b3a38998 NH |
2100 | * |
2101 | * The requests are reference counted, so upon creation they should have an | |
2102 | * initial reference taken using kref_init | |
673a394b EA |
2103 | */ |
2104 | struct drm_i915_gem_request { | |
abfe262a JH |
2105 | struct kref ref; |
2106 | ||
852835f3 | 2107 | /** On Which ring this request was generated */ |
efab6d8d | 2108 | struct drm_i915_private *i915; |
a4872ba6 | 2109 | struct intel_engine_cs *ring; |
852835f3 | 2110 | |
673a394b EA |
2111 | /** GEM sequence number associated with this request. */ |
2112 | uint32_t seqno; | |
2113 | ||
7d736f4f MK |
2114 | /** Position in the ringbuffer of the start of the request */ |
2115 | u32 head; | |
2116 | ||
72f95afa NH |
2117 | /** |
2118 | * Position in the ringbuffer of the start of the postfix. | |
2119 | * This is required to calculate the maximum available ringbuffer | |
2120 | * space without overwriting the postfix. | |
2121 | */ | |
2122 | u32 postfix; | |
2123 | ||
2124 | /** Position in the ringbuffer of the end of the whole request */ | |
a71d8d94 CW |
2125 | u32 tail; |
2126 | ||
b3a38998 | 2127 | /** |
a8c6ecb3 | 2128 | * Context and ring buffer related to this request |
b3a38998 NH |
2129 | * Contexts are refcounted, so when this request is associated with a |
2130 | * context, we must increment the context's refcount, to guarantee that | |
2131 | * it persists while any request is linked to it. Requests themselves | |
2132 | * are also refcounted, so the request will only be freed when the last | |
2133 | * reference to it is dismissed, and the code in | |
2134 | * i915_gem_request_free() will then decrement the refcount on the | |
2135 | * context. | |
2136 | */ | |
273497e5 | 2137 | struct intel_context *ctx; |
98e1bd4a | 2138 | struct intel_ringbuffer *ringbuf; |
0e50e96b | 2139 | |
7d736f4f MK |
2140 | /** Batch buffer related to this request if any */ |
2141 | struct drm_i915_gem_object *batch_obj; | |
2142 | ||
673a394b EA |
2143 | /** Time at which this request was emitted, in jiffies. */ |
2144 | unsigned long emitted_jiffies; | |
2145 | ||
b962442e | 2146 | /** global list entry for this request */ |
673a394b | 2147 | struct list_head list; |
b962442e | 2148 | |
f787a5f5 | 2149 | struct drm_i915_file_private *file_priv; |
b962442e EA |
2150 | /** file_priv list entry for this request */ |
2151 | struct list_head client_list; | |
67e2937b | 2152 | |
071c92de MK |
2153 | /** process identifier submitting this request */ |
2154 | struct pid *pid; | |
2155 | ||
6d3d8274 NH |
2156 | /** |
2157 | * The ELSP only accepts two elements at a time, so we queue | |
2158 | * context/tail pairs on a given queue (ring->execlist_queue) until the | |
2159 | * hardware is available. The queue serves a double purpose: we also use | |
2160 | * it to keep track of the up to 2 contexts currently in the hardware | |
2161 | * (usually one in execution and the other queued up by the GPU): We | |
2162 | * only remove elements from the head of the queue when the hardware | |
2163 | * informs us that an element has been completed. | |
2164 | * | |
2165 | * All accesses to the queue are mediated by a spinlock | |
2166 | * (ring->execlist_lock). | |
2167 | */ | |
2168 | ||
2169 | /** Execlist link in the submission queue.*/ | |
2170 | struct list_head execlist_link; | |
2171 | ||
2172 | /** Execlists no. of times this request has been sent to the ELSP */ | |
2173 | int elsp_submitted; | |
2174 | ||
673a394b EA |
2175 | }; |
2176 | ||
6689cb2b JH |
2177 | int i915_gem_request_alloc(struct intel_engine_cs *ring, |
2178 | struct intel_context *ctx); | |
abfe262a JH |
2179 | void i915_gem_request_free(struct kref *req_ref); |
2180 | ||
b793a00a JH |
2181 | static inline uint32_t |
2182 | i915_gem_request_get_seqno(struct drm_i915_gem_request *req) | |
2183 | { | |
2184 | return req ? req->seqno : 0; | |
2185 | } | |
2186 | ||
2187 | static inline struct intel_engine_cs * | |
2188 | i915_gem_request_get_ring(struct drm_i915_gem_request *req) | |
2189 | { | |
2190 | return req ? req->ring : NULL; | |
2191 | } | |
2192 | ||
b2cfe0ab | 2193 | static inline struct drm_i915_gem_request * |
abfe262a JH |
2194 | i915_gem_request_reference(struct drm_i915_gem_request *req) |
2195 | { | |
b2cfe0ab CW |
2196 | if (req) |
2197 | kref_get(&req->ref); | |
2198 | return req; | |
abfe262a JH |
2199 | } |
2200 | ||
2201 | static inline void | |
2202 | i915_gem_request_unreference(struct drm_i915_gem_request *req) | |
2203 | { | |
f245860e | 2204 | WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex)); |
abfe262a JH |
2205 | kref_put(&req->ref, i915_gem_request_free); |
2206 | } | |
2207 | ||
41037f9f CW |
2208 | static inline void |
2209 | i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req) | |
2210 | { | |
b833bb61 ML |
2211 | struct drm_device *dev; |
2212 | ||
2213 | if (!req) | |
2214 | return; | |
41037f9f | 2215 | |
b833bb61 ML |
2216 | dev = req->ring->dev; |
2217 | if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex)) | |
41037f9f | 2218 | mutex_unlock(&dev->struct_mutex); |
41037f9f CW |
2219 | } |
2220 | ||
abfe262a JH |
2221 | static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst, |
2222 | struct drm_i915_gem_request *src) | |
2223 | { | |
2224 | if (src) | |
2225 | i915_gem_request_reference(src); | |
2226 | ||
2227 | if (*pdst) | |
2228 | i915_gem_request_unreference(*pdst); | |
2229 | ||
2230 | *pdst = src; | |
2231 | } | |
2232 | ||
1b5a433a JH |
2233 | /* |
2234 | * XXX: i915_gem_request_completed should be here but currently needs the | |
2235 | * definition of i915_seqno_passed() which is below. It will be moved in | |
2236 | * a later patch when the call to i915_seqno_passed() is obsoleted... | |
2237 | */ | |
2238 | ||
351e3db2 BV |
2239 | /* |
2240 | * A command that requires special handling by the command parser. | |
2241 | */ | |
2242 | struct drm_i915_cmd_descriptor { | |
2243 | /* | |
2244 | * Flags describing how the command parser processes the command. | |
2245 | * | |
2246 | * CMD_DESC_FIXED: The command has a fixed length if this is set, | |
2247 | * a length mask if not set | |
2248 | * CMD_DESC_SKIP: The command is allowed but does not follow the | |
2249 | * standard length encoding for the opcode range in | |
2250 | * which it falls | |
2251 | * CMD_DESC_REJECT: The command is never allowed | |
2252 | * CMD_DESC_REGISTER: The command should be checked against the | |
2253 | * register whitelist for the appropriate ring | |
2254 | * CMD_DESC_MASTER: The command is allowed if the submitting process | |
2255 | * is the DRM master | |
2256 | */ | |
2257 | u32 flags; | |
2258 | #define CMD_DESC_FIXED (1<<0) | |
2259 | #define CMD_DESC_SKIP (1<<1) | |
2260 | #define CMD_DESC_REJECT (1<<2) | |
2261 | #define CMD_DESC_REGISTER (1<<3) | |
2262 | #define CMD_DESC_BITMASK (1<<4) | |
2263 | #define CMD_DESC_MASTER (1<<5) | |
2264 | ||
2265 | /* | |
2266 | * The command's unique identification bits and the bitmask to get them. | |
2267 | * This isn't strictly the opcode field as defined in the spec and may | |
2268 | * also include type, subtype, and/or subop fields. | |
2269 | */ | |
2270 | struct { | |
2271 | u32 value; | |
2272 | u32 mask; | |
2273 | } cmd; | |
2274 | ||
2275 | /* | |
2276 | * The command's length. The command is either fixed length (i.e. does | |
2277 | * not include a length field) or has a length field mask. The flag | |
2278 | * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has | |
2279 | * a length mask. All command entries in a command table must include | |
2280 | * length information. | |
2281 | */ | |
2282 | union { | |
2283 | u32 fixed; | |
2284 | u32 mask; | |
2285 | } length; | |
2286 | ||
2287 | /* | |
2288 | * Describes where to find a register address in the command to check | |
2289 | * against the ring's register whitelist. Only valid if flags has the | |
2290 | * CMD_DESC_REGISTER bit set. | |
2291 | */ | |
2292 | struct { | |
2293 | u32 offset; | |
2294 | u32 mask; | |
2295 | } reg; | |
2296 | ||
2297 | #define MAX_CMD_DESC_BITMASKS 3 | |
2298 | /* | |
2299 | * Describes command checks where a particular dword is masked and | |
2300 | * compared against an expected value. If the command does not match | |
2301 | * the expected value, the parser rejects it. Only valid if flags has | |
2302 | * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero | |
2303 | * are valid. | |
d4d48035 BV |
2304 | * |
2305 | * If the check specifies a non-zero condition_mask then the parser | |
2306 | * only performs the check when the bits specified by condition_mask | |
2307 | * are non-zero. | |
351e3db2 BV |
2308 | */ |
2309 | struct { | |
2310 | u32 offset; | |
2311 | u32 mask; | |
2312 | u32 expected; | |
d4d48035 BV |
2313 | u32 condition_offset; |
2314 | u32 condition_mask; | |
351e3db2 BV |
2315 | } bits[MAX_CMD_DESC_BITMASKS]; |
2316 | }; | |
2317 | ||
2318 | /* | |
2319 | * A table of commands requiring special handling by the command parser. | |
2320 | * | |
2321 | * Each ring has an array of tables. Each table consists of an array of command | |
2322 | * descriptors, which must be sorted with command opcodes in ascending order. | |
2323 | */ | |
2324 | struct drm_i915_cmd_table { | |
2325 | const struct drm_i915_cmd_descriptor *table; | |
2326 | int count; | |
2327 | }; | |
2328 | ||
dbbe9127 | 2329 | /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */ |
7312e2dd CW |
2330 | #define __I915__(p) ({ \ |
2331 | struct drm_i915_private *__p; \ | |
2332 | if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \ | |
2333 | __p = (struct drm_i915_private *)p; \ | |
2334 | else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \ | |
2335 | __p = to_i915((struct drm_device *)p); \ | |
2336 | else \ | |
2337 | BUILD_BUG(); \ | |
2338 | __p; \ | |
2339 | }) | |
dbbe9127 | 2340 | #define INTEL_INFO(p) (&__I915__(p)->info) |
87f1f465 | 2341 | #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id) |
e90a21d4 | 2342 | #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision) |
cae5852d | 2343 | |
87f1f465 CW |
2344 | #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577) |
2345 | #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562) | |
cae5852d | 2346 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
87f1f465 | 2347 | #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572) |
cae5852d | 2348 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
87f1f465 CW |
2349 | #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592) |
2350 | #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772) | |
cae5852d ZN |
2351 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
2352 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
2353 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
87f1f465 | 2354 | #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42) |
cae5852d | 2355 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
87f1f465 CW |
2356 | #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001) |
2357 | #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011) | |
cae5852d ZN |
2358 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
2359 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
87f1f465 | 2360 | #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046) |
4b65177b | 2361 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
87f1f465 CW |
2362 | #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \ |
2363 | INTEL_DEVID(dev) == 0x0152 || \ | |
2364 | INTEL_DEVID(dev) == 0x015a) | |
70a3eb7a | 2365 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
6df4027b | 2366 | #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) |
4cae9ae0 | 2367 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
8179f1f0 | 2368 | #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) |
7201c0b3 | 2369 | #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake) |
1feed885 | 2370 | #define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev)) |
cae5852d | 2371 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
ed1c9e2c | 2372 | #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2373 | (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) |
5dd8c4c3 | 2374 | #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ |
6b96d705 | 2375 | ((INTEL_DEVID(dev) & 0xf) == 0x6 || \ |
0dc6f20b | 2376 | (INTEL_DEVID(dev) & 0xf) == 0xb || \ |
87f1f465 | 2377 | (INTEL_DEVID(dev) & 0xf) == 0xe)) |
a0fcbd95 RV |
2378 | #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \ |
2379 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) | |
5dd8c4c3 | 2380 | #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2381 | (INTEL_DEVID(dev) & 0xFF00) == 0x0A00) |
9435373e | 2382 | #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2383 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) |
9bbfd20a | 2384 | /* ULX machines are also considered ULT. */ |
87f1f465 CW |
2385 | #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \ |
2386 | INTEL_DEVID(dev) == 0x0A1E) | |
b833d685 | 2387 | #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) |
cae5852d | 2388 | |
e90a21d4 HN |
2389 | #define SKL_REVID_A0 (0x0) |
2390 | #define SKL_REVID_B0 (0x1) | |
2391 | #define SKL_REVID_C0 (0x2) | |
2392 | #define SKL_REVID_D0 (0x3) | |
8bc0ccf6 | 2393 | #define SKL_REVID_E0 (0x4) |
b88baa2a | 2394 | #define SKL_REVID_F0 (0x5) |
e90a21d4 | 2395 | |
6c74c87f NH |
2396 | #define BXT_REVID_A0 (0x0) |
2397 | #define BXT_REVID_B0 (0x3) | |
2398 | #define BXT_REVID_C0 (0x6) | |
2399 | ||
85436696 JB |
2400 | /* |
2401 | * The genX designation typically refers to the render engine, so render | |
2402 | * capability related checks should use IS_GEN, while display and other checks | |
2403 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
2404 | * chips, etc.). | |
2405 | */ | |
cae5852d ZN |
2406 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
2407 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) | |
2408 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) | |
2409 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) | |
2410 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) | |
85436696 | 2411 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
d2980845 | 2412 | #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8) |
b71252dc | 2413 | #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9) |
cae5852d | 2414 | |
73ae478c BW |
2415 | #define RENDER_RING (1<<RCS) |
2416 | #define BSD_RING (1<<VCS) | |
2417 | #define BLT_RING (1<<BCS) | |
2418 | #define VEBOX_RING (1<<VECS) | |
845f74a7 | 2419 | #define BSD2_RING (1<<VCS2) |
63c42e56 | 2420 | #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) |
845f74a7 | 2421 | #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING) |
63c42e56 BW |
2422 | #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) |
2423 | #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) | |
2424 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) | |
2425 | #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ | |
f2fbc690 | 2426 | __I915__(dev)->ellc_size) |
cae5852d ZN |
2427 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
2428 | ||
254f965c | 2429 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
d7f621e5 | 2430 | #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8) |
692ef70c JB |
2431 | #define USES_PPGTT(dev) (i915.enable_ppgtt) |
2432 | #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2) | |
1d2a314c | 2433 | |
05394f39 | 2434 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
cae5852d ZN |
2435 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
2436 | ||
b45305fc DV |
2437 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
2438 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) | |
4e6b788c DV |
2439 | /* |
2440 | * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts | |
2441 | * even when in MSI mode. This results in spurious interrupt warnings if the | |
2442 | * legacy irq no. is shared with another device. The kernel then disables that | |
2443 | * interrupt source and so prevents the other device from working properly. | |
2444 | */ | |
2445 | #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
2446 | #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
b45305fc | 2447 | |
cae5852d ZN |
2448 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
2449 | * rows, which changed the alignment requirements and fence programming. | |
2450 | */ | |
2451 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
2452 | IS_I915GM(dev))) | |
2453 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) | |
2454 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
2455 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
cae5852d ZN |
2456 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
2457 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
cae5852d ZN |
2458 | |
2459 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
2460 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
3a77c4c4 | 2461 | #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
cae5852d | 2462 | |
dbf7786e | 2463 | #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev)) |
f5adf94e | 2464 | |
0c9b3715 JN |
2465 | #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ |
2466 | INTEL_INFO(dev)->gen >= 9) | |
2467 | ||
dd93be58 | 2468 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) |
30568c45 | 2469 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) |
b32c6f48 | 2470 | #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ |
e3d99845 SJ |
2471 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \ |
2472 | IS_SKYLAKE(dev)) | |
6157d3c8 | 2473 | #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ |
00776511 SS |
2474 | IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \ |
2475 | IS_SKYLAKE(dev)) | |
58abf1da RV |
2476 | #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) |
2477 | #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev)) | |
affa9354 | 2478 | |
eb805623 DV |
2479 | #define HAS_CSR(dev) (IS_SKYLAKE(dev)) |
2480 | ||
17a303ec PZ |
2481 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
2482 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 | |
2483 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
2484 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 | |
2485 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 | |
2486 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 | |
e7e7ea20 S |
2487 | #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 |
2488 | #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 | |
17a303ec | 2489 | |
f2fbc690 | 2490 | #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type) |
e7e7ea20 | 2491 | #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT) |
eb877ebf | 2492 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
cae5852d ZN |
2493 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
2494 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
40c7ead9 | 2495 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
45e6e3a1 | 2496 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
cae5852d | 2497 | |
5fafe292 SJ |
2498 | #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)) |
2499 | ||
040d2baa BW |
2500 | /* DPF == dynamic parity feature */ |
2501 | #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
2502 | #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) | |
e1ef7cc2 | 2503 | |
c8735b0c | 2504 | #define GT_FREQUENCY_MULTIPLIER 50 |
de43ae9d | 2505 | #define GEN9_FREQ_SCALER 3 |
c8735b0c | 2506 | |
05394f39 CW |
2507 | #include "i915_trace.h" |
2508 | ||
baa70943 | 2509 | extern const struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 DA |
2510 | extern int i915_max_ioctl; |
2511 | ||
fc49b3da ID |
2512 | extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state); |
2513 | extern int i915_resume_legacy(struct drm_device *dev); | |
7c1c2871 | 2514 | |
d330a953 JN |
2515 | /* i915_params.c */ |
2516 | struct i915_params { | |
2517 | int modeset; | |
2518 | int panel_ignore_lid; | |
d330a953 JN |
2519 | int semaphores; |
2520 | unsigned int lvds_downclock; | |
2521 | int lvds_channel_mode; | |
2522 | int panel_use_ssc; | |
2523 | int vbt_sdvo_panel_type; | |
2524 | int enable_rc6; | |
2525 | int enable_fbc; | |
d330a953 | 2526 | int enable_ppgtt; |
127f1003 | 2527 | int enable_execlists; |
d330a953 JN |
2528 | int enable_psr; |
2529 | unsigned int preliminary_hw_support; | |
2530 | int disable_power_well; | |
2531 | int enable_ips; | |
e5aa6541 | 2532 | int invert_brightness; |
351e3db2 | 2533 | int enable_cmd_parser; |
e5aa6541 DL |
2534 | /* leave bools at the end to not create holes */ |
2535 | bool enable_hangcheck; | |
2536 | bool fastboot; | |
d330a953 | 2537 | bool prefault_disable; |
5bedeb2d | 2538 | bool load_detect_test; |
d330a953 | 2539 | bool reset; |
a0bae57f | 2540 | bool disable_display; |
7a10dfa6 | 2541 | bool disable_vtd_wa; |
84c33a64 | 2542 | int use_mmio_flip; |
48572edd | 2543 | int mmio_debug; |
e2c719b7 | 2544 | bool verbose_state_checks; |
b2e7723b | 2545 | bool nuclear_pageflip; |
9e458034 | 2546 | int edp_vswing; |
d330a953 JN |
2547 | }; |
2548 | extern struct i915_params i915 __read_mostly; | |
2549 | ||
1da177e4 | 2550 | /* i915_dma.c */ |
22eae947 | 2551 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 2552 | extern int i915_driver_unload(struct drm_device *); |
2885f6ac | 2553 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file); |
84b1fd10 | 2554 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac | 2555 | extern void i915_driver_preclose(struct drm_device *dev, |
2885f6ac | 2556 | struct drm_file *file); |
673a394b | 2557 | extern void i915_driver_postclose(struct drm_device *dev, |
2885f6ac | 2558 | struct drm_file *file); |
84b1fd10 | 2559 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
c43b5634 | 2560 | #ifdef CONFIG_COMPAT |
0d6aa60b DA |
2561 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
2562 | unsigned long arg); | |
c43b5634 | 2563 | #endif |
8e96d9c4 | 2564 | extern int intel_gpu_reset(struct drm_device *dev); |
d4b8bb2a | 2565 | extern int i915_reset(struct drm_device *dev); |
7648fa99 JB |
2566 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
2567 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
2568 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
2569 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
650ad970 | 2570 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); |
1d0d343a | 2571 | void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); |
eb805623 | 2572 | void i915_firmware_load_error_print(const char *fw_path, int err); |
7648fa99 | 2573 | |
1da177e4 | 2574 | /* i915_irq.c */ |
10cd45b6 | 2575 | void i915_queue_hangcheck(struct drm_device *dev); |
58174462 MK |
2576 | __printf(3, 4) |
2577 | void i915_handle_error(struct drm_device *dev, bool wedged, | |
2578 | const char *fmt, ...); | |
1da177e4 | 2579 | |
b963291c DV |
2580 | extern void intel_irq_init(struct drm_i915_private *dev_priv); |
2581 | extern void intel_hpd_init(struct drm_i915_private *dev_priv); | |
2aeb7d3a DV |
2582 | int intel_irq_install(struct drm_i915_private *dev_priv); |
2583 | void intel_irq_uninstall(struct drm_i915_private *dev_priv); | |
907b28c5 CW |
2584 | |
2585 | extern void intel_uncore_sanitize(struct drm_device *dev); | |
10018603 ID |
2586 | extern void intel_uncore_early_sanitize(struct drm_device *dev, |
2587 | bool restore_forcewake); | |
907b28c5 | 2588 | extern void intel_uncore_init(struct drm_device *dev); |
907b28c5 | 2589 | extern void intel_uncore_check_errors(struct drm_device *dev); |
aec347ab | 2590 | extern void intel_uncore_fini(struct drm_device *dev); |
156c7ca0 | 2591 | extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore); |
48c1026a | 2592 | const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id); |
59bad947 | 2593 | void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, |
48c1026a | 2594 | enum forcewake_domains domains); |
59bad947 | 2595 | void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, |
48c1026a | 2596 | enum forcewake_domains domains); |
a6111f7b CW |
2597 | /* Like above but the caller must manage the uncore.lock itself. |
2598 | * Must be used with I915_READ_FW and friends. | |
2599 | */ | |
2600 | void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv, | |
2601 | enum forcewake_domains domains); | |
2602 | void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv, | |
2603 | enum forcewake_domains domains); | |
59bad947 | 2604 | void assert_forcewakes_inactive(struct drm_i915_private *dev_priv); |
cf9d2890 YZ |
2605 | static inline bool intel_vgpu_active(struct drm_device *dev) |
2606 | { | |
2607 | return to_i915(dev)->vgpu.active; | |
2608 | } | |
b1f14ad0 | 2609 | |
7c463586 | 2610 | void |
50227e1c | 2611 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2612 | u32 status_mask); |
7c463586 KP |
2613 | |
2614 | void | |
50227e1c | 2615 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2616 | u32 status_mask); |
7c463586 | 2617 | |
f8b79e58 ID |
2618 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); |
2619 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); | |
47339cd9 DV |
2620 | void |
2621 | ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask); | |
2622 | void | |
2623 | ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask); | |
2624 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, | |
2625 | uint32_t interrupt_mask, | |
2626 | uint32_t enabled_irq_mask); | |
2627 | #define ibx_enable_display_interrupt(dev_priv, bits) \ | |
2628 | ibx_display_interrupt_update((dev_priv), (bits), (bits)) | |
2629 | #define ibx_disable_display_interrupt(dev_priv, bits) \ | |
2630 | ibx_display_interrupt_update((dev_priv), (bits), 0) | |
f8b79e58 | 2631 | |
673a394b | 2632 | /* i915_gem.c */ |
673a394b EA |
2633 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
2634 | struct drm_file *file_priv); | |
2635 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
2636 | struct drm_file *file_priv); | |
2637 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
2638 | struct drm_file *file_priv); | |
2639 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
2640 | struct drm_file *file_priv); | |
de151cf6 JB |
2641 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
2642 | struct drm_file *file_priv); | |
673a394b EA |
2643 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
2644 | struct drm_file *file_priv); | |
2645 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
2646 | struct drm_file *file_priv); | |
ba8b7ccb OM |
2647 | void i915_gem_execbuffer_move_to_active(struct list_head *vmas, |
2648 | struct intel_engine_cs *ring); | |
2649 | void i915_gem_execbuffer_retire_commands(struct drm_device *dev, | |
2650 | struct drm_file *file, | |
2651 | struct intel_engine_cs *ring, | |
2652 | struct drm_i915_gem_object *obj); | |
a83014d3 OM |
2653 | int i915_gem_ringbuffer_submission(struct drm_device *dev, |
2654 | struct drm_file *file, | |
2655 | struct intel_engine_cs *ring, | |
2656 | struct intel_context *ctx, | |
2657 | struct drm_i915_gem_execbuffer2 *args, | |
2658 | struct list_head *vmas, | |
2659 | struct drm_i915_gem_object *batch_obj, | |
2660 | u64 exec_start, u32 flags); | |
673a394b EA |
2661 | int i915_gem_execbuffer(struct drm_device *dev, void *data, |
2662 | struct drm_file *file_priv); | |
76446cac JB |
2663 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
2664 | struct drm_file *file_priv); | |
673a394b EA |
2665 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
2666 | struct drm_file *file_priv); | |
199adf40 BW |
2667 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
2668 | struct drm_file *file); | |
2669 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, | |
2670 | struct drm_file *file); | |
673a394b EA |
2671 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
2672 | struct drm_file *file_priv); | |
3ef94daa CW |
2673 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
2674 | struct drm_file *file_priv); | |
673a394b EA |
2675 | int i915_gem_set_tiling(struct drm_device *dev, void *data, |
2676 | struct drm_file *file_priv); | |
2677 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
2678 | struct drm_file *file_priv); | |
5cc9ed4b CW |
2679 | int i915_gem_init_userptr(struct drm_device *dev); |
2680 | int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, | |
2681 | struct drm_file *file); | |
5a125c3c EA |
2682 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
2683 | struct drm_file *file_priv); | |
23ba4fd0 BW |
2684 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
2685 | struct drm_file *file_priv); | |
673a394b | 2686 | void i915_gem_load(struct drm_device *dev); |
42dcedd4 CW |
2687 | void *i915_gem_object_alloc(struct drm_device *dev); |
2688 | void i915_gem_object_free(struct drm_i915_gem_object *obj); | |
37e680a1 CW |
2689 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
2690 | const struct drm_i915_gem_object_ops *ops); | |
05394f39 CW |
2691 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
2692 | size_t size); | |
7e0d96bc BW |
2693 | void i915_init_vm(struct drm_i915_private *dev_priv, |
2694 | struct i915_address_space *vm); | |
673a394b | 2695 | void i915_gem_free_object(struct drm_gem_object *obj); |
2f633156 | 2696 | void i915_gem_vma_destroy(struct i915_vma *vma); |
42dcedd4 | 2697 | |
0875546c DV |
2698 | /* Flags used by pin/bind&friends. */ |
2699 | #define PIN_MAPPABLE (1<<0) | |
2700 | #define PIN_NONBLOCK (1<<1) | |
2701 | #define PIN_GLOBAL (1<<2) | |
2702 | #define PIN_OFFSET_BIAS (1<<3) | |
2703 | #define PIN_USER (1<<4) | |
2704 | #define PIN_UPDATE (1<<5) | |
d23db88c | 2705 | #define PIN_OFFSET_MASK (~4095) |
ec7adb6e JL |
2706 | int __must_check |
2707 | i915_gem_object_pin(struct drm_i915_gem_object *obj, | |
2708 | struct i915_address_space *vm, | |
2709 | uint32_t alignment, | |
2710 | uint64_t flags); | |
2711 | int __must_check | |
2712 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, | |
2713 | const struct i915_ggtt_view *view, | |
2714 | uint32_t alignment, | |
2715 | uint64_t flags); | |
fe14d5f4 TU |
2716 | |
2717 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, | |
2718 | u32 flags); | |
07fe0b12 | 2719 | int __must_check i915_vma_unbind(struct i915_vma *vma); |
dd624afd | 2720 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); |
48018a57 | 2721 | void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); |
05394f39 | 2722 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
f787a5f5 | 2723 | |
4c914c0c BV |
2724 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, |
2725 | int *needs_clflush); | |
2726 | ||
37e680a1 | 2727 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
ee286370 CW |
2728 | |
2729 | static inline int __sg_page_count(struct scatterlist *sg) | |
9da3da66 | 2730 | { |
ee286370 CW |
2731 | return sg->length >> PAGE_SHIFT; |
2732 | } | |
67d5a50c | 2733 | |
ee286370 CW |
2734 | static inline struct page * |
2735 | i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) | |
9da3da66 | 2736 | { |
ee286370 CW |
2737 | if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT)) |
2738 | return NULL; | |
67d5a50c | 2739 | |
ee286370 CW |
2740 | if (n < obj->get_page.last) { |
2741 | obj->get_page.sg = obj->pages->sgl; | |
2742 | obj->get_page.last = 0; | |
2743 | } | |
67d5a50c | 2744 | |
ee286370 CW |
2745 | while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) { |
2746 | obj->get_page.last += __sg_page_count(obj->get_page.sg++); | |
2747 | if (unlikely(sg_is_chain(obj->get_page.sg))) | |
2748 | obj->get_page.sg = sg_chain_ptr(obj->get_page.sg); | |
2749 | } | |
67d5a50c | 2750 | |
ee286370 | 2751 | return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last); |
9da3da66 | 2752 | } |
ee286370 | 2753 | |
a5570178 CW |
2754 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
2755 | { | |
2756 | BUG_ON(obj->pages == NULL); | |
2757 | obj->pages_pin_count++; | |
2758 | } | |
2759 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) | |
2760 | { | |
2761 | BUG_ON(obj->pages_pin_count == 0); | |
2762 | obj->pages_pin_count--; | |
2763 | } | |
2764 | ||
54cf91dc | 2765 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
2911a35b | 2766 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
a4872ba6 | 2767 | struct intel_engine_cs *to); |
e2d05a8b | 2768 | void i915_vma_move_to_active(struct i915_vma *vma, |
a4872ba6 | 2769 | struct intel_engine_cs *ring); |
ff72145b DA |
2770 | int i915_gem_dumb_create(struct drm_file *file_priv, |
2771 | struct drm_device *dev, | |
2772 | struct drm_mode_create_dumb *args); | |
da6b51d0 DA |
2773 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, |
2774 | uint32_t handle, uint64_t *offset); | |
f787a5f5 CW |
2775 | /** |
2776 | * Returns true if seq1 is later than seq2. | |
2777 | */ | |
2778 | static inline bool | |
2779 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
2780 | { | |
2781 | return (int32_t)(seq1 - seq2) >= 0; | |
2782 | } | |
2783 | ||
1b5a433a JH |
2784 | static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req, |
2785 | bool lazy_coherency) | |
2786 | { | |
2787 | u32 seqno; | |
2788 | ||
2789 | BUG_ON(req == NULL); | |
2790 | ||
2791 | seqno = req->ring->get_seqno(req->ring, lazy_coherency); | |
2792 | ||
2793 | return i915_seqno_passed(seqno, req->seqno); | |
2794 | } | |
2795 | ||
fca26bb4 MK |
2796 | int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); |
2797 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); | |
06d98131 | 2798 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); |
d9e86c0e | 2799 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
2021746e | 2800 | |
d8ffa60b DV |
2801 | bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj); |
2802 | void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj); | |
1690e1eb | 2803 | |
8d9fc7fd | 2804 | struct drm_i915_gem_request * |
a4872ba6 | 2805 | i915_gem_find_active_request(struct intel_engine_cs *ring); |
8d9fc7fd | 2806 | |
b29c19b6 | 2807 | bool i915_gem_retire_requests(struct drm_device *dev); |
a4872ba6 | 2808 | void i915_gem_retire_requests_ring(struct intel_engine_cs *ring); |
33196ded | 2809 | int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, |
d6b2c790 | 2810 | bool interruptible); |
b6660d59 | 2811 | int __must_check i915_gem_check_olr(struct drm_i915_gem_request *req); |
84c33a64 | 2812 | |
1f83fee0 DV |
2813 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
2814 | { | |
2815 | return unlikely(atomic_read(&error->reset_counter) | |
2ac0f450 | 2816 | & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); |
1f83fee0 DV |
2817 | } |
2818 | ||
2819 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) | |
2820 | { | |
2ac0f450 MK |
2821 | return atomic_read(&error->reset_counter) & I915_WEDGED; |
2822 | } | |
2823 | ||
2824 | static inline u32 i915_reset_count(struct i915_gpu_error *error) | |
2825 | { | |
2826 | return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2; | |
1f83fee0 | 2827 | } |
a71d8d94 | 2828 | |
88b4aa87 MK |
2829 | static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv) |
2830 | { | |
2831 | return dev_priv->gpu_error.stop_rings == 0 || | |
2832 | dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN; | |
2833 | } | |
2834 | ||
2835 | static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv) | |
2836 | { | |
2837 | return dev_priv->gpu_error.stop_rings == 0 || | |
2838 | dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN; | |
2839 | } | |
2840 | ||
069efc1d | 2841 | void i915_gem_reset(struct drm_device *dev); |
000433b6 | 2842 | bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); |
1070a42b | 2843 | int __must_check i915_gem_init(struct drm_device *dev); |
a83014d3 | 2844 | int i915_gem_init_rings(struct drm_device *dev); |
f691e2f4 | 2845 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
a4872ba6 | 2846 | int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice); |
f691e2f4 | 2847 | void i915_gem_init_swizzling(struct drm_device *dev); |
79e53945 | 2848 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
b2da9fe5 | 2849 | int __must_check i915_gpu_idle(struct drm_device *dev); |
45c5f202 | 2850 | int __must_check i915_gem_suspend(struct drm_device *dev); |
a4872ba6 | 2851 | int __i915_add_request(struct intel_engine_cs *ring, |
0025c077 | 2852 | struct drm_file *file, |
9400ae5c JH |
2853 | struct drm_i915_gem_object *batch_obj); |
2854 | #define i915_add_request(ring) \ | |
2855 | __i915_add_request(ring, NULL, NULL) | |
9c654818 | 2856 | int __i915_wait_request(struct drm_i915_gem_request *req, |
16e9a21f ACO |
2857 | unsigned reset_counter, |
2858 | bool interruptible, | |
2859 | s64 *timeout, | |
2e1b8730 | 2860 | struct intel_rps_client *rps); |
a4b3a571 | 2861 | int __must_check i915_wait_request(struct drm_i915_gem_request *req); |
de151cf6 | 2862 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
2021746e | 2863 | int __must_check |
2e2f351d CW |
2864 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
2865 | bool readonly); | |
2866 | int __must_check | |
2021746e CW |
2867 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, |
2868 | bool write); | |
2869 | int __must_check | |
dabdfe02 CW |
2870 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
2871 | int __must_check | |
2da3b9b9 CW |
2872 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
2873 | u32 alignment, | |
e6617330 TU |
2874 | struct intel_engine_cs *pipelined, |
2875 | const struct i915_ggtt_view *view); | |
2876 | void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, | |
2877 | const struct i915_ggtt_view *view); | |
00731155 | 2878 | int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, |
6eeefaf3 | 2879 | int align); |
b29c19b6 | 2880 | int i915_gem_open(struct drm_device *dev, struct drm_file *file); |
05394f39 | 2881 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 2882 | |
0fa87796 ID |
2883 | uint32_t |
2884 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); | |
467cffba | 2885 | uint32_t |
d865110c ID |
2886 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
2887 | int tiling_mode, bool fenced); | |
467cffba | 2888 | |
e4ffd173 CW |
2889 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
2890 | enum i915_cache_level cache_level); | |
2891 | ||
1286ff73 DV |
2892 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
2893 | struct dma_buf *dma_buf); | |
2894 | ||
2895 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, | |
2896 | struct drm_gem_object *gem_obj, int flags); | |
2897 | ||
19b2dbde CW |
2898 | void i915_gem_restore_fences(struct drm_device *dev); |
2899 | ||
ec7adb6e JL |
2900 | unsigned long |
2901 | i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, | |
9abc4648 | 2902 | const struct i915_ggtt_view *view); |
ec7adb6e JL |
2903 | unsigned long |
2904 | i915_gem_obj_offset(struct drm_i915_gem_object *o, | |
2905 | struct i915_address_space *vm); | |
2906 | static inline unsigned long | |
2907 | i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o) | |
fe14d5f4 | 2908 | { |
9abc4648 | 2909 | return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal); |
fe14d5f4 | 2910 | } |
ec7adb6e | 2911 | |
a70a3148 | 2912 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); |
ec7adb6e | 2913 | bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, |
9abc4648 | 2914 | const struct i915_ggtt_view *view); |
a70a3148 | 2915 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, |
ec7adb6e | 2916 | struct i915_address_space *vm); |
fe14d5f4 | 2917 | |
a70a3148 BW |
2918 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, |
2919 | struct i915_address_space *vm); | |
fe14d5f4 | 2920 | struct i915_vma * |
ec7adb6e JL |
2921 | i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
2922 | struct i915_address_space *vm); | |
2923 | struct i915_vma * | |
2924 | i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, | |
2925 | const struct i915_ggtt_view *view); | |
fe14d5f4 | 2926 | |
accfef2e BW |
2927 | struct i915_vma * |
2928 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
ec7adb6e JL |
2929 | struct i915_address_space *vm); |
2930 | struct i915_vma * | |
2931 | i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj, | |
2932 | const struct i915_ggtt_view *view); | |
5c2abbea | 2933 | |
ec7adb6e JL |
2934 | static inline struct i915_vma * |
2935 | i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) | |
2936 | { | |
2937 | return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal); | |
d7f46fc4 | 2938 | } |
ec7adb6e | 2939 | bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj); |
5c2abbea | 2940 | |
a70a3148 | 2941 | /* Some GGTT VM helpers */ |
5dc383b0 | 2942 | #define i915_obj_to_ggtt(obj) \ |
a70a3148 BW |
2943 | (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) |
2944 | static inline bool i915_is_ggtt(struct i915_address_space *vm) | |
2945 | { | |
2946 | struct i915_address_space *ggtt = | |
2947 | &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base; | |
2948 | return vm == ggtt; | |
2949 | } | |
2950 | ||
841cd773 DV |
2951 | static inline struct i915_hw_ppgtt * |
2952 | i915_vm_to_ppgtt(struct i915_address_space *vm) | |
2953 | { | |
2954 | WARN_ON(i915_is_ggtt(vm)); | |
2955 | ||
2956 | return container_of(vm, struct i915_hw_ppgtt, base); | |
2957 | } | |
2958 | ||
2959 | ||
a70a3148 BW |
2960 | static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) |
2961 | { | |
9abc4648 | 2962 | return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal); |
a70a3148 BW |
2963 | } |
2964 | ||
2965 | static inline unsigned long | |
2966 | i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) | |
2967 | { | |
5dc383b0 | 2968 | return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj)); |
a70a3148 | 2969 | } |
c37e2204 BW |
2970 | |
2971 | static inline int __must_check | |
2972 | i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, | |
2973 | uint32_t alignment, | |
1ec9e26d | 2974 | unsigned flags) |
c37e2204 | 2975 | { |
5dc383b0 DV |
2976 | return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj), |
2977 | alignment, flags | PIN_GLOBAL); | |
c37e2204 | 2978 | } |
a70a3148 | 2979 | |
b287110e DV |
2980 | static inline int |
2981 | i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) | |
2982 | { | |
2983 | return i915_vma_unbind(i915_gem_obj_to_ggtt(obj)); | |
2984 | } | |
2985 | ||
e6617330 TU |
2986 | void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, |
2987 | const struct i915_ggtt_view *view); | |
2988 | static inline void | |
2989 | i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) | |
2990 | { | |
2991 | i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal); | |
2992 | } | |
b287110e | 2993 | |
254f965c | 2994 | /* i915_gem_context.c */ |
8245be31 | 2995 | int __must_check i915_gem_context_init(struct drm_device *dev); |
254f965c | 2996 | void i915_gem_context_fini(struct drm_device *dev); |
acce9ffa | 2997 | void i915_gem_context_reset(struct drm_device *dev); |
e422b888 | 2998 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); |
2fa48d8d | 2999 | int i915_gem_context_enable(struct drm_i915_private *dev_priv); |
254f965c | 3000 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
a4872ba6 | 3001 | int i915_switch_context(struct intel_engine_cs *ring, |
273497e5 OM |
3002 | struct intel_context *to); |
3003 | struct intel_context * | |
41bde553 | 3004 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); |
dce3271b | 3005 | void i915_gem_context_free(struct kref *ctx_ref); |
8c857917 OM |
3006 | struct drm_i915_gem_object * |
3007 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size); | |
273497e5 | 3008 | static inline void i915_gem_context_reference(struct intel_context *ctx) |
dce3271b | 3009 | { |
691e6415 | 3010 | kref_get(&ctx->ref); |
dce3271b MK |
3011 | } |
3012 | ||
273497e5 | 3013 | static inline void i915_gem_context_unreference(struct intel_context *ctx) |
dce3271b | 3014 | { |
691e6415 | 3015 | kref_put(&ctx->ref, i915_gem_context_free); |
dce3271b MK |
3016 | } |
3017 | ||
273497e5 | 3018 | static inline bool i915_gem_context_is_default(const struct intel_context *c) |
3fac8978 | 3019 | { |
821d66dd | 3020 | return c->user_handle == DEFAULT_CONTEXT_HANDLE; |
3fac8978 MK |
3021 | } |
3022 | ||
84624813 BW |
3023 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
3024 | struct drm_file *file); | |
3025 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
3026 | struct drm_file *file); | |
c9dc0f35 CW |
3027 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, |
3028 | struct drm_file *file_priv); | |
3029 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, | |
3030 | struct drm_file *file_priv); | |
1286ff73 | 3031 | |
679845ed BW |
3032 | /* i915_gem_evict.c */ |
3033 | int __must_check i915_gem_evict_something(struct drm_device *dev, | |
3034 | struct i915_address_space *vm, | |
3035 | int min_size, | |
3036 | unsigned alignment, | |
3037 | unsigned cache_level, | |
d23db88c CW |
3038 | unsigned long start, |
3039 | unsigned long end, | |
1ec9e26d | 3040 | unsigned flags); |
679845ed BW |
3041 | int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); |
3042 | int i915_gem_evict_everything(struct drm_device *dev); | |
1d2a314c | 3043 | |
0260c420 | 3044 | /* belongs in i915_gem_gtt.h */ |
d09105c6 | 3045 | static inline void i915_gem_chipset_flush(struct drm_device *dev) |
e76e9aeb BW |
3046 | { |
3047 | if (INTEL_INFO(dev)->gen < 6) | |
3048 | intel_gtt_chipset_flush(); | |
3049 | } | |
246cbfb5 | 3050 | |
9797fbfb CW |
3051 | /* i915_gem_stolen.c */ |
3052 | int i915_gem_init_stolen(struct drm_device *dev); | |
5e59f717 | 3053 | int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp); |
11be49eb | 3054 | void i915_gem_stolen_cleanup_compression(struct drm_device *dev); |
9797fbfb | 3055 | void i915_gem_cleanup_stolen(struct drm_device *dev); |
0104fdbb CW |
3056 | struct drm_i915_gem_object * |
3057 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); | |
866d12b4 CW |
3058 | struct drm_i915_gem_object * |
3059 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, | |
3060 | u32 stolen_offset, | |
3061 | u32 gtt_offset, | |
3062 | u32 size); | |
9797fbfb | 3063 | |
be6a0376 DV |
3064 | /* i915_gem_shrinker.c */ |
3065 | unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, | |
3066 | long target, | |
3067 | unsigned flags); | |
3068 | #define I915_SHRINK_PURGEABLE 0x1 | |
3069 | #define I915_SHRINK_UNBOUND 0x2 | |
3070 | #define I915_SHRINK_BOUND 0x4 | |
3071 | unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); | |
3072 | void i915_gem_shrinker_init(struct drm_i915_private *dev_priv); | |
3073 | ||
3074 | ||
673a394b | 3075 | /* i915_gem_tiling.c */ |
2c1792a1 | 3076 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
e9b73c67 | 3077 | { |
50227e1c | 3078 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e9b73c67 CW |
3079 | |
3080 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
3081 | obj->tiling_mode != I915_TILING_NONE; | |
3082 | } | |
3083 | ||
673a394b | 3084 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
05394f39 CW |
3085 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
3086 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
673a394b EA |
3087 | |
3088 | /* i915_gem_debug.c */ | |
23bc5982 CW |
3089 | #if WATCH_LISTS |
3090 | int i915_verify_lists(struct drm_device *dev); | |
673a394b | 3091 | #else |
23bc5982 | 3092 | #define i915_verify_lists(dev) 0 |
673a394b | 3093 | #endif |
1da177e4 | 3094 | |
2017263e | 3095 | /* i915_debugfs.c */ |
27c202ad BG |
3096 | int i915_debugfs_init(struct drm_minor *minor); |
3097 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
f8c168fa | 3098 | #ifdef CONFIG_DEBUG_FS |
249e87de | 3099 | int i915_debugfs_connector_add(struct drm_connector *connector); |
07144428 DL |
3100 | void intel_display_crc_init(struct drm_device *dev); |
3101 | #else | |
249e87de | 3102 | static inline int i915_debugfs_connector_add(struct drm_connector *connector) {} |
f8c168fa | 3103 | static inline void intel_display_crc_init(struct drm_device *dev) {} |
07144428 | 3104 | #endif |
84734a04 MK |
3105 | |
3106 | /* i915_gpu_error.c */ | |
edc3d884 MK |
3107 | __printf(2, 3) |
3108 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); | |
fc16b48b MK |
3109 | int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, |
3110 | const struct i915_error_state_file_priv *error); | |
4dc955f7 | 3111 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, |
0a4cd7c8 | 3112 | struct drm_i915_private *i915, |
4dc955f7 MK |
3113 | size_t count, loff_t pos); |
3114 | static inline void i915_error_state_buf_release( | |
3115 | struct drm_i915_error_state_buf *eb) | |
3116 | { | |
3117 | kfree(eb->buf); | |
3118 | } | |
58174462 MK |
3119 | void i915_capture_error_state(struct drm_device *dev, bool wedge, |
3120 | const char *error_msg); | |
84734a04 MK |
3121 | void i915_error_state_get(struct drm_device *dev, |
3122 | struct i915_error_state_file_priv *error_priv); | |
3123 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv); | |
3124 | void i915_destroy_error_state(struct drm_device *dev); | |
3125 | ||
3126 | void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); | |
0a4cd7c8 | 3127 | const char *i915_cache_level_str(struct drm_i915_private *i915, int type); |
2017263e | 3128 | |
351e3db2 | 3129 | /* i915_cmd_parser.c */ |
d728c8ef | 3130 | int i915_cmd_parser_get_version(void); |
a4872ba6 OM |
3131 | int i915_cmd_parser_init_ring(struct intel_engine_cs *ring); |
3132 | void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring); | |
3133 | bool i915_needs_cmd_parser(struct intel_engine_cs *ring); | |
3134 | int i915_parse_cmds(struct intel_engine_cs *ring, | |
351e3db2 | 3135 | struct drm_i915_gem_object *batch_obj, |
78a42377 | 3136 | struct drm_i915_gem_object *shadow_batch_obj, |
351e3db2 | 3137 | u32 batch_start_offset, |
b9ffd80e | 3138 | u32 batch_len, |
351e3db2 BV |
3139 | bool is_master); |
3140 | ||
317c35d1 JB |
3141 | /* i915_suspend.c */ |
3142 | extern int i915_save_state(struct drm_device *dev); | |
3143 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 | 3144 | |
0136db58 BW |
3145 | /* i915_sysfs.c */ |
3146 | void i915_setup_sysfs(struct drm_device *dev_priv); | |
3147 | void i915_teardown_sysfs(struct drm_device *dev_priv); | |
3148 | ||
f899fc64 CW |
3149 | /* intel_i2c.c */ |
3150 | extern int intel_setup_gmbus(struct drm_device *dev); | |
3151 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
88ac7939 JN |
3152 | extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, |
3153 | unsigned int pin); | |
3bd7d909 | 3154 | |
0184df46 JN |
3155 | extern struct i2c_adapter * |
3156 | intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin); | |
e957d772 CW |
3157 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
3158 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
8f375e10 | 3159 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
b8232e90 CW |
3160 | { |
3161 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
3162 | } | |
f899fc64 CW |
3163 | extern void intel_i2c_reset(struct drm_device *dev); |
3164 | ||
3b617967 | 3165 | /* intel_opregion.c */ |
44834a67 | 3166 | #ifdef CONFIG_ACPI |
27d50c82 | 3167 | extern int intel_opregion_setup(struct drm_device *dev); |
44834a67 CW |
3168 | extern void intel_opregion_init(struct drm_device *dev); |
3169 | extern void intel_opregion_fini(struct drm_device *dev); | |
3b617967 | 3170 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
9c4b0a68 JN |
3171 | extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, |
3172 | bool enable); | |
ecbc5cf3 JN |
3173 | extern int intel_opregion_notify_adapter(struct drm_device *dev, |
3174 | pci_power_t state); | |
65e082c9 | 3175 | #else |
27d50c82 | 3176 | static inline int intel_opregion_setup(struct drm_device *dev) { return 0; } |
44834a67 CW |
3177 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
3178 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } | |
3b617967 | 3179 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
9c4b0a68 JN |
3180 | static inline int |
3181 | intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) | |
3182 | { | |
3183 | return 0; | |
3184 | } | |
ecbc5cf3 JN |
3185 | static inline int |
3186 | intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state) | |
3187 | { | |
3188 | return 0; | |
3189 | } | |
65e082c9 | 3190 | #endif |
8ee1c3db | 3191 | |
723bfd70 JB |
3192 | /* intel_acpi.c */ |
3193 | #ifdef CONFIG_ACPI | |
3194 | extern void intel_register_dsm_handler(void); | |
3195 | extern void intel_unregister_dsm_handler(void); | |
3196 | #else | |
3197 | static inline void intel_register_dsm_handler(void) { return; } | |
3198 | static inline void intel_unregister_dsm_handler(void) { return; } | |
3199 | #endif /* CONFIG_ACPI */ | |
3200 | ||
79e53945 | 3201 | /* modesetting */ |
f817586c | 3202 | extern void intel_modeset_init_hw(struct drm_device *dev); |
79e53945 | 3203 | extern void intel_modeset_init(struct drm_device *dev); |
2c7111db | 3204 | extern void intel_modeset_gem_init(struct drm_device *dev); |
79e53945 | 3205 | extern void intel_modeset_cleanup(struct drm_device *dev); |
4932e2c3 | 3206 | extern void intel_connector_unregister(struct intel_connector *); |
28d52043 | 3207 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
45e2b5f6 DV |
3208 | extern void intel_modeset_setup_hw_state(struct drm_device *dev, |
3209 | bool force_restore); | |
44cec740 | 3210 | extern void i915_redisable_vga(struct drm_device *dev); |
04098753 | 3211 | extern void i915_redisable_vga_power_on(struct drm_device *dev); |
7648fa99 | 3212 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
dde86e2d | 3213 | extern void intel_init_pch_refclk(struct drm_device *dev); |
ffe02b40 | 3214 | extern void intel_set_rps(struct drm_device *dev, u8 val); |
5209b1f4 ID |
3215 | extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, |
3216 | bool enable); | |
0206e353 AJ |
3217 | extern void intel_detect_pch(struct drm_device *dev); |
3218 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); | |
0136db58 | 3219 | extern int intel_enable_rc6(const struct drm_device *dev); |
3bad0781 | 3220 | |
2911a35b | 3221 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
c0c7babc BW |
3222 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
3223 | struct drm_file *file); | |
b6359918 MK |
3224 | int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, |
3225 | struct drm_file *file); | |
575155a9 | 3226 | |
6ef3d427 CW |
3227 | /* overlay */ |
3228 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); | |
edc3d884 MK |
3229 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
3230 | struct intel_overlay_error_state *error); | |
c4a1d9e4 CW |
3231 | |
3232 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); | |
edc3d884 | 3233 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
c4a1d9e4 CW |
3234 | struct drm_device *dev, |
3235 | struct intel_display_error_state *error); | |
6ef3d427 | 3236 | |
151a49d0 TR |
3237 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); |
3238 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val); | |
59de0813 JN |
3239 | |
3240 | /* intel_sideband.c */ | |
707b6e3d D |
3241 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr); |
3242 | void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val); | |
64936258 | 3243 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); |
e9f882a3 JN |
3244 | u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); |
3245 | void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
3246 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); | |
3247 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
3248 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); | |
3249 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
f3419158 JB |
3250 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); |
3251 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
e9f882a3 JN |
3252 | u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg); |
3253 | void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
5e69f97f CML |
3254 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); |
3255 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); | |
59de0813 JN |
3256 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
3257 | enum intel_sbi_destination destination); | |
3258 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, | |
3259 | enum intel_sbi_destination destination); | |
e9fe51c6 SK |
3260 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); |
3261 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
0a073b84 | 3262 | |
616bc820 VS |
3263 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); |
3264 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); | |
c8d9a590 | 3265 | |
0b274481 BW |
3266 | #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) |
3267 | #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) | |
3268 | ||
3269 | #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) | |
3270 | #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) | |
3271 | #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) | |
3272 | #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) | |
3273 | ||
3274 | #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) | |
3275 | #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) | |
3276 | #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) | |
3277 | #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) | |
3278 | ||
698b3135 CW |
3279 | /* Be very careful with read/write 64-bit values. On 32-bit machines, they |
3280 | * will be implemented using 2 32-bit writes in an arbitrary order with | |
3281 | * an arbitrary delay between them. This can cause the hardware to | |
3282 | * act upon the intermediate value, possibly leading to corruption and | |
3283 | * machine death. You have been warned. | |
3284 | */ | |
0b274481 BW |
3285 | #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) |
3286 | #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) | |
cae5852d | 3287 | |
50877445 CW |
3288 | #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ |
3289 | u32 upper = I915_READ(upper_reg); \ | |
3290 | u32 lower = I915_READ(lower_reg); \ | |
3291 | u32 tmp = I915_READ(upper_reg); \ | |
3292 | if (upper != tmp) { \ | |
3293 | upper = tmp; \ | |
3294 | lower = I915_READ(lower_reg); \ | |
3295 | WARN_ON(I915_READ(upper_reg) != upper); \ | |
3296 | } \ | |
3297 | (u64)upper << 32 | lower; }) | |
3298 | ||
cae5852d ZN |
3299 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
3300 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
3301 | ||
a6111f7b CW |
3302 | /* These are untraced mmio-accessors that are only valid to be used inside |
3303 | * criticial sections inside IRQ handlers where forcewake is explicitly | |
3304 | * controlled. | |
3305 | * Think twice, and think again, before using these. | |
3306 | * Note: Should only be used between intel_uncore_forcewake_irqlock() and | |
3307 | * intel_uncore_forcewake_irqunlock(). | |
3308 | */ | |
3309 | #define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__)) | |
3310 | #define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__)) | |
3311 | #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__) | |
3312 | ||
55bc60db VS |
3313 | /* "Broadcast RGB" property */ |
3314 | #define INTEL_BROADCAST_RGB_AUTO 0 | |
3315 | #define INTEL_BROADCAST_RGB_FULL 1 | |
3316 | #define INTEL_BROADCAST_RGB_LIMITED 2 | |
ba4f01a3 | 3317 | |
766aa1c4 VS |
3318 | static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) |
3319 | { | |
92e23b99 | 3320 | if (IS_VALLEYVIEW(dev)) |
766aa1c4 | 3321 | return VLV_VGACNTRL; |
92e23b99 SJ |
3322 | else if (INTEL_INFO(dev)->gen >= 5) |
3323 | return CPU_VGACNTRL; | |
766aa1c4 VS |
3324 | else |
3325 | return VGACNTRL; | |
3326 | } | |
3327 | ||
2bb4629a VS |
3328 | static inline void __user *to_user_ptr(u64 address) |
3329 | { | |
3330 | return (void __user *)(uintptr_t)address; | |
3331 | } | |
3332 | ||
df97729f ID |
3333 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
3334 | { | |
3335 | unsigned long j = msecs_to_jiffies(m); | |
3336 | ||
3337 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3338 | } | |
3339 | ||
7bd0e226 DV |
3340 | static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) |
3341 | { | |
3342 | return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); | |
3343 | } | |
3344 | ||
df97729f ID |
3345 | static inline unsigned long |
3346 | timespec_to_jiffies_timeout(const struct timespec *value) | |
3347 | { | |
3348 | unsigned long j = timespec_to_jiffies(value); | |
3349 | ||
3350 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3351 | } | |
3352 | ||
dce56b3c PZ |
3353 | /* |
3354 | * If you need to wait X milliseconds between events A and B, but event B | |
3355 | * doesn't happen exactly after event A, you record the timestamp (jiffies) of | |
3356 | * when event A happened, then just before event B you call this function and | |
3357 | * pass the timestamp as the first argument, and X as the second argument. | |
3358 | */ | |
3359 | static inline void | |
3360 | wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) | |
3361 | { | |
ec5e0cfb | 3362 | unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; |
dce56b3c PZ |
3363 | |
3364 | /* | |
3365 | * Don't re-read the value of "jiffies" every time since it may change | |
3366 | * behind our back and break the math. | |
3367 | */ | |
3368 | tmp_jiffies = jiffies; | |
3369 | target_jiffies = timestamp_jiffies + | |
3370 | msecs_to_jiffies_timeout(to_wait_ms); | |
3371 | ||
3372 | if (time_after(target_jiffies, tmp_jiffies)) { | |
ec5e0cfb ID |
3373 | remaining_jiffies = target_jiffies - tmp_jiffies; |
3374 | while (remaining_jiffies) | |
3375 | remaining_jiffies = | |
3376 | schedule_timeout_uninterruptible(remaining_jiffies); | |
dce56b3c PZ |
3377 | } |
3378 | } | |
3379 | ||
581c26e8 JH |
3380 | static inline void i915_trace_irq_get(struct intel_engine_cs *ring, |
3381 | struct drm_i915_gem_request *req) | |
3382 | { | |
3383 | if (ring->trace_irq_req == NULL && ring->irq_get(ring)) | |
3384 | i915_gem_request_assign(&ring->trace_irq_req, req); | |
3385 | } | |
3386 | ||
1da177e4 | 3387 | #endif |