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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
319c1d42 | 40 | #include <drm/drm_atomic.h> |
c196e1d6 | 41 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
42 | #include <drm/drm_dp_helper.h> |
43 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
44 | #include <drm/drm_plane_helper.h> |
45 | #include <drm/drm_rect.h> | |
c0f372b3 | 46 | #include <linux/dma_remapping.h> |
fd8e058a AG |
47 | #include <linux/reservation.h> |
48 | #include <linux/dma-buf.h> | |
79e53945 | 49 | |
465c120c | 50 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 51 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
52 | DRM_FORMAT_C8, |
53 | DRM_FORMAT_RGB565, | |
465c120c | 54 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 55 | DRM_FORMAT_XRGB8888, |
465c120c MR |
56 | }; |
57 | ||
58 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 59 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
60 | DRM_FORMAT_C8, |
61 | DRM_FORMAT_RGB565, | |
62 | DRM_FORMAT_XRGB8888, | |
63 | DRM_FORMAT_XBGR8888, | |
64 | DRM_FORMAT_XRGB2101010, | |
65 | DRM_FORMAT_XBGR2101010, | |
66 | }; | |
67 | ||
68 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
69 | DRM_FORMAT_C8, |
70 | DRM_FORMAT_RGB565, | |
71 | DRM_FORMAT_XRGB8888, | |
465c120c | 72 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 73 | DRM_FORMAT_ARGB8888, |
465c120c MR |
74 | DRM_FORMAT_ABGR8888, |
75 | DRM_FORMAT_XRGB2101010, | |
465c120c | 76 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
77 | DRM_FORMAT_YUYV, |
78 | DRM_FORMAT_YVYU, | |
79 | DRM_FORMAT_UYVY, | |
80 | DRM_FORMAT_VYUY, | |
465c120c MR |
81 | }; |
82 | ||
3d7d6510 MR |
83 | /* Cursor formats */ |
84 | static const uint32_t intel_cursor_formats[] = { | |
85 | DRM_FORMAT_ARGB8888, | |
86 | }; | |
87 | ||
f1f644dc | 88 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 89 | struct intel_crtc_state *pipe_config); |
18442d08 | 90 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 91 | struct intel_crtc_state *pipe_config); |
f1f644dc | 92 | |
eb1bfe80 JB |
93 | static int intel_framebuffer_init(struct drm_device *dev, |
94 | struct intel_framebuffer *ifb, | |
95 | struct drm_mode_fb_cmd2 *mode_cmd, | |
96 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
97 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
98 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 99 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
100 | struct intel_link_m_n *m_n, |
101 | struct intel_link_m_n *m2_n2); | |
29407aab | 102 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
103 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
104 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f | 105 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 106 | const struct intel_crtc_state *pipe_config); |
d288f65f | 107 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 108 | const struct intel_crtc_state *pipe_config); |
613d2b27 ML |
109 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
110 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
549e2bfb CK |
111 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
112 | struct intel_crtc_state *crtc_state); | |
5ab7b0b7 ID |
113 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
114 | int num_connectors); | |
bfd16b2a ML |
115 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
116 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
117 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 118 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
200757f5 | 119 | static void intel_pre_disable_primary(struct drm_crtc *crtc); |
e7457a9a | 120 | |
79e53945 | 121 | typedef struct { |
0206e353 | 122 | int min, max; |
79e53945 JB |
123 | } intel_range_t; |
124 | ||
125 | typedef struct { | |
0206e353 AJ |
126 | int dot_limit; |
127 | int p2_slow, p2_fast; | |
79e53945 JB |
128 | } intel_p2_t; |
129 | ||
d4906093 ML |
130 | typedef struct intel_limit intel_limit_t; |
131 | struct intel_limit { | |
0206e353 AJ |
132 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
133 | intel_p2_t p2; | |
d4906093 | 134 | }; |
79e53945 | 135 | |
bfa7df01 VS |
136 | /* returns HPLL frequency in kHz */ |
137 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) | |
138 | { | |
139 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
140 | ||
141 | /* Obtain SKU information */ | |
142 | mutex_lock(&dev_priv->sb_lock); | |
143 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
144 | CCK_FUSE_HPLL_FREQ_MASK; | |
145 | mutex_unlock(&dev_priv->sb_lock); | |
146 | ||
147 | return vco_freq[hpll_freq] * 1000; | |
148 | } | |
149 | ||
150 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
151 | const char *name, u32 reg) | |
152 | { | |
153 | u32 val; | |
154 | int divider; | |
155 | ||
156 | if (dev_priv->hpll_freq == 0) | |
157 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
158 | ||
159 | mutex_lock(&dev_priv->sb_lock); | |
160 | val = vlv_cck_read(dev_priv, reg); | |
161 | mutex_unlock(&dev_priv->sb_lock); | |
162 | ||
163 | divider = val & CCK_FREQUENCY_VALUES; | |
164 | ||
165 | WARN((val & CCK_FREQUENCY_STATUS) != | |
166 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
167 | "%s change in progress\n", name); | |
168 | ||
169 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); | |
170 | } | |
171 | ||
d2acd215 DV |
172 | int |
173 | intel_pch_rawclk(struct drm_device *dev) | |
174 | { | |
175 | struct drm_i915_private *dev_priv = dev->dev_private; | |
176 | ||
177 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
178 | ||
179 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
180 | } | |
181 | ||
79e50a4f JN |
182 | /* hrawclock is 1/4 the FSB frequency */ |
183 | int intel_hrawclk(struct drm_device *dev) | |
184 | { | |
185 | struct drm_i915_private *dev_priv = dev->dev_private; | |
186 | uint32_t clkcfg; | |
187 | ||
188 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ | |
666a4537 | 189 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
79e50a4f JN |
190 | return 200; |
191 | ||
192 | clkcfg = I915_READ(CLKCFG); | |
193 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
194 | case CLKCFG_FSB_400: | |
195 | return 100; | |
196 | case CLKCFG_FSB_533: | |
197 | return 133; | |
198 | case CLKCFG_FSB_667: | |
199 | return 166; | |
200 | case CLKCFG_FSB_800: | |
201 | return 200; | |
202 | case CLKCFG_FSB_1067: | |
203 | return 266; | |
204 | case CLKCFG_FSB_1333: | |
205 | return 333; | |
206 | /* these two are just a guess; one of them might be right */ | |
207 | case CLKCFG_FSB_1600: | |
208 | case CLKCFG_FSB_1600_ALT: | |
209 | return 400; | |
210 | default: | |
211 | return 133; | |
212 | } | |
213 | } | |
214 | ||
bfa7df01 VS |
215 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
216 | { | |
666a4537 | 217 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
218 | return; |
219 | ||
220 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
221 | CCK_CZ_CLOCK_CONTROL); | |
222 | ||
223 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
224 | } | |
225 | ||
021357ac CW |
226 | static inline u32 /* units of 100MHz */ |
227 | intel_fdi_link_freq(struct drm_device *dev) | |
228 | { | |
8b99e68c CW |
229 | if (IS_GEN5(dev)) { |
230 | struct drm_i915_private *dev_priv = dev->dev_private; | |
231 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
232 | } else | |
233 | return 27; | |
021357ac CW |
234 | } |
235 | ||
5d536e28 | 236 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 237 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 238 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 239 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
240 | .m = { .min = 96, .max = 140 }, |
241 | .m1 = { .min = 18, .max = 26 }, | |
242 | .m2 = { .min = 6, .max = 16 }, | |
243 | .p = { .min = 4, .max = 128 }, | |
244 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
245 | .p2 = { .dot_limit = 165000, |
246 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
247 | }; |
248 | ||
5d536e28 DV |
249 | static const intel_limit_t intel_limits_i8xx_dvo = { |
250 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 251 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 252 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
253 | .m = { .min = 96, .max = 140 }, |
254 | .m1 = { .min = 18, .max = 26 }, | |
255 | .m2 = { .min = 6, .max = 16 }, | |
256 | .p = { .min = 4, .max = 128 }, | |
257 | .p1 = { .min = 2, .max = 33 }, | |
258 | .p2 = { .dot_limit = 165000, | |
259 | .p2_slow = 4, .p2_fast = 4 }, | |
260 | }; | |
261 | ||
e4b36699 | 262 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 263 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 264 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 265 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
266 | .m = { .min = 96, .max = 140 }, |
267 | .m1 = { .min = 18, .max = 26 }, | |
268 | .m2 = { .min = 6, .max = 16 }, | |
269 | .p = { .min = 4, .max = 128 }, | |
270 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
271 | .p2 = { .dot_limit = 165000, |
272 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 273 | }; |
273e27ca | 274 | |
e4b36699 | 275 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
276 | .dot = { .min = 20000, .max = 400000 }, |
277 | .vco = { .min = 1400000, .max = 2800000 }, | |
278 | .n = { .min = 1, .max = 6 }, | |
279 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
280 | .m1 = { .min = 8, .max = 18 }, |
281 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
282 | .p = { .min = 5, .max = 80 }, |
283 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
284 | .p2 = { .dot_limit = 200000, |
285 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
286 | }; |
287 | ||
288 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
289 | .dot = { .min = 20000, .max = 400000 }, |
290 | .vco = { .min = 1400000, .max = 2800000 }, | |
291 | .n = { .min = 1, .max = 6 }, | |
292 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
293 | .m1 = { .min = 8, .max = 18 }, |
294 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
295 | .p = { .min = 7, .max = 98 }, |
296 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
297 | .p2 = { .dot_limit = 112000, |
298 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
299 | }; |
300 | ||
273e27ca | 301 | |
e4b36699 | 302 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
303 | .dot = { .min = 25000, .max = 270000 }, |
304 | .vco = { .min = 1750000, .max = 3500000}, | |
305 | .n = { .min = 1, .max = 4 }, | |
306 | .m = { .min = 104, .max = 138 }, | |
307 | .m1 = { .min = 17, .max = 23 }, | |
308 | .m2 = { .min = 5, .max = 11 }, | |
309 | .p = { .min = 10, .max = 30 }, | |
310 | .p1 = { .min = 1, .max = 3}, | |
311 | .p2 = { .dot_limit = 270000, | |
312 | .p2_slow = 10, | |
313 | .p2_fast = 10 | |
044c7c41 | 314 | }, |
e4b36699 KP |
315 | }; |
316 | ||
317 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
318 | .dot = { .min = 22000, .max = 400000 }, |
319 | .vco = { .min = 1750000, .max = 3500000}, | |
320 | .n = { .min = 1, .max = 4 }, | |
321 | .m = { .min = 104, .max = 138 }, | |
322 | .m1 = { .min = 16, .max = 23 }, | |
323 | .m2 = { .min = 5, .max = 11 }, | |
324 | .p = { .min = 5, .max = 80 }, | |
325 | .p1 = { .min = 1, .max = 8}, | |
326 | .p2 = { .dot_limit = 165000, | |
327 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
328 | }; |
329 | ||
330 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
331 | .dot = { .min = 20000, .max = 115000 }, |
332 | .vco = { .min = 1750000, .max = 3500000 }, | |
333 | .n = { .min = 1, .max = 3 }, | |
334 | .m = { .min = 104, .max = 138 }, | |
335 | .m1 = { .min = 17, .max = 23 }, | |
336 | .m2 = { .min = 5, .max = 11 }, | |
337 | .p = { .min = 28, .max = 112 }, | |
338 | .p1 = { .min = 2, .max = 8 }, | |
339 | .p2 = { .dot_limit = 0, | |
340 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 341 | }, |
e4b36699 KP |
342 | }; |
343 | ||
344 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
345 | .dot = { .min = 80000, .max = 224000 }, |
346 | .vco = { .min = 1750000, .max = 3500000 }, | |
347 | .n = { .min = 1, .max = 3 }, | |
348 | .m = { .min = 104, .max = 138 }, | |
349 | .m1 = { .min = 17, .max = 23 }, | |
350 | .m2 = { .min = 5, .max = 11 }, | |
351 | .p = { .min = 14, .max = 42 }, | |
352 | .p1 = { .min = 2, .max = 6 }, | |
353 | .p2 = { .dot_limit = 0, | |
354 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 355 | }, |
e4b36699 KP |
356 | }; |
357 | ||
f2b115e6 | 358 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
359 | .dot = { .min = 20000, .max = 400000}, |
360 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 361 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
362 | .n = { .min = 3, .max = 6 }, |
363 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 364 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
365 | .m1 = { .min = 0, .max = 0 }, |
366 | .m2 = { .min = 0, .max = 254 }, | |
367 | .p = { .min = 5, .max = 80 }, | |
368 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
369 | .p2 = { .dot_limit = 200000, |
370 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
371 | }; |
372 | ||
f2b115e6 | 373 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
374 | .dot = { .min = 20000, .max = 400000 }, |
375 | .vco = { .min = 1700000, .max = 3500000 }, | |
376 | .n = { .min = 3, .max = 6 }, | |
377 | .m = { .min = 2, .max = 256 }, | |
378 | .m1 = { .min = 0, .max = 0 }, | |
379 | .m2 = { .min = 0, .max = 254 }, | |
380 | .p = { .min = 7, .max = 112 }, | |
381 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
382 | .p2 = { .dot_limit = 112000, |
383 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
384 | }; |
385 | ||
273e27ca EA |
386 | /* Ironlake / Sandybridge |
387 | * | |
388 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
389 | * the range value for them is (actual_value - 2). | |
390 | */ | |
b91ad0ec | 391 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
392 | .dot = { .min = 25000, .max = 350000 }, |
393 | .vco = { .min = 1760000, .max = 3510000 }, | |
394 | .n = { .min = 1, .max = 5 }, | |
395 | .m = { .min = 79, .max = 127 }, | |
396 | .m1 = { .min = 12, .max = 22 }, | |
397 | .m2 = { .min = 5, .max = 9 }, | |
398 | .p = { .min = 5, .max = 80 }, | |
399 | .p1 = { .min = 1, .max = 8 }, | |
400 | .p2 = { .dot_limit = 225000, | |
401 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
402 | }; |
403 | ||
b91ad0ec | 404 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
405 | .dot = { .min = 25000, .max = 350000 }, |
406 | .vco = { .min = 1760000, .max = 3510000 }, | |
407 | .n = { .min = 1, .max = 3 }, | |
408 | .m = { .min = 79, .max = 118 }, | |
409 | .m1 = { .min = 12, .max = 22 }, | |
410 | .m2 = { .min = 5, .max = 9 }, | |
411 | .p = { .min = 28, .max = 112 }, | |
412 | .p1 = { .min = 2, .max = 8 }, | |
413 | .p2 = { .dot_limit = 225000, | |
414 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
415 | }; |
416 | ||
417 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
418 | .dot = { .min = 25000, .max = 350000 }, |
419 | .vco = { .min = 1760000, .max = 3510000 }, | |
420 | .n = { .min = 1, .max = 3 }, | |
421 | .m = { .min = 79, .max = 127 }, | |
422 | .m1 = { .min = 12, .max = 22 }, | |
423 | .m2 = { .min = 5, .max = 9 }, | |
424 | .p = { .min = 14, .max = 56 }, | |
425 | .p1 = { .min = 2, .max = 8 }, | |
426 | .p2 = { .dot_limit = 225000, | |
427 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
428 | }; |
429 | ||
273e27ca | 430 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 431 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
432 | .dot = { .min = 25000, .max = 350000 }, |
433 | .vco = { .min = 1760000, .max = 3510000 }, | |
434 | .n = { .min = 1, .max = 2 }, | |
435 | .m = { .min = 79, .max = 126 }, | |
436 | .m1 = { .min = 12, .max = 22 }, | |
437 | .m2 = { .min = 5, .max = 9 }, | |
438 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 439 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
440 | .p2 = { .dot_limit = 225000, |
441 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
442 | }; |
443 | ||
444 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
445 | .dot = { .min = 25000, .max = 350000 }, |
446 | .vco = { .min = 1760000, .max = 3510000 }, | |
447 | .n = { .min = 1, .max = 3 }, | |
448 | .m = { .min = 79, .max = 126 }, | |
449 | .m1 = { .min = 12, .max = 22 }, | |
450 | .m2 = { .min = 5, .max = 9 }, | |
451 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 452 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
453 | .p2 = { .dot_limit = 225000, |
454 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
455 | }; |
456 | ||
dc730512 | 457 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
458 | /* |
459 | * These are the data rate limits (measured in fast clocks) | |
460 | * since those are the strictest limits we have. The fast | |
461 | * clock and actual rate limits are more relaxed, so checking | |
462 | * them would make no difference. | |
463 | */ | |
464 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 465 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 466 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
467 | .m1 = { .min = 2, .max = 3 }, |
468 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 469 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 470 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
471 | }; |
472 | ||
ef9348c8 CML |
473 | static const intel_limit_t intel_limits_chv = { |
474 | /* | |
475 | * These are the data rate limits (measured in fast clocks) | |
476 | * since those are the strictest limits we have. The fast | |
477 | * clock and actual rate limits are more relaxed, so checking | |
478 | * them would make no difference. | |
479 | */ | |
480 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 481 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
482 | .n = { .min = 1, .max = 1 }, |
483 | .m1 = { .min = 2, .max = 2 }, | |
484 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
485 | .p1 = { .min = 2, .max = 4 }, | |
486 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
487 | }; | |
488 | ||
5ab7b0b7 ID |
489 | static const intel_limit_t intel_limits_bxt = { |
490 | /* FIXME: find real dot limits */ | |
491 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 492 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
493 | .n = { .min = 1, .max = 1 }, |
494 | .m1 = { .min = 2, .max = 2 }, | |
495 | /* FIXME: find real m2 limits */ | |
496 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
497 | .p1 = { .min = 2, .max = 4 }, | |
498 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
499 | }; | |
500 | ||
cdba954e ACO |
501 | static bool |
502 | needs_modeset(struct drm_crtc_state *state) | |
503 | { | |
fc596660 | 504 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
505 | } |
506 | ||
e0638cdf PZ |
507 | /** |
508 | * Returns whether any output on the specified pipe is of the specified type | |
509 | */ | |
4093561b | 510 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 511 | { |
409ee761 | 512 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
513 | struct intel_encoder *encoder; |
514 | ||
409ee761 | 515 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
516 | if (encoder->type == type) |
517 | return true; | |
518 | ||
519 | return false; | |
520 | } | |
521 | ||
d0737e1d ACO |
522 | /** |
523 | * Returns whether any output on the specified pipe will have the specified | |
524 | * type after a staged modeset is complete, i.e., the same as | |
525 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
526 | * encoder->crtc. | |
527 | */ | |
a93e255f ACO |
528 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
529 | int type) | |
d0737e1d | 530 | { |
a93e255f | 531 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 532 | struct drm_connector *connector; |
a93e255f | 533 | struct drm_connector_state *connector_state; |
d0737e1d | 534 | struct intel_encoder *encoder; |
a93e255f ACO |
535 | int i, num_connectors = 0; |
536 | ||
da3ced29 | 537 | for_each_connector_in_state(state, connector, connector_state, i) { |
a93e255f ACO |
538 | if (connector_state->crtc != crtc_state->base.crtc) |
539 | continue; | |
540 | ||
541 | num_connectors++; | |
d0737e1d | 542 | |
a93e255f ACO |
543 | encoder = to_intel_encoder(connector_state->best_encoder); |
544 | if (encoder->type == type) | |
d0737e1d | 545 | return true; |
a93e255f ACO |
546 | } |
547 | ||
548 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
549 | |
550 | return false; | |
551 | } | |
552 | ||
a93e255f ACO |
553 | static const intel_limit_t * |
554 | intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) | |
2c07245f | 555 | { |
a93e255f | 556 | struct drm_device *dev = crtc_state->base.crtc->dev; |
2c07245f | 557 | const intel_limit_t *limit; |
b91ad0ec | 558 | |
a93e255f | 559 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 560 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 561 | if (refclk == 100000) |
b91ad0ec ZW |
562 | limit = &intel_limits_ironlake_dual_lvds_100m; |
563 | else | |
564 | limit = &intel_limits_ironlake_dual_lvds; | |
565 | } else { | |
1b894b59 | 566 | if (refclk == 100000) |
b91ad0ec ZW |
567 | limit = &intel_limits_ironlake_single_lvds_100m; |
568 | else | |
569 | limit = &intel_limits_ironlake_single_lvds; | |
570 | } | |
c6bb3538 | 571 | } else |
b91ad0ec | 572 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
573 | |
574 | return limit; | |
575 | } | |
576 | ||
a93e255f ACO |
577 | static const intel_limit_t * |
578 | intel_g4x_limit(struct intel_crtc_state *crtc_state) | |
044c7c41 | 579 | { |
a93e255f | 580 | struct drm_device *dev = crtc_state->base.crtc->dev; |
044c7c41 ML |
581 | const intel_limit_t *limit; |
582 | ||
a93e255f | 583 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 584 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 585 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 586 | else |
e4b36699 | 587 | limit = &intel_limits_g4x_single_channel_lvds; |
a93e255f ACO |
588 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || |
589 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 590 | limit = &intel_limits_g4x_hdmi; |
a93e255f | 591 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 592 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 593 | } else /* The option is for other outputs */ |
e4b36699 | 594 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
595 | |
596 | return limit; | |
597 | } | |
598 | ||
a93e255f ACO |
599 | static const intel_limit_t * |
600 | intel_limit(struct intel_crtc_state *crtc_state, int refclk) | |
79e53945 | 601 | { |
a93e255f | 602 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 JB |
603 | const intel_limit_t *limit; |
604 | ||
5ab7b0b7 ID |
605 | if (IS_BROXTON(dev)) |
606 | limit = &intel_limits_bxt; | |
607 | else if (HAS_PCH_SPLIT(dev)) | |
a93e255f | 608 | limit = intel_ironlake_limit(crtc_state, refclk); |
2c07245f | 609 | else if (IS_G4X(dev)) { |
a93e255f | 610 | limit = intel_g4x_limit(crtc_state); |
f2b115e6 | 611 | } else if (IS_PINEVIEW(dev)) { |
a93e255f | 612 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 613 | limit = &intel_limits_pineview_lvds; |
2177832f | 614 | else |
f2b115e6 | 615 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
616 | } else if (IS_CHERRYVIEW(dev)) { |
617 | limit = &intel_limits_chv; | |
a0c4da24 | 618 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 619 | limit = &intel_limits_vlv; |
a6c45cf0 | 620 | } else if (!IS_GEN2(dev)) { |
a93e255f | 621 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
622 | limit = &intel_limits_i9xx_lvds; |
623 | else | |
624 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 625 | } else { |
a93e255f | 626 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
e4b36699 | 627 | limit = &intel_limits_i8xx_lvds; |
a93e255f | 628 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
e4b36699 | 629 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
630 | else |
631 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
632 | } |
633 | return limit; | |
634 | } | |
635 | ||
dccbea3b ID |
636 | /* |
637 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
638 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
639 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
640 | * The helpers' return value is the rate of the clock that is fed to the | |
641 | * display engine's pipe which can be the above fast dot clock rate or a | |
642 | * divided-down version of it. | |
643 | */ | |
f2b115e6 | 644 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
dccbea3b | 645 | static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock) |
79e53945 | 646 | { |
2177832f SL |
647 | clock->m = clock->m2 + 2; |
648 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 649 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 650 | return 0; |
fb03ac01 VS |
651 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
652 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
653 | |
654 | return clock->dot; | |
2177832f SL |
655 | } |
656 | ||
7429e9d4 DV |
657 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
658 | { | |
659 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
660 | } | |
661 | ||
dccbea3b | 662 | static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock) |
2177832f | 663 | { |
7429e9d4 | 664 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 665 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 666 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 667 | return 0; |
fb03ac01 VS |
668 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
669 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
670 | |
671 | return clock->dot; | |
79e53945 JB |
672 | } |
673 | ||
dccbea3b | 674 | static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock) |
589eca67 ID |
675 | { |
676 | clock->m = clock->m1 * clock->m2; | |
677 | clock->p = clock->p1 * clock->p2; | |
678 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 679 | return 0; |
589eca67 ID |
680 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
681 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
682 | |
683 | return clock->dot / 5; | |
589eca67 ID |
684 | } |
685 | ||
dccbea3b | 686 | int chv_calc_dpll_params(int refclk, intel_clock_t *clock) |
ef9348c8 CML |
687 | { |
688 | clock->m = clock->m1 * clock->m2; | |
689 | clock->p = clock->p1 * clock->p2; | |
690 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 691 | return 0; |
ef9348c8 CML |
692 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
693 | clock->n << 22); | |
694 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
695 | |
696 | return clock->dot / 5; | |
ef9348c8 CML |
697 | } |
698 | ||
7c04d1d9 | 699 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
700 | /** |
701 | * Returns whether the given set of divisors are valid for a given refclk with | |
702 | * the given connectors. | |
703 | */ | |
704 | ||
1b894b59 CW |
705 | static bool intel_PLL_is_valid(struct drm_device *dev, |
706 | const intel_limit_t *limit, | |
707 | const intel_clock_t *clock) | |
79e53945 | 708 | { |
f01b7962 VS |
709 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
710 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 711 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 712 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 713 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 714 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 715 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 716 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 717 | |
666a4537 WB |
718 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && |
719 | !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) | |
f01b7962 VS |
720 | if (clock->m1 <= clock->m2) |
721 | INTELPllInvalid("m1 <= m2\n"); | |
722 | ||
666a4537 | 723 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
724 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
725 | INTELPllInvalid("p out of range\n"); | |
726 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
727 | INTELPllInvalid("m out of range\n"); | |
728 | } | |
729 | ||
79e53945 | 730 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 731 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
732 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
733 | * connector, etc., rather than just a single range. | |
734 | */ | |
735 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 736 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
737 | |
738 | return true; | |
739 | } | |
740 | ||
3b1429d9 VS |
741 | static int |
742 | i9xx_select_p2_div(const intel_limit_t *limit, | |
743 | const struct intel_crtc_state *crtc_state, | |
744 | int target) | |
79e53945 | 745 | { |
3b1429d9 | 746 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 747 | |
a93e255f | 748 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 749 | /* |
a210b028 DV |
750 | * For LVDS just rely on its current settings for dual-channel. |
751 | * We haven't figured out how to reliably set up different | |
752 | * single/dual channel state, if we even can. | |
79e53945 | 753 | */ |
1974cad0 | 754 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 755 | return limit->p2.p2_fast; |
79e53945 | 756 | else |
3b1429d9 | 757 | return limit->p2.p2_slow; |
79e53945 JB |
758 | } else { |
759 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 760 | return limit->p2.p2_slow; |
79e53945 | 761 | else |
3b1429d9 | 762 | return limit->p2.p2_fast; |
79e53945 | 763 | } |
3b1429d9 VS |
764 | } |
765 | ||
766 | static bool | |
767 | i9xx_find_best_dpll(const intel_limit_t *limit, | |
768 | struct intel_crtc_state *crtc_state, | |
769 | int target, int refclk, intel_clock_t *match_clock, | |
770 | intel_clock_t *best_clock) | |
771 | { | |
772 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
773 | intel_clock_t clock; | |
774 | int err = target; | |
79e53945 | 775 | |
0206e353 | 776 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 777 | |
3b1429d9 VS |
778 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
779 | ||
42158660 ZY |
780 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
781 | clock.m1++) { | |
782 | for (clock.m2 = limit->m2.min; | |
783 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 784 | if (clock.m2 >= clock.m1) |
42158660 ZY |
785 | break; |
786 | for (clock.n = limit->n.min; | |
787 | clock.n <= limit->n.max; clock.n++) { | |
788 | for (clock.p1 = limit->p1.min; | |
789 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
790 | int this_err; |
791 | ||
dccbea3b | 792 | i9xx_calc_dpll_params(refclk, &clock); |
ac58c3f0 DV |
793 | if (!intel_PLL_is_valid(dev, limit, |
794 | &clock)) | |
795 | continue; | |
796 | if (match_clock && | |
797 | clock.p != match_clock->p) | |
798 | continue; | |
799 | ||
800 | this_err = abs(clock.dot - target); | |
801 | if (this_err < err) { | |
802 | *best_clock = clock; | |
803 | err = this_err; | |
804 | } | |
805 | } | |
806 | } | |
807 | } | |
808 | } | |
809 | ||
810 | return (err != target); | |
811 | } | |
812 | ||
813 | static bool | |
a93e255f ACO |
814 | pnv_find_best_dpll(const intel_limit_t *limit, |
815 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
816 | int target, int refclk, intel_clock_t *match_clock, |
817 | intel_clock_t *best_clock) | |
79e53945 | 818 | { |
3b1429d9 | 819 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 820 | intel_clock_t clock; |
79e53945 JB |
821 | int err = target; |
822 | ||
0206e353 | 823 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 824 | |
3b1429d9 VS |
825 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
826 | ||
42158660 ZY |
827 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
828 | clock.m1++) { | |
829 | for (clock.m2 = limit->m2.min; | |
830 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
831 | for (clock.n = limit->n.min; |
832 | clock.n <= limit->n.max; clock.n++) { | |
833 | for (clock.p1 = limit->p1.min; | |
834 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
835 | int this_err; |
836 | ||
dccbea3b | 837 | pnv_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
838 | if (!intel_PLL_is_valid(dev, limit, |
839 | &clock)) | |
79e53945 | 840 | continue; |
cec2f356 SP |
841 | if (match_clock && |
842 | clock.p != match_clock->p) | |
843 | continue; | |
79e53945 JB |
844 | |
845 | this_err = abs(clock.dot - target); | |
846 | if (this_err < err) { | |
847 | *best_clock = clock; | |
848 | err = this_err; | |
849 | } | |
850 | } | |
851 | } | |
852 | } | |
853 | } | |
854 | ||
855 | return (err != target); | |
856 | } | |
857 | ||
d4906093 | 858 | static bool |
a93e255f ACO |
859 | g4x_find_best_dpll(const intel_limit_t *limit, |
860 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
861 | int target, int refclk, intel_clock_t *match_clock, |
862 | intel_clock_t *best_clock) | |
d4906093 | 863 | { |
3b1429d9 | 864 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d4906093 ML |
865 | intel_clock_t clock; |
866 | int max_n; | |
3b1429d9 | 867 | bool found = false; |
6ba770dc AJ |
868 | /* approximately equals target * 0.00585 */ |
869 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
870 | |
871 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
872 | |
873 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
874 | ||
d4906093 | 875 | max_n = limit->n.max; |
f77f13e2 | 876 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 877 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 878 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
879 | for (clock.m1 = limit->m1.max; |
880 | clock.m1 >= limit->m1.min; clock.m1--) { | |
881 | for (clock.m2 = limit->m2.max; | |
882 | clock.m2 >= limit->m2.min; clock.m2--) { | |
883 | for (clock.p1 = limit->p1.max; | |
884 | clock.p1 >= limit->p1.min; clock.p1--) { | |
885 | int this_err; | |
886 | ||
dccbea3b | 887 | i9xx_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
888 | if (!intel_PLL_is_valid(dev, limit, |
889 | &clock)) | |
d4906093 | 890 | continue; |
1b894b59 CW |
891 | |
892 | this_err = abs(clock.dot - target); | |
d4906093 ML |
893 | if (this_err < err_most) { |
894 | *best_clock = clock; | |
895 | err_most = this_err; | |
896 | max_n = clock.n; | |
897 | found = true; | |
898 | } | |
899 | } | |
900 | } | |
901 | } | |
902 | } | |
2c07245f ZW |
903 | return found; |
904 | } | |
905 | ||
d5dd62bd ID |
906 | /* |
907 | * Check if the calculated PLL configuration is more optimal compared to the | |
908 | * best configuration and error found so far. Return the calculated error. | |
909 | */ | |
910 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
911 | const intel_clock_t *calculated_clock, | |
912 | const intel_clock_t *best_clock, | |
913 | unsigned int best_error_ppm, | |
914 | unsigned int *error_ppm) | |
915 | { | |
9ca3ba01 ID |
916 | /* |
917 | * For CHV ignore the error and consider only the P value. | |
918 | * Prefer a bigger P value based on HW requirements. | |
919 | */ | |
920 | if (IS_CHERRYVIEW(dev)) { | |
921 | *error_ppm = 0; | |
922 | ||
923 | return calculated_clock->p > best_clock->p; | |
924 | } | |
925 | ||
24be4e46 ID |
926 | if (WARN_ON_ONCE(!target_freq)) |
927 | return false; | |
928 | ||
d5dd62bd ID |
929 | *error_ppm = div_u64(1000000ULL * |
930 | abs(target_freq - calculated_clock->dot), | |
931 | target_freq); | |
932 | /* | |
933 | * Prefer a better P value over a better (smaller) error if the error | |
934 | * is small. Ensure this preference for future configurations too by | |
935 | * setting the error to 0. | |
936 | */ | |
937 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
938 | *error_ppm = 0; | |
939 | ||
940 | return true; | |
941 | } | |
942 | ||
943 | return *error_ppm + 10 < best_error_ppm; | |
944 | } | |
945 | ||
a0c4da24 | 946 | static bool |
a93e255f ACO |
947 | vlv_find_best_dpll(const intel_limit_t *limit, |
948 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
949 | int target, int refclk, intel_clock_t *match_clock, |
950 | intel_clock_t *best_clock) | |
a0c4da24 | 951 | { |
a93e255f | 952 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 953 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 954 | intel_clock_t clock; |
69e4f900 | 955 | unsigned int bestppm = 1000000; |
27e639bf VS |
956 | /* min update 19.2 MHz */ |
957 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 958 | bool found = false; |
a0c4da24 | 959 | |
6b4bf1c4 VS |
960 | target *= 5; /* fast clock */ |
961 | ||
962 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
963 | |
964 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 965 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 966 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 967 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 968 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 969 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 970 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 971 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 972 | unsigned int ppm; |
69e4f900 | 973 | |
6b4bf1c4 VS |
974 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
975 | refclk * clock.m1); | |
976 | ||
dccbea3b | 977 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 978 | |
f01b7962 VS |
979 | if (!intel_PLL_is_valid(dev, limit, |
980 | &clock)) | |
43b0ac53 VS |
981 | continue; |
982 | ||
d5dd62bd ID |
983 | if (!vlv_PLL_is_optimal(dev, target, |
984 | &clock, | |
985 | best_clock, | |
986 | bestppm, &ppm)) | |
987 | continue; | |
6b4bf1c4 | 988 | |
d5dd62bd ID |
989 | *best_clock = clock; |
990 | bestppm = ppm; | |
991 | found = true; | |
a0c4da24 JB |
992 | } |
993 | } | |
994 | } | |
995 | } | |
a0c4da24 | 996 | |
49e497ef | 997 | return found; |
a0c4da24 | 998 | } |
a4fc5ed6 | 999 | |
ef9348c8 | 1000 | static bool |
a93e255f ACO |
1001 | chv_find_best_dpll(const intel_limit_t *limit, |
1002 | struct intel_crtc_state *crtc_state, | |
ef9348c8 CML |
1003 | int target, int refclk, intel_clock_t *match_clock, |
1004 | intel_clock_t *best_clock) | |
1005 | { | |
a93e255f | 1006 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 1007 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 1008 | unsigned int best_error_ppm; |
ef9348c8 CML |
1009 | intel_clock_t clock; |
1010 | uint64_t m2; | |
1011 | int found = false; | |
1012 | ||
1013 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 1014 | best_error_ppm = 1000000; |
ef9348c8 CML |
1015 | |
1016 | /* | |
1017 | * Based on hardware doc, the n always set to 1, and m1 always | |
1018 | * set to 2. If requires to support 200Mhz refclk, we need to | |
1019 | * revisit this because n may not 1 anymore. | |
1020 | */ | |
1021 | clock.n = 1, clock.m1 = 2; | |
1022 | target *= 5; /* fast clock */ | |
1023 | ||
1024 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
1025 | for (clock.p2 = limit->p2.p2_fast; | |
1026 | clock.p2 >= limit->p2.p2_slow; | |
1027 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 1028 | unsigned int error_ppm; |
ef9348c8 CML |
1029 | |
1030 | clock.p = clock.p1 * clock.p2; | |
1031 | ||
1032 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
1033 | clock.n) << 22, refclk * clock.m1); | |
1034 | ||
1035 | if (m2 > INT_MAX/clock.m1) | |
1036 | continue; | |
1037 | ||
1038 | clock.m2 = m2; | |
1039 | ||
dccbea3b | 1040 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 CML |
1041 | |
1042 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
1043 | continue; | |
1044 | ||
9ca3ba01 ID |
1045 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
1046 | best_error_ppm, &error_ppm)) | |
1047 | continue; | |
1048 | ||
1049 | *best_clock = clock; | |
1050 | best_error_ppm = error_ppm; | |
1051 | found = true; | |
ef9348c8 CML |
1052 | } |
1053 | } | |
1054 | ||
1055 | return found; | |
1056 | } | |
1057 | ||
5ab7b0b7 ID |
1058 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
1059 | intel_clock_t *best_clock) | |
1060 | { | |
1061 | int refclk = i9xx_get_refclk(crtc_state, 0); | |
1062 | ||
1063 | return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state, | |
1064 | target_clock, refclk, NULL, best_clock); | |
1065 | } | |
1066 | ||
20ddf665 VS |
1067 | bool intel_crtc_active(struct drm_crtc *crtc) |
1068 | { | |
1069 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1070 | ||
1071 | /* Be paranoid as we can arrive here with only partial | |
1072 | * state retrieved from the hardware during setup. | |
1073 | * | |
241bfc38 | 1074 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1075 | * as Haswell has gained clock readout/fastboot support. |
1076 | * | |
66e514c1 | 1077 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1078 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1079 | * |
1080 | * FIXME: The intel_crtc->active here should be switched to | |
1081 | * crtc->state->active once we have proper CRTC states wired up | |
1082 | * for atomic. | |
20ddf665 | 1083 | */ |
c3d1f436 | 1084 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1085 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1086 | } |
1087 | ||
a5c961d1 PZ |
1088 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1089 | enum pipe pipe) | |
1090 | { | |
1091 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1092 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1093 | ||
6e3c9717 | 1094 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1095 | } |
1096 | ||
fbf49ea2 VS |
1097 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1098 | { | |
1099 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1100 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1101 | u32 line1, line2; |
1102 | u32 line_mask; | |
1103 | ||
1104 | if (IS_GEN2(dev)) | |
1105 | line_mask = DSL_LINEMASK_GEN2; | |
1106 | else | |
1107 | line_mask = DSL_LINEMASK_GEN3; | |
1108 | ||
1109 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1110 | msleep(5); |
fbf49ea2 VS |
1111 | line2 = I915_READ(reg) & line_mask; |
1112 | ||
1113 | return line1 == line2; | |
1114 | } | |
1115 | ||
ab7ad7f6 KP |
1116 | /* |
1117 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1118 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1119 | * |
1120 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1121 | * spinning on the vblank interrupt status bit, since we won't actually | |
1122 | * see an interrupt when the pipe is disabled. | |
1123 | * | |
ab7ad7f6 KP |
1124 | * On Gen4 and above: |
1125 | * wait for the pipe register state bit to turn off | |
1126 | * | |
1127 | * Otherwise: | |
1128 | * wait for the display line value to settle (it usually | |
1129 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1130 | * |
9d0498a2 | 1131 | */ |
575f7ab7 | 1132 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1133 | { |
575f7ab7 | 1134 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1135 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1136 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1137 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1138 | |
1139 | if (INTEL_INFO(dev)->gen >= 4) { | |
f0f59a00 | 1140 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1141 | |
1142 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1143 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1144 | 100)) | |
284637d9 | 1145 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1146 | } else { |
ab7ad7f6 | 1147 | /* Wait for the display line to settle */ |
fbf49ea2 | 1148 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1149 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1150 | } |
79e53945 JB |
1151 | } |
1152 | ||
b24e7179 | 1153 | /* Only for pre-ILK configs */ |
55607e8a DV |
1154 | void assert_pll(struct drm_i915_private *dev_priv, |
1155 | enum pipe pipe, bool state) | |
b24e7179 | 1156 | { |
b24e7179 JB |
1157 | u32 val; |
1158 | bool cur_state; | |
1159 | ||
649636ef | 1160 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1161 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1162 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1163 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1164 | onoff(state), onoff(cur_state)); |
b24e7179 | 1165 | } |
b24e7179 | 1166 | |
23538ef1 JN |
1167 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1168 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1169 | { | |
1170 | u32 val; | |
1171 | bool cur_state; | |
1172 | ||
a580516d | 1173 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1174 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1175 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1176 | |
1177 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1178 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1179 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1180 | onoff(state), onoff(cur_state)); |
23538ef1 JN |
1181 | } |
1182 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1183 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1184 | ||
55607e8a | 1185 | struct intel_shared_dpll * |
e2b78267 DV |
1186 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1187 | { | |
1188 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1189 | ||
6e3c9717 | 1190 | if (crtc->config->shared_dpll < 0) |
e2b78267 DV |
1191 | return NULL; |
1192 | ||
6e3c9717 | 1193 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
e2b78267 DV |
1194 | } |
1195 | ||
040484af | 1196 | /* For ILK+ */ |
55607e8a DV |
1197 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1198 | struct intel_shared_dpll *pll, | |
1199 | bool state) | |
040484af | 1200 | { |
040484af | 1201 | bool cur_state; |
5358901f | 1202 | struct intel_dpll_hw_state hw_state; |
040484af | 1203 | |
87ad3212 | 1204 | if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state))) |
ee7b9f93 | 1205 | return; |
ee7b9f93 | 1206 | |
5358901f | 1207 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
e2c719b7 | 1208 | I915_STATE_WARN(cur_state != state, |
5358901f | 1209 | "%s assertion failure (expected %s, current %s)\n", |
87ad3212 | 1210 | pll->name, onoff(state), onoff(cur_state)); |
040484af | 1211 | } |
040484af JB |
1212 | |
1213 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1214 | enum pipe pipe, bool state) | |
1215 | { | |
040484af | 1216 | bool cur_state; |
ad80a810 PZ |
1217 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1218 | pipe); | |
040484af | 1219 | |
affa9354 PZ |
1220 | if (HAS_DDI(dev_priv->dev)) { |
1221 | /* DDI does not have a specific FDI_TX register */ | |
649636ef | 1222 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1223 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1224 | } else { |
649636ef | 1225 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1226 | cur_state = !!(val & FDI_TX_ENABLE); |
1227 | } | |
e2c719b7 | 1228 | I915_STATE_WARN(cur_state != state, |
040484af | 1229 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1230 | onoff(state), onoff(cur_state)); |
040484af JB |
1231 | } |
1232 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1233 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1234 | ||
1235 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1236 | enum pipe pipe, bool state) | |
1237 | { | |
040484af JB |
1238 | u32 val; |
1239 | bool cur_state; | |
1240 | ||
649636ef | 1241 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1242 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1243 | I915_STATE_WARN(cur_state != state, |
040484af | 1244 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1245 | onoff(state), onoff(cur_state)); |
040484af JB |
1246 | } |
1247 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1248 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1249 | ||
1250 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1251 | enum pipe pipe) | |
1252 | { | |
040484af JB |
1253 | u32 val; |
1254 | ||
1255 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1256 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1257 | return; |
1258 | ||
bf507ef7 | 1259 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1260 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1261 | return; |
1262 | ||
649636ef | 1263 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1264 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1265 | } |
1266 | ||
55607e8a DV |
1267 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1268 | enum pipe pipe, bool state) | |
040484af | 1269 | { |
040484af | 1270 | u32 val; |
55607e8a | 1271 | bool cur_state; |
040484af | 1272 | |
649636ef | 1273 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1274 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1275 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1276 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1277 | onoff(state), onoff(cur_state)); |
040484af JB |
1278 | } |
1279 | ||
b680c37a DV |
1280 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1281 | enum pipe pipe) | |
ea0760cf | 1282 | { |
bedd4dba | 1283 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 | 1284 | i915_reg_t pp_reg; |
ea0760cf JB |
1285 | u32 val; |
1286 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1287 | bool locked = true; |
ea0760cf | 1288 | |
bedd4dba JN |
1289 | if (WARN_ON(HAS_DDI(dev))) |
1290 | return; | |
1291 | ||
1292 | if (HAS_PCH_SPLIT(dev)) { | |
1293 | u32 port_sel; | |
1294 | ||
ea0760cf | 1295 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1296 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1297 | ||
1298 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1299 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1300 | panel_pipe = PIPE_B; | |
1301 | /* XXX: else fix for eDP */ | |
666a4537 | 1302 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
bedd4dba JN |
1303 | /* presumably write lock depends on pipe, not port select */ |
1304 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1305 | panel_pipe = pipe; | |
ea0760cf JB |
1306 | } else { |
1307 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1308 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1309 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1310 | } |
1311 | ||
1312 | val = I915_READ(pp_reg); | |
1313 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1314 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1315 | locked = false; |
1316 | ||
e2c719b7 | 1317 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1318 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1319 | pipe_name(pipe)); |
ea0760cf JB |
1320 | } |
1321 | ||
93ce0ba6 JN |
1322 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1323 | enum pipe pipe, bool state) | |
1324 | { | |
1325 | struct drm_device *dev = dev_priv->dev; | |
1326 | bool cur_state; | |
1327 | ||
d9d82081 | 1328 | if (IS_845G(dev) || IS_I865G(dev)) |
0b87c24e | 1329 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1330 | else |
5efb3e28 | 1331 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1332 | |
e2c719b7 | 1333 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1334 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1335 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1336 | } |
1337 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1338 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1339 | ||
b840d907 JB |
1340 | void assert_pipe(struct drm_i915_private *dev_priv, |
1341 | enum pipe pipe, bool state) | |
b24e7179 | 1342 | { |
63d7bbe9 | 1343 | bool cur_state; |
702e7a56 PZ |
1344 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1345 | pipe); | |
b24e7179 | 1346 | |
b6b5d049 VS |
1347 | /* if we need the pipe quirk it must be always on */ |
1348 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1349 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1350 | state = true; |
1351 | ||
f458ebbc | 1352 | if (!intel_display_power_is_enabled(dev_priv, |
b97186f0 | 1353 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1354 | cur_state = false; |
1355 | } else { | |
649636ef | 1356 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 PZ |
1357 | cur_state = !!(val & PIPECONF_ENABLE); |
1358 | } | |
1359 | ||
e2c719b7 | 1360 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1361 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1362 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1363 | } |
1364 | ||
931872fc CW |
1365 | static void assert_plane(struct drm_i915_private *dev_priv, |
1366 | enum plane plane, bool state) | |
b24e7179 | 1367 | { |
b24e7179 | 1368 | u32 val; |
931872fc | 1369 | bool cur_state; |
b24e7179 | 1370 | |
649636ef | 1371 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1372 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1373 | I915_STATE_WARN(cur_state != state, |
931872fc | 1374 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1375 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1376 | } |
1377 | ||
931872fc CW |
1378 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1379 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1380 | ||
b24e7179 JB |
1381 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1382 | enum pipe pipe) | |
1383 | { | |
653e1026 | 1384 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1385 | int i; |
b24e7179 | 1386 | |
653e1026 VS |
1387 | /* Primary planes are fixed to pipes on gen4+ */ |
1388 | if (INTEL_INFO(dev)->gen >= 4) { | |
649636ef | 1389 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1390 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1391 | "plane %c assertion failure, should be disabled but not\n", |
1392 | plane_name(pipe)); | |
19ec1358 | 1393 | return; |
28c05794 | 1394 | } |
19ec1358 | 1395 | |
b24e7179 | 1396 | /* Need to check both planes against the pipe */ |
055e393f | 1397 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1398 | u32 val = I915_READ(DSPCNTR(i)); |
1399 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1400 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1401 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1402 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1403 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1404 | } |
1405 | } | |
1406 | ||
19332d7a JB |
1407 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1408 | enum pipe pipe) | |
1409 | { | |
20674eef | 1410 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1411 | int sprite; |
19332d7a | 1412 | |
7feb8b88 | 1413 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1414 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1415 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1416 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1417 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1418 | sprite, pipe_name(pipe)); | |
1419 | } | |
666a4537 | 1420 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
3bdcfc0c | 1421 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1422 | u32 val = I915_READ(SPCNTR(pipe, sprite)); |
e2c719b7 | 1423 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1424 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1425 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1426 | } |
1427 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
649636ef | 1428 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1429 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1430 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1431 | plane_name(pipe), pipe_name(pipe)); |
1432 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
649636ef | 1433 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1434 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1435 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1436 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1437 | } |
1438 | } | |
1439 | ||
08c71e5e VS |
1440 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1441 | { | |
e2c719b7 | 1442 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1443 | drm_crtc_vblank_put(crtc); |
1444 | } | |
1445 | ||
89eff4be | 1446 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1447 | { |
1448 | u32 val; | |
1449 | bool enabled; | |
1450 | ||
e2c719b7 | 1451 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1452 | |
92f2584a JB |
1453 | val = I915_READ(PCH_DREF_CONTROL); |
1454 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1455 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
e2c719b7 | 1456 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
92f2584a JB |
1457 | } |
1458 | ||
ab9412ba DV |
1459 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1460 | enum pipe pipe) | |
92f2584a | 1461 | { |
92f2584a JB |
1462 | u32 val; |
1463 | bool enabled; | |
1464 | ||
649636ef | 1465 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1466 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1467 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1468 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1469 | pipe_name(pipe)); | |
92f2584a JB |
1470 | } |
1471 | ||
4e634389 KP |
1472 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1473 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1474 | { |
1475 | if ((val & DP_PORT_EN) == 0) | |
1476 | return false; | |
1477 | ||
1478 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
f0f59a00 | 1479 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1480 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1481 | return false; | |
44f37d1f CML |
1482 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1483 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1484 | return false; | |
f0575e92 KP |
1485 | } else { |
1486 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1487 | return false; | |
1488 | } | |
1489 | return true; | |
1490 | } | |
1491 | ||
1519b995 KP |
1492 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1493 | enum pipe pipe, u32 val) | |
1494 | { | |
dc0fa718 | 1495 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1496 | return false; |
1497 | ||
1498 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1499 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1500 | return false; |
44f37d1f CML |
1501 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1502 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1503 | return false; | |
1519b995 | 1504 | } else { |
dc0fa718 | 1505 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1506 | return false; |
1507 | } | |
1508 | return true; | |
1509 | } | |
1510 | ||
1511 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1512 | enum pipe pipe, u32 val) | |
1513 | { | |
1514 | if ((val & LVDS_PORT_EN) == 0) | |
1515 | return false; | |
1516 | ||
1517 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1518 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1519 | return false; | |
1520 | } else { | |
1521 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1522 | return false; | |
1523 | } | |
1524 | return true; | |
1525 | } | |
1526 | ||
1527 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1528 | enum pipe pipe, u32 val) | |
1529 | { | |
1530 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1531 | return false; | |
1532 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1533 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1534 | return false; | |
1535 | } else { | |
1536 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1537 | return false; | |
1538 | } | |
1539 | return true; | |
1540 | } | |
1541 | ||
291906f1 | 1542 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1543 | enum pipe pipe, i915_reg_t reg, |
1544 | u32 port_sel) | |
291906f1 | 1545 | { |
47a05eca | 1546 | u32 val = I915_READ(reg); |
e2c719b7 | 1547 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1548 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1549 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1550 | |
e2c719b7 | 1551 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1552 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1553 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1554 | } |
1555 | ||
1556 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1557 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1558 | { |
47a05eca | 1559 | u32 val = I915_READ(reg); |
e2c719b7 | 1560 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1561 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1562 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1563 | |
e2c719b7 | 1564 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1565 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1566 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1567 | } |
1568 | ||
1569 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1570 | enum pipe pipe) | |
1571 | { | |
291906f1 | 1572 | u32 val; |
291906f1 | 1573 | |
f0575e92 KP |
1574 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1575 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1576 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1577 | |
649636ef | 1578 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1579 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1580 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1581 | pipe_name(pipe)); |
291906f1 | 1582 | |
649636ef | 1583 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1584 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1585 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1586 | pipe_name(pipe)); |
291906f1 | 1587 | |
e2debe91 PZ |
1588 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1589 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1590 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1591 | } |
1592 | ||
d288f65f | 1593 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1594 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1595 | { |
426115cf DV |
1596 | struct drm_device *dev = crtc->base.dev; |
1597 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1598 | i915_reg_t reg = DPLL(crtc->pipe); |
d288f65f | 1599 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1600 | |
426115cf | 1601 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 | 1602 | |
87442f73 | 1603 | /* PLL is protected by panel, make sure we can write it */ |
6a9e7363 | 1604 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1605 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1606 | |
426115cf DV |
1607 | I915_WRITE(reg, dpll); |
1608 | POSTING_READ(reg); | |
1609 | udelay(150); | |
1610 | ||
1611 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1612 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1613 | ||
d288f65f | 1614 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1615 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1616 | |
1617 | /* We do this three times for luck */ | |
426115cf | 1618 | I915_WRITE(reg, dpll); |
87442f73 DV |
1619 | POSTING_READ(reg); |
1620 | udelay(150); /* wait for warmup */ | |
426115cf | 1621 | I915_WRITE(reg, dpll); |
87442f73 DV |
1622 | POSTING_READ(reg); |
1623 | udelay(150); /* wait for warmup */ | |
426115cf | 1624 | I915_WRITE(reg, dpll); |
87442f73 DV |
1625 | POSTING_READ(reg); |
1626 | udelay(150); /* wait for warmup */ | |
1627 | } | |
1628 | ||
d288f65f | 1629 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1630 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1631 | { |
1632 | struct drm_device *dev = crtc->base.dev; | |
1633 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1634 | int pipe = crtc->pipe; | |
1635 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1636 | u32 tmp; |
1637 | ||
1638 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1639 | ||
a580516d | 1640 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1641 | |
1642 | /* Enable back the 10bit clock to display controller */ | |
1643 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1644 | tmp |= DPIO_DCLKP_EN; | |
1645 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1646 | ||
54433e91 VS |
1647 | mutex_unlock(&dev_priv->sb_lock); |
1648 | ||
9d556c99 CML |
1649 | /* |
1650 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1651 | */ | |
1652 | udelay(1); | |
1653 | ||
1654 | /* Enable PLL */ | |
d288f65f | 1655 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1656 | |
1657 | /* Check PLL is locked */ | |
a11b0703 | 1658 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1659 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1660 | ||
a11b0703 | 1661 | /* not sure when this should be written */ |
d288f65f | 1662 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 | 1663 | POSTING_READ(DPLL_MD(pipe)); |
9d556c99 CML |
1664 | } |
1665 | ||
1c4e0274 VS |
1666 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1667 | { | |
1668 | struct intel_crtc *crtc; | |
1669 | int count = 0; | |
1670 | ||
1671 | for_each_intel_crtc(dev, crtc) | |
3538b9df | 1672 | count += crtc->base.state->active && |
409ee761 | 1673 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1674 | |
1675 | return count; | |
1676 | } | |
1677 | ||
66e3d5c0 | 1678 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1679 | { |
66e3d5c0 DV |
1680 | struct drm_device *dev = crtc->base.dev; |
1681 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1682 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1683 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1684 | |
66e3d5c0 | 1685 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1686 | |
63d7bbe9 | 1687 | /* No really, not for ILK+ */ |
3d13ef2e | 1688 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1689 | |
1690 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1691 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1692 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1693 | |
1c4e0274 VS |
1694 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1695 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1696 | /* | |
1697 | * It appears to be important that we don't enable this | |
1698 | * for the current pipe before otherwise configuring the | |
1699 | * PLL. No idea how this should be handled if multiple | |
1700 | * DVO outputs are enabled simultaneosly. | |
1701 | */ | |
1702 | dpll |= DPLL_DVO_2X_MODE; | |
1703 | I915_WRITE(DPLL(!crtc->pipe), | |
1704 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1705 | } | |
66e3d5c0 | 1706 | |
c2b63374 VS |
1707 | /* |
1708 | * Apparently we need to have VGA mode enabled prior to changing | |
1709 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1710 | * dividers, even though the register value does change. | |
1711 | */ | |
1712 | I915_WRITE(reg, 0); | |
1713 | ||
8e7a65aa VS |
1714 | I915_WRITE(reg, dpll); |
1715 | ||
66e3d5c0 DV |
1716 | /* Wait for the clocks to stabilize. */ |
1717 | POSTING_READ(reg); | |
1718 | udelay(150); | |
1719 | ||
1720 | if (INTEL_INFO(dev)->gen >= 4) { | |
1721 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1722 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1723 | } else { |
1724 | /* The pixel multiplier can only be updated once the | |
1725 | * DPLL is enabled and the clocks are stable. | |
1726 | * | |
1727 | * So write it again. | |
1728 | */ | |
1729 | I915_WRITE(reg, dpll); | |
1730 | } | |
63d7bbe9 JB |
1731 | |
1732 | /* We do this three times for luck */ | |
66e3d5c0 | 1733 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1734 | POSTING_READ(reg); |
1735 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1736 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1737 | POSTING_READ(reg); |
1738 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1739 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1740 | POSTING_READ(reg); |
1741 | udelay(150); /* wait for warmup */ | |
1742 | } | |
1743 | ||
1744 | /** | |
50b44a44 | 1745 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1746 | * @dev_priv: i915 private structure |
1747 | * @pipe: pipe PLL to disable | |
1748 | * | |
1749 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1750 | * | |
1751 | * Note! This is for pre-ILK only. | |
1752 | */ | |
1c4e0274 | 1753 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1754 | { |
1c4e0274 VS |
1755 | struct drm_device *dev = crtc->base.dev; |
1756 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1757 | enum pipe pipe = crtc->pipe; | |
1758 | ||
1759 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1760 | if (IS_I830(dev) && | |
409ee761 | 1761 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
3538b9df | 1762 | !intel_num_dvo_pipes(dev)) { |
1c4e0274 VS |
1763 | I915_WRITE(DPLL(PIPE_B), |
1764 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1765 | I915_WRITE(DPLL(PIPE_A), | |
1766 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1767 | } | |
1768 | ||
b6b5d049 VS |
1769 | /* Don't disable pipe or pipe PLLs if needed */ |
1770 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1771 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1772 | return; |
1773 | ||
1774 | /* Make sure the pipe isn't still relying on us */ | |
1775 | assert_pipe_disabled(dev_priv, pipe); | |
1776 | ||
b8afb911 | 1777 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1778 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1779 | } |
1780 | ||
f6071166 JB |
1781 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1782 | { | |
b8afb911 | 1783 | u32 val; |
f6071166 JB |
1784 | |
1785 | /* Make sure the pipe isn't still relying on us */ | |
1786 | assert_pipe_disabled(dev_priv, pipe); | |
1787 | ||
e5cbfbfb ID |
1788 | /* |
1789 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1790 | * The latter is needed for VGA hotplug / manual detection. | |
1791 | */ | |
b8afb911 | 1792 | val = DPLL_VGA_MODE_DIS; |
f6071166 | 1793 | if (pipe == PIPE_B) |
60bfe44f | 1794 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV; |
f6071166 JB |
1795 | I915_WRITE(DPLL(pipe), val); |
1796 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1797 | |
1798 | } | |
1799 | ||
1800 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1801 | { | |
d752048d | 1802 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1803 | u32 val; |
1804 | ||
a11b0703 VS |
1805 | /* Make sure the pipe isn't still relying on us */ |
1806 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1807 | |
a11b0703 | 1808 | /* Set PLL en = 0 */ |
60bfe44f VS |
1809 | val = DPLL_SSC_REF_CLK_CHV | |
1810 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1811 | if (pipe != PIPE_A) |
1812 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1813 | I915_WRITE(DPLL(pipe), val); | |
1814 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1815 | |
a580516d | 1816 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1817 | |
1818 | /* Disable 10bit clock to display controller */ | |
1819 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1820 | val &= ~DPIO_DCLKP_EN; | |
1821 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1822 | ||
a580516d | 1823 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1824 | } |
1825 | ||
e4607fcf | 1826 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1827 | struct intel_digital_port *dport, |
1828 | unsigned int expected_mask) | |
89b667f8 JB |
1829 | { |
1830 | u32 port_mask; | |
f0f59a00 | 1831 | i915_reg_t dpll_reg; |
89b667f8 | 1832 | |
e4607fcf CML |
1833 | switch (dport->port) { |
1834 | case PORT_B: | |
89b667f8 | 1835 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1836 | dpll_reg = DPLL(0); |
e4607fcf CML |
1837 | break; |
1838 | case PORT_C: | |
89b667f8 | 1839 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1840 | dpll_reg = DPLL(0); |
9b6de0a1 | 1841 | expected_mask <<= 4; |
00fc31b7 CML |
1842 | break; |
1843 | case PORT_D: | |
1844 | port_mask = DPLL_PORTD_READY_MASK; | |
1845 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1846 | break; |
1847 | default: | |
1848 | BUG(); | |
1849 | } | |
89b667f8 | 1850 | |
9b6de0a1 VS |
1851 | if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) |
1852 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", | |
1853 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1854 | } |
1855 | ||
b14b1055 DV |
1856 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1857 | { | |
1858 | struct drm_device *dev = crtc->base.dev; | |
1859 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1860 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1861 | ||
be19f0ff CW |
1862 | if (WARN_ON(pll == NULL)) |
1863 | return; | |
1864 | ||
3e369b76 | 1865 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1866 | if (pll->active == 0) { |
1867 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1868 | WARN_ON(pll->on); | |
1869 | assert_shared_dpll_disabled(dev_priv, pll); | |
1870 | ||
1871 | pll->mode_set(dev_priv, pll); | |
1872 | } | |
1873 | } | |
1874 | ||
92f2584a | 1875 | /** |
85b3894f | 1876 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1877 | * @dev_priv: i915 private structure |
1878 | * @pipe: pipe PLL to enable | |
1879 | * | |
1880 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1881 | * drives the transcoder clock. | |
1882 | */ | |
85b3894f | 1883 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1884 | { |
3d13ef2e DL |
1885 | struct drm_device *dev = crtc->base.dev; |
1886 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1887 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1888 | |
87a875bb | 1889 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1890 | return; |
1891 | ||
3e369b76 | 1892 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1893 | return; |
ee7b9f93 | 1894 | |
74dd6928 | 1895 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1896 | pll->name, pll->active, pll->on, |
e2b78267 | 1897 | crtc->base.base.id); |
92f2584a | 1898 | |
cdbd2316 DV |
1899 | if (pll->active++) { |
1900 | WARN_ON(!pll->on); | |
e9d6944e | 1901 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1902 | return; |
1903 | } | |
f4a091c7 | 1904 | WARN_ON(pll->on); |
ee7b9f93 | 1905 | |
bd2bb1b9 PZ |
1906 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1907 | ||
46edb027 | 1908 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1909 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1910 | pll->on = true; |
92f2584a JB |
1911 | } |
1912 | ||
f6daaec2 | 1913 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1914 | { |
3d13ef2e DL |
1915 | struct drm_device *dev = crtc->base.dev; |
1916 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1917 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1918 | |
92f2584a | 1919 | /* PCH only available on ILK+ */ |
80aa9312 JB |
1920 | if (INTEL_INFO(dev)->gen < 5) |
1921 | return; | |
1922 | ||
eddfcbcd ML |
1923 | if (pll == NULL) |
1924 | return; | |
92f2584a | 1925 | |
eddfcbcd | 1926 | if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base))))) |
48da64a8 | 1927 | return; |
7a419866 | 1928 | |
46edb027 DV |
1929 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1930 | pll->name, pll->active, pll->on, | |
e2b78267 | 1931 | crtc->base.base.id); |
7a419866 | 1932 | |
48da64a8 | 1933 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1934 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1935 | return; |
1936 | } | |
1937 | ||
e9d6944e | 1938 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1939 | WARN_ON(!pll->on); |
cdbd2316 | 1940 | if (--pll->active) |
7a419866 | 1941 | return; |
ee7b9f93 | 1942 | |
46edb027 | 1943 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1944 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1945 | pll->on = false; |
bd2bb1b9 PZ |
1946 | |
1947 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1948 | } |
1949 | ||
b8a4f404 PZ |
1950 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1951 | enum pipe pipe) | |
040484af | 1952 | { |
23670b32 | 1953 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1954 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1955 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
f0f59a00 VS |
1956 | i915_reg_t reg; |
1957 | uint32_t val, pipeconf_val; | |
040484af JB |
1958 | |
1959 | /* PCH only available on ILK+ */ | |
55522f37 | 1960 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1961 | |
1962 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1963 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1964 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1965 | |
1966 | /* FDI must be feeding us bits for PCH ports */ | |
1967 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1968 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1969 | ||
23670b32 DV |
1970 | if (HAS_PCH_CPT(dev)) { |
1971 | /* Workaround: Set the timing override bit before enabling the | |
1972 | * pch transcoder. */ | |
1973 | reg = TRANS_CHICKEN2(pipe); | |
1974 | val = I915_READ(reg); | |
1975 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1976 | I915_WRITE(reg, val); | |
59c859d6 | 1977 | } |
23670b32 | 1978 | |
ab9412ba | 1979 | reg = PCH_TRANSCONF(pipe); |
040484af | 1980 | val = I915_READ(reg); |
5f7f726d | 1981 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1982 | |
1983 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1984 | /* | |
c5de7c6f VS |
1985 | * Make the BPC in transcoder be consistent with |
1986 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1987 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1988 | */ |
dfd07d72 | 1989 | val &= ~PIPECONF_BPC_MASK; |
c5de7c6f VS |
1990 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) |
1991 | val |= PIPECONF_8BPC; | |
1992 | else | |
1993 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1994 | } |
5f7f726d PZ |
1995 | |
1996 | val &= ~TRANS_INTERLACE_MASK; | |
1997 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 1998 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 1999 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
2000 | val |= TRANS_LEGACY_INTERLACED_ILK; |
2001 | else | |
2002 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
2003 | else |
2004 | val |= TRANS_PROGRESSIVE; | |
2005 | ||
040484af JB |
2006 | I915_WRITE(reg, val | TRANS_ENABLE); |
2007 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 2008 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
2009 | } |
2010 | ||
8fb033d7 | 2011 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 2012 | enum transcoder cpu_transcoder) |
040484af | 2013 | { |
8fb033d7 | 2014 | u32 val, pipeconf_val; |
8fb033d7 PZ |
2015 | |
2016 | /* PCH only available on ILK+ */ | |
55522f37 | 2017 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 2018 | |
8fb033d7 | 2019 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 2020 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 2021 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 2022 | |
223a6fdf | 2023 | /* Workaround: set timing override bit. */ |
36c0d0cf | 2024 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 2025 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 2026 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 2027 | |
25f3ef11 | 2028 | val = TRANS_ENABLE; |
937bb610 | 2029 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 2030 | |
9a76b1c6 PZ |
2031 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
2032 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 2033 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
2034 | else |
2035 | val |= TRANS_PROGRESSIVE; | |
2036 | ||
ab9412ba DV |
2037 | I915_WRITE(LPT_TRANSCONF, val); |
2038 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 2039 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
2040 | } |
2041 | ||
b8a4f404 PZ |
2042 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
2043 | enum pipe pipe) | |
040484af | 2044 | { |
23670b32 | 2045 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 VS |
2046 | i915_reg_t reg; |
2047 | uint32_t val; | |
040484af JB |
2048 | |
2049 | /* FDI relies on the transcoder */ | |
2050 | assert_fdi_tx_disabled(dev_priv, pipe); | |
2051 | assert_fdi_rx_disabled(dev_priv, pipe); | |
2052 | ||
291906f1 JB |
2053 | /* Ports must be off as well */ |
2054 | assert_pch_ports_disabled(dev_priv, pipe); | |
2055 | ||
ab9412ba | 2056 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
2057 | val = I915_READ(reg); |
2058 | val &= ~TRANS_ENABLE; | |
2059 | I915_WRITE(reg, val); | |
2060 | /* wait for PCH transcoder off, transcoder state */ | |
2061 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 2062 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 2063 | |
c465613b | 2064 | if (HAS_PCH_CPT(dev)) { |
23670b32 DV |
2065 | /* Workaround: Clear the timing override chicken bit again. */ |
2066 | reg = TRANS_CHICKEN2(pipe); | |
2067 | val = I915_READ(reg); | |
2068 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2069 | I915_WRITE(reg, val); | |
2070 | } | |
040484af JB |
2071 | } |
2072 | ||
ab4d966c | 2073 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 2074 | { |
8fb033d7 PZ |
2075 | u32 val; |
2076 | ||
ab9412ba | 2077 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 2078 | val &= ~TRANS_ENABLE; |
ab9412ba | 2079 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 2080 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 2081 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 2082 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
2083 | |
2084 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 2085 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 2086 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 2087 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
2088 | } |
2089 | ||
b24e7179 | 2090 | /** |
309cfea8 | 2091 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2092 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2093 | * |
0372264a | 2094 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2095 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2096 | */ |
e1fdc473 | 2097 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2098 | { |
0372264a PZ |
2099 | struct drm_device *dev = crtc->base.dev; |
2100 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2101 | enum pipe pipe = crtc->pipe; | |
1a70a728 | 2102 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
1a240d4d | 2103 | enum pipe pch_transcoder; |
f0f59a00 | 2104 | i915_reg_t reg; |
b24e7179 JB |
2105 | u32 val; |
2106 | ||
9e2ee2dd VS |
2107 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
2108 | ||
58c6eaa2 | 2109 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2110 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2111 | assert_sprites_disabled(dev_priv, pipe); |
2112 | ||
681e5811 | 2113 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2114 | pch_transcoder = TRANSCODER_A; |
2115 | else | |
2116 | pch_transcoder = pipe; | |
2117 | ||
b24e7179 JB |
2118 | /* |
2119 | * A pipe without a PLL won't actually be able to drive bits from | |
2120 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2121 | * need the check. | |
2122 | */ | |
50360403 | 2123 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) |
a65347ba | 2124 | if (crtc->config->has_dsi_encoder) |
23538ef1 JN |
2125 | assert_dsi_pll_enabled(dev_priv); |
2126 | else | |
2127 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2128 | else { |
6e3c9717 | 2129 | if (crtc->config->has_pch_encoder) { |
040484af | 2130 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2131 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2132 | assert_fdi_tx_pll_enabled(dev_priv, |
2133 | (enum pipe) cpu_transcoder); | |
040484af JB |
2134 | } |
2135 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2136 | } | |
b24e7179 | 2137 | |
702e7a56 | 2138 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2139 | val = I915_READ(reg); |
7ad25d48 | 2140 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2141 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2142 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2143 | return; |
7ad25d48 | 2144 | } |
00d70b15 CW |
2145 | |
2146 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2147 | POSTING_READ(reg); |
b7792d8b VS |
2148 | |
2149 | /* | |
2150 | * Until the pipe starts DSL will read as 0, which would cause | |
2151 | * an apparent vblank timestamp jump, which messes up also the | |
2152 | * frame count when it's derived from the timestamps. So let's | |
2153 | * wait for the pipe to start properly before we call | |
2154 | * drm_crtc_vblank_on() | |
2155 | */ | |
2156 | if (dev->max_vblank_count == 0 && | |
2157 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
2158 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
2159 | } |
2160 | ||
2161 | /** | |
309cfea8 | 2162 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2163 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2164 | * |
575f7ab7 VS |
2165 | * Disable the pipe of @crtc, making sure that various hardware |
2166 | * specific requirements are met, if applicable, e.g. plane | |
2167 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2168 | * |
2169 | * Will wait until the pipe has shut down before returning. | |
2170 | */ | |
575f7ab7 | 2171 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2172 | { |
575f7ab7 | 2173 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2174 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2175 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 2176 | i915_reg_t reg; |
b24e7179 JB |
2177 | u32 val; |
2178 | ||
9e2ee2dd VS |
2179 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2180 | ||
b24e7179 JB |
2181 | /* |
2182 | * Make sure planes won't keep trying to pump pixels to us, | |
2183 | * or we might hang the display. | |
2184 | */ | |
2185 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2186 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2187 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2188 | |
702e7a56 | 2189 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2190 | val = I915_READ(reg); |
00d70b15 CW |
2191 | if ((val & PIPECONF_ENABLE) == 0) |
2192 | return; | |
2193 | ||
67adc644 VS |
2194 | /* |
2195 | * Double wide has implications for planes | |
2196 | * so best keep it disabled when not needed. | |
2197 | */ | |
6e3c9717 | 2198 | if (crtc->config->double_wide) |
67adc644 VS |
2199 | val &= ~PIPECONF_DOUBLE_WIDE; |
2200 | ||
2201 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2202 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2203 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2204 | val &= ~PIPECONF_ENABLE; |
2205 | ||
2206 | I915_WRITE(reg, val); | |
2207 | if ((val & PIPECONF_ENABLE) == 0) | |
2208 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2209 | } |
2210 | ||
693db184 CW |
2211 | static bool need_vtd_wa(struct drm_device *dev) |
2212 | { | |
2213 | #ifdef CONFIG_INTEL_IOMMU | |
2214 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2215 | return true; | |
2216 | #endif | |
2217 | return false; | |
2218 | } | |
2219 | ||
832be82f VS |
2220 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
2221 | { | |
2222 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
2223 | } | |
2224 | ||
7b49f948 VS |
2225 | static unsigned int intel_tile_width(const struct drm_i915_private *dev_priv, |
2226 | uint64_t fb_modifier, unsigned int cpp) | |
2227 | { | |
2228 | switch (fb_modifier) { | |
2229 | case DRM_FORMAT_MOD_NONE: | |
2230 | return cpp; | |
2231 | case I915_FORMAT_MOD_X_TILED: | |
2232 | if (IS_GEN2(dev_priv)) | |
2233 | return 128; | |
2234 | else | |
2235 | return 512; | |
2236 | case I915_FORMAT_MOD_Y_TILED: | |
2237 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2238 | return 128; | |
2239 | else | |
2240 | return 512; | |
2241 | case I915_FORMAT_MOD_Yf_TILED: | |
2242 | switch (cpp) { | |
2243 | case 1: | |
2244 | return 64; | |
2245 | case 2: | |
2246 | case 4: | |
2247 | return 128; | |
2248 | case 8: | |
2249 | case 16: | |
2250 | return 256; | |
2251 | default: | |
2252 | MISSING_CASE(cpp); | |
2253 | return cpp; | |
2254 | } | |
2255 | break; | |
2256 | default: | |
2257 | MISSING_CASE(fb_modifier); | |
2258 | return cpp; | |
2259 | } | |
2260 | } | |
2261 | ||
832be82f VS |
2262 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
2263 | uint64_t fb_modifier, unsigned int cpp) | |
a57ce0b2 | 2264 | { |
832be82f VS |
2265 | if (fb_modifier == DRM_FORMAT_MOD_NONE) |
2266 | return 1; | |
2267 | else | |
2268 | return intel_tile_size(dev_priv) / | |
2269 | intel_tile_width(dev_priv, fb_modifier, cpp); | |
6761dd31 TU |
2270 | } |
2271 | ||
2272 | unsigned int | |
2273 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
832be82f | 2274 | uint32_t pixel_format, uint64_t fb_modifier) |
6761dd31 | 2275 | { |
832be82f VS |
2276 | unsigned int cpp = drm_format_plane_cpp(pixel_format, 0); |
2277 | unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp); | |
2278 | ||
2279 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2280 | } |
2281 | ||
75c82a53 | 2282 | static void |
f64b98cd TU |
2283 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, |
2284 | const struct drm_plane_state *plane_state) | |
2285 | { | |
832be82f | 2286 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
a6d09186 | 2287 | struct intel_rotation_info *info = &view->params.rotation_info; |
d9b3288e | 2288 | unsigned int tile_size, tile_width, tile_height, cpp; |
50470bb0 | 2289 | |
f64b98cd TU |
2290 | *view = i915_ggtt_view_normal; |
2291 | ||
50470bb0 | 2292 | if (!plane_state) |
75c82a53 | 2293 | return; |
50470bb0 | 2294 | |
121920fa | 2295 | if (!intel_rotation_90_or_270(plane_state->rotation)) |
75c82a53 | 2296 | return; |
50470bb0 | 2297 | |
9abc4648 | 2298 | *view = i915_ggtt_view_rotated; |
50470bb0 TU |
2299 | |
2300 | info->height = fb->height; | |
2301 | info->pixel_format = fb->pixel_format; | |
2302 | info->pitch = fb->pitches[0]; | |
89e3e142 | 2303 | info->uv_offset = fb->offsets[1]; |
50470bb0 TU |
2304 | info->fb_modifier = fb->modifier[0]; |
2305 | ||
d9b3288e VS |
2306 | tile_size = intel_tile_size(dev_priv); |
2307 | ||
2308 | cpp = drm_format_plane_cpp(fb->pixel_format, 0); | |
2309 | tile_width = intel_tile_width(dev_priv, cpp, fb->modifier[0]); | |
2310 | tile_height = tile_size / tile_width; | |
2311 | ||
2312 | info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_width); | |
84fe03f7 | 2313 | info->height_pages = DIV_ROUND_UP(fb->height, tile_height); |
d9b3288e | 2314 | info->size = info->width_pages * info->height_pages * tile_size; |
84fe03f7 | 2315 | |
89e3e142 | 2316 | if (info->pixel_format == DRM_FORMAT_NV12) { |
832be82f | 2317 | cpp = drm_format_plane_cpp(fb->pixel_format, 1); |
d9b3288e VS |
2318 | tile_width = intel_tile_width(dev_priv, fb->modifier[1], cpp); |
2319 | tile_height = tile_size / tile_width; | |
2320 | ||
2321 | info->width_pages_uv = DIV_ROUND_UP(fb->pitches[1], tile_width); | |
832be82f | 2322 | info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, tile_height); |
d9b3288e | 2323 | info->size_uv = info->width_pages_uv * info->height_pages_uv * tile_size; |
89e3e142 | 2324 | } |
f64b98cd TU |
2325 | } |
2326 | ||
603525d7 | 2327 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2328 | { |
2329 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2330 | return 256 * 1024; | |
985b8bb4 | 2331 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
666a4537 | 2332 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2333 | return 128 * 1024; |
2334 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2335 | return 4 * 1024; | |
2336 | else | |
44c5905e | 2337 | return 0; |
4e9a86b6 VS |
2338 | } |
2339 | ||
603525d7 VS |
2340 | static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv, |
2341 | uint64_t fb_modifier) | |
2342 | { | |
2343 | switch (fb_modifier) { | |
2344 | case DRM_FORMAT_MOD_NONE: | |
2345 | return intel_linear_alignment(dev_priv); | |
2346 | case I915_FORMAT_MOD_X_TILED: | |
2347 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2348 | return 256 * 1024; | |
2349 | return 0; | |
2350 | case I915_FORMAT_MOD_Y_TILED: | |
2351 | case I915_FORMAT_MOD_Yf_TILED: | |
2352 | return 1 * 1024 * 1024; | |
2353 | default: | |
2354 | MISSING_CASE(fb_modifier); | |
2355 | return 0; | |
2356 | } | |
2357 | } | |
2358 | ||
127bd2ac | 2359 | int |
850c4cdc TU |
2360 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2361 | struct drm_framebuffer *fb, | |
7580d774 | 2362 | const struct drm_plane_state *plane_state) |
6b95a207 | 2363 | { |
850c4cdc | 2364 | struct drm_device *dev = fb->dev; |
ce453d81 | 2365 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2366 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2367 | struct i915_ggtt_view view; |
6b95a207 KH |
2368 | u32 alignment; |
2369 | int ret; | |
2370 | ||
ebcdd39e MR |
2371 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2372 | ||
603525d7 | 2373 | alignment = intel_surf_alignment(dev_priv, fb->modifier[0]); |
6b95a207 | 2374 | |
75c82a53 | 2375 | intel_fill_fb_ggtt_view(&view, fb, plane_state); |
f64b98cd | 2376 | |
693db184 CW |
2377 | /* Note that the w/a also requires 64 PTE of padding following the |
2378 | * bo. We currently fill all unused PTE with the shadow page and so | |
2379 | * we should always have valid PTE following the scanout preventing | |
2380 | * the VT-d warning. | |
2381 | */ | |
2382 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2383 | alignment = 256 * 1024; | |
2384 | ||
d6dd6843 PZ |
2385 | /* |
2386 | * Global gtt pte registers are special registers which actually forward | |
2387 | * writes to a chunk of system memory. Which means that there is no risk | |
2388 | * that the register values disappear as soon as we call | |
2389 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2390 | * pin/unpin/fence and not more. | |
2391 | */ | |
2392 | intel_runtime_pm_get(dev_priv); | |
2393 | ||
7580d774 ML |
2394 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, |
2395 | &view); | |
48b956c5 | 2396 | if (ret) |
b26a6b35 | 2397 | goto err_pm; |
6b95a207 KH |
2398 | |
2399 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2400 | * fence, whereas 965+ only requires a fence if using | |
2401 | * framebuffer compression. For simplicity, we always install | |
2402 | * a fence as the cost is not that onerous. | |
2403 | */ | |
9807216f VK |
2404 | if (view.type == I915_GGTT_VIEW_NORMAL) { |
2405 | ret = i915_gem_object_get_fence(obj); | |
2406 | if (ret == -EDEADLK) { | |
2407 | /* | |
2408 | * -EDEADLK means there are no free fences | |
2409 | * no pending flips. | |
2410 | * | |
2411 | * This is propagated to atomic, but it uses | |
2412 | * -EDEADLK to force a locking recovery, so | |
2413 | * change the returned error to -EBUSY. | |
2414 | */ | |
2415 | ret = -EBUSY; | |
2416 | goto err_unpin; | |
2417 | } else if (ret) | |
2418 | goto err_unpin; | |
1690e1eb | 2419 | |
9807216f VK |
2420 | i915_gem_object_pin_fence(obj); |
2421 | } | |
6b95a207 | 2422 | |
d6dd6843 | 2423 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2424 | return 0; |
48b956c5 CW |
2425 | |
2426 | err_unpin: | |
f64b98cd | 2427 | i915_gem_object_unpin_from_display_plane(obj, &view); |
b26a6b35 | 2428 | err_pm: |
d6dd6843 | 2429 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2430 | return ret; |
6b95a207 KH |
2431 | } |
2432 | ||
82bc3b2d TU |
2433 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, |
2434 | const struct drm_plane_state *plane_state) | |
1690e1eb | 2435 | { |
82bc3b2d | 2436 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2437 | struct i915_ggtt_view view; |
82bc3b2d | 2438 | |
ebcdd39e MR |
2439 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2440 | ||
75c82a53 | 2441 | intel_fill_fb_ggtt_view(&view, fb, plane_state); |
f64b98cd | 2442 | |
9807216f VK |
2443 | if (view.type == I915_GGTT_VIEW_NORMAL) |
2444 | i915_gem_object_unpin_fence(obj); | |
2445 | ||
f64b98cd | 2446 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2447 | } |
2448 | ||
c2c75131 DV |
2449 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2450 | * is assumed to be a power-of-two. */ | |
ce1e5c14 VS |
2451 | unsigned long intel_compute_tile_offset(struct drm_i915_private *dev_priv, |
2452 | int *x, int *y, | |
2453 | uint64_t fb_modifier, | |
2454 | unsigned int cpp, | |
2455 | unsigned int pitch) | |
c2c75131 | 2456 | { |
b5c65338 | 2457 | if (fb_modifier != DRM_FORMAT_MOD_NONE) { |
d843310d | 2458 | unsigned int tile_size, tile_width, tile_height; |
bc752862 | 2459 | unsigned int tile_rows, tiles; |
c2c75131 | 2460 | |
d843310d VS |
2461 | tile_size = intel_tile_size(dev_priv); |
2462 | tile_width = intel_tile_width(dev_priv, fb_modifier, cpp); | |
2463 | tile_height = tile_size / tile_width; | |
2464 | ||
2465 | tile_rows = *y / tile_height; | |
2466 | *y %= tile_height; | |
c2c75131 | 2467 | |
d843310d VS |
2468 | tiles = *x / (tile_width/cpp); |
2469 | *x %= tile_width/cpp; | |
bc752862 | 2470 | |
d843310d | 2471 | return tile_rows * pitch * tile_height + tiles * tile_size; |
bc752862 | 2472 | } else { |
4e9a86b6 | 2473 | unsigned int alignment = intel_linear_alignment(dev_priv) - 1; |
bc752862 CW |
2474 | unsigned int offset; |
2475 | ||
2476 | offset = *y * pitch + *x * cpp; | |
4e9a86b6 VS |
2477 | *y = (offset & alignment) / pitch; |
2478 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
2479 | return offset & ~alignment; | |
bc752862 | 2480 | } |
c2c75131 DV |
2481 | } |
2482 | ||
b35d63fa | 2483 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2484 | { |
2485 | switch (format) { | |
2486 | case DISPPLANE_8BPP: | |
2487 | return DRM_FORMAT_C8; | |
2488 | case DISPPLANE_BGRX555: | |
2489 | return DRM_FORMAT_XRGB1555; | |
2490 | case DISPPLANE_BGRX565: | |
2491 | return DRM_FORMAT_RGB565; | |
2492 | default: | |
2493 | case DISPPLANE_BGRX888: | |
2494 | return DRM_FORMAT_XRGB8888; | |
2495 | case DISPPLANE_RGBX888: | |
2496 | return DRM_FORMAT_XBGR8888; | |
2497 | case DISPPLANE_BGRX101010: | |
2498 | return DRM_FORMAT_XRGB2101010; | |
2499 | case DISPPLANE_RGBX101010: | |
2500 | return DRM_FORMAT_XBGR2101010; | |
2501 | } | |
2502 | } | |
2503 | ||
bc8d7dff DL |
2504 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2505 | { | |
2506 | switch (format) { | |
2507 | case PLANE_CTL_FORMAT_RGB_565: | |
2508 | return DRM_FORMAT_RGB565; | |
2509 | default: | |
2510 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2511 | if (rgb_order) { | |
2512 | if (alpha) | |
2513 | return DRM_FORMAT_ABGR8888; | |
2514 | else | |
2515 | return DRM_FORMAT_XBGR8888; | |
2516 | } else { | |
2517 | if (alpha) | |
2518 | return DRM_FORMAT_ARGB8888; | |
2519 | else | |
2520 | return DRM_FORMAT_XRGB8888; | |
2521 | } | |
2522 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2523 | if (rgb_order) | |
2524 | return DRM_FORMAT_XBGR2101010; | |
2525 | else | |
2526 | return DRM_FORMAT_XRGB2101010; | |
2527 | } | |
2528 | } | |
2529 | ||
5724dbd1 | 2530 | static bool |
f6936e29 DV |
2531 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2532 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2533 | { |
2534 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2535 | struct drm_i915_private *dev_priv = to_i915(dev); |
46f297fb JB |
2536 | struct drm_i915_gem_object *obj = NULL; |
2537 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2538 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2539 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2540 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2541 | PAGE_SIZE); | |
2542 | ||
2543 | size_aligned -= base_aligned; | |
46f297fb | 2544 | |
ff2652ea CW |
2545 | if (plane_config->size == 0) |
2546 | return false; | |
2547 | ||
3badb49f PZ |
2548 | /* If the FB is too big, just don't use it since fbdev is not very |
2549 | * important and we should probably use that space with FBC or other | |
2550 | * features. */ | |
2551 | if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size) | |
2552 | return false; | |
2553 | ||
f37b5c2b DV |
2554 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2555 | base_aligned, | |
2556 | base_aligned, | |
2557 | size_aligned); | |
46f297fb | 2558 | if (!obj) |
484b41dd | 2559 | return false; |
46f297fb | 2560 | |
49af449b DL |
2561 | obj->tiling_mode = plane_config->tiling; |
2562 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2563 | obj->stride = fb->pitches[0]; |
46f297fb | 2564 | |
6bf129df DL |
2565 | mode_cmd.pixel_format = fb->pixel_format; |
2566 | mode_cmd.width = fb->width; | |
2567 | mode_cmd.height = fb->height; | |
2568 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2569 | mode_cmd.modifier[0] = fb->modifier[0]; |
2570 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb JB |
2571 | |
2572 | mutex_lock(&dev->struct_mutex); | |
6bf129df | 2573 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2574 | &mode_cmd, obj)) { |
46f297fb JB |
2575 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2576 | goto out_unref_obj; | |
2577 | } | |
46f297fb | 2578 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2579 | |
f6936e29 | 2580 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2581 | return true; |
46f297fb JB |
2582 | |
2583 | out_unref_obj: | |
2584 | drm_gem_object_unreference(&obj->base); | |
2585 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2586 | return false; |
2587 | } | |
2588 | ||
afd65eb4 MR |
2589 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2590 | static void | |
2591 | update_state_fb(struct drm_plane *plane) | |
2592 | { | |
2593 | if (plane->fb == plane->state->fb) | |
2594 | return; | |
2595 | ||
2596 | if (plane->state->fb) | |
2597 | drm_framebuffer_unreference(plane->state->fb); | |
2598 | plane->state->fb = plane->fb; | |
2599 | if (plane->state->fb) | |
2600 | drm_framebuffer_reference(plane->state->fb); | |
2601 | } | |
2602 | ||
5724dbd1 | 2603 | static void |
f6936e29 DV |
2604 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2605 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2606 | { |
2607 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2608 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2609 | struct drm_crtc *c; |
2610 | struct intel_crtc *i; | |
2ff8fde1 | 2611 | struct drm_i915_gem_object *obj; |
88595ac9 | 2612 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2613 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2614 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2615 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2616 | struct intel_plane_state *intel_state = |
2617 | to_intel_plane_state(plane_state); | |
88595ac9 | 2618 | struct drm_framebuffer *fb; |
484b41dd | 2619 | |
2d14030b | 2620 | if (!plane_config->fb) |
484b41dd JB |
2621 | return; |
2622 | ||
f6936e29 | 2623 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2624 | fb = &plane_config->fb->base; |
2625 | goto valid_fb; | |
f55548b5 | 2626 | } |
484b41dd | 2627 | |
2d14030b | 2628 | kfree(plane_config->fb); |
484b41dd JB |
2629 | |
2630 | /* | |
2631 | * Failed to alloc the obj, check to see if we should share | |
2632 | * an fb with another CRTC instead | |
2633 | */ | |
70e1e0ec | 2634 | for_each_crtc(dev, c) { |
484b41dd JB |
2635 | i = to_intel_crtc(c); |
2636 | ||
2637 | if (c == &intel_crtc->base) | |
2638 | continue; | |
2639 | ||
2ff8fde1 MR |
2640 | if (!i->active) |
2641 | continue; | |
2642 | ||
88595ac9 DV |
2643 | fb = c->primary->fb; |
2644 | if (!fb) | |
484b41dd JB |
2645 | continue; |
2646 | ||
88595ac9 | 2647 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2648 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2649 | drm_framebuffer_reference(fb); |
2650 | goto valid_fb; | |
484b41dd JB |
2651 | } |
2652 | } | |
88595ac9 | 2653 | |
200757f5 MR |
2654 | /* |
2655 | * We've failed to reconstruct the BIOS FB. Current display state | |
2656 | * indicates that the primary plane is visible, but has a NULL FB, | |
2657 | * which will lead to problems later if we don't fix it up. The | |
2658 | * simplest solution is to just disable the primary plane now and | |
2659 | * pretend the BIOS never had it enabled. | |
2660 | */ | |
2661 | to_intel_plane_state(plane_state)->visible = false; | |
2662 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); | |
2663 | intel_pre_disable_primary(&intel_crtc->base); | |
2664 | intel_plane->disable_plane(primary, &intel_crtc->base); | |
2665 | ||
88595ac9 DV |
2666 | return; |
2667 | ||
2668 | valid_fb: | |
f44e2659 VS |
2669 | plane_state->src_x = 0; |
2670 | plane_state->src_y = 0; | |
be5651f2 ML |
2671 | plane_state->src_w = fb->width << 16; |
2672 | plane_state->src_h = fb->height << 16; | |
2673 | ||
f44e2659 VS |
2674 | plane_state->crtc_x = 0; |
2675 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2676 | plane_state->crtc_w = fb->width; |
2677 | plane_state->crtc_h = fb->height; | |
2678 | ||
0a8d8a86 MR |
2679 | intel_state->src.x1 = plane_state->src_x; |
2680 | intel_state->src.y1 = plane_state->src_y; | |
2681 | intel_state->src.x2 = plane_state->src_x + plane_state->src_w; | |
2682 | intel_state->src.y2 = plane_state->src_y + plane_state->src_h; | |
2683 | intel_state->dst.x1 = plane_state->crtc_x; | |
2684 | intel_state->dst.y1 = plane_state->crtc_y; | |
2685 | intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w; | |
2686 | intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h; | |
2687 | ||
88595ac9 DV |
2688 | obj = intel_fb_obj(fb); |
2689 | if (obj->tiling_mode != I915_TILING_NONE) | |
2690 | dev_priv->preserve_bios_swizzle = true; | |
2691 | ||
be5651f2 ML |
2692 | drm_framebuffer_reference(fb); |
2693 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2694 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2695 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
a9ff8714 | 2696 | obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit; |
46f297fb JB |
2697 | } |
2698 | ||
a8d201af ML |
2699 | static void i9xx_update_primary_plane(struct drm_plane *primary, |
2700 | const struct intel_crtc_state *crtc_state, | |
2701 | const struct intel_plane_state *plane_state) | |
81255565 | 2702 | { |
a8d201af | 2703 | struct drm_device *dev = primary->dev; |
81255565 | 2704 | struct drm_i915_private *dev_priv = dev->dev_private; |
a8d201af ML |
2705 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2706 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2707 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
81255565 | 2708 | int plane = intel_crtc->plane; |
e506a0c6 | 2709 | unsigned long linear_offset; |
a8d201af ML |
2710 | int x = plane_state->src.x1 >> 16; |
2711 | int y = plane_state->src.y1 >> 16; | |
81255565 | 2712 | u32 dspcntr; |
f0f59a00 | 2713 | i915_reg_t reg = DSPCNTR(plane); |
48404c1e | 2714 | int pixel_size; |
f45651ba | 2715 | |
c9ba6fad VS |
2716 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); |
2717 | ||
f45651ba VS |
2718 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2719 | ||
fdd508a6 | 2720 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2721 | |
2722 | if (INTEL_INFO(dev)->gen < 4) { | |
2723 | if (intel_crtc->pipe == PIPE_B) | |
2724 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2725 | ||
2726 | /* pipesrc and dspsize control the size that is scaled from, | |
2727 | * which should always be the user's requested size. | |
2728 | */ | |
2729 | I915_WRITE(DSPSIZE(plane), | |
a8d201af ML |
2730 | ((crtc_state->pipe_src_h - 1) << 16) | |
2731 | (crtc_state->pipe_src_w - 1)); | |
f45651ba | 2732 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2733 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2734 | I915_WRITE(PRIMSIZE(plane), | |
a8d201af ML |
2735 | ((crtc_state->pipe_src_h - 1) << 16) | |
2736 | (crtc_state->pipe_src_w - 1)); | |
c14b0485 VS |
2737 | I915_WRITE(PRIMPOS(plane), 0); |
2738 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2739 | } |
81255565 | 2740 | |
57779d06 VS |
2741 | switch (fb->pixel_format) { |
2742 | case DRM_FORMAT_C8: | |
81255565 JB |
2743 | dspcntr |= DISPPLANE_8BPP; |
2744 | break; | |
57779d06 | 2745 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2746 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2747 | break; |
57779d06 VS |
2748 | case DRM_FORMAT_RGB565: |
2749 | dspcntr |= DISPPLANE_BGRX565; | |
2750 | break; | |
2751 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2752 | dspcntr |= DISPPLANE_BGRX888; |
2753 | break; | |
2754 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2755 | dspcntr |= DISPPLANE_RGBX888; |
2756 | break; | |
2757 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2758 | dspcntr |= DISPPLANE_BGRX101010; |
2759 | break; | |
2760 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2761 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
2762 | break; |
2763 | default: | |
baba133a | 2764 | BUG(); |
81255565 | 2765 | } |
57779d06 | 2766 | |
f45651ba VS |
2767 | if (INTEL_INFO(dev)->gen >= 4 && |
2768 | obj->tiling_mode != I915_TILING_NONE) | |
2769 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2770 | |
de1aa629 VS |
2771 | if (IS_G4X(dev)) |
2772 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2773 | ||
b9897127 | 2774 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
81255565 | 2775 | |
c2c75131 DV |
2776 | if (INTEL_INFO(dev)->gen >= 4) { |
2777 | intel_crtc->dspaddr_offset = | |
ce1e5c14 VS |
2778 | intel_compute_tile_offset(dev_priv, &x, &y, |
2779 | fb->modifier[0], | |
2780 | pixel_size, | |
2781 | fb->pitches[0]); | |
c2c75131 DV |
2782 | linear_offset -= intel_crtc->dspaddr_offset; |
2783 | } else { | |
e506a0c6 | 2784 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2785 | } |
e506a0c6 | 2786 | |
a8d201af | 2787 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2788 | dspcntr |= DISPPLANE_ROTATE_180; |
2789 | ||
a8d201af ML |
2790 | x += (crtc_state->pipe_src_w - 1); |
2791 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2792 | |
2793 | /* Finding the last pixel of the last line of the display | |
2794 | data and adding to linear_offset*/ | |
2795 | linear_offset += | |
a8d201af ML |
2796 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
2797 | (crtc_state->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2798 | } |
2799 | ||
2db3366b PZ |
2800 | intel_crtc->adjusted_x = x; |
2801 | intel_crtc->adjusted_y = y; | |
2802 | ||
48404c1e SJ |
2803 | I915_WRITE(reg, dspcntr); |
2804 | ||
01f2c773 | 2805 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2806 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2807 | I915_WRITE(DSPSURF(plane), |
2808 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2809 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2810 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2811 | } else |
f343c5f6 | 2812 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2813 | POSTING_READ(reg); |
17638cd6 JB |
2814 | } |
2815 | ||
a8d201af ML |
2816 | static void i9xx_disable_primary_plane(struct drm_plane *primary, |
2817 | struct drm_crtc *crtc) | |
17638cd6 JB |
2818 | { |
2819 | struct drm_device *dev = crtc->dev; | |
2820 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2821 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
17638cd6 | 2822 | int plane = intel_crtc->plane; |
f45651ba | 2823 | |
a8d201af ML |
2824 | I915_WRITE(DSPCNTR(plane), 0); |
2825 | if (INTEL_INFO(dev_priv)->gen >= 4) | |
fdd508a6 | 2826 | I915_WRITE(DSPSURF(plane), 0); |
a8d201af ML |
2827 | else |
2828 | I915_WRITE(DSPADDR(plane), 0); | |
2829 | POSTING_READ(DSPCNTR(plane)); | |
2830 | } | |
c9ba6fad | 2831 | |
a8d201af ML |
2832 | static void ironlake_update_primary_plane(struct drm_plane *primary, |
2833 | const struct intel_crtc_state *crtc_state, | |
2834 | const struct intel_plane_state *plane_state) | |
2835 | { | |
2836 | struct drm_device *dev = primary->dev; | |
2837 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2838 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
2839 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2840 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
2841 | int plane = intel_crtc->plane; | |
2842 | unsigned long linear_offset; | |
2843 | u32 dspcntr; | |
2844 | i915_reg_t reg = DSPCNTR(plane); | |
2845 | int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2846 | int x = plane_state->src.x1 >> 16; | |
2847 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2848 | |
f45651ba | 2849 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
fdd508a6 | 2850 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2851 | |
2852 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2853 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2854 | |
57779d06 VS |
2855 | switch (fb->pixel_format) { |
2856 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2857 | dspcntr |= DISPPLANE_8BPP; |
2858 | break; | |
57779d06 VS |
2859 | case DRM_FORMAT_RGB565: |
2860 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2861 | break; |
57779d06 | 2862 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
2863 | dspcntr |= DISPPLANE_BGRX888; |
2864 | break; | |
2865 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2866 | dspcntr |= DISPPLANE_RGBX888; |
2867 | break; | |
2868 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2869 | dspcntr |= DISPPLANE_BGRX101010; |
2870 | break; | |
2871 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2872 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
2873 | break; |
2874 | default: | |
baba133a | 2875 | BUG(); |
17638cd6 JB |
2876 | } |
2877 | ||
2878 | if (obj->tiling_mode != I915_TILING_NONE) | |
2879 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2880 | |
f45651ba | 2881 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2882 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2883 | |
b9897127 | 2884 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
c2c75131 | 2885 | intel_crtc->dspaddr_offset = |
ce1e5c14 VS |
2886 | intel_compute_tile_offset(dev_priv, &x, &y, |
2887 | fb->modifier[0], | |
2888 | pixel_size, | |
2889 | fb->pitches[0]); | |
c2c75131 | 2890 | linear_offset -= intel_crtc->dspaddr_offset; |
a8d201af | 2891 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2892 | dspcntr |= DISPPLANE_ROTATE_180; |
2893 | ||
2894 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
a8d201af ML |
2895 | x += (crtc_state->pipe_src_w - 1); |
2896 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2897 | |
2898 | /* Finding the last pixel of the last line of the display | |
2899 | data and adding to linear_offset*/ | |
2900 | linear_offset += | |
a8d201af ML |
2901 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
2902 | (crtc_state->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2903 | } |
2904 | } | |
2905 | ||
2db3366b PZ |
2906 | intel_crtc->adjusted_x = x; |
2907 | intel_crtc->adjusted_y = y; | |
2908 | ||
48404c1e | 2909 | I915_WRITE(reg, dspcntr); |
17638cd6 | 2910 | |
01f2c773 | 2911 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2912 | I915_WRITE(DSPSURF(plane), |
2913 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2914 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2915 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2916 | } else { | |
2917 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2918 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2919 | } | |
17638cd6 | 2920 | POSTING_READ(reg); |
17638cd6 JB |
2921 | } |
2922 | ||
7b49f948 VS |
2923 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
2924 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 2925 | { |
7b49f948 | 2926 | if (fb_modifier == DRM_FORMAT_MOD_NONE) { |
b321803d | 2927 | return 64; |
7b49f948 VS |
2928 | } else { |
2929 | int cpp = drm_format_plane_cpp(pixel_format, 0); | |
2930 | ||
2931 | return intel_tile_width(dev_priv, fb_modifier, cpp); | |
b321803d DL |
2932 | } |
2933 | } | |
2934 | ||
44eb0cb9 MK |
2935 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, |
2936 | struct drm_i915_gem_object *obj, | |
2937 | unsigned int plane) | |
121920fa | 2938 | { |
ce7f1728 | 2939 | struct i915_ggtt_view view; |
dedf278c | 2940 | struct i915_vma *vma; |
44eb0cb9 | 2941 | u64 offset; |
121920fa | 2942 | |
ce7f1728 DV |
2943 | intel_fill_fb_ggtt_view(&view, intel_plane->base.fb, |
2944 | intel_plane->base.state); | |
121920fa | 2945 | |
ce7f1728 | 2946 | vma = i915_gem_obj_to_ggtt_view(obj, &view); |
dedf278c | 2947 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", |
ce7f1728 | 2948 | view.type)) |
dedf278c TU |
2949 | return -1; |
2950 | ||
44eb0cb9 | 2951 | offset = vma->node.start; |
dedf278c TU |
2952 | |
2953 | if (plane == 1) { | |
a6d09186 | 2954 | offset += vma->ggtt_view.params.rotation_info.uv_start_page * |
dedf278c TU |
2955 | PAGE_SIZE; |
2956 | } | |
2957 | ||
44eb0cb9 MK |
2958 | WARN_ON(upper_32_bits(offset)); |
2959 | ||
2960 | return lower_32_bits(offset); | |
121920fa TU |
2961 | } |
2962 | ||
e435d6e5 ML |
2963 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
2964 | { | |
2965 | struct drm_device *dev = intel_crtc->base.dev; | |
2966 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2967 | ||
2968 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
2969 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
2970 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
2971 | } |
2972 | ||
a1b2278e CK |
2973 | /* |
2974 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2975 | */ | |
0583236e | 2976 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 2977 | { |
a1b2278e CK |
2978 | struct intel_crtc_scaler_state *scaler_state; |
2979 | int i; | |
2980 | ||
a1b2278e CK |
2981 | scaler_state = &intel_crtc->config->scaler_state; |
2982 | ||
2983 | /* loop through and disable scalers that aren't in use */ | |
2984 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
2985 | if (!scaler_state->scalers[i].in_use) |
2986 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
2987 | } |
2988 | } | |
2989 | ||
6156a456 | 2990 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 2991 | { |
6156a456 | 2992 | switch (pixel_format) { |
d161cf7a | 2993 | case DRM_FORMAT_C8: |
c34ce3d1 | 2994 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 2995 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 2996 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 2997 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 2998 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 2999 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 3000 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
3001 | /* |
3002 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
3003 | * to be already pre-multiplied. We need to add a knob (or a different | |
3004 | * DRM_FORMAT) for user-space to configure that. | |
3005 | */ | |
f75fb42a | 3006 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 3007 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 3008 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 3009 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 3010 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 3011 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 3012 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 3013 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 3014 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 3015 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 3016 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 3017 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 3018 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 3019 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 3020 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 3021 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 3022 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 3023 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 3024 | default: |
4249eeef | 3025 | MISSING_CASE(pixel_format); |
70d21f0e | 3026 | } |
8cfcba41 | 3027 | |
c34ce3d1 | 3028 | return 0; |
6156a456 | 3029 | } |
70d21f0e | 3030 | |
6156a456 CK |
3031 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
3032 | { | |
6156a456 | 3033 | switch (fb_modifier) { |
30af77c4 | 3034 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 3035 | break; |
30af77c4 | 3036 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 3037 | return PLANE_CTL_TILED_X; |
b321803d | 3038 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3039 | return PLANE_CTL_TILED_Y; |
b321803d | 3040 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3041 | return PLANE_CTL_TILED_YF; |
70d21f0e | 3042 | default: |
6156a456 | 3043 | MISSING_CASE(fb_modifier); |
70d21f0e | 3044 | } |
8cfcba41 | 3045 | |
c34ce3d1 | 3046 | return 0; |
6156a456 | 3047 | } |
70d21f0e | 3048 | |
6156a456 CK |
3049 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
3050 | { | |
3b7a5119 | 3051 | switch (rotation) { |
6156a456 CK |
3052 | case BIT(DRM_ROTATE_0): |
3053 | break; | |
1e8df167 SJ |
3054 | /* |
3055 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
3056 | * while i915 HW rotation is clockwise, thats why this swapping. | |
3057 | */ | |
3b7a5119 | 3058 | case BIT(DRM_ROTATE_90): |
1e8df167 | 3059 | return PLANE_CTL_ROTATE_270; |
3b7a5119 | 3060 | case BIT(DRM_ROTATE_180): |
c34ce3d1 | 3061 | return PLANE_CTL_ROTATE_180; |
3b7a5119 | 3062 | case BIT(DRM_ROTATE_270): |
1e8df167 | 3063 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3064 | default: |
3065 | MISSING_CASE(rotation); | |
3066 | } | |
3067 | ||
c34ce3d1 | 3068 | return 0; |
6156a456 CK |
3069 | } |
3070 | ||
a8d201af ML |
3071 | static void skylake_update_primary_plane(struct drm_plane *plane, |
3072 | const struct intel_crtc_state *crtc_state, | |
3073 | const struct intel_plane_state *plane_state) | |
6156a456 | 3074 | { |
a8d201af | 3075 | struct drm_device *dev = plane->dev; |
6156a456 | 3076 | struct drm_i915_private *dev_priv = dev->dev_private; |
a8d201af ML |
3077 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3078 | struct drm_framebuffer *fb = plane_state->base.fb; | |
3079 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
6156a456 CK |
3080 | int pipe = intel_crtc->pipe; |
3081 | u32 plane_ctl, stride_div, stride; | |
3082 | u32 tile_height, plane_offset, plane_size; | |
a8d201af | 3083 | unsigned int rotation = plane_state->base.rotation; |
6156a456 | 3084 | int x_offset, y_offset; |
44eb0cb9 | 3085 | u32 surf_addr; |
a8d201af ML |
3086 | int scaler_id = plane_state->scaler_id; |
3087 | int src_x = plane_state->src.x1 >> 16; | |
3088 | int src_y = plane_state->src.y1 >> 16; | |
3089 | int src_w = drm_rect_width(&plane_state->src) >> 16; | |
3090 | int src_h = drm_rect_height(&plane_state->src) >> 16; | |
3091 | int dst_x = plane_state->dst.x1; | |
3092 | int dst_y = plane_state->dst.y1; | |
3093 | int dst_w = drm_rect_width(&plane_state->dst); | |
3094 | int dst_h = drm_rect_height(&plane_state->dst); | |
70d21f0e | 3095 | |
6156a456 CK |
3096 | plane_ctl = PLANE_CTL_ENABLE | |
3097 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3098 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3099 | ||
3100 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3101 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3102 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
6156a456 CK |
3103 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
3104 | ||
7b49f948 | 3105 | stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
b321803d | 3106 | fb->pixel_format); |
dedf278c | 3107 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); |
3b7a5119 | 3108 | |
a42e5a23 PZ |
3109 | WARN_ON(drm_rect_width(&plane_state->src) == 0); |
3110 | ||
3b7a5119 | 3111 | if (intel_rotation_90_or_270(rotation)) { |
832be82f VS |
3112 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
3113 | ||
3b7a5119 | 3114 | /* stride = Surface height in tiles */ |
832be82f | 3115 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp); |
3b7a5119 | 3116 | stride = DIV_ROUND_UP(fb->height, tile_height); |
a8d201af ML |
3117 | x_offset = stride * tile_height - src_y - src_h; |
3118 | y_offset = src_x; | |
6156a456 | 3119 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3120 | } else { |
3121 | stride = fb->pitches[0] / stride_div; | |
a8d201af ML |
3122 | x_offset = src_x; |
3123 | y_offset = src_y; | |
6156a456 | 3124 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3125 | } |
3126 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3127 | |
2db3366b PZ |
3128 | intel_crtc->adjusted_x = x_offset; |
3129 | intel_crtc->adjusted_y = y_offset; | |
3130 | ||
70d21f0e | 3131 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3132 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3133 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3134 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3135 | |
3136 | if (scaler_id >= 0) { | |
3137 | uint32_t ps_ctrl = 0; | |
3138 | ||
3139 | WARN_ON(!dst_w || !dst_h); | |
3140 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3141 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3142 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3143 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3144 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3145 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3146 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3147 | } else { | |
3148 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3149 | } | |
3150 | ||
121920fa | 3151 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3152 | |
3153 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3154 | } | |
3155 | ||
a8d201af ML |
3156 | static void skylake_disable_primary_plane(struct drm_plane *primary, |
3157 | struct drm_crtc *crtc) | |
17638cd6 JB |
3158 | { |
3159 | struct drm_device *dev = crtc->dev; | |
3160 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a8d201af | 3161 | int pipe = to_intel_crtc(crtc)->pipe; |
17638cd6 | 3162 | |
0e631adc PZ |
3163 | if (dev_priv->fbc.deactivate) |
3164 | dev_priv->fbc.deactivate(dev_priv); | |
81255565 | 3165 | |
a8d201af ML |
3166 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3167 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3168 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3169 | } | |
29b9bde6 | 3170 | |
a8d201af ML |
3171 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3172 | static int | |
3173 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3174 | int x, int y, enum mode_set_atomic state) | |
3175 | { | |
3176 | /* Support for kgdboc is disabled, this needs a major rework. */ | |
3177 | DRM_ERROR("legacy panic handler not supported any more.\n"); | |
3178 | ||
3179 | return -ENODEV; | |
81255565 JB |
3180 | } |
3181 | ||
7514747d | 3182 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 3183 | { |
96a02917 VS |
3184 | struct drm_crtc *crtc; |
3185 | ||
70e1e0ec | 3186 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3187 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3188 | enum plane plane = intel_crtc->plane; | |
3189 | ||
3190 | intel_prepare_page_flip(dev, plane); | |
3191 | intel_finish_page_flip_plane(dev, plane); | |
3192 | } | |
7514747d VS |
3193 | } |
3194 | ||
3195 | static void intel_update_primary_planes(struct drm_device *dev) | |
3196 | { | |
7514747d | 3197 | struct drm_crtc *crtc; |
96a02917 | 3198 | |
70e1e0ec | 3199 | for_each_crtc(dev, crtc) { |
11c22da6 ML |
3200 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
3201 | struct intel_plane_state *plane_state; | |
96a02917 | 3202 | |
11c22da6 | 3203 | drm_modeset_lock_crtc(crtc, &plane->base); |
11c22da6 ML |
3204 | plane_state = to_intel_plane_state(plane->base.state); |
3205 | ||
a8d201af ML |
3206 | if (plane_state->visible) |
3207 | plane->update_plane(&plane->base, | |
3208 | to_intel_crtc_state(crtc->state), | |
3209 | plane_state); | |
11c22da6 ML |
3210 | |
3211 | drm_modeset_unlock_crtc(crtc); | |
96a02917 VS |
3212 | } |
3213 | } | |
3214 | ||
7514747d VS |
3215 | void intel_prepare_reset(struct drm_device *dev) |
3216 | { | |
3217 | /* no reset support for gen2 */ | |
3218 | if (IS_GEN2(dev)) | |
3219 | return; | |
3220 | ||
3221 | /* reset doesn't touch the display */ | |
3222 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3223 | return; | |
3224 | ||
3225 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3226 | /* |
3227 | * Disabling the crtcs gracefully seems nicer. Also the | |
3228 | * g33 docs say we should at least disable all the planes. | |
3229 | */ | |
6b72d486 | 3230 | intel_display_suspend(dev); |
7514747d VS |
3231 | } |
3232 | ||
3233 | void intel_finish_reset(struct drm_device *dev) | |
3234 | { | |
3235 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3236 | ||
3237 | /* | |
3238 | * Flips in the rings will be nuked by the reset, | |
3239 | * so complete all pending flips so that user space | |
3240 | * will get its events and not get stuck. | |
3241 | */ | |
3242 | intel_complete_page_flips(dev); | |
3243 | ||
3244 | /* no reset support for gen2 */ | |
3245 | if (IS_GEN2(dev)) | |
3246 | return; | |
3247 | ||
3248 | /* reset doesn't touch the display */ | |
3249 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3250 | /* | |
3251 | * Flips in the rings have been nuked by the reset, | |
3252 | * so update the base address of all primary | |
3253 | * planes to the the last fb to make sure we're | |
3254 | * showing the correct fb after a reset. | |
11c22da6 ML |
3255 | * |
3256 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3257 | * CS-based flips (which might get lost in gpu resets) any more. | |
7514747d VS |
3258 | */ |
3259 | intel_update_primary_planes(dev); | |
3260 | return; | |
3261 | } | |
3262 | ||
3263 | /* | |
3264 | * The display has been reset as well, | |
3265 | * so need a full re-initialization. | |
3266 | */ | |
3267 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3268 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3269 | ||
3270 | intel_modeset_init_hw(dev); | |
3271 | ||
3272 | spin_lock_irq(&dev_priv->irq_lock); | |
3273 | if (dev_priv->display.hpd_irq_setup) | |
3274 | dev_priv->display.hpd_irq_setup(dev); | |
3275 | spin_unlock_irq(&dev_priv->irq_lock); | |
3276 | ||
043e9bda | 3277 | intel_display_resume(dev); |
7514747d VS |
3278 | |
3279 | intel_hpd_init(dev_priv); | |
3280 | ||
3281 | drm_modeset_unlock_all(dev); | |
3282 | } | |
3283 | ||
7d5e3799 CW |
3284 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3285 | { | |
3286 | struct drm_device *dev = crtc->dev; | |
3287 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3288 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3289 | bool pending; |
3290 | ||
3291 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3292 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3293 | return false; | |
3294 | ||
5e2d7afc | 3295 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3296 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3297 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3298 | |
3299 | return pending; | |
3300 | } | |
3301 | ||
bfd16b2a ML |
3302 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3303 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 GP |
3304 | { |
3305 | struct drm_device *dev = crtc->base.dev; | |
3306 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bfd16b2a ML |
3307 | struct intel_crtc_state *pipe_config = |
3308 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3309 | |
bfd16b2a ML |
3310 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3311 | crtc->base.mode = crtc->base.state->mode; | |
3312 | ||
3313 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3314 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3315 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 | 3316 | |
44522d85 ML |
3317 | if (HAS_DDI(dev)) |
3318 | intel_set_pipe_csc(&crtc->base); | |
3319 | ||
e30e8f75 GP |
3320 | /* |
3321 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3322 | * that in compute_mode_changes we check the native mode (not the pfit | |
3323 | * mode) to see if we can flip rather than do a full mode set. In the | |
3324 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3325 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3326 | * sized surface. | |
e30e8f75 GP |
3327 | */ |
3328 | ||
e30e8f75 | 3329 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3330 | ((pipe_config->pipe_src_w - 1) << 16) | |
3331 | (pipe_config->pipe_src_h - 1)); | |
3332 | ||
3333 | /* on skylake this is done by detaching scalers */ | |
3334 | if (INTEL_INFO(dev)->gen >= 9) { | |
3335 | skl_detach_scalers(crtc); | |
3336 | ||
3337 | if (pipe_config->pch_pfit.enabled) | |
3338 | skylake_pfit_enable(crtc); | |
3339 | } else if (HAS_PCH_SPLIT(dev)) { | |
3340 | if (pipe_config->pch_pfit.enabled) | |
3341 | ironlake_pfit_enable(crtc); | |
3342 | else if (old_crtc_state->pch_pfit.enabled) | |
3343 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3344 | } |
e30e8f75 GP |
3345 | } |
3346 | ||
5e84e1a4 ZW |
3347 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3348 | { | |
3349 | struct drm_device *dev = crtc->dev; | |
3350 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3351 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3352 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3353 | i915_reg_t reg; |
3354 | u32 temp; | |
5e84e1a4 ZW |
3355 | |
3356 | /* enable normal train */ | |
3357 | reg = FDI_TX_CTL(pipe); | |
3358 | temp = I915_READ(reg); | |
61e499bf | 3359 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3360 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3361 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3362 | } else { |
3363 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3364 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3365 | } |
5e84e1a4 ZW |
3366 | I915_WRITE(reg, temp); |
3367 | ||
3368 | reg = FDI_RX_CTL(pipe); | |
3369 | temp = I915_READ(reg); | |
3370 | if (HAS_PCH_CPT(dev)) { | |
3371 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3372 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3373 | } else { | |
3374 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3375 | temp |= FDI_LINK_TRAIN_NONE; | |
3376 | } | |
3377 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3378 | ||
3379 | /* wait one idle pattern time */ | |
3380 | POSTING_READ(reg); | |
3381 | udelay(1000); | |
357555c0 JB |
3382 | |
3383 | /* IVB wants error correction enabled */ | |
3384 | if (IS_IVYBRIDGE(dev)) | |
3385 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3386 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3387 | } |
3388 | ||
8db9d77b ZW |
3389 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3390 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3391 | { | |
3392 | struct drm_device *dev = crtc->dev; | |
3393 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3394 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3395 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3396 | i915_reg_t reg; |
3397 | u32 temp, tries; | |
8db9d77b | 3398 | |
1c8562f6 | 3399 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3400 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3401 | |
e1a44743 AJ |
3402 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3403 | for train result */ | |
5eddb70b CW |
3404 | reg = FDI_RX_IMR(pipe); |
3405 | temp = I915_READ(reg); | |
e1a44743 AJ |
3406 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3407 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3408 | I915_WRITE(reg, temp); |
3409 | I915_READ(reg); | |
e1a44743 AJ |
3410 | udelay(150); |
3411 | ||
8db9d77b | 3412 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3413 | reg = FDI_TX_CTL(pipe); |
3414 | temp = I915_READ(reg); | |
627eb5a3 | 3415 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3416 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3417 | temp &= ~FDI_LINK_TRAIN_NONE; |
3418 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3419 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3420 | |
5eddb70b CW |
3421 | reg = FDI_RX_CTL(pipe); |
3422 | temp = I915_READ(reg); | |
8db9d77b ZW |
3423 | temp &= ~FDI_LINK_TRAIN_NONE; |
3424 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3425 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3426 | ||
3427 | POSTING_READ(reg); | |
8db9d77b ZW |
3428 | udelay(150); |
3429 | ||
5b2adf89 | 3430 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3431 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3432 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3433 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3434 | |
5eddb70b | 3435 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3436 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3437 | temp = I915_READ(reg); |
8db9d77b ZW |
3438 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3439 | ||
3440 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3441 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3442 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3443 | break; |
3444 | } | |
8db9d77b | 3445 | } |
e1a44743 | 3446 | if (tries == 5) |
5eddb70b | 3447 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3448 | |
3449 | /* Train 2 */ | |
5eddb70b CW |
3450 | reg = FDI_TX_CTL(pipe); |
3451 | temp = I915_READ(reg); | |
8db9d77b ZW |
3452 | temp &= ~FDI_LINK_TRAIN_NONE; |
3453 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3454 | I915_WRITE(reg, temp); |
8db9d77b | 3455 | |
5eddb70b CW |
3456 | reg = FDI_RX_CTL(pipe); |
3457 | temp = I915_READ(reg); | |
8db9d77b ZW |
3458 | temp &= ~FDI_LINK_TRAIN_NONE; |
3459 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3460 | I915_WRITE(reg, temp); |
8db9d77b | 3461 | |
5eddb70b CW |
3462 | POSTING_READ(reg); |
3463 | udelay(150); | |
8db9d77b | 3464 | |
5eddb70b | 3465 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3466 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3467 | temp = I915_READ(reg); |
8db9d77b ZW |
3468 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3469 | ||
3470 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3471 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3472 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3473 | break; | |
3474 | } | |
8db9d77b | 3475 | } |
e1a44743 | 3476 | if (tries == 5) |
5eddb70b | 3477 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3478 | |
3479 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3480 | |
8db9d77b ZW |
3481 | } |
3482 | ||
0206e353 | 3483 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3484 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3485 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3486 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3487 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3488 | }; | |
3489 | ||
3490 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3491 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3492 | { | |
3493 | struct drm_device *dev = crtc->dev; | |
3494 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3495 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3496 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3497 | i915_reg_t reg; |
3498 | u32 temp, i, retry; | |
8db9d77b | 3499 | |
e1a44743 AJ |
3500 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3501 | for train result */ | |
5eddb70b CW |
3502 | reg = FDI_RX_IMR(pipe); |
3503 | temp = I915_READ(reg); | |
e1a44743 AJ |
3504 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3505 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3506 | I915_WRITE(reg, temp); |
3507 | ||
3508 | POSTING_READ(reg); | |
e1a44743 AJ |
3509 | udelay(150); |
3510 | ||
8db9d77b | 3511 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3512 | reg = FDI_TX_CTL(pipe); |
3513 | temp = I915_READ(reg); | |
627eb5a3 | 3514 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3515 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3516 | temp &= ~FDI_LINK_TRAIN_NONE; |
3517 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3518 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3519 | /* SNB-B */ | |
3520 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3521 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3522 | |
d74cf324 DV |
3523 | I915_WRITE(FDI_RX_MISC(pipe), |
3524 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3525 | ||
5eddb70b CW |
3526 | reg = FDI_RX_CTL(pipe); |
3527 | temp = I915_READ(reg); | |
8db9d77b ZW |
3528 | if (HAS_PCH_CPT(dev)) { |
3529 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3530 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3531 | } else { | |
3532 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3533 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3534 | } | |
5eddb70b CW |
3535 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3536 | ||
3537 | POSTING_READ(reg); | |
8db9d77b ZW |
3538 | udelay(150); |
3539 | ||
0206e353 | 3540 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3541 | reg = FDI_TX_CTL(pipe); |
3542 | temp = I915_READ(reg); | |
8db9d77b ZW |
3543 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3544 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3545 | I915_WRITE(reg, temp); |
3546 | ||
3547 | POSTING_READ(reg); | |
8db9d77b ZW |
3548 | udelay(500); |
3549 | ||
fa37d39e SP |
3550 | for (retry = 0; retry < 5; retry++) { |
3551 | reg = FDI_RX_IIR(pipe); | |
3552 | temp = I915_READ(reg); | |
3553 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3554 | if (temp & FDI_RX_BIT_LOCK) { | |
3555 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3556 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3557 | break; | |
3558 | } | |
3559 | udelay(50); | |
8db9d77b | 3560 | } |
fa37d39e SP |
3561 | if (retry < 5) |
3562 | break; | |
8db9d77b ZW |
3563 | } |
3564 | if (i == 4) | |
5eddb70b | 3565 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3566 | |
3567 | /* Train 2 */ | |
5eddb70b CW |
3568 | reg = FDI_TX_CTL(pipe); |
3569 | temp = I915_READ(reg); | |
8db9d77b ZW |
3570 | temp &= ~FDI_LINK_TRAIN_NONE; |
3571 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3572 | if (IS_GEN6(dev)) { | |
3573 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3574 | /* SNB-B */ | |
3575 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3576 | } | |
5eddb70b | 3577 | I915_WRITE(reg, temp); |
8db9d77b | 3578 | |
5eddb70b CW |
3579 | reg = FDI_RX_CTL(pipe); |
3580 | temp = I915_READ(reg); | |
8db9d77b ZW |
3581 | if (HAS_PCH_CPT(dev)) { |
3582 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3583 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3584 | } else { | |
3585 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3586 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3587 | } | |
5eddb70b CW |
3588 | I915_WRITE(reg, temp); |
3589 | ||
3590 | POSTING_READ(reg); | |
8db9d77b ZW |
3591 | udelay(150); |
3592 | ||
0206e353 | 3593 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3594 | reg = FDI_TX_CTL(pipe); |
3595 | temp = I915_READ(reg); | |
8db9d77b ZW |
3596 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3597 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3598 | I915_WRITE(reg, temp); |
3599 | ||
3600 | POSTING_READ(reg); | |
8db9d77b ZW |
3601 | udelay(500); |
3602 | ||
fa37d39e SP |
3603 | for (retry = 0; retry < 5; retry++) { |
3604 | reg = FDI_RX_IIR(pipe); | |
3605 | temp = I915_READ(reg); | |
3606 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3607 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3608 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3609 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3610 | break; | |
3611 | } | |
3612 | udelay(50); | |
8db9d77b | 3613 | } |
fa37d39e SP |
3614 | if (retry < 5) |
3615 | break; | |
8db9d77b ZW |
3616 | } |
3617 | if (i == 4) | |
5eddb70b | 3618 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3619 | |
3620 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3621 | } | |
3622 | ||
357555c0 JB |
3623 | /* Manual link training for Ivy Bridge A0 parts */ |
3624 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3625 | { | |
3626 | struct drm_device *dev = crtc->dev; | |
3627 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3628 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3629 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3630 | i915_reg_t reg; |
3631 | u32 temp, i, j; | |
357555c0 JB |
3632 | |
3633 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3634 | for train result */ | |
3635 | reg = FDI_RX_IMR(pipe); | |
3636 | temp = I915_READ(reg); | |
3637 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3638 | temp &= ~FDI_RX_BIT_LOCK; | |
3639 | I915_WRITE(reg, temp); | |
3640 | ||
3641 | POSTING_READ(reg); | |
3642 | udelay(150); | |
3643 | ||
01a415fd DV |
3644 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3645 | I915_READ(FDI_RX_IIR(pipe))); | |
3646 | ||
139ccd3f JB |
3647 | /* Try each vswing and preemphasis setting twice before moving on */ |
3648 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3649 | /* disable first in case we need to retry */ | |
3650 | reg = FDI_TX_CTL(pipe); | |
3651 | temp = I915_READ(reg); | |
3652 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3653 | temp &= ~FDI_TX_ENABLE; | |
3654 | I915_WRITE(reg, temp); | |
357555c0 | 3655 | |
139ccd3f JB |
3656 | reg = FDI_RX_CTL(pipe); |
3657 | temp = I915_READ(reg); | |
3658 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3659 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3660 | temp &= ~FDI_RX_ENABLE; | |
3661 | I915_WRITE(reg, temp); | |
357555c0 | 3662 | |
139ccd3f | 3663 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3664 | reg = FDI_TX_CTL(pipe); |
3665 | temp = I915_READ(reg); | |
139ccd3f | 3666 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3667 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3668 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3669 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3670 | temp |= snb_b_fdi_train_param[j/2]; |
3671 | temp |= FDI_COMPOSITE_SYNC; | |
3672 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3673 | |
139ccd3f JB |
3674 | I915_WRITE(FDI_RX_MISC(pipe), |
3675 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3676 | |
139ccd3f | 3677 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3678 | temp = I915_READ(reg); |
139ccd3f JB |
3679 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3680 | temp |= FDI_COMPOSITE_SYNC; | |
3681 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3682 | |
139ccd3f JB |
3683 | POSTING_READ(reg); |
3684 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3685 | |
139ccd3f JB |
3686 | for (i = 0; i < 4; i++) { |
3687 | reg = FDI_RX_IIR(pipe); | |
3688 | temp = I915_READ(reg); | |
3689 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3690 | |
139ccd3f JB |
3691 | if (temp & FDI_RX_BIT_LOCK || |
3692 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3693 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3694 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3695 | i); | |
3696 | break; | |
3697 | } | |
3698 | udelay(1); /* should be 0.5us */ | |
3699 | } | |
3700 | if (i == 4) { | |
3701 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3702 | continue; | |
3703 | } | |
357555c0 | 3704 | |
139ccd3f | 3705 | /* Train 2 */ |
357555c0 JB |
3706 | reg = FDI_TX_CTL(pipe); |
3707 | temp = I915_READ(reg); | |
139ccd3f JB |
3708 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3709 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3710 | I915_WRITE(reg, temp); | |
3711 | ||
3712 | reg = FDI_RX_CTL(pipe); | |
3713 | temp = I915_READ(reg); | |
3714 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3715 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3716 | I915_WRITE(reg, temp); |
3717 | ||
3718 | POSTING_READ(reg); | |
139ccd3f | 3719 | udelay(2); /* should be 1.5us */ |
357555c0 | 3720 | |
139ccd3f JB |
3721 | for (i = 0; i < 4; i++) { |
3722 | reg = FDI_RX_IIR(pipe); | |
3723 | temp = I915_READ(reg); | |
3724 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3725 | |
139ccd3f JB |
3726 | if (temp & FDI_RX_SYMBOL_LOCK || |
3727 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3728 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3729 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3730 | i); | |
3731 | goto train_done; | |
3732 | } | |
3733 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3734 | } |
139ccd3f JB |
3735 | if (i == 4) |
3736 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3737 | } |
357555c0 | 3738 | |
139ccd3f | 3739 | train_done: |
357555c0 JB |
3740 | DRM_DEBUG_KMS("FDI train done.\n"); |
3741 | } | |
3742 | ||
88cefb6c | 3743 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3744 | { |
88cefb6c | 3745 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3746 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3747 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
3748 | i915_reg_t reg; |
3749 | u32 temp; | |
c64e311e | 3750 | |
c98e9dcf | 3751 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3752 | reg = FDI_RX_CTL(pipe); |
3753 | temp = I915_READ(reg); | |
627eb5a3 | 3754 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3755 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3756 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3757 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3758 | ||
3759 | POSTING_READ(reg); | |
c98e9dcf JB |
3760 | udelay(200); |
3761 | ||
3762 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3763 | temp = I915_READ(reg); |
3764 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3765 | ||
3766 | POSTING_READ(reg); | |
c98e9dcf JB |
3767 | udelay(200); |
3768 | ||
20749730 PZ |
3769 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3770 | reg = FDI_TX_CTL(pipe); | |
3771 | temp = I915_READ(reg); | |
3772 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3773 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3774 | |
20749730 PZ |
3775 | POSTING_READ(reg); |
3776 | udelay(100); | |
6be4a607 | 3777 | } |
0e23b99d JB |
3778 | } |
3779 | ||
88cefb6c DV |
3780 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3781 | { | |
3782 | struct drm_device *dev = intel_crtc->base.dev; | |
3783 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3784 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3785 | i915_reg_t reg; |
3786 | u32 temp; | |
88cefb6c DV |
3787 | |
3788 | /* Switch from PCDclk to Rawclk */ | |
3789 | reg = FDI_RX_CTL(pipe); | |
3790 | temp = I915_READ(reg); | |
3791 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3792 | ||
3793 | /* Disable CPU FDI TX PLL */ | |
3794 | reg = FDI_TX_CTL(pipe); | |
3795 | temp = I915_READ(reg); | |
3796 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3797 | ||
3798 | POSTING_READ(reg); | |
3799 | udelay(100); | |
3800 | ||
3801 | reg = FDI_RX_CTL(pipe); | |
3802 | temp = I915_READ(reg); | |
3803 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3804 | ||
3805 | /* Wait for the clocks to turn off. */ | |
3806 | POSTING_READ(reg); | |
3807 | udelay(100); | |
3808 | } | |
3809 | ||
0fc932b8 JB |
3810 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3811 | { | |
3812 | struct drm_device *dev = crtc->dev; | |
3813 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3814 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3815 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3816 | i915_reg_t reg; |
3817 | u32 temp; | |
0fc932b8 JB |
3818 | |
3819 | /* disable CPU FDI tx and PCH FDI rx */ | |
3820 | reg = FDI_TX_CTL(pipe); | |
3821 | temp = I915_READ(reg); | |
3822 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3823 | POSTING_READ(reg); | |
3824 | ||
3825 | reg = FDI_RX_CTL(pipe); | |
3826 | temp = I915_READ(reg); | |
3827 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3828 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3829 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3830 | ||
3831 | POSTING_READ(reg); | |
3832 | udelay(100); | |
3833 | ||
3834 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3835 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3836 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3837 | |
3838 | /* still set train pattern 1 */ | |
3839 | reg = FDI_TX_CTL(pipe); | |
3840 | temp = I915_READ(reg); | |
3841 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3842 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3843 | I915_WRITE(reg, temp); | |
3844 | ||
3845 | reg = FDI_RX_CTL(pipe); | |
3846 | temp = I915_READ(reg); | |
3847 | if (HAS_PCH_CPT(dev)) { | |
3848 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3849 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3850 | } else { | |
3851 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3852 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3853 | } | |
3854 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3855 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3856 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3857 | I915_WRITE(reg, temp); |
3858 | ||
3859 | POSTING_READ(reg); | |
3860 | udelay(100); | |
3861 | } | |
3862 | ||
5dce5b93 CW |
3863 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3864 | { | |
3865 | struct intel_crtc *crtc; | |
3866 | ||
3867 | /* Note that we don't need to be called with mode_config.lock here | |
3868 | * as our list of CRTC objects is static for the lifetime of the | |
3869 | * device and so cannot disappear as we iterate. Similarly, we can | |
3870 | * happily treat the predicates as racy, atomic checks as userspace | |
3871 | * cannot claim and pin a new fb without at least acquring the | |
3872 | * struct_mutex and so serialising with us. | |
3873 | */ | |
d3fcc808 | 3874 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3875 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3876 | continue; | |
3877 | ||
3878 | if (crtc->unpin_work) | |
3879 | intel_wait_for_vblank(dev, crtc->pipe); | |
3880 | ||
3881 | return true; | |
3882 | } | |
3883 | ||
3884 | return false; | |
3885 | } | |
3886 | ||
d6bbafa1 CW |
3887 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3888 | { | |
3889 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3890 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3891 | ||
3892 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3893 | smp_rmb(); | |
3894 | intel_crtc->unpin_work = NULL; | |
3895 | ||
3896 | if (work->event) | |
3897 | drm_send_vblank_event(intel_crtc->base.dev, | |
3898 | intel_crtc->pipe, | |
3899 | work->event); | |
3900 | ||
3901 | drm_crtc_vblank_put(&intel_crtc->base); | |
3902 | ||
3903 | wake_up_all(&dev_priv->pending_flip_queue); | |
3904 | queue_work(dev_priv->wq, &work->work); | |
3905 | ||
3906 | trace_i915_flip_complete(intel_crtc->plane, | |
3907 | work->pending_flip_obj); | |
3908 | } | |
3909 | ||
5008e874 | 3910 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3911 | { |
0f91128d | 3912 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3913 | struct drm_i915_private *dev_priv = dev->dev_private; |
5008e874 | 3914 | long ret; |
e6c3a2a6 | 3915 | |
2c10d571 | 3916 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
3917 | |
3918 | ret = wait_event_interruptible_timeout( | |
3919 | dev_priv->pending_flip_queue, | |
3920 | !intel_crtc_has_pending_flip(crtc), | |
3921 | 60*HZ); | |
3922 | ||
3923 | if (ret < 0) | |
3924 | return ret; | |
3925 | ||
3926 | if (ret == 0) { | |
9c787942 | 3927 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2c10d571 | 3928 | |
5e2d7afc | 3929 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3930 | if (intel_crtc->unpin_work) { |
3931 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3932 | page_flip_completed(intel_crtc); | |
3933 | } | |
5e2d7afc | 3934 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3935 | } |
5bb61643 | 3936 | |
5008e874 | 3937 | return 0; |
e6c3a2a6 CW |
3938 | } |
3939 | ||
060f02d8 VS |
3940 | static void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
3941 | { | |
3942 | u32 temp; | |
3943 | ||
3944 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3945 | ||
3946 | mutex_lock(&dev_priv->sb_lock); | |
3947 | ||
3948 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
3949 | temp |= SBI_SSCCTL_DISABLE; | |
3950 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
3951 | ||
3952 | mutex_unlock(&dev_priv->sb_lock); | |
3953 | } | |
3954 | ||
e615efe4 ED |
3955 | /* Program iCLKIP clock to the desired frequency */ |
3956 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3957 | { | |
3958 | struct drm_device *dev = crtc->dev; | |
3959 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3960 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3961 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3962 | u32 temp; | |
3963 | ||
060f02d8 | 3964 | lpt_disable_iclkip(dev_priv); |
e615efe4 ED |
3965 | |
3966 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3967 | if (clock == 20000) { |
e615efe4 ED |
3968 | auxdiv = 1; |
3969 | divsel = 0x41; | |
3970 | phaseinc = 0x20; | |
3971 | } else { | |
3972 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3973 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3974 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3975 | * convert the virtual clock precision to KHz here for higher |
3976 | * precision. | |
3977 | */ | |
3978 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3979 | u32 iclk_pi_range = 64; | |
3980 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3981 | ||
a2572f5c | 3982 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, clock); |
e615efe4 ED |
3983 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3984 | pi_value = desired_divisor % iclk_pi_range; | |
3985 | ||
3986 | auxdiv = 0; | |
3987 | divsel = msb_divisor_value - 2; | |
3988 | phaseinc = pi_value; | |
3989 | } | |
3990 | ||
3991 | /* This should not happen with any sane values */ | |
3992 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3993 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3994 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3995 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3996 | ||
3997 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3998 | clock, |
e615efe4 ED |
3999 | auxdiv, |
4000 | divsel, | |
4001 | phasedir, | |
4002 | phaseinc); | |
4003 | ||
060f02d8 VS |
4004 | mutex_lock(&dev_priv->sb_lock); |
4005 | ||
e615efe4 | 4006 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 4007 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4008 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4009 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4010 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4011 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4012 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4013 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4014 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4015 | |
4016 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4017 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4018 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4019 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4020 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4021 | |
4022 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4023 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4024 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4025 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 4026 | |
060f02d8 VS |
4027 | mutex_unlock(&dev_priv->sb_lock); |
4028 | ||
e615efe4 ED |
4029 | /* Wait for initialization time */ |
4030 | udelay(24); | |
4031 | ||
4032 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
4033 | } | |
4034 | ||
275f01b2 DV |
4035 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4036 | enum pipe pch_transcoder) | |
4037 | { | |
4038 | struct drm_device *dev = crtc->base.dev; | |
4039 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4040 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4041 | |
4042 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4043 | I915_READ(HTOTAL(cpu_transcoder))); | |
4044 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4045 | I915_READ(HBLANK(cpu_transcoder))); | |
4046 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4047 | I915_READ(HSYNC(cpu_transcoder))); | |
4048 | ||
4049 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4050 | I915_READ(VTOTAL(cpu_transcoder))); | |
4051 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4052 | I915_READ(VBLANK(cpu_transcoder))); | |
4053 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4054 | I915_READ(VSYNC(cpu_transcoder))); | |
4055 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4056 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4057 | } | |
4058 | ||
003632d9 | 4059 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
4060 | { |
4061 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4062 | uint32_t temp; | |
4063 | ||
4064 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4065 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4066 | return; |
4067 | ||
4068 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4069 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4070 | ||
003632d9 ACO |
4071 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4072 | if (enable) | |
4073 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4074 | ||
4075 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4076 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4077 | POSTING_READ(SOUTH_CHICKEN1); | |
4078 | } | |
4079 | ||
4080 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4081 | { | |
4082 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4083 | |
4084 | switch (intel_crtc->pipe) { | |
4085 | case PIPE_A: | |
4086 | break; | |
4087 | case PIPE_B: | |
6e3c9717 | 4088 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4089 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4090 | else |
003632d9 | 4091 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4092 | |
4093 | break; | |
4094 | case PIPE_C: | |
003632d9 | 4095 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4096 | |
4097 | break; | |
4098 | default: | |
4099 | BUG(); | |
4100 | } | |
4101 | } | |
4102 | ||
c48b5305 VS |
4103 | /* Return which DP Port should be selected for Transcoder DP control */ |
4104 | static enum port | |
4105 | intel_trans_dp_port_sel(struct drm_crtc *crtc) | |
4106 | { | |
4107 | struct drm_device *dev = crtc->dev; | |
4108 | struct intel_encoder *encoder; | |
4109 | ||
4110 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
4111 | if (encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
4112 | encoder->type == INTEL_OUTPUT_EDP) | |
4113 | return enc_to_dig_port(&encoder->base)->port; | |
4114 | } | |
4115 | ||
4116 | return -1; | |
4117 | } | |
4118 | ||
f67a559d JB |
4119 | /* |
4120 | * Enable PCH resources required for PCH ports: | |
4121 | * - PCH PLLs | |
4122 | * - FDI training & RX/TX | |
4123 | * - update transcoder timings | |
4124 | * - DP transcoding bits | |
4125 | * - transcoder | |
4126 | */ | |
4127 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4128 | { |
4129 | struct drm_device *dev = crtc->dev; | |
4130 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4131 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4132 | int pipe = intel_crtc->pipe; | |
f0f59a00 | 4133 | u32 temp; |
2c07245f | 4134 | |
ab9412ba | 4135 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4136 | |
1fbc0d78 DV |
4137 | if (IS_IVYBRIDGE(dev)) |
4138 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4139 | ||
cd986abb DV |
4140 | /* Write the TU size bits before fdi link training, so that error |
4141 | * detection works. */ | |
4142 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4143 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4144 | ||
3860b2ec VS |
4145 | /* |
4146 | * Sometimes spurious CPU pipe underruns happen during FDI | |
4147 | * training, at least with VGA+HDMI cloning. Suppress them. | |
4148 | */ | |
4149 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4150 | ||
c98e9dcf | 4151 | /* For PCH output, training FDI link */ |
674cf967 | 4152 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4153 | |
3ad8a208 DV |
4154 | /* We need to program the right clock selection before writing the pixel |
4155 | * mutliplier into the DPLL. */ | |
303b81e0 | 4156 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4157 | u32 sel; |
4b645f14 | 4158 | |
c98e9dcf | 4159 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4160 | temp |= TRANS_DPLL_ENABLE(pipe); |
4161 | sel = TRANS_DPLLB_SEL(pipe); | |
6e3c9717 | 4162 | if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
4163 | temp |= sel; |
4164 | else | |
4165 | temp &= ~sel; | |
c98e9dcf | 4166 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4167 | } |
5eddb70b | 4168 | |
3ad8a208 DV |
4169 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4170 | * transcoder, and we actually should do this to not upset any PCH | |
4171 | * transcoder that already use the clock when we share it. | |
4172 | * | |
4173 | * Note that enable_shared_dpll tries to do the right thing, but | |
4174 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4175 | * the right LVDS enable sequence. */ | |
85b3894f | 4176 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4177 | |
d9b6cb56 JB |
4178 | /* set transcoder timing, panel must allow it */ |
4179 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4180 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4181 | |
303b81e0 | 4182 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4183 | |
3860b2ec VS |
4184 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4185 | ||
c98e9dcf | 4186 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4187 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
9c4edaee VS |
4188 | const struct drm_display_mode *adjusted_mode = |
4189 | &intel_crtc->config->base.adjusted_mode; | |
dfd07d72 | 4190 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4191 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4192 | temp = I915_READ(reg); |
4193 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4194 | TRANS_DP_SYNC_MASK | |
4195 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4196 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4197 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4198 | |
9c4edaee | 4199 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4200 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4201 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4202 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4203 | |
4204 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4205 | case PORT_B: |
5eddb70b | 4206 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4207 | break; |
c48b5305 | 4208 | case PORT_C: |
5eddb70b | 4209 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4210 | break; |
c48b5305 | 4211 | case PORT_D: |
5eddb70b | 4212 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4213 | break; |
4214 | default: | |
e95d41e1 | 4215 | BUG(); |
32f9d658 | 4216 | } |
2c07245f | 4217 | |
5eddb70b | 4218 | I915_WRITE(reg, temp); |
6be4a607 | 4219 | } |
b52eb4dc | 4220 | |
b8a4f404 | 4221 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4222 | } |
4223 | ||
1507e5bd PZ |
4224 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4225 | { | |
4226 | struct drm_device *dev = crtc->dev; | |
4227 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4228 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4229 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4230 | |
ab9412ba | 4231 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4232 | |
8c52b5e8 | 4233 | lpt_program_iclkip(crtc); |
1507e5bd | 4234 | |
0540e488 | 4235 | /* Set transcoder timing. */ |
275f01b2 | 4236 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4237 | |
937bb610 | 4238 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4239 | } |
4240 | ||
190f68c5 ACO |
4241 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
4242 | struct intel_crtc_state *crtc_state) | |
ee7b9f93 | 4243 | { |
e2b78267 | 4244 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 4245 | struct intel_shared_dpll *pll; |
de419ab6 | 4246 | struct intel_shared_dpll_config *shared_dpll; |
e2b78267 | 4247 | enum intel_dpll_id i; |
00490c22 | 4248 | int max = dev_priv->num_shared_dpll; |
ee7b9f93 | 4249 | |
de419ab6 ML |
4250 | shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state); |
4251 | ||
98b6bd99 DV |
4252 | if (HAS_PCH_IBX(dev_priv->dev)) { |
4253 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 4254 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 4255 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 4256 | |
46edb027 DV |
4257 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
4258 | crtc->base.base.id, pll->name); | |
98b6bd99 | 4259 | |
de419ab6 | 4260 | WARN_ON(shared_dpll[i].crtc_mask); |
f2a69f44 | 4261 | |
98b6bd99 DV |
4262 | goto found; |
4263 | } | |
4264 | ||
bcddf610 S |
4265 | if (IS_BROXTON(dev_priv->dev)) { |
4266 | /* PLL is attached to port in bxt */ | |
4267 | struct intel_encoder *encoder; | |
4268 | struct intel_digital_port *intel_dig_port; | |
4269 | ||
4270 | encoder = intel_ddi_get_crtc_new_encoder(crtc_state); | |
4271 | if (WARN_ON(!encoder)) | |
4272 | return NULL; | |
4273 | ||
4274 | intel_dig_port = enc_to_dig_port(&encoder->base); | |
4275 | /* 1:1 mapping between ports and PLLs */ | |
4276 | i = (enum intel_dpll_id)intel_dig_port->port; | |
4277 | pll = &dev_priv->shared_dplls[i]; | |
4278 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", | |
4279 | crtc->base.base.id, pll->name); | |
de419ab6 | 4280 | WARN_ON(shared_dpll[i].crtc_mask); |
bcddf610 S |
4281 | |
4282 | goto found; | |
00490c22 ML |
4283 | } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv)) |
4284 | /* Do not consider SPLL */ | |
4285 | max = 2; | |
bcddf610 | 4286 | |
00490c22 | 4287 | for (i = 0; i < max; i++) { |
e72f9fbf | 4288 | pll = &dev_priv->shared_dplls[i]; |
ee7b9f93 JB |
4289 | |
4290 | /* Only want to check enabled timings first */ | |
de419ab6 | 4291 | if (shared_dpll[i].crtc_mask == 0) |
ee7b9f93 JB |
4292 | continue; |
4293 | ||
190f68c5 | 4294 | if (memcmp(&crtc_state->dpll_hw_state, |
de419ab6 ML |
4295 | &shared_dpll[i].hw_state, |
4296 | sizeof(crtc_state->dpll_hw_state)) == 0) { | |
8bd31e67 | 4297 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", |
1e6f2ddc | 4298 | crtc->base.base.id, pll->name, |
de419ab6 | 4299 | shared_dpll[i].crtc_mask, |
8bd31e67 | 4300 | pll->active); |
ee7b9f93 JB |
4301 | goto found; |
4302 | } | |
4303 | } | |
4304 | ||
4305 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
4306 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4307 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4308 | if (shared_dpll[i].crtc_mask == 0) { |
46edb027 DV |
4309 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
4310 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
4311 | goto found; |
4312 | } | |
4313 | } | |
4314 | ||
4315 | return NULL; | |
4316 | ||
4317 | found: | |
de419ab6 ML |
4318 | if (shared_dpll[i].crtc_mask == 0) |
4319 | shared_dpll[i].hw_state = | |
4320 | crtc_state->dpll_hw_state; | |
f2a69f44 | 4321 | |
190f68c5 | 4322 | crtc_state->shared_dpll = i; |
46edb027 DV |
4323 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
4324 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 4325 | |
de419ab6 | 4326 | shared_dpll[i].crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 4327 | |
ee7b9f93 JB |
4328 | return pll; |
4329 | } | |
4330 | ||
de419ab6 | 4331 | static void intel_shared_dpll_commit(struct drm_atomic_state *state) |
8bd31e67 | 4332 | { |
de419ab6 ML |
4333 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
4334 | struct intel_shared_dpll_config *shared_dpll; | |
8bd31e67 ACO |
4335 | struct intel_shared_dpll *pll; |
4336 | enum intel_dpll_id i; | |
4337 | ||
de419ab6 ML |
4338 | if (!to_intel_atomic_state(state)->dpll_set) |
4339 | return; | |
8bd31e67 | 4340 | |
de419ab6 | 4341 | shared_dpll = to_intel_atomic_state(state)->shared_dpll; |
8bd31e67 ACO |
4342 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4343 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4344 | pll->config = shared_dpll[i]; |
8bd31e67 ACO |
4345 | } |
4346 | } | |
4347 | ||
a1520318 | 4348 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4349 | { |
4350 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 4351 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4352 | u32 temp; |
4353 | ||
4354 | temp = I915_READ(dslreg); | |
4355 | udelay(500); | |
4356 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4357 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4358 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4359 | } |
4360 | } | |
4361 | ||
86adf9d7 ML |
4362 | static int |
4363 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4364 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4365 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4366 | { |
86adf9d7 ML |
4367 | struct intel_crtc_scaler_state *scaler_state = |
4368 | &crtc_state->scaler_state; | |
4369 | struct intel_crtc *intel_crtc = | |
4370 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4371 | int need_scaling; |
6156a456 CK |
4372 | |
4373 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4374 | (src_h != dst_w || src_w != dst_h): | |
4375 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4376 | |
4377 | /* | |
4378 | * if plane is being disabled or scaler is no more required or force detach | |
4379 | * - free scaler binded to this plane/crtc | |
4380 | * - in order to do this, update crtc->scaler_usage | |
4381 | * | |
4382 | * Here scaler state in crtc_state is set free so that | |
4383 | * scaler can be assigned to other user. Actual register | |
4384 | * update to free the scaler is done in plane/panel-fit programming. | |
4385 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4386 | */ | |
86adf9d7 | 4387 | if (force_detach || !need_scaling) { |
a1b2278e | 4388 | if (*scaler_id >= 0) { |
86adf9d7 | 4389 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4390 | scaler_state->scalers[*scaler_id].in_use = 0; |
4391 | ||
86adf9d7 ML |
4392 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4393 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4394 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4395 | scaler_state->scaler_users); |
4396 | *scaler_id = -1; | |
4397 | } | |
4398 | return 0; | |
4399 | } | |
4400 | ||
4401 | /* range checks */ | |
4402 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4403 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4404 | ||
4405 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4406 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4407 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4408 | "size is out of scaler range\n", |
86adf9d7 | 4409 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4410 | return -EINVAL; |
4411 | } | |
4412 | ||
86adf9d7 ML |
4413 | /* mark this plane as a scaler user in crtc_state */ |
4414 | scaler_state->scaler_users |= (1 << scaler_user); | |
4415 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4416 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4417 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4418 | scaler_state->scaler_users); | |
4419 | ||
4420 | return 0; | |
4421 | } | |
4422 | ||
4423 | /** | |
4424 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4425 | * | |
4426 | * @state: crtc's scaler state | |
86adf9d7 ML |
4427 | * |
4428 | * Return | |
4429 | * 0 - scaler_usage updated successfully | |
4430 | * error - requested scaling cannot be supported or other error condition | |
4431 | */ | |
e435d6e5 | 4432 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 ML |
4433 | { |
4434 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); | |
7c5f93b0 | 4435 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 ML |
4436 | |
4437 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n", | |
4438 | intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX); | |
4439 | ||
e435d6e5 | 4440 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
86adf9d7 ML |
4441 | &state->scaler_state.scaler_id, DRM_ROTATE_0, |
4442 | state->pipe_src_w, state->pipe_src_h, | |
aad941d5 | 4443 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4444 | } |
4445 | ||
4446 | /** | |
4447 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4448 | * | |
4449 | * @state: crtc's scaler state | |
86adf9d7 ML |
4450 | * @plane_state: atomic plane state to update |
4451 | * | |
4452 | * Return | |
4453 | * 0 - scaler_usage updated successfully | |
4454 | * error - requested scaling cannot be supported or other error condition | |
4455 | */ | |
da20eabd ML |
4456 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4457 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4458 | { |
4459 | ||
4460 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
da20eabd ML |
4461 | struct intel_plane *intel_plane = |
4462 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4463 | struct drm_framebuffer *fb = plane_state->base.fb; |
4464 | int ret; | |
4465 | ||
4466 | bool force_detach = !fb || !plane_state->visible; | |
4467 | ||
4468 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n", | |
4469 | intel_plane->base.base.id, intel_crtc->pipe, | |
4470 | drm_plane_index(&intel_plane->base)); | |
4471 | ||
4472 | ret = skl_update_scaler(crtc_state, force_detach, | |
4473 | drm_plane_index(&intel_plane->base), | |
4474 | &plane_state->scaler_id, | |
4475 | plane_state->base.rotation, | |
4476 | drm_rect_width(&plane_state->src) >> 16, | |
4477 | drm_rect_height(&plane_state->src) >> 16, | |
4478 | drm_rect_width(&plane_state->dst), | |
4479 | drm_rect_height(&plane_state->dst)); | |
4480 | ||
4481 | if (ret || plane_state->scaler_id < 0) | |
4482 | return ret; | |
4483 | ||
a1b2278e | 4484 | /* check colorkey */ |
818ed961 | 4485 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
86adf9d7 | 4486 | DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed", |
818ed961 | 4487 | intel_plane->base.base.id); |
a1b2278e CK |
4488 | return -EINVAL; |
4489 | } | |
4490 | ||
4491 | /* Check src format */ | |
86adf9d7 ML |
4492 | switch (fb->pixel_format) { |
4493 | case DRM_FORMAT_RGB565: | |
4494 | case DRM_FORMAT_XBGR8888: | |
4495 | case DRM_FORMAT_XRGB8888: | |
4496 | case DRM_FORMAT_ABGR8888: | |
4497 | case DRM_FORMAT_ARGB8888: | |
4498 | case DRM_FORMAT_XRGB2101010: | |
4499 | case DRM_FORMAT_XBGR2101010: | |
4500 | case DRM_FORMAT_YUYV: | |
4501 | case DRM_FORMAT_YVYU: | |
4502 | case DRM_FORMAT_UYVY: | |
4503 | case DRM_FORMAT_VYUY: | |
4504 | break; | |
4505 | default: | |
4506 | DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n", | |
4507 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); | |
4508 | return -EINVAL; | |
a1b2278e CK |
4509 | } |
4510 | ||
a1b2278e CK |
4511 | return 0; |
4512 | } | |
4513 | ||
e435d6e5 ML |
4514 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4515 | { | |
4516 | int i; | |
4517 | ||
4518 | for (i = 0; i < crtc->num_scalers; i++) | |
4519 | skl_detach_scaler(crtc, i); | |
4520 | } | |
4521 | ||
4522 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4523 | { |
4524 | struct drm_device *dev = crtc->base.dev; | |
4525 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4526 | int pipe = crtc->pipe; | |
a1b2278e CK |
4527 | struct intel_crtc_scaler_state *scaler_state = |
4528 | &crtc->config->scaler_state; | |
4529 | ||
4530 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4531 | ||
6e3c9717 | 4532 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4533 | int id; |
4534 | ||
4535 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4536 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4537 | return; | |
4538 | } | |
4539 | ||
4540 | id = scaler_state->scaler_id; | |
4541 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4542 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4543 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4544 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4545 | ||
4546 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4547 | } |
4548 | } | |
4549 | ||
b074cec8 JB |
4550 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4551 | { | |
4552 | struct drm_device *dev = crtc->base.dev; | |
4553 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4554 | int pipe = crtc->pipe; | |
4555 | ||
6e3c9717 | 4556 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4557 | /* Force use of hard-coded filter coefficients |
4558 | * as some pre-programmed values are broken, | |
4559 | * e.g. x201. | |
4560 | */ | |
4561 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4562 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4563 | PF_PIPE_SEL_IVB(pipe)); | |
4564 | else | |
4565 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4566 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4567 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4568 | } |
4569 | } | |
4570 | ||
20bc8673 | 4571 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4572 | { |
cea165c3 VS |
4573 | struct drm_device *dev = crtc->base.dev; |
4574 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4575 | |
6e3c9717 | 4576 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4577 | return; |
4578 | ||
cea165c3 VS |
4579 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4580 | intel_wait_for_vblank(dev, crtc->pipe); | |
4581 | ||
d77e4531 | 4582 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4583 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4584 | mutex_lock(&dev_priv->rps.hw_lock); |
4585 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4586 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4587 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4588 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4589 | * mailbox." Moreover, the mailbox may return a bogus state, |
4590 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4591 | */ |
4592 | } else { | |
4593 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4594 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4595 | * is essentially intel_wait_for_vblank. If we don't have this | |
4596 | * and don't wait for vblanks until the end of crtc_enable, then | |
4597 | * the HW state readout code will complain that the expected | |
4598 | * IPS_CTL value is not the one we read. */ | |
4599 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4600 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4601 | } | |
d77e4531 PZ |
4602 | } |
4603 | ||
20bc8673 | 4604 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4605 | { |
4606 | struct drm_device *dev = crtc->base.dev; | |
4607 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4608 | ||
6e3c9717 | 4609 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4610 | return; |
4611 | ||
4612 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4613 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4614 | mutex_lock(&dev_priv->rps.hw_lock); |
4615 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4616 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4617 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4618 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4619 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4620 | } else { |
2a114cc1 | 4621 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4622 | POSTING_READ(IPS_CTL); |
4623 | } | |
d77e4531 PZ |
4624 | |
4625 | /* We need to wait for a vblank before we can disable the plane. */ | |
4626 | intel_wait_for_vblank(dev, crtc->pipe); | |
4627 | } | |
4628 | ||
4629 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4630 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4631 | { | |
4632 | struct drm_device *dev = crtc->dev; | |
4633 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4634 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4635 | enum pipe pipe = intel_crtc->pipe; | |
d77e4531 PZ |
4636 | int i; |
4637 | bool reenable_ips = false; | |
4638 | ||
4639 | /* The clocks have to be on to load the palette. */ | |
53d9f4e9 | 4640 | if (!crtc->state->active) |
d77e4531 PZ |
4641 | return; |
4642 | ||
50360403 | 4643 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) { |
a65347ba | 4644 | if (intel_crtc->config->has_dsi_encoder) |
d77e4531 PZ |
4645 | assert_dsi_pll_enabled(dev_priv); |
4646 | else | |
4647 | assert_pll_enabled(dev_priv, pipe); | |
4648 | } | |
4649 | ||
d77e4531 PZ |
4650 | /* Workaround : Do not read or write the pipe palette/gamma data while |
4651 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4652 | */ | |
6e3c9717 | 4653 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
d77e4531 PZ |
4654 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4655 | GAMMA_MODE_MODE_SPLIT)) { | |
4656 | hsw_disable_ips(intel_crtc); | |
4657 | reenable_ips = true; | |
4658 | } | |
4659 | ||
4660 | for (i = 0; i < 256; i++) { | |
f0f59a00 | 4661 | i915_reg_t palreg; |
f65a9c5b VS |
4662 | |
4663 | if (HAS_GMCH_DISPLAY(dev)) | |
4664 | palreg = PALETTE(pipe, i); | |
4665 | else | |
4666 | palreg = LGC_PALETTE(pipe, i); | |
4667 | ||
4668 | I915_WRITE(palreg, | |
d77e4531 PZ |
4669 | (intel_crtc->lut_r[i] << 16) | |
4670 | (intel_crtc->lut_g[i] << 8) | | |
4671 | intel_crtc->lut_b[i]); | |
4672 | } | |
4673 | ||
4674 | if (reenable_ips) | |
4675 | hsw_enable_ips(intel_crtc); | |
4676 | } | |
4677 | ||
7cac945f | 4678 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4679 | { |
7cac945f | 4680 | if (intel_crtc->overlay) { |
d3eedb1a VS |
4681 | struct drm_device *dev = intel_crtc->base.dev; |
4682 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4683 | ||
4684 | mutex_lock(&dev->struct_mutex); | |
4685 | dev_priv->mm.interruptible = false; | |
4686 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4687 | dev_priv->mm.interruptible = true; | |
4688 | mutex_unlock(&dev->struct_mutex); | |
4689 | } | |
4690 | ||
4691 | /* Let userspace switch the overlay on again. In most cases userspace | |
4692 | * has to recompute where to put it anyway. | |
4693 | */ | |
4694 | } | |
4695 | ||
87d4300a ML |
4696 | /** |
4697 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4698 | * @crtc: the CRTC whose primary plane was just enabled | |
4699 | * | |
4700 | * Performs potentially sleeping operations that must be done after the primary | |
4701 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4702 | * called due to an explicit primary plane update, or due to an implicit | |
4703 | * re-enable that is caused when a sprite plane is updated to no longer | |
4704 | * completely hide the primary plane. | |
4705 | */ | |
4706 | static void | |
4707 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4708 | { |
4709 | struct drm_device *dev = crtc->dev; | |
87d4300a | 4710 | struct drm_i915_private *dev_priv = dev->dev_private; |
a5c4d7bc VS |
4711 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4712 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4713 | |
87d4300a ML |
4714 | /* |
4715 | * FIXME IPS should be fine as long as one plane is | |
4716 | * enabled, but in practice it seems to have problems | |
4717 | * when going from primary only to sprite only and vice | |
4718 | * versa. | |
4719 | */ | |
a5c4d7bc VS |
4720 | hsw_enable_ips(intel_crtc); |
4721 | ||
f99d7069 | 4722 | /* |
87d4300a ML |
4723 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4724 | * So don't enable underrun reporting before at least some planes | |
4725 | * are enabled. | |
4726 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4727 | * but leave the pipe running. | |
f99d7069 | 4728 | */ |
87d4300a ML |
4729 | if (IS_GEN2(dev)) |
4730 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4731 | ||
aca7b684 VS |
4732 | /* Underruns don't always raise interrupts, so check manually. */ |
4733 | intel_check_cpu_fifo_underruns(dev_priv); | |
4734 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4735 | } |
4736 | ||
87d4300a ML |
4737 | /** |
4738 | * intel_pre_disable_primary - Perform operations before disabling primary plane | |
4739 | * @crtc: the CRTC whose primary plane is to be disabled | |
4740 | * | |
4741 | * Performs potentially sleeping operations that must be done before the | |
4742 | * primary plane is disabled, such as updating FBC and IPS. Note that this may | |
4743 | * be called due to an explicit primary plane update, or due to an implicit | |
4744 | * disable that is caused when a sprite plane completely hides the primary | |
4745 | * plane. | |
4746 | */ | |
4747 | static void | |
4748 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4749 | { |
4750 | struct drm_device *dev = crtc->dev; | |
4751 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4752 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4753 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4754 | |
87d4300a ML |
4755 | /* |
4756 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4757 | * So diasble underrun reporting before all the planes get disabled. | |
4758 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4759 | * but leave the pipe running. | |
4760 | */ | |
4761 | if (IS_GEN2(dev)) | |
4762 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4763 | |
87d4300a ML |
4764 | /* |
4765 | * Vblank time updates from the shadow to live plane control register | |
4766 | * are blocked if the memory self-refresh mode is active at that | |
4767 | * moment. So to make sure the plane gets truly disabled, disable | |
4768 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4769 | * will be checked/applied by the HW only at the next frame start | |
4770 | * event which is after the vblank start event, so we need to have a | |
4771 | * wait-for-vblank between disabling the plane and the pipe. | |
4772 | */ | |
262cd2e1 | 4773 | if (HAS_GMCH_DISPLAY(dev)) { |
87d4300a | 4774 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 VS |
4775 | dev_priv->wm.vlv.cxsr = false; |
4776 | intel_wait_for_vblank(dev, pipe); | |
4777 | } | |
87d4300a | 4778 | |
87d4300a ML |
4779 | /* |
4780 | * FIXME IPS should be fine as long as one plane is | |
4781 | * enabled, but in practice it seems to have problems | |
4782 | * when going from primary only to sprite only and vice | |
4783 | * versa. | |
4784 | */ | |
a5c4d7bc | 4785 | hsw_disable_ips(intel_crtc); |
87d4300a ML |
4786 | } |
4787 | ||
ac21b225 ML |
4788 | static void intel_post_plane_update(struct intel_crtc *crtc) |
4789 | { | |
4790 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; | |
92826fcd ML |
4791 | struct intel_crtc_state *pipe_config = |
4792 | to_intel_crtc_state(crtc->base.state); | |
ac21b225 | 4793 | struct drm_device *dev = crtc->base.dev; |
ac21b225 ML |
4794 | |
4795 | if (atomic->wait_vblank) | |
4796 | intel_wait_for_vblank(dev, crtc->pipe); | |
4797 | ||
4798 | intel_frontbuffer_flip(dev, atomic->fb_bits); | |
4799 | ||
ab1d3a0e | 4800 | crtc->wm.cxsr_allowed = true; |
852eb00d | 4801 | |
b9001114 | 4802 | if (pipe_config->wm_changed && pipe_config->base.active) |
f015c551 VS |
4803 | intel_update_watermarks(&crtc->base); |
4804 | ||
c80ac854 | 4805 | if (atomic->update_fbc) |
754d1133 | 4806 | intel_fbc_update(crtc); |
ac21b225 ML |
4807 | |
4808 | if (atomic->post_enable_primary) | |
4809 | intel_post_enable_primary(&crtc->base); | |
4810 | ||
ac21b225 ML |
4811 | memset(atomic, 0, sizeof(*atomic)); |
4812 | } | |
4813 | ||
4814 | static void intel_pre_plane_update(struct intel_crtc *crtc) | |
4815 | { | |
4816 | struct drm_device *dev = crtc->base.dev; | |
eddfcbcd | 4817 | struct drm_i915_private *dev_priv = dev->dev_private; |
ac21b225 | 4818 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; |
ab1d3a0e ML |
4819 | struct intel_crtc_state *pipe_config = |
4820 | to_intel_crtc_state(crtc->base.state); | |
ac21b225 | 4821 | |
c80ac854 | 4822 | if (atomic->disable_fbc) |
d029bcad | 4823 | intel_fbc_deactivate(crtc); |
ac21b225 | 4824 | |
066cf55b RV |
4825 | if (crtc->atomic.disable_ips) |
4826 | hsw_disable_ips(crtc); | |
4827 | ||
ac21b225 ML |
4828 | if (atomic->pre_disable_primary) |
4829 | intel_pre_disable_primary(&crtc->base); | |
852eb00d | 4830 | |
ab1d3a0e | 4831 | if (pipe_config->disable_cxsr) { |
852eb00d VS |
4832 | crtc->wm.cxsr_allowed = false; |
4833 | intel_set_memory_cxsr(dev_priv, false); | |
4834 | } | |
92826fcd | 4835 | |
396e33ae MR |
4836 | /* |
4837 | * IVB workaround: must disable low power watermarks for at least | |
4838 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
4839 | * when scaling is disabled. | |
4840 | * | |
4841 | * WaCxSRDisabledForSpriteScaling:ivb | |
4842 | */ | |
4843 | if (pipe_config->disable_lp_wm) { | |
4844 | ilk_disable_lp_wm(dev); | |
4845 | intel_wait_for_vblank(dev, crtc->pipe); | |
4846 | } | |
4847 | ||
4848 | /* | |
4849 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
4850 | * watermark programming here. | |
4851 | */ | |
4852 | if (needs_modeset(&pipe_config->base)) | |
4853 | return; | |
4854 | ||
4855 | /* | |
4856 | * For platforms that support atomic watermarks, program the | |
4857 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
4858 | * will be the intermediate values that are safe for both pre- and | |
4859 | * post- vblank; when vblank happens, the 'active' values will be set | |
4860 | * to the final 'target' values and we'll do this again to get the | |
4861 | * optimal watermarks. For gen9+ platforms, the values we program here | |
4862 | * will be the final target values which will get automatically latched | |
4863 | * at vblank time; no further programming will be necessary. | |
4864 | * | |
4865 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
4866 | * we'll continue to update watermarks the old way, if flags tell | |
4867 | * us to. | |
4868 | */ | |
4869 | if (dev_priv->display.initial_watermarks != NULL) | |
4870 | dev_priv->display.initial_watermarks(pipe_config); | |
4871 | else if (pipe_config->wm_changed) | |
92826fcd | 4872 | intel_update_watermarks(&crtc->base); |
ac21b225 ML |
4873 | } |
4874 | ||
d032ffa0 | 4875 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
4876 | { |
4877 | struct drm_device *dev = crtc->dev; | |
4878 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 4879 | struct drm_plane *p; |
87d4300a ML |
4880 | int pipe = intel_crtc->pipe; |
4881 | ||
7cac945f | 4882 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 4883 | |
d032ffa0 ML |
4884 | drm_for_each_plane_mask(p, dev, plane_mask) |
4885 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 4886 | |
f99d7069 DV |
4887 | /* |
4888 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4889 | * to compute the mask of flip planes precisely. For the time being | |
4890 | * consider this a flip to a NULL plane. | |
4891 | */ | |
4892 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4893 | } |
4894 | ||
f67a559d JB |
4895 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4896 | { | |
4897 | struct drm_device *dev = crtc->dev; | |
4898 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4899 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4900 | struct intel_encoder *encoder; |
f67a559d | 4901 | int pipe = intel_crtc->pipe; |
f67a559d | 4902 | |
53d9f4e9 | 4903 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
4904 | return; |
4905 | ||
81b088ca VS |
4906 | if (intel_crtc->config->has_pch_encoder) |
4907 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
4908 | ||
6e3c9717 | 4909 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4910 | intel_prepare_shared_dpll(intel_crtc); |
4911 | ||
6e3c9717 | 4912 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4913 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4914 | |
4915 | intel_set_pipe_timings(intel_crtc); | |
4916 | ||
6e3c9717 | 4917 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4918 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4919 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4920 | } |
4921 | ||
4922 | ironlake_set_pipeconf(crtc); | |
4923 | ||
f67a559d | 4924 | intel_crtc->active = true; |
8664281b | 4925 | |
a72e4c9f | 4926 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
8664281b | 4927 | |
f6736a1a | 4928 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4929 | if (encoder->pre_enable) |
4930 | encoder->pre_enable(encoder); | |
f67a559d | 4931 | |
6e3c9717 | 4932 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4933 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4934 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4935 | * enabling. */ | |
88cefb6c | 4936 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4937 | } else { |
4938 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4939 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4940 | } | |
f67a559d | 4941 | |
b074cec8 | 4942 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4943 | |
9c54c0dd JB |
4944 | /* |
4945 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4946 | * clocks enabled | |
4947 | */ | |
4948 | intel_crtc_load_lut(crtc); | |
4949 | ||
f37fcc2a | 4950 | intel_update_watermarks(crtc); |
e1fdc473 | 4951 | intel_enable_pipe(intel_crtc); |
f67a559d | 4952 | |
6e3c9717 | 4953 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4954 | ironlake_pch_enable(crtc); |
c98e9dcf | 4955 | |
f9b61ff6 DV |
4956 | assert_vblank_disabled(crtc); |
4957 | drm_crtc_vblank_on(crtc); | |
4958 | ||
fa5c73b1 DV |
4959 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4960 | encoder->enable(encoder); | |
61b77ddd DV |
4961 | |
4962 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4963 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
4964 | |
4965 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
4966 | if (intel_crtc->config->has_pch_encoder) | |
4967 | intel_wait_for_vblank(dev, pipe); | |
4968 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
d029bcad PZ |
4969 | |
4970 | intel_fbc_enable(intel_crtc); | |
6be4a607 JB |
4971 | } |
4972 | ||
42db64ef PZ |
4973 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4974 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4975 | { | |
f5adf94e | 4976 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4977 | } |
4978 | ||
4f771f10 PZ |
4979 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4980 | { | |
4981 | struct drm_device *dev = crtc->dev; | |
4982 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4983 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4984 | struct intel_encoder *encoder; | |
99d736a2 ML |
4985 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4986 | struct intel_crtc_state *pipe_config = | |
4987 | to_intel_crtc_state(crtc->state); | |
4f771f10 | 4988 | |
53d9f4e9 | 4989 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
4990 | return; |
4991 | ||
81b088ca VS |
4992 | if (intel_crtc->config->has_pch_encoder) |
4993 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
4994 | false); | |
4995 | ||
df8ad70c DV |
4996 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4997 | intel_enable_shared_dpll(intel_crtc); | |
4998 | ||
6e3c9717 | 4999 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 5000 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 DV |
5001 | |
5002 | intel_set_pipe_timings(intel_crtc); | |
5003 | ||
6e3c9717 ACO |
5004 | if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
5005 | I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), | |
5006 | intel_crtc->config->pixel_multiplier - 1); | |
ebb69c95 CT |
5007 | } |
5008 | ||
6e3c9717 | 5009 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 5010 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5011 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
5012 | } |
5013 | ||
5014 | haswell_set_pipeconf(crtc); | |
5015 | ||
5016 | intel_set_pipe_csc(crtc); | |
5017 | ||
4f771f10 | 5018 | intel_crtc->active = true; |
8664281b | 5019 | |
6b698516 DV |
5020 | if (intel_crtc->config->has_pch_encoder) |
5021 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5022 | else | |
5023 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5024 | ||
7d4aefd0 | 5025 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 PZ |
5026 | if (encoder->pre_enable) |
5027 | encoder->pre_enable(encoder); | |
7d4aefd0 | 5028 | } |
4f771f10 | 5029 | |
d2d65408 | 5030 | if (intel_crtc->config->has_pch_encoder) |
4fe9467d | 5031 | dev_priv->display.fdi_link_train(crtc); |
4fe9467d | 5032 | |
a65347ba | 5033 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5034 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 5035 | |
1c132b44 | 5036 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5037 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 5038 | else |
1c132b44 | 5039 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
5040 | |
5041 | /* | |
5042 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5043 | * clocks enabled | |
5044 | */ | |
5045 | intel_crtc_load_lut(crtc); | |
5046 | ||
1f544388 | 5047 | intel_ddi_set_pipe_settings(crtc); |
a65347ba | 5048 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5049 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 5050 | |
f37fcc2a | 5051 | intel_update_watermarks(crtc); |
e1fdc473 | 5052 | intel_enable_pipe(intel_crtc); |
42db64ef | 5053 | |
6e3c9717 | 5054 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 5055 | lpt_pch_enable(crtc); |
4f771f10 | 5056 | |
a65347ba | 5057 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
5058 | intel_ddi_set_vc_payload_alloc(crtc, true); |
5059 | ||
f9b61ff6 DV |
5060 | assert_vblank_disabled(crtc); |
5061 | drm_crtc_vblank_on(crtc); | |
5062 | ||
8807e55b | 5063 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 5064 | encoder->enable(encoder); |
8807e55b JN |
5065 | intel_opregion_notify_encoder(encoder, true); |
5066 | } | |
4f771f10 | 5067 | |
6b698516 DV |
5068 | if (intel_crtc->config->has_pch_encoder) { |
5069 | intel_wait_for_vblank(dev, pipe); | |
5070 | intel_wait_for_vblank(dev, pipe); | |
5071 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
d2d65408 VS |
5072 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5073 | true); | |
6b698516 | 5074 | } |
d2d65408 | 5075 | |
e4916946 PZ |
5076 | /* If we change the relative order between pipe/planes enabling, we need |
5077 | * to change the workaround. */ | |
99d736a2 ML |
5078 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
5079 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { | |
5080 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5081 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5082 | } | |
d029bcad PZ |
5083 | |
5084 | intel_fbc_enable(intel_crtc); | |
4f771f10 PZ |
5085 | } |
5086 | ||
bfd16b2a | 5087 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
5088 | { |
5089 | struct drm_device *dev = crtc->base.dev; | |
5090 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5091 | int pipe = crtc->pipe; | |
5092 | ||
5093 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5094 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5095 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5096 | I915_WRITE(PF_CTL(pipe), 0); |
5097 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5098 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5099 | } | |
5100 | } | |
5101 | ||
6be4a607 JB |
5102 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
5103 | { | |
5104 | struct drm_device *dev = crtc->dev; | |
5105 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5106 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5107 | struct intel_encoder *encoder; |
6be4a607 | 5108 | int pipe = intel_crtc->pipe; |
b52eb4dc | 5109 | |
37ca8d4c VS |
5110 | if (intel_crtc->config->has_pch_encoder) |
5111 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
5112 | ||
ea9d758d DV |
5113 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5114 | encoder->disable(encoder); | |
5115 | ||
f9b61ff6 DV |
5116 | drm_crtc_vblank_off(crtc); |
5117 | assert_vblank_disabled(crtc); | |
5118 | ||
3860b2ec VS |
5119 | /* |
5120 | * Sometimes spurious CPU pipe underruns happen when the | |
5121 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
5122 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
5123 | */ | |
5124 | if (intel_crtc->config->has_pch_encoder) | |
5125 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5126 | ||
575f7ab7 | 5127 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5128 | |
bfd16b2a | 5129 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5130 | |
3860b2ec | 5131 | if (intel_crtc->config->has_pch_encoder) { |
5a74f70a | 5132 | ironlake_fdi_disable(crtc); |
3860b2ec VS |
5133 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5134 | } | |
5a74f70a | 5135 | |
bf49ec8c DV |
5136 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5137 | if (encoder->post_disable) | |
5138 | encoder->post_disable(encoder); | |
2c07245f | 5139 | |
6e3c9717 | 5140 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5141 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5142 | |
d925c59a | 5143 | if (HAS_PCH_CPT(dev)) { |
f0f59a00 VS |
5144 | i915_reg_t reg; |
5145 | u32 temp; | |
5146 | ||
d925c59a DV |
5147 | /* disable TRANS_DP_CTL */ |
5148 | reg = TRANS_DP_CTL(pipe); | |
5149 | temp = I915_READ(reg); | |
5150 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5151 | TRANS_DP_PORT_SEL_MASK); | |
5152 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5153 | I915_WRITE(reg, temp); | |
5154 | ||
5155 | /* disable DPLL_SEL */ | |
5156 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5157 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5158 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5159 | } |
e3421a18 | 5160 | |
d925c59a DV |
5161 | ironlake_fdi_pll_disable(intel_crtc); |
5162 | } | |
81b088ca VS |
5163 | |
5164 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
d029bcad PZ |
5165 | |
5166 | intel_fbc_disable_crtc(intel_crtc); | |
6be4a607 | 5167 | } |
1b3c7a47 | 5168 | |
4f771f10 | 5169 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5170 | { |
4f771f10 PZ |
5171 | struct drm_device *dev = crtc->dev; |
5172 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 5173 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5174 | struct intel_encoder *encoder; |
6e3c9717 | 5175 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5176 | |
d2d65408 VS |
5177 | if (intel_crtc->config->has_pch_encoder) |
5178 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5179 | false); | |
5180 | ||
8807e55b JN |
5181 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5182 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5183 | encoder->disable(encoder); |
8807e55b | 5184 | } |
4f771f10 | 5185 | |
f9b61ff6 DV |
5186 | drm_crtc_vblank_off(crtc); |
5187 | assert_vblank_disabled(crtc); | |
5188 | ||
575f7ab7 | 5189 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5190 | |
6e3c9717 | 5191 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5192 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5193 | ||
a65347ba | 5194 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5195 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5196 | |
1c132b44 | 5197 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5198 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5199 | else |
bfd16b2a | 5200 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5201 | |
a65347ba | 5202 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5203 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5204 | |
97b040aa ID |
5205 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5206 | if (encoder->post_disable) | |
5207 | encoder->post_disable(encoder); | |
81b088ca | 5208 | |
92966a37 VS |
5209 | if (intel_crtc->config->has_pch_encoder) { |
5210 | lpt_disable_pch_transcoder(dev_priv); | |
503a74e9 | 5211 | lpt_disable_iclkip(dev_priv); |
92966a37 VS |
5212 | intel_ddi_fdi_disable(crtc); |
5213 | ||
81b088ca VS |
5214 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5215 | true); | |
92966a37 | 5216 | } |
d029bcad PZ |
5217 | |
5218 | intel_fbc_disable_crtc(intel_crtc); | |
4f771f10 PZ |
5219 | } |
5220 | ||
2dd24552 JB |
5221 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5222 | { | |
5223 | struct drm_device *dev = crtc->base.dev; | |
5224 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 5225 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5226 | |
681a8504 | 5227 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5228 | return; |
5229 | ||
2dd24552 | 5230 | /* |
c0b03411 DV |
5231 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5232 | * according to register description and PRM. | |
2dd24552 | 5233 | */ |
c0b03411 DV |
5234 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5235 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5236 | |
b074cec8 JB |
5237 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5238 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5239 | |
5240 | /* Border color in case we don't scale up to the full screen. Black by | |
5241 | * default, change to something else for debugging. */ | |
5242 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5243 | } |
5244 | ||
d05410f9 DA |
5245 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5246 | { | |
5247 | switch (port) { | |
5248 | case PORT_A: | |
6331a704 | 5249 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5250 | case PORT_B: |
6331a704 | 5251 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5252 | case PORT_C: |
6331a704 | 5253 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5254 | case PORT_D: |
6331a704 | 5255 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5256 | case PORT_E: |
6331a704 | 5257 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5258 | default: |
b9fec167 | 5259 | MISSING_CASE(port); |
d05410f9 DA |
5260 | return POWER_DOMAIN_PORT_OTHER; |
5261 | } | |
5262 | } | |
5263 | ||
25f78f58 VS |
5264 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
5265 | { | |
5266 | switch (port) { | |
5267 | case PORT_A: | |
5268 | return POWER_DOMAIN_AUX_A; | |
5269 | case PORT_B: | |
5270 | return POWER_DOMAIN_AUX_B; | |
5271 | case PORT_C: | |
5272 | return POWER_DOMAIN_AUX_C; | |
5273 | case PORT_D: | |
5274 | return POWER_DOMAIN_AUX_D; | |
5275 | case PORT_E: | |
5276 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5277 | return POWER_DOMAIN_AUX_D; | |
5278 | default: | |
b9fec167 | 5279 | MISSING_CASE(port); |
25f78f58 VS |
5280 | return POWER_DOMAIN_AUX_A; |
5281 | } | |
5282 | } | |
5283 | ||
319be8ae ID |
5284 | enum intel_display_power_domain |
5285 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5286 | { | |
5287 | struct drm_device *dev = intel_encoder->base.dev; | |
5288 | struct intel_digital_port *intel_dig_port; | |
5289 | ||
5290 | switch (intel_encoder->type) { | |
5291 | case INTEL_OUTPUT_UNKNOWN: | |
5292 | /* Only DDI platforms should ever use this output type */ | |
5293 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5294 | case INTEL_OUTPUT_DISPLAYPORT: | |
5295 | case INTEL_OUTPUT_HDMI: | |
5296 | case INTEL_OUTPUT_EDP: | |
5297 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5298 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5299 | case INTEL_OUTPUT_DP_MST: |
5300 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5301 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5302 | case INTEL_OUTPUT_ANALOG: |
5303 | return POWER_DOMAIN_PORT_CRT; | |
5304 | case INTEL_OUTPUT_DSI: | |
5305 | return POWER_DOMAIN_PORT_DSI; | |
5306 | default: | |
5307 | return POWER_DOMAIN_PORT_OTHER; | |
5308 | } | |
5309 | } | |
5310 | ||
25f78f58 VS |
5311 | enum intel_display_power_domain |
5312 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) | |
5313 | { | |
5314 | struct drm_device *dev = intel_encoder->base.dev; | |
5315 | struct intel_digital_port *intel_dig_port; | |
5316 | ||
5317 | switch (intel_encoder->type) { | |
5318 | case INTEL_OUTPUT_UNKNOWN: | |
651174a4 ID |
5319 | case INTEL_OUTPUT_HDMI: |
5320 | /* | |
5321 | * Only DDI platforms should ever use these output types. | |
5322 | * We can get here after the HDMI detect code has already set | |
5323 | * the type of the shared encoder. Since we can't be sure | |
5324 | * what's the status of the given connectors, play safe and | |
5325 | * run the DP detection too. | |
5326 | */ | |
25f78f58 VS |
5327 | WARN_ON_ONCE(!HAS_DDI(dev)); |
5328 | case INTEL_OUTPUT_DISPLAYPORT: | |
5329 | case INTEL_OUTPUT_EDP: | |
5330 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
5331 | return port_to_aux_power_domain(intel_dig_port->port); | |
5332 | case INTEL_OUTPUT_DP_MST: | |
5333 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5334 | return port_to_aux_power_domain(intel_dig_port->port); | |
5335 | default: | |
b9fec167 | 5336 | MISSING_CASE(intel_encoder->type); |
25f78f58 VS |
5337 | return POWER_DOMAIN_AUX_A; |
5338 | } | |
5339 | } | |
5340 | ||
319be8ae | 5341 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) |
77d22dca | 5342 | { |
319be8ae ID |
5343 | struct drm_device *dev = crtc->dev; |
5344 | struct intel_encoder *intel_encoder; | |
5345 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5346 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca | 5347 | unsigned long mask; |
1a70a728 | 5348 | enum transcoder transcoder = intel_crtc->config->cpu_transcoder; |
77d22dca | 5349 | |
292b990e ML |
5350 | if (!crtc->state->active) |
5351 | return 0; | |
5352 | ||
77d22dca ID |
5353 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5354 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
6e3c9717 ACO |
5355 | if (intel_crtc->config->pch_pfit.enabled || |
5356 | intel_crtc->config->pch_pfit.force_thru) | |
77d22dca ID |
5357 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5358 | ||
319be8ae ID |
5359 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
5360 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
5361 | ||
77d22dca ID |
5362 | return mask; |
5363 | } | |
5364 | ||
292b990e | 5365 | static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc) |
77d22dca | 5366 | { |
292b990e ML |
5367 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5368 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5369 | enum intel_display_power_domain domain; | |
5370 | unsigned long domains, new_domains, old_domains; | |
77d22dca | 5371 | |
292b990e ML |
5372 | old_domains = intel_crtc->enabled_power_domains; |
5373 | intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc); | |
77d22dca | 5374 | |
292b990e ML |
5375 | domains = new_domains & ~old_domains; |
5376 | ||
5377 | for_each_power_domain(domain, domains) | |
5378 | intel_display_power_get(dev_priv, domain); | |
5379 | ||
5380 | return old_domains & ~new_domains; | |
5381 | } | |
5382 | ||
5383 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5384 | unsigned long domains) | |
5385 | { | |
5386 | enum intel_display_power_domain domain; | |
5387 | ||
5388 | for_each_power_domain(domain, domains) | |
5389 | intel_display_power_put(dev_priv, domain); | |
5390 | } | |
77d22dca | 5391 | |
292b990e ML |
5392 | static void modeset_update_crtc_power_domains(struct drm_atomic_state *state) |
5393 | { | |
1a617b77 | 5394 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
292b990e ML |
5395 | struct drm_device *dev = state->dev; |
5396 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5397 | unsigned long put_domains[I915_MAX_PIPES] = {}; | |
5398 | struct drm_crtc_state *crtc_state; | |
5399 | struct drm_crtc *crtc; | |
5400 | int i; | |
77d22dca | 5401 | |
292b990e ML |
5402 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
5403 | if (needs_modeset(crtc->state)) | |
5404 | put_domains[to_intel_crtc(crtc)->pipe] = | |
5405 | modeset_get_crtc_power_domains(crtc); | |
77d22dca ID |
5406 | } |
5407 | ||
1a617b77 ML |
5408 | if (dev_priv->display.modeset_commit_cdclk && |
5409 | intel_state->dev_cdclk != dev_priv->cdclk_freq) | |
5410 | dev_priv->display.modeset_commit_cdclk(state); | |
50f6e502 | 5411 | |
292b990e ML |
5412 | for (i = 0; i < I915_MAX_PIPES; i++) |
5413 | if (put_domains[i]) | |
5414 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
77d22dca ID |
5415 | } |
5416 | ||
adafdc6f MK |
5417 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5418 | { | |
5419 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5420 | ||
5421 | if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5422 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
5423 | return max_cdclk_freq; | |
5424 | else if (IS_CHERRYVIEW(dev_priv)) | |
5425 | return max_cdclk_freq*95/100; | |
5426 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5427 | return 2*max_cdclk_freq*90/100; | |
5428 | else | |
5429 | return max_cdclk_freq*90/100; | |
5430 | } | |
5431 | ||
560a7ae4 DL |
5432 | static void intel_update_max_cdclk(struct drm_device *dev) |
5433 | { | |
5434 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5435 | ||
ef11bdb3 | 5436 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
560a7ae4 DL |
5437 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
5438 | ||
5439 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) | |
5440 | dev_priv->max_cdclk_freq = 675000; | |
5441 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) | |
5442 | dev_priv->max_cdclk_freq = 540000; | |
5443 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) | |
5444 | dev_priv->max_cdclk_freq = 450000; | |
5445 | else | |
5446 | dev_priv->max_cdclk_freq = 337500; | |
5447 | } else if (IS_BROADWELL(dev)) { | |
5448 | /* | |
5449 | * FIXME with extra cooling we can allow | |
5450 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5451 | * How can we know if extra cooling is | |
5452 | * available? PCI ID, VTB, something else? | |
5453 | */ | |
5454 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5455 | dev_priv->max_cdclk_freq = 450000; | |
5456 | else if (IS_BDW_ULX(dev)) | |
5457 | dev_priv->max_cdclk_freq = 450000; | |
5458 | else if (IS_BDW_ULT(dev)) | |
5459 | dev_priv->max_cdclk_freq = 540000; | |
5460 | else | |
5461 | dev_priv->max_cdclk_freq = 675000; | |
0904deaf MK |
5462 | } else if (IS_CHERRYVIEW(dev)) { |
5463 | dev_priv->max_cdclk_freq = 320000; | |
560a7ae4 DL |
5464 | } else if (IS_VALLEYVIEW(dev)) { |
5465 | dev_priv->max_cdclk_freq = 400000; | |
5466 | } else { | |
5467 | /* otherwise assume cdclk is fixed */ | |
5468 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5469 | } | |
5470 | ||
adafdc6f MK |
5471 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5472 | ||
560a7ae4 DL |
5473 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5474 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5475 | |
5476 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5477 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5478 | } |
5479 | ||
5480 | static void intel_update_cdclk(struct drm_device *dev) | |
5481 | { | |
5482 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5483 | ||
5484 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
5485 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5486 | dev_priv->cdclk_freq); | |
5487 | ||
5488 | /* | |
5489 | * Program the gmbus_freq based on the cdclk frequency. | |
5490 | * BSpec erroneously claims we should aim for 4MHz, but | |
5491 | * in fact 1MHz is the correct frequency. | |
5492 | */ | |
666a4537 | 5493 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
560a7ae4 DL |
5494 | /* |
5495 | * Program the gmbus_freq based on the cdclk frequency. | |
5496 | * BSpec erroneously claims we should aim for 4MHz, but | |
5497 | * in fact 1MHz is the correct frequency. | |
5498 | */ | |
5499 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); | |
5500 | } | |
5501 | ||
5502 | if (dev_priv->max_cdclk_freq == 0) | |
5503 | intel_update_max_cdclk(dev); | |
5504 | } | |
5505 | ||
70d0c574 | 5506 | static void broxton_set_cdclk(struct drm_device *dev, int frequency) |
f8437dd1 VK |
5507 | { |
5508 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5509 | uint32_t divider; | |
5510 | uint32_t ratio; | |
5511 | uint32_t current_freq; | |
5512 | int ret; | |
5513 | ||
5514 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ | |
5515 | switch (frequency) { | |
5516 | case 144000: | |
5517 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
5518 | ratio = BXT_DE_PLL_RATIO(60); | |
5519 | break; | |
5520 | case 288000: | |
5521 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
5522 | ratio = BXT_DE_PLL_RATIO(60); | |
5523 | break; | |
5524 | case 384000: | |
5525 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
5526 | ratio = BXT_DE_PLL_RATIO(60); | |
5527 | break; | |
5528 | case 576000: | |
5529 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5530 | ratio = BXT_DE_PLL_RATIO(60); | |
5531 | break; | |
5532 | case 624000: | |
5533 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5534 | ratio = BXT_DE_PLL_RATIO(65); | |
5535 | break; | |
5536 | case 19200: | |
5537 | /* | |
5538 | * Bypass frequency with DE PLL disabled. Init ratio, divider | |
5539 | * to suppress GCC warning. | |
5540 | */ | |
5541 | ratio = 0; | |
5542 | divider = 0; | |
5543 | break; | |
5544 | default: | |
5545 | DRM_ERROR("unsupported CDCLK freq %d", frequency); | |
5546 | ||
5547 | return; | |
5548 | } | |
5549 | ||
5550 | mutex_lock(&dev_priv->rps.hw_lock); | |
5551 | /* Inform power controller of upcoming frequency change */ | |
5552 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5553 | 0x80000000); | |
5554 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5555 | ||
5556 | if (ret) { | |
5557 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
5558 | ret, frequency); | |
5559 | return; | |
5560 | } | |
5561 | ||
5562 | current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; | |
5563 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ | |
5564 | current_freq = current_freq * 500 + 1000; | |
5565 | ||
5566 | /* | |
5567 | * DE PLL has to be disabled when | |
5568 | * - setting to 19.2MHz (bypass, PLL isn't used) | |
5569 | * - before setting to 624MHz (PLL needs toggling) | |
5570 | * - before setting to any frequency from 624MHz (PLL needs toggling) | |
5571 | */ | |
5572 | if (frequency == 19200 || frequency == 624000 || | |
5573 | current_freq == 624000) { | |
5574 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); | |
5575 | /* Timeout 200us */ | |
5576 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), | |
5577 | 1)) | |
5578 | DRM_ERROR("timout waiting for DE PLL unlock\n"); | |
5579 | } | |
5580 | ||
5581 | if (frequency != 19200) { | |
5582 | uint32_t val; | |
5583 | ||
5584 | val = I915_READ(BXT_DE_PLL_CTL); | |
5585 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5586 | val |= ratio; | |
5587 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
5588 | ||
5589 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5590 | /* Timeout 200us */ | |
5591 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) | |
5592 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
5593 | ||
5594 | val = I915_READ(CDCLK_CTL); | |
5595 | val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
5596 | val |= divider; | |
5597 | /* | |
5598 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5599 | * enable otherwise. | |
5600 | */ | |
5601 | val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5602 | if (frequency >= 500000) | |
5603 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5604 | ||
5605 | val &= ~CDCLK_FREQ_DECIMAL_MASK; | |
5606 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
5607 | val |= (frequency - 1000) / 500; | |
5608 | I915_WRITE(CDCLK_CTL, val); | |
5609 | } | |
5610 | ||
5611 | mutex_lock(&dev_priv->rps.hw_lock); | |
5612 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5613 | DIV_ROUND_UP(frequency, 25000)); | |
5614 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5615 | ||
5616 | if (ret) { | |
5617 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
5618 | ret, frequency); | |
5619 | return; | |
5620 | } | |
5621 | ||
a47871bd | 5622 | intel_update_cdclk(dev); |
f8437dd1 VK |
5623 | } |
5624 | ||
5625 | void broxton_init_cdclk(struct drm_device *dev) | |
5626 | { | |
5627 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5628 | uint32_t val; | |
5629 | ||
5630 | /* | |
5631 | * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT | |
5632 | * or else the reset will hang because there is no PCH to respond. | |
5633 | * Move the handshake programming to initialization sequence. | |
5634 | * Previously was left up to BIOS. | |
5635 | */ | |
5636 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5637 | val &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
5638 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val); | |
5639 | ||
5640 | /* Enable PG1 for cdclk */ | |
5641 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5642 | ||
5643 | /* check if cd clock is enabled */ | |
5644 | if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { | |
5645 | DRM_DEBUG_KMS("Display already initialized\n"); | |
5646 | return; | |
5647 | } | |
5648 | ||
5649 | /* | |
5650 | * FIXME: | |
5651 | * - The initial CDCLK needs to be read from VBT. | |
5652 | * Need to make this change after VBT has changes for BXT. | |
5653 | * - check if setting the max (or any) cdclk freq is really necessary | |
5654 | * here, it belongs to modeset time | |
5655 | */ | |
5656 | broxton_set_cdclk(dev, 624000); | |
5657 | ||
5658 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
22e02c0b VS |
5659 | POSTING_READ(DBUF_CTL); |
5660 | ||
f8437dd1 VK |
5661 | udelay(10); |
5662 | ||
5663 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5664 | DRM_ERROR("DBuf power enable timeout!\n"); | |
5665 | } | |
5666 | ||
5667 | void broxton_uninit_cdclk(struct drm_device *dev) | |
5668 | { | |
5669 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5670 | ||
5671 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
22e02c0b VS |
5672 | POSTING_READ(DBUF_CTL); |
5673 | ||
f8437dd1 VK |
5674 | udelay(10); |
5675 | ||
5676 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5677 | DRM_ERROR("DBuf power disable timeout!\n"); | |
5678 | ||
5679 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ | |
5680 | broxton_set_cdclk(dev, 19200); | |
5681 | ||
5682 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5683 | } | |
5684 | ||
5d96d8af DL |
5685 | static const struct skl_cdclk_entry { |
5686 | unsigned int freq; | |
5687 | unsigned int vco; | |
5688 | } skl_cdclk_frequencies[] = { | |
5689 | { .freq = 308570, .vco = 8640 }, | |
5690 | { .freq = 337500, .vco = 8100 }, | |
5691 | { .freq = 432000, .vco = 8640 }, | |
5692 | { .freq = 450000, .vco = 8100 }, | |
5693 | { .freq = 540000, .vco = 8100 }, | |
5694 | { .freq = 617140, .vco = 8640 }, | |
5695 | { .freq = 675000, .vco = 8100 }, | |
5696 | }; | |
5697 | ||
5698 | static unsigned int skl_cdclk_decimal(unsigned int freq) | |
5699 | { | |
5700 | return (freq - 1000) / 500; | |
5701 | } | |
5702 | ||
5703 | static unsigned int skl_cdclk_get_vco(unsigned int freq) | |
5704 | { | |
5705 | unsigned int i; | |
5706 | ||
5707 | for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) { | |
5708 | const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i]; | |
5709 | ||
5710 | if (e->freq == freq) | |
5711 | return e->vco; | |
5712 | } | |
5713 | ||
5714 | return 8100; | |
5715 | } | |
5716 | ||
5717 | static void | |
5718 | skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco) | |
5719 | { | |
5720 | unsigned int min_freq; | |
5721 | u32 val; | |
5722 | ||
5723 | /* select the minimum CDCLK before enabling DPLL 0 */ | |
5724 | val = I915_READ(CDCLK_CTL); | |
5725 | val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK; | |
5726 | val |= CDCLK_FREQ_337_308; | |
5727 | ||
5728 | if (required_vco == 8640) | |
5729 | min_freq = 308570; | |
5730 | else | |
5731 | min_freq = 337500; | |
5732 | ||
5733 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq); | |
5734 | ||
5735 | I915_WRITE(CDCLK_CTL, val); | |
5736 | POSTING_READ(CDCLK_CTL); | |
5737 | ||
5738 | /* | |
5739 | * We always enable DPLL0 with the lowest link rate possible, but still | |
5740 | * taking into account the VCO required to operate the eDP panel at the | |
5741 | * desired frequency. The usual DP link rates operate with a VCO of | |
5742 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
5743 | * The modeset code is responsible for the selection of the exact link | |
5744 | * rate later on, with the constraint of choosing a frequency that | |
5745 | * works with required_vco. | |
5746 | */ | |
5747 | val = I915_READ(DPLL_CTRL1); | |
5748 | ||
5749 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5750 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
5751 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
5752 | if (required_vco == 8640) | |
5753 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, | |
5754 | SKL_DPLL0); | |
5755 | else | |
5756 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
5757 | SKL_DPLL0); | |
5758 | ||
5759 | I915_WRITE(DPLL_CTRL1, val); | |
5760 | POSTING_READ(DPLL_CTRL1); | |
5761 | ||
5762 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
5763 | ||
5764 | if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) | |
5765 | DRM_ERROR("DPLL0 not locked\n"); | |
5766 | } | |
5767 | ||
5768 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) | |
5769 | { | |
5770 | int ret; | |
5771 | u32 val; | |
5772 | ||
5773 | /* inform PCU we want to change CDCLK */ | |
5774 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
5775 | mutex_lock(&dev_priv->rps.hw_lock); | |
5776 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
5777 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5778 | ||
5779 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
5780 | } | |
5781 | ||
5782 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
5783 | { | |
5784 | unsigned int i; | |
5785 | ||
5786 | for (i = 0; i < 15; i++) { | |
5787 | if (skl_cdclk_pcu_ready(dev_priv)) | |
5788 | return true; | |
5789 | udelay(10); | |
5790 | } | |
5791 | ||
5792 | return false; | |
5793 | } | |
5794 | ||
5795 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq) | |
5796 | { | |
560a7ae4 | 5797 | struct drm_device *dev = dev_priv->dev; |
5d96d8af DL |
5798 | u32 freq_select, pcu_ack; |
5799 | ||
5800 | DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq); | |
5801 | ||
5802 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
5803 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
5804 | return; | |
5805 | } | |
5806 | ||
5807 | /* set CDCLK_CTL */ | |
5808 | switch(freq) { | |
5809 | case 450000: | |
5810 | case 432000: | |
5811 | freq_select = CDCLK_FREQ_450_432; | |
5812 | pcu_ack = 1; | |
5813 | break; | |
5814 | case 540000: | |
5815 | freq_select = CDCLK_FREQ_540; | |
5816 | pcu_ack = 2; | |
5817 | break; | |
5818 | case 308570: | |
5819 | case 337500: | |
5820 | default: | |
5821 | freq_select = CDCLK_FREQ_337_308; | |
5822 | pcu_ack = 0; | |
5823 | break; | |
5824 | case 617140: | |
5825 | case 675000: | |
5826 | freq_select = CDCLK_FREQ_675_617; | |
5827 | pcu_ack = 3; | |
5828 | break; | |
5829 | } | |
5830 | ||
5831 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq)); | |
5832 | POSTING_READ(CDCLK_CTL); | |
5833 | ||
5834 | /* inform PCU of the change */ | |
5835 | mutex_lock(&dev_priv->rps.hw_lock); | |
5836 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
5837 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 DL |
5838 | |
5839 | intel_update_cdclk(dev); | |
5d96d8af DL |
5840 | } |
5841 | ||
5842 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
5843 | { | |
5844 | /* disable DBUF power */ | |
5845 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
5846 | POSTING_READ(DBUF_CTL); | |
5847 | ||
5848 | udelay(10); | |
5849 | ||
5850 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5851 | DRM_ERROR("DBuf power disable timeout\n"); | |
5852 | ||
ab96c1ee ID |
5853 | /* disable DPLL0 */ |
5854 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
5855 | if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) | |
5856 | DRM_ERROR("Couldn't disable DPLL0\n"); | |
5d96d8af DL |
5857 | } |
5858 | ||
5859 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
5860 | { | |
5d96d8af DL |
5861 | unsigned int required_vco; |
5862 | ||
39d9b85a GW |
5863 | /* DPLL0 not enabled (happens on early BIOS versions) */ |
5864 | if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) { | |
5865 | /* enable DPLL0 */ | |
5866 | required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); | |
5867 | skl_dpll0_enable(dev_priv, required_vco); | |
5d96d8af DL |
5868 | } |
5869 | ||
5d96d8af DL |
5870 | /* set CDCLK to the frequency the BIOS chose */ |
5871 | skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); | |
5872 | ||
5873 | /* enable DBUF power */ | |
5874 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
5875 | POSTING_READ(DBUF_CTL); | |
5876 | ||
5877 | udelay(10); | |
5878 | ||
5879 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5880 | DRM_ERROR("DBuf power enable timeout\n"); | |
5881 | } | |
5882 | ||
c73666f3 SK |
5883 | int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
5884 | { | |
5885 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
5886 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
5887 | int freq = dev_priv->skl_boot_cdclk; | |
5888 | ||
f1b391a5 SK |
5889 | /* |
5890 | * check if the pre-os intialized the display | |
5891 | * There is SWF18 scratchpad register defined which is set by the | |
5892 | * pre-os which can be used by the OS drivers to check the status | |
5893 | */ | |
5894 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
5895 | goto sanitize; | |
5896 | ||
c73666f3 SK |
5897 | /* Is PLL enabled and locked ? */ |
5898 | if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK))) | |
5899 | goto sanitize; | |
5900 | ||
5901 | /* DPLL okay; verify the cdclock | |
5902 | * | |
5903 | * Noticed in some instances that the freq selection is correct but | |
5904 | * decimal part is programmed wrong from BIOS where pre-os does not | |
5905 | * enable display. Verify the same as well. | |
5906 | */ | |
5907 | if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq))) | |
5908 | /* All well; nothing to sanitize */ | |
5909 | return false; | |
5910 | sanitize: | |
5911 | /* | |
5912 | * As of now initialize with max cdclk till | |
5913 | * we get dynamic cdclk support | |
5914 | * */ | |
5915 | dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq; | |
5916 | skl_init_cdclk(dev_priv); | |
5917 | ||
5918 | /* we did have to sanitize */ | |
5919 | return true; | |
5920 | } | |
5921 | ||
30a970c6 JB |
5922 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5923 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5924 | { | |
5925 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5926 | u32 val, cmd; | |
5927 | ||
164dfd28 VK |
5928 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5929 | != dev_priv->cdclk_freq); | |
d60c4473 | 5930 | |
dfcab17e | 5931 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5932 | cmd = 2; |
dfcab17e | 5933 | else if (cdclk == 266667) |
30a970c6 JB |
5934 | cmd = 1; |
5935 | else | |
5936 | cmd = 0; | |
5937 | ||
5938 | mutex_lock(&dev_priv->rps.hw_lock); | |
5939 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5940 | val &= ~DSPFREQGUAR_MASK; | |
5941 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5942 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5943 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5944 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5945 | 50)) { | |
5946 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5947 | } | |
5948 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5949 | ||
54433e91 VS |
5950 | mutex_lock(&dev_priv->sb_lock); |
5951 | ||
dfcab17e | 5952 | if (cdclk == 400000) { |
6bcda4f0 | 5953 | u32 divider; |
30a970c6 | 5954 | |
6bcda4f0 | 5955 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 5956 | |
30a970c6 JB |
5957 | /* adjust cdclk divider */ |
5958 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
87d5d259 | 5959 | val &= ~CCK_FREQUENCY_VALUES; |
30a970c6 JB |
5960 | val |= divider; |
5961 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5962 | |
5963 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
87d5d259 | 5964 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
a877e801 VS |
5965 | 50)) |
5966 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5967 | } |
5968 | ||
30a970c6 JB |
5969 | /* adjust self-refresh exit latency value */ |
5970 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5971 | val &= ~0x7f; | |
5972 | ||
5973 | /* | |
5974 | * For high bandwidth configs, we set a higher latency in the bunit | |
5975 | * so that the core display fetch happens in time to avoid underruns. | |
5976 | */ | |
dfcab17e | 5977 | if (cdclk == 400000) |
30a970c6 JB |
5978 | val |= 4500 / 250; /* 4.5 usec */ |
5979 | else | |
5980 | val |= 3000 / 250; /* 3.0 usec */ | |
5981 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 5982 | |
a580516d | 5983 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5984 | |
b6283055 | 5985 | intel_update_cdclk(dev); |
30a970c6 JB |
5986 | } |
5987 | ||
383c5a6a VS |
5988 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5989 | { | |
5990 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5991 | u32 val, cmd; | |
5992 | ||
164dfd28 VK |
5993 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5994 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5995 | |
5996 | switch (cdclk) { | |
383c5a6a VS |
5997 | case 333333: |
5998 | case 320000: | |
383c5a6a | 5999 | case 266667: |
383c5a6a | 6000 | case 200000: |
383c5a6a VS |
6001 | break; |
6002 | default: | |
5f77eeb0 | 6003 | MISSING_CASE(cdclk); |
383c5a6a VS |
6004 | return; |
6005 | } | |
6006 | ||
9d0d3fda VS |
6007 | /* |
6008 | * Specs are full of misinformation, but testing on actual | |
6009 | * hardware has shown that we just need to write the desired | |
6010 | * CCK divider into the Punit register. | |
6011 | */ | |
6012 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
6013 | ||
383c5a6a VS |
6014 | mutex_lock(&dev_priv->rps.hw_lock); |
6015 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
6016 | val &= ~DSPFREQGUAR_MASK_CHV; | |
6017 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
6018 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
6019 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
6020 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
6021 | 50)) { | |
6022 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
6023 | } | |
6024 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6025 | ||
b6283055 | 6026 | intel_update_cdclk(dev); |
383c5a6a VS |
6027 | } |
6028 | ||
30a970c6 JB |
6029 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
6030 | int max_pixclk) | |
6031 | { | |
6bcda4f0 | 6032 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 6033 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 6034 | |
30a970c6 JB |
6035 | /* |
6036 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
6037 | * 200MHz | |
6038 | * 267MHz | |
29dc7ef3 | 6039 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
6040 | * 400MHz (VLV only) |
6041 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
6042 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
6043 | * |
6044 | * We seem to get an unstable or solid color picture at 200MHz. | |
6045 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
6046 | * are off. | |
30a970c6 | 6047 | */ |
6cca3195 VS |
6048 | if (!IS_CHERRYVIEW(dev_priv) && |
6049 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 6050 | return 400000; |
6cca3195 | 6051 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 6052 | return freq_320; |
e37c67a1 | 6053 | else if (max_pixclk > 0) |
dfcab17e | 6054 | return 266667; |
e37c67a1 VS |
6055 | else |
6056 | return 200000; | |
30a970c6 JB |
6057 | } |
6058 | ||
f8437dd1 VK |
6059 | static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, |
6060 | int max_pixclk) | |
6061 | { | |
6062 | /* | |
6063 | * FIXME: | |
6064 | * - remove the guardband, it's not needed on BXT | |
6065 | * - set 19.2MHz bypass frequency if there are no active pipes | |
6066 | */ | |
6067 | if (max_pixclk > 576000*9/10) | |
6068 | return 624000; | |
6069 | else if (max_pixclk > 384000*9/10) | |
6070 | return 576000; | |
6071 | else if (max_pixclk > 288000*9/10) | |
6072 | return 384000; | |
6073 | else if (max_pixclk > 144000*9/10) | |
6074 | return 288000; | |
6075 | else | |
6076 | return 144000; | |
6077 | } | |
6078 | ||
a821fc46 ACO |
6079 | /* Compute the max pixel clock for new configuration. Uses atomic state if |
6080 | * that's non-NULL, look at current state otherwise. */ | |
6081 | static int intel_mode_max_pixclk(struct drm_device *dev, | |
6082 | struct drm_atomic_state *state) | |
30a970c6 | 6083 | { |
565602d7 ML |
6084 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
6085 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6086 | struct drm_crtc *crtc; | |
6087 | struct drm_crtc_state *crtc_state; | |
6088 | unsigned max_pixclk = 0, i; | |
6089 | enum pipe pipe; | |
30a970c6 | 6090 | |
565602d7 ML |
6091 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
6092 | sizeof(intel_state->min_pixclk)); | |
304603f4 | 6093 | |
565602d7 ML |
6094 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
6095 | int pixclk = 0; | |
6096 | ||
6097 | if (crtc_state->enable) | |
6098 | pixclk = crtc_state->adjusted_mode.crtc_clock; | |
304603f4 | 6099 | |
565602d7 | 6100 | intel_state->min_pixclk[i] = pixclk; |
30a970c6 JB |
6101 | } |
6102 | ||
565602d7 ML |
6103 | if (!intel_state->active_crtcs) |
6104 | return 0; | |
6105 | ||
6106 | for_each_pipe(dev_priv, pipe) | |
6107 | max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); | |
6108 | ||
30a970c6 JB |
6109 | return max_pixclk; |
6110 | } | |
6111 | ||
27c329ed | 6112 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 6113 | { |
27c329ed ML |
6114 | struct drm_device *dev = state->dev; |
6115 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6116 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
1a617b77 ML |
6117 | struct intel_atomic_state *intel_state = |
6118 | to_intel_atomic_state(state); | |
30a970c6 | 6119 | |
304603f4 ACO |
6120 | if (max_pixclk < 0) |
6121 | return max_pixclk; | |
30a970c6 | 6122 | |
1a617b77 | 6123 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 6124 | valleyview_calc_cdclk(dev_priv, max_pixclk); |
0a9ab303 | 6125 | |
1a617b77 ML |
6126 | if (!intel_state->active_crtcs) |
6127 | intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); | |
6128 | ||
27c329ed ML |
6129 | return 0; |
6130 | } | |
304603f4 | 6131 | |
27c329ed ML |
6132 | static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state) |
6133 | { | |
6134 | struct drm_device *dev = state->dev; | |
6135 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6136 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
1a617b77 ML |
6137 | struct intel_atomic_state *intel_state = |
6138 | to_intel_atomic_state(state); | |
85a96e7a | 6139 | |
27c329ed ML |
6140 | if (max_pixclk < 0) |
6141 | return max_pixclk; | |
85a96e7a | 6142 | |
1a617b77 | 6143 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 6144 | broxton_calc_cdclk(dev_priv, max_pixclk); |
85a96e7a | 6145 | |
1a617b77 ML |
6146 | if (!intel_state->active_crtcs) |
6147 | intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0); | |
6148 | ||
27c329ed | 6149 | return 0; |
30a970c6 JB |
6150 | } |
6151 | ||
1e69cd74 VS |
6152 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
6153 | { | |
6154 | unsigned int credits, default_credits; | |
6155 | ||
6156 | if (IS_CHERRYVIEW(dev_priv)) | |
6157 | default_credits = PFI_CREDIT(12); | |
6158 | else | |
6159 | default_credits = PFI_CREDIT(8); | |
6160 | ||
bfa7df01 | 6161 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
1e69cd74 VS |
6162 | /* CHV suggested value is 31 or 63 */ |
6163 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 6164 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
6165 | else |
6166 | credits = PFI_CREDIT(15); | |
6167 | } else { | |
6168 | credits = default_credits; | |
6169 | } | |
6170 | ||
6171 | /* | |
6172 | * WA - write default credits before re-programming | |
6173 | * FIXME: should we also set the resend bit here? | |
6174 | */ | |
6175 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6176 | default_credits); | |
6177 | ||
6178 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6179 | credits | PFI_CREDIT_RESEND); | |
6180 | ||
6181 | /* | |
6182 | * FIXME is this guaranteed to clear | |
6183 | * immediately or should we poll for it? | |
6184 | */ | |
6185 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6186 | } | |
6187 | ||
27c329ed | 6188 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 6189 | { |
a821fc46 | 6190 | struct drm_device *dev = old_state->dev; |
30a970c6 | 6191 | struct drm_i915_private *dev_priv = dev->dev_private; |
1a617b77 ML |
6192 | struct intel_atomic_state *old_intel_state = |
6193 | to_intel_atomic_state(old_state); | |
6194 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
30a970c6 | 6195 | |
27c329ed ML |
6196 | /* |
6197 | * FIXME: We can end up here with all power domains off, yet | |
6198 | * with a CDCLK frequency other than the minimum. To account | |
6199 | * for this take the PIPE-A power domain, which covers the HW | |
6200 | * blocks needed for the following programming. This can be | |
6201 | * removed once it's guaranteed that we get here either with | |
6202 | * the minimum CDCLK set, or the required power domains | |
6203 | * enabled. | |
6204 | */ | |
6205 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6206 | |
27c329ed ML |
6207 | if (IS_CHERRYVIEW(dev)) |
6208 | cherryview_set_cdclk(dev, req_cdclk); | |
6209 | else | |
6210 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6211 | |
27c329ed | 6212 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6213 | |
27c329ed | 6214 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6215 | } |
6216 | ||
89b667f8 JB |
6217 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
6218 | { | |
6219 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6220 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
6221 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6222 | struct intel_encoder *encoder; | |
6223 | int pipe = intel_crtc->pipe; | |
89b667f8 | 6224 | |
53d9f4e9 | 6225 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6226 | return; |
6227 | ||
6e3c9717 | 6228 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6229 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6230 | |
6231 | intel_set_pipe_timings(intel_crtc); | |
6232 | ||
c14b0485 VS |
6233 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
6234 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6235 | ||
6236 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6237 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6238 | } | |
6239 | ||
5b18e57c DV |
6240 | i9xx_set_pipeconf(intel_crtc); |
6241 | ||
89b667f8 | 6242 | intel_crtc->active = true; |
89b667f8 | 6243 | |
a72e4c9f | 6244 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6245 | |
89b667f8 JB |
6246 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6247 | if (encoder->pre_pll_enable) | |
6248 | encoder->pre_pll_enable(encoder); | |
6249 | ||
a65347ba | 6250 | if (!intel_crtc->config->has_dsi_encoder) { |
c0b4c660 VS |
6251 | if (IS_CHERRYVIEW(dev)) { |
6252 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6253 | chv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 VS |
6254 | } else { |
6255 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6256 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 | 6257 | } |
9d556c99 | 6258 | } |
89b667f8 JB |
6259 | |
6260 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6261 | if (encoder->pre_enable) | |
6262 | encoder->pre_enable(encoder); | |
6263 | ||
2dd24552 JB |
6264 | i9xx_pfit_enable(intel_crtc); |
6265 | ||
63cbb074 VS |
6266 | intel_crtc_load_lut(crtc); |
6267 | ||
e1fdc473 | 6268 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6269 | |
4b3a9526 VS |
6270 | assert_vblank_disabled(crtc); |
6271 | drm_crtc_vblank_on(crtc); | |
6272 | ||
f9b61ff6 DV |
6273 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6274 | encoder->enable(encoder); | |
89b667f8 JB |
6275 | } |
6276 | ||
f13c2ef3 DV |
6277 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6278 | { | |
6279 | struct drm_device *dev = crtc->base.dev; | |
6280 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6281 | ||
6e3c9717 ACO |
6282 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6283 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6284 | } |
6285 | ||
0b8765c6 | 6286 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
6287 | { |
6288 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6289 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6290 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6291 | struct intel_encoder *encoder; |
79e53945 | 6292 | int pipe = intel_crtc->pipe; |
79e53945 | 6293 | |
53d9f4e9 | 6294 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6295 | return; |
6296 | ||
f13c2ef3 DV |
6297 | i9xx_set_pll_dividers(intel_crtc); |
6298 | ||
6e3c9717 | 6299 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6300 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6301 | |
6302 | intel_set_pipe_timings(intel_crtc); | |
6303 | ||
5b18e57c DV |
6304 | i9xx_set_pipeconf(intel_crtc); |
6305 | ||
f7abfe8b | 6306 | intel_crtc->active = true; |
6b383a7f | 6307 | |
4a3436e8 | 6308 | if (!IS_GEN2(dev)) |
a72e4c9f | 6309 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6310 | |
9d6d9f19 MK |
6311 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6312 | if (encoder->pre_enable) | |
6313 | encoder->pre_enable(encoder); | |
6314 | ||
f6736a1a DV |
6315 | i9xx_enable_pll(intel_crtc); |
6316 | ||
2dd24552 JB |
6317 | i9xx_pfit_enable(intel_crtc); |
6318 | ||
63cbb074 VS |
6319 | intel_crtc_load_lut(crtc); |
6320 | ||
f37fcc2a | 6321 | intel_update_watermarks(crtc); |
e1fdc473 | 6322 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6323 | |
4b3a9526 VS |
6324 | assert_vblank_disabled(crtc); |
6325 | drm_crtc_vblank_on(crtc); | |
6326 | ||
f9b61ff6 DV |
6327 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6328 | encoder->enable(encoder); | |
d029bcad PZ |
6329 | |
6330 | intel_fbc_enable(intel_crtc); | |
0b8765c6 | 6331 | } |
79e53945 | 6332 | |
87476d63 DV |
6333 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6334 | { | |
6335 | struct drm_device *dev = crtc->base.dev; | |
6336 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 6337 | |
6e3c9717 | 6338 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6339 | return; |
87476d63 | 6340 | |
328d8e82 | 6341 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6342 | |
328d8e82 DV |
6343 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6344 | I915_READ(PFIT_CONTROL)); | |
6345 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6346 | } |
6347 | ||
0b8765c6 JB |
6348 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6349 | { | |
6350 | struct drm_device *dev = crtc->dev; | |
6351 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6352 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 6353 | struct intel_encoder *encoder; |
0b8765c6 | 6354 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6355 | |
6304cd91 VS |
6356 | /* |
6357 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6358 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
6359 | * We also need to wait on all gmch platforms because of the |
6360 | * self-refresh mode constraint explained above. | |
6304cd91 | 6361 | */ |
564ed191 | 6362 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 6363 | |
4b3a9526 VS |
6364 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6365 | encoder->disable(encoder); | |
6366 | ||
f9b61ff6 DV |
6367 | drm_crtc_vblank_off(crtc); |
6368 | assert_vblank_disabled(crtc); | |
6369 | ||
575f7ab7 | 6370 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6371 | |
87476d63 | 6372 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6373 | |
89b667f8 JB |
6374 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6375 | if (encoder->post_disable) | |
6376 | encoder->post_disable(encoder); | |
6377 | ||
a65347ba | 6378 | if (!intel_crtc->config->has_dsi_encoder) { |
076ed3b2 CML |
6379 | if (IS_CHERRYVIEW(dev)) |
6380 | chv_disable_pll(dev_priv, pipe); | |
6381 | else if (IS_VALLEYVIEW(dev)) | |
6382 | vlv_disable_pll(dev_priv, pipe); | |
6383 | else | |
1c4e0274 | 6384 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6385 | } |
0b8765c6 | 6386 | |
d6db995f VS |
6387 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6388 | if (encoder->post_pll_disable) | |
6389 | encoder->post_pll_disable(encoder); | |
6390 | ||
4a3436e8 | 6391 | if (!IS_GEN2(dev)) |
a72e4c9f | 6392 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
d029bcad PZ |
6393 | |
6394 | intel_fbc_disable_crtc(intel_crtc); | |
0b8765c6 JB |
6395 | } |
6396 | ||
b17d48e2 ML |
6397 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6398 | { | |
6399 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6400 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6401 | enum intel_display_power_domain domain; | |
6402 | unsigned long domains; | |
6403 | ||
6404 | if (!intel_crtc->active) | |
6405 | return; | |
6406 | ||
a539205a | 6407 | if (to_intel_plane_state(crtc->primary->state)->visible) { |
fc32b1fd ML |
6408 | WARN_ON(intel_crtc->unpin_work); |
6409 | ||
a539205a | 6410 | intel_pre_disable_primary(crtc); |
54a41961 ML |
6411 | |
6412 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); | |
6413 | to_intel_plane_state(crtc->primary->state)->visible = false; | |
a539205a ML |
6414 | } |
6415 | ||
b17d48e2 | 6416 | dev_priv->display.crtc_disable(crtc); |
37d9078b MR |
6417 | intel_crtc->active = false; |
6418 | intel_update_watermarks(crtc); | |
1f7457b1 | 6419 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6420 | |
6421 | domains = intel_crtc->enabled_power_domains; | |
6422 | for_each_power_domain(domain, domains) | |
6423 | intel_display_power_put(dev_priv, domain); | |
6424 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
6425 | |
6426 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
6427 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
6428 | } |
6429 | ||
6b72d486 ML |
6430 | /* |
6431 | * turn all crtc's off, but do not adjust state | |
6432 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6433 | */ | |
70e0bd74 | 6434 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6435 | { |
70e0bd74 ML |
6436 | struct drm_mode_config *config = &dev->mode_config; |
6437 | struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx; | |
6438 | struct drm_atomic_state *state; | |
6b72d486 | 6439 | struct drm_crtc *crtc; |
70e0bd74 ML |
6440 | unsigned crtc_mask = 0; |
6441 | int ret = 0; | |
6442 | ||
6443 | if (WARN_ON(!ctx)) | |
6444 | return 0; | |
6445 | ||
6446 | lockdep_assert_held(&ctx->ww_ctx); | |
6447 | state = drm_atomic_state_alloc(dev); | |
6448 | if (WARN_ON(!state)) | |
6449 | return -ENOMEM; | |
6450 | ||
6451 | state->acquire_ctx = ctx; | |
6452 | state->allow_modeset = true; | |
6453 | ||
6454 | for_each_crtc(dev, crtc) { | |
6455 | struct drm_crtc_state *crtc_state = | |
6456 | drm_atomic_get_crtc_state(state, crtc); | |
6b72d486 | 6457 | |
70e0bd74 ML |
6458 | ret = PTR_ERR_OR_ZERO(crtc_state); |
6459 | if (ret) | |
6460 | goto free; | |
6461 | ||
6462 | if (!crtc_state->active) | |
6463 | continue; | |
6464 | ||
6465 | crtc_state->active = false; | |
6466 | crtc_mask |= 1 << drm_crtc_index(crtc); | |
6467 | } | |
6468 | ||
6469 | if (crtc_mask) { | |
74c090b1 | 6470 | ret = drm_atomic_commit(state); |
70e0bd74 ML |
6471 | |
6472 | if (!ret) { | |
6473 | for_each_crtc(dev, crtc) | |
6474 | if (crtc_mask & (1 << drm_crtc_index(crtc))) | |
6475 | crtc->state->active = true; | |
6476 | ||
6477 | return ret; | |
6478 | } | |
6479 | } | |
6480 | ||
6481 | free: | |
6482 | if (ret) | |
6483 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
6484 | drm_atomic_state_free(state); | |
6485 | return ret; | |
ee7b9f93 JB |
6486 | } |
6487 | ||
ea5b213a | 6488 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6489 | { |
4ef69c7a | 6490 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6491 | |
ea5b213a CW |
6492 | drm_encoder_cleanup(encoder); |
6493 | kfree(intel_encoder); | |
7e7d76c3 JB |
6494 | } |
6495 | ||
0a91ca29 DV |
6496 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6497 | * internal consistency). */ | |
b980514c | 6498 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 6499 | { |
35dd3c64 ML |
6500 | struct drm_crtc *crtc = connector->base.state->crtc; |
6501 | ||
6502 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6503 | connector->base.base.id, | |
6504 | connector->base.name); | |
6505 | ||
0a91ca29 | 6506 | if (connector->get_hw_state(connector)) { |
e85376cb | 6507 | struct intel_encoder *encoder = connector->encoder; |
35dd3c64 | 6508 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 6509 | |
35dd3c64 ML |
6510 | I915_STATE_WARN(!crtc, |
6511 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6512 | |
35dd3c64 ML |
6513 | if (!crtc) |
6514 | return; | |
6515 | ||
6516 | I915_STATE_WARN(!crtc->state->active, | |
6517 | "connector is active, but attached crtc isn't\n"); | |
6518 | ||
e85376cb | 6519 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6520 | return; |
6521 | ||
e85376cb | 6522 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6523 | "atomic encoder doesn't match attached encoder\n"); |
6524 | ||
e85376cb | 6525 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6526 | "attached encoder crtc differs from connector crtc\n"); |
6527 | } else { | |
4d688a2a ML |
6528 | I915_STATE_WARN(crtc && crtc->state->active, |
6529 | "attached crtc is active, but connector isn't\n"); | |
35dd3c64 ML |
6530 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
6531 | "best encoder set without crtc!\n"); | |
0a91ca29 | 6532 | } |
79e53945 JB |
6533 | } |
6534 | ||
08d9bc92 ACO |
6535 | int intel_connector_init(struct intel_connector *connector) |
6536 | { | |
6537 | struct drm_connector_state *connector_state; | |
6538 | ||
6539 | connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL); | |
6540 | if (!connector_state) | |
6541 | return -ENOMEM; | |
6542 | ||
6543 | connector->base.state = connector_state; | |
6544 | return 0; | |
6545 | } | |
6546 | ||
6547 | struct intel_connector *intel_connector_alloc(void) | |
6548 | { | |
6549 | struct intel_connector *connector; | |
6550 | ||
6551 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6552 | if (!connector) | |
6553 | return NULL; | |
6554 | ||
6555 | if (intel_connector_init(connector) < 0) { | |
6556 | kfree(connector); | |
6557 | return NULL; | |
6558 | } | |
6559 | ||
6560 | return connector; | |
6561 | } | |
6562 | ||
f0947c37 DV |
6563 | /* Simple connector->get_hw_state implementation for encoders that support only |
6564 | * one connector and no cloning and hence the encoder state determines the state | |
6565 | * of the connector. */ | |
6566 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6567 | { |
24929352 | 6568 | enum pipe pipe = 0; |
f0947c37 | 6569 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6570 | |
f0947c37 | 6571 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6572 | } |
6573 | ||
6d293983 | 6574 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6575 | { |
6d293983 ACO |
6576 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6577 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6578 | |
6579 | return 0; | |
6580 | } | |
6581 | ||
6d293983 | 6582 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6583 | struct intel_crtc_state *pipe_config) |
1857e1da | 6584 | { |
6d293983 ACO |
6585 | struct drm_atomic_state *state = pipe_config->base.state; |
6586 | struct intel_crtc *other_crtc; | |
6587 | struct intel_crtc_state *other_crtc_state; | |
6588 | ||
1857e1da DV |
6589 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6590 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6591 | if (pipe_config->fdi_lanes > 4) { | |
6592 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6593 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6594 | return -EINVAL; |
1857e1da DV |
6595 | } |
6596 | ||
bafb6553 | 6597 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6598 | if (pipe_config->fdi_lanes > 2) { |
6599 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6600 | pipe_config->fdi_lanes); | |
6d293983 | 6601 | return -EINVAL; |
1857e1da | 6602 | } else { |
6d293983 | 6603 | return 0; |
1857e1da DV |
6604 | } |
6605 | } | |
6606 | ||
6607 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6608 | return 0; |
1857e1da DV |
6609 | |
6610 | /* Ivybridge 3 pipe is really complicated */ | |
6611 | switch (pipe) { | |
6612 | case PIPE_A: | |
6d293983 | 6613 | return 0; |
1857e1da | 6614 | case PIPE_B: |
6d293983 ACO |
6615 | if (pipe_config->fdi_lanes <= 2) |
6616 | return 0; | |
6617 | ||
6618 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6619 | other_crtc_state = | |
6620 | intel_atomic_get_crtc_state(state, other_crtc); | |
6621 | if (IS_ERR(other_crtc_state)) | |
6622 | return PTR_ERR(other_crtc_state); | |
6623 | ||
6624 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6625 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6626 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6627 | return -EINVAL; |
1857e1da | 6628 | } |
6d293983 | 6629 | return 0; |
1857e1da | 6630 | case PIPE_C: |
251cc67c VS |
6631 | if (pipe_config->fdi_lanes > 2) { |
6632 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6633 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6634 | return -EINVAL; |
251cc67c | 6635 | } |
6d293983 ACO |
6636 | |
6637 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6638 | other_crtc_state = | |
6639 | intel_atomic_get_crtc_state(state, other_crtc); | |
6640 | if (IS_ERR(other_crtc_state)) | |
6641 | return PTR_ERR(other_crtc_state); | |
6642 | ||
6643 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6644 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6645 | return -EINVAL; |
1857e1da | 6646 | } |
6d293983 | 6647 | return 0; |
1857e1da DV |
6648 | default: |
6649 | BUG(); | |
6650 | } | |
6651 | } | |
6652 | ||
e29c22c0 DV |
6653 | #define RETRY 1 |
6654 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6655 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6656 | { |
1857e1da | 6657 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6658 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6659 | int lane, link_bw, fdi_dotclock, ret; |
6660 | bool needs_recompute = false; | |
877d48d5 | 6661 | |
e29c22c0 | 6662 | retry: |
877d48d5 DV |
6663 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6664 | * each output octet as 10 bits. The actual frequency | |
6665 | * is stored as a divider into a 100MHz clock, and the | |
6666 | * mode pixel clock is stored in units of 1KHz. | |
6667 | * Hence the bw of each lane in terms of the mode signal | |
6668 | * is: | |
6669 | */ | |
6670 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
6671 | ||
241bfc38 | 6672 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6673 | |
2bd89a07 | 6674 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6675 | pipe_config->pipe_bpp); |
6676 | ||
6677 | pipe_config->fdi_lanes = lane; | |
6678 | ||
2bd89a07 | 6679 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6680 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6681 | |
6d293983 ACO |
6682 | ret = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
6683 | intel_crtc->pipe, pipe_config); | |
6684 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { | |
e29c22c0 DV |
6685 | pipe_config->pipe_bpp -= 2*3; |
6686 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6687 | pipe_config->pipe_bpp); | |
6688 | needs_recompute = true; | |
6689 | pipe_config->bw_constrained = true; | |
6690 | ||
6691 | goto retry; | |
6692 | } | |
6693 | ||
6694 | if (needs_recompute) | |
6695 | return RETRY; | |
6696 | ||
6d293983 | 6697 | return ret; |
877d48d5 DV |
6698 | } |
6699 | ||
8cfb3407 VS |
6700 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6701 | struct intel_crtc_state *pipe_config) | |
6702 | { | |
6703 | if (pipe_config->pipe_bpp > 24) | |
6704 | return false; | |
6705 | ||
6706 | /* HSW can handle pixel rate up to cdclk? */ | |
6707 | if (IS_HASWELL(dev_priv->dev)) | |
6708 | return true; | |
6709 | ||
6710 | /* | |
b432e5cf VS |
6711 | * We compare against max which means we must take |
6712 | * the increased cdclk requirement into account when | |
6713 | * calculating the new cdclk. | |
6714 | * | |
6715 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
6716 | */ |
6717 | return ilk_pipe_pixel_rate(pipe_config) <= | |
6718 | dev_priv->max_cdclk_freq * 95 / 100; | |
6719 | } | |
6720 | ||
42db64ef | 6721 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6722 | struct intel_crtc_state *pipe_config) |
42db64ef | 6723 | { |
8cfb3407 VS |
6724 | struct drm_device *dev = crtc->base.dev; |
6725 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6726 | ||
d330a953 | 6727 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
6728 | hsw_crtc_supports_ips(crtc) && |
6729 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
6730 | } |
6731 | ||
39acb4aa VS |
6732 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
6733 | { | |
6734 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
6735 | ||
6736 | /* GDG double wide on either pipe, otherwise pipe A only */ | |
6737 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6738 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
6739 | } | |
6740 | ||
a43f6e0f | 6741 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6742 | struct intel_crtc_state *pipe_config) |
79e53945 | 6743 | { |
a43f6e0f | 6744 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 6745 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c5f93b0 | 6746 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
89749350 | 6747 | |
ad3a4479 | 6748 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 6749 | if (INTEL_INFO(dev)->gen < 4) { |
39acb4aa | 6750 | int clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
cf532bb2 VS |
6751 | |
6752 | /* | |
39acb4aa | 6753 | * Enable double wide mode when the dot clock |
cf532bb2 | 6754 | * is > 90% of the (display) core speed. |
cf532bb2 | 6755 | */ |
39acb4aa VS |
6756 | if (intel_crtc_supports_double_wide(crtc) && |
6757 | adjusted_mode->crtc_clock > clock_limit) { | |
ad3a4479 | 6758 | clock_limit *= 2; |
cf532bb2 | 6759 | pipe_config->double_wide = true; |
ad3a4479 VS |
6760 | } |
6761 | ||
39acb4aa VS |
6762 | if (adjusted_mode->crtc_clock > clock_limit) { |
6763 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6764 | adjusted_mode->crtc_clock, clock_limit, | |
6765 | yesno(pipe_config->double_wide)); | |
e29c22c0 | 6766 | return -EINVAL; |
39acb4aa | 6767 | } |
2c07245f | 6768 | } |
89749350 | 6769 | |
1d1d0e27 VS |
6770 | /* |
6771 | * Pipe horizontal size must be even in: | |
6772 | * - DVO ganged mode | |
6773 | * - LVDS dual channel mode | |
6774 | * - Double wide pipe | |
6775 | */ | |
a93e255f | 6776 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6777 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6778 | pipe_config->pipe_src_w &= ~1; | |
6779 | ||
8693a824 DL |
6780 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6781 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6782 | */ |
6783 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
aad941d5 | 6784 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
e29c22c0 | 6785 | return -EINVAL; |
44f46b42 | 6786 | |
f5adf94e | 6787 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6788 | hsw_compute_ips_config(crtc, pipe_config); |
6789 | ||
877d48d5 | 6790 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6791 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6792 | |
cf5a15be | 6793 | return 0; |
79e53945 JB |
6794 | } |
6795 | ||
1652d19e VS |
6796 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6797 | { | |
6798 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6799 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
6800 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6801 | uint32_t linkrate; | |
6802 | ||
414355a7 | 6803 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) |
1652d19e | 6804 | return 24000; /* 24MHz is the cd freq with NSSC ref */ |
1652d19e VS |
6805 | |
6806 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
6807 | return 540000; | |
6808 | ||
6809 | linkrate = (I915_READ(DPLL_CTRL1) & | |
71cd8423 | 6810 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; |
1652d19e | 6811 | |
71cd8423 DL |
6812 | if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || |
6813 | linkrate == DPLL_CTRL1_LINK_RATE_1080) { | |
1652d19e VS |
6814 | /* vco 8640 */ |
6815 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6816 | case CDCLK_FREQ_450_432: | |
6817 | return 432000; | |
6818 | case CDCLK_FREQ_337_308: | |
6819 | return 308570; | |
6820 | case CDCLK_FREQ_675_617: | |
6821 | return 617140; | |
6822 | default: | |
6823 | WARN(1, "Unknown cd freq selection\n"); | |
6824 | } | |
6825 | } else { | |
6826 | /* vco 8100 */ | |
6827 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6828 | case CDCLK_FREQ_450_432: | |
6829 | return 450000; | |
6830 | case CDCLK_FREQ_337_308: | |
6831 | return 337500; | |
6832 | case CDCLK_FREQ_675_617: | |
6833 | return 675000; | |
6834 | default: | |
6835 | WARN(1, "Unknown cd freq selection\n"); | |
6836 | } | |
6837 | } | |
6838 | ||
6839 | /* error case, do as if DPLL0 isn't enabled */ | |
6840 | return 24000; | |
6841 | } | |
6842 | ||
acd3f3d3 BP |
6843 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
6844 | { | |
6845 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6846 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6847 | uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; | |
6848 | uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE); | |
6849 | int cdclk; | |
6850 | ||
6851 | if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE)) | |
6852 | return 19200; | |
6853 | ||
6854 | cdclk = 19200 * pll_ratio / 2; | |
6855 | ||
6856 | switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) { | |
6857 | case BXT_CDCLK_CD2X_DIV_SEL_1: | |
6858 | return cdclk; /* 576MHz or 624MHz */ | |
6859 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: | |
6860 | return cdclk * 2 / 3; /* 384MHz */ | |
6861 | case BXT_CDCLK_CD2X_DIV_SEL_2: | |
6862 | return cdclk / 2; /* 288MHz */ | |
6863 | case BXT_CDCLK_CD2X_DIV_SEL_4: | |
6864 | return cdclk / 4; /* 144MHz */ | |
6865 | } | |
6866 | ||
6867 | /* error case, do as if DE PLL isn't enabled */ | |
6868 | return 19200; | |
6869 | } | |
6870 | ||
1652d19e VS |
6871 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
6872 | { | |
6873 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6874 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6875 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6876 | ||
6877 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6878 | return 800000; | |
6879 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6880 | return 450000; | |
6881 | else if (freq == LCPLL_CLK_FREQ_450) | |
6882 | return 450000; | |
6883 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6884 | return 540000; | |
6885 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6886 | return 337500; | |
6887 | else | |
6888 | return 675000; | |
6889 | } | |
6890 | ||
6891 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6892 | { | |
6893 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6894 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6895 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6896 | ||
6897 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6898 | return 800000; | |
6899 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6900 | return 450000; | |
6901 | else if (freq == LCPLL_CLK_FREQ_450) | |
6902 | return 450000; | |
6903 | else if (IS_HSW_ULT(dev)) | |
6904 | return 337500; | |
6905 | else | |
6906 | return 540000; | |
79e53945 JB |
6907 | } |
6908 | ||
25eb05fc JB |
6909 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6910 | { | |
bfa7df01 VS |
6911 | return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", |
6912 | CCK_DISPLAY_CLOCK_CONTROL); | |
25eb05fc JB |
6913 | } |
6914 | ||
b37a6434 VS |
6915 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6916 | { | |
6917 | return 450000; | |
6918 | } | |
6919 | ||
e70236a8 JB |
6920 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6921 | { | |
6922 | return 400000; | |
6923 | } | |
79e53945 | 6924 | |
e70236a8 | 6925 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6926 | { |
e907f170 | 6927 | return 333333; |
e70236a8 | 6928 | } |
79e53945 | 6929 | |
e70236a8 JB |
6930 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6931 | { | |
6932 | return 200000; | |
6933 | } | |
79e53945 | 6934 | |
257a7ffc DV |
6935 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6936 | { | |
6937 | u16 gcfgc = 0; | |
6938 | ||
6939 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6940 | ||
6941 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6942 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6943 | return 266667; |
257a7ffc | 6944 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6945 | return 333333; |
257a7ffc | 6946 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6947 | return 444444; |
257a7ffc DV |
6948 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6949 | return 200000; | |
6950 | default: | |
6951 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6952 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6953 | return 133333; |
257a7ffc | 6954 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6955 | return 166667; |
257a7ffc DV |
6956 | } |
6957 | } | |
6958 | ||
e70236a8 JB |
6959 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6960 | { | |
6961 | u16 gcfgc = 0; | |
79e53945 | 6962 | |
e70236a8 JB |
6963 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6964 | ||
6965 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6966 | return 133333; |
e70236a8 JB |
6967 | else { |
6968 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6969 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6970 | return 333333; |
e70236a8 JB |
6971 | default: |
6972 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6973 | return 190000; | |
79e53945 | 6974 | } |
e70236a8 JB |
6975 | } |
6976 | } | |
6977 | ||
6978 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6979 | { | |
e907f170 | 6980 | return 266667; |
e70236a8 JB |
6981 | } |
6982 | ||
1b1d2716 | 6983 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 JB |
6984 | { |
6985 | u16 hpllcc = 0; | |
1b1d2716 | 6986 | |
65cd2b3f VS |
6987 | /* |
6988 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
6989 | * encoding is different :( | |
6990 | * FIXME is this the right way to detect 852GM/852GMV? | |
6991 | */ | |
6992 | if (dev->pdev->revision == 0x1) | |
6993 | return 133333; | |
6994 | ||
1b1d2716 VS |
6995 | pci_bus_read_config_word(dev->pdev->bus, |
6996 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
6997 | ||
e70236a8 JB |
6998 | /* Assume that the hardware is in the high speed state. This |
6999 | * should be the default. | |
7000 | */ | |
7001 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
7002 | case GC_CLOCK_133_200: | |
1b1d2716 | 7003 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
7004 | case GC_CLOCK_100_200: |
7005 | return 200000; | |
7006 | case GC_CLOCK_166_250: | |
7007 | return 250000; | |
7008 | case GC_CLOCK_100_133: | |
e907f170 | 7009 | return 133333; |
1b1d2716 VS |
7010 | case GC_CLOCK_133_266: |
7011 | case GC_CLOCK_133_266_2: | |
7012 | case GC_CLOCK_166_266: | |
7013 | return 266667; | |
e70236a8 | 7014 | } |
79e53945 | 7015 | |
e70236a8 JB |
7016 | /* Shouldn't happen */ |
7017 | return 0; | |
7018 | } | |
79e53945 | 7019 | |
e70236a8 JB |
7020 | static int i830_get_display_clock_speed(struct drm_device *dev) |
7021 | { | |
e907f170 | 7022 | return 133333; |
79e53945 JB |
7023 | } |
7024 | ||
34edce2f VS |
7025 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
7026 | { | |
7027 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7028 | static const unsigned int blb_vco[8] = { | |
7029 | [0] = 3200000, | |
7030 | [1] = 4000000, | |
7031 | [2] = 5333333, | |
7032 | [3] = 4800000, | |
7033 | [4] = 6400000, | |
7034 | }; | |
7035 | static const unsigned int pnv_vco[8] = { | |
7036 | [0] = 3200000, | |
7037 | [1] = 4000000, | |
7038 | [2] = 5333333, | |
7039 | [3] = 4800000, | |
7040 | [4] = 2666667, | |
7041 | }; | |
7042 | static const unsigned int cl_vco[8] = { | |
7043 | [0] = 3200000, | |
7044 | [1] = 4000000, | |
7045 | [2] = 5333333, | |
7046 | [3] = 6400000, | |
7047 | [4] = 3333333, | |
7048 | [5] = 3566667, | |
7049 | [6] = 4266667, | |
7050 | }; | |
7051 | static const unsigned int elk_vco[8] = { | |
7052 | [0] = 3200000, | |
7053 | [1] = 4000000, | |
7054 | [2] = 5333333, | |
7055 | [3] = 4800000, | |
7056 | }; | |
7057 | static const unsigned int ctg_vco[8] = { | |
7058 | [0] = 3200000, | |
7059 | [1] = 4000000, | |
7060 | [2] = 5333333, | |
7061 | [3] = 6400000, | |
7062 | [4] = 2666667, | |
7063 | [5] = 4266667, | |
7064 | }; | |
7065 | const unsigned int *vco_table; | |
7066 | unsigned int vco; | |
7067 | uint8_t tmp = 0; | |
7068 | ||
7069 | /* FIXME other chipsets? */ | |
7070 | if (IS_GM45(dev)) | |
7071 | vco_table = ctg_vco; | |
7072 | else if (IS_G4X(dev)) | |
7073 | vco_table = elk_vco; | |
7074 | else if (IS_CRESTLINE(dev)) | |
7075 | vco_table = cl_vco; | |
7076 | else if (IS_PINEVIEW(dev)) | |
7077 | vco_table = pnv_vco; | |
7078 | else if (IS_G33(dev)) | |
7079 | vco_table = blb_vco; | |
7080 | else | |
7081 | return 0; | |
7082 | ||
7083 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
7084 | ||
7085 | vco = vco_table[tmp & 0x7]; | |
7086 | if (vco == 0) | |
7087 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
7088 | else | |
7089 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
7090 | ||
7091 | return vco; | |
7092 | } | |
7093 | ||
7094 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
7095 | { | |
7096 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7097 | uint16_t tmp = 0; | |
7098 | ||
7099 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7100 | ||
7101 | cdclk_sel = (tmp >> 12) & 0x1; | |
7102 | ||
7103 | switch (vco) { | |
7104 | case 2666667: | |
7105 | case 4000000: | |
7106 | case 5333333: | |
7107 | return cdclk_sel ? 333333 : 222222; | |
7108 | case 3200000: | |
7109 | return cdclk_sel ? 320000 : 228571; | |
7110 | default: | |
7111 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
7112 | return 222222; | |
7113 | } | |
7114 | } | |
7115 | ||
7116 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
7117 | { | |
7118 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
7119 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
7120 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
7121 | const uint8_t *div_table; | |
7122 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7123 | uint16_t tmp = 0; | |
7124 | ||
7125 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7126 | ||
7127 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
7128 | ||
7129 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7130 | goto fail; | |
7131 | ||
7132 | switch (vco) { | |
7133 | case 3200000: | |
7134 | div_table = div_3200; | |
7135 | break; | |
7136 | case 4000000: | |
7137 | div_table = div_4000; | |
7138 | break; | |
7139 | case 5333333: | |
7140 | div_table = div_5333; | |
7141 | break; | |
7142 | default: | |
7143 | goto fail; | |
7144 | } | |
7145 | ||
7146 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7147 | ||
caf4e252 | 7148 | fail: |
34edce2f VS |
7149 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
7150 | return 200000; | |
7151 | } | |
7152 | ||
7153 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
7154 | { | |
7155 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
7156 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
7157 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
7158 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
7159 | const uint8_t *div_table; | |
7160 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7161 | uint16_t tmp = 0; | |
7162 | ||
7163 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7164 | ||
7165 | cdclk_sel = (tmp >> 4) & 0x7; | |
7166 | ||
7167 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7168 | goto fail; | |
7169 | ||
7170 | switch (vco) { | |
7171 | case 3200000: | |
7172 | div_table = div_3200; | |
7173 | break; | |
7174 | case 4000000: | |
7175 | div_table = div_4000; | |
7176 | break; | |
7177 | case 4800000: | |
7178 | div_table = div_4800; | |
7179 | break; | |
7180 | case 5333333: | |
7181 | div_table = div_5333; | |
7182 | break; | |
7183 | default: | |
7184 | goto fail; | |
7185 | } | |
7186 | ||
7187 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7188 | ||
caf4e252 | 7189 | fail: |
34edce2f VS |
7190 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
7191 | return 190476; | |
7192 | } | |
7193 | ||
2c07245f | 7194 | static void |
a65851af | 7195 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 7196 | { |
a65851af VS |
7197 | while (*num > DATA_LINK_M_N_MASK || |
7198 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
7199 | *num >>= 1; |
7200 | *den >>= 1; | |
7201 | } | |
7202 | } | |
7203 | ||
a65851af VS |
7204 | static void compute_m_n(unsigned int m, unsigned int n, |
7205 | uint32_t *ret_m, uint32_t *ret_n) | |
7206 | { | |
7207 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7208 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7209 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7210 | } | |
7211 | ||
e69d0bc1 DV |
7212 | void |
7213 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7214 | int pixel_clock, int link_clock, | |
7215 | struct intel_link_m_n *m_n) | |
2c07245f | 7216 | { |
e69d0bc1 | 7217 | m_n->tu = 64; |
a65851af VS |
7218 | |
7219 | compute_m_n(bits_per_pixel * pixel_clock, | |
7220 | link_clock * nlanes * 8, | |
7221 | &m_n->gmch_m, &m_n->gmch_n); | |
7222 | ||
7223 | compute_m_n(pixel_clock, link_clock, | |
7224 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7225 | } |
7226 | ||
a7615030 CW |
7227 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7228 | { | |
d330a953 JN |
7229 | if (i915.panel_use_ssc >= 0) |
7230 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7231 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7232 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7233 | } |
7234 | ||
a93e255f ACO |
7235 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
7236 | int num_connectors) | |
c65d77d8 | 7237 | { |
a93e255f | 7238 | struct drm_device *dev = crtc_state->base.crtc->dev; |
c65d77d8 JB |
7239 | struct drm_i915_private *dev_priv = dev->dev_private; |
7240 | int refclk; | |
7241 | ||
a93e255f ACO |
7242 | WARN_ON(!crtc_state->base.state); |
7243 | ||
666a4537 | 7244 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) { |
9a0ea498 | 7245 | refclk = 100000; |
a93e255f | 7246 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 7247 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
7248 | refclk = dev_priv->vbt.lvds_ssc_freq; |
7249 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
7250 | } else if (!IS_GEN2(dev)) { |
7251 | refclk = 96000; | |
7252 | } else { | |
7253 | refclk = 48000; | |
7254 | } | |
7255 | ||
7256 | return refclk; | |
7257 | } | |
7258 | ||
7429e9d4 | 7259 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7260 | { |
7df00d7a | 7261 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7262 | } |
f47709a9 | 7263 | |
7429e9d4 DV |
7264 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7265 | { | |
7266 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7267 | } |
7268 | ||
f47709a9 | 7269 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7270 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
7271 | intel_clock_t *reduced_clock) |
7272 | { | |
f47709a9 | 7273 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
7274 | u32 fp, fp2 = 0; |
7275 | ||
7276 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 7277 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7278 | if (reduced_clock) |
7429e9d4 | 7279 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7280 | } else { |
190f68c5 | 7281 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7282 | if (reduced_clock) |
7429e9d4 | 7283 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7284 | } |
7285 | ||
190f68c5 | 7286 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7287 | |
f47709a9 | 7288 | crtc->lowfreq_avail = false; |
a93e255f | 7289 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7290 | reduced_clock) { |
190f68c5 | 7291 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7292 | crtc->lowfreq_avail = true; |
a7516a05 | 7293 | } else { |
190f68c5 | 7294 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7295 | } |
7296 | } | |
7297 | ||
5e69f97f CML |
7298 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7299 | pipe) | |
89b667f8 JB |
7300 | { |
7301 | u32 reg_val; | |
7302 | ||
7303 | /* | |
7304 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7305 | * and set it to a reasonable value instead. | |
7306 | */ | |
ab3c759a | 7307 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7308 | reg_val &= 0xffffff00; |
7309 | reg_val |= 0x00000030; | |
ab3c759a | 7310 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7311 | |
ab3c759a | 7312 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7313 | reg_val &= 0x8cffffff; |
7314 | reg_val = 0x8c000000; | |
ab3c759a | 7315 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7316 | |
ab3c759a | 7317 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7318 | reg_val &= 0xffffff00; |
ab3c759a | 7319 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7320 | |
ab3c759a | 7321 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7322 | reg_val &= 0x00ffffff; |
7323 | reg_val |= 0xb0000000; | |
ab3c759a | 7324 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7325 | } |
7326 | ||
b551842d DV |
7327 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7328 | struct intel_link_m_n *m_n) | |
7329 | { | |
7330 | struct drm_device *dev = crtc->base.dev; | |
7331 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7332 | int pipe = crtc->pipe; | |
7333 | ||
e3b95f1e DV |
7334 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7335 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7336 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7337 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7338 | } |
7339 | ||
7340 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7341 | struct intel_link_m_n *m_n, |
7342 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7343 | { |
7344 | struct drm_device *dev = crtc->base.dev; | |
7345 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7346 | int pipe = crtc->pipe; | |
6e3c9717 | 7347 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7348 | |
7349 | if (INTEL_INFO(dev)->gen >= 5) { | |
7350 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7351 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7352 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7353 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7354 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7355 | * for gen < 8) and if DRRS is supported (to make sure the | |
7356 | * registers are not unnecessarily accessed). | |
7357 | */ | |
44395bfe | 7358 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 7359 | crtc->config->has_drrs) { |
f769cd24 VK |
7360 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7361 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7362 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7363 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7364 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7365 | } | |
b551842d | 7366 | } else { |
e3b95f1e DV |
7367 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7368 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7369 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7370 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7371 | } |
7372 | } | |
7373 | ||
fe3cd48d | 7374 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7375 | { |
fe3cd48d R |
7376 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7377 | ||
7378 | if (m_n == M1_N1) { | |
7379 | dp_m_n = &crtc->config->dp_m_n; | |
7380 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7381 | } else if (m_n == M2_N2) { | |
7382 | ||
7383 | /* | |
7384 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7385 | * needs to be programmed into M1_N1. | |
7386 | */ | |
7387 | dp_m_n = &crtc->config->dp_m2_n2; | |
7388 | } else { | |
7389 | DRM_ERROR("Unsupported divider value\n"); | |
7390 | return; | |
7391 | } | |
7392 | ||
6e3c9717 ACO |
7393 | if (crtc->config->has_pch_encoder) |
7394 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7395 | else |
fe3cd48d | 7396 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7397 | } |
7398 | ||
251ac862 DV |
7399 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7400 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 DV |
7401 | { |
7402 | u32 dpll, dpll_md; | |
7403 | ||
7404 | /* | |
7405 | * Enable DPIO clock input. We should never disable the reference | |
7406 | * clock for pipe B, since VGA hotplug / manual detection depends | |
7407 | * on it. | |
7408 | */ | |
60bfe44f VS |
7409 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV | |
7410 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV; | |
bdd4b6a6 DV |
7411 | /* We should never disable this, set it here for state tracking */ |
7412 | if (crtc->pipe == PIPE_B) | |
7413 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7414 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 7415 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 7416 | |
d288f65f | 7417 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 7418 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 7419 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
7420 | } |
7421 | ||
d288f65f | 7422 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7423 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7424 | { |
f47709a9 | 7425 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 7426 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 7427 | int pipe = crtc->pipe; |
bdd4b6a6 | 7428 | u32 mdiv; |
a0c4da24 | 7429 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7430 | u32 coreclk, reg_val; |
a0c4da24 | 7431 | |
a580516d | 7432 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7433 | |
d288f65f VS |
7434 | bestn = pipe_config->dpll.n; |
7435 | bestm1 = pipe_config->dpll.m1; | |
7436 | bestm2 = pipe_config->dpll.m2; | |
7437 | bestp1 = pipe_config->dpll.p1; | |
7438 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7439 | |
89b667f8 JB |
7440 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7441 | ||
7442 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7443 | if (pipe == PIPE_B) |
5e69f97f | 7444 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7445 | |
7446 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7447 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7448 | |
7449 | /* Disable target IRef on PLL */ | |
ab3c759a | 7450 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7451 | reg_val &= 0x00ffffff; |
ab3c759a | 7452 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7453 | |
7454 | /* Disable fast lock */ | |
ab3c759a | 7455 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7456 | |
7457 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7458 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7459 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7460 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7461 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7462 | |
7463 | /* | |
7464 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7465 | * but we don't support that). | |
7466 | * Note: don't use the DAC post divider as it seems unstable. | |
7467 | */ | |
7468 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7469 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7470 | |
a0c4da24 | 7471 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7472 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7473 | |
89b667f8 | 7474 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7475 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
7476 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
7477 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7478 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7479 | 0x009f0003); |
89b667f8 | 7480 | else |
ab3c759a | 7481 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7482 | 0x00d0000f); |
7483 | ||
681a8504 | 7484 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 7485 | /* Use SSC source */ |
bdd4b6a6 | 7486 | if (pipe == PIPE_A) |
ab3c759a | 7487 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7488 | 0x0df40000); |
7489 | else | |
ab3c759a | 7490 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7491 | 0x0df70000); |
7492 | } else { /* HDMI or VGA */ | |
7493 | /* Use bend source */ | |
bdd4b6a6 | 7494 | if (pipe == PIPE_A) |
ab3c759a | 7495 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7496 | 0x0df70000); |
7497 | else | |
ab3c759a | 7498 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7499 | 0x0df40000); |
7500 | } | |
a0c4da24 | 7501 | |
ab3c759a | 7502 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7503 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
7504 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
7505 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 7506 | coreclk |= 0x01000000; |
ab3c759a | 7507 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7508 | |
ab3c759a | 7509 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7510 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7511 | } |
7512 | ||
251ac862 DV |
7513 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7514 | struct intel_crtc_state *pipe_config) | |
1ae0d137 | 7515 | { |
60bfe44f VS |
7516 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | |
7517 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | | |
1ae0d137 VS |
7518 | DPLL_VCO_ENABLE; |
7519 | if (crtc->pipe != PIPE_A) | |
d288f65f | 7520 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 7521 | |
d288f65f VS |
7522 | pipe_config->dpll_hw_state.dpll_md = |
7523 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
7524 | } |
7525 | ||
d288f65f | 7526 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7527 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7528 | { |
7529 | struct drm_device *dev = crtc->base.dev; | |
7530 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7531 | int pipe = crtc->pipe; | |
f0f59a00 | 7532 | i915_reg_t dpll_reg = DPLL(crtc->pipe); |
9d556c99 | 7533 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 7534 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7535 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7536 | u32 dpio_val; |
9cbe40c1 | 7537 | int vco; |
9d556c99 | 7538 | |
d288f65f VS |
7539 | bestn = pipe_config->dpll.n; |
7540 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7541 | bestm1 = pipe_config->dpll.m1; | |
7542 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7543 | bestp1 = pipe_config->dpll.p1; | |
7544 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7545 | vco = pipe_config->dpll.vco; |
a945ce7e | 7546 | dpio_val = 0; |
9cbe40c1 | 7547 | loopfilter = 0; |
9d556c99 CML |
7548 | |
7549 | /* | |
7550 | * Enable Refclk and SSC | |
7551 | */ | |
a11b0703 | 7552 | I915_WRITE(dpll_reg, |
d288f65f | 7553 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 | 7554 | |
a580516d | 7555 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7556 | |
9d556c99 CML |
7557 | /* p1 and p2 divider */ |
7558 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7559 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7560 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7561 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7562 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7563 | ||
7564 | /* Feedback post-divider - m2 */ | |
7565 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7566 | ||
7567 | /* Feedback refclk divider - n and m1 */ | |
7568 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7569 | DPIO_CHV_M1_DIV_BY_2 | | |
7570 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7571 | ||
7572 | /* M2 fraction division */ | |
25a25dfc | 7573 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
7574 | |
7575 | /* M2 fraction division enable */ | |
a945ce7e VP |
7576 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7577 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7578 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7579 | if (bestm2_frac) | |
7580 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7581 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7582 | |
de3a0fde VP |
7583 | /* Program digital lock detect threshold */ |
7584 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7585 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7586 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7587 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7588 | if (!bestm2_frac) | |
7589 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7590 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7591 | ||
9d556c99 | 7592 | /* Loop filter */ |
9cbe40c1 VP |
7593 | if (vco == 5400000) { |
7594 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7595 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7596 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7597 | tribuf_calcntr = 0x9; | |
7598 | } else if (vco <= 6200000) { | |
7599 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7600 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7601 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7602 | tribuf_calcntr = 0x9; | |
7603 | } else if (vco <= 6480000) { | |
7604 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7605 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7606 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7607 | tribuf_calcntr = 0x8; | |
7608 | } else { | |
7609 | /* Not supported. Apply the same limits as in the max case */ | |
7610 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7611 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7612 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7613 | tribuf_calcntr = 0; | |
7614 | } | |
9d556c99 CML |
7615 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7616 | ||
968040b2 | 7617 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7618 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7619 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7620 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7621 | ||
9d556c99 CML |
7622 | /* AFC Recal */ |
7623 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7624 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7625 | DPIO_AFC_RECAL); | |
7626 | ||
a580516d | 7627 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
7628 | } |
7629 | ||
d288f65f VS |
7630 | /** |
7631 | * vlv_force_pll_on - forcibly enable just the PLL | |
7632 | * @dev_priv: i915 private structure | |
7633 | * @pipe: pipe PLL to enable | |
7634 | * @dpll: PLL configuration | |
7635 | * | |
7636 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7637 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7638 | * be enabled. | |
7639 | */ | |
7640 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, | |
7641 | const struct dpll *dpll) | |
7642 | { | |
7643 | struct intel_crtc *crtc = | |
7644 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
5cec258b | 7645 | struct intel_crtc_state pipe_config = { |
a93e255f | 7646 | .base.crtc = &crtc->base, |
d288f65f VS |
7647 | .pixel_multiplier = 1, |
7648 | .dpll = *dpll, | |
7649 | }; | |
7650 | ||
7651 | if (IS_CHERRYVIEW(dev)) { | |
251ac862 | 7652 | chv_compute_dpll(crtc, &pipe_config); |
d288f65f VS |
7653 | chv_prepare_pll(crtc, &pipe_config); |
7654 | chv_enable_pll(crtc, &pipe_config); | |
7655 | } else { | |
251ac862 | 7656 | vlv_compute_dpll(crtc, &pipe_config); |
d288f65f VS |
7657 | vlv_prepare_pll(crtc, &pipe_config); |
7658 | vlv_enable_pll(crtc, &pipe_config); | |
7659 | } | |
7660 | } | |
7661 | ||
7662 | /** | |
7663 | * vlv_force_pll_off - forcibly disable just the PLL | |
7664 | * @dev_priv: i915 private structure | |
7665 | * @pipe: pipe PLL to disable | |
7666 | * | |
7667 | * Disable the PLL for @pipe. To be used in cases where we need | |
7668 | * the PLL enabled even when @pipe is not going to be enabled. | |
7669 | */ | |
7670 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7671 | { | |
7672 | if (IS_CHERRYVIEW(dev)) | |
7673 | chv_disable_pll(to_i915(dev), pipe); | |
7674 | else | |
7675 | vlv_disable_pll(to_i915(dev), pipe); | |
7676 | } | |
7677 | ||
251ac862 DV |
7678 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
7679 | struct intel_crtc_state *crtc_state, | |
7680 | intel_clock_t *reduced_clock, | |
7681 | int num_connectors) | |
eb1cbe48 | 7682 | { |
f47709a9 | 7683 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7684 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
7685 | u32 dpll; |
7686 | bool is_sdvo; | |
190f68c5 | 7687 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7688 | |
190f68c5 | 7689 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7690 | |
a93e255f ACO |
7691 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7692 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
7693 | |
7694 | dpll = DPLL_VGA_MODE_DIS; | |
7695 | ||
a93e255f | 7696 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7697 | dpll |= DPLLB_MODE_LVDS; |
7698 | else | |
7699 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7700 | |
ef1b460d | 7701 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7702 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7703 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7704 | } |
198a037f DV |
7705 | |
7706 | if (is_sdvo) | |
4a33e48d | 7707 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7708 | |
190f68c5 | 7709 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7710 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7711 | |
7712 | /* compute bitmask from p1 value */ | |
7713 | if (IS_PINEVIEW(dev)) | |
7714 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7715 | else { | |
7716 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7717 | if (IS_G4X(dev) && reduced_clock) | |
7718 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7719 | } | |
7720 | switch (clock->p2) { | |
7721 | case 5: | |
7722 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7723 | break; | |
7724 | case 7: | |
7725 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7726 | break; | |
7727 | case 10: | |
7728 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7729 | break; | |
7730 | case 14: | |
7731 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7732 | break; | |
7733 | } | |
7734 | if (INTEL_INFO(dev)->gen >= 4) | |
7735 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7736 | ||
190f68c5 | 7737 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7738 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 7739 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7740 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7741 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7742 | else | |
7743 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7744 | ||
7745 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7746 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7747 | |
eb1cbe48 | 7748 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7749 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7750 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7751 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7752 | } |
7753 | } | |
7754 | ||
251ac862 DV |
7755 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
7756 | struct intel_crtc_state *crtc_state, | |
7757 | intel_clock_t *reduced_clock, | |
7758 | int num_connectors) | |
eb1cbe48 | 7759 | { |
f47709a9 | 7760 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7761 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 7762 | u32 dpll; |
190f68c5 | 7763 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7764 | |
190f68c5 | 7765 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7766 | |
eb1cbe48 DV |
7767 | dpll = DPLL_VGA_MODE_DIS; |
7768 | ||
a93e255f | 7769 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7770 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7771 | } else { | |
7772 | if (clock->p1 == 2) | |
7773 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7774 | else | |
7775 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7776 | if (clock->p2 == 4) | |
7777 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7778 | } | |
7779 | ||
a93e255f | 7780 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7781 | dpll |= DPLL_DVO_2X_MODE; |
7782 | ||
a93e255f | 7783 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7784 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7785 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7786 | else | |
7787 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7788 | ||
7789 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7790 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7791 | } |
7792 | ||
8a654f3b | 7793 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7794 | { |
7795 | struct drm_device *dev = intel_crtc->base.dev; | |
7796 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7797 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 7798 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 7799 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7800 | uint32_t crtc_vtotal, crtc_vblank_end; |
7801 | int vsyncshift = 0; | |
4d8a62ea DV |
7802 | |
7803 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7804 | * the hw state checker will get angry at the mismatch. */ | |
7805 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7806 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7807 | |
609aeaca | 7808 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7809 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7810 | crtc_vtotal -= 1; |
7811 | crtc_vblank_end -= 1; | |
609aeaca | 7812 | |
409ee761 | 7813 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7814 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7815 | else | |
7816 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7817 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7818 | if (vsyncshift < 0) |
7819 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7820 | } |
7821 | ||
7822 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7823 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7824 | |
fe2b8f9d | 7825 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7826 | (adjusted_mode->crtc_hdisplay - 1) | |
7827 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7828 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7829 | (adjusted_mode->crtc_hblank_start - 1) | |
7830 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7831 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7832 | (adjusted_mode->crtc_hsync_start - 1) | |
7833 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7834 | ||
fe2b8f9d | 7835 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7836 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7837 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7838 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7839 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7840 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7841 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7842 | (adjusted_mode->crtc_vsync_start - 1) | |
7843 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7844 | ||
b5e508d4 PZ |
7845 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7846 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7847 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7848 | * bits. */ | |
7849 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7850 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7851 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7852 | ||
b0e77b9c PZ |
7853 | /* pipesrc controls the size that is scaled from, which should |
7854 | * always be the user's requested size. | |
7855 | */ | |
7856 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7857 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7858 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7859 | } |
7860 | ||
1bd1bd80 | 7861 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7862 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7863 | { |
7864 | struct drm_device *dev = crtc->base.dev; | |
7865 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7866 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7867 | uint32_t tmp; | |
7868 | ||
7869 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7870 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7871 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7872 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7873 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7874 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7875 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7876 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7877 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7878 | |
7879 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7880 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7881 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7882 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7883 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7884 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7885 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7886 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7887 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7888 | |
7889 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7890 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7891 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7892 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 DV |
7893 | } |
7894 | ||
7895 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7896 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7897 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7898 | ||
2d112de7 ACO |
7899 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7900 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7901 | } |
7902 | ||
f6a83288 | 7903 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7904 | struct intel_crtc_state *pipe_config) |
babea61d | 7905 | { |
2d112de7 ACO |
7906 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7907 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7908 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7909 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7910 | |
2d112de7 ACO |
7911 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7912 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7913 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7914 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7915 | |
2d112de7 | 7916 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7917 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7918 | |
2d112de7 ACO |
7919 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7920 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
7921 | |
7922 | mode->hsync = drm_mode_hsync(mode); | |
7923 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7924 | drm_mode_set_name(mode); | |
babea61d JB |
7925 | } |
7926 | ||
84b046f3 DV |
7927 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7928 | { | |
7929 | struct drm_device *dev = intel_crtc->base.dev; | |
7930 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7931 | uint32_t pipeconf; | |
7932 | ||
9f11a9e4 | 7933 | pipeconf = 0; |
84b046f3 | 7934 | |
b6b5d049 VS |
7935 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7936 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7937 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7938 | |
6e3c9717 | 7939 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7940 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7941 | |
ff9ce46e | 7942 | /* only g4x and later have fancy bpc/dither controls */ |
666a4537 | 7943 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
ff9ce46e | 7944 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7945 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7946 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7947 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7948 | |
6e3c9717 | 7949 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7950 | case 18: |
7951 | pipeconf |= PIPECONF_6BPC; | |
7952 | break; | |
7953 | case 24: | |
7954 | pipeconf |= PIPECONF_8BPC; | |
7955 | break; | |
7956 | case 30: | |
7957 | pipeconf |= PIPECONF_10BPC; | |
7958 | break; | |
7959 | default: | |
7960 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7961 | BUG(); | |
84b046f3 DV |
7962 | } |
7963 | } | |
7964 | ||
7965 | if (HAS_PIPE_CXSR(dev)) { | |
7966 | if (intel_crtc->lowfreq_avail) { | |
7967 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7968 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7969 | } else { | |
7970 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7971 | } |
7972 | } | |
7973 | ||
6e3c9717 | 7974 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7975 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 7976 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7977 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7978 | else | |
7979 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7980 | } else | |
84b046f3 DV |
7981 | pipeconf |= PIPECONF_PROGRESSIVE; |
7982 | ||
666a4537 WB |
7983 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
7984 | intel_crtc->config->limited_color_range) | |
9f11a9e4 | 7985 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7986 | |
84b046f3 DV |
7987 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7988 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7989 | } | |
7990 | ||
190f68c5 ACO |
7991 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7992 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7993 | { |
c7653199 | 7994 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7995 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 7996 | int refclk, num_connectors = 0; |
c329a4ec DV |
7997 | intel_clock_t clock; |
7998 | bool ok; | |
d4906093 | 7999 | const intel_limit_t *limit; |
55bb9992 | 8000 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8001 | struct drm_connector *connector; |
55bb9992 ACO |
8002 | struct drm_connector_state *connector_state; |
8003 | int i; | |
79e53945 | 8004 | |
dd3cd74a ACO |
8005 | memset(&crtc_state->dpll_hw_state, 0, |
8006 | sizeof(crtc_state->dpll_hw_state)); | |
8007 | ||
a65347ba JN |
8008 | if (crtc_state->has_dsi_encoder) |
8009 | return 0; | |
43565a06 | 8010 | |
a65347ba JN |
8011 | for_each_connector_in_state(state, connector, connector_state, i) { |
8012 | if (connector_state->crtc == &crtc->base) | |
8013 | num_connectors++; | |
79e53945 JB |
8014 | } |
8015 | ||
190f68c5 | 8016 | if (!crtc_state->clock_set) { |
a93e255f | 8017 | refclk = i9xx_get_refclk(crtc_state, num_connectors); |
79e53945 | 8018 | |
e9fd1c02 JN |
8019 | /* |
8020 | * Returns a set of divisors for the desired target clock with | |
8021 | * the given refclk, or FALSE. The returned values represent | |
8022 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
8023 | * 2) / p1 / p2. | |
8024 | */ | |
a93e255f ACO |
8025 | limit = intel_limit(crtc_state, refclk); |
8026 | ok = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 8027 | crtc_state->port_clock, |
e9fd1c02 | 8028 | refclk, NULL, &clock); |
f2335330 | 8029 | if (!ok) { |
e9fd1c02 JN |
8030 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8031 | return -EINVAL; | |
8032 | } | |
79e53945 | 8033 | |
f2335330 | 8034 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
8035 | crtc_state->dpll.n = clock.n; |
8036 | crtc_state->dpll.m1 = clock.m1; | |
8037 | crtc_state->dpll.m2 = clock.m2; | |
8038 | crtc_state->dpll.p1 = clock.p1; | |
8039 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 8040 | } |
7026d4ac | 8041 | |
e9fd1c02 | 8042 | if (IS_GEN2(dev)) { |
c329a4ec | 8043 | i8xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 8044 | num_connectors); |
9d556c99 | 8045 | } else if (IS_CHERRYVIEW(dev)) { |
251ac862 | 8046 | chv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 8047 | } else if (IS_VALLEYVIEW(dev)) { |
251ac862 | 8048 | vlv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 8049 | } else { |
c329a4ec | 8050 | i9xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 8051 | num_connectors); |
e9fd1c02 | 8052 | } |
79e53945 | 8053 | |
c8f7a0db | 8054 | return 0; |
f564048e EA |
8055 | } |
8056 | ||
2fa2fe9a | 8057 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8058 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8059 | { |
8060 | struct drm_device *dev = crtc->base.dev; | |
8061 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8062 | uint32_t tmp; | |
8063 | ||
dc9e7dec VS |
8064 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
8065 | return; | |
8066 | ||
2fa2fe9a | 8067 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
8068 | if (!(tmp & PFIT_ENABLE)) |
8069 | return; | |
2fa2fe9a | 8070 | |
06922821 | 8071 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
8072 | if (INTEL_INFO(dev)->gen < 4) { |
8073 | if (crtc->pipe != PIPE_B) | |
8074 | return; | |
2fa2fe9a DV |
8075 | } else { |
8076 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
8077 | return; | |
8078 | } | |
8079 | ||
06922821 | 8080 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
8081 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
8082 | if (INTEL_INFO(dev)->gen < 5) | |
8083 | pipe_config->gmch_pfit.lvds_border_bits = | |
8084 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
8085 | } | |
8086 | ||
acbec814 | 8087 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8088 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
8089 | { |
8090 | struct drm_device *dev = crtc->base.dev; | |
8091 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8092 | int pipe = pipe_config->cpu_transcoder; | |
8093 | intel_clock_t clock; | |
8094 | u32 mdiv; | |
662c6ecb | 8095 | int refclk = 100000; |
acbec814 | 8096 | |
f573de5a SK |
8097 | /* In case of MIPI DPLL will not even be used */ |
8098 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
8099 | return; | |
8100 | ||
a580516d | 8101 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 8102 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 8103 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
8104 | |
8105 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
8106 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
8107 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
8108 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
8109 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
8110 | ||
dccbea3b | 8111 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
8112 | } |
8113 | ||
5724dbd1 DL |
8114 | static void |
8115 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
8116 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
8117 | { |
8118 | struct drm_device *dev = crtc->base.dev; | |
8119 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8120 | u32 val, base, offset; | |
8121 | int pipe = crtc->pipe, plane = crtc->plane; | |
8122 | int fourcc, pixel_format; | |
6761dd31 | 8123 | unsigned int aligned_height; |
b113d5ee | 8124 | struct drm_framebuffer *fb; |
1b842c89 | 8125 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 8126 | |
42a7b088 DL |
8127 | val = I915_READ(DSPCNTR(plane)); |
8128 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8129 | return; | |
8130 | ||
d9806c9f | 8131 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8132 | if (!intel_fb) { |
1ad292b5 JB |
8133 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8134 | return; | |
8135 | } | |
8136 | ||
1b842c89 DL |
8137 | fb = &intel_fb->base; |
8138 | ||
18c5247e DV |
8139 | if (INTEL_INFO(dev)->gen >= 4) { |
8140 | if (val & DISPPLANE_TILED) { | |
49af449b | 8141 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8142 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8143 | } | |
8144 | } | |
1ad292b5 JB |
8145 | |
8146 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8147 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8148 | fb->pixel_format = fourcc; |
8149 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
8150 | |
8151 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 8152 | if (plane_config->tiling) |
1ad292b5 JB |
8153 | offset = I915_READ(DSPTILEOFF(plane)); |
8154 | else | |
8155 | offset = I915_READ(DSPLINOFF(plane)); | |
8156 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8157 | } else { | |
8158 | base = I915_READ(DSPADDR(plane)); | |
8159 | } | |
8160 | plane_config->base = base; | |
8161 | ||
8162 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8163 | fb->width = ((val >> 16) & 0xfff) + 1; |
8164 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8165 | |
8166 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8167 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8168 | |
b113d5ee | 8169 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8170 | fb->pixel_format, |
8171 | fb->modifier[0]); | |
1ad292b5 | 8172 | |
f37b5c2b | 8173 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8174 | |
2844a921 DL |
8175 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8176 | pipe_name(pipe), plane, fb->width, fb->height, | |
8177 | fb->bits_per_pixel, base, fb->pitches[0], | |
8178 | plane_config->size); | |
1ad292b5 | 8179 | |
2d14030b | 8180 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8181 | } |
8182 | ||
70b23a98 | 8183 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8184 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8185 | { |
8186 | struct drm_device *dev = crtc->base.dev; | |
8187 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8188 | int pipe = pipe_config->cpu_transcoder; | |
8189 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
8190 | intel_clock_t clock; | |
0d7b6b11 | 8191 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8192 | int refclk = 100000; |
8193 | ||
a580516d | 8194 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8195 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8196 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8197 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8198 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8199 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8200 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8201 | |
8202 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8203 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8204 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8205 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8206 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8207 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8208 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8209 | ||
dccbea3b | 8210 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8211 | } |
8212 | ||
0e8ffe1b | 8213 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8214 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8215 | { |
8216 | struct drm_device *dev = crtc->base.dev; | |
8217 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8218 | uint32_t tmp; | |
8219 | ||
f458ebbc DV |
8220 | if (!intel_display_power_is_enabled(dev_priv, |
8221 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
b5482bd0 ID |
8222 | return false; |
8223 | ||
e143a21c | 8224 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 8225 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 8226 | |
0e8ffe1b DV |
8227 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8228 | if (!(tmp & PIPECONF_ENABLE)) | |
8229 | return false; | |
8230 | ||
666a4537 | 8231 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
42571aef VS |
8232 | switch (tmp & PIPECONF_BPC_MASK) { |
8233 | case PIPECONF_6BPC: | |
8234 | pipe_config->pipe_bpp = 18; | |
8235 | break; | |
8236 | case PIPECONF_8BPC: | |
8237 | pipe_config->pipe_bpp = 24; | |
8238 | break; | |
8239 | case PIPECONF_10BPC: | |
8240 | pipe_config->pipe_bpp = 30; | |
8241 | break; | |
8242 | default: | |
8243 | break; | |
8244 | } | |
8245 | } | |
8246 | ||
666a4537 WB |
8247 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
8248 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) | |
b5a9fa09 DV |
8249 | pipe_config->limited_color_range = true; |
8250 | ||
282740f7 VS |
8251 | if (INTEL_INFO(dev)->gen < 4) |
8252 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8253 | ||
1bd1bd80 DV |
8254 | intel_get_pipe_timings(crtc, pipe_config); |
8255 | ||
2fa2fe9a DV |
8256 | i9xx_get_pfit_config(crtc, pipe_config); |
8257 | ||
6c49f241 DV |
8258 | if (INTEL_INFO(dev)->gen >= 4) { |
8259 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
8260 | pipe_config->pixel_multiplier = | |
8261 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8262 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8263 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
8264 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
8265 | tmp = I915_READ(DPLL(crtc->pipe)); | |
8266 | pipe_config->pixel_multiplier = | |
8267 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8268 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8269 | } else { | |
8270 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8271 | * port and will be fixed up in the encoder->get_config | |
8272 | * function. */ | |
8273 | pipe_config->pixel_multiplier = 1; | |
8274 | } | |
8bcc2795 | 8275 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
666a4537 | 8276 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
1c4e0274 VS |
8277 | /* |
8278 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8279 | * on 830. Filter it out here so that we don't | |
8280 | * report errors due to that. | |
8281 | */ | |
8282 | if (IS_I830(dev)) | |
8283 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
8284 | ||
8bcc2795 DV |
8285 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8286 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8287 | } else { |
8288 | /* Mask out read-only status bits. */ | |
8289 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8290 | DPLL_PORTC_READY_MASK | | |
8291 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8292 | } |
6c49f241 | 8293 | |
70b23a98 VS |
8294 | if (IS_CHERRYVIEW(dev)) |
8295 | chv_crtc_clock_get(crtc, pipe_config); | |
8296 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
8297 | vlv_crtc_clock_get(crtc, pipe_config); |
8298 | else | |
8299 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8300 | |
0f64614d VS |
8301 | /* |
8302 | * Normally the dotclock is filled in by the encoder .get_config() | |
8303 | * but in case the pipe is enabled w/o any ports we need a sane | |
8304 | * default. | |
8305 | */ | |
8306 | pipe_config->base.adjusted_mode.crtc_clock = | |
8307 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8308 | ||
0e8ffe1b DV |
8309 | return true; |
8310 | } | |
8311 | ||
dde86e2d | 8312 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
8313 | { |
8314 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 8315 | struct intel_encoder *encoder; |
74cfd7ac | 8316 | u32 val, final; |
13d83a67 | 8317 | bool has_lvds = false; |
199e5d79 | 8318 | bool has_cpu_edp = false; |
199e5d79 | 8319 | bool has_panel = false; |
99eb6a01 KP |
8320 | bool has_ck505 = false; |
8321 | bool can_ssc = false; | |
13d83a67 JB |
8322 | |
8323 | /* We need to take the global config into account */ | |
b2784e15 | 8324 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8325 | switch (encoder->type) { |
8326 | case INTEL_OUTPUT_LVDS: | |
8327 | has_panel = true; | |
8328 | has_lvds = true; | |
8329 | break; | |
8330 | case INTEL_OUTPUT_EDP: | |
8331 | has_panel = true; | |
2de6905f | 8332 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8333 | has_cpu_edp = true; |
8334 | break; | |
6847d71b PZ |
8335 | default: |
8336 | break; | |
13d83a67 JB |
8337 | } |
8338 | } | |
8339 | ||
99eb6a01 | 8340 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 8341 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8342 | can_ssc = has_ck505; |
8343 | } else { | |
8344 | has_ck505 = false; | |
8345 | can_ssc = true; | |
8346 | } | |
8347 | ||
2de6905f ID |
8348 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
8349 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
8350 | |
8351 | /* Ironlake: try to setup display ref clock before DPLL | |
8352 | * enabling. This is only under driver's control after | |
8353 | * PCH B stepping, previous chipset stepping should be | |
8354 | * ignoring this setting. | |
8355 | */ | |
74cfd7ac CW |
8356 | val = I915_READ(PCH_DREF_CONTROL); |
8357 | ||
8358 | /* As we must carefully and slowly disable/enable each source in turn, | |
8359 | * compute the final state we want first and check if we need to | |
8360 | * make any changes at all. | |
8361 | */ | |
8362 | final = val; | |
8363 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8364 | if (has_ck505) | |
8365 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8366 | else | |
8367 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8368 | ||
8369 | final &= ~DREF_SSC_SOURCE_MASK; | |
8370 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
8371 | final &= ~DREF_SSC1_ENABLE; | |
8372 | ||
8373 | if (has_panel) { | |
8374 | final |= DREF_SSC_SOURCE_ENABLE; | |
8375 | ||
8376 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8377 | final |= DREF_SSC1_ENABLE; | |
8378 | ||
8379 | if (has_cpu_edp) { | |
8380 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8381 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8382 | else | |
8383 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8384 | } else | |
8385 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8386 | } else { | |
8387 | final |= DREF_SSC_SOURCE_DISABLE; | |
8388 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8389 | } | |
8390 | ||
8391 | if (final == val) | |
8392 | return; | |
8393 | ||
13d83a67 | 8394 | /* Always enable nonspread source */ |
74cfd7ac | 8395 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8396 | |
99eb6a01 | 8397 | if (has_ck505) |
74cfd7ac | 8398 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 8399 | else |
74cfd7ac | 8400 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 8401 | |
199e5d79 | 8402 | if (has_panel) { |
74cfd7ac CW |
8403 | val &= ~DREF_SSC_SOURCE_MASK; |
8404 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 8405 | |
199e5d79 | 8406 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 8407 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8408 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 8409 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 8410 | } else |
74cfd7ac | 8411 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
8412 | |
8413 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 8414 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8415 | POSTING_READ(PCH_DREF_CONTROL); |
8416 | udelay(200); | |
8417 | ||
74cfd7ac | 8418 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
8419 | |
8420 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 8421 | if (has_cpu_edp) { |
99eb6a01 | 8422 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8423 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 8424 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 8425 | } else |
74cfd7ac | 8426 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 8427 | } else |
74cfd7ac | 8428 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8429 | |
74cfd7ac | 8430 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8431 | POSTING_READ(PCH_DREF_CONTROL); |
8432 | udelay(200); | |
8433 | } else { | |
8434 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
8435 | ||
74cfd7ac | 8436 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
8437 | |
8438 | /* Turn off CPU output */ | |
74cfd7ac | 8439 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8440 | |
74cfd7ac | 8441 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8442 | POSTING_READ(PCH_DREF_CONTROL); |
8443 | udelay(200); | |
8444 | ||
8445 | /* Turn off the SSC source */ | |
74cfd7ac CW |
8446 | val &= ~DREF_SSC_SOURCE_MASK; |
8447 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
8448 | |
8449 | /* Turn off SSC1 */ | |
74cfd7ac | 8450 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 8451 | |
74cfd7ac | 8452 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
8453 | POSTING_READ(PCH_DREF_CONTROL); |
8454 | udelay(200); | |
8455 | } | |
74cfd7ac CW |
8456 | |
8457 | BUG_ON(val != final); | |
13d83a67 JB |
8458 | } |
8459 | ||
f31f2d55 | 8460 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 8461 | { |
f31f2d55 | 8462 | uint32_t tmp; |
dde86e2d | 8463 | |
0ff066a9 PZ |
8464 | tmp = I915_READ(SOUTH_CHICKEN2); |
8465 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8466 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8467 | |
0ff066a9 PZ |
8468 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
8469 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
8470 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 8471 | |
0ff066a9 PZ |
8472 | tmp = I915_READ(SOUTH_CHICKEN2); |
8473 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8474 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8475 | |
0ff066a9 PZ |
8476 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
8477 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
8478 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
8479 | } |
8480 | ||
8481 | /* WaMPhyProgramming:hsw */ | |
8482 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8483 | { | |
8484 | uint32_t tmp; | |
dde86e2d PZ |
8485 | |
8486 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8487 | tmp &= ~(0xFF << 24); | |
8488 | tmp |= (0x12 << 24); | |
8489 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8490 | ||
dde86e2d PZ |
8491 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
8492 | tmp |= (1 << 11); | |
8493 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8494 | ||
8495 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8496 | tmp |= (1 << 11); | |
8497 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8498 | ||
dde86e2d PZ |
8499 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
8500 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8501 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
8502 | ||
8503 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
8504 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8505 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8506 | ||
0ff066a9 PZ |
8507 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
8508 | tmp &= ~(7 << 13); | |
8509 | tmp |= (5 << 13); | |
8510 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 8511 | |
0ff066a9 PZ |
8512 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
8513 | tmp &= ~(7 << 13); | |
8514 | tmp |= (5 << 13); | |
8515 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
8516 | |
8517 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8518 | tmp &= ~0xFF; | |
8519 | tmp |= 0x1C; | |
8520 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8521 | ||
8522 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8523 | tmp &= ~0xFF; | |
8524 | tmp |= 0x1C; | |
8525 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8526 | ||
8527 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8528 | tmp &= ~(0xFF << 16); | |
8529 | tmp |= (0x1C << 16); | |
8530 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8531 | ||
8532 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8533 | tmp &= ~(0xFF << 16); | |
8534 | tmp |= (0x1C << 16); | |
8535 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8536 | ||
0ff066a9 PZ |
8537 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8538 | tmp |= (1 << 27); | |
8539 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8540 | |
0ff066a9 PZ |
8541 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8542 | tmp |= (1 << 27); | |
8543 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8544 | |
0ff066a9 PZ |
8545 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8546 | tmp &= ~(0xF << 28); | |
8547 | tmp |= (4 << 28); | |
8548 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8549 | |
0ff066a9 PZ |
8550 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8551 | tmp &= ~(0xF << 28); | |
8552 | tmp |= (4 << 28); | |
8553 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8554 | } |
8555 | ||
2fa86a1f PZ |
8556 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8557 | * Programming" based on the parameters passed: | |
8558 | * - Sequence to enable CLKOUT_DP | |
8559 | * - Sequence to enable CLKOUT_DP without spread | |
8560 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8561 | */ | |
8562 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8563 | bool with_fdi) | |
f31f2d55 PZ |
8564 | { |
8565 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
8566 | uint32_t reg, tmp; |
8567 | ||
8568 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8569 | with_spread = true; | |
c2699524 | 8570 | if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) |
2fa86a1f | 8571 | with_fdi = false; |
f31f2d55 | 8572 | |
a580516d | 8573 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
8574 | |
8575 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8576 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8577 | tmp |= SBI_SSCCTL_PATHALT; | |
8578 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8579 | ||
8580 | udelay(24); | |
8581 | ||
2fa86a1f PZ |
8582 | if (with_spread) { |
8583 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8584 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8585 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8586 | |
2fa86a1f PZ |
8587 | if (with_fdi) { |
8588 | lpt_reset_fdi_mphy(dev_priv); | |
8589 | lpt_program_fdi_mphy(dev_priv); | |
8590 | } | |
8591 | } | |
dde86e2d | 8592 | |
c2699524 | 8593 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
8594 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8595 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8596 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 8597 | |
a580516d | 8598 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
8599 | } |
8600 | ||
47701c3b PZ |
8601 | /* Sequence to disable CLKOUT_DP */ |
8602 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8603 | { | |
8604 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8605 | uint32_t reg, tmp; | |
8606 | ||
a580516d | 8607 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 8608 | |
c2699524 | 8609 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
8610 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8611 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8612 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8613 | ||
8614 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8615 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8616 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8617 | tmp |= SBI_SSCCTL_PATHALT; | |
8618 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8619 | udelay(32); | |
8620 | } | |
8621 | tmp |= SBI_SSCCTL_DISABLE; | |
8622 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8623 | } | |
8624 | ||
a580516d | 8625 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8626 | } |
8627 | ||
f7be2c21 VS |
8628 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
8629 | ||
8630 | static const uint16_t sscdivintphase[] = { | |
8631 | [BEND_IDX( 50)] = 0x3B23, | |
8632 | [BEND_IDX( 45)] = 0x3B23, | |
8633 | [BEND_IDX( 40)] = 0x3C23, | |
8634 | [BEND_IDX( 35)] = 0x3C23, | |
8635 | [BEND_IDX( 30)] = 0x3D23, | |
8636 | [BEND_IDX( 25)] = 0x3D23, | |
8637 | [BEND_IDX( 20)] = 0x3E23, | |
8638 | [BEND_IDX( 15)] = 0x3E23, | |
8639 | [BEND_IDX( 10)] = 0x3F23, | |
8640 | [BEND_IDX( 5)] = 0x3F23, | |
8641 | [BEND_IDX( 0)] = 0x0025, | |
8642 | [BEND_IDX( -5)] = 0x0025, | |
8643 | [BEND_IDX(-10)] = 0x0125, | |
8644 | [BEND_IDX(-15)] = 0x0125, | |
8645 | [BEND_IDX(-20)] = 0x0225, | |
8646 | [BEND_IDX(-25)] = 0x0225, | |
8647 | [BEND_IDX(-30)] = 0x0325, | |
8648 | [BEND_IDX(-35)] = 0x0325, | |
8649 | [BEND_IDX(-40)] = 0x0425, | |
8650 | [BEND_IDX(-45)] = 0x0425, | |
8651 | [BEND_IDX(-50)] = 0x0525, | |
8652 | }; | |
8653 | ||
8654 | /* | |
8655 | * Bend CLKOUT_DP | |
8656 | * steps -50 to 50 inclusive, in steps of 5 | |
8657 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
8658 | * change in clock period = -(steps / 10) * 5.787 ps | |
8659 | */ | |
8660 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
8661 | { | |
8662 | uint32_t tmp; | |
8663 | int idx = BEND_IDX(steps); | |
8664 | ||
8665 | if (WARN_ON(steps % 5 != 0)) | |
8666 | return; | |
8667 | ||
8668 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
8669 | return; | |
8670 | ||
8671 | mutex_lock(&dev_priv->sb_lock); | |
8672 | ||
8673 | if (steps % 10 != 0) | |
8674 | tmp = 0xAAAAAAAB; | |
8675 | else | |
8676 | tmp = 0x00000000; | |
8677 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
8678 | ||
8679 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
8680 | tmp &= 0xffff0000; | |
8681 | tmp |= sscdivintphase[idx]; | |
8682 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
8683 | ||
8684 | mutex_unlock(&dev_priv->sb_lock); | |
8685 | } | |
8686 | ||
8687 | #undef BEND_IDX | |
8688 | ||
bf8fa3d3 PZ |
8689 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8690 | { | |
bf8fa3d3 PZ |
8691 | struct intel_encoder *encoder; |
8692 | bool has_vga = false; | |
8693 | ||
b2784e15 | 8694 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8695 | switch (encoder->type) { |
8696 | case INTEL_OUTPUT_ANALOG: | |
8697 | has_vga = true; | |
8698 | break; | |
6847d71b PZ |
8699 | default: |
8700 | break; | |
bf8fa3d3 PZ |
8701 | } |
8702 | } | |
8703 | ||
f7be2c21 VS |
8704 | if (has_vga) { |
8705 | lpt_bend_clkout_dp(to_i915(dev), 0); | |
47701c3b | 8706 | lpt_enable_clkout_dp(dev, true, true); |
f7be2c21 | 8707 | } else { |
47701c3b | 8708 | lpt_disable_clkout_dp(dev); |
f7be2c21 | 8709 | } |
bf8fa3d3 PZ |
8710 | } |
8711 | ||
dde86e2d PZ |
8712 | /* |
8713 | * Initialize reference clocks when the driver loads | |
8714 | */ | |
8715 | void intel_init_pch_refclk(struct drm_device *dev) | |
8716 | { | |
8717 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8718 | ironlake_init_pch_refclk(dev); | |
8719 | else if (HAS_PCH_LPT(dev)) | |
8720 | lpt_init_pch_refclk(dev); | |
8721 | } | |
8722 | ||
55bb9992 | 8723 | static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) |
d9d444cb | 8724 | { |
55bb9992 | 8725 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d9d444cb | 8726 | struct drm_i915_private *dev_priv = dev->dev_private; |
55bb9992 | 8727 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8728 | struct drm_connector *connector; |
55bb9992 | 8729 | struct drm_connector_state *connector_state; |
d9d444cb | 8730 | struct intel_encoder *encoder; |
55bb9992 | 8731 | int num_connectors = 0, i; |
d9d444cb JB |
8732 | bool is_lvds = false; |
8733 | ||
da3ced29 | 8734 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8735 | if (connector_state->crtc != crtc_state->base.crtc) |
8736 | continue; | |
8737 | ||
8738 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8739 | ||
d9d444cb JB |
8740 | switch (encoder->type) { |
8741 | case INTEL_OUTPUT_LVDS: | |
8742 | is_lvds = true; | |
8743 | break; | |
6847d71b PZ |
8744 | default: |
8745 | break; | |
d9d444cb JB |
8746 | } |
8747 | num_connectors++; | |
8748 | } | |
8749 | ||
8750 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 8751 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 8752 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 8753 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
8754 | } |
8755 | ||
8756 | return 120000; | |
8757 | } | |
8758 | ||
6ff93609 | 8759 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8760 | { |
c8203565 | 8761 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
8762 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8763 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8764 | uint32_t val; |
8765 | ||
78114071 | 8766 | val = 0; |
c8203565 | 8767 | |
6e3c9717 | 8768 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8769 | case 18: |
dfd07d72 | 8770 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8771 | break; |
8772 | case 24: | |
dfd07d72 | 8773 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8774 | break; |
8775 | case 30: | |
dfd07d72 | 8776 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8777 | break; |
8778 | case 36: | |
dfd07d72 | 8779 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8780 | break; |
8781 | default: | |
cc769b62 PZ |
8782 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8783 | BUG(); | |
c8203565 PZ |
8784 | } |
8785 | ||
6e3c9717 | 8786 | if (intel_crtc->config->dither) |
c8203565 PZ |
8787 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8788 | ||
6e3c9717 | 8789 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8790 | val |= PIPECONF_INTERLACED_ILK; |
8791 | else | |
8792 | val |= PIPECONF_PROGRESSIVE; | |
8793 | ||
6e3c9717 | 8794 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8795 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8796 | |
c8203565 PZ |
8797 | I915_WRITE(PIPECONF(pipe), val); |
8798 | POSTING_READ(PIPECONF(pipe)); | |
8799 | } | |
8800 | ||
86d3efce VS |
8801 | /* |
8802 | * Set up the pipe CSC unit. | |
8803 | * | |
8804 | * Currently only full range RGB to limited range RGB conversion | |
8805 | * is supported, but eventually this should handle various | |
8806 | * RGB<->YCbCr scenarios as well. | |
8807 | */ | |
50f3b016 | 8808 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
8809 | { |
8810 | struct drm_device *dev = crtc->dev; | |
8811 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8812 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8813 | int pipe = intel_crtc->pipe; | |
8814 | uint16_t coeff = 0x7800; /* 1.0 */ | |
8815 | ||
8816 | /* | |
8817 | * TODO: Check what kind of values actually come out of the pipe | |
8818 | * with these coeff/postoff values and adjust to get the best | |
8819 | * accuracy. Perhaps we even need to take the bpc value into | |
8820 | * consideration. | |
8821 | */ | |
8822 | ||
6e3c9717 | 8823 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8824 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
8825 | ||
8826 | /* | |
8827 | * GY/GU and RY/RU should be the other way around according | |
8828 | * to BSpec, but reality doesn't agree. Just set them up in | |
8829 | * a way that results in the correct picture. | |
8830 | */ | |
8831 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
8832 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
8833 | ||
8834 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
8835 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
8836 | ||
8837 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
8838 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
8839 | ||
8840 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
8841 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
8842 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
8843 | ||
8844 | if (INTEL_INFO(dev)->gen > 6) { | |
8845 | uint16_t postoff = 0; | |
8846 | ||
6e3c9717 | 8847 | if (intel_crtc->config->limited_color_range) |
32cf0cb0 | 8848 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
8849 | |
8850 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
8851 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
8852 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
8853 | ||
8854 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
8855 | } else { | |
8856 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
8857 | ||
6e3c9717 | 8858 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8859 | mode |= CSC_BLACK_SCREEN_OFFSET; |
8860 | ||
8861 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
8862 | } | |
8863 | } | |
8864 | ||
6ff93609 | 8865 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8866 | { |
756f85cf PZ |
8867 | struct drm_device *dev = crtc->dev; |
8868 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 8869 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 8870 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 8871 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee2b0b38 PZ |
8872 | uint32_t val; |
8873 | ||
3eff4faa | 8874 | val = 0; |
ee2b0b38 | 8875 | |
6e3c9717 | 8876 | if (IS_HASWELL(dev) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8877 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8878 | ||
6e3c9717 | 8879 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8880 | val |= PIPECONF_INTERLACED_ILK; |
8881 | else | |
8882 | val |= PIPECONF_PROGRESSIVE; | |
8883 | ||
702e7a56 PZ |
8884 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8885 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
8886 | |
8887 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
8888 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 8889 | |
3cdf122c | 8890 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
8891 | val = 0; |
8892 | ||
6e3c9717 | 8893 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8894 | case 18: |
8895 | val |= PIPEMISC_DITHER_6_BPC; | |
8896 | break; | |
8897 | case 24: | |
8898 | val |= PIPEMISC_DITHER_8_BPC; | |
8899 | break; | |
8900 | case 30: | |
8901 | val |= PIPEMISC_DITHER_10_BPC; | |
8902 | break; | |
8903 | case 36: | |
8904 | val |= PIPEMISC_DITHER_12_BPC; | |
8905 | break; | |
8906 | default: | |
8907 | /* Case prevented by pipe_config_set_bpp. */ | |
8908 | BUG(); | |
8909 | } | |
8910 | ||
6e3c9717 | 8911 | if (intel_crtc->config->dither) |
756f85cf PZ |
8912 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8913 | ||
8914 | I915_WRITE(PIPEMISC(pipe), val); | |
8915 | } | |
ee2b0b38 PZ |
8916 | } |
8917 | ||
6591c6e4 | 8918 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
190f68c5 | 8919 | struct intel_crtc_state *crtc_state, |
6591c6e4 PZ |
8920 | intel_clock_t *clock, |
8921 | bool *has_reduced_clock, | |
8922 | intel_clock_t *reduced_clock) | |
8923 | { | |
8924 | struct drm_device *dev = crtc->dev; | |
8925 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6591c6e4 | 8926 | int refclk; |
d4906093 | 8927 | const intel_limit_t *limit; |
c329a4ec | 8928 | bool ret; |
79e53945 | 8929 | |
55bb9992 | 8930 | refclk = ironlake_get_refclk(crtc_state); |
79e53945 | 8931 | |
d4906093 ML |
8932 | /* |
8933 | * Returns a set of divisors for the desired target clock with the given | |
8934 | * refclk, or FALSE. The returned values represent the clock equation: | |
8935 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
8936 | */ | |
a93e255f ACO |
8937 | limit = intel_limit(crtc_state, refclk); |
8938 | ret = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 8939 | crtc_state->port_clock, |
ee9300bb | 8940 | refclk, NULL, clock); |
6591c6e4 PZ |
8941 | if (!ret) |
8942 | return false; | |
cda4b7d3 | 8943 | |
6591c6e4 PZ |
8944 | return true; |
8945 | } | |
8946 | ||
d4b1931c PZ |
8947 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8948 | { | |
8949 | /* | |
8950 | * Account for spread spectrum to avoid | |
8951 | * oversubscribing the link. Max center spread | |
8952 | * is 2.5%; use 5% for safety's sake. | |
8953 | */ | |
8954 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8955 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8956 | } |
8957 | ||
7429e9d4 | 8958 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8959 | { |
7429e9d4 | 8960 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8961 | } |
8962 | ||
de13a2e3 | 8963 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
190f68c5 | 8964 | struct intel_crtc_state *crtc_state, |
7429e9d4 | 8965 | u32 *fp, |
9a7c7890 | 8966 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 8967 | { |
de13a2e3 | 8968 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
8969 | struct drm_device *dev = crtc->dev; |
8970 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 | 8971 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8972 | struct drm_connector *connector; |
55bb9992 ACO |
8973 | struct drm_connector_state *connector_state; |
8974 | struct intel_encoder *encoder; | |
de13a2e3 | 8975 | uint32_t dpll; |
55bb9992 | 8976 | int factor, num_connectors = 0, i; |
09ede541 | 8977 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 8978 | |
da3ced29 | 8979 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8980 | if (connector_state->crtc != crtc_state->base.crtc) |
8981 | continue; | |
8982 | ||
8983 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8984 | ||
8985 | switch (encoder->type) { | |
79e53945 JB |
8986 | case INTEL_OUTPUT_LVDS: |
8987 | is_lvds = true; | |
8988 | break; | |
8989 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 8990 | case INTEL_OUTPUT_HDMI: |
79e53945 | 8991 | is_sdvo = true; |
79e53945 | 8992 | break; |
6847d71b PZ |
8993 | default: |
8994 | break; | |
79e53945 | 8995 | } |
43565a06 | 8996 | |
c751ce4f | 8997 | num_connectors++; |
79e53945 | 8998 | } |
79e53945 | 8999 | |
c1858123 | 9000 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
9001 | factor = 21; |
9002 | if (is_lvds) { | |
9003 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 9004 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 9005 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 9006 | factor = 25; |
190f68c5 | 9007 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 9008 | factor = 20; |
c1858123 | 9009 | |
190f68c5 | 9010 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
7d0ac5b7 | 9011 | *fp |= FP_CB_TUNE; |
2c07245f | 9012 | |
9a7c7890 DV |
9013 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
9014 | *fp2 |= FP_CB_TUNE; | |
9015 | ||
5eddb70b | 9016 | dpll = 0; |
2c07245f | 9017 | |
a07d6787 EA |
9018 | if (is_lvds) |
9019 | dpll |= DPLLB_MODE_LVDS; | |
9020 | else | |
9021 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 9022 | |
190f68c5 | 9023 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 9024 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
9025 | |
9026 | if (is_sdvo) | |
4a33e48d | 9027 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 9028 | if (crtc_state->has_dp_encoder) |
4a33e48d | 9029 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 9030 | |
a07d6787 | 9031 | /* compute bitmask from p1 value */ |
190f68c5 | 9032 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 9033 | /* also FPA1 */ |
190f68c5 | 9034 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 9035 | |
190f68c5 | 9036 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
9037 | case 5: |
9038 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
9039 | break; | |
9040 | case 7: | |
9041 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
9042 | break; | |
9043 | case 10: | |
9044 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
9045 | break; | |
9046 | case 14: | |
9047 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
9048 | break; | |
79e53945 JB |
9049 | } |
9050 | ||
b4c09f3b | 9051 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 9052 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
9053 | else |
9054 | dpll |= PLL_REF_INPUT_DREFCLK; | |
9055 | ||
959e16d6 | 9056 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
9057 | } |
9058 | ||
190f68c5 ACO |
9059 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
9060 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 9061 | { |
c7653199 | 9062 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 9063 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 9064 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 9065 | bool ok, has_reduced_clock = false; |
8b47047b | 9066 | bool is_lvds = false; |
e2b78267 | 9067 | struct intel_shared_dpll *pll; |
de13a2e3 | 9068 | |
dd3cd74a ACO |
9069 | memset(&crtc_state->dpll_hw_state, 0, |
9070 | sizeof(crtc_state->dpll_hw_state)); | |
9071 | ||
7905df29 | 9072 | is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS); |
79e53945 | 9073 | |
5dc5298b PZ |
9074 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
9075 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 9076 | |
190f68c5 | 9077 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
de13a2e3 | 9078 | &has_reduced_clock, &reduced_clock); |
190f68c5 | 9079 | if (!ok && !crtc_state->clock_set) { |
de13a2e3 PZ |
9080 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
9081 | return -EINVAL; | |
79e53945 | 9082 | } |
f47709a9 | 9083 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
9084 | if (!crtc_state->clock_set) { |
9085 | crtc_state->dpll.n = clock.n; | |
9086 | crtc_state->dpll.m1 = clock.m1; | |
9087 | crtc_state->dpll.m2 = clock.m2; | |
9088 | crtc_state->dpll.p1 = clock.p1; | |
9089 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 9090 | } |
79e53945 | 9091 | |
5dc5298b | 9092 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
190f68c5 ACO |
9093 | if (crtc_state->has_pch_encoder) { |
9094 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
cbbab5bd | 9095 | if (has_reduced_clock) |
7429e9d4 | 9096 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 9097 | |
190f68c5 | 9098 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
cbbab5bd DV |
9099 | &fp, &reduced_clock, |
9100 | has_reduced_clock ? &fp2 : NULL); | |
9101 | ||
190f68c5 ACO |
9102 | crtc_state->dpll_hw_state.dpll = dpll; |
9103 | crtc_state->dpll_hw_state.fp0 = fp; | |
66e985c0 | 9104 | if (has_reduced_clock) |
190f68c5 | 9105 | crtc_state->dpll_hw_state.fp1 = fp2; |
66e985c0 | 9106 | else |
190f68c5 | 9107 | crtc_state->dpll_hw_state.fp1 = fp; |
66e985c0 | 9108 | |
190f68c5 | 9109 | pll = intel_get_shared_dpll(crtc, crtc_state); |
ee7b9f93 | 9110 | if (pll == NULL) { |
84f44ce7 | 9111 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 9112 | pipe_name(crtc->pipe)); |
4b645f14 JB |
9113 | return -EINVAL; |
9114 | } | |
3fb37703 | 9115 | } |
79e53945 | 9116 | |
ab585dea | 9117 | if (is_lvds && has_reduced_clock) |
c7653199 | 9118 | crtc->lowfreq_avail = true; |
bcd644e0 | 9119 | else |
c7653199 | 9120 | crtc->lowfreq_avail = false; |
e2b78267 | 9121 | |
c8f7a0db | 9122 | return 0; |
79e53945 JB |
9123 | } |
9124 | ||
eb14cb74 VS |
9125 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
9126 | struct intel_link_m_n *m_n) | |
9127 | { | |
9128 | struct drm_device *dev = crtc->base.dev; | |
9129 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9130 | enum pipe pipe = crtc->pipe; | |
9131 | ||
9132 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
9133 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
9134 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9135 | & ~TU_SIZE_MASK; | |
9136 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
9137 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9138 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9139 | } | |
9140 | ||
9141 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
9142 | enum transcoder transcoder, | |
b95af8be VK |
9143 | struct intel_link_m_n *m_n, |
9144 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
9145 | { |
9146 | struct drm_device *dev = crtc->base.dev; | |
9147 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 9148 | enum pipe pipe = crtc->pipe; |
72419203 | 9149 | |
eb14cb74 VS |
9150 | if (INTEL_INFO(dev)->gen >= 5) { |
9151 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
9152 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
9153 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
9154 | & ~TU_SIZE_MASK; | |
9155 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
9156 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
9157 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
9158 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
9159 | * gen < 8) and if DRRS is supported (to make sure the | |
9160 | * registers are not unnecessarily read). | |
9161 | */ | |
9162 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 9163 | crtc->config->has_drrs) { |
b95af8be VK |
9164 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
9165 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
9166 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
9167 | & ~TU_SIZE_MASK; | |
9168 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
9169 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
9170 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9171 | } | |
eb14cb74 VS |
9172 | } else { |
9173 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
9174 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
9175 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9176 | & ~TU_SIZE_MASK; | |
9177 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
9178 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9179 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9180 | } | |
9181 | } | |
9182 | ||
9183 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 9184 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 9185 | { |
681a8504 | 9186 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
9187 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
9188 | else | |
9189 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
9190 | &pipe_config->dp_m_n, |
9191 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 9192 | } |
72419203 | 9193 | |
eb14cb74 | 9194 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 9195 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
9196 | { |
9197 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 9198 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
9199 | } |
9200 | ||
bd2e244f | 9201 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9202 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
9203 | { |
9204 | struct drm_device *dev = crtc->base.dev; | |
9205 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a1b2278e CK |
9206 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
9207 | uint32_t ps_ctrl = 0; | |
9208 | int id = -1; | |
9209 | int i; | |
bd2e244f | 9210 | |
a1b2278e CK |
9211 | /* find scaler attached to this pipe */ |
9212 | for (i = 0; i < crtc->num_scalers; i++) { | |
9213 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9214 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9215 | id = i; | |
9216 | pipe_config->pch_pfit.enabled = true; | |
9217 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9218 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9219 | break; | |
9220 | } | |
9221 | } | |
bd2e244f | 9222 | |
a1b2278e CK |
9223 | scaler_state->scaler_id = id; |
9224 | if (id >= 0) { | |
9225 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9226 | } else { | |
9227 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9228 | } |
9229 | } | |
9230 | ||
5724dbd1 DL |
9231 | static void |
9232 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9233 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9234 | { |
9235 | struct drm_device *dev = crtc->base.dev; | |
9236 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 9237 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9238 | int pipe = crtc->pipe; |
9239 | int fourcc, pixel_format; | |
6761dd31 | 9240 | unsigned int aligned_height; |
bc8d7dff | 9241 | struct drm_framebuffer *fb; |
1b842c89 | 9242 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9243 | |
d9806c9f | 9244 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9245 | if (!intel_fb) { |
bc8d7dff DL |
9246 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9247 | return; | |
9248 | } | |
9249 | ||
1b842c89 DL |
9250 | fb = &intel_fb->base; |
9251 | ||
bc8d7dff | 9252 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9253 | if (!(val & PLANE_CTL_ENABLE)) |
9254 | goto error; | |
9255 | ||
bc8d7dff DL |
9256 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9257 | fourcc = skl_format_to_fourcc(pixel_format, | |
9258 | val & PLANE_CTL_ORDER_RGBX, | |
9259 | val & PLANE_CTL_ALPHA_MASK); | |
9260 | fb->pixel_format = fourcc; | |
9261 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9262 | ||
40f46283 DL |
9263 | tiling = val & PLANE_CTL_TILED_MASK; |
9264 | switch (tiling) { | |
9265 | case PLANE_CTL_TILED_LINEAR: | |
9266 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9267 | break; | |
9268 | case PLANE_CTL_TILED_X: | |
9269 | plane_config->tiling = I915_TILING_X; | |
9270 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9271 | break; | |
9272 | case PLANE_CTL_TILED_Y: | |
9273 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9274 | break; | |
9275 | case PLANE_CTL_TILED_YF: | |
9276 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9277 | break; | |
9278 | default: | |
9279 | MISSING_CASE(tiling); | |
9280 | goto error; | |
9281 | } | |
9282 | ||
bc8d7dff DL |
9283 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9284 | plane_config->base = base; | |
9285 | ||
9286 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9287 | ||
9288 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9289 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9290 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9291 | ||
9292 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
7b49f948 | 9293 | stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
40f46283 | 9294 | fb->pixel_format); |
bc8d7dff DL |
9295 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9296 | ||
9297 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9298 | fb->pixel_format, |
9299 | fb->modifier[0]); | |
bc8d7dff | 9300 | |
f37b5c2b | 9301 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9302 | |
9303 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9304 | pipe_name(pipe), fb->width, fb->height, | |
9305 | fb->bits_per_pixel, base, fb->pitches[0], | |
9306 | plane_config->size); | |
9307 | ||
2d14030b | 9308 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9309 | return; |
9310 | ||
9311 | error: | |
9312 | kfree(fb); | |
9313 | } | |
9314 | ||
2fa2fe9a | 9315 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9316 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9317 | { |
9318 | struct drm_device *dev = crtc->base.dev; | |
9319 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9320 | uint32_t tmp; | |
9321 | ||
9322 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9323 | ||
9324 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9325 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9326 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9327 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9328 | |
9329 | /* We currently do not free assignements of panel fitters on | |
9330 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9331 | * differentiates them) so just WARN about this case for now. */ | |
9332 | if (IS_GEN7(dev)) { | |
9333 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
9334 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9335 | } | |
2fa2fe9a | 9336 | } |
79e53945 JB |
9337 | } |
9338 | ||
5724dbd1 DL |
9339 | static void |
9340 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9341 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9342 | { |
9343 | struct drm_device *dev = crtc->base.dev; | |
9344 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9345 | u32 val, base, offset; | |
aeee5a49 | 9346 | int pipe = crtc->pipe; |
4c6baa59 | 9347 | int fourcc, pixel_format; |
6761dd31 | 9348 | unsigned int aligned_height; |
b113d5ee | 9349 | struct drm_framebuffer *fb; |
1b842c89 | 9350 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9351 | |
42a7b088 DL |
9352 | val = I915_READ(DSPCNTR(pipe)); |
9353 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9354 | return; | |
9355 | ||
d9806c9f | 9356 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9357 | if (!intel_fb) { |
4c6baa59 JB |
9358 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9359 | return; | |
9360 | } | |
9361 | ||
1b842c89 DL |
9362 | fb = &intel_fb->base; |
9363 | ||
18c5247e DV |
9364 | if (INTEL_INFO(dev)->gen >= 4) { |
9365 | if (val & DISPPLANE_TILED) { | |
49af449b | 9366 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9367 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9368 | } | |
9369 | } | |
4c6baa59 JB |
9370 | |
9371 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9372 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9373 | fb->pixel_format = fourcc; |
9374 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9375 | |
aeee5a49 | 9376 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 9377 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 9378 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9379 | } else { |
49af449b | 9380 | if (plane_config->tiling) |
aeee5a49 | 9381 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9382 | else |
aeee5a49 | 9383 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9384 | } |
9385 | plane_config->base = base; | |
9386 | ||
9387 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9388 | fb->width = ((val >> 16) & 0xfff) + 1; |
9389 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9390 | |
9391 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9392 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9393 | |
b113d5ee | 9394 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9395 | fb->pixel_format, |
9396 | fb->modifier[0]); | |
4c6baa59 | 9397 | |
f37b5c2b | 9398 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9399 | |
2844a921 DL |
9400 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9401 | pipe_name(pipe), fb->width, fb->height, | |
9402 | fb->bits_per_pixel, base, fb->pitches[0], | |
9403 | plane_config->size); | |
b113d5ee | 9404 | |
2d14030b | 9405 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9406 | } |
9407 | ||
0e8ffe1b | 9408 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9409 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9410 | { |
9411 | struct drm_device *dev = crtc->base.dev; | |
9412 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9413 | uint32_t tmp; | |
9414 | ||
f458ebbc DV |
9415 | if (!intel_display_power_is_enabled(dev_priv, |
9416 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
930e8c9e PZ |
9417 | return false; |
9418 | ||
e143a21c | 9419 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 9420 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 9421 | |
0e8ffe1b DV |
9422 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9423 | if (!(tmp & PIPECONF_ENABLE)) | |
9424 | return false; | |
9425 | ||
42571aef VS |
9426 | switch (tmp & PIPECONF_BPC_MASK) { |
9427 | case PIPECONF_6BPC: | |
9428 | pipe_config->pipe_bpp = 18; | |
9429 | break; | |
9430 | case PIPECONF_8BPC: | |
9431 | pipe_config->pipe_bpp = 24; | |
9432 | break; | |
9433 | case PIPECONF_10BPC: | |
9434 | pipe_config->pipe_bpp = 30; | |
9435 | break; | |
9436 | case PIPECONF_12BPC: | |
9437 | pipe_config->pipe_bpp = 36; | |
9438 | break; | |
9439 | default: | |
9440 | break; | |
9441 | } | |
9442 | ||
b5a9fa09 DV |
9443 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9444 | pipe_config->limited_color_range = true; | |
9445 | ||
ab9412ba | 9446 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
9447 | struct intel_shared_dpll *pll; |
9448 | ||
88adfff1 DV |
9449 | pipe_config->has_pch_encoder = true; |
9450 | ||
627eb5a3 DV |
9451 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9452 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9453 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9454 | |
9455 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9456 | |
c0d43d62 | 9457 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
9458 | pipe_config->shared_dpll = |
9459 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
9460 | } else { |
9461 | tmp = I915_READ(PCH_DPLL_SEL); | |
9462 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
9463 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
9464 | else | |
9465 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
9466 | } | |
66e985c0 DV |
9467 | |
9468 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9469 | ||
9470 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9471 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9472 | |
9473 | tmp = pipe_config->dpll_hw_state.dpll; | |
9474 | pipe_config->pixel_multiplier = | |
9475 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9476 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9477 | |
9478 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9479 | } else { |
9480 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9481 | } |
9482 | ||
1bd1bd80 DV |
9483 | intel_get_pipe_timings(crtc, pipe_config); |
9484 | ||
2fa2fe9a DV |
9485 | ironlake_get_pfit_config(crtc, pipe_config); |
9486 | ||
0e8ffe1b DV |
9487 | return true; |
9488 | } | |
9489 | ||
be256dc7 PZ |
9490 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9491 | { | |
9492 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 9493 | struct intel_crtc *crtc; |
be256dc7 | 9494 | |
d3fcc808 | 9495 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9496 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9497 | pipe_name(crtc->pipe)); |
9498 | ||
e2c719b7 RC |
9499 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9500 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
9501 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
9502 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
e2c719b7 RC |
9503 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
9504 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 9505 | "CPU PWM1 enabled\n"); |
c5107b87 | 9506 | if (IS_HASWELL(dev)) |
e2c719b7 | 9507 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 9508 | "CPU PWM2 enabled\n"); |
e2c719b7 | 9509 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 9510 | "PCH PWM1 enabled\n"); |
e2c719b7 | 9511 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 9512 | "Utility pin enabled\n"); |
e2c719b7 | 9513 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 9514 | |
9926ada1 PZ |
9515 | /* |
9516 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9517 | * interrupts remain enabled. We used to check for that, but since it's | |
9518 | * gen-specific and since we only disable LCPLL after we fully disable | |
9519 | * the interrupts, the check below should be enough. | |
9520 | */ | |
e2c719b7 | 9521 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
9522 | } |
9523 | ||
9ccd5aeb PZ |
9524 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
9525 | { | |
9526 | struct drm_device *dev = dev_priv->dev; | |
9527 | ||
9528 | if (IS_HASWELL(dev)) | |
9529 | return I915_READ(D_COMP_HSW); | |
9530 | else | |
9531 | return I915_READ(D_COMP_BDW); | |
9532 | } | |
9533 | ||
3c4c9b81 PZ |
9534 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
9535 | { | |
9536 | struct drm_device *dev = dev_priv->dev; | |
9537 | ||
9538 | if (IS_HASWELL(dev)) { | |
9539 | mutex_lock(&dev_priv->rps.hw_lock); | |
9540 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9541 | val)) | |
f475dadf | 9542 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
9543 | mutex_unlock(&dev_priv->rps.hw_lock); |
9544 | } else { | |
9ccd5aeb PZ |
9545 | I915_WRITE(D_COMP_BDW, val); |
9546 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 9547 | } |
be256dc7 PZ |
9548 | } |
9549 | ||
9550 | /* | |
9551 | * This function implements pieces of two sequences from BSpec: | |
9552 | * - Sequence for display software to disable LCPLL | |
9553 | * - Sequence for display software to allow package C8+ | |
9554 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9555 | * register. Callers should take care of disabling all the display engine | |
9556 | * functions, doing the mode unset, fixing interrupts, etc. | |
9557 | */ | |
6ff58d53 PZ |
9558 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9559 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9560 | { |
9561 | uint32_t val; | |
9562 | ||
9563 | assert_can_disable_lcpll(dev_priv); | |
9564 | ||
9565 | val = I915_READ(LCPLL_CTL); | |
9566 | ||
9567 | if (switch_to_fclk) { | |
9568 | val |= LCPLL_CD_SOURCE_FCLK; | |
9569 | I915_WRITE(LCPLL_CTL, val); | |
9570 | ||
9571 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9572 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9573 | DRM_ERROR("Switching to FCLK failed\n"); | |
9574 | ||
9575 | val = I915_READ(LCPLL_CTL); | |
9576 | } | |
9577 | ||
9578 | val |= LCPLL_PLL_DISABLE; | |
9579 | I915_WRITE(LCPLL_CTL, val); | |
9580 | POSTING_READ(LCPLL_CTL); | |
9581 | ||
9582 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
9583 | DRM_ERROR("LCPLL still locked\n"); | |
9584 | ||
9ccd5aeb | 9585 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9586 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9587 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9588 | ndelay(100); |
9589 | ||
9ccd5aeb PZ |
9590 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9591 | 1)) | |
be256dc7 PZ |
9592 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9593 | ||
9594 | if (allow_power_down) { | |
9595 | val = I915_READ(LCPLL_CTL); | |
9596 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9597 | I915_WRITE(LCPLL_CTL, val); | |
9598 | POSTING_READ(LCPLL_CTL); | |
9599 | } | |
9600 | } | |
9601 | ||
9602 | /* | |
9603 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9604 | * source. | |
9605 | */ | |
6ff58d53 | 9606 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9607 | { |
9608 | uint32_t val; | |
9609 | ||
9610 | val = I915_READ(LCPLL_CTL); | |
9611 | ||
9612 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9613 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9614 | return; | |
9615 | ||
a8a8bd54 PZ |
9616 | /* |
9617 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9618 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9619 | */ |
59bad947 | 9620 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9621 | |
be256dc7 PZ |
9622 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9623 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9624 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9625 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9626 | } |
9627 | ||
9ccd5aeb | 9628 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9629 | val |= D_COMP_COMP_FORCE; |
9630 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9631 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9632 | |
9633 | val = I915_READ(LCPLL_CTL); | |
9634 | val &= ~LCPLL_PLL_DISABLE; | |
9635 | I915_WRITE(LCPLL_CTL, val); | |
9636 | ||
9637 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
9638 | DRM_ERROR("LCPLL not locked yet\n"); | |
9639 | ||
9640 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9641 | val = I915_READ(LCPLL_CTL); | |
9642 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9643 | I915_WRITE(LCPLL_CTL, val); | |
9644 | ||
9645 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9646 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9647 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9648 | } | |
215733fa | 9649 | |
59bad947 | 9650 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b6283055 | 9651 | intel_update_cdclk(dev_priv->dev); |
be256dc7 PZ |
9652 | } |
9653 | ||
765dab67 PZ |
9654 | /* |
9655 | * Package states C8 and deeper are really deep PC states that can only be | |
9656 | * reached when all the devices on the system allow it, so even if the graphics | |
9657 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9658 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9659 | * | |
9660 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9661 | * well is disabled and most interrupts are disabled, and these are also | |
9662 | * requirements for runtime PM. When these conditions are met, we manually do | |
9663 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9664 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9665 | * hang the machine. | |
9666 | * | |
9667 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9668 | * the state of some registers, so when we come back from PC8+ we need to | |
9669 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9670 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9671 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9672 | * because of the runtime PM support). | |
9673 | * | |
9674 | * For more, read "Display Sequences for Package C8" on the hardware | |
9675 | * documentation. | |
9676 | */ | |
a14cb6fc | 9677 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9678 | { |
c67a470b PZ |
9679 | struct drm_device *dev = dev_priv->dev; |
9680 | uint32_t val; | |
9681 | ||
c67a470b PZ |
9682 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9683 | ||
c2699524 | 9684 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9685 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9686 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9687 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9688 | } | |
9689 | ||
9690 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9691 | hsw_disable_lcpll(dev_priv, true, true); |
9692 | } | |
9693 | ||
a14cb6fc | 9694 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
9695 | { |
9696 | struct drm_device *dev = dev_priv->dev; | |
9697 | uint32_t val; | |
9698 | ||
c67a470b PZ |
9699 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9700 | ||
9701 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9702 | lpt_init_pch_refclk(dev); |
9703 | ||
c2699524 | 9704 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9705 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9706 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9707 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9708 | } | |
c67a470b PZ |
9709 | } |
9710 | ||
27c329ed | 9711 | static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 9712 | { |
a821fc46 | 9713 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9714 | struct intel_atomic_state *old_intel_state = |
9715 | to_intel_atomic_state(old_state); | |
9716 | unsigned int req_cdclk = old_intel_state->dev_cdclk; | |
f8437dd1 | 9717 | |
27c329ed | 9718 | broxton_set_cdclk(dev, req_cdclk); |
f8437dd1 VK |
9719 | } |
9720 | ||
b432e5cf | 9721 | /* compute the max rate for new configuration */ |
27c329ed | 9722 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 9723 | { |
565602d7 ML |
9724 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
9725 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
9726 | struct drm_crtc *crtc; | |
9727 | struct drm_crtc_state *cstate; | |
27c329ed | 9728 | struct intel_crtc_state *crtc_state; |
565602d7 ML |
9729 | unsigned max_pixel_rate = 0, i; |
9730 | enum pipe pipe; | |
b432e5cf | 9731 | |
565602d7 ML |
9732 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
9733 | sizeof(intel_state->min_pixclk)); | |
27c329ed | 9734 | |
565602d7 ML |
9735 | for_each_crtc_in_state(state, crtc, cstate, i) { |
9736 | int pixel_rate; | |
27c329ed | 9737 | |
565602d7 ML |
9738 | crtc_state = to_intel_crtc_state(cstate); |
9739 | if (!crtc_state->base.enable) { | |
9740 | intel_state->min_pixclk[i] = 0; | |
b432e5cf | 9741 | continue; |
565602d7 | 9742 | } |
b432e5cf | 9743 | |
27c329ed | 9744 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf VS |
9745 | |
9746 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
565602d7 | 9747 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
b432e5cf VS |
9748 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
9749 | ||
565602d7 | 9750 | intel_state->min_pixclk[i] = pixel_rate; |
b432e5cf VS |
9751 | } |
9752 | ||
565602d7 ML |
9753 | if (!intel_state->active_crtcs) |
9754 | return 0; | |
9755 | ||
9756 | for_each_pipe(dev_priv, pipe) | |
9757 | max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate); | |
9758 | ||
b432e5cf VS |
9759 | return max_pixel_rate; |
9760 | } | |
9761 | ||
9762 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
9763 | { | |
9764 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9765 | uint32_t val, data; | |
9766 | int ret; | |
9767 | ||
9768 | if (WARN((I915_READ(LCPLL_CTL) & | |
9769 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
9770 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
9771 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
9772 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
9773 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
9774 | return; | |
9775 | ||
9776 | mutex_lock(&dev_priv->rps.hw_lock); | |
9777 | ret = sandybridge_pcode_write(dev_priv, | |
9778 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
9779 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9780 | if (ret) { | |
9781 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
9782 | return; | |
9783 | } | |
9784 | ||
9785 | val = I915_READ(LCPLL_CTL); | |
9786 | val |= LCPLL_CD_SOURCE_FCLK; | |
9787 | I915_WRITE(LCPLL_CTL, val); | |
9788 | ||
9789 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9790 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9791 | DRM_ERROR("Switching to FCLK failed\n"); | |
9792 | ||
9793 | val = I915_READ(LCPLL_CTL); | |
9794 | val &= ~LCPLL_CLK_FREQ_MASK; | |
9795 | ||
9796 | switch (cdclk) { | |
9797 | case 450000: | |
9798 | val |= LCPLL_CLK_FREQ_450; | |
9799 | data = 0; | |
9800 | break; | |
9801 | case 540000: | |
9802 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
9803 | data = 1; | |
9804 | break; | |
9805 | case 337500: | |
9806 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
9807 | data = 2; | |
9808 | break; | |
9809 | case 675000: | |
9810 | val |= LCPLL_CLK_FREQ_675_BDW; | |
9811 | data = 3; | |
9812 | break; | |
9813 | default: | |
9814 | WARN(1, "invalid cdclk frequency\n"); | |
9815 | return; | |
9816 | } | |
9817 | ||
9818 | I915_WRITE(LCPLL_CTL, val); | |
9819 | ||
9820 | val = I915_READ(LCPLL_CTL); | |
9821 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9822 | I915_WRITE(LCPLL_CTL, val); | |
9823 | ||
9824 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9825 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9826 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9827 | ||
9828 | mutex_lock(&dev_priv->rps.hw_lock); | |
9829 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
9830 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9831 | ||
9832 | intel_update_cdclk(dev); | |
9833 | ||
9834 | WARN(cdclk != dev_priv->cdclk_freq, | |
9835 | "cdclk requested %d kHz but got %d kHz\n", | |
9836 | cdclk, dev_priv->cdclk_freq); | |
9837 | } | |
9838 | ||
27c329ed | 9839 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 9840 | { |
27c329ed | 9841 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
1a617b77 | 9842 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
27c329ed | 9843 | int max_pixclk = ilk_max_pixel_rate(state); |
b432e5cf VS |
9844 | int cdclk; |
9845 | ||
9846 | /* | |
9847 | * FIXME should also account for plane ratio | |
9848 | * once 64bpp pixel formats are supported. | |
9849 | */ | |
27c329ed | 9850 | if (max_pixclk > 540000) |
b432e5cf | 9851 | cdclk = 675000; |
27c329ed | 9852 | else if (max_pixclk > 450000) |
b432e5cf | 9853 | cdclk = 540000; |
27c329ed | 9854 | else if (max_pixclk > 337500) |
b432e5cf VS |
9855 | cdclk = 450000; |
9856 | else | |
9857 | cdclk = 337500; | |
9858 | ||
b432e5cf | 9859 | if (cdclk > dev_priv->max_cdclk_freq) { |
63ba534e ML |
9860 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
9861 | cdclk, dev_priv->max_cdclk_freq); | |
9862 | return -EINVAL; | |
b432e5cf VS |
9863 | } |
9864 | ||
1a617b77 ML |
9865 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
9866 | if (!intel_state->active_crtcs) | |
9867 | intel_state->dev_cdclk = 337500; | |
b432e5cf VS |
9868 | |
9869 | return 0; | |
9870 | } | |
9871 | ||
27c329ed | 9872 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 9873 | { |
27c329ed | 9874 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9875 | struct intel_atomic_state *old_intel_state = |
9876 | to_intel_atomic_state(old_state); | |
9877 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
b432e5cf | 9878 | |
27c329ed | 9879 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
9880 | } |
9881 | ||
190f68c5 ACO |
9882 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9883 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9884 | { |
190f68c5 | 9885 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
6441ab5f | 9886 | return -EINVAL; |
716c2e55 | 9887 | |
c7653199 | 9888 | crtc->lowfreq_avail = false; |
644cef34 | 9889 | |
c8f7a0db | 9890 | return 0; |
79e53945 JB |
9891 | } |
9892 | ||
3760b59c S |
9893 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9894 | enum port port, | |
9895 | struct intel_crtc_state *pipe_config) | |
9896 | { | |
9897 | switch (port) { | |
9898 | case PORT_A: | |
9899 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
9900 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9901 | break; | |
9902 | case PORT_B: | |
9903 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
9904 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9905 | break; | |
9906 | case PORT_C: | |
9907 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
9908 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9909 | break; | |
9910 | default: | |
9911 | DRM_ERROR("Incorrect port type\n"); | |
9912 | } | |
9913 | } | |
9914 | ||
96b7dfb7 S |
9915 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9916 | enum port port, | |
5cec258b | 9917 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9918 | { |
3148ade7 | 9919 | u32 temp, dpll_ctl1; |
96b7dfb7 S |
9920 | |
9921 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9922 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9923 | ||
9924 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 DL |
9925 | case SKL_DPLL0: |
9926 | /* | |
9927 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part | |
9928 | * of the shared DPLL framework and thus needs to be read out | |
9929 | * separately | |
9930 | */ | |
9931 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
9932 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; | |
9933 | break; | |
96b7dfb7 S |
9934 | case SKL_DPLL1: |
9935 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9936 | break; | |
9937 | case SKL_DPLL2: | |
9938 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9939 | break; | |
9940 | case SKL_DPLL3: | |
9941 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9942 | break; | |
96b7dfb7 S |
9943 | } |
9944 | } | |
9945 | ||
7d2c8175 DL |
9946 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9947 | enum port port, | |
5cec258b | 9948 | struct intel_crtc_state *pipe_config) |
7d2c8175 DL |
9949 | { |
9950 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
9951 | ||
9952 | switch (pipe_config->ddi_pll_sel) { | |
9953 | case PORT_CLK_SEL_WRPLL1: | |
9954 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
9955 | break; | |
9956 | case PORT_CLK_SEL_WRPLL2: | |
9957 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
9958 | break; | |
00490c22 ML |
9959 | case PORT_CLK_SEL_SPLL: |
9960 | pipe_config->shared_dpll = DPLL_ID_SPLL; | |
79bd23da | 9961 | break; |
7d2c8175 DL |
9962 | } |
9963 | } | |
9964 | ||
26804afd | 9965 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9966 | struct intel_crtc_state *pipe_config) |
26804afd DV |
9967 | { |
9968 | struct drm_device *dev = crtc->base.dev; | |
9969 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 9970 | struct intel_shared_dpll *pll; |
26804afd DV |
9971 | enum port port; |
9972 | uint32_t tmp; | |
9973 | ||
9974 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9975 | ||
9976 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9977 | ||
ef11bdb3 | 9978 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
96b7dfb7 | 9979 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
3760b59c S |
9980 | else if (IS_BROXTON(dev)) |
9981 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
9982 | else |
9983 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9984 | |
d452c5b6 DV |
9985 | if (pipe_config->shared_dpll >= 0) { |
9986 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9987 | ||
9988 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9989 | &pipe_config->dpll_hw_state)); | |
9990 | } | |
9991 | ||
26804afd DV |
9992 | /* |
9993 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9994 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9995 | * the PCH transcoder is on. | |
9996 | */ | |
ca370455 DL |
9997 | if (INTEL_INFO(dev)->gen < 9 && |
9998 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
9999 | pipe_config->has_pch_encoder = true; |
10000 | ||
10001 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
10002 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
10003 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
10004 | ||
10005 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
10006 | } | |
10007 | } | |
10008 | ||
0e8ffe1b | 10009 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 10010 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
10011 | { |
10012 | struct drm_device *dev = crtc->base.dev; | |
10013 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 10014 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
10015 | uint32_t tmp; |
10016 | ||
f458ebbc | 10017 | if (!intel_display_power_is_enabled(dev_priv, |
b5482bd0 ID |
10018 | POWER_DOMAIN_PIPE(crtc->pipe))) |
10019 | return false; | |
10020 | ||
e143a21c | 10021 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
10022 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
10023 | ||
eccb140b DV |
10024 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
10025 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
10026 | enum pipe trans_edp_pipe; | |
10027 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
10028 | default: | |
10029 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
10030 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
10031 | case TRANS_DDI_EDP_INPUT_A_ON: | |
10032 | trans_edp_pipe = PIPE_A; | |
10033 | break; | |
10034 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
10035 | trans_edp_pipe = PIPE_B; | |
10036 | break; | |
10037 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
10038 | trans_edp_pipe = PIPE_C; | |
10039 | break; | |
10040 | } | |
10041 | ||
10042 | if (trans_edp_pipe == crtc->pipe) | |
10043 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
10044 | } | |
10045 | ||
f458ebbc | 10046 | if (!intel_display_power_is_enabled(dev_priv, |
eccb140b | 10047 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
10048 | return false; |
10049 | ||
eccb140b | 10050 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
10051 | if (!(tmp & PIPECONF_ENABLE)) |
10052 | return false; | |
10053 | ||
26804afd | 10054 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 10055 | |
1bd1bd80 DV |
10056 | intel_get_pipe_timings(crtc, pipe_config); |
10057 | ||
a1b2278e CK |
10058 | if (INTEL_INFO(dev)->gen >= 9) { |
10059 | skl_init_scalers(dev, crtc, pipe_config); | |
10060 | } | |
10061 | ||
2fa2fe9a | 10062 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
af99ceda CK |
10063 | |
10064 | if (INTEL_INFO(dev)->gen >= 9) { | |
10065 | pipe_config->scaler_state.scaler_id = -1; | |
10066 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
10067 | } | |
10068 | ||
bd2e244f | 10069 | if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { |
1c132b44 | 10070 | if (INTEL_INFO(dev)->gen >= 9) |
bd2e244f | 10071 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 10072 | else |
1c132b44 | 10073 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 10074 | } |
88adfff1 | 10075 | |
e59150dc JB |
10076 | if (IS_HASWELL(dev)) |
10077 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
10078 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 10079 | |
ebb69c95 CT |
10080 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
10081 | pipe_config->pixel_multiplier = | |
10082 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
10083 | } else { | |
10084 | pipe_config->pixel_multiplier = 1; | |
10085 | } | |
6c49f241 | 10086 | |
0e8ffe1b DV |
10087 | return true; |
10088 | } | |
10089 | ||
55a08b3f ML |
10090 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, |
10091 | const struct intel_plane_state *plane_state) | |
560b85bb CW |
10092 | { |
10093 | struct drm_device *dev = crtc->dev; | |
10094 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10095 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 10096 | uint32_t cntl = 0, size = 0; |
560b85bb | 10097 | |
55a08b3f ML |
10098 | if (plane_state && plane_state->visible) { |
10099 | unsigned int width = plane_state->base.crtc_w; | |
10100 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 VS |
10101 | unsigned int stride = roundup_pow_of_two(width) * 4; |
10102 | ||
10103 | switch (stride) { | |
10104 | default: | |
10105 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
10106 | width, stride); | |
10107 | stride = 256; | |
10108 | /* fallthrough */ | |
10109 | case 256: | |
10110 | case 512: | |
10111 | case 1024: | |
10112 | case 2048: | |
10113 | break; | |
4b0e333e CW |
10114 | } |
10115 | ||
dc41c154 VS |
10116 | cntl |= CURSOR_ENABLE | |
10117 | CURSOR_GAMMA_ENABLE | | |
10118 | CURSOR_FORMAT_ARGB | | |
10119 | CURSOR_STRIDE(stride); | |
10120 | ||
10121 | size = (height << 12) | width; | |
4b0e333e | 10122 | } |
560b85bb | 10123 | |
dc41c154 VS |
10124 | if (intel_crtc->cursor_cntl != 0 && |
10125 | (intel_crtc->cursor_base != base || | |
10126 | intel_crtc->cursor_size != size || | |
10127 | intel_crtc->cursor_cntl != cntl)) { | |
10128 | /* On these chipsets we can only modify the base/size/stride | |
10129 | * whilst the cursor is disabled. | |
10130 | */ | |
0b87c24e VS |
10131 | I915_WRITE(CURCNTR(PIPE_A), 0); |
10132 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 10133 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 10134 | } |
560b85bb | 10135 | |
99d1f387 | 10136 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 10137 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
10138 | intel_crtc->cursor_base = base; |
10139 | } | |
4726e0b0 | 10140 | |
dc41c154 VS |
10141 | if (intel_crtc->cursor_size != size) { |
10142 | I915_WRITE(CURSIZE, size); | |
10143 | intel_crtc->cursor_size = size; | |
4b0e333e | 10144 | } |
560b85bb | 10145 | |
4b0e333e | 10146 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
10147 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
10148 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 10149 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 10150 | } |
560b85bb CW |
10151 | } |
10152 | ||
55a08b3f ML |
10153 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, |
10154 | const struct intel_plane_state *plane_state) | |
65a21cd6 JB |
10155 | { |
10156 | struct drm_device *dev = crtc->dev; | |
10157 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10158 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10159 | int pipe = intel_crtc->pipe; | |
663f3122 | 10160 | uint32_t cntl = 0; |
4b0e333e | 10161 | |
55a08b3f | 10162 | if (plane_state && plane_state->visible) { |
4b0e333e | 10163 | cntl = MCURSOR_GAMMA_ENABLE; |
55a08b3f | 10164 | switch (plane_state->base.crtc_w) { |
4726e0b0 SK |
10165 | case 64: |
10166 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
10167 | break; | |
10168 | case 128: | |
10169 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
10170 | break; | |
10171 | case 256: | |
10172 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
10173 | break; | |
10174 | default: | |
55a08b3f | 10175 | MISSING_CASE(plane_state->base.crtc_w); |
4726e0b0 | 10176 | return; |
65a21cd6 | 10177 | } |
4b0e333e | 10178 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 10179 | |
fc6f93bc | 10180 | if (HAS_DDI(dev)) |
47bf17a7 | 10181 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
65a21cd6 | 10182 | |
55a08b3f ML |
10183 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) |
10184 | cntl |= CURSOR_ROTATE_180; | |
10185 | } | |
4398ad45 | 10186 | |
4b0e333e CW |
10187 | if (intel_crtc->cursor_cntl != cntl) { |
10188 | I915_WRITE(CURCNTR(pipe), cntl); | |
10189 | POSTING_READ(CURCNTR(pipe)); | |
10190 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 10191 | } |
4b0e333e | 10192 | |
65a21cd6 | 10193 | /* and commit changes on next vblank */ |
5efb3e28 VS |
10194 | I915_WRITE(CURBASE(pipe), base); |
10195 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
10196 | |
10197 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
10198 | } |
10199 | ||
cda4b7d3 | 10200 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f | 10201 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
55a08b3f | 10202 | const struct intel_plane_state *plane_state) |
cda4b7d3 CW |
10203 | { |
10204 | struct drm_device *dev = crtc->dev; | |
10205 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10206 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10207 | int pipe = intel_crtc->pipe; | |
55a08b3f ML |
10208 | u32 base = intel_crtc->cursor_addr; |
10209 | u32 pos = 0; | |
cda4b7d3 | 10210 | |
55a08b3f ML |
10211 | if (plane_state) { |
10212 | int x = plane_state->base.crtc_x; | |
10213 | int y = plane_state->base.crtc_y; | |
cda4b7d3 | 10214 | |
55a08b3f ML |
10215 | if (x < 0) { |
10216 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10217 | x = -x; | |
10218 | } | |
10219 | pos |= x << CURSOR_X_SHIFT; | |
cda4b7d3 | 10220 | |
55a08b3f ML |
10221 | if (y < 0) { |
10222 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10223 | y = -y; | |
10224 | } | |
10225 | pos |= y << CURSOR_Y_SHIFT; | |
10226 | ||
10227 | /* ILK+ do this automagically */ | |
10228 | if (HAS_GMCH_DISPLAY(dev) && | |
10229 | plane_state->base.rotation == BIT(DRM_ROTATE_180)) { | |
10230 | base += (plane_state->base.crtc_h * | |
10231 | plane_state->base.crtc_w - 1) * 4; | |
10232 | } | |
cda4b7d3 | 10233 | } |
cda4b7d3 | 10234 | |
5efb3e28 VS |
10235 | I915_WRITE(CURPOS(pipe), pos); |
10236 | ||
8ac54669 | 10237 | if (IS_845G(dev) || IS_I865G(dev)) |
55a08b3f | 10238 | i845_update_cursor(crtc, base, plane_state); |
5efb3e28 | 10239 | else |
55a08b3f | 10240 | i9xx_update_cursor(crtc, base, plane_state); |
cda4b7d3 CW |
10241 | } |
10242 | ||
dc41c154 VS |
10243 | static bool cursor_size_ok(struct drm_device *dev, |
10244 | uint32_t width, uint32_t height) | |
10245 | { | |
10246 | if (width == 0 || height == 0) | |
10247 | return false; | |
10248 | ||
10249 | /* | |
10250 | * 845g/865g are special in that they are only limited by | |
10251 | * the width of their cursors, the height is arbitrary up to | |
10252 | * the precision of the register. Everything else requires | |
10253 | * square cursors, limited to a few power-of-two sizes. | |
10254 | */ | |
10255 | if (IS_845G(dev) || IS_I865G(dev)) { | |
10256 | if ((width & 63) != 0) | |
10257 | return false; | |
10258 | ||
10259 | if (width > (IS_845G(dev) ? 64 : 512)) | |
10260 | return false; | |
10261 | ||
10262 | if (height > 1023) | |
10263 | return false; | |
10264 | } else { | |
10265 | switch (width | height) { | |
10266 | case 256: | |
10267 | case 128: | |
10268 | if (IS_GEN2(dev)) | |
10269 | return false; | |
10270 | case 64: | |
10271 | break; | |
10272 | default: | |
10273 | return false; | |
10274 | } | |
10275 | } | |
10276 | ||
10277 | return true; | |
10278 | } | |
10279 | ||
79e53945 | 10280 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 10281 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 10282 | { |
7203425a | 10283 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 10284 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 10285 | |
7203425a | 10286 | for (i = start; i < end; i++) { |
79e53945 JB |
10287 | intel_crtc->lut_r[i] = red[i] >> 8; |
10288 | intel_crtc->lut_g[i] = green[i] >> 8; | |
10289 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
10290 | } | |
10291 | ||
10292 | intel_crtc_load_lut(crtc); | |
10293 | } | |
10294 | ||
79e53945 JB |
10295 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10296 | static struct drm_display_mode load_detect_mode = { | |
10297 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10298 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10299 | }; | |
10300 | ||
a8bb6818 DV |
10301 | struct drm_framebuffer * |
10302 | __intel_framebuffer_create(struct drm_device *dev, | |
10303 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10304 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10305 | { |
10306 | struct intel_framebuffer *intel_fb; | |
10307 | int ret; | |
10308 | ||
10309 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 10310 | if (!intel_fb) |
d2dff872 | 10311 | return ERR_PTR(-ENOMEM); |
d2dff872 CW |
10312 | |
10313 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10314 | if (ret) |
10315 | goto err; | |
d2dff872 CW |
10316 | |
10317 | return &intel_fb->base; | |
dcb1394e | 10318 | |
dd4916c5 | 10319 | err: |
dd4916c5 | 10320 | kfree(intel_fb); |
dd4916c5 | 10321 | return ERR_PTR(ret); |
d2dff872 CW |
10322 | } |
10323 | ||
b5ea642a | 10324 | static struct drm_framebuffer * |
a8bb6818 DV |
10325 | intel_framebuffer_create(struct drm_device *dev, |
10326 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10327 | struct drm_i915_gem_object *obj) | |
10328 | { | |
10329 | struct drm_framebuffer *fb; | |
10330 | int ret; | |
10331 | ||
10332 | ret = i915_mutex_lock_interruptible(dev); | |
10333 | if (ret) | |
10334 | return ERR_PTR(ret); | |
10335 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10336 | mutex_unlock(&dev->struct_mutex); | |
10337 | ||
10338 | return fb; | |
10339 | } | |
10340 | ||
d2dff872 CW |
10341 | static u32 |
10342 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10343 | { | |
10344 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10345 | return ALIGN(pitch, 64); | |
10346 | } | |
10347 | ||
10348 | static u32 | |
10349 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10350 | { | |
10351 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 10352 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
10353 | } |
10354 | ||
10355 | static struct drm_framebuffer * | |
10356 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10357 | struct drm_display_mode *mode, | |
10358 | int depth, int bpp) | |
10359 | { | |
dcb1394e | 10360 | struct drm_framebuffer *fb; |
d2dff872 | 10361 | struct drm_i915_gem_object *obj; |
0fed39bd | 10362 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
10363 | |
10364 | obj = i915_gem_alloc_object(dev, | |
10365 | intel_framebuffer_size_for_mode(mode, bpp)); | |
10366 | if (obj == NULL) | |
10367 | return ERR_PTR(-ENOMEM); | |
10368 | ||
10369 | mode_cmd.width = mode->hdisplay; | |
10370 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
10371 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10372 | bpp); | |
5ca0c34a | 10373 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 10374 | |
dcb1394e LW |
10375 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
10376 | if (IS_ERR(fb)) | |
10377 | drm_gem_object_unreference_unlocked(&obj->base); | |
10378 | ||
10379 | return fb; | |
d2dff872 CW |
10380 | } |
10381 | ||
10382 | static struct drm_framebuffer * | |
10383 | mode_fits_in_fbdev(struct drm_device *dev, | |
10384 | struct drm_display_mode *mode) | |
10385 | { | |
0695726e | 10386 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
d2dff872 CW |
10387 | struct drm_i915_private *dev_priv = dev->dev_private; |
10388 | struct drm_i915_gem_object *obj; | |
10389 | struct drm_framebuffer *fb; | |
10390 | ||
4c0e5528 | 10391 | if (!dev_priv->fbdev) |
d2dff872 CW |
10392 | return NULL; |
10393 | ||
4c0e5528 | 10394 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
10395 | return NULL; |
10396 | ||
4c0e5528 DV |
10397 | obj = dev_priv->fbdev->fb->obj; |
10398 | BUG_ON(!obj); | |
10399 | ||
8bcd4553 | 10400 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
10401 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
10402 | fb->bits_per_pixel)) | |
d2dff872 CW |
10403 | return NULL; |
10404 | ||
01f2c773 | 10405 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
10406 | return NULL; |
10407 | ||
10408 | return fb; | |
4520f53a DV |
10409 | #else |
10410 | return NULL; | |
10411 | #endif | |
d2dff872 CW |
10412 | } |
10413 | ||
d3a40d1b ACO |
10414 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
10415 | struct drm_crtc *crtc, | |
10416 | struct drm_display_mode *mode, | |
10417 | struct drm_framebuffer *fb, | |
10418 | int x, int y) | |
10419 | { | |
10420 | struct drm_plane_state *plane_state; | |
10421 | int hdisplay, vdisplay; | |
10422 | int ret; | |
10423 | ||
10424 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
10425 | if (IS_ERR(plane_state)) | |
10426 | return PTR_ERR(plane_state); | |
10427 | ||
10428 | if (mode) | |
10429 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
10430 | else | |
10431 | hdisplay = vdisplay = 0; | |
10432 | ||
10433 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
10434 | if (ret) | |
10435 | return ret; | |
10436 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10437 | plane_state->crtc_x = 0; | |
10438 | plane_state->crtc_y = 0; | |
10439 | plane_state->crtc_w = hdisplay; | |
10440 | plane_state->crtc_h = vdisplay; | |
10441 | plane_state->src_x = x << 16; | |
10442 | plane_state->src_y = y << 16; | |
10443 | plane_state->src_w = hdisplay << 16; | |
10444 | plane_state->src_h = vdisplay << 16; | |
10445 | ||
10446 | return 0; | |
10447 | } | |
10448 | ||
d2434ab7 | 10449 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 10450 | struct drm_display_mode *mode, |
51fd371b RC |
10451 | struct intel_load_detect_pipe *old, |
10452 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
10453 | { |
10454 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
10455 | struct intel_encoder *intel_encoder = |
10456 | intel_attached_encoder(connector); | |
79e53945 | 10457 | struct drm_crtc *possible_crtc; |
4ef69c7a | 10458 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
10459 | struct drm_crtc *crtc = NULL; |
10460 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 10461 | struct drm_framebuffer *fb; |
51fd371b | 10462 | struct drm_mode_config *config = &dev->mode_config; |
83a57153 | 10463 | struct drm_atomic_state *state = NULL; |
944b0c76 | 10464 | struct drm_connector_state *connector_state; |
4be07317 | 10465 | struct intel_crtc_state *crtc_state; |
51fd371b | 10466 | int ret, i = -1; |
79e53945 | 10467 | |
d2dff872 | 10468 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10469 | connector->base.id, connector->name, |
8e329a03 | 10470 | encoder->base.id, encoder->name); |
d2dff872 | 10471 | |
51fd371b RC |
10472 | retry: |
10473 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
10474 | if (ret) | |
ad3c558f | 10475 | goto fail; |
6e9f798d | 10476 | |
79e53945 JB |
10477 | /* |
10478 | * Algorithm gets a little messy: | |
7a5e4805 | 10479 | * |
79e53945 JB |
10480 | * - if the connector already has an assigned crtc, use it (but make |
10481 | * sure it's on first) | |
7a5e4805 | 10482 | * |
79e53945 JB |
10483 | * - try to find the first unused crtc that can drive this connector, |
10484 | * and use that if we find one | |
79e53945 JB |
10485 | */ |
10486 | ||
10487 | /* See if we already have a CRTC for this connector */ | |
10488 | if (encoder->crtc) { | |
10489 | crtc = encoder->crtc; | |
8261b191 | 10490 | |
51fd371b | 10491 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 10492 | if (ret) |
ad3c558f | 10493 | goto fail; |
4d02e2de | 10494 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
51fd371b | 10495 | if (ret) |
ad3c558f | 10496 | goto fail; |
7b24056b | 10497 | |
24218aac | 10498 | old->dpms_mode = connector->dpms; |
8261b191 CW |
10499 | old->load_detect_temp = false; |
10500 | ||
10501 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
10502 | if (connector->dpms != DRM_MODE_DPMS_ON) |
10503 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 10504 | |
7173188d | 10505 | return true; |
79e53945 JB |
10506 | } |
10507 | ||
10508 | /* Find an unused one (if possible) */ | |
70e1e0ec | 10509 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
10510 | i++; |
10511 | if (!(encoder->possible_crtcs & (1 << i))) | |
10512 | continue; | |
83d65738 | 10513 | if (possible_crtc->state->enable) |
a459249c | 10514 | continue; |
a459249c VS |
10515 | |
10516 | crtc = possible_crtc; | |
10517 | break; | |
79e53945 JB |
10518 | } |
10519 | ||
10520 | /* | |
10521 | * If we didn't find an unused CRTC, don't use any. | |
10522 | */ | |
10523 | if (!crtc) { | |
7173188d | 10524 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 10525 | goto fail; |
79e53945 JB |
10526 | } |
10527 | ||
51fd371b RC |
10528 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
10529 | if (ret) | |
ad3c558f | 10530 | goto fail; |
4d02e2de DV |
10531 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
10532 | if (ret) | |
ad3c558f | 10533 | goto fail; |
79e53945 JB |
10534 | |
10535 | intel_crtc = to_intel_crtc(crtc); | |
24218aac | 10536 | old->dpms_mode = connector->dpms; |
8261b191 | 10537 | old->load_detect_temp = true; |
d2dff872 | 10538 | old->release_fb = NULL; |
79e53945 | 10539 | |
83a57153 ACO |
10540 | state = drm_atomic_state_alloc(dev); |
10541 | if (!state) | |
10542 | return false; | |
10543 | ||
10544 | state->acquire_ctx = ctx; | |
10545 | ||
944b0c76 ACO |
10546 | connector_state = drm_atomic_get_connector_state(state, connector); |
10547 | if (IS_ERR(connector_state)) { | |
10548 | ret = PTR_ERR(connector_state); | |
10549 | goto fail; | |
10550 | } | |
10551 | ||
10552 | connector_state->crtc = crtc; | |
10553 | connector_state->best_encoder = &intel_encoder->base; | |
10554 | ||
4be07317 ACO |
10555 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10556 | if (IS_ERR(crtc_state)) { | |
10557 | ret = PTR_ERR(crtc_state); | |
10558 | goto fail; | |
10559 | } | |
10560 | ||
49d6fa21 | 10561 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 10562 | |
6492711d CW |
10563 | if (!mode) |
10564 | mode = &load_detect_mode; | |
79e53945 | 10565 | |
d2dff872 CW |
10566 | /* We need a framebuffer large enough to accommodate all accesses |
10567 | * that the plane may generate whilst we perform load detection. | |
10568 | * We can not rely on the fbcon either being present (we get called | |
10569 | * during its initialisation to detect all boot displays, or it may | |
10570 | * not even exist) or that it is large enough to satisfy the | |
10571 | * requested mode. | |
10572 | */ | |
94352cf9 DV |
10573 | fb = mode_fits_in_fbdev(dev, mode); |
10574 | if (fb == NULL) { | |
d2dff872 | 10575 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
10576 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
10577 | old->release_fb = fb; | |
d2dff872 CW |
10578 | } else |
10579 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10580 | if (IS_ERR(fb)) { |
d2dff872 | 10581 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 10582 | goto fail; |
79e53945 | 10583 | } |
79e53945 | 10584 | |
d3a40d1b ACO |
10585 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10586 | if (ret) | |
10587 | goto fail; | |
10588 | ||
8c7b5ccb ACO |
10589 | drm_mode_copy(&crtc_state->base.mode, mode); |
10590 | ||
74c090b1 | 10591 | if (drm_atomic_commit(state)) { |
6492711d | 10592 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
10593 | if (old->release_fb) |
10594 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 10595 | goto fail; |
79e53945 | 10596 | } |
9128b040 | 10597 | crtc->primary->crtc = crtc; |
7173188d | 10598 | |
79e53945 | 10599 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 10600 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 10601 | return true; |
412b61d8 | 10602 | |
ad3c558f | 10603 | fail: |
e5d958ef ACO |
10604 | drm_atomic_state_free(state); |
10605 | state = NULL; | |
83a57153 | 10606 | |
51fd371b RC |
10607 | if (ret == -EDEADLK) { |
10608 | drm_modeset_backoff(ctx); | |
10609 | goto retry; | |
10610 | } | |
10611 | ||
412b61d8 | 10612 | return false; |
79e53945 JB |
10613 | } |
10614 | ||
d2434ab7 | 10615 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10616 | struct intel_load_detect_pipe *old, |
10617 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10618 | { |
83a57153 | 10619 | struct drm_device *dev = connector->dev; |
d2434ab7 DV |
10620 | struct intel_encoder *intel_encoder = |
10621 | intel_attached_encoder(connector); | |
4ef69c7a | 10622 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 10623 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 10624 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83a57153 | 10625 | struct drm_atomic_state *state; |
944b0c76 | 10626 | struct drm_connector_state *connector_state; |
4be07317 | 10627 | struct intel_crtc_state *crtc_state; |
d3a40d1b | 10628 | int ret; |
79e53945 | 10629 | |
d2dff872 | 10630 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10631 | connector->base.id, connector->name, |
8e329a03 | 10632 | encoder->base.id, encoder->name); |
d2dff872 | 10633 | |
8261b191 | 10634 | if (old->load_detect_temp) { |
83a57153 | 10635 | state = drm_atomic_state_alloc(dev); |
944b0c76 ACO |
10636 | if (!state) |
10637 | goto fail; | |
83a57153 ACO |
10638 | |
10639 | state->acquire_ctx = ctx; | |
10640 | ||
944b0c76 ACO |
10641 | connector_state = drm_atomic_get_connector_state(state, connector); |
10642 | if (IS_ERR(connector_state)) | |
10643 | goto fail; | |
10644 | ||
4be07317 ACO |
10645 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10646 | if (IS_ERR(crtc_state)) | |
10647 | goto fail; | |
10648 | ||
944b0c76 ACO |
10649 | connector_state->best_encoder = NULL; |
10650 | connector_state->crtc = NULL; | |
10651 | ||
49d6fa21 | 10652 | crtc_state->base.enable = crtc_state->base.active = false; |
4be07317 | 10653 | |
d3a40d1b ACO |
10654 | ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL, |
10655 | 0, 0); | |
10656 | if (ret) | |
10657 | goto fail; | |
10658 | ||
74c090b1 | 10659 | ret = drm_atomic_commit(state); |
2bfb4627 ACO |
10660 | if (ret) |
10661 | goto fail; | |
d2dff872 | 10662 | |
36206361 DV |
10663 | if (old->release_fb) { |
10664 | drm_framebuffer_unregister_private(old->release_fb); | |
10665 | drm_framebuffer_unreference(old->release_fb); | |
10666 | } | |
d2dff872 | 10667 | |
0622a53c | 10668 | return; |
79e53945 JB |
10669 | } |
10670 | ||
c751ce4f | 10671 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
10672 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
10673 | connector->funcs->dpms(connector, old->dpms_mode); | |
944b0c76 ACO |
10674 | |
10675 | return; | |
10676 | fail: | |
10677 | DRM_DEBUG_KMS("Couldn't release load detect pipe.\n"); | |
10678 | drm_atomic_state_free(state); | |
79e53945 JB |
10679 | } |
10680 | ||
da4a1efa | 10681 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10682 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
10683 | { |
10684 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10685 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
10686 | ||
10687 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10688 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
10689 | else if (HAS_PCH_SPLIT(dev)) |
10690 | return 120000; | |
10691 | else if (!IS_GEN2(dev)) | |
10692 | return 96000; | |
10693 | else | |
10694 | return 48000; | |
10695 | } | |
10696 | ||
79e53945 | 10697 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10698 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10699 | struct intel_crtc_state *pipe_config) |
79e53945 | 10700 | { |
f1f644dc | 10701 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 10702 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 10703 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10704 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
10705 | u32 fp; |
10706 | intel_clock_t clock; | |
dccbea3b | 10707 | int port_clock; |
da4a1efa | 10708 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10709 | |
10710 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10711 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10712 | else |
293623f7 | 10713 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10714 | |
10715 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10716 | if (IS_PINEVIEW(dev)) { |
10717 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10718 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10719 | } else { |
10720 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10721 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10722 | } | |
10723 | ||
a6c45cf0 | 10724 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10725 | if (IS_PINEVIEW(dev)) |
10726 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10727 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10728 | else |
10729 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10730 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10731 | ||
10732 | switch (dpll & DPLL_MODE_MASK) { | |
10733 | case DPLLB_MODE_DAC_SERIAL: | |
10734 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10735 | 5 : 10; | |
10736 | break; | |
10737 | case DPLLB_MODE_LVDS: | |
10738 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10739 | 7 : 14; | |
10740 | break; | |
10741 | default: | |
28c97730 | 10742 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10743 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10744 | return; |
79e53945 JB |
10745 | } |
10746 | ||
ac58c3f0 | 10747 | if (IS_PINEVIEW(dev)) |
dccbea3b | 10748 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 10749 | else |
dccbea3b | 10750 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 10751 | } else { |
0fb58223 | 10752 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10753 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10754 | |
10755 | if (is_lvds) { | |
10756 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10757 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10758 | |
10759 | if (lvds & LVDS_CLKB_POWER_UP) | |
10760 | clock.p2 = 7; | |
10761 | else | |
10762 | clock.p2 = 14; | |
79e53945 JB |
10763 | } else { |
10764 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10765 | clock.p1 = 2; | |
10766 | else { | |
10767 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10768 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10769 | } | |
10770 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10771 | clock.p2 = 4; | |
10772 | else | |
10773 | clock.p2 = 2; | |
79e53945 | 10774 | } |
da4a1efa | 10775 | |
dccbea3b | 10776 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
10777 | } |
10778 | ||
18442d08 VS |
10779 | /* |
10780 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10781 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10782 | * encoder's get_config() function. |
10783 | */ | |
dccbea3b | 10784 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
10785 | } |
10786 | ||
6878da05 VS |
10787 | int intel_dotclock_calculate(int link_freq, |
10788 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10789 | { |
f1f644dc JB |
10790 | /* |
10791 | * The calculation for the data clock is: | |
1041a02f | 10792 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10793 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10794 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10795 | * |
10796 | * and the link clock is simpler: | |
1041a02f | 10797 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10798 | */ |
10799 | ||
6878da05 VS |
10800 | if (!m_n->link_n) |
10801 | return 0; | |
f1f644dc | 10802 | |
6878da05 VS |
10803 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10804 | } | |
f1f644dc | 10805 | |
18442d08 | 10806 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10807 | struct intel_crtc_state *pipe_config) |
6878da05 VS |
10808 | { |
10809 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 10810 | |
18442d08 VS |
10811 | /* read out port_clock from the DPLL */ |
10812 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10813 | |
f1f644dc | 10814 | /* |
18442d08 | 10815 | * This value does not include pixel_multiplier. |
241bfc38 | 10816 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
10817 | * agree once we know their relationship in the encoder's |
10818 | * get_config() function. | |
79e53945 | 10819 | */ |
2d112de7 | 10820 | pipe_config->base.adjusted_mode.crtc_clock = |
18442d08 VS |
10821 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
10822 | &pipe_config->fdi_m_n); | |
79e53945 JB |
10823 | } |
10824 | ||
10825 | /** Returns the currently programmed mode of the given pipe. */ | |
10826 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10827 | struct drm_crtc *crtc) | |
10828 | { | |
548f245b | 10829 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 10830 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10831 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10832 | struct drm_display_mode *mode; |
5cec258b | 10833 | struct intel_crtc_state pipe_config; |
fe2b8f9d PZ |
10834 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10835 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10836 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10837 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10838 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10839 | |
10840 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10841 | if (!mode) | |
10842 | return NULL; | |
10843 | ||
f1f644dc JB |
10844 | /* |
10845 | * Construct a pipe_config sufficient for getting the clock info | |
10846 | * back out of crtc_clock_get. | |
10847 | * | |
10848 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10849 | * to use a real value here instead. | |
10850 | */ | |
293623f7 | 10851 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 10852 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
10853 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
10854 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10855 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
10856 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
10857 | ||
773ae034 | 10858 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
10859 | mode->hdisplay = (htot & 0xffff) + 1; |
10860 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10861 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10862 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10863 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10864 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10865 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10866 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10867 | ||
10868 | drm_mode_set_name(mode); | |
79e53945 JB |
10869 | |
10870 | return mode; | |
10871 | } | |
10872 | ||
f047e395 CW |
10873 | void intel_mark_busy(struct drm_device *dev) |
10874 | { | |
c67a470b PZ |
10875 | struct drm_i915_private *dev_priv = dev->dev_private; |
10876 | ||
f62a0076 CW |
10877 | if (dev_priv->mm.busy) |
10878 | return; | |
10879 | ||
43694d69 | 10880 | intel_runtime_pm_get(dev_priv); |
c67a470b | 10881 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
10882 | if (INTEL_INFO(dev)->gen >= 6) |
10883 | gen6_rps_busy(dev_priv); | |
f62a0076 | 10884 | dev_priv->mm.busy = true; |
f047e395 CW |
10885 | } |
10886 | ||
10887 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 10888 | { |
c67a470b | 10889 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10890 | |
f62a0076 CW |
10891 | if (!dev_priv->mm.busy) |
10892 | return; | |
10893 | ||
10894 | dev_priv->mm.busy = false; | |
10895 | ||
3d13ef2e | 10896 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 10897 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 | 10898 | |
43694d69 | 10899 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
10900 | } |
10901 | ||
79e53945 JB |
10902 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
10903 | { | |
10904 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
10905 | struct drm_device *dev = crtc->dev; |
10906 | struct intel_unpin_work *work; | |
67e77c5a | 10907 | |
5e2d7afc | 10908 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
10909 | work = intel_crtc->unpin_work; |
10910 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 10911 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
10912 | |
10913 | if (work) { | |
10914 | cancel_work_sync(&work->work); | |
10915 | kfree(work); | |
10916 | } | |
79e53945 JB |
10917 | |
10918 | drm_crtc_cleanup(crtc); | |
67e77c5a | 10919 | |
79e53945 JB |
10920 | kfree(intel_crtc); |
10921 | } | |
10922 | ||
6b95a207 KH |
10923 | static void intel_unpin_work_fn(struct work_struct *__work) |
10924 | { | |
10925 | struct intel_unpin_work *work = | |
10926 | container_of(__work, struct intel_unpin_work, work); | |
a9ff8714 VS |
10927 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
10928 | struct drm_device *dev = crtc->base.dev; | |
10929 | struct drm_plane *primary = crtc->base.primary; | |
6b95a207 | 10930 | |
b4a98e57 | 10931 | mutex_lock(&dev->struct_mutex); |
a9ff8714 | 10932 | intel_unpin_fb_obj(work->old_fb, primary->state); |
05394f39 | 10933 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 10934 | |
f06cc1b9 | 10935 | if (work->flip_queued_req) |
146d84f0 | 10936 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
10937 | mutex_unlock(&dev->struct_mutex); |
10938 | ||
a9ff8714 | 10939 | intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit); |
89ed88ba | 10940 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 10941 | |
a9ff8714 VS |
10942 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
10943 | atomic_dec(&crtc->unpin_work_count); | |
b4a98e57 | 10944 | |
6b95a207 KH |
10945 | kfree(work); |
10946 | } | |
10947 | ||
1afe3e9d | 10948 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 10949 | struct drm_crtc *crtc) |
6b95a207 | 10950 | { |
6b95a207 KH |
10951 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10952 | struct intel_unpin_work *work; | |
6b95a207 KH |
10953 | unsigned long flags; |
10954 | ||
10955 | /* Ignore early vblank irqs */ | |
10956 | if (intel_crtc == NULL) | |
10957 | return; | |
10958 | ||
f326038a DV |
10959 | /* |
10960 | * This is called both by irq handlers and the reset code (to complete | |
10961 | * lost pageflips) so needs the full irqsave spinlocks. | |
10962 | */ | |
6b95a207 KH |
10963 | spin_lock_irqsave(&dev->event_lock, flags); |
10964 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
10965 | |
10966 | /* Ensure we don't miss a work->pending update ... */ | |
10967 | smp_rmb(); | |
10968 | ||
10969 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
10970 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10971 | return; | |
10972 | } | |
10973 | ||
d6bbafa1 | 10974 | page_flip_completed(intel_crtc); |
0af7e4df | 10975 | |
6b95a207 | 10976 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
10977 | } |
10978 | ||
1afe3e9d JB |
10979 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
10980 | { | |
fbee40df | 10981 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10982 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
10983 | ||
49b14a5c | 10984 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10985 | } |
10986 | ||
10987 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
10988 | { | |
fbee40df | 10989 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10990 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
10991 | ||
49b14a5c | 10992 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10993 | } |
10994 | ||
75f7f3ec VS |
10995 | /* Is 'a' after or equal to 'b'? */ |
10996 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
10997 | { | |
10998 | return !((a - b) & 0x80000000); | |
10999 | } | |
11000 | ||
11001 | static bool page_flip_finished(struct intel_crtc *crtc) | |
11002 | { | |
11003 | struct drm_device *dev = crtc->base.dev; | |
11004 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11005 | ||
bdfa7542 VS |
11006 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
11007 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
11008 | return true; | |
11009 | ||
75f7f3ec VS |
11010 | /* |
11011 | * The relevant registers doen't exist on pre-ctg. | |
11012 | * As the flip done interrupt doesn't trigger for mmio | |
11013 | * flips on gmch platforms, a flip count check isn't | |
11014 | * really needed there. But since ctg has the registers, | |
11015 | * include it in the check anyway. | |
11016 | */ | |
11017 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
11018 | return true; | |
11019 | ||
11020 | /* | |
11021 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
11022 | * used the same base address. In that case the mmio flip might | |
11023 | * have completed, but the CS hasn't even executed the flip yet. | |
11024 | * | |
11025 | * A flip count check isn't enough as the CS might have updated | |
11026 | * the base address just after start of vblank, but before we | |
11027 | * managed to process the interrupt. This means we'd complete the | |
11028 | * CS flip too soon. | |
11029 | * | |
11030 | * Combining both checks should get us a good enough result. It may | |
11031 | * still happen that the CS flip has been executed, but has not | |
11032 | * yet actually completed. But in case the base address is the same | |
11033 | * anyway, we don't really care. | |
11034 | */ | |
11035 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
11036 | crtc->unpin_work->gtt_offset && | |
fd8f507c | 11037 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), |
75f7f3ec VS |
11038 | crtc->unpin_work->flip_count); |
11039 | } | |
11040 | ||
6b95a207 KH |
11041 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
11042 | { | |
fbee40df | 11043 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
11044 | struct intel_crtc *intel_crtc = |
11045 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
11046 | unsigned long flags; | |
11047 | ||
f326038a DV |
11048 | |
11049 | /* | |
11050 | * This is called both by irq handlers and the reset code (to complete | |
11051 | * lost pageflips) so needs the full irqsave spinlocks. | |
11052 | * | |
11053 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
11054 | * generate a page-flip completion irq, i.e. every modeset |
11055 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
11056 | */ | |
6b95a207 | 11057 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 11058 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 11059 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
11060 | spin_unlock_irqrestore(&dev->event_lock, flags); |
11061 | } | |
11062 | ||
6042639c | 11063 | static inline void intel_mark_page_flip_active(struct intel_unpin_work *work) |
e7d841ca CW |
11064 | { |
11065 | /* Ensure that the work item is consistent when activating it ... */ | |
11066 | smp_wmb(); | |
6042639c | 11067 | atomic_set(&work->pending, INTEL_FLIP_PENDING); |
e7d841ca CW |
11068 | /* and that it is marked active as soon as the irq could fire. */ |
11069 | smp_wmb(); | |
11070 | } | |
11071 | ||
8c9f3aaf JB |
11072 | static int intel_gen2_queue_flip(struct drm_device *dev, |
11073 | struct drm_crtc *crtc, | |
11074 | struct drm_framebuffer *fb, | |
ed8d1975 | 11075 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11076 | struct drm_i915_gem_request *req, |
ed8d1975 | 11077 | uint32_t flags) |
8c9f3aaf | 11078 | { |
6258fbe2 | 11079 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf | 11080 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
11081 | u32 flip_mask; |
11082 | int ret; | |
11083 | ||
5fb9de1a | 11084 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 11085 | if (ret) |
4fa62c89 | 11086 | return ret; |
8c9f3aaf JB |
11087 | |
11088 | /* Can't queue multiple flips, so wait for the previous | |
11089 | * one to finish before executing the next. | |
11090 | */ | |
11091 | if (intel_crtc->plane) | |
11092 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11093 | else | |
11094 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
11095 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11096 | intel_ring_emit(ring, MI_NOOP); | |
11097 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
11098 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11099 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11100 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 11101 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca | 11102 | |
6042639c | 11103 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11104 | return 0; |
8c9f3aaf JB |
11105 | } |
11106 | ||
11107 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
11108 | struct drm_crtc *crtc, | |
11109 | struct drm_framebuffer *fb, | |
ed8d1975 | 11110 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11111 | struct drm_i915_gem_request *req, |
ed8d1975 | 11112 | uint32_t flags) |
8c9f3aaf | 11113 | { |
6258fbe2 | 11114 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf | 11115 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
11116 | u32 flip_mask; |
11117 | int ret; | |
11118 | ||
5fb9de1a | 11119 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 11120 | if (ret) |
4fa62c89 | 11121 | return ret; |
8c9f3aaf JB |
11122 | |
11123 | if (intel_crtc->plane) | |
11124 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11125 | else | |
11126 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
11127 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11128 | intel_ring_emit(ring, MI_NOOP); | |
11129 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
11130 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11131 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11132 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
11133 | intel_ring_emit(ring, MI_NOOP); |
11134 | ||
6042639c | 11135 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11136 | return 0; |
8c9f3aaf JB |
11137 | } |
11138 | ||
11139 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
11140 | struct drm_crtc *crtc, | |
11141 | struct drm_framebuffer *fb, | |
ed8d1975 | 11142 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11143 | struct drm_i915_gem_request *req, |
ed8d1975 | 11144 | uint32_t flags) |
8c9f3aaf | 11145 | { |
6258fbe2 | 11146 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf JB |
11147 | struct drm_i915_private *dev_priv = dev->dev_private; |
11148 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11149 | uint32_t pf, pipesrc; | |
11150 | int ret; | |
11151 | ||
5fb9de1a | 11152 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11153 | if (ret) |
4fa62c89 | 11154 | return ret; |
8c9f3aaf JB |
11155 | |
11156 | /* i965+ uses the linear or tiled offsets from the | |
11157 | * Display Registers (which do not change across a page-flip) | |
11158 | * so we need only reprogram the base address. | |
11159 | */ | |
6d90c952 DV |
11160 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
11161 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11162 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11163 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 11164 | obj->tiling_mode); |
8c9f3aaf JB |
11165 | |
11166 | /* XXX Enabling the panel-fitter across page-flip is so far | |
11167 | * untested on non-native modes, so ignore it for now. | |
11168 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
11169 | */ | |
11170 | pf = 0; | |
11171 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 11172 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca | 11173 | |
6042639c | 11174 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11175 | return 0; |
8c9f3aaf JB |
11176 | } |
11177 | ||
11178 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
11179 | struct drm_crtc *crtc, | |
11180 | struct drm_framebuffer *fb, | |
ed8d1975 | 11181 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11182 | struct drm_i915_gem_request *req, |
ed8d1975 | 11183 | uint32_t flags) |
8c9f3aaf | 11184 | { |
6258fbe2 | 11185 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf JB |
11186 | struct drm_i915_private *dev_priv = dev->dev_private; |
11187 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11188 | uint32_t pf, pipesrc; | |
11189 | int ret; | |
11190 | ||
5fb9de1a | 11191 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11192 | if (ret) |
4fa62c89 | 11193 | return ret; |
8c9f3aaf | 11194 | |
6d90c952 DV |
11195 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
11196 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11197 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 11198 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 11199 | |
dc257cf1 DV |
11200 | /* Contrary to the suggestions in the documentation, |
11201 | * "Enable Panel Fitter" does not seem to be required when page | |
11202 | * flipping with a non-native mode, and worse causes a normal | |
11203 | * modeset to fail. | |
11204 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
11205 | */ | |
11206 | pf = 0; | |
8c9f3aaf | 11207 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 11208 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca | 11209 | |
6042639c | 11210 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11211 | return 0; |
8c9f3aaf JB |
11212 | } |
11213 | ||
7c9017e5 JB |
11214 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11215 | struct drm_crtc *crtc, | |
11216 | struct drm_framebuffer *fb, | |
ed8d1975 | 11217 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11218 | struct drm_i915_gem_request *req, |
ed8d1975 | 11219 | uint32_t flags) |
7c9017e5 | 11220 | { |
6258fbe2 | 11221 | struct intel_engine_cs *ring = req->ring; |
7c9017e5 | 11222 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 11223 | uint32_t plane_bit = 0; |
ffe74d75 CW |
11224 | int len, ret; |
11225 | ||
eba905b2 | 11226 | switch (intel_crtc->plane) { |
cb05d8de DV |
11227 | case PLANE_A: |
11228 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11229 | break; | |
11230 | case PLANE_B: | |
11231 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11232 | break; | |
11233 | case PLANE_C: | |
11234 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11235 | break; | |
11236 | default: | |
11237 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 11238 | return -ENODEV; |
cb05d8de DV |
11239 | } |
11240 | ||
ffe74d75 | 11241 | len = 4; |
f476828a | 11242 | if (ring->id == RCS) { |
ffe74d75 | 11243 | len += 6; |
f476828a DL |
11244 | /* |
11245 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11246 | * 48bits addresses, and we need a NOOP for the batch size to | |
11247 | * stay even. | |
11248 | */ | |
11249 | if (IS_GEN8(dev)) | |
11250 | len += 2; | |
11251 | } | |
ffe74d75 | 11252 | |
f66fab8e VS |
11253 | /* |
11254 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11255 | * "The full packet must be contained within the same cache line." | |
11256 | * | |
11257 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11258 | * cacheline, if we ever start emitting more commands before | |
11259 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11260 | * then do the cacheline alignment, and finally emit the | |
11261 | * MI_DISPLAY_FLIP. | |
11262 | */ | |
bba09b12 | 11263 | ret = intel_ring_cacheline_align(req); |
f66fab8e | 11264 | if (ret) |
4fa62c89 | 11265 | return ret; |
f66fab8e | 11266 | |
5fb9de1a | 11267 | ret = intel_ring_begin(req, len); |
7c9017e5 | 11268 | if (ret) |
4fa62c89 | 11269 | return ret; |
7c9017e5 | 11270 | |
ffe74d75 CW |
11271 | /* Unmask the flip-done completion message. Note that the bspec says that |
11272 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11273 | * more than one flip event at any time (or ensure that one flip message | |
11274 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11275 | * Experimentation says that BCS works despite DERRMR masking all | |
11276 | * flip-done completion events and that unmasking all planes at once | |
11277 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11278 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11279 | */ | |
11280 | if (ring->id == RCS) { | |
11281 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
f92a9162 | 11282 | intel_ring_emit_reg(ring, DERRMR); |
ffe74d75 CW |
11283 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | |
11284 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
11285 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a | 11286 | if (IS_GEN8(dev)) |
f1afe24f | 11287 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 | |
f476828a DL |
11288 | MI_SRM_LRM_GLOBAL_GTT); |
11289 | else | |
f1afe24f | 11290 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM | |
f476828a | 11291 | MI_SRM_LRM_GLOBAL_GTT); |
f92a9162 | 11292 | intel_ring_emit_reg(ring, DERRMR); |
ffe74d75 | 11293 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
f476828a DL |
11294 | if (IS_GEN8(dev)) { |
11295 | intel_ring_emit(ring, 0); | |
11296 | intel_ring_emit(ring, MI_NOOP); | |
11297 | } | |
ffe74d75 CW |
11298 | } |
11299 | ||
cb05d8de | 11300 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 11301 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 11302 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 11303 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca | 11304 | |
6042639c | 11305 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11306 | return 0; |
7c9017e5 JB |
11307 | } |
11308 | ||
84c33a64 SG |
11309 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
11310 | struct drm_i915_gem_object *obj) | |
11311 | { | |
11312 | /* | |
11313 | * This is not being used for older platforms, because | |
11314 | * non-availability of flip done interrupt forces us to use | |
11315 | * CS flips. Older platforms derive flip done using some clever | |
11316 | * tricks involving the flip_pending status bits and vblank irqs. | |
11317 | * So using MMIO flips there would disrupt this mechanism. | |
11318 | */ | |
11319 | ||
8e09bf83 CW |
11320 | if (ring == NULL) |
11321 | return true; | |
11322 | ||
84c33a64 SG |
11323 | if (INTEL_INFO(ring->dev)->gen < 5) |
11324 | return false; | |
11325 | ||
11326 | if (i915.use_mmio_flip < 0) | |
11327 | return false; | |
11328 | else if (i915.use_mmio_flip > 0) | |
11329 | return true; | |
14bf993e OM |
11330 | else if (i915.enable_execlists) |
11331 | return true; | |
fd8e058a AG |
11332 | else if (obj->base.dma_buf && |
11333 | !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv, | |
11334 | false)) | |
11335 | return true; | |
84c33a64 | 11336 | else |
b4716185 | 11337 | return ring != i915_gem_request_get_ring(obj->last_write_req); |
84c33a64 SG |
11338 | } |
11339 | ||
6042639c | 11340 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, |
86efe24a | 11341 | unsigned int rotation, |
6042639c | 11342 | struct intel_unpin_work *work) |
ff944564 DL |
11343 | { |
11344 | struct drm_device *dev = intel_crtc->base.dev; | |
11345 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11346 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
ff944564 | 11347 | const enum pipe pipe = intel_crtc->pipe; |
86efe24a | 11348 | u32 ctl, stride, tile_height; |
ff944564 DL |
11349 | |
11350 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
11351 | ctl &= ~PLANE_CTL_TILED_MASK; | |
2ebef630 TU |
11352 | switch (fb->modifier[0]) { |
11353 | case DRM_FORMAT_MOD_NONE: | |
11354 | break; | |
11355 | case I915_FORMAT_MOD_X_TILED: | |
ff944564 | 11356 | ctl |= PLANE_CTL_TILED_X; |
2ebef630 TU |
11357 | break; |
11358 | case I915_FORMAT_MOD_Y_TILED: | |
11359 | ctl |= PLANE_CTL_TILED_Y; | |
11360 | break; | |
11361 | case I915_FORMAT_MOD_Yf_TILED: | |
11362 | ctl |= PLANE_CTL_TILED_YF; | |
11363 | break; | |
11364 | default: | |
11365 | MISSING_CASE(fb->modifier[0]); | |
11366 | } | |
ff944564 DL |
11367 | |
11368 | /* | |
11369 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
11370 | * linear buffers or in number of tiles for tiled buffers. | |
11371 | */ | |
86efe24a TU |
11372 | if (intel_rotation_90_or_270(rotation)) { |
11373 | /* stride = Surface height in tiles */ | |
832be82f | 11374 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0); |
86efe24a TU |
11375 | stride = DIV_ROUND_UP(fb->height, tile_height); |
11376 | } else { | |
11377 | stride = fb->pitches[0] / | |
7b49f948 VS |
11378 | intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
11379 | fb->pixel_format); | |
86efe24a | 11380 | } |
ff944564 DL |
11381 | |
11382 | /* | |
11383 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
11384 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
11385 | */ | |
11386 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
11387 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
11388 | ||
6042639c | 11389 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); |
ff944564 DL |
11390 | POSTING_READ(PLANE_SURF(pipe, 0)); |
11391 | } | |
11392 | ||
6042639c CW |
11393 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, |
11394 | struct intel_unpin_work *work) | |
84c33a64 SG |
11395 | { |
11396 | struct drm_device *dev = intel_crtc->base.dev; | |
11397 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11398 | struct intel_framebuffer *intel_fb = | |
11399 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
11400 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
f0f59a00 | 11401 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); |
84c33a64 | 11402 | u32 dspcntr; |
84c33a64 | 11403 | |
84c33a64 SG |
11404 | dspcntr = I915_READ(reg); |
11405 | ||
c5d97472 DL |
11406 | if (obj->tiling_mode != I915_TILING_NONE) |
11407 | dspcntr |= DISPPLANE_TILED; | |
11408 | else | |
11409 | dspcntr &= ~DISPPLANE_TILED; | |
11410 | ||
84c33a64 SG |
11411 | I915_WRITE(reg, dspcntr); |
11412 | ||
6042639c | 11413 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); |
84c33a64 | 11414 | POSTING_READ(DSPSURF(intel_crtc->plane)); |
ff944564 DL |
11415 | } |
11416 | ||
11417 | /* | |
11418 | * XXX: This is the temporary way to update the plane registers until we get | |
11419 | * around to using the usual plane update functions for MMIO flips | |
11420 | */ | |
6042639c | 11421 | static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip) |
ff944564 | 11422 | { |
6042639c CW |
11423 | struct intel_crtc *crtc = mmio_flip->crtc; |
11424 | struct intel_unpin_work *work; | |
11425 | ||
11426 | spin_lock_irq(&crtc->base.dev->event_lock); | |
11427 | work = crtc->unpin_work; | |
11428 | spin_unlock_irq(&crtc->base.dev->event_lock); | |
11429 | if (work == NULL) | |
11430 | return; | |
ff944564 | 11431 | |
6042639c | 11432 | intel_mark_page_flip_active(work); |
ff944564 | 11433 | |
6042639c | 11434 | intel_pipe_update_start(crtc); |
ff944564 | 11435 | |
6042639c | 11436 | if (INTEL_INFO(mmio_flip->i915)->gen >= 9) |
86efe24a | 11437 | skl_do_mmio_flip(crtc, mmio_flip->rotation, work); |
ff944564 DL |
11438 | else |
11439 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
6042639c | 11440 | ilk_do_mmio_flip(crtc, work); |
ff944564 | 11441 | |
6042639c | 11442 | intel_pipe_update_end(crtc); |
84c33a64 SG |
11443 | } |
11444 | ||
9362c7c5 | 11445 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 11446 | { |
b2cfe0ab CW |
11447 | struct intel_mmio_flip *mmio_flip = |
11448 | container_of(work, struct intel_mmio_flip, work); | |
fd8e058a AG |
11449 | struct intel_framebuffer *intel_fb = |
11450 | to_intel_framebuffer(mmio_flip->crtc->base.primary->fb); | |
11451 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
84c33a64 | 11452 | |
6042639c | 11453 | if (mmio_flip->req) { |
eed29a5b | 11454 | WARN_ON(__i915_wait_request(mmio_flip->req, |
b2cfe0ab | 11455 | mmio_flip->crtc->reset_counter, |
bcafc4e3 CW |
11456 | false, NULL, |
11457 | &mmio_flip->i915->rps.mmioflips)); | |
6042639c CW |
11458 | i915_gem_request_unreference__unlocked(mmio_flip->req); |
11459 | } | |
84c33a64 | 11460 | |
fd8e058a AG |
11461 | /* For framebuffer backed by dmabuf, wait for fence */ |
11462 | if (obj->base.dma_buf) | |
11463 | WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
11464 | false, false, | |
11465 | MAX_SCHEDULE_TIMEOUT) < 0); | |
11466 | ||
6042639c | 11467 | intel_do_mmio_flip(mmio_flip); |
b2cfe0ab | 11468 | kfree(mmio_flip); |
84c33a64 SG |
11469 | } |
11470 | ||
11471 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
11472 | struct drm_crtc *crtc, | |
86efe24a | 11473 | struct drm_i915_gem_object *obj) |
84c33a64 | 11474 | { |
b2cfe0ab CW |
11475 | struct intel_mmio_flip *mmio_flip; |
11476 | ||
11477 | mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); | |
11478 | if (mmio_flip == NULL) | |
11479 | return -ENOMEM; | |
84c33a64 | 11480 | |
bcafc4e3 | 11481 | mmio_flip->i915 = to_i915(dev); |
eed29a5b | 11482 | mmio_flip->req = i915_gem_request_reference(obj->last_write_req); |
b2cfe0ab | 11483 | mmio_flip->crtc = to_intel_crtc(crtc); |
86efe24a | 11484 | mmio_flip->rotation = crtc->primary->state->rotation; |
536f5b5e | 11485 | |
b2cfe0ab CW |
11486 | INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); |
11487 | schedule_work(&mmio_flip->work); | |
84c33a64 | 11488 | |
84c33a64 SG |
11489 | return 0; |
11490 | } | |
11491 | ||
8c9f3aaf JB |
11492 | static int intel_default_queue_flip(struct drm_device *dev, |
11493 | struct drm_crtc *crtc, | |
11494 | struct drm_framebuffer *fb, | |
ed8d1975 | 11495 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11496 | struct drm_i915_gem_request *req, |
ed8d1975 | 11497 | uint32_t flags) |
8c9f3aaf JB |
11498 | { |
11499 | return -ENODEV; | |
11500 | } | |
11501 | ||
d6bbafa1 CW |
11502 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
11503 | struct drm_crtc *crtc) | |
11504 | { | |
11505 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11506 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11507 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
11508 | u32 addr; | |
11509 | ||
11510 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
11511 | return true; | |
11512 | ||
908565c2 CW |
11513 | if (atomic_read(&work->pending) < INTEL_FLIP_PENDING) |
11514 | return false; | |
11515 | ||
d6bbafa1 CW |
11516 | if (!work->enable_stall_check) |
11517 | return false; | |
11518 | ||
11519 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
11520 | if (work->flip_queued_req && |
11521 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
11522 | return false; |
11523 | ||
1e3feefd | 11524 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
11525 | } |
11526 | ||
1e3feefd | 11527 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
11528 | return false; |
11529 | ||
11530 | /* Potential stall - if we see that the flip has happened, | |
11531 | * assume a missed interrupt. */ | |
11532 | if (INTEL_INFO(dev)->gen >= 4) | |
11533 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
11534 | else | |
11535 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
11536 | ||
11537 | /* There is a potential issue here with a false positive after a flip | |
11538 | * to the same address. We could address this by checking for a | |
11539 | * non-incrementing frame counter. | |
11540 | */ | |
11541 | return addr == work->gtt_offset; | |
11542 | } | |
11543 | ||
11544 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
11545 | { | |
11546 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11547 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
11548 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6ad790c0 | 11549 | struct intel_unpin_work *work; |
f326038a | 11550 | |
6c51d46f | 11551 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
11552 | |
11553 | if (crtc == NULL) | |
11554 | return; | |
11555 | ||
f326038a | 11556 | spin_lock(&dev->event_lock); |
6ad790c0 CW |
11557 | work = intel_crtc->unpin_work; |
11558 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
d6bbafa1 | 11559 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
6ad790c0 | 11560 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
d6bbafa1 | 11561 | page_flip_completed(intel_crtc); |
6ad790c0 | 11562 | work = NULL; |
d6bbafa1 | 11563 | } |
6ad790c0 CW |
11564 | if (work != NULL && |
11565 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
11566 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); | |
f326038a | 11567 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
11568 | } |
11569 | ||
6b95a207 KH |
11570 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
11571 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
11572 | struct drm_pending_vblank_event *event, |
11573 | uint32_t page_flip_flags) | |
6b95a207 KH |
11574 | { |
11575 | struct drm_device *dev = crtc->dev; | |
11576 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 11577 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 11578 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 11579 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 11580 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 11581 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 11582 | struct intel_unpin_work *work; |
a4872ba6 | 11583 | struct intel_engine_cs *ring; |
cf5d8a46 | 11584 | bool mmio_flip; |
91af127f | 11585 | struct drm_i915_gem_request *request = NULL; |
52e68630 | 11586 | int ret; |
6b95a207 | 11587 | |
2ff8fde1 MR |
11588 | /* |
11589 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
11590 | * check to be safe. In the future we may enable pageflipping from | |
11591 | * a disabled primary plane. | |
11592 | */ | |
11593 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
11594 | return -EBUSY; | |
11595 | ||
e6a595d2 | 11596 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 11597 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
11598 | return -EINVAL; |
11599 | ||
11600 | /* | |
11601 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
11602 | * Note that pitch changes could also affect these register. | |
11603 | */ | |
11604 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
11605 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
11606 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
11607 | return -EINVAL; |
11608 | ||
f900db47 CW |
11609 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
11610 | goto out_hang; | |
11611 | ||
b14c5679 | 11612 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
11613 | if (work == NULL) |
11614 | return -ENOMEM; | |
11615 | ||
6b95a207 | 11616 | work->event = event; |
b4a98e57 | 11617 | work->crtc = crtc; |
ab8d6675 | 11618 | work->old_fb = old_fb; |
6b95a207 KH |
11619 | INIT_WORK(&work->work, intel_unpin_work_fn); |
11620 | ||
87b6b101 | 11621 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
11622 | if (ret) |
11623 | goto free_work; | |
11624 | ||
6b95a207 | 11625 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 11626 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 11627 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
11628 | /* Before declaring the flip queue wedged, check if |
11629 | * the hardware completed the operation behind our backs. | |
11630 | */ | |
11631 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
11632 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
11633 | page_flip_completed(intel_crtc); | |
11634 | } else { | |
11635 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 11636 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 11637 | |
d6bbafa1 CW |
11638 | drm_crtc_vblank_put(crtc); |
11639 | kfree(work); | |
11640 | return -EBUSY; | |
11641 | } | |
6b95a207 KH |
11642 | } |
11643 | intel_crtc->unpin_work = work; | |
5e2d7afc | 11644 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 11645 | |
b4a98e57 CW |
11646 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
11647 | flush_workqueue(dev_priv->wq); | |
11648 | ||
75dfca80 | 11649 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 11650 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 11651 | drm_gem_object_reference(&obj->base); |
6b95a207 | 11652 | |
f4510a27 | 11653 | crtc->primary->fb = fb; |
afd65eb4 | 11654 | update_state_fb(crtc->primary); |
1ed1f968 | 11655 | |
e1f99ce6 | 11656 | work->pending_flip_obj = obj; |
e1f99ce6 | 11657 | |
89ed88ba CW |
11658 | ret = i915_mutex_lock_interruptible(dev); |
11659 | if (ret) | |
11660 | goto cleanup; | |
11661 | ||
b4a98e57 | 11662 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 11663 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 11664 | |
75f7f3ec | 11665 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
fd8f507c | 11666 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
75f7f3ec | 11667 | |
666a4537 | 11668 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
4fa62c89 | 11669 | ring = &dev_priv->ring[BCS]; |
ab8d6675 | 11670 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 CW |
11671 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
11672 | ring = NULL; | |
48bf5b2d | 11673 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
2a92d5bc | 11674 | ring = &dev_priv->ring[BCS]; |
4fa62c89 | 11675 | } else if (INTEL_INFO(dev)->gen >= 7) { |
b4716185 | 11676 | ring = i915_gem_request_get_ring(obj->last_write_req); |
4fa62c89 VS |
11677 | if (ring == NULL || ring->id != RCS) |
11678 | ring = &dev_priv->ring[BCS]; | |
11679 | } else { | |
11680 | ring = &dev_priv->ring[RCS]; | |
11681 | } | |
11682 | ||
cf5d8a46 CW |
11683 | mmio_flip = use_mmio_flip(ring, obj); |
11684 | ||
11685 | /* When using CS flips, we want to emit semaphores between rings. | |
11686 | * However, when using mmio flips we will create a task to do the | |
11687 | * synchronisation, so all we want here is to pin the framebuffer | |
11688 | * into the display plane and skip any waits. | |
11689 | */ | |
7580d774 ML |
11690 | if (!mmio_flip) { |
11691 | ret = i915_gem_object_sync(obj, ring, &request); | |
11692 | if (ret) | |
11693 | goto cleanup_pending; | |
11694 | } | |
11695 | ||
82bc3b2d | 11696 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, |
7580d774 | 11697 | crtc->primary->state); |
8c9f3aaf JB |
11698 | if (ret) |
11699 | goto cleanup_pending; | |
6b95a207 | 11700 | |
dedf278c TU |
11701 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), |
11702 | obj, 0); | |
11703 | work->gtt_offset += intel_crtc->dspaddr_offset; | |
4fa62c89 | 11704 | |
cf5d8a46 | 11705 | if (mmio_flip) { |
86efe24a | 11706 | ret = intel_queue_mmio_flip(dev, crtc, obj); |
d6bbafa1 CW |
11707 | if (ret) |
11708 | goto cleanup_unpin; | |
11709 | ||
f06cc1b9 JH |
11710 | i915_gem_request_assign(&work->flip_queued_req, |
11711 | obj->last_write_req); | |
d6bbafa1 | 11712 | } else { |
6258fbe2 JH |
11713 | if (!request) { |
11714 | ret = i915_gem_request_alloc(ring, ring->default_context, &request); | |
11715 | if (ret) | |
11716 | goto cleanup_unpin; | |
11717 | } | |
11718 | ||
11719 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, | |
d6bbafa1 CW |
11720 | page_flip_flags); |
11721 | if (ret) | |
11722 | goto cleanup_unpin; | |
11723 | ||
6258fbe2 | 11724 | i915_gem_request_assign(&work->flip_queued_req, request); |
d6bbafa1 CW |
11725 | } |
11726 | ||
91af127f | 11727 | if (request) |
75289874 | 11728 | i915_add_request_no_flush(request); |
91af127f | 11729 | |
1e3feefd | 11730 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 11731 | work->enable_stall_check = true; |
4fa62c89 | 11732 | |
ab8d6675 | 11733 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a9ff8714 | 11734 | to_intel_plane(primary)->frontbuffer_bit); |
c80ac854 | 11735 | mutex_unlock(&dev->struct_mutex); |
a071fa00 | 11736 | |
d029bcad | 11737 | intel_fbc_deactivate(intel_crtc); |
a9ff8714 VS |
11738 | intel_frontbuffer_flip_prepare(dev, |
11739 | to_intel_plane(primary)->frontbuffer_bit); | |
6b95a207 | 11740 | |
e5510fac JB |
11741 | trace_i915_flip_request(intel_crtc->plane, obj); |
11742 | ||
6b95a207 | 11743 | return 0; |
96b099fd | 11744 | |
4fa62c89 | 11745 | cleanup_unpin: |
82bc3b2d | 11746 | intel_unpin_fb_obj(fb, crtc->primary->state); |
8c9f3aaf | 11747 | cleanup_pending: |
91af127f JH |
11748 | if (request) |
11749 | i915_gem_request_cancel(request); | |
b4a98e57 | 11750 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
11751 | mutex_unlock(&dev->struct_mutex); |
11752 | cleanup: | |
f4510a27 | 11753 | crtc->primary->fb = old_fb; |
afd65eb4 | 11754 | update_state_fb(crtc->primary); |
89ed88ba CW |
11755 | |
11756 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 11757 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 11758 | |
5e2d7afc | 11759 | spin_lock_irq(&dev->event_lock); |
96b099fd | 11760 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 11761 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 11762 | |
87b6b101 | 11763 | drm_crtc_vblank_put(crtc); |
7317c75e | 11764 | free_work: |
96b099fd CW |
11765 | kfree(work); |
11766 | ||
f900db47 | 11767 | if (ret == -EIO) { |
02e0efb5 ML |
11768 | struct drm_atomic_state *state; |
11769 | struct drm_plane_state *plane_state; | |
11770 | ||
f900db47 | 11771 | out_hang: |
02e0efb5 ML |
11772 | state = drm_atomic_state_alloc(dev); |
11773 | if (!state) | |
11774 | return -ENOMEM; | |
11775 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
11776 | ||
11777 | retry: | |
11778 | plane_state = drm_atomic_get_plane_state(state, primary); | |
11779 | ret = PTR_ERR_OR_ZERO(plane_state); | |
11780 | if (!ret) { | |
11781 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11782 | ||
11783 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
11784 | if (!ret) | |
11785 | ret = drm_atomic_commit(state); | |
11786 | } | |
11787 | ||
11788 | if (ret == -EDEADLK) { | |
11789 | drm_modeset_backoff(state->acquire_ctx); | |
11790 | drm_atomic_state_clear(state); | |
11791 | goto retry; | |
11792 | } | |
11793 | ||
11794 | if (ret) | |
11795 | drm_atomic_state_free(state); | |
11796 | ||
f0d3dad3 | 11797 | if (ret == 0 && event) { |
5e2d7afc | 11798 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 11799 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 11800 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 11801 | } |
f900db47 | 11802 | } |
96b099fd | 11803 | return ret; |
6b95a207 KH |
11804 | } |
11805 | ||
da20eabd ML |
11806 | |
11807 | /** | |
11808 | * intel_wm_need_update - Check whether watermarks need updating | |
11809 | * @plane: drm plane | |
11810 | * @state: new plane state | |
11811 | * | |
11812 | * Check current plane state versus the new one to determine whether | |
11813 | * watermarks need to be recalculated. | |
11814 | * | |
11815 | * Returns true or false. | |
11816 | */ | |
11817 | static bool intel_wm_need_update(struct drm_plane *plane, | |
11818 | struct drm_plane_state *state) | |
11819 | { | |
d21fbe87 MR |
11820 | struct intel_plane_state *new = to_intel_plane_state(state); |
11821 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
11822 | ||
11823 | /* Update watermarks on tiling or size changes. */ | |
92826fcd ML |
11824 | if (new->visible != cur->visible) |
11825 | return true; | |
11826 | ||
11827 | if (!cur->base.fb || !new->base.fb) | |
11828 | return false; | |
11829 | ||
11830 | if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] || | |
11831 | cur->base.rotation != new->base.rotation || | |
d21fbe87 MR |
11832 | drm_rect_width(&new->src) != drm_rect_width(&cur->src) || |
11833 | drm_rect_height(&new->src) != drm_rect_height(&cur->src) || | |
11834 | drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) || | |
11835 | drm_rect_height(&new->dst) != drm_rect_height(&cur->dst)) | |
2791a16c | 11836 | return true; |
7809e5ae | 11837 | |
2791a16c | 11838 | return false; |
7809e5ae MR |
11839 | } |
11840 | ||
d21fbe87 MR |
11841 | static bool needs_scaling(struct intel_plane_state *state) |
11842 | { | |
11843 | int src_w = drm_rect_width(&state->src) >> 16; | |
11844 | int src_h = drm_rect_height(&state->src) >> 16; | |
11845 | int dst_w = drm_rect_width(&state->dst); | |
11846 | int dst_h = drm_rect_height(&state->dst); | |
11847 | ||
11848 | return (src_w != dst_w || src_h != dst_h); | |
11849 | } | |
11850 | ||
da20eabd ML |
11851 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
11852 | struct drm_plane_state *plane_state) | |
11853 | { | |
ab1d3a0e | 11854 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
11855 | struct drm_crtc *crtc = crtc_state->crtc; |
11856 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11857 | struct drm_plane *plane = plane_state->plane; | |
11858 | struct drm_device *dev = crtc->dev; | |
11859 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11860 | struct intel_plane_state *old_plane_state = | |
11861 | to_intel_plane_state(plane->state); | |
11862 | int idx = intel_crtc->base.base.id, ret; | |
11863 | int i = drm_plane_index(plane); | |
11864 | bool mode_changed = needs_modeset(crtc_state); | |
11865 | bool was_crtc_enabled = crtc->state->active; | |
11866 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
11867 | bool turn_off, turn_on, visible, was_visible; |
11868 | struct drm_framebuffer *fb = plane_state->fb; | |
11869 | ||
11870 | if (crtc_state && INTEL_INFO(dev)->gen >= 9 && | |
11871 | plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11872 | ret = skl_update_scaler_plane( | |
11873 | to_intel_crtc_state(crtc_state), | |
11874 | to_intel_plane_state(plane_state)); | |
11875 | if (ret) | |
11876 | return ret; | |
11877 | } | |
11878 | ||
da20eabd ML |
11879 | was_visible = old_plane_state->visible; |
11880 | visible = to_intel_plane_state(plane_state)->visible; | |
11881 | ||
11882 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
11883 | was_visible = false; | |
11884 | ||
35c08f43 ML |
11885 | /* |
11886 | * Visibility is calculated as if the crtc was on, but | |
11887 | * after scaler setup everything depends on it being off | |
11888 | * when the crtc isn't active. | |
11889 | */ | |
11890 | if (!is_crtc_enabled) | |
11891 | to_intel_plane_state(plane_state)->visible = visible = false; | |
da20eabd ML |
11892 | |
11893 | if (!was_visible && !visible) | |
11894 | return 0; | |
11895 | ||
11896 | turn_off = was_visible && (!visible || mode_changed); | |
11897 | turn_on = visible && (!was_visible || mode_changed); | |
11898 | ||
11899 | DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx, | |
11900 | plane->base.id, fb ? fb->base.id : -1); | |
11901 | ||
11902 | DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n", | |
11903 | plane->base.id, was_visible, visible, | |
11904 | turn_off, turn_on, mode_changed); | |
11905 | ||
92826fcd ML |
11906 | if (turn_on || turn_off) { |
11907 | pipe_config->wm_changed = true; | |
11908 | ||
852eb00d VS |
11909 | /* must disable cxsr around plane enable/disable */ |
11910 | if (plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11911 | if (is_crtc_enabled) | |
11912 | intel_crtc->atomic.wait_vblank = true; | |
ab1d3a0e | 11913 | pipe_config->disable_cxsr = true; |
852eb00d VS |
11914 | } |
11915 | } else if (intel_wm_need_update(plane, plane_state)) { | |
92826fcd | 11916 | pipe_config->wm_changed = true; |
852eb00d | 11917 | } |
da20eabd | 11918 | |
396e33ae MR |
11919 | /* Pre-gen9 platforms need two-step watermark updates */ |
11920 | if (pipe_config->wm_changed && INTEL_INFO(dev)->gen < 9 && | |
11921 | dev_priv->display.optimize_watermarks) | |
11922 | to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true; | |
11923 | ||
8be6ca85 | 11924 | if (visible || was_visible) |
a9ff8714 VS |
11925 | intel_crtc->atomic.fb_bits |= |
11926 | to_intel_plane(plane)->frontbuffer_bit; | |
11927 | ||
da20eabd ML |
11928 | switch (plane->type) { |
11929 | case DRM_PLANE_TYPE_PRIMARY: | |
da20eabd ML |
11930 | intel_crtc->atomic.pre_disable_primary = turn_off; |
11931 | intel_crtc->atomic.post_enable_primary = turn_on; | |
11932 | ||
066cf55b RV |
11933 | if (turn_off) { |
11934 | /* | |
11935 | * FIXME: Actually if we will still have any other | |
11936 | * plane enabled on the pipe we could let IPS enabled | |
11937 | * still, but for now lets consider that when we make | |
11938 | * primary invisible by setting DSPCNTR to 0 on | |
11939 | * update_primary_plane function IPS needs to be | |
11940 | * disable. | |
11941 | */ | |
11942 | intel_crtc->atomic.disable_ips = true; | |
11943 | ||
da20eabd | 11944 | intel_crtc->atomic.disable_fbc = true; |
066cf55b | 11945 | } |
da20eabd ML |
11946 | |
11947 | /* | |
11948 | * FBC does not work on some platforms for rotated | |
11949 | * planes, so disable it when rotation is not 0 and | |
11950 | * update it when rotation is set back to 0. | |
11951 | * | |
11952 | * FIXME: This is redundant with the fbc update done in | |
11953 | * the primary plane enable function except that that | |
11954 | * one is done too late. We eventually need to unify | |
11955 | * this. | |
11956 | */ | |
11957 | ||
11958 | if (visible && | |
11959 | INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && | |
11960 | dev_priv->fbc.crtc == intel_crtc && | |
11961 | plane_state->rotation != BIT(DRM_ROTATE_0)) | |
11962 | intel_crtc->atomic.disable_fbc = true; | |
11963 | ||
11964 | /* | |
11965 | * BDW signals flip done immediately if the plane | |
11966 | * is disabled, even if the plane enable is already | |
11967 | * armed to occur at the next vblank :( | |
11968 | */ | |
11969 | if (turn_on && IS_BROADWELL(dev)) | |
11970 | intel_crtc->atomic.wait_vblank = true; | |
11971 | ||
11972 | intel_crtc->atomic.update_fbc |= visible || mode_changed; | |
11973 | break; | |
11974 | case DRM_PLANE_TYPE_CURSOR: | |
da20eabd ML |
11975 | break; |
11976 | case DRM_PLANE_TYPE_OVERLAY: | |
d21fbe87 MR |
11977 | /* |
11978 | * WaCxSRDisabledForSpriteScaling:ivb | |
11979 | * | |
11980 | * cstate->update_wm was already set above, so this flag will | |
11981 | * take effect when we commit and program watermarks. | |
11982 | */ | |
11983 | if (IS_IVYBRIDGE(dev) && | |
11984 | needs_scaling(to_intel_plane_state(plane_state)) && | |
11985 | !needs_scaling(old_plane_state)) { | |
11986 | to_intel_crtc_state(crtc_state)->disable_lp_wm = true; | |
11987 | } else if (turn_off && !mode_changed) { | |
da20eabd ML |
11988 | intel_crtc->atomic.wait_vblank = true; |
11989 | intel_crtc->atomic.update_sprite_watermarks |= | |
11990 | 1 << i; | |
11991 | } | |
d21fbe87 MR |
11992 | |
11993 | break; | |
da20eabd ML |
11994 | } |
11995 | return 0; | |
11996 | } | |
11997 | ||
6d3a1ce7 ML |
11998 | static bool encoders_cloneable(const struct intel_encoder *a, |
11999 | const struct intel_encoder *b) | |
12000 | { | |
12001 | /* masks could be asymmetric, so check both ways */ | |
12002 | return a == b || (a->cloneable & (1 << b->type) && | |
12003 | b->cloneable & (1 << a->type)); | |
12004 | } | |
12005 | ||
12006 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
12007 | struct intel_crtc *crtc, | |
12008 | struct intel_encoder *encoder) | |
12009 | { | |
12010 | struct intel_encoder *source_encoder; | |
12011 | struct drm_connector *connector; | |
12012 | struct drm_connector_state *connector_state; | |
12013 | int i; | |
12014 | ||
12015 | for_each_connector_in_state(state, connector, connector_state, i) { | |
12016 | if (connector_state->crtc != &crtc->base) | |
12017 | continue; | |
12018 | ||
12019 | source_encoder = | |
12020 | to_intel_encoder(connector_state->best_encoder); | |
12021 | if (!encoders_cloneable(encoder, source_encoder)) | |
12022 | return false; | |
12023 | } | |
12024 | ||
12025 | return true; | |
12026 | } | |
12027 | ||
12028 | static bool check_encoder_cloning(struct drm_atomic_state *state, | |
12029 | struct intel_crtc *crtc) | |
12030 | { | |
12031 | struct intel_encoder *encoder; | |
12032 | struct drm_connector *connector; | |
12033 | struct drm_connector_state *connector_state; | |
12034 | int i; | |
12035 | ||
12036 | for_each_connector_in_state(state, connector, connector_state, i) { | |
12037 | if (connector_state->crtc != &crtc->base) | |
12038 | continue; | |
12039 | ||
12040 | encoder = to_intel_encoder(connector_state->best_encoder); | |
12041 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
12042 | return false; | |
12043 | } | |
12044 | ||
12045 | return true; | |
12046 | } | |
12047 | ||
12048 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, | |
12049 | struct drm_crtc_state *crtc_state) | |
12050 | { | |
cf5a15be | 12051 | struct drm_device *dev = crtc->dev; |
ad421372 | 12052 | struct drm_i915_private *dev_priv = dev->dev_private; |
6d3a1ce7 | 12053 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
12054 | struct intel_crtc_state *pipe_config = |
12055 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 12056 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 12057 | int ret; |
6d3a1ce7 ML |
12058 | bool mode_changed = needs_modeset(crtc_state); |
12059 | ||
12060 | if (mode_changed && !check_encoder_cloning(state, intel_crtc)) { | |
12061 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
12062 | return -EINVAL; | |
12063 | } | |
12064 | ||
852eb00d | 12065 | if (mode_changed && !crtc_state->active) |
92826fcd | 12066 | pipe_config->wm_changed = true; |
eddfcbcd | 12067 | |
ad421372 ML |
12068 | if (mode_changed && crtc_state->enable && |
12069 | dev_priv->display.crtc_compute_clock && | |
12070 | !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) { | |
12071 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, | |
12072 | pipe_config); | |
12073 | if (ret) | |
12074 | return ret; | |
12075 | } | |
12076 | ||
e435d6e5 | 12077 | ret = 0; |
86c8bbbe MR |
12078 | if (dev_priv->display.compute_pipe_wm) { |
12079 | ret = dev_priv->display.compute_pipe_wm(intel_crtc, state); | |
396e33ae MR |
12080 | if (ret) { |
12081 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
12082 | return ret; | |
12083 | } | |
12084 | } | |
12085 | ||
12086 | if (dev_priv->display.compute_intermediate_wm && | |
12087 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
12088 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
12089 | return 0; | |
12090 | ||
12091 | /* | |
12092 | * Calculate 'intermediate' watermarks that satisfy both the | |
12093 | * old state and the new state. We can program these | |
12094 | * immediately. | |
12095 | */ | |
12096 | ret = dev_priv->display.compute_intermediate_wm(crtc->dev, | |
12097 | intel_crtc, | |
12098 | pipe_config); | |
12099 | if (ret) { | |
12100 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 12101 | return ret; |
396e33ae | 12102 | } |
86c8bbbe MR |
12103 | } |
12104 | ||
e435d6e5 ML |
12105 | if (INTEL_INFO(dev)->gen >= 9) { |
12106 | if (mode_changed) | |
12107 | ret = skl_update_scaler_crtc(pipe_config); | |
12108 | ||
12109 | if (!ret) | |
12110 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
12111 | pipe_config); | |
12112 | } | |
12113 | ||
12114 | return ret; | |
6d3a1ce7 ML |
12115 | } |
12116 | ||
65b38e0d | 12117 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
12118 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
12119 | .load_lut = intel_crtc_load_lut, | |
ea2c67bb MR |
12120 | .atomic_begin = intel_begin_crtc_commit, |
12121 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 12122 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
12123 | }; |
12124 | ||
d29b2f9d ACO |
12125 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
12126 | { | |
12127 | struct intel_connector *connector; | |
12128 | ||
12129 | for_each_intel_connector(dev, connector) { | |
12130 | if (connector->base.encoder) { | |
12131 | connector->base.state->best_encoder = | |
12132 | connector->base.encoder; | |
12133 | connector->base.state->crtc = | |
12134 | connector->base.encoder->crtc; | |
12135 | } else { | |
12136 | connector->base.state->best_encoder = NULL; | |
12137 | connector->base.state->crtc = NULL; | |
12138 | } | |
12139 | } | |
12140 | } | |
12141 | ||
050f7aeb | 12142 | static void |
eba905b2 | 12143 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 12144 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
12145 | { |
12146 | int bpp = pipe_config->pipe_bpp; | |
12147 | ||
12148 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
12149 | connector->base.base.id, | |
c23cc417 | 12150 | connector->base.name); |
050f7aeb DV |
12151 | |
12152 | /* Don't use an invalid EDID bpc value */ | |
12153 | if (connector->base.display_info.bpc && | |
12154 | connector->base.display_info.bpc * 3 < bpp) { | |
12155 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
12156 | bpp, connector->base.display_info.bpc*3); | |
12157 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
12158 | } | |
12159 | ||
013dd9e0 JN |
12160 | /* Clamp bpp to default limit on screens without EDID 1.4 */ |
12161 | if (connector->base.display_info.bpc == 0) { | |
12162 | int type = connector->base.connector_type; | |
12163 | int clamp_bpp = 24; | |
12164 | ||
12165 | /* Fall back to 18 bpp when DP sink capability is unknown. */ | |
12166 | if (type == DRM_MODE_CONNECTOR_DisplayPort || | |
12167 | type == DRM_MODE_CONNECTOR_eDP) | |
12168 | clamp_bpp = 18; | |
12169 | ||
12170 | if (bpp > clamp_bpp) { | |
12171 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n", | |
12172 | bpp, clamp_bpp); | |
12173 | pipe_config->pipe_bpp = clamp_bpp; | |
12174 | } | |
050f7aeb DV |
12175 | } |
12176 | } | |
12177 | ||
4e53c2e0 | 12178 | static int |
050f7aeb | 12179 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 12180 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 12181 | { |
050f7aeb | 12182 | struct drm_device *dev = crtc->base.dev; |
1486017f | 12183 | struct drm_atomic_state *state; |
da3ced29 ACO |
12184 | struct drm_connector *connector; |
12185 | struct drm_connector_state *connector_state; | |
1486017f | 12186 | int bpp, i; |
4e53c2e0 | 12187 | |
666a4537 | 12188 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) |
4e53c2e0 | 12189 | bpp = 10*3; |
d328c9d7 DV |
12190 | else if (INTEL_INFO(dev)->gen >= 5) |
12191 | bpp = 12*3; | |
12192 | else | |
12193 | bpp = 8*3; | |
12194 | ||
4e53c2e0 | 12195 | |
4e53c2e0 DV |
12196 | pipe_config->pipe_bpp = bpp; |
12197 | ||
1486017f ACO |
12198 | state = pipe_config->base.state; |
12199 | ||
4e53c2e0 | 12200 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
12201 | for_each_connector_in_state(state, connector, connector_state, i) { |
12202 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
12203 | continue; |
12204 | ||
da3ced29 ACO |
12205 | connected_sink_compute_bpp(to_intel_connector(connector), |
12206 | pipe_config); | |
4e53c2e0 DV |
12207 | } |
12208 | ||
12209 | return bpp; | |
12210 | } | |
12211 | ||
644db711 DV |
12212 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
12213 | { | |
12214 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
12215 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 12216 | mode->crtc_clock, |
644db711 DV |
12217 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
12218 | mode->crtc_hsync_end, mode->crtc_htotal, | |
12219 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
12220 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
12221 | } | |
12222 | ||
c0b03411 | 12223 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 12224 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
12225 | const char *context) |
12226 | { | |
6a60cd87 CK |
12227 | struct drm_device *dev = crtc->base.dev; |
12228 | struct drm_plane *plane; | |
12229 | struct intel_plane *intel_plane; | |
12230 | struct intel_plane_state *state; | |
12231 | struct drm_framebuffer *fb; | |
12232 | ||
12233 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
12234 | context, pipe_config, pipe_name(crtc->pipe)); | |
c0b03411 DV |
12235 | |
12236 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
12237 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
12238 | pipe_config->pipe_bpp, pipe_config->dither); | |
12239 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
12240 | pipe_config->has_pch_encoder, | |
12241 | pipe_config->fdi_lanes, | |
12242 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
12243 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
12244 | pipe_config->fdi_m_n.tu); | |
90a6b7b0 | 12245 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
eb14cb74 | 12246 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12247 | pipe_config->lane_count, |
eb14cb74 VS |
12248 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
12249 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
12250 | pipe_config->dp_m_n.tu); | |
b95af8be | 12251 | |
90a6b7b0 | 12252 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
b95af8be | 12253 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12254 | pipe_config->lane_count, |
b95af8be VK |
12255 | pipe_config->dp_m2_n2.gmch_m, |
12256 | pipe_config->dp_m2_n2.gmch_n, | |
12257 | pipe_config->dp_m2_n2.link_m, | |
12258 | pipe_config->dp_m2_n2.link_n, | |
12259 | pipe_config->dp_m2_n2.tu); | |
12260 | ||
55072d19 DV |
12261 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
12262 | pipe_config->has_audio, | |
12263 | pipe_config->has_infoframe); | |
12264 | ||
c0b03411 | 12265 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 12266 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 12267 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
12268 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
12269 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 12270 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
12271 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
12272 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
12273 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
12274 | crtc->num_scalers, | |
12275 | pipe_config->scaler_state.scaler_users, | |
12276 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
12277 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
12278 | pipe_config->gmch_pfit.control, | |
12279 | pipe_config->gmch_pfit.pgm_ratios, | |
12280 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 12281 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 12282 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
12283 | pipe_config->pch_pfit.size, |
12284 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 12285 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 12286 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 12287 | |
415ff0f6 | 12288 | if (IS_BROXTON(dev)) { |
05712c15 | 12289 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 12290 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 12291 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 TU |
12292 | pipe_config->ddi_pll_sel, |
12293 | pipe_config->dpll_hw_state.ebb0, | |
05712c15 | 12294 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
12295 | pipe_config->dpll_hw_state.pll0, |
12296 | pipe_config->dpll_hw_state.pll1, | |
12297 | pipe_config->dpll_hw_state.pll2, | |
12298 | pipe_config->dpll_hw_state.pll3, | |
12299 | pipe_config->dpll_hw_state.pll6, | |
12300 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 12301 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 12302 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 | 12303 | pipe_config->dpll_hw_state.pcsdw12); |
ef11bdb3 | 12304 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
415ff0f6 TU |
12305 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " |
12306 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
12307 | pipe_config->ddi_pll_sel, | |
12308 | pipe_config->dpll_hw_state.ctrl1, | |
12309 | pipe_config->dpll_hw_state.cfgcr1, | |
12310 | pipe_config->dpll_hw_state.cfgcr2); | |
12311 | } else if (HAS_DDI(dev)) { | |
00490c22 | 12312 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
415ff0f6 | 12313 | pipe_config->ddi_pll_sel, |
00490c22 ML |
12314 | pipe_config->dpll_hw_state.wrpll, |
12315 | pipe_config->dpll_hw_state.spll); | |
415ff0f6 TU |
12316 | } else { |
12317 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12318 | "fp0: 0x%x, fp1: 0x%x\n", | |
12319 | pipe_config->dpll_hw_state.dpll, | |
12320 | pipe_config->dpll_hw_state.dpll_md, | |
12321 | pipe_config->dpll_hw_state.fp0, | |
12322 | pipe_config->dpll_hw_state.fp1); | |
12323 | } | |
12324 | ||
6a60cd87 CK |
12325 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12326 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
12327 | intel_plane = to_intel_plane(plane); | |
12328 | if (intel_plane->pipe != crtc->pipe) | |
12329 | continue; | |
12330 | ||
12331 | state = to_intel_plane_state(plane->state); | |
12332 | fb = state->base.fb; | |
12333 | if (!fb) { | |
12334 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
12335 | "disabled, scaler_id = %d\n", | |
12336 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12337 | plane->base.id, intel_plane->pipe, | |
12338 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
12339 | drm_plane_index(plane), state->scaler_id); | |
12340 | continue; | |
12341 | } | |
12342 | ||
12343 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
12344 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12345 | plane->base.id, intel_plane->pipe, | |
12346 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
12347 | drm_plane_index(plane)); | |
12348 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
12349 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
12350 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
12351 | state->scaler_id, | |
12352 | state->src.x1 >> 16, state->src.y1 >> 16, | |
12353 | drm_rect_width(&state->src) >> 16, | |
12354 | drm_rect_height(&state->src) >> 16, | |
12355 | state->dst.x1, state->dst.y1, | |
12356 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
12357 | } | |
c0b03411 DV |
12358 | } |
12359 | ||
5448a00d | 12360 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12361 | { |
5448a00d | 12362 | struct drm_device *dev = state->dev; |
da3ced29 | 12363 | struct drm_connector *connector; |
00f0b378 VS |
12364 | unsigned int used_ports = 0; |
12365 | ||
12366 | /* | |
12367 | * Walk the connector list instead of the encoder | |
12368 | * list to detect the problem on ddi platforms | |
12369 | * where there's just one encoder per digital port. | |
12370 | */ | |
0bff4858 VS |
12371 | drm_for_each_connector(connector, dev) { |
12372 | struct drm_connector_state *connector_state; | |
12373 | struct intel_encoder *encoder; | |
12374 | ||
12375 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
12376 | if (!connector_state) | |
12377 | connector_state = connector->state; | |
12378 | ||
5448a00d | 12379 | if (!connector_state->best_encoder) |
00f0b378 VS |
12380 | continue; |
12381 | ||
5448a00d ACO |
12382 | encoder = to_intel_encoder(connector_state->best_encoder); |
12383 | ||
12384 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12385 | |
12386 | switch (encoder->type) { | |
12387 | unsigned int port_mask; | |
12388 | case INTEL_OUTPUT_UNKNOWN: | |
12389 | if (WARN_ON(!HAS_DDI(dev))) | |
12390 | break; | |
12391 | case INTEL_OUTPUT_DISPLAYPORT: | |
12392 | case INTEL_OUTPUT_HDMI: | |
12393 | case INTEL_OUTPUT_EDP: | |
12394 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12395 | ||
12396 | /* the same port mustn't appear more than once */ | |
12397 | if (used_ports & port_mask) | |
12398 | return false; | |
12399 | ||
12400 | used_ports |= port_mask; | |
12401 | default: | |
12402 | break; | |
12403 | } | |
12404 | } | |
12405 | ||
12406 | return true; | |
12407 | } | |
12408 | ||
83a57153 ACO |
12409 | static void |
12410 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12411 | { | |
12412 | struct drm_crtc_state tmp_state; | |
663a3640 | 12413 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 ACO |
12414 | struct intel_dpll_hw_state dpll_hw_state; |
12415 | enum intel_dpll_id shared_dpll; | |
8504c74c | 12416 | uint32_t ddi_pll_sel; |
c4e2d043 | 12417 | bool force_thru; |
83a57153 | 12418 | |
7546a384 ACO |
12419 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12420 | * kzalloc'd. Code that depends on any field being zero should be | |
12421 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12422 | * only fields that are know to not cause problems are preserved. */ | |
12423 | ||
83a57153 | 12424 | tmp_state = crtc_state->base; |
663a3640 | 12425 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12426 | shared_dpll = crtc_state->shared_dpll; |
12427 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 12428 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
c4e2d043 | 12429 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 12430 | |
83a57153 | 12431 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12432 | |
83a57153 | 12433 | crtc_state->base = tmp_state; |
663a3640 | 12434 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12435 | crtc_state->shared_dpll = shared_dpll; |
12436 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 12437 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
c4e2d043 | 12438 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
12439 | } |
12440 | ||
548ee15b | 12441 | static int |
b8cecdf5 | 12442 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12443 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12444 | { |
b359283a | 12445 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12446 | struct intel_encoder *encoder; |
da3ced29 | 12447 | struct drm_connector *connector; |
0b901879 | 12448 | struct drm_connector_state *connector_state; |
d328c9d7 | 12449 | int base_bpp, ret = -EINVAL; |
0b901879 | 12450 | int i; |
e29c22c0 | 12451 | bool retry = true; |
ee7b9f93 | 12452 | |
83a57153 | 12453 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12454 | |
e143a21c DV |
12455 | pipe_config->cpu_transcoder = |
12456 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12457 | |
2960bc9c ID |
12458 | /* |
12459 | * Sanitize sync polarity flags based on requested ones. If neither | |
12460 | * positive or negative polarity is requested, treat this as meaning | |
12461 | * negative polarity. | |
12462 | */ | |
2d112de7 | 12463 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12464 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12465 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 12466 | |
2d112de7 | 12467 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12468 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 12469 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 12470 | |
d328c9d7 DV |
12471 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
12472 | pipe_config); | |
12473 | if (base_bpp < 0) | |
4e53c2e0 DV |
12474 | goto fail; |
12475 | ||
e41a56be VS |
12476 | /* |
12477 | * Determine the real pipe dimensions. Note that stereo modes can | |
12478 | * increase the actual pipe size due to the frame doubling and | |
12479 | * insertion of additional space for blanks between the frame. This | |
12480 | * is stored in the crtc timings. We use the requested mode to do this | |
12481 | * computation to clearly distinguish it from the adjusted mode, which | |
12482 | * can be changed by the connectors in the below retry loop. | |
12483 | */ | |
2d112de7 | 12484 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
12485 | &pipe_config->pipe_src_w, |
12486 | &pipe_config->pipe_src_h); | |
e41a56be | 12487 | |
e29c22c0 | 12488 | encoder_retry: |
ef1b460d | 12489 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 12490 | pipe_config->port_clock = 0; |
ef1b460d | 12491 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 12492 | |
135c81b8 | 12493 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
12494 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
12495 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 12496 | |
7758a113 DV |
12497 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
12498 | * adjust it according to limitations or connector properties, and also | |
12499 | * a chance to reject the mode entirely. | |
47f1c6c9 | 12500 | */ |
da3ced29 | 12501 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 12502 | if (connector_state->crtc != crtc) |
7758a113 | 12503 | continue; |
7ae89233 | 12504 | |
0b901879 ACO |
12505 | encoder = to_intel_encoder(connector_state->best_encoder); |
12506 | ||
efea6e8e DV |
12507 | if (!(encoder->compute_config(encoder, pipe_config))) { |
12508 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
12509 | goto fail; |
12510 | } | |
ee7b9f93 | 12511 | } |
47f1c6c9 | 12512 | |
ff9a6750 DV |
12513 | /* Set default port clock if not overwritten by the encoder. Needs to be |
12514 | * done afterwards in case the encoder adjusts the mode. */ | |
12515 | if (!pipe_config->port_clock) | |
2d112de7 | 12516 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 12517 | * pipe_config->pixel_multiplier; |
ff9a6750 | 12518 | |
a43f6e0f | 12519 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 12520 | if (ret < 0) { |
7758a113 DV |
12521 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
12522 | goto fail; | |
ee7b9f93 | 12523 | } |
e29c22c0 DV |
12524 | |
12525 | if (ret == RETRY) { | |
12526 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
12527 | ret = -EINVAL; | |
12528 | goto fail; | |
12529 | } | |
12530 | ||
12531 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
12532 | retry = false; | |
12533 | goto encoder_retry; | |
12534 | } | |
12535 | ||
e8fa4270 DV |
12536 | /* Dithering seems to not pass-through bits correctly when it should, so |
12537 | * only enable it on 6bpc panels. */ | |
12538 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 12539 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 12540 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 12541 | |
7758a113 | 12542 | fail: |
548ee15b | 12543 | return ret; |
ee7b9f93 | 12544 | } |
47f1c6c9 | 12545 | |
ea9d758d | 12546 | static void |
4740b0f2 | 12547 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 12548 | { |
0a9ab303 ACO |
12549 | struct drm_crtc *crtc; |
12550 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 12551 | int i; |
ea9d758d | 12552 | |
7668851f | 12553 | /* Double check state. */ |
8a75d157 | 12554 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 12555 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
12556 | |
12557 | /* Update hwmode for vblank functions */ | |
12558 | if (crtc->state->active) | |
12559 | crtc->hwmode = crtc->state->adjusted_mode; | |
12560 | else | |
12561 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
12562 | |
12563 | /* | |
12564 | * Update legacy state to satisfy fbc code. This can | |
12565 | * be removed when fbc uses the atomic state. | |
12566 | */ | |
12567 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12568 | struct drm_plane_state *plane_state = crtc->primary->state; | |
12569 | ||
12570 | crtc->primary->fb = plane_state->fb; | |
12571 | crtc->x = plane_state->src_x >> 16; | |
12572 | crtc->y = plane_state->src_y >> 16; | |
12573 | } | |
ea9d758d | 12574 | } |
ea9d758d DV |
12575 | } |
12576 | ||
3bd26263 | 12577 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 12578 | { |
3bd26263 | 12579 | int diff; |
f1f644dc JB |
12580 | |
12581 | if (clock1 == clock2) | |
12582 | return true; | |
12583 | ||
12584 | if (!clock1 || !clock2) | |
12585 | return false; | |
12586 | ||
12587 | diff = abs(clock1 - clock2); | |
12588 | ||
12589 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
12590 | return true; | |
12591 | ||
12592 | return false; | |
12593 | } | |
12594 | ||
25c5b266 DV |
12595 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
12596 | list_for_each_entry((intel_crtc), \ | |
12597 | &(dev)->mode_config.crtc_list, \ | |
12598 | base.head) \ | |
95150bdf | 12599 | for_each_if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 12600 | |
cfb23ed6 ML |
12601 | static bool |
12602 | intel_compare_m_n(unsigned int m, unsigned int n, | |
12603 | unsigned int m2, unsigned int n2, | |
12604 | bool exact) | |
12605 | { | |
12606 | if (m == m2 && n == n2) | |
12607 | return true; | |
12608 | ||
12609 | if (exact || !m || !n || !m2 || !n2) | |
12610 | return false; | |
12611 | ||
12612 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
12613 | ||
31d10b57 ML |
12614 | if (n > n2) { |
12615 | while (n > n2) { | |
cfb23ed6 ML |
12616 | m2 <<= 1; |
12617 | n2 <<= 1; | |
12618 | } | |
31d10b57 ML |
12619 | } else if (n < n2) { |
12620 | while (n < n2) { | |
cfb23ed6 ML |
12621 | m <<= 1; |
12622 | n <<= 1; | |
12623 | } | |
12624 | } | |
12625 | ||
31d10b57 ML |
12626 | if (n != n2) |
12627 | return false; | |
12628 | ||
12629 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
12630 | } |
12631 | ||
12632 | static bool | |
12633 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
12634 | struct intel_link_m_n *m2_n2, | |
12635 | bool adjust) | |
12636 | { | |
12637 | if (m_n->tu == m2_n2->tu && | |
12638 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
12639 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
12640 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
12641 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
12642 | if (adjust) | |
12643 | *m2_n2 = *m_n; | |
12644 | ||
12645 | return true; | |
12646 | } | |
12647 | ||
12648 | return false; | |
12649 | } | |
12650 | ||
0e8ffe1b | 12651 | static bool |
2fa2fe9a | 12652 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b | 12653 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
12654 | struct intel_crtc_state *pipe_config, |
12655 | bool adjust) | |
0e8ffe1b | 12656 | { |
cfb23ed6 ML |
12657 | bool ret = true; |
12658 | ||
12659 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
12660 | do { \ | |
12661 | if (!adjust) \ | |
12662 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
12663 | else \ | |
12664 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
12665 | } while (0) | |
12666 | ||
66e985c0 DV |
12667 | #define PIPE_CONF_CHECK_X(name) \ |
12668 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12669 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
12670 | "(expected 0x%08x, found 0x%08x)\n", \ |
12671 | current_config->name, \ | |
12672 | pipe_config->name); \ | |
cfb23ed6 | 12673 | ret = false; \ |
66e985c0 DV |
12674 | } |
12675 | ||
08a24034 DV |
12676 | #define PIPE_CONF_CHECK_I(name) \ |
12677 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12678 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
12679 | "(expected %i, found %i)\n", \ |
12680 | current_config->name, \ | |
12681 | pipe_config->name); \ | |
cfb23ed6 ML |
12682 | ret = false; \ |
12683 | } | |
12684 | ||
12685 | #define PIPE_CONF_CHECK_M_N(name) \ | |
12686 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12687 | &pipe_config->name,\ | |
12688 | adjust)) { \ | |
12689 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12690 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12691 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12692 | current_config->name.tu, \ | |
12693 | current_config->name.gmch_m, \ | |
12694 | current_config->name.gmch_n, \ | |
12695 | current_config->name.link_m, \ | |
12696 | current_config->name.link_n, \ | |
12697 | pipe_config->name.tu, \ | |
12698 | pipe_config->name.gmch_m, \ | |
12699 | pipe_config->name.gmch_n, \ | |
12700 | pipe_config->name.link_m, \ | |
12701 | pipe_config->name.link_n); \ | |
12702 | ret = false; \ | |
12703 | } | |
12704 | ||
12705 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ | |
12706 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12707 | &pipe_config->name, adjust) && \ | |
12708 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
12709 | &pipe_config->name, adjust)) { \ | |
12710 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12711 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12712 | "or tu %i gmch %i/%i link %i/%i, " \ | |
12713 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12714 | current_config->name.tu, \ | |
12715 | current_config->name.gmch_m, \ | |
12716 | current_config->name.gmch_n, \ | |
12717 | current_config->name.link_m, \ | |
12718 | current_config->name.link_n, \ | |
12719 | current_config->alt_name.tu, \ | |
12720 | current_config->alt_name.gmch_m, \ | |
12721 | current_config->alt_name.gmch_n, \ | |
12722 | current_config->alt_name.link_m, \ | |
12723 | current_config->alt_name.link_n, \ | |
12724 | pipe_config->name.tu, \ | |
12725 | pipe_config->name.gmch_m, \ | |
12726 | pipe_config->name.gmch_n, \ | |
12727 | pipe_config->name.link_m, \ | |
12728 | pipe_config->name.link_n); \ | |
12729 | ret = false; \ | |
88adfff1 DV |
12730 | } |
12731 | ||
b95af8be VK |
12732 | /* This is required for BDW+ where there is only one set of registers for |
12733 | * switching between high and low RR. | |
12734 | * This macro can be used whenever a comparison has to be made between one | |
12735 | * hw state and multiple sw state variables. | |
12736 | */ | |
12737 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
12738 | if ((current_config->name != pipe_config->name) && \ | |
12739 | (current_config->alt_name != pipe_config->name)) { \ | |
cfb23ed6 | 12740 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
b95af8be VK |
12741 | "(expected %i or %i, found %i)\n", \ |
12742 | current_config->name, \ | |
12743 | current_config->alt_name, \ | |
12744 | pipe_config->name); \ | |
cfb23ed6 | 12745 | ret = false; \ |
b95af8be VK |
12746 | } |
12747 | ||
1bd1bd80 DV |
12748 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
12749 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 12750 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
12751 | "(expected %i, found %i)\n", \ |
12752 | current_config->name & (mask), \ | |
12753 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 12754 | ret = false; \ |
1bd1bd80 DV |
12755 | } |
12756 | ||
5e550656 VS |
12757 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
12758 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 12759 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
12760 | "(expected %i, found %i)\n", \ |
12761 | current_config->name, \ | |
12762 | pipe_config->name); \ | |
cfb23ed6 | 12763 | ret = false; \ |
5e550656 VS |
12764 | } |
12765 | ||
bb760063 DV |
12766 | #define PIPE_CONF_QUIRK(quirk) \ |
12767 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
12768 | ||
eccb140b DV |
12769 | PIPE_CONF_CHECK_I(cpu_transcoder); |
12770 | ||
08a24034 DV |
12771 | PIPE_CONF_CHECK_I(has_pch_encoder); |
12772 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 12773 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 12774 | |
eb14cb74 | 12775 | PIPE_CONF_CHECK_I(has_dp_encoder); |
90a6b7b0 | 12776 | PIPE_CONF_CHECK_I(lane_count); |
b95af8be VK |
12777 | |
12778 | if (INTEL_INFO(dev)->gen < 8) { | |
cfb23ed6 ML |
12779 | PIPE_CONF_CHECK_M_N(dp_m_n); |
12780 | ||
cfb23ed6 ML |
12781 | if (current_config->has_drrs) |
12782 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
12783 | } else | |
12784 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 12785 | |
a65347ba JN |
12786 | PIPE_CONF_CHECK_I(has_dsi_encoder); |
12787 | ||
2d112de7 ACO |
12788 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12789 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
12790 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
12791 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
12792 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
12793 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 12794 | |
2d112de7 ACO |
12795 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
12796 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
12797 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
12798 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
12799 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
12800 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 12801 | |
c93f54cf | 12802 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 12803 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 | 12804 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
666a4537 | 12805 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
b5a9fa09 | 12806 | PIPE_CONF_CHECK_I(limited_color_range); |
e43823ec | 12807 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 12808 | |
9ed109a7 DV |
12809 | PIPE_CONF_CHECK_I(has_audio); |
12810 | ||
2d112de7 | 12811 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
12812 | DRM_MODE_FLAG_INTERLACE); |
12813 | ||
bb760063 | 12814 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 12815 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12816 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 12817 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12818 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 12819 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12820 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 12821 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
12822 | DRM_MODE_FLAG_NVSYNC); |
12823 | } | |
045ac3b5 | 12824 | |
333b8ca8 | 12825 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a DV |
12826 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
12827 | if (INTEL_INFO(dev)->gen < 4) | |
12828 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
333b8ca8 | 12829 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 12830 | |
bfd16b2a ML |
12831 | if (!adjust) { |
12832 | PIPE_CONF_CHECK_I(pipe_src_w); | |
12833 | PIPE_CONF_CHECK_I(pipe_src_h); | |
12834 | ||
12835 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
12836 | if (current_config->pch_pfit.enabled) { | |
12837 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
12838 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
12839 | } | |
2fa2fe9a | 12840 | |
7aefe2b5 ML |
12841 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
12842 | } | |
a1b2278e | 12843 | |
e59150dc JB |
12844 | /* BDW+ don't expose a synchronous way to read the state */ |
12845 | if (IS_HASWELL(dev)) | |
12846 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 12847 | |
282740f7 VS |
12848 | PIPE_CONF_CHECK_I(double_wide); |
12849 | ||
26804afd DV |
12850 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
12851 | ||
c0d43d62 | 12852 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 12853 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 12854 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
12855 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
12856 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 12857 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 12858 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
12859 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
12860 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
12861 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 12862 | |
42571aef VS |
12863 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
12864 | PIPE_CONF_CHECK_I(pipe_bpp); | |
12865 | ||
2d112de7 | 12866 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 12867 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 12868 | |
66e985c0 | 12869 | #undef PIPE_CONF_CHECK_X |
08a24034 | 12870 | #undef PIPE_CONF_CHECK_I |
b95af8be | 12871 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 12872 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 12873 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 12874 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 12875 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 12876 | |
cfb23ed6 | 12877 | return ret; |
0e8ffe1b DV |
12878 | } |
12879 | ||
08db6652 DL |
12880 | static void check_wm_state(struct drm_device *dev) |
12881 | { | |
12882 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12883 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
12884 | struct intel_crtc *intel_crtc; | |
12885 | int plane; | |
12886 | ||
12887 | if (INTEL_INFO(dev)->gen < 9) | |
12888 | return; | |
12889 | ||
12890 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
12891 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
12892 | ||
12893 | for_each_intel_crtc(dev, intel_crtc) { | |
12894 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
12895 | const enum pipe pipe = intel_crtc->pipe; | |
12896 | ||
12897 | if (!intel_crtc->active) | |
12898 | continue; | |
12899 | ||
12900 | /* planes */ | |
dd740780 | 12901 | for_each_plane(dev_priv, pipe, plane) { |
08db6652 DL |
12902 | hw_entry = &hw_ddb.plane[pipe][plane]; |
12903 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
12904 | ||
12905 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12906 | continue; | |
12907 | ||
12908 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
12909 | "(expected (%u,%u), found (%u,%u))\n", | |
12910 | pipe_name(pipe), plane + 1, | |
12911 | sw_entry->start, sw_entry->end, | |
12912 | hw_entry->start, hw_entry->end); | |
12913 | } | |
12914 | ||
12915 | /* cursor */ | |
4969d33e MR |
12916 | hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; |
12917 | sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
08db6652 DL |
12918 | |
12919 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12920 | continue; | |
12921 | ||
12922 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
12923 | "(expected (%u,%u), found (%u,%u))\n", | |
12924 | pipe_name(pipe), | |
12925 | sw_entry->start, sw_entry->end, | |
12926 | hw_entry->start, hw_entry->end); | |
12927 | } | |
12928 | } | |
12929 | ||
91d1b4bd | 12930 | static void |
35dd3c64 ML |
12931 | check_connector_state(struct drm_device *dev, |
12932 | struct drm_atomic_state *old_state) | |
8af6cf88 | 12933 | { |
35dd3c64 ML |
12934 | struct drm_connector_state *old_conn_state; |
12935 | struct drm_connector *connector; | |
12936 | int i; | |
8af6cf88 | 12937 | |
35dd3c64 ML |
12938 | for_each_connector_in_state(old_state, connector, old_conn_state, i) { |
12939 | struct drm_encoder *encoder = connector->encoder; | |
12940 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 12941 | |
8af6cf88 DV |
12942 | /* This also checks the encoder/connector hw state with the |
12943 | * ->get_hw_state callbacks. */ | |
35dd3c64 | 12944 | intel_connector_check_state(to_intel_connector(connector)); |
8af6cf88 | 12945 | |
ad3c558f | 12946 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 12947 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 12948 | } |
91d1b4bd DV |
12949 | } |
12950 | ||
12951 | static void | |
12952 | check_encoder_state(struct drm_device *dev) | |
12953 | { | |
12954 | struct intel_encoder *encoder; | |
12955 | struct intel_connector *connector; | |
8af6cf88 | 12956 | |
b2784e15 | 12957 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 12958 | bool enabled = false; |
4d20cd86 | 12959 | enum pipe pipe; |
8af6cf88 DV |
12960 | |
12961 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
12962 | encoder->base.base.id, | |
8e329a03 | 12963 | encoder->base.name); |
8af6cf88 | 12964 | |
3a3371ff | 12965 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 12966 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
12967 | continue; |
12968 | enabled = true; | |
ad3c558f ML |
12969 | |
12970 | I915_STATE_WARN(connector->base.state->crtc != | |
12971 | encoder->base.crtc, | |
12972 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 12973 | } |
0e32b39c | 12974 | |
e2c719b7 | 12975 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
12976 | "encoder's enabled state mismatch " |
12977 | "(expected %i, found %i)\n", | |
12978 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
12979 | |
12980 | if (!encoder->base.crtc) { | |
4d20cd86 | 12981 | bool active; |
7c60d198 | 12982 | |
4d20cd86 ML |
12983 | active = encoder->get_hw_state(encoder, &pipe); |
12984 | I915_STATE_WARN(active, | |
12985 | "encoder detached but still enabled on pipe %c.\n", | |
12986 | pipe_name(pipe)); | |
7c60d198 | 12987 | } |
8af6cf88 | 12988 | } |
91d1b4bd DV |
12989 | } |
12990 | ||
12991 | static void | |
4d20cd86 | 12992 | check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state) |
91d1b4bd | 12993 | { |
fbee40df | 12994 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd | 12995 | struct intel_encoder *encoder; |
4d20cd86 ML |
12996 | struct drm_crtc_state *old_crtc_state; |
12997 | struct drm_crtc *crtc; | |
12998 | int i; | |
8af6cf88 | 12999 | |
4d20cd86 ML |
13000 | for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) { |
13001 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
13002 | struct intel_crtc_state *pipe_config, *sw_config; | |
7b89b8de | 13003 | bool active; |
8af6cf88 | 13004 | |
bfd16b2a ML |
13005 | if (!needs_modeset(crtc->state) && |
13006 | !to_intel_crtc_state(crtc->state)->update_pipe) | |
4d20cd86 | 13007 | continue; |
045ac3b5 | 13008 | |
4d20cd86 ML |
13009 | __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state); |
13010 | pipe_config = to_intel_crtc_state(old_crtc_state); | |
13011 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
13012 | pipe_config->base.crtc = crtc; | |
13013 | pipe_config->base.state = old_state; | |
8af6cf88 | 13014 | |
4d20cd86 ML |
13015 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
13016 | crtc->base.id); | |
8af6cf88 | 13017 | |
4d20cd86 ML |
13018 | active = dev_priv->display.get_pipe_config(intel_crtc, |
13019 | pipe_config); | |
d62cf62a | 13020 | |
b6b5d049 | 13021 | /* hw state is inconsistent with the pipe quirk */ |
4d20cd86 ML |
13022 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
13023 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
13024 | active = crtc->state->active; | |
6c49f241 | 13025 | |
4d20cd86 | 13026 | I915_STATE_WARN(crtc->state->active != active, |
0e8ffe1b | 13027 | "crtc active state doesn't match with hw state " |
4d20cd86 | 13028 | "(expected %i, found %i)\n", crtc->state->active, active); |
0e8ffe1b | 13029 | |
4d20cd86 | 13030 | I915_STATE_WARN(intel_crtc->active != crtc->state->active, |
53d9f4e9 | 13031 | "transitional active state does not match atomic hw state " |
4d20cd86 ML |
13032 | "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active); |
13033 | ||
13034 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
13035 | enum pipe pipe; | |
13036 | ||
13037 | active = encoder->get_hw_state(encoder, &pipe); | |
13038 | I915_STATE_WARN(active != crtc->state->active, | |
13039 | "[ENCODER:%i] active %i with crtc active %i\n", | |
13040 | encoder->base.base.id, active, crtc->state->active); | |
13041 | ||
13042 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, | |
13043 | "Encoder connected to wrong pipe %c\n", | |
13044 | pipe_name(pipe)); | |
13045 | ||
13046 | if (active) | |
13047 | encoder->get_config(encoder, pipe_config); | |
13048 | } | |
53d9f4e9 | 13049 | |
4d20cd86 | 13050 | if (!crtc->state->active) |
cfb23ed6 ML |
13051 | continue; |
13052 | ||
4d20cd86 ML |
13053 | sw_config = to_intel_crtc_state(crtc->state); |
13054 | if (!intel_pipe_config_compare(dev, sw_config, | |
13055 | pipe_config, false)) { | |
e2c719b7 | 13056 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
4d20cd86 | 13057 | intel_dump_pipe_config(intel_crtc, pipe_config, |
c0b03411 | 13058 | "[hw state]"); |
4d20cd86 | 13059 | intel_dump_pipe_config(intel_crtc, sw_config, |
c0b03411 DV |
13060 | "[sw state]"); |
13061 | } | |
8af6cf88 DV |
13062 | } |
13063 | } | |
13064 | ||
91d1b4bd DV |
13065 | static void |
13066 | check_shared_dpll_state(struct drm_device *dev) | |
13067 | { | |
fbee40df | 13068 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
13069 | struct intel_crtc *crtc; |
13070 | struct intel_dpll_hw_state dpll_hw_state; | |
13071 | int i; | |
5358901f DV |
13072 | |
13073 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
13074 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
13075 | int enabled_crtcs = 0, active_crtcs = 0; | |
13076 | bool active; | |
13077 | ||
13078 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
13079 | ||
13080 | DRM_DEBUG_KMS("%s\n", pll->name); | |
13081 | ||
13082 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
13083 | ||
e2c719b7 | 13084 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 13085 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 13086 | pll->active, hweight32(pll->config.crtc_mask)); |
e2c719b7 | 13087 | I915_STATE_WARN(pll->active && !pll->on, |
5358901f | 13088 | "pll in active use but not on in sw tracking\n"); |
e2c719b7 | 13089 | I915_STATE_WARN(pll->on && !pll->active, |
35c95375 | 13090 | "pll in on but not on in use in sw tracking\n"); |
e2c719b7 | 13091 | I915_STATE_WARN(pll->on != active, |
5358901f DV |
13092 | "pll on state mismatch (expected %i, found %i)\n", |
13093 | pll->on, active); | |
13094 | ||
d3fcc808 | 13095 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 13096 | if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
5358901f DV |
13097 | enabled_crtcs++; |
13098 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
13099 | active_crtcs++; | |
13100 | } | |
e2c719b7 | 13101 | I915_STATE_WARN(pll->active != active_crtcs, |
5358901f DV |
13102 | "pll active crtcs mismatch (expected %i, found %i)\n", |
13103 | pll->active, active_crtcs); | |
e2c719b7 | 13104 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 13105 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 13106 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 13107 | |
e2c719b7 | 13108 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
13109 | sizeof(dpll_hw_state)), |
13110 | "pll hw state mismatch\n"); | |
5358901f | 13111 | } |
8af6cf88 DV |
13112 | } |
13113 | ||
ee165b1a ML |
13114 | static void |
13115 | intel_modeset_check_state(struct drm_device *dev, | |
13116 | struct drm_atomic_state *old_state) | |
91d1b4bd | 13117 | { |
08db6652 | 13118 | check_wm_state(dev); |
35dd3c64 | 13119 | check_connector_state(dev, old_state); |
91d1b4bd | 13120 | check_encoder_state(dev); |
4d20cd86 | 13121 | check_crtc_state(dev, old_state); |
91d1b4bd DV |
13122 | check_shared_dpll_state(dev); |
13123 | } | |
13124 | ||
5cec258b | 13125 | void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
18442d08 VS |
13126 | int dotclock) |
13127 | { | |
13128 | /* | |
13129 | * FDI already provided one idea for the dotclock. | |
13130 | * Yell if the encoder disagrees. | |
13131 | */ | |
2d112de7 | 13132 | WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), |
18442d08 | 13133 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
2d112de7 | 13134 | pipe_config->base.adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
13135 | } |
13136 | ||
80715b2f VS |
13137 | static void update_scanline_offset(struct intel_crtc *crtc) |
13138 | { | |
13139 | struct drm_device *dev = crtc->base.dev; | |
13140 | ||
13141 | /* | |
13142 | * The scanline counter increments at the leading edge of hsync. | |
13143 | * | |
13144 | * On most platforms it starts counting from vtotal-1 on the | |
13145 | * first active line. That means the scanline counter value is | |
13146 | * always one less than what we would expect. Ie. just after | |
13147 | * start of vblank, which also occurs at start of hsync (on the | |
13148 | * last active line), the scanline counter will read vblank_start-1. | |
13149 | * | |
13150 | * On gen2 the scanline counter starts counting from 1 instead | |
13151 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
13152 | * to keep the value positive), instead of adding one. | |
13153 | * | |
13154 | * On HSW+ the behaviour of the scanline counter depends on the output | |
13155 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
13156 | * there's an extra 1 line difference. So we need to add two instead of | |
13157 | * one to the value. | |
13158 | */ | |
13159 | if (IS_GEN2(dev)) { | |
124abe07 | 13160 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
13161 | int vtotal; |
13162 | ||
124abe07 VS |
13163 | vtotal = adjusted_mode->crtc_vtotal; |
13164 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
13165 | vtotal /= 2; |
13166 | ||
13167 | crtc->scanline_offset = vtotal - 1; | |
13168 | } else if (HAS_DDI(dev) && | |
409ee761 | 13169 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
13170 | crtc->scanline_offset = 2; |
13171 | } else | |
13172 | crtc->scanline_offset = 1; | |
13173 | } | |
13174 | ||
ad421372 | 13175 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 13176 | { |
225da59b | 13177 | struct drm_device *dev = state->dev; |
ed6739ef | 13178 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 13179 | struct intel_shared_dpll_config *shared_dpll = NULL; |
ed6739ef | 13180 | struct intel_crtc *intel_crtc; |
0a9ab303 ACO |
13181 | struct intel_crtc_state *intel_crtc_state; |
13182 | struct drm_crtc *crtc; | |
13183 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 13184 | int i; |
ed6739ef ACO |
13185 | |
13186 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 13187 | return; |
ed6739ef | 13188 | |
0a9ab303 | 13189 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
ad421372 ML |
13190 | int dpll; |
13191 | ||
0a9ab303 | 13192 | intel_crtc = to_intel_crtc(crtc); |
4978cc93 | 13193 | intel_crtc_state = to_intel_crtc_state(crtc_state); |
ad421372 | 13194 | dpll = intel_crtc_state->shared_dpll; |
0a9ab303 | 13195 | |
ad421372 | 13196 | if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE) |
225da59b ACO |
13197 | continue; |
13198 | ||
ad421372 | 13199 | intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE; |
0a9ab303 | 13200 | |
ad421372 ML |
13201 | if (!shared_dpll) |
13202 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 13203 | |
ad421372 ML |
13204 | shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe); |
13205 | } | |
ed6739ef ACO |
13206 | } |
13207 | ||
99d736a2 ML |
13208 | /* |
13209 | * This implements the workaround described in the "notes" section of the mode | |
13210 | * set sequence documentation. When going from no pipes or single pipe to | |
13211 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
13212 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
13213 | */ | |
13214 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
13215 | { | |
13216 | struct drm_crtc_state *crtc_state; | |
13217 | struct intel_crtc *intel_crtc; | |
13218 | struct drm_crtc *crtc; | |
13219 | struct intel_crtc_state *first_crtc_state = NULL; | |
13220 | struct intel_crtc_state *other_crtc_state = NULL; | |
13221 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
13222 | int i; | |
13223 | ||
13224 | /* look at all crtc's that are going to be enabled in during modeset */ | |
13225 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13226 | intel_crtc = to_intel_crtc(crtc); | |
13227 | ||
13228 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
13229 | continue; | |
13230 | ||
13231 | if (first_crtc_state) { | |
13232 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
13233 | break; | |
13234 | } else { | |
13235 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
13236 | first_pipe = intel_crtc->pipe; | |
13237 | } | |
13238 | } | |
13239 | ||
13240 | /* No workaround needed? */ | |
13241 | if (!first_crtc_state) | |
13242 | return 0; | |
13243 | ||
13244 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
13245 | for_each_intel_crtc(state->dev, intel_crtc) { | |
13246 | struct intel_crtc_state *pipe_config; | |
13247 | ||
13248 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
13249 | if (IS_ERR(pipe_config)) | |
13250 | return PTR_ERR(pipe_config); | |
13251 | ||
13252 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
13253 | ||
13254 | if (!pipe_config->base.active || | |
13255 | needs_modeset(&pipe_config->base)) | |
13256 | continue; | |
13257 | ||
13258 | /* 2 or more enabled crtcs means no need for w/a */ | |
13259 | if (enabled_pipe != INVALID_PIPE) | |
13260 | return 0; | |
13261 | ||
13262 | enabled_pipe = intel_crtc->pipe; | |
13263 | } | |
13264 | ||
13265 | if (enabled_pipe != INVALID_PIPE) | |
13266 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
13267 | else if (other_crtc_state) | |
13268 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
13269 | ||
13270 | return 0; | |
13271 | } | |
13272 | ||
27c329ed ML |
13273 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
13274 | { | |
13275 | struct drm_crtc *crtc; | |
13276 | struct drm_crtc_state *crtc_state; | |
13277 | int ret = 0; | |
13278 | ||
13279 | /* add all active pipes to the state */ | |
13280 | for_each_crtc(state->dev, crtc) { | |
13281 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13282 | if (IS_ERR(crtc_state)) | |
13283 | return PTR_ERR(crtc_state); | |
13284 | ||
13285 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
13286 | continue; | |
13287 | ||
13288 | crtc_state->mode_changed = true; | |
13289 | ||
13290 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
13291 | if (ret) | |
13292 | break; | |
13293 | ||
13294 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13295 | if (ret) | |
13296 | break; | |
13297 | } | |
13298 | ||
13299 | return ret; | |
13300 | } | |
13301 | ||
c347a676 | 13302 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 13303 | { |
565602d7 ML |
13304 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
13305 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
13306 | struct drm_crtc *crtc; | |
13307 | struct drm_crtc_state *crtc_state; | |
13308 | int ret = 0, i; | |
054518dd | 13309 | |
b359283a ML |
13310 | if (!check_digital_port_conflicts(state)) { |
13311 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
13312 | return -EINVAL; | |
13313 | } | |
13314 | ||
565602d7 ML |
13315 | intel_state->modeset = true; |
13316 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
13317 | ||
13318 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13319 | if (crtc_state->active) | |
13320 | intel_state->active_crtcs |= 1 << i; | |
13321 | else | |
13322 | intel_state->active_crtcs &= ~(1 << i); | |
13323 | } | |
13324 | ||
054518dd ACO |
13325 | /* |
13326 | * See if the config requires any additional preparation, e.g. | |
13327 | * to adjust global state with pipes off. We need to do this | |
13328 | * here so we can get the modeset_pipe updated config for the new | |
13329 | * mode set on this crtc. For other crtcs we need to use the | |
13330 | * adjusted_mode bits in the crtc directly. | |
13331 | */ | |
27c329ed | 13332 | if (dev_priv->display.modeset_calc_cdclk) { |
27c329ed ML |
13333 | ret = dev_priv->display.modeset_calc_cdclk(state); |
13334 | ||
1a617b77 | 13335 | if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq) |
27c329ed ML |
13336 | ret = intel_modeset_all_pipes(state); |
13337 | ||
13338 | if (ret < 0) | |
054518dd | 13339 | return ret; |
27c329ed | 13340 | } else |
1a617b77 | 13341 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; |
054518dd | 13342 | |
ad421372 | 13343 | intel_modeset_clear_plls(state); |
054518dd | 13344 | |
565602d7 | 13345 | if (IS_HASWELL(dev_priv)) |
ad421372 | 13346 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 13347 | |
ad421372 | 13348 | return 0; |
c347a676 ACO |
13349 | } |
13350 | ||
aa363136 MR |
13351 | /* |
13352 | * Handle calculation of various watermark data at the end of the atomic check | |
13353 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
13354 | * handlers to ensure that all derived state has been updated. | |
13355 | */ | |
13356 | static void calc_watermark_data(struct drm_atomic_state *state) | |
13357 | { | |
13358 | struct drm_device *dev = state->dev; | |
13359 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
13360 | struct drm_crtc *crtc; | |
13361 | struct drm_crtc_state *cstate; | |
13362 | struct drm_plane *plane; | |
13363 | struct drm_plane_state *pstate; | |
13364 | ||
13365 | /* | |
13366 | * Calculate watermark configuration details now that derived | |
13367 | * plane/crtc state is all properly updated. | |
13368 | */ | |
13369 | drm_for_each_crtc(crtc, dev) { | |
13370 | cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?: | |
13371 | crtc->state; | |
13372 | ||
13373 | if (cstate->active) | |
13374 | intel_state->wm_config.num_pipes_active++; | |
13375 | } | |
13376 | drm_for_each_legacy_plane(plane, dev) { | |
13377 | pstate = drm_atomic_get_existing_plane_state(state, plane) ?: | |
13378 | plane->state; | |
13379 | ||
13380 | if (!to_intel_plane_state(pstate)->visible) | |
13381 | continue; | |
13382 | ||
13383 | intel_state->wm_config.sprites_enabled = true; | |
13384 | if (pstate->crtc_w != pstate->src_w >> 16 || | |
13385 | pstate->crtc_h != pstate->src_h >> 16) | |
13386 | intel_state->wm_config.sprites_scaled = true; | |
13387 | } | |
13388 | } | |
13389 | ||
74c090b1 ML |
13390 | /** |
13391 | * intel_atomic_check - validate state object | |
13392 | * @dev: drm device | |
13393 | * @state: state to validate | |
13394 | */ | |
13395 | static int intel_atomic_check(struct drm_device *dev, | |
13396 | struct drm_atomic_state *state) | |
c347a676 | 13397 | { |
aa363136 | 13398 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
13399 | struct drm_crtc *crtc; |
13400 | struct drm_crtc_state *crtc_state; | |
13401 | int ret, i; | |
61333b60 | 13402 | bool any_ms = false; |
c347a676 | 13403 | |
74c090b1 | 13404 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
13405 | if (ret) |
13406 | return ret; | |
13407 | ||
c347a676 | 13408 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
13409 | struct intel_crtc_state *pipe_config = |
13410 | to_intel_crtc_state(crtc_state); | |
1ed51de9 | 13411 | |
ba8af3e5 ML |
13412 | memset(&to_intel_crtc(crtc)->atomic, 0, |
13413 | sizeof(struct intel_crtc_atomic_commit)); | |
13414 | ||
1ed51de9 DV |
13415 | /* Catch I915_MODE_FLAG_INHERITED */ |
13416 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
13417 | crtc_state->mode_changed = true; | |
cfb23ed6 | 13418 | |
61333b60 ML |
13419 | if (!crtc_state->enable) { |
13420 | if (needs_modeset(crtc_state)) | |
13421 | any_ms = true; | |
c347a676 | 13422 | continue; |
61333b60 | 13423 | } |
c347a676 | 13424 | |
26495481 | 13425 | if (!needs_modeset(crtc_state)) |
cfb23ed6 ML |
13426 | continue; |
13427 | ||
26495481 DV |
13428 | /* FIXME: For only active_changed we shouldn't need to do any |
13429 | * state recomputation at all. */ | |
13430 | ||
1ed51de9 DV |
13431 | ret = drm_atomic_add_affected_connectors(state, crtc); |
13432 | if (ret) | |
13433 | return ret; | |
b359283a | 13434 | |
cfb23ed6 | 13435 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
c347a676 ACO |
13436 | if (ret) |
13437 | return ret; | |
13438 | ||
73831236 JN |
13439 | if (i915.fastboot && |
13440 | intel_pipe_config_compare(state->dev, | |
cfb23ed6 | 13441 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 13442 | pipe_config, true)) { |
26495481 | 13443 | crtc_state->mode_changed = false; |
bfd16b2a | 13444 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
13445 | } |
13446 | ||
13447 | if (needs_modeset(crtc_state)) { | |
13448 | any_ms = true; | |
cfb23ed6 ML |
13449 | |
13450 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13451 | if (ret) | |
13452 | return ret; | |
13453 | } | |
61333b60 | 13454 | |
26495481 DV |
13455 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
13456 | needs_modeset(crtc_state) ? | |
13457 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
13458 | } |
13459 | ||
61333b60 ML |
13460 | if (any_ms) { |
13461 | ret = intel_modeset_checks(state); | |
13462 | ||
13463 | if (ret) | |
13464 | return ret; | |
27c329ed | 13465 | } else |
aa363136 | 13466 | intel_state->cdclk = to_i915(state->dev)->cdclk_freq; |
76305b1a | 13467 | |
aa363136 MR |
13468 | ret = drm_atomic_helper_check_planes(state->dev, state); |
13469 | if (ret) | |
13470 | return ret; | |
13471 | ||
13472 | calc_watermark_data(state); | |
13473 | ||
13474 | return 0; | |
054518dd ACO |
13475 | } |
13476 | ||
5008e874 ML |
13477 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
13478 | struct drm_atomic_state *state, | |
13479 | bool async) | |
13480 | { | |
7580d774 ML |
13481 | struct drm_i915_private *dev_priv = dev->dev_private; |
13482 | struct drm_plane_state *plane_state; | |
5008e874 | 13483 | struct drm_crtc_state *crtc_state; |
7580d774 | 13484 | struct drm_plane *plane; |
5008e874 ML |
13485 | struct drm_crtc *crtc; |
13486 | int i, ret; | |
13487 | ||
13488 | if (async) { | |
13489 | DRM_DEBUG_KMS("i915 does not yet support async commit\n"); | |
13490 | return -EINVAL; | |
13491 | } | |
13492 | ||
13493 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13494 | ret = intel_crtc_wait_for_pending_flips(crtc); | |
13495 | if (ret) | |
13496 | return ret; | |
7580d774 ML |
13497 | |
13498 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) | |
13499 | flush_workqueue(dev_priv->wq); | |
5008e874 ML |
13500 | } |
13501 | ||
f935675f ML |
13502 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
13503 | if (ret) | |
13504 | return ret; | |
13505 | ||
5008e874 | 13506 | ret = drm_atomic_helper_prepare_planes(dev, state); |
7580d774 ML |
13507 | if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) { |
13508 | u32 reset_counter; | |
13509 | ||
13510 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); | |
13511 | mutex_unlock(&dev->struct_mutex); | |
13512 | ||
13513 | for_each_plane_in_state(state, plane, plane_state, i) { | |
13514 | struct intel_plane_state *intel_plane_state = | |
13515 | to_intel_plane_state(plane_state); | |
13516 | ||
13517 | if (!intel_plane_state->wait_req) | |
13518 | continue; | |
13519 | ||
13520 | ret = __i915_wait_request(intel_plane_state->wait_req, | |
13521 | reset_counter, true, | |
13522 | NULL, NULL); | |
13523 | ||
13524 | /* Swallow -EIO errors to allow updates during hw lockup. */ | |
13525 | if (ret == -EIO) | |
13526 | ret = 0; | |
13527 | ||
13528 | if (ret) | |
13529 | break; | |
13530 | } | |
13531 | ||
13532 | if (!ret) | |
13533 | return 0; | |
13534 | ||
13535 | mutex_lock(&dev->struct_mutex); | |
13536 | drm_atomic_helper_cleanup_planes(dev, state); | |
13537 | } | |
5008e874 | 13538 | |
f935675f | 13539 | mutex_unlock(&dev->struct_mutex); |
5008e874 ML |
13540 | return ret; |
13541 | } | |
13542 | ||
74c090b1 ML |
13543 | /** |
13544 | * intel_atomic_commit - commit validated state object | |
13545 | * @dev: DRM device | |
13546 | * @state: the top-level driver state object | |
13547 | * @async: asynchronous commit | |
13548 | * | |
13549 | * This function commits a top-level state object that has been validated | |
13550 | * with drm_atomic_helper_check(). | |
13551 | * | |
13552 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment | |
13553 | * we can only handle plane-related operations and do not yet support | |
13554 | * asynchronous commit. | |
13555 | * | |
13556 | * RETURNS | |
13557 | * Zero for success or -errno. | |
13558 | */ | |
13559 | static int intel_atomic_commit(struct drm_device *dev, | |
13560 | struct drm_atomic_state *state, | |
13561 | bool async) | |
a6778b3c | 13562 | { |
565602d7 | 13563 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fbee40df | 13564 | struct drm_i915_private *dev_priv = dev->dev_private; |
0a9ab303 | 13565 | struct drm_crtc_state *crtc_state; |
7580d774 | 13566 | struct drm_crtc *crtc; |
396e33ae | 13567 | struct intel_crtc_state *intel_cstate; |
565602d7 ML |
13568 | int ret = 0, i; |
13569 | bool hw_check = intel_state->modeset; | |
a6778b3c | 13570 | |
5008e874 | 13571 | ret = intel_atomic_prepare_commit(dev, state, async); |
7580d774 ML |
13572 | if (ret) { |
13573 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
d4afb8cc | 13574 | return ret; |
7580d774 | 13575 | } |
d4afb8cc | 13576 | |
1c5e19f8 | 13577 | drm_atomic_helper_swap_state(dev, state); |
aa363136 | 13578 | dev_priv->wm.config = to_intel_atomic_state(state)->wm_config; |
1c5e19f8 | 13579 | |
565602d7 ML |
13580 | if (intel_state->modeset) { |
13581 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
13582 | sizeof(intel_state->min_pixclk)); | |
13583 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
1a617b77 | 13584 | dev_priv->atomic_cdclk_freq = intel_state->cdclk; |
565602d7 ML |
13585 | } |
13586 | ||
0a9ab303 | 13587 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
a539205a ML |
13588 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13589 | ||
61333b60 ML |
13590 | if (!needs_modeset(crtc->state)) |
13591 | continue; | |
13592 | ||
a539205a | 13593 | intel_pre_plane_update(intel_crtc); |
460da916 | 13594 | |
a539205a ML |
13595 | if (crtc_state->active) { |
13596 | intel_crtc_disable_planes(crtc, crtc_state->plane_mask); | |
13597 | dev_priv->display.crtc_disable(crtc); | |
eddfcbcd ML |
13598 | intel_crtc->active = false; |
13599 | intel_disable_shared_dpll(intel_crtc); | |
9bbc8258 VS |
13600 | |
13601 | /* | |
13602 | * Underruns don't always raise | |
13603 | * interrupts, so check manually. | |
13604 | */ | |
13605 | intel_check_cpu_fifo_underruns(dev_priv); | |
13606 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 ML |
13607 | |
13608 | if (!crtc->state->active) | |
13609 | intel_update_watermarks(crtc); | |
a539205a | 13610 | } |
b8cecdf5 | 13611 | } |
7758a113 | 13612 | |
ea9d758d DV |
13613 | /* Only after disabling all output pipelines that will be changed can we |
13614 | * update the the output configuration. */ | |
4740b0f2 | 13615 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 13616 | |
565602d7 | 13617 | if (intel_state->modeset) { |
4740b0f2 ML |
13618 | intel_shared_dpll_commit(state); |
13619 | ||
13620 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); | |
61333b60 | 13621 | modeset_update_crtc_power_domains(state); |
4740b0f2 | 13622 | } |
47fab737 | 13623 | |
a6778b3c | 13624 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
0a9ab303 | 13625 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
f6ac4b2a ML |
13626 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13627 | bool modeset = needs_modeset(crtc->state); | |
bfd16b2a ML |
13628 | bool update_pipe = !modeset && |
13629 | to_intel_crtc_state(crtc->state)->update_pipe; | |
13630 | unsigned long put_domains = 0; | |
f6ac4b2a | 13631 | |
9f836f90 PJ |
13632 | if (modeset) |
13633 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); | |
13634 | ||
f6ac4b2a | 13635 | if (modeset && crtc->state->active) { |
a539205a ML |
13636 | update_scanline_offset(to_intel_crtc(crtc)); |
13637 | dev_priv->display.crtc_enable(crtc); | |
13638 | } | |
80715b2f | 13639 | |
bfd16b2a ML |
13640 | if (update_pipe) { |
13641 | put_domains = modeset_get_crtc_power_domains(crtc); | |
13642 | ||
13643 | /* make sure intel_modeset_check_state runs */ | |
565602d7 | 13644 | hw_check = true; |
bfd16b2a ML |
13645 | } |
13646 | ||
f6ac4b2a ML |
13647 | if (!modeset) |
13648 | intel_pre_plane_update(intel_crtc); | |
13649 | ||
6173ee28 ML |
13650 | if (crtc->state->active && |
13651 | (crtc->state->planes_changed || update_pipe)) | |
62852622 | 13652 | drm_atomic_helper_commit_planes_on_crtc(crtc_state); |
bfd16b2a ML |
13653 | |
13654 | if (put_domains) | |
13655 | modeset_put_power_domains(dev_priv, put_domains); | |
13656 | ||
f6ac4b2a | 13657 | intel_post_plane_update(intel_crtc); |
9f836f90 PJ |
13658 | |
13659 | if (modeset) | |
13660 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
80715b2f | 13661 | } |
a6778b3c | 13662 | |
a6778b3c | 13663 | /* FIXME: add subpixel order */ |
83a57153 | 13664 | |
74c090b1 | 13665 | drm_atomic_helper_wait_for_vblanks(dev, state); |
f935675f | 13666 | |
396e33ae MR |
13667 | /* |
13668 | * Now that the vblank has passed, we can go ahead and program the | |
13669 | * optimal watermarks on platforms that need two-step watermark | |
13670 | * programming. | |
13671 | * | |
13672 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
13673 | */ | |
13674 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13675 | intel_cstate = to_intel_crtc_state(crtc->state); | |
13676 | ||
13677 | if (dev_priv->display.optimize_watermarks) | |
13678 | dev_priv->display.optimize_watermarks(intel_cstate); | |
13679 | } | |
13680 | ||
f935675f | 13681 | mutex_lock(&dev->struct_mutex); |
d4afb8cc | 13682 | drm_atomic_helper_cleanup_planes(dev, state); |
f935675f | 13683 | mutex_unlock(&dev->struct_mutex); |
2bfb4627 | 13684 | |
565602d7 | 13685 | if (hw_check) |
ee165b1a ML |
13686 | intel_modeset_check_state(dev, state); |
13687 | ||
13688 | drm_atomic_state_free(state); | |
f30da187 | 13689 | |
75714940 MK |
13690 | /* As one of the primary mmio accessors, KMS has a high likelihood |
13691 | * of triggering bugs in unclaimed access. After we finish | |
13692 | * modesetting, see if an error has been flagged, and if so | |
13693 | * enable debugging for the next modeset - and hope we catch | |
13694 | * the culprit. | |
13695 | * | |
13696 | * XXX note that we assume display power is on at this point. | |
13697 | * This might hold true now but we need to add pm helper to check | |
13698 | * unclaimed only when the hardware is on, as atomic commits | |
13699 | * can happen also when the device is completely off. | |
13700 | */ | |
13701 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
13702 | ||
74c090b1 | 13703 | return 0; |
7f27126e JB |
13704 | } |
13705 | ||
c0c36b94 CW |
13706 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13707 | { | |
83a57153 ACO |
13708 | struct drm_device *dev = crtc->dev; |
13709 | struct drm_atomic_state *state; | |
e694eb02 | 13710 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 13711 | int ret; |
83a57153 ACO |
13712 | |
13713 | state = drm_atomic_state_alloc(dev); | |
13714 | if (!state) { | |
e694eb02 | 13715 | DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory", |
83a57153 ACO |
13716 | crtc->base.id); |
13717 | return; | |
13718 | } | |
13719 | ||
e694eb02 | 13720 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 13721 | |
e694eb02 ML |
13722 | retry: |
13723 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13724 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
13725 | if (!ret) { | |
13726 | if (!crtc_state->active) | |
13727 | goto out; | |
83a57153 | 13728 | |
e694eb02 | 13729 | crtc_state->mode_changed = true; |
74c090b1 | 13730 | ret = drm_atomic_commit(state); |
83a57153 ACO |
13731 | } |
13732 | ||
e694eb02 ML |
13733 | if (ret == -EDEADLK) { |
13734 | drm_atomic_state_clear(state); | |
13735 | drm_modeset_backoff(state->acquire_ctx); | |
13736 | goto retry; | |
4ed9fb37 | 13737 | } |
4be07317 | 13738 | |
2bfb4627 | 13739 | if (ret) |
e694eb02 | 13740 | out: |
2bfb4627 | 13741 | drm_atomic_state_free(state); |
c0c36b94 CW |
13742 | } |
13743 | ||
25c5b266 DV |
13744 | #undef for_each_intel_crtc_masked |
13745 | ||
f6e5b160 | 13746 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
f6e5b160 | 13747 | .gamma_set = intel_crtc_gamma_set, |
74c090b1 | 13748 | .set_config = drm_atomic_helper_set_config, |
f6e5b160 CW |
13749 | .destroy = intel_crtc_destroy, |
13750 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
13751 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13752 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
13753 | }; |
13754 | ||
5358901f DV |
13755 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
13756 | struct intel_shared_dpll *pll, | |
13757 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 13758 | { |
5358901f | 13759 | uint32_t val; |
ee7b9f93 | 13760 | |
f458ebbc | 13761 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
13762 | return false; |
13763 | ||
5358901f | 13764 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
13765 | hw_state->dpll = val; |
13766 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
13767 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
13768 | |
13769 | return val & DPLL_VCO_ENABLE; | |
13770 | } | |
13771 | ||
15bdd4cf DV |
13772 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
13773 | struct intel_shared_dpll *pll) | |
13774 | { | |
3e369b76 ACO |
13775 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
13776 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
13777 | } |
13778 | ||
e7b903d2 DV |
13779 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
13780 | struct intel_shared_dpll *pll) | |
13781 | { | |
e7b903d2 | 13782 | /* PCH refclock must be enabled first */ |
89eff4be | 13783 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 13784 | |
3e369b76 | 13785 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
13786 | |
13787 | /* Wait for the clocks to stabilize. */ | |
13788 | POSTING_READ(PCH_DPLL(pll->id)); | |
13789 | udelay(150); | |
13790 | ||
13791 | /* The pixel multiplier can only be updated once the | |
13792 | * DPLL is enabled and the clocks are stable. | |
13793 | * | |
13794 | * So write it again. | |
13795 | */ | |
3e369b76 | 13796 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 13797 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
13798 | udelay(200); |
13799 | } | |
13800 | ||
13801 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
13802 | struct intel_shared_dpll *pll) | |
13803 | { | |
13804 | struct drm_device *dev = dev_priv->dev; | |
13805 | struct intel_crtc *crtc; | |
e7b903d2 DV |
13806 | |
13807 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 13808 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
13809 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
13810 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
13811 | } |
13812 | ||
15bdd4cf DV |
13813 | I915_WRITE(PCH_DPLL(pll->id), 0); |
13814 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
13815 | udelay(200); |
13816 | } | |
13817 | ||
46edb027 DV |
13818 | static char *ibx_pch_dpll_names[] = { |
13819 | "PCH DPLL A", | |
13820 | "PCH DPLL B", | |
13821 | }; | |
13822 | ||
7c74ade1 | 13823 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 13824 | { |
e7b903d2 | 13825 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
13826 | int i; |
13827 | ||
7c74ade1 | 13828 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 13829 | |
e72f9fbf | 13830 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
13831 | dev_priv->shared_dplls[i].id = i; |
13832 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 13833 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
13834 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
13835 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
13836 | dev_priv->shared_dplls[i].get_hw_state = |
13837 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
13838 | } |
13839 | } | |
13840 | ||
7c74ade1 DV |
13841 | static void intel_shared_dpll_init(struct drm_device *dev) |
13842 | { | |
e7b903d2 | 13843 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 13844 | |
9cd86933 DV |
13845 | if (HAS_DDI(dev)) |
13846 | intel_ddi_pll_init(dev); | |
13847 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
13848 | ibx_pch_dpll_init(dev); |
13849 | else | |
13850 | dev_priv->num_shared_dpll = 0; | |
13851 | ||
13852 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
13853 | } |
13854 | ||
6beb8c23 MR |
13855 | /** |
13856 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13857 | * @plane: drm plane to prepare for | |
13858 | * @fb: framebuffer to prepare for presentation | |
13859 | * | |
13860 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13861 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13862 | * bits. Some older platforms need special physical address handling for | |
13863 | * cursor planes. | |
13864 | * | |
f935675f ML |
13865 | * Must be called with struct_mutex held. |
13866 | * | |
6beb8c23 MR |
13867 | * Returns 0 on success, negative error code on failure. |
13868 | */ | |
13869 | int | |
13870 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee | 13871 | const struct drm_plane_state *new_state) |
465c120c MR |
13872 | { |
13873 | struct drm_device *dev = plane->dev; | |
844f9111 | 13874 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 13875 | struct intel_plane *intel_plane = to_intel_plane(plane); |
6beb8c23 | 13876 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 13877 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
6beb8c23 | 13878 | int ret = 0; |
465c120c | 13879 | |
1ee49399 | 13880 | if (!obj && !old_obj) |
465c120c MR |
13881 | return 0; |
13882 | ||
5008e874 ML |
13883 | if (old_obj) { |
13884 | struct drm_crtc_state *crtc_state = | |
13885 | drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc); | |
13886 | ||
13887 | /* Big Hammer, we also need to ensure that any pending | |
13888 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
13889 | * current scanout is retired before unpinning the old | |
13890 | * framebuffer. Note that we rely on userspace rendering | |
13891 | * into the buffer attached to the pipe they are waiting | |
13892 | * on. If not, userspace generates a GPU hang with IPEHR | |
13893 | * point to the MI_WAIT_FOR_EVENT. | |
13894 | * | |
13895 | * This should only fail upon a hung GPU, in which case we | |
13896 | * can safely continue. | |
13897 | */ | |
13898 | if (needs_modeset(crtc_state)) | |
13899 | ret = i915_gem_object_wait_rendering(old_obj, true); | |
13900 | ||
13901 | /* Swallow -EIO errors to allow updates during hw lockup. */ | |
13902 | if (ret && ret != -EIO) | |
f935675f | 13903 | return ret; |
5008e874 ML |
13904 | } |
13905 | ||
3c28ff22 AG |
13906 | /* For framebuffer backed by dmabuf, wait for fence */ |
13907 | if (obj && obj->base.dma_buf) { | |
bcf8be27 ML |
13908 | long lret; |
13909 | ||
13910 | lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
13911 | false, true, | |
13912 | MAX_SCHEDULE_TIMEOUT); | |
13913 | if (lret == -ERESTARTSYS) | |
13914 | return lret; | |
3c28ff22 | 13915 | |
bcf8be27 | 13916 | WARN(lret < 0, "waiting returns %li\n", lret); |
3c28ff22 AG |
13917 | } |
13918 | ||
1ee49399 ML |
13919 | if (!obj) { |
13920 | ret = 0; | |
13921 | } else if (plane->type == DRM_PLANE_TYPE_CURSOR && | |
6beb8c23 MR |
13922 | INTEL_INFO(dev)->cursor_needs_physical) { |
13923 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
13924 | ret = i915_gem_object_attach_phys(obj, align); | |
13925 | if (ret) | |
13926 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13927 | } else { | |
7580d774 | 13928 | ret = intel_pin_and_fence_fb_obj(plane, fb, new_state); |
6beb8c23 | 13929 | } |
465c120c | 13930 | |
7580d774 ML |
13931 | if (ret == 0) { |
13932 | if (obj) { | |
13933 | struct intel_plane_state *plane_state = | |
13934 | to_intel_plane_state(new_state); | |
13935 | ||
13936 | i915_gem_request_assign(&plane_state->wait_req, | |
13937 | obj->last_write_req); | |
13938 | } | |
13939 | ||
a9ff8714 | 13940 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); |
7580d774 | 13941 | } |
fdd508a6 | 13942 | |
6beb8c23 MR |
13943 | return ret; |
13944 | } | |
13945 | ||
38f3ce3a MR |
13946 | /** |
13947 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13948 | * @plane: drm plane to clean up for | |
13949 | * @fb: old framebuffer that was on plane | |
13950 | * | |
13951 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
13952 | * |
13953 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
13954 | */ |
13955 | void | |
13956 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee | 13957 | const struct drm_plane_state *old_state) |
38f3ce3a MR |
13958 | { |
13959 | struct drm_device *dev = plane->dev; | |
1ee49399 | 13960 | struct intel_plane *intel_plane = to_intel_plane(plane); |
7580d774 | 13961 | struct intel_plane_state *old_intel_state; |
1ee49399 ML |
13962 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
13963 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); | |
38f3ce3a | 13964 | |
7580d774 ML |
13965 | old_intel_state = to_intel_plane_state(old_state); |
13966 | ||
1ee49399 | 13967 | if (!obj && !old_obj) |
38f3ce3a MR |
13968 | return; |
13969 | ||
1ee49399 ML |
13970 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
13971 | !INTEL_INFO(dev)->cursor_needs_physical)) | |
844f9111 | 13972 | intel_unpin_fb_obj(old_state->fb, old_state); |
1ee49399 ML |
13973 | |
13974 | /* prepare_fb aborted? */ | |
13975 | if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) || | |
13976 | (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit))) | |
13977 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); | |
7580d774 ML |
13978 | |
13979 | i915_gem_request_assign(&old_intel_state->wait_req, NULL); | |
13980 | ||
465c120c MR |
13981 | } |
13982 | ||
6156a456 CK |
13983 | int |
13984 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
13985 | { | |
13986 | int max_scale; | |
13987 | struct drm_device *dev; | |
13988 | struct drm_i915_private *dev_priv; | |
13989 | int crtc_clock, cdclk; | |
13990 | ||
bf8a0af0 | 13991 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
13992 | return DRM_PLANE_HELPER_NO_SCALING; |
13993 | ||
13994 | dev = intel_crtc->base.dev; | |
13995 | dev_priv = dev->dev_private; | |
13996 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; | |
27c329ed | 13997 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 | 13998 | |
54bf1ce6 | 13999 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
6156a456 CK |
14000 | return DRM_PLANE_HELPER_NO_SCALING; |
14001 | ||
14002 | /* | |
14003 | * skl max scale is lower of: | |
14004 | * close to 3 but not 3, -1 is for that purpose | |
14005 | * or | |
14006 | * cdclk/crtc_clock | |
14007 | */ | |
14008 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
14009 | ||
14010 | return max_scale; | |
14011 | } | |
14012 | ||
465c120c | 14013 | static int |
3c692a41 | 14014 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 14015 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
14016 | struct intel_plane_state *state) |
14017 | { | |
2b875c22 MR |
14018 | struct drm_crtc *crtc = state->base.crtc; |
14019 | struct drm_framebuffer *fb = state->base.fb; | |
6156a456 | 14020 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
14021 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
14022 | bool can_position = false; | |
465c120c | 14023 | |
061e4b8d ML |
14024 | /* use scaler when colorkey is not required */ |
14025 | if (INTEL_INFO(plane->dev)->gen >= 9 && | |
818ed961 | 14026 | state->ckey.flags == I915_SET_COLORKEY_NONE) { |
061e4b8d ML |
14027 | min_scale = 1; |
14028 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
d8106366 | 14029 | can_position = true; |
6156a456 | 14030 | } |
d8106366 | 14031 | |
061e4b8d ML |
14032 | return drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
14033 | &state->dst, &state->clip, | |
da20eabd ML |
14034 | min_scale, max_scale, |
14035 | can_position, true, | |
14036 | &state->visible); | |
14af293f GP |
14037 | } |
14038 | ||
613d2b27 ML |
14039 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
14040 | struct drm_crtc_state *old_crtc_state) | |
3c692a41 | 14041 | { |
32b7eeec | 14042 | struct drm_device *dev = crtc->dev; |
3c692a41 | 14043 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
bfd16b2a ML |
14044 | struct intel_crtc_state *old_intel_state = |
14045 | to_intel_crtc_state(old_crtc_state); | |
14046 | bool modeset = needs_modeset(crtc->state); | |
3c692a41 | 14047 | |
c34c9ee4 | 14048 | /* Perform vblank evasion around commit operation */ |
62852622 | 14049 | intel_pipe_update_start(intel_crtc); |
0583236e | 14050 | |
bfd16b2a ML |
14051 | if (modeset) |
14052 | return; | |
14053 | ||
14054 | if (to_intel_crtc_state(crtc->state)->update_pipe) | |
14055 | intel_update_pipe_config(intel_crtc, old_intel_state); | |
14056 | else if (INTEL_INFO(dev)->gen >= 9) | |
0583236e | 14057 | skl_detach_scalers(intel_crtc); |
32b7eeec MR |
14058 | } |
14059 | ||
613d2b27 ML |
14060 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, |
14061 | struct drm_crtc_state *old_crtc_state) | |
32b7eeec | 14062 | { |
32b7eeec | 14063 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
32b7eeec | 14064 | |
62852622 | 14065 | intel_pipe_update_end(intel_crtc); |
3c692a41 GP |
14066 | } |
14067 | ||
cf4c7c12 | 14068 | /** |
4a3b8769 MR |
14069 | * intel_plane_destroy - destroy a plane |
14070 | * @plane: plane to destroy | |
cf4c7c12 | 14071 | * |
4a3b8769 MR |
14072 | * Common destruction function for all types of planes (primary, cursor, |
14073 | * sprite). | |
cf4c7c12 | 14074 | */ |
4a3b8769 | 14075 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
14076 | { |
14077 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
14078 | drm_plane_cleanup(plane); | |
14079 | kfree(intel_plane); | |
14080 | } | |
14081 | ||
65a3fea0 | 14082 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
14083 | .update_plane = drm_atomic_helper_update_plane, |
14084 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 14085 | .destroy = intel_plane_destroy, |
c196e1d6 | 14086 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
14087 | .atomic_get_property = intel_plane_atomic_get_property, |
14088 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
14089 | .atomic_duplicate_state = intel_plane_duplicate_state, |
14090 | .atomic_destroy_state = intel_plane_destroy_state, | |
14091 | ||
465c120c MR |
14092 | }; |
14093 | ||
14094 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
14095 | int pipe) | |
14096 | { | |
14097 | struct intel_plane *primary; | |
8e7d688b | 14098 | struct intel_plane_state *state; |
465c120c | 14099 | const uint32_t *intel_primary_formats; |
45e3743a | 14100 | unsigned int num_formats; |
465c120c MR |
14101 | |
14102 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
14103 | if (primary == NULL) | |
14104 | return NULL; | |
14105 | ||
8e7d688b MR |
14106 | state = intel_create_plane_state(&primary->base); |
14107 | if (!state) { | |
ea2c67bb MR |
14108 | kfree(primary); |
14109 | return NULL; | |
14110 | } | |
8e7d688b | 14111 | primary->base.state = &state->base; |
ea2c67bb | 14112 | |
465c120c MR |
14113 | primary->can_scale = false; |
14114 | primary->max_downscale = 1; | |
6156a456 CK |
14115 | if (INTEL_INFO(dev)->gen >= 9) { |
14116 | primary->can_scale = true; | |
af99ceda | 14117 | state->scaler_id = -1; |
6156a456 | 14118 | } |
465c120c MR |
14119 | primary->pipe = pipe; |
14120 | primary->plane = pipe; | |
a9ff8714 | 14121 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 14122 | primary->check_plane = intel_check_primary_plane; |
465c120c MR |
14123 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
14124 | primary->plane = !pipe; | |
14125 | ||
6c0fd451 DL |
14126 | if (INTEL_INFO(dev)->gen >= 9) { |
14127 | intel_primary_formats = skl_primary_formats; | |
14128 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
a8d201af ML |
14129 | |
14130 | primary->update_plane = skylake_update_primary_plane; | |
14131 | primary->disable_plane = skylake_disable_primary_plane; | |
14132 | } else if (HAS_PCH_SPLIT(dev)) { | |
14133 | intel_primary_formats = i965_primary_formats; | |
14134 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
14135 | ||
14136 | primary->update_plane = ironlake_update_primary_plane; | |
14137 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 | 14138 | } else if (INTEL_INFO(dev)->gen >= 4) { |
568db4f2 DL |
14139 | intel_primary_formats = i965_primary_formats; |
14140 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
a8d201af ML |
14141 | |
14142 | primary->update_plane = i9xx_update_primary_plane; | |
14143 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
14144 | } else { |
14145 | intel_primary_formats = i8xx_primary_formats; | |
14146 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
a8d201af ML |
14147 | |
14148 | primary->update_plane = i9xx_update_primary_plane; | |
14149 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
14150 | } |
14151 | ||
14152 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 14153 | &intel_plane_funcs, |
465c120c MR |
14154 | intel_primary_formats, num_formats, |
14155 | DRM_PLANE_TYPE_PRIMARY); | |
48404c1e | 14156 | |
3b7a5119 SJ |
14157 | if (INTEL_INFO(dev)->gen >= 4) |
14158 | intel_create_rotation_property(dev, primary); | |
48404c1e | 14159 | |
ea2c67bb MR |
14160 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
14161 | ||
465c120c MR |
14162 | return &primary->base; |
14163 | } | |
14164 | ||
3b7a5119 SJ |
14165 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
14166 | { | |
14167 | if (!dev->mode_config.rotation_property) { | |
14168 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
14169 | BIT(DRM_ROTATE_180); | |
14170 | ||
14171 | if (INTEL_INFO(dev)->gen >= 9) | |
14172 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
14173 | ||
14174 | dev->mode_config.rotation_property = | |
14175 | drm_mode_create_rotation_property(dev, flags); | |
14176 | } | |
14177 | if (dev->mode_config.rotation_property) | |
14178 | drm_object_attach_property(&plane->base.base, | |
14179 | dev->mode_config.rotation_property, | |
14180 | plane->base.state->rotation); | |
14181 | } | |
14182 | ||
3d7d6510 | 14183 | static int |
852e787c | 14184 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 14185 | struct intel_crtc_state *crtc_state, |
852e787c | 14186 | struct intel_plane_state *state) |
3d7d6510 | 14187 | { |
061e4b8d | 14188 | struct drm_crtc *crtc = crtc_state->base.crtc; |
2b875c22 | 14189 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 14190 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
b29ec92c | 14191 | enum pipe pipe = to_intel_plane(plane)->pipe; |
757f9a3e GP |
14192 | unsigned stride; |
14193 | int ret; | |
3d7d6510 | 14194 | |
061e4b8d ML |
14195 | ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
14196 | &state->dst, &state->clip, | |
3d7d6510 MR |
14197 | DRM_PLANE_HELPER_NO_SCALING, |
14198 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 14199 | true, true, &state->visible); |
757f9a3e GP |
14200 | if (ret) |
14201 | return ret; | |
14202 | ||
757f9a3e GP |
14203 | /* if we want to turn off the cursor ignore width and height */ |
14204 | if (!obj) | |
da20eabd | 14205 | return 0; |
757f9a3e | 14206 | |
757f9a3e | 14207 | /* Check for which cursor types we support */ |
061e4b8d | 14208 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
ea2c67bb MR |
14209 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
14210 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
14211 | return -EINVAL; |
14212 | } | |
14213 | ||
ea2c67bb MR |
14214 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
14215 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
14216 | DRM_DEBUG_KMS("buffer is too small\n"); |
14217 | return -ENOMEM; | |
14218 | } | |
14219 | ||
3a656b54 | 14220 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 14221 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 14222 | return -EINVAL; |
32b7eeec MR |
14223 | } |
14224 | ||
b29ec92c VS |
14225 | /* |
14226 | * There's something wrong with the cursor on CHV pipe C. | |
14227 | * If it straddles the left edge of the screen then | |
14228 | * moving it away from the edge or disabling it often | |
14229 | * results in a pipe underrun, and often that can lead to | |
14230 | * dead pipe (constant underrun reported, and it scans | |
14231 | * out just a solid color). To recover from that, the | |
14232 | * display power well must be turned off and on again. | |
14233 | * Refuse the put the cursor into that compromised position. | |
14234 | */ | |
14235 | if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C && | |
14236 | state->visible && state->base.crtc_x < 0) { | |
14237 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); | |
14238 | return -EINVAL; | |
14239 | } | |
14240 | ||
da20eabd | 14241 | return 0; |
852e787c | 14242 | } |
3d7d6510 | 14243 | |
a8ad0d8e ML |
14244 | static void |
14245 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 14246 | struct drm_crtc *crtc) |
a8ad0d8e | 14247 | { |
f2858021 ML |
14248 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
14249 | ||
14250 | intel_crtc->cursor_addr = 0; | |
55a08b3f | 14251 | intel_crtc_update_cursor(crtc, NULL); |
a8ad0d8e ML |
14252 | } |
14253 | ||
f4a2cf29 | 14254 | static void |
55a08b3f ML |
14255 | intel_update_cursor_plane(struct drm_plane *plane, |
14256 | const struct intel_crtc_state *crtc_state, | |
14257 | const struct intel_plane_state *state) | |
852e787c | 14258 | { |
55a08b3f ML |
14259 | struct drm_crtc *crtc = crtc_state->base.crtc; |
14260 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ea2c67bb | 14261 | struct drm_device *dev = plane->dev; |
2b875c22 | 14262 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 14263 | uint32_t addr; |
852e787c | 14264 | |
f4a2cf29 | 14265 | if (!obj) |
a912f12f | 14266 | addr = 0; |
f4a2cf29 | 14267 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 14268 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 14269 | else |
a912f12f | 14270 | addr = obj->phys_handle->busaddr; |
852e787c | 14271 | |
a912f12f | 14272 | intel_crtc->cursor_addr = addr; |
55a08b3f | 14273 | intel_crtc_update_cursor(crtc, state); |
852e787c GP |
14274 | } |
14275 | ||
3d7d6510 MR |
14276 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
14277 | int pipe) | |
14278 | { | |
14279 | struct intel_plane *cursor; | |
8e7d688b | 14280 | struct intel_plane_state *state; |
3d7d6510 MR |
14281 | |
14282 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
14283 | if (cursor == NULL) | |
14284 | return NULL; | |
14285 | ||
8e7d688b MR |
14286 | state = intel_create_plane_state(&cursor->base); |
14287 | if (!state) { | |
ea2c67bb MR |
14288 | kfree(cursor); |
14289 | return NULL; | |
14290 | } | |
8e7d688b | 14291 | cursor->base.state = &state->base; |
ea2c67bb | 14292 | |
3d7d6510 MR |
14293 | cursor->can_scale = false; |
14294 | cursor->max_downscale = 1; | |
14295 | cursor->pipe = pipe; | |
14296 | cursor->plane = pipe; | |
a9ff8714 | 14297 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 | 14298 | cursor->check_plane = intel_check_cursor_plane; |
55a08b3f | 14299 | cursor->update_plane = intel_update_cursor_plane; |
a8ad0d8e | 14300 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 MR |
14301 | |
14302 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 14303 | &intel_plane_funcs, |
3d7d6510 MR |
14304 | intel_cursor_formats, |
14305 | ARRAY_SIZE(intel_cursor_formats), | |
14306 | DRM_PLANE_TYPE_CURSOR); | |
4398ad45 VS |
14307 | |
14308 | if (INTEL_INFO(dev)->gen >= 4) { | |
14309 | if (!dev->mode_config.rotation_property) | |
14310 | dev->mode_config.rotation_property = | |
14311 | drm_mode_create_rotation_property(dev, | |
14312 | BIT(DRM_ROTATE_0) | | |
14313 | BIT(DRM_ROTATE_180)); | |
14314 | if (dev->mode_config.rotation_property) | |
14315 | drm_object_attach_property(&cursor->base.base, | |
14316 | dev->mode_config.rotation_property, | |
8e7d688b | 14317 | state->base.rotation); |
4398ad45 VS |
14318 | } |
14319 | ||
af99ceda CK |
14320 | if (INTEL_INFO(dev)->gen >=9) |
14321 | state->scaler_id = -1; | |
14322 | ||
ea2c67bb MR |
14323 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
14324 | ||
3d7d6510 MR |
14325 | return &cursor->base; |
14326 | } | |
14327 | ||
549e2bfb CK |
14328 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
14329 | struct intel_crtc_state *crtc_state) | |
14330 | { | |
14331 | int i; | |
14332 | struct intel_scaler *intel_scaler; | |
14333 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
14334 | ||
14335 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
14336 | intel_scaler = &scaler_state->scalers[i]; | |
14337 | intel_scaler->in_use = 0; | |
549e2bfb CK |
14338 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
14339 | } | |
14340 | ||
14341 | scaler_state->scaler_id = -1; | |
14342 | } | |
14343 | ||
b358d0a6 | 14344 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 14345 | { |
fbee40df | 14346 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 14347 | struct intel_crtc *intel_crtc; |
f5de6e07 | 14348 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
14349 | struct drm_plane *primary = NULL; |
14350 | struct drm_plane *cursor = NULL; | |
465c120c | 14351 | int i, ret; |
79e53945 | 14352 | |
955382f3 | 14353 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
14354 | if (intel_crtc == NULL) |
14355 | return; | |
14356 | ||
f5de6e07 ACO |
14357 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
14358 | if (!crtc_state) | |
14359 | goto fail; | |
550acefd ACO |
14360 | intel_crtc->config = crtc_state; |
14361 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 14362 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 14363 | |
549e2bfb CK |
14364 | /* initialize shared scalers */ |
14365 | if (INTEL_INFO(dev)->gen >= 9) { | |
14366 | if (pipe == PIPE_C) | |
14367 | intel_crtc->num_scalers = 1; | |
14368 | else | |
14369 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
14370 | ||
14371 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
14372 | } | |
14373 | ||
465c120c | 14374 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
14375 | if (!primary) |
14376 | goto fail; | |
14377 | ||
14378 | cursor = intel_cursor_plane_create(dev, pipe); | |
14379 | if (!cursor) | |
14380 | goto fail; | |
14381 | ||
465c120c | 14382 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
14383 | cursor, &intel_crtc_funcs); |
14384 | if (ret) | |
14385 | goto fail; | |
79e53945 JB |
14386 | |
14387 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
14388 | for (i = 0; i < 256; i++) { |
14389 | intel_crtc->lut_r[i] = i; | |
14390 | intel_crtc->lut_g[i] = i; | |
14391 | intel_crtc->lut_b[i] = i; | |
14392 | } | |
14393 | ||
1f1c2e24 VS |
14394 | /* |
14395 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 14396 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 14397 | */ |
80824003 JB |
14398 | intel_crtc->pipe = pipe; |
14399 | intel_crtc->plane = pipe; | |
3a77c4c4 | 14400 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 14401 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 14402 | intel_crtc->plane = !pipe; |
80824003 JB |
14403 | } |
14404 | ||
4b0e333e CW |
14405 | intel_crtc->cursor_base = ~0; |
14406 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 14407 | intel_crtc->cursor_size = ~0; |
8d7849db | 14408 | |
852eb00d VS |
14409 | intel_crtc->wm.cxsr_allowed = true; |
14410 | ||
22fd0fab JB |
14411 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
14412 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
14413 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
14414 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
14415 | ||
79e53945 | 14416 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
14417 | |
14418 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
14419 | return; |
14420 | ||
14421 | fail: | |
14422 | if (primary) | |
14423 | drm_plane_cleanup(primary); | |
14424 | if (cursor) | |
14425 | drm_plane_cleanup(cursor); | |
f5de6e07 | 14426 | kfree(crtc_state); |
3d7d6510 | 14427 | kfree(intel_crtc); |
79e53945 JB |
14428 | } |
14429 | ||
752aa88a JB |
14430 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
14431 | { | |
14432 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 14433 | struct drm_device *dev = connector->base.dev; |
752aa88a | 14434 | |
51fd371b | 14435 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 14436 | |
d3babd3f | 14437 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
14438 | return INVALID_PIPE; |
14439 | ||
14440 | return to_intel_crtc(encoder->crtc)->pipe; | |
14441 | } | |
14442 | ||
08d7b3d1 | 14443 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 14444 | struct drm_file *file) |
08d7b3d1 | 14445 | { |
08d7b3d1 | 14446 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 14447 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 14448 | struct intel_crtc *crtc; |
08d7b3d1 | 14449 | |
7707e653 | 14450 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 14451 | |
7707e653 | 14452 | if (!drmmode_crtc) { |
08d7b3d1 | 14453 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 14454 | return -ENOENT; |
08d7b3d1 CW |
14455 | } |
14456 | ||
7707e653 | 14457 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 14458 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 14459 | |
c05422d5 | 14460 | return 0; |
08d7b3d1 CW |
14461 | } |
14462 | ||
66a9278e | 14463 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 14464 | { |
66a9278e DV |
14465 | struct drm_device *dev = encoder->base.dev; |
14466 | struct intel_encoder *source_encoder; | |
79e53945 | 14467 | int index_mask = 0; |
79e53945 JB |
14468 | int entry = 0; |
14469 | ||
b2784e15 | 14470 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 14471 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
14472 | index_mask |= (1 << entry); |
14473 | ||
79e53945 JB |
14474 | entry++; |
14475 | } | |
4ef69c7a | 14476 | |
79e53945 JB |
14477 | return index_mask; |
14478 | } | |
14479 | ||
4d302442 CW |
14480 | static bool has_edp_a(struct drm_device *dev) |
14481 | { | |
14482 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14483 | ||
14484 | if (!IS_MOBILE(dev)) | |
14485 | return false; | |
14486 | ||
14487 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
14488 | return false; | |
14489 | ||
e3589908 | 14490 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
14491 | return false; |
14492 | ||
14493 | return true; | |
14494 | } | |
14495 | ||
84b4e042 JB |
14496 | static bool intel_crt_present(struct drm_device *dev) |
14497 | { | |
14498 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14499 | ||
884497ed DL |
14500 | if (INTEL_INFO(dev)->gen >= 9) |
14501 | return false; | |
14502 | ||
cf404ce4 | 14503 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
14504 | return false; |
14505 | ||
14506 | if (IS_CHERRYVIEW(dev)) | |
14507 | return false; | |
14508 | ||
65e472e4 VS |
14509 | if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) |
14510 | return false; | |
14511 | ||
70ac54d0 VS |
14512 | /* DDI E can't be used if DDI A requires 4 lanes */ |
14513 | if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) | |
14514 | return false; | |
14515 | ||
e4abb733 | 14516 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
14517 | return false; |
14518 | ||
14519 | return true; | |
14520 | } | |
14521 | ||
79e53945 JB |
14522 | static void intel_setup_outputs(struct drm_device *dev) |
14523 | { | |
725e30ad | 14524 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 14525 | struct intel_encoder *encoder; |
cb0953d7 | 14526 | bool dpd_is_edp = false; |
79e53945 | 14527 | |
c9093354 | 14528 | intel_lvds_init(dev); |
79e53945 | 14529 | |
84b4e042 | 14530 | if (intel_crt_present(dev)) |
79935fca | 14531 | intel_crt_init(dev); |
cb0953d7 | 14532 | |
c776eb2e VK |
14533 | if (IS_BROXTON(dev)) { |
14534 | /* | |
14535 | * FIXME: Broxton doesn't support port detection via the | |
14536 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14537 | * detect the ports. | |
14538 | */ | |
14539 | intel_ddi_init(dev, PORT_A); | |
14540 | intel_ddi_init(dev, PORT_B); | |
14541 | intel_ddi_init(dev, PORT_C); | |
14542 | } else if (HAS_DDI(dev)) { | |
0e72a5b5 ED |
14543 | int found; |
14544 | ||
de31facd JB |
14545 | /* |
14546 | * Haswell uses DDI functions to detect digital outputs. | |
14547 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14548 | * it's there. | |
14549 | */ | |
77179400 | 14550 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 14551 | /* WaIgnoreDDIAStrap: skl */ |
ef11bdb3 | 14552 | if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
0e72a5b5 ED |
14553 | intel_ddi_init(dev, PORT_A); |
14554 | ||
14555 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14556 | * register */ | |
14557 | found = I915_READ(SFUSE_STRAP); | |
14558 | ||
14559 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
14560 | intel_ddi_init(dev, PORT_B); | |
14561 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
14562 | intel_ddi_init(dev, PORT_C); | |
14563 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
14564 | intel_ddi_init(dev, PORT_D); | |
2800e4c2 RV |
14565 | /* |
14566 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
14567 | */ | |
ef11bdb3 | 14568 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && |
2800e4c2 RV |
14569 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
14570 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
14571 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
14572 | intel_ddi_init(dev, PORT_E); | |
14573 | ||
0e72a5b5 | 14574 | } else if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 14575 | int found; |
5d8a7752 | 14576 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
14577 | |
14578 | if (has_edp_a(dev)) | |
14579 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 14580 | |
dc0fa718 | 14581 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14582 | /* PCH SDVOB multiplex with HDMIB */ |
2a5c0832 | 14583 | found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); |
30ad48b7 | 14584 | if (!found) |
e2debe91 | 14585 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 14586 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 14587 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14588 | } |
14589 | ||
dc0fa718 | 14590 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 14591 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 14592 | |
dc0fa718 | 14593 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 14594 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 14595 | |
5eb08b69 | 14596 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 14597 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 14598 | |
270b3042 | 14599 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 14600 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
666a4537 | 14601 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
e17ac6db VS |
14602 | /* |
14603 | * The DP_DETECTED bit is the latched state of the DDC | |
14604 | * SDA pin at boot. However since eDP doesn't require DDC | |
14605 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14606 | * eDP ports may have been muxed to an alternate function. | |
14607 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14608 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14609 | * detect eDP ports. | |
14610 | */ | |
e66eb81d | 14611 | if (I915_READ(VLV_HDMIB) & SDVO_DETECTED && |
d2182a66 | 14612 | !intel_dp_is_edp(dev, PORT_B)) |
e66eb81d VS |
14613 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
14614 | if (I915_READ(VLV_DP_B) & DP_DETECTED || | |
e17ac6db | 14615 | intel_dp_is_edp(dev, PORT_B)) |
e66eb81d | 14616 | intel_dp_init(dev, VLV_DP_B, PORT_B); |
585a94b8 | 14617 | |
e66eb81d | 14618 | if (I915_READ(VLV_HDMIC) & SDVO_DETECTED && |
d2182a66 | 14619 | !intel_dp_is_edp(dev, PORT_C)) |
e66eb81d VS |
14620 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
14621 | if (I915_READ(VLV_DP_C) & DP_DETECTED || | |
e17ac6db | 14622 | intel_dp_is_edp(dev, PORT_C)) |
e66eb81d | 14623 | intel_dp_init(dev, VLV_DP_C, PORT_C); |
19c03924 | 14624 | |
9418c1f1 | 14625 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 14626 | /* eDP not supported on port D, so don't check VBT */ |
e66eb81d VS |
14627 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED) |
14628 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); | |
14629 | if (I915_READ(CHV_DP_D) & DP_DETECTED) | |
14630 | intel_dp_init(dev, CHV_DP_D, PORT_D); | |
9418c1f1 VS |
14631 | } |
14632 | ||
3cfca973 | 14633 | intel_dsi_init(dev); |
09da55dc | 14634 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
27185ae1 | 14635 | bool found = false; |
7d57382e | 14636 | |
e2debe91 | 14637 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14638 | DRM_DEBUG_KMS("probing SDVOB\n"); |
2a5c0832 | 14639 | found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B); |
3fec3d2f | 14640 | if (!found && IS_G4X(dev)) { |
b01f2c3a | 14641 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
e2debe91 | 14642 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14643 | } |
27185ae1 | 14644 | |
3fec3d2f | 14645 | if (!found && IS_G4X(dev)) |
ab9d7c30 | 14646 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 14647 | } |
13520b05 KH |
14648 | |
14649 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14650 | |
e2debe91 | 14651 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14652 | DRM_DEBUG_KMS("probing SDVOC\n"); |
2a5c0832 | 14653 | found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); |
b01f2c3a | 14654 | } |
27185ae1 | 14655 | |
e2debe91 | 14656 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14657 | |
3fec3d2f | 14658 | if (IS_G4X(dev)) { |
b01f2c3a | 14659 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
e2debe91 | 14660 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14661 | } |
3fec3d2f | 14662 | if (IS_G4X(dev)) |
ab9d7c30 | 14663 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 14664 | } |
27185ae1 | 14665 | |
3fec3d2f | 14666 | if (IS_G4X(dev) && |
e7281eab | 14667 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 14668 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 14669 | } else if (IS_GEN2(dev)) |
79e53945 JB |
14670 | intel_dvo_init(dev); |
14671 | ||
103a196f | 14672 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
14673 | intel_tv_init(dev); |
14674 | ||
0bc12bcb | 14675 | intel_psr_init(dev); |
7c8f8a70 | 14676 | |
b2784e15 | 14677 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
14678 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14679 | encoder->base.possible_clones = | |
66a9278e | 14680 | intel_encoder_clones(encoder); |
79e53945 | 14681 | } |
47356eb6 | 14682 | |
dde86e2d | 14683 | intel_init_pch_refclk(dev); |
270b3042 DV |
14684 | |
14685 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
14686 | } |
14687 | ||
14688 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14689 | { | |
60a5ca01 | 14690 | struct drm_device *dev = fb->dev; |
79e53945 | 14691 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 14692 | |
ef2d633e | 14693 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 14694 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 14695 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
14696 | drm_gem_object_unreference(&intel_fb->obj->base); |
14697 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14698 | kfree(intel_fb); |
14699 | } | |
14700 | ||
14701 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14702 | struct drm_file *file, |
79e53945 JB |
14703 | unsigned int *handle) |
14704 | { | |
14705 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14706 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14707 | |
cc917ab4 CW |
14708 | if (obj->userptr.mm) { |
14709 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
14710 | return -EINVAL; | |
14711 | } | |
14712 | ||
05394f39 | 14713 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14714 | } |
14715 | ||
86c98588 RV |
14716 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
14717 | struct drm_file *file, | |
14718 | unsigned flags, unsigned color, | |
14719 | struct drm_clip_rect *clips, | |
14720 | unsigned num_clips) | |
14721 | { | |
14722 | struct drm_device *dev = fb->dev; | |
14723 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
14724 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
14725 | ||
14726 | mutex_lock(&dev->struct_mutex); | |
74b4ea1e | 14727 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
14728 | mutex_unlock(&dev->struct_mutex); |
14729 | ||
14730 | return 0; | |
14731 | } | |
14732 | ||
79e53945 JB |
14733 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
14734 | .destroy = intel_user_framebuffer_destroy, | |
14735 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 14736 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
14737 | }; |
14738 | ||
b321803d DL |
14739 | static |
14740 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
14741 | uint32_t pixel_format) | |
14742 | { | |
14743 | u32 gen = INTEL_INFO(dev)->gen; | |
14744 | ||
14745 | if (gen >= 9) { | |
14746 | /* "The stride in bytes must not exceed the of the size of 8K | |
14747 | * pixels and 32K bytes." | |
14748 | */ | |
14749 | return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768); | |
666a4537 | 14750 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
b321803d DL |
14751 | return 32*1024; |
14752 | } else if (gen >= 4) { | |
14753 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14754 | return 16*1024; | |
14755 | else | |
14756 | return 32*1024; | |
14757 | } else if (gen >= 3) { | |
14758 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14759 | return 8*1024; | |
14760 | else | |
14761 | return 16*1024; | |
14762 | } else { | |
14763 | /* XXX DSPC is limited to 4k tiled */ | |
14764 | return 8*1024; | |
14765 | } | |
14766 | } | |
14767 | ||
b5ea642a DV |
14768 | static int intel_framebuffer_init(struct drm_device *dev, |
14769 | struct intel_framebuffer *intel_fb, | |
14770 | struct drm_mode_fb_cmd2 *mode_cmd, | |
14771 | struct drm_i915_gem_object *obj) | |
79e53945 | 14772 | { |
7b49f948 | 14773 | struct drm_i915_private *dev_priv = to_i915(dev); |
6761dd31 | 14774 | unsigned int aligned_height; |
79e53945 | 14775 | int ret; |
b321803d | 14776 | u32 pitch_limit, stride_alignment; |
79e53945 | 14777 | |
dd4916c5 DV |
14778 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
14779 | ||
2a80eada DV |
14780 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
14781 | /* Enforce that fb modifier and tiling mode match, but only for | |
14782 | * X-tiled. This is needed for FBC. */ | |
14783 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
14784 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
14785 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
14786 | return -EINVAL; | |
14787 | } | |
14788 | } else { | |
14789 | if (obj->tiling_mode == I915_TILING_X) | |
14790 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
14791 | else if (obj->tiling_mode == I915_TILING_Y) { | |
14792 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
14793 | return -EINVAL; | |
14794 | } | |
14795 | } | |
14796 | ||
9a8f0a12 TU |
14797 | /* Passed in modifier sanity checking. */ |
14798 | switch (mode_cmd->modifier[0]) { | |
14799 | case I915_FORMAT_MOD_Y_TILED: | |
14800 | case I915_FORMAT_MOD_Yf_TILED: | |
14801 | if (INTEL_INFO(dev)->gen < 9) { | |
14802 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
14803 | mode_cmd->modifier[0]); | |
14804 | return -EINVAL; | |
14805 | } | |
14806 | case DRM_FORMAT_MOD_NONE: | |
14807 | case I915_FORMAT_MOD_X_TILED: | |
14808 | break; | |
14809 | default: | |
c0f40428 JB |
14810 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14811 | mode_cmd->modifier[0]); | |
57cd6508 | 14812 | return -EINVAL; |
c16ed4be | 14813 | } |
57cd6508 | 14814 | |
7b49f948 VS |
14815 | stride_alignment = intel_fb_stride_alignment(dev_priv, |
14816 | mode_cmd->modifier[0], | |
b321803d DL |
14817 | mode_cmd->pixel_format); |
14818 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
14819 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
14820 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 14821 | return -EINVAL; |
c16ed4be | 14822 | } |
57cd6508 | 14823 | |
b321803d DL |
14824 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
14825 | mode_cmd->pixel_format); | |
a35cdaa0 | 14826 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
14827 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
14828 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 14829 | "tiled" : "linear", |
a35cdaa0 | 14830 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 14831 | return -EINVAL; |
c16ed4be | 14832 | } |
5d7bd705 | 14833 | |
2a80eada | 14834 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
14835 | mode_cmd->pitches[0] != obj->stride) { |
14836 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
14837 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 14838 | return -EINVAL; |
c16ed4be | 14839 | } |
5d7bd705 | 14840 | |
57779d06 | 14841 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14842 | switch (mode_cmd->pixel_format) { |
57779d06 | 14843 | case DRM_FORMAT_C8: |
04b3924d VS |
14844 | case DRM_FORMAT_RGB565: |
14845 | case DRM_FORMAT_XRGB8888: | |
14846 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14847 | break; |
14848 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 14849 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
14850 | DRM_DEBUG("unsupported pixel format: %s\n", |
14851 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14852 | return -EINVAL; |
c16ed4be | 14853 | } |
57779d06 | 14854 | break; |
57779d06 | 14855 | case DRM_FORMAT_ABGR8888: |
666a4537 WB |
14856 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
14857 | INTEL_INFO(dev)->gen < 9) { | |
6c0fd451 DL |
14858 | DRM_DEBUG("unsupported pixel format: %s\n", |
14859 | drm_get_format_name(mode_cmd->pixel_format)); | |
14860 | return -EINVAL; | |
14861 | } | |
14862 | break; | |
14863 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 14864 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 14865 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 14866 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
14867 | DRM_DEBUG("unsupported pixel format: %s\n", |
14868 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14869 | return -EINVAL; |
c16ed4be | 14870 | } |
b5626747 | 14871 | break; |
7531208b | 14872 | case DRM_FORMAT_ABGR2101010: |
666a4537 | 14873 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
7531208b DL |
14874 | DRM_DEBUG("unsupported pixel format: %s\n", |
14875 | drm_get_format_name(mode_cmd->pixel_format)); | |
14876 | return -EINVAL; | |
14877 | } | |
14878 | break; | |
04b3924d VS |
14879 | case DRM_FORMAT_YUYV: |
14880 | case DRM_FORMAT_UYVY: | |
14881 | case DRM_FORMAT_YVYU: | |
14882 | case DRM_FORMAT_VYUY: | |
c16ed4be | 14883 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
14884 | DRM_DEBUG("unsupported pixel format: %s\n", |
14885 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14886 | return -EINVAL; |
c16ed4be | 14887 | } |
57cd6508 CW |
14888 | break; |
14889 | default: | |
4ee62c76 VS |
14890 | DRM_DEBUG("unsupported pixel format: %s\n", |
14891 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
14892 | return -EINVAL; |
14893 | } | |
14894 | ||
90f9a336 VS |
14895 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14896 | if (mode_cmd->offsets[0] != 0) | |
14897 | return -EINVAL; | |
14898 | ||
ec2c981e | 14899 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
14900 | mode_cmd->pixel_format, |
14901 | mode_cmd->modifier[0]); | |
53155c0a DV |
14902 | /* FIXME drm helper for size checks (especially planar formats)? */ |
14903 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
14904 | return -EINVAL; | |
14905 | ||
c7d73f6a DV |
14906 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
14907 | intel_fb->obj = obj; | |
80075d49 | 14908 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 14909 | |
79e53945 JB |
14910 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
14911 | if (ret) { | |
14912 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
14913 | return ret; | |
14914 | } | |
14915 | ||
79e53945 JB |
14916 | return 0; |
14917 | } | |
14918 | ||
79e53945 JB |
14919 | static struct drm_framebuffer * |
14920 | intel_user_framebuffer_create(struct drm_device *dev, | |
14921 | struct drm_file *filp, | |
1eb83451 | 14922 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 14923 | { |
dcb1394e | 14924 | struct drm_framebuffer *fb; |
05394f39 | 14925 | struct drm_i915_gem_object *obj; |
76dc3769 | 14926 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 14927 | |
308e5bcb | 14928 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
76dc3769 | 14929 | mode_cmd.handles[0])); |
c8725226 | 14930 | if (&obj->base == NULL) |
cce13ff7 | 14931 | return ERR_PTR(-ENOENT); |
79e53945 | 14932 | |
92907cbb | 14933 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
dcb1394e LW |
14934 | if (IS_ERR(fb)) |
14935 | drm_gem_object_unreference_unlocked(&obj->base); | |
14936 | ||
14937 | return fb; | |
79e53945 JB |
14938 | } |
14939 | ||
0695726e | 14940 | #ifndef CONFIG_DRM_FBDEV_EMULATION |
0632fef6 | 14941 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
14942 | { |
14943 | } | |
14944 | #endif | |
14945 | ||
79e53945 | 14946 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14947 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14948 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14949 | .atomic_check = intel_atomic_check, |
14950 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
14951 | .atomic_state_alloc = intel_atomic_state_alloc, |
14952 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
14953 | }; |
14954 | ||
e70236a8 JB |
14955 | /* Set up chip specific display functions */ |
14956 | static void intel_init_display(struct drm_device *dev) | |
14957 | { | |
14958 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14959 | ||
ee9300bb DV |
14960 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
14961 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
14962 | else if (IS_CHERRYVIEW(dev)) |
14963 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
14964 | else if (IS_VALLEYVIEW(dev)) |
14965 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
14966 | else if (IS_PINEVIEW(dev)) | |
14967 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
14968 | else | |
14969 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
14970 | ||
bc8d7dff DL |
14971 | if (INTEL_INFO(dev)->gen >= 9) { |
14972 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; | |
5724dbd1 DL |
14973 | dev_priv->display.get_initial_plane_config = |
14974 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14975 | dev_priv->display.crtc_compute_clock = |
14976 | haswell_crtc_compute_clock; | |
14977 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14978 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
bc8d7dff | 14979 | } else if (HAS_DDI(dev)) { |
0e8ffe1b | 14980 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14981 | dev_priv->display.get_initial_plane_config = |
14982 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14983 | dev_priv->display.crtc_compute_clock = |
14984 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14985 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14986 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
09b4ddf9 | 14987 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 14988 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14989 | dev_priv->display.get_initial_plane_config = |
14990 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14991 | dev_priv->display.crtc_compute_clock = |
14992 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14993 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14994 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
666a4537 | 14995 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
89b667f8 | 14996 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14997 | dev_priv->display.get_initial_plane_config = |
14998 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14999 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
15000 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
15001 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 15002 | } else { |
0e8ffe1b | 15003 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
15004 | dev_priv->display.get_initial_plane_config = |
15005 | i9xx_get_initial_plane_config; | |
d6dfee7a | 15006 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
15007 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
15008 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 15009 | } |
e70236a8 | 15010 | |
e70236a8 | 15011 | /* Returns the core display clock speed */ |
ef11bdb3 | 15012 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
1652d19e VS |
15013 | dev_priv->display.get_display_clock_speed = |
15014 | skylake_get_display_clock_speed; | |
acd3f3d3 BP |
15015 | else if (IS_BROXTON(dev)) |
15016 | dev_priv->display.get_display_clock_speed = | |
15017 | broxton_get_display_clock_speed; | |
1652d19e VS |
15018 | else if (IS_BROADWELL(dev)) |
15019 | dev_priv->display.get_display_clock_speed = | |
15020 | broadwell_get_display_clock_speed; | |
15021 | else if (IS_HASWELL(dev)) | |
15022 | dev_priv->display.get_display_clock_speed = | |
15023 | haswell_get_display_clock_speed; | |
666a4537 | 15024 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
25eb05fc JB |
15025 | dev_priv->display.get_display_clock_speed = |
15026 | valleyview_get_display_clock_speed; | |
b37a6434 VS |
15027 | else if (IS_GEN5(dev)) |
15028 | dev_priv->display.get_display_clock_speed = | |
15029 | ilk_get_display_clock_speed; | |
a7c66cd8 | 15030 | else if (IS_I945G(dev) || IS_BROADWATER(dev) || |
34edce2f | 15031 | IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
e70236a8 JB |
15032 | dev_priv->display.get_display_clock_speed = |
15033 | i945_get_display_clock_speed; | |
34edce2f VS |
15034 | else if (IS_GM45(dev)) |
15035 | dev_priv->display.get_display_clock_speed = | |
15036 | gm45_get_display_clock_speed; | |
15037 | else if (IS_CRESTLINE(dev)) | |
15038 | dev_priv->display.get_display_clock_speed = | |
15039 | i965gm_get_display_clock_speed; | |
15040 | else if (IS_PINEVIEW(dev)) | |
15041 | dev_priv->display.get_display_clock_speed = | |
15042 | pnv_get_display_clock_speed; | |
15043 | else if (IS_G33(dev) || IS_G4X(dev)) | |
15044 | dev_priv->display.get_display_clock_speed = | |
15045 | g33_get_display_clock_speed; | |
e70236a8 JB |
15046 | else if (IS_I915G(dev)) |
15047 | dev_priv->display.get_display_clock_speed = | |
15048 | i915_get_display_clock_speed; | |
257a7ffc | 15049 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
15050 | dev_priv->display.get_display_clock_speed = |
15051 | i9xx_misc_get_display_clock_speed; | |
15052 | else if (IS_I915GM(dev)) | |
15053 | dev_priv->display.get_display_clock_speed = | |
15054 | i915gm_get_display_clock_speed; | |
15055 | else if (IS_I865G(dev)) | |
15056 | dev_priv->display.get_display_clock_speed = | |
15057 | i865_get_display_clock_speed; | |
f0f8a9ce | 15058 | else if (IS_I85X(dev)) |
e70236a8 | 15059 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 15060 | i85x_get_display_clock_speed; |
623e01e5 VS |
15061 | else { /* 830 */ |
15062 | WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n"); | |
e70236a8 JB |
15063 | dev_priv->display.get_display_clock_speed = |
15064 | i830_get_display_clock_speed; | |
623e01e5 | 15065 | } |
e70236a8 | 15066 | |
7c10a2b5 | 15067 | if (IS_GEN5(dev)) { |
3bb11b53 | 15068 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
15069 | } else if (IS_GEN6(dev)) { |
15070 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
15071 | } else if (IS_IVYBRIDGE(dev)) { |
15072 | /* FIXME: detect B0+ stepping and use auto training */ | |
15073 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
059b2fe9 | 15074 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 15075 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
27c329ed ML |
15076 | if (IS_BROADWELL(dev)) { |
15077 | dev_priv->display.modeset_commit_cdclk = | |
15078 | broadwell_modeset_commit_cdclk; | |
15079 | dev_priv->display.modeset_calc_cdclk = | |
15080 | broadwell_modeset_calc_cdclk; | |
15081 | } | |
666a4537 | 15082 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
27c329ed ML |
15083 | dev_priv->display.modeset_commit_cdclk = |
15084 | valleyview_modeset_commit_cdclk; | |
15085 | dev_priv->display.modeset_calc_cdclk = | |
15086 | valleyview_modeset_calc_cdclk; | |
f8437dd1 | 15087 | } else if (IS_BROXTON(dev)) { |
27c329ed ML |
15088 | dev_priv->display.modeset_commit_cdclk = |
15089 | broxton_modeset_commit_cdclk; | |
15090 | dev_priv->display.modeset_calc_cdclk = | |
15091 | broxton_modeset_calc_cdclk; | |
e70236a8 | 15092 | } |
8c9f3aaf | 15093 | |
8c9f3aaf JB |
15094 | switch (INTEL_INFO(dev)->gen) { |
15095 | case 2: | |
15096 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
15097 | break; | |
15098 | ||
15099 | case 3: | |
15100 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
15101 | break; | |
15102 | ||
15103 | case 4: | |
15104 | case 5: | |
15105 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
15106 | break; | |
15107 | ||
15108 | case 6: | |
15109 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
15110 | break; | |
7c9017e5 | 15111 | case 7: |
4e0bbc31 | 15112 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
15113 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
15114 | break; | |
830c81db | 15115 | case 9: |
ba343e02 TU |
15116 | /* Drop through - unsupported since execlist only. */ |
15117 | default: | |
15118 | /* Default just returns -ENODEV to indicate unsupported */ | |
15119 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 15120 | } |
7bd688cd | 15121 | |
e39b999a | 15122 | mutex_init(&dev_priv->pps_mutex); |
e70236a8 JB |
15123 | } |
15124 | ||
b690e96c JB |
15125 | /* |
15126 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
15127 | * resume, or other times. This quirk makes sure that's the case for | |
15128 | * affected systems. | |
15129 | */ | |
0206e353 | 15130 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
15131 | { |
15132 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15133 | ||
15134 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 15135 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
15136 | } |
15137 | ||
b6b5d049 VS |
15138 | static void quirk_pipeb_force(struct drm_device *dev) |
15139 | { | |
15140 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15141 | ||
15142 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
15143 | DRM_INFO("applying pipe b force quirk\n"); | |
15144 | } | |
15145 | ||
435793df KP |
15146 | /* |
15147 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
15148 | */ | |
15149 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
15150 | { | |
15151 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15152 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 15153 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
15154 | } |
15155 | ||
4dca20ef | 15156 | /* |
5a15ab5b CE |
15157 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
15158 | * brightness value | |
4dca20ef CE |
15159 | */ |
15160 | static void quirk_invert_brightness(struct drm_device *dev) | |
15161 | { | |
15162 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15163 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 15164 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
15165 | } |
15166 | ||
9c72cc6f SD |
15167 | /* Some VBT's incorrectly indicate no backlight is present */ |
15168 | static void quirk_backlight_present(struct drm_device *dev) | |
15169 | { | |
15170 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15171 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
15172 | DRM_INFO("applying backlight present quirk\n"); | |
15173 | } | |
15174 | ||
b690e96c JB |
15175 | struct intel_quirk { |
15176 | int device; | |
15177 | int subsystem_vendor; | |
15178 | int subsystem_device; | |
15179 | void (*hook)(struct drm_device *dev); | |
15180 | }; | |
15181 | ||
5f85f176 EE |
15182 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
15183 | struct intel_dmi_quirk { | |
15184 | void (*hook)(struct drm_device *dev); | |
15185 | const struct dmi_system_id (*dmi_id_list)[]; | |
15186 | }; | |
15187 | ||
15188 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
15189 | { | |
15190 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
15191 | return 1; | |
15192 | } | |
15193 | ||
15194 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
15195 | { | |
15196 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
15197 | { | |
15198 | .callback = intel_dmi_reverse_brightness, | |
15199 | .ident = "NCR Corporation", | |
15200 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
15201 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
15202 | }, | |
15203 | }, | |
15204 | { } /* terminating entry */ | |
15205 | }, | |
15206 | .hook = quirk_invert_brightness, | |
15207 | }, | |
15208 | }; | |
15209 | ||
c43b5634 | 15210 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
15211 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
15212 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
15213 | ||
b690e96c JB |
15214 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
15215 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
15216 | ||
5f080c0f VS |
15217 | /* 830 needs to leave pipe A & dpll A up */ |
15218 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
15219 | ||
b6b5d049 VS |
15220 | /* 830 needs to leave pipe B & dpll B up */ |
15221 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
15222 | ||
435793df KP |
15223 | /* Lenovo U160 cannot use SSC on LVDS */ |
15224 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
15225 | |
15226 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
15227 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 15228 | |
be505f64 AH |
15229 | /* Acer Aspire 5734Z must invert backlight brightness */ |
15230 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
15231 | ||
15232 | /* Acer/eMachines G725 */ | |
15233 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
15234 | ||
15235 | /* Acer/eMachines e725 */ | |
15236 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
15237 | ||
15238 | /* Acer/Packard Bell NCL20 */ | |
15239 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
15240 | ||
15241 | /* Acer Aspire 4736Z */ | |
15242 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
15243 | |
15244 | /* Acer Aspire 5336 */ | |
15245 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
15246 | |
15247 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
15248 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 15249 | |
dfb3d47b SD |
15250 | /* Acer C720 Chromebook (Core i3 4005U) */ |
15251 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
15252 | ||
b2a9601c | 15253 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
15254 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
15255 | ||
1b9448b0 JN |
15256 | /* Apple Macbook 4,1 */ |
15257 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
15258 | ||
d4967d8c SD |
15259 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
15260 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
15261 | |
15262 | /* HP Chromebook 14 (Celeron 2955U) */ | |
15263 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
15264 | |
15265 | /* Dell Chromebook 11 */ | |
15266 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
15267 | |
15268 | /* Dell Chromebook 11 (2015 version) */ | |
15269 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
15270 | }; |
15271 | ||
15272 | static void intel_init_quirks(struct drm_device *dev) | |
15273 | { | |
15274 | struct pci_dev *d = dev->pdev; | |
15275 | int i; | |
15276 | ||
15277 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
15278 | struct intel_quirk *q = &intel_quirks[i]; | |
15279 | ||
15280 | if (d->device == q->device && | |
15281 | (d->subsystem_vendor == q->subsystem_vendor || | |
15282 | q->subsystem_vendor == PCI_ANY_ID) && | |
15283 | (d->subsystem_device == q->subsystem_device || | |
15284 | q->subsystem_device == PCI_ANY_ID)) | |
15285 | q->hook(dev); | |
15286 | } | |
5f85f176 EE |
15287 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
15288 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
15289 | intel_dmi_quirks[i].hook(dev); | |
15290 | } | |
b690e96c JB |
15291 | } |
15292 | ||
9cce37f4 JB |
15293 | /* Disable the VGA plane that we never use */ |
15294 | static void i915_disable_vga(struct drm_device *dev) | |
15295 | { | |
15296 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15297 | u8 sr1; | |
f0f59a00 | 15298 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 15299 | |
2b37c616 | 15300 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 15301 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 15302 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
15303 | sr1 = inb(VGA_SR_DATA); |
15304 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
15305 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
15306 | udelay(300); | |
15307 | ||
01f5a626 | 15308 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
15309 | POSTING_READ(vga_reg); |
15310 | } | |
15311 | ||
f817586c DV |
15312 | void intel_modeset_init_hw(struct drm_device *dev) |
15313 | { | |
1a617b77 ML |
15314 | struct drm_i915_private *dev_priv = dev->dev_private; |
15315 | ||
b6283055 | 15316 | intel_update_cdclk(dev); |
1a617b77 ML |
15317 | |
15318 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; | |
15319 | ||
f817586c | 15320 | intel_init_clock_gating(dev); |
8090c6b9 | 15321 | intel_enable_gt_powersave(dev); |
f817586c DV |
15322 | } |
15323 | ||
d93c0372 MR |
15324 | /* |
15325 | * Calculate what we think the watermarks should be for the state we've read | |
15326 | * out of the hardware and then immediately program those watermarks so that | |
15327 | * we ensure the hardware settings match our internal state. | |
15328 | * | |
15329 | * We can calculate what we think WM's should be by creating a duplicate of the | |
15330 | * current state (which was constructed during hardware readout) and running it | |
15331 | * through the atomic check code to calculate new watermark values in the | |
15332 | * state object. | |
15333 | */ | |
15334 | static void sanitize_watermarks(struct drm_device *dev) | |
15335 | { | |
15336 | struct drm_i915_private *dev_priv = to_i915(dev); | |
15337 | struct drm_atomic_state *state; | |
15338 | struct drm_crtc *crtc; | |
15339 | struct drm_crtc_state *cstate; | |
15340 | struct drm_modeset_acquire_ctx ctx; | |
15341 | int ret; | |
15342 | int i; | |
15343 | ||
15344 | /* Only supported on platforms that use atomic watermark design */ | |
396e33ae | 15345 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
15346 | return; |
15347 | ||
15348 | /* | |
15349 | * We need to hold connection_mutex before calling duplicate_state so | |
15350 | * that the connector loop is protected. | |
15351 | */ | |
15352 | drm_modeset_acquire_init(&ctx, 0); | |
15353 | retry: | |
0cd1262d | 15354 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
15355 | if (ret == -EDEADLK) { |
15356 | drm_modeset_backoff(&ctx); | |
15357 | goto retry; | |
15358 | } else if (WARN_ON(ret)) { | |
0cd1262d | 15359 | goto fail; |
d93c0372 MR |
15360 | } |
15361 | ||
15362 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
15363 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 15364 | goto fail; |
d93c0372 | 15365 | |
396e33ae MR |
15366 | /* |
15367 | * Hardware readout is the only time we don't want to calculate | |
15368 | * intermediate watermarks (since we don't trust the current | |
15369 | * watermarks). | |
15370 | */ | |
15371 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
15372 | ||
d93c0372 MR |
15373 | ret = intel_atomic_check(dev, state); |
15374 | if (ret) { | |
15375 | /* | |
15376 | * If we fail here, it means that the hardware appears to be | |
15377 | * programmed in a way that shouldn't be possible, given our | |
15378 | * understanding of watermark requirements. This might mean a | |
15379 | * mistake in the hardware readout code or a mistake in the | |
15380 | * watermark calculations for a given platform. Raise a WARN | |
15381 | * so that this is noticeable. | |
15382 | * | |
15383 | * If this actually happens, we'll have to just leave the | |
15384 | * BIOS-programmed watermarks untouched and hope for the best. | |
15385 | */ | |
15386 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
0cd1262d | 15387 | goto fail; |
d93c0372 MR |
15388 | } |
15389 | ||
15390 | /* Write calculated watermark values back */ | |
15391 | to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config; | |
15392 | for_each_crtc_in_state(state, crtc, cstate, i) { | |
15393 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); | |
15394 | ||
396e33ae MR |
15395 | cs->wm.need_postvbl_update = true; |
15396 | dev_priv->display.optimize_watermarks(cs); | |
d93c0372 MR |
15397 | } |
15398 | ||
15399 | drm_atomic_state_free(state); | |
0cd1262d | 15400 | fail: |
d93c0372 MR |
15401 | drm_modeset_drop_locks(&ctx); |
15402 | drm_modeset_acquire_fini(&ctx); | |
15403 | } | |
15404 | ||
79e53945 JB |
15405 | void intel_modeset_init(struct drm_device *dev) |
15406 | { | |
652c393a | 15407 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 15408 | int sprite, ret; |
8cc87b75 | 15409 | enum pipe pipe; |
46f297fb | 15410 | struct intel_crtc *crtc; |
79e53945 JB |
15411 | |
15412 | drm_mode_config_init(dev); | |
15413 | ||
15414 | dev->mode_config.min_width = 0; | |
15415 | dev->mode_config.min_height = 0; | |
15416 | ||
019d96cb DA |
15417 | dev->mode_config.preferred_depth = 24; |
15418 | dev->mode_config.prefer_shadow = 1; | |
15419 | ||
25bab385 TU |
15420 | dev->mode_config.allow_fb_modifiers = true; |
15421 | ||
e6ecefaa | 15422 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 15423 | |
b690e96c JB |
15424 | intel_init_quirks(dev); |
15425 | ||
1fa61106 ED |
15426 | intel_init_pm(dev); |
15427 | ||
e3c74757 BW |
15428 | if (INTEL_INFO(dev)->num_pipes == 0) |
15429 | return; | |
15430 | ||
69f92f67 LW |
15431 | /* |
15432 | * There may be no VBT; and if the BIOS enabled SSC we can | |
15433 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
15434 | * BIOS isn't using it, don't assume it will work even if the VBT | |
15435 | * indicates as much. | |
15436 | */ | |
15437 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { | |
15438 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
15439 | DREF_SSC1_ENABLE); | |
15440 | ||
15441 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
15442 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
15443 | bios_lvds_use_ssc ? "en" : "dis", | |
15444 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
15445 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
15446 | } | |
15447 | } | |
15448 | ||
e70236a8 | 15449 | intel_init_display(dev); |
7c10a2b5 | 15450 | intel_init_audio(dev); |
e70236a8 | 15451 | |
a6c45cf0 CW |
15452 | if (IS_GEN2(dev)) { |
15453 | dev->mode_config.max_width = 2048; | |
15454 | dev->mode_config.max_height = 2048; | |
15455 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
15456 | dev->mode_config.max_width = 4096; |
15457 | dev->mode_config.max_height = 4096; | |
79e53945 | 15458 | } else { |
a6c45cf0 CW |
15459 | dev->mode_config.max_width = 8192; |
15460 | dev->mode_config.max_height = 8192; | |
79e53945 | 15461 | } |
068be561 | 15462 | |
dc41c154 VS |
15463 | if (IS_845G(dev) || IS_I865G(dev)) { |
15464 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
15465 | dev->mode_config.cursor_height = 1023; | |
15466 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
15467 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
15468 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
15469 | } else { | |
15470 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
15471 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
15472 | } | |
15473 | ||
5d4545ae | 15474 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 15475 | |
28c97730 | 15476 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
15477 | INTEL_INFO(dev)->num_pipes, |
15478 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 15479 | |
055e393f | 15480 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 15481 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 15482 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 15483 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 15484 | if (ret) |
06da8da2 | 15485 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 15486 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 15487 | } |
79e53945 JB |
15488 | } |
15489 | ||
bfa7df01 VS |
15490 | intel_update_czclk(dev_priv); |
15491 | intel_update_cdclk(dev); | |
15492 | ||
e72f9fbf | 15493 | intel_shared_dpll_init(dev); |
ee7b9f93 | 15494 | |
9cce37f4 JB |
15495 | /* Just disable it once at startup */ |
15496 | i915_disable_vga(dev); | |
79e53945 | 15497 | intel_setup_outputs(dev); |
11be49eb | 15498 | |
6e9f798d | 15499 | drm_modeset_lock_all(dev); |
043e9bda | 15500 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 15501 | drm_modeset_unlock_all(dev); |
46f297fb | 15502 | |
d3fcc808 | 15503 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
15504 | struct intel_initial_plane_config plane_config = {}; |
15505 | ||
46f297fb JB |
15506 | if (!crtc->active) |
15507 | continue; | |
15508 | ||
46f297fb | 15509 | /* |
46f297fb JB |
15510 | * Note that reserving the BIOS fb up front prevents us |
15511 | * from stuffing other stolen allocations like the ring | |
15512 | * on top. This prevents some ugliness at boot time, and | |
15513 | * can even allow for smooth boot transitions if the BIOS | |
15514 | * fb is large enough for the active pipe configuration. | |
15515 | */ | |
eeebeac5 ML |
15516 | dev_priv->display.get_initial_plane_config(crtc, |
15517 | &plane_config); | |
15518 | ||
15519 | /* | |
15520 | * If the fb is shared between multiple heads, we'll | |
15521 | * just get the first one. | |
15522 | */ | |
15523 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 15524 | } |
d93c0372 MR |
15525 | |
15526 | /* | |
15527 | * Make sure hardware watermarks really match the state we read out. | |
15528 | * Note that we need to do this after reconstructing the BIOS fb's | |
15529 | * since the watermark calculation done here will use pstate->fb. | |
15530 | */ | |
15531 | sanitize_watermarks(dev); | |
2c7111db CW |
15532 | } |
15533 | ||
7fad798e DV |
15534 | static void intel_enable_pipe_a(struct drm_device *dev) |
15535 | { | |
15536 | struct intel_connector *connector; | |
15537 | struct drm_connector *crt = NULL; | |
15538 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 15539 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
15540 | |
15541 | /* We can't just switch on the pipe A, we need to set things up with a | |
15542 | * proper mode and output configuration. As a gross hack, enable pipe A | |
15543 | * by enabling the load detect pipe once. */ | |
3a3371ff | 15544 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
15545 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
15546 | crt = &connector->base; | |
15547 | break; | |
15548 | } | |
15549 | } | |
15550 | ||
15551 | if (!crt) | |
15552 | return; | |
15553 | ||
208bf9fd | 15554 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 15555 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
15556 | } |
15557 | ||
fa555837 DV |
15558 | static bool |
15559 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15560 | { | |
7eb552ae BW |
15561 | struct drm_device *dev = crtc->base.dev; |
15562 | struct drm_i915_private *dev_priv = dev->dev_private; | |
649636ef | 15563 | u32 val; |
fa555837 | 15564 | |
7eb552ae | 15565 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
15566 | return true; |
15567 | ||
649636ef | 15568 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
15569 | |
15570 | if ((val & DISPLAY_PLANE_ENABLE) && | |
15571 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
15572 | return false; | |
15573 | ||
15574 | return true; | |
15575 | } | |
15576 | ||
02e93c35 VS |
15577 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
15578 | { | |
15579 | struct drm_device *dev = crtc->base.dev; | |
15580 | struct intel_encoder *encoder; | |
15581 | ||
15582 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
15583 | return true; | |
15584 | ||
15585 | return false; | |
15586 | } | |
15587 | ||
24929352 DV |
15588 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15589 | { | |
15590 | struct drm_device *dev = crtc->base.dev; | |
15591 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 15592 | i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder); |
24929352 | 15593 | |
24929352 | 15594 | /* Clear any frame start delays used for debugging left by the BIOS */ |
24929352 DV |
15595 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
15596 | ||
d3eaf884 | 15597 | /* restore vblank interrupts to correct state */ |
9625604c | 15598 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 15599 | if (crtc->active) { |
f9cd7b88 VS |
15600 | struct intel_plane *plane; |
15601 | ||
9625604c | 15602 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
15603 | |
15604 | /* Disable everything but the primary plane */ | |
15605 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
15606 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
15607 | continue; | |
15608 | ||
15609 | plane->disable_plane(&plane->base, &crtc->base); | |
15610 | } | |
9625604c | 15611 | } |
d3eaf884 | 15612 | |
24929352 | 15613 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
15614 | * disable the crtc (and hence change the state) if it is wrong. Note |
15615 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
15616 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
15617 | bool plane; |
15618 | ||
24929352 DV |
15619 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
15620 | crtc->base.base.id); | |
15621 | ||
15622 | /* Pipe has the wrong plane attached and the plane is active. | |
15623 | * Temporarily change the plane mapping and disable everything | |
15624 | * ... */ | |
15625 | plane = crtc->plane; | |
b70709a6 | 15626 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 15627 | crtc->plane = !plane; |
b17d48e2 | 15628 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15629 | crtc->plane = plane; |
24929352 | 15630 | } |
24929352 | 15631 | |
7fad798e DV |
15632 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
15633 | crtc->pipe == PIPE_A && !crtc->active) { | |
15634 | /* BIOS forgot to enable pipe A, this mostly happens after | |
15635 | * resume. Force-enable the pipe to fix this, the update_dpms | |
15636 | * call below we restore the pipe to the right state, but leave | |
15637 | * the required bits on. */ | |
15638 | intel_enable_pipe_a(dev); | |
15639 | } | |
15640 | ||
24929352 DV |
15641 | /* Adjust the state of the output pipe according to whether we |
15642 | * have active connectors/encoders. */ | |
02e93c35 | 15643 | if (!intel_crtc_has_encoders(crtc)) |
b17d48e2 | 15644 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15645 | |
53d9f4e9 | 15646 | if (crtc->active != crtc->base.state->active) { |
02e93c35 | 15647 | struct intel_encoder *encoder; |
24929352 DV |
15648 | |
15649 | /* This can happen either due to bugs in the get_hw_state | |
b17d48e2 ML |
15650 | * functions or because of calls to intel_crtc_disable_noatomic, |
15651 | * or because the pipe is force-enabled due to the | |
24929352 DV |
15652 | * pipe A quirk. */ |
15653 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
15654 | crtc->base.base.id, | |
83d65738 | 15655 | crtc->base.state->enable ? "enabled" : "disabled", |
24929352 DV |
15656 | crtc->active ? "enabled" : "disabled"); |
15657 | ||
4be40c98 | 15658 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0); |
49d6fa21 | 15659 | crtc->base.state->active = crtc->active; |
24929352 DV |
15660 | crtc->base.enabled = crtc->active; |
15661 | ||
15662 | /* Because we only establish the connector -> encoder -> | |
15663 | * crtc links if something is active, this means the | |
15664 | * crtc is now deactivated. Break the links. connector | |
15665 | * -> encoder links are only establish when things are | |
15666 | * actually up, hence no need to break them. */ | |
15667 | WARN_ON(crtc->active); | |
15668 | ||
2d406bb0 | 15669 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
24929352 | 15670 | encoder->base.crtc = NULL; |
24929352 | 15671 | } |
c5ab3bc0 | 15672 | |
a3ed6aad | 15673 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
15674 | /* |
15675 | * We start out with underrun reporting disabled to avoid races. | |
15676 | * For correct bookkeeping mark this on active crtcs. | |
15677 | * | |
c5ab3bc0 DV |
15678 | * Also on gmch platforms we dont have any hardware bits to |
15679 | * disable the underrun reporting. Which means we need to start | |
15680 | * out with underrun reporting disabled also on inactive pipes, | |
15681 | * since otherwise we'll complain about the garbage we read when | |
15682 | * e.g. coming up after runtime pm. | |
15683 | * | |
4cc31489 DV |
15684 | * No protection against concurrent access is required - at |
15685 | * worst a fifo underrun happens which also sets this to false. | |
15686 | */ | |
15687 | crtc->cpu_fifo_underrun_disabled = true; | |
15688 | crtc->pch_fifo_underrun_disabled = true; | |
15689 | } | |
24929352 DV |
15690 | } |
15691 | ||
15692 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15693 | { | |
15694 | struct intel_connector *connector; | |
15695 | struct drm_device *dev = encoder->base.dev; | |
873ffe69 | 15696 | bool active = false; |
24929352 DV |
15697 | |
15698 | /* We need to check both for a crtc link (meaning that the | |
15699 | * encoder is active and trying to read from a pipe) and the | |
15700 | * pipe itself being active. */ | |
15701 | bool has_active_crtc = encoder->base.crtc && | |
15702 | to_intel_crtc(encoder->base.crtc)->active; | |
15703 | ||
873ffe69 ML |
15704 | for_each_intel_connector(dev, connector) { |
15705 | if (connector->base.encoder != &encoder->base) | |
15706 | continue; | |
15707 | ||
15708 | active = true; | |
15709 | break; | |
15710 | } | |
15711 | ||
15712 | if (active && !has_active_crtc) { | |
24929352 DV |
15713 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
15714 | encoder->base.base.id, | |
8e329a03 | 15715 | encoder->base.name); |
24929352 DV |
15716 | |
15717 | /* Connector is active, but has no active pipe. This is | |
15718 | * fallout from our resume register restoring. Disable | |
15719 | * the encoder manually again. */ | |
15720 | if (encoder->base.crtc) { | |
15721 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
15722 | encoder->base.base.id, | |
8e329a03 | 15723 | encoder->base.name); |
24929352 | 15724 | encoder->disable(encoder); |
a62d1497 VS |
15725 | if (encoder->post_disable) |
15726 | encoder->post_disable(encoder); | |
24929352 | 15727 | } |
7f1950fb | 15728 | encoder->base.crtc = NULL; |
24929352 DV |
15729 | |
15730 | /* Inconsistent output/port/pipe state happens presumably due to | |
15731 | * a bug in one of the get_hw_state functions. Or someplace else | |
15732 | * in our code, like the register restore mess on resume. Clamp | |
15733 | * things to off as a safer default. */ | |
3a3371ff | 15734 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15735 | if (connector->encoder != encoder) |
15736 | continue; | |
7f1950fb EE |
15737 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
15738 | connector->base.encoder = NULL; | |
24929352 DV |
15739 | } |
15740 | } | |
15741 | /* Enabled encoders without active connectors will be fixed in | |
15742 | * the crtc fixup. */ | |
15743 | } | |
15744 | ||
04098753 | 15745 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
15746 | { |
15747 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 15748 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 15749 | |
04098753 ID |
15750 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15751 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
15752 | i915_disable_vga(dev); | |
15753 | } | |
15754 | } | |
15755 | ||
15756 | void i915_redisable_vga(struct drm_device *dev) | |
15757 | { | |
15758 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15759 | ||
8dc8a27c PZ |
15760 | /* This function can be called both from intel_modeset_setup_hw_state or |
15761 | * at a very early point in our resume sequence, where the power well | |
15762 | * structures are not yet restored. Since this function is at a very | |
15763 | * paranoid "someone might have enabled VGA while we were not looking" | |
15764 | * level, just check if the power well is enabled instead of trying to | |
15765 | * follow the "don't touch the power well if we don't need it" policy | |
15766 | * the rest of the driver uses. */ | |
f458ebbc | 15767 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15768 | return; |
15769 | ||
04098753 | 15770 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
15771 | } |
15772 | ||
f9cd7b88 | 15773 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 15774 | { |
f9cd7b88 | 15775 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 15776 | |
f9cd7b88 | 15777 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
15778 | } |
15779 | ||
f9cd7b88 VS |
15780 | /* FIXME read out full plane state for all planes */ |
15781 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 15782 | { |
b26d3ea3 | 15783 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 15784 | struct intel_plane_state *plane_state = |
b26d3ea3 | 15785 | to_intel_plane_state(primary->state); |
d032ffa0 | 15786 | |
19b8d387 | 15787 | plane_state->visible = crtc->active && |
b26d3ea3 ML |
15788 | primary_get_hw_state(to_intel_plane(primary)); |
15789 | ||
15790 | if (plane_state->visible) | |
15791 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); | |
98ec7739 VS |
15792 | } |
15793 | ||
30e984df | 15794 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
15795 | { |
15796 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15797 | enum pipe pipe; | |
24929352 DV |
15798 | struct intel_crtc *crtc; |
15799 | struct intel_encoder *encoder; | |
15800 | struct intel_connector *connector; | |
5358901f | 15801 | int i; |
24929352 | 15802 | |
565602d7 ML |
15803 | dev_priv->active_crtcs = 0; |
15804 | ||
d3fcc808 | 15805 | for_each_intel_crtc(dev, crtc) { |
565602d7 ML |
15806 | struct intel_crtc_state *crtc_state = crtc->config; |
15807 | int pixclk = 0; | |
3b117c8f | 15808 | |
565602d7 ML |
15809 | __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base); |
15810 | memset(crtc_state, 0, sizeof(*crtc_state)); | |
15811 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 15812 | |
565602d7 ML |
15813 | crtc_state->base.active = crtc_state->base.enable = |
15814 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
15815 | ||
15816 | crtc->base.enabled = crtc_state->base.enable; | |
15817 | crtc->active = crtc_state->base.active; | |
15818 | ||
15819 | if (crtc_state->base.active) { | |
15820 | dev_priv->active_crtcs |= 1 << crtc->pipe; | |
15821 | ||
15822 | if (IS_BROADWELL(dev_priv)) { | |
15823 | pixclk = ilk_pipe_pixel_rate(crtc_state); | |
15824 | ||
15825 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
15826 | if (crtc_state->ips_enabled) | |
15827 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); | |
15828 | } else if (IS_VALLEYVIEW(dev_priv) || | |
15829 | IS_CHERRYVIEW(dev_priv) || | |
15830 | IS_BROXTON(dev_priv)) | |
15831 | pixclk = crtc_state->base.adjusted_mode.crtc_clock; | |
15832 | else | |
15833 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
15834 | } | |
15835 | ||
15836 | dev_priv->min_pixclk[crtc->pipe] = pixclk; | |
b70709a6 | 15837 | |
f9cd7b88 | 15838 | readout_plane_state(crtc); |
24929352 DV |
15839 | |
15840 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
15841 | crtc->base.base.id, | |
15842 | crtc->active ? "enabled" : "disabled"); | |
15843 | } | |
15844 | ||
5358901f DV |
15845 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15846 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15847 | ||
3e369b76 ACO |
15848 | pll->on = pll->get_hw_state(dev_priv, pll, |
15849 | &pll->config.hw_state); | |
5358901f | 15850 | pll->active = 0; |
3e369b76 | 15851 | pll->config.crtc_mask = 0; |
d3fcc808 | 15852 | for_each_intel_crtc(dev, crtc) { |
1e6f2ddc | 15853 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
5358901f | 15854 | pll->active++; |
3e369b76 | 15855 | pll->config.crtc_mask |= 1 << crtc->pipe; |
1e6f2ddc | 15856 | } |
5358901f | 15857 | } |
5358901f | 15858 | |
1e6f2ddc | 15859 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 15860 | pll->name, pll->config.crtc_mask, pll->on); |
bd2bb1b9 | 15861 | |
3e369b76 | 15862 | if (pll->config.crtc_mask) |
bd2bb1b9 | 15863 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
15864 | } |
15865 | ||
b2784e15 | 15866 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15867 | pipe = 0; |
15868 | ||
15869 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
15870 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15871 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 15872 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
15873 | } else { |
15874 | encoder->base.crtc = NULL; | |
15875 | } | |
15876 | ||
6f2bcceb | 15877 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 15878 | encoder->base.base.id, |
8e329a03 | 15879 | encoder->base.name, |
24929352 | 15880 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 15881 | pipe_name(pipe)); |
24929352 DV |
15882 | } |
15883 | ||
3a3371ff | 15884 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15885 | if (connector->get_hw_state(connector)) { |
15886 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
24929352 DV |
15887 | connector->base.encoder = &connector->encoder->base; |
15888 | } else { | |
15889 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15890 | connector->base.encoder = NULL; | |
15891 | } | |
15892 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
15893 | connector->base.base.id, | |
c23cc417 | 15894 | connector->base.name, |
24929352 DV |
15895 | connector->base.encoder ? "enabled" : "disabled"); |
15896 | } | |
7f4c6284 VS |
15897 | |
15898 | for_each_intel_crtc(dev, crtc) { | |
15899 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
15900 | ||
15901 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
15902 | if (crtc->base.state->active) { | |
15903 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
15904 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
15905 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
15906 | ||
15907 | /* | |
15908 | * The initial mode needs to be set in order to keep | |
15909 | * the atomic core happy. It wants a valid mode if the | |
15910 | * crtc's enabled, so we do the above call. | |
15911 | * | |
15912 | * At this point some state updated by the connectors | |
15913 | * in their ->detect() callback has not run yet, so | |
15914 | * no recalculation can be done yet. | |
15915 | * | |
15916 | * Even if we could do a recalculation and modeset | |
15917 | * right now it would cause a double modeset if | |
15918 | * fbdev or userspace chooses a different initial mode. | |
15919 | * | |
15920 | * If that happens, someone indicated they wanted a | |
15921 | * mode change, which means it's safe to do a full | |
15922 | * recalculation. | |
15923 | */ | |
15924 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
15925 | |
15926 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
15927 | update_scanline_offset(crtc); | |
7f4c6284 VS |
15928 | } |
15929 | } | |
30e984df DV |
15930 | } |
15931 | ||
043e9bda ML |
15932 | /* Scan out the current hw modeset state, |
15933 | * and sanitizes it to the current state | |
15934 | */ | |
15935 | static void | |
15936 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df DV |
15937 | { |
15938 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15939 | enum pipe pipe; | |
30e984df DV |
15940 | struct intel_crtc *crtc; |
15941 | struct intel_encoder *encoder; | |
35c95375 | 15942 | int i; |
30e984df DV |
15943 | |
15944 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
15945 | |
15946 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 15947 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15948 | intel_sanitize_encoder(encoder); |
15949 | } | |
15950 | ||
055e393f | 15951 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
15952 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15953 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
15954 | intel_dump_pipe_config(crtc, crtc->config, |
15955 | "[setup_hw_state]"); | |
24929352 | 15956 | } |
9a935856 | 15957 | |
d29b2f9d ACO |
15958 | intel_modeset_update_connector_atomic_state(dev); |
15959 | ||
35c95375 DV |
15960 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15961 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15962 | ||
15963 | if (!pll->on || pll->active) | |
15964 | continue; | |
15965 | ||
15966 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15967 | ||
15968 | pll->disable(dev_priv, pll); | |
15969 | pll->on = false; | |
15970 | } | |
15971 | ||
666a4537 | 15972 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6eb1a681 VS |
15973 | vlv_wm_get_hw_state(dev); |
15974 | else if (IS_GEN9(dev)) | |
3078999f PB |
15975 | skl_wm_get_hw_state(dev); |
15976 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 | 15977 | ilk_wm_get_hw_state(dev); |
292b990e ML |
15978 | |
15979 | for_each_intel_crtc(dev, crtc) { | |
15980 | unsigned long put_domains; | |
15981 | ||
15982 | put_domains = modeset_get_crtc_power_domains(&crtc->base); | |
15983 | if (WARN_ON(put_domains)) | |
15984 | modeset_put_power_domains(dev_priv, put_domains); | |
15985 | } | |
15986 | intel_display_set_init_power(dev_priv, false); | |
043e9bda | 15987 | } |
7d0bc1ea | 15988 | |
043e9bda ML |
15989 | void intel_display_resume(struct drm_device *dev) |
15990 | { | |
15991 | struct drm_atomic_state *state = drm_atomic_state_alloc(dev); | |
15992 | struct intel_connector *conn; | |
15993 | struct intel_plane *plane; | |
15994 | struct drm_crtc *crtc; | |
15995 | int ret; | |
f30da187 | 15996 | |
043e9bda ML |
15997 | if (!state) |
15998 | return; | |
15999 | ||
16000 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
16001 | ||
16002 | /* preserve complete old state, including dpll */ | |
16003 | intel_atomic_get_shared_dpll_state(state); | |
16004 | ||
16005 | for_each_crtc(dev, crtc) { | |
16006 | struct drm_crtc_state *crtc_state = | |
16007 | drm_atomic_get_crtc_state(state, crtc); | |
16008 | ||
16009 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
16010 | if (ret) | |
16011 | goto err; | |
16012 | ||
16013 | /* force a restore */ | |
16014 | crtc_state->mode_changed = true; | |
45e2b5f6 | 16015 | } |
8af6cf88 | 16016 | |
043e9bda ML |
16017 | for_each_intel_plane(dev, plane) { |
16018 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base)); | |
16019 | if (ret) | |
16020 | goto err; | |
16021 | } | |
16022 | ||
16023 | for_each_intel_connector(dev, conn) { | |
16024 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base)); | |
16025 | if (ret) | |
16026 | goto err; | |
16027 | } | |
16028 | ||
16029 | intel_modeset_setup_hw_state(dev); | |
16030 | ||
16031 | i915_redisable_vga(dev); | |
74c090b1 | 16032 | ret = drm_atomic_commit(state); |
043e9bda ML |
16033 | if (!ret) |
16034 | return; | |
16035 | ||
16036 | err: | |
16037 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
16038 | drm_atomic_state_free(state); | |
2c7111db CW |
16039 | } |
16040 | ||
16041 | void intel_modeset_gem_init(struct drm_device *dev) | |
16042 | { | |
484b41dd | 16043 | struct drm_crtc *c; |
2ff8fde1 | 16044 | struct drm_i915_gem_object *obj; |
e0d6149b | 16045 | int ret; |
484b41dd | 16046 | |
ae48434c ID |
16047 | mutex_lock(&dev->struct_mutex); |
16048 | intel_init_gt_powersave(dev); | |
16049 | mutex_unlock(&dev->struct_mutex); | |
16050 | ||
1833b134 | 16051 | intel_modeset_init_hw(dev); |
02e792fb DV |
16052 | |
16053 | intel_setup_overlay(dev); | |
484b41dd JB |
16054 | |
16055 | /* | |
16056 | * Make sure any fbs we allocated at startup are properly | |
16057 | * pinned & fenced. When we do the allocation it's too early | |
16058 | * for this. | |
16059 | */ | |
70e1e0ec | 16060 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
16061 | obj = intel_fb_obj(c->primary->fb); |
16062 | if (obj == NULL) | |
484b41dd JB |
16063 | continue; |
16064 | ||
e0d6149b TU |
16065 | mutex_lock(&dev->struct_mutex); |
16066 | ret = intel_pin_and_fence_fb_obj(c->primary, | |
16067 | c->primary->fb, | |
7580d774 | 16068 | c->primary->state); |
e0d6149b TU |
16069 | mutex_unlock(&dev->struct_mutex); |
16070 | if (ret) { | |
484b41dd JB |
16071 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
16072 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
16073 | drm_framebuffer_unreference(c->primary->fb); |
16074 | c->primary->fb = NULL; | |
36750f28 | 16075 | c->primary->crtc = c->primary->state->crtc = NULL; |
afd65eb4 | 16076 | update_state_fb(c->primary); |
36750f28 | 16077 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
16078 | } |
16079 | } | |
0962c3c9 VS |
16080 | |
16081 | intel_backlight_register(dev); | |
79e53945 JB |
16082 | } |
16083 | ||
4932e2c3 ID |
16084 | void intel_connector_unregister(struct intel_connector *intel_connector) |
16085 | { | |
16086 | struct drm_connector *connector = &intel_connector->base; | |
16087 | ||
16088 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 16089 | drm_connector_unregister(connector); |
4932e2c3 ID |
16090 | } |
16091 | ||
79e53945 JB |
16092 | void intel_modeset_cleanup(struct drm_device *dev) |
16093 | { | |
652c393a | 16094 | struct drm_i915_private *dev_priv = dev->dev_private; |
19c8054c | 16095 | struct intel_connector *connector; |
652c393a | 16096 | |
2eb5252e ID |
16097 | intel_disable_gt_powersave(dev); |
16098 | ||
0962c3c9 VS |
16099 | intel_backlight_unregister(dev); |
16100 | ||
fd0c0642 DV |
16101 | /* |
16102 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 16103 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
16104 | * experience fancy races otherwise. |
16105 | */ | |
2aeb7d3a | 16106 | intel_irq_uninstall(dev_priv); |
eb21b92b | 16107 | |
fd0c0642 DV |
16108 | /* |
16109 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
16110 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
16111 | */ | |
f87ea761 | 16112 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 16113 | |
723bfd70 JB |
16114 | intel_unregister_dsm_handler(); |
16115 | ||
7733b49b | 16116 | intel_fbc_disable(dev_priv); |
69341a5e | 16117 | |
1630fe75 CW |
16118 | /* flush any delayed tasks or pending work */ |
16119 | flush_scheduled_work(); | |
16120 | ||
db31af1d | 16121 | /* destroy the backlight and sysfs files before encoders/connectors */ |
19c8054c JN |
16122 | for_each_intel_connector(dev, connector) |
16123 | connector->unregister(connector); | |
d9255d57 | 16124 | |
79e53945 | 16125 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
16126 | |
16127 | intel_cleanup_overlay(dev); | |
ae48434c ID |
16128 | |
16129 | mutex_lock(&dev->struct_mutex); | |
16130 | intel_cleanup_gt_powersave(dev); | |
16131 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
16132 | } |
16133 | ||
f1c79df3 ZW |
16134 | /* |
16135 | * Return which encoder is currently attached for connector. | |
16136 | */ | |
df0e9248 | 16137 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 16138 | { |
df0e9248 CW |
16139 | return &intel_attached_encoder(connector)->base; |
16140 | } | |
f1c79df3 | 16141 | |
df0e9248 CW |
16142 | void intel_connector_attach_encoder(struct intel_connector *connector, |
16143 | struct intel_encoder *encoder) | |
16144 | { | |
16145 | connector->encoder = encoder; | |
16146 | drm_mode_connector_attach_encoder(&connector->base, | |
16147 | &encoder->base); | |
79e53945 | 16148 | } |
28d52043 DA |
16149 | |
16150 | /* | |
16151 | * set vga decode state - true == enable VGA decode | |
16152 | */ | |
16153 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
16154 | { | |
16155 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 16156 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
16157 | u16 gmch_ctrl; |
16158 | ||
75fa041d CW |
16159 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
16160 | DRM_ERROR("failed to read control word\n"); | |
16161 | return -EIO; | |
16162 | } | |
16163 | ||
c0cc8a55 CW |
16164 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
16165 | return 0; | |
16166 | ||
28d52043 DA |
16167 | if (state) |
16168 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
16169 | else | |
16170 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
16171 | |
16172 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
16173 | DRM_ERROR("failed to write control word\n"); | |
16174 | return -EIO; | |
16175 | } | |
16176 | ||
28d52043 DA |
16177 | return 0; |
16178 | } | |
c4a1d9e4 | 16179 | |
c4a1d9e4 | 16180 | struct intel_display_error_state { |
ff57f1b0 PZ |
16181 | |
16182 | u32 power_well_driver; | |
16183 | ||
63b66e5b CW |
16184 | int num_transcoders; |
16185 | ||
c4a1d9e4 CW |
16186 | struct intel_cursor_error_state { |
16187 | u32 control; | |
16188 | u32 position; | |
16189 | u32 base; | |
16190 | u32 size; | |
52331309 | 16191 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16192 | |
16193 | struct intel_pipe_error_state { | |
ddf9c536 | 16194 | bool power_domain_on; |
c4a1d9e4 | 16195 | u32 source; |
f301b1e1 | 16196 | u32 stat; |
52331309 | 16197 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16198 | |
16199 | struct intel_plane_error_state { | |
16200 | u32 control; | |
16201 | u32 stride; | |
16202 | u32 size; | |
16203 | u32 pos; | |
16204 | u32 addr; | |
16205 | u32 surface; | |
16206 | u32 tile_offset; | |
52331309 | 16207 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
16208 | |
16209 | struct intel_transcoder_error_state { | |
ddf9c536 | 16210 | bool power_domain_on; |
63b66e5b CW |
16211 | enum transcoder cpu_transcoder; |
16212 | ||
16213 | u32 conf; | |
16214 | ||
16215 | u32 htotal; | |
16216 | u32 hblank; | |
16217 | u32 hsync; | |
16218 | u32 vtotal; | |
16219 | u32 vblank; | |
16220 | u32 vsync; | |
16221 | } transcoder[4]; | |
c4a1d9e4 CW |
16222 | }; |
16223 | ||
16224 | struct intel_display_error_state * | |
16225 | intel_display_capture_error_state(struct drm_device *dev) | |
16226 | { | |
fbee40df | 16227 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 16228 | struct intel_display_error_state *error; |
63b66e5b CW |
16229 | int transcoders[] = { |
16230 | TRANSCODER_A, | |
16231 | TRANSCODER_B, | |
16232 | TRANSCODER_C, | |
16233 | TRANSCODER_EDP, | |
16234 | }; | |
c4a1d9e4 CW |
16235 | int i; |
16236 | ||
63b66e5b CW |
16237 | if (INTEL_INFO(dev)->num_pipes == 0) |
16238 | return NULL; | |
16239 | ||
9d1cb914 | 16240 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
16241 | if (error == NULL) |
16242 | return NULL; | |
16243 | ||
190be112 | 16244 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
16245 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
16246 | ||
055e393f | 16247 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 16248 | error->pipe[i].power_domain_on = |
f458ebbc DV |
16249 | __intel_display_power_is_enabled(dev_priv, |
16250 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 16251 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
16252 | continue; |
16253 | ||
5efb3e28 VS |
16254 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
16255 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
16256 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
16257 | |
16258 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
16259 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 16260 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 16261 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
16262 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
16263 | } | |
ca291363 PZ |
16264 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
16265 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
16266 | if (INTEL_INFO(dev)->gen >= 4) { |
16267 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
16268 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
16269 | } | |
16270 | ||
c4a1d9e4 | 16271 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 16272 | |
3abfce77 | 16273 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 16274 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
16275 | } |
16276 | ||
16277 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
16278 | if (HAS_DDI(dev_priv->dev)) | |
16279 | error->num_transcoders++; /* Account for eDP. */ | |
16280 | ||
16281 | for (i = 0; i < error->num_transcoders; i++) { | |
16282 | enum transcoder cpu_transcoder = transcoders[i]; | |
16283 | ||
ddf9c536 | 16284 | error->transcoder[i].power_domain_on = |
f458ebbc | 16285 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 16286 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 16287 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
16288 | continue; |
16289 | ||
63b66e5b CW |
16290 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
16291 | ||
16292 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
16293 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
16294 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
16295 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
16296 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
16297 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
16298 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
16299 | } |
16300 | ||
16301 | return error; | |
16302 | } | |
16303 | ||
edc3d884 MK |
16304 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
16305 | ||
c4a1d9e4 | 16306 | void |
edc3d884 | 16307 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
16308 | struct drm_device *dev, |
16309 | struct intel_display_error_state *error) | |
16310 | { | |
055e393f | 16311 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
16312 | int i; |
16313 | ||
63b66e5b CW |
16314 | if (!error) |
16315 | return; | |
16316 | ||
edc3d884 | 16317 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 16318 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 16319 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 16320 | error->power_well_driver); |
055e393f | 16321 | for_each_pipe(dev_priv, i) { |
edc3d884 | 16322 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 16323 | err_printf(m, " Power: %s\n", |
87ad3212 | 16324 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 16325 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 16326 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
16327 | |
16328 | err_printf(m, "Plane [%d]:\n", i); | |
16329 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
16330 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 16331 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
16332 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
16333 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 16334 | } |
4b71a570 | 16335 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 16336 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 16337 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
16338 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
16339 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
16340 | } |
16341 | ||
edc3d884 MK |
16342 | err_printf(m, "Cursor [%d]:\n", i); |
16343 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
16344 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
16345 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 16346 | } |
63b66e5b CW |
16347 | |
16348 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 16349 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 16350 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 16351 | err_printf(m, " Power: %s\n", |
87ad3212 | 16352 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
16353 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
16354 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
16355 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
16356 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
16357 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
16358 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
16359 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
16360 | } | |
c4a1d9e4 | 16361 | } |
e2fcdaa9 VS |
16362 | |
16363 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) | |
16364 | { | |
16365 | struct intel_crtc *crtc; | |
16366 | ||
16367 | for_each_intel_crtc(dev, crtc) { | |
16368 | struct intel_unpin_work *work; | |
e2fcdaa9 | 16369 | |
5e2d7afc | 16370 | spin_lock_irq(&dev->event_lock); |
e2fcdaa9 VS |
16371 | |
16372 | work = crtc->unpin_work; | |
16373 | ||
16374 | if (work && work->event && | |
16375 | work->event->base.file_priv == file) { | |
16376 | kfree(work->event); | |
16377 | work->event = NULL; | |
16378 | } | |
16379 | ||
5e2d7afc | 16380 | spin_unlock_irq(&dev->event_lock); |
e2fcdaa9 VS |
16381 | } |
16382 | } |