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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
5d723d7a | 37 | #include "intel_frontbuffer.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
79e53945 | 39 | #include "i915_drv.h" |
57822dc6 | 40 | #include "i915_gem_clflush.h" |
db18b6a6 | 41 | #include "intel_dsi.h" |
e5510fac | 42 | #include "i915_trace.h" |
319c1d42 | 43 | #include <drm/drm_atomic.h> |
c196e1d6 | 44 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
45 | #include <drm/drm_dp_helper.h> |
46 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
47 | #include <drm/drm_plane_helper.h> |
48 | #include <drm/drm_rect.h> | |
c0f372b3 | 49 | #include <linux/dma_remapping.h> |
fd8e058a | 50 | #include <linux/reservation.h> |
79e53945 | 51 | |
5a21b665 DV |
52 | static bool is_mmio_work(struct intel_flip_work *work) |
53 | { | |
54 | return work->mmio_work.func; | |
55 | } | |
56 | ||
465c120c | 57 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 58 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
59 | DRM_FORMAT_C8, |
60 | DRM_FORMAT_RGB565, | |
465c120c | 61 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 62 | DRM_FORMAT_XRGB8888, |
465c120c MR |
63 | }; |
64 | ||
65 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 66 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
67 | DRM_FORMAT_C8, |
68 | DRM_FORMAT_RGB565, | |
69 | DRM_FORMAT_XRGB8888, | |
70 | DRM_FORMAT_XBGR8888, | |
71 | DRM_FORMAT_XRGB2101010, | |
72 | DRM_FORMAT_XBGR2101010, | |
73 | }; | |
74 | ||
75 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
76 | DRM_FORMAT_C8, |
77 | DRM_FORMAT_RGB565, | |
78 | DRM_FORMAT_XRGB8888, | |
465c120c | 79 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 80 | DRM_FORMAT_ARGB8888, |
465c120c MR |
81 | DRM_FORMAT_ABGR8888, |
82 | DRM_FORMAT_XRGB2101010, | |
465c120c | 83 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
84 | DRM_FORMAT_YUYV, |
85 | DRM_FORMAT_YVYU, | |
86 | DRM_FORMAT_UYVY, | |
87 | DRM_FORMAT_VYUY, | |
465c120c MR |
88 | }; |
89 | ||
3d7d6510 MR |
90 | /* Cursor formats */ |
91 | static const uint32_t intel_cursor_formats[] = { | |
92 | DRM_FORMAT_ARGB8888, | |
93 | }; | |
94 | ||
f1f644dc | 95 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 96 | struct intel_crtc_state *pipe_config); |
18442d08 | 97 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 98 | struct intel_crtc_state *pipe_config); |
f1f644dc | 99 | |
24dbf51a CW |
100 | static int intel_framebuffer_init(struct intel_framebuffer *ifb, |
101 | struct drm_i915_gem_object *obj, | |
102 | struct drm_mode_fb_cmd2 *mode_cmd); | |
5b18e57c DV |
103 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
104 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
bc58be60 | 105 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc); |
29407aab | 106 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
107 | struct intel_link_m_n *m_n, |
108 | struct intel_link_m_n *m2_n2); | |
29407aab | 109 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 | 110 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
391bf048 | 111 | static void haswell_set_pipemisc(struct drm_crtc *crtc); |
d288f65f | 112 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 113 | const struct intel_crtc_state *pipe_config); |
d288f65f | 114 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 115 | const struct intel_crtc_state *pipe_config); |
5a21b665 DV |
116 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
117 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
1c74eeaf NM |
118 | static void intel_crtc_init_scalers(struct intel_crtc *crtc, |
119 | struct intel_crtc_state *crtc_state); | |
bfd16b2a ML |
120 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
121 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
122 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 123 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
2622a081 | 124 | static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); |
e7457a9a | 125 | |
d4906093 | 126 | struct intel_limit { |
4c5def93 ACO |
127 | struct { |
128 | int min, max; | |
129 | } dot, vco, n, m, m1, m2, p, p1; | |
130 | ||
131 | struct { | |
132 | int dot_limit; | |
133 | int p2_slow, p2_fast; | |
134 | } p2; | |
d4906093 | 135 | }; |
79e53945 | 136 | |
bfa7df01 | 137 | /* returns HPLL frequency in kHz */ |
49cd97a3 | 138 | int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) |
bfa7df01 VS |
139 | { |
140 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
141 | ||
142 | /* Obtain SKU information */ | |
143 | mutex_lock(&dev_priv->sb_lock); | |
144 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
145 | CCK_FUSE_HPLL_FREQ_MASK; | |
146 | mutex_unlock(&dev_priv->sb_lock); | |
147 | ||
148 | return vco_freq[hpll_freq] * 1000; | |
149 | } | |
150 | ||
c30fec65 VS |
151 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
152 | const char *name, u32 reg, int ref_freq) | |
bfa7df01 VS |
153 | { |
154 | u32 val; | |
155 | int divider; | |
156 | ||
bfa7df01 VS |
157 | mutex_lock(&dev_priv->sb_lock); |
158 | val = vlv_cck_read(dev_priv, reg); | |
159 | mutex_unlock(&dev_priv->sb_lock); | |
160 | ||
161 | divider = val & CCK_FREQUENCY_VALUES; | |
162 | ||
163 | WARN((val & CCK_FREQUENCY_STATUS) != | |
164 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
165 | "%s change in progress\n", name); | |
166 | ||
c30fec65 VS |
167 | return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); |
168 | } | |
169 | ||
7ff89ca2 VS |
170 | int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, |
171 | const char *name, u32 reg) | |
c30fec65 VS |
172 | { |
173 | if (dev_priv->hpll_freq == 0) | |
49cd97a3 | 174 | dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); |
c30fec65 VS |
175 | |
176 | return vlv_get_cck_clock(dev_priv, name, reg, | |
177 | dev_priv->hpll_freq); | |
bfa7df01 VS |
178 | } |
179 | ||
bfa7df01 VS |
180 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
181 | { | |
666a4537 | 182 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
183 | return; |
184 | ||
185 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
186 | CCK_CZ_CLOCK_CONTROL); | |
187 | ||
188 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
189 | } | |
190 | ||
021357ac | 191 | static inline u32 /* units of 100MHz */ |
21a727b3 VS |
192 | intel_fdi_link_freq(struct drm_i915_private *dev_priv, |
193 | const struct intel_crtc_state *pipe_config) | |
021357ac | 194 | { |
21a727b3 VS |
195 | if (HAS_DDI(dev_priv)) |
196 | return pipe_config->port_clock; /* SPLL */ | |
197 | else if (IS_GEN5(dev_priv)) | |
198 | return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; | |
e3b247da | 199 | else |
21a727b3 | 200 | return 270000; |
021357ac CW |
201 | } |
202 | ||
1b6f4958 | 203 | static const struct intel_limit intel_limits_i8xx_dac = { |
0206e353 | 204 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 205 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 206 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
207 | .m = { .min = 96, .max = 140 }, |
208 | .m1 = { .min = 18, .max = 26 }, | |
209 | .m2 = { .min = 6, .max = 16 }, | |
210 | .p = { .min = 4, .max = 128 }, | |
211 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
212 | .p2 = { .dot_limit = 165000, |
213 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
214 | }; |
215 | ||
1b6f4958 | 216 | static const struct intel_limit intel_limits_i8xx_dvo = { |
5d536e28 | 217 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 218 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 219 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
220 | .m = { .min = 96, .max = 140 }, |
221 | .m1 = { .min = 18, .max = 26 }, | |
222 | .m2 = { .min = 6, .max = 16 }, | |
223 | .p = { .min = 4, .max = 128 }, | |
224 | .p1 = { .min = 2, .max = 33 }, | |
225 | .p2 = { .dot_limit = 165000, | |
226 | .p2_slow = 4, .p2_fast = 4 }, | |
227 | }; | |
228 | ||
1b6f4958 | 229 | static const struct intel_limit intel_limits_i8xx_lvds = { |
0206e353 | 230 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 231 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 232 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
233 | .m = { .min = 96, .max = 140 }, |
234 | .m1 = { .min = 18, .max = 26 }, | |
235 | .m2 = { .min = 6, .max = 16 }, | |
236 | .p = { .min = 4, .max = 128 }, | |
237 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
238 | .p2 = { .dot_limit = 165000, |
239 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 240 | }; |
273e27ca | 241 | |
1b6f4958 | 242 | static const struct intel_limit intel_limits_i9xx_sdvo = { |
0206e353 AJ |
243 | .dot = { .min = 20000, .max = 400000 }, |
244 | .vco = { .min = 1400000, .max = 2800000 }, | |
245 | .n = { .min = 1, .max = 6 }, | |
246 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
247 | .m1 = { .min = 8, .max = 18 }, |
248 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
249 | .p = { .min = 5, .max = 80 }, |
250 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
251 | .p2 = { .dot_limit = 200000, |
252 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
253 | }; |
254 | ||
1b6f4958 | 255 | static const struct intel_limit intel_limits_i9xx_lvds = { |
0206e353 AJ |
256 | .dot = { .min = 20000, .max = 400000 }, |
257 | .vco = { .min = 1400000, .max = 2800000 }, | |
258 | .n = { .min = 1, .max = 6 }, | |
259 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
260 | .m1 = { .min = 8, .max = 18 }, |
261 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
262 | .p = { .min = 7, .max = 98 }, |
263 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
264 | .p2 = { .dot_limit = 112000, |
265 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
266 | }; |
267 | ||
273e27ca | 268 | |
1b6f4958 | 269 | static const struct intel_limit intel_limits_g4x_sdvo = { |
273e27ca EA |
270 | .dot = { .min = 25000, .max = 270000 }, |
271 | .vco = { .min = 1750000, .max = 3500000}, | |
272 | .n = { .min = 1, .max = 4 }, | |
273 | .m = { .min = 104, .max = 138 }, | |
274 | .m1 = { .min = 17, .max = 23 }, | |
275 | .m2 = { .min = 5, .max = 11 }, | |
276 | .p = { .min = 10, .max = 30 }, | |
277 | .p1 = { .min = 1, .max = 3}, | |
278 | .p2 = { .dot_limit = 270000, | |
279 | .p2_slow = 10, | |
280 | .p2_fast = 10 | |
044c7c41 | 281 | }, |
e4b36699 KP |
282 | }; |
283 | ||
1b6f4958 | 284 | static const struct intel_limit intel_limits_g4x_hdmi = { |
273e27ca EA |
285 | .dot = { .min = 22000, .max = 400000 }, |
286 | .vco = { .min = 1750000, .max = 3500000}, | |
287 | .n = { .min = 1, .max = 4 }, | |
288 | .m = { .min = 104, .max = 138 }, | |
289 | .m1 = { .min = 16, .max = 23 }, | |
290 | .m2 = { .min = 5, .max = 11 }, | |
291 | .p = { .min = 5, .max = 80 }, | |
292 | .p1 = { .min = 1, .max = 8}, | |
293 | .p2 = { .dot_limit = 165000, | |
294 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
295 | }; |
296 | ||
1b6f4958 | 297 | static const struct intel_limit intel_limits_g4x_single_channel_lvds = { |
273e27ca EA |
298 | .dot = { .min = 20000, .max = 115000 }, |
299 | .vco = { .min = 1750000, .max = 3500000 }, | |
300 | .n = { .min = 1, .max = 3 }, | |
301 | .m = { .min = 104, .max = 138 }, | |
302 | .m1 = { .min = 17, .max = 23 }, | |
303 | .m2 = { .min = 5, .max = 11 }, | |
304 | .p = { .min = 28, .max = 112 }, | |
305 | .p1 = { .min = 2, .max = 8 }, | |
306 | .p2 = { .dot_limit = 0, | |
307 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 308 | }, |
e4b36699 KP |
309 | }; |
310 | ||
1b6f4958 | 311 | static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { |
273e27ca EA |
312 | .dot = { .min = 80000, .max = 224000 }, |
313 | .vco = { .min = 1750000, .max = 3500000 }, | |
314 | .n = { .min = 1, .max = 3 }, | |
315 | .m = { .min = 104, .max = 138 }, | |
316 | .m1 = { .min = 17, .max = 23 }, | |
317 | .m2 = { .min = 5, .max = 11 }, | |
318 | .p = { .min = 14, .max = 42 }, | |
319 | .p1 = { .min = 2, .max = 6 }, | |
320 | .p2 = { .dot_limit = 0, | |
321 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 322 | }, |
e4b36699 KP |
323 | }; |
324 | ||
1b6f4958 | 325 | static const struct intel_limit intel_limits_pineview_sdvo = { |
0206e353 AJ |
326 | .dot = { .min = 20000, .max = 400000}, |
327 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 328 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
329 | .n = { .min = 3, .max = 6 }, |
330 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 331 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
332 | .m1 = { .min = 0, .max = 0 }, |
333 | .m2 = { .min = 0, .max = 254 }, | |
334 | .p = { .min = 5, .max = 80 }, | |
335 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
336 | .p2 = { .dot_limit = 200000, |
337 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
338 | }; |
339 | ||
1b6f4958 | 340 | static const struct intel_limit intel_limits_pineview_lvds = { |
0206e353 AJ |
341 | .dot = { .min = 20000, .max = 400000 }, |
342 | .vco = { .min = 1700000, .max = 3500000 }, | |
343 | .n = { .min = 3, .max = 6 }, | |
344 | .m = { .min = 2, .max = 256 }, | |
345 | .m1 = { .min = 0, .max = 0 }, | |
346 | .m2 = { .min = 0, .max = 254 }, | |
347 | .p = { .min = 7, .max = 112 }, | |
348 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
349 | .p2 = { .dot_limit = 112000, |
350 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
351 | }; |
352 | ||
273e27ca EA |
353 | /* Ironlake / Sandybridge |
354 | * | |
355 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
356 | * the range value for them is (actual_value - 2). | |
357 | */ | |
1b6f4958 | 358 | static const struct intel_limit intel_limits_ironlake_dac = { |
273e27ca EA |
359 | .dot = { .min = 25000, .max = 350000 }, |
360 | .vco = { .min = 1760000, .max = 3510000 }, | |
361 | .n = { .min = 1, .max = 5 }, | |
362 | .m = { .min = 79, .max = 127 }, | |
363 | .m1 = { .min = 12, .max = 22 }, | |
364 | .m2 = { .min = 5, .max = 9 }, | |
365 | .p = { .min = 5, .max = 80 }, | |
366 | .p1 = { .min = 1, .max = 8 }, | |
367 | .p2 = { .dot_limit = 225000, | |
368 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
369 | }; |
370 | ||
1b6f4958 | 371 | static const struct intel_limit intel_limits_ironlake_single_lvds = { |
273e27ca EA |
372 | .dot = { .min = 25000, .max = 350000 }, |
373 | .vco = { .min = 1760000, .max = 3510000 }, | |
374 | .n = { .min = 1, .max = 3 }, | |
375 | .m = { .min = 79, .max = 118 }, | |
376 | .m1 = { .min = 12, .max = 22 }, | |
377 | .m2 = { .min = 5, .max = 9 }, | |
378 | .p = { .min = 28, .max = 112 }, | |
379 | .p1 = { .min = 2, .max = 8 }, | |
380 | .p2 = { .dot_limit = 225000, | |
381 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
382 | }; |
383 | ||
1b6f4958 | 384 | static const struct intel_limit intel_limits_ironlake_dual_lvds = { |
273e27ca EA |
385 | .dot = { .min = 25000, .max = 350000 }, |
386 | .vco = { .min = 1760000, .max = 3510000 }, | |
387 | .n = { .min = 1, .max = 3 }, | |
388 | .m = { .min = 79, .max = 127 }, | |
389 | .m1 = { .min = 12, .max = 22 }, | |
390 | .m2 = { .min = 5, .max = 9 }, | |
391 | .p = { .min = 14, .max = 56 }, | |
392 | .p1 = { .min = 2, .max = 8 }, | |
393 | .p2 = { .dot_limit = 225000, | |
394 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
395 | }; |
396 | ||
273e27ca | 397 | /* LVDS 100mhz refclk limits. */ |
1b6f4958 | 398 | static const struct intel_limit intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
399 | .dot = { .min = 25000, .max = 350000 }, |
400 | .vco = { .min = 1760000, .max = 3510000 }, | |
401 | .n = { .min = 1, .max = 2 }, | |
402 | .m = { .min = 79, .max = 126 }, | |
403 | .m1 = { .min = 12, .max = 22 }, | |
404 | .m2 = { .min = 5, .max = 9 }, | |
405 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 406 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
407 | .p2 = { .dot_limit = 225000, |
408 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
409 | }; |
410 | ||
1b6f4958 | 411 | static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = { |
273e27ca EA |
412 | .dot = { .min = 25000, .max = 350000 }, |
413 | .vco = { .min = 1760000, .max = 3510000 }, | |
414 | .n = { .min = 1, .max = 3 }, | |
415 | .m = { .min = 79, .max = 126 }, | |
416 | .m1 = { .min = 12, .max = 22 }, | |
417 | .m2 = { .min = 5, .max = 9 }, | |
418 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 419 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
420 | .p2 = { .dot_limit = 225000, |
421 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
422 | }; |
423 | ||
1b6f4958 | 424 | static const struct intel_limit intel_limits_vlv = { |
f01b7962 VS |
425 | /* |
426 | * These are the data rate limits (measured in fast clocks) | |
427 | * since those are the strictest limits we have. The fast | |
428 | * clock and actual rate limits are more relaxed, so checking | |
429 | * them would make no difference. | |
430 | */ | |
431 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 432 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 433 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
434 | .m1 = { .min = 2, .max = 3 }, |
435 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 436 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 437 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
438 | }; |
439 | ||
1b6f4958 | 440 | static const struct intel_limit intel_limits_chv = { |
ef9348c8 CML |
441 | /* |
442 | * These are the data rate limits (measured in fast clocks) | |
443 | * since those are the strictest limits we have. The fast | |
444 | * clock and actual rate limits are more relaxed, so checking | |
445 | * them would make no difference. | |
446 | */ | |
447 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 448 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
449 | .n = { .min = 1, .max = 1 }, |
450 | .m1 = { .min = 2, .max = 2 }, | |
451 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
452 | .p1 = { .min = 2, .max = 4 }, | |
453 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
454 | }; | |
455 | ||
1b6f4958 | 456 | static const struct intel_limit intel_limits_bxt = { |
5ab7b0b7 ID |
457 | /* FIXME: find real dot limits */ |
458 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 459 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
460 | .n = { .min = 1, .max = 1 }, |
461 | .m1 = { .min = 2, .max = 2 }, | |
462 | /* FIXME: find real m2 limits */ | |
463 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
464 | .p1 = { .min = 2, .max = 4 }, | |
465 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
466 | }; | |
467 | ||
cdba954e ACO |
468 | static bool |
469 | needs_modeset(struct drm_crtc_state *state) | |
470 | { | |
fc596660 | 471 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
472 | } |
473 | ||
dccbea3b ID |
474 | /* |
475 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
476 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
477 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
478 | * The helpers' return value is the rate of the clock that is fed to the | |
479 | * display engine's pipe which can be the above fast dot clock rate or a | |
480 | * divided-down version of it. | |
481 | */ | |
f2b115e6 | 482 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
9e2c8475 | 483 | static int pnv_calc_dpll_params(int refclk, struct dpll *clock) |
79e53945 | 484 | { |
2177832f SL |
485 | clock->m = clock->m2 + 2; |
486 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 487 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 488 | return 0; |
fb03ac01 VS |
489 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
490 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
491 | |
492 | return clock->dot; | |
2177832f SL |
493 | } |
494 | ||
7429e9d4 DV |
495 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
496 | { | |
497 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
498 | } | |
499 | ||
9e2c8475 | 500 | static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) |
2177832f | 501 | { |
7429e9d4 | 502 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 503 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 504 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 505 | return 0; |
fb03ac01 VS |
506 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
507 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
508 | |
509 | return clock->dot; | |
79e53945 JB |
510 | } |
511 | ||
9e2c8475 | 512 | static int vlv_calc_dpll_params(int refclk, struct dpll *clock) |
589eca67 ID |
513 | { |
514 | clock->m = clock->m1 * clock->m2; | |
515 | clock->p = clock->p1 * clock->p2; | |
516 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 517 | return 0; |
589eca67 ID |
518 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
519 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
520 | |
521 | return clock->dot / 5; | |
589eca67 ID |
522 | } |
523 | ||
9e2c8475 | 524 | int chv_calc_dpll_params(int refclk, struct dpll *clock) |
ef9348c8 CML |
525 | { |
526 | clock->m = clock->m1 * clock->m2; | |
527 | clock->p = clock->p1 * clock->p2; | |
528 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 529 | return 0; |
ef9348c8 CML |
530 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
531 | clock->n << 22); | |
532 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
533 | |
534 | return clock->dot / 5; | |
ef9348c8 CML |
535 | } |
536 | ||
7c04d1d9 | 537 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
538 | /** |
539 | * Returns whether the given set of divisors are valid for a given refclk with | |
540 | * the given connectors. | |
541 | */ | |
542 | ||
e2d214ae | 543 | static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv, |
1b6f4958 | 544 | const struct intel_limit *limit, |
9e2c8475 | 545 | const struct dpll *clock) |
79e53945 | 546 | { |
f01b7962 VS |
547 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
548 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 549 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 550 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 551 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 552 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 553 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 554 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 555 | |
e2d214ae | 556 | if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) && |
cc3f90f0 | 557 | !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv)) |
f01b7962 VS |
558 | if (clock->m1 <= clock->m2) |
559 | INTELPllInvalid("m1 <= m2\n"); | |
560 | ||
e2d214ae | 561 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
cc3f90f0 | 562 | !IS_GEN9_LP(dev_priv)) { |
f01b7962 VS |
563 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
564 | INTELPllInvalid("p out of range\n"); | |
565 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
566 | INTELPllInvalid("m out of range\n"); | |
567 | } | |
568 | ||
79e53945 | 569 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 570 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
571 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
572 | * connector, etc., rather than just a single range. | |
573 | */ | |
574 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 575 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
576 | |
577 | return true; | |
578 | } | |
579 | ||
3b1429d9 | 580 | static int |
1b6f4958 | 581 | i9xx_select_p2_div(const struct intel_limit *limit, |
3b1429d9 VS |
582 | const struct intel_crtc_state *crtc_state, |
583 | int target) | |
79e53945 | 584 | { |
3b1429d9 | 585 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 586 | |
2d84d2b3 | 587 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 588 | /* |
a210b028 DV |
589 | * For LVDS just rely on its current settings for dual-channel. |
590 | * We haven't figured out how to reliably set up different | |
591 | * single/dual channel state, if we even can. | |
79e53945 | 592 | */ |
1974cad0 | 593 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 594 | return limit->p2.p2_fast; |
79e53945 | 595 | else |
3b1429d9 | 596 | return limit->p2.p2_slow; |
79e53945 JB |
597 | } else { |
598 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 599 | return limit->p2.p2_slow; |
79e53945 | 600 | else |
3b1429d9 | 601 | return limit->p2.p2_fast; |
79e53945 | 602 | } |
3b1429d9 VS |
603 | } |
604 | ||
70e8aa21 ACO |
605 | /* |
606 | * Returns a set of divisors for the desired target clock with the given | |
607 | * refclk, or FALSE. The returned values represent the clock equation: | |
608 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
609 | * | |
610 | * Target and reference clocks are specified in kHz. | |
611 | * | |
612 | * If match_clock is provided, then best_clock P divider must match the P | |
613 | * divider from @match_clock used for LVDS downclocking. | |
614 | */ | |
3b1429d9 | 615 | static bool |
1b6f4958 | 616 | i9xx_find_best_dpll(const struct intel_limit *limit, |
3b1429d9 | 617 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
618 | int target, int refclk, struct dpll *match_clock, |
619 | struct dpll *best_clock) | |
3b1429d9 VS |
620 | { |
621 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
9e2c8475 | 622 | struct dpll clock; |
3b1429d9 | 623 | int err = target; |
79e53945 | 624 | |
0206e353 | 625 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 626 | |
3b1429d9 VS |
627 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
628 | ||
42158660 ZY |
629 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
630 | clock.m1++) { | |
631 | for (clock.m2 = limit->m2.min; | |
632 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 633 | if (clock.m2 >= clock.m1) |
42158660 ZY |
634 | break; |
635 | for (clock.n = limit->n.min; | |
636 | clock.n <= limit->n.max; clock.n++) { | |
637 | for (clock.p1 = limit->p1.min; | |
638 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
639 | int this_err; |
640 | ||
dccbea3b | 641 | i9xx_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
642 | if (!intel_PLL_is_valid(to_i915(dev), |
643 | limit, | |
ac58c3f0 DV |
644 | &clock)) |
645 | continue; | |
646 | if (match_clock && | |
647 | clock.p != match_clock->p) | |
648 | continue; | |
649 | ||
650 | this_err = abs(clock.dot - target); | |
651 | if (this_err < err) { | |
652 | *best_clock = clock; | |
653 | err = this_err; | |
654 | } | |
655 | } | |
656 | } | |
657 | } | |
658 | } | |
659 | ||
660 | return (err != target); | |
661 | } | |
662 | ||
70e8aa21 ACO |
663 | /* |
664 | * Returns a set of divisors for the desired target clock with the given | |
665 | * refclk, or FALSE. The returned values represent the clock equation: | |
666 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
667 | * | |
668 | * Target and reference clocks are specified in kHz. | |
669 | * | |
670 | * If match_clock is provided, then best_clock P divider must match the P | |
671 | * divider from @match_clock used for LVDS downclocking. | |
672 | */ | |
ac58c3f0 | 673 | static bool |
1b6f4958 | 674 | pnv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 675 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
676 | int target, int refclk, struct dpll *match_clock, |
677 | struct dpll *best_clock) | |
79e53945 | 678 | { |
3b1429d9 | 679 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 680 | struct dpll clock; |
79e53945 JB |
681 | int err = target; |
682 | ||
0206e353 | 683 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 684 | |
3b1429d9 VS |
685 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
686 | ||
42158660 ZY |
687 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
688 | clock.m1++) { | |
689 | for (clock.m2 = limit->m2.min; | |
690 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
691 | for (clock.n = limit->n.min; |
692 | clock.n <= limit->n.max; clock.n++) { | |
693 | for (clock.p1 = limit->p1.min; | |
694 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
695 | int this_err; |
696 | ||
dccbea3b | 697 | pnv_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
698 | if (!intel_PLL_is_valid(to_i915(dev), |
699 | limit, | |
1b894b59 | 700 | &clock)) |
79e53945 | 701 | continue; |
cec2f356 SP |
702 | if (match_clock && |
703 | clock.p != match_clock->p) | |
704 | continue; | |
79e53945 JB |
705 | |
706 | this_err = abs(clock.dot - target); | |
707 | if (this_err < err) { | |
708 | *best_clock = clock; | |
709 | err = this_err; | |
710 | } | |
711 | } | |
712 | } | |
713 | } | |
714 | } | |
715 | ||
716 | return (err != target); | |
717 | } | |
718 | ||
997c030c ACO |
719 | /* |
720 | * Returns a set of divisors for the desired target clock with the given | |
721 | * refclk, or FALSE. The returned values represent the clock equation: | |
722 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
70e8aa21 ACO |
723 | * |
724 | * Target and reference clocks are specified in kHz. | |
725 | * | |
726 | * If match_clock is provided, then best_clock P divider must match the P | |
727 | * divider from @match_clock used for LVDS downclocking. | |
997c030c | 728 | */ |
d4906093 | 729 | static bool |
1b6f4958 | 730 | g4x_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 731 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
732 | int target, int refclk, struct dpll *match_clock, |
733 | struct dpll *best_clock) | |
d4906093 | 734 | { |
3b1429d9 | 735 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 736 | struct dpll clock; |
d4906093 | 737 | int max_n; |
3b1429d9 | 738 | bool found = false; |
6ba770dc AJ |
739 | /* approximately equals target * 0.00585 */ |
740 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
741 | |
742 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
743 | |
744 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
745 | ||
d4906093 | 746 | max_n = limit->n.max; |
f77f13e2 | 747 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 748 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 749 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
750 | for (clock.m1 = limit->m1.max; |
751 | clock.m1 >= limit->m1.min; clock.m1--) { | |
752 | for (clock.m2 = limit->m2.max; | |
753 | clock.m2 >= limit->m2.min; clock.m2--) { | |
754 | for (clock.p1 = limit->p1.max; | |
755 | clock.p1 >= limit->p1.min; clock.p1--) { | |
756 | int this_err; | |
757 | ||
dccbea3b | 758 | i9xx_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
759 | if (!intel_PLL_is_valid(to_i915(dev), |
760 | limit, | |
1b894b59 | 761 | &clock)) |
d4906093 | 762 | continue; |
1b894b59 CW |
763 | |
764 | this_err = abs(clock.dot - target); | |
d4906093 ML |
765 | if (this_err < err_most) { |
766 | *best_clock = clock; | |
767 | err_most = this_err; | |
768 | max_n = clock.n; | |
769 | found = true; | |
770 | } | |
771 | } | |
772 | } | |
773 | } | |
774 | } | |
2c07245f ZW |
775 | return found; |
776 | } | |
777 | ||
d5dd62bd ID |
778 | /* |
779 | * Check if the calculated PLL configuration is more optimal compared to the | |
780 | * best configuration and error found so far. Return the calculated error. | |
781 | */ | |
782 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
9e2c8475 ACO |
783 | const struct dpll *calculated_clock, |
784 | const struct dpll *best_clock, | |
d5dd62bd ID |
785 | unsigned int best_error_ppm, |
786 | unsigned int *error_ppm) | |
787 | { | |
9ca3ba01 ID |
788 | /* |
789 | * For CHV ignore the error and consider only the P value. | |
790 | * Prefer a bigger P value based on HW requirements. | |
791 | */ | |
920a14b2 | 792 | if (IS_CHERRYVIEW(to_i915(dev))) { |
9ca3ba01 ID |
793 | *error_ppm = 0; |
794 | ||
795 | return calculated_clock->p > best_clock->p; | |
796 | } | |
797 | ||
24be4e46 ID |
798 | if (WARN_ON_ONCE(!target_freq)) |
799 | return false; | |
800 | ||
d5dd62bd ID |
801 | *error_ppm = div_u64(1000000ULL * |
802 | abs(target_freq - calculated_clock->dot), | |
803 | target_freq); | |
804 | /* | |
805 | * Prefer a better P value over a better (smaller) error if the error | |
806 | * is small. Ensure this preference for future configurations too by | |
807 | * setting the error to 0. | |
808 | */ | |
809 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
810 | *error_ppm = 0; | |
811 | ||
812 | return true; | |
813 | } | |
814 | ||
815 | return *error_ppm + 10 < best_error_ppm; | |
816 | } | |
817 | ||
65b3d6a9 ACO |
818 | /* |
819 | * Returns a set of divisors for the desired target clock with the given | |
820 | * refclk, or FALSE. The returned values represent the clock equation: | |
821 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
822 | */ | |
a0c4da24 | 823 | static bool |
1b6f4958 | 824 | vlv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 825 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
826 | int target, int refclk, struct dpll *match_clock, |
827 | struct dpll *best_clock) | |
a0c4da24 | 828 | { |
a93e255f | 829 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 830 | struct drm_device *dev = crtc->base.dev; |
9e2c8475 | 831 | struct dpll clock; |
69e4f900 | 832 | unsigned int bestppm = 1000000; |
27e639bf VS |
833 | /* min update 19.2 MHz */ |
834 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 835 | bool found = false; |
a0c4da24 | 836 | |
6b4bf1c4 VS |
837 | target *= 5; /* fast clock */ |
838 | ||
839 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
840 | |
841 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 842 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 843 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 844 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 845 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 846 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 847 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 848 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 849 | unsigned int ppm; |
69e4f900 | 850 | |
6b4bf1c4 VS |
851 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
852 | refclk * clock.m1); | |
853 | ||
dccbea3b | 854 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 855 | |
e2d214ae TU |
856 | if (!intel_PLL_is_valid(to_i915(dev), |
857 | limit, | |
f01b7962 | 858 | &clock)) |
43b0ac53 VS |
859 | continue; |
860 | ||
d5dd62bd ID |
861 | if (!vlv_PLL_is_optimal(dev, target, |
862 | &clock, | |
863 | best_clock, | |
864 | bestppm, &ppm)) | |
865 | continue; | |
6b4bf1c4 | 866 | |
d5dd62bd ID |
867 | *best_clock = clock; |
868 | bestppm = ppm; | |
869 | found = true; | |
a0c4da24 JB |
870 | } |
871 | } | |
872 | } | |
873 | } | |
a0c4da24 | 874 | |
49e497ef | 875 | return found; |
a0c4da24 | 876 | } |
a4fc5ed6 | 877 | |
65b3d6a9 ACO |
878 | /* |
879 | * Returns a set of divisors for the desired target clock with the given | |
880 | * refclk, or FALSE. The returned values represent the clock equation: | |
881 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
882 | */ | |
ef9348c8 | 883 | static bool |
1b6f4958 | 884 | chv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 885 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
886 | int target, int refclk, struct dpll *match_clock, |
887 | struct dpll *best_clock) | |
ef9348c8 | 888 | { |
a93e255f | 889 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 890 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 891 | unsigned int best_error_ppm; |
9e2c8475 | 892 | struct dpll clock; |
ef9348c8 CML |
893 | uint64_t m2; |
894 | int found = false; | |
895 | ||
896 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 897 | best_error_ppm = 1000000; |
ef9348c8 CML |
898 | |
899 | /* | |
900 | * Based on hardware doc, the n always set to 1, and m1 always | |
901 | * set to 2. If requires to support 200Mhz refclk, we need to | |
902 | * revisit this because n may not 1 anymore. | |
903 | */ | |
904 | clock.n = 1, clock.m1 = 2; | |
905 | target *= 5; /* fast clock */ | |
906 | ||
907 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
908 | for (clock.p2 = limit->p2.p2_fast; | |
909 | clock.p2 >= limit->p2.p2_slow; | |
910 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 911 | unsigned int error_ppm; |
ef9348c8 CML |
912 | |
913 | clock.p = clock.p1 * clock.p2; | |
914 | ||
915 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
916 | clock.n) << 22, refclk * clock.m1); | |
917 | ||
918 | if (m2 > INT_MAX/clock.m1) | |
919 | continue; | |
920 | ||
921 | clock.m2 = m2; | |
922 | ||
dccbea3b | 923 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 | 924 | |
e2d214ae | 925 | if (!intel_PLL_is_valid(to_i915(dev), limit, &clock)) |
ef9348c8 CML |
926 | continue; |
927 | ||
9ca3ba01 ID |
928 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
929 | best_error_ppm, &error_ppm)) | |
930 | continue; | |
931 | ||
932 | *best_clock = clock; | |
933 | best_error_ppm = error_ppm; | |
934 | found = true; | |
ef9348c8 CML |
935 | } |
936 | } | |
937 | ||
938 | return found; | |
939 | } | |
940 | ||
5ab7b0b7 | 941 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
9e2c8475 | 942 | struct dpll *best_clock) |
5ab7b0b7 | 943 | { |
65b3d6a9 | 944 | int refclk = 100000; |
1b6f4958 | 945 | const struct intel_limit *limit = &intel_limits_bxt; |
5ab7b0b7 | 946 | |
65b3d6a9 | 947 | return chv_find_best_dpll(limit, crtc_state, |
5ab7b0b7 ID |
948 | target_clock, refclk, NULL, best_clock); |
949 | } | |
950 | ||
525b9311 | 951 | bool intel_crtc_active(struct intel_crtc *crtc) |
20ddf665 | 952 | { |
20ddf665 VS |
953 | /* Be paranoid as we can arrive here with only partial |
954 | * state retrieved from the hardware during setup. | |
955 | * | |
241bfc38 | 956 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
957 | * as Haswell has gained clock readout/fastboot support. |
958 | * | |
66e514c1 | 959 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 960 | * properly reconstruct framebuffers. |
c3d1f436 MR |
961 | * |
962 | * FIXME: The intel_crtc->active here should be switched to | |
963 | * crtc->state->active once we have proper CRTC states wired up | |
964 | * for atomic. | |
20ddf665 | 965 | */ |
525b9311 VS |
966 | return crtc->active && crtc->base.primary->state->fb && |
967 | crtc->config->base.adjusted_mode.crtc_clock; | |
20ddf665 VS |
968 | } |
969 | ||
a5c961d1 PZ |
970 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
971 | enum pipe pipe) | |
972 | { | |
98187836 | 973 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
a5c961d1 | 974 | |
e2af48c6 | 975 | return crtc->config->cpu_transcoder; |
a5c961d1 PZ |
976 | } |
977 | ||
6315b5d3 | 978 | static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe) |
fbf49ea2 | 979 | { |
f0f59a00 | 980 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
981 | u32 line1, line2; |
982 | u32 line_mask; | |
983 | ||
5db94019 | 984 | if (IS_GEN2(dev_priv)) |
fbf49ea2 VS |
985 | line_mask = DSL_LINEMASK_GEN2; |
986 | else | |
987 | line_mask = DSL_LINEMASK_GEN3; | |
988 | ||
989 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 990 | msleep(5); |
fbf49ea2 VS |
991 | line2 = I915_READ(reg) & line_mask; |
992 | ||
993 | return line1 == line2; | |
994 | } | |
995 | ||
ab7ad7f6 KP |
996 | /* |
997 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 998 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
999 | * |
1000 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1001 | * spinning on the vblank interrupt status bit, since we won't actually | |
1002 | * see an interrupt when the pipe is disabled. | |
1003 | * | |
ab7ad7f6 KP |
1004 | * On Gen4 and above: |
1005 | * wait for the pipe register state bit to turn off | |
1006 | * | |
1007 | * Otherwise: | |
1008 | * wait for the display line value to settle (it usually | |
1009 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1010 | * |
9d0498a2 | 1011 | */ |
575f7ab7 | 1012 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1013 | { |
6315b5d3 | 1014 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 1015 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1016 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 | 1017 | |
6315b5d3 | 1018 | if (INTEL_GEN(dev_priv) >= 4) { |
f0f59a00 | 1019 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1020 | |
1021 | /* Wait for the Pipe State to go off */ | |
b8511f53 CW |
1022 | if (intel_wait_for_register(dev_priv, |
1023 | reg, I965_PIPECONF_ACTIVE, 0, | |
1024 | 100)) | |
284637d9 | 1025 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1026 | } else { |
ab7ad7f6 | 1027 | /* Wait for the display line to settle */ |
6315b5d3 | 1028 | if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100)) |
284637d9 | 1029 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1030 | } |
79e53945 JB |
1031 | } |
1032 | ||
b24e7179 | 1033 | /* Only for pre-ILK configs */ |
55607e8a DV |
1034 | void assert_pll(struct drm_i915_private *dev_priv, |
1035 | enum pipe pipe, bool state) | |
b24e7179 | 1036 | { |
b24e7179 JB |
1037 | u32 val; |
1038 | bool cur_state; | |
1039 | ||
649636ef | 1040 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1041 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1042 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1043 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1044 | onoff(state), onoff(cur_state)); |
b24e7179 | 1045 | } |
b24e7179 | 1046 | |
23538ef1 | 1047 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
8563b1e8 | 1048 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
23538ef1 JN |
1049 | { |
1050 | u32 val; | |
1051 | bool cur_state; | |
1052 | ||
a580516d | 1053 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1054 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1055 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1056 | |
1057 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1058 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1059 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1060 | onoff(state), onoff(cur_state)); |
23538ef1 | 1061 | } |
23538ef1 | 1062 | |
040484af JB |
1063 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1064 | enum pipe pipe, bool state) | |
1065 | { | |
040484af | 1066 | bool cur_state; |
ad80a810 PZ |
1067 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1068 | pipe); | |
040484af | 1069 | |
2d1fe073 | 1070 | if (HAS_DDI(dev_priv)) { |
affa9354 | 1071 | /* DDI does not have a specific FDI_TX register */ |
649636ef | 1072 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1073 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1074 | } else { |
649636ef | 1075 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1076 | cur_state = !!(val & FDI_TX_ENABLE); |
1077 | } | |
e2c719b7 | 1078 | I915_STATE_WARN(cur_state != state, |
040484af | 1079 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1080 | onoff(state), onoff(cur_state)); |
040484af JB |
1081 | } |
1082 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1083 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1084 | ||
1085 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1086 | enum pipe pipe, bool state) | |
1087 | { | |
040484af JB |
1088 | u32 val; |
1089 | bool cur_state; | |
1090 | ||
649636ef | 1091 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1092 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1093 | I915_STATE_WARN(cur_state != state, |
040484af | 1094 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1095 | onoff(state), onoff(cur_state)); |
040484af JB |
1096 | } |
1097 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1098 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1099 | ||
1100 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1101 | enum pipe pipe) | |
1102 | { | |
040484af JB |
1103 | u32 val; |
1104 | ||
1105 | /* ILK FDI PLL is always enabled */ | |
7e22dbbb | 1106 | if (IS_GEN5(dev_priv)) |
040484af JB |
1107 | return; |
1108 | ||
bf507ef7 | 1109 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
2d1fe073 | 1110 | if (HAS_DDI(dev_priv)) |
bf507ef7 ED |
1111 | return; |
1112 | ||
649636ef | 1113 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1114 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1115 | } |
1116 | ||
55607e8a DV |
1117 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1118 | enum pipe pipe, bool state) | |
040484af | 1119 | { |
040484af | 1120 | u32 val; |
55607e8a | 1121 | bool cur_state; |
040484af | 1122 | |
649636ef | 1123 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1124 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1125 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1126 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1127 | onoff(state), onoff(cur_state)); |
040484af JB |
1128 | } |
1129 | ||
4f8036a2 | 1130 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) |
ea0760cf | 1131 | { |
f0f59a00 | 1132 | i915_reg_t pp_reg; |
ea0760cf JB |
1133 | u32 val; |
1134 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1135 | bool locked = true; |
ea0760cf | 1136 | |
4f8036a2 | 1137 | if (WARN_ON(HAS_DDI(dev_priv))) |
bedd4dba JN |
1138 | return; |
1139 | ||
4f8036a2 | 1140 | if (HAS_PCH_SPLIT(dev_priv)) { |
bedd4dba JN |
1141 | u32 port_sel; |
1142 | ||
44cb734c ID |
1143 | pp_reg = PP_CONTROL(0); |
1144 | port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; | |
bedd4dba JN |
1145 | |
1146 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1147 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1148 | panel_pipe = PIPE_B; | |
1149 | /* XXX: else fix for eDP */ | |
4f8036a2 | 1150 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
bedd4dba | 1151 | /* presumably write lock depends on pipe, not port select */ |
44cb734c | 1152 | pp_reg = PP_CONTROL(pipe); |
bedd4dba | 1153 | panel_pipe = pipe; |
ea0760cf | 1154 | } else { |
44cb734c | 1155 | pp_reg = PP_CONTROL(0); |
bedd4dba JN |
1156 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1157 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1158 | } |
1159 | ||
1160 | val = I915_READ(pp_reg); | |
1161 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1162 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1163 | locked = false; |
1164 | ||
e2c719b7 | 1165 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1166 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1167 | pipe_name(pipe)); |
ea0760cf JB |
1168 | } |
1169 | ||
93ce0ba6 JN |
1170 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1171 | enum pipe pipe, bool state) | |
1172 | { | |
93ce0ba6 JN |
1173 | bool cur_state; |
1174 | ||
2a307c2e | 1175 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
0b87c24e | 1176 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1177 | else |
5efb3e28 | 1178 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1179 | |
e2c719b7 | 1180 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1181 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1182 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1183 | } |
1184 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1185 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1186 | ||
b840d907 JB |
1187 | void assert_pipe(struct drm_i915_private *dev_priv, |
1188 | enum pipe pipe, bool state) | |
b24e7179 | 1189 | { |
63d7bbe9 | 1190 | bool cur_state; |
702e7a56 PZ |
1191 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1192 | pipe); | |
4feed0eb | 1193 | enum intel_display_power_domain power_domain; |
b24e7179 | 1194 | |
b6b5d049 VS |
1195 | /* if we need the pipe quirk it must be always on */ |
1196 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1197 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1198 | state = true; |
1199 | ||
4feed0eb ID |
1200 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1201 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
649636ef | 1202 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 | 1203 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb ID |
1204 | |
1205 | intel_display_power_put(dev_priv, power_domain); | |
1206 | } else { | |
1207 | cur_state = false; | |
69310161 PZ |
1208 | } |
1209 | ||
e2c719b7 | 1210 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1211 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1212 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1213 | } |
1214 | ||
931872fc CW |
1215 | static void assert_plane(struct drm_i915_private *dev_priv, |
1216 | enum plane plane, bool state) | |
b24e7179 | 1217 | { |
b24e7179 | 1218 | u32 val; |
931872fc | 1219 | bool cur_state; |
b24e7179 | 1220 | |
649636ef | 1221 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1222 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1223 | I915_STATE_WARN(cur_state != state, |
931872fc | 1224 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1225 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1226 | } |
1227 | ||
931872fc CW |
1228 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1229 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1230 | ||
b24e7179 JB |
1231 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1232 | enum pipe pipe) | |
1233 | { | |
649636ef | 1234 | int i; |
b24e7179 | 1235 | |
653e1026 | 1236 | /* Primary planes are fixed to pipes on gen4+ */ |
6315b5d3 | 1237 | if (INTEL_GEN(dev_priv) >= 4) { |
649636ef | 1238 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1239 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1240 | "plane %c assertion failure, should be disabled but not\n", |
1241 | plane_name(pipe)); | |
19ec1358 | 1242 | return; |
28c05794 | 1243 | } |
19ec1358 | 1244 | |
b24e7179 | 1245 | /* Need to check both planes against the pipe */ |
055e393f | 1246 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1247 | u32 val = I915_READ(DSPCNTR(i)); |
1248 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1249 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1250 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1251 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1252 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1253 | } |
1254 | } | |
1255 | ||
19332d7a JB |
1256 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1257 | enum pipe pipe) | |
1258 | { | |
649636ef | 1259 | int sprite; |
19332d7a | 1260 | |
6315b5d3 | 1261 | if (INTEL_GEN(dev_priv) >= 9) { |
3bdcfc0c | 1262 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1263 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1264 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1265 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1266 | sprite, pipe_name(pipe)); | |
1267 | } | |
920a14b2 | 1268 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
3bdcfc0c | 1269 | for_each_sprite(dev_priv, pipe, sprite) { |
83c04a62 | 1270 | u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite)); |
e2c719b7 | 1271 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1272 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1273 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef | 1274 | } |
6315b5d3 | 1275 | } else if (INTEL_GEN(dev_priv) >= 7) { |
649636ef | 1276 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1277 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1278 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1279 | plane_name(pipe), pipe_name(pipe)); |
6315b5d3 | 1280 | } else if (INTEL_GEN(dev_priv) >= 5) { |
649636ef | 1281 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1282 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1283 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1284 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1285 | } |
1286 | } | |
1287 | ||
08c71e5e VS |
1288 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1289 | { | |
e2c719b7 | 1290 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1291 | drm_crtc_vblank_put(crtc); |
1292 | } | |
1293 | ||
7abd4b35 ACO |
1294 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1295 | enum pipe pipe) | |
92f2584a | 1296 | { |
92f2584a JB |
1297 | u32 val; |
1298 | bool enabled; | |
1299 | ||
649636ef | 1300 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1301 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1302 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1303 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1304 | pipe_name(pipe)); | |
92f2584a JB |
1305 | } |
1306 | ||
4e634389 KP |
1307 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1308 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1309 | { |
1310 | if ((val & DP_PORT_EN) == 0) | |
1311 | return false; | |
1312 | ||
2d1fe073 | 1313 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 | 1314 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1315 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1316 | return false; | |
2d1fe073 | 1317 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1318 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
1319 | return false; | |
f0575e92 KP |
1320 | } else { |
1321 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1322 | return false; | |
1323 | } | |
1324 | return true; | |
1325 | } | |
1326 | ||
1519b995 KP |
1327 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1328 | enum pipe pipe, u32 val) | |
1329 | { | |
dc0fa718 | 1330 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1331 | return false; |
1332 | ||
2d1fe073 | 1333 | if (HAS_PCH_CPT(dev_priv)) { |
dc0fa718 | 1334 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1335 | return false; |
2d1fe073 | 1336 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1337 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) |
1338 | return false; | |
1519b995 | 1339 | } else { |
dc0fa718 | 1340 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1341 | return false; |
1342 | } | |
1343 | return true; | |
1344 | } | |
1345 | ||
1346 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1347 | enum pipe pipe, u32 val) | |
1348 | { | |
1349 | if ((val & LVDS_PORT_EN) == 0) | |
1350 | return false; | |
1351 | ||
2d1fe073 | 1352 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1353 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1354 | return false; | |
1355 | } else { | |
1356 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1357 | return false; | |
1358 | } | |
1359 | return true; | |
1360 | } | |
1361 | ||
1362 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1363 | enum pipe pipe, u32 val) | |
1364 | { | |
1365 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1366 | return false; | |
2d1fe073 | 1367 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1368 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1369 | return false; | |
1370 | } else { | |
1371 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1372 | return false; | |
1373 | } | |
1374 | return true; | |
1375 | } | |
1376 | ||
291906f1 | 1377 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1378 | enum pipe pipe, i915_reg_t reg, |
1379 | u32 port_sel) | |
291906f1 | 1380 | { |
47a05eca | 1381 | u32 val = I915_READ(reg); |
e2c719b7 | 1382 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1383 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1384 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1385 | |
2d1fe073 | 1386 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1387 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1388 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1389 | } |
1390 | ||
1391 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1392 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1393 | { |
47a05eca | 1394 | u32 val = I915_READ(reg); |
e2c719b7 | 1395 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1396 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1397 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1398 | |
2d1fe073 | 1399 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1400 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1401 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1402 | } |
1403 | ||
1404 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1405 | enum pipe pipe) | |
1406 | { | |
291906f1 | 1407 | u32 val; |
291906f1 | 1408 | |
f0575e92 KP |
1409 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1410 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1411 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1412 | |
649636ef | 1413 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1414 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1415 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1416 | pipe_name(pipe)); |
291906f1 | 1417 | |
649636ef | 1418 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1419 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1420 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1421 | pipe_name(pipe)); |
291906f1 | 1422 | |
e2debe91 PZ |
1423 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1424 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1425 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1426 | } |
1427 | ||
cd2d34d9 VS |
1428 | static void _vlv_enable_pll(struct intel_crtc *crtc, |
1429 | const struct intel_crtc_state *pipe_config) | |
1430 | { | |
1431 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1432 | enum pipe pipe = crtc->pipe; | |
1433 | ||
1434 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); | |
1435 | POSTING_READ(DPLL(pipe)); | |
1436 | udelay(150); | |
1437 | ||
2c30b43b CW |
1438 | if (intel_wait_for_register(dev_priv, |
1439 | DPLL(pipe), | |
1440 | DPLL_LOCK_VLV, | |
1441 | DPLL_LOCK_VLV, | |
1442 | 1)) | |
cd2d34d9 VS |
1443 | DRM_ERROR("DPLL %d failed to lock\n", pipe); |
1444 | } | |
1445 | ||
d288f65f | 1446 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1447 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1448 | { |
cd2d34d9 | 1449 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1450 | enum pipe pipe = crtc->pipe; |
87442f73 | 1451 | |
8bd3f301 | 1452 | assert_pipe_disabled(dev_priv, pipe); |
87442f73 | 1453 | |
87442f73 | 1454 | /* PLL is protected by panel, make sure we can write it */ |
7d1a83cb | 1455 | assert_panel_unlocked(dev_priv, pipe); |
87442f73 | 1456 | |
cd2d34d9 VS |
1457 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) |
1458 | _vlv_enable_pll(crtc, pipe_config); | |
426115cf | 1459 | |
8bd3f301 VS |
1460 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
1461 | POSTING_READ(DPLL_MD(pipe)); | |
87442f73 DV |
1462 | } |
1463 | ||
cd2d34d9 VS |
1464 | |
1465 | static void _chv_enable_pll(struct intel_crtc *crtc, | |
1466 | const struct intel_crtc_state *pipe_config) | |
9d556c99 | 1467 | { |
cd2d34d9 | 1468 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1469 | enum pipe pipe = crtc->pipe; |
9d556c99 | 1470 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9d556c99 CML |
1471 | u32 tmp; |
1472 | ||
a580516d | 1473 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1474 | |
1475 | /* Enable back the 10bit clock to display controller */ | |
1476 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1477 | tmp |= DPIO_DCLKP_EN; | |
1478 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1479 | ||
54433e91 VS |
1480 | mutex_unlock(&dev_priv->sb_lock); |
1481 | ||
9d556c99 CML |
1482 | /* |
1483 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1484 | */ | |
1485 | udelay(1); | |
1486 | ||
1487 | /* Enable PLL */ | |
d288f65f | 1488 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1489 | |
1490 | /* Check PLL is locked */ | |
6b18826a CW |
1491 | if (intel_wait_for_register(dev_priv, |
1492 | DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV, | |
1493 | 1)) | |
9d556c99 | 1494 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
cd2d34d9 VS |
1495 | } |
1496 | ||
1497 | static void chv_enable_pll(struct intel_crtc *crtc, | |
1498 | const struct intel_crtc_state *pipe_config) | |
1499 | { | |
1500 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1501 | enum pipe pipe = crtc->pipe; | |
1502 | ||
1503 | assert_pipe_disabled(dev_priv, pipe); | |
1504 | ||
1505 | /* PLL is protected by panel, make sure we can write it */ | |
1506 | assert_panel_unlocked(dev_priv, pipe); | |
1507 | ||
1508 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) | |
1509 | _chv_enable_pll(crtc, pipe_config); | |
9d556c99 | 1510 | |
c231775c VS |
1511 | if (pipe != PIPE_A) { |
1512 | /* | |
1513 | * WaPixelRepeatModeFixForC0:chv | |
1514 | * | |
1515 | * DPLLCMD is AWOL. Use chicken bits to propagate | |
1516 | * the value from DPLLBMD to either pipe B or C. | |
1517 | */ | |
1518 | I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C); | |
1519 | I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); | |
1520 | I915_WRITE(CBR4_VLV, 0); | |
1521 | dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; | |
1522 | ||
1523 | /* | |
1524 | * DPLLB VGA mode also seems to cause problems. | |
1525 | * We should always have it disabled. | |
1526 | */ | |
1527 | WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); | |
1528 | } else { | |
1529 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); | |
1530 | POSTING_READ(DPLL_MD(pipe)); | |
1531 | } | |
9d556c99 CML |
1532 | } |
1533 | ||
6315b5d3 | 1534 | static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv) |
1c4e0274 VS |
1535 | { |
1536 | struct intel_crtc *crtc; | |
1537 | int count = 0; | |
1538 | ||
6315b5d3 | 1539 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
3538b9df | 1540 | count += crtc->base.state->active && |
2d84d2b3 VS |
1541 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO); |
1542 | } | |
1c4e0274 VS |
1543 | |
1544 | return count; | |
1545 | } | |
1546 | ||
66e3d5c0 | 1547 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1548 | { |
6315b5d3 | 1549 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
f0f59a00 | 1550 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1551 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1552 | |
66e3d5c0 | 1553 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1554 | |
63d7bbe9 | 1555 | /* PLL is protected by panel, make sure we can write it */ |
50a0bc90 | 1556 | if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv)) |
66e3d5c0 | 1557 | assert_panel_unlocked(dev_priv, crtc->pipe); |
63d7bbe9 | 1558 | |
1c4e0274 | 1559 | /* Enable DVO 2x clock on both PLLs if necessary */ |
6315b5d3 | 1560 | if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) { |
1c4e0274 VS |
1561 | /* |
1562 | * It appears to be important that we don't enable this | |
1563 | * for the current pipe before otherwise configuring the | |
1564 | * PLL. No idea how this should be handled if multiple | |
1565 | * DVO outputs are enabled simultaneosly. | |
1566 | */ | |
1567 | dpll |= DPLL_DVO_2X_MODE; | |
1568 | I915_WRITE(DPLL(!crtc->pipe), | |
1569 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1570 | } | |
66e3d5c0 | 1571 | |
c2b63374 VS |
1572 | /* |
1573 | * Apparently we need to have VGA mode enabled prior to changing | |
1574 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1575 | * dividers, even though the register value does change. | |
1576 | */ | |
1577 | I915_WRITE(reg, 0); | |
1578 | ||
8e7a65aa VS |
1579 | I915_WRITE(reg, dpll); |
1580 | ||
66e3d5c0 DV |
1581 | /* Wait for the clocks to stabilize. */ |
1582 | POSTING_READ(reg); | |
1583 | udelay(150); | |
1584 | ||
6315b5d3 | 1585 | if (INTEL_GEN(dev_priv) >= 4) { |
66e3d5c0 | 1586 | I915_WRITE(DPLL_MD(crtc->pipe), |
6e3c9717 | 1587 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1588 | } else { |
1589 | /* The pixel multiplier can only be updated once the | |
1590 | * DPLL is enabled and the clocks are stable. | |
1591 | * | |
1592 | * So write it again. | |
1593 | */ | |
1594 | I915_WRITE(reg, dpll); | |
1595 | } | |
63d7bbe9 JB |
1596 | |
1597 | /* We do this three times for luck */ | |
66e3d5c0 | 1598 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1599 | POSTING_READ(reg); |
1600 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1601 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1602 | POSTING_READ(reg); |
1603 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1604 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1605 | POSTING_READ(reg); |
1606 | udelay(150); /* wait for warmup */ | |
1607 | } | |
1608 | ||
1609 | /** | |
50b44a44 | 1610 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1611 | * @dev_priv: i915 private structure |
1612 | * @pipe: pipe PLL to disable | |
1613 | * | |
1614 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1615 | * | |
1616 | * Note! This is for pre-ILK only. | |
1617 | */ | |
1c4e0274 | 1618 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1619 | { |
6315b5d3 | 1620 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1c4e0274 VS |
1621 | enum pipe pipe = crtc->pipe; |
1622 | ||
1623 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
50a0bc90 | 1624 | if (IS_I830(dev_priv) && |
2d84d2b3 | 1625 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) && |
6315b5d3 | 1626 | !intel_num_dvo_pipes(dev_priv)) { |
1c4e0274 VS |
1627 | I915_WRITE(DPLL(PIPE_B), |
1628 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1629 | I915_WRITE(DPLL(PIPE_A), | |
1630 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1631 | } | |
1632 | ||
b6b5d049 VS |
1633 | /* Don't disable pipe or pipe PLLs if needed */ |
1634 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1635 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1636 | return; |
1637 | ||
1638 | /* Make sure the pipe isn't still relying on us */ | |
1639 | assert_pipe_disabled(dev_priv, pipe); | |
1640 | ||
b8afb911 | 1641 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1642 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1643 | } |
1644 | ||
f6071166 JB |
1645 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1646 | { | |
b8afb911 | 1647 | u32 val; |
f6071166 JB |
1648 | |
1649 | /* Make sure the pipe isn't still relying on us */ | |
1650 | assert_pipe_disabled(dev_priv, pipe); | |
1651 | ||
03ed5cbf VS |
1652 | val = DPLL_INTEGRATED_REF_CLK_VLV | |
1653 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
1654 | if (pipe != PIPE_A) | |
1655 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1656 | ||
f6071166 JB |
1657 | I915_WRITE(DPLL(pipe), val); |
1658 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1659 | } |
1660 | ||
1661 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1662 | { | |
d752048d | 1663 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1664 | u32 val; |
1665 | ||
a11b0703 VS |
1666 | /* Make sure the pipe isn't still relying on us */ |
1667 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1668 | |
60bfe44f VS |
1669 | val = DPLL_SSC_REF_CLK_CHV | |
1670 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1671 | if (pipe != PIPE_A) |
1672 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
03ed5cbf | 1673 | |
a11b0703 VS |
1674 | I915_WRITE(DPLL(pipe), val); |
1675 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1676 | |
a580516d | 1677 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1678 | |
1679 | /* Disable 10bit clock to display controller */ | |
1680 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1681 | val &= ~DPIO_DCLKP_EN; | |
1682 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1683 | ||
a580516d | 1684 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1685 | } |
1686 | ||
e4607fcf | 1687 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1688 | struct intel_digital_port *dport, |
1689 | unsigned int expected_mask) | |
89b667f8 JB |
1690 | { |
1691 | u32 port_mask; | |
f0f59a00 | 1692 | i915_reg_t dpll_reg; |
89b667f8 | 1693 | |
e4607fcf CML |
1694 | switch (dport->port) { |
1695 | case PORT_B: | |
89b667f8 | 1696 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1697 | dpll_reg = DPLL(0); |
e4607fcf CML |
1698 | break; |
1699 | case PORT_C: | |
89b667f8 | 1700 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1701 | dpll_reg = DPLL(0); |
9b6de0a1 | 1702 | expected_mask <<= 4; |
00fc31b7 CML |
1703 | break; |
1704 | case PORT_D: | |
1705 | port_mask = DPLL_PORTD_READY_MASK; | |
1706 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1707 | break; |
1708 | default: | |
1709 | BUG(); | |
1710 | } | |
89b667f8 | 1711 | |
370004d3 CW |
1712 | if (intel_wait_for_register(dev_priv, |
1713 | dpll_reg, port_mask, expected_mask, | |
1714 | 1000)) | |
9b6de0a1 VS |
1715 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", |
1716 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1717 | } |
1718 | ||
b8a4f404 PZ |
1719 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1720 | enum pipe pipe) | |
040484af | 1721 | { |
98187836 VS |
1722 | struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv, |
1723 | pipe); | |
f0f59a00 VS |
1724 | i915_reg_t reg; |
1725 | uint32_t val, pipeconf_val; | |
040484af | 1726 | |
040484af | 1727 | /* Make sure PCH DPLL is enabled */ |
8106ddbd | 1728 | assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll); |
040484af JB |
1729 | |
1730 | /* FDI must be feeding us bits for PCH ports */ | |
1731 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1732 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1733 | ||
6e266956 | 1734 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 DV |
1735 | /* Workaround: Set the timing override bit before enabling the |
1736 | * pch transcoder. */ | |
1737 | reg = TRANS_CHICKEN2(pipe); | |
1738 | val = I915_READ(reg); | |
1739 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1740 | I915_WRITE(reg, val); | |
59c859d6 | 1741 | } |
23670b32 | 1742 | |
ab9412ba | 1743 | reg = PCH_TRANSCONF(pipe); |
040484af | 1744 | val = I915_READ(reg); |
5f7f726d | 1745 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c | 1746 | |
2d1fe073 | 1747 | if (HAS_PCH_IBX(dev_priv)) { |
e9bcff5c | 1748 | /* |
c5de7c6f VS |
1749 | * Make the BPC in transcoder be consistent with |
1750 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1751 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1752 | */ |
dfd07d72 | 1753 | val &= ~PIPECONF_BPC_MASK; |
2d84d2b3 | 1754 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI)) |
c5de7c6f VS |
1755 | val |= PIPECONF_8BPC; |
1756 | else | |
1757 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1758 | } |
5f7f726d PZ |
1759 | |
1760 | val &= ~TRANS_INTERLACE_MASK; | |
1761 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
2d1fe073 | 1762 | if (HAS_PCH_IBX(dev_priv) && |
2d84d2b3 | 1763 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1764 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1765 | else | |
1766 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1767 | else |
1768 | val |= TRANS_PROGRESSIVE; | |
1769 | ||
040484af | 1770 | I915_WRITE(reg, val | TRANS_ENABLE); |
650fbd84 CW |
1771 | if (intel_wait_for_register(dev_priv, |
1772 | reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE, | |
1773 | 100)) | |
4bb6f1f3 | 1774 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1775 | } |
1776 | ||
8fb033d7 | 1777 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1778 | enum transcoder cpu_transcoder) |
040484af | 1779 | { |
8fb033d7 | 1780 | u32 val, pipeconf_val; |
8fb033d7 | 1781 | |
8fb033d7 | 1782 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1783 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1784 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1785 | |
223a6fdf | 1786 | /* Workaround: set timing override bit. */ |
36c0d0cf | 1787 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1788 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1789 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 1790 | |
25f3ef11 | 1791 | val = TRANS_ENABLE; |
937bb610 | 1792 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1793 | |
9a76b1c6 PZ |
1794 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1795 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1796 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1797 | else |
1798 | val |= TRANS_PROGRESSIVE; | |
1799 | ||
ab9412ba | 1800 | I915_WRITE(LPT_TRANSCONF, val); |
d9f96244 CW |
1801 | if (intel_wait_for_register(dev_priv, |
1802 | LPT_TRANSCONF, | |
1803 | TRANS_STATE_ENABLE, | |
1804 | TRANS_STATE_ENABLE, | |
1805 | 100)) | |
937bb610 | 1806 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1807 | } |
1808 | ||
b8a4f404 PZ |
1809 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1810 | enum pipe pipe) | |
040484af | 1811 | { |
f0f59a00 VS |
1812 | i915_reg_t reg; |
1813 | uint32_t val; | |
040484af JB |
1814 | |
1815 | /* FDI relies on the transcoder */ | |
1816 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1817 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1818 | ||
291906f1 JB |
1819 | /* Ports must be off as well */ |
1820 | assert_pch_ports_disabled(dev_priv, pipe); | |
1821 | ||
ab9412ba | 1822 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1823 | val = I915_READ(reg); |
1824 | val &= ~TRANS_ENABLE; | |
1825 | I915_WRITE(reg, val); | |
1826 | /* wait for PCH transcoder off, transcoder state */ | |
a7d04662 CW |
1827 | if (intel_wait_for_register(dev_priv, |
1828 | reg, TRANS_STATE_ENABLE, 0, | |
1829 | 50)) | |
4bb6f1f3 | 1830 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 1831 | |
6e266956 | 1832 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 DV |
1833 | /* Workaround: Clear the timing override chicken bit again. */ |
1834 | reg = TRANS_CHICKEN2(pipe); | |
1835 | val = I915_READ(reg); | |
1836 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1837 | I915_WRITE(reg, val); | |
1838 | } | |
040484af JB |
1839 | } |
1840 | ||
b7076546 | 1841 | void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1842 | { |
8fb033d7 PZ |
1843 | u32 val; |
1844 | ||
ab9412ba | 1845 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1846 | val &= ~TRANS_ENABLE; |
ab9412ba | 1847 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1848 | /* wait for PCH transcoder off, transcoder state */ |
dfdb4749 CW |
1849 | if (intel_wait_for_register(dev_priv, |
1850 | LPT_TRANSCONF, TRANS_STATE_ENABLE, 0, | |
1851 | 50)) | |
8a52fd9f | 1852 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1853 | |
1854 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 1855 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1856 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1857 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
1858 | } |
1859 | ||
65f2130c VS |
1860 | enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc) |
1861 | { | |
1862 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1863 | ||
1864 | WARN_ON(!crtc->config->has_pch_encoder); | |
1865 | ||
1866 | if (HAS_PCH_LPT(dev_priv)) | |
1867 | return TRANSCODER_A; | |
1868 | else | |
1869 | return (enum transcoder) crtc->pipe; | |
1870 | } | |
1871 | ||
b24e7179 | 1872 | /** |
309cfea8 | 1873 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1874 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1875 | * |
0372264a | 1876 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1877 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1878 | */ |
e1fdc473 | 1879 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1880 | { |
0372264a | 1881 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1882 | struct drm_i915_private *dev_priv = to_i915(dev); |
0372264a | 1883 | enum pipe pipe = crtc->pipe; |
1a70a728 | 1884 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
f0f59a00 | 1885 | i915_reg_t reg; |
b24e7179 JB |
1886 | u32 val; |
1887 | ||
9e2ee2dd VS |
1888 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
1889 | ||
58c6eaa2 | 1890 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1891 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1892 | assert_sprites_disabled(dev_priv, pipe); |
1893 | ||
b24e7179 JB |
1894 | /* |
1895 | * A pipe without a PLL won't actually be able to drive bits from | |
1896 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1897 | * need the check. | |
1898 | */ | |
09fa8bb9 | 1899 | if (HAS_GMCH_DISPLAY(dev_priv)) { |
d7edc4e5 | 1900 | if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
1901 | assert_dsi_pll_enabled(dev_priv); |
1902 | else | |
1903 | assert_pll_enabled(dev_priv, pipe); | |
09fa8bb9 | 1904 | } else { |
6e3c9717 | 1905 | if (crtc->config->has_pch_encoder) { |
040484af | 1906 | /* if driving the PCH, we need FDI enabled */ |
65f2130c VS |
1907 | assert_fdi_rx_pll_enabled(dev_priv, |
1908 | (enum pipe) intel_crtc_pch_transcoder(crtc)); | |
1a240d4d DV |
1909 | assert_fdi_tx_pll_enabled(dev_priv, |
1910 | (enum pipe) cpu_transcoder); | |
040484af JB |
1911 | } |
1912 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1913 | } | |
b24e7179 | 1914 | |
702e7a56 | 1915 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1916 | val = I915_READ(reg); |
7ad25d48 | 1917 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
1918 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
1919 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 1920 | return; |
7ad25d48 | 1921 | } |
00d70b15 CW |
1922 | |
1923 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 1924 | POSTING_READ(reg); |
b7792d8b VS |
1925 | |
1926 | /* | |
1927 | * Until the pipe starts DSL will read as 0, which would cause | |
1928 | * an apparent vblank timestamp jump, which messes up also the | |
1929 | * frame count when it's derived from the timestamps. So let's | |
1930 | * wait for the pipe to start properly before we call | |
1931 | * drm_crtc_vblank_on() | |
1932 | */ | |
1933 | if (dev->max_vblank_count == 0 && | |
1934 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
1935 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
1936 | } |
1937 | ||
1938 | /** | |
309cfea8 | 1939 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 1940 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 1941 | * |
575f7ab7 VS |
1942 | * Disable the pipe of @crtc, making sure that various hardware |
1943 | * specific requirements are met, if applicable, e.g. plane | |
1944 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
1945 | * |
1946 | * Will wait until the pipe has shut down before returning. | |
1947 | */ | |
575f7ab7 | 1948 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1949 | { |
fac5e23e | 1950 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 1951 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1952 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 1953 | i915_reg_t reg; |
b24e7179 JB |
1954 | u32 val; |
1955 | ||
9e2ee2dd VS |
1956 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
1957 | ||
b24e7179 JB |
1958 | /* |
1959 | * Make sure planes won't keep trying to pump pixels to us, | |
1960 | * or we might hang the display. | |
1961 | */ | |
1962 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 1963 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 1964 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 1965 | |
702e7a56 | 1966 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1967 | val = I915_READ(reg); |
00d70b15 CW |
1968 | if ((val & PIPECONF_ENABLE) == 0) |
1969 | return; | |
1970 | ||
67adc644 VS |
1971 | /* |
1972 | * Double wide has implications for planes | |
1973 | * so best keep it disabled when not needed. | |
1974 | */ | |
6e3c9717 | 1975 | if (crtc->config->double_wide) |
67adc644 VS |
1976 | val &= ~PIPECONF_DOUBLE_WIDE; |
1977 | ||
1978 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
1979 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
1980 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
1981 | val &= ~PIPECONF_ENABLE; |
1982 | ||
1983 | I915_WRITE(reg, val); | |
1984 | if ((val & PIPECONF_ENABLE) == 0) | |
1985 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
1986 | } |
1987 | ||
832be82f VS |
1988 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
1989 | { | |
1990 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
1991 | } | |
1992 | ||
27ba3910 VS |
1993 | static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv, |
1994 | uint64_t fb_modifier, unsigned int cpp) | |
7b49f948 VS |
1995 | { |
1996 | switch (fb_modifier) { | |
1997 | case DRM_FORMAT_MOD_NONE: | |
1998 | return cpp; | |
1999 | case I915_FORMAT_MOD_X_TILED: | |
2000 | if (IS_GEN2(dev_priv)) | |
2001 | return 128; | |
2002 | else | |
2003 | return 512; | |
2004 | case I915_FORMAT_MOD_Y_TILED: | |
2005 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2006 | return 128; | |
2007 | else | |
2008 | return 512; | |
2009 | case I915_FORMAT_MOD_Yf_TILED: | |
2010 | switch (cpp) { | |
2011 | case 1: | |
2012 | return 64; | |
2013 | case 2: | |
2014 | case 4: | |
2015 | return 128; | |
2016 | case 8: | |
2017 | case 16: | |
2018 | return 256; | |
2019 | default: | |
2020 | MISSING_CASE(cpp); | |
2021 | return cpp; | |
2022 | } | |
2023 | break; | |
2024 | default: | |
2025 | MISSING_CASE(fb_modifier); | |
2026 | return cpp; | |
2027 | } | |
2028 | } | |
2029 | ||
832be82f VS |
2030 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
2031 | uint64_t fb_modifier, unsigned int cpp) | |
a57ce0b2 | 2032 | { |
832be82f VS |
2033 | if (fb_modifier == DRM_FORMAT_MOD_NONE) |
2034 | return 1; | |
2035 | else | |
2036 | return intel_tile_size(dev_priv) / | |
27ba3910 | 2037 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
6761dd31 TU |
2038 | } |
2039 | ||
8d0deca8 VS |
2040 | /* Return the tile dimensions in pixel units */ |
2041 | static void intel_tile_dims(const struct drm_i915_private *dev_priv, | |
2042 | unsigned int *tile_width, | |
2043 | unsigned int *tile_height, | |
2044 | uint64_t fb_modifier, | |
2045 | unsigned int cpp) | |
2046 | { | |
2047 | unsigned int tile_width_bytes = | |
2048 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); | |
2049 | ||
2050 | *tile_width = tile_width_bytes / cpp; | |
2051 | *tile_height = intel_tile_size(dev_priv) / tile_width_bytes; | |
2052 | } | |
2053 | ||
6761dd31 | 2054 | unsigned int |
24dbf51a CW |
2055 | intel_fb_align_height(struct drm_i915_private *dev_priv, |
2056 | unsigned int height, | |
2057 | uint32_t pixel_format, | |
2058 | uint64_t fb_modifier) | |
6761dd31 | 2059 | { |
832be82f | 2060 | unsigned int cpp = drm_format_plane_cpp(pixel_format, 0); |
24dbf51a | 2061 | unsigned int tile_height = intel_tile_height(dev_priv, fb_modifier, cpp); |
832be82f VS |
2062 | |
2063 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2064 | } |
2065 | ||
1663b9d6 VS |
2066 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
2067 | { | |
2068 | unsigned int size = 0; | |
2069 | int i; | |
2070 | ||
2071 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2072 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2073 | ||
2074 | return size; | |
2075 | } | |
2076 | ||
75c82a53 | 2077 | static void |
3465c580 VS |
2078 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
2079 | const struct drm_framebuffer *fb, | |
2080 | unsigned int rotation) | |
f64b98cd | 2081 | { |
7b92c047 | 2082 | view->type = I915_GGTT_VIEW_NORMAL; |
bd2ef25d | 2083 | if (drm_rotation_90_or_270(rotation)) { |
7b92c047 | 2084 | view->type = I915_GGTT_VIEW_ROTATED; |
8bab1193 | 2085 | view->rotated = to_intel_framebuffer(fb)->rot_info; |
2d7a215f VS |
2086 | } |
2087 | } | |
50470bb0 | 2088 | |
603525d7 | 2089 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2090 | { |
2091 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2092 | return 256 * 1024; | |
c0f86832 | 2093 | else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) || |
666a4537 | 2094 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2095 | return 128 * 1024; |
2096 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2097 | return 4 * 1024; | |
2098 | else | |
44c5905e | 2099 | return 0; |
4e9a86b6 VS |
2100 | } |
2101 | ||
603525d7 VS |
2102 | static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv, |
2103 | uint64_t fb_modifier) | |
2104 | { | |
2105 | switch (fb_modifier) { | |
2106 | case DRM_FORMAT_MOD_NONE: | |
2107 | return intel_linear_alignment(dev_priv); | |
2108 | case I915_FORMAT_MOD_X_TILED: | |
2109 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2110 | return 256 * 1024; | |
2111 | return 0; | |
2112 | case I915_FORMAT_MOD_Y_TILED: | |
2113 | case I915_FORMAT_MOD_Yf_TILED: | |
2114 | return 1 * 1024 * 1024; | |
2115 | default: | |
2116 | MISSING_CASE(fb_modifier); | |
2117 | return 0; | |
2118 | } | |
2119 | } | |
2120 | ||
058d88c4 CW |
2121 | struct i915_vma * |
2122 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) | |
6b95a207 | 2123 | { |
850c4cdc | 2124 | struct drm_device *dev = fb->dev; |
fac5e23e | 2125 | struct drm_i915_private *dev_priv = to_i915(dev); |
850c4cdc | 2126 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2127 | struct i915_ggtt_view view; |
058d88c4 | 2128 | struct i915_vma *vma; |
6b95a207 | 2129 | u32 alignment; |
6b95a207 | 2130 | |
ebcdd39e MR |
2131 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2132 | ||
bae781b2 | 2133 | alignment = intel_surf_alignment(dev_priv, fb->modifier); |
6b95a207 | 2134 | |
3465c580 | 2135 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2136 | |
693db184 CW |
2137 | /* Note that the w/a also requires 64 PTE of padding following the |
2138 | * bo. We currently fill all unused PTE with the shadow page and so | |
2139 | * we should always have valid PTE following the scanout preventing | |
2140 | * the VT-d warning. | |
2141 | */ | |
48f112fe | 2142 | if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024) |
693db184 CW |
2143 | alignment = 256 * 1024; |
2144 | ||
d6dd6843 PZ |
2145 | /* |
2146 | * Global gtt pte registers are special registers which actually forward | |
2147 | * writes to a chunk of system memory. Which means that there is no risk | |
2148 | * that the register values disappear as soon as we call | |
2149 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2150 | * pin/unpin/fence and not more. | |
2151 | */ | |
2152 | intel_runtime_pm_get(dev_priv); | |
2153 | ||
058d88c4 | 2154 | vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view); |
49ef5294 CW |
2155 | if (IS_ERR(vma)) |
2156 | goto err; | |
6b95a207 | 2157 | |
05a20d09 | 2158 | if (i915_vma_is_map_and_fenceable(vma)) { |
49ef5294 CW |
2159 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
2160 | * fence, whereas 965+ only requires a fence if using | |
2161 | * framebuffer compression. For simplicity, we always, when | |
2162 | * possible, install a fence as the cost is not that onerous. | |
2163 | * | |
2164 | * If we fail to fence the tiled scanout, then either the | |
2165 | * modeset will reject the change (which is highly unlikely as | |
2166 | * the affected systems, all but one, do not have unmappable | |
2167 | * space) or we will not be able to enable full powersaving | |
2168 | * techniques (also likely not to apply due to various limits | |
2169 | * FBC and the like impose on the size of the buffer, which | |
2170 | * presumably we violated anyway with this unmappable buffer). | |
2171 | * Anyway, it is presumably better to stumble onwards with | |
2172 | * something and try to run the system in a "less than optimal" | |
2173 | * mode that matches the user configuration. | |
2174 | */ | |
2175 | if (i915_vma_get_fence(vma) == 0) | |
2176 | i915_vma_pin_fence(vma); | |
9807216f | 2177 | } |
6b95a207 | 2178 | |
be1e3415 | 2179 | i915_vma_get(vma); |
49ef5294 | 2180 | err: |
d6dd6843 | 2181 | intel_runtime_pm_put(dev_priv); |
058d88c4 | 2182 | return vma; |
6b95a207 KH |
2183 | } |
2184 | ||
be1e3415 | 2185 | void intel_unpin_fb_vma(struct i915_vma *vma) |
1690e1eb | 2186 | { |
be1e3415 | 2187 | lockdep_assert_held(&vma->vm->i915->drm.struct_mutex); |
f64b98cd | 2188 | |
49ef5294 | 2189 | i915_vma_unpin_fence(vma); |
058d88c4 | 2190 | i915_gem_object_unpin_from_display_plane(vma); |
be1e3415 | 2191 | i915_vma_put(vma); |
1690e1eb CW |
2192 | } |
2193 | ||
ef78ec94 VS |
2194 | static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane, |
2195 | unsigned int rotation) | |
2196 | { | |
bd2ef25d | 2197 | if (drm_rotation_90_or_270(rotation)) |
ef78ec94 VS |
2198 | return to_intel_framebuffer(fb)->rotated[plane].pitch; |
2199 | else | |
2200 | return fb->pitches[plane]; | |
2201 | } | |
2202 | ||
6687c906 VS |
2203 | /* |
2204 | * Convert the x/y offsets into a linear offset. | |
2205 | * Only valid with 0/180 degree rotation, which is fine since linear | |
2206 | * offset is only used with linear buffers on pre-hsw and tiled buffers | |
2207 | * with gen2/3, and 90/270 degree rotations isn't supported on any of them. | |
2208 | */ | |
2209 | u32 intel_fb_xy_to_linear(int x, int y, | |
2949056c VS |
2210 | const struct intel_plane_state *state, |
2211 | int plane) | |
6687c906 | 2212 | { |
2949056c | 2213 | const struct drm_framebuffer *fb = state->base.fb; |
353c8598 | 2214 | unsigned int cpp = fb->format->cpp[plane]; |
6687c906 VS |
2215 | unsigned int pitch = fb->pitches[plane]; |
2216 | ||
2217 | return y * pitch + x * cpp; | |
2218 | } | |
2219 | ||
2220 | /* | |
2221 | * Add the x/y offsets derived from fb->offsets[] to the user | |
2222 | * specified plane src x/y offsets. The resulting x/y offsets | |
2223 | * specify the start of scanout from the beginning of the gtt mapping. | |
2224 | */ | |
2225 | void intel_add_fb_offsets(int *x, int *y, | |
2949056c VS |
2226 | const struct intel_plane_state *state, |
2227 | int plane) | |
6687c906 VS |
2228 | |
2229 | { | |
2949056c VS |
2230 | const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb); |
2231 | unsigned int rotation = state->base.rotation; | |
6687c906 | 2232 | |
bd2ef25d | 2233 | if (drm_rotation_90_or_270(rotation)) { |
6687c906 VS |
2234 | *x += intel_fb->rotated[plane].x; |
2235 | *y += intel_fb->rotated[plane].y; | |
2236 | } else { | |
2237 | *x += intel_fb->normal[plane].x; | |
2238 | *y += intel_fb->normal[plane].y; | |
2239 | } | |
2240 | } | |
2241 | ||
29cf9491 | 2242 | /* |
29cf9491 VS |
2243 | * Input tile dimensions and pitch must already be |
2244 | * rotated to match x and y, and in pixel units. | |
2245 | */ | |
66a2d927 VS |
2246 | static u32 _intel_adjust_tile_offset(int *x, int *y, |
2247 | unsigned int tile_width, | |
2248 | unsigned int tile_height, | |
2249 | unsigned int tile_size, | |
2250 | unsigned int pitch_tiles, | |
2251 | u32 old_offset, | |
2252 | u32 new_offset) | |
29cf9491 | 2253 | { |
b9b24038 | 2254 | unsigned int pitch_pixels = pitch_tiles * tile_width; |
29cf9491 VS |
2255 | unsigned int tiles; |
2256 | ||
2257 | WARN_ON(old_offset & (tile_size - 1)); | |
2258 | WARN_ON(new_offset & (tile_size - 1)); | |
2259 | WARN_ON(new_offset > old_offset); | |
2260 | ||
2261 | tiles = (old_offset - new_offset) / tile_size; | |
2262 | ||
2263 | *y += tiles / pitch_tiles * tile_height; | |
2264 | *x += tiles % pitch_tiles * tile_width; | |
2265 | ||
b9b24038 VS |
2266 | /* minimize x in case it got needlessly big */ |
2267 | *y += *x / pitch_pixels * tile_height; | |
2268 | *x %= pitch_pixels; | |
2269 | ||
29cf9491 VS |
2270 | return new_offset; |
2271 | } | |
2272 | ||
66a2d927 VS |
2273 | /* |
2274 | * Adjust the tile offset by moving the difference into | |
2275 | * the x/y offsets. | |
2276 | */ | |
2277 | static u32 intel_adjust_tile_offset(int *x, int *y, | |
2278 | const struct intel_plane_state *state, int plane, | |
2279 | u32 old_offset, u32 new_offset) | |
2280 | { | |
2281 | const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev); | |
2282 | const struct drm_framebuffer *fb = state->base.fb; | |
353c8598 | 2283 | unsigned int cpp = fb->format->cpp[plane]; |
66a2d927 VS |
2284 | unsigned int rotation = state->base.rotation; |
2285 | unsigned int pitch = intel_fb_pitch(fb, plane, rotation); | |
2286 | ||
2287 | WARN_ON(new_offset > old_offset); | |
2288 | ||
bae781b2 | 2289 | if (fb->modifier != DRM_FORMAT_MOD_NONE) { |
66a2d927 VS |
2290 | unsigned int tile_size, tile_width, tile_height; |
2291 | unsigned int pitch_tiles; | |
2292 | ||
2293 | tile_size = intel_tile_size(dev_priv); | |
2294 | intel_tile_dims(dev_priv, &tile_width, &tile_height, | |
bae781b2 | 2295 | fb->modifier, cpp); |
66a2d927 | 2296 | |
bd2ef25d | 2297 | if (drm_rotation_90_or_270(rotation)) { |
66a2d927 VS |
2298 | pitch_tiles = pitch / tile_height; |
2299 | swap(tile_width, tile_height); | |
2300 | } else { | |
2301 | pitch_tiles = pitch / (tile_width * cpp); | |
2302 | } | |
2303 | ||
2304 | _intel_adjust_tile_offset(x, y, tile_width, tile_height, | |
2305 | tile_size, pitch_tiles, | |
2306 | old_offset, new_offset); | |
2307 | } else { | |
2308 | old_offset += *y * pitch + *x * cpp; | |
2309 | ||
2310 | *y = (old_offset - new_offset) / pitch; | |
2311 | *x = ((old_offset - new_offset) - *y * pitch) / cpp; | |
2312 | } | |
2313 | ||
2314 | return new_offset; | |
2315 | } | |
2316 | ||
8d0deca8 VS |
2317 | /* |
2318 | * Computes the linear offset to the base tile and adjusts | |
2319 | * x, y. bytes per pixel is assumed to be a power-of-two. | |
2320 | * | |
2321 | * In the 90/270 rotated case, x and y are assumed | |
2322 | * to be already rotated to match the rotated GTT view, and | |
2323 | * pitch is the tile_height aligned framebuffer height. | |
6687c906 VS |
2324 | * |
2325 | * This function is used when computing the derived information | |
2326 | * under intel_framebuffer, so using any of that information | |
2327 | * here is not allowed. Anything under drm_framebuffer can be | |
2328 | * used. This is why the user has to pass in the pitch since it | |
2329 | * is specified in the rotated orientation. | |
8d0deca8 | 2330 | */ |
6687c906 VS |
2331 | static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv, |
2332 | int *x, int *y, | |
2333 | const struct drm_framebuffer *fb, int plane, | |
2334 | unsigned int pitch, | |
2335 | unsigned int rotation, | |
2336 | u32 alignment) | |
c2c75131 | 2337 | { |
bae781b2 | 2338 | uint64_t fb_modifier = fb->modifier; |
353c8598 | 2339 | unsigned int cpp = fb->format->cpp[plane]; |
6687c906 | 2340 | u32 offset, offset_aligned; |
29cf9491 | 2341 | |
29cf9491 VS |
2342 | if (alignment) |
2343 | alignment--; | |
2344 | ||
b5c65338 | 2345 | if (fb_modifier != DRM_FORMAT_MOD_NONE) { |
8d0deca8 VS |
2346 | unsigned int tile_size, tile_width, tile_height; |
2347 | unsigned int tile_rows, tiles, pitch_tiles; | |
c2c75131 | 2348 | |
d843310d | 2349 | tile_size = intel_tile_size(dev_priv); |
8d0deca8 VS |
2350 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2351 | fb_modifier, cpp); | |
2352 | ||
bd2ef25d | 2353 | if (drm_rotation_90_or_270(rotation)) { |
8d0deca8 VS |
2354 | pitch_tiles = pitch / tile_height; |
2355 | swap(tile_width, tile_height); | |
2356 | } else { | |
2357 | pitch_tiles = pitch / (tile_width * cpp); | |
2358 | } | |
d843310d VS |
2359 | |
2360 | tile_rows = *y / tile_height; | |
2361 | *y %= tile_height; | |
c2c75131 | 2362 | |
8d0deca8 VS |
2363 | tiles = *x / tile_width; |
2364 | *x %= tile_width; | |
bc752862 | 2365 | |
29cf9491 VS |
2366 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
2367 | offset_aligned = offset & ~alignment; | |
bc752862 | 2368 | |
66a2d927 VS |
2369 | _intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2370 | tile_size, pitch_tiles, | |
2371 | offset, offset_aligned); | |
29cf9491 | 2372 | } else { |
bc752862 | 2373 | offset = *y * pitch + *x * cpp; |
29cf9491 VS |
2374 | offset_aligned = offset & ~alignment; |
2375 | ||
4e9a86b6 VS |
2376 | *y = (offset & alignment) / pitch; |
2377 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
bc752862 | 2378 | } |
29cf9491 VS |
2379 | |
2380 | return offset_aligned; | |
c2c75131 DV |
2381 | } |
2382 | ||
6687c906 | 2383 | u32 intel_compute_tile_offset(int *x, int *y, |
2949056c VS |
2384 | const struct intel_plane_state *state, |
2385 | int plane) | |
6687c906 | 2386 | { |
2949056c VS |
2387 | const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev); |
2388 | const struct drm_framebuffer *fb = state->base.fb; | |
2389 | unsigned int rotation = state->base.rotation; | |
ef78ec94 | 2390 | int pitch = intel_fb_pitch(fb, plane, rotation); |
8d970654 VS |
2391 | u32 alignment; |
2392 | ||
2393 | /* AUX_DIST needs only 4K alignment */ | |
438b74a5 | 2394 | if (fb->format->format == DRM_FORMAT_NV12 && plane == 1) |
8d970654 VS |
2395 | alignment = 4096; |
2396 | else | |
bae781b2 | 2397 | alignment = intel_surf_alignment(dev_priv, fb->modifier); |
6687c906 VS |
2398 | |
2399 | return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch, | |
2400 | rotation, alignment); | |
2401 | } | |
2402 | ||
2403 | /* Convert the fb->offset[] linear offset into x/y offsets */ | |
2404 | static void intel_fb_offset_to_xy(int *x, int *y, | |
2405 | const struct drm_framebuffer *fb, int plane) | |
2406 | { | |
353c8598 | 2407 | unsigned int cpp = fb->format->cpp[plane]; |
6687c906 VS |
2408 | unsigned int pitch = fb->pitches[plane]; |
2409 | u32 linear_offset = fb->offsets[plane]; | |
2410 | ||
2411 | *y = linear_offset / pitch; | |
2412 | *x = linear_offset % pitch / cpp; | |
2413 | } | |
2414 | ||
72618ebf VS |
2415 | static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier) |
2416 | { | |
2417 | switch (fb_modifier) { | |
2418 | case I915_FORMAT_MOD_X_TILED: | |
2419 | return I915_TILING_X; | |
2420 | case I915_FORMAT_MOD_Y_TILED: | |
2421 | return I915_TILING_Y; | |
2422 | default: | |
2423 | return I915_TILING_NONE; | |
2424 | } | |
2425 | } | |
2426 | ||
6687c906 VS |
2427 | static int |
2428 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
2429 | struct drm_framebuffer *fb) | |
2430 | { | |
2431 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
2432 | struct intel_rotation_info *rot_info = &intel_fb->rot_info; | |
2433 | u32 gtt_offset_rotated = 0; | |
2434 | unsigned int max_size = 0; | |
bcb0b461 | 2435 | int i, num_planes = fb->format->num_planes; |
6687c906 VS |
2436 | unsigned int tile_size = intel_tile_size(dev_priv); |
2437 | ||
2438 | for (i = 0; i < num_planes; i++) { | |
2439 | unsigned int width, height; | |
2440 | unsigned int cpp, size; | |
2441 | u32 offset; | |
2442 | int x, y; | |
2443 | ||
353c8598 | 2444 | cpp = fb->format->cpp[i]; |
145fcb11 VS |
2445 | width = drm_framebuffer_plane_width(fb->width, fb, i); |
2446 | height = drm_framebuffer_plane_height(fb->height, fb, i); | |
6687c906 VS |
2447 | |
2448 | intel_fb_offset_to_xy(&x, &y, fb, i); | |
2449 | ||
60d5f2a4 VS |
2450 | /* |
2451 | * The fence (if used) is aligned to the start of the object | |
2452 | * so having the framebuffer wrap around across the edge of the | |
2453 | * fenced region doesn't really work. We have no API to configure | |
2454 | * the fence start offset within the object (nor could we probably | |
2455 | * on gen2/3). So it's just easier if we just require that the | |
2456 | * fb layout agrees with the fence layout. We already check that the | |
2457 | * fb stride matches the fence stride elsewhere. | |
2458 | */ | |
2459 | if (i915_gem_object_is_tiled(intel_fb->obj) && | |
2460 | (x + width) * cpp > fb->pitches[i]) { | |
2461 | DRM_DEBUG("bad fb plane %d offset: 0x%x\n", | |
2462 | i, fb->offsets[i]); | |
2463 | return -EINVAL; | |
2464 | } | |
2465 | ||
6687c906 VS |
2466 | /* |
2467 | * First pixel of the framebuffer from | |
2468 | * the start of the normal gtt mapping. | |
2469 | */ | |
2470 | intel_fb->normal[i].x = x; | |
2471 | intel_fb->normal[i].y = y; | |
2472 | ||
2473 | offset = _intel_compute_tile_offset(dev_priv, &x, &y, | |
2474 | fb, 0, fb->pitches[i], | |
cc926387 | 2475 | DRM_ROTATE_0, tile_size); |
6687c906 VS |
2476 | offset /= tile_size; |
2477 | ||
bae781b2 | 2478 | if (fb->modifier != DRM_FORMAT_MOD_NONE) { |
6687c906 VS |
2479 | unsigned int tile_width, tile_height; |
2480 | unsigned int pitch_tiles; | |
2481 | struct drm_rect r; | |
2482 | ||
2483 | intel_tile_dims(dev_priv, &tile_width, &tile_height, | |
bae781b2 | 2484 | fb->modifier, cpp); |
6687c906 VS |
2485 | |
2486 | rot_info->plane[i].offset = offset; | |
2487 | rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp); | |
2488 | rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width); | |
2489 | rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height); | |
2490 | ||
2491 | intel_fb->rotated[i].pitch = | |
2492 | rot_info->plane[i].height * tile_height; | |
2493 | ||
2494 | /* how many tiles does this plane need */ | |
2495 | size = rot_info->plane[i].stride * rot_info->plane[i].height; | |
2496 | /* | |
2497 | * If the plane isn't horizontally tile aligned, | |
2498 | * we need one more tile. | |
2499 | */ | |
2500 | if (x != 0) | |
2501 | size++; | |
2502 | ||
2503 | /* rotate the x/y offsets to match the GTT view */ | |
2504 | r.x1 = x; | |
2505 | r.y1 = y; | |
2506 | r.x2 = x + width; | |
2507 | r.y2 = y + height; | |
2508 | drm_rect_rotate(&r, | |
2509 | rot_info->plane[i].width * tile_width, | |
2510 | rot_info->plane[i].height * tile_height, | |
cc926387 | 2511 | DRM_ROTATE_270); |
6687c906 VS |
2512 | x = r.x1; |
2513 | y = r.y1; | |
2514 | ||
2515 | /* rotate the tile dimensions to match the GTT view */ | |
2516 | pitch_tiles = intel_fb->rotated[i].pitch / tile_height; | |
2517 | swap(tile_width, tile_height); | |
2518 | ||
2519 | /* | |
2520 | * We only keep the x/y offsets, so push all of the | |
2521 | * gtt offset into the x/y offsets. | |
2522 | */ | |
46a1bd28 ACO |
2523 | _intel_adjust_tile_offset(&x, &y, |
2524 | tile_width, tile_height, | |
2525 | tile_size, pitch_tiles, | |
66a2d927 | 2526 | gtt_offset_rotated * tile_size, 0); |
6687c906 VS |
2527 | |
2528 | gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height; | |
2529 | ||
2530 | /* | |
2531 | * First pixel of the framebuffer from | |
2532 | * the start of the rotated gtt mapping. | |
2533 | */ | |
2534 | intel_fb->rotated[i].x = x; | |
2535 | intel_fb->rotated[i].y = y; | |
2536 | } else { | |
2537 | size = DIV_ROUND_UP((y + height) * fb->pitches[i] + | |
2538 | x * cpp, tile_size); | |
2539 | } | |
2540 | ||
2541 | /* how many tiles in total needed in the bo */ | |
2542 | max_size = max(max_size, offset + size); | |
2543 | } | |
2544 | ||
2545 | if (max_size * tile_size > to_intel_framebuffer(fb)->obj->base.size) { | |
2546 | DRM_DEBUG("fb too big for bo (need %u bytes, have %zu bytes)\n", | |
2547 | max_size * tile_size, to_intel_framebuffer(fb)->obj->base.size); | |
2548 | return -EINVAL; | |
2549 | } | |
2550 | ||
2551 | return 0; | |
2552 | } | |
2553 | ||
b35d63fa | 2554 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2555 | { |
2556 | switch (format) { | |
2557 | case DISPPLANE_8BPP: | |
2558 | return DRM_FORMAT_C8; | |
2559 | case DISPPLANE_BGRX555: | |
2560 | return DRM_FORMAT_XRGB1555; | |
2561 | case DISPPLANE_BGRX565: | |
2562 | return DRM_FORMAT_RGB565; | |
2563 | default: | |
2564 | case DISPPLANE_BGRX888: | |
2565 | return DRM_FORMAT_XRGB8888; | |
2566 | case DISPPLANE_RGBX888: | |
2567 | return DRM_FORMAT_XBGR8888; | |
2568 | case DISPPLANE_BGRX101010: | |
2569 | return DRM_FORMAT_XRGB2101010; | |
2570 | case DISPPLANE_RGBX101010: | |
2571 | return DRM_FORMAT_XBGR2101010; | |
2572 | } | |
2573 | } | |
2574 | ||
bc8d7dff DL |
2575 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2576 | { | |
2577 | switch (format) { | |
2578 | case PLANE_CTL_FORMAT_RGB_565: | |
2579 | return DRM_FORMAT_RGB565; | |
2580 | default: | |
2581 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2582 | if (rgb_order) { | |
2583 | if (alpha) | |
2584 | return DRM_FORMAT_ABGR8888; | |
2585 | else | |
2586 | return DRM_FORMAT_XBGR8888; | |
2587 | } else { | |
2588 | if (alpha) | |
2589 | return DRM_FORMAT_ARGB8888; | |
2590 | else | |
2591 | return DRM_FORMAT_XRGB8888; | |
2592 | } | |
2593 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2594 | if (rgb_order) | |
2595 | return DRM_FORMAT_XBGR2101010; | |
2596 | else | |
2597 | return DRM_FORMAT_XRGB2101010; | |
2598 | } | |
2599 | } | |
2600 | ||
5724dbd1 | 2601 | static bool |
f6936e29 DV |
2602 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2603 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2604 | { |
2605 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2606 | struct drm_i915_private *dev_priv = to_i915(dev); |
72e96d64 | 2607 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
46f297fb JB |
2608 | struct drm_i915_gem_object *obj = NULL; |
2609 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2610 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2611 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2612 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2613 | PAGE_SIZE); | |
2614 | ||
2615 | size_aligned -= base_aligned; | |
46f297fb | 2616 | |
ff2652ea CW |
2617 | if (plane_config->size == 0) |
2618 | return false; | |
2619 | ||
3badb49f PZ |
2620 | /* If the FB is too big, just don't use it since fbdev is not very |
2621 | * important and we should probably use that space with FBC or other | |
2622 | * features. */ | |
72e96d64 | 2623 | if (size_aligned * 2 > ggtt->stolen_usable_size) |
3badb49f PZ |
2624 | return false; |
2625 | ||
12c83d99 | 2626 | mutex_lock(&dev->struct_mutex); |
187685cb | 2627 | obj = i915_gem_object_create_stolen_for_preallocated(dev_priv, |
f37b5c2b DV |
2628 | base_aligned, |
2629 | base_aligned, | |
2630 | size_aligned); | |
24dbf51a CW |
2631 | mutex_unlock(&dev->struct_mutex); |
2632 | if (!obj) | |
484b41dd | 2633 | return false; |
46f297fb | 2634 | |
3e510a8e CW |
2635 | if (plane_config->tiling == I915_TILING_X) |
2636 | obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X; | |
46f297fb | 2637 | |
438b74a5 | 2638 | mode_cmd.pixel_format = fb->format->format; |
6bf129df DL |
2639 | mode_cmd.width = fb->width; |
2640 | mode_cmd.height = fb->height; | |
2641 | mode_cmd.pitches[0] = fb->pitches[0]; | |
bae781b2 | 2642 | mode_cmd.modifier[0] = fb->modifier; |
18c5247e | 2643 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; |
46f297fb | 2644 | |
24dbf51a | 2645 | if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) { |
46f297fb JB |
2646 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2647 | goto out_unref_obj; | |
2648 | } | |
12c83d99 | 2649 | |
484b41dd | 2650 | |
f6936e29 | 2651 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2652 | return true; |
46f297fb JB |
2653 | |
2654 | out_unref_obj: | |
f8c417cd | 2655 | i915_gem_object_put(obj); |
484b41dd JB |
2656 | return false; |
2657 | } | |
2658 | ||
5a21b665 DV |
2659 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2660 | static void | |
2661 | update_state_fb(struct drm_plane *plane) | |
2662 | { | |
2663 | if (plane->fb == plane->state->fb) | |
2664 | return; | |
2665 | ||
2666 | if (plane->state->fb) | |
2667 | drm_framebuffer_unreference(plane->state->fb); | |
2668 | plane->state->fb = plane->fb; | |
2669 | if (plane->state->fb) | |
2670 | drm_framebuffer_reference(plane->state->fb); | |
2671 | } | |
2672 | ||
5724dbd1 | 2673 | static void |
f6936e29 DV |
2674 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2675 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2676 | { |
2677 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 2678 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 2679 | struct drm_crtc *c; |
2ff8fde1 | 2680 | struct drm_i915_gem_object *obj; |
88595ac9 | 2681 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2682 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2683 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2684 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2685 | struct intel_plane_state *intel_state = |
2686 | to_intel_plane_state(plane_state); | |
88595ac9 | 2687 | struct drm_framebuffer *fb; |
484b41dd | 2688 | |
2d14030b | 2689 | if (!plane_config->fb) |
484b41dd JB |
2690 | return; |
2691 | ||
f6936e29 | 2692 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2693 | fb = &plane_config->fb->base; |
2694 | goto valid_fb; | |
f55548b5 | 2695 | } |
484b41dd | 2696 | |
2d14030b | 2697 | kfree(plane_config->fb); |
484b41dd JB |
2698 | |
2699 | /* | |
2700 | * Failed to alloc the obj, check to see if we should share | |
2701 | * an fb with another CRTC instead | |
2702 | */ | |
70e1e0ec | 2703 | for_each_crtc(dev, c) { |
be1e3415 | 2704 | struct intel_plane_state *state; |
484b41dd JB |
2705 | |
2706 | if (c == &intel_crtc->base) | |
2707 | continue; | |
2708 | ||
be1e3415 | 2709 | if (!to_intel_crtc(c)->active) |
2ff8fde1 MR |
2710 | continue; |
2711 | ||
be1e3415 CW |
2712 | state = to_intel_plane_state(c->primary->state); |
2713 | if (!state->vma) | |
484b41dd JB |
2714 | continue; |
2715 | ||
be1e3415 CW |
2716 | if (intel_plane_ggtt_offset(state) == plane_config->base) { |
2717 | fb = c->primary->fb; | |
88595ac9 DV |
2718 | drm_framebuffer_reference(fb); |
2719 | goto valid_fb; | |
484b41dd JB |
2720 | } |
2721 | } | |
88595ac9 | 2722 | |
200757f5 MR |
2723 | /* |
2724 | * We've failed to reconstruct the BIOS FB. Current display state | |
2725 | * indicates that the primary plane is visible, but has a NULL FB, | |
2726 | * which will lead to problems later if we don't fix it up. The | |
2727 | * simplest solution is to just disable the primary plane now and | |
2728 | * pretend the BIOS never had it enabled. | |
2729 | */ | |
1d4258db | 2730 | plane_state->visible = false; |
200757f5 | 2731 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); |
2622a081 | 2732 | intel_pre_disable_primary_noatomic(&intel_crtc->base); |
200757f5 MR |
2733 | intel_plane->disable_plane(primary, &intel_crtc->base); |
2734 | ||
88595ac9 DV |
2735 | return; |
2736 | ||
2737 | valid_fb: | |
be1e3415 CW |
2738 | mutex_lock(&dev->struct_mutex); |
2739 | intel_state->vma = | |
2740 | intel_pin_and_fence_fb_obj(fb, primary->state->rotation); | |
2741 | mutex_unlock(&dev->struct_mutex); | |
2742 | if (IS_ERR(intel_state->vma)) { | |
2743 | DRM_ERROR("failed to pin boot fb on pipe %d: %li\n", | |
2744 | intel_crtc->pipe, PTR_ERR(intel_state->vma)); | |
2745 | ||
2746 | intel_state->vma = NULL; | |
2747 | drm_framebuffer_unreference(fb); | |
2748 | return; | |
2749 | } | |
2750 | ||
f44e2659 VS |
2751 | plane_state->src_x = 0; |
2752 | plane_state->src_y = 0; | |
be5651f2 ML |
2753 | plane_state->src_w = fb->width << 16; |
2754 | plane_state->src_h = fb->height << 16; | |
2755 | ||
f44e2659 VS |
2756 | plane_state->crtc_x = 0; |
2757 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2758 | plane_state->crtc_w = fb->width; |
2759 | plane_state->crtc_h = fb->height; | |
2760 | ||
1638d30c RC |
2761 | intel_state->base.src = drm_plane_state_src(plane_state); |
2762 | intel_state->base.dst = drm_plane_state_dest(plane_state); | |
0a8d8a86 | 2763 | |
88595ac9 | 2764 | obj = intel_fb_obj(fb); |
3e510a8e | 2765 | if (i915_gem_object_is_tiled(obj)) |
88595ac9 DV |
2766 | dev_priv->preserve_bios_swizzle = true; |
2767 | ||
be5651f2 ML |
2768 | drm_framebuffer_reference(fb); |
2769 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2770 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2771 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
faf5bf0a CW |
2772 | atomic_or(to_intel_plane(primary)->frontbuffer_bit, |
2773 | &obj->frontbuffer_bits); | |
46f297fb JB |
2774 | } |
2775 | ||
b63a16f6 VS |
2776 | static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane, |
2777 | unsigned int rotation) | |
2778 | { | |
353c8598 | 2779 | int cpp = fb->format->cpp[plane]; |
b63a16f6 | 2780 | |
bae781b2 | 2781 | switch (fb->modifier) { |
b63a16f6 VS |
2782 | case DRM_FORMAT_MOD_NONE: |
2783 | case I915_FORMAT_MOD_X_TILED: | |
2784 | switch (cpp) { | |
2785 | case 8: | |
2786 | return 4096; | |
2787 | case 4: | |
2788 | case 2: | |
2789 | case 1: | |
2790 | return 8192; | |
2791 | default: | |
2792 | MISSING_CASE(cpp); | |
2793 | break; | |
2794 | } | |
2795 | break; | |
2796 | case I915_FORMAT_MOD_Y_TILED: | |
2797 | case I915_FORMAT_MOD_Yf_TILED: | |
2798 | switch (cpp) { | |
2799 | case 8: | |
2800 | return 2048; | |
2801 | case 4: | |
2802 | return 4096; | |
2803 | case 2: | |
2804 | case 1: | |
2805 | return 8192; | |
2806 | default: | |
2807 | MISSING_CASE(cpp); | |
2808 | break; | |
2809 | } | |
2810 | break; | |
2811 | default: | |
bae781b2 | 2812 | MISSING_CASE(fb->modifier); |
b63a16f6 VS |
2813 | } |
2814 | ||
2815 | return 2048; | |
2816 | } | |
2817 | ||
2818 | static int skl_check_main_surface(struct intel_plane_state *plane_state) | |
2819 | { | |
2820 | const struct drm_i915_private *dev_priv = to_i915(plane_state->base.plane->dev); | |
2821 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2822 | unsigned int rotation = plane_state->base.rotation; | |
cc926387 DV |
2823 | int x = plane_state->base.src.x1 >> 16; |
2824 | int y = plane_state->base.src.y1 >> 16; | |
2825 | int w = drm_rect_width(&plane_state->base.src) >> 16; | |
2826 | int h = drm_rect_height(&plane_state->base.src) >> 16; | |
b63a16f6 VS |
2827 | int max_width = skl_max_plane_width(fb, 0, rotation); |
2828 | int max_height = 4096; | |
8d970654 | 2829 | u32 alignment, offset, aux_offset = plane_state->aux.offset; |
b63a16f6 VS |
2830 | |
2831 | if (w > max_width || h > max_height) { | |
2832 | DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n", | |
2833 | w, h, max_width, max_height); | |
2834 | return -EINVAL; | |
2835 | } | |
2836 | ||
2837 | intel_add_fb_offsets(&x, &y, plane_state, 0); | |
2838 | offset = intel_compute_tile_offset(&x, &y, plane_state, 0); | |
2839 | ||
bae781b2 | 2840 | alignment = intel_surf_alignment(dev_priv, fb->modifier); |
b63a16f6 | 2841 | |
8d970654 VS |
2842 | /* |
2843 | * AUX surface offset is specified as the distance from the | |
2844 | * main surface offset, and it must be non-negative. Make | |
2845 | * sure that is what we will get. | |
2846 | */ | |
2847 | if (offset > aux_offset) | |
2848 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
2849 | offset, aux_offset & ~(alignment - 1)); | |
2850 | ||
b63a16f6 VS |
2851 | /* |
2852 | * When using an X-tiled surface, the plane blows up | |
2853 | * if the x offset + width exceed the stride. | |
2854 | * | |
2855 | * TODO: linear and Y-tiled seem fine, Yf untested, | |
2856 | */ | |
bae781b2 | 2857 | if (fb->modifier == I915_FORMAT_MOD_X_TILED) { |
353c8598 | 2858 | int cpp = fb->format->cpp[0]; |
b63a16f6 VS |
2859 | |
2860 | while ((x + w) * cpp > fb->pitches[0]) { | |
2861 | if (offset == 0) { | |
2862 | DRM_DEBUG_KMS("Unable to find suitable display surface offset\n"); | |
2863 | return -EINVAL; | |
2864 | } | |
2865 | ||
2866 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
2867 | offset, offset - alignment); | |
2868 | } | |
2869 | } | |
2870 | ||
2871 | plane_state->main.offset = offset; | |
2872 | plane_state->main.x = x; | |
2873 | plane_state->main.y = y; | |
2874 | ||
2875 | return 0; | |
2876 | } | |
2877 | ||
8d970654 VS |
2878 | static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) |
2879 | { | |
2880 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2881 | unsigned int rotation = plane_state->base.rotation; | |
2882 | int max_width = skl_max_plane_width(fb, 1, rotation); | |
2883 | int max_height = 4096; | |
cc926387 DV |
2884 | int x = plane_state->base.src.x1 >> 17; |
2885 | int y = plane_state->base.src.y1 >> 17; | |
2886 | int w = drm_rect_width(&plane_state->base.src) >> 17; | |
2887 | int h = drm_rect_height(&plane_state->base.src) >> 17; | |
8d970654 VS |
2888 | u32 offset; |
2889 | ||
2890 | intel_add_fb_offsets(&x, &y, plane_state, 1); | |
2891 | offset = intel_compute_tile_offset(&x, &y, plane_state, 1); | |
2892 | ||
2893 | /* FIXME not quite sure how/if these apply to the chroma plane */ | |
2894 | if (w > max_width || h > max_height) { | |
2895 | DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n", | |
2896 | w, h, max_width, max_height); | |
2897 | return -EINVAL; | |
2898 | } | |
2899 | ||
2900 | plane_state->aux.offset = offset; | |
2901 | plane_state->aux.x = x; | |
2902 | plane_state->aux.y = y; | |
2903 | ||
2904 | return 0; | |
2905 | } | |
2906 | ||
b63a16f6 VS |
2907 | int skl_check_plane_surface(struct intel_plane_state *plane_state) |
2908 | { | |
2909 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2910 | unsigned int rotation = plane_state->base.rotation; | |
2911 | int ret; | |
2912 | ||
a5e4c7d0 VS |
2913 | if (!plane_state->base.visible) |
2914 | return 0; | |
2915 | ||
b63a16f6 | 2916 | /* Rotate src coordinates to match rotated GTT view */ |
bd2ef25d | 2917 | if (drm_rotation_90_or_270(rotation)) |
cc926387 | 2918 | drm_rect_rotate(&plane_state->base.src, |
da064b47 VS |
2919 | fb->width << 16, fb->height << 16, |
2920 | DRM_ROTATE_270); | |
b63a16f6 | 2921 | |
8d970654 VS |
2922 | /* |
2923 | * Handle the AUX surface first since | |
2924 | * the main surface setup depends on it. | |
2925 | */ | |
438b74a5 | 2926 | if (fb->format->format == DRM_FORMAT_NV12) { |
8d970654 VS |
2927 | ret = skl_check_nv12_aux_surface(plane_state); |
2928 | if (ret) | |
2929 | return ret; | |
2930 | } else { | |
2931 | plane_state->aux.offset = ~0xfff; | |
2932 | plane_state->aux.x = 0; | |
2933 | plane_state->aux.y = 0; | |
2934 | } | |
2935 | ||
b63a16f6 VS |
2936 | ret = skl_check_main_surface(plane_state); |
2937 | if (ret) | |
2938 | return ret; | |
2939 | ||
2940 | return 0; | |
2941 | } | |
2942 | ||
a8d201af ML |
2943 | static void i9xx_update_primary_plane(struct drm_plane *primary, |
2944 | const struct intel_crtc_state *crtc_state, | |
2945 | const struct intel_plane_state *plane_state) | |
81255565 | 2946 | { |
6315b5d3 | 2947 | struct drm_i915_private *dev_priv = to_i915(primary->dev); |
a8d201af ML |
2948 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2949 | struct drm_framebuffer *fb = plane_state->base.fb; | |
81255565 | 2950 | int plane = intel_crtc->plane; |
54ea9da8 | 2951 | u32 linear_offset; |
81255565 | 2952 | u32 dspcntr; |
f0f59a00 | 2953 | i915_reg_t reg = DSPCNTR(plane); |
8d0deca8 | 2954 | unsigned int rotation = plane_state->base.rotation; |
936e71e3 VS |
2955 | int x = plane_state->base.src.x1 >> 16; |
2956 | int y = plane_state->base.src.y1 >> 16; | |
c9ba6fad | 2957 | |
f45651ba VS |
2958 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2959 | ||
fdd508a6 | 2960 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba | 2961 | |
6315b5d3 | 2962 | if (INTEL_GEN(dev_priv) < 4) { |
f45651ba VS |
2963 | if (intel_crtc->pipe == PIPE_B) |
2964 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2965 | ||
2966 | /* pipesrc and dspsize control the size that is scaled from, | |
2967 | * which should always be the user's requested size. | |
2968 | */ | |
2969 | I915_WRITE(DSPSIZE(plane), | |
a8d201af ML |
2970 | ((crtc_state->pipe_src_h - 1) << 16) | |
2971 | (crtc_state->pipe_src_w - 1)); | |
f45651ba | 2972 | I915_WRITE(DSPPOS(plane), 0); |
920a14b2 | 2973 | } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) { |
c14b0485 | 2974 | I915_WRITE(PRIMSIZE(plane), |
a8d201af ML |
2975 | ((crtc_state->pipe_src_h - 1) << 16) | |
2976 | (crtc_state->pipe_src_w - 1)); | |
c14b0485 VS |
2977 | I915_WRITE(PRIMPOS(plane), 0); |
2978 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2979 | } |
81255565 | 2980 | |
438b74a5 | 2981 | switch (fb->format->format) { |
57779d06 | 2982 | case DRM_FORMAT_C8: |
81255565 JB |
2983 | dspcntr |= DISPPLANE_8BPP; |
2984 | break; | |
57779d06 | 2985 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2986 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2987 | break; |
57779d06 VS |
2988 | case DRM_FORMAT_RGB565: |
2989 | dspcntr |= DISPPLANE_BGRX565; | |
2990 | break; | |
2991 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2992 | dspcntr |= DISPPLANE_BGRX888; |
2993 | break; | |
2994 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2995 | dspcntr |= DISPPLANE_RGBX888; |
2996 | break; | |
2997 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2998 | dspcntr |= DISPPLANE_BGRX101010; |
2999 | break; | |
3000 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 3001 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
3002 | break; |
3003 | default: | |
baba133a | 3004 | BUG(); |
81255565 | 3005 | } |
57779d06 | 3006 | |
72618ebf | 3007 | if (INTEL_GEN(dev_priv) >= 4 && |
bae781b2 | 3008 | fb->modifier == I915_FORMAT_MOD_X_TILED) |
f45651ba | 3009 | dspcntr |= DISPPLANE_TILED; |
81255565 | 3010 | |
df0cd455 VS |
3011 | if (rotation & DRM_ROTATE_180) |
3012 | dspcntr |= DISPPLANE_ROTATE_180; | |
3013 | ||
4ea7be2b VS |
3014 | if (rotation & DRM_REFLECT_X) |
3015 | dspcntr |= DISPPLANE_MIRROR; | |
3016 | ||
9beb5fea | 3017 | if (IS_G4X(dev_priv)) |
de1aa629 VS |
3018 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
3019 | ||
2949056c | 3020 | intel_add_fb_offsets(&x, &y, plane_state, 0); |
81255565 | 3021 | |
6315b5d3 | 3022 | if (INTEL_GEN(dev_priv) >= 4) |
c2c75131 | 3023 | intel_crtc->dspaddr_offset = |
2949056c | 3024 | intel_compute_tile_offset(&x, &y, plane_state, 0); |
e506a0c6 | 3025 | |
f22aa143 | 3026 | if (rotation & DRM_ROTATE_180) { |
df0cd455 VS |
3027 | x += crtc_state->pipe_src_w - 1; |
3028 | y += crtc_state->pipe_src_h - 1; | |
4ea7be2b VS |
3029 | } else if (rotation & DRM_REFLECT_X) { |
3030 | x += crtc_state->pipe_src_w - 1; | |
48404c1e SJ |
3031 | } |
3032 | ||
2949056c | 3033 | linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); |
6687c906 | 3034 | |
6315b5d3 | 3035 | if (INTEL_GEN(dev_priv) < 4) |
6687c906 VS |
3036 | intel_crtc->dspaddr_offset = linear_offset; |
3037 | ||
2db3366b PZ |
3038 | intel_crtc->adjusted_x = x; |
3039 | intel_crtc->adjusted_y = y; | |
3040 | ||
48404c1e SJ |
3041 | I915_WRITE(reg, dspcntr); |
3042 | ||
01f2c773 | 3043 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
6315b5d3 | 3044 | if (INTEL_GEN(dev_priv) >= 4) { |
85ba7b7d | 3045 | I915_WRITE(DSPSURF(plane), |
be1e3415 | 3046 | intel_plane_ggtt_offset(plane_state) + |
6687c906 | 3047 | intel_crtc->dspaddr_offset); |
5eddb70b | 3048 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 3049 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
bfb81049 VS |
3050 | } else { |
3051 | I915_WRITE(DSPADDR(plane), | |
be1e3415 | 3052 | intel_plane_ggtt_offset(plane_state) + |
bfb81049 VS |
3053 | intel_crtc->dspaddr_offset); |
3054 | } | |
5eddb70b | 3055 | POSTING_READ(reg); |
17638cd6 JB |
3056 | } |
3057 | ||
a8d201af ML |
3058 | static void i9xx_disable_primary_plane(struct drm_plane *primary, |
3059 | struct drm_crtc *crtc) | |
17638cd6 JB |
3060 | { |
3061 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3062 | struct drm_i915_private *dev_priv = to_i915(dev); |
17638cd6 | 3063 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
17638cd6 | 3064 | int plane = intel_crtc->plane; |
f45651ba | 3065 | |
a8d201af ML |
3066 | I915_WRITE(DSPCNTR(plane), 0); |
3067 | if (INTEL_INFO(dev_priv)->gen >= 4) | |
fdd508a6 | 3068 | I915_WRITE(DSPSURF(plane), 0); |
a8d201af ML |
3069 | else |
3070 | I915_WRITE(DSPADDR(plane), 0); | |
3071 | POSTING_READ(DSPCNTR(plane)); | |
3072 | } | |
c9ba6fad | 3073 | |
a8d201af ML |
3074 | static void ironlake_update_primary_plane(struct drm_plane *primary, |
3075 | const struct intel_crtc_state *crtc_state, | |
3076 | const struct intel_plane_state *plane_state) | |
3077 | { | |
3078 | struct drm_device *dev = primary->dev; | |
fac5e23e | 3079 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
3080 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3081 | struct drm_framebuffer *fb = plane_state->base.fb; | |
a8d201af | 3082 | int plane = intel_crtc->plane; |
54ea9da8 | 3083 | u32 linear_offset; |
a8d201af ML |
3084 | u32 dspcntr; |
3085 | i915_reg_t reg = DSPCNTR(plane); | |
8d0deca8 | 3086 | unsigned int rotation = plane_state->base.rotation; |
936e71e3 VS |
3087 | int x = plane_state->base.src.x1 >> 16; |
3088 | int y = plane_state->base.src.y1 >> 16; | |
c9ba6fad | 3089 | |
f45651ba | 3090 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
fdd508a6 | 3091 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba | 3092 | |
8652744b | 3093 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
f45651ba | 3094 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; |
17638cd6 | 3095 | |
438b74a5 | 3096 | switch (fb->format->format) { |
57779d06 | 3097 | case DRM_FORMAT_C8: |
17638cd6 JB |
3098 | dspcntr |= DISPPLANE_8BPP; |
3099 | break; | |
57779d06 VS |
3100 | case DRM_FORMAT_RGB565: |
3101 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 3102 | break; |
57779d06 | 3103 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
3104 | dspcntr |= DISPPLANE_BGRX888; |
3105 | break; | |
3106 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
3107 | dspcntr |= DISPPLANE_RGBX888; |
3108 | break; | |
3109 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
3110 | dspcntr |= DISPPLANE_BGRX101010; |
3111 | break; | |
3112 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 3113 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
3114 | break; |
3115 | default: | |
baba133a | 3116 | BUG(); |
17638cd6 JB |
3117 | } |
3118 | ||
bae781b2 | 3119 | if (fb->modifier == I915_FORMAT_MOD_X_TILED) |
17638cd6 | 3120 | dspcntr |= DISPPLANE_TILED; |
17638cd6 | 3121 | |
df0cd455 VS |
3122 | if (rotation & DRM_ROTATE_180) |
3123 | dspcntr |= DISPPLANE_ROTATE_180; | |
3124 | ||
8652744b | 3125 | if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) |
1f5d76db | 3126 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 3127 | |
2949056c | 3128 | intel_add_fb_offsets(&x, &y, plane_state, 0); |
6687c906 | 3129 | |
c2c75131 | 3130 | intel_crtc->dspaddr_offset = |
2949056c | 3131 | intel_compute_tile_offset(&x, &y, plane_state, 0); |
6687c906 | 3132 | |
df0cd455 VS |
3133 | /* HSW+ does this automagically in hardware */ |
3134 | if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv) && | |
3135 | rotation & DRM_ROTATE_180) { | |
3136 | x += crtc_state->pipe_src_w - 1; | |
3137 | y += crtc_state->pipe_src_h - 1; | |
48404c1e SJ |
3138 | } |
3139 | ||
2949056c | 3140 | linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); |
6687c906 | 3141 | |
2db3366b PZ |
3142 | intel_crtc->adjusted_x = x; |
3143 | intel_crtc->adjusted_y = y; | |
3144 | ||
48404c1e | 3145 | I915_WRITE(reg, dspcntr); |
17638cd6 | 3146 | |
01f2c773 | 3147 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d | 3148 | I915_WRITE(DSPSURF(plane), |
be1e3415 | 3149 | intel_plane_ggtt_offset(plane_state) + |
6687c906 | 3150 | intel_crtc->dspaddr_offset); |
8652744b | 3151 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
bc1c91eb DL |
3152 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
3153 | } else { | |
3154 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
3155 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
3156 | } | |
17638cd6 | 3157 | POSTING_READ(reg); |
17638cd6 JB |
3158 | } |
3159 | ||
7b49f948 VS |
3160 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
3161 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 3162 | { |
7b49f948 | 3163 | if (fb_modifier == DRM_FORMAT_MOD_NONE) { |
b321803d | 3164 | return 64; |
7b49f948 VS |
3165 | } else { |
3166 | int cpp = drm_format_plane_cpp(pixel_format, 0); | |
3167 | ||
27ba3910 | 3168 | return intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
b321803d DL |
3169 | } |
3170 | } | |
3171 | ||
e435d6e5 ML |
3172 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
3173 | { | |
3174 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 3175 | struct drm_i915_private *dev_priv = to_i915(dev); |
e435d6e5 ML |
3176 | |
3177 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
3178 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
3179 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
3180 | } |
3181 | ||
a1b2278e CK |
3182 | /* |
3183 | * This function detaches (aka. unbinds) unused scalers in hardware | |
3184 | */ | |
0583236e | 3185 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 3186 | { |
a1b2278e CK |
3187 | struct intel_crtc_scaler_state *scaler_state; |
3188 | int i; | |
3189 | ||
a1b2278e CK |
3190 | scaler_state = &intel_crtc->config->scaler_state; |
3191 | ||
3192 | /* loop through and disable scalers that aren't in use */ | |
3193 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
3194 | if (!scaler_state->scalers[i].in_use) |
3195 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
3196 | } |
3197 | } | |
3198 | ||
d2196774 VS |
3199 | u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane, |
3200 | unsigned int rotation) | |
3201 | { | |
3202 | const struct drm_i915_private *dev_priv = to_i915(fb->dev); | |
3203 | u32 stride = intel_fb_pitch(fb, plane, rotation); | |
3204 | ||
3205 | /* | |
3206 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
3207 | * linear buffers or in number of tiles for tiled buffers. | |
3208 | */ | |
bd2ef25d | 3209 | if (drm_rotation_90_or_270(rotation)) { |
353c8598 | 3210 | int cpp = fb->format->cpp[plane]; |
d2196774 | 3211 | |
bae781b2 | 3212 | stride /= intel_tile_height(dev_priv, fb->modifier, cpp); |
d2196774 | 3213 | } else { |
bae781b2 | 3214 | stride /= intel_fb_stride_alignment(dev_priv, fb->modifier, |
438b74a5 | 3215 | fb->format->format); |
d2196774 VS |
3216 | } |
3217 | ||
3218 | return stride; | |
3219 | } | |
3220 | ||
6156a456 | 3221 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 3222 | { |
6156a456 | 3223 | switch (pixel_format) { |
d161cf7a | 3224 | case DRM_FORMAT_C8: |
c34ce3d1 | 3225 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 3226 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 3227 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 3228 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 3229 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 3230 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 3231 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
3232 | /* |
3233 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
3234 | * to be already pre-multiplied. We need to add a knob (or a different | |
3235 | * DRM_FORMAT) for user-space to configure that. | |
3236 | */ | |
f75fb42a | 3237 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 3238 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 3239 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 3240 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 3241 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 3242 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 3243 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 3244 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 3245 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 3246 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 3247 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 3248 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 3249 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 3250 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 3251 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 3252 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 3253 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 3254 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 3255 | default: |
4249eeef | 3256 | MISSING_CASE(pixel_format); |
70d21f0e | 3257 | } |
8cfcba41 | 3258 | |
c34ce3d1 | 3259 | return 0; |
6156a456 | 3260 | } |
70d21f0e | 3261 | |
6156a456 CK |
3262 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
3263 | { | |
6156a456 | 3264 | switch (fb_modifier) { |
30af77c4 | 3265 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 3266 | break; |
30af77c4 | 3267 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 3268 | return PLANE_CTL_TILED_X; |
b321803d | 3269 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3270 | return PLANE_CTL_TILED_Y; |
b321803d | 3271 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3272 | return PLANE_CTL_TILED_YF; |
70d21f0e | 3273 | default: |
6156a456 | 3274 | MISSING_CASE(fb_modifier); |
70d21f0e | 3275 | } |
8cfcba41 | 3276 | |
c34ce3d1 | 3277 | return 0; |
6156a456 | 3278 | } |
70d21f0e | 3279 | |
6156a456 CK |
3280 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
3281 | { | |
3b7a5119 | 3282 | switch (rotation) { |
31ad61e4 | 3283 | case DRM_ROTATE_0: |
6156a456 | 3284 | break; |
1e8df167 SJ |
3285 | /* |
3286 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
3287 | * while i915 HW rotation is clockwise, thats why this swapping. | |
3288 | */ | |
31ad61e4 | 3289 | case DRM_ROTATE_90: |
1e8df167 | 3290 | return PLANE_CTL_ROTATE_270; |
31ad61e4 | 3291 | case DRM_ROTATE_180: |
c34ce3d1 | 3292 | return PLANE_CTL_ROTATE_180; |
31ad61e4 | 3293 | case DRM_ROTATE_270: |
1e8df167 | 3294 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3295 | default: |
3296 | MISSING_CASE(rotation); | |
3297 | } | |
3298 | ||
c34ce3d1 | 3299 | return 0; |
6156a456 CK |
3300 | } |
3301 | ||
a8d201af ML |
3302 | static void skylake_update_primary_plane(struct drm_plane *plane, |
3303 | const struct intel_crtc_state *crtc_state, | |
3304 | const struct intel_plane_state *plane_state) | |
6156a456 | 3305 | { |
a8d201af | 3306 | struct drm_device *dev = plane->dev; |
fac5e23e | 3307 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
3308 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3309 | struct drm_framebuffer *fb = plane_state->base.fb; | |
8e816bb4 VS |
3310 | enum plane_id plane_id = to_intel_plane(plane)->id; |
3311 | enum pipe pipe = to_intel_plane(plane)->pipe; | |
d2196774 | 3312 | u32 plane_ctl; |
a8d201af | 3313 | unsigned int rotation = plane_state->base.rotation; |
d2196774 | 3314 | u32 stride = skl_plane_stride(fb, 0, rotation); |
b63a16f6 | 3315 | u32 surf_addr = plane_state->main.offset; |
a8d201af | 3316 | int scaler_id = plane_state->scaler_id; |
b63a16f6 VS |
3317 | int src_x = plane_state->main.x; |
3318 | int src_y = plane_state->main.y; | |
936e71e3 VS |
3319 | int src_w = drm_rect_width(&plane_state->base.src) >> 16; |
3320 | int src_h = drm_rect_height(&plane_state->base.src) >> 16; | |
3321 | int dst_x = plane_state->base.dst.x1; | |
3322 | int dst_y = plane_state->base.dst.y1; | |
3323 | int dst_w = drm_rect_width(&plane_state->base.dst); | |
3324 | int dst_h = drm_rect_height(&plane_state->base.dst); | |
70d21f0e | 3325 | |
47f9ea8b ACO |
3326 | plane_ctl = PLANE_CTL_ENABLE; |
3327 | ||
3328 | if (IS_GEMINILAKE(dev_priv)) { | |
3329 | I915_WRITE(PLANE_COLOR_CTL(pipe, plane_id), | |
3330 | PLANE_COLOR_PIPE_GAMMA_ENABLE | | |
3bb56da7 | 3331 | PLANE_COLOR_PIPE_CSC_ENABLE | |
47f9ea8b ACO |
3332 | PLANE_COLOR_PLANE_GAMMA_DISABLE); |
3333 | } else { | |
3334 | plane_ctl |= | |
3335 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3336 | PLANE_CTL_PIPE_CSC_ENABLE | | |
3337 | PLANE_CTL_PLANE_GAMMA_DISABLE; | |
3338 | } | |
6156a456 | 3339 | |
438b74a5 | 3340 | plane_ctl |= skl_plane_ctl_format(fb->format->format); |
bae781b2 | 3341 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier); |
6156a456 CK |
3342 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
3343 | ||
6687c906 VS |
3344 | /* Sizes are 0 based */ |
3345 | src_w--; | |
3346 | src_h--; | |
3347 | dst_w--; | |
3348 | dst_h--; | |
3349 | ||
4c0b8a8b PZ |
3350 | intel_crtc->dspaddr_offset = surf_addr; |
3351 | ||
6687c906 VS |
3352 | intel_crtc->adjusted_x = src_x; |
3353 | intel_crtc->adjusted_y = src_y; | |
2db3366b | 3354 | |
8e816bb4 VS |
3355 | I915_WRITE(PLANE_CTL(pipe, plane_id), plane_ctl); |
3356 | I915_WRITE(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x); | |
3357 | I915_WRITE(PLANE_STRIDE(pipe, plane_id), stride); | |
3358 | I915_WRITE(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); | |
6156a456 CK |
3359 | |
3360 | if (scaler_id >= 0) { | |
3361 | uint32_t ps_ctrl = 0; | |
3362 | ||
3363 | WARN_ON(!dst_w || !dst_h); | |
8e816bb4 | 3364 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) | |
6156a456 CK |
3365 | crtc_state->scaler_state.scalers[scaler_id].mode; |
3366 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3367 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3368 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3369 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
8e816bb4 | 3370 | I915_WRITE(PLANE_POS(pipe, plane_id), 0); |
6156a456 | 3371 | } else { |
8e816bb4 | 3372 | I915_WRITE(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x); |
6156a456 CK |
3373 | } |
3374 | ||
8e816bb4 | 3375 | I915_WRITE(PLANE_SURF(pipe, plane_id), |
be1e3415 | 3376 | intel_plane_ggtt_offset(plane_state) + surf_addr); |
70d21f0e | 3377 | |
8e816bb4 | 3378 | POSTING_READ(PLANE_SURF(pipe, plane_id)); |
70d21f0e DL |
3379 | } |
3380 | ||
a8d201af ML |
3381 | static void skylake_disable_primary_plane(struct drm_plane *primary, |
3382 | struct drm_crtc *crtc) | |
17638cd6 JB |
3383 | { |
3384 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3385 | struct drm_i915_private *dev_priv = to_i915(dev); |
8e816bb4 VS |
3386 | enum plane_id plane_id = to_intel_plane(primary)->id; |
3387 | enum pipe pipe = to_intel_plane(primary)->pipe; | |
62e0fb88 | 3388 | |
8e816bb4 VS |
3389 | I915_WRITE(PLANE_CTL(pipe, plane_id), 0); |
3390 | I915_WRITE(PLANE_SURF(pipe, plane_id), 0); | |
3391 | POSTING_READ(PLANE_SURF(pipe, plane_id)); | |
a8d201af | 3392 | } |
29b9bde6 | 3393 | |
a8d201af ML |
3394 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3395 | static int | |
3396 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3397 | int x, int y, enum mode_set_atomic state) | |
3398 | { | |
3399 | /* Support for kgdboc is disabled, this needs a major rework. */ | |
3400 | DRM_ERROR("legacy panic handler not supported any more.\n"); | |
3401 | ||
3402 | return -ENODEV; | |
81255565 JB |
3403 | } |
3404 | ||
5a21b665 DV |
3405 | static void intel_complete_page_flips(struct drm_i915_private *dev_priv) |
3406 | { | |
3407 | struct intel_crtc *crtc; | |
3408 | ||
91c8a326 | 3409 | for_each_intel_crtc(&dev_priv->drm, crtc) |
5a21b665 DV |
3410 | intel_finish_page_flip_cs(dev_priv, crtc->pipe); |
3411 | } | |
3412 | ||
7514747d VS |
3413 | static void intel_update_primary_planes(struct drm_device *dev) |
3414 | { | |
7514747d | 3415 | struct drm_crtc *crtc; |
96a02917 | 3416 | |
70e1e0ec | 3417 | for_each_crtc(dev, crtc) { |
11c22da6 | 3418 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
73974893 ML |
3419 | struct intel_plane_state *plane_state = |
3420 | to_intel_plane_state(plane->base.state); | |
11c22da6 | 3421 | |
936e71e3 | 3422 | if (plane_state->base.visible) |
a8d201af ML |
3423 | plane->update_plane(&plane->base, |
3424 | to_intel_crtc_state(crtc->state), | |
3425 | plane_state); | |
73974893 ML |
3426 | } |
3427 | } | |
3428 | ||
3429 | static int | |
3430 | __intel_display_resume(struct drm_device *dev, | |
3431 | struct drm_atomic_state *state) | |
3432 | { | |
3433 | struct drm_crtc_state *crtc_state; | |
3434 | struct drm_crtc *crtc; | |
3435 | int i, ret; | |
11c22da6 | 3436 | |
73974893 | 3437 | intel_modeset_setup_hw_state(dev); |
29b74b7f | 3438 | i915_redisable_vga(to_i915(dev)); |
73974893 ML |
3439 | |
3440 | if (!state) | |
3441 | return 0; | |
3442 | ||
3443 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
3444 | /* | |
3445 | * Force recalculation even if we restore | |
3446 | * current state. With fast modeset this may not result | |
3447 | * in a modeset when the state is compatible. | |
3448 | */ | |
3449 | crtc_state->mode_changed = true; | |
96a02917 | 3450 | } |
73974893 ML |
3451 | |
3452 | /* ignore any reset values/BIOS leftovers in the WM registers */ | |
3453 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
3454 | ||
3455 | ret = drm_atomic_commit(state); | |
3456 | ||
3457 | WARN_ON(ret == -EDEADLK); | |
3458 | return ret; | |
96a02917 VS |
3459 | } |
3460 | ||
4ac2ba2f VS |
3461 | static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) |
3462 | { | |
ae98104b VS |
3463 | return intel_has_gpu_reset(dev_priv) && |
3464 | INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv); | |
4ac2ba2f VS |
3465 | } |
3466 | ||
c033666a | 3467 | void intel_prepare_reset(struct drm_i915_private *dev_priv) |
7514747d | 3468 | { |
73974893 ML |
3469 | struct drm_device *dev = &dev_priv->drm; |
3470 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3471 | struct drm_atomic_state *state; | |
3472 | int ret; | |
3473 | ||
73974893 ML |
3474 | /* |
3475 | * Need mode_config.mutex so that we don't | |
3476 | * trample ongoing ->detect() and whatnot. | |
3477 | */ | |
3478 | mutex_lock(&dev->mode_config.mutex); | |
3479 | drm_modeset_acquire_init(ctx, 0); | |
3480 | while (1) { | |
3481 | ret = drm_modeset_lock_all_ctx(dev, ctx); | |
3482 | if (ret != -EDEADLK) | |
3483 | break; | |
3484 | ||
3485 | drm_modeset_backoff(ctx); | |
3486 | } | |
3487 | ||
3488 | /* reset doesn't touch the display, but flips might get nuked anyway, */ | |
522a63de | 3489 | if (!i915.force_reset_modeset_test && |
4ac2ba2f | 3490 | !gpu_reset_clobbers_display(dev_priv)) |
7514747d VS |
3491 | return; |
3492 | ||
f98ce92f VS |
3493 | /* |
3494 | * Disabling the crtcs gracefully seems nicer. Also the | |
3495 | * g33 docs say we should at least disable all the planes. | |
3496 | */ | |
73974893 ML |
3497 | state = drm_atomic_helper_duplicate_state(dev, ctx); |
3498 | if (IS_ERR(state)) { | |
3499 | ret = PTR_ERR(state); | |
73974893 | 3500 | DRM_ERROR("Duplicating state failed with %i\n", ret); |
1e5a15d6 | 3501 | return; |
73974893 ML |
3502 | } |
3503 | ||
3504 | ret = drm_atomic_helper_disable_all(dev, ctx); | |
3505 | if (ret) { | |
3506 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
1e5a15d6 ACO |
3507 | drm_atomic_state_put(state); |
3508 | return; | |
73974893 ML |
3509 | } |
3510 | ||
3511 | dev_priv->modeset_restore_state = state; | |
3512 | state->acquire_ctx = ctx; | |
7514747d VS |
3513 | } |
3514 | ||
c033666a | 3515 | void intel_finish_reset(struct drm_i915_private *dev_priv) |
7514747d | 3516 | { |
73974893 ML |
3517 | struct drm_device *dev = &dev_priv->drm; |
3518 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3519 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
3520 | int ret; | |
3521 | ||
5a21b665 DV |
3522 | /* |
3523 | * Flips in the rings will be nuked by the reset, | |
3524 | * so complete all pending flips so that user space | |
3525 | * will get its events and not get stuck. | |
3526 | */ | |
3527 | intel_complete_page_flips(dev_priv); | |
3528 | ||
73974893 ML |
3529 | dev_priv->modeset_restore_state = NULL; |
3530 | ||
7514747d | 3531 | /* reset doesn't touch the display */ |
4ac2ba2f | 3532 | if (!gpu_reset_clobbers_display(dev_priv)) { |
522a63de ML |
3533 | if (!state) { |
3534 | /* | |
3535 | * Flips in the rings have been nuked by the reset, | |
3536 | * so update the base address of all primary | |
3537 | * planes to the the last fb to make sure we're | |
3538 | * showing the correct fb after a reset. | |
3539 | * | |
3540 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3541 | * CS-based flips (which might get lost in gpu resets) any more. | |
3542 | */ | |
3543 | intel_update_primary_planes(dev); | |
3544 | } else { | |
3545 | ret = __intel_display_resume(dev, state); | |
3546 | if (ret) | |
3547 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
3548 | } | |
73974893 ML |
3549 | } else { |
3550 | /* | |
3551 | * The display has been reset as well, | |
3552 | * so need a full re-initialization. | |
3553 | */ | |
3554 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3555 | intel_runtime_pm_enable_interrupts(dev_priv); | |
7514747d | 3556 | |
51f59205 | 3557 | intel_pps_unlock_regs_wa(dev_priv); |
73974893 | 3558 | intel_modeset_init_hw(dev); |
7514747d | 3559 | |
73974893 ML |
3560 | spin_lock_irq(&dev_priv->irq_lock); |
3561 | if (dev_priv->display.hpd_irq_setup) | |
3562 | dev_priv->display.hpd_irq_setup(dev_priv); | |
3563 | spin_unlock_irq(&dev_priv->irq_lock); | |
7514747d | 3564 | |
73974893 ML |
3565 | ret = __intel_display_resume(dev, state); |
3566 | if (ret) | |
3567 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
7514747d | 3568 | |
73974893 ML |
3569 | intel_hpd_init(dev_priv); |
3570 | } | |
7514747d | 3571 | |
0853695c CW |
3572 | if (state) |
3573 | drm_atomic_state_put(state); | |
73974893 ML |
3574 | drm_modeset_drop_locks(ctx); |
3575 | drm_modeset_acquire_fini(ctx); | |
3576 | mutex_unlock(&dev->mode_config.mutex); | |
7514747d VS |
3577 | } |
3578 | ||
8af29b0c CW |
3579 | static bool abort_flip_on_reset(struct intel_crtc *crtc) |
3580 | { | |
3581 | struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error; | |
3582 | ||
3583 | if (i915_reset_in_progress(error)) | |
3584 | return true; | |
3585 | ||
3586 | if (crtc->reset_count != i915_reset_count(error)) | |
3587 | return true; | |
3588 | ||
3589 | return false; | |
3590 | } | |
3591 | ||
7d5e3799 CW |
3592 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3593 | { | |
5a21b665 DV |
3594 | struct drm_device *dev = crtc->dev; |
3595 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5a21b665 DV |
3596 | bool pending; |
3597 | ||
8af29b0c | 3598 | if (abort_flip_on_reset(intel_crtc)) |
5a21b665 DV |
3599 | return false; |
3600 | ||
3601 | spin_lock_irq(&dev->event_lock); | |
3602 | pending = to_intel_crtc(crtc)->flip_work != NULL; | |
3603 | spin_unlock_irq(&dev->event_lock); | |
3604 | ||
3605 | return pending; | |
7d5e3799 CW |
3606 | } |
3607 | ||
bfd16b2a ML |
3608 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3609 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 | 3610 | { |
6315b5d3 | 3611 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
bfd16b2a ML |
3612 | struct intel_crtc_state *pipe_config = |
3613 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3614 | |
bfd16b2a ML |
3615 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3616 | crtc->base.mode = crtc->base.state->mode; | |
3617 | ||
3618 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3619 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3620 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 GP |
3621 | |
3622 | /* | |
3623 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3624 | * that in compute_mode_changes we check the native mode (not the pfit | |
3625 | * mode) to see if we can flip rather than do a full mode set. In the | |
3626 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3627 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3628 | * sized surface. | |
e30e8f75 GP |
3629 | */ |
3630 | ||
e30e8f75 | 3631 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3632 | ((pipe_config->pipe_src_w - 1) << 16) | |
3633 | (pipe_config->pipe_src_h - 1)); | |
3634 | ||
3635 | /* on skylake this is done by detaching scalers */ | |
6315b5d3 | 3636 | if (INTEL_GEN(dev_priv) >= 9) { |
bfd16b2a ML |
3637 | skl_detach_scalers(crtc); |
3638 | ||
3639 | if (pipe_config->pch_pfit.enabled) | |
3640 | skylake_pfit_enable(crtc); | |
6e266956 | 3641 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
bfd16b2a ML |
3642 | if (pipe_config->pch_pfit.enabled) |
3643 | ironlake_pfit_enable(crtc); | |
3644 | else if (old_crtc_state->pch_pfit.enabled) | |
3645 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3646 | } |
e30e8f75 GP |
3647 | } |
3648 | ||
4cbe4b2b | 3649 | static void intel_fdi_normal_train(struct intel_crtc *crtc) |
5e84e1a4 | 3650 | { |
4cbe4b2b | 3651 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3652 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3653 | int pipe = crtc->pipe; |
f0f59a00 VS |
3654 | i915_reg_t reg; |
3655 | u32 temp; | |
5e84e1a4 ZW |
3656 | |
3657 | /* enable normal train */ | |
3658 | reg = FDI_TX_CTL(pipe); | |
3659 | temp = I915_READ(reg); | |
fd6b8f43 | 3660 | if (IS_IVYBRIDGE(dev_priv)) { |
357555c0 JB |
3661 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3662 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3663 | } else { |
3664 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3665 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3666 | } |
5e84e1a4 ZW |
3667 | I915_WRITE(reg, temp); |
3668 | ||
3669 | reg = FDI_RX_CTL(pipe); | |
3670 | temp = I915_READ(reg); | |
6e266956 | 3671 | if (HAS_PCH_CPT(dev_priv)) { |
5e84e1a4 ZW |
3672 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3673 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3674 | } else { | |
3675 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3676 | temp |= FDI_LINK_TRAIN_NONE; | |
3677 | } | |
3678 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3679 | ||
3680 | /* wait one idle pattern time */ | |
3681 | POSTING_READ(reg); | |
3682 | udelay(1000); | |
357555c0 JB |
3683 | |
3684 | /* IVB wants error correction enabled */ | |
fd6b8f43 | 3685 | if (IS_IVYBRIDGE(dev_priv)) |
357555c0 JB |
3686 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
3687 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3688 | } |
3689 | ||
8db9d77b | 3690 | /* The FDI link training functions for ILK/Ibexpeak. */ |
4cbe4b2b | 3691 | static void ironlake_fdi_link_train(struct intel_crtc *crtc) |
8db9d77b | 3692 | { |
4cbe4b2b | 3693 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3694 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3695 | int pipe = crtc->pipe; |
f0f59a00 VS |
3696 | i915_reg_t reg; |
3697 | u32 temp, tries; | |
8db9d77b | 3698 | |
1c8562f6 | 3699 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3700 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3701 | |
e1a44743 AJ |
3702 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3703 | for train result */ | |
5eddb70b CW |
3704 | reg = FDI_RX_IMR(pipe); |
3705 | temp = I915_READ(reg); | |
e1a44743 AJ |
3706 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3707 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3708 | I915_WRITE(reg, temp); |
3709 | I915_READ(reg); | |
e1a44743 AJ |
3710 | udelay(150); |
3711 | ||
8db9d77b | 3712 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3713 | reg = FDI_TX_CTL(pipe); |
3714 | temp = I915_READ(reg); | |
627eb5a3 | 3715 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
4cbe4b2b | 3716 | temp |= FDI_DP_PORT_WIDTH(crtc->config->fdi_lanes); |
8db9d77b ZW |
3717 | temp &= ~FDI_LINK_TRAIN_NONE; |
3718 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3719 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3720 | |
5eddb70b CW |
3721 | reg = FDI_RX_CTL(pipe); |
3722 | temp = I915_READ(reg); | |
8db9d77b ZW |
3723 | temp &= ~FDI_LINK_TRAIN_NONE; |
3724 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3725 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3726 | ||
3727 | POSTING_READ(reg); | |
8db9d77b ZW |
3728 | udelay(150); |
3729 | ||
5b2adf89 | 3730 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3731 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3732 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3733 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3734 | |
5eddb70b | 3735 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3736 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3737 | temp = I915_READ(reg); |
8db9d77b ZW |
3738 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3739 | ||
3740 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3741 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3742 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3743 | break; |
3744 | } | |
8db9d77b | 3745 | } |
e1a44743 | 3746 | if (tries == 5) |
5eddb70b | 3747 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3748 | |
3749 | /* Train 2 */ | |
5eddb70b CW |
3750 | reg = FDI_TX_CTL(pipe); |
3751 | temp = I915_READ(reg); | |
8db9d77b ZW |
3752 | temp &= ~FDI_LINK_TRAIN_NONE; |
3753 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3754 | I915_WRITE(reg, temp); |
8db9d77b | 3755 | |
5eddb70b CW |
3756 | reg = FDI_RX_CTL(pipe); |
3757 | temp = I915_READ(reg); | |
8db9d77b ZW |
3758 | temp &= ~FDI_LINK_TRAIN_NONE; |
3759 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3760 | I915_WRITE(reg, temp); |
8db9d77b | 3761 | |
5eddb70b CW |
3762 | POSTING_READ(reg); |
3763 | udelay(150); | |
8db9d77b | 3764 | |
5eddb70b | 3765 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3766 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3767 | temp = I915_READ(reg); |
8db9d77b ZW |
3768 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3769 | ||
3770 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3771 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3772 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3773 | break; | |
3774 | } | |
8db9d77b | 3775 | } |
e1a44743 | 3776 | if (tries == 5) |
5eddb70b | 3777 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3778 | |
3779 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3780 | |
8db9d77b ZW |
3781 | } |
3782 | ||
0206e353 | 3783 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3784 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3785 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3786 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3787 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3788 | }; | |
3789 | ||
3790 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
4cbe4b2b | 3791 | static void gen6_fdi_link_train(struct intel_crtc *crtc) |
8db9d77b | 3792 | { |
4cbe4b2b | 3793 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3794 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3795 | int pipe = crtc->pipe; |
f0f59a00 VS |
3796 | i915_reg_t reg; |
3797 | u32 temp, i, retry; | |
8db9d77b | 3798 | |
e1a44743 AJ |
3799 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3800 | for train result */ | |
5eddb70b CW |
3801 | reg = FDI_RX_IMR(pipe); |
3802 | temp = I915_READ(reg); | |
e1a44743 AJ |
3803 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3804 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3805 | I915_WRITE(reg, temp); |
3806 | ||
3807 | POSTING_READ(reg); | |
e1a44743 AJ |
3808 | udelay(150); |
3809 | ||
8db9d77b | 3810 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3811 | reg = FDI_TX_CTL(pipe); |
3812 | temp = I915_READ(reg); | |
627eb5a3 | 3813 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
4cbe4b2b | 3814 | temp |= FDI_DP_PORT_WIDTH(crtc->config->fdi_lanes); |
8db9d77b ZW |
3815 | temp &= ~FDI_LINK_TRAIN_NONE; |
3816 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3817 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3818 | /* SNB-B */ | |
3819 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3820 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3821 | |
d74cf324 DV |
3822 | I915_WRITE(FDI_RX_MISC(pipe), |
3823 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3824 | ||
5eddb70b CW |
3825 | reg = FDI_RX_CTL(pipe); |
3826 | temp = I915_READ(reg); | |
6e266956 | 3827 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
3828 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3829 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3830 | } else { | |
3831 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3832 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3833 | } | |
5eddb70b CW |
3834 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3835 | ||
3836 | POSTING_READ(reg); | |
8db9d77b ZW |
3837 | udelay(150); |
3838 | ||
0206e353 | 3839 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3840 | reg = FDI_TX_CTL(pipe); |
3841 | temp = I915_READ(reg); | |
8db9d77b ZW |
3842 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3843 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3844 | I915_WRITE(reg, temp); |
3845 | ||
3846 | POSTING_READ(reg); | |
8db9d77b ZW |
3847 | udelay(500); |
3848 | ||
fa37d39e SP |
3849 | for (retry = 0; retry < 5; retry++) { |
3850 | reg = FDI_RX_IIR(pipe); | |
3851 | temp = I915_READ(reg); | |
3852 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3853 | if (temp & FDI_RX_BIT_LOCK) { | |
3854 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3855 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3856 | break; | |
3857 | } | |
3858 | udelay(50); | |
8db9d77b | 3859 | } |
fa37d39e SP |
3860 | if (retry < 5) |
3861 | break; | |
8db9d77b ZW |
3862 | } |
3863 | if (i == 4) | |
5eddb70b | 3864 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3865 | |
3866 | /* Train 2 */ | |
5eddb70b CW |
3867 | reg = FDI_TX_CTL(pipe); |
3868 | temp = I915_READ(reg); | |
8db9d77b ZW |
3869 | temp &= ~FDI_LINK_TRAIN_NONE; |
3870 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5db94019 | 3871 | if (IS_GEN6(dev_priv)) { |
8db9d77b ZW |
3872 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3873 | /* SNB-B */ | |
3874 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3875 | } | |
5eddb70b | 3876 | I915_WRITE(reg, temp); |
8db9d77b | 3877 | |
5eddb70b CW |
3878 | reg = FDI_RX_CTL(pipe); |
3879 | temp = I915_READ(reg); | |
6e266956 | 3880 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
3881 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3882 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3883 | } else { | |
3884 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3885 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3886 | } | |
5eddb70b CW |
3887 | I915_WRITE(reg, temp); |
3888 | ||
3889 | POSTING_READ(reg); | |
8db9d77b ZW |
3890 | udelay(150); |
3891 | ||
0206e353 | 3892 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3893 | reg = FDI_TX_CTL(pipe); |
3894 | temp = I915_READ(reg); | |
8db9d77b ZW |
3895 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3896 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3897 | I915_WRITE(reg, temp); |
3898 | ||
3899 | POSTING_READ(reg); | |
8db9d77b ZW |
3900 | udelay(500); |
3901 | ||
fa37d39e SP |
3902 | for (retry = 0; retry < 5; retry++) { |
3903 | reg = FDI_RX_IIR(pipe); | |
3904 | temp = I915_READ(reg); | |
3905 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3906 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3907 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3908 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3909 | break; | |
3910 | } | |
3911 | udelay(50); | |
8db9d77b | 3912 | } |
fa37d39e SP |
3913 | if (retry < 5) |
3914 | break; | |
8db9d77b ZW |
3915 | } |
3916 | if (i == 4) | |
5eddb70b | 3917 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3918 | |
3919 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3920 | } | |
3921 | ||
357555c0 | 3922 | /* Manual link training for Ivy Bridge A0 parts */ |
4cbe4b2b | 3923 | static void ivb_manual_fdi_link_train(struct intel_crtc *crtc) |
357555c0 | 3924 | { |
4cbe4b2b | 3925 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3926 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3927 | int pipe = crtc->pipe; |
f0f59a00 VS |
3928 | i915_reg_t reg; |
3929 | u32 temp, i, j; | |
357555c0 JB |
3930 | |
3931 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3932 | for train result */ | |
3933 | reg = FDI_RX_IMR(pipe); | |
3934 | temp = I915_READ(reg); | |
3935 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3936 | temp &= ~FDI_RX_BIT_LOCK; | |
3937 | I915_WRITE(reg, temp); | |
3938 | ||
3939 | POSTING_READ(reg); | |
3940 | udelay(150); | |
3941 | ||
01a415fd DV |
3942 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3943 | I915_READ(FDI_RX_IIR(pipe))); | |
3944 | ||
139ccd3f JB |
3945 | /* Try each vswing and preemphasis setting twice before moving on */ |
3946 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3947 | /* disable first in case we need to retry */ | |
3948 | reg = FDI_TX_CTL(pipe); | |
3949 | temp = I915_READ(reg); | |
3950 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3951 | temp &= ~FDI_TX_ENABLE; | |
3952 | I915_WRITE(reg, temp); | |
357555c0 | 3953 | |
139ccd3f JB |
3954 | reg = FDI_RX_CTL(pipe); |
3955 | temp = I915_READ(reg); | |
3956 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3957 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3958 | temp &= ~FDI_RX_ENABLE; | |
3959 | I915_WRITE(reg, temp); | |
357555c0 | 3960 | |
139ccd3f | 3961 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3962 | reg = FDI_TX_CTL(pipe); |
3963 | temp = I915_READ(reg); | |
139ccd3f | 3964 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
4cbe4b2b | 3965 | temp |= FDI_DP_PORT_WIDTH(crtc->config->fdi_lanes); |
139ccd3f | 3966 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3967 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3968 | temp |= snb_b_fdi_train_param[j/2]; |
3969 | temp |= FDI_COMPOSITE_SYNC; | |
3970 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3971 | |
139ccd3f JB |
3972 | I915_WRITE(FDI_RX_MISC(pipe), |
3973 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3974 | |
139ccd3f | 3975 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3976 | temp = I915_READ(reg); |
139ccd3f JB |
3977 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3978 | temp |= FDI_COMPOSITE_SYNC; | |
3979 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3980 | |
139ccd3f JB |
3981 | POSTING_READ(reg); |
3982 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3983 | |
139ccd3f JB |
3984 | for (i = 0; i < 4; i++) { |
3985 | reg = FDI_RX_IIR(pipe); | |
3986 | temp = I915_READ(reg); | |
3987 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3988 | |
139ccd3f JB |
3989 | if (temp & FDI_RX_BIT_LOCK || |
3990 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3991 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3992 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3993 | i); | |
3994 | break; | |
3995 | } | |
3996 | udelay(1); /* should be 0.5us */ | |
3997 | } | |
3998 | if (i == 4) { | |
3999 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
4000 | continue; | |
4001 | } | |
357555c0 | 4002 | |
139ccd3f | 4003 | /* Train 2 */ |
357555c0 JB |
4004 | reg = FDI_TX_CTL(pipe); |
4005 | temp = I915_READ(reg); | |
139ccd3f JB |
4006 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
4007 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
4008 | I915_WRITE(reg, temp); | |
4009 | ||
4010 | reg = FDI_RX_CTL(pipe); | |
4011 | temp = I915_READ(reg); | |
4012 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
4013 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
4014 | I915_WRITE(reg, temp); |
4015 | ||
4016 | POSTING_READ(reg); | |
139ccd3f | 4017 | udelay(2); /* should be 1.5us */ |
357555c0 | 4018 | |
139ccd3f JB |
4019 | for (i = 0; i < 4; i++) { |
4020 | reg = FDI_RX_IIR(pipe); | |
4021 | temp = I915_READ(reg); | |
4022 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 4023 | |
139ccd3f JB |
4024 | if (temp & FDI_RX_SYMBOL_LOCK || |
4025 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
4026 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
4027 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
4028 | i); | |
4029 | goto train_done; | |
4030 | } | |
4031 | udelay(2); /* should be 1.5us */ | |
357555c0 | 4032 | } |
139ccd3f JB |
4033 | if (i == 4) |
4034 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 4035 | } |
357555c0 | 4036 | |
139ccd3f | 4037 | train_done: |
357555c0 JB |
4038 | DRM_DEBUG_KMS("FDI train done.\n"); |
4039 | } | |
4040 | ||
88cefb6c | 4041 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 4042 | { |
88cefb6c | 4043 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 4044 | struct drm_i915_private *dev_priv = to_i915(dev); |
2c07245f | 4045 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
4046 | i915_reg_t reg; |
4047 | u32 temp; | |
c64e311e | 4048 | |
c98e9dcf | 4049 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
4050 | reg = FDI_RX_CTL(pipe); |
4051 | temp = I915_READ(reg); | |
627eb5a3 | 4052 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 4053 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 4054 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
4055 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
4056 | ||
4057 | POSTING_READ(reg); | |
c98e9dcf JB |
4058 | udelay(200); |
4059 | ||
4060 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
4061 | temp = I915_READ(reg); |
4062 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
4063 | ||
4064 | POSTING_READ(reg); | |
c98e9dcf JB |
4065 | udelay(200); |
4066 | ||
20749730 PZ |
4067 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
4068 | reg = FDI_TX_CTL(pipe); | |
4069 | temp = I915_READ(reg); | |
4070 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
4071 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 4072 | |
20749730 PZ |
4073 | POSTING_READ(reg); |
4074 | udelay(100); | |
6be4a607 | 4075 | } |
0e23b99d JB |
4076 | } |
4077 | ||
88cefb6c DV |
4078 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
4079 | { | |
4080 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 4081 | struct drm_i915_private *dev_priv = to_i915(dev); |
88cefb6c | 4082 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
4083 | i915_reg_t reg; |
4084 | u32 temp; | |
88cefb6c DV |
4085 | |
4086 | /* Switch from PCDclk to Rawclk */ | |
4087 | reg = FDI_RX_CTL(pipe); | |
4088 | temp = I915_READ(reg); | |
4089 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
4090 | ||
4091 | /* Disable CPU FDI TX PLL */ | |
4092 | reg = FDI_TX_CTL(pipe); | |
4093 | temp = I915_READ(reg); | |
4094 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
4095 | ||
4096 | POSTING_READ(reg); | |
4097 | udelay(100); | |
4098 | ||
4099 | reg = FDI_RX_CTL(pipe); | |
4100 | temp = I915_READ(reg); | |
4101 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
4102 | ||
4103 | /* Wait for the clocks to turn off. */ | |
4104 | POSTING_READ(reg); | |
4105 | udelay(100); | |
4106 | } | |
4107 | ||
0fc932b8 JB |
4108 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
4109 | { | |
4110 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4111 | struct drm_i915_private *dev_priv = to_i915(dev); |
0fc932b8 JB |
4112 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4113 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
4114 | i915_reg_t reg; |
4115 | u32 temp; | |
0fc932b8 JB |
4116 | |
4117 | /* disable CPU FDI tx and PCH FDI rx */ | |
4118 | reg = FDI_TX_CTL(pipe); | |
4119 | temp = I915_READ(reg); | |
4120 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
4121 | POSTING_READ(reg); | |
4122 | ||
4123 | reg = FDI_RX_CTL(pipe); | |
4124 | temp = I915_READ(reg); | |
4125 | temp &= ~(0x7 << 16); | |
dfd07d72 | 4126 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
4127 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
4128 | ||
4129 | POSTING_READ(reg); | |
4130 | udelay(100); | |
4131 | ||
4132 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6e266956 | 4133 | if (HAS_PCH_IBX(dev_priv)) |
6f06ce18 | 4134 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
4135 | |
4136 | /* still set train pattern 1 */ | |
4137 | reg = FDI_TX_CTL(pipe); | |
4138 | temp = I915_READ(reg); | |
4139 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4140 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4141 | I915_WRITE(reg, temp); | |
4142 | ||
4143 | reg = FDI_RX_CTL(pipe); | |
4144 | temp = I915_READ(reg); | |
6e266956 | 4145 | if (HAS_PCH_CPT(dev_priv)) { |
0fc932b8 JB |
4146 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
4147 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
4148 | } else { | |
4149 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4150 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4151 | } | |
4152 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
4153 | temp &= ~(0x07 << 16); | |
dfd07d72 | 4154 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
4155 | I915_WRITE(reg, temp); |
4156 | ||
4157 | POSTING_READ(reg); | |
4158 | udelay(100); | |
4159 | } | |
4160 | ||
49d73912 | 4161 | bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) |
5dce5b93 CW |
4162 | { |
4163 | struct intel_crtc *crtc; | |
4164 | ||
4165 | /* Note that we don't need to be called with mode_config.lock here | |
4166 | * as our list of CRTC objects is static for the lifetime of the | |
4167 | * device and so cannot disappear as we iterate. Similarly, we can | |
4168 | * happily treat the predicates as racy, atomic checks as userspace | |
4169 | * cannot claim and pin a new fb without at least acquring the | |
4170 | * struct_mutex and so serialising with us. | |
4171 | */ | |
49d73912 | 4172 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
5dce5b93 CW |
4173 | if (atomic_read(&crtc->unpin_work_count) == 0) |
4174 | continue; | |
4175 | ||
5a21b665 | 4176 | if (crtc->flip_work) |
0f0f74bc | 4177 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
5dce5b93 CW |
4178 | |
4179 | return true; | |
4180 | } | |
4181 | ||
4182 | return false; | |
4183 | } | |
4184 | ||
5a21b665 | 4185 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
d6bbafa1 CW |
4186 | { |
4187 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
5a21b665 DV |
4188 | struct intel_flip_work *work = intel_crtc->flip_work; |
4189 | ||
4190 | intel_crtc->flip_work = NULL; | |
d6bbafa1 CW |
4191 | |
4192 | if (work->event) | |
560ce1dc | 4193 | drm_crtc_send_vblank_event(&intel_crtc->base, work->event); |
d6bbafa1 CW |
4194 | |
4195 | drm_crtc_vblank_put(&intel_crtc->base); | |
4196 | ||
5a21b665 | 4197 | wake_up_all(&dev_priv->pending_flip_queue); |
5a21b665 DV |
4198 | trace_i915_flip_complete(intel_crtc->plane, |
4199 | work->pending_flip_obj); | |
05c41f92 AR |
4200 | |
4201 | queue_work(dev_priv->wq, &work->unpin_work); | |
d6bbafa1 CW |
4202 | } |
4203 | ||
5008e874 | 4204 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 4205 | { |
0f91128d | 4206 | struct drm_device *dev = crtc->dev; |
fac5e23e | 4207 | struct drm_i915_private *dev_priv = to_i915(dev); |
5008e874 | 4208 | long ret; |
e6c3a2a6 | 4209 | |
2c10d571 | 4210 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
4211 | |
4212 | ret = wait_event_interruptible_timeout( | |
4213 | dev_priv->pending_flip_queue, | |
4214 | !intel_crtc_has_pending_flip(crtc), | |
4215 | 60*HZ); | |
4216 | ||
4217 | if (ret < 0) | |
4218 | return ret; | |
4219 | ||
5a21b665 DV |
4220 | if (ret == 0) { |
4221 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4222 | struct intel_flip_work *work; | |
4223 | ||
4224 | spin_lock_irq(&dev->event_lock); | |
4225 | work = intel_crtc->flip_work; | |
4226 | if (work && !is_mmio_work(work)) { | |
4227 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
4228 | page_flip_completed(intel_crtc); | |
4229 | } | |
4230 | spin_unlock_irq(&dev->event_lock); | |
4231 | } | |
5bb61643 | 4232 | |
5008e874 | 4233 | return 0; |
e6c3a2a6 CW |
4234 | } |
4235 | ||
b7076546 | 4236 | void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
060f02d8 VS |
4237 | { |
4238 | u32 temp; | |
4239 | ||
4240 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
4241 | ||
4242 | mutex_lock(&dev_priv->sb_lock); | |
4243 | ||
4244 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4245 | temp |= SBI_SSCCTL_DISABLE; | |
4246 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
4247 | ||
4248 | mutex_unlock(&dev_priv->sb_lock); | |
4249 | } | |
4250 | ||
e615efe4 | 4251 | /* Program iCLKIP clock to the desired frequency */ |
0dcdc382 | 4252 | static void lpt_program_iclkip(struct intel_crtc *crtc) |
e615efe4 | 4253 | { |
0dcdc382 ACO |
4254 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
4255 | int clock = crtc->config->base.adjusted_mode.crtc_clock; | |
e615efe4 ED |
4256 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
4257 | u32 temp; | |
4258 | ||
060f02d8 | 4259 | lpt_disable_iclkip(dev_priv); |
e615efe4 | 4260 | |
64b46a06 VS |
4261 | /* The iCLK virtual clock root frequency is in MHz, |
4262 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
4263 | * divisors, it is necessary to divide one by another, so we | |
4264 | * convert the virtual clock precision to KHz here for higher | |
4265 | * precision. | |
4266 | */ | |
4267 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
e615efe4 ED |
4268 | u32 iclk_virtual_root_freq = 172800 * 1000; |
4269 | u32 iclk_pi_range = 64; | |
64b46a06 | 4270 | u32 desired_divisor; |
e615efe4 | 4271 | |
64b46a06 VS |
4272 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
4273 | clock << auxdiv); | |
4274 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
4275 | phaseinc = desired_divisor % iclk_pi_range; | |
e615efe4 | 4276 | |
64b46a06 VS |
4277 | /* |
4278 | * Near 20MHz is a corner case which is | |
4279 | * out of range for the 7-bit divisor | |
4280 | */ | |
4281 | if (divsel <= 0x7f) | |
4282 | break; | |
e615efe4 ED |
4283 | } |
4284 | ||
4285 | /* This should not happen with any sane values */ | |
4286 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
4287 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
4288 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
4289 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
4290 | ||
4291 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 4292 | clock, |
e615efe4 ED |
4293 | auxdiv, |
4294 | divsel, | |
4295 | phasedir, | |
4296 | phaseinc); | |
4297 | ||
060f02d8 VS |
4298 | mutex_lock(&dev_priv->sb_lock); |
4299 | ||
e615efe4 | 4300 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 4301 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4302 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4303 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4304 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4305 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4306 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4307 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4308 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4309 | |
4310 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4311 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4312 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4313 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4314 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4315 | |
4316 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4317 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4318 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4319 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 4320 | |
060f02d8 VS |
4321 | mutex_unlock(&dev_priv->sb_lock); |
4322 | ||
e615efe4 ED |
4323 | /* Wait for initialization time */ |
4324 | udelay(24); | |
4325 | ||
4326 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
4327 | } | |
4328 | ||
8802e5b6 VS |
4329 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
4330 | { | |
4331 | u32 divsel, phaseinc, auxdiv; | |
4332 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
4333 | u32 iclk_pi_range = 64; | |
4334 | u32 desired_divisor; | |
4335 | u32 temp; | |
4336 | ||
4337 | if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) | |
4338 | return 0; | |
4339 | ||
4340 | mutex_lock(&dev_priv->sb_lock); | |
4341 | ||
4342 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4343 | if (temp & SBI_SSCCTL_DISABLE) { | |
4344 | mutex_unlock(&dev_priv->sb_lock); | |
4345 | return 0; | |
4346 | } | |
4347 | ||
4348 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
4349 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
4350 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
4351 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
4352 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
4353 | ||
4354 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
4355 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
4356 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
4357 | ||
4358 | mutex_unlock(&dev_priv->sb_lock); | |
4359 | ||
4360 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
4361 | ||
4362 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
4363 | desired_divisor << auxdiv); | |
4364 | } | |
4365 | ||
275f01b2 DV |
4366 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4367 | enum pipe pch_transcoder) | |
4368 | { | |
4369 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4370 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 4371 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4372 | |
4373 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4374 | I915_READ(HTOTAL(cpu_transcoder))); | |
4375 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4376 | I915_READ(HBLANK(cpu_transcoder))); | |
4377 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4378 | I915_READ(HSYNC(cpu_transcoder))); | |
4379 | ||
4380 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4381 | I915_READ(VTOTAL(cpu_transcoder))); | |
4382 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4383 | I915_READ(VBLANK(cpu_transcoder))); | |
4384 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4385 | I915_READ(VSYNC(cpu_transcoder))); | |
4386 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4387 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4388 | } | |
4389 | ||
003632d9 | 4390 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 | 4391 | { |
fac5e23e | 4392 | struct drm_i915_private *dev_priv = to_i915(dev); |
1fbc0d78 DV |
4393 | uint32_t temp; |
4394 | ||
4395 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4396 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4397 | return; |
4398 | ||
4399 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4400 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4401 | ||
003632d9 ACO |
4402 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4403 | if (enable) | |
4404 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4405 | ||
4406 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4407 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4408 | POSTING_READ(SOUTH_CHICKEN1); | |
4409 | } | |
4410 | ||
4411 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4412 | { | |
4413 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4414 | |
4415 | switch (intel_crtc->pipe) { | |
4416 | case PIPE_A: | |
4417 | break; | |
4418 | case PIPE_B: | |
6e3c9717 | 4419 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4420 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4421 | else |
003632d9 | 4422 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4423 | |
4424 | break; | |
4425 | case PIPE_C: | |
003632d9 | 4426 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4427 | |
4428 | break; | |
4429 | default: | |
4430 | BUG(); | |
4431 | } | |
4432 | } | |
4433 | ||
c48b5305 VS |
4434 | /* Return which DP Port should be selected for Transcoder DP control */ |
4435 | static enum port | |
4cbe4b2b | 4436 | intel_trans_dp_port_sel(struct intel_crtc *crtc) |
c48b5305 | 4437 | { |
4cbe4b2b | 4438 | struct drm_device *dev = crtc->base.dev; |
c48b5305 VS |
4439 | struct intel_encoder *encoder; |
4440 | ||
4cbe4b2b | 4441 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
cca0502b | 4442 | if (encoder->type == INTEL_OUTPUT_DP || |
c48b5305 VS |
4443 | encoder->type == INTEL_OUTPUT_EDP) |
4444 | return enc_to_dig_port(&encoder->base)->port; | |
4445 | } | |
4446 | ||
4447 | return -1; | |
4448 | } | |
4449 | ||
f67a559d JB |
4450 | /* |
4451 | * Enable PCH resources required for PCH ports: | |
4452 | * - PCH PLLs | |
4453 | * - FDI training & RX/TX | |
4454 | * - update transcoder timings | |
4455 | * - DP transcoding bits | |
4456 | * - transcoder | |
4457 | */ | |
2ce42273 | 4458 | static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state) |
0e23b99d | 4459 | { |
2ce42273 | 4460 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
4cbe4b2b | 4461 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4462 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 4463 | int pipe = crtc->pipe; |
f0f59a00 | 4464 | u32 temp; |
2c07245f | 4465 | |
ab9412ba | 4466 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4467 | |
fd6b8f43 | 4468 | if (IS_IVYBRIDGE(dev_priv)) |
4cbe4b2b | 4469 | ivybridge_update_fdi_bc_bifurcation(crtc); |
1fbc0d78 | 4470 | |
cd986abb DV |
4471 | /* Write the TU size bits before fdi link training, so that error |
4472 | * detection works. */ | |
4473 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4474 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4475 | ||
c98e9dcf | 4476 | /* For PCH output, training FDI link */ |
674cf967 | 4477 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4478 | |
3ad8a208 DV |
4479 | /* We need to program the right clock selection before writing the pixel |
4480 | * mutliplier into the DPLL. */ | |
6e266956 | 4481 | if (HAS_PCH_CPT(dev_priv)) { |
ee7b9f93 | 4482 | u32 sel; |
4b645f14 | 4483 | |
c98e9dcf | 4484 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4485 | temp |= TRANS_DPLL_ENABLE(pipe); |
4486 | sel = TRANS_DPLLB_SEL(pipe); | |
2ce42273 | 4487 | if (crtc_state->shared_dpll == |
8106ddbd | 4488 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) |
ee7b9f93 JB |
4489 | temp |= sel; |
4490 | else | |
4491 | temp &= ~sel; | |
c98e9dcf | 4492 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4493 | } |
5eddb70b | 4494 | |
3ad8a208 DV |
4495 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4496 | * transcoder, and we actually should do this to not upset any PCH | |
4497 | * transcoder that already use the clock when we share it. | |
4498 | * | |
4499 | * Note that enable_shared_dpll tries to do the right thing, but | |
4500 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4501 | * the right LVDS enable sequence. */ | |
4cbe4b2b | 4502 | intel_enable_shared_dpll(crtc); |
3ad8a208 | 4503 | |
d9b6cb56 JB |
4504 | /* set transcoder timing, panel must allow it */ |
4505 | assert_panel_unlocked(dev_priv, pipe); | |
4cbe4b2b | 4506 | ironlake_pch_transcoder_set_timings(crtc, pipe); |
8db9d77b | 4507 | |
303b81e0 | 4508 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4509 | |
c98e9dcf | 4510 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e266956 | 4511 | if (HAS_PCH_CPT(dev_priv) && |
2ce42273 | 4512 | intel_crtc_has_dp_encoder(crtc_state)) { |
9c4edaee | 4513 | const struct drm_display_mode *adjusted_mode = |
2ce42273 | 4514 | &crtc_state->base.adjusted_mode; |
dfd07d72 | 4515 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4516 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4517 | temp = I915_READ(reg); |
4518 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4519 | TRANS_DP_SYNC_MASK | |
4520 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4521 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4522 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4523 | |
9c4edaee | 4524 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4525 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4526 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4527 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4528 | |
4529 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4530 | case PORT_B: |
5eddb70b | 4531 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4532 | break; |
c48b5305 | 4533 | case PORT_C: |
5eddb70b | 4534 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4535 | break; |
c48b5305 | 4536 | case PORT_D: |
5eddb70b | 4537 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4538 | break; |
4539 | default: | |
e95d41e1 | 4540 | BUG(); |
32f9d658 | 4541 | } |
2c07245f | 4542 | |
5eddb70b | 4543 | I915_WRITE(reg, temp); |
6be4a607 | 4544 | } |
b52eb4dc | 4545 | |
b8a4f404 | 4546 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4547 | } |
4548 | ||
2ce42273 | 4549 | static void lpt_pch_enable(const struct intel_crtc_state *crtc_state) |
1507e5bd | 4550 | { |
2ce42273 | 4551 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
0dcdc382 | 4552 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2ce42273 | 4553 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
1507e5bd | 4554 | |
ab9412ba | 4555 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4556 | |
8c52b5e8 | 4557 | lpt_program_iclkip(crtc); |
1507e5bd | 4558 | |
0540e488 | 4559 | /* Set transcoder timing. */ |
0dcdc382 | 4560 | ironlake_pch_transcoder_set_timings(crtc, PIPE_A); |
1507e5bd | 4561 | |
937bb610 | 4562 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4563 | } |
4564 | ||
a1520318 | 4565 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 | 4566 | { |
fac5e23e | 4567 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 4568 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4569 | u32 temp; |
4570 | ||
4571 | temp = I915_READ(dslreg); | |
4572 | udelay(500); | |
4573 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4574 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4575 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4576 | } |
4577 | } | |
4578 | ||
86adf9d7 ML |
4579 | static int |
4580 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4581 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4582 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4583 | { |
86adf9d7 ML |
4584 | struct intel_crtc_scaler_state *scaler_state = |
4585 | &crtc_state->scaler_state; | |
4586 | struct intel_crtc *intel_crtc = | |
4587 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4588 | int need_scaling; |
6156a456 | 4589 | |
bd2ef25d | 4590 | need_scaling = drm_rotation_90_or_270(rotation) ? |
6156a456 CK |
4591 | (src_h != dst_w || src_w != dst_h): |
4592 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4593 | |
4594 | /* | |
4595 | * if plane is being disabled or scaler is no more required or force detach | |
4596 | * - free scaler binded to this plane/crtc | |
4597 | * - in order to do this, update crtc->scaler_usage | |
4598 | * | |
4599 | * Here scaler state in crtc_state is set free so that | |
4600 | * scaler can be assigned to other user. Actual register | |
4601 | * update to free the scaler is done in plane/panel-fit programming. | |
4602 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4603 | */ | |
86adf9d7 | 4604 | if (force_detach || !need_scaling) { |
a1b2278e | 4605 | if (*scaler_id >= 0) { |
86adf9d7 | 4606 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4607 | scaler_state->scalers[*scaler_id].in_use = 0; |
4608 | ||
86adf9d7 ML |
4609 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4610 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4611 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4612 | scaler_state->scaler_users); |
4613 | *scaler_id = -1; | |
4614 | } | |
4615 | return 0; | |
4616 | } | |
4617 | ||
4618 | /* range checks */ | |
4619 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4620 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4621 | ||
4622 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4623 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4624 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4625 | "size is out of scaler range\n", |
86adf9d7 | 4626 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4627 | return -EINVAL; |
4628 | } | |
4629 | ||
86adf9d7 ML |
4630 | /* mark this plane as a scaler user in crtc_state */ |
4631 | scaler_state->scaler_users |= (1 << scaler_user); | |
4632 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4633 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4634 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4635 | scaler_state->scaler_users); | |
4636 | ||
4637 | return 0; | |
4638 | } | |
4639 | ||
4640 | /** | |
4641 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4642 | * | |
4643 | * @state: crtc's scaler state | |
86adf9d7 ML |
4644 | * |
4645 | * Return | |
4646 | * 0 - scaler_usage updated successfully | |
4647 | * error - requested scaling cannot be supported or other error condition | |
4648 | */ | |
e435d6e5 | 4649 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 | 4650 | { |
7c5f93b0 | 4651 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 | 4652 | |
e435d6e5 | 4653 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
31ad61e4 | 4654 | &state->scaler_state.scaler_id, DRM_ROTATE_0, |
86adf9d7 | 4655 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4656 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4657 | } |
4658 | ||
4659 | /** | |
4660 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4661 | * | |
4662 | * @state: crtc's scaler state | |
86adf9d7 ML |
4663 | * @plane_state: atomic plane state to update |
4664 | * | |
4665 | * Return | |
4666 | * 0 - scaler_usage updated successfully | |
4667 | * error - requested scaling cannot be supported or other error condition | |
4668 | */ | |
da20eabd ML |
4669 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4670 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4671 | { |
4672 | ||
da20eabd ML |
4673 | struct intel_plane *intel_plane = |
4674 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4675 | struct drm_framebuffer *fb = plane_state->base.fb; |
4676 | int ret; | |
4677 | ||
936e71e3 | 4678 | bool force_detach = !fb || !plane_state->base.visible; |
86adf9d7 | 4679 | |
86adf9d7 ML |
4680 | ret = skl_update_scaler(crtc_state, force_detach, |
4681 | drm_plane_index(&intel_plane->base), | |
4682 | &plane_state->scaler_id, | |
4683 | plane_state->base.rotation, | |
936e71e3 VS |
4684 | drm_rect_width(&plane_state->base.src) >> 16, |
4685 | drm_rect_height(&plane_state->base.src) >> 16, | |
4686 | drm_rect_width(&plane_state->base.dst), | |
4687 | drm_rect_height(&plane_state->base.dst)); | |
86adf9d7 ML |
4688 | |
4689 | if (ret || plane_state->scaler_id < 0) | |
4690 | return ret; | |
4691 | ||
a1b2278e | 4692 | /* check colorkey */ |
818ed961 | 4693 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
72660ce0 VS |
4694 | DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed", |
4695 | intel_plane->base.base.id, | |
4696 | intel_plane->base.name); | |
a1b2278e CK |
4697 | return -EINVAL; |
4698 | } | |
4699 | ||
4700 | /* Check src format */ | |
438b74a5 | 4701 | switch (fb->format->format) { |
86adf9d7 ML |
4702 | case DRM_FORMAT_RGB565: |
4703 | case DRM_FORMAT_XBGR8888: | |
4704 | case DRM_FORMAT_XRGB8888: | |
4705 | case DRM_FORMAT_ABGR8888: | |
4706 | case DRM_FORMAT_ARGB8888: | |
4707 | case DRM_FORMAT_XRGB2101010: | |
4708 | case DRM_FORMAT_XBGR2101010: | |
4709 | case DRM_FORMAT_YUYV: | |
4710 | case DRM_FORMAT_YVYU: | |
4711 | case DRM_FORMAT_UYVY: | |
4712 | case DRM_FORMAT_VYUY: | |
4713 | break; | |
4714 | default: | |
72660ce0 VS |
4715 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", |
4716 | intel_plane->base.base.id, intel_plane->base.name, | |
438b74a5 | 4717 | fb->base.id, fb->format->format); |
86adf9d7 | 4718 | return -EINVAL; |
a1b2278e CK |
4719 | } |
4720 | ||
a1b2278e CK |
4721 | return 0; |
4722 | } | |
4723 | ||
e435d6e5 ML |
4724 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4725 | { | |
4726 | int i; | |
4727 | ||
4728 | for (i = 0; i < crtc->num_scalers; i++) | |
4729 | skl_detach_scaler(crtc, i); | |
4730 | } | |
4731 | ||
4732 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4733 | { |
4734 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4735 | struct drm_i915_private *dev_priv = to_i915(dev); |
bd2e244f | 4736 | int pipe = crtc->pipe; |
a1b2278e CK |
4737 | struct intel_crtc_scaler_state *scaler_state = |
4738 | &crtc->config->scaler_state; | |
4739 | ||
4740 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4741 | ||
6e3c9717 | 4742 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4743 | int id; |
4744 | ||
4745 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4746 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4747 | return; | |
4748 | } | |
4749 | ||
4750 | id = scaler_state->scaler_id; | |
4751 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4752 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4753 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4754 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4755 | ||
4756 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4757 | } |
4758 | } | |
4759 | ||
b074cec8 JB |
4760 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4761 | { | |
4762 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4763 | struct drm_i915_private *dev_priv = to_i915(dev); |
b074cec8 JB |
4764 | int pipe = crtc->pipe; |
4765 | ||
6e3c9717 | 4766 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4767 | /* Force use of hard-coded filter coefficients |
4768 | * as some pre-programmed values are broken, | |
4769 | * e.g. x201. | |
4770 | */ | |
fd6b8f43 | 4771 | if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) |
b074cec8 JB |
4772 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | |
4773 | PF_PIPE_SEL_IVB(pipe)); | |
4774 | else | |
4775 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4776 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4777 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4778 | } |
4779 | } | |
4780 | ||
20bc8673 | 4781 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4782 | { |
cea165c3 | 4783 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4784 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4785 | |
6e3c9717 | 4786 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4787 | return; |
4788 | ||
307e4498 ML |
4789 | /* |
4790 | * We can only enable IPS after we enable a plane and wait for a vblank | |
4791 | * This function is called from post_plane_update, which is run after | |
4792 | * a vblank wait. | |
4793 | */ | |
cea165c3 | 4794 | |
d77e4531 | 4795 | assert_plane_enabled(dev_priv, crtc->plane); |
8652744b | 4796 | if (IS_BROADWELL(dev_priv)) { |
2a114cc1 BW |
4797 | mutex_lock(&dev_priv->rps.hw_lock); |
4798 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4799 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4800 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4801 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4802 | * mailbox." Moreover, the mailbox may return a bogus state, |
4803 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4804 | */ |
4805 | } else { | |
4806 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4807 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4808 | * is essentially intel_wait_for_vblank. If we don't have this | |
4809 | * and don't wait for vblanks until the end of crtc_enable, then | |
4810 | * the HW state readout code will complain that the expected | |
4811 | * IPS_CTL value is not the one we read. */ | |
2ec9ba3c CW |
4812 | if (intel_wait_for_register(dev_priv, |
4813 | IPS_CTL, IPS_ENABLE, IPS_ENABLE, | |
4814 | 50)) | |
2a114cc1 BW |
4815 | DRM_ERROR("Timed out waiting for IPS enable\n"); |
4816 | } | |
d77e4531 PZ |
4817 | } |
4818 | ||
20bc8673 | 4819 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4820 | { |
4821 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4822 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4823 | |
6e3c9717 | 4824 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4825 | return; |
4826 | ||
4827 | assert_plane_enabled(dev_priv, crtc->plane); | |
8652744b | 4828 | if (IS_BROADWELL(dev_priv)) { |
2a114cc1 BW |
4829 | mutex_lock(&dev_priv->rps.hw_lock); |
4830 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4831 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 | 4832 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
b85c1ecf CW |
4833 | if (intel_wait_for_register(dev_priv, |
4834 | IPS_CTL, IPS_ENABLE, 0, | |
4835 | 42)) | |
23d0b130 | 4836 | DRM_ERROR("Timed out waiting for IPS disable\n"); |
e59150dc | 4837 | } else { |
2a114cc1 | 4838 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4839 | POSTING_READ(IPS_CTL); |
4840 | } | |
d77e4531 PZ |
4841 | |
4842 | /* We need to wait for a vblank before we can disable the plane. */ | |
0f0f74bc | 4843 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
d77e4531 PZ |
4844 | } |
4845 | ||
7cac945f | 4846 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4847 | { |
7cac945f | 4848 | if (intel_crtc->overlay) { |
d3eedb1a | 4849 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 4850 | struct drm_i915_private *dev_priv = to_i915(dev); |
d3eedb1a VS |
4851 | |
4852 | mutex_lock(&dev->struct_mutex); | |
4853 | dev_priv->mm.interruptible = false; | |
4854 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4855 | dev_priv->mm.interruptible = true; | |
4856 | mutex_unlock(&dev->struct_mutex); | |
4857 | } | |
4858 | ||
4859 | /* Let userspace switch the overlay on again. In most cases userspace | |
4860 | * has to recompute where to put it anyway. | |
4861 | */ | |
4862 | } | |
4863 | ||
87d4300a ML |
4864 | /** |
4865 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4866 | * @crtc: the CRTC whose primary plane was just enabled | |
4867 | * | |
4868 | * Performs potentially sleeping operations that must be done after the primary | |
4869 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4870 | * called due to an explicit primary plane update, or due to an implicit | |
4871 | * re-enable that is caused when a sprite plane is updated to no longer | |
4872 | * completely hide the primary plane. | |
4873 | */ | |
4874 | static void | |
4875 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4876 | { |
4877 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4878 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4879 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4880 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4881 | |
87d4300a ML |
4882 | /* |
4883 | * FIXME IPS should be fine as long as one plane is | |
4884 | * enabled, but in practice it seems to have problems | |
4885 | * when going from primary only to sprite only and vice | |
4886 | * versa. | |
4887 | */ | |
a5c4d7bc VS |
4888 | hsw_enable_ips(intel_crtc); |
4889 | ||
f99d7069 | 4890 | /* |
87d4300a ML |
4891 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4892 | * So don't enable underrun reporting before at least some planes | |
4893 | * are enabled. | |
4894 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4895 | * but leave the pipe running. | |
f99d7069 | 4896 | */ |
5db94019 | 4897 | if (IS_GEN2(dev_priv)) |
87d4300a ML |
4898 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4899 | ||
aca7b684 VS |
4900 | /* Underruns don't always raise interrupts, so check manually. */ |
4901 | intel_check_cpu_fifo_underruns(dev_priv); | |
4902 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4903 | } |
4904 | ||
2622a081 | 4905 | /* FIXME move all this to pre_plane_update() with proper state tracking */ |
87d4300a ML |
4906 | static void |
4907 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4908 | { |
4909 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4910 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4911 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4912 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4913 | |
87d4300a ML |
4914 | /* |
4915 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4916 | * So diasble underrun reporting before all the planes get disabled. | |
4917 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4918 | * but leave the pipe running. | |
4919 | */ | |
5db94019 | 4920 | if (IS_GEN2(dev_priv)) |
87d4300a | 4921 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
a5c4d7bc | 4922 | |
2622a081 VS |
4923 | /* |
4924 | * FIXME IPS should be fine as long as one plane is | |
4925 | * enabled, but in practice it seems to have problems | |
4926 | * when going from primary only to sprite only and vice | |
4927 | * versa. | |
4928 | */ | |
4929 | hsw_disable_ips(intel_crtc); | |
4930 | } | |
4931 | ||
4932 | /* FIXME get rid of this and use pre_plane_update */ | |
4933 | static void | |
4934 | intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) | |
4935 | { | |
4936 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4937 | struct drm_i915_private *dev_priv = to_i915(dev); |
2622a081 VS |
4938 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4939 | int pipe = intel_crtc->pipe; | |
4940 | ||
4941 | intel_pre_disable_primary(crtc); | |
4942 | ||
87d4300a ML |
4943 | /* |
4944 | * Vblank time updates from the shadow to live plane control register | |
4945 | * are blocked if the memory self-refresh mode is active at that | |
4946 | * moment. So to make sure the plane gets truly disabled, disable | |
4947 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4948 | * will be checked/applied by the HW only at the next frame start | |
4949 | * event which is after the vblank start event, so we need to have a | |
4950 | * wait-for-vblank between disabling the plane and the pipe. | |
4951 | */ | |
11a85d6a VS |
4952 | if (HAS_GMCH_DISPLAY(dev_priv) && |
4953 | intel_set_memory_cxsr(dev_priv, false)) | |
0f0f74bc | 4954 | intel_wait_for_vblank(dev_priv, pipe); |
87d4300a ML |
4955 | } |
4956 | ||
5a21b665 DV |
4957 | static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) |
4958 | { | |
4959 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); | |
4960 | struct drm_atomic_state *old_state = old_crtc_state->base.state; | |
4961 | struct intel_crtc_state *pipe_config = | |
4962 | to_intel_crtc_state(crtc->base.state); | |
5a21b665 DV |
4963 | struct drm_plane *primary = crtc->base.primary; |
4964 | struct drm_plane_state *old_pri_state = | |
4965 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4966 | ||
5748b6a1 | 4967 | intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits); |
5a21b665 DV |
4968 | |
4969 | crtc->wm.cxsr_allowed = true; | |
4970 | ||
4971 | if (pipe_config->update_wm_post && pipe_config->base.active) | |
432081bc | 4972 | intel_update_watermarks(crtc); |
5a21b665 DV |
4973 | |
4974 | if (old_pri_state) { | |
4975 | struct intel_plane_state *primary_state = | |
4976 | to_intel_plane_state(primary->state); | |
4977 | struct intel_plane_state *old_primary_state = | |
4978 | to_intel_plane_state(old_pri_state); | |
4979 | ||
4980 | intel_fbc_post_update(crtc); | |
4981 | ||
936e71e3 | 4982 | if (primary_state->base.visible && |
5a21b665 | 4983 | (needs_modeset(&pipe_config->base) || |
936e71e3 | 4984 | !old_primary_state->base.visible)) |
5a21b665 DV |
4985 | intel_post_enable_primary(&crtc->base); |
4986 | } | |
4987 | } | |
4988 | ||
5c74cd73 | 4989 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 4990 | { |
5c74cd73 | 4991 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 4992 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4993 | struct drm_i915_private *dev_priv = to_i915(dev); |
ab1d3a0e ML |
4994 | struct intel_crtc_state *pipe_config = |
4995 | to_intel_crtc_state(crtc->base.state); | |
5c74cd73 ML |
4996 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
4997 | struct drm_plane *primary = crtc->base.primary; | |
4998 | struct drm_plane_state *old_pri_state = | |
4999 | drm_atomic_get_existing_plane_state(old_state, primary); | |
5000 | bool modeset = needs_modeset(&pipe_config->base); | |
ccf010fb ML |
5001 | struct intel_atomic_state *old_intel_state = |
5002 | to_intel_atomic_state(old_state); | |
ac21b225 | 5003 | |
5c74cd73 ML |
5004 | if (old_pri_state) { |
5005 | struct intel_plane_state *primary_state = | |
5006 | to_intel_plane_state(primary->state); | |
5007 | struct intel_plane_state *old_primary_state = | |
5008 | to_intel_plane_state(old_pri_state); | |
5009 | ||
faf68d92 | 5010 | intel_fbc_pre_update(crtc, pipe_config, primary_state); |
31ae71fc | 5011 | |
936e71e3 VS |
5012 | if (old_primary_state->base.visible && |
5013 | (modeset || !primary_state->base.visible)) | |
5c74cd73 ML |
5014 | intel_pre_disable_primary(&crtc->base); |
5015 | } | |
852eb00d | 5016 | |
49cff963 | 5017 | if (pipe_config->disable_cxsr && HAS_GMCH_DISPLAY(dev_priv)) { |
852eb00d | 5018 | crtc->wm.cxsr_allowed = false; |
2dfd178d | 5019 | |
2622a081 VS |
5020 | /* |
5021 | * Vblank time updates from the shadow to live plane control register | |
5022 | * are blocked if the memory self-refresh mode is active at that | |
5023 | * moment. So to make sure the plane gets truly disabled, disable | |
5024 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5025 | * will be checked/applied by the HW only at the next frame start | |
5026 | * event which is after the vblank start event, so we need to have a | |
5027 | * wait-for-vblank between disabling the plane and the pipe. | |
5028 | */ | |
11a85d6a VS |
5029 | if (old_crtc_state->base.active && |
5030 | intel_set_memory_cxsr(dev_priv, false)) | |
0f0f74bc | 5031 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
852eb00d | 5032 | } |
92826fcd | 5033 | |
ed4a6a7c MR |
5034 | /* |
5035 | * IVB workaround: must disable low power watermarks for at least | |
5036 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
5037 | * when scaling is disabled. | |
5038 | * | |
5039 | * WaCxSRDisabledForSpriteScaling:ivb | |
5040 | */ | |
ddd2b792 | 5041 | if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev)) |
0f0f74bc | 5042 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
ed4a6a7c MR |
5043 | |
5044 | /* | |
5045 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
5046 | * watermark programming here. | |
5047 | */ | |
5048 | if (needs_modeset(&pipe_config->base)) | |
5049 | return; | |
5050 | ||
5051 | /* | |
5052 | * For platforms that support atomic watermarks, program the | |
5053 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
5054 | * will be the intermediate values that are safe for both pre- and | |
5055 | * post- vblank; when vblank happens, the 'active' values will be set | |
5056 | * to the final 'target' values and we'll do this again to get the | |
5057 | * optimal watermarks. For gen9+ platforms, the values we program here | |
5058 | * will be the final target values which will get automatically latched | |
5059 | * at vblank time; no further programming will be necessary. | |
5060 | * | |
5061 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
5062 | * we'll continue to update watermarks the old way, if flags tell | |
5063 | * us to. | |
5064 | */ | |
5065 | if (dev_priv->display.initial_watermarks != NULL) | |
ccf010fb ML |
5066 | dev_priv->display.initial_watermarks(old_intel_state, |
5067 | pipe_config); | |
caed361d | 5068 | else if (pipe_config->update_wm_pre) |
432081bc | 5069 | intel_update_watermarks(crtc); |
ac21b225 ML |
5070 | } |
5071 | ||
d032ffa0 | 5072 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
5073 | { |
5074 | struct drm_device *dev = crtc->dev; | |
5075 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 5076 | struct drm_plane *p; |
87d4300a ML |
5077 | int pipe = intel_crtc->pipe; |
5078 | ||
7cac945f | 5079 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 5080 | |
d032ffa0 ML |
5081 | drm_for_each_plane_mask(p, dev, plane_mask) |
5082 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 5083 | |
f99d7069 DV |
5084 | /* |
5085 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
5086 | * to compute the mask of flip planes precisely. For the time being | |
5087 | * consider this a flip to a NULL plane. | |
5088 | */ | |
5748b6a1 | 5089 | intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe)); |
a5c4d7bc VS |
5090 | } |
5091 | ||
fb1c98b1 | 5092 | static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc, |
fd6bbda9 | 5093 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5094 | struct drm_atomic_state *old_state) |
5095 | { | |
5096 | struct drm_connector_state *old_conn_state; | |
5097 | struct drm_connector *conn; | |
5098 | int i; | |
5099 | ||
5100 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5101 | struct drm_connector_state *conn_state = conn->state; | |
5102 | struct intel_encoder *encoder = | |
5103 | to_intel_encoder(conn_state->best_encoder); | |
5104 | ||
5105 | if (conn_state->crtc != crtc) | |
5106 | continue; | |
5107 | ||
5108 | if (encoder->pre_pll_enable) | |
fd6bbda9 | 5109 | encoder->pre_pll_enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5110 | } |
5111 | } | |
5112 | ||
5113 | static void intel_encoders_pre_enable(struct drm_crtc *crtc, | |
fd6bbda9 | 5114 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5115 | struct drm_atomic_state *old_state) |
5116 | { | |
5117 | struct drm_connector_state *old_conn_state; | |
5118 | struct drm_connector *conn; | |
5119 | int i; | |
5120 | ||
5121 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5122 | struct drm_connector_state *conn_state = conn->state; | |
5123 | struct intel_encoder *encoder = | |
5124 | to_intel_encoder(conn_state->best_encoder); | |
5125 | ||
5126 | if (conn_state->crtc != crtc) | |
5127 | continue; | |
5128 | ||
5129 | if (encoder->pre_enable) | |
fd6bbda9 | 5130 | encoder->pre_enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5131 | } |
5132 | } | |
5133 | ||
5134 | static void intel_encoders_enable(struct drm_crtc *crtc, | |
fd6bbda9 | 5135 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5136 | struct drm_atomic_state *old_state) |
5137 | { | |
5138 | struct drm_connector_state *old_conn_state; | |
5139 | struct drm_connector *conn; | |
5140 | int i; | |
5141 | ||
5142 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5143 | struct drm_connector_state *conn_state = conn->state; | |
5144 | struct intel_encoder *encoder = | |
5145 | to_intel_encoder(conn_state->best_encoder); | |
5146 | ||
5147 | if (conn_state->crtc != crtc) | |
5148 | continue; | |
5149 | ||
fd6bbda9 | 5150 | encoder->enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5151 | intel_opregion_notify_encoder(encoder, true); |
5152 | } | |
5153 | } | |
5154 | ||
5155 | static void intel_encoders_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5156 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5157 | struct drm_atomic_state *old_state) |
5158 | { | |
5159 | struct drm_connector_state *old_conn_state; | |
5160 | struct drm_connector *conn; | |
5161 | int i; | |
5162 | ||
5163 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5164 | struct intel_encoder *encoder = | |
5165 | to_intel_encoder(old_conn_state->best_encoder); | |
5166 | ||
5167 | if (old_conn_state->crtc != crtc) | |
5168 | continue; | |
5169 | ||
5170 | intel_opregion_notify_encoder(encoder, false); | |
fd6bbda9 | 5171 | encoder->disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5172 | } |
5173 | } | |
5174 | ||
5175 | static void intel_encoders_post_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5176 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5177 | struct drm_atomic_state *old_state) |
5178 | { | |
5179 | struct drm_connector_state *old_conn_state; | |
5180 | struct drm_connector *conn; | |
5181 | int i; | |
5182 | ||
5183 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5184 | struct intel_encoder *encoder = | |
5185 | to_intel_encoder(old_conn_state->best_encoder); | |
5186 | ||
5187 | if (old_conn_state->crtc != crtc) | |
5188 | continue; | |
5189 | ||
5190 | if (encoder->post_disable) | |
fd6bbda9 | 5191 | encoder->post_disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5192 | } |
5193 | } | |
5194 | ||
5195 | static void intel_encoders_post_pll_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5196 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5197 | struct drm_atomic_state *old_state) |
5198 | { | |
5199 | struct drm_connector_state *old_conn_state; | |
5200 | struct drm_connector *conn; | |
5201 | int i; | |
5202 | ||
5203 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5204 | struct intel_encoder *encoder = | |
5205 | to_intel_encoder(old_conn_state->best_encoder); | |
5206 | ||
5207 | if (old_conn_state->crtc != crtc) | |
5208 | continue; | |
5209 | ||
5210 | if (encoder->post_pll_disable) | |
fd6bbda9 | 5211 | encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5212 | } |
5213 | } | |
5214 | ||
4a806558 ML |
5215 | static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config, |
5216 | struct drm_atomic_state *old_state) | |
f67a559d | 5217 | { |
4a806558 | 5218 | struct drm_crtc *crtc = pipe_config->base.crtc; |
f67a559d | 5219 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5220 | struct drm_i915_private *dev_priv = to_i915(dev); |
f67a559d JB |
5221 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5222 | int pipe = intel_crtc->pipe; | |
ccf010fb ML |
5223 | struct intel_atomic_state *old_intel_state = |
5224 | to_intel_atomic_state(old_state); | |
f67a559d | 5225 | |
53d9f4e9 | 5226 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
5227 | return; |
5228 | ||
b2c0593a VS |
5229 | /* |
5230 | * Sometimes spurious CPU pipe underruns happen during FDI | |
5231 | * training, at least with VGA+HDMI cloning. Suppress them. | |
5232 | * | |
5233 | * On ILK we get an occasional spurious CPU pipe underruns | |
5234 | * between eDP port A enable and vdd enable. Also PCH port | |
5235 | * enable seems to result in the occasional CPU pipe underrun. | |
5236 | * | |
5237 | * Spurious PCH underruns also occur during PCH enabling. | |
5238 | */ | |
5239 | if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv)) | |
5240 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
81b088ca VS |
5241 | if (intel_crtc->config->has_pch_encoder) |
5242 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
5243 | ||
6e3c9717 | 5244 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
5245 | intel_prepare_shared_dpll(intel_crtc); |
5246 | ||
37a5650b | 5247 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5248 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
5249 | |
5250 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 5251 | intel_set_pipe_src_size(intel_crtc); |
29407aab | 5252 | |
6e3c9717 | 5253 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 5254 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5255 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
5256 | } |
5257 | ||
5258 | ironlake_set_pipeconf(crtc); | |
5259 | ||
f67a559d | 5260 | intel_crtc->active = true; |
8664281b | 5261 | |
fd6bbda9 | 5262 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
f67a559d | 5263 | |
6e3c9717 | 5264 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
5265 | /* Note: FDI PLL enabling _must_ be done before we enable the |
5266 | * cpu pipes, hence this is separate from all the other fdi/pch | |
5267 | * enabling. */ | |
88cefb6c | 5268 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
5269 | } else { |
5270 | assert_fdi_tx_disabled(dev_priv, pipe); | |
5271 | assert_fdi_rx_disabled(dev_priv, pipe); | |
5272 | } | |
f67a559d | 5273 | |
b074cec8 | 5274 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 5275 | |
9c54c0dd JB |
5276 | /* |
5277 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5278 | * clocks enabled | |
5279 | */ | |
b95c5321 | 5280 | intel_color_load_luts(&pipe_config->base); |
9c54c0dd | 5281 | |
1d5bf5d9 | 5282 | if (dev_priv->display.initial_watermarks != NULL) |
ccf010fb | 5283 | dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config); |
e1fdc473 | 5284 | intel_enable_pipe(intel_crtc); |
f67a559d | 5285 | |
6e3c9717 | 5286 | if (intel_crtc->config->has_pch_encoder) |
2ce42273 | 5287 | ironlake_pch_enable(pipe_config); |
c98e9dcf | 5288 | |
f9b61ff6 DV |
5289 | assert_vblank_disabled(crtc); |
5290 | drm_crtc_vblank_on(crtc); | |
5291 | ||
fd6bbda9 | 5292 | intel_encoders_enable(crtc, pipe_config, old_state); |
61b77ddd | 5293 | |
6e266956 | 5294 | if (HAS_PCH_CPT(dev_priv)) |
a1520318 | 5295 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
5296 | |
5297 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
5298 | if (intel_crtc->config->has_pch_encoder) | |
0f0f74bc | 5299 | intel_wait_for_vblank(dev_priv, pipe); |
b2c0593a | 5300 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
37ca8d4c | 5301 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 JB |
5302 | } |
5303 | ||
42db64ef PZ |
5304 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
5305 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
5306 | { | |
50a0bc90 | 5307 | return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A; |
42db64ef PZ |
5308 | } |
5309 | ||
4a806558 ML |
5310 | static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, |
5311 | struct drm_atomic_state *old_state) | |
4f771f10 | 5312 | { |
4a806558 | 5313 | struct drm_crtc *crtc = pipe_config->base.crtc; |
6315b5d3 | 5314 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
4f771f10 | 5315 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
99d736a2 | 5316 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4d1de975 | 5317 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ccf010fb ML |
5318 | struct intel_atomic_state *old_intel_state = |
5319 | to_intel_atomic_state(old_state); | |
4f771f10 | 5320 | |
53d9f4e9 | 5321 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
5322 | return; |
5323 | ||
81b088ca VS |
5324 | if (intel_crtc->config->has_pch_encoder) |
5325 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5326 | false); | |
5327 | ||
fd6bbda9 | 5328 | intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); |
95a7a2ae | 5329 | |
8106ddbd | 5330 | if (intel_crtc->config->shared_dpll) |
df8ad70c DV |
5331 | intel_enable_shared_dpll(intel_crtc); |
5332 | ||
37a5650b | 5333 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5334 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 | 5335 | |
d7edc4e5 | 5336 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5337 | intel_set_pipe_timings(intel_crtc); |
5338 | ||
bc58be60 | 5339 | intel_set_pipe_src_size(intel_crtc); |
229fca97 | 5340 | |
4d1de975 JN |
5341 | if (cpu_transcoder != TRANSCODER_EDP && |
5342 | !transcoder_is_dsi(cpu_transcoder)) { | |
5343 | I915_WRITE(PIPE_MULT(cpu_transcoder), | |
6e3c9717 | 5344 | intel_crtc->config->pixel_multiplier - 1); |
ebb69c95 CT |
5345 | } |
5346 | ||
6e3c9717 | 5347 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 5348 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5349 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
5350 | } |
5351 | ||
d7edc4e5 | 5352 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5353 | haswell_set_pipeconf(crtc); |
5354 | ||
391bf048 | 5355 | haswell_set_pipemisc(crtc); |
229fca97 | 5356 | |
b95c5321 | 5357 | intel_color_set_csc(&pipe_config->base); |
229fca97 | 5358 | |
4f771f10 | 5359 | intel_crtc->active = true; |
8664281b | 5360 | |
6b698516 DV |
5361 | if (intel_crtc->config->has_pch_encoder) |
5362 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5363 | else | |
5364 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5365 | ||
fd6bbda9 | 5366 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
4f771f10 | 5367 | |
d2d65408 | 5368 | if (intel_crtc->config->has_pch_encoder) |
4cbe4b2b | 5369 | dev_priv->display.fdi_link_train(intel_crtc); |
4fe9467d | 5370 | |
d7edc4e5 | 5371 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5372 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 5373 | |
6315b5d3 | 5374 | if (INTEL_GEN(dev_priv) >= 9) |
e435d6e5 | 5375 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 5376 | else |
1c132b44 | 5377 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
5378 | |
5379 | /* | |
5380 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5381 | * clocks enabled | |
5382 | */ | |
b95c5321 | 5383 | intel_color_load_luts(&pipe_config->base); |
4f771f10 | 5384 | |
1f544388 | 5385 | intel_ddi_set_pipe_settings(crtc); |
d7edc4e5 | 5386 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5387 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 5388 | |
1d5bf5d9 | 5389 | if (dev_priv->display.initial_watermarks != NULL) |
3125d39f | 5390 | dev_priv->display.initial_watermarks(old_intel_state, pipe_config); |
4d1de975 JN |
5391 | |
5392 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ | |
d7edc4e5 | 5393 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5394 | intel_enable_pipe(intel_crtc); |
42db64ef | 5395 | |
6e3c9717 | 5396 | if (intel_crtc->config->has_pch_encoder) |
2ce42273 | 5397 | lpt_pch_enable(pipe_config); |
4f771f10 | 5398 | |
0037071d | 5399 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST)) |
0e32b39c DA |
5400 | intel_ddi_set_vc_payload_alloc(crtc, true); |
5401 | ||
f9b61ff6 DV |
5402 | assert_vblank_disabled(crtc); |
5403 | drm_crtc_vblank_on(crtc); | |
5404 | ||
fd6bbda9 | 5405 | intel_encoders_enable(crtc, pipe_config, old_state); |
4f771f10 | 5406 | |
6b698516 | 5407 | if (intel_crtc->config->has_pch_encoder) { |
0f0f74bc VS |
5408 | intel_wait_for_vblank(dev_priv, pipe); |
5409 | intel_wait_for_vblank(dev_priv, pipe); | |
6b698516 | 5410 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
d2d65408 VS |
5411 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5412 | true); | |
6b698516 | 5413 | } |
d2d65408 | 5414 | |
e4916946 PZ |
5415 | /* If we change the relative order between pipe/planes enabling, we need |
5416 | * to change the workaround. */ | |
99d736a2 | 5417 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
772c2a51 | 5418 | if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { |
0f0f74bc VS |
5419 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); |
5420 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); | |
99d736a2 | 5421 | } |
4f771f10 PZ |
5422 | } |
5423 | ||
bfd16b2a | 5424 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
5425 | { |
5426 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5427 | struct drm_i915_private *dev_priv = to_i915(dev); |
3f8dce3a DV |
5428 | int pipe = crtc->pipe; |
5429 | ||
5430 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5431 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5432 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5433 | I915_WRITE(PF_CTL(pipe), 0); |
5434 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5435 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5436 | } | |
5437 | } | |
5438 | ||
4a806558 ML |
5439 | static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5440 | struct drm_atomic_state *old_state) | |
6be4a607 | 5441 | { |
4a806558 | 5442 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
6be4a607 | 5443 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5444 | struct drm_i915_private *dev_priv = to_i915(dev); |
6be4a607 JB |
5445 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5446 | int pipe = intel_crtc->pipe; | |
b52eb4dc | 5447 | |
b2c0593a VS |
5448 | /* |
5449 | * Sometimes spurious CPU pipe underruns happen when the | |
5450 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
5451 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
5452 | */ | |
5453 | if (intel_crtc->config->has_pch_encoder) { | |
5454 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
37ca8d4c | 5455 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
b2c0593a | 5456 | } |
37ca8d4c | 5457 | |
fd6bbda9 | 5458 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
ea9d758d | 5459 | |
f9b61ff6 DV |
5460 | drm_crtc_vblank_off(crtc); |
5461 | assert_vblank_disabled(crtc); | |
5462 | ||
575f7ab7 | 5463 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5464 | |
bfd16b2a | 5465 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5466 | |
b2c0593a | 5467 | if (intel_crtc->config->has_pch_encoder) |
5a74f70a VS |
5468 | ironlake_fdi_disable(crtc); |
5469 | ||
fd6bbda9 | 5470 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
2c07245f | 5471 | |
6e3c9717 | 5472 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5473 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5474 | |
6e266956 | 5475 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 VS |
5476 | i915_reg_t reg; |
5477 | u32 temp; | |
5478 | ||
d925c59a DV |
5479 | /* disable TRANS_DP_CTL */ |
5480 | reg = TRANS_DP_CTL(pipe); | |
5481 | temp = I915_READ(reg); | |
5482 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5483 | TRANS_DP_PORT_SEL_MASK); | |
5484 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5485 | I915_WRITE(reg, temp); | |
5486 | ||
5487 | /* disable DPLL_SEL */ | |
5488 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5489 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5490 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5491 | } |
e3421a18 | 5492 | |
d925c59a DV |
5493 | ironlake_fdi_pll_disable(intel_crtc); |
5494 | } | |
81b088ca | 5495 | |
b2c0593a | 5496 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
81b088ca | 5497 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 | 5498 | } |
1b3c7a47 | 5499 | |
4a806558 ML |
5500 | static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5501 | struct drm_atomic_state *old_state) | |
ee7b9f93 | 5502 | { |
4a806558 | 5503 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
6315b5d3 | 5504 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee7b9f93 | 5505 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 5506 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5507 | |
d2d65408 VS |
5508 | if (intel_crtc->config->has_pch_encoder) |
5509 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5510 | false); | |
5511 | ||
fd6bbda9 | 5512 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
4f771f10 | 5513 | |
f9b61ff6 DV |
5514 | drm_crtc_vblank_off(crtc); |
5515 | assert_vblank_disabled(crtc); | |
5516 | ||
4d1de975 | 5517 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ |
d7edc4e5 | 5518 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5519 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5520 | |
0037071d | 5521 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST)) |
a4bf214f VS |
5522 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5523 | ||
d7edc4e5 | 5524 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5525 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5526 | |
6315b5d3 | 5527 | if (INTEL_GEN(dev_priv) >= 9) |
e435d6e5 | 5528 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5529 | else |
bfd16b2a | 5530 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5531 | |
d7edc4e5 | 5532 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5533 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5534 | |
fd6bbda9 | 5535 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
81b088ca | 5536 | |
b7076546 | 5537 | if (old_crtc_state->has_pch_encoder) |
81b088ca VS |
5538 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5539 | true); | |
4f771f10 PZ |
5540 | } |
5541 | ||
2dd24552 JB |
5542 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5543 | { | |
5544 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5545 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 5546 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5547 | |
681a8504 | 5548 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5549 | return; |
5550 | ||
2dd24552 | 5551 | /* |
c0b03411 DV |
5552 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5553 | * according to register description and PRM. | |
2dd24552 | 5554 | */ |
c0b03411 DV |
5555 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5556 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5557 | |
b074cec8 JB |
5558 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5559 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5560 | |
5561 | /* Border color in case we don't scale up to the full screen. Black by | |
5562 | * default, change to something else for debugging. */ | |
5563 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5564 | } |
5565 | ||
79f255a0 | 5566 | enum intel_display_power_domain intel_port_to_power_domain(enum port port) |
d05410f9 DA |
5567 | { |
5568 | switch (port) { | |
5569 | case PORT_A: | |
6331a704 | 5570 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5571 | case PORT_B: |
6331a704 | 5572 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5573 | case PORT_C: |
6331a704 | 5574 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5575 | case PORT_D: |
6331a704 | 5576 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5577 | case PORT_E: |
6331a704 | 5578 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5579 | default: |
b9fec167 | 5580 | MISSING_CASE(port); |
d05410f9 DA |
5581 | return POWER_DOMAIN_PORT_OTHER; |
5582 | } | |
5583 | } | |
5584 | ||
d8fc70b7 ACO |
5585 | static u64 get_crtc_power_domains(struct drm_crtc *crtc, |
5586 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5587 | { |
319be8ae | 5588 | struct drm_device *dev = crtc->dev; |
37255d8d | 5589 | struct drm_i915_private *dev_priv = to_i915(dev); |
74bff5f9 | 5590 | struct drm_encoder *encoder; |
319be8ae ID |
5591 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5592 | enum pipe pipe = intel_crtc->pipe; | |
d8fc70b7 | 5593 | u64 mask; |
74bff5f9 | 5594 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 5595 | |
74bff5f9 | 5596 | if (!crtc_state->base.active) |
292b990e ML |
5597 | return 0; |
5598 | ||
77d22dca ID |
5599 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5600 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
5601 | if (crtc_state->pch_pfit.enabled || |
5602 | crtc_state->pch_pfit.force_thru) | |
d8fc70b7 | 5603 | mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
77d22dca | 5604 | |
74bff5f9 ML |
5605 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
5606 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5607 | ||
79f255a0 | 5608 | mask |= BIT_ULL(intel_encoder->power_domain); |
74bff5f9 | 5609 | } |
319be8ae | 5610 | |
37255d8d ML |
5611 | if (HAS_DDI(dev_priv) && crtc_state->has_audio) |
5612 | mask |= BIT(POWER_DOMAIN_AUDIO); | |
5613 | ||
15e7ec29 | 5614 | if (crtc_state->shared_dpll) |
d8fc70b7 | 5615 | mask |= BIT_ULL(POWER_DOMAIN_PLLS); |
15e7ec29 | 5616 | |
77d22dca ID |
5617 | return mask; |
5618 | } | |
5619 | ||
d2d15016 | 5620 | static u64 |
74bff5f9 ML |
5621 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, |
5622 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5623 | { |
fac5e23e | 5624 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
292b990e ML |
5625 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5626 | enum intel_display_power_domain domain; | |
d8fc70b7 | 5627 | u64 domains, new_domains, old_domains; |
77d22dca | 5628 | |
292b990e | 5629 | old_domains = intel_crtc->enabled_power_domains; |
74bff5f9 ML |
5630 | intel_crtc->enabled_power_domains = new_domains = |
5631 | get_crtc_power_domains(crtc, crtc_state); | |
77d22dca | 5632 | |
5a21b665 | 5633 | domains = new_domains & ~old_domains; |
292b990e ML |
5634 | |
5635 | for_each_power_domain(domain, domains) | |
5636 | intel_display_power_get(dev_priv, domain); | |
5637 | ||
5a21b665 | 5638 | return old_domains & ~new_domains; |
292b990e ML |
5639 | } |
5640 | ||
5641 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
d8fc70b7 | 5642 | u64 domains) |
292b990e ML |
5643 | { |
5644 | enum intel_display_power_domain domain; | |
5645 | ||
5646 | for_each_power_domain(domain, domains) | |
5647 | intel_display_power_put(dev_priv, domain); | |
5648 | } | |
77d22dca | 5649 | |
7ff89ca2 VS |
5650 | static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config, |
5651 | struct drm_atomic_state *old_state) | |
adafdc6f | 5652 | { |
7ff89ca2 VS |
5653 | struct drm_crtc *crtc = pipe_config->base.crtc; |
5654 | struct drm_device *dev = crtc->dev; | |
5655 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5656 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5657 | int pipe = intel_crtc->pipe; | |
adafdc6f | 5658 | |
7ff89ca2 VS |
5659 | if (WARN_ON(intel_crtc->active)) |
5660 | return; | |
adafdc6f | 5661 | |
7ff89ca2 VS |
5662 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
5663 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
b2045352 | 5664 | |
7ff89ca2 VS |
5665 | intel_set_pipe_timings(intel_crtc); |
5666 | intel_set_pipe_src_size(intel_crtc); | |
b2045352 | 5667 | |
7ff89ca2 VS |
5668 | if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { |
5669 | struct drm_i915_private *dev_priv = to_i915(dev); | |
560a7ae4 | 5670 | |
7ff89ca2 VS |
5671 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); |
5672 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
560a7ae4 DL |
5673 | } |
5674 | ||
7ff89ca2 | 5675 | i9xx_set_pipeconf(intel_crtc); |
560a7ae4 | 5676 | |
7ff89ca2 | 5677 | intel_crtc->active = true; |
92891e45 | 5678 | |
7ff89ca2 | 5679 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5f199dfa | 5680 | |
7ff89ca2 | 5681 | intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); |
5f199dfa | 5682 | |
7ff89ca2 VS |
5683 | if (IS_CHERRYVIEW(dev_priv)) { |
5684 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
5685 | chv_enable_pll(intel_crtc, intel_crtc->config); | |
5686 | } else { | |
5687 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
5688 | vlv_enable_pll(intel_crtc, intel_crtc->config); | |
5f199dfa VS |
5689 | } |
5690 | ||
7ff89ca2 | 5691 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
5f199dfa | 5692 | |
7ff89ca2 | 5693 | i9xx_pfit_enable(intel_crtc); |
89b3c3c7 | 5694 | |
7ff89ca2 | 5695 | intel_color_load_luts(&pipe_config->base); |
89b3c3c7 | 5696 | |
7ff89ca2 VS |
5697 | intel_update_watermarks(intel_crtc); |
5698 | intel_enable_pipe(intel_crtc); | |
5699 | ||
5700 | assert_vblank_disabled(crtc); | |
5701 | drm_crtc_vblank_on(crtc); | |
89b3c3c7 | 5702 | |
7ff89ca2 | 5703 | intel_encoders_enable(crtc, pipe_config, old_state); |
89b3c3c7 ACO |
5704 | } |
5705 | ||
7ff89ca2 | 5706 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
2b73001e | 5707 | { |
7ff89ca2 VS |
5708 | struct drm_device *dev = crtc->base.dev; |
5709 | struct drm_i915_private *dev_priv = to_i915(dev); | |
83d7c81f | 5710 | |
7ff89ca2 VS |
5711 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
5712 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
2b73001e VS |
5713 | } |
5714 | ||
7ff89ca2 VS |
5715 | static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config, |
5716 | struct drm_atomic_state *old_state) | |
2b73001e | 5717 | { |
7ff89ca2 VS |
5718 | struct drm_crtc *crtc = pipe_config->base.crtc; |
5719 | struct drm_device *dev = crtc->dev; | |
5720 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5721 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5722 | enum pipe pipe = intel_crtc->pipe; | |
2b73001e | 5723 | |
7ff89ca2 VS |
5724 | if (WARN_ON(intel_crtc->active)) |
5725 | return; | |
2b73001e | 5726 | |
7ff89ca2 | 5727 | i9xx_set_pll_dividers(intel_crtc); |
2b73001e | 5728 | |
7ff89ca2 VS |
5729 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
5730 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
83d7c81f | 5731 | |
7ff89ca2 VS |
5732 | intel_set_pipe_timings(intel_crtc); |
5733 | intel_set_pipe_src_size(intel_crtc); | |
2b73001e | 5734 | |
7ff89ca2 | 5735 | i9xx_set_pipeconf(intel_crtc); |
f8437dd1 | 5736 | |
7ff89ca2 | 5737 | intel_crtc->active = true; |
5f199dfa | 5738 | |
7ff89ca2 VS |
5739 | if (!IS_GEN2(dev_priv)) |
5740 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5f199dfa | 5741 | |
7ff89ca2 | 5742 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
f8437dd1 | 5743 | |
7ff89ca2 | 5744 | i9xx_enable_pll(intel_crtc); |
f8437dd1 | 5745 | |
7ff89ca2 | 5746 | i9xx_pfit_enable(intel_crtc); |
f8437dd1 | 5747 | |
7ff89ca2 | 5748 | intel_color_load_luts(&pipe_config->base); |
f8437dd1 | 5749 | |
7ff89ca2 VS |
5750 | intel_update_watermarks(intel_crtc); |
5751 | intel_enable_pipe(intel_crtc); | |
f8437dd1 | 5752 | |
7ff89ca2 VS |
5753 | assert_vblank_disabled(crtc); |
5754 | drm_crtc_vblank_on(crtc); | |
f8437dd1 | 5755 | |
7ff89ca2 VS |
5756 | intel_encoders_enable(crtc, pipe_config, old_state); |
5757 | } | |
f8437dd1 | 5758 | |
7ff89ca2 VS |
5759 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
5760 | { | |
5761 | struct drm_device *dev = crtc->base.dev; | |
5762 | struct drm_i915_private *dev_priv = to_i915(dev); | |
f8437dd1 | 5763 | |
7ff89ca2 | 5764 | if (!crtc->config->gmch_pfit.control) |
f8437dd1 | 5765 | return; |
f8437dd1 | 5766 | |
7ff89ca2 VS |
5767 | assert_pipe_disabled(dev_priv, crtc->pipe); |
5768 | ||
5769 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", | |
5770 | I915_READ(PFIT_CONTROL)); | |
5771 | I915_WRITE(PFIT_CONTROL, 0); | |
f8437dd1 VK |
5772 | } |
5773 | ||
7ff89ca2 VS |
5774 | static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5775 | struct drm_atomic_state *old_state) | |
f8437dd1 | 5776 | { |
7ff89ca2 VS |
5777 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
5778 | struct drm_device *dev = crtc->dev; | |
5779 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5780 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5781 | int pipe = intel_crtc->pipe; | |
d66a2194 | 5782 | |
d66a2194 | 5783 | /* |
7ff89ca2 VS |
5784 | * On gen2 planes are double buffered but the pipe isn't, so we must |
5785 | * wait for planes to fully turn off before disabling the pipe. | |
d66a2194 | 5786 | */ |
7ff89ca2 VS |
5787 | if (IS_GEN2(dev_priv)) |
5788 | intel_wait_for_vblank(dev_priv, pipe); | |
d66a2194 | 5789 | |
7ff89ca2 | 5790 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
d66a2194 | 5791 | |
7ff89ca2 VS |
5792 | drm_crtc_vblank_off(crtc); |
5793 | assert_vblank_disabled(crtc); | |
d66a2194 | 5794 | |
7ff89ca2 | 5795 | intel_disable_pipe(intel_crtc); |
d66a2194 | 5796 | |
7ff89ca2 | 5797 | i9xx_pfit_disable(intel_crtc); |
89b3c3c7 | 5798 | |
7ff89ca2 | 5799 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
d66a2194 | 5800 | |
7ff89ca2 VS |
5801 | if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) { |
5802 | if (IS_CHERRYVIEW(dev_priv)) | |
5803 | chv_disable_pll(dev_priv, pipe); | |
5804 | else if (IS_VALLEYVIEW(dev_priv)) | |
5805 | vlv_disable_pll(dev_priv, pipe); | |
5806 | else | |
5807 | i9xx_disable_pll(intel_crtc); | |
5808 | } | |
c2e001ef | 5809 | |
7ff89ca2 | 5810 | intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state); |
89b3c3c7 | 5811 | |
7ff89ca2 VS |
5812 | if (!IS_GEN2(dev_priv)) |
5813 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
f8437dd1 VK |
5814 | } |
5815 | ||
7ff89ca2 | 5816 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
f8437dd1 | 5817 | { |
7ff89ca2 VS |
5818 | struct intel_encoder *encoder; |
5819 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5820 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
5821 | enum intel_display_power_domain domain; | |
d2d15016 | 5822 | u64 domains; |
7ff89ca2 VS |
5823 | struct drm_atomic_state *state; |
5824 | struct intel_crtc_state *crtc_state; | |
5825 | int ret; | |
f8437dd1 | 5826 | |
7ff89ca2 VS |
5827 | if (!intel_crtc->active) |
5828 | return; | |
a8ca4934 | 5829 | |
7ff89ca2 VS |
5830 | if (crtc->primary->state->visible) { |
5831 | WARN_ON(intel_crtc->flip_work); | |
5d96d8af | 5832 | |
7ff89ca2 | 5833 | intel_pre_disable_primary_noatomic(crtc); |
709e05c3 | 5834 | |
7ff89ca2 VS |
5835 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); |
5836 | crtc->primary->state->visible = false; | |
5837 | } | |
5d96d8af | 5838 | |
7ff89ca2 VS |
5839 | state = drm_atomic_state_alloc(crtc->dev); |
5840 | if (!state) { | |
5841 | DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory", | |
5842 | crtc->base.id, crtc->name); | |
1c3f7700 | 5843 | return; |
7ff89ca2 | 5844 | } |
9f7eb31a | 5845 | |
7ff89ca2 | 5846 | state->acquire_ctx = crtc->dev->mode_config.acquire_ctx; |
ea61791e | 5847 | |
7ff89ca2 VS |
5848 | /* Everything's already locked, -EDEADLK can't happen. */ |
5849 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); | |
5850 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
9f7eb31a | 5851 | |
7ff89ca2 | 5852 | WARN_ON(IS_ERR(crtc_state) || ret); |
5d96d8af | 5853 | |
7ff89ca2 | 5854 | dev_priv->display.crtc_disable(crtc_state, state); |
4a806558 | 5855 | |
0853695c | 5856 | drm_atomic_state_put(state); |
842e0307 | 5857 | |
78108b7c VS |
5858 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", |
5859 | crtc->base.id, crtc->name); | |
842e0307 ML |
5860 | |
5861 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0); | |
5862 | crtc->state->active = false; | |
37d9078b | 5863 | intel_crtc->active = false; |
842e0307 ML |
5864 | crtc->enabled = false; |
5865 | crtc->state->connector_mask = 0; | |
5866 | crtc->state->encoder_mask = 0; | |
5867 | ||
5868 | for_each_encoder_on_crtc(crtc->dev, crtc, encoder) | |
5869 | encoder->base.crtc = NULL; | |
5870 | ||
58f9c0bc | 5871 | intel_fbc_disable(intel_crtc); |
432081bc | 5872 | intel_update_watermarks(intel_crtc); |
1f7457b1 | 5873 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
5874 | |
5875 | domains = intel_crtc->enabled_power_domains; | |
5876 | for_each_power_domain(domain, domains) | |
5877 | intel_display_power_put(dev_priv, domain); | |
5878 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
5879 | |
5880 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
5881 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
5882 | } |
5883 | ||
6b72d486 ML |
5884 | /* |
5885 | * turn all crtc's off, but do not adjust state | |
5886 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
5887 | */ | |
70e0bd74 | 5888 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 5889 | { |
e2c8b870 | 5890 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 5891 | struct drm_atomic_state *state; |
e2c8b870 | 5892 | int ret; |
70e0bd74 | 5893 | |
e2c8b870 ML |
5894 | state = drm_atomic_helper_suspend(dev); |
5895 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
5896 | if (ret) |
5897 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
5898 | else |
5899 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 5900 | return ret; |
ee7b9f93 JB |
5901 | } |
5902 | ||
ea5b213a | 5903 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 5904 | { |
4ef69c7a | 5905 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 5906 | |
ea5b213a CW |
5907 | drm_encoder_cleanup(encoder); |
5908 | kfree(intel_encoder); | |
7e7d76c3 JB |
5909 | } |
5910 | ||
0a91ca29 DV |
5911 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
5912 | * internal consistency). */ | |
5a21b665 | 5913 | static void intel_connector_verify_state(struct intel_connector *connector) |
79e53945 | 5914 | { |
5a21b665 | 5915 | struct drm_crtc *crtc = connector->base.state->crtc; |
35dd3c64 ML |
5916 | |
5917 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
5918 | connector->base.base.id, | |
5919 | connector->base.name); | |
5920 | ||
0a91ca29 | 5921 | if (connector->get_hw_state(connector)) { |
e85376cb | 5922 | struct intel_encoder *encoder = connector->encoder; |
5a21b665 | 5923 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 5924 | |
35dd3c64 ML |
5925 | I915_STATE_WARN(!crtc, |
5926 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 5927 | |
35dd3c64 ML |
5928 | if (!crtc) |
5929 | return; | |
5930 | ||
5931 | I915_STATE_WARN(!crtc->state->active, | |
5932 | "connector is active, but attached crtc isn't\n"); | |
5933 | ||
e85376cb | 5934 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
5935 | return; |
5936 | ||
e85376cb | 5937 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
5938 | "atomic encoder doesn't match attached encoder\n"); |
5939 | ||
e85376cb | 5940 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
5941 | "attached encoder crtc differs from connector crtc\n"); |
5942 | } else { | |
4d688a2a ML |
5943 | I915_STATE_WARN(crtc && crtc->state->active, |
5944 | "attached crtc is active, but connector isn't\n"); | |
5a21b665 | 5945 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
35dd3c64 | 5946 | "best encoder set without crtc!\n"); |
0a91ca29 | 5947 | } |
79e53945 JB |
5948 | } |
5949 | ||
08d9bc92 ACO |
5950 | int intel_connector_init(struct intel_connector *connector) |
5951 | { | |
5350a031 | 5952 | drm_atomic_helper_connector_reset(&connector->base); |
08d9bc92 | 5953 | |
5350a031 | 5954 | if (!connector->base.state) |
08d9bc92 ACO |
5955 | return -ENOMEM; |
5956 | ||
08d9bc92 ACO |
5957 | return 0; |
5958 | } | |
5959 | ||
5960 | struct intel_connector *intel_connector_alloc(void) | |
5961 | { | |
5962 | struct intel_connector *connector; | |
5963 | ||
5964 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
5965 | if (!connector) | |
5966 | return NULL; | |
5967 | ||
5968 | if (intel_connector_init(connector) < 0) { | |
5969 | kfree(connector); | |
5970 | return NULL; | |
5971 | } | |
5972 | ||
5973 | return connector; | |
5974 | } | |
5975 | ||
f0947c37 DV |
5976 | /* Simple connector->get_hw_state implementation for encoders that support only |
5977 | * one connector and no cloning and hence the encoder state determines the state | |
5978 | * of the connector. */ | |
5979 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 5980 | { |
24929352 | 5981 | enum pipe pipe = 0; |
f0947c37 | 5982 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 5983 | |
f0947c37 | 5984 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
5985 | } |
5986 | ||
6d293983 | 5987 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 5988 | { |
6d293983 ACO |
5989 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
5990 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
5991 | |
5992 | return 0; | |
5993 | } | |
5994 | ||
6d293983 | 5995 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 5996 | struct intel_crtc_state *pipe_config) |
1857e1da | 5997 | { |
8652744b | 5998 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d293983 ACO |
5999 | struct drm_atomic_state *state = pipe_config->base.state; |
6000 | struct intel_crtc *other_crtc; | |
6001 | struct intel_crtc_state *other_crtc_state; | |
6002 | ||
1857e1da DV |
6003 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6004 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6005 | if (pipe_config->fdi_lanes > 4) { | |
6006 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6007 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6008 | return -EINVAL; |
1857e1da DV |
6009 | } |
6010 | ||
8652744b | 6011 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
1857e1da DV |
6012 | if (pipe_config->fdi_lanes > 2) { |
6013 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6014 | pipe_config->fdi_lanes); | |
6d293983 | 6015 | return -EINVAL; |
1857e1da | 6016 | } else { |
6d293983 | 6017 | return 0; |
1857e1da DV |
6018 | } |
6019 | } | |
6020 | ||
b7f05d4a | 6021 | if (INTEL_INFO(dev_priv)->num_pipes == 2) |
6d293983 | 6022 | return 0; |
1857e1da DV |
6023 | |
6024 | /* Ivybridge 3 pipe is really complicated */ | |
6025 | switch (pipe) { | |
6026 | case PIPE_A: | |
6d293983 | 6027 | return 0; |
1857e1da | 6028 | case PIPE_B: |
6d293983 ACO |
6029 | if (pipe_config->fdi_lanes <= 2) |
6030 | return 0; | |
6031 | ||
b91eb5cc | 6032 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C); |
6d293983 ACO |
6033 | other_crtc_state = |
6034 | intel_atomic_get_crtc_state(state, other_crtc); | |
6035 | if (IS_ERR(other_crtc_state)) | |
6036 | return PTR_ERR(other_crtc_state); | |
6037 | ||
6038 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6039 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6040 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6041 | return -EINVAL; |
1857e1da | 6042 | } |
6d293983 | 6043 | return 0; |
1857e1da | 6044 | case PIPE_C: |
251cc67c VS |
6045 | if (pipe_config->fdi_lanes > 2) { |
6046 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6047 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6048 | return -EINVAL; |
251cc67c | 6049 | } |
6d293983 | 6050 | |
b91eb5cc | 6051 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B); |
6d293983 ACO |
6052 | other_crtc_state = |
6053 | intel_atomic_get_crtc_state(state, other_crtc); | |
6054 | if (IS_ERR(other_crtc_state)) | |
6055 | return PTR_ERR(other_crtc_state); | |
6056 | ||
6057 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6058 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6059 | return -EINVAL; |
1857e1da | 6060 | } |
6d293983 | 6061 | return 0; |
1857e1da DV |
6062 | default: |
6063 | BUG(); | |
6064 | } | |
6065 | } | |
6066 | ||
e29c22c0 DV |
6067 | #define RETRY 1 |
6068 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6069 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6070 | { |
1857e1da | 6071 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6072 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6073 | int lane, link_bw, fdi_dotclock, ret; |
6074 | bool needs_recompute = false; | |
877d48d5 | 6075 | |
e29c22c0 | 6076 | retry: |
877d48d5 DV |
6077 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6078 | * each output octet as 10 bits. The actual frequency | |
6079 | * is stored as a divider into a 100MHz clock, and the | |
6080 | * mode pixel clock is stored in units of 1KHz. | |
6081 | * Hence the bw of each lane in terms of the mode signal | |
6082 | * is: | |
6083 | */ | |
21a727b3 | 6084 | link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); |
877d48d5 | 6085 | |
241bfc38 | 6086 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6087 | |
2bd89a07 | 6088 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6089 | pipe_config->pipe_bpp); |
6090 | ||
6091 | pipe_config->fdi_lanes = lane; | |
6092 | ||
2bd89a07 | 6093 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6094 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6095 | |
e3b247da | 6096 | ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
6d293983 | 6097 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
e29c22c0 | 6098 | pipe_config->pipe_bpp -= 2*3; |
7ff89ca2 VS |
6099 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", |
6100 | pipe_config->pipe_bpp); | |
6101 | needs_recompute = true; | |
6102 | pipe_config->bw_constrained = true; | |
257a7ffc | 6103 | |
7ff89ca2 | 6104 | goto retry; |
257a7ffc | 6105 | } |
79e53945 | 6106 | |
7ff89ca2 VS |
6107 | if (needs_recompute) |
6108 | return RETRY; | |
e70236a8 | 6109 | |
7ff89ca2 | 6110 | return ret; |
e70236a8 JB |
6111 | } |
6112 | ||
7ff89ca2 VS |
6113 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6114 | struct intel_crtc_state *pipe_config) | |
e70236a8 | 6115 | { |
7ff89ca2 VS |
6116 | if (pipe_config->pipe_bpp > 24) |
6117 | return false; | |
e70236a8 | 6118 | |
7ff89ca2 VS |
6119 | /* HSW can handle pixel rate up to cdclk? */ |
6120 | if (IS_HASWELL(dev_priv)) | |
6121 | return true; | |
1b1d2716 | 6122 | |
65cd2b3f | 6123 | /* |
7ff89ca2 VS |
6124 | * We compare against max which means we must take |
6125 | * the increased cdclk requirement into account when | |
6126 | * calculating the new cdclk. | |
6127 | * | |
6128 | * Should measure whether using a lower cdclk w/o IPS | |
e70236a8 | 6129 | */ |
7ff89ca2 VS |
6130 | return pipe_config->pixel_rate <= |
6131 | dev_priv->max_cdclk_freq * 95 / 100; | |
e70236a8 | 6132 | } |
79e53945 | 6133 | |
7ff89ca2 VS |
6134 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
6135 | struct intel_crtc_state *pipe_config) | |
6136 | { | |
6137 | struct drm_device *dev = crtc->base.dev; | |
6138 | struct drm_i915_private *dev_priv = to_i915(dev); | |
34edce2f | 6139 | |
7ff89ca2 VS |
6140 | pipe_config->ips_enabled = i915.enable_ips && |
6141 | hsw_crtc_supports_ips(crtc) && | |
6142 | pipe_config_supports_ips(dev_priv, pipe_config); | |
34edce2f VS |
6143 | } |
6144 | ||
7ff89ca2 | 6145 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
34edce2f | 6146 | { |
7ff89ca2 | 6147 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
34edce2f | 6148 | |
7ff89ca2 VS |
6149 | /* GDG double wide on either pipe, otherwise pipe A only */ |
6150 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6151 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
34edce2f VS |
6152 | } |
6153 | ||
ceb99320 VS |
6154 | static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) |
6155 | { | |
6156 | uint32_t pixel_rate; | |
6157 | ||
6158 | pixel_rate = pipe_config->base.adjusted_mode.crtc_clock; | |
6159 | ||
6160 | /* | |
6161 | * We only use IF-ID interlacing. If we ever use | |
6162 | * PF-ID we'll need to adjust the pixel_rate here. | |
6163 | */ | |
6164 | ||
6165 | if (pipe_config->pch_pfit.enabled) { | |
6166 | uint64_t pipe_w, pipe_h, pfit_w, pfit_h; | |
6167 | uint32_t pfit_size = pipe_config->pch_pfit.size; | |
6168 | ||
6169 | pipe_w = pipe_config->pipe_src_w; | |
6170 | pipe_h = pipe_config->pipe_src_h; | |
6171 | ||
6172 | pfit_w = (pfit_size >> 16) & 0xFFFF; | |
6173 | pfit_h = pfit_size & 0xFFFF; | |
6174 | if (pipe_w < pfit_w) | |
6175 | pipe_w = pfit_w; | |
6176 | if (pipe_h < pfit_h) | |
6177 | pipe_h = pfit_h; | |
6178 | ||
6179 | if (WARN_ON(!pfit_w || !pfit_h)) | |
6180 | return pixel_rate; | |
6181 | ||
6182 | pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, | |
6183 | pfit_w * pfit_h); | |
6184 | } | |
6185 | ||
6186 | return pixel_rate; | |
6187 | } | |
6188 | ||
7ff89ca2 | 6189 | static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) |
34edce2f | 6190 | { |
7ff89ca2 | 6191 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); |
34edce2f | 6192 | |
7ff89ca2 VS |
6193 | if (HAS_GMCH_DISPLAY(dev_priv)) |
6194 | /* FIXME calculate proper pipe pixel rate for GMCH pfit */ | |
6195 | crtc_state->pixel_rate = | |
6196 | crtc_state->base.adjusted_mode.crtc_clock; | |
6197 | else | |
6198 | crtc_state->pixel_rate = | |
6199 | ilk_pipe_pixel_rate(crtc_state); | |
6200 | } | |
34edce2f | 6201 | |
7ff89ca2 VS |
6202 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
6203 | struct intel_crtc_state *pipe_config) | |
6204 | { | |
6205 | struct drm_device *dev = crtc->base.dev; | |
6206 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6207 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; | |
6208 | int clock_limit = dev_priv->max_dotclk_freq; | |
34edce2f | 6209 | |
7ff89ca2 VS |
6210 | if (INTEL_GEN(dev_priv) < 4) { |
6211 | clock_limit = dev_priv->max_cdclk_freq * 9 / 10; | |
34edce2f | 6212 | |
7ff89ca2 VS |
6213 | /* |
6214 | * Enable double wide mode when the dot clock | |
6215 | * is > 90% of the (display) core speed. | |
6216 | */ | |
6217 | if (intel_crtc_supports_double_wide(crtc) && | |
6218 | adjusted_mode->crtc_clock > clock_limit) { | |
6219 | clock_limit = dev_priv->max_dotclk_freq; | |
6220 | pipe_config->double_wide = true; | |
6221 | } | |
34edce2f VS |
6222 | } |
6223 | ||
7ff89ca2 VS |
6224 | if (adjusted_mode->crtc_clock > clock_limit) { |
6225 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6226 | adjusted_mode->crtc_clock, clock_limit, | |
6227 | yesno(pipe_config->double_wide)); | |
6228 | return -EINVAL; | |
6229 | } | |
34edce2f | 6230 | |
7ff89ca2 VS |
6231 | /* |
6232 | * Pipe horizontal size must be even in: | |
6233 | * - DVO ganged mode | |
6234 | * - LVDS dual channel mode | |
6235 | * - Double wide pipe | |
6236 | */ | |
6237 | if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) && | |
6238 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) | |
6239 | pipe_config->pipe_src_w &= ~1; | |
34edce2f | 6240 | |
7ff89ca2 VS |
6241 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6242 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
6243 | */ | |
6244 | if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) && | |
6245 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) | |
6246 | return -EINVAL; | |
34edce2f | 6247 | |
7ff89ca2 | 6248 | intel_crtc_compute_pixel_rate(pipe_config); |
34edce2f | 6249 | |
7ff89ca2 VS |
6250 | if (HAS_IPS(dev_priv)) |
6251 | hsw_compute_ips_config(crtc, pipe_config); | |
34edce2f | 6252 | |
7ff89ca2 VS |
6253 | if (pipe_config->has_pch_encoder) |
6254 | return ironlake_fdi_compute_config(crtc, pipe_config); | |
34edce2f | 6255 | |
7ff89ca2 | 6256 | return 0; |
34edce2f VS |
6257 | } |
6258 | ||
2c07245f | 6259 | static void |
a65851af | 6260 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 6261 | { |
a65851af VS |
6262 | while (*num > DATA_LINK_M_N_MASK || |
6263 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
6264 | *num >>= 1; |
6265 | *den >>= 1; | |
6266 | } | |
6267 | } | |
6268 | ||
a65851af VS |
6269 | static void compute_m_n(unsigned int m, unsigned int n, |
6270 | uint32_t *ret_m, uint32_t *ret_n) | |
6271 | { | |
6272 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
6273 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
6274 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
6275 | } | |
6276 | ||
e69d0bc1 DV |
6277 | void |
6278 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
6279 | int pixel_clock, int link_clock, | |
6280 | struct intel_link_m_n *m_n) | |
2c07245f | 6281 | { |
e69d0bc1 | 6282 | m_n->tu = 64; |
a65851af VS |
6283 | |
6284 | compute_m_n(bits_per_pixel * pixel_clock, | |
6285 | link_clock * nlanes * 8, | |
6286 | &m_n->gmch_m, &m_n->gmch_n); | |
6287 | ||
6288 | compute_m_n(pixel_clock, link_clock, | |
6289 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
6290 | } |
6291 | ||
a7615030 CW |
6292 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
6293 | { | |
d330a953 JN |
6294 | if (i915.panel_use_ssc >= 0) |
6295 | return i915.panel_use_ssc != 0; | |
41aa3448 | 6296 | return dev_priv->vbt.lvds_use_ssc |
435793df | 6297 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
6298 | } |
6299 | ||
7429e9d4 | 6300 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 6301 | { |
7df00d7a | 6302 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 6303 | } |
f47709a9 | 6304 | |
7429e9d4 DV |
6305 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
6306 | { | |
6307 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
6308 | } |
6309 | ||
f47709a9 | 6310 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 6311 | struct intel_crtc_state *crtc_state, |
9e2c8475 | 6312 | struct dpll *reduced_clock) |
a7516a05 | 6313 | { |
9b1e14f4 | 6314 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
a7516a05 JB |
6315 | u32 fp, fp2 = 0; |
6316 | ||
9b1e14f4 | 6317 | if (IS_PINEVIEW(dev_priv)) { |
190f68c5 | 6318 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6319 | if (reduced_clock) |
7429e9d4 | 6320 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 6321 | } else { |
190f68c5 | 6322 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6323 | if (reduced_clock) |
7429e9d4 | 6324 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
6325 | } |
6326 | ||
190f68c5 | 6327 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 6328 | |
f47709a9 | 6329 | crtc->lowfreq_avail = false; |
2d84d2b3 | 6330 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 6331 | reduced_clock) { |
190f68c5 | 6332 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 6333 | crtc->lowfreq_avail = true; |
a7516a05 | 6334 | } else { |
190f68c5 | 6335 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
6336 | } |
6337 | } | |
6338 | ||
5e69f97f CML |
6339 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
6340 | pipe) | |
89b667f8 JB |
6341 | { |
6342 | u32 reg_val; | |
6343 | ||
6344 | /* | |
6345 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
6346 | * and set it to a reasonable value instead. | |
6347 | */ | |
ab3c759a | 6348 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
6349 | reg_val &= 0xffffff00; |
6350 | reg_val |= 0x00000030; | |
ab3c759a | 6351 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6352 | |
ab3c759a | 6353 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6354 | reg_val &= 0x8cffffff; |
6355 | reg_val = 0x8c000000; | |
ab3c759a | 6356 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 6357 | |
ab3c759a | 6358 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 6359 | reg_val &= 0xffffff00; |
ab3c759a | 6360 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6361 | |
ab3c759a | 6362 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6363 | reg_val &= 0x00ffffff; |
6364 | reg_val |= 0xb0000000; | |
ab3c759a | 6365 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
6366 | } |
6367 | ||
b551842d DV |
6368 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
6369 | struct intel_link_m_n *m_n) | |
6370 | { | |
6371 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6372 | struct drm_i915_private *dev_priv = to_i915(dev); |
b551842d DV |
6373 | int pipe = crtc->pipe; |
6374 | ||
e3b95f1e DV |
6375 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6376 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
6377 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
6378 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
6379 | } |
6380 | ||
6381 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
6382 | struct intel_link_m_n *m_n, |
6383 | struct intel_link_m_n *m2_n2) | |
b551842d | 6384 | { |
6315b5d3 | 6385 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
b551842d | 6386 | int pipe = crtc->pipe; |
6e3c9717 | 6387 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d | 6388 | |
6315b5d3 | 6389 | if (INTEL_GEN(dev_priv) >= 5) { |
b551842d DV |
6390 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6391 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
6392 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
6393 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
6394 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
6395 | * for gen < 8) and if DRRS is supported (to make sure the | |
6396 | * registers are not unnecessarily accessed). | |
6397 | */ | |
920a14b2 TU |
6398 | if (m2_n2 && (IS_CHERRYVIEW(dev_priv) || |
6399 | INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) { | |
f769cd24 VK |
6400 | I915_WRITE(PIPE_DATA_M2(transcoder), |
6401 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
6402 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
6403 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
6404 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
6405 | } | |
b551842d | 6406 | } else { |
e3b95f1e DV |
6407 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6408 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
6409 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
6410 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
6411 | } |
6412 | } | |
6413 | ||
fe3cd48d | 6414 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 6415 | { |
fe3cd48d R |
6416 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
6417 | ||
6418 | if (m_n == M1_N1) { | |
6419 | dp_m_n = &crtc->config->dp_m_n; | |
6420 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
6421 | } else if (m_n == M2_N2) { | |
6422 | ||
6423 | /* | |
6424 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
6425 | * needs to be programmed into M1_N1. | |
6426 | */ | |
6427 | dp_m_n = &crtc->config->dp_m2_n2; | |
6428 | } else { | |
6429 | DRM_ERROR("Unsupported divider value\n"); | |
6430 | return; | |
6431 | } | |
6432 | ||
6e3c9717 ACO |
6433 | if (crtc->config->has_pch_encoder) |
6434 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 6435 | else |
fe3cd48d | 6436 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
6437 | } |
6438 | ||
251ac862 DV |
6439 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
6440 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 | 6441 | { |
03ed5cbf | 6442 | pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | |
cd2d34d9 | 6443 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
6444 | if (crtc->pipe != PIPE_A) |
6445 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
bdd4b6a6 | 6446 | |
cd2d34d9 | 6447 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 6448 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
6449 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | |
6450 | DPLL_EXT_BUFFER_ENABLE_VLV; | |
6451 | ||
03ed5cbf VS |
6452 | pipe_config->dpll_hw_state.dpll_md = |
6453 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
6454 | } | |
bdd4b6a6 | 6455 | |
03ed5cbf VS |
6456 | static void chv_compute_dpll(struct intel_crtc *crtc, |
6457 | struct intel_crtc_state *pipe_config) | |
6458 | { | |
6459 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | | |
cd2d34d9 | 6460 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
6461 | if (crtc->pipe != PIPE_A) |
6462 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
6463 | ||
cd2d34d9 | 6464 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 6465 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
6466 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; |
6467 | ||
03ed5cbf VS |
6468 | pipe_config->dpll_hw_state.dpll_md = |
6469 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
bdd4b6a6 DV |
6470 | } |
6471 | ||
d288f65f | 6472 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6473 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 6474 | { |
f47709a9 | 6475 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6476 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 6477 | enum pipe pipe = crtc->pipe; |
bdd4b6a6 | 6478 | u32 mdiv; |
a0c4da24 | 6479 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 6480 | u32 coreclk, reg_val; |
a0c4da24 | 6481 | |
cd2d34d9 VS |
6482 | /* Enable Refclk */ |
6483 | I915_WRITE(DPLL(pipe), | |
6484 | pipe_config->dpll_hw_state.dpll & | |
6485 | ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); | |
6486 | ||
6487 | /* No need to actually set up the DPLL with DSI */ | |
6488 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
6489 | return; | |
6490 | ||
a580516d | 6491 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 6492 | |
d288f65f VS |
6493 | bestn = pipe_config->dpll.n; |
6494 | bestm1 = pipe_config->dpll.m1; | |
6495 | bestm2 = pipe_config->dpll.m2; | |
6496 | bestp1 = pipe_config->dpll.p1; | |
6497 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 6498 | |
89b667f8 JB |
6499 | /* See eDP HDMI DPIO driver vbios notes doc */ |
6500 | ||
6501 | /* PLL B needs special handling */ | |
bdd4b6a6 | 6502 | if (pipe == PIPE_B) |
5e69f97f | 6503 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
6504 | |
6505 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 6506 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
6507 | |
6508 | /* Disable target IRef on PLL */ | |
ab3c759a | 6509 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 6510 | reg_val &= 0x00ffffff; |
ab3c759a | 6511 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
6512 | |
6513 | /* Disable fast lock */ | |
ab3c759a | 6514 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
6515 | |
6516 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
6517 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
6518 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
6519 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 6520 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
6521 | |
6522 | /* | |
6523 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
6524 | * but we don't support that). | |
6525 | * Note: don't use the DAC post divider as it seems unstable. | |
6526 | */ | |
6527 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 6528 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6529 | |
a0c4da24 | 6530 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 6531 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6532 | |
89b667f8 | 6533 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 6534 | if (pipe_config->port_clock == 162000 || |
2d84d2b3 VS |
6535 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) || |
6536 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 6537 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 6538 | 0x009f0003); |
89b667f8 | 6539 | else |
ab3c759a | 6540 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
6541 | 0x00d0000f); |
6542 | ||
37a5650b | 6543 | if (intel_crtc_has_dp_encoder(pipe_config)) { |
89b667f8 | 6544 | /* Use SSC source */ |
bdd4b6a6 | 6545 | if (pipe == PIPE_A) |
ab3c759a | 6546 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6547 | 0x0df40000); |
6548 | else | |
ab3c759a | 6549 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6550 | 0x0df70000); |
6551 | } else { /* HDMI or VGA */ | |
6552 | /* Use bend source */ | |
bdd4b6a6 | 6553 | if (pipe == PIPE_A) |
ab3c759a | 6554 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6555 | 0x0df70000); |
6556 | else | |
ab3c759a | 6557 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6558 | 0x0df40000); |
6559 | } | |
a0c4da24 | 6560 | |
ab3c759a | 6561 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 6562 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
2210ce7f | 6563 | if (intel_crtc_has_dp_encoder(crtc->config)) |
89b667f8 | 6564 | coreclk |= 0x01000000; |
ab3c759a | 6565 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 6566 | |
ab3c759a | 6567 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 6568 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
6569 | } |
6570 | ||
d288f65f | 6571 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6572 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
6573 | { |
6574 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6575 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 6576 | enum pipe pipe = crtc->pipe; |
9d556c99 | 6577 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 6578 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 6579 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 6580 | u32 dpio_val; |
9cbe40c1 | 6581 | int vco; |
9d556c99 | 6582 | |
cd2d34d9 VS |
6583 | /* Enable Refclk and SSC */ |
6584 | I915_WRITE(DPLL(pipe), | |
6585 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
6586 | ||
6587 | /* No need to actually set up the DPLL with DSI */ | |
6588 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
6589 | return; | |
6590 | ||
d288f65f VS |
6591 | bestn = pipe_config->dpll.n; |
6592 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
6593 | bestm1 = pipe_config->dpll.m1; | |
6594 | bestm2 = pipe_config->dpll.m2 >> 22; | |
6595 | bestp1 = pipe_config->dpll.p1; | |
6596 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 6597 | vco = pipe_config->dpll.vco; |
a945ce7e | 6598 | dpio_val = 0; |
9cbe40c1 | 6599 | loopfilter = 0; |
9d556c99 | 6600 | |
a580516d | 6601 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 6602 | |
9d556c99 CML |
6603 | /* p1 and p2 divider */ |
6604 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
6605 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
6606 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
6607 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
6608 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
6609 | ||
6610 | /* Feedback post-divider - m2 */ | |
6611 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
6612 | ||
6613 | /* Feedback refclk divider - n and m1 */ | |
6614 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
6615 | DPIO_CHV_M1_DIV_BY_2 | | |
6616 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
6617 | ||
6618 | /* M2 fraction division */ | |
25a25dfc | 6619 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
6620 | |
6621 | /* M2 fraction division enable */ | |
a945ce7e VP |
6622 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
6623 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
6624 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
6625 | if (bestm2_frac) | |
6626 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
6627 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 6628 | |
de3a0fde VP |
6629 | /* Program digital lock detect threshold */ |
6630 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
6631 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
6632 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
6633 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
6634 | if (!bestm2_frac) | |
6635 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
6636 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
6637 | ||
9d556c99 | 6638 | /* Loop filter */ |
9cbe40c1 VP |
6639 | if (vco == 5400000) { |
6640 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6641 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
6642 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6643 | tribuf_calcntr = 0x9; | |
6644 | } else if (vco <= 6200000) { | |
6645 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6646 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
6647 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6648 | tribuf_calcntr = 0x9; | |
6649 | } else if (vco <= 6480000) { | |
6650 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6651 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6652 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6653 | tribuf_calcntr = 0x8; | |
6654 | } else { | |
6655 | /* Not supported. Apply the same limits as in the max case */ | |
6656 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6657 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6658 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6659 | tribuf_calcntr = 0; | |
6660 | } | |
9d556c99 CML |
6661 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
6662 | ||
968040b2 | 6663 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
6664 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
6665 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
6666 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
6667 | ||
9d556c99 CML |
6668 | /* AFC Recal */ |
6669 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
6670 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
6671 | DPIO_AFC_RECAL); | |
6672 | ||
a580516d | 6673 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
6674 | } |
6675 | ||
d288f65f VS |
6676 | /** |
6677 | * vlv_force_pll_on - forcibly enable just the PLL | |
6678 | * @dev_priv: i915 private structure | |
6679 | * @pipe: pipe PLL to enable | |
6680 | * @dpll: PLL configuration | |
6681 | * | |
6682 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
6683 | * in cases where we need the PLL enabled even when @pipe is not going to | |
6684 | * be enabled. | |
6685 | */ | |
30ad9814 | 6686 | int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, |
3f36b937 | 6687 | const struct dpll *dpll) |
d288f65f | 6688 | { |
b91eb5cc | 6689 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
3f36b937 TU |
6690 | struct intel_crtc_state *pipe_config; |
6691 | ||
6692 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
6693 | if (!pipe_config) | |
6694 | return -ENOMEM; | |
6695 | ||
6696 | pipe_config->base.crtc = &crtc->base; | |
6697 | pipe_config->pixel_multiplier = 1; | |
6698 | pipe_config->dpll = *dpll; | |
d288f65f | 6699 | |
30ad9814 | 6700 | if (IS_CHERRYVIEW(dev_priv)) { |
3f36b937 TU |
6701 | chv_compute_dpll(crtc, pipe_config); |
6702 | chv_prepare_pll(crtc, pipe_config); | |
6703 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 6704 | } else { |
3f36b937 TU |
6705 | vlv_compute_dpll(crtc, pipe_config); |
6706 | vlv_prepare_pll(crtc, pipe_config); | |
6707 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 6708 | } |
3f36b937 TU |
6709 | |
6710 | kfree(pipe_config); | |
6711 | ||
6712 | return 0; | |
d288f65f VS |
6713 | } |
6714 | ||
6715 | /** | |
6716 | * vlv_force_pll_off - forcibly disable just the PLL | |
6717 | * @dev_priv: i915 private structure | |
6718 | * @pipe: pipe PLL to disable | |
6719 | * | |
6720 | * Disable the PLL for @pipe. To be used in cases where we need | |
6721 | * the PLL enabled even when @pipe is not going to be enabled. | |
6722 | */ | |
30ad9814 | 6723 | void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe) |
d288f65f | 6724 | { |
30ad9814 VS |
6725 | if (IS_CHERRYVIEW(dev_priv)) |
6726 | chv_disable_pll(dev_priv, pipe); | |
d288f65f | 6727 | else |
30ad9814 | 6728 | vlv_disable_pll(dev_priv, pipe); |
d288f65f VS |
6729 | } |
6730 | ||
251ac862 DV |
6731 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
6732 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 6733 | struct dpll *reduced_clock) |
eb1cbe48 | 6734 | { |
9b1e14f4 | 6735 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
eb1cbe48 | 6736 | u32 dpll; |
190f68c5 | 6737 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 6738 | |
190f68c5 | 6739 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 6740 | |
eb1cbe48 DV |
6741 | dpll = DPLL_VGA_MODE_DIS; |
6742 | ||
2d84d2b3 | 6743 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
6744 | dpll |= DPLLB_MODE_LVDS; |
6745 | else | |
6746 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 6747 | |
73f67aa8 JN |
6748 | if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || |
6749 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { | |
190f68c5 | 6750 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 6751 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 6752 | } |
198a037f | 6753 | |
3d6e9ee0 VS |
6754 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
6755 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 6756 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 6757 | |
37a5650b | 6758 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 6759 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
6760 | |
6761 | /* compute bitmask from p1 value */ | |
9b1e14f4 | 6762 | if (IS_PINEVIEW(dev_priv)) |
eb1cbe48 DV |
6763 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
6764 | else { | |
6765 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
9beb5fea | 6766 | if (IS_G4X(dev_priv) && reduced_clock) |
eb1cbe48 DV |
6767 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
6768 | } | |
6769 | switch (clock->p2) { | |
6770 | case 5: | |
6771 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6772 | break; | |
6773 | case 7: | |
6774 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
6775 | break; | |
6776 | case 10: | |
6777 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
6778 | break; | |
6779 | case 14: | |
6780 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
6781 | break; | |
6782 | } | |
9b1e14f4 | 6783 | if (INTEL_GEN(dev_priv) >= 4) |
eb1cbe48 DV |
6784 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
6785 | ||
190f68c5 | 6786 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 6787 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
2d84d2b3 | 6788 | else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 6789 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
6790 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
6791 | else | |
6792 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6793 | ||
6794 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 6795 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 6796 | |
9b1e14f4 | 6797 | if (INTEL_GEN(dev_priv) >= 4) { |
190f68c5 | 6798 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 6799 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 6800 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
6801 | } |
6802 | } | |
6803 | ||
251ac862 DV |
6804 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
6805 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 6806 | struct dpll *reduced_clock) |
eb1cbe48 | 6807 | { |
f47709a9 | 6808 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6809 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb1cbe48 | 6810 | u32 dpll; |
190f68c5 | 6811 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 6812 | |
190f68c5 | 6813 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 6814 | |
eb1cbe48 DV |
6815 | dpll = DPLL_VGA_MODE_DIS; |
6816 | ||
2d84d2b3 | 6817 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
6818 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
6819 | } else { | |
6820 | if (clock->p1 == 2) | |
6821 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
6822 | else | |
6823 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
6824 | if (clock->p2 == 4) | |
6825 | dpll |= PLL_P2_DIVIDE_BY_4; | |
6826 | } | |
6827 | ||
50a0bc90 TU |
6828 | if (!IS_I830(dev_priv) && |
6829 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) | |
4a33e48d DV |
6830 | dpll |= DPLL_DVO_2X_MODE; |
6831 | ||
2d84d2b3 | 6832 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 6833 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
6834 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
6835 | else | |
6836 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6837 | ||
6838 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 6839 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
6840 | } |
6841 | ||
8a654f3b | 6842 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c | 6843 | { |
6315b5d3 | 6844 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
b0e77b9c | 6845 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 6846 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 6847 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
6848 | uint32_t crtc_vtotal, crtc_vblank_end; |
6849 | int vsyncshift = 0; | |
4d8a62ea DV |
6850 | |
6851 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
6852 | * the hw state checker will get angry at the mismatch. */ | |
6853 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
6854 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 6855 | |
609aeaca | 6856 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 6857 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
6858 | crtc_vtotal -= 1; |
6859 | crtc_vblank_end -= 1; | |
609aeaca | 6860 | |
2d84d2b3 | 6861 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
6862 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
6863 | else | |
6864 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
6865 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
6866 | if (vsyncshift < 0) |
6867 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
6868 | } |
6869 | ||
6315b5d3 | 6870 | if (INTEL_GEN(dev_priv) > 3) |
fe2b8f9d | 6871 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 6872 | |
fe2b8f9d | 6873 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
6874 | (adjusted_mode->crtc_hdisplay - 1) | |
6875 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 6876 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
6877 | (adjusted_mode->crtc_hblank_start - 1) | |
6878 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 6879 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
6880 | (adjusted_mode->crtc_hsync_start - 1) | |
6881 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
6882 | ||
fe2b8f9d | 6883 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 6884 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 6885 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 6886 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 6887 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 6888 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 6889 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
6890 | (adjusted_mode->crtc_vsync_start - 1) | |
6891 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
6892 | ||
b5e508d4 PZ |
6893 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
6894 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
6895 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
6896 | * bits. */ | |
772c2a51 | 6897 | if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && |
b5e508d4 PZ |
6898 | (pipe == PIPE_B || pipe == PIPE_C)) |
6899 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
6900 | ||
bc58be60 JN |
6901 | } |
6902 | ||
6903 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) | |
6904 | { | |
6905 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 6906 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 JN |
6907 | enum pipe pipe = intel_crtc->pipe; |
6908 | ||
b0e77b9c PZ |
6909 | /* pipesrc controls the size that is scaled from, which should |
6910 | * always be the user's requested size. | |
6911 | */ | |
6912 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
6913 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
6914 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
6915 | } |
6916 | ||
1bd1bd80 | 6917 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 6918 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
6919 | { |
6920 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6921 | struct drm_i915_private *dev_priv = to_i915(dev); |
1bd1bd80 DV |
6922 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
6923 | uint32_t tmp; | |
6924 | ||
6925 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
6926 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
6927 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6928 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
6929 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
6930 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6931 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
6932 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
6933 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
6934 | |
6935 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
6936 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
6937 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6938 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
6939 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
6940 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6941 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
6942 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
6943 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
6944 | |
6945 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
6946 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
6947 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
6948 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 | 6949 | } |
bc58be60 JN |
6950 | } |
6951 | ||
6952 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, | |
6953 | struct intel_crtc_state *pipe_config) | |
6954 | { | |
6955 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6956 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 | 6957 | u32 tmp; |
1bd1bd80 DV |
6958 | |
6959 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
6960 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
6961 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
6962 | ||
2d112de7 ACO |
6963 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
6964 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
6965 | } |
6966 | ||
f6a83288 | 6967 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 6968 | struct intel_crtc_state *pipe_config) |
babea61d | 6969 | { |
2d112de7 ACO |
6970 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
6971 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
6972 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
6973 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 6974 | |
2d112de7 ACO |
6975 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
6976 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
6977 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
6978 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 6979 | |
2d112de7 | 6980 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 6981 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 6982 | |
2d112de7 | 6983 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
cd13f5ab ML |
6984 | |
6985 | mode->hsync = drm_mode_hsync(mode); | |
6986 | mode->vrefresh = drm_mode_vrefresh(mode); | |
6987 | drm_mode_set_name(mode); | |
babea61d JB |
6988 | } |
6989 | ||
84b046f3 DV |
6990 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
6991 | { | |
6315b5d3 | 6992 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
84b046f3 DV |
6993 | uint32_t pipeconf; |
6994 | ||
9f11a9e4 | 6995 | pipeconf = 0; |
84b046f3 | 6996 | |
b6b5d049 VS |
6997 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
6998 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
6999 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7000 | |
6e3c9717 | 7001 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7002 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7003 | |
ff9ce46e | 7004 | /* only g4x and later have fancy bpc/dither controls */ |
9beb5fea TU |
7005 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
7006 | IS_CHERRYVIEW(dev_priv)) { | |
ff9ce46e | 7007 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7008 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7009 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7010 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7011 | |
6e3c9717 | 7012 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7013 | case 18: |
7014 | pipeconf |= PIPECONF_6BPC; | |
7015 | break; | |
7016 | case 24: | |
7017 | pipeconf |= PIPECONF_8BPC; | |
7018 | break; | |
7019 | case 30: | |
7020 | pipeconf |= PIPECONF_10BPC; | |
7021 | break; | |
7022 | default: | |
7023 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7024 | BUG(); | |
84b046f3 DV |
7025 | } |
7026 | } | |
7027 | ||
56b857a5 | 7028 | if (HAS_PIPE_CXSR(dev_priv)) { |
84b046f3 DV |
7029 | if (intel_crtc->lowfreq_avail) { |
7030 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7031 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7032 | } else { | |
7033 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7034 | } |
7035 | } | |
7036 | ||
6e3c9717 | 7037 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
6315b5d3 | 7038 | if (INTEL_GEN(dev_priv) < 4 || |
2d84d2b3 | 7039 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7040 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7041 | else | |
7042 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7043 | } else | |
84b046f3 DV |
7044 | pipeconf |= PIPECONF_PROGRESSIVE; |
7045 | ||
920a14b2 | 7046 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 7047 | intel_crtc->config->limited_color_range) |
9f11a9e4 | 7048 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7049 | |
84b046f3 DV |
7050 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7051 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7052 | } | |
7053 | ||
81c97f52 ACO |
7054 | static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, |
7055 | struct intel_crtc_state *crtc_state) | |
7056 | { | |
7057 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7058 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7059 | const struct intel_limit *limit; |
81c97f52 ACO |
7060 | int refclk = 48000; |
7061 | ||
7062 | memset(&crtc_state->dpll_hw_state, 0, | |
7063 | sizeof(crtc_state->dpll_hw_state)); | |
7064 | ||
2d84d2b3 | 7065 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
81c97f52 ACO |
7066 | if (intel_panel_use_ssc(dev_priv)) { |
7067 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7068 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7069 | } | |
7070 | ||
7071 | limit = &intel_limits_i8xx_lvds; | |
2d84d2b3 | 7072 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { |
81c97f52 ACO |
7073 | limit = &intel_limits_i8xx_dvo; |
7074 | } else { | |
7075 | limit = &intel_limits_i8xx_dac; | |
7076 | } | |
7077 | ||
7078 | if (!crtc_state->clock_set && | |
7079 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7080 | refclk, NULL, &crtc_state->dpll)) { | |
7081 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7082 | return -EINVAL; | |
7083 | } | |
7084 | ||
7085 | i8xx_compute_dpll(crtc, crtc_state, NULL); | |
7086 | ||
7087 | return 0; | |
7088 | } | |
7089 | ||
19ec6693 ACO |
7090 | static int g4x_crtc_compute_clock(struct intel_crtc *crtc, |
7091 | struct intel_crtc_state *crtc_state) | |
7092 | { | |
7093 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7094 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7095 | const struct intel_limit *limit; |
19ec6693 ACO |
7096 | int refclk = 96000; |
7097 | ||
7098 | memset(&crtc_state->dpll_hw_state, 0, | |
7099 | sizeof(crtc_state->dpll_hw_state)); | |
7100 | ||
2d84d2b3 | 7101 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
19ec6693 ACO |
7102 | if (intel_panel_use_ssc(dev_priv)) { |
7103 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7104 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7105 | } | |
7106 | ||
7107 | if (intel_is_dual_link_lvds(dev)) | |
7108 | limit = &intel_limits_g4x_dual_channel_lvds; | |
7109 | else | |
7110 | limit = &intel_limits_g4x_single_channel_lvds; | |
2d84d2b3 VS |
7111 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || |
7112 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
19ec6693 | 7113 | limit = &intel_limits_g4x_hdmi; |
2d84d2b3 | 7114 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
19ec6693 ACO |
7115 | limit = &intel_limits_g4x_sdvo; |
7116 | } else { | |
7117 | /* The option is for other outputs */ | |
7118 | limit = &intel_limits_i9xx_sdvo; | |
7119 | } | |
7120 | ||
7121 | if (!crtc_state->clock_set && | |
7122 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7123 | refclk, NULL, &crtc_state->dpll)) { | |
7124 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7125 | return -EINVAL; | |
7126 | } | |
7127 | ||
7128 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7129 | ||
7130 | return 0; | |
7131 | } | |
7132 | ||
70e8aa21 ACO |
7133 | static int pnv_crtc_compute_clock(struct intel_crtc *crtc, |
7134 | struct intel_crtc_state *crtc_state) | |
7135 | { | |
7136 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7137 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7138 | const struct intel_limit *limit; |
70e8aa21 ACO |
7139 | int refclk = 96000; |
7140 | ||
7141 | memset(&crtc_state->dpll_hw_state, 0, | |
7142 | sizeof(crtc_state->dpll_hw_state)); | |
7143 | ||
2d84d2b3 | 7144 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
7145 | if (intel_panel_use_ssc(dev_priv)) { |
7146 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7147 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7148 | } | |
7149 | ||
7150 | limit = &intel_limits_pineview_lvds; | |
7151 | } else { | |
7152 | limit = &intel_limits_pineview_sdvo; | |
7153 | } | |
7154 | ||
7155 | if (!crtc_state->clock_set && | |
7156 | !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7157 | refclk, NULL, &crtc_state->dpll)) { | |
7158 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7159 | return -EINVAL; | |
7160 | } | |
7161 | ||
7162 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7163 | ||
7164 | return 0; | |
7165 | } | |
7166 | ||
190f68c5 ACO |
7167 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7168 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7169 | { |
c7653199 | 7170 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7171 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7172 | const struct intel_limit *limit; |
81c97f52 | 7173 | int refclk = 96000; |
79e53945 | 7174 | |
dd3cd74a ACO |
7175 | memset(&crtc_state->dpll_hw_state, 0, |
7176 | sizeof(crtc_state->dpll_hw_state)); | |
7177 | ||
2d84d2b3 | 7178 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
7179 | if (intel_panel_use_ssc(dev_priv)) { |
7180 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7181 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7182 | } | |
43565a06 | 7183 | |
70e8aa21 ACO |
7184 | limit = &intel_limits_i9xx_lvds; |
7185 | } else { | |
7186 | limit = &intel_limits_i9xx_sdvo; | |
81c97f52 | 7187 | } |
79e53945 | 7188 | |
70e8aa21 ACO |
7189 | if (!crtc_state->clock_set && |
7190 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7191 | refclk, NULL, &crtc_state->dpll)) { | |
7192 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7193 | return -EINVAL; | |
f47709a9 | 7194 | } |
7026d4ac | 7195 | |
81c97f52 | 7196 | i9xx_compute_dpll(crtc, crtc_state, NULL); |
79e53945 | 7197 | |
c8f7a0db | 7198 | return 0; |
f564048e EA |
7199 | } |
7200 | ||
65b3d6a9 ACO |
7201 | static int chv_crtc_compute_clock(struct intel_crtc *crtc, |
7202 | struct intel_crtc_state *crtc_state) | |
7203 | { | |
7204 | int refclk = 100000; | |
1b6f4958 | 7205 | const struct intel_limit *limit = &intel_limits_chv; |
65b3d6a9 ACO |
7206 | |
7207 | memset(&crtc_state->dpll_hw_state, 0, | |
7208 | sizeof(crtc_state->dpll_hw_state)); | |
7209 | ||
65b3d6a9 ACO |
7210 | if (!crtc_state->clock_set && |
7211 | !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7212 | refclk, NULL, &crtc_state->dpll)) { | |
7213 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7214 | return -EINVAL; | |
7215 | } | |
7216 | ||
7217 | chv_compute_dpll(crtc, crtc_state); | |
7218 | ||
7219 | return 0; | |
7220 | } | |
7221 | ||
7222 | static int vlv_crtc_compute_clock(struct intel_crtc *crtc, | |
7223 | struct intel_crtc_state *crtc_state) | |
7224 | { | |
7225 | int refclk = 100000; | |
1b6f4958 | 7226 | const struct intel_limit *limit = &intel_limits_vlv; |
65b3d6a9 ACO |
7227 | |
7228 | memset(&crtc_state->dpll_hw_state, 0, | |
7229 | sizeof(crtc_state->dpll_hw_state)); | |
7230 | ||
65b3d6a9 ACO |
7231 | if (!crtc_state->clock_set && |
7232 | !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7233 | refclk, NULL, &crtc_state->dpll)) { | |
7234 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7235 | return -EINVAL; | |
7236 | } | |
7237 | ||
7238 | vlv_compute_dpll(crtc, crtc_state); | |
7239 | ||
7240 | return 0; | |
7241 | } | |
7242 | ||
2fa2fe9a | 7243 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7244 | struct intel_crtc_state *pipe_config) |
2fa2fe9a | 7245 | { |
6315b5d3 | 7246 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2fa2fe9a DV |
7247 | uint32_t tmp; |
7248 | ||
50a0bc90 TU |
7249 | if (INTEL_GEN(dev_priv) <= 3 && |
7250 | (IS_I830(dev_priv) || !IS_MOBILE(dev_priv))) | |
dc9e7dec VS |
7251 | return; |
7252 | ||
2fa2fe9a | 7253 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7254 | if (!(tmp & PFIT_ENABLE)) |
7255 | return; | |
2fa2fe9a | 7256 | |
06922821 | 7257 | /* Check whether the pfit is attached to our pipe. */ |
6315b5d3 | 7258 | if (INTEL_GEN(dev_priv) < 4) { |
2fa2fe9a DV |
7259 | if (crtc->pipe != PIPE_B) |
7260 | return; | |
2fa2fe9a DV |
7261 | } else { |
7262 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
7263 | return; | |
7264 | } | |
7265 | ||
06922821 | 7266 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a | 7267 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
2fa2fe9a DV |
7268 | } |
7269 | ||
acbec814 | 7270 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7271 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
7272 | { |
7273 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7274 | struct drm_i915_private *dev_priv = to_i915(dev); |
acbec814 | 7275 | int pipe = pipe_config->cpu_transcoder; |
9e2c8475 | 7276 | struct dpll clock; |
acbec814 | 7277 | u32 mdiv; |
662c6ecb | 7278 | int refclk = 100000; |
acbec814 | 7279 | |
b521973b VS |
7280 | /* In case of DSI, DPLL will not be used */ |
7281 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
f573de5a SK |
7282 | return; |
7283 | ||
a580516d | 7284 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 7285 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 7286 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
7287 | |
7288 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
7289 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
7290 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
7291 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
7292 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
7293 | ||
dccbea3b | 7294 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
7295 | } |
7296 | ||
5724dbd1 DL |
7297 | static void |
7298 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
7299 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
7300 | { |
7301 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7302 | struct drm_i915_private *dev_priv = to_i915(dev); |
1ad292b5 JB |
7303 | u32 val, base, offset; |
7304 | int pipe = crtc->pipe, plane = crtc->plane; | |
7305 | int fourcc, pixel_format; | |
6761dd31 | 7306 | unsigned int aligned_height; |
b113d5ee | 7307 | struct drm_framebuffer *fb; |
1b842c89 | 7308 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 7309 | |
42a7b088 DL |
7310 | val = I915_READ(DSPCNTR(plane)); |
7311 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
7312 | return; | |
7313 | ||
d9806c9f | 7314 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 7315 | if (!intel_fb) { |
1ad292b5 JB |
7316 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7317 | return; | |
7318 | } | |
7319 | ||
1b842c89 DL |
7320 | fb = &intel_fb->base; |
7321 | ||
d2e9f5fc VS |
7322 | fb->dev = dev; |
7323 | ||
6315b5d3 | 7324 | if (INTEL_GEN(dev_priv) >= 4) { |
18c5247e | 7325 | if (val & DISPPLANE_TILED) { |
49af449b | 7326 | plane_config->tiling = I915_TILING_X; |
bae781b2 | 7327 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
18c5247e DV |
7328 | } |
7329 | } | |
1ad292b5 JB |
7330 | |
7331 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 7332 | fourcc = i9xx_format_to_fourcc(pixel_format); |
2f3f4763 | 7333 | fb->format = drm_format_info(fourcc); |
1ad292b5 | 7334 | |
6315b5d3 | 7335 | if (INTEL_GEN(dev_priv) >= 4) { |
49af449b | 7336 | if (plane_config->tiling) |
1ad292b5 JB |
7337 | offset = I915_READ(DSPTILEOFF(plane)); |
7338 | else | |
7339 | offset = I915_READ(DSPLINOFF(plane)); | |
7340 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7341 | } else { | |
7342 | base = I915_READ(DSPADDR(plane)); | |
7343 | } | |
7344 | plane_config->base = base; | |
7345 | ||
7346 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
7347 | fb->width = ((val >> 16) & 0xfff) + 1; |
7348 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
7349 | |
7350 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 7351 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 7352 | |
24dbf51a CW |
7353 | aligned_height = intel_fb_align_height(dev_priv, |
7354 | fb->height, | |
438b74a5 | 7355 | fb->format->format, |
bae781b2 | 7356 | fb->modifier); |
1ad292b5 | 7357 | |
f37b5c2b | 7358 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 7359 | |
2844a921 DL |
7360 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
7361 | pipe_name(pipe), plane, fb->width, fb->height, | |
272725c7 | 7362 | fb->format->cpp[0] * 8, base, fb->pitches[0], |
2844a921 | 7363 | plane_config->size); |
1ad292b5 | 7364 | |
2d14030b | 7365 | plane_config->fb = intel_fb; |
1ad292b5 JB |
7366 | } |
7367 | ||
70b23a98 | 7368 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7369 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
7370 | { |
7371 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7372 | struct drm_i915_private *dev_priv = to_i915(dev); |
70b23a98 VS |
7373 | int pipe = pipe_config->cpu_transcoder; |
7374 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9e2c8475 | 7375 | struct dpll clock; |
0d7b6b11 | 7376 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
7377 | int refclk = 100000; |
7378 | ||
b521973b VS |
7379 | /* In case of DSI, DPLL will not be used */ |
7380 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7381 | return; | |
7382 | ||
a580516d | 7383 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
7384 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
7385 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
7386 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
7387 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 7388 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 7389 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
7390 | |
7391 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
7392 | clock.m2 = (pll_dw0 & 0xff) << 22; |
7393 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
7394 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
7395 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
7396 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
7397 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
7398 | ||
dccbea3b | 7399 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
7400 | } |
7401 | ||
0e8ffe1b | 7402 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 7403 | struct intel_crtc_state *pipe_config) |
0e8ffe1b | 7404 | { |
6315b5d3 | 7405 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1729050e | 7406 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 7407 | uint32_t tmp; |
1729050e | 7408 | bool ret; |
0e8ffe1b | 7409 | |
1729050e ID |
7410 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
7411 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 ID |
7412 | return false; |
7413 | ||
e143a21c | 7414 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 7415 | pipe_config->shared_dpll = NULL; |
eccb140b | 7416 | |
1729050e ID |
7417 | ret = false; |
7418 | ||
0e8ffe1b DV |
7419 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7420 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 7421 | goto out; |
0e8ffe1b | 7422 | |
9beb5fea TU |
7423 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
7424 | IS_CHERRYVIEW(dev_priv)) { | |
42571aef VS |
7425 | switch (tmp & PIPECONF_BPC_MASK) { |
7426 | case PIPECONF_6BPC: | |
7427 | pipe_config->pipe_bpp = 18; | |
7428 | break; | |
7429 | case PIPECONF_8BPC: | |
7430 | pipe_config->pipe_bpp = 24; | |
7431 | break; | |
7432 | case PIPECONF_10BPC: | |
7433 | pipe_config->pipe_bpp = 30; | |
7434 | break; | |
7435 | default: | |
7436 | break; | |
7437 | } | |
7438 | } | |
7439 | ||
920a14b2 | 7440 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 7441 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
b5a9fa09 DV |
7442 | pipe_config->limited_color_range = true; |
7443 | ||
6315b5d3 | 7444 | if (INTEL_GEN(dev_priv) < 4) |
282740f7 VS |
7445 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; |
7446 | ||
1bd1bd80 | 7447 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 7448 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 7449 | |
2fa2fe9a DV |
7450 | i9xx_get_pfit_config(crtc, pipe_config); |
7451 | ||
6315b5d3 | 7452 | if (INTEL_GEN(dev_priv) >= 4) { |
c231775c | 7453 | /* No way to read it out on pipes B and C */ |
920a14b2 | 7454 | if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) |
c231775c VS |
7455 | tmp = dev_priv->chv_dpll_md[crtc->pipe]; |
7456 | else | |
7457 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6c49f241 DV |
7458 | pipe_config->pixel_multiplier = |
7459 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
7460 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 7461 | pipe_config->dpll_hw_state.dpll_md = tmp; |
50a0bc90 | 7462 | } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || |
73f67aa8 | 7463 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { |
6c49f241 DV |
7464 | tmp = I915_READ(DPLL(crtc->pipe)); |
7465 | pipe_config->pixel_multiplier = | |
7466 | ((tmp & SDVO_MULTIPLIER_MASK) | |
7467 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
7468 | } else { | |
7469 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
7470 | * port and will be fixed up in the encoder->get_config | |
7471 | * function. */ | |
7472 | pipe_config->pixel_multiplier = 1; | |
7473 | } | |
8bcc2795 | 7474 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
920a14b2 | 7475 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
1c4e0274 VS |
7476 | /* |
7477 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
7478 | * on 830. Filter it out here so that we don't | |
7479 | * report errors due to that. | |
7480 | */ | |
50a0bc90 | 7481 | if (IS_I830(dev_priv)) |
1c4e0274 VS |
7482 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; |
7483 | ||
8bcc2795 DV |
7484 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
7485 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
7486 | } else { |
7487 | /* Mask out read-only status bits. */ | |
7488 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
7489 | DPLL_PORTC_READY_MASK | | |
7490 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 7491 | } |
6c49f241 | 7492 | |
920a14b2 | 7493 | if (IS_CHERRYVIEW(dev_priv)) |
70b23a98 | 7494 | chv_crtc_clock_get(crtc, pipe_config); |
11a914c2 | 7495 | else if (IS_VALLEYVIEW(dev_priv)) |
acbec814 JB |
7496 | vlv_crtc_clock_get(crtc, pipe_config); |
7497 | else | |
7498 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 7499 | |
0f64614d VS |
7500 | /* |
7501 | * Normally the dotclock is filled in by the encoder .get_config() | |
7502 | * but in case the pipe is enabled w/o any ports we need a sane | |
7503 | * default. | |
7504 | */ | |
7505 | pipe_config->base.adjusted_mode.crtc_clock = | |
7506 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
7507 | ||
1729050e ID |
7508 | ret = true; |
7509 | ||
7510 | out: | |
7511 | intel_display_power_put(dev_priv, power_domain); | |
7512 | ||
7513 | return ret; | |
0e8ffe1b DV |
7514 | } |
7515 | ||
c39055b0 | 7516 | static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv) |
13d83a67 | 7517 | { |
13d83a67 | 7518 | struct intel_encoder *encoder; |
1c1a24d2 | 7519 | int i; |
74cfd7ac | 7520 | u32 val, final; |
13d83a67 | 7521 | bool has_lvds = false; |
199e5d79 | 7522 | bool has_cpu_edp = false; |
199e5d79 | 7523 | bool has_panel = false; |
99eb6a01 KP |
7524 | bool has_ck505 = false; |
7525 | bool can_ssc = false; | |
1c1a24d2 | 7526 | bool using_ssc_source = false; |
13d83a67 JB |
7527 | |
7528 | /* We need to take the global config into account */ | |
c39055b0 | 7529 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
199e5d79 KP |
7530 | switch (encoder->type) { |
7531 | case INTEL_OUTPUT_LVDS: | |
7532 | has_panel = true; | |
7533 | has_lvds = true; | |
7534 | break; | |
7535 | case INTEL_OUTPUT_EDP: | |
7536 | has_panel = true; | |
2de6905f | 7537 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
7538 | has_cpu_edp = true; |
7539 | break; | |
6847d71b PZ |
7540 | default: |
7541 | break; | |
13d83a67 JB |
7542 | } |
7543 | } | |
7544 | ||
6e266956 | 7545 | if (HAS_PCH_IBX(dev_priv)) { |
41aa3448 | 7546 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
7547 | can_ssc = has_ck505; |
7548 | } else { | |
7549 | has_ck505 = false; | |
7550 | can_ssc = true; | |
7551 | } | |
7552 | ||
1c1a24d2 L |
7553 | /* Check if any DPLLs are using the SSC source */ |
7554 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
7555 | u32 temp = I915_READ(PCH_DPLL(i)); | |
7556 | ||
7557 | if (!(temp & DPLL_VCO_ENABLE)) | |
7558 | continue; | |
7559 | ||
7560 | if ((temp & PLL_REF_INPUT_MASK) == | |
7561 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
7562 | using_ssc_source = true; | |
7563 | break; | |
7564 | } | |
7565 | } | |
7566 | ||
7567 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n", | |
7568 | has_panel, has_lvds, has_ck505, using_ssc_source); | |
13d83a67 JB |
7569 | |
7570 | /* Ironlake: try to setup display ref clock before DPLL | |
7571 | * enabling. This is only under driver's control after | |
7572 | * PCH B stepping, previous chipset stepping should be | |
7573 | * ignoring this setting. | |
7574 | */ | |
74cfd7ac CW |
7575 | val = I915_READ(PCH_DREF_CONTROL); |
7576 | ||
7577 | /* As we must carefully and slowly disable/enable each source in turn, | |
7578 | * compute the final state we want first and check if we need to | |
7579 | * make any changes at all. | |
7580 | */ | |
7581 | final = val; | |
7582 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
7583 | if (has_ck505) | |
7584 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
7585 | else | |
7586 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
7587 | ||
8c07eb68 | 7588 | final &= ~DREF_SSC_SOURCE_MASK; |
74cfd7ac | 7589 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
8c07eb68 | 7590 | final &= ~DREF_SSC1_ENABLE; |
74cfd7ac CW |
7591 | |
7592 | if (has_panel) { | |
7593 | final |= DREF_SSC_SOURCE_ENABLE; | |
7594 | ||
7595 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7596 | final |= DREF_SSC1_ENABLE; | |
7597 | ||
7598 | if (has_cpu_edp) { | |
7599 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7600 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
7601 | else | |
7602 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
7603 | } else | |
7604 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
1c1a24d2 L |
7605 | } else if (using_ssc_source) { |
7606 | final |= DREF_SSC_SOURCE_ENABLE; | |
7607 | final |= DREF_SSC1_ENABLE; | |
74cfd7ac CW |
7608 | } |
7609 | ||
7610 | if (final == val) | |
7611 | return; | |
7612 | ||
13d83a67 | 7613 | /* Always enable nonspread source */ |
74cfd7ac | 7614 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 7615 | |
99eb6a01 | 7616 | if (has_ck505) |
74cfd7ac | 7617 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 7618 | else |
74cfd7ac | 7619 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 7620 | |
199e5d79 | 7621 | if (has_panel) { |
74cfd7ac CW |
7622 | val &= ~DREF_SSC_SOURCE_MASK; |
7623 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 7624 | |
199e5d79 | 7625 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 7626 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7627 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 7628 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 7629 | } else |
74cfd7ac | 7630 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
7631 | |
7632 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 7633 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7634 | POSTING_READ(PCH_DREF_CONTROL); |
7635 | udelay(200); | |
7636 | ||
74cfd7ac | 7637 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
7638 | |
7639 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 7640 | if (has_cpu_edp) { |
99eb6a01 | 7641 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7642 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 7643 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 7644 | } else |
74cfd7ac | 7645 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 7646 | } else |
74cfd7ac | 7647 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7648 | |
74cfd7ac | 7649 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7650 | POSTING_READ(PCH_DREF_CONTROL); |
7651 | udelay(200); | |
7652 | } else { | |
1c1a24d2 | 7653 | DRM_DEBUG_KMS("Disabling CPU source output\n"); |
199e5d79 | 7654 | |
74cfd7ac | 7655 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
7656 | |
7657 | /* Turn off CPU output */ | |
74cfd7ac | 7658 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7659 | |
74cfd7ac | 7660 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7661 | POSTING_READ(PCH_DREF_CONTROL); |
7662 | udelay(200); | |
7663 | ||
1c1a24d2 L |
7664 | if (!using_ssc_source) { |
7665 | DRM_DEBUG_KMS("Disabling SSC source\n"); | |
199e5d79 | 7666 | |
1c1a24d2 L |
7667 | /* Turn off the SSC source */ |
7668 | val &= ~DREF_SSC_SOURCE_MASK; | |
7669 | val |= DREF_SSC_SOURCE_DISABLE; | |
f165d283 | 7670 | |
1c1a24d2 L |
7671 | /* Turn off SSC1 */ |
7672 | val &= ~DREF_SSC1_ENABLE; | |
7673 | ||
7674 | I915_WRITE(PCH_DREF_CONTROL, val); | |
7675 | POSTING_READ(PCH_DREF_CONTROL); | |
7676 | udelay(200); | |
7677 | } | |
13d83a67 | 7678 | } |
74cfd7ac CW |
7679 | |
7680 | BUG_ON(val != final); | |
13d83a67 JB |
7681 | } |
7682 | ||
f31f2d55 | 7683 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 7684 | { |
f31f2d55 | 7685 | uint32_t tmp; |
dde86e2d | 7686 | |
0ff066a9 PZ |
7687 | tmp = I915_READ(SOUTH_CHICKEN2); |
7688 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
7689 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7690 | |
cf3598c2 ID |
7691 | if (wait_for_us(I915_READ(SOUTH_CHICKEN2) & |
7692 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
0ff066a9 | 7693 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
dde86e2d | 7694 | |
0ff066a9 PZ |
7695 | tmp = I915_READ(SOUTH_CHICKEN2); |
7696 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
7697 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7698 | |
cf3598c2 ID |
7699 | if (wait_for_us((I915_READ(SOUTH_CHICKEN2) & |
7700 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
0ff066a9 | 7701 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
f31f2d55 PZ |
7702 | } |
7703 | ||
7704 | /* WaMPhyProgramming:hsw */ | |
7705 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
7706 | { | |
7707 | uint32_t tmp; | |
dde86e2d PZ |
7708 | |
7709 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
7710 | tmp &= ~(0xFF << 24); | |
7711 | tmp |= (0x12 << 24); | |
7712 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
7713 | ||
dde86e2d PZ |
7714 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
7715 | tmp |= (1 << 11); | |
7716 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
7717 | ||
7718 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
7719 | tmp |= (1 << 11); | |
7720 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
7721 | ||
dde86e2d PZ |
7722 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
7723 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7724 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
7725 | ||
7726 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
7727 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7728 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
7729 | ||
0ff066a9 PZ |
7730 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
7731 | tmp &= ~(7 << 13); | |
7732 | tmp |= (5 << 13); | |
7733 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 7734 | |
0ff066a9 PZ |
7735 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
7736 | tmp &= ~(7 << 13); | |
7737 | tmp |= (5 << 13); | |
7738 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
7739 | |
7740 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
7741 | tmp &= ~0xFF; | |
7742 | tmp |= 0x1C; | |
7743 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
7744 | ||
7745 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
7746 | tmp &= ~0xFF; | |
7747 | tmp |= 0x1C; | |
7748 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
7749 | ||
7750 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
7751 | tmp &= ~(0xFF << 16); | |
7752 | tmp |= (0x1C << 16); | |
7753 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
7754 | ||
7755 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
7756 | tmp &= ~(0xFF << 16); | |
7757 | tmp |= (0x1C << 16); | |
7758 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
7759 | ||
0ff066a9 PZ |
7760 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
7761 | tmp |= (1 << 27); | |
7762 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 7763 | |
0ff066a9 PZ |
7764 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
7765 | tmp |= (1 << 27); | |
7766 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 7767 | |
0ff066a9 PZ |
7768 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
7769 | tmp &= ~(0xF << 28); | |
7770 | tmp |= (4 << 28); | |
7771 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 7772 | |
0ff066a9 PZ |
7773 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
7774 | tmp &= ~(0xF << 28); | |
7775 | tmp |= (4 << 28); | |
7776 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
7777 | } |
7778 | ||
2fa86a1f PZ |
7779 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
7780 | * Programming" based on the parameters passed: | |
7781 | * - Sequence to enable CLKOUT_DP | |
7782 | * - Sequence to enable CLKOUT_DP without spread | |
7783 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
7784 | */ | |
c39055b0 ACO |
7785 | static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv, |
7786 | bool with_spread, bool with_fdi) | |
f31f2d55 | 7787 | { |
2fa86a1f PZ |
7788 | uint32_t reg, tmp; |
7789 | ||
7790 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
7791 | with_spread = true; | |
4f8036a2 TU |
7792 | if (WARN(HAS_PCH_LPT_LP(dev_priv) && |
7793 | with_fdi, "LP PCH doesn't have FDI\n")) | |
2fa86a1f | 7794 | with_fdi = false; |
f31f2d55 | 7795 | |
a580516d | 7796 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
7797 | |
7798 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7799 | tmp &= ~SBI_SSCCTL_DISABLE; | |
7800 | tmp |= SBI_SSCCTL_PATHALT; | |
7801 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7802 | ||
7803 | udelay(24); | |
7804 | ||
2fa86a1f PZ |
7805 | if (with_spread) { |
7806 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7807 | tmp &= ~SBI_SSCCTL_PATHALT; | |
7808 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 7809 | |
2fa86a1f PZ |
7810 | if (with_fdi) { |
7811 | lpt_reset_fdi_mphy(dev_priv); | |
7812 | lpt_program_fdi_mphy(dev_priv); | |
7813 | } | |
7814 | } | |
dde86e2d | 7815 | |
4f8036a2 | 7816 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
7817 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
7818 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7819 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 7820 | |
a580516d | 7821 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
7822 | } |
7823 | ||
47701c3b | 7824 | /* Sequence to disable CLKOUT_DP */ |
c39055b0 | 7825 | static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv) |
47701c3b | 7826 | { |
47701c3b PZ |
7827 | uint32_t reg, tmp; |
7828 | ||
a580516d | 7829 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 7830 | |
4f8036a2 | 7831 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
7832 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
7833 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7834 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
7835 | ||
7836 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7837 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
7838 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
7839 | tmp |= SBI_SSCCTL_PATHALT; | |
7840 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7841 | udelay(32); | |
7842 | } | |
7843 | tmp |= SBI_SSCCTL_DISABLE; | |
7844 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7845 | } | |
7846 | ||
a580516d | 7847 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
7848 | } |
7849 | ||
f7be2c21 VS |
7850 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
7851 | ||
7852 | static const uint16_t sscdivintphase[] = { | |
7853 | [BEND_IDX( 50)] = 0x3B23, | |
7854 | [BEND_IDX( 45)] = 0x3B23, | |
7855 | [BEND_IDX( 40)] = 0x3C23, | |
7856 | [BEND_IDX( 35)] = 0x3C23, | |
7857 | [BEND_IDX( 30)] = 0x3D23, | |
7858 | [BEND_IDX( 25)] = 0x3D23, | |
7859 | [BEND_IDX( 20)] = 0x3E23, | |
7860 | [BEND_IDX( 15)] = 0x3E23, | |
7861 | [BEND_IDX( 10)] = 0x3F23, | |
7862 | [BEND_IDX( 5)] = 0x3F23, | |
7863 | [BEND_IDX( 0)] = 0x0025, | |
7864 | [BEND_IDX( -5)] = 0x0025, | |
7865 | [BEND_IDX(-10)] = 0x0125, | |
7866 | [BEND_IDX(-15)] = 0x0125, | |
7867 | [BEND_IDX(-20)] = 0x0225, | |
7868 | [BEND_IDX(-25)] = 0x0225, | |
7869 | [BEND_IDX(-30)] = 0x0325, | |
7870 | [BEND_IDX(-35)] = 0x0325, | |
7871 | [BEND_IDX(-40)] = 0x0425, | |
7872 | [BEND_IDX(-45)] = 0x0425, | |
7873 | [BEND_IDX(-50)] = 0x0525, | |
7874 | }; | |
7875 | ||
7876 | /* | |
7877 | * Bend CLKOUT_DP | |
7878 | * steps -50 to 50 inclusive, in steps of 5 | |
7879 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
7880 | * change in clock period = -(steps / 10) * 5.787 ps | |
7881 | */ | |
7882 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
7883 | { | |
7884 | uint32_t tmp; | |
7885 | int idx = BEND_IDX(steps); | |
7886 | ||
7887 | if (WARN_ON(steps % 5 != 0)) | |
7888 | return; | |
7889 | ||
7890 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
7891 | return; | |
7892 | ||
7893 | mutex_lock(&dev_priv->sb_lock); | |
7894 | ||
7895 | if (steps % 10 != 0) | |
7896 | tmp = 0xAAAAAAAB; | |
7897 | else | |
7898 | tmp = 0x00000000; | |
7899 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
7900 | ||
7901 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
7902 | tmp &= 0xffff0000; | |
7903 | tmp |= sscdivintphase[idx]; | |
7904 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
7905 | ||
7906 | mutex_unlock(&dev_priv->sb_lock); | |
7907 | } | |
7908 | ||
7909 | #undef BEND_IDX | |
7910 | ||
c39055b0 | 7911 | static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv) |
bf8fa3d3 | 7912 | { |
bf8fa3d3 PZ |
7913 | struct intel_encoder *encoder; |
7914 | bool has_vga = false; | |
7915 | ||
c39055b0 | 7916 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
bf8fa3d3 PZ |
7917 | switch (encoder->type) { |
7918 | case INTEL_OUTPUT_ANALOG: | |
7919 | has_vga = true; | |
7920 | break; | |
6847d71b PZ |
7921 | default: |
7922 | break; | |
bf8fa3d3 PZ |
7923 | } |
7924 | } | |
7925 | ||
f7be2c21 | 7926 | if (has_vga) { |
c39055b0 ACO |
7927 | lpt_bend_clkout_dp(dev_priv, 0); |
7928 | lpt_enable_clkout_dp(dev_priv, true, true); | |
f7be2c21 | 7929 | } else { |
c39055b0 | 7930 | lpt_disable_clkout_dp(dev_priv); |
f7be2c21 | 7931 | } |
bf8fa3d3 PZ |
7932 | } |
7933 | ||
dde86e2d PZ |
7934 | /* |
7935 | * Initialize reference clocks when the driver loads | |
7936 | */ | |
c39055b0 | 7937 | void intel_init_pch_refclk(struct drm_i915_private *dev_priv) |
dde86e2d | 7938 | { |
6e266956 | 7939 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) |
c39055b0 | 7940 | ironlake_init_pch_refclk(dev_priv); |
6e266956 | 7941 | else if (HAS_PCH_LPT(dev_priv)) |
c39055b0 | 7942 | lpt_init_pch_refclk(dev_priv); |
dde86e2d PZ |
7943 | } |
7944 | ||
6ff93609 | 7945 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 7946 | { |
fac5e23e | 7947 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
79e53945 JB |
7948 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7949 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
7950 | uint32_t val; |
7951 | ||
78114071 | 7952 | val = 0; |
c8203565 | 7953 | |
6e3c9717 | 7954 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 7955 | case 18: |
dfd07d72 | 7956 | val |= PIPECONF_6BPC; |
c8203565 PZ |
7957 | break; |
7958 | case 24: | |
dfd07d72 | 7959 | val |= PIPECONF_8BPC; |
c8203565 PZ |
7960 | break; |
7961 | case 30: | |
dfd07d72 | 7962 | val |= PIPECONF_10BPC; |
c8203565 PZ |
7963 | break; |
7964 | case 36: | |
dfd07d72 | 7965 | val |= PIPECONF_12BPC; |
c8203565 PZ |
7966 | break; |
7967 | default: | |
cc769b62 PZ |
7968 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
7969 | BUG(); | |
c8203565 PZ |
7970 | } |
7971 | ||
6e3c9717 | 7972 | if (intel_crtc->config->dither) |
c8203565 PZ |
7973 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
7974 | ||
6e3c9717 | 7975 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
7976 | val |= PIPECONF_INTERLACED_ILK; |
7977 | else | |
7978 | val |= PIPECONF_PROGRESSIVE; | |
7979 | ||
6e3c9717 | 7980 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 7981 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 7982 | |
c8203565 PZ |
7983 | I915_WRITE(PIPECONF(pipe), val); |
7984 | POSTING_READ(PIPECONF(pipe)); | |
7985 | } | |
7986 | ||
6ff93609 | 7987 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 7988 | { |
fac5e23e | 7989 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee2b0b38 | 7990 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 7991 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
391bf048 | 7992 | u32 val = 0; |
ee2b0b38 | 7993 | |
391bf048 | 7994 | if (IS_HASWELL(dev_priv) && intel_crtc->config->dither) |
ee2b0b38 PZ |
7995 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
7996 | ||
6e3c9717 | 7997 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
7998 | val |= PIPECONF_INTERLACED_ILK; |
7999 | else | |
8000 | val |= PIPECONF_PROGRESSIVE; | |
8001 | ||
702e7a56 PZ |
8002 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8003 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
391bf048 JN |
8004 | } |
8005 | ||
391bf048 JN |
8006 | static void haswell_set_pipemisc(struct drm_crtc *crtc) |
8007 | { | |
fac5e23e | 8008 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
391bf048 | 8009 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 8010 | |
391bf048 JN |
8011 | if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { |
8012 | u32 val = 0; | |
756f85cf | 8013 | |
6e3c9717 | 8014 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8015 | case 18: |
8016 | val |= PIPEMISC_DITHER_6_BPC; | |
8017 | break; | |
8018 | case 24: | |
8019 | val |= PIPEMISC_DITHER_8_BPC; | |
8020 | break; | |
8021 | case 30: | |
8022 | val |= PIPEMISC_DITHER_10_BPC; | |
8023 | break; | |
8024 | case 36: | |
8025 | val |= PIPEMISC_DITHER_12_BPC; | |
8026 | break; | |
8027 | default: | |
8028 | /* Case prevented by pipe_config_set_bpp. */ | |
8029 | BUG(); | |
8030 | } | |
8031 | ||
6e3c9717 | 8032 | if (intel_crtc->config->dither) |
756f85cf PZ |
8033 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8034 | ||
391bf048 | 8035 | I915_WRITE(PIPEMISC(intel_crtc->pipe), val); |
756f85cf | 8036 | } |
ee2b0b38 PZ |
8037 | } |
8038 | ||
d4b1931c PZ |
8039 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8040 | { | |
8041 | /* | |
8042 | * Account for spread spectrum to avoid | |
8043 | * oversubscribing the link. Max center spread | |
8044 | * is 2.5%; use 5% for safety's sake. | |
8045 | */ | |
8046 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8047 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8048 | } |
8049 | ||
7429e9d4 | 8050 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8051 | { |
7429e9d4 | 8052 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8053 | } |
8054 | ||
b75ca6f6 ACO |
8055 | static void ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
8056 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 8057 | struct dpll *reduced_clock) |
79e53945 | 8058 | { |
de13a2e3 | 8059 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 | 8060 | struct drm_device *dev = crtc->dev; |
fac5e23e | 8061 | struct drm_i915_private *dev_priv = to_i915(dev); |
b75ca6f6 | 8062 | u32 dpll, fp, fp2; |
3d6e9ee0 | 8063 | int factor; |
79e53945 | 8064 | |
c1858123 | 8065 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 | 8066 | factor = 21; |
3d6e9ee0 | 8067 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
8febb297 | 8068 | if ((intel_panel_use_ssc(dev_priv) && |
e91e941b | 8069 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
6e266956 | 8070 | (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8071 | factor = 25; |
190f68c5 | 8072 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8073 | factor = 20; |
c1858123 | 8074 | |
b75ca6f6 ACO |
8075 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
8076 | ||
190f68c5 | 8077 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
b75ca6f6 ACO |
8078 | fp |= FP_CB_TUNE; |
8079 | ||
8080 | if (reduced_clock) { | |
8081 | fp2 = i9xx_dpll_compute_fp(reduced_clock); | |
2c07245f | 8082 | |
b75ca6f6 ACO |
8083 | if (reduced_clock->m < factor * reduced_clock->n) |
8084 | fp2 |= FP_CB_TUNE; | |
8085 | } else { | |
8086 | fp2 = fp; | |
8087 | } | |
9a7c7890 | 8088 | |
5eddb70b | 8089 | dpll = 0; |
2c07245f | 8090 | |
3d6e9ee0 | 8091 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a07d6787 EA |
8092 | dpll |= DPLLB_MODE_LVDS; |
8093 | else | |
8094 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8095 | |
190f68c5 | 8096 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8097 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f | 8098 | |
3d6e9ee0 VS |
8099 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
8100 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 8101 | dpll |= DPLL_SDVO_HIGH_SPEED; |
3d6e9ee0 | 8102 | |
37a5650b | 8103 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 8104 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8105 | |
7d7f8633 VS |
8106 | /* |
8107 | * The high speed IO clock is only really required for | |
8108 | * SDVO/HDMI/DP, but we also enable it for CRT to make it | |
8109 | * possible to share the DPLL between CRT and HDMI. Enabling | |
8110 | * the clock needlessly does no real harm, except use up a | |
8111 | * bit of power potentially. | |
8112 | * | |
8113 | * We'll limit this to IVB with 3 pipes, since it has only two | |
8114 | * DPLLs and so DPLL sharing is the only way to get three pipes | |
8115 | * driving PCH ports at the same time. On SNB we could do this, | |
8116 | * and potentially avoid enabling the second DPLL, but it's not | |
8117 | * clear if it''s a win or loss power wise. No point in doing | |
8118 | * this on ILK at all since it has a fixed DPLL<->pipe mapping. | |
8119 | */ | |
8120 | if (INTEL_INFO(dev_priv)->num_pipes == 3 && | |
8121 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) | |
8122 | dpll |= DPLL_SDVO_HIGH_SPEED; | |
8123 | ||
a07d6787 | 8124 | /* compute bitmask from p1 value */ |
190f68c5 | 8125 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8126 | /* also FPA1 */ |
190f68c5 | 8127 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8128 | |
190f68c5 | 8129 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8130 | case 5: |
8131 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8132 | break; | |
8133 | case 7: | |
8134 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8135 | break; | |
8136 | case 10: | |
8137 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8138 | break; | |
8139 | case 14: | |
8140 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8141 | break; | |
79e53945 JB |
8142 | } |
8143 | ||
3d6e9ee0 VS |
8144 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
8145 | intel_panel_use_ssc(dev_priv)) | |
43565a06 | 8146 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8147 | else |
8148 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8149 | ||
b75ca6f6 ACO |
8150 | dpll |= DPLL_VCO_ENABLE; |
8151 | ||
8152 | crtc_state->dpll_hw_state.dpll = dpll; | |
8153 | crtc_state->dpll_hw_state.fp0 = fp; | |
8154 | crtc_state->dpll_hw_state.fp1 = fp2; | |
de13a2e3 PZ |
8155 | } |
8156 | ||
190f68c5 ACO |
8157 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8158 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8159 | { |
997c030c | 8160 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8161 | struct drm_i915_private *dev_priv = to_i915(dev); |
9e2c8475 | 8162 | struct dpll reduced_clock; |
7ed9f894 | 8163 | bool has_reduced_clock = false; |
e2b78267 | 8164 | struct intel_shared_dpll *pll; |
1b6f4958 | 8165 | const struct intel_limit *limit; |
997c030c | 8166 | int refclk = 120000; |
de13a2e3 | 8167 | |
dd3cd74a ACO |
8168 | memset(&crtc_state->dpll_hw_state, 0, |
8169 | sizeof(crtc_state->dpll_hw_state)); | |
8170 | ||
ded220e2 ACO |
8171 | crtc->lowfreq_avail = false; |
8172 | ||
8173 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ | |
8174 | if (!crtc_state->has_pch_encoder) | |
8175 | return 0; | |
79e53945 | 8176 | |
2d84d2b3 | 8177 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
997c030c ACO |
8178 | if (intel_panel_use_ssc(dev_priv)) { |
8179 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", | |
8180 | dev_priv->vbt.lvds_ssc_freq); | |
8181 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8182 | } | |
8183 | ||
8184 | if (intel_is_dual_link_lvds(dev)) { | |
8185 | if (refclk == 100000) | |
8186 | limit = &intel_limits_ironlake_dual_lvds_100m; | |
8187 | else | |
8188 | limit = &intel_limits_ironlake_dual_lvds; | |
8189 | } else { | |
8190 | if (refclk == 100000) | |
8191 | limit = &intel_limits_ironlake_single_lvds_100m; | |
8192 | else | |
8193 | limit = &intel_limits_ironlake_single_lvds; | |
8194 | } | |
8195 | } else { | |
8196 | limit = &intel_limits_ironlake_dac; | |
8197 | } | |
8198 | ||
364ee29d | 8199 | if (!crtc_state->clock_set && |
997c030c ACO |
8200 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
8201 | refclk, NULL, &crtc_state->dpll)) { | |
364ee29d ACO |
8202 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8203 | return -EINVAL; | |
f47709a9 | 8204 | } |
79e53945 | 8205 | |
b75ca6f6 ACO |
8206 | ironlake_compute_dpll(crtc, crtc_state, |
8207 | has_reduced_clock ? &reduced_clock : NULL); | |
66e985c0 | 8208 | |
ded220e2 ACO |
8209 | pll = intel_get_shared_dpll(crtc, crtc_state, NULL); |
8210 | if (pll == NULL) { | |
8211 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
8212 | pipe_name(crtc->pipe)); | |
8213 | return -EINVAL; | |
3fb37703 | 8214 | } |
79e53945 | 8215 | |
2d84d2b3 | 8216 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ded220e2 | 8217 | has_reduced_clock) |
c7653199 | 8218 | crtc->lowfreq_avail = true; |
e2b78267 | 8219 | |
c8f7a0db | 8220 | return 0; |
79e53945 JB |
8221 | } |
8222 | ||
eb14cb74 VS |
8223 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
8224 | struct intel_link_m_n *m_n) | |
8225 | { | |
8226 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8227 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb14cb74 VS |
8228 | enum pipe pipe = crtc->pipe; |
8229 | ||
8230 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
8231 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
8232 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8233 | & ~TU_SIZE_MASK; | |
8234 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
8235 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8236 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8237 | } | |
8238 | ||
8239 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
8240 | enum transcoder transcoder, | |
b95af8be VK |
8241 | struct intel_link_m_n *m_n, |
8242 | struct intel_link_m_n *m2_n2) | |
72419203 | 8243 | { |
6315b5d3 | 8244 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
eb14cb74 | 8245 | enum pipe pipe = crtc->pipe; |
72419203 | 8246 | |
6315b5d3 | 8247 | if (INTEL_GEN(dev_priv) >= 5) { |
eb14cb74 VS |
8248 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); |
8249 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
8250 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
8251 | & ~TU_SIZE_MASK; | |
8252 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
8253 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
8254 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
8255 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
8256 | * gen < 8) and if DRRS is supported (to make sure the | |
8257 | * registers are not unnecessarily read). | |
8258 | */ | |
6315b5d3 | 8259 | if (m2_n2 && INTEL_GEN(dev_priv) < 8 && |
6e3c9717 | 8260 | crtc->config->has_drrs) { |
b95af8be VK |
8261 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
8262 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
8263 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
8264 | & ~TU_SIZE_MASK; | |
8265 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
8266 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
8267 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8268 | } | |
eb14cb74 VS |
8269 | } else { |
8270 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
8271 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
8272 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8273 | & ~TU_SIZE_MASK; | |
8274 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
8275 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8276 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8277 | } | |
8278 | } | |
8279 | ||
8280 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 8281 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 8282 | { |
681a8504 | 8283 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
8284 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
8285 | else | |
8286 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
8287 | &pipe_config->dp_m_n, |
8288 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 8289 | } |
72419203 | 8290 | |
eb14cb74 | 8291 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 8292 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
8293 | { |
8294 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 8295 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
8296 | } |
8297 | ||
bd2e244f | 8298 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8299 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
8300 | { |
8301 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8302 | struct drm_i915_private *dev_priv = to_i915(dev); |
a1b2278e CK |
8303 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
8304 | uint32_t ps_ctrl = 0; | |
8305 | int id = -1; | |
8306 | int i; | |
bd2e244f | 8307 | |
a1b2278e CK |
8308 | /* find scaler attached to this pipe */ |
8309 | for (i = 0; i < crtc->num_scalers; i++) { | |
8310 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
8311 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
8312 | id = i; | |
8313 | pipe_config->pch_pfit.enabled = true; | |
8314 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
8315 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
8316 | break; | |
8317 | } | |
8318 | } | |
bd2e244f | 8319 | |
a1b2278e CK |
8320 | scaler_state->scaler_id = id; |
8321 | if (id >= 0) { | |
8322 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
8323 | } else { | |
8324 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
8325 | } |
8326 | } | |
8327 | ||
5724dbd1 DL |
8328 | static void |
8329 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
8330 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
8331 | { |
8332 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8333 | struct drm_i915_private *dev_priv = to_i915(dev); |
40f46283 | 8334 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
8335 | int pipe = crtc->pipe; |
8336 | int fourcc, pixel_format; | |
6761dd31 | 8337 | unsigned int aligned_height; |
bc8d7dff | 8338 | struct drm_framebuffer *fb; |
1b842c89 | 8339 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 8340 | |
d9806c9f | 8341 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8342 | if (!intel_fb) { |
bc8d7dff DL |
8343 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8344 | return; | |
8345 | } | |
8346 | ||
1b842c89 DL |
8347 | fb = &intel_fb->base; |
8348 | ||
d2e9f5fc VS |
8349 | fb->dev = dev; |
8350 | ||
bc8d7dff | 8351 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
8352 | if (!(val & PLANE_CTL_ENABLE)) |
8353 | goto error; | |
8354 | ||
bc8d7dff DL |
8355 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
8356 | fourcc = skl_format_to_fourcc(pixel_format, | |
8357 | val & PLANE_CTL_ORDER_RGBX, | |
8358 | val & PLANE_CTL_ALPHA_MASK); | |
2f3f4763 | 8359 | fb->format = drm_format_info(fourcc); |
bc8d7dff | 8360 | |
40f46283 DL |
8361 | tiling = val & PLANE_CTL_TILED_MASK; |
8362 | switch (tiling) { | |
8363 | case PLANE_CTL_TILED_LINEAR: | |
bae781b2 | 8364 | fb->modifier = DRM_FORMAT_MOD_NONE; |
40f46283 DL |
8365 | break; |
8366 | case PLANE_CTL_TILED_X: | |
8367 | plane_config->tiling = I915_TILING_X; | |
bae781b2 | 8368 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
40f46283 DL |
8369 | break; |
8370 | case PLANE_CTL_TILED_Y: | |
bae781b2 | 8371 | fb->modifier = I915_FORMAT_MOD_Y_TILED; |
40f46283 DL |
8372 | break; |
8373 | case PLANE_CTL_TILED_YF: | |
bae781b2 | 8374 | fb->modifier = I915_FORMAT_MOD_Yf_TILED; |
40f46283 DL |
8375 | break; |
8376 | default: | |
8377 | MISSING_CASE(tiling); | |
8378 | goto error; | |
8379 | } | |
8380 | ||
bc8d7dff DL |
8381 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
8382 | plane_config->base = base; | |
8383 | ||
8384 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
8385 | ||
8386 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
8387 | fb->height = ((val >> 16) & 0xfff) + 1; | |
8388 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
8389 | ||
8390 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
bae781b2 | 8391 | stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier, |
438b74a5 | 8392 | fb->format->format); |
bc8d7dff DL |
8393 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
8394 | ||
24dbf51a CW |
8395 | aligned_height = intel_fb_align_height(dev_priv, |
8396 | fb->height, | |
438b74a5 | 8397 | fb->format->format, |
bae781b2 | 8398 | fb->modifier); |
bc8d7dff | 8399 | |
f37b5c2b | 8400 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
8401 | |
8402 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
8403 | pipe_name(pipe), fb->width, fb->height, | |
272725c7 | 8404 | fb->format->cpp[0] * 8, base, fb->pitches[0], |
bc8d7dff DL |
8405 | plane_config->size); |
8406 | ||
2d14030b | 8407 | plane_config->fb = intel_fb; |
bc8d7dff DL |
8408 | return; |
8409 | ||
8410 | error: | |
d1a3a036 | 8411 | kfree(intel_fb); |
bc8d7dff DL |
8412 | } |
8413 | ||
2fa2fe9a | 8414 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8415 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8416 | { |
8417 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8418 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa2fe9a DV |
8419 | uint32_t tmp; |
8420 | ||
8421 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
8422 | ||
8423 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 8424 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
8425 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
8426 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
8427 | |
8428 | /* We currently do not free assignements of panel fitters on | |
8429 | * ivb/hsw (since we don't use the higher upscaling modes which | |
8430 | * differentiates them) so just WARN about this case for now. */ | |
5db94019 | 8431 | if (IS_GEN7(dev_priv)) { |
cb8b2a30 DV |
8432 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != |
8433 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
8434 | } | |
2fa2fe9a | 8435 | } |
79e53945 JB |
8436 | } |
8437 | ||
5724dbd1 DL |
8438 | static void |
8439 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
8440 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
8441 | { |
8442 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8443 | struct drm_i915_private *dev_priv = to_i915(dev); |
4c6baa59 | 8444 | u32 val, base, offset; |
aeee5a49 | 8445 | int pipe = crtc->pipe; |
4c6baa59 | 8446 | int fourcc, pixel_format; |
6761dd31 | 8447 | unsigned int aligned_height; |
b113d5ee | 8448 | struct drm_framebuffer *fb; |
1b842c89 | 8449 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 8450 | |
42a7b088 DL |
8451 | val = I915_READ(DSPCNTR(pipe)); |
8452 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8453 | return; | |
8454 | ||
d9806c9f | 8455 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8456 | if (!intel_fb) { |
4c6baa59 JB |
8457 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8458 | return; | |
8459 | } | |
8460 | ||
1b842c89 DL |
8461 | fb = &intel_fb->base; |
8462 | ||
d2e9f5fc VS |
8463 | fb->dev = dev; |
8464 | ||
6315b5d3 | 8465 | if (INTEL_GEN(dev_priv) >= 4) { |
18c5247e | 8466 | if (val & DISPPLANE_TILED) { |
49af449b | 8467 | plane_config->tiling = I915_TILING_X; |
bae781b2 | 8468 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
18c5247e DV |
8469 | } |
8470 | } | |
4c6baa59 JB |
8471 | |
8472 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8473 | fourcc = i9xx_format_to_fourcc(pixel_format); |
2f3f4763 | 8474 | fb->format = drm_format_info(fourcc); |
4c6baa59 | 8475 | |
aeee5a49 | 8476 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
8652744b | 8477 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
aeee5a49 | 8478 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 8479 | } else { |
49af449b | 8480 | if (plane_config->tiling) |
aeee5a49 | 8481 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 8482 | else |
aeee5a49 | 8483 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
8484 | } |
8485 | plane_config->base = base; | |
8486 | ||
8487 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8488 | fb->width = ((val >> 16) & 0xfff) + 1; |
8489 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
8490 | |
8491 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8492 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 8493 | |
24dbf51a CW |
8494 | aligned_height = intel_fb_align_height(dev_priv, |
8495 | fb->height, | |
438b74a5 | 8496 | fb->format->format, |
bae781b2 | 8497 | fb->modifier); |
4c6baa59 | 8498 | |
f37b5c2b | 8499 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 8500 | |
2844a921 DL |
8501 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8502 | pipe_name(pipe), fb->width, fb->height, | |
272725c7 | 8503 | fb->format->cpp[0] * 8, base, fb->pitches[0], |
2844a921 | 8504 | plane_config->size); |
b113d5ee | 8505 | |
2d14030b | 8506 | plane_config->fb = intel_fb; |
4c6baa59 JB |
8507 | } |
8508 | ||
0e8ffe1b | 8509 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8510 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8511 | { |
8512 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8513 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e | 8514 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 8515 | uint32_t tmp; |
1729050e | 8516 | bool ret; |
0e8ffe1b | 8517 | |
1729050e ID |
8518 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8519 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
930e8c9e PZ |
8520 | return false; |
8521 | ||
e143a21c | 8522 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 8523 | pipe_config->shared_dpll = NULL; |
eccb140b | 8524 | |
1729050e | 8525 | ret = false; |
0e8ffe1b DV |
8526 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8527 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 8528 | goto out; |
0e8ffe1b | 8529 | |
42571aef VS |
8530 | switch (tmp & PIPECONF_BPC_MASK) { |
8531 | case PIPECONF_6BPC: | |
8532 | pipe_config->pipe_bpp = 18; | |
8533 | break; | |
8534 | case PIPECONF_8BPC: | |
8535 | pipe_config->pipe_bpp = 24; | |
8536 | break; | |
8537 | case PIPECONF_10BPC: | |
8538 | pipe_config->pipe_bpp = 30; | |
8539 | break; | |
8540 | case PIPECONF_12BPC: | |
8541 | pipe_config->pipe_bpp = 36; | |
8542 | break; | |
8543 | default: | |
8544 | break; | |
8545 | } | |
8546 | ||
b5a9fa09 DV |
8547 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
8548 | pipe_config->limited_color_range = true; | |
8549 | ||
ab9412ba | 8550 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 | 8551 | struct intel_shared_dpll *pll; |
8106ddbd | 8552 | enum intel_dpll_id pll_id; |
66e985c0 | 8553 | |
88adfff1 DV |
8554 | pipe_config->has_pch_encoder = true; |
8555 | ||
627eb5a3 DV |
8556 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
8557 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
8558 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
8559 | |
8560 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 8561 | |
2d1fe073 | 8562 | if (HAS_PCH_IBX(dev_priv)) { |
d9a7bc67 ID |
8563 | /* |
8564 | * The pipe->pch transcoder and pch transcoder->pll | |
8565 | * mapping is fixed. | |
8566 | */ | |
8106ddbd | 8567 | pll_id = (enum intel_dpll_id) crtc->pipe; |
c0d43d62 DV |
8568 | } else { |
8569 | tmp = I915_READ(PCH_DPLL_SEL); | |
8570 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8106ddbd | 8571 | pll_id = DPLL_ID_PCH_PLL_B; |
c0d43d62 | 8572 | else |
8106ddbd | 8573 | pll_id= DPLL_ID_PCH_PLL_A; |
c0d43d62 | 8574 | } |
66e985c0 | 8575 | |
8106ddbd ACO |
8576 | pipe_config->shared_dpll = |
8577 | intel_get_shared_dpll_by_id(dev_priv, pll_id); | |
8578 | pll = pipe_config->shared_dpll; | |
66e985c0 | 8579 | |
2edd6443 ACO |
8580 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
8581 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
8582 | |
8583 | tmp = pipe_config->dpll_hw_state.dpll; | |
8584 | pipe_config->pixel_multiplier = | |
8585 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
8586 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
8587 | |
8588 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
8589 | } else { |
8590 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
8591 | } |
8592 | ||
1bd1bd80 | 8593 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 8594 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 8595 | |
2fa2fe9a DV |
8596 | ironlake_get_pfit_config(crtc, pipe_config); |
8597 | ||
1729050e ID |
8598 | ret = true; |
8599 | ||
8600 | out: | |
8601 | intel_display_power_put(dev_priv, power_domain); | |
8602 | ||
8603 | return ret; | |
0e8ffe1b DV |
8604 | } |
8605 | ||
be256dc7 PZ |
8606 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
8607 | { | |
91c8a326 | 8608 | struct drm_device *dev = &dev_priv->drm; |
be256dc7 | 8609 | struct intel_crtc *crtc; |
be256dc7 | 8610 | |
d3fcc808 | 8611 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 8612 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
8613 | pipe_name(crtc->pipe)); |
8614 | ||
e2c719b7 RC |
8615 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
8616 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
8617 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
8618 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
44cb734c | 8619 | I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n"); |
e2c719b7 | 8620 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
be256dc7 | 8621 | "CPU PWM1 enabled\n"); |
772c2a51 | 8622 | if (IS_HASWELL(dev_priv)) |
e2c719b7 | 8623 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 8624 | "CPU PWM2 enabled\n"); |
e2c719b7 | 8625 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 8626 | "PCH PWM1 enabled\n"); |
e2c719b7 | 8627 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 8628 | "Utility pin enabled\n"); |
e2c719b7 | 8629 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 8630 | |
9926ada1 PZ |
8631 | /* |
8632 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
8633 | * interrupts remain enabled. We used to check for that, but since it's | |
8634 | * gen-specific and since we only disable LCPLL after we fully disable | |
8635 | * the interrupts, the check below should be enough. | |
8636 | */ | |
e2c719b7 | 8637 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
8638 | } |
8639 | ||
9ccd5aeb PZ |
8640 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
8641 | { | |
772c2a51 | 8642 | if (IS_HASWELL(dev_priv)) |
9ccd5aeb PZ |
8643 | return I915_READ(D_COMP_HSW); |
8644 | else | |
8645 | return I915_READ(D_COMP_BDW); | |
8646 | } | |
8647 | ||
3c4c9b81 PZ |
8648 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
8649 | { | |
772c2a51 | 8650 | if (IS_HASWELL(dev_priv)) { |
3c4c9b81 PZ |
8651 | mutex_lock(&dev_priv->rps.hw_lock); |
8652 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
8653 | val)) | |
79cf219a | 8654 | DRM_DEBUG_KMS("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
8655 | mutex_unlock(&dev_priv->rps.hw_lock); |
8656 | } else { | |
9ccd5aeb PZ |
8657 | I915_WRITE(D_COMP_BDW, val); |
8658 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 8659 | } |
be256dc7 PZ |
8660 | } |
8661 | ||
8662 | /* | |
8663 | * This function implements pieces of two sequences from BSpec: | |
8664 | * - Sequence for display software to disable LCPLL | |
8665 | * - Sequence for display software to allow package C8+ | |
8666 | * The steps implemented here are just the steps that actually touch the LCPLL | |
8667 | * register. Callers should take care of disabling all the display engine | |
8668 | * functions, doing the mode unset, fixing interrupts, etc. | |
8669 | */ | |
6ff58d53 PZ |
8670 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
8671 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
8672 | { |
8673 | uint32_t val; | |
8674 | ||
8675 | assert_can_disable_lcpll(dev_priv); | |
8676 | ||
8677 | val = I915_READ(LCPLL_CTL); | |
8678 | ||
8679 | if (switch_to_fclk) { | |
8680 | val |= LCPLL_CD_SOURCE_FCLK; | |
8681 | I915_WRITE(LCPLL_CTL, val); | |
8682 | ||
f53dd63f ID |
8683 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
8684 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
be256dc7 PZ |
8685 | DRM_ERROR("Switching to FCLK failed\n"); |
8686 | ||
8687 | val = I915_READ(LCPLL_CTL); | |
8688 | } | |
8689 | ||
8690 | val |= LCPLL_PLL_DISABLE; | |
8691 | I915_WRITE(LCPLL_CTL, val); | |
8692 | POSTING_READ(LCPLL_CTL); | |
8693 | ||
24d8441d | 8694 | if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1)) |
be256dc7 PZ |
8695 | DRM_ERROR("LCPLL still locked\n"); |
8696 | ||
9ccd5aeb | 8697 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 8698 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 8699 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8700 | ndelay(100); |
8701 | ||
9ccd5aeb PZ |
8702 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
8703 | 1)) | |
be256dc7 PZ |
8704 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
8705 | ||
8706 | if (allow_power_down) { | |
8707 | val = I915_READ(LCPLL_CTL); | |
8708 | val |= LCPLL_POWER_DOWN_ALLOW; | |
8709 | I915_WRITE(LCPLL_CTL, val); | |
8710 | POSTING_READ(LCPLL_CTL); | |
8711 | } | |
8712 | } | |
8713 | ||
8714 | /* | |
8715 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
8716 | * source. | |
8717 | */ | |
6ff58d53 | 8718 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
8719 | { |
8720 | uint32_t val; | |
8721 | ||
8722 | val = I915_READ(LCPLL_CTL); | |
8723 | ||
8724 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
8725 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
8726 | return; | |
8727 | ||
a8a8bd54 PZ |
8728 | /* |
8729 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
8730 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 8731 | */ |
59bad947 | 8732 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 8733 | |
be256dc7 PZ |
8734 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
8735 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
8736 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 8737 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
8738 | } |
8739 | ||
9ccd5aeb | 8740 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
8741 | val |= D_COMP_COMP_FORCE; |
8742 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 8743 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8744 | |
8745 | val = I915_READ(LCPLL_CTL); | |
8746 | val &= ~LCPLL_PLL_DISABLE; | |
8747 | I915_WRITE(LCPLL_CTL, val); | |
8748 | ||
93220c08 CW |
8749 | if (intel_wait_for_register(dev_priv, |
8750 | LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
8751 | 5)) | |
be256dc7 PZ |
8752 | DRM_ERROR("LCPLL not locked yet\n"); |
8753 | ||
8754 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
8755 | val = I915_READ(LCPLL_CTL); | |
8756 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
8757 | I915_WRITE(LCPLL_CTL, val); | |
8758 | ||
f53dd63f ID |
8759 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
8760 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
be256dc7 PZ |
8761 | DRM_ERROR("Switching back to LCPLL failed\n"); |
8762 | } | |
215733fa | 8763 | |
59bad947 | 8764 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
4c75b940 | 8765 | intel_update_cdclk(dev_priv); |
be256dc7 PZ |
8766 | } |
8767 | ||
765dab67 PZ |
8768 | /* |
8769 | * Package states C8 and deeper are really deep PC states that can only be | |
8770 | * reached when all the devices on the system allow it, so even if the graphics | |
8771 | * device allows PC8+, it doesn't mean the system will actually get to these | |
8772 | * states. Our driver only allows PC8+ when going into runtime PM. | |
8773 | * | |
8774 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
8775 | * well is disabled and most interrupts are disabled, and these are also | |
8776 | * requirements for runtime PM. When these conditions are met, we manually do | |
8777 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
8778 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
8779 | * hang the machine. | |
8780 | * | |
8781 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
8782 | * the state of some registers, so when we come back from PC8+ we need to | |
8783 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
8784 | * need to take care of the registers kept by RC6. Notice that this happens even | |
8785 | * if we don't put the device in PCI D3 state (which is what currently happens | |
8786 | * because of the runtime PM support). | |
8787 | * | |
8788 | * For more, read "Display Sequences for Package C8" on the hardware | |
8789 | * documentation. | |
8790 | */ | |
a14cb6fc | 8791 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 8792 | { |
c67a470b PZ |
8793 | uint32_t val; |
8794 | ||
c67a470b PZ |
8795 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
8796 | ||
4f8036a2 | 8797 | if (HAS_PCH_LPT_LP(dev_priv)) { |
c67a470b PZ |
8798 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
8799 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
8800 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8801 | } | |
8802 | ||
c39055b0 | 8803 | lpt_disable_clkout_dp(dev_priv); |
c67a470b PZ |
8804 | hsw_disable_lcpll(dev_priv, true, true); |
8805 | } | |
8806 | ||
a14cb6fc | 8807 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 8808 | { |
c67a470b PZ |
8809 | uint32_t val; |
8810 | ||
c67a470b PZ |
8811 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
8812 | ||
8813 | hsw_restore_lcpll(dev_priv); | |
c39055b0 | 8814 | lpt_init_pch_refclk(dev_priv); |
c67a470b | 8815 | |
4f8036a2 | 8816 | if (HAS_PCH_LPT_LP(dev_priv)) { |
c67a470b PZ |
8817 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
8818 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
8819 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8820 | } | |
c67a470b PZ |
8821 | } |
8822 | ||
190f68c5 ACO |
8823 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
8824 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 8825 | { |
d7edc4e5 | 8826 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) { |
af3997b5 MK |
8827 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
8828 | return -EINVAL; | |
8829 | } | |
716c2e55 | 8830 | |
c7653199 | 8831 | crtc->lowfreq_avail = false; |
644cef34 | 8832 | |
c8f7a0db | 8833 | return 0; |
79e53945 JB |
8834 | } |
8835 | ||
3760b59c S |
8836 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
8837 | enum port port, | |
8838 | struct intel_crtc_state *pipe_config) | |
8839 | { | |
8106ddbd ACO |
8840 | enum intel_dpll_id id; |
8841 | ||
3760b59c S |
8842 | switch (port) { |
8843 | case PORT_A: | |
08250c4b | 8844 | id = DPLL_ID_SKL_DPLL0; |
3760b59c S |
8845 | break; |
8846 | case PORT_B: | |
08250c4b | 8847 | id = DPLL_ID_SKL_DPLL1; |
3760b59c S |
8848 | break; |
8849 | case PORT_C: | |
08250c4b | 8850 | id = DPLL_ID_SKL_DPLL2; |
3760b59c S |
8851 | break; |
8852 | default: | |
8853 | DRM_ERROR("Incorrect port type\n"); | |
8106ddbd | 8854 | return; |
3760b59c | 8855 | } |
8106ddbd ACO |
8856 | |
8857 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
3760b59c S |
8858 | } |
8859 | ||
96b7dfb7 S |
8860 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
8861 | enum port port, | |
5cec258b | 8862 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 8863 | { |
8106ddbd | 8864 | enum intel_dpll_id id; |
a3c988ea | 8865 | u32 temp; |
96b7dfb7 S |
8866 | |
8867 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
c856052a | 8868 | id = temp >> (port * 3 + 1); |
96b7dfb7 | 8869 | |
c856052a | 8870 | if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3)) |
8106ddbd | 8871 | return; |
8106ddbd ACO |
8872 | |
8873 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
96b7dfb7 S |
8874 | } |
8875 | ||
7d2c8175 DL |
8876 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
8877 | enum port port, | |
5cec258b | 8878 | struct intel_crtc_state *pipe_config) |
7d2c8175 | 8879 | { |
8106ddbd | 8880 | enum intel_dpll_id id; |
c856052a | 8881 | uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
8106ddbd | 8882 | |
c856052a | 8883 | switch (ddi_pll_sel) { |
7d2c8175 | 8884 | case PORT_CLK_SEL_WRPLL1: |
8106ddbd | 8885 | id = DPLL_ID_WRPLL1; |
7d2c8175 DL |
8886 | break; |
8887 | case PORT_CLK_SEL_WRPLL2: | |
8106ddbd | 8888 | id = DPLL_ID_WRPLL2; |
7d2c8175 | 8889 | break; |
00490c22 | 8890 | case PORT_CLK_SEL_SPLL: |
8106ddbd | 8891 | id = DPLL_ID_SPLL; |
79bd23da | 8892 | break; |
9d16da65 ACO |
8893 | case PORT_CLK_SEL_LCPLL_810: |
8894 | id = DPLL_ID_LCPLL_810; | |
8895 | break; | |
8896 | case PORT_CLK_SEL_LCPLL_1350: | |
8897 | id = DPLL_ID_LCPLL_1350; | |
8898 | break; | |
8899 | case PORT_CLK_SEL_LCPLL_2700: | |
8900 | id = DPLL_ID_LCPLL_2700; | |
8901 | break; | |
8106ddbd | 8902 | default: |
c856052a | 8903 | MISSING_CASE(ddi_pll_sel); |
8106ddbd ACO |
8904 | /* fall through */ |
8905 | case PORT_CLK_SEL_NONE: | |
8106ddbd | 8906 | return; |
7d2c8175 | 8907 | } |
8106ddbd ACO |
8908 | |
8909 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
7d2c8175 DL |
8910 | } |
8911 | ||
cf30429e JN |
8912 | static bool hsw_get_transcoder_state(struct intel_crtc *crtc, |
8913 | struct intel_crtc_state *pipe_config, | |
d8fc70b7 | 8914 | u64 *power_domain_mask) |
cf30429e JN |
8915 | { |
8916 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8917 | struct drm_i915_private *dev_priv = to_i915(dev); |
cf30429e JN |
8918 | enum intel_display_power_domain power_domain; |
8919 | u32 tmp; | |
8920 | ||
d9a7bc67 ID |
8921 | /* |
8922 | * The pipe->transcoder mapping is fixed with the exception of the eDP | |
8923 | * transcoder handled below. | |
8924 | */ | |
cf30429e JN |
8925 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8926 | ||
8927 | /* | |
8928 | * XXX: Do intel_display_power_get_if_enabled before reading this (for | |
8929 | * consistency and less surprising code; it's in always on power). | |
8930 | */ | |
8931 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
8932 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
8933 | enum pipe trans_edp_pipe; | |
8934 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
8935 | default: | |
8936 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
8937 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
8938 | case TRANS_DDI_EDP_INPUT_A_ON: | |
8939 | trans_edp_pipe = PIPE_A; | |
8940 | break; | |
8941 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
8942 | trans_edp_pipe = PIPE_B; | |
8943 | break; | |
8944 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
8945 | trans_edp_pipe = PIPE_C; | |
8946 | break; | |
8947 | } | |
8948 | ||
8949 | if (trans_edp_pipe == crtc->pipe) | |
8950 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
8951 | } | |
8952 | ||
8953 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); | |
8954 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
8955 | return false; | |
d8fc70b7 | 8956 | *power_domain_mask |= BIT_ULL(power_domain); |
cf30429e JN |
8957 | |
8958 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); | |
8959 | ||
8960 | return tmp & PIPECONF_ENABLE; | |
8961 | } | |
8962 | ||
4d1de975 JN |
8963 | static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, |
8964 | struct intel_crtc_state *pipe_config, | |
d8fc70b7 | 8965 | u64 *power_domain_mask) |
4d1de975 JN |
8966 | { |
8967 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8968 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 JN |
8969 | enum intel_display_power_domain power_domain; |
8970 | enum port port; | |
8971 | enum transcoder cpu_transcoder; | |
8972 | u32 tmp; | |
8973 | ||
4d1de975 JN |
8974 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { |
8975 | if (port == PORT_A) | |
8976 | cpu_transcoder = TRANSCODER_DSI_A; | |
8977 | else | |
8978 | cpu_transcoder = TRANSCODER_DSI_C; | |
8979 | ||
8980 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
8981 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
8982 | continue; | |
d8fc70b7 | 8983 | *power_domain_mask |= BIT_ULL(power_domain); |
4d1de975 | 8984 | |
db18b6a6 ID |
8985 | /* |
8986 | * The PLL needs to be enabled with a valid divider | |
8987 | * configuration, otherwise accessing DSI registers will hang | |
8988 | * the machine. See BSpec North Display Engine | |
8989 | * registers/MIPI[BXT]. We can break out here early, since we | |
8990 | * need the same DSI PLL to be enabled for both DSI ports. | |
8991 | */ | |
8992 | if (!intel_dsi_pll_is_enabled(dev_priv)) | |
8993 | break; | |
8994 | ||
4d1de975 JN |
8995 | /* XXX: this works for video mode only */ |
8996 | tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
8997 | if (!(tmp & DPI_ENABLE)) | |
8998 | continue; | |
8999 | ||
9000 | tmp = I915_READ(MIPI_CTRL(port)); | |
9001 | if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) | |
9002 | continue; | |
9003 | ||
9004 | pipe_config->cpu_transcoder = cpu_transcoder; | |
4d1de975 JN |
9005 | break; |
9006 | } | |
9007 | ||
d7edc4e5 | 9008 | return transcoder_is_dsi(pipe_config->cpu_transcoder); |
4d1de975 JN |
9009 | } |
9010 | ||
26804afd | 9011 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9012 | struct intel_crtc_state *pipe_config) |
26804afd | 9013 | { |
6315b5d3 | 9014 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
d452c5b6 | 9015 | struct intel_shared_dpll *pll; |
26804afd DV |
9016 | enum port port; |
9017 | uint32_t tmp; | |
9018 | ||
9019 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9020 | ||
9021 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9022 | ||
b976dc53 | 9023 | if (IS_GEN9_BC(dev_priv)) |
96b7dfb7 | 9024 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
cc3f90f0 | 9025 | else if (IS_GEN9_LP(dev_priv)) |
3760b59c | 9026 | bxt_get_ddi_pll(dev_priv, port, pipe_config); |
96b7dfb7 S |
9027 | else |
9028 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9029 | |
8106ddbd ACO |
9030 | pll = pipe_config->shared_dpll; |
9031 | if (pll) { | |
2edd6443 ACO |
9032 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
9033 | &pipe_config->dpll_hw_state)); | |
d452c5b6 DV |
9034 | } |
9035 | ||
26804afd DV |
9036 | /* |
9037 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9038 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9039 | * the PCH transcoder is on. | |
9040 | */ | |
6315b5d3 | 9041 | if (INTEL_GEN(dev_priv) < 9 && |
ca370455 | 9042 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
26804afd DV |
9043 | pipe_config->has_pch_encoder = true; |
9044 | ||
9045 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9046 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9047 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9048 | ||
9049 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9050 | } | |
9051 | } | |
9052 | ||
0e8ffe1b | 9053 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9054 | struct intel_crtc_state *pipe_config) |
0e8ffe1b | 9055 | { |
6315b5d3 | 9056 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1729050e | 9057 | enum intel_display_power_domain power_domain; |
d8fc70b7 | 9058 | u64 power_domain_mask; |
cf30429e | 9059 | bool active; |
0e8ffe1b | 9060 | |
1729050e ID |
9061 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9062 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 | 9063 | return false; |
d8fc70b7 | 9064 | power_domain_mask = BIT_ULL(power_domain); |
1729050e | 9065 | |
8106ddbd | 9066 | pipe_config->shared_dpll = NULL; |
c0d43d62 | 9067 | |
cf30429e | 9068 | active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); |
eccb140b | 9069 | |
cc3f90f0 | 9070 | if (IS_GEN9_LP(dev_priv) && |
d7edc4e5 VS |
9071 | bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) { |
9072 | WARN_ON(active); | |
9073 | active = true; | |
4d1de975 JN |
9074 | } |
9075 | ||
cf30429e | 9076 | if (!active) |
1729050e | 9077 | goto out; |
0e8ffe1b | 9078 | |
d7edc4e5 | 9079 | if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { |
4d1de975 JN |
9080 | haswell_get_ddi_port_state(crtc, pipe_config); |
9081 | intel_get_pipe_timings(crtc, pipe_config); | |
9082 | } | |
627eb5a3 | 9083 | |
bc58be60 | 9084 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 9085 | |
05dc698c LL |
9086 | pipe_config->gamma_mode = |
9087 | I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; | |
9088 | ||
6315b5d3 | 9089 | if (INTEL_GEN(dev_priv) >= 9) { |
1c74eeaf | 9090 | intel_crtc_init_scalers(crtc, pipe_config); |
a1b2278e | 9091 | |
af99ceda CK |
9092 | pipe_config->scaler_state.scaler_id = -1; |
9093 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
9094 | } | |
9095 | ||
1729050e ID |
9096 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
9097 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
d8fc70b7 | 9098 | power_domain_mask |= BIT_ULL(power_domain); |
6315b5d3 | 9099 | if (INTEL_GEN(dev_priv) >= 9) |
bd2e244f | 9100 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 9101 | else |
1c132b44 | 9102 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 9103 | } |
88adfff1 | 9104 | |
772c2a51 | 9105 | if (IS_HASWELL(dev_priv)) |
e59150dc JB |
9106 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
9107 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 9108 | |
4d1de975 JN |
9109 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && |
9110 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { | |
ebb69c95 CT |
9111 | pipe_config->pixel_multiplier = |
9112 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
9113 | } else { | |
9114 | pipe_config->pixel_multiplier = 1; | |
9115 | } | |
6c49f241 | 9116 | |
1729050e ID |
9117 | out: |
9118 | for_each_power_domain(power_domain, power_domain_mask) | |
9119 | intel_display_power_put(dev_priv, power_domain); | |
9120 | ||
cf30429e | 9121 | return active; |
0e8ffe1b DV |
9122 | } |
9123 | ||
55a08b3f ML |
9124 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, |
9125 | const struct intel_plane_state *plane_state) | |
560b85bb CW |
9126 | { |
9127 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 9128 | struct drm_i915_private *dev_priv = to_i915(dev); |
560b85bb | 9129 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
dc41c154 | 9130 | uint32_t cntl = 0, size = 0; |
560b85bb | 9131 | |
936e71e3 | 9132 | if (plane_state && plane_state->base.visible) { |
55a08b3f ML |
9133 | unsigned int width = plane_state->base.crtc_w; |
9134 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 VS |
9135 | unsigned int stride = roundup_pow_of_two(width) * 4; |
9136 | ||
9137 | switch (stride) { | |
9138 | default: | |
9139 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
9140 | width, stride); | |
9141 | stride = 256; | |
9142 | /* fallthrough */ | |
9143 | case 256: | |
9144 | case 512: | |
9145 | case 1024: | |
9146 | case 2048: | |
9147 | break; | |
4b0e333e CW |
9148 | } |
9149 | ||
dc41c154 VS |
9150 | cntl |= CURSOR_ENABLE | |
9151 | CURSOR_GAMMA_ENABLE | | |
9152 | CURSOR_FORMAT_ARGB | | |
9153 | CURSOR_STRIDE(stride); | |
9154 | ||
9155 | size = (height << 12) | width; | |
4b0e333e | 9156 | } |
560b85bb | 9157 | |
dc41c154 VS |
9158 | if (intel_crtc->cursor_cntl != 0 && |
9159 | (intel_crtc->cursor_base != base || | |
9160 | intel_crtc->cursor_size != size || | |
9161 | intel_crtc->cursor_cntl != cntl)) { | |
9162 | /* On these chipsets we can only modify the base/size/stride | |
9163 | * whilst the cursor is disabled. | |
9164 | */ | |
0b87c24e VS |
9165 | I915_WRITE(CURCNTR(PIPE_A), 0); |
9166 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 9167 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 9168 | } |
560b85bb | 9169 | |
99d1f387 | 9170 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 9171 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
9172 | intel_crtc->cursor_base = base; |
9173 | } | |
4726e0b0 | 9174 | |
dc41c154 VS |
9175 | if (intel_crtc->cursor_size != size) { |
9176 | I915_WRITE(CURSIZE, size); | |
9177 | intel_crtc->cursor_size = size; | |
4b0e333e | 9178 | } |
560b85bb | 9179 | |
4b0e333e | 9180 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
9181 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
9182 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 9183 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 9184 | } |
560b85bb CW |
9185 | } |
9186 | ||
55a08b3f ML |
9187 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, |
9188 | const struct intel_plane_state *plane_state) | |
65a21cd6 JB |
9189 | { |
9190 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 9191 | struct drm_i915_private *dev_priv = to_i915(dev); |
65a21cd6 JB |
9192 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9193 | int pipe = intel_crtc->pipe; | |
663f3122 | 9194 | uint32_t cntl = 0; |
4b0e333e | 9195 | |
936e71e3 | 9196 | if (plane_state && plane_state->base.visible) { |
4b0e333e | 9197 | cntl = MCURSOR_GAMMA_ENABLE; |
55a08b3f | 9198 | switch (plane_state->base.crtc_w) { |
4726e0b0 SK |
9199 | case 64: |
9200 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
9201 | break; | |
9202 | case 128: | |
9203 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
9204 | break; | |
9205 | case 256: | |
9206 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
9207 | break; | |
9208 | default: | |
55a08b3f | 9209 | MISSING_CASE(plane_state->base.crtc_w); |
4726e0b0 | 9210 | return; |
65a21cd6 | 9211 | } |
4b0e333e | 9212 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 9213 | |
4f8036a2 | 9214 | if (HAS_DDI(dev_priv)) |
47bf17a7 | 9215 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
65a21cd6 | 9216 | |
f22aa143 | 9217 | if (plane_state->base.rotation & DRM_ROTATE_180) |
55a08b3f ML |
9218 | cntl |= CURSOR_ROTATE_180; |
9219 | } | |
4398ad45 | 9220 | |
4b0e333e CW |
9221 | if (intel_crtc->cursor_cntl != cntl) { |
9222 | I915_WRITE(CURCNTR(pipe), cntl); | |
9223 | POSTING_READ(CURCNTR(pipe)); | |
9224 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 9225 | } |
4b0e333e | 9226 | |
65a21cd6 | 9227 | /* and commit changes on next vblank */ |
5efb3e28 VS |
9228 | I915_WRITE(CURBASE(pipe), base); |
9229 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
9230 | |
9231 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
9232 | } |
9233 | ||
cda4b7d3 | 9234 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f | 9235 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
55a08b3f | 9236 | const struct intel_plane_state *plane_state) |
cda4b7d3 CW |
9237 | { |
9238 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 9239 | struct drm_i915_private *dev_priv = to_i915(dev); |
cda4b7d3 CW |
9240 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9241 | int pipe = intel_crtc->pipe; | |
55a08b3f ML |
9242 | u32 base = intel_crtc->cursor_addr; |
9243 | u32 pos = 0; | |
cda4b7d3 | 9244 | |
55a08b3f ML |
9245 | if (plane_state) { |
9246 | int x = plane_state->base.crtc_x; | |
9247 | int y = plane_state->base.crtc_y; | |
cda4b7d3 | 9248 | |
55a08b3f ML |
9249 | if (x < 0) { |
9250 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
9251 | x = -x; | |
9252 | } | |
9253 | pos |= x << CURSOR_X_SHIFT; | |
cda4b7d3 | 9254 | |
55a08b3f ML |
9255 | if (y < 0) { |
9256 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
9257 | y = -y; | |
9258 | } | |
9259 | pos |= y << CURSOR_Y_SHIFT; | |
9260 | ||
9261 | /* ILK+ do this automagically */ | |
49cff963 | 9262 | if (HAS_GMCH_DISPLAY(dev_priv) && |
f22aa143 | 9263 | plane_state->base.rotation & DRM_ROTATE_180) { |
55a08b3f ML |
9264 | base += (plane_state->base.crtc_h * |
9265 | plane_state->base.crtc_w - 1) * 4; | |
9266 | } | |
cda4b7d3 | 9267 | } |
cda4b7d3 | 9268 | |
5efb3e28 VS |
9269 | I915_WRITE(CURPOS(pipe), pos); |
9270 | ||
2a307c2e | 9271 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
55a08b3f | 9272 | i845_update_cursor(crtc, base, plane_state); |
5efb3e28 | 9273 | else |
55a08b3f | 9274 | i9xx_update_cursor(crtc, base, plane_state); |
cda4b7d3 CW |
9275 | } |
9276 | ||
50a0bc90 | 9277 | static bool cursor_size_ok(struct drm_i915_private *dev_priv, |
dc41c154 VS |
9278 | uint32_t width, uint32_t height) |
9279 | { | |
9280 | if (width == 0 || height == 0) | |
9281 | return false; | |
9282 | ||
9283 | /* | |
9284 | * 845g/865g are special in that they are only limited by | |
9285 | * the width of their cursors, the height is arbitrary up to | |
9286 | * the precision of the register. Everything else requires | |
9287 | * square cursors, limited to a few power-of-two sizes. | |
9288 | */ | |
2a307c2e | 9289 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { |
dc41c154 VS |
9290 | if ((width & 63) != 0) |
9291 | return false; | |
9292 | ||
2a307c2e | 9293 | if (width > (IS_I845G(dev_priv) ? 64 : 512)) |
dc41c154 VS |
9294 | return false; |
9295 | ||
9296 | if (height > 1023) | |
9297 | return false; | |
9298 | } else { | |
9299 | switch (width | height) { | |
9300 | case 256: | |
9301 | case 128: | |
50a0bc90 | 9302 | if (IS_GEN2(dev_priv)) |
dc41c154 VS |
9303 | return false; |
9304 | case 64: | |
9305 | break; | |
9306 | default: | |
9307 | return false; | |
9308 | } | |
9309 | } | |
9310 | ||
9311 | return true; | |
9312 | } | |
9313 | ||
79e53945 JB |
9314 | /* VESA 640x480x72Hz mode to set on the pipe */ |
9315 | static struct drm_display_mode load_detect_mode = { | |
9316 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
9317 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
9318 | }; | |
9319 | ||
a8bb6818 | 9320 | struct drm_framebuffer * |
24dbf51a CW |
9321 | intel_framebuffer_create(struct drm_i915_gem_object *obj, |
9322 | struct drm_mode_fb_cmd2 *mode_cmd) | |
d2dff872 CW |
9323 | { |
9324 | struct intel_framebuffer *intel_fb; | |
9325 | int ret; | |
9326 | ||
9327 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 9328 | if (!intel_fb) |
d2dff872 | 9329 | return ERR_PTR(-ENOMEM); |
d2dff872 | 9330 | |
24dbf51a | 9331 | ret = intel_framebuffer_init(intel_fb, obj, mode_cmd); |
dd4916c5 DV |
9332 | if (ret) |
9333 | goto err; | |
d2dff872 CW |
9334 | |
9335 | return &intel_fb->base; | |
dcb1394e | 9336 | |
dd4916c5 | 9337 | err: |
dd4916c5 | 9338 | kfree(intel_fb); |
dd4916c5 | 9339 | return ERR_PTR(ret); |
d2dff872 CW |
9340 | } |
9341 | ||
9342 | static u32 | |
9343 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
9344 | { | |
9345 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
9346 | return ALIGN(pitch, 64); | |
9347 | } | |
9348 | ||
9349 | static u32 | |
9350 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
9351 | { | |
9352 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 9353 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
9354 | } |
9355 | ||
9356 | static struct drm_framebuffer * | |
9357 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
9358 | struct drm_display_mode *mode, | |
9359 | int depth, int bpp) | |
9360 | { | |
dcb1394e | 9361 | struct drm_framebuffer *fb; |
d2dff872 | 9362 | struct drm_i915_gem_object *obj; |
0fed39bd | 9363 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 | 9364 | |
12d79d78 | 9365 | obj = i915_gem_object_create(to_i915(dev), |
d2dff872 | 9366 | intel_framebuffer_size_for_mode(mode, bpp)); |
fe3db79b CW |
9367 | if (IS_ERR(obj)) |
9368 | return ERR_CAST(obj); | |
d2dff872 CW |
9369 | |
9370 | mode_cmd.width = mode->hdisplay; | |
9371 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
9372 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
9373 | bpp); | |
5ca0c34a | 9374 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 9375 | |
24dbf51a | 9376 | fb = intel_framebuffer_create(obj, &mode_cmd); |
dcb1394e | 9377 | if (IS_ERR(fb)) |
f0cd5182 | 9378 | i915_gem_object_put(obj); |
dcb1394e LW |
9379 | |
9380 | return fb; | |
d2dff872 CW |
9381 | } |
9382 | ||
9383 | static struct drm_framebuffer * | |
9384 | mode_fits_in_fbdev(struct drm_device *dev, | |
9385 | struct drm_display_mode *mode) | |
9386 | { | |
0695726e | 9387 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
fac5e23e | 9388 | struct drm_i915_private *dev_priv = to_i915(dev); |
d2dff872 CW |
9389 | struct drm_i915_gem_object *obj; |
9390 | struct drm_framebuffer *fb; | |
9391 | ||
4c0e5528 | 9392 | if (!dev_priv->fbdev) |
d2dff872 CW |
9393 | return NULL; |
9394 | ||
4c0e5528 | 9395 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
9396 | return NULL; |
9397 | ||
4c0e5528 DV |
9398 | obj = dev_priv->fbdev->fb->obj; |
9399 | BUG_ON(!obj); | |
9400 | ||
8bcd4553 | 9401 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 | 9402 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
272725c7 | 9403 | fb->format->cpp[0] * 8)) |
d2dff872 CW |
9404 | return NULL; |
9405 | ||
01f2c773 | 9406 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
9407 | return NULL; |
9408 | ||
edde3617 | 9409 | drm_framebuffer_reference(fb); |
d2dff872 | 9410 | return fb; |
4520f53a DV |
9411 | #else |
9412 | return NULL; | |
9413 | #endif | |
d2dff872 CW |
9414 | } |
9415 | ||
d3a40d1b ACO |
9416 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
9417 | struct drm_crtc *crtc, | |
9418 | struct drm_display_mode *mode, | |
9419 | struct drm_framebuffer *fb, | |
9420 | int x, int y) | |
9421 | { | |
9422 | struct drm_plane_state *plane_state; | |
9423 | int hdisplay, vdisplay; | |
9424 | int ret; | |
9425 | ||
9426 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
9427 | if (IS_ERR(plane_state)) | |
9428 | return PTR_ERR(plane_state); | |
9429 | ||
9430 | if (mode) | |
196cd5d3 | 9431 | drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay); |
d3a40d1b ACO |
9432 | else |
9433 | hdisplay = vdisplay = 0; | |
9434 | ||
9435 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
9436 | if (ret) | |
9437 | return ret; | |
9438 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
9439 | plane_state->crtc_x = 0; | |
9440 | plane_state->crtc_y = 0; | |
9441 | plane_state->crtc_w = hdisplay; | |
9442 | plane_state->crtc_h = vdisplay; | |
9443 | plane_state->src_x = x << 16; | |
9444 | plane_state->src_y = y << 16; | |
9445 | plane_state->src_w = hdisplay << 16; | |
9446 | plane_state->src_h = vdisplay << 16; | |
9447 | ||
9448 | return 0; | |
9449 | } | |
9450 | ||
d2434ab7 | 9451 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 9452 | struct drm_display_mode *mode, |
51fd371b RC |
9453 | struct intel_load_detect_pipe *old, |
9454 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
9455 | { |
9456 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
9457 | struct intel_encoder *intel_encoder = |
9458 | intel_attached_encoder(connector); | |
79e53945 | 9459 | struct drm_crtc *possible_crtc; |
4ef69c7a | 9460 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
9461 | struct drm_crtc *crtc = NULL; |
9462 | struct drm_device *dev = encoder->dev; | |
0f0f74bc | 9463 | struct drm_i915_private *dev_priv = to_i915(dev); |
94352cf9 | 9464 | struct drm_framebuffer *fb; |
51fd371b | 9465 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 9466 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 9467 | struct drm_connector_state *connector_state; |
4be07317 | 9468 | struct intel_crtc_state *crtc_state; |
51fd371b | 9469 | int ret, i = -1; |
79e53945 | 9470 | |
d2dff872 | 9471 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9472 | connector->base.id, connector->name, |
8e329a03 | 9473 | encoder->base.id, encoder->name); |
d2dff872 | 9474 | |
edde3617 ML |
9475 | old->restore_state = NULL; |
9476 | ||
51fd371b RC |
9477 | retry: |
9478 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
9479 | if (ret) | |
ad3c558f | 9480 | goto fail; |
6e9f798d | 9481 | |
79e53945 JB |
9482 | /* |
9483 | * Algorithm gets a little messy: | |
7a5e4805 | 9484 | * |
79e53945 JB |
9485 | * - if the connector already has an assigned crtc, use it (but make |
9486 | * sure it's on first) | |
7a5e4805 | 9487 | * |
79e53945 JB |
9488 | * - try to find the first unused crtc that can drive this connector, |
9489 | * and use that if we find one | |
79e53945 JB |
9490 | */ |
9491 | ||
9492 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
9493 | if (connector->state->crtc) { |
9494 | crtc = connector->state->crtc; | |
8261b191 | 9495 | |
51fd371b | 9496 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 9497 | if (ret) |
ad3c558f | 9498 | goto fail; |
8261b191 CW |
9499 | |
9500 | /* Make sure the crtc and connector are running */ | |
edde3617 | 9501 | goto found; |
79e53945 JB |
9502 | } |
9503 | ||
9504 | /* Find an unused one (if possible) */ | |
70e1e0ec | 9505 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
9506 | i++; |
9507 | if (!(encoder->possible_crtcs & (1 << i))) | |
9508 | continue; | |
edde3617 ML |
9509 | |
9510 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
9511 | if (ret) | |
9512 | goto fail; | |
9513 | ||
9514 | if (possible_crtc->state->enable) { | |
9515 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 9516 | continue; |
edde3617 | 9517 | } |
a459249c VS |
9518 | |
9519 | crtc = possible_crtc; | |
9520 | break; | |
79e53945 JB |
9521 | } |
9522 | ||
9523 | /* | |
9524 | * If we didn't find an unused CRTC, don't use any. | |
9525 | */ | |
9526 | if (!crtc) { | |
7173188d | 9527 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 9528 | goto fail; |
79e53945 JB |
9529 | } |
9530 | ||
edde3617 ML |
9531 | found: |
9532 | intel_crtc = to_intel_crtc(crtc); | |
9533 | ||
4d02e2de DV |
9534 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
9535 | if (ret) | |
ad3c558f | 9536 | goto fail; |
79e53945 | 9537 | |
83a57153 | 9538 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
9539 | restore_state = drm_atomic_state_alloc(dev); |
9540 | if (!state || !restore_state) { | |
9541 | ret = -ENOMEM; | |
9542 | goto fail; | |
9543 | } | |
83a57153 ACO |
9544 | |
9545 | state->acquire_ctx = ctx; | |
edde3617 | 9546 | restore_state->acquire_ctx = ctx; |
83a57153 | 9547 | |
944b0c76 ACO |
9548 | connector_state = drm_atomic_get_connector_state(state, connector); |
9549 | if (IS_ERR(connector_state)) { | |
9550 | ret = PTR_ERR(connector_state); | |
9551 | goto fail; | |
9552 | } | |
9553 | ||
edde3617 ML |
9554 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
9555 | if (ret) | |
9556 | goto fail; | |
944b0c76 | 9557 | |
4be07317 ACO |
9558 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
9559 | if (IS_ERR(crtc_state)) { | |
9560 | ret = PTR_ERR(crtc_state); | |
9561 | goto fail; | |
9562 | } | |
9563 | ||
49d6fa21 | 9564 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 9565 | |
6492711d CW |
9566 | if (!mode) |
9567 | mode = &load_detect_mode; | |
79e53945 | 9568 | |
d2dff872 CW |
9569 | /* We need a framebuffer large enough to accommodate all accesses |
9570 | * that the plane may generate whilst we perform load detection. | |
9571 | * We can not rely on the fbcon either being present (we get called | |
9572 | * during its initialisation to detect all boot displays, or it may | |
9573 | * not even exist) or that it is large enough to satisfy the | |
9574 | * requested mode. | |
9575 | */ | |
94352cf9 DV |
9576 | fb = mode_fits_in_fbdev(dev, mode); |
9577 | if (fb == NULL) { | |
d2dff872 | 9578 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 | 9579 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
d2dff872 CW |
9580 | } else |
9581 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 9582 | if (IS_ERR(fb)) { |
d2dff872 | 9583 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 9584 | goto fail; |
79e53945 | 9585 | } |
79e53945 | 9586 | |
d3a40d1b ACO |
9587 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
9588 | if (ret) | |
9589 | goto fail; | |
9590 | ||
edde3617 ML |
9591 | drm_framebuffer_unreference(fb); |
9592 | ||
9593 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
9594 | if (ret) | |
9595 | goto fail; | |
9596 | ||
9597 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
9598 | if (!ret) | |
9599 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
9600 | if (!ret) | |
9601 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
9602 | if (ret) { | |
9603 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
9604 | goto fail; | |
9605 | } | |
8c7b5ccb | 9606 | |
3ba86073 ML |
9607 | ret = drm_atomic_commit(state); |
9608 | if (ret) { | |
6492711d | 9609 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
412b61d8 | 9610 | goto fail; |
79e53945 | 9611 | } |
edde3617 ML |
9612 | |
9613 | old->restore_state = restore_state; | |
7abbd11f | 9614 | drm_atomic_state_put(state); |
7173188d | 9615 | |
79e53945 | 9616 | /* let the connector get through one full cycle before testing */ |
0f0f74bc | 9617 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
7173188d | 9618 | return true; |
412b61d8 | 9619 | |
ad3c558f | 9620 | fail: |
7fb71c8f CW |
9621 | if (state) { |
9622 | drm_atomic_state_put(state); | |
9623 | state = NULL; | |
9624 | } | |
9625 | if (restore_state) { | |
9626 | drm_atomic_state_put(restore_state); | |
9627 | restore_state = NULL; | |
9628 | } | |
83a57153 | 9629 | |
51fd371b RC |
9630 | if (ret == -EDEADLK) { |
9631 | drm_modeset_backoff(ctx); | |
9632 | goto retry; | |
9633 | } | |
9634 | ||
412b61d8 | 9635 | return false; |
79e53945 JB |
9636 | } |
9637 | ||
d2434ab7 | 9638 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
9639 | struct intel_load_detect_pipe *old, |
9640 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 9641 | { |
d2434ab7 DV |
9642 | struct intel_encoder *intel_encoder = |
9643 | intel_attached_encoder(connector); | |
4ef69c7a | 9644 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 9645 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 9646 | int ret; |
79e53945 | 9647 | |
d2dff872 | 9648 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9649 | connector->base.id, connector->name, |
8e329a03 | 9650 | encoder->base.id, encoder->name); |
d2dff872 | 9651 | |
edde3617 | 9652 | if (!state) |
0622a53c | 9653 | return; |
79e53945 | 9654 | |
edde3617 | 9655 | ret = drm_atomic_commit(state); |
0853695c | 9656 | if (ret) |
edde3617 | 9657 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); |
0853695c | 9658 | drm_atomic_state_put(state); |
79e53945 JB |
9659 | } |
9660 | ||
da4a1efa | 9661 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 9662 | const struct intel_crtc_state *pipe_config) |
da4a1efa | 9663 | { |
fac5e23e | 9664 | struct drm_i915_private *dev_priv = to_i915(dev); |
da4a1efa VS |
9665 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
9666 | ||
9667 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 9668 | return dev_priv->vbt.lvds_ssc_freq; |
6e266956 | 9669 | else if (HAS_PCH_SPLIT(dev_priv)) |
da4a1efa | 9670 | return 120000; |
5db94019 | 9671 | else if (!IS_GEN2(dev_priv)) |
da4a1efa VS |
9672 | return 96000; |
9673 | else | |
9674 | return 48000; | |
9675 | } | |
9676 | ||
79e53945 | 9677 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 9678 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 9679 | struct intel_crtc_state *pipe_config) |
79e53945 | 9680 | { |
f1f644dc | 9681 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 9682 | struct drm_i915_private *dev_priv = to_i915(dev); |
f1f644dc | 9683 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 9684 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 | 9685 | u32 fp; |
9e2c8475 | 9686 | struct dpll clock; |
dccbea3b | 9687 | int port_clock; |
da4a1efa | 9688 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
9689 | |
9690 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 9691 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 9692 | else |
293623f7 | 9693 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
9694 | |
9695 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
9b1e14f4 | 9696 | if (IS_PINEVIEW(dev_priv)) { |
f2b115e6 AJ |
9697 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
9698 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
9699 | } else { |
9700 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
9701 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
9702 | } | |
9703 | ||
5db94019 | 9704 | if (!IS_GEN2(dev_priv)) { |
9b1e14f4 | 9705 | if (IS_PINEVIEW(dev_priv)) |
f2b115e6 AJ |
9706 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
9707 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
9708 | else |
9709 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
9710 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
9711 | ||
9712 | switch (dpll & DPLL_MODE_MASK) { | |
9713 | case DPLLB_MODE_DAC_SERIAL: | |
9714 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
9715 | 5 : 10; | |
9716 | break; | |
9717 | case DPLLB_MODE_LVDS: | |
9718 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
9719 | 7 : 14; | |
9720 | break; | |
9721 | default: | |
28c97730 | 9722 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 9723 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 9724 | return; |
79e53945 JB |
9725 | } |
9726 | ||
9b1e14f4 | 9727 | if (IS_PINEVIEW(dev_priv)) |
dccbea3b | 9728 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 9729 | else |
dccbea3b | 9730 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 9731 | } else { |
50a0bc90 | 9732 | u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS); |
b1c560d1 | 9733 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
9734 | |
9735 | if (is_lvds) { | |
9736 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
9737 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
9738 | |
9739 | if (lvds & LVDS_CLKB_POWER_UP) | |
9740 | clock.p2 = 7; | |
9741 | else | |
9742 | clock.p2 = 14; | |
79e53945 JB |
9743 | } else { |
9744 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
9745 | clock.p1 = 2; | |
9746 | else { | |
9747 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
9748 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
9749 | } | |
9750 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
9751 | clock.p2 = 4; | |
9752 | else | |
9753 | clock.p2 = 2; | |
79e53945 | 9754 | } |
da4a1efa | 9755 | |
dccbea3b | 9756 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
9757 | } |
9758 | ||
18442d08 VS |
9759 | /* |
9760 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 9761 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
9762 | * encoder's get_config() function. |
9763 | */ | |
dccbea3b | 9764 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
9765 | } |
9766 | ||
6878da05 VS |
9767 | int intel_dotclock_calculate(int link_freq, |
9768 | const struct intel_link_m_n *m_n) | |
f1f644dc | 9769 | { |
f1f644dc JB |
9770 | /* |
9771 | * The calculation for the data clock is: | |
1041a02f | 9772 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 9773 | * But we want to avoid losing precison if possible, so: |
1041a02f | 9774 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
9775 | * |
9776 | * and the link clock is simpler: | |
1041a02f | 9777 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
9778 | */ |
9779 | ||
6878da05 VS |
9780 | if (!m_n->link_n) |
9781 | return 0; | |
f1f644dc | 9782 | |
6878da05 VS |
9783 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
9784 | } | |
f1f644dc | 9785 | |
18442d08 | 9786 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 9787 | struct intel_crtc_state *pipe_config) |
6878da05 | 9788 | { |
e3b247da | 9789 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
79e53945 | 9790 | |
18442d08 VS |
9791 | /* read out port_clock from the DPLL */ |
9792 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 9793 | |
f1f644dc | 9794 | /* |
e3b247da VS |
9795 | * In case there is an active pipe without active ports, |
9796 | * we may need some idea for the dotclock anyway. | |
9797 | * Calculate one based on the FDI configuration. | |
79e53945 | 9798 | */ |
2d112de7 | 9799 | pipe_config->base.adjusted_mode.crtc_clock = |
21a727b3 | 9800 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
18442d08 | 9801 | &pipe_config->fdi_m_n); |
79e53945 JB |
9802 | } |
9803 | ||
9804 | /** Returns the currently programmed mode of the given pipe. */ | |
9805 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
9806 | struct drm_crtc *crtc) | |
9807 | { | |
fac5e23e | 9808 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 9809 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 9810 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 9811 | struct drm_display_mode *mode; |
3f36b937 | 9812 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
9813 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
9814 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
9815 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
9816 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 9817 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
9818 | |
9819 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
9820 | if (!mode) | |
9821 | return NULL; | |
9822 | ||
3f36b937 TU |
9823 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
9824 | if (!pipe_config) { | |
9825 | kfree(mode); | |
9826 | return NULL; | |
9827 | } | |
9828 | ||
f1f644dc JB |
9829 | /* |
9830 | * Construct a pipe_config sufficient for getting the clock info | |
9831 | * back out of crtc_clock_get. | |
9832 | * | |
9833 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
9834 | * to use a real value here instead. | |
9835 | */ | |
3f36b937 TU |
9836 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
9837 | pipe_config->pixel_multiplier = 1; | |
9838 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
9839 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
9840 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
9841 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
9842 | ||
9843 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
9844 | mode->hdisplay = (htot & 0xffff) + 1; |
9845 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
9846 | mode->hsync_start = (hsync & 0xffff) + 1; | |
9847 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
9848 | mode->vdisplay = (vtot & 0xffff) + 1; | |
9849 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
9850 | mode->vsync_start = (vsync & 0xffff) + 1; | |
9851 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
9852 | ||
9853 | drm_mode_set_name(mode); | |
79e53945 | 9854 | |
3f36b937 TU |
9855 | kfree(pipe_config); |
9856 | ||
79e53945 JB |
9857 | return mode; |
9858 | } | |
9859 | ||
9860 | static void intel_crtc_destroy(struct drm_crtc *crtc) | |
9861 | { | |
9862 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a | 9863 | struct drm_device *dev = crtc->dev; |
51cbaf01 | 9864 | struct intel_flip_work *work; |
67e77c5a | 9865 | |
5e2d7afc | 9866 | spin_lock_irq(&dev->event_lock); |
5a21b665 DV |
9867 | work = intel_crtc->flip_work; |
9868 | intel_crtc->flip_work = NULL; | |
9869 | spin_unlock_irq(&dev->event_lock); | |
67e77c5a | 9870 | |
5a21b665 | 9871 | if (work) { |
51cbaf01 ML |
9872 | cancel_work_sync(&work->mmio_work); |
9873 | cancel_work_sync(&work->unpin_work); | |
5a21b665 | 9874 | kfree(work); |
67e77c5a | 9875 | } |
79e53945 JB |
9876 | |
9877 | drm_crtc_cleanup(crtc); | |
67e77c5a | 9878 | |
79e53945 JB |
9879 | kfree(intel_crtc); |
9880 | } | |
9881 | ||
6b95a207 KH |
9882 | static void intel_unpin_work_fn(struct work_struct *__work) |
9883 | { | |
51cbaf01 ML |
9884 | struct intel_flip_work *work = |
9885 | container_of(__work, struct intel_flip_work, unpin_work); | |
5a21b665 DV |
9886 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
9887 | struct drm_device *dev = crtc->base.dev; | |
9888 | struct drm_plane *primary = crtc->base.primary; | |
03f476e1 | 9889 | |
5a21b665 DV |
9890 | if (is_mmio_work(work)) |
9891 | flush_work(&work->mmio_work); | |
03f476e1 | 9892 | |
5a21b665 | 9893 | mutex_lock(&dev->struct_mutex); |
be1e3415 | 9894 | intel_unpin_fb_vma(work->old_vma); |
f8c417cd | 9895 | i915_gem_object_put(work->pending_flip_obj); |
5a21b665 | 9896 | mutex_unlock(&dev->struct_mutex); |
143f73b3 | 9897 | |
e8a261ea CW |
9898 | i915_gem_request_put(work->flip_queued_req); |
9899 | ||
5748b6a1 CW |
9900 | intel_frontbuffer_flip_complete(to_i915(dev), |
9901 | to_intel_plane(primary)->frontbuffer_bit); | |
5a21b665 DV |
9902 | intel_fbc_post_update(crtc); |
9903 | drm_framebuffer_unreference(work->old_fb); | |
143f73b3 | 9904 | |
5a21b665 DV |
9905 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
9906 | atomic_dec(&crtc->unpin_work_count); | |
a6747b73 | 9907 | |
5a21b665 DV |
9908 | kfree(work); |
9909 | } | |
d9e86c0e | 9910 | |
5a21b665 DV |
9911 | /* Is 'a' after or equal to 'b'? */ |
9912 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
9913 | { | |
9914 | return !((a - b) & 0x80000000); | |
9915 | } | |
143f73b3 | 9916 | |
5a21b665 DV |
9917 | static bool __pageflip_finished_cs(struct intel_crtc *crtc, |
9918 | struct intel_flip_work *work) | |
9919 | { | |
9920 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9921 | struct drm_i915_private *dev_priv = to_i915(dev); |
143f73b3 | 9922 | |
8af29b0c | 9923 | if (abort_flip_on_reset(crtc)) |
5a21b665 | 9924 | return true; |
143f73b3 | 9925 | |
5a21b665 DV |
9926 | /* |
9927 | * The relevant registers doen't exist on pre-ctg. | |
9928 | * As the flip done interrupt doesn't trigger for mmio | |
9929 | * flips on gmch platforms, a flip count check isn't | |
9930 | * really needed there. But since ctg has the registers, | |
9931 | * include it in the check anyway. | |
9932 | */ | |
9beb5fea | 9933 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
5a21b665 | 9934 | return true; |
b4a98e57 | 9935 | |
5a21b665 DV |
9936 | /* |
9937 | * BDW signals flip done immediately if the plane | |
9938 | * is disabled, even if the plane enable is already | |
9939 | * armed to occur at the next vblank :( | |
9940 | */ | |
f99d7069 | 9941 | |
5a21b665 DV |
9942 | /* |
9943 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
9944 | * used the same base address. In that case the mmio flip might | |
9945 | * have completed, but the CS hasn't even executed the flip yet. | |
9946 | * | |
9947 | * A flip count check isn't enough as the CS might have updated | |
9948 | * the base address just after start of vblank, but before we | |
9949 | * managed to process the interrupt. This means we'd complete the | |
9950 | * CS flip too soon. | |
9951 | * | |
9952 | * Combining both checks should get us a good enough result. It may | |
9953 | * still happen that the CS flip has been executed, but has not | |
9954 | * yet actually completed. But in case the base address is the same | |
9955 | * anyway, we don't really care. | |
9956 | */ | |
9957 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
9958 | crtc->flip_work->gtt_offset && | |
9959 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), | |
9960 | crtc->flip_work->flip_count); | |
9961 | } | |
b4a98e57 | 9962 | |
5a21b665 DV |
9963 | static bool |
9964 | __pageflip_finished_mmio(struct intel_crtc *crtc, | |
9965 | struct intel_flip_work *work) | |
9966 | { | |
9967 | /* | |
9968 | * MMIO work completes when vblank is different from | |
9969 | * flip_queued_vblank. | |
9970 | * | |
9971 | * Reset counter value doesn't matter, this is handled by | |
9972 | * i915_wait_request finishing early, so no need to handle | |
9973 | * reset here. | |
9974 | */ | |
9975 | return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank; | |
6b95a207 KH |
9976 | } |
9977 | ||
51cbaf01 ML |
9978 | |
9979 | static bool pageflip_finished(struct intel_crtc *crtc, | |
9980 | struct intel_flip_work *work) | |
9981 | { | |
9982 | if (!atomic_read(&work->pending)) | |
9983 | return false; | |
9984 | ||
9985 | smp_rmb(); | |
9986 | ||
5a21b665 DV |
9987 | if (is_mmio_work(work)) |
9988 | return __pageflip_finished_mmio(crtc, work); | |
9989 | else | |
9990 | return __pageflip_finished_cs(crtc, work); | |
9991 | } | |
9992 | ||
9993 | void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe) | |
9994 | { | |
91c8a326 | 9995 | struct drm_device *dev = &dev_priv->drm; |
98187836 | 9996 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
5a21b665 DV |
9997 | struct intel_flip_work *work; |
9998 | unsigned long flags; | |
9999 | ||
10000 | /* Ignore early vblank irqs */ | |
10001 | if (!crtc) | |
10002 | return; | |
10003 | ||
51cbaf01 | 10004 | /* |
5a21b665 DV |
10005 | * This is called both by irq handlers and the reset code (to complete |
10006 | * lost pageflips) so needs the full irqsave spinlocks. | |
51cbaf01 | 10007 | */ |
5a21b665 | 10008 | spin_lock_irqsave(&dev->event_lock, flags); |
e2af48c6 | 10009 | work = crtc->flip_work; |
5a21b665 DV |
10010 | |
10011 | if (work != NULL && | |
10012 | !is_mmio_work(work) && | |
e2af48c6 VS |
10013 | pageflip_finished(crtc, work)) |
10014 | page_flip_completed(crtc); | |
5a21b665 DV |
10015 | |
10016 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
75f7f3ec VS |
10017 | } |
10018 | ||
51cbaf01 | 10019 | void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe) |
6b95a207 | 10020 | { |
91c8a326 | 10021 | struct drm_device *dev = &dev_priv->drm; |
98187836 | 10022 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
51cbaf01 | 10023 | struct intel_flip_work *work; |
6b95a207 KH |
10024 | unsigned long flags; |
10025 | ||
5251f04e ML |
10026 | /* Ignore early vblank irqs */ |
10027 | if (!crtc) | |
10028 | return; | |
f326038a DV |
10029 | |
10030 | /* | |
10031 | * This is called both by irq handlers and the reset code (to complete | |
10032 | * lost pageflips) so needs the full irqsave spinlocks. | |
e7d841ca | 10033 | */ |
6b95a207 | 10034 | spin_lock_irqsave(&dev->event_lock, flags); |
e2af48c6 | 10035 | work = crtc->flip_work; |
5251f04e | 10036 | |
5a21b665 DV |
10037 | if (work != NULL && |
10038 | is_mmio_work(work) && | |
e2af48c6 VS |
10039 | pageflip_finished(crtc, work)) |
10040 | page_flip_completed(crtc); | |
5251f04e | 10041 | |
6b95a207 KH |
10042 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10043 | } | |
10044 | ||
5a21b665 DV |
10045 | static inline void intel_mark_page_flip_active(struct intel_crtc *crtc, |
10046 | struct intel_flip_work *work) | |
84c33a64 | 10047 | { |
5a21b665 | 10048 | work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc); |
84c33a64 | 10049 | |
5a21b665 DV |
10050 | /* Ensure that the work item is consistent when activating it ... */ |
10051 | smp_mb__before_atomic(); | |
10052 | atomic_set(&work->pending, 1); | |
10053 | } | |
a6747b73 | 10054 | |
5a21b665 DV |
10055 | static int intel_gen2_queue_flip(struct drm_device *dev, |
10056 | struct drm_crtc *crtc, | |
10057 | struct drm_framebuffer *fb, | |
10058 | struct drm_i915_gem_object *obj, | |
10059 | struct drm_i915_gem_request *req, | |
10060 | uint32_t flags) | |
10061 | { | |
5a21b665 | 10062 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
73dec95e | 10063 | u32 flip_mask, *cs; |
143f73b3 | 10064 | |
73dec95e TU |
10065 | cs = intel_ring_begin(req, 6); |
10066 | if (IS_ERR(cs)) | |
10067 | return PTR_ERR(cs); | |
143f73b3 | 10068 | |
5a21b665 DV |
10069 | /* Can't queue multiple flips, so wait for the previous |
10070 | * one to finish before executing the next. | |
10071 | */ | |
10072 | if (intel_crtc->plane) | |
10073 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10074 | else | |
10075 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
73dec95e TU |
10076 | *cs++ = MI_WAIT_FOR_EVENT | flip_mask; |
10077 | *cs++ = MI_NOOP; | |
10078 | *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane); | |
10079 | *cs++ = fb->pitches[0]; | |
10080 | *cs++ = intel_crtc->flip_work->gtt_offset; | |
10081 | *cs++ = 0; /* aux display base address, unused */ | |
143f73b3 | 10082 | |
5a21b665 DV |
10083 | return 0; |
10084 | } | |
84c33a64 | 10085 | |
5a21b665 DV |
10086 | static int intel_gen3_queue_flip(struct drm_device *dev, |
10087 | struct drm_crtc *crtc, | |
10088 | struct drm_framebuffer *fb, | |
10089 | struct drm_i915_gem_object *obj, | |
10090 | struct drm_i915_gem_request *req, | |
10091 | uint32_t flags) | |
10092 | { | |
5a21b665 | 10093 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
73dec95e | 10094 | u32 flip_mask, *cs; |
d55dbd06 | 10095 | |
73dec95e TU |
10096 | cs = intel_ring_begin(req, 6); |
10097 | if (IS_ERR(cs)) | |
10098 | return PTR_ERR(cs); | |
d55dbd06 | 10099 | |
5a21b665 DV |
10100 | if (intel_crtc->plane) |
10101 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10102 | else | |
10103 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
73dec95e TU |
10104 | *cs++ = MI_WAIT_FOR_EVENT | flip_mask; |
10105 | *cs++ = MI_NOOP; | |
10106 | *cs++ = MI_DISPLAY_FLIP_I915 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane); | |
10107 | *cs++ = fb->pitches[0]; | |
10108 | *cs++ = intel_crtc->flip_work->gtt_offset; | |
10109 | *cs++ = MI_NOOP; | |
fd8e058a | 10110 | |
5a21b665 DV |
10111 | return 0; |
10112 | } | |
84c33a64 | 10113 | |
5a21b665 DV |
10114 | static int intel_gen4_queue_flip(struct drm_device *dev, |
10115 | struct drm_crtc *crtc, | |
10116 | struct drm_framebuffer *fb, | |
10117 | struct drm_i915_gem_object *obj, | |
10118 | struct drm_i915_gem_request *req, | |
10119 | uint32_t flags) | |
10120 | { | |
fac5e23e | 10121 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 10122 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
73dec95e | 10123 | u32 pf, pipesrc, *cs; |
143f73b3 | 10124 | |
73dec95e TU |
10125 | cs = intel_ring_begin(req, 4); |
10126 | if (IS_ERR(cs)) | |
10127 | return PTR_ERR(cs); | |
143f73b3 | 10128 | |
5a21b665 DV |
10129 | /* i965+ uses the linear or tiled offsets from the |
10130 | * Display Registers (which do not change across a page-flip) | |
10131 | * so we need only reprogram the base address. | |
10132 | */ | |
73dec95e TU |
10133 | *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane); |
10134 | *cs++ = fb->pitches[0]; | |
10135 | *cs++ = intel_crtc->flip_work->gtt_offset | | |
10136 | intel_fb_modifier_to_tiling(fb->modifier); | |
5a21b665 DV |
10137 | |
10138 | /* XXX Enabling the panel-fitter across page-flip is so far | |
10139 | * untested on non-native modes, so ignore it for now. | |
10140 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
10141 | */ | |
10142 | pf = 0; | |
10143 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
73dec95e | 10144 | *cs++ = pf | pipesrc; |
143f73b3 | 10145 | |
5a21b665 | 10146 | return 0; |
8c9f3aaf JB |
10147 | } |
10148 | ||
5a21b665 DV |
10149 | static int intel_gen6_queue_flip(struct drm_device *dev, |
10150 | struct drm_crtc *crtc, | |
10151 | struct drm_framebuffer *fb, | |
10152 | struct drm_i915_gem_object *obj, | |
10153 | struct drm_i915_gem_request *req, | |
10154 | uint32_t flags) | |
da20eabd | 10155 | { |
fac5e23e | 10156 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 10157 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
73dec95e | 10158 | u32 pf, pipesrc, *cs; |
d21fbe87 | 10159 | |
73dec95e TU |
10160 | cs = intel_ring_begin(req, 4); |
10161 | if (IS_ERR(cs)) | |
10162 | return PTR_ERR(cs); | |
92826fcd | 10163 | |
73dec95e TU |
10164 | *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane); |
10165 | *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier); | |
10166 | *cs++ = intel_crtc->flip_work->gtt_offset; | |
92826fcd | 10167 | |
5a21b665 DV |
10168 | /* Contrary to the suggestions in the documentation, |
10169 | * "Enable Panel Fitter" does not seem to be required when page | |
10170 | * flipping with a non-native mode, and worse causes a normal | |
10171 | * modeset to fail. | |
10172 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
10173 | */ | |
10174 | pf = 0; | |
10175 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
73dec95e | 10176 | *cs++ = pf | pipesrc; |
7809e5ae | 10177 | |
5a21b665 | 10178 | return 0; |
7809e5ae MR |
10179 | } |
10180 | ||
5a21b665 DV |
10181 | static int intel_gen7_queue_flip(struct drm_device *dev, |
10182 | struct drm_crtc *crtc, | |
10183 | struct drm_framebuffer *fb, | |
10184 | struct drm_i915_gem_object *obj, | |
10185 | struct drm_i915_gem_request *req, | |
10186 | uint32_t flags) | |
d21fbe87 | 10187 | { |
5db94019 | 10188 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 10189 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
73dec95e | 10190 | u32 *cs, plane_bit = 0; |
5a21b665 | 10191 | int len, ret; |
d21fbe87 | 10192 | |
5a21b665 DV |
10193 | switch (intel_crtc->plane) { |
10194 | case PLANE_A: | |
10195 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
10196 | break; | |
10197 | case PLANE_B: | |
10198 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
10199 | break; | |
10200 | case PLANE_C: | |
10201 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
10202 | break; | |
10203 | default: | |
10204 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
10205 | return -ENODEV; | |
10206 | } | |
10207 | ||
10208 | len = 4; | |
b5321f30 | 10209 | if (req->engine->id == RCS) { |
5a21b665 DV |
10210 | len += 6; |
10211 | /* | |
10212 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
10213 | * 48bits addresses, and we need a NOOP for the batch size to | |
10214 | * stay even. | |
10215 | */ | |
5db94019 | 10216 | if (IS_GEN8(dev_priv)) |
5a21b665 DV |
10217 | len += 2; |
10218 | } | |
10219 | ||
10220 | /* | |
10221 | * BSpec MI_DISPLAY_FLIP for IVB: | |
10222 | * "The full packet must be contained within the same cache line." | |
10223 | * | |
10224 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
10225 | * cacheline, if we ever start emitting more commands before | |
10226 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
10227 | * then do the cacheline alignment, and finally emit the | |
10228 | * MI_DISPLAY_FLIP. | |
10229 | */ | |
10230 | ret = intel_ring_cacheline_align(req); | |
10231 | if (ret) | |
10232 | return ret; | |
10233 | ||
73dec95e TU |
10234 | cs = intel_ring_begin(req, len); |
10235 | if (IS_ERR(cs)) | |
10236 | return PTR_ERR(cs); | |
5a21b665 DV |
10237 | |
10238 | /* Unmask the flip-done completion message. Note that the bspec says that | |
10239 | * we should do this for both the BCS and RCS, and that we must not unmask | |
10240 | * more than one flip event at any time (or ensure that one flip message | |
10241 | * can be sent by waiting for flip-done prior to queueing new flips). | |
10242 | * Experimentation says that BCS works despite DERRMR masking all | |
10243 | * flip-done completion events and that unmasking all planes at once | |
10244 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
10245 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
10246 | */ | |
b5321f30 | 10247 | if (req->engine->id == RCS) { |
73dec95e TU |
10248 | *cs++ = MI_LOAD_REGISTER_IMM(1); |
10249 | *cs++ = i915_mmio_reg_offset(DERRMR); | |
10250 | *cs++ = ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
10251 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
10252 | DERRMR_PIPEC_PRI_FLIP_DONE); | |
5db94019 | 10253 | if (IS_GEN8(dev_priv)) |
73dec95e TU |
10254 | *cs++ = MI_STORE_REGISTER_MEM_GEN8 | |
10255 | MI_SRM_LRM_GLOBAL_GTT; | |
5a21b665 | 10256 | else |
73dec95e TU |
10257 | *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; |
10258 | *cs++ = i915_mmio_reg_offset(DERRMR); | |
10259 | *cs++ = i915_ggtt_offset(req->engine->scratch) + 256; | |
5db94019 | 10260 | if (IS_GEN8(dev_priv)) { |
73dec95e TU |
10261 | *cs++ = 0; |
10262 | *cs++ = MI_NOOP; | |
5a21b665 DV |
10263 | } |
10264 | } | |
10265 | ||
73dec95e TU |
10266 | *cs++ = MI_DISPLAY_FLIP_I915 | plane_bit; |
10267 | *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier); | |
10268 | *cs++ = intel_crtc->flip_work->gtt_offset; | |
10269 | *cs++ = MI_NOOP; | |
5a21b665 DV |
10270 | |
10271 | return 0; | |
10272 | } | |
10273 | ||
10274 | static bool use_mmio_flip(struct intel_engine_cs *engine, | |
10275 | struct drm_i915_gem_object *obj) | |
10276 | { | |
10277 | /* | |
10278 | * This is not being used for older platforms, because | |
10279 | * non-availability of flip done interrupt forces us to use | |
10280 | * CS flips. Older platforms derive flip done using some clever | |
10281 | * tricks involving the flip_pending status bits and vblank irqs. | |
10282 | * So using MMIO flips there would disrupt this mechanism. | |
10283 | */ | |
10284 | ||
10285 | if (engine == NULL) | |
10286 | return true; | |
10287 | ||
10288 | if (INTEL_GEN(engine->i915) < 5) | |
10289 | return false; | |
10290 | ||
10291 | if (i915.use_mmio_flip < 0) | |
10292 | return false; | |
10293 | else if (i915.use_mmio_flip > 0) | |
10294 | return true; | |
10295 | else if (i915.enable_execlists) | |
10296 | return true; | |
c37efb99 | 10297 | |
d07f0e59 | 10298 | return engine != i915_gem_object_last_write_engine(obj); |
5a21b665 DV |
10299 | } |
10300 | ||
10301 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, | |
10302 | unsigned int rotation, | |
10303 | struct intel_flip_work *work) | |
10304 | { | |
10305 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 10306 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
10307 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; |
10308 | const enum pipe pipe = intel_crtc->pipe; | |
d2196774 | 10309 | u32 ctl, stride = skl_plane_stride(fb, 0, rotation); |
5a21b665 DV |
10310 | |
10311 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
10312 | ctl &= ~PLANE_CTL_TILED_MASK; | |
bae781b2 | 10313 | switch (fb->modifier) { |
5a21b665 DV |
10314 | case DRM_FORMAT_MOD_NONE: |
10315 | break; | |
10316 | case I915_FORMAT_MOD_X_TILED: | |
10317 | ctl |= PLANE_CTL_TILED_X; | |
10318 | break; | |
10319 | case I915_FORMAT_MOD_Y_TILED: | |
10320 | ctl |= PLANE_CTL_TILED_Y; | |
10321 | break; | |
10322 | case I915_FORMAT_MOD_Yf_TILED: | |
10323 | ctl |= PLANE_CTL_TILED_YF; | |
10324 | break; | |
10325 | default: | |
bae781b2 | 10326 | MISSING_CASE(fb->modifier); |
5a21b665 DV |
10327 | } |
10328 | ||
5a21b665 DV |
10329 | /* |
10330 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
10331 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
10332 | */ | |
10333 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
10334 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
10335 | ||
10336 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); | |
10337 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
10338 | } | |
10339 | ||
10340 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, | |
10341 | struct intel_flip_work *work) | |
10342 | { | |
10343 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 10344 | struct drm_i915_private *dev_priv = to_i915(dev); |
72618ebf | 10345 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; |
5a21b665 DV |
10346 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); |
10347 | u32 dspcntr; | |
10348 | ||
10349 | dspcntr = I915_READ(reg); | |
10350 | ||
bae781b2 | 10351 | if (fb->modifier == I915_FORMAT_MOD_X_TILED) |
5a21b665 DV |
10352 | dspcntr |= DISPPLANE_TILED; |
10353 | else | |
10354 | dspcntr &= ~DISPPLANE_TILED; | |
10355 | ||
10356 | I915_WRITE(reg, dspcntr); | |
10357 | ||
10358 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); | |
10359 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
10360 | } | |
10361 | ||
10362 | static void intel_mmio_flip_work_func(struct work_struct *w) | |
10363 | { | |
10364 | struct intel_flip_work *work = | |
10365 | container_of(w, struct intel_flip_work, mmio_work); | |
10366 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); | |
10367 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
10368 | struct intel_framebuffer *intel_fb = | |
10369 | to_intel_framebuffer(crtc->base.primary->fb); | |
10370 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
10371 | ||
d07f0e59 | 10372 | WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0); |
5a21b665 DV |
10373 | |
10374 | intel_pipe_update_start(crtc); | |
10375 | ||
10376 | if (INTEL_GEN(dev_priv) >= 9) | |
10377 | skl_do_mmio_flip(crtc, work->rotation, work); | |
10378 | else | |
10379 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
10380 | ilk_do_mmio_flip(crtc, work); | |
10381 | ||
10382 | intel_pipe_update_end(crtc, work); | |
10383 | } | |
10384 | ||
10385 | static int intel_default_queue_flip(struct drm_device *dev, | |
10386 | struct drm_crtc *crtc, | |
10387 | struct drm_framebuffer *fb, | |
10388 | struct drm_i915_gem_object *obj, | |
10389 | struct drm_i915_gem_request *req, | |
10390 | uint32_t flags) | |
10391 | { | |
10392 | return -ENODEV; | |
10393 | } | |
10394 | ||
10395 | static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv, | |
10396 | struct intel_crtc *intel_crtc, | |
10397 | struct intel_flip_work *work) | |
10398 | { | |
10399 | u32 addr, vblank; | |
10400 | ||
10401 | if (!atomic_read(&work->pending)) | |
10402 | return false; | |
10403 | ||
10404 | smp_rmb(); | |
10405 | ||
10406 | vblank = intel_crtc_get_vblank_counter(intel_crtc); | |
10407 | if (work->flip_ready_vblank == 0) { | |
10408 | if (work->flip_queued_req && | |
f69a02c9 | 10409 | !i915_gem_request_completed(work->flip_queued_req)) |
5a21b665 DV |
10410 | return false; |
10411 | ||
10412 | work->flip_ready_vblank = vblank; | |
10413 | } | |
10414 | ||
10415 | if (vblank - work->flip_ready_vblank < 3) | |
10416 | return false; | |
10417 | ||
10418 | /* Potential stall - if we see that the flip has happened, | |
10419 | * assume a missed interrupt. */ | |
10420 | if (INTEL_GEN(dev_priv) >= 4) | |
10421 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
10422 | else | |
10423 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
10424 | ||
10425 | /* There is a potential issue here with a false positive after a flip | |
10426 | * to the same address. We could address this by checking for a | |
10427 | * non-incrementing frame counter. | |
10428 | */ | |
10429 | return addr == work->gtt_offset; | |
10430 | } | |
10431 | ||
10432 | void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe) | |
10433 | { | |
91c8a326 | 10434 | struct drm_device *dev = &dev_priv->drm; |
98187836 | 10435 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
5a21b665 DV |
10436 | struct intel_flip_work *work; |
10437 | ||
10438 | WARN_ON(!in_interrupt()); | |
10439 | ||
10440 | if (crtc == NULL) | |
10441 | return; | |
10442 | ||
10443 | spin_lock(&dev->event_lock); | |
e2af48c6 | 10444 | work = crtc->flip_work; |
5a21b665 DV |
10445 | |
10446 | if (work != NULL && !is_mmio_work(work) && | |
e2af48c6 | 10447 | __pageflip_stall_check_cs(dev_priv, crtc, work)) { |
5a21b665 DV |
10448 | WARN_ONCE(1, |
10449 | "Kicking stuck page flip: queued at %d, now %d\n", | |
e2af48c6 VS |
10450 | work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc)); |
10451 | page_flip_completed(crtc); | |
5a21b665 DV |
10452 | work = NULL; |
10453 | } | |
10454 | ||
10455 | if (work != NULL && !is_mmio_work(work) && | |
e2af48c6 | 10456 | intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1) |
5a21b665 DV |
10457 | intel_queue_rps_boost_for_request(work->flip_queued_req); |
10458 | spin_unlock(&dev->event_lock); | |
10459 | } | |
10460 | ||
4c01ded5 | 10461 | __maybe_unused |
5a21b665 DV |
10462 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
10463 | struct drm_framebuffer *fb, | |
10464 | struct drm_pending_vblank_event *event, | |
10465 | uint32_t page_flip_flags) | |
10466 | { | |
10467 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10468 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
10469 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
10470 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
10471 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10472 | struct drm_plane *primary = crtc->primary; | |
10473 | enum pipe pipe = intel_crtc->pipe; | |
10474 | struct intel_flip_work *work; | |
10475 | struct intel_engine_cs *engine; | |
10476 | bool mmio_flip; | |
8e637178 | 10477 | struct drm_i915_gem_request *request; |
058d88c4 | 10478 | struct i915_vma *vma; |
5a21b665 DV |
10479 | int ret; |
10480 | ||
10481 | /* | |
10482 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
10483 | * check to be safe. In the future we may enable pageflipping from | |
10484 | * a disabled primary plane. | |
10485 | */ | |
10486 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
10487 | return -EBUSY; | |
10488 | ||
10489 | /* Can't change pixel format via MI display flips. */ | |
dbd4d576 | 10490 | if (fb->format != crtc->primary->fb->format) |
5a21b665 DV |
10491 | return -EINVAL; |
10492 | ||
10493 | /* | |
10494 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
10495 | * Note that pitch changes could also affect these register. | |
10496 | */ | |
6315b5d3 | 10497 | if (INTEL_GEN(dev_priv) > 3 && |
5a21b665 DV |
10498 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
10499 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
10500 | return -EINVAL; | |
10501 | ||
10502 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
10503 | goto out_hang; | |
10504 | ||
10505 | work = kzalloc(sizeof(*work), GFP_KERNEL); | |
10506 | if (work == NULL) | |
10507 | return -ENOMEM; | |
10508 | ||
10509 | work->event = event; | |
10510 | work->crtc = crtc; | |
10511 | work->old_fb = old_fb; | |
10512 | INIT_WORK(&work->unpin_work, intel_unpin_work_fn); | |
10513 | ||
10514 | ret = drm_crtc_vblank_get(crtc); | |
10515 | if (ret) | |
10516 | goto free_work; | |
10517 | ||
10518 | /* We borrow the event spin lock for protecting flip_work */ | |
10519 | spin_lock_irq(&dev->event_lock); | |
10520 | if (intel_crtc->flip_work) { | |
10521 | /* Before declaring the flip queue wedged, check if | |
10522 | * the hardware completed the operation behind our backs. | |
10523 | */ | |
10524 | if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) { | |
10525 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
10526 | page_flip_completed(intel_crtc); | |
10527 | } else { | |
10528 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
10529 | spin_unlock_irq(&dev->event_lock); | |
10530 | ||
10531 | drm_crtc_vblank_put(crtc); | |
10532 | kfree(work); | |
10533 | return -EBUSY; | |
10534 | } | |
10535 | } | |
10536 | intel_crtc->flip_work = work; | |
10537 | spin_unlock_irq(&dev->event_lock); | |
10538 | ||
10539 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) | |
10540 | flush_workqueue(dev_priv->wq); | |
10541 | ||
10542 | /* Reference the objects for the scheduled work. */ | |
10543 | drm_framebuffer_reference(work->old_fb); | |
5a21b665 DV |
10544 | |
10545 | crtc->primary->fb = fb; | |
10546 | update_state_fb(crtc->primary); | |
faf68d92 | 10547 | |
25dc556a | 10548 | work->pending_flip_obj = i915_gem_object_get(obj); |
5a21b665 DV |
10549 | |
10550 | ret = i915_mutex_lock_interruptible(dev); | |
10551 | if (ret) | |
10552 | goto cleanup; | |
10553 | ||
8af29b0c CW |
10554 | intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error); |
10555 | if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) { | |
5a21b665 | 10556 | ret = -EIO; |
ddbb271a | 10557 | goto unlock; |
5a21b665 DV |
10558 | } |
10559 | ||
10560 | atomic_inc(&intel_crtc->unpin_work_count); | |
10561 | ||
9beb5fea | 10562 | if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
5a21b665 DV |
10563 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
10564 | ||
920a14b2 | 10565 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
3b3f1650 | 10566 | engine = dev_priv->engine[BCS]; |
bae781b2 | 10567 | if (fb->modifier != old_fb->modifier) |
5a21b665 DV |
10568 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
10569 | engine = NULL; | |
fd6b8f43 | 10570 | } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) { |
3b3f1650 | 10571 | engine = dev_priv->engine[BCS]; |
6315b5d3 | 10572 | } else if (INTEL_GEN(dev_priv) >= 7) { |
d07f0e59 | 10573 | engine = i915_gem_object_last_write_engine(obj); |
5a21b665 | 10574 | if (engine == NULL || engine->id != RCS) |
3b3f1650 | 10575 | engine = dev_priv->engine[BCS]; |
5a21b665 | 10576 | } else { |
3b3f1650 | 10577 | engine = dev_priv->engine[RCS]; |
5a21b665 DV |
10578 | } |
10579 | ||
10580 | mmio_flip = use_mmio_flip(engine, obj); | |
10581 | ||
058d88c4 CW |
10582 | vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation); |
10583 | if (IS_ERR(vma)) { | |
10584 | ret = PTR_ERR(vma); | |
5a21b665 | 10585 | goto cleanup_pending; |
058d88c4 | 10586 | } |
5a21b665 | 10587 | |
be1e3415 CW |
10588 | work->old_vma = to_intel_plane_state(primary->state)->vma; |
10589 | to_intel_plane_state(primary->state)->vma = vma; | |
10590 | ||
10591 | work->gtt_offset = i915_ggtt_offset(vma) + intel_crtc->dspaddr_offset; | |
5a21b665 DV |
10592 | work->rotation = crtc->primary->state->rotation; |
10593 | ||
1f061316 PZ |
10594 | /* |
10595 | * There's the potential that the next frame will not be compatible with | |
10596 | * FBC, so we want to call pre_update() before the actual page flip. | |
10597 | * The problem is that pre_update() caches some information about the fb | |
10598 | * object, so we want to do this only after the object is pinned. Let's | |
10599 | * be on the safe side and do this immediately before scheduling the | |
10600 | * flip. | |
10601 | */ | |
10602 | intel_fbc_pre_update(intel_crtc, intel_crtc->config, | |
10603 | to_intel_plane_state(primary->state)); | |
10604 | ||
5a21b665 DV |
10605 | if (mmio_flip) { |
10606 | INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func); | |
6277c8d0 | 10607 | queue_work(system_unbound_wq, &work->mmio_work); |
5a21b665 | 10608 | } else { |
e8a9c58f CW |
10609 | request = i915_gem_request_alloc(engine, |
10610 | dev_priv->kernel_context); | |
8e637178 CW |
10611 | if (IS_ERR(request)) { |
10612 | ret = PTR_ERR(request); | |
10613 | goto cleanup_unpin; | |
10614 | } | |
10615 | ||
a2bc4695 | 10616 | ret = i915_gem_request_await_object(request, obj, false); |
8e637178 CW |
10617 | if (ret) |
10618 | goto cleanup_request; | |
10619 | ||
5a21b665 DV |
10620 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, |
10621 | page_flip_flags); | |
10622 | if (ret) | |
8e637178 | 10623 | goto cleanup_request; |
5a21b665 DV |
10624 | |
10625 | intel_mark_page_flip_active(intel_crtc, work); | |
10626 | ||
8e637178 | 10627 | work->flip_queued_req = i915_gem_request_get(request); |
5a21b665 DV |
10628 | i915_add_request_no_flush(request); |
10629 | } | |
10630 | ||
92117f0b | 10631 | i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); |
5a21b665 DV |
10632 | i915_gem_track_fb(intel_fb_obj(old_fb), obj, |
10633 | to_intel_plane(primary)->frontbuffer_bit); | |
10634 | mutex_unlock(&dev->struct_mutex); | |
10635 | ||
5748b6a1 | 10636 | intel_frontbuffer_flip_prepare(to_i915(dev), |
5a21b665 DV |
10637 | to_intel_plane(primary)->frontbuffer_bit); |
10638 | ||
10639 | trace_i915_flip_request(intel_crtc->plane, obj); | |
10640 | ||
10641 | return 0; | |
10642 | ||
8e637178 CW |
10643 | cleanup_request: |
10644 | i915_add_request_no_flush(request); | |
5a21b665 | 10645 | cleanup_unpin: |
be1e3415 CW |
10646 | to_intel_plane_state(primary->state)->vma = work->old_vma; |
10647 | intel_unpin_fb_vma(vma); | |
5a21b665 | 10648 | cleanup_pending: |
5a21b665 | 10649 | atomic_dec(&intel_crtc->unpin_work_count); |
ddbb271a | 10650 | unlock: |
5a21b665 DV |
10651 | mutex_unlock(&dev->struct_mutex); |
10652 | cleanup: | |
10653 | crtc->primary->fb = old_fb; | |
10654 | update_state_fb(crtc->primary); | |
10655 | ||
f0cd5182 | 10656 | i915_gem_object_put(obj); |
5a21b665 DV |
10657 | drm_framebuffer_unreference(work->old_fb); |
10658 | ||
10659 | spin_lock_irq(&dev->event_lock); | |
10660 | intel_crtc->flip_work = NULL; | |
10661 | spin_unlock_irq(&dev->event_lock); | |
10662 | ||
10663 | drm_crtc_vblank_put(crtc); | |
10664 | free_work: | |
10665 | kfree(work); | |
10666 | ||
10667 | if (ret == -EIO) { | |
10668 | struct drm_atomic_state *state; | |
10669 | struct drm_plane_state *plane_state; | |
10670 | ||
10671 | out_hang: | |
10672 | state = drm_atomic_state_alloc(dev); | |
10673 | if (!state) | |
10674 | return -ENOMEM; | |
10675 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
10676 | ||
10677 | retry: | |
10678 | plane_state = drm_atomic_get_plane_state(state, primary); | |
10679 | ret = PTR_ERR_OR_ZERO(plane_state); | |
10680 | if (!ret) { | |
10681 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10682 | ||
10683 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
10684 | if (!ret) | |
10685 | ret = drm_atomic_commit(state); | |
10686 | } | |
10687 | ||
10688 | if (ret == -EDEADLK) { | |
10689 | drm_modeset_backoff(state->acquire_ctx); | |
10690 | drm_atomic_state_clear(state); | |
10691 | goto retry; | |
10692 | } | |
10693 | ||
0853695c | 10694 | drm_atomic_state_put(state); |
5a21b665 DV |
10695 | |
10696 | if (ret == 0 && event) { | |
10697 | spin_lock_irq(&dev->event_lock); | |
10698 | drm_crtc_send_vblank_event(crtc, event); | |
10699 | spin_unlock_irq(&dev->event_lock); | |
10700 | } | |
10701 | } | |
10702 | return ret; | |
10703 | } | |
10704 | ||
10705 | ||
10706 | /** | |
10707 | * intel_wm_need_update - Check whether watermarks need updating | |
10708 | * @plane: drm plane | |
10709 | * @state: new plane state | |
10710 | * | |
10711 | * Check current plane state versus the new one to determine whether | |
10712 | * watermarks need to be recalculated. | |
10713 | * | |
10714 | * Returns true or false. | |
10715 | */ | |
10716 | static bool intel_wm_need_update(struct drm_plane *plane, | |
10717 | struct drm_plane_state *state) | |
10718 | { | |
10719 | struct intel_plane_state *new = to_intel_plane_state(state); | |
10720 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
10721 | ||
10722 | /* Update watermarks on tiling or size changes. */ | |
936e71e3 | 10723 | if (new->base.visible != cur->base.visible) |
5a21b665 DV |
10724 | return true; |
10725 | ||
10726 | if (!cur->base.fb || !new->base.fb) | |
10727 | return false; | |
10728 | ||
bae781b2 | 10729 | if (cur->base.fb->modifier != new->base.fb->modifier || |
5a21b665 | 10730 | cur->base.rotation != new->base.rotation || |
936e71e3 VS |
10731 | drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) || |
10732 | drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) || | |
10733 | drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) || | |
10734 | drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst)) | |
5a21b665 DV |
10735 | return true; |
10736 | ||
10737 | return false; | |
10738 | } | |
10739 | ||
10740 | static bool needs_scaling(struct intel_plane_state *state) | |
10741 | { | |
936e71e3 VS |
10742 | int src_w = drm_rect_width(&state->base.src) >> 16; |
10743 | int src_h = drm_rect_height(&state->base.src) >> 16; | |
10744 | int dst_w = drm_rect_width(&state->base.dst); | |
10745 | int dst_h = drm_rect_height(&state->base.dst); | |
5a21b665 DV |
10746 | |
10747 | return (src_w != dst_w || src_h != dst_h); | |
10748 | } | |
d21fbe87 | 10749 | |
da20eabd ML |
10750 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
10751 | struct drm_plane_state *plane_state) | |
10752 | { | |
ab1d3a0e | 10753 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
10754 | struct drm_crtc *crtc = crtc_state->crtc; |
10755 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10756 | struct drm_plane *plane = plane_state->plane; | |
10757 | struct drm_device *dev = crtc->dev; | |
ed4a6a7c | 10758 | struct drm_i915_private *dev_priv = to_i915(dev); |
da20eabd ML |
10759 | struct intel_plane_state *old_plane_state = |
10760 | to_intel_plane_state(plane->state); | |
da20eabd ML |
10761 | bool mode_changed = needs_modeset(crtc_state); |
10762 | bool was_crtc_enabled = crtc->state->active; | |
10763 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
10764 | bool turn_off, turn_on, visible, was_visible; |
10765 | struct drm_framebuffer *fb = plane_state->fb; | |
78108b7c | 10766 | int ret; |
da20eabd | 10767 | |
55b8f2a7 | 10768 | if (INTEL_GEN(dev_priv) >= 9 && plane->type != DRM_PLANE_TYPE_CURSOR) { |
da20eabd ML |
10769 | ret = skl_update_scaler_plane( |
10770 | to_intel_crtc_state(crtc_state), | |
10771 | to_intel_plane_state(plane_state)); | |
10772 | if (ret) | |
10773 | return ret; | |
10774 | } | |
10775 | ||
936e71e3 | 10776 | was_visible = old_plane_state->base.visible; |
1d4258db | 10777 | visible = plane_state->visible; |
da20eabd ML |
10778 | |
10779 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
10780 | was_visible = false; | |
10781 | ||
35c08f43 ML |
10782 | /* |
10783 | * Visibility is calculated as if the crtc was on, but | |
10784 | * after scaler setup everything depends on it being off | |
10785 | * when the crtc isn't active. | |
f818ffea VS |
10786 | * |
10787 | * FIXME this is wrong for watermarks. Watermarks should also | |
10788 | * be computed as if the pipe would be active. Perhaps move | |
10789 | * per-plane wm computation to the .check_plane() hook, and | |
10790 | * only combine the results from all planes in the current place? | |
35c08f43 ML |
10791 | */ |
10792 | if (!is_crtc_enabled) | |
1d4258db | 10793 | plane_state->visible = visible = false; |
da20eabd ML |
10794 | |
10795 | if (!was_visible && !visible) | |
10796 | return 0; | |
10797 | ||
e8861675 ML |
10798 | if (fb != old_plane_state->base.fb) |
10799 | pipe_config->fb_changed = true; | |
10800 | ||
da20eabd ML |
10801 | turn_off = was_visible && (!visible || mode_changed); |
10802 | turn_on = visible && (!was_visible || mode_changed); | |
10803 | ||
72660ce0 | 10804 | DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n", |
78108b7c VS |
10805 | intel_crtc->base.base.id, |
10806 | intel_crtc->base.name, | |
72660ce0 VS |
10807 | plane->base.id, plane->name, |
10808 | fb ? fb->base.id : -1); | |
da20eabd | 10809 | |
72660ce0 VS |
10810 | DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n", |
10811 | plane->base.id, plane->name, | |
10812 | was_visible, visible, | |
da20eabd ML |
10813 | turn_off, turn_on, mode_changed); |
10814 | ||
caed361d VS |
10815 | if (turn_on) { |
10816 | pipe_config->update_wm_pre = true; | |
10817 | ||
10818 | /* must disable cxsr around plane enable/disable */ | |
10819 | if (plane->type != DRM_PLANE_TYPE_CURSOR) | |
10820 | pipe_config->disable_cxsr = true; | |
10821 | } else if (turn_off) { | |
10822 | pipe_config->update_wm_post = true; | |
92826fcd | 10823 | |
852eb00d | 10824 | /* must disable cxsr around plane enable/disable */ |
e8861675 | 10825 | if (plane->type != DRM_PLANE_TYPE_CURSOR) |
ab1d3a0e | 10826 | pipe_config->disable_cxsr = true; |
852eb00d | 10827 | } else if (intel_wm_need_update(plane, plane_state)) { |
caed361d VS |
10828 | /* FIXME bollocks */ |
10829 | pipe_config->update_wm_pre = true; | |
10830 | pipe_config->update_wm_post = true; | |
852eb00d | 10831 | } |
da20eabd | 10832 | |
ed4a6a7c | 10833 | /* Pre-gen9 platforms need two-step watermark updates */ |
caed361d | 10834 | if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) && |
6315b5d3 | 10835 | INTEL_GEN(dev_priv) < 9 && dev_priv->display.optimize_watermarks) |
ed4a6a7c MR |
10836 | to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true; |
10837 | ||
8be6ca85 | 10838 | if (visible || was_visible) |
cd202f69 | 10839 | pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit; |
a9ff8714 | 10840 | |
31ae71fc ML |
10841 | /* |
10842 | * WaCxSRDisabledForSpriteScaling:ivb | |
10843 | * | |
10844 | * cstate->update_wm was already set above, so this flag will | |
10845 | * take effect when we commit and program watermarks. | |
10846 | */ | |
fd6b8f43 | 10847 | if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev_priv) && |
31ae71fc ML |
10848 | needs_scaling(to_intel_plane_state(plane_state)) && |
10849 | !needs_scaling(old_plane_state)) | |
10850 | pipe_config->disable_lp_wm = true; | |
d21fbe87 | 10851 | |
da20eabd ML |
10852 | return 0; |
10853 | } | |
10854 | ||
6d3a1ce7 ML |
10855 | static bool encoders_cloneable(const struct intel_encoder *a, |
10856 | const struct intel_encoder *b) | |
10857 | { | |
10858 | /* masks could be asymmetric, so check both ways */ | |
10859 | return a == b || (a->cloneable & (1 << b->type) && | |
10860 | b->cloneable & (1 << a->type)); | |
10861 | } | |
10862 | ||
10863 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
10864 | struct intel_crtc *crtc, | |
10865 | struct intel_encoder *encoder) | |
10866 | { | |
10867 | struct intel_encoder *source_encoder; | |
10868 | struct drm_connector *connector; | |
10869 | struct drm_connector_state *connector_state; | |
10870 | int i; | |
10871 | ||
10872 | for_each_connector_in_state(state, connector, connector_state, i) { | |
10873 | if (connector_state->crtc != &crtc->base) | |
10874 | continue; | |
10875 | ||
10876 | source_encoder = | |
10877 | to_intel_encoder(connector_state->best_encoder); | |
10878 | if (!encoders_cloneable(encoder, source_encoder)) | |
10879 | return false; | |
10880 | } | |
10881 | ||
10882 | return true; | |
10883 | } | |
10884 | ||
6d3a1ce7 ML |
10885 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, |
10886 | struct drm_crtc_state *crtc_state) | |
10887 | { | |
cf5a15be | 10888 | struct drm_device *dev = crtc->dev; |
fac5e23e | 10889 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d3a1ce7 | 10890 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
10891 | struct intel_crtc_state *pipe_config = |
10892 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 10893 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 10894 | int ret; |
6d3a1ce7 ML |
10895 | bool mode_changed = needs_modeset(crtc_state); |
10896 | ||
852eb00d | 10897 | if (mode_changed && !crtc_state->active) |
caed361d | 10898 | pipe_config->update_wm_post = true; |
eddfcbcd | 10899 | |
ad421372 ML |
10900 | if (mode_changed && crtc_state->enable && |
10901 | dev_priv->display.crtc_compute_clock && | |
8106ddbd | 10902 | !WARN_ON(pipe_config->shared_dpll)) { |
ad421372 ML |
10903 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
10904 | pipe_config); | |
10905 | if (ret) | |
10906 | return ret; | |
10907 | } | |
10908 | ||
82cf435b LL |
10909 | if (crtc_state->color_mgmt_changed) { |
10910 | ret = intel_color_check(crtc, crtc_state); | |
10911 | if (ret) | |
10912 | return ret; | |
e7852a4b LL |
10913 | |
10914 | /* | |
10915 | * Changing color management on Intel hardware is | |
10916 | * handled as part of planes update. | |
10917 | */ | |
10918 | crtc_state->planes_changed = true; | |
82cf435b LL |
10919 | } |
10920 | ||
e435d6e5 | 10921 | ret = 0; |
86c8bbbe | 10922 | if (dev_priv->display.compute_pipe_wm) { |
e3bddded | 10923 | ret = dev_priv->display.compute_pipe_wm(pipe_config); |
ed4a6a7c MR |
10924 | if (ret) { |
10925 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
10926 | return ret; | |
10927 | } | |
10928 | } | |
10929 | ||
10930 | if (dev_priv->display.compute_intermediate_wm && | |
10931 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
10932 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
10933 | return 0; | |
10934 | ||
10935 | /* | |
10936 | * Calculate 'intermediate' watermarks that satisfy both the | |
10937 | * old state and the new state. We can program these | |
10938 | * immediately. | |
10939 | */ | |
6315b5d3 | 10940 | ret = dev_priv->display.compute_intermediate_wm(dev, |
ed4a6a7c MR |
10941 | intel_crtc, |
10942 | pipe_config); | |
10943 | if (ret) { | |
10944 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 10945 | return ret; |
ed4a6a7c | 10946 | } |
e3d5457c VS |
10947 | } else if (dev_priv->display.compute_intermediate_wm) { |
10948 | if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9) | |
10949 | pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; | |
86c8bbbe MR |
10950 | } |
10951 | ||
6315b5d3 | 10952 | if (INTEL_GEN(dev_priv) >= 9) { |
e435d6e5 ML |
10953 | if (mode_changed) |
10954 | ret = skl_update_scaler_crtc(pipe_config); | |
10955 | ||
10956 | if (!ret) | |
6ebc6923 | 10957 | ret = intel_atomic_setup_scalers(dev_priv, intel_crtc, |
e435d6e5 ML |
10958 | pipe_config); |
10959 | } | |
10960 | ||
10961 | return ret; | |
6d3a1ce7 ML |
10962 | } |
10963 | ||
65b38e0d | 10964 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 | 10965 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
5a21b665 DV |
10966 | .atomic_begin = intel_begin_crtc_commit, |
10967 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 10968 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
10969 | }; |
10970 | ||
d29b2f9d ACO |
10971 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
10972 | { | |
10973 | struct intel_connector *connector; | |
10974 | ||
10975 | for_each_intel_connector(dev, connector) { | |
8863dc7f DV |
10976 | if (connector->base.state->crtc) |
10977 | drm_connector_unreference(&connector->base); | |
10978 | ||
d29b2f9d ACO |
10979 | if (connector->base.encoder) { |
10980 | connector->base.state->best_encoder = | |
10981 | connector->base.encoder; | |
10982 | connector->base.state->crtc = | |
10983 | connector->base.encoder->crtc; | |
8863dc7f DV |
10984 | |
10985 | drm_connector_reference(&connector->base); | |
d29b2f9d ACO |
10986 | } else { |
10987 | connector->base.state->best_encoder = NULL; | |
10988 | connector->base.state->crtc = NULL; | |
10989 | } | |
10990 | } | |
10991 | } | |
10992 | ||
050f7aeb | 10993 | static void |
eba905b2 | 10994 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 10995 | struct intel_crtc_state *pipe_config) |
050f7aeb | 10996 | { |
6a2a5c5d | 10997 | const struct drm_display_info *info = &connector->base.display_info; |
050f7aeb DV |
10998 | int bpp = pipe_config->pipe_bpp; |
10999 | ||
11000 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
6a2a5c5d VS |
11001 | connector->base.base.id, |
11002 | connector->base.name); | |
050f7aeb DV |
11003 | |
11004 | /* Don't use an invalid EDID bpc value */ | |
6a2a5c5d | 11005 | if (info->bpc != 0 && info->bpc * 3 < bpp) { |
050f7aeb | 11006 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", |
6a2a5c5d VS |
11007 | bpp, info->bpc * 3); |
11008 | pipe_config->pipe_bpp = info->bpc * 3; | |
050f7aeb DV |
11009 | } |
11010 | ||
196f954e | 11011 | /* Clamp bpp to 8 on screens without EDID 1.4 */ |
6a2a5c5d | 11012 | if (info->bpc == 0 && bpp > 24) { |
196f954e MK |
11013 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", |
11014 | bpp); | |
11015 | pipe_config->pipe_bpp = 24; | |
050f7aeb DV |
11016 | } |
11017 | } | |
11018 | ||
4e53c2e0 | 11019 | static int |
050f7aeb | 11020 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 11021 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 11022 | { |
9beb5fea | 11023 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1486017f | 11024 | struct drm_atomic_state *state; |
da3ced29 ACO |
11025 | struct drm_connector *connector; |
11026 | struct drm_connector_state *connector_state; | |
1486017f | 11027 | int bpp, i; |
4e53c2e0 | 11028 | |
9beb5fea TU |
11029 | if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
11030 | IS_CHERRYVIEW(dev_priv))) | |
4e53c2e0 | 11031 | bpp = 10*3; |
9beb5fea | 11032 | else if (INTEL_GEN(dev_priv) >= 5) |
d328c9d7 DV |
11033 | bpp = 12*3; |
11034 | else | |
11035 | bpp = 8*3; | |
11036 | ||
4e53c2e0 | 11037 | |
4e53c2e0 DV |
11038 | pipe_config->pipe_bpp = bpp; |
11039 | ||
1486017f ACO |
11040 | state = pipe_config->base.state; |
11041 | ||
4e53c2e0 | 11042 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
11043 | for_each_connector_in_state(state, connector, connector_state, i) { |
11044 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
11045 | continue; |
11046 | ||
da3ced29 ACO |
11047 | connected_sink_compute_bpp(to_intel_connector(connector), |
11048 | pipe_config); | |
4e53c2e0 DV |
11049 | } |
11050 | ||
11051 | return bpp; | |
11052 | } | |
11053 | ||
644db711 DV |
11054 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
11055 | { | |
11056 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
11057 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 11058 | mode->crtc_clock, |
644db711 DV |
11059 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
11060 | mode->crtc_hsync_end, mode->crtc_htotal, | |
11061 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
11062 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
11063 | } | |
11064 | ||
f6982332 TU |
11065 | static inline void |
11066 | intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id, | |
a4309657 | 11067 | unsigned int lane_count, struct intel_link_m_n *m_n) |
f6982332 | 11068 | { |
a4309657 TU |
11069 | DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
11070 | id, lane_count, | |
f6982332 TU |
11071 | m_n->gmch_m, m_n->gmch_n, |
11072 | m_n->link_m, m_n->link_n, m_n->tu); | |
11073 | } | |
11074 | ||
c0b03411 | 11075 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 11076 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
11077 | const char *context) |
11078 | { | |
6a60cd87 | 11079 | struct drm_device *dev = crtc->base.dev; |
4f8036a2 | 11080 | struct drm_i915_private *dev_priv = to_i915(dev); |
6a60cd87 CK |
11081 | struct drm_plane *plane; |
11082 | struct intel_plane *intel_plane; | |
11083 | struct intel_plane_state *state; | |
11084 | struct drm_framebuffer *fb; | |
11085 | ||
66766e4f TU |
11086 | DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n", |
11087 | crtc->base.base.id, crtc->base.name, context); | |
c0b03411 | 11088 | |
2c89429e TU |
11089 | DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", |
11090 | transcoder_name(pipe_config->cpu_transcoder), | |
c0b03411 | 11091 | pipe_config->pipe_bpp, pipe_config->dither); |
a4309657 TU |
11092 | |
11093 | if (pipe_config->has_pch_encoder) | |
11094 | intel_dump_m_n_config(pipe_config, "fdi", | |
11095 | pipe_config->fdi_lanes, | |
11096 | &pipe_config->fdi_m_n); | |
f6982332 TU |
11097 | |
11098 | if (intel_crtc_has_dp_encoder(pipe_config)) { | |
a4309657 TU |
11099 | intel_dump_m_n_config(pipe_config, "dp m_n", |
11100 | pipe_config->lane_count, &pipe_config->dp_m_n); | |
d806e682 TU |
11101 | if (pipe_config->has_drrs) |
11102 | intel_dump_m_n_config(pipe_config, "dp m2_n2", | |
11103 | pipe_config->lane_count, | |
11104 | &pipe_config->dp_m2_n2); | |
f6982332 | 11105 | } |
b95af8be | 11106 | |
55072d19 | 11107 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
2c89429e | 11108 | pipe_config->has_audio, pipe_config->has_infoframe); |
55072d19 | 11109 | |
c0b03411 | 11110 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 11111 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 11112 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
11113 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
11114 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
a7d1b3f4 | 11115 | DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n", |
2c89429e | 11116 | pipe_config->port_clock, |
a7d1b3f4 VS |
11117 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
11118 | pipe_config->pixel_rate); | |
dd2f616d TU |
11119 | |
11120 | if (INTEL_GEN(dev_priv) >= 9) | |
11121 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", | |
11122 | crtc->num_scalers, | |
11123 | pipe_config->scaler_state.scaler_users, | |
11124 | pipe_config->scaler_state.scaler_id); | |
a74f8375 TU |
11125 | |
11126 | if (HAS_GMCH_DISPLAY(dev_priv)) | |
11127 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", | |
11128 | pipe_config->gmch_pfit.control, | |
11129 | pipe_config->gmch_pfit.pgm_ratios, | |
11130 | pipe_config->gmch_pfit.lvds_border_bits); | |
11131 | else | |
11132 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", | |
11133 | pipe_config->pch_pfit.pos, | |
11134 | pipe_config->pch_pfit.size, | |
08c4d7fc | 11135 | enableddisabled(pipe_config->pch_pfit.enabled)); |
a74f8375 | 11136 | |
2c89429e TU |
11137 | DRM_DEBUG_KMS("ips: %i, double wide: %i\n", |
11138 | pipe_config->ips_enabled, pipe_config->double_wide); | |
6a60cd87 | 11139 | |
f50b79f0 | 11140 | intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state); |
415ff0f6 | 11141 | |
6a60cd87 CK |
11142 | DRM_DEBUG_KMS("planes on this crtc\n"); |
11143 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
b3c11ac2 | 11144 | struct drm_format_name_buf format_name; |
6a60cd87 CK |
11145 | intel_plane = to_intel_plane(plane); |
11146 | if (intel_plane->pipe != crtc->pipe) | |
11147 | continue; | |
11148 | ||
11149 | state = to_intel_plane_state(plane->state); | |
11150 | fb = state->base.fb; | |
11151 | if (!fb) { | |
1d577e02 VS |
11152 | DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n", |
11153 | plane->base.id, plane->name, state->scaler_id); | |
6a60cd87 CK |
11154 | continue; |
11155 | } | |
11156 | ||
dd2f616d TU |
11157 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n", |
11158 | plane->base.id, plane->name, | |
b3c11ac2 | 11159 | fb->base.id, fb->width, fb->height, |
438b74a5 | 11160 | drm_get_format_name(fb->format->format, &format_name)); |
dd2f616d TU |
11161 | if (INTEL_GEN(dev_priv) >= 9) |
11162 | DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n", | |
11163 | state->scaler_id, | |
11164 | state->base.src.x1 >> 16, | |
11165 | state->base.src.y1 >> 16, | |
11166 | drm_rect_width(&state->base.src) >> 16, | |
11167 | drm_rect_height(&state->base.src) >> 16, | |
11168 | state->base.dst.x1, state->base.dst.y1, | |
11169 | drm_rect_width(&state->base.dst), | |
11170 | drm_rect_height(&state->base.dst)); | |
6a60cd87 | 11171 | } |
c0b03411 DV |
11172 | } |
11173 | ||
5448a00d | 11174 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 11175 | { |
5448a00d | 11176 | struct drm_device *dev = state->dev; |
da3ced29 | 11177 | struct drm_connector *connector; |
00f0b378 | 11178 | unsigned int used_ports = 0; |
477321e0 | 11179 | unsigned int used_mst_ports = 0; |
00f0b378 VS |
11180 | |
11181 | /* | |
11182 | * Walk the connector list instead of the encoder | |
11183 | * list to detect the problem on ddi platforms | |
11184 | * where there's just one encoder per digital port. | |
11185 | */ | |
0bff4858 VS |
11186 | drm_for_each_connector(connector, dev) { |
11187 | struct drm_connector_state *connector_state; | |
11188 | struct intel_encoder *encoder; | |
11189 | ||
11190 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
11191 | if (!connector_state) | |
11192 | connector_state = connector->state; | |
11193 | ||
5448a00d | 11194 | if (!connector_state->best_encoder) |
00f0b378 VS |
11195 | continue; |
11196 | ||
5448a00d ACO |
11197 | encoder = to_intel_encoder(connector_state->best_encoder); |
11198 | ||
11199 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
11200 | |
11201 | switch (encoder->type) { | |
11202 | unsigned int port_mask; | |
11203 | case INTEL_OUTPUT_UNKNOWN: | |
4f8036a2 | 11204 | if (WARN_ON(!HAS_DDI(to_i915(dev)))) |
00f0b378 | 11205 | break; |
cca0502b | 11206 | case INTEL_OUTPUT_DP: |
00f0b378 VS |
11207 | case INTEL_OUTPUT_HDMI: |
11208 | case INTEL_OUTPUT_EDP: | |
11209 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
11210 | ||
11211 | /* the same port mustn't appear more than once */ | |
11212 | if (used_ports & port_mask) | |
11213 | return false; | |
11214 | ||
11215 | used_ports |= port_mask; | |
477321e0 VS |
11216 | break; |
11217 | case INTEL_OUTPUT_DP_MST: | |
11218 | used_mst_ports |= | |
11219 | 1 << enc_to_mst(&encoder->base)->primary->port; | |
11220 | break; | |
00f0b378 VS |
11221 | default: |
11222 | break; | |
11223 | } | |
11224 | } | |
11225 | ||
477321e0 VS |
11226 | /* can't mix MST and SST/HDMI on the same port */ |
11227 | if (used_ports & used_mst_ports) | |
11228 | return false; | |
11229 | ||
00f0b378 VS |
11230 | return true; |
11231 | } | |
11232 | ||
83a57153 ACO |
11233 | static void |
11234 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
11235 | { | |
11236 | struct drm_crtc_state tmp_state; | |
663a3640 | 11237 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 | 11238 | struct intel_dpll_hw_state dpll_hw_state; |
8106ddbd | 11239 | struct intel_shared_dpll *shared_dpll; |
c4e2d043 | 11240 | bool force_thru; |
83a57153 | 11241 | |
7546a384 ACO |
11242 | /* FIXME: before the switch to atomic started, a new pipe_config was |
11243 | * kzalloc'd. Code that depends on any field being zero should be | |
11244 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
11245 | * only fields that are know to not cause problems are preserved. */ | |
11246 | ||
83a57153 | 11247 | tmp_state = crtc_state->base; |
663a3640 | 11248 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
11249 | shared_dpll = crtc_state->shared_dpll; |
11250 | dpll_hw_state = crtc_state->dpll_hw_state; | |
c4e2d043 | 11251 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 11252 | |
83a57153 | 11253 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 11254 | |
83a57153 | 11255 | crtc_state->base = tmp_state; |
663a3640 | 11256 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
11257 | crtc_state->shared_dpll = shared_dpll; |
11258 | crtc_state->dpll_hw_state = dpll_hw_state; | |
c4e2d043 | 11259 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
11260 | } |
11261 | ||
548ee15b | 11262 | static int |
b8cecdf5 | 11263 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 11264 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 11265 | { |
b359283a | 11266 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 11267 | struct intel_encoder *encoder; |
da3ced29 | 11268 | struct drm_connector *connector; |
0b901879 | 11269 | struct drm_connector_state *connector_state; |
d328c9d7 | 11270 | int base_bpp, ret = -EINVAL; |
0b901879 | 11271 | int i; |
e29c22c0 | 11272 | bool retry = true; |
ee7b9f93 | 11273 | |
83a57153 | 11274 | clear_intel_crtc_state(pipe_config); |
7758a113 | 11275 | |
e143a21c DV |
11276 | pipe_config->cpu_transcoder = |
11277 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 11278 | |
2960bc9c ID |
11279 | /* |
11280 | * Sanitize sync polarity flags based on requested ones. If neither | |
11281 | * positive or negative polarity is requested, treat this as meaning | |
11282 | * negative polarity. | |
11283 | */ | |
2d112de7 | 11284 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 11285 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 11286 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 11287 | |
2d112de7 | 11288 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 11289 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 11290 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 11291 | |
d328c9d7 DV |
11292 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
11293 | pipe_config); | |
11294 | if (base_bpp < 0) | |
4e53c2e0 DV |
11295 | goto fail; |
11296 | ||
e41a56be VS |
11297 | /* |
11298 | * Determine the real pipe dimensions. Note that stereo modes can | |
11299 | * increase the actual pipe size due to the frame doubling and | |
11300 | * insertion of additional space for blanks between the frame. This | |
11301 | * is stored in the crtc timings. We use the requested mode to do this | |
11302 | * computation to clearly distinguish it from the adjusted mode, which | |
11303 | * can be changed by the connectors in the below retry loop. | |
11304 | */ | |
196cd5d3 | 11305 | drm_mode_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
11306 | &pipe_config->pipe_src_w, |
11307 | &pipe_config->pipe_src_h); | |
e41a56be | 11308 | |
253c84c8 VS |
11309 | for_each_connector_in_state(state, connector, connector_state, i) { |
11310 | if (connector_state->crtc != crtc) | |
11311 | continue; | |
11312 | ||
11313 | encoder = to_intel_encoder(connector_state->best_encoder); | |
11314 | ||
e25148d0 VS |
11315 | if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) { |
11316 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
11317 | goto fail; | |
11318 | } | |
11319 | ||
253c84c8 VS |
11320 | /* |
11321 | * Determine output_types before calling the .compute_config() | |
11322 | * hooks so that the hooks can use this information safely. | |
11323 | */ | |
11324 | pipe_config->output_types |= 1 << encoder->type; | |
11325 | } | |
11326 | ||
e29c22c0 | 11327 | encoder_retry: |
ef1b460d | 11328 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 11329 | pipe_config->port_clock = 0; |
ef1b460d | 11330 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 11331 | |
135c81b8 | 11332 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
11333 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
11334 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 11335 | |
7758a113 DV |
11336 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
11337 | * adjust it according to limitations or connector properties, and also | |
11338 | * a chance to reject the mode entirely. | |
47f1c6c9 | 11339 | */ |
da3ced29 | 11340 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 11341 | if (connector_state->crtc != crtc) |
7758a113 | 11342 | continue; |
7ae89233 | 11343 | |
0b901879 ACO |
11344 | encoder = to_intel_encoder(connector_state->best_encoder); |
11345 | ||
0a478c27 | 11346 | if (!(encoder->compute_config(encoder, pipe_config, connector_state))) { |
efea6e8e | 11347 | DRM_DEBUG_KMS("Encoder config failure\n"); |
7758a113 DV |
11348 | goto fail; |
11349 | } | |
ee7b9f93 | 11350 | } |
47f1c6c9 | 11351 | |
ff9a6750 DV |
11352 | /* Set default port clock if not overwritten by the encoder. Needs to be |
11353 | * done afterwards in case the encoder adjusts the mode. */ | |
11354 | if (!pipe_config->port_clock) | |
2d112de7 | 11355 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 11356 | * pipe_config->pixel_multiplier; |
ff9a6750 | 11357 | |
a43f6e0f | 11358 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 11359 | if (ret < 0) { |
7758a113 DV |
11360 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
11361 | goto fail; | |
ee7b9f93 | 11362 | } |
e29c22c0 DV |
11363 | |
11364 | if (ret == RETRY) { | |
11365 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
11366 | ret = -EINVAL; | |
11367 | goto fail; | |
11368 | } | |
11369 | ||
11370 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
11371 | retry = false; | |
11372 | goto encoder_retry; | |
11373 | } | |
11374 | ||
e8fa4270 | 11375 | /* Dithering seems to not pass-through bits correctly when it should, so |
611032bf MN |
11376 | * only enable it on 6bpc panels and when its not a compliance |
11377 | * test requesting 6bpc video pattern. | |
11378 | */ | |
11379 | pipe_config->dither = (pipe_config->pipe_bpp == 6*3) && | |
11380 | !pipe_config->dither_force_disable; | |
62f0ace5 | 11381 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 11382 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 11383 | |
7758a113 | 11384 | fail: |
548ee15b | 11385 | return ret; |
ee7b9f93 | 11386 | } |
47f1c6c9 | 11387 | |
ea9d758d | 11388 | static void |
4740b0f2 | 11389 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 11390 | { |
0a9ab303 ACO |
11391 | struct drm_crtc *crtc; |
11392 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 11393 | int i; |
ea9d758d | 11394 | |
7668851f | 11395 | /* Double check state. */ |
8a75d157 | 11396 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 11397 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
11398 | |
11399 | /* Update hwmode for vblank functions */ | |
11400 | if (crtc->state->active) | |
11401 | crtc->hwmode = crtc->state->adjusted_mode; | |
11402 | else | |
11403 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
11404 | |
11405 | /* | |
11406 | * Update legacy state to satisfy fbc code. This can | |
11407 | * be removed when fbc uses the atomic state. | |
11408 | */ | |
11409 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
11410 | struct drm_plane_state *plane_state = crtc->primary->state; | |
11411 | ||
11412 | crtc->primary->fb = plane_state->fb; | |
11413 | crtc->x = plane_state->src_x >> 16; | |
11414 | crtc->y = plane_state->src_y >> 16; | |
11415 | } | |
ea9d758d | 11416 | } |
ea9d758d DV |
11417 | } |
11418 | ||
3bd26263 | 11419 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 11420 | { |
3bd26263 | 11421 | int diff; |
f1f644dc JB |
11422 | |
11423 | if (clock1 == clock2) | |
11424 | return true; | |
11425 | ||
11426 | if (!clock1 || !clock2) | |
11427 | return false; | |
11428 | ||
11429 | diff = abs(clock1 - clock2); | |
11430 | ||
11431 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
11432 | return true; | |
11433 | ||
11434 | return false; | |
11435 | } | |
11436 | ||
cfb23ed6 ML |
11437 | static bool |
11438 | intel_compare_m_n(unsigned int m, unsigned int n, | |
11439 | unsigned int m2, unsigned int n2, | |
11440 | bool exact) | |
11441 | { | |
11442 | if (m == m2 && n == n2) | |
11443 | return true; | |
11444 | ||
11445 | if (exact || !m || !n || !m2 || !n2) | |
11446 | return false; | |
11447 | ||
11448 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
11449 | ||
31d10b57 ML |
11450 | if (n > n2) { |
11451 | while (n > n2) { | |
cfb23ed6 ML |
11452 | m2 <<= 1; |
11453 | n2 <<= 1; | |
11454 | } | |
31d10b57 ML |
11455 | } else if (n < n2) { |
11456 | while (n < n2) { | |
cfb23ed6 ML |
11457 | m <<= 1; |
11458 | n <<= 1; | |
11459 | } | |
11460 | } | |
11461 | ||
31d10b57 ML |
11462 | if (n != n2) |
11463 | return false; | |
11464 | ||
11465 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
11466 | } |
11467 | ||
11468 | static bool | |
11469 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
11470 | struct intel_link_m_n *m2_n2, | |
11471 | bool adjust) | |
11472 | { | |
11473 | if (m_n->tu == m2_n2->tu && | |
11474 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
11475 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
11476 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
11477 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
11478 | if (adjust) | |
11479 | *m2_n2 = *m_n; | |
11480 | ||
11481 | return true; | |
11482 | } | |
11483 | ||
11484 | return false; | |
11485 | } | |
11486 | ||
4e8048f8 TU |
11487 | static void __printf(3, 4) |
11488 | pipe_config_err(bool adjust, const char *name, const char *format, ...) | |
11489 | { | |
11490 | char *level; | |
11491 | unsigned int category; | |
11492 | struct va_format vaf; | |
11493 | va_list args; | |
11494 | ||
11495 | if (adjust) { | |
11496 | level = KERN_DEBUG; | |
11497 | category = DRM_UT_KMS; | |
11498 | } else { | |
11499 | level = KERN_ERR; | |
11500 | category = DRM_UT_NONE; | |
11501 | } | |
11502 | ||
11503 | va_start(args, format); | |
11504 | vaf.fmt = format; | |
11505 | vaf.va = &args; | |
11506 | ||
11507 | drm_printk(level, category, "mismatch in %s %pV", name, &vaf); | |
11508 | ||
11509 | va_end(args); | |
11510 | } | |
11511 | ||
0e8ffe1b | 11512 | static bool |
6315b5d3 | 11513 | intel_pipe_config_compare(struct drm_i915_private *dev_priv, |
5cec258b | 11514 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
11515 | struct intel_crtc_state *pipe_config, |
11516 | bool adjust) | |
0e8ffe1b | 11517 | { |
cfb23ed6 ML |
11518 | bool ret = true; |
11519 | ||
66e985c0 DV |
11520 | #define PIPE_CONF_CHECK_X(name) \ |
11521 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 11522 | pipe_config_err(adjust, __stringify(name), \ |
66e985c0 DV |
11523 | "(expected 0x%08x, found 0x%08x)\n", \ |
11524 | current_config->name, \ | |
11525 | pipe_config->name); \ | |
cfb23ed6 | 11526 | ret = false; \ |
66e985c0 DV |
11527 | } |
11528 | ||
08a24034 DV |
11529 | #define PIPE_CONF_CHECK_I(name) \ |
11530 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 11531 | pipe_config_err(adjust, __stringify(name), \ |
08a24034 DV |
11532 | "(expected %i, found %i)\n", \ |
11533 | current_config->name, \ | |
11534 | pipe_config->name); \ | |
cfb23ed6 ML |
11535 | ret = false; \ |
11536 | } | |
11537 | ||
8106ddbd ACO |
11538 | #define PIPE_CONF_CHECK_P(name) \ |
11539 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 11540 | pipe_config_err(adjust, __stringify(name), \ |
8106ddbd ACO |
11541 | "(expected %p, found %p)\n", \ |
11542 | current_config->name, \ | |
11543 | pipe_config->name); \ | |
11544 | ret = false; \ | |
11545 | } | |
11546 | ||
cfb23ed6 ML |
11547 | #define PIPE_CONF_CHECK_M_N(name) \ |
11548 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
11549 | &pipe_config->name,\ | |
11550 | adjust)) { \ | |
4e8048f8 | 11551 | pipe_config_err(adjust, __stringify(name), \ |
cfb23ed6 ML |
11552 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
11553 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
11554 | current_config->name.tu, \ | |
11555 | current_config->name.gmch_m, \ | |
11556 | current_config->name.gmch_n, \ | |
11557 | current_config->name.link_m, \ | |
11558 | current_config->name.link_n, \ | |
11559 | pipe_config->name.tu, \ | |
11560 | pipe_config->name.gmch_m, \ | |
11561 | pipe_config->name.gmch_n, \ | |
11562 | pipe_config->name.link_m, \ | |
11563 | pipe_config->name.link_n); \ | |
11564 | ret = false; \ | |
11565 | } | |
11566 | ||
55c561a7 DV |
11567 | /* This is required for BDW+ where there is only one set of registers for |
11568 | * switching between high and low RR. | |
11569 | * This macro can be used whenever a comparison has to be made between one | |
11570 | * hw state and multiple sw state variables. | |
11571 | */ | |
cfb23ed6 ML |
11572 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ |
11573 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
11574 | &pipe_config->name, adjust) && \ | |
11575 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
11576 | &pipe_config->name, adjust)) { \ | |
4e8048f8 | 11577 | pipe_config_err(adjust, __stringify(name), \ |
cfb23ed6 ML |
11578 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
11579 | "or tu %i gmch %i/%i link %i/%i, " \ | |
11580 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
11581 | current_config->name.tu, \ | |
11582 | current_config->name.gmch_m, \ | |
11583 | current_config->name.gmch_n, \ | |
11584 | current_config->name.link_m, \ | |
11585 | current_config->name.link_n, \ | |
11586 | current_config->alt_name.tu, \ | |
11587 | current_config->alt_name.gmch_m, \ | |
11588 | current_config->alt_name.gmch_n, \ | |
11589 | current_config->alt_name.link_m, \ | |
11590 | current_config->alt_name.link_n, \ | |
11591 | pipe_config->name.tu, \ | |
11592 | pipe_config->name.gmch_m, \ | |
11593 | pipe_config->name.gmch_n, \ | |
11594 | pipe_config->name.link_m, \ | |
11595 | pipe_config->name.link_n); \ | |
11596 | ret = false; \ | |
88adfff1 DV |
11597 | } |
11598 | ||
1bd1bd80 DV |
11599 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
11600 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
4e8048f8 TU |
11601 | pipe_config_err(adjust, __stringify(name), \ |
11602 | "(%x) (expected %i, found %i)\n", \ | |
11603 | (mask), \ | |
1bd1bd80 DV |
11604 | current_config->name & (mask), \ |
11605 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 11606 | ret = false; \ |
1bd1bd80 DV |
11607 | } |
11608 | ||
5e550656 VS |
11609 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
11610 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
4e8048f8 | 11611 | pipe_config_err(adjust, __stringify(name), \ |
5e550656 VS |
11612 | "(expected %i, found %i)\n", \ |
11613 | current_config->name, \ | |
11614 | pipe_config->name); \ | |
cfb23ed6 | 11615 | ret = false; \ |
5e550656 VS |
11616 | } |
11617 | ||
bb760063 DV |
11618 | #define PIPE_CONF_QUIRK(quirk) \ |
11619 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
11620 | ||
eccb140b DV |
11621 | PIPE_CONF_CHECK_I(cpu_transcoder); |
11622 | ||
08a24034 DV |
11623 | PIPE_CONF_CHECK_I(has_pch_encoder); |
11624 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 11625 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 11626 | |
90a6b7b0 | 11627 | PIPE_CONF_CHECK_I(lane_count); |
95a7a2ae | 11628 | PIPE_CONF_CHECK_X(lane_lat_optim_mask); |
b95af8be | 11629 | |
6315b5d3 | 11630 | if (INTEL_GEN(dev_priv) < 8) { |
cfb23ed6 ML |
11631 | PIPE_CONF_CHECK_M_N(dp_m_n); |
11632 | ||
cfb23ed6 ML |
11633 | if (current_config->has_drrs) |
11634 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
11635 | } else | |
11636 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 11637 | |
253c84c8 | 11638 | PIPE_CONF_CHECK_X(output_types); |
a65347ba | 11639 | |
2d112de7 ACO |
11640 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
11641 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
11642 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
11643 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
11644 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
11645 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 11646 | |
2d112de7 ACO |
11647 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
11648 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
11649 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
11650 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
11651 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
11652 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 11653 | |
c93f54cf | 11654 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 11655 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
772c2a51 | 11656 | if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || |
920a14b2 | 11657 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
b5a9fa09 | 11658 | PIPE_CONF_CHECK_I(limited_color_range); |
e43823ec | 11659 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 11660 | |
9ed109a7 DV |
11661 | PIPE_CONF_CHECK_I(has_audio); |
11662 | ||
2d112de7 | 11663 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
11664 | DRM_MODE_FLAG_INTERLACE); |
11665 | ||
bb760063 | 11666 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 11667 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11668 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 11669 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11670 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 11671 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11672 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 11673 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
11674 | DRM_MODE_FLAG_NVSYNC); |
11675 | } | |
045ac3b5 | 11676 | |
333b8ca8 | 11677 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a | 11678 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
6315b5d3 | 11679 | if (INTEL_GEN(dev_priv) < 4) |
7f7d8dd6 | 11680 | PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); |
333b8ca8 | 11681 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 11682 | |
bfd16b2a ML |
11683 | if (!adjust) { |
11684 | PIPE_CONF_CHECK_I(pipe_src_w); | |
11685 | PIPE_CONF_CHECK_I(pipe_src_h); | |
11686 | ||
11687 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
11688 | if (current_config->pch_pfit.enabled) { | |
11689 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
11690 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
11691 | } | |
2fa2fe9a | 11692 | |
7aefe2b5 | 11693 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
a7d1b3f4 | 11694 | PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate); |
7aefe2b5 | 11695 | } |
a1b2278e | 11696 | |
e59150dc | 11697 | /* BDW+ don't expose a synchronous way to read the state */ |
772c2a51 | 11698 | if (IS_HASWELL(dev_priv)) |
e59150dc | 11699 | PIPE_CONF_CHECK_I(ips_enabled); |
42db64ef | 11700 | |
282740f7 VS |
11701 | PIPE_CONF_CHECK_I(double_wide); |
11702 | ||
8106ddbd | 11703 | PIPE_CONF_CHECK_P(shared_dpll); |
66e985c0 | 11704 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 11705 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
11706 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
11707 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 11708 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 11709 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
11710 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
11711 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
11712 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 11713 | |
47eacbab VS |
11714 | PIPE_CONF_CHECK_X(dsi_pll.ctrl); |
11715 | PIPE_CONF_CHECK_X(dsi_pll.div); | |
11716 | ||
9beb5fea | 11717 | if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) |
42571aef VS |
11718 | PIPE_CONF_CHECK_I(pipe_bpp); |
11719 | ||
2d112de7 | 11720 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 11721 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 11722 | |
66e985c0 | 11723 | #undef PIPE_CONF_CHECK_X |
08a24034 | 11724 | #undef PIPE_CONF_CHECK_I |
8106ddbd | 11725 | #undef PIPE_CONF_CHECK_P |
1bd1bd80 | 11726 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 11727 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 11728 | #undef PIPE_CONF_QUIRK |
88adfff1 | 11729 | |
cfb23ed6 | 11730 | return ret; |
0e8ffe1b DV |
11731 | } |
11732 | ||
e3b247da VS |
11733 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
11734 | const struct intel_crtc_state *pipe_config) | |
11735 | { | |
11736 | if (pipe_config->has_pch_encoder) { | |
21a727b3 | 11737 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
e3b247da VS |
11738 | &pipe_config->fdi_m_n); |
11739 | int dotclock = pipe_config->base.adjusted_mode.crtc_clock; | |
11740 | ||
11741 | /* | |
11742 | * FDI already provided one idea for the dotclock. | |
11743 | * Yell if the encoder disagrees. | |
11744 | */ | |
11745 | WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
11746 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
11747 | fdi_dotclock, dotclock); | |
11748 | } | |
11749 | } | |
11750 | ||
c0ead703 ML |
11751 | static void verify_wm_state(struct drm_crtc *crtc, |
11752 | struct drm_crtc_state *new_state) | |
08db6652 | 11753 | { |
6315b5d3 | 11754 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
08db6652 | 11755 | struct skl_ddb_allocation hw_ddb, *sw_ddb; |
3de8a14c | 11756 | struct skl_pipe_wm hw_wm, *sw_wm; |
11757 | struct skl_plane_wm *hw_plane_wm, *sw_plane_wm; | |
11758 | struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; | |
e7c84544 ML |
11759 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11760 | const enum pipe pipe = intel_crtc->pipe; | |
3de8a14c | 11761 | int plane, level, max_level = ilk_wm_max_level(dev_priv); |
08db6652 | 11762 | |
6315b5d3 | 11763 | if (INTEL_GEN(dev_priv) < 9 || !new_state->active) |
08db6652 DL |
11764 | return; |
11765 | ||
3de8a14c | 11766 | skl_pipe_wm_get_hw_state(crtc, &hw_wm); |
03af79e0 | 11767 | sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal; |
3de8a14c | 11768 | |
08db6652 DL |
11769 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); |
11770 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
11771 | ||
e7c84544 | 11772 | /* planes */ |
8b364b41 | 11773 | for_each_universal_plane(dev_priv, pipe, plane) { |
3de8a14c | 11774 | hw_plane_wm = &hw_wm.planes[plane]; |
11775 | sw_plane_wm = &sw_wm->planes[plane]; | |
08db6652 | 11776 | |
3de8a14c | 11777 | /* Watermarks */ |
11778 | for (level = 0; level <= max_level; level++) { | |
11779 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
11780 | &sw_plane_wm->wm[level])) | |
11781 | continue; | |
11782 | ||
11783 | DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11784 | pipe_name(pipe), plane + 1, level, | |
11785 | sw_plane_wm->wm[level].plane_en, | |
11786 | sw_plane_wm->wm[level].plane_res_b, | |
11787 | sw_plane_wm->wm[level].plane_res_l, | |
11788 | hw_plane_wm->wm[level].plane_en, | |
11789 | hw_plane_wm->wm[level].plane_res_b, | |
11790 | hw_plane_wm->wm[level].plane_res_l); | |
11791 | } | |
08db6652 | 11792 | |
3de8a14c | 11793 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, |
11794 | &sw_plane_wm->trans_wm)) { | |
11795 | DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11796 | pipe_name(pipe), plane + 1, | |
11797 | sw_plane_wm->trans_wm.plane_en, | |
11798 | sw_plane_wm->trans_wm.plane_res_b, | |
11799 | sw_plane_wm->trans_wm.plane_res_l, | |
11800 | hw_plane_wm->trans_wm.plane_en, | |
11801 | hw_plane_wm->trans_wm.plane_res_b, | |
11802 | hw_plane_wm->trans_wm.plane_res_l); | |
11803 | } | |
11804 | ||
11805 | /* DDB */ | |
11806 | hw_ddb_entry = &hw_ddb.plane[pipe][plane]; | |
11807 | sw_ddb_entry = &sw_ddb->plane[pipe][plane]; | |
11808 | ||
11809 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { | |
faccd994 | 11810 | DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n", |
3de8a14c | 11811 | pipe_name(pipe), plane + 1, |
11812 | sw_ddb_entry->start, sw_ddb_entry->end, | |
11813 | hw_ddb_entry->start, hw_ddb_entry->end); | |
11814 | } | |
e7c84544 | 11815 | } |
08db6652 | 11816 | |
27082493 L |
11817 | /* |
11818 | * cursor | |
11819 | * If the cursor plane isn't active, we may not have updated it's ddb | |
11820 | * allocation. In that case since the ddb allocation will be updated | |
11821 | * once the plane becomes visible, we can skip this check | |
11822 | */ | |
11823 | if (intel_crtc->cursor_addr) { | |
3de8a14c | 11824 | hw_plane_wm = &hw_wm.planes[PLANE_CURSOR]; |
11825 | sw_plane_wm = &sw_wm->planes[PLANE_CURSOR]; | |
11826 | ||
11827 | /* Watermarks */ | |
11828 | for (level = 0; level <= max_level; level++) { | |
11829 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
11830 | &sw_plane_wm->wm[level])) | |
11831 | continue; | |
11832 | ||
11833 | DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11834 | pipe_name(pipe), level, | |
11835 | sw_plane_wm->wm[level].plane_en, | |
11836 | sw_plane_wm->wm[level].plane_res_b, | |
11837 | sw_plane_wm->wm[level].plane_res_l, | |
11838 | hw_plane_wm->wm[level].plane_en, | |
11839 | hw_plane_wm->wm[level].plane_res_b, | |
11840 | hw_plane_wm->wm[level].plane_res_l); | |
11841 | } | |
11842 | ||
11843 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, | |
11844 | &sw_plane_wm->trans_wm)) { | |
11845 | DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11846 | pipe_name(pipe), | |
11847 | sw_plane_wm->trans_wm.plane_en, | |
11848 | sw_plane_wm->trans_wm.plane_res_b, | |
11849 | sw_plane_wm->trans_wm.plane_res_l, | |
11850 | hw_plane_wm->trans_wm.plane_en, | |
11851 | hw_plane_wm->trans_wm.plane_res_b, | |
11852 | hw_plane_wm->trans_wm.plane_res_l); | |
11853 | } | |
11854 | ||
11855 | /* DDB */ | |
11856 | hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; | |
11857 | sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
27082493 | 11858 | |
3de8a14c | 11859 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { |
faccd994 | 11860 | DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n", |
27082493 | 11861 | pipe_name(pipe), |
3de8a14c | 11862 | sw_ddb_entry->start, sw_ddb_entry->end, |
11863 | hw_ddb_entry->start, hw_ddb_entry->end); | |
27082493 | 11864 | } |
08db6652 DL |
11865 | } |
11866 | } | |
11867 | ||
91d1b4bd | 11868 | static void |
677100ce ML |
11869 | verify_connector_state(struct drm_device *dev, |
11870 | struct drm_atomic_state *state, | |
11871 | struct drm_crtc *crtc) | |
8af6cf88 | 11872 | { |
35dd3c64 | 11873 | struct drm_connector *connector; |
677100ce ML |
11874 | struct drm_connector_state *old_conn_state; |
11875 | int i; | |
8af6cf88 | 11876 | |
677100ce | 11877 | for_each_connector_in_state(state, connector, old_conn_state, i) { |
35dd3c64 ML |
11878 | struct drm_encoder *encoder = connector->encoder; |
11879 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 11880 | |
e7c84544 ML |
11881 | if (state->crtc != crtc) |
11882 | continue; | |
11883 | ||
5a21b665 | 11884 | intel_connector_verify_state(to_intel_connector(connector)); |
8af6cf88 | 11885 | |
ad3c558f | 11886 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 11887 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 11888 | } |
91d1b4bd DV |
11889 | } |
11890 | ||
11891 | static void | |
c0ead703 | 11892 | verify_encoder_state(struct drm_device *dev) |
91d1b4bd DV |
11893 | { |
11894 | struct intel_encoder *encoder; | |
11895 | struct intel_connector *connector; | |
8af6cf88 | 11896 | |
b2784e15 | 11897 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 11898 | bool enabled = false; |
4d20cd86 | 11899 | enum pipe pipe; |
8af6cf88 DV |
11900 | |
11901 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
11902 | encoder->base.base.id, | |
8e329a03 | 11903 | encoder->base.name); |
8af6cf88 | 11904 | |
3a3371ff | 11905 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 11906 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
11907 | continue; |
11908 | enabled = true; | |
ad3c558f ML |
11909 | |
11910 | I915_STATE_WARN(connector->base.state->crtc != | |
11911 | encoder->base.crtc, | |
11912 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 11913 | } |
0e32b39c | 11914 | |
e2c719b7 | 11915 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
11916 | "encoder's enabled state mismatch " |
11917 | "(expected %i, found %i)\n", | |
11918 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
11919 | |
11920 | if (!encoder->base.crtc) { | |
4d20cd86 | 11921 | bool active; |
7c60d198 | 11922 | |
4d20cd86 ML |
11923 | active = encoder->get_hw_state(encoder, &pipe); |
11924 | I915_STATE_WARN(active, | |
11925 | "encoder detached but still enabled on pipe %c.\n", | |
11926 | pipe_name(pipe)); | |
7c60d198 | 11927 | } |
8af6cf88 | 11928 | } |
91d1b4bd DV |
11929 | } |
11930 | ||
11931 | static void | |
c0ead703 ML |
11932 | verify_crtc_state(struct drm_crtc *crtc, |
11933 | struct drm_crtc_state *old_crtc_state, | |
11934 | struct drm_crtc_state *new_crtc_state) | |
91d1b4bd | 11935 | { |
e7c84544 | 11936 | struct drm_device *dev = crtc->dev; |
fac5e23e | 11937 | struct drm_i915_private *dev_priv = to_i915(dev); |
91d1b4bd | 11938 | struct intel_encoder *encoder; |
e7c84544 ML |
11939 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11940 | struct intel_crtc_state *pipe_config, *sw_config; | |
11941 | struct drm_atomic_state *old_state; | |
11942 | bool active; | |
045ac3b5 | 11943 | |
e7c84544 | 11944 | old_state = old_crtc_state->state; |
ec2dc6a0 | 11945 | __drm_atomic_helper_crtc_destroy_state(old_crtc_state); |
e7c84544 ML |
11946 | pipe_config = to_intel_crtc_state(old_crtc_state); |
11947 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
11948 | pipe_config->base.crtc = crtc; | |
11949 | pipe_config->base.state = old_state; | |
8af6cf88 | 11950 | |
78108b7c | 11951 | DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); |
8af6cf88 | 11952 | |
e7c84544 | 11953 | active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config); |
d62cf62a | 11954 | |
e7c84544 ML |
11955 | /* hw state is inconsistent with the pipe quirk */ |
11956 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
11957 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
11958 | active = new_crtc_state->active; | |
6c49f241 | 11959 | |
e7c84544 ML |
11960 | I915_STATE_WARN(new_crtc_state->active != active, |
11961 | "crtc active state doesn't match with hw state " | |
11962 | "(expected %i, found %i)\n", new_crtc_state->active, active); | |
0e8ffe1b | 11963 | |
e7c84544 ML |
11964 | I915_STATE_WARN(intel_crtc->active != new_crtc_state->active, |
11965 | "transitional active state does not match atomic hw state " | |
11966 | "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active); | |
4d20cd86 | 11967 | |
e7c84544 ML |
11968 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
11969 | enum pipe pipe; | |
4d20cd86 | 11970 | |
e7c84544 ML |
11971 | active = encoder->get_hw_state(encoder, &pipe); |
11972 | I915_STATE_WARN(active != new_crtc_state->active, | |
11973 | "[ENCODER:%i] active %i with crtc active %i\n", | |
11974 | encoder->base.base.id, active, new_crtc_state->active); | |
4d20cd86 | 11975 | |
e7c84544 ML |
11976 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, |
11977 | "Encoder connected to wrong pipe %c\n", | |
11978 | pipe_name(pipe)); | |
4d20cd86 | 11979 | |
253c84c8 VS |
11980 | if (active) { |
11981 | pipe_config->output_types |= 1 << encoder->type; | |
e7c84544 | 11982 | encoder->get_config(encoder, pipe_config); |
253c84c8 | 11983 | } |
e7c84544 | 11984 | } |
53d9f4e9 | 11985 | |
a7d1b3f4 VS |
11986 | intel_crtc_compute_pixel_rate(pipe_config); |
11987 | ||
e7c84544 ML |
11988 | if (!new_crtc_state->active) |
11989 | return; | |
cfb23ed6 | 11990 | |
e7c84544 | 11991 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
e3b247da | 11992 | |
e7c84544 | 11993 | sw_config = to_intel_crtc_state(crtc->state); |
6315b5d3 | 11994 | if (!intel_pipe_config_compare(dev_priv, sw_config, |
e7c84544 ML |
11995 | pipe_config, false)) { |
11996 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); | |
11997 | intel_dump_pipe_config(intel_crtc, pipe_config, | |
11998 | "[hw state]"); | |
11999 | intel_dump_pipe_config(intel_crtc, sw_config, | |
12000 | "[sw state]"); | |
8af6cf88 DV |
12001 | } |
12002 | } | |
12003 | ||
91d1b4bd | 12004 | static void |
c0ead703 ML |
12005 | verify_single_dpll_state(struct drm_i915_private *dev_priv, |
12006 | struct intel_shared_dpll *pll, | |
12007 | struct drm_crtc *crtc, | |
12008 | struct drm_crtc_state *new_state) | |
91d1b4bd | 12009 | { |
91d1b4bd | 12010 | struct intel_dpll_hw_state dpll_hw_state; |
e7c84544 ML |
12011 | unsigned crtc_mask; |
12012 | bool active; | |
5358901f | 12013 | |
e7c84544 | 12014 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
5358901f | 12015 | |
e7c84544 | 12016 | DRM_DEBUG_KMS("%s\n", pll->name); |
5358901f | 12017 | |
e7c84544 | 12018 | active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state); |
5358901f | 12019 | |
e7c84544 ML |
12020 | if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) { |
12021 | I915_STATE_WARN(!pll->on && pll->active_mask, | |
12022 | "pll in active use but not on in sw tracking\n"); | |
12023 | I915_STATE_WARN(pll->on && !pll->active_mask, | |
12024 | "pll is on but not used by any active crtc\n"); | |
12025 | I915_STATE_WARN(pll->on != active, | |
12026 | "pll on state mismatch (expected %i, found %i)\n", | |
12027 | pll->on, active); | |
12028 | } | |
5358901f | 12029 | |
e7c84544 | 12030 | if (!crtc) { |
2c42e535 | 12031 | I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask, |
e7c84544 | 12032 | "more active pll users than references: %x vs %x\n", |
2c42e535 | 12033 | pll->active_mask, pll->state.crtc_mask); |
5358901f | 12034 | |
e7c84544 ML |
12035 | return; |
12036 | } | |
12037 | ||
12038 | crtc_mask = 1 << drm_crtc_index(crtc); | |
12039 | ||
12040 | if (new_state->active) | |
12041 | I915_STATE_WARN(!(pll->active_mask & crtc_mask), | |
12042 | "pll active mismatch (expected pipe %c in active mask 0x%02x)\n", | |
12043 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
12044 | else | |
12045 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
12046 | "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n", | |
12047 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
2dd66ebd | 12048 | |
2c42e535 | 12049 | I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask), |
e7c84544 | 12050 | "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", |
2c42e535 | 12051 | crtc_mask, pll->state.crtc_mask); |
66e985c0 | 12052 | |
2c42e535 | 12053 | I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state, |
e7c84544 ML |
12054 | &dpll_hw_state, |
12055 | sizeof(dpll_hw_state)), | |
12056 | "pll hw state mismatch\n"); | |
12057 | } | |
12058 | ||
12059 | static void | |
c0ead703 ML |
12060 | verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc, |
12061 | struct drm_crtc_state *old_crtc_state, | |
12062 | struct drm_crtc_state *new_crtc_state) | |
e7c84544 | 12063 | { |
fac5e23e | 12064 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
12065 | struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state); |
12066 | struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state); | |
12067 | ||
12068 | if (new_state->shared_dpll) | |
c0ead703 | 12069 | verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state); |
e7c84544 ML |
12070 | |
12071 | if (old_state->shared_dpll && | |
12072 | old_state->shared_dpll != new_state->shared_dpll) { | |
12073 | unsigned crtc_mask = 1 << drm_crtc_index(crtc); | |
12074 | struct intel_shared_dpll *pll = old_state->shared_dpll; | |
12075 | ||
12076 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
12077 | "pll active mismatch (didn't expect pipe %c in active mask)\n", | |
12078 | pipe_name(drm_crtc_index(crtc))); | |
2c42e535 | 12079 | I915_STATE_WARN(pll->state.crtc_mask & crtc_mask, |
e7c84544 ML |
12080 | "pll enabled crtcs mismatch (found %x in enabled mask)\n", |
12081 | pipe_name(drm_crtc_index(crtc))); | |
5358901f | 12082 | } |
8af6cf88 DV |
12083 | } |
12084 | ||
e7c84544 | 12085 | static void |
c0ead703 | 12086 | intel_modeset_verify_crtc(struct drm_crtc *crtc, |
677100ce ML |
12087 | struct drm_atomic_state *state, |
12088 | struct drm_crtc_state *old_state, | |
12089 | struct drm_crtc_state *new_state) | |
e7c84544 | 12090 | { |
5a21b665 DV |
12091 | if (!needs_modeset(new_state) && |
12092 | !to_intel_crtc_state(new_state)->update_pipe) | |
12093 | return; | |
12094 | ||
c0ead703 | 12095 | verify_wm_state(crtc, new_state); |
677100ce | 12096 | verify_connector_state(crtc->dev, state, crtc); |
c0ead703 ML |
12097 | verify_crtc_state(crtc, old_state, new_state); |
12098 | verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state); | |
e7c84544 ML |
12099 | } |
12100 | ||
12101 | static void | |
c0ead703 | 12102 | verify_disabled_dpll_state(struct drm_device *dev) |
e7c84544 | 12103 | { |
fac5e23e | 12104 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
12105 | int i; |
12106 | ||
12107 | for (i = 0; i < dev_priv->num_shared_dpll; i++) | |
c0ead703 | 12108 | verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL); |
e7c84544 ML |
12109 | } |
12110 | ||
12111 | static void | |
677100ce ML |
12112 | intel_modeset_verify_disabled(struct drm_device *dev, |
12113 | struct drm_atomic_state *state) | |
e7c84544 | 12114 | { |
c0ead703 | 12115 | verify_encoder_state(dev); |
677100ce | 12116 | verify_connector_state(dev, state, NULL); |
c0ead703 | 12117 | verify_disabled_dpll_state(dev); |
e7c84544 ML |
12118 | } |
12119 | ||
80715b2f VS |
12120 | static void update_scanline_offset(struct intel_crtc *crtc) |
12121 | { | |
4f8036a2 | 12122 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
80715b2f VS |
12123 | |
12124 | /* | |
12125 | * The scanline counter increments at the leading edge of hsync. | |
12126 | * | |
12127 | * On most platforms it starts counting from vtotal-1 on the | |
12128 | * first active line. That means the scanline counter value is | |
12129 | * always one less than what we would expect. Ie. just after | |
12130 | * start of vblank, which also occurs at start of hsync (on the | |
12131 | * last active line), the scanline counter will read vblank_start-1. | |
12132 | * | |
12133 | * On gen2 the scanline counter starts counting from 1 instead | |
12134 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
12135 | * to keep the value positive), instead of adding one. | |
12136 | * | |
12137 | * On HSW+ the behaviour of the scanline counter depends on the output | |
12138 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
12139 | * there's an extra 1 line difference. So we need to add two instead of | |
12140 | * one to the value. | |
12141 | */ | |
4f8036a2 | 12142 | if (IS_GEN2(dev_priv)) { |
124abe07 | 12143 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
12144 | int vtotal; |
12145 | ||
124abe07 VS |
12146 | vtotal = adjusted_mode->crtc_vtotal; |
12147 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
12148 | vtotal /= 2; |
12149 | ||
12150 | crtc->scanline_offset = vtotal - 1; | |
4f8036a2 | 12151 | } else if (HAS_DDI(dev_priv) && |
2d84d2b3 | 12152 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
12153 | crtc->scanline_offset = 2; |
12154 | } else | |
12155 | crtc->scanline_offset = 1; | |
12156 | } | |
12157 | ||
ad421372 | 12158 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 12159 | { |
225da59b | 12160 | struct drm_device *dev = state->dev; |
ed6739ef | 12161 | struct drm_i915_private *dev_priv = to_i915(dev); |
0a9ab303 ACO |
12162 | struct drm_crtc *crtc; |
12163 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 12164 | int i; |
ed6739ef ACO |
12165 | |
12166 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 12167 | return; |
ed6739ef | 12168 | |
0a9ab303 | 12169 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
fb1a38a9 | 12170 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8106ddbd ACO |
12171 | struct intel_shared_dpll *old_dpll = |
12172 | to_intel_crtc_state(crtc->state)->shared_dpll; | |
0a9ab303 | 12173 | |
fb1a38a9 | 12174 | if (!needs_modeset(crtc_state)) |
225da59b ACO |
12175 | continue; |
12176 | ||
8106ddbd | 12177 | to_intel_crtc_state(crtc_state)->shared_dpll = NULL; |
fb1a38a9 | 12178 | |
8106ddbd | 12179 | if (!old_dpll) |
fb1a38a9 | 12180 | continue; |
0a9ab303 | 12181 | |
a1c414ee | 12182 | intel_release_shared_dpll(old_dpll, intel_crtc, state); |
ad421372 | 12183 | } |
ed6739ef ACO |
12184 | } |
12185 | ||
99d736a2 ML |
12186 | /* |
12187 | * This implements the workaround described in the "notes" section of the mode | |
12188 | * set sequence documentation. When going from no pipes or single pipe to | |
12189 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
12190 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
12191 | */ | |
12192 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
12193 | { | |
12194 | struct drm_crtc_state *crtc_state; | |
12195 | struct intel_crtc *intel_crtc; | |
12196 | struct drm_crtc *crtc; | |
12197 | struct intel_crtc_state *first_crtc_state = NULL; | |
12198 | struct intel_crtc_state *other_crtc_state = NULL; | |
12199 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
12200 | int i; | |
12201 | ||
12202 | /* look at all crtc's that are going to be enabled in during modeset */ | |
12203 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
12204 | intel_crtc = to_intel_crtc(crtc); | |
12205 | ||
12206 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
12207 | continue; | |
12208 | ||
12209 | if (first_crtc_state) { | |
12210 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
12211 | break; | |
12212 | } else { | |
12213 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
12214 | first_pipe = intel_crtc->pipe; | |
12215 | } | |
12216 | } | |
12217 | ||
12218 | /* No workaround needed? */ | |
12219 | if (!first_crtc_state) | |
12220 | return 0; | |
12221 | ||
12222 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
12223 | for_each_intel_crtc(state->dev, intel_crtc) { | |
12224 | struct intel_crtc_state *pipe_config; | |
12225 | ||
12226 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
12227 | if (IS_ERR(pipe_config)) | |
12228 | return PTR_ERR(pipe_config); | |
12229 | ||
12230 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
12231 | ||
12232 | if (!pipe_config->base.active || | |
12233 | needs_modeset(&pipe_config->base)) | |
12234 | continue; | |
12235 | ||
12236 | /* 2 or more enabled crtcs means no need for w/a */ | |
12237 | if (enabled_pipe != INVALID_PIPE) | |
12238 | return 0; | |
12239 | ||
12240 | enabled_pipe = intel_crtc->pipe; | |
12241 | } | |
12242 | ||
12243 | if (enabled_pipe != INVALID_PIPE) | |
12244 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
12245 | else if (other_crtc_state) | |
12246 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
12247 | ||
12248 | return 0; | |
12249 | } | |
12250 | ||
8d96561a VS |
12251 | static int intel_lock_all_pipes(struct drm_atomic_state *state) |
12252 | { | |
12253 | struct drm_crtc *crtc; | |
12254 | ||
12255 | /* Add all pipes to the state */ | |
12256 | for_each_crtc(state->dev, crtc) { | |
12257 | struct drm_crtc_state *crtc_state; | |
12258 | ||
12259 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
12260 | if (IS_ERR(crtc_state)) | |
12261 | return PTR_ERR(crtc_state); | |
12262 | } | |
12263 | ||
12264 | return 0; | |
12265 | } | |
12266 | ||
27c329ed ML |
12267 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
12268 | { | |
12269 | struct drm_crtc *crtc; | |
27c329ed | 12270 | |
8d96561a VS |
12271 | /* |
12272 | * Add all pipes to the state, and force | |
12273 | * a modeset on all the active ones. | |
12274 | */ | |
27c329ed | 12275 | for_each_crtc(state->dev, crtc) { |
9780aad5 VS |
12276 | struct drm_crtc_state *crtc_state; |
12277 | int ret; | |
12278 | ||
27c329ed ML |
12279 | crtc_state = drm_atomic_get_crtc_state(state, crtc); |
12280 | if (IS_ERR(crtc_state)) | |
12281 | return PTR_ERR(crtc_state); | |
12282 | ||
12283 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
12284 | continue; | |
12285 | ||
12286 | crtc_state->mode_changed = true; | |
12287 | ||
12288 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
12289 | if (ret) | |
9780aad5 | 12290 | return ret; |
27c329ed ML |
12291 | |
12292 | ret = drm_atomic_add_affected_planes(state, crtc); | |
12293 | if (ret) | |
9780aad5 | 12294 | return ret; |
27c329ed ML |
12295 | } |
12296 | ||
9780aad5 | 12297 | return 0; |
27c329ed ML |
12298 | } |
12299 | ||
c347a676 | 12300 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 12301 | { |
565602d7 | 12302 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 12303 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
565602d7 ML |
12304 | struct drm_crtc *crtc; |
12305 | struct drm_crtc_state *crtc_state; | |
12306 | int ret = 0, i; | |
054518dd | 12307 | |
b359283a ML |
12308 | if (!check_digital_port_conflicts(state)) { |
12309 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
12310 | return -EINVAL; | |
12311 | } | |
12312 | ||
565602d7 ML |
12313 | intel_state->modeset = true; |
12314 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
bb0f4aab VS |
12315 | intel_state->cdclk.logical = dev_priv->cdclk.logical; |
12316 | intel_state->cdclk.actual = dev_priv->cdclk.actual; | |
565602d7 ML |
12317 | |
12318 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
12319 | if (crtc_state->active) | |
12320 | intel_state->active_crtcs |= 1 << i; | |
12321 | else | |
12322 | intel_state->active_crtcs &= ~(1 << i); | |
8b4a7d05 MR |
12323 | |
12324 | if (crtc_state->active != crtc->state->active) | |
12325 | intel_state->active_pipe_changes |= drm_crtc_mask(crtc); | |
565602d7 ML |
12326 | } |
12327 | ||
054518dd ACO |
12328 | /* |
12329 | * See if the config requires any additional preparation, e.g. | |
12330 | * to adjust global state with pipes off. We need to do this | |
12331 | * here so we can get the modeset_pipe updated config for the new | |
12332 | * mode set on this crtc. For other crtcs we need to use the | |
12333 | * adjusted_mode bits in the crtc directly. | |
12334 | */ | |
27c329ed | 12335 | if (dev_priv->display.modeset_calc_cdclk) { |
27c329ed | 12336 | ret = dev_priv->display.modeset_calc_cdclk(state); |
c89e39f3 CT |
12337 | if (ret < 0) |
12338 | return ret; | |
27c329ed | 12339 | |
8d96561a | 12340 | /* |
bb0f4aab | 12341 | * Writes to dev_priv->cdclk.logical must protected by |
8d96561a VS |
12342 | * holding all the crtc locks, even if we don't end up |
12343 | * touching the hardware | |
12344 | */ | |
bb0f4aab VS |
12345 | if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical, |
12346 | &intel_state->cdclk.logical)) { | |
8d96561a VS |
12347 | ret = intel_lock_all_pipes(state); |
12348 | if (ret < 0) | |
12349 | return ret; | |
12350 | } | |
12351 | ||
12352 | /* All pipes must be switched off while we change the cdclk. */ | |
bb0f4aab VS |
12353 | if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual, |
12354 | &intel_state->cdclk.actual)) { | |
27c329ed | 12355 | ret = intel_modeset_all_pipes(state); |
8d96561a VS |
12356 | if (ret < 0) |
12357 | return ret; | |
12358 | } | |
e8788cbc | 12359 | |
bb0f4aab VS |
12360 | DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n", |
12361 | intel_state->cdclk.logical.cdclk, | |
12362 | intel_state->cdclk.actual.cdclk); | |
e0ca7a6b | 12363 | } else { |
bb0f4aab | 12364 | to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical; |
e0ca7a6b | 12365 | } |
054518dd | 12366 | |
ad421372 | 12367 | intel_modeset_clear_plls(state); |
054518dd | 12368 | |
565602d7 | 12369 | if (IS_HASWELL(dev_priv)) |
ad421372 | 12370 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 12371 | |
ad421372 | 12372 | return 0; |
c347a676 ACO |
12373 | } |
12374 | ||
aa363136 MR |
12375 | /* |
12376 | * Handle calculation of various watermark data at the end of the atomic check | |
12377 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
12378 | * handlers to ensure that all derived state has been updated. | |
12379 | */ | |
55994c2c | 12380 | static int calc_watermark_data(struct drm_atomic_state *state) |
aa363136 MR |
12381 | { |
12382 | struct drm_device *dev = state->dev; | |
98d39494 | 12383 | struct drm_i915_private *dev_priv = to_i915(dev); |
98d39494 MR |
12384 | |
12385 | /* Is there platform-specific watermark information to calculate? */ | |
12386 | if (dev_priv->display.compute_global_watermarks) | |
55994c2c MR |
12387 | return dev_priv->display.compute_global_watermarks(state); |
12388 | ||
12389 | return 0; | |
aa363136 MR |
12390 | } |
12391 | ||
74c090b1 ML |
12392 | /** |
12393 | * intel_atomic_check - validate state object | |
12394 | * @dev: drm device | |
12395 | * @state: state to validate | |
12396 | */ | |
12397 | static int intel_atomic_check(struct drm_device *dev, | |
12398 | struct drm_atomic_state *state) | |
c347a676 | 12399 | { |
dd8b3bdb | 12400 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 12401 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
12402 | struct drm_crtc *crtc; |
12403 | struct drm_crtc_state *crtc_state; | |
12404 | int ret, i; | |
61333b60 | 12405 | bool any_ms = false; |
c347a676 | 12406 | |
74c090b1 | 12407 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
12408 | if (ret) |
12409 | return ret; | |
12410 | ||
c347a676 | 12411 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
12412 | struct intel_crtc_state *pipe_config = |
12413 | to_intel_crtc_state(crtc_state); | |
1ed51de9 DV |
12414 | |
12415 | /* Catch I915_MODE_FLAG_INHERITED */ | |
12416 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
12417 | crtc_state->mode_changed = true; | |
cfb23ed6 | 12418 | |
af4a879e | 12419 | if (!needs_modeset(crtc_state)) |
c347a676 ACO |
12420 | continue; |
12421 | ||
af4a879e DV |
12422 | if (!crtc_state->enable) { |
12423 | any_ms = true; | |
cfb23ed6 | 12424 | continue; |
af4a879e | 12425 | } |
cfb23ed6 | 12426 | |
26495481 DV |
12427 | /* FIXME: For only active_changed we shouldn't need to do any |
12428 | * state recomputation at all. */ | |
12429 | ||
1ed51de9 DV |
12430 | ret = drm_atomic_add_affected_connectors(state, crtc); |
12431 | if (ret) | |
12432 | return ret; | |
b359283a | 12433 | |
cfb23ed6 | 12434 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
25aa1c39 ML |
12435 | if (ret) { |
12436 | intel_dump_pipe_config(to_intel_crtc(crtc), | |
12437 | pipe_config, "[failed]"); | |
c347a676 | 12438 | return ret; |
25aa1c39 | 12439 | } |
c347a676 | 12440 | |
73831236 | 12441 | if (i915.fastboot && |
6315b5d3 | 12442 | intel_pipe_config_compare(dev_priv, |
cfb23ed6 | 12443 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 12444 | pipe_config, true)) { |
26495481 | 12445 | crtc_state->mode_changed = false; |
bfd16b2a | 12446 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
12447 | } |
12448 | ||
af4a879e | 12449 | if (needs_modeset(crtc_state)) |
26495481 | 12450 | any_ms = true; |
cfb23ed6 | 12451 | |
af4a879e DV |
12452 | ret = drm_atomic_add_affected_planes(state, crtc); |
12453 | if (ret) | |
12454 | return ret; | |
61333b60 | 12455 | |
26495481 DV |
12456 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
12457 | needs_modeset(crtc_state) ? | |
12458 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
12459 | } |
12460 | ||
61333b60 ML |
12461 | if (any_ms) { |
12462 | ret = intel_modeset_checks(state); | |
12463 | ||
12464 | if (ret) | |
12465 | return ret; | |
e0ca7a6b | 12466 | } else { |
bb0f4aab | 12467 | intel_state->cdclk.logical = dev_priv->cdclk.logical; |
e0ca7a6b | 12468 | } |
76305b1a | 12469 | |
dd8b3bdb | 12470 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
12471 | if (ret) |
12472 | return ret; | |
12473 | ||
f51be2e0 | 12474 | intel_fbc_choose_crtc(dev_priv, state); |
55994c2c | 12475 | return calc_watermark_data(state); |
054518dd ACO |
12476 | } |
12477 | ||
5008e874 | 12478 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
d07f0e59 | 12479 | struct drm_atomic_state *state) |
5008e874 | 12480 | { |
fac5e23e | 12481 | struct drm_i915_private *dev_priv = to_i915(dev); |
5008e874 ML |
12482 | struct drm_crtc_state *crtc_state; |
12483 | struct drm_crtc *crtc; | |
12484 | int i, ret; | |
12485 | ||
5a21b665 DV |
12486 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
12487 | if (state->legacy_cursor_update) | |
a6747b73 ML |
12488 | continue; |
12489 | ||
5a21b665 DV |
12490 | ret = intel_crtc_wait_for_pending_flips(crtc); |
12491 | if (ret) | |
12492 | return ret; | |
5008e874 | 12493 | |
5a21b665 DV |
12494 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) |
12495 | flush_workqueue(dev_priv->wq); | |
d55dbd06 ML |
12496 | } |
12497 | ||
f935675f ML |
12498 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
12499 | if (ret) | |
12500 | return ret; | |
12501 | ||
5008e874 | 12502 | ret = drm_atomic_helper_prepare_planes(dev, state); |
f7e5838b | 12503 | mutex_unlock(&dev->struct_mutex); |
7580d774 | 12504 | |
5008e874 ML |
12505 | return ret; |
12506 | } | |
12507 | ||
a2991414 ML |
12508 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) |
12509 | { | |
12510 | struct drm_device *dev = crtc->base.dev; | |
12511 | ||
12512 | if (!dev->max_vblank_count) | |
12513 | return drm_accurate_vblank_count(&crtc->base); | |
12514 | ||
12515 | return dev->driver->get_vblank_counter(dev, crtc->pipe); | |
12516 | } | |
12517 | ||
5a21b665 DV |
12518 | static void intel_atomic_wait_for_vblanks(struct drm_device *dev, |
12519 | struct drm_i915_private *dev_priv, | |
12520 | unsigned crtc_mask) | |
e8861675 | 12521 | { |
5a21b665 DV |
12522 | unsigned last_vblank_count[I915_MAX_PIPES]; |
12523 | enum pipe pipe; | |
12524 | int ret; | |
e8861675 | 12525 | |
5a21b665 DV |
12526 | if (!crtc_mask) |
12527 | return; | |
e8861675 | 12528 | |
5a21b665 | 12529 | for_each_pipe(dev_priv, pipe) { |
98187836 VS |
12530 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, |
12531 | pipe); | |
e8861675 | 12532 | |
5a21b665 | 12533 | if (!((1 << pipe) & crtc_mask)) |
e8861675 ML |
12534 | continue; |
12535 | ||
e2af48c6 | 12536 | ret = drm_crtc_vblank_get(&crtc->base); |
5a21b665 DV |
12537 | if (WARN_ON(ret != 0)) { |
12538 | crtc_mask &= ~(1 << pipe); | |
12539 | continue; | |
e8861675 ML |
12540 | } |
12541 | ||
e2af48c6 | 12542 | last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base); |
e8861675 ML |
12543 | } |
12544 | ||
5a21b665 | 12545 | for_each_pipe(dev_priv, pipe) { |
98187836 VS |
12546 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, |
12547 | pipe); | |
5a21b665 | 12548 | long lret; |
e8861675 | 12549 | |
5a21b665 DV |
12550 | if (!((1 << pipe) & crtc_mask)) |
12551 | continue; | |
d55dbd06 | 12552 | |
5a21b665 DV |
12553 | lret = wait_event_timeout(dev->vblank[pipe].queue, |
12554 | last_vblank_count[pipe] != | |
e2af48c6 | 12555 | drm_crtc_vblank_count(&crtc->base), |
5a21b665 | 12556 | msecs_to_jiffies(50)); |
d55dbd06 | 12557 | |
5a21b665 | 12558 | WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe)); |
d55dbd06 | 12559 | |
e2af48c6 | 12560 | drm_crtc_vblank_put(&crtc->base); |
d55dbd06 ML |
12561 | } |
12562 | } | |
12563 | ||
5a21b665 | 12564 | static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) |
a6747b73 | 12565 | { |
5a21b665 DV |
12566 | /* fb updated, need to unpin old fb */ |
12567 | if (crtc_state->fb_changed) | |
12568 | return true; | |
a6747b73 | 12569 | |
5a21b665 DV |
12570 | /* wm changes, need vblank before final wm's */ |
12571 | if (crtc_state->update_wm_post) | |
12572 | return true; | |
a6747b73 | 12573 | |
5a21b665 DV |
12574 | /* |
12575 | * cxsr is re-enabled after vblank. | |
12576 | * This is already handled by crtc_state->update_wm_post, | |
12577 | * but added for clarity. | |
12578 | */ | |
12579 | if (crtc_state->disable_cxsr) | |
12580 | return true; | |
a6747b73 | 12581 | |
5a21b665 | 12582 | return false; |
e8861675 ML |
12583 | } |
12584 | ||
896e5bb0 L |
12585 | static void intel_update_crtc(struct drm_crtc *crtc, |
12586 | struct drm_atomic_state *state, | |
12587 | struct drm_crtc_state *old_crtc_state, | |
12588 | unsigned int *crtc_vblank_mask) | |
12589 | { | |
12590 | struct drm_device *dev = crtc->dev; | |
12591 | struct drm_i915_private *dev_priv = to_i915(dev); | |
12592 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12593 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state); | |
12594 | bool modeset = needs_modeset(crtc->state); | |
12595 | ||
12596 | if (modeset) { | |
12597 | update_scanline_offset(intel_crtc); | |
12598 | dev_priv->display.crtc_enable(pipe_config, state); | |
12599 | } else { | |
12600 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); | |
12601 | } | |
12602 | ||
12603 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12604 | intel_fbc_enable( | |
12605 | intel_crtc, pipe_config, | |
12606 | to_intel_plane_state(crtc->primary->state)); | |
12607 | } | |
12608 | ||
12609 | drm_atomic_helper_commit_planes_on_crtc(old_crtc_state); | |
12610 | ||
12611 | if (needs_vblank_wait(pipe_config)) | |
12612 | *crtc_vblank_mask |= drm_crtc_mask(crtc); | |
12613 | } | |
12614 | ||
12615 | static void intel_update_crtcs(struct drm_atomic_state *state, | |
12616 | unsigned int *crtc_vblank_mask) | |
12617 | { | |
12618 | struct drm_crtc *crtc; | |
12619 | struct drm_crtc_state *old_crtc_state; | |
12620 | int i; | |
12621 | ||
12622 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
12623 | if (!crtc->state->active) | |
12624 | continue; | |
12625 | ||
12626 | intel_update_crtc(crtc, state, old_crtc_state, | |
12627 | crtc_vblank_mask); | |
12628 | } | |
12629 | } | |
12630 | ||
27082493 L |
12631 | static void skl_update_crtcs(struct drm_atomic_state *state, |
12632 | unsigned int *crtc_vblank_mask) | |
12633 | { | |
0f0f74bc | 12634 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
27082493 L |
12635 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
12636 | struct drm_crtc *crtc; | |
ce0ba283 | 12637 | struct intel_crtc *intel_crtc; |
27082493 | 12638 | struct drm_crtc_state *old_crtc_state; |
ce0ba283 | 12639 | struct intel_crtc_state *cstate; |
27082493 L |
12640 | unsigned int updated = 0; |
12641 | bool progress; | |
12642 | enum pipe pipe; | |
5eff503b ML |
12643 | int i; |
12644 | ||
12645 | const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {}; | |
12646 | ||
12647 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) | |
12648 | /* ignore allocations for crtc's that have been turned off. */ | |
12649 | if (crtc->state->active) | |
12650 | entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb; | |
27082493 L |
12651 | |
12652 | /* | |
12653 | * Whenever the number of active pipes changes, we need to make sure we | |
12654 | * update the pipes in the right order so that their ddb allocations | |
12655 | * never overlap with eachother inbetween CRTC updates. Otherwise we'll | |
12656 | * cause pipe underruns and other bad stuff. | |
12657 | */ | |
12658 | do { | |
27082493 L |
12659 | progress = false; |
12660 | ||
12661 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
12662 | bool vbl_wait = false; | |
12663 | unsigned int cmask = drm_crtc_mask(crtc); | |
ce0ba283 L |
12664 | |
12665 | intel_crtc = to_intel_crtc(crtc); | |
12666 | cstate = to_intel_crtc_state(crtc->state); | |
12667 | pipe = intel_crtc->pipe; | |
27082493 | 12668 | |
5eff503b | 12669 | if (updated & cmask || !cstate->base.active) |
27082493 | 12670 | continue; |
5eff503b ML |
12671 | |
12672 | if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i)) | |
27082493 L |
12673 | continue; |
12674 | ||
12675 | updated |= cmask; | |
5eff503b | 12676 | entries[i] = &cstate->wm.skl.ddb; |
27082493 L |
12677 | |
12678 | /* | |
12679 | * If this is an already active pipe, it's DDB changed, | |
12680 | * and this isn't the last pipe that needs updating | |
12681 | * then we need to wait for a vblank to pass for the | |
12682 | * new ddb allocation to take effect. | |
12683 | */ | |
ce0ba283 | 12684 | if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb, |
512b5527 | 12685 | &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) && |
27082493 L |
12686 | !crtc->state->active_changed && |
12687 | intel_state->wm_results.dirty_pipes != updated) | |
12688 | vbl_wait = true; | |
12689 | ||
12690 | intel_update_crtc(crtc, state, old_crtc_state, | |
12691 | crtc_vblank_mask); | |
12692 | ||
12693 | if (vbl_wait) | |
0f0f74bc | 12694 | intel_wait_for_vblank(dev_priv, pipe); |
27082493 L |
12695 | |
12696 | progress = true; | |
12697 | } | |
12698 | } while (progress); | |
12699 | } | |
12700 | ||
ba318c61 CW |
12701 | static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) |
12702 | { | |
12703 | struct intel_atomic_state *state, *next; | |
12704 | struct llist_node *freed; | |
12705 | ||
12706 | freed = llist_del_all(&dev_priv->atomic_helper.free_list); | |
12707 | llist_for_each_entry_safe(state, next, freed, freed) | |
12708 | drm_atomic_state_put(&state->base); | |
12709 | } | |
12710 | ||
12711 | static void intel_atomic_helper_free_state_worker(struct work_struct *work) | |
12712 | { | |
12713 | struct drm_i915_private *dev_priv = | |
12714 | container_of(work, typeof(*dev_priv), atomic_helper.free_work); | |
12715 | ||
12716 | intel_atomic_helper_free_state(dev_priv); | |
12717 | } | |
12718 | ||
94f05024 | 12719 | static void intel_atomic_commit_tail(struct drm_atomic_state *state) |
a6778b3c | 12720 | { |
94f05024 | 12721 | struct drm_device *dev = state->dev; |
565602d7 | 12722 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 12723 | struct drm_i915_private *dev_priv = to_i915(dev); |
29ceb0e6 | 12724 | struct drm_crtc_state *old_crtc_state; |
7580d774 | 12725 | struct drm_crtc *crtc; |
5a21b665 | 12726 | struct intel_crtc_state *intel_cstate; |
5a21b665 | 12727 | bool hw_check = intel_state->modeset; |
d8fc70b7 | 12728 | u64 put_domains[I915_MAX_PIPES] = {}; |
5a21b665 | 12729 | unsigned crtc_vblank_mask = 0; |
e95433c7 | 12730 | int i; |
a6778b3c | 12731 | |
ea0000f0 DV |
12732 | drm_atomic_helper_wait_for_dependencies(state); |
12733 | ||
c3b32658 | 12734 | if (intel_state->modeset) |
5a21b665 | 12735 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); |
565602d7 | 12736 | |
29ceb0e6 | 12737 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
a539205a ML |
12738 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
12739 | ||
5a21b665 DV |
12740 | if (needs_modeset(crtc->state) || |
12741 | to_intel_crtc_state(crtc->state)->update_pipe) { | |
12742 | hw_check = true; | |
12743 | ||
12744 | put_domains[to_intel_crtc(crtc)->pipe] = | |
12745 | modeset_get_crtc_power_domains(crtc, | |
12746 | to_intel_crtc_state(crtc->state)); | |
12747 | } | |
12748 | ||
61333b60 ML |
12749 | if (!needs_modeset(crtc->state)) |
12750 | continue; | |
12751 | ||
29ceb0e6 | 12752 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
460da916 | 12753 | |
29ceb0e6 VS |
12754 | if (old_crtc_state->active) { |
12755 | intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); | |
4a806558 | 12756 | dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state); |
eddfcbcd | 12757 | intel_crtc->active = false; |
58f9c0bc | 12758 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 12759 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
12760 | |
12761 | /* | |
12762 | * Underruns don't always raise | |
12763 | * interrupts, so check manually. | |
12764 | */ | |
12765 | intel_check_cpu_fifo_underruns(dev_priv); | |
12766 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 | 12767 | |
e62929b3 ML |
12768 | if (!crtc->state->active) { |
12769 | /* | |
12770 | * Make sure we don't call initial_watermarks | |
12771 | * for ILK-style watermark updates. | |
12772 | */ | |
12773 | if (dev_priv->display.atomic_update_watermarks) | |
12774 | dev_priv->display.initial_watermarks(intel_state, | |
12775 | to_intel_crtc_state(crtc->state)); | |
12776 | else | |
12777 | intel_update_watermarks(intel_crtc); | |
12778 | } | |
a539205a | 12779 | } |
b8cecdf5 | 12780 | } |
7758a113 | 12781 | |
ea9d758d DV |
12782 | /* Only after disabling all output pipelines that will be changed can we |
12783 | * update the the output configuration. */ | |
4740b0f2 | 12784 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 12785 | |
565602d7 | 12786 | if (intel_state->modeset) { |
4740b0f2 | 12787 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
33c8df89 | 12788 | |
b0587e4d | 12789 | intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual); |
f6d1973d | 12790 | |
656d1b89 L |
12791 | /* |
12792 | * SKL workaround: bspec recommends we disable the SAGV when we | |
12793 | * have more then one pipe enabled | |
12794 | */ | |
56feca91 | 12795 | if (!intel_can_enable_sagv(state)) |
16dcdc4e | 12796 | intel_disable_sagv(dev_priv); |
656d1b89 | 12797 | |
677100ce | 12798 | intel_modeset_verify_disabled(dev, state); |
4740b0f2 | 12799 | } |
47fab737 | 12800 | |
896e5bb0 | 12801 | /* Complete the events for pipes that have now been disabled */ |
29ceb0e6 | 12802 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
f6ac4b2a | 12803 | bool modeset = needs_modeset(crtc->state); |
80715b2f | 12804 | |
1f7528c4 DV |
12805 | /* Complete events for now disable pipes here. */ |
12806 | if (modeset && !crtc->state->active && crtc->state->event) { | |
12807 | spin_lock_irq(&dev->event_lock); | |
12808 | drm_crtc_send_vblank_event(crtc, crtc->state->event); | |
12809 | spin_unlock_irq(&dev->event_lock); | |
12810 | ||
12811 | crtc->state->event = NULL; | |
12812 | } | |
177246a8 MR |
12813 | } |
12814 | ||
896e5bb0 L |
12815 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
12816 | dev_priv->display.update_crtcs(state, &crtc_vblank_mask); | |
12817 | ||
94f05024 DV |
12818 | /* FIXME: We should call drm_atomic_helper_commit_hw_done() here |
12819 | * already, but still need the state for the delayed optimization. To | |
12820 | * fix this: | |
12821 | * - wrap the optimization/post_plane_update stuff into a per-crtc work. | |
12822 | * - schedule that vblank worker _before_ calling hw_done | |
12823 | * - at the start of commit_tail, cancel it _synchrously | |
12824 | * - switch over to the vblank wait helper in the core after that since | |
12825 | * we don't need out special handling any more. | |
12826 | */ | |
5a21b665 DV |
12827 | if (!state->legacy_cursor_update) |
12828 | intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); | |
12829 | ||
12830 | /* | |
12831 | * Now that the vblank has passed, we can go ahead and program the | |
12832 | * optimal watermarks on platforms that need two-step watermark | |
12833 | * programming. | |
12834 | * | |
12835 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
12836 | */ | |
12837 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
12838 | intel_cstate = to_intel_crtc_state(crtc->state); | |
12839 | ||
12840 | if (dev_priv->display.optimize_watermarks) | |
ccf010fb ML |
12841 | dev_priv->display.optimize_watermarks(intel_state, |
12842 | intel_cstate); | |
5a21b665 DV |
12843 | } |
12844 | ||
12845 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
12846 | intel_post_plane_update(to_intel_crtc_state(old_crtc_state)); | |
12847 | ||
12848 | if (put_domains[i]) | |
12849 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
12850 | ||
677100ce | 12851 | intel_modeset_verify_crtc(crtc, state, old_crtc_state, crtc->state); |
5a21b665 DV |
12852 | } |
12853 | ||
56feca91 | 12854 | if (intel_state->modeset && intel_can_enable_sagv(state)) |
16dcdc4e | 12855 | intel_enable_sagv(dev_priv); |
656d1b89 | 12856 | |
94f05024 DV |
12857 | drm_atomic_helper_commit_hw_done(state); |
12858 | ||
5a21b665 DV |
12859 | if (intel_state->modeset) |
12860 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
12861 | ||
12862 | mutex_lock(&dev->struct_mutex); | |
12863 | drm_atomic_helper_cleanup_planes(dev, state); | |
12864 | mutex_unlock(&dev->struct_mutex); | |
12865 | ||
ea0000f0 DV |
12866 | drm_atomic_helper_commit_cleanup_done(state); |
12867 | ||
0853695c | 12868 | drm_atomic_state_put(state); |
f30da187 | 12869 | |
75714940 MK |
12870 | /* As one of the primary mmio accessors, KMS has a high likelihood |
12871 | * of triggering bugs in unclaimed access. After we finish | |
12872 | * modesetting, see if an error has been flagged, and if so | |
12873 | * enable debugging for the next modeset - and hope we catch | |
12874 | * the culprit. | |
12875 | * | |
12876 | * XXX note that we assume display power is on at this point. | |
12877 | * This might hold true now but we need to add pm helper to check | |
12878 | * unclaimed only when the hardware is on, as atomic commits | |
12879 | * can happen also when the device is completely off. | |
12880 | */ | |
12881 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
ba318c61 CW |
12882 | |
12883 | intel_atomic_helper_free_state(dev_priv); | |
94f05024 DV |
12884 | } |
12885 | ||
12886 | static void intel_atomic_commit_work(struct work_struct *work) | |
12887 | { | |
c004a90b CW |
12888 | struct drm_atomic_state *state = |
12889 | container_of(work, struct drm_atomic_state, commit_work); | |
12890 | ||
94f05024 DV |
12891 | intel_atomic_commit_tail(state); |
12892 | } | |
12893 | ||
c004a90b CW |
12894 | static int __i915_sw_fence_call |
12895 | intel_atomic_commit_ready(struct i915_sw_fence *fence, | |
12896 | enum i915_sw_fence_notify notify) | |
12897 | { | |
12898 | struct intel_atomic_state *state = | |
12899 | container_of(fence, struct intel_atomic_state, commit_ready); | |
12900 | ||
12901 | switch (notify) { | |
12902 | case FENCE_COMPLETE: | |
12903 | if (state->base.commit_work.func) | |
12904 | queue_work(system_unbound_wq, &state->base.commit_work); | |
12905 | break; | |
12906 | ||
12907 | case FENCE_FREE: | |
eb955eee CW |
12908 | { |
12909 | struct intel_atomic_helper *helper = | |
12910 | &to_i915(state->base.dev)->atomic_helper; | |
12911 | ||
12912 | if (llist_add(&state->freed, &helper->free_list)) | |
12913 | schedule_work(&helper->free_work); | |
12914 | break; | |
12915 | } | |
c004a90b CW |
12916 | } |
12917 | ||
12918 | return NOTIFY_DONE; | |
12919 | } | |
12920 | ||
6c9c1b38 DV |
12921 | static void intel_atomic_track_fbs(struct drm_atomic_state *state) |
12922 | { | |
12923 | struct drm_plane_state *old_plane_state; | |
12924 | struct drm_plane *plane; | |
6c9c1b38 DV |
12925 | int i; |
12926 | ||
faf5bf0a CW |
12927 | for_each_plane_in_state(state, plane, old_plane_state, i) |
12928 | i915_gem_track_fb(intel_fb_obj(old_plane_state->fb), | |
12929 | intel_fb_obj(plane->state->fb), | |
12930 | to_intel_plane(plane)->frontbuffer_bit); | |
6c9c1b38 DV |
12931 | } |
12932 | ||
94f05024 DV |
12933 | /** |
12934 | * intel_atomic_commit - commit validated state object | |
12935 | * @dev: DRM device | |
12936 | * @state: the top-level driver state object | |
12937 | * @nonblock: nonblocking commit | |
12938 | * | |
12939 | * This function commits a top-level state object that has been validated | |
12940 | * with drm_atomic_helper_check(). | |
12941 | * | |
94f05024 DV |
12942 | * RETURNS |
12943 | * Zero for success or -errno. | |
12944 | */ | |
12945 | static int intel_atomic_commit(struct drm_device *dev, | |
12946 | struct drm_atomic_state *state, | |
12947 | bool nonblock) | |
12948 | { | |
12949 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
fac5e23e | 12950 | struct drm_i915_private *dev_priv = to_i915(dev); |
94f05024 DV |
12951 | int ret = 0; |
12952 | ||
a5509abd VS |
12953 | /* |
12954 | * The intel_legacy_cursor_update() fast path takes care | |
12955 | * of avoiding the vblank waits for simple cursor | |
12956 | * movement and flips. For cursor on/off and size changes, | |
12957 | * we want to perform the vblank waits so that watermark | |
12958 | * updates happen during the correct frames. Gen9+ have | |
12959 | * double buffered watermarks and so shouldn't need this. | |
12960 | */ | |
12961 | if (INTEL_GEN(dev_priv) < 9) | |
12962 | state->legacy_cursor_update = false; | |
12963 | ||
94f05024 DV |
12964 | ret = drm_atomic_helper_setup_commit(state, nonblock); |
12965 | if (ret) | |
12966 | return ret; | |
12967 | ||
c004a90b CW |
12968 | drm_atomic_state_get(state); |
12969 | i915_sw_fence_init(&intel_state->commit_ready, | |
12970 | intel_atomic_commit_ready); | |
94f05024 | 12971 | |
d07f0e59 | 12972 | ret = intel_atomic_prepare_commit(dev, state); |
94f05024 DV |
12973 | if (ret) { |
12974 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
c004a90b | 12975 | i915_sw_fence_commit(&intel_state->commit_ready); |
94f05024 DV |
12976 | return ret; |
12977 | } | |
12978 | ||
12979 | drm_atomic_helper_swap_state(state, true); | |
12980 | dev_priv->wm.distrust_bios_wm = false; | |
3c0fb588 | 12981 | intel_shared_dpll_swap_state(state); |
6c9c1b38 | 12982 | intel_atomic_track_fbs(state); |
94f05024 | 12983 | |
c3b32658 ML |
12984 | if (intel_state->modeset) { |
12985 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
12986 | sizeof(intel_state->min_pixclk)); | |
12987 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
bb0f4aab VS |
12988 | dev_priv->cdclk.logical = intel_state->cdclk.logical; |
12989 | dev_priv->cdclk.actual = intel_state->cdclk.actual; | |
c3b32658 ML |
12990 | } |
12991 | ||
0853695c | 12992 | drm_atomic_state_get(state); |
c004a90b CW |
12993 | INIT_WORK(&state->commit_work, |
12994 | nonblock ? intel_atomic_commit_work : NULL); | |
12995 | ||
12996 | i915_sw_fence_commit(&intel_state->commit_ready); | |
12997 | if (!nonblock) { | |
12998 | i915_sw_fence_wait(&intel_state->commit_ready); | |
94f05024 | 12999 | intel_atomic_commit_tail(state); |
c004a90b | 13000 | } |
75714940 | 13001 | |
74c090b1 | 13002 | return 0; |
7f27126e JB |
13003 | } |
13004 | ||
c0c36b94 CW |
13005 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13006 | { | |
83a57153 ACO |
13007 | struct drm_device *dev = crtc->dev; |
13008 | struct drm_atomic_state *state; | |
e694eb02 | 13009 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 13010 | int ret; |
83a57153 ACO |
13011 | |
13012 | state = drm_atomic_state_alloc(dev); | |
13013 | if (!state) { | |
78108b7c VS |
13014 | DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory", |
13015 | crtc->base.id, crtc->name); | |
83a57153 ACO |
13016 | return; |
13017 | } | |
13018 | ||
e694eb02 | 13019 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 13020 | |
e694eb02 ML |
13021 | retry: |
13022 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13023 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
13024 | if (!ret) { | |
13025 | if (!crtc_state->active) | |
13026 | goto out; | |
83a57153 | 13027 | |
e694eb02 | 13028 | crtc_state->mode_changed = true; |
74c090b1 | 13029 | ret = drm_atomic_commit(state); |
83a57153 ACO |
13030 | } |
13031 | ||
e694eb02 ML |
13032 | if (ret == -EDEADLK) { |
13033 | drm_atomic_state_clear(state); | |
13034 | drm_modeset_backoff(state->acquire_ctx); | |
13035 | goto retry; | |
4ed9fb37 | 13036 | } |
4be07317 | 13037 | |
e694eb02 | 13038 | out: |
0853695c | 13039 | drm_atomic_state_put(state); |
c0c36b94 CW |
13040 | } |
13041 | ||
a8784875 BP |
13042 | /* |
13043 | * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling | |
13044 | * drm_atomic_helper_legacy_gamma_set() directly. | |
13045 | */ | |
13046 | static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc, | |
13047 | u16 *red, u16 *green, u16 *blue, | |
13048 | uint32_t size) | |
13049 | { | |
13050 | struct drm_device *dev = crtc->dev; | |
13051 | struct drm_mode_config *config = &dev->mode_config; | |
13052 | struct drm_crtc_state *state; | |
13053 | int ret; | |
13054 | ||
13055 | ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size); | |
13056 | if (ret) | |
13057 | return ret; | |
13058 | ||
13059 | /* | |
13060 | * Make sure we update the legacy properties so this works when | |
13061 | * atomic is not enabled. | |
13062 | */ | |
13063 | ||
13064 | state = crtc->state; | |
13065 | ||
13066 | drm_object_property_set_value(&crtc->base, | |
13067 | config->degamma_lut_property, | |
13068 | (state->degamma_lut) ? | |
13069 | state->degamma_lut->base.id : 0); | |
13070 | ||
13071 | drm_object_property_set_value(&crtc->base, | |
13072 | config->ctm_property, | |
13073 | (state->ctm) ? | |
13074 | state->ctm->base.id : 0); | |
13075 | ||
13076 | drm_object_property_set_value(&crtc->base, | |
13077 | config->gamma_lut_property, | |
13078 | (state->gamma_lut) ? | |
13079 | state->gamma_lut->base.id : 0); | |
13080 | ||
13081 | return 0; | |
13082 | } | |
13083 | ||
f6e5b160 | 13084 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
a8784875 | 13085 | .gamma_set = intel_atomic_legacy_gamma_set, |
74c090b1 | 13086 | .set_config = drm_atomic_helper_set_config, |
82cf435b | 13087 | .set_property = drm_atomic_helper_crtc_set_property, |
f6e5b160 | 13088 | .destroy = intel_crtc_destroy, |
4c01ded5 | 13089 | .page_flip = drm_atomic_helper_page_flip, |
1356837e MR |
13090 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13091 | .atomic_destroy_state = intel_crtc_destroy_state, | |
8c6b709d | 13092 | .set_crc_source = intel_crtc_set_crc_source, |
f6e5b160 CW |
13093 | }; |
13094 | ||
6beb8c23 MR |
13095 | /** |
13096 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13097 | * @plane: drm plane to prepare for | |
13098 | * @fb: framebuffer to prepare for presentation | |
13099 | * | |
13100 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13101 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13102 | * bits. Some older platforms need special physical address handling for | |
13103 | * cursor planes. | |
13104 | * | |
f935675f ML |
13105 | * Must be called with struct_mutex held. |
13106 | * | |
6beb8c23 MR |
13107 | * Returns 0 on success, negative error code on failure. |
13108 | */ | |
13109 | int | |
13110 | intel_prepare_plane_fb(struct drm_plane *plane, | |
1832040d | 13111 | struct drm_plane_state *new_state) |
465c120c | 13112 | { |
c004a90b CW |
13113 | struct intel_atomic_state *intel_state = |
13114 | to_intel_atomic_state(new_state->state); | |
b7f05d4a | 13115 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
844f9111 | 13116 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 13117 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 13118 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
c004a90b | 13119 | int ret; |
465c120c | 13120 | |
57822dc6 CW |
13121 | if (obj) { |
13122 | if (plane->type == DRM_PLANE_TYPE_CURSOR && | |
13123 | INTEL_INFO(dev_priv)->cursor_needs_physical) { | |
13124 | const int align = IS_I830(dev_priv) ? 16 * 1024 : 256; | |
13125 | ||
13126 | ret = i915_gem_object_attach_phys(obj, align); | |
13127 | if (ret) { | |
13128 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13129 | return ret; | |
13130 | } | |
13131 | } else { | |
13132 | struct i915_vma *vma; | |
13133 | ||
13134 | vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation); | |
13135 | if (IS_ERR(vma)) { | |
13136 | DRM_DEBUG_KMS("failed to pin object\n"); | |
13137 | return PTR_ERR(vma); | |
13138 | } | |
13139 | ||
13140 | to_intel_plane_state(new_state)->vma = vma; | |
13141 | } | |
13142 | } | |
13143 | ||
1ee49399 | 13144 | if (!obj && !old_obj) |
465c120c MR |
13145 | return 0; |
13146 | ||
5008e874 ML |
13147 | if (old_obj) { |
13148 | struct drm_crtc_state *crtc_state = | |
c004a90b CW |
13149 | drm_atomic_get_existing_crtc_state(new_state->state, |
13150 | plane->state->crtc); | |
5008e874 ML |
13151 | |
13152 | /* Big Hammer, we also need to ensure that any pending | |
13153 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
13154 | * current scanout is retired before unpinning the old | |
13155 | * framebuffer. Note that we rely on userspace rendering | |
13156 | * into the buffer attached to the pipe they are waiting | |
13157 | * on. If not, userspace generates a GPU hang with IPEHR | |
13158 | * point to the MI_WAIT_FOR_EVENT. | |
13159 | * | |
13160 | * This should only fail upon a hung GPU, in which case we | |
13161 | * can safely continue. | |
13162 | */ | |
c004a90b CW |
13163 | if (needs_modeset(crtc_state)) { |
13164 | ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, | |
13165 | old_obj->resv, NULL, | |
13166 | false, 0, | |
13167 | GFP_KERNEL); | |
13168 | if (ret < 0) | |
13169 | return ret; | |
f4457ae7 | 13170 | } |
5008e874 ML |
13171 | } |
13172 | ||
c004a90b CW |
13173 | if (new_state->fence) { /* explicit fencing */ |
13174 | ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready, | |
13175 | new_state->fence, | |
13176 | I915_FENCE_TIMEOUT, | |
13177 | GFP_KERNEL); | |
13178 | if (ret < 0) | |
13179 | return ret; | |
13180 | } | |
13181 | ||
c37efb99 CW |
13182 | if (!obj) |
13183 | return 0; | |
13184 | ||
c004a90b CW |
13185 | if (!new_state->fence) { /* implicit fencing */ |
13186 | ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, | |
13187 | obj->resv, NULL, | |
13188 | false, I915_FENCE_TIMEOUT, | |
13189 | GFP_KERNEL); | |
13190 | if (ret < 0) | |
13191 | return ret; | |
6b5e90f5 CW |
13192 | |
13193 | i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); | |
c004a90b | 13194 | } |
5a21b665 | 13195 | |
d07f0e59 | 13196 | return 0; |
6beb8c23 MR |
13197 | } |
13198 | ||
38f3ce3a MR |
13199 | /** |
13200 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13201 | * @plane: drm plane to clean up for | |
13202 | * @fb: old framebuffer that was on plane | |
13203 | * | |
13204 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
13205 | * |
13206 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
13207 | */ |
13208 | void | |
13209 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
1832040d | 13210 | struct drm_plane_state *old_state) |
38f3ce3a | 13211 | { |
be1e3415 | 13212 | struct i915_vma *vma; |
38f3ce3a | 13213 | |
be1e3415 CW |
13214 | /* Should only be called after a successful intel_prepare_plane_fb()! */ |
13215 | vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma); | |
13216 | if (vma) | |
13217 | intel_unpin_fb_vma(vma); | |
465c120c MR |
13218 | } |
13219 | ||
6156a456 CK |
13220 | int |
13221 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
13222 | { | |
5b7280f0 | 13223 | struct drm_i915_private *dev_priv; |
6156a456 | 13224 | int max_scale; |
5b7280f0 | 13225 | int crtc_clock, max_dotclk; |
6156a456 | 13226 | |
bf8a0af0 | 13227 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
13228 | return DRM_PLANE_HELPER_NO_SCALING; |
13229 | ||
5b7280f0 ACO |
13230 | dev_priv = to_i915(intel_crtc->base.dev); |
13231 | ||
6156a456 | 13232 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; |
5b7280f0 ACO |
13233 | max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk; |
13234 | ||
13235 | if (IS_GEMINILAKE(dev_priv)) | |
13236 | max_dotclk *= 2; | |
6156a456 | 13237 | |
5b7280f0 | 13238 | if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock)) |
6156a456 CK |
13239 | return DRM_PLANE_HELPER_NO_SCALING; |
13240 | ||
13241 | /* | |
13242 | * skl max scale is lower of: | |
13243 | * close to 3 but not 3, -1 is for that purpose | |
13244 | * or | |
13245 | * cdclk/crtc_clock | |
13246 | */ | |
5b7280f0 ACO |
13247 | max_scale = min((1 << 16) * 3 - 1, |
13248 | (1 << 8) * ((max_dotclk << 8) / crtc_clock)); | |
6156a456 CK |
13249 | |
13250 | return max_scale; | |
13251 | } | |
13252 | ||
465c120c | 13253 | static int |
3c692a41 | 13254 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 13255 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
13256 | struct intel_plane_state *state) |
13257 | { | |
b63a16f6 | 13258 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
2b875c22 | 13259 | struct drm_crtc *crtc = state->base.crtc; |
6156a456 | 13260 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
13261 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
13262 | bool can_position = false; | |
b63a16f6 | 13263 | int ret; |
465c120c | 13264 | |
b63a16f6 | 13265 | if (INTEL_GEN(dev_priv) >= 9) { |
693bdc28 VS |
13266 | /* use scaler when colorkey is not required */ |
13267 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
13268 | min_scale = 1; | |
13269 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
13270 | } | |
d8106366 | 13271 | can_position = true; |
6156a456 | 13272 | } |
d8106366 | 13273 | |
cc926387 DV |
13274 | ret = drm_plane_helper_check_state(&state->base, |
13275 | &state->clip, | |
13276 | min_scale, max_scale, | |
13277 | can_position, true); | |
b63a16f6 VS |
13278 | if (ret) |
13279 | return ret; | |
13280 | ||
cc926387 | 13281 | if (!state->base.fb) |
b63a16f6 VS |
13282 | return 0; |
13283 | ||
13284 | if (INTEL_GEN(dev_priv) >= 9) { | |
13285 | ret = skl_check_plane_surface(state); | |
13286 | if (ret) | |
13287 | return ret; | |
13288 | } | |
13289 | ||
13290 | return 0; | |
14af293f GP |
13291 | } |
13292 | ||
5a21b665 DV |
13293 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
13294 | struct drm_crtc_state *old_crtc_state) | |
13295 | { | |
13296 | struct drm_device *dev = crtc->dev; | |
62e0fb88 | 13297 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 13298 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b707aa50 L |
13299 | struct intel_crtc_state *intel_cstate = |
13300 | to_intel_crtc_state(crtc->state); | |
ccf010fb | 13301 | struct intel_crtc_state *old_intel_cstate = |
5a21b665 | 13302 | to_intel_crtc_state(old_crtc_state); |
ccf010fb ML |
13303 | struct intel_atomic_state *old_intel_state = |
13304 | to_intel_atomic_state(old_crtc_state->state); | |
5a21b665 DV |
13305 | bool modeset = needs_modeset(crtc->state); |
13306 | ||
13307 | /* Perform vblank evasion around commit operation */ | |
13308 | intel_pipe_update_start(intel_crtc); | |
13309 | ||
13310 | if (modeset) | |
e62929b3 | 13311 | goto out; |
5a21b665 DV |
13312 | |
13313 | if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) { | |
13314 | intel_color_set_csc(crtc->state); | |
13315 | intel_color_load_luts(crtc->state); | |
13316 | } | |
13317 | ||
ccf010fb ML |
13318 | if (intel_cstate->update_pipe) |
13319 | intel_update_pipe_config(intel_crtc, old_intel_cstate); | |
13320 | else if (INTEL_GEN(dev_priv) >= 9) | |
5a21b665 | 13321 | skl_detach_scalers(intel_crtc); |
62e0fb88 | 13322 | |
e62929b3 | 13323 | out: |
ccf010fb ML |
13324 | if (dev_priv->display.atomic_update_watermarks) |
13325 | dev_priv->display.atomic_update_watermarks(old_intel_state, | |
13326 | intel_cstate); | |
5a21b665 DV |
13327 | } |
13328 | ||
13329 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, | |
13330 | struct drm_crtc_state *old_crtc_state) | |
13331 | { | |
13332 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
13333 | ||
13334 | intel_pipe_update_end(intel_crtc, NULL); | |
13335 | } | |
13336 | ||
cf4c7c12 | 13337 | /** |
4a3b8769 MR |
13338 | * intel_plane_destroy - destroy a plane |
13339 | * @plane: plane to destroy | |
cf4c7c12 | 13340 | * |
4a3b8769 MR |
13341 | * Common destruction function for all types of planes (primary, cursor, |
13342 | * sprite). | |
cf4c7c12 | 13343 | */ |
4a3b8769 | 13344 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c | 13345 | { |
465c120c | 13346 | drm_plane_cleanup(plane); |
69ae561f | 13347 | kfree(to_intel_plane(plane)); |
465c120c MR |
13348 | } |
13349 | ||
65a3fea0 | 13350 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
13351 | .update_plane = drm_atomic_helper_update_plane, |
13352 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 13353 | .destroy = intel_plane_destroy, |
c196e1d6 | 13354 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
13355 | .atomic_get_property = intel_plane_atomic_get_property, |
13356 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
13357 | .atomic_duplicate_state = intel_plane_duplicate_state, |
13358 | .atomic_destroy_state = intel_plane_destroy_state, | |
465c120c MR |
13359 | }; |
13360 | ||
f79f2692 ML |
13361 | static int |
13362 | intel_legacy_cursor_update(struct drm_plane *plane, | |
13363 | struct drm_crtc *crtc, | |
13364 | struct drm_framebuffer *fb, | |
13365 | int crtc_x, int crtc_y, | |
13366 | unsigned int crtc_w, unsigned int crtc_h, | |
13367 | uint32_t src_x, uint32_t src_y, | |
13368 | uint32_t src_w, uint32_t src_h) | |
13369 | { | |
13370 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
13371 | int ret; | |
13372 | struct drm_plane_state *old_plane_state, *new_plane_state; | |
13373 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13374 | struct drm_framebuffer *old_fb; | |
13375 | struct drm_crtc_state *crtc_state = crtc->state; | |
be1e3415 | 13376 | struct i915_vma *old_vma; |
f79f2692 ML |
13377 | |
13378 | /* | |
13379 | * When crtc is inactive or there is a modeset pending, | |
13380 | * wait for it to complete in the slowpath | |
13381 | */ | |
13382 | if (!crtc_state->active || needs_modeset(crtc_state) || | |
13383 | to_intel_crtc_state(crtc_state)->update_pipe) | |
13384 | goto slow; | |
13385 | ||
13386 | old_plane_state = plane->state; | |
13387 | ||
13388 | /* | |
13389 | * If any parameters change that may affect watermarks, | |
13390 | * take the slowpath. Only changing fb or position should be | |
13391 | * in the fastpath. | |
13392 | */ | |
13393 | if (old_plane_state->crtc != crtc || | |
13394 | old_plane_state->src_w != src_w || | |
13395 | old_plane_state->src_h != src_h || | |
13396 | old_plane_state->crtc_w != crtc_w || | |
13397 | old_plane_state->crtc_h != crtc_h || | |
a5509abd | 13398 | !old_plane_state->fb != !fb) |
f79f2692 ML |
13399 | goto slow; |
13400 | ||
13401 | new_plane_state = intel_plane_duplicate_state(plane); | |
13402 | if (!new_plane_state) | |
13403 | return -ENOMEM; | |
13404 | ||
13405 | drm_atomic_set_fb_for_plane(new_plane_state, fb); | |
13406 | ||
13407 | new_plane_state->src_x = src_x; | |
13408 | new_plane_state->src_y = src_y; | |
13409 | new_plane_state->src_w = src_w; | |
13410 | new_plane_state->src_h = src_h; | |
13411 | new_plane_state->crtc_x = crtc_x; | |
13412 | new_plane_state->crtc_y = crtc_y; | |
13413 | new_plane_state->crtc_w = crtc_w; | |
13414 | new_plane_state->crtc_h = crtc_h; | |
13415 | ||
13416 | ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state), | |
13417 | to_intel_plane_state(new_plane_state)); | |
13418 | if (ret) | |
13419 | goto out_free; | |
13420 | ||
f79f2692 ML |
13421 | ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex); |
13422 | if (ret) | |
13423 | goto out_free; | |
13424 | ||
13425 | if (INTEL_INFO(dev_priv)->cursor_needs_physical) { | |
13426 | int align = IS_I830(dev_priv) ? 16 * 1024 : 256; | |
13427 | ||
13428 | ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align); | |
13429 | if (ret) { | |
13430 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13431 | goto out_unlock; | |
13432 | } | |
13433 | } else { | |
13434 | struct i915_vma *vma; | |
13435 | ||
13436 | vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation); | |
13437 | if (IS_ERR(vma)) { | |
13438 | DRM_DEBUG_KMS("failed to pin object\n"); | |
13439 | ||
13440 | ret = PTR_ERR(vma); | |
13441 | goto out_unlock; | |
13442 | } | |
be1e3415 CW |
13443 | |
13444 | to_intel_plane_state(new_plane_state)->vma = vma; | |
f79f2692 ML |
13445 | } |
13446 | ||
13447 | old_fb = old_plane_state->fb; | |
be1e3415 | 13448 | old_vma = to_intel_plane_state(old_plane_state)->vma; |
f79f2692 ML |
13449 | |
13450 | i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb), | |
13451 | intel_plane->frontbuffer_bit); | |
13452 | ||
13453 | /* Swap plane state */ | |
13454 | new_plane_state->fence = old_plane_state->fence; | |
13455 | *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state); | |
13456 | new_plane_state->fence = NULL; | |
13457 | new_plane_state->fb = old_fb; | |
be1e3415 | 13458 | to_intel_plane_state(new_plane_state)->vma = old_vma; |
f79f2692 | 13459 | |
a5509abd VS |
13460 | if (plane->state->visible) |
13461 | intel_plane->update_plane(plane, | |
13462 | to_intel_crtc_state(crtc->state), | |
13463 | to_intel_plane_state(plane->state)); | |
13464 | else | |
13465 | intel_plane->disable_plane(plane, crtc); | |
f79f2692 ML |
13466 | |
13467 | intel_cleanup_plane_fb(plane, new_plane_state); | |
13468 | ||
13469 | out_unlock: | |
13470 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
13471 | out_free: | |
13472 | intel_plane_destroy_state(plane, new_plane_state); | |
13473 | return ret; | |
13474 | ||
f79f2692 ML |
13475 | slow: |
13476 | return drm_atomic_helper_update_plane(plane, crtc, fb, | |
13477 | crtc_x, crtc_y, crtc_w, crtc_h, | |
13478 | src_x, src_y, src_w, src_h); | |
13479 | } | |
13480 | ||
13481 | static const struct drm_plane_funcs intel_cursor_plane_funcs = { | |
13482 | .update_plane = intel_legacy_cursor_update, | |
13483 | .disable_plane = drm_atomic_helper_disable_plane, | |
13484 | .destroy = intel_plane_destroy, | |
13485 | .set_property = drm_atomic_helper_plane_set_property, | |
13486 | .atomic_get_property = intel_plane_atomic_get_property, | |
13487 | .atomic_set_property = intel_plane_atomic_set_property, | |
13488 | .atomic_duplicate_state = intel_plane_duplicate_state, | |
13489 | .atomic_destroy_state = intel_plane_destroy_state, | |
13490 | }; | |
13491 | ||
b079bd17 | 13492 | static struct intel_plane * |
580503c7 | 13493 | intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) |
465c120c | 13494 | { |
fca0ce2a VS |
13495 | struct intel_plane *primary = NULL; |
13496 | struct intel_plane_state *state = NULL; | |
465c120c | 13497 | const uint32_t *intel_primary_formats; |
93ca7e00 | 13498 | unsigned int supported_rotations; |
45e3743a | 13499 | unsigned int num_formats; |
fca0ce2a | 13500 | int ret; |
465c120c MR |
13501 | |
13502 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
b079bd17 VS |
13503 | if (!primary) { |
13504 | ret = -ENOMEM; | |
fca0ce2a | 13505 | goto fail; |
b079bd17 | 13506 | } |
465c120c | 13507 | |
8e7d688b | 13508 | state = intel_create_plane_state(&primary->base); |
b079bd17 VS |
13509 | if (!state) { |
13510 | ret = -ENOMEM; | |
fca0ce2a | 13511 | goto fail; |
b079bd17 VS |
13512 | } |
13513 | ||
8e7d688b | 13514 | primary->base.state = &state->base; |
ea2c67bb | 13515 | |
465c120c MR |
13516 | primary->can_scale = false; |
13517 | primary->max_downscale = 1; | |
580503c7 | 13518 | if (INTEL_GEN(dev_priv) >= 9) { |
6156a456 | 13519 | primary->can_scale = true; |
af99ceda | 13520 | state->scaler_id = -1; |
6156a456 | 13521 | } |
465c120c | 13522 | primary->pipe = pipe; |
e3c566df VS |
13523 | /* |
13524 | * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS | |
13525 | * port is hooked to pipe B. Hence we want plane A feeding pipe B. | |
13526 | */ | |
13527 | if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4) | |
13528 | primary->plane = (enum plane) !pipe; | |
13529 | else | |
13530 | primary->plane = (enum plane) pipe; | |
b14e5848 | 13531 | primary->id = PLANE_PRIMARY; |
a9ff8714 | 13532 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 13533 | primary->check_plane = intel_check_primary_plane; |
465c120c | 13534 | |
580503c7 | 13535 | if (INTEL_GEN(dev_priv) >= 9) { |
6c0fd451 DL |
13536 | intel_primary_formats = skl_primary_formats; |
13537 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
a8d201af ML |
13538 | |
13539 | primary->update_plane = skylake_update_primary_plane; | |
13540 | primary->disable_plane = skylake_disable_primary_plane; | |
6e266956 | 13541 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
a8d201af ML |
13542 | intel_primary_formats = i965_primary_formats; |
13543 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
13544 | ||
13545 | primary->update_plane = ironlake_update_primary_plane; | |
13546 | primary->disable_plane = i9xx_disable_primary_plane; | |
580503c7 | 13547 | } else if (INTEL_GEN(dev_priv) >= 4) { |
568db4f2 DL |
13548 | intel_primary_formats = i965_primary_formats; |
13549 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
a8d201af ML |
13550 | |
13551 | primary->update_plane = i9xx_update_primary_plane; | |
13552 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
13553 | } else { |
13554 | intel_primary_formats = i8xx_primary_formats; | |
13555 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
a8d201af ML |
13556 | |
13557 | primary->update_plane = i9xx_update_primary_plane; | |
13558 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
13559 | } |
13560 | ||
580503c7 VS |
13561 | if (INTEL_GEN(dev_priv) >= 9) |
13562 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, | |
13563 | 0, &intel_plane_funcs, | |
38573dc1 VS |
13564 | intel_primary_formats, num_formats, |
13565 | DRM_PLANE_TYPE_PRIMARY, | |
13566 | "plane 1%c", pipe_name(pipe)); | |
9beb5fea | 13567 | else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
580503c7 VS |
13568 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, |
13569 | 0, &intel_plane_funcs, | |
38573dc1 VS |
13570 | intel_primary_formats, num_formats, |
13571 | DRM_PLANE_TYPE_PRIMARY, | |
13572 | "primary %c", pipe_name(pipe)); | |
13573 | else | |
580503c7 VS |
13574 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, |
13575 | 0, &intel_plane_funcs, | |
38573dc1 VS |
13576 | intel_primary_formats, num_formats, |
13577 | DRM_PLANE_TYPE_PRIMARY, | |
13578 | "plane %c", plane_name(primary->plane)); | |
fca0ce2a VS |
13579 | if (ret) |
13580 | goto fail; | |
48404c1e | 13581 | |
5481e27f | 13582 | if (INTEL_GEN(dev_priv) >= 9) { |
93ca7e00 VS |
13583 | supported_rotations = |
13584 | DRM_ROTATE_0 | DRM_ROTATE_90 | | |
13585 | DRM_ROTATE_180 | DRM_ROTATE_270; | |
4ea7be2b VS |
13586 | } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { |
13587 | supported_rotations = | |
13588 | DRM_ROTATE_0 | DRM_ROTATE_180 | | |
13589 | DRM_REFLECT_X; | |
5481e27f | 13590 | } else if (INTEL_GEN(dev_priv) >= 4) { |
93ca7e00 VS |
13591 | supported_rotations = |
13592 | DRM_ROTATE_0 | DRM_ROTATE_180; | |
13593 | } else { | |
13594 | supported_rotations = DRM_ROTATE_0; | |
13595 | } | |
13596 | ||
5481e27f | 13597 | if (INTEL_GEN(dev_priv) >= 4) |
93ca7e00 VS |
13598 | drm_plane_create_rotation_property(&primary->base, |
13599 | DRM_ROTATE_0, | |
13600 | supported_rotations); | |
48404c1e | 13601 | |
ea2c67bb MR |
13602 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
13603 | ||
b079bd17 | 13604 | return primary; |
fca0ce2a VS |
13605 | |
13606 | fail: | |
13607 | kfree(state); | |
13608 | kfree(primary); | |
13609 | ||
b079bd17 | 13610 | return ERR_PTR(ret); |
465c120c MR |
13611 | } |
13612 | ||
3d7d6510 | 13613 | static int |
852e787c | 13614 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 13615 | struct intel_crtc_state *crtc_state, |
852e787c | 13616 | struct intel_plane_state *state) |
3d7d6510 | 13617 | { |
2b875c22 | 13618 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 13619 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
b29ec92c | 13620 | enum pipe pipe = to_intel_plane(plane)->pipe; |
757f9a3e GP |
13621 | unsigned stride; |
13622 | int ret; | |
3d7d6510 | 13623 | |
f8856a44 VS |
13624 | ret = drm_plane_helper_check_state(&state->base, |
13625 | &state->clip, | |
13626 | DRM_PLANE_HELPER_NO_SCALING, | |
13627 | DRM_PLANE_HELPER_NO_SCALING, | |
13628 | true, true); | |
757f9a3e GP |
13629 | if (ret) |
13630 | return ret; | |
13631 | ||
757f9a3e GP |
13632 | /* if we want to turn off the cursor ignore width and height */ |
13633 | if (!obj) | |
da20eabd | 13634 | return 0; |
757f9a3e | 13635 | |
757f9a3e | 13636 | /* Check for which cursor types we support */ |
50a0bc90 TU |
13637 | if (!cursor_size_ok(to_i915(plane->dev), state->base.crtc_w, |
13638 | state->base.crtc_h)) { | |
ea2c67bb MR |
13639 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
13640 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
13641 | return -EINVAL; |
13642 | } | |
13643 | ||
ea2c67bb MR |
13644 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
13645 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
13646 | DRM_DEBUG_KMS("buffer is too small\n"); |
13647 | return -ENOMEM; | |
13648 | } | |
13649 | ||
bae781b2 | 13650 | if (fb->modifier != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 13651 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 13652 | return -EINVAL; |
32b7eeec MR |
13653 | } |
13654 | ||
b29ec92c VS |
13655 | /* |
13656 | * There's something wrong with the cursor on CHV pipe C. | |
13657 | * If it straddles the left edge of the screen then | |
13658 | * moving it away from the edge or disabling it often | |
13659 | * results in a pipe underrun, and often that can lead to | |
13660 | * dead pipe (constant underrun reported, and it scans | |
13661 | * out just a solid color). To recover from that, the | |
13662 | * display power well must be turned off and on again. | |
13663 | * Refuse the put the cursor into that compromised position. | |
13664 | */ | |
920a14b2 | 13665 | if (IS_CHERRYVIEW(to_i915(plane->dev)) && pipe == PIPE_C && |
936e71e3 | 13666 | state->base.visible && state->base.crtc_x < 0) { |
b29ec92c VS |
13667 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); |
13668 | return -EINVAL; | |
13669 | } | |
13670 | ||
da20eabd | 13671 | return 0; |
852e787c | 13672 | } |
3d7d6510 | 13673 | |
a8ad0d8e ML |
13674 | static void |
13675 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 13676 | struct drm_crtc *crtc) |
a8ad0d8e | 13677 | { |
f2858021 ML |
13678 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13679 | ||
13680 | intel_crtc->cursor_addr = 0; | |
55a08b3f | 13681 | intel_crtc_update_cursor(crtc, NULL); |
a8ad0d8e ML |
13682 | } |
13683 | ||
f4a2cf29 | 13684 | static void |
55a08b3f ML |
13685 | intel_update_cursor_plane(struct drm_plane *plane, |
13686 | const struct intel_crtc_state *crtc_state, | |
13687 | const struct intel_plane_state *state) | |
852e787c | 13688 | { |
55a08b3f ML |
13689 | struct drm_crtc *crtc = crtc_state->base.crtc; |
13690 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b7f05d4a | 13691 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
2b875c22 | 13692 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 13693 | uint32_t addr; |
852e787c | 13694 | |
f4a2cf29 | 13695 | if (!obj) |
a912f12f | 13696 | addr = 0; |
b7f05d4a | 13697 | else if (!INTEL_INFO(dev_priv)->cursor_needs_physical) |
be1e3415 | 13698 | addr = intel_plane_ggtt_offset(state); |
f4a2cf29 | 13699 | else |
a912f12f | 13700 | addr = obj->phys_handle->busaddr; |
852e787c | 13701 | |
a912f12f | 13702 | intel_crtc->cursor_addr = addr; |
55a08b3f | 13703 | intel_crtc_update_cursor(crtc, state); |
852e787c GP |
13704 | } |
13705 | ||
b079bd17 | 13706 | static struct intel_plane * |
580503c7 | 13707 | intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) |
3d7d6510 | 13708 | { |
fca0ce2a VS |
13709 | struct intel_plane *cursor = NULL; |
13710 | struct intel_plane_state *state = NULL; | |
13711 | int ret; | |
3d7d6510 MR |
13712 | |
13713 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
b079bd17 VS |
13714 | if (!cursor) { |
13715 | ret = -ENOMEM; | |
fca0ce2a | 13716 | goto fail; |
b079bd17 | 13717 | } |
3d7d6510 | 13718 | |
8e7d688b | 13719 | state = intel_create_plane_state(&cursor->base); |
b079bd17 VS |
13720 | if (!state) { |
13721 | ret = -ENOMEM; | |
fca0ce2a | 13722 | goto fail; |
b079bd17 VS |
13723 | } |
13724 | ||
8e7d688b | 13725 | cursor->base.state = &state->base; |
ea2c67bb | 13726 | |
3d7d6510 MR |
13727 | cursor->can_scale = false; |
13728 | cursor->max_downscale = 1; | |
13729 | cursor->pipe = pipe; | |
13730 | cursor->plane = pipe; | |
b14e5848 | 13731 | cursor->id = PLANE_CURSOR; |
a9ff8714 | 13732 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 | 13733 | cursor->check_plane = intel_check_cursor_plane; |
55a08b3f | 13734 | cursor->update_plane = intel_update_cursor_plane; |
a8ad0d8e | 13735 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 | 13736 | |
580503c7 | 13737 | ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, |
f79f2692 | 13738 | 0, &intel_cursor_plane_funcs, |
fca0ce2a VS |
13739 | intel_cursor_formats, |
13740 | ARRAY_SIZE(intel_cursor_formats), | |
38573dc1 VS |
13741 | DRM_PLANE_TYPE_CURSOR, |
13742 | "cursor %c", pipe_name(pipe)); | |
fca0ce2a VS |
13743 | if (ret) |
13744 | goto fail; | |
4398ad45 | 13745 | |
5481e27f | 13746 | if (INTEL_GEN(dev_priv) >= 4) |
93ca7e00 VS |
13747 | drm_plane_create_rotation_property(&cursor->base, |
13748 | DRM_ROTATE_0, | |
13749 | DRM_ROTATE_0 | | |
13750 | DRM_ROTATE_180); | |
4398ad45 | 13751 | |
580503c7 | 13752 | if (INTEL_GEN(dev_priv) >= 9) |
af99ceda CK |
13753 | state->scaler_id = -1; |
13754 | ||
ea2c67bb MR |
13755 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
13756 | ||
b079bd17 | 13757 | return cursor; |
fca0ce2a VS |
13758 | |
13759 | fail: | |
13760 | kfree(state); | |
13761 | kfree(cursor); | |
13762 | ||
b079bd17 | 13763 | return ERR_PTR(ret); |
3d7d6510 MR |
13764 | } |
13765 | ||
1c74eeaf NM |
13766 | static void intel_crtc_init_scalers(struct intel_crtc *crtc, |
13767 | struct intel_crtc_state *crtc_state) | |
549e2bfb | 13768 | { |
65edccce VS |
13769 | struct intel_crtc_scaler_state *scaler_state = |
13770 | &crtc_state->scaler_state; | |
1c74eeaf | 13771 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
549e2bfb | 13772 | int i; |
549e2bfb | 13773 | |
1c74eeaf NM |
13774 | crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe]; |
13775 | if (!crtc->num_scalers) | |
13776 | return; | |
13777 | ||
65edccce VS |
13778 | for (i = 0; i < crtc->num_scalers; i++) { |
13779 | struct intel_scaler *scaler = &scaler_state->scalers[i]; | |
13780 | ||
13781 | scaler->in_use = 0; | |
13782 | scaler->mode = PS_SCALER_MODE_DYN; | |
549e2bfb CK |
13783 | } |
13784 | ||
13785 | scaler_state->scaler_id = -1; | |
13786 | } | |
13787 | ||
5ab0d85b | 13788 | static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) |
79e53945 JB |
13789 | { |
13790 | struct intel_crtc *intel_crtc; | |
f5de6e07 | 13791 | struct intel_crtc_state *crtc_state = NULL; |
b079bd17 VS |
13792 | struct intel_plane *primary = NULL; |
13793 | struct intel_plane *cursor = NULL; | |
a81d6fa0 | 13794 | int sprite, ret; |
79e53945 | 13795 | |
955382f3 | 13796 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
b079bd17 VS |
13797 | if (!intel_crtc) |
13798 | return -ENOMEM; | |
79e53945 | 13799 | |
f5de6e07 | 13800 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
b079bd17 VS |
13801 | if (!crtc_state) { |
13802 | ret = -ENOMEM; | |
f5de6e07 | 13803 | goto fail; |
b079bd17 | 13804 | } |
550acefd ACO |
13805 | intel_crtc->config = crtc_state; |
13806 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 13807 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 13808 | |
580503c7 | 13809 | primary = intel_primary_plane_create(dev_priv, pipe); |
b079bd17 VS |
13810 | if (IS_ERR(primary)) { |
13811 | ret = PTR_ERR(primary); | |
3d7d6510 | 13812 | goto fail; |
b079bd17 | 13813 | } |
d97d7b48 | 13814 | intel_crtc->plane_ids_mask |= BIT(primary->id); |
3d7d6510 | 13815 | |
a81d6fa0 | 13816 | for_each_sprite(dev_priv, pipe, sprite) { |
b079bd17 VS |
13817 | struct intel_plane *plane; |
13818 | ||
580503c7 | 13819 | plane = intel_sprite_plane_create(dev_priv, pipe, sprite); |
d2b2cbce | 13820 | if (IS_ERR(plane)) { |
b079bd17 VS |
13821 | ret = PTR_ERR(plane); |
13822 | goto fail; | |
13823 | } | |
d97d7b48 | 13824 | intel_crtc->plane_ids_mask |= BIT(plane->id); |
a81d6fa0 VS |
13825 | } |
13826 | ||
580503c7 | 13827 | cursor = intel_cursor_plane_create(dev_priv, pipe); |
d2b2cbce | 13828 | if (IS_ERR(cursor)) { |
b079bd17 | 13829 | ret = PTR_ERR(cursor); |
3d7d6510 | 13830 | goto fail; |
b079bd17 | 13831 | } |
d97d7b48 | 13832 | intel_crtc->plane_ids_mask |= BIT(cursor->id); |
3d7d6510 | 13833 | |
5ab0d85b | 13834 | ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base, |
b079bd17 VS |
13835 | &primary->base, &cursor->base, |
13836 | &intel_crtc_funcs, | |
4d5d72b7 | 13837 | "pipe %c", pipe_name(pipe)); |
3d7d6510 MR |
13838 | if (ret) |
13839 | goto fail; | |
79e53945 | 13840 | |
80824003 | 13841 | intel_crtc->pipe = pipe; |
e3c566df | 13842 | intel_crtc->plane = primary->plane; |
80824003 | 13843 | |
4b0e333e CW |
13844 | intel_crtc->cursor_base = ~0; |
13845 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 13846 | intel_crtc->cursor_size = ~0; |
8d7849db | 13847 | |
852eb00d VS |
13848 | intel_crtc->wm.cxsr_allowed = true; |
13849 | ||
1c74eeaf NM |
13850 | /* initialize shared scalers */ |
13851 | intel_crtc_init_scalers(intel_crtc, crtc_state); | |
13852 | ||
22fd0fab JB |
13853 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
13854 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
e2af48c6 VS |
13855 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc; |
13856 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc; | |
22fd0fab | 13857 | |
79e53945 | 13858 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 | 13859 | |
8563b1e8 LL |
13860 | intel_color_init(&intel_crtc->base); |
13861 | ||
87b6b101 | 13862 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
b079bd17 VS |
13863 | |
13864 | return 0; | |
3d7d6510 MR |
13865 | |
13866 | fail: | |
b079bd17 VS |
13867 | /* |
13868 | * drm_mode_config_cleanup() will free up any | |
13869 | * crtcs/planes already initialized. | |
13870 | */ | |
f5de6e07 | 13871 | kfree(crtc_state); |
3d7d6510 | 13872 | kfree(intel_crtc); |
b079bd17 VS |
13873 | |
13874 | return ret; | |
79e53945 JB |
13875 | } |
13876 | ||
752aa88a JB |
13877 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
13878 | { | |
13879 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 13880 | struct drm_device *dev = connector->base.dev; |
752aa88a | 13881 | |
51fd371b | 13882 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 13883 | |
d3babd3f | 13884 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
13885 | return INVALID_PIPE; |
13886 | ||
13887 | return to_intel_crtc(encoder->crtc)->pipe; | |
13888 | } | |
13889 | ||
08d7b3d1 | 13890 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 13891 | struct drm_file *file) |
08d7b3d1 | 13892 | { |
08d7b3d1 | 13893 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 13894 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 13895 | struct intel_crtc *crtc; |
08d7b3d1 | 13896 | |
7707e653 | 13897 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
71240ed2 | 13898 | if (!drmmode_crtc) |
3f2c2057 | 13899 | return -ENOENT; |
08d7b3d1 | 13900 | |
7707e653 | 13901 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 13902 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 13903 | |
c05422d5 | 13904 | return 0; |
08d7b3d1 CW |
13905 | } |
13906 | ||
66a9278e | 13907 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 13908 | { |
66a9278e DV |
13909 | struct drm_device *dev = encoder->base.dev; |
13910 | struct intel_encoder *source_encoder; | |
79e53945 | 13911 | int index_mask = 0; |
79e53945 JB |
13912 | int entry = 0; |
13913 | ||
b2784e15 | 13914 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 13915 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
13916 | index_mask |= (1 << entry); |
13917 | ||
79e53945 JB |
13918 | entry++; |
13919 | } | |
4ef69c7a | 13920 | |
79e53945 JB |
13921 | return index_mask; |
13922 | } | |
13923 | ||
646d5772 | 13924 | static bool has_edp_a(struct drm_i915_private *dev_priv) |
4d302442 | 13925 | { |
646d5772 | 13926 | if (!IS_MOBILE(dev_priv)) |
4d302442 CW |
13927 | return false; |
13928 | ||
13929 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
13930 | return false; | |
13931 | ||
5db94019 | 13932 | if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
13933 | return false; |
13934 | ||
13935 | return true; | |
13936 | } | |
13937 | ||
6315b5d3 | 13938 | static bool intel_crt_present(struct drm_i915_private *dev_priv) |
84b4e042 | 13939 | { |
6315b5d3 | 13940 | if (INTEL_GEN(dev_priv) >= 9) |
884497ed DL |
13941 | return false; |
13942 | ||
50a0bc90 | 13943 | if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) |
84b4e042 JB |
13944 | return false; |
13945 | ||
920a14b2 | 13946 | if (IS_CHERRYVIEW(dev_priv)) |
84b4e042 JB |
13947 | return false; |
13948 | ||
4f8036a2 TU |
13949 | if (HAS_PCH_LPT_H(dev_priv) && |
13950 | I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) | |
65e472e4 VS |
13951 | return false; |
13952 | ||
70ac54d0 | 13953 | /* DDI E can't be used if DDI A requires 4 lanes */ |
4f8036a2 | 13954 | if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) |
70ac54d0 VS |
13955 | return false; |
13956 | ||
e4abb733 | 13957 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
13958 | return false; |
13959 | ||
13960 | return true; | |
13961 | } | |
13962 | ||
8090ba8c ID |
13963 | void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv) |
13964 | { | |
13965 | int pps_num; | |
13966 | int pps_idx; | |
13967 | ||
13968 | if (HAS_DDI(dev_priv)) | |
13969 | return; | |
13970 | /* | |
13971 | * This w/a is needed at least on CPT/PPT, but to be sure apply it | |
13972 | * everywhere where registers can be write protected. | |
13973 | */ | |
13974 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
13975 | pps_num = 2; | |
13976 | else | |
13977 | pps_num = 1; | |
13978 | ||
13979 | for (pps_idx = 0; pps_idx < pps_num; pps_idx++) { | |
13980 | u32 val = I915_READ(PP_CONTROL(pps_idx)); | |
13981 | ||
13982 | val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS; | |
13983 | I915_WRITE(PP_CONTROL(pps_idx), val); | |
13984 | } | |
13985 | } | |
13986 | ||
44cb734c ID |
13987 | static void intel_pps_init(struct drm_i915_private *dev_priv) |
13988 | { | |
cc3f90f0 | 13989 | if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv)) |
44cb734c ID |
13990 | dev_priv->pps_mmio_base = PCH_PPS_BASE; |
13991 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
13992 | dev_priv->pps_mmio_base = VLV_PPS_BASE; | |
13993 | else | |
13994 | dev_priv->pps_mmio_base = PPS_BASE; | |
8090ba8c ID |
13995 | |
13996 | intel_pps_unlock_regs_wa(dev_priv); | |
44cb734c ID |
13997 | } |
13998 | ||
c39055b0 | 13999 | static void intel_setup_outputs(struct drm_i915_private *dev_priv) |
79e53945 | 14000 | { |
4ef69c7a | 14001 | struct intel_encoder *encoder; |
cb0953d7 | 14002 | bool dpd_is_edp = false; |
79e53945 | 14003 | |
44cb734c ID |
14004 | intel_pps_init(dev_priv); |
14005 | ||
97a824e1 ID |
14006 | /* |
14007 | * intel_edp_init_connector() depends on this completing first, to | |
14008 | * prevent the registeration of both eDP and LVDS and the incorrect | |
14009 | * sharing of the PPS. | |
14010 | */ | |
c39055b0 | 14011 | intel_lvds_init(dev_priv); |
79e53945 | 14012 | |
6315b5d3 | 14013 | if (intel_crt_present(dev_priv)) |
c39055b0 | 14014 | intel_crt_init(dev_priv); |
cb0953d7 | 14015 | |
cc3f90f0 | 14016 | if (IS_GEN9_LP(dev_priv)) { |
c776eb2e VK |
14017 | /* |
14018 | * FIXME: Broxton doesn't support port detection via the | |
14019 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14020 | * detect the ports. | |
14021 | */ | |
c39055b0 ACO |
14022 | intel_ddi_init(dev_priv, PORT_A); |
14023 | intel_ddi_init(dev_priv, PORT_B); | |
14024 | intel_ddi_init(dev_priv, PORT_C); | |
c6c794a2 | 14025 | |
c39055b0 | 14026 | intel_dsi_init(dev_priv); |
4f8036a2 | 14027 | } else if (HAS_DDI(dev_priv)) { |
0e72a5b5 ED |
14028 | int found; |
14029 | ||
de31facd JB |
14030 | /* |
14031 | * Haswell uses DDI functions to detect digital outputs. | |
14032 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14033 | * it's there. | |
14034 | */ | |
77179400 | 14035 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 14036 | /* WaIgnoreDDIAStrap: skl */ |
b976dc53 | 14037 | if (found || IS_GEN9_BC(dev_priv)) |
c39055b0 | 14038 | intel_ddi_init(dev_priv, PORT_A); |
0e72a5b5 ED |
14039 | |
14040 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14041 | * register */ | |
14042 | found = I915_READ(SFUSE_STRAP); | |
14043 | ||
14044 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
c39055b0 | 14045 | intel_ddi_init(dev_priv, PORT_B); |
0e72a5b5 | 14046 | if (found & SFUSE_STRAP_DDIC_DETECTED) |
c39055b0 | 14047 | intel_ddi_init(dev_priv, PORT_C); |
0e72a5b5 | 14048 | if (found & SFUSE_STRAP_DDID_DETECTED) |
c39055b0 | 14049 | intel_ddi_init(dev_priv, PORT_D); |
2800e4c2 RV |
14050 | /* |
14051 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
14052 | */ | |
b976dc53 | 14053 | if (IS_GEN9_BC(dev_priv) && |
2800e4c2 RV |
14054 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
14055 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
14056 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
c39055b0 | 14057 | intel_ddi_init(dev_priv, PORT_E); |
2800e4c2 | 14058 | |
6e266956 | 14059 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
cb0953d7 | 14060 | int found; |
dd11bc10 | 14061 | dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D); |
270b3042 | 14062 | |
646d5772 | 14063 | if (has_edp_a(dev_priv)) |
c39055b0 | 14064 | intel_dp_init(dev_priv, DP_A, PORT_A); |
cb0953d7 | 14065 | |
dc0fa718 | 14066 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14067 | /* PCH SDVOB multiplex with HDMIB */ |
c39055b0 | 14068 | found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); |
30ad48b7 | 14069 | if (!found) |
c39055b0 | 14070 | intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); |
5eb08b69 | 14071 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
c39055b0 | 14072 | intel_dp_init(dev_priv, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14073 | } |
14074 | ||
dc0fa718 | 14075 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
c39055b0 | 14076 | intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); |
30ad48b7 | 14077 | |
dc0fa718 | 14078 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
c39055b0 | 14079 | intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D); |
30ad48b7 | 14080 | |
5eb08b69 | 14081 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
c39055b0 | 14082 | intel_dp_init(dev_priv, PCH_DP_C, PORT_C); |
5eb08b69 | 14083 | |
270b3042 | 14084 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
c39055b0 | 14085 | intel_dp_init(dev_priv, PCH_DP_D, PORT_D); |
920a14b2 | 14086 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
22f35042 | 14087 | bool has_edp, has_port; |
457c52d8 | 14088 | |
e17ac6db VS |
14089 | /* |
14090 | * The DP_DETECTED bit is the latched state of the DDC | |
14091 | * SDA pin at boot. However since eDP doesn't require DDC | |
14092 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14093 | * eDP ports may have been muxed to an alternate function. | |
14094 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14095 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14096 | * detect eDP ports. | |
22f35042 VS |
14097 | * |
14098 | * Sadly the straps seem to be missing sometimes even for HDMI | |
14099 | * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap | |
14100 | * and VBT for the presence of the port. Additionally we can't | |
14101 | * trust the port type the VBT declares as we've seen at least | |
14102 | * HDMI ports that the VBT claim are DP or eDP. | |
e17ac6db | 14103 | */ |
dd11bc10 | 14104 | has_edp = intel_dp_is_edp(dev_priv, PORT_B); |
22f35042 VS |
14105 | has_port = intel_bios_is_port_present(dev_priv, PORT_B); |
14106 | if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port) | |
c39055b0 | 14107 | has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B); |
22f35042 | 14108 | if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) |
c39055b0 | 14109 | intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); |
585a94b8 | 14110 | |
dd11bc10 | 14111 | has_edp = intel_dp_is_edp(dev_priv, PORT_C); |
22f35042 VS |
14112 | has_port = intel_bios_is_port_present(dev_priv, PORT_C); |
14113 | if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port) | |
c39055b0 | 14114 | has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C); |
22f35042 | 14115 | if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) |
c39055b0 | 14116 | intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); |
19c03924 | 14117 | |
920a14b2 | 14118 | if (IS_CHERRYVIEW(dev_priv)) { |
22f35042 VS |
14119 | /* |
14120 | * eDP not supported on port D, | |
14121 | * so no need to worry about it | |
14122 | */ | |
14123 | has_port = intel_bios_is_port_present(dev_priv, PORT_D); | |
14124 | if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port) | |
c39055b0 | 14125 | intel_dp_init(dev_priv, CHV_DP_D, PORT_D); |
22f35042 | 14126 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port) |
c39055b0 | 14127 | intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D); |
9418c1f1 VS |
14128 | } |
14129 | ||
c39055b0 | 14130 | intel_dsi_init(dev_priv); |
5db94019 | 14131 | } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) { |
27185ae1 | 14132 | bool found = false; |
7d57382e | 14133 | |
e2debe91 | 14134 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14135 | DRM_DEBUG_KMS("probing SDVOB\n"); |
c39055b0 | 14136 | found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); |
9beb5fea | 14137 | if (!found && IS_G4X(dev_priv)) { |
b01f2c3a | 14138 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
c39055b0 | 14139 | intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14140 | } |
27185ae1 | 14141 | |
9beb5fea | 14142 | if (!found && IS_G4X(dev_priv)) |
c39055b0 | 14143 | intel_dp_init(dev_priv, DP_B, PORT_B); |
725e30ad | 14144 | } |
13520b05 KH |
14145 | |
14146 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14147 | |
e2debe91 | 14148 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14149 | DRM_DEBUG_KMS("probing SDVOC\n"); |
c39055b0 | 14150 | found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); |
b01f2c3a | 14151 | } |
27185ae1 | 14152 | |
e2debe91 | 14153 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14154 | |
9beb5fea | 14155 | if (IS_G4X(dev_priv)) { |
b01f2c3a | 14156 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
c39055b0 | 14157 | intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14158 | } |
9beb5fea | 14159 | if (IS_G4X(dev_priv)) |
c39055b0 | 14160 | intel_dp_init(dev_priv, DP_C, PORT_C); |
725e30ad | 14161 | } |
27185ae1 | 14162 | |
9beb5fea | 14163 | if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED)) |
c39055b0 | 14164 | intel_dp_init(dev_priv, DP_D, PORT_D); |
5db94019 | 14165 | } else if (IS_GEN2(dev_priv)) |
c39055b0 | 14166 | intel_dvo_init(dev_priv); |
79e53945 | 14167 | |
56b857a5 | 14168 | if (SUPPORTS_TV(dev_priv)) |
c39055b0 | 14169 | intel_tv_init(dev_priv); |
79e53945 | 14170 | |
c39055b0 | 14171 | intel_psr_init(dev_priv); |
7c8f8a70 | 14172 | |
c39055b0 | 14173 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
4ef69c7a CW |
14174 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14175 | encoder->base.possible_clones = | |
66a9278e | 14176 | intel_encoder_clones(encoder); |
79e53945 | 14177 | } |
47356eb6 | 14178 | |
c39055b0 | 14179 | intel_init_pch_refclk(dev_priv); |
270b3042 | 14180 | |
c39055b0 | 14181 | drm_helper_move_panel_connectors_to_head(&dev_priv->drm); |
79e53945 JB |
14182 | } |
14183 | ||
14184 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14185 | { | |
14186 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 | 14187 | |
ef2d633e | 14188 | drm_framebuffer_cleanup(fb); |
70001cd2 | 14189 | |
dd689287 CW |
14190 | i915_gem_object_lock(intel_fb->obj); |
14191 | WARN_ON(!intel_fb->obj->framebuffer_references--); | |
14192 | i915_gem_object_unlock(intel_fb->obj); | |
14193 | ||
f8c417cd | 14194 | i915_gem_object_put(intel_fb->obj); |
70001cd2 | 14195 | |
79e53945 JB |
14196 | kfree(intel_fb); |
14197 | } | |
14198 | ||
14199 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14200 | struct drm_file *file, |
79e53945 JB |
14201 | unsigned int *handle) |
14202 | { | |
14203 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14204 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14205 | |
cc917ab4 CW |
14206 | if (obj->userptr.mm) { |
14207 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
14208 | return -EINVAL; | |
14209 | } | |
14210 | ||
05394f39 | 14211 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14212 | } |
14213 | ||
86c98588 RV |
14214 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
14215 | struct drm_file *file, | |
14216 | unsigned flags, unsigned color, | |
14217 | struct drm_clip_rect *clips, | |
14218 | unsigned num_clips) | |
14219 | { | |
5a97bcc6 | 14220 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
86c98588 | 14221 | |
5a97bcc6 | 14222 | i915_gem_object_flush_if_display(obj); |
d59b21ec | 14223 | intel_fb_obj_flush(obj, ORIGIN_DIRTYFB); |
86c98588 RV |
14224 | |
14225 | return 0; | |
14226 | } | |
14227 | ||
79e53945 JB |
14228 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
14229 | .destroy = intel_user_framebuffer_destroy, | |
14230 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 14231 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
14232 | }; |
14233 | ||
b321803d | 14234 | static |
920a14b2 TU |
14235 | u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv, |
14236 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 14237 | { |
24dbf51a | 14238 | u32 gen = INTEL_GEN(dev_priv); |
b321803d DL |
14239 | |
14240 | if (gen >= 9) { | |
ac484963 VS |
14241 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
14242 | ||
b321803d DL |
14243 | /* "The stride in bytes must not exceed the of the size of 8K |
14244 | * pixels and 32K bytes." | |
14245 | */ | |
ac484963 | 14246 | return min(8192 * cpp, 32768); |
6401c37d | 14247 | } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) { |
b321803d DL |
14248 | return 32*1024; |
14249 | } else if (gen >= 4) { | |
14250 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14251 | return 16*1024; | |
14252 | else | |
14253 | return 32*1024; | |
14254 | } else if (gen >= 3) { | |
14255 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14256 | return 8*1024; | |
14257 | else | |
14258 | return 16*1024; | |
14259 | } else { | |
14260 | /* XXX DSPC is limited to 4k tiled */ | |
14261 | return 8*1024; | |
14262 | } | |
14263 | } | |
14264 | ||
24dbf51a CW |
14265 | static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, |
14266 | struct drm_i915_gem_object *obj, | |
14267 | struct drm_mode_fb_cmd2 *mode_cmd) | |
79e53945 | 14268 | { |
24dbf51a | 14269 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
b3c11ac2 | 14270 | struct drm_format_name_buf format_name; |
dd689287 CW |
14271 | u32 pitch_limit, stride_alignment; |
14272 | unsigned int tiling, stride; | |
24dbf51a | 14273 | int ret = -EINVAL; |
79e53945 | 14274 | |
dd689287 CW |
14275 | i915_gem_object_lock(obj); |
14276 | obj->framebuffer_references++; | |
14277 | tiling = i915_gem_object_get_tiling(obj); | |
14278 | stride = i915_gem_object_get_stride(obj); | |
14279 | i915_gem_object_unlock(obj); | |
dd4916c5 | 14280 | |
2a80eada | 14281 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
c2ff7370 VS |
14282 | /* |
14283 | * If there's a fence, enforce that | |
14284 | * the fb modifier and tiling mode match. | |
14285 | */ | |
14286 | if (tiling != I915_TILING_NONE && | |
14287 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
2a80eada | 14288 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); |
24dbf51a | 14289 | goto err; |
2a80eada DV |
14290 | } |
14291 | } else { | |
c2ff7370 | 14292 | if (tiling == I915_TILING_X) { |
2a80eada | 14293 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; |
c2ff7370 | 14294 | } else if (tiling == I915_TILING_Y) { |
2a80eada | 14295 | DRM_DEBUG("No Y tiling for legacy addfb\n"); |
24dbf51a | 14296 | goto err; |
2a80eada DV |
14297 | } |
14298 | } | |
14299 | ||
9a8f0a12 TU |
14300 | /* Passed in modifier sanity checking. */ |
14301 | switch (mode_cmd->modifier[0]) { | |
14302 | case I915_FORMAT_MOD_Y_TILED: | |
14303 | case I915_FORMAT_MOD_Yf_TILED: | |
6315b5d3 | 14304 | if (INTEL_GEN(dev_priv) < 9) { |
9a8f0a12 TU |
14305 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", |
14306 | mode_cmd->modifier[0]); | |
24dbf51a | 14307 | goto err; |
9a8f0a12 TU |
14308 | } |
14309 | case DRM_FORMAT_MOD_NONE: | |
14310 | case I915_FORMAT_MOD_X_TILED: | |
14311 | break; | |
14312 | default: | |
c0f40428 JB |
14313 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14314 | mode_cmd->modifier[0]); | |
24dbf51a | 14315 | goto err; |
c16ed4be | 14316 | } |
57cd6508 | 14317 | |
c2ff7370 VS |
14318 | /* |
14319 | * gen2/3 display engine uses the fence if present, | |
14320 | * so the tiling mode must match the fb modifier exactly. | |
14321 | */ | |
14322 | if (INTEL_INFO(dev_priv)->gen < 4 && | |
14323 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
14324 | DRM_DEBUG("tiling_mode must match fb modifier exactly on gen2/3\n"); | |
9aceb5c1 | 14325 | goto err; |
c2ff7370 VS |
14326 | } |
14327 | ||
7b49f948 VS |
14328 | stride_alignment = intel_fb_stride_alignment(dev_priv, |
14329 | mode_cmd->modifier[0], | |
b321803d DL |
14330 | mode_cmd->pixel_format); |
14331 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
14332 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
14333 | mode_cmd->pitches[0], stride_alignment); | |
24dbf51a | 14334 | goto err; |
c16ed4be | 14335 | } |
57cd6508 | 14336 | |
920a14b2 | 14337 | pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0], |
b321803d | 14338 | mode_cmd->pixel_format); |
a35cdaa0 | 14339 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
14340 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
14341 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 14342 | "tiled" : "linear", |
a35cdaa0 | 14343 | mode_cmd->pitches[0], pitch_limit); |
24dbf51a | 14344 | goto err; |
c16ed4be | 14345 | } |
5d7bd705 | 14346 | |
c2ff7370 VS |
14347 | /* |
14348 | * If there's a fence, enforce that | |
14349 | * the fb pitch and fence stride match. | |
14350 | */ | |
dd689287 | 14351 | if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) { |
c16ed4be | 14352 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", |
dd689287 | 14353 | mode_cmd->pitches[0], stride); |
24dbf51a | 14354 | goto err; |
c16ed4be | 14355 | } |
5d7bd705 | 14356 | |
57779d06 | 14357 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14358 | switch (mode_cmd->pixel_format) { |
57779d06 | 14359 | case DRM_FORMAT_C8: |
04b3924d VS |
14360 | case DRM_FORMAT_RGB565: |
14361 | case DRM_FORMAT_XRGB8888: | |
14362 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14363 | break; |
14364 | case DRM_FORMAT_XRGB1555: | |
6315b5d3 | 14365 | if (INTEL_GEN(dev_priv) > 3) { |
b3c11ac2 EE |
14366 | DRM_DEBUG("unsupported pixel format: %s\n", |
14367 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14368 | goto err; |
c16ed4be | 14369 | } |
57779d06 | 14370 | break; |
57779d06 | 14371 | case DRM_FORMAT_ABGR8888: |
920a14b2 | 14372 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
6315b5d3 | 14373 | INTEL_GEN(dev_priv) < 9) { |
b3c11ac2 EE |
14374 | DRM_DEBUG("unsupported pixel format: %s\n", |
14375 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14376 | goto err; |
6c0fd451 DL |
14377 | } |
14378 | break; | |
14379 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 14380 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 14381 | case DRM_FORMAT_XBGR2101010: |
6315b5d3 | 14382 | if (INTEL_GEN(dev_priv) < 4) { |
b3c11ac2 EE |
14383 | DRM_DEBUG("unsupported pixel format: %s\n", |
14384 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14385 | goto err; |
c16ed4be | 14386 | } |
b5626747 | 14387 | break; |
7531208b | 14388 | case DRM_FORMAT_ABGR2101010: |
920a14b2 | 14389 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
b3c11ac2 EE |
14390 | DRM_DEBUG("unsupported pixel format: %s\n", |
14391 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14392 | goto err; |
7531208b DL |
14393 | } |
14394 | break; | |
04b3924d VS |
14395 | case DRM_FORMAT_YUYV: |
14396 | case DRM_FORMAT_UYVY: | |
14397 | case DRM_FORMAT_YVYU: | |
14398 | case DRM_FORMAT_VYUY: | |
6315b5d3 | 14399 | if (INTEL_GEN(dev_priv) < 5) { |
b3c11ac2 EE |
14400 | DRM_DEBUG("unsupported pixel format: %s\n", |
14401 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14402 | goto err; |
c16ed4be | 14403 | } |
57cd6508 CW |
14404 | break; |
14405 | default: | |
b3c11ac2 EE |
14406 | DRM_DEBUG("unsupported pixel format: %s\n", |
14407 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14408 | goto err; |
57cd6508 CW |
14409 | } |
14410 | ||
90f9a336 VS |
14411 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14412 | if (mode_cmd->offsets[0] != 0) | |
24dbf51a | 14413 | goto err; |
90f9a336 | 14414 | |
24dbf51a CW |
14415 | drm_helper_mode_fill_fb_struct(&dev_priv->drm, |
14416 | &intel_fb->base, mode_cmd); | |
c7d73f6a DV |
14417 | intel_fb->obj = obj; |
14418 | ||
6687c906 VS |
14419 | ret = intel_fill_fb_info(dev_priv, &intel_fb->base); |
14420 | if (ret) | |
9aceb5c1 | 14421 | goto err; |
2d7a215f | 14422 | |
24dbf51a CW |
14423 | ret = drm_framebuffer_init(obj->base.dev, |
14424 | &intel_fb->base, | |
14425 | &intel_fb_funcs); | |
79e53945 JB |
14426 | if (ret) { |
14427 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
24dbf51a | 14428 | goto err; |
79e53945 JB |
14429 | } |
14430 | ||
79e53945 | 14431 | return 0; |
24dbf51a CW |
14432 | |
14433 | err: | |
dd689287 CW |
14434 | i915_gem_object_lock(obj); |
14435 | obj->framebuffer_references--; | |
14436 | i915_gem_object_unlock(obj); | |
24dbf51a | 14437 | return ret; |
79e53945 JB |
14438 | } |
14439 | ||
79e53945 JB |
14440 | static struct drm_framebuffer * |
14441 | intel_user_framebuffer_create(struct drm_device *dev, | |
14442 | struct drm_file *filp, | |
1eb83451 | 14443 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 14444 | { |
dcb1394e | 14445 | struct drm_framebuffer *fb; |
05394f39 | 14446 | struct drm_i915_gem_object *obj; |
76dc3769 | 14447 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 14448 | |
03ac0642 CW |
14449 | obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]); |
14450 | if (!obj) | |
cce13ff7 | 14451 | return ERR_PTR(-ENOENT); |
79e53945 | 14452 | |
24dbf51a | 14453 | fb = intel_framebuffer_create(obj, &mode_cmd); |
dcb1394e | 14454 | if (IS_ERR(fb)) |
f0cd5182 | 14455 | i915_gem_object_put(obj); |
dcb1394e LW |
14456 | |
14457 | return fb; | |
79e53945 JB |
14458 | } |
14459 | ||
778e23a9 CW |
14460 | static void intel_atomic_state_free(struct drm_atomic_state *state) |
14461 | { | |
14462 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
14463 | ||
14464 | drm_atomic_state_default_release(state); | |
14465 | ||
14466 | i915_sw_fence_fini(&intel_state->commit_ready); | |
14467 | ||
14468 | kfree(state); | |
14469 | } | |
14470 | ||
79e53945 | 14471 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14472 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14473 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14474 | .atomic_check = intel_atomic_check, |
14475 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
14476 | .atomic_state_alloc = intel_atomic_state_alloc, |
14477 | .atomic_state_clear = intel_atomic_state_clear, | |
778e23a9 | 14478 | .atomic_state_free = intel_atomic_state_free, |
79e53945 JB |
14479 | }; |
14480 | ||
88212941 ID |
14481 | /** |
14482 | * intel_init_display_hooks - initialize the display modesetting hooks | |
14483 | * @dev_priv: device private | |
14484 | */ | |
14485 | void intel_init_display_hooks(struct drm_i915_private *dev_priv) | |
e70236a8 | 14486 | { |
7ff89ca2 VS |
14487 | intel_init_cdclk_hooks(dev_priv); |
14488 | ||
88212941 | 14489 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
bc8d7dff | 14490 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14491 | dev_priv->display.get_initial_plane_config = |
14492 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14493 | dev_priv->display.crtc_compute_clock = |
14494 | haswell_crtc_compute_clock; | |
14495 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14496 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 14497 | } else if (HAS_DDI(dev_priv)) { |
0e8ffe1b | 14498 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14499 | dev_priv->display.get_initial_plane_config = |
14500 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14501 | dev_priv->display.crtc_compute_clock = |
14502 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14503 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14504 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 14505 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
0e8ffe1b | 14506 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14507 | dev_priv->display.get_initial_plane_config = |
14508 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14509 | dev_priv->display.crtc_compute_clock = |
14510 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14511 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14512 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
65b3d6a9 | 14513 | } else if (IS_CHERRYVIEW(dev_priv)) { |
89b667f8 | 14514 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14515 | dev_priv->display.get_initial_plane_config = |
14516 | i9xx_get_initial_plane_config; | |
65b3d6a9 ACO |
14517 | dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; |
14518 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
14519 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
14520 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
14521 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14522 | dev_priv->display.get_initial_plane_config = | |
14523 | i9xx_get_initial_plane_config; | |
14524 | dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; | |
89b667f8 JB |
14525 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14526 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
19ec6693 ACO |
14527 | } else if (IS_G4X(dev_priv)) { |
14528 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14529 | dev_priv->display.get_initial_plane_config = | |
14530 | i9xx_get_initial_plane_config; | |
14531 | dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; | |
14532 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14533 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
70e8aa21 ACO |
14534 | } else if (IS_PINEVIEW(dev_priv)) { |
14535 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14536 | dev_priv->display.get_initial_plane_config = | |
14537 | i9xx_get_initial_plane_config; | |
14538 | dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; | |
14539 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14540 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 | 14541 | } else if (!IS_GEN2(dev_priv)) { |
0e8ffe1b | 14542 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14543 | dev_priv->display.get_initial_plane_config = |
14544 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14545 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14546 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14547 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 ACO |
14548 | } else { |
14549 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14550 | dev_priv->display.get_initial_plane_config = | |
14551 | i9xx_get_initial_plane_config; | |
14552 | dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; | |
14553 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14554 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 14555 | } |
e70236a8 | 14556 | |
88212941 | 14557 | if (IS_GEN5(dev_priv)) { |
3bb11b53 | 14558 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
88212941 | 14559 | } else if (IS_GEN6(dev_priv)) { |
3bb11b53 | 14560 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
88212941 | 14561 | } else if (IS_IVYBRIDGE(dev_priv)) { |
3bb11b53 SJ |
14562 | /* FIXME: detect B0+ stepping and use auto training */ |
14563 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
88212941 | 14564 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3bb11b53 | 14565 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
445e780b VS |
14566 | } |
14567 | ||
27082493 L |
14568 | if (dev_priv->info.gen >= 9) |
14569 | dev_priv->display.update_crtcs = skl_update_crtcs; | |
14570 | else | |
14571 | dev_priv->display.update_crtcs = intel_update_crtcs; | |
14572 | ||
5a21b665 DV |
14573 | switch (INTEL_INFO(dev_priv)->gen) { |
14574 | case 2: | |
14575 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
14576 | break; | |
14577 | ||
14578 | case 3: | |
14579 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
14580 | break; | |
14581 | ||
14582 | case 4: | |
14583 | case 5: | |
14584 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
14585 | break; | |
14586 | ||
14587 | case 6: | |
14588 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
14589 | break; | |
14590 | case 7: | |
14591 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ | |
14592 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
14593 | break; | |
14594 | case 9: | |
14595 | /* Drop through - unsupported since execlist only. */ | |
14596 | default: | |
14597 | /* Default just returns -ENODEV to indicate unsupported */ | |
14598 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
14599 | } | |
e70236a8 JB |
14600 | } |
14601 | ||
b690e96c JB |
14602 | /* |
14603 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
14604 | * resume, or other times. This quirk makes sure that's the case for | |
14605 | * affected systems. | |
14606 | */ | |
0206e353 | 14607 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c | 14608 | { |
fac5e23e | 14609 | struct drm_i915_private *dev_priv = to_i915(dev); |
b690e96c JB |
14610 | |
14611 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 14612 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
14613 | } |
14614 | ||
b6b5d049 VS |
14615 | static void quirk_pipeb_force(struct drm_device *dev) |
14616 | { | |
fac5e23e | 14617 | struct drm_i915_private *dev_priv = to_i915(dev); |
b6b5d049 VS |
14618 | |
14619 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
14620 | DRM_INFO("applying pipe b force quirk\n"); | |
14621 | } | |
14622 | ||
435793df KP |
14623 | /* |
14624 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
14625 | */ | |
14626 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
14627 | { | |
fac5e23e | 14628 | struct drm_i915_private *dev_priv = to_i915(dev); |
435793df | 14629 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
bc0daf48 | 14630 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
14631 | } |
14632 | ||
4dca20ef | 14633 | /* |
5a15ab5b CE |
14634 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
14635 | * brightness value | |
4dca20ef CE |
14636 | */ |
14637 | static void quirk_invert_brightness(struct drm_device *dev) | |
14638 | { | |
fac5e23e | 14639 | struct drm_i915_private *dev_priv = to_i915(dev); |
4dca20ef | 14640 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
bc0daf48 | 14641 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
14642 | } |
14643 | ||
9c72cc6f SD |
14644 | /* Some VBT's incorrectly indicate no backlight is present */ |
14645 | static void quirk_backlight_present(struct drm_device *dev) | |
14646 | { | |
fac5e23e | 14647 | struct drm_i915_private *dev_priv = to_i915(dev); |
9c72cc6f SD |
14648 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; |
14649 | DRM_INFO("applying backlight present quirk\n"); | |
14650 | } | |
14651 | ||
b690e96c JB |
14652 | struct intel_quirk { |
14653 | int device; | |
14654 | int subsystem_vendor; | |
14655 | int subsystem_device; | |
14656 | void (*hook)(struct drm_device *dev); | |
14657 | }; | |
14658 | ||
5f85f176 EE |
14659 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
14660 | struct intel_dmi_quirk { | |
14661 | void (*hook)(struct drm_device *dev); | |
14662 | const struct dmi_system_id (*dmi_id_list)[]; | |
14663 | }; | |
14664 | ||
14665 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
14666 | { | |
14667 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
14668 | return 1; | |
14669 | } | |
14670 | ||
14671 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
14672 | { | |
14673 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
14674 | { | |
14675 | .callback = intel_dmi_reverse_brightness, | |
14676 | .ident = "NCR Corporation", | |
14677 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
14678 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
14679 | }, | |
14680 | }, | |
14681 | { } /* terminating entry */ | |
14682 | }, | |
14683 | .hook = quirk_invert_brightness, | |
14684 | }, | |
14685 | }; | |
14686 | ||
c43b5634 | 14687 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
14688 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
14689 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
14690 | ||
b690e96c JB |
14691 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
14692 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
14693 | ||
5f080c0f VS |
14694 | /* 830 needs to leave pipe A & dpll A up */ |
14695 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
14696 | ||
b6b5d049 VS |
14697 | /* 830 needs to leave pipe B & dpll B up */ |
14698 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
14699 | ||
435793df KP |
14700 | /* Lenovo U160 cannot use SSC on LVDS */ |
14701 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
14702 | |
14703 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
14704 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 14705 | |
be505f64 AH |
14706 | /* Acer Aspire 5734Z must invert backlight brightness */ |
14707 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
14708 | ||
14709 | /* Acer/eMachines G725 */ | |
14710 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
14711 | ||
14712 | /* Acer/eMachines e725 */ | |
14713 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
14714 | ||
14715 | /* Acer/Packard Bell NCL20 */ | |
14716 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
14717 | ||
14718 | /* Acer Aspire 4736Z */ | |
14719 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
14720 | |
14721 | /* Acer Aspire 5336 */ | |
14722 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
14723 | |
14724 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
14725 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 14726 | |
dfb3d47b SD |
14727 | /* Acer C720 Chromebook (Core i3 4005U) */ |
14728 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
14729 | ||
b2a9601c | 14730 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
14731 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
14732 | ||
1b9448b0 JN |
14733 | /* Apple Macbook 4,1 */ |
14734 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
14735 | ||
d4967d8c SD |
14736 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
14737 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
14738 | |
14739 | /* HP Chromebook 14 (Celeron 2955U) */ | |
14740 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
14741 | |
14742 | /* Dell Chromebook 11 */ | |
14743 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
14744 | |
14745 | /* Dell Chromebook 11 (2015 version) */ | |
14746 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
14747 | }; |
14748 | ||
14749 | static void intel_init_quirks(struct drm_device *dev) | |
14750 | { | |
14751 | struct pci_dev *d = dev->pdev; | |
14752 | int i; | |
14753 | ||
14754 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
14755 | struct intel_quirk *q = &intel_quirks[i]; | |
14756 | ||
14757 | if (d->device == q->device && | |
14758 | (d->subsystem_vendor == q->subsystem_vendor || | |
14759 | q->subsystem_vendor == PCI_ANY_ID) && | |
14760 | (d->subsystem_device == q->subsystem_device || | |
14761 | q->subsystem_device == PCI_ANY_ID)) | |
14762 | q->hook(dev); | |
14763 | } | |
5f85f176 EE |
14764 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
14765 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
14766 | intel_dmi_quirks[i].hook(dev); | |
14767 | } | |
b690e96c JB |
14768 | } |
14769 | ||
9cce37f4 | 14770 | /* Disable the VGA plane that we never use */ |
29b74b7f | 14771 | static void i915_disable_vga(struct drm_i915_private *dev_priv) |
9cce37f4 | 14772 | { |
52a05c30 | 14773 | struct pci_dev *pdev = dev_priv->drm.pdev; |
9cce37f4 | 14774 | u8 sr1; |
920a14b2 | 14775 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); |
9cce37f4 | 14776 | |
2b37c616 | 14777 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
52a05c30 | 14778 | vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 14779 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
14780 | sr1 = inb(VGA_SR_DATA); |
14781 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
52a05c30 | 14782 | vga_put(pdev, VGA_RSRC_LEGACY_IO); |
9cce37f4 JB |
14783 | udelay(300); |
14784 | ||
01f5a626 | 14785 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
14786 | POSTING_READ(vga_reg); |
14787 | } | |
14788 | ||
f817586c DV |
14789 | void intel_modeset_init_hw(struct drm_device *dev) |
14790 | { | |
fac5e23e | 14791 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a617b77 | 14792 | |
4c75b940 | 14793 | intel_update_cdclk(dev_priv); |
bb0f4aab | 14794 | dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw; |
1a617b77 | 14795 | |
46f16e63 | 14796 | intel_init_clock_gating(dev_priv); |
f817586c DV |
14797 | } |
14798 | ||
d93c0372 MR |
14799 | /* |
14800 | * Calculate what we think the watermarks should be for the state we've read | |
14801 | * out of the hardware and then immediately program those watermarks so that | |
14802 | * we ensure the hardware settings match our internal state. | |
14803 | * | |
14804 | * We can calculate what we think WM's should be by creating a duplicate of the | |
14805 | * current state (which was constructed during hardware readout) and running it | |
14806 | * through the atomic check code to calculate new watermark values in the | |
14807 | * state object. | |
14808 | */ | |
14809 | static void sanitize_watermarks(struct drm_device *dev) | |
14810 | { | |
14811 | struct drm_i915_private *dev_priv = to_i915(dev); | |
14812 | struct drm_atomic_state *state; | |
ccf010fb | 14813 | struct intel_atomic_state *intel_state; |
d93c0372 MR |
14814 | struct drm_crtc *crtc; |
14815 | struct drm_crtc_state *cstate; | |
14816 | struct drm_modeset_acquire_ctx ctx; | |
14817 | int ret; | |
14818 | int i; | |
14819 | ||
14820 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 14821 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
14822 | return; |
14823 | ||
14824 | /* | |
14825 | * We need to hold connection_mutex before calling duplicate_state so | |
14826 | * that the connector loop is protected. | |
14827 | */ | |
14828 | drm_modeset_acquire_init(&ctx, 0); | |
14829 | retry: | |
0cd1262d | 14830 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
14831 | if (ret == -EDEADLK) { |
14832 | drm_modeset_backoff(&ctx); | |
14833 | goto retry; | |
14834 | } else if (WARN_ON(ret)) { | |
0cd1262d | 14835 | goto fail; |
d93c0372 MR |
14836 | } |
14837 | ||
14838 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
14839 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 14840 | goto fail; |
d93c0372 | 14841 | |
ccf010fb ML |
14842 | intel_state = to_intel_atomic_state(state); |
14843 | ||
ed4a6a7c MR |
14844 | /* |
14845 | * Hardware readout is the only time we don't want to calculate | |
14846 | * intermediate watermarks (since we don't trust the current | |
14847 | * watermarks). | |
14848 | */ | |
ccf010fb | 14849 | intel_state->skip_intermediate_wm = true; |
ed4a6a7c | 14850 | |
d93c0372 MR |
14851 | ret = intel_atomic_check(dev, state); |
14852 | if (ret) { | |
14853 | /* | |
14854 | * If we fail here, it means that the hardware appears to be | |
14855 | * programmed in a way that shouldn't be possible, given our | |
14856 | * understanding of watermark requirements. This might mean a | |
14857 | * mistake in the hardware readout code or a mistake in the | |
14858 | * watermark calculations for a given platform. Raise a WARN | |
14859 | * so that this is noticeable. | |
14860 | * | |
14861 | * If this actually happens, we'll have to just leave the | |
14862 | * BIOS-programmed watermarks untouched and hope for the best. | |
14863 | */ | |
14864 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
b9a1b717 | 14865 | goto put_state; |
d93c0372 MR |
14866 | } |
14867 | ||
14868 | /* Write calculated watermark values back */ | |
d93c0372 MR |
14869 | for_each_crtc_in_state(state, crtc, cstate, i) { |
14870 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); | |
14871 | ||
ed4a6a7c | 14872 | cs->wm.need_postvbl_update = true; |
ccf010fb | 14873 | dev_priv->display.optimize_watermarks(intel_state, cs); |
d93c0372 MR |
14874 | } |
14875 | ||
b9a1b717 | 14876 | put_state: |
0853695c | 14877 | drm_atomic_state_put(state); |
0cd1262d | 14878 | fail: |
d93c0372 MR |
14879 | drm_modeset_drop_locks(&ctx); |
14880 | drm_modeset_acquire_fini(&ctx); | |
14881 | } | |
14882 | ||
b079bd17 | 14883 | int intel_modeset_init(struct drm_device *dev) |
79e53945 | 14884 | { |
72e96d64 JL |
14885 | struct drm_i915_private *dev_priv = to_i915(dev); |
14886 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
8cc87b75 | 14887 | enum pipe pipe; |
46f297fb | 14888 | struct intel_crtc *crtc; |
79e53945 JB |
14889 | |
14890 | drm_mode_config_init(dev); | |
14891 | ||
14892 | dev->mode_config.min_width = 0; | |
14893 | dev->mode_config.min_height = 0; | |
14894 | ||
019d96cb DA |
14895 | dev->mode_config.preferred_depth = 24; |
14896 | dev->mode_config.prefer_shadow = 1; | |
14897 | ||
25bab385 TU |
14898 | dev->mode_config.allow_fb_modifiers = true; |
14899 | ||
e6ecefaa | 14900 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 14901 | |
eb955eee | 14902 | INIT_WORK(&dev_priv->atomic_helper.free_work, |
ba318c61 | 14903 | intel_atomic_helper_free_state_worker); |
eb955eee | 14904 | |
b690e96c JB |
14905 | intel_init_quirks(dev); |
14906 | ||
62d75df7 | 14907 | intel_init_pm(dev_priv); |
1fa61106 | 14908 | |
b7f05d4a | 14909 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
b079bd17 | 14910 | return 0; |
e3c74757 | 14911 | |
69f92f67 LW |
14912 | /* |
14913 | * There may be no VBT; and if the BIOS enabled SSC we can | |
14914 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
14915 | * BIOS isn't using it, don't assume it will work even if the VBT | |
14916 | * indicates as much. | |
14917 | */ | |
6e266956 | 14918 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { |
69f92f67 LW |
14919 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & |
14920 | DREF_SSC1_ENABLE); | |
14921 | ||
14922 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
14923 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
14924 | bios_lvds_use_ssc ? "en" : "dis", | |
14925 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
14926 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
14927 | } | |
14928 | } | |
14929 | ||
5db94019 | 14930 | if (IS_GEN2(dev_priv)) { |
a6c45cf0 CW |
14931 | dev->mode_config.max_width = 2048; |
14932 | dev->mode_config.max_height = 2048; | |
5db94019 | 14933 | } else if (IS_GEN3(dev_priv)) { |
5e4d6fa7 KP |
14934 | dev->mode_config.max_width = 4096; |
14935 | dev->mode_config.max_height = 4096; | |
79e53945 | 14936 | } else { |
a6c45cf0 CW |
14937 | dev->mode_config.max_width = 8192; |
14938 | dev->mode_config.max_height = 8192; | |
79e53945 | 14939 | } |
068be561 | 14940 | |
2a307c2e JN |
14941 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { |
14942 | dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512; | |
dc41c154 | 14943 | dev->mode_config.cursor_height = 1023; |
5db94019 | 14944 | } else if (IS_GEN2(dev_priv)) { |
068be561 DL |
14945 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
14946 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
14947 | } else { | |
14948 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
14949 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
14950 | } | |
14951 | ||
72e96d64 | 14952 | dev->mode_config.fb_base = ggtt->mappable_base; |
79e53945 | 14953 | |
28c97730 | 14954 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
b7f05d4a TU |
14955 | INTEL_INFO(dev_priv)->num_pipes, |
14956 | INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 14957 | |
055e393f | 14958 | for_each_pipe(dev_priv, pipe) { |
b079bd17 VS |
14959 | int ret; |
14960 | ||
5ab0d85b | 14961 | ret = intel_crtc_init(dev_priv, pipe); |
b079bd17 VS |
14962 | if (ret) { |
14963 | drm_mode_config_cleanup(dev); | |
14964 | return ret; | |
14965 | } | |
79e53945 JB |
14966 | } |
14967 | ||
e72f9fbf | 14968 | intel_shared_dpll_init(dev); |
ee7b9f93 | 14969 | |
5be6e334 VS |
14970 | intel_update_czclk(dev_priv); |
14971 | intel_modeset_init_hw(dev); | |
14972 | ||
b2045352 | 14973 | if (dev_priv->max_cdclk_freq == 0) |
4c75b940 | 14974 | intel_update_max_cdclk(dev_priv); |
b2045352 | 14975 | |
9cce37f4 | 14976 | /* Just disable it once at startup */ |
29b74b7f | 14977 | i915_disable_vga(dev_priv); |
c39055b0 | 14978 | intel_setup_outputs(dev_priv); |
11be49eb | 14979 | |
6e9f798d | 14980 | drm_modeset_lock_all(dev); |
043e9bda | 14981 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 14982 | drm_modeset_unlock_all(dev); |
46f297fb | 14983 | |
d3fcc808 | 14984 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
14985 | struct intel_initial_plane_config plane_config = {}; |
14986 | ||
46f297fb JB |
14987 | if (!crtc->active) |
14988 | continue; | |
14989 | ||
46f297fb | 14990 | /* |
46f297fb JB |
14991 | * Note that reserving the BIOS fb up front prevents us |
14992 | * from stuffing other stolen allocations like the ring | |
14993 | * on top. This prevents some ugliness at boot time, and | |
14994 | * can even allow for smooth boot transitions if the BIOS | |
14995 | * fb is large enough for the active pipe configuration. | |
14996 | */ | |
eeebeac5 ML |
14997 | dev_priv->display.get_initial_plane_config(crtc, |
14998 | &plane_config); | |
14999 | ||
15000 | /* | |
15001 | * If the fb is shared between multiple heads, we'll | |
15002 | * just get the first one. | |
15003 | */ | |
15004 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 15005 | } |
d93c0372 MR |
15006 | |
15007 | /* | |
15008 | * Make sure hardware watermarks really match the state we read out. | |
15009 | * Note that we need to do this after reconstructing the BIOS fb's | |
15010 | * since the watermark calculation done here will use pstate->fb. | |
15011 | */ | |
15012 | sanitize_watermarks(dev); | |
b079bd17 VS |
15013 | |
15014 | return 0; | |
2c7111db CW |
15015 | } |
15016 | ||
7fad798e DV |
15017 | static void intel_enable_pipe_a(struct drm_device *dev) |
15018 | { | |
15019 | struct intel_connector *connector; | |
15020 | struct drm_connector *crt = NULL; | |
15021 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 15022 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
15023 | |
15024 | /* We can't just switch on the pipe A, we need to set things up with a | |
15025 | * proper mode and output configuration. As a gross hack, enable pipe A | |
15026 | * by enabling the load detect pipe once. */ | |
3a3371ff | 15027 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
15028 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
15029 | crt = &connector->base; | |
15030 | break; | |
15031 | } | |
15032 | } | |
15033 | ||
15034 | if (!crt) | |
15035 | return; | |
15036 | ||
208bf9fd | 15037 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 15038 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
15039 | } |
15040 | ||
fa555837 DV |
15041 | static bool |
15042 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15043 | { | |
b7f05d4a | 15044 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
649636ef | 15045 | u32 val; |
fa555837 | 15046 | |
b7f05d4a | 15047 | if (INTEL_INFO(dev_priv)->num_pipes == 1) |
fa555837 DV |
15048 | return true; |
15049 | ||
649636ef | 15050 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
15051 | |
15052 | if ((val & DISPLAY_PLANE_ENABLE) && | |
15053 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
15054 | return false; | |
15055 | ||
15056 | return true; | |
15057 | } | |
15058 | ||
02e93c35 VS |
15059 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
15060 | { | |
15061 | struct drm_device *dev = crtc->base.dev; | |
15062 | struct intel_encoder *encoder; | |
15063 | ||
15064 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
15065 | return true; | |
15066 | ||
15067 | return false; | |
15068 | } | |
15069 | ||
496b0fc3 ML |
15070 | static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) |
15071 | { | |
15072 | struct drm_device *dev = encoder->base.dev; | |
15073 | struct intel_connector *connector; | |
15074 | ||
15075 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
15076 | return connector; | |
15077 | ||
15078 | return NULL; | |
15079 | } | |
15080 | ||
a168f5b3 VS |
15081 | static bool has_pch_trancoder(struct drm_i915_private *dev_priv, |
15082 | enum transcoder pch_transcoder) | |
15083 | { | |
15084 | return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || | |
15085 | (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A); | |
15086 | } | |
15087 | ||
24929352 DV |
15088 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15089 | { | |
15090 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 15091 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 | 15092 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
24929352 | 15093 | |
24929352 | 15094 | /* Clear any frame start delays used for debugging left by the BIOS */ |
4d1de975 JN |
15095 | if (!transcoder_is_dsi(cpu_transcoder)) { |
15096 | i915_reg_t reg = PIPECONF(cpu_transcoder); | |
15097 | ||
15098 | I915_WRITE(reg, | |
15099 | I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | |
15100 | } | |
24929352 | 15101 | |
d3eaf884 | 15102 | /* restore vblank interrupts to correct state */ |
9625604c | 15103 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 15104 | if (crtc->active) { |
f9cd7b88 VS |
15105 | struct intel_plane *plane; |
15106 | ||
9625604c | 15107 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
15108 | |
15109 | /* Disable everything but the primary plane */ | |
15110 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
15111 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
15112 | continue; | |
15113 | ||
15114 | plane->disable_plane(&plane->base, &crtc->base); | |
15115 | } | |
9625604c | 15116 | } |
d3eaf884 | 15117 | |
24929352 | 15118 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
15119 | * disable the crtc (and hence change the state) if it is wrong. Note |
15120 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
6315b5d3 | 15121 | if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) { |
24929352 DV |
15122 | bool plane; |
15123 | ||
78108b7c VS |
15124 | DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n", |
15125 | crtc->base.base.id, crtc->base.name); | |
24929352 DV |
15126 | |
15127 | /* Pipe has the wrong plane attached and the plane is active. | |
15128 | * Temporarily change the plane mapping and disable everything | |
15129 | * ... */ | |
15130 | plane = crtc->plane; | |
1d4258db | 15131 | crtc->base.primary->state->visible = true; |
24929352 | 15132 | crtc->plane = !plane; |
b17d48e2 | 15133 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15134 | crtc->plane = plane; |
24929352 | 15135 | } |
24929352 | 15136 | |
7fad798e DV |
15137 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
15138 | crtc->pipe == PIPE_A && !crtc->active) { | |
15139 | /* BIOS forgot to enable pipe A, this mostly happens after | |
15140 | * resume. Force-enable the pipe to fix this, the update_dpms | |
15141 | * call below we restore the pipe to the right state, but leave | |
15142 | * the required bits on. */ | |
15143 | intel_enable_pipe_a(dev); | |
15144 | } | |
15145 | ||
24929352 DV |
15146 | /* Adjust the state of the output pipe according to whether we |
15147 | * have active connectors/encoders. */ | |
842e0307 | 15148 | if (crtc->active && !intel_crtc_has_encoders(crtc)) |
b17d48e2 | 15149 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15150 | |
49cff963 | 15151 | if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) { |
4cc31489 DV |
15152 | /* |
15153 | * We start out with underrun reporting disabled to avoid races. | |
15154 | * For correct bookkeeping mark this on active crtcs. | |
15155 | * | |
c5ab3bc0 DV |
15156 | * Also on gmch platforms we dont have any hardware bits to |
15157 | * disable the underrun reporting. Which means we need to start | |
15158 | * out with underrun reporting disabled also on inactive pipes, | |
15159 | * since otherwise we'll complain about the garbage we read when | |
15160 | * e.g. coming up after runtime pm. | |
15161 | * | |
4cc31489 DV |
15162 | * No protection against concurrent access is required - at |
15163 | * worst a fifo underrun happens which also sets this to false. | |
15164 | */ | |
15165 | crtc->cpu_fifo_underrun_disabled = true; | |
a168f5b3 VS |
15166 | /* |
15167 | * We track the PCH trancoder underrun reporting state | |
15168 | * within the crtc. With crtc for pipe A housing the underrun | |
15169 | * reporting state for PCH transcoder A, crtc for pipe B housing | |
15170 | * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, | |
15171 | * and marking underrun reporting as disabled for the non-existing | |
15172 | * PCH transcoders B and C would prevent enabling the south | |
15173 | * error interrupt (see cpt_can_enable_serr_int()). | |
15174 | */ | |
15175 | if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe)) | |
15176 | crtc->pch_fifo_underrun_disabled = true; | |
4cc31489 | 15177 | } |
24929352 DV |
15178 | } |
15179 | ||
15180 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15181 | { | |
15182 | struct intel_connector *connector; | |
24929352 DV |
15183 | |
15184 | /* We need to check both for a crtc link (meaning that the | |
15185 | * encoder is active and trying to read from a pipe) and the | |
15186 | * pipe itself being active. */ | |
15187 | bool has_active_crtc = encoder->base.crtc && | |
15188 | to_intel_crtc(encoder->base.crtc)->active; | |
15189 | ||
496b0fc3 ML |
15190 | connector = intel_encoder_find_connector(encoder); |
15191 | if (connector && !has_active_crtc) { | |
24929352 DV |
15192 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
15193 | encoder->base.base.id, | |
8e329a03 | 15194 | encoder->base.name); |
24929352 DV |
15195 | |
15196 | /* Connector is active, but has no active pipe. This is | |
15197 | * fallout from our resume register restoring. Disable | |
15198 | * the encoder manually again. */ | |
15199 | if (encoder->base.crtc) { | |
fd6bbda9 ML |
15200 | struct drm_crtc_state *crtc_state = encoder->base.crtc->state; |
15201 | ||
24929352 DV |
15202 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", |
15203 | encoder->base.base.id, | |
8e329a03 | 15204 | encoder->base.name); |
fd6bbda9 | 15205 | encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); |
a62d1497 | 15206 | if (encoder->post_disable) |
fd6bbda9 | 15207 | encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); |
24929352 | 15208 | } |
7f1950fb | 15209 | encoder->base.crtc = NULL; |
24929352 DV |
15210 | |
15211 | /* Inconsistent output/port/pipe state happens presumably due to | |
15212 | * a bug in one of the get_hw_state functions. Or someplace else | |
15213 | * in our code, like the register restore mess on resume. Clamp | |
15214 | * things to off as a safer default. */ | |
fd6bbda9 ML |
15215 | |
15216 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15217 | connector->base.encoder = NULL; | |
24929352 DV |
15218 | } |
15219 | /* Enabled encoders without active connectors will be fixed in | |
15220 | * the crtc fixup. */ | |
15221 | } | |
15222 | ||
29b74b7f | 15223 | void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv) |
0fde901f | 15224 | { |
920a14b2 | 15225 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); |
0fde901f | 15226 | |
04098753 ID |
15227 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15228 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
29b74b7f | 15229 | i915_disable_vga(dev_priv); |
04098753 ID |
15230 | } |
15231 | } | |
15232 | ||
29b74b7f | 15233 | void i915_redisable_vga(struct drm_i915_private *dev_priv) |
04098753 | 15234 | { |
8dc8a27c PZ |
15235 | /* This function can be called both from intel_modeset_setup_hw_state or |
15236 | * at a very early point in our resume sequence, where the power well | |
15237 | * structures are not yet restored. Since this function is at a very | |
15238 | * paranoid "someone might have enabled VGA while we were not looking" | |
15239 | * level, just check if the power well is enabled instead of trying to | |
15240 | * follow the "don't touch the power well if we don't need it" policy | |
15241 | * the rest of the driver uses. */ | |
6392f847 | 15242 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15243 | return; |
15244 | ||
29b74b7f | 15245 | i915_redisable_vga_power_on(dev_priv); |
6392f847 ID |
15246 | |
15247 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
0fde901f KM |
15248 | } |
15249 | ||
f9cd7b88 | 15250 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 15251 | { |
f9cd7b88 | 15252 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 15253 | |
f9cd7b88 | 15254 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
15255 | } |
15256 | ||
f9cd7b88 VS |
15257 | /* FIXME read out full plane state for all planes */ |
15258 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 15259 | { |
b26d3ea3 | 15260 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 15261 | struct intel_plane_state *plane_state = |
b26d3ea3 | 15262 | to_intel_plane_state(primary->state); |
d032ffa0 | 15263 | |
936e71e3 | 15264 | plane_state->base.visible = crtc->active && |
b26d3ea3 ML |
15265 | primary_get_hw_state(to_intel_plane(primary)); |
15266 | ||
936e71e3 | 15267 | if (plane_state->base.visible) |
b26d3ea3 | 15268 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); |
98ec7739 VS |
15269 | } |
15270 | ||
30e984df | 15271 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 | 15272 | { |
fac5e23e | 15273 | struct drm_i915_private *dev_priv = to_i915(dev); |
24929352 | 15274 | enum pipe pipe; |
24929352 DV |
15275 | struct intel_crtc *crtc; |
15276 | struct intel_encoder *encoder; | |
15277 | struct intel_connector *connector; | |
5358901f | 15278 | int i; |
24929352 | 15279 | |
565602d7 ML |
15280 | dev_priv->active_crtcs = 0; |
15281 | ||
d3fcc808 | 15282 | for_each_intel_crtc(dev, crtc) { |
a8cd6da0 VS |
15283 | struct intel_crtc_state *crtc_state = |
15284 | to_intel_crtc_state(crtc->base.state); | |
3b117c8f | 15285 | |
ec2dc6a0 | 15286 | __drm_atomic_helper_crtc_destroy_state(&crtc_state->base); |
565602d7 ML |
15287 | memset(crtc_state, 0, sizeof(*crtc_state)); |
15288 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 15289 | |
565602d7 ML |
15290 | crtc_state->base.active = crtc_state->base.enable = |
15291 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
15292 | ||
15293 | crtc->base.enabled = crtc_state->base.enable; | |
15294 | crtc->active = crtc_state->base.active; | |
15295 | ||
aca1ebf4 | 15296 | if (crtc_state->base.active) |
565602d7 ML |
15297 | dev_priv->active_crtcs |= 1 << crtc->pipe; |
15298 | ||
f9cd7b88 | 15299 | readout_plane_state(crtc); |
24929352 | 15300 | |
78108b7c VS |
15301 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n", |
15302 | crtc->base.base.id, crtc->base.name, | |
a8cd6da0 | 15303 | enableddisabled(crtc_state->base.active)); |
24929352 DV |
15304 | } |
15305 | ||
5358901f DV |
15306 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15307 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15308 | ||
2edd6443 | 15309 | pll->on = pll->funcs.get_hw_state(dev_priv, pll, |
2c42e535 ACO |
15310 | &pll->state.hw_state); |
15311 | pll->state.crtc_mask = 0; | |
d3fcc808 | 15312 | for_each_intel_crtc(dev, crtc) { |
a8cd6da0 VS |
15313 | struct intel_crtc_state *crtc_state = |
15314 | to_intel_crtc_state(crtc->base.state); | |
15315 | ||
15316 | if (crtc_state->base.active && | |
15317 | crtc_state->shared_dpll == pll) | |
2c42e535 | 15318 | pll->state.crtc_mask |= 1 << crtc->pipe; |
5358901f | 15319 | } |
2c42e535 | 15320 | pll->active_mask = pll->state.crtc_mask; |
5358901f | 15321 | |
1e6f2ddc | 15322 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
2c42e535 | 15323 | pll->name, pll->state.crtc_mask, pll->on); |
5358901f DV |
15324 | } |
15325 | ||
b2784e15 | 15326 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15327 | pipe = 0; |
15328 | ||
15329 | if (encoder->get_hw_state(encoder, &pipe)) { | |
a8cd6da0 VS |
15330 | struct intel_crtc_state *crtc_state; |
15331 | ||
98187836 | 15332 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
a8cd6da0 | 15333 | crtc_state = to_intel_crtc_state(crtc->base.state); |
e2af48c6 | 15334 | |
045ac3b5 | 15335 | encoder->base.crtc = &crtc->base; |
a8cd6da0 VS |
15336 | crtc_state->output_types |= 1 << encoder->type; |
15337 | encoder->get_config(encoder, crtc_state); | |
24929352 DV |
15338 | } else { |
15339 | encoder->base.crtc = NULL; | |
15340 | } | |
15341 | ||
6f2bcceb | 15342 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
08c4d7fc TU |
15343 | encoder->base.base.id, encoder->base.name, |
15344 | enableddisabled(encoder->base.crtc), | |
6f2bcceb | 15345 | pipe_name(pipe)); |
24929352 DV |
15346 | } |
15347 | ||
3a3371ff | 15348 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15349 | if (connector->get_hw_state(connector)) { |
15350 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
15351 | |
15352 | encoder = connector->encoder; | |
15353 | connector->base.encoder = &encoder->base; | |
15354 | ||
15355 | if (encoder->base.crtc && | |
15356 | encoder->base.crtc->state->active) { | |
15357 | /* | |
15358 | * This has to be done during hardware readout | |
15359 | * because anything calling .crtc_disable may | |
15360 | * rely on the connector_mask being accurate. | |
15361 | */ | |
15362 | encoder->base.crtc->state->connector_mask |= | |
15363 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
15364 | encoder->base.crtc->state->encoder_mask |= |
15365 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
15366 | } |
15367 | ||
24929352 DV |
15368 | } else { |
15369 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15370 | connector->base.encoder = NULL; | |
15371 | } | |
15372 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
08c4d7fc TU |
15373 | connector->base.base.id, connector->base.name, |
15374 | enableddisabled(connector->base.encoder)); | |
24929352 | 15375 | } |
7f4c6284 VS |
15376 | |
15377 | for_each_intel_crtc(dev, crtc) { | |
a8cd6da0 VS |
15378 | struct intel_crtc_state *crtc_state = |
15379 | to_intel_crtc_state(crtc->base.state); | |
aca1ebf4 VS |
15380 | int pixclk = 0; |
15381 | ||
a8cd6da0 | 15382 | crtc->base.hwmode = crtc_state->base.adjusted_mode; |
7f4c6284 VS |
15383 | |
15384 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
a8cd6da0 VS |
15385 | if (crtc_state->base.active) { |
15386 | intel_mode_from_pipe_config(&crtc->base.mode, crtc_state); | |
15387 | intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state); | |
7f4c6284 VS |
15388 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); |
15389 | ||
15390 | /* | |
15391 | * The initial mode needs to be set in order to keep | |
15392 | * the atomic core happy. It wants a valid mode if the | |
15393 | * crtc's enabled, so we do the above call. | |
15394 | * | |
7800fb69 DV |
15395 | * But we don't set all the derived state fully, hence |
15396 | * set a flag to indicate that a full recalculation is | |
15397 | * needed on the next commit. | |
7f4c6284 | 15398 | */ |
a8cd6da0 | 15399 | crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED; |
9eca6832 | 15400 | |
a7d1b3f4 VS |
15401 | intel_crtc_compute_pixel_rate(crtc_state); |
15402 | ||
15403 | if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) || | |
15404 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
15405 | pixclk = crtc_state->pixel_rate; | |
aca1ebf4 VS |
15406 | else |
15407 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
15408 | ||
15409 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
a8cd6da0 | 15410 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
aca1ebf4 VS |
15411 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); |
15412 | ||
9eca6832 VS |
15413 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); |
15414 | update_scanline_offset(crtc); | |
7f4c6284 | 15415 | } |
e3b247da | 15416 | |
aca1ebf4 VS |
15417 | dev_priv->min_pixclk[crtc->pipe] = pixclk; |
15418 | ||
a8cd6da0 | 15419 | intel_pipe_config_sanity_check(dev_priv, crtc_state); |
7f4c6284 | 15420 | } |
30e984df DV |
15421 | } |
15422 | ||
62b69566 ACO |
15423 | static void |
15424 | get_encoder_power_domains(struct drm_i915_private *dev_priv) | |
15425 | { | |
15426 | struct intel_encoder *encoder; | |
15427 | ||
15428 | for_each_intel_encoder(&dev_priv->drm, encoder) { | |
15429 | u64 get_domains; | |
15430 | enum intel_display_power_domain domain; | |
15431 | ||
15432 | if (!encoder->get_power_domains) | |
15433 | continue; | |
15434 | ||
15435 | get_domains = encoder->get_power_domains(encoder); | |
15436 | for_each_power_domain(domain, get_domains) | |
15437 | intel_display_power_get(dev_priv, domain); | |
15438 | } | |
15439 | } | |
15440 | ||
043e9bda ML |
15441 | /* Scan out the current hw modeset state, |
15442 | * and sanitizes it to the current state | |
15443 | */ | |
15444 | static void | |
15445 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df | 15446 | { |
fac5e23e | 15447 | struct drm_i915_private *dev_priv = to_i915(dev); |
30e984df | 15448 | enum pipe pipe; |
30e984df DV |
15449 | struct intel_crtc *crtc; |
15450 | struct intel_encoder *encoder; | |
35c95375 | 15451 | int i; |
30e984df DV |
15452 | |
15453 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
15454 | |
15455 | /* HW state is read out, now we need to sanitize this mess. */ | |
62b69566 ACO |
15456 | get_encoder_power_domains(dev_priv); |
15457 | ||
b2784e15 | 15458 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15459 | intel_sanitize_encoder(encoder); |
15460 | } | |
15461 | ||
055e393f | 15462 | for_each_pipe(dev_priv, pipe) { |
98187836 | 15463 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
e2af48c6 | 15464 | |
24929352 | 15465 | intel_sanitize_crtc(crtc); |
6e3c9717 ACO |
15466 | intel_dump_pipe_config(crtc, crtc->config, |
15467 | "[setup_hw_state]"); | |
24929352 | 15468 | } |
9a935856 | 15469 | |
d29b2f9d ACO |
15470 | intel_modeset_update_connector_atomic_state(dev); |
15471 | ||
35c95375 DV |
15472 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15473 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15474 | ||
2dd66ebd | 15475 | if (!pll->on || pll->active_mask) |
35c95375 DV |
15476 | continue; |
15477 | ||
15478 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15479 | ||
2edd6443 | 15480 | pll->funcs.disable(dev_priv, pll); |
35c95375 DV |
15481 | pll->on = false; |
15482 | } | |
15483 | ||
920a14b2 | 15484 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
6eb1a681 | 15485 | vlv_wm_get_hw_state(dev); |
5db94019 | 15486 | else if (IS_GEN9(dev_priv)) |
3078999f | 15487 | skl_wm_get_hw_state(dev); |
6e266956 | 15488 | else if (HAS_PCH_SPLIT(dev_priv)) |
243e6a44 | 15489 | ilk_wm_get_hw_state(dev); |
292b990e ML |
15490 | |
15491 | for_each_intel_crtc(dev, crtc) { | |
d8fc70b7 | 15492 | u64 put_domains; |
292b990e | 15493 | |
74bff5f9 | 15494 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
292b990e ML |
15495 | if (WARN_ON(put_domains)) |
15496 | modeset_put_power_domains(dev_priv, put_domains); | |
15497 | } | |
15498 | intel_display_set_init_power(dev_priv, false); | |
010cf73d | 15499 | |
8d8c386c ID |
15500 | intel_power_domains_verify_state(dev_priv); |
15501 | ||
010cf73d | 15502 | intel_fbc_init_pipe_state(dev_priv); |
043e9bda | 15503 | } |
7d0bc1ea | 15504 | |
043e9bda ML |
15505 | void intel_display_resume(struct drm_device *dev) |
15506 | { | |
e2c8b870 ML |
15507 | struct drm_i915_private *dev_priv = to_i915(dev); |
15508 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
15509 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 15510 | int ret; |
f30da187 | 15511 | |
e2c8b870 | 15512 | dev_priv->modeset_restore_state = NULL; |
73974893 ML |
15513 | if (state) |
15514 | state->acquire_ctx = &ctx; | |
043e9bda | 15515 | |
ea49c9ac ML |
15516 | /* |
15517 | * This is a cludge because with real atomic modeset mode_config.mutex | |
15518 | * won't be taken. Unfortunately some probed state like | |
15519 | * audio_codec_enable is still protected by mode_config.mutex, so lock | |
15520 | * it here for now. | |
15521 | */ | |
15522 | mutex_lock(&dev->mode_config.mutex); | |
e2c8b870 | 15523 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 15524 | |
73974893 ML |
15525 | while (1) { |
15526 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
15527 | if (ret != -EDEADLK) | |
15528 | break; | |
043e9bda | 15529 | |
e2c8b870 | 15530 | drm_modeset_backoff(&ctx); |
e2c8b870 | 15531 | } |
043e9bda | 15532 | |
73974893 ML |
15533 | if (!ret) |
15534 | ret = __intel_display_resume(dev, state); | |
15535 | ||
e2c8b870 ML |
15536 | drm_modeset_drop_locks(&ctx); |
15537 | drm_modeset_acquire_fini(&ctx); | |
ea49c9ac | 15538 | mutex_unlock(&dev->mode_config.mutex); |
043e9bda | 15539 | |
0853695c | 15540 | if (ret) |
e2c8b870 | 15541 | DRM_ERROR("Restoring old state failed with %i\n", ret); |
3c5e37f1 CW |
15542 | if (state) |
15543 | drm_atomic_state_put(state); | |
2c7111db CW |
15544 | } |
15545 | ||
15546 | void intel_modeset_gem_init(struct drm_device *dev) | |
15547 | { | |
dc97997a | 15548 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 15549 | |
dc97997a | 15550 | intel_init_gt_powersave(dev_priv); |
ae48434c | 15551 | |
1ee8da6d | 15552 | intel_setup_overlay(dev_priv); |
1ebaa0b9 CW |
15553 | } |
15554 | ||
15555 | int intel_connector_register(struct drm_connector *connector) | |
15556 | { | |
15557 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
15558 | int ret; | |
15559 | ||
15560 | ret = intel_backlight_device_register(intel_connector); | |
15561 | if (ret) | |
15562 | goto err; | |
15563 | ||
15564 | return 0; | |
0962c3c9 | 15565 | |
1ebaa0b9 CW |
15566 | err: |
15567 | return ret; | |
79e53945 JB |
15568 | } |
15569 | ||
c191eca1 | 15570 | void intel_connector_unregister(struct drm_connector *connector) |
4932e2c3 | 15571 | { |
e63d87c0 | 15572 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4932e2c3 | 15573 | |
e63d87c0 | 15574 | intel_backlight_device_unregister(intel_connector); |
4932e2c3 | 15575 | intel_panel_destroy_backlight(connector); |
4932e2c3 ID |
15576 | } |
15577 | ||
79e53945 JB |
15578 | void intel_modeset_cleanup(struct drm_device *dev) |
15579 | { | |
fac5e23e | 15580 | struct drm_i915_private *dev_priv = to_i915(dev); |
652c393a | 15581 | |
eb955eee CW |
15582 | flush_work(&dev_priv->atomic_helper.free_work); |
15583 | WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list)); | |
15584 | ||
dc97997a | 15585 | intel_disable_gt_powersave(dev_priv); |
2eb5252e | 15586 | |
fd0c0642 DV |
15587 | /* |
15588 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 15589 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
15590 | * experience fancy races otherwise. |
15591 | */ | |
2aeb7d3a | 15592 | intel_irq_uninstall(dev_priv); |
eb21b92b | 15593 | |
fd0c0642 DV |
15594 | /* |
15595 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
15596 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
15597 | */ | |
f87ea761 | 15598 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 15599 | |
723bfd70 JB |
15600 | intel_unregister_dsm_handler(); |
15601 | ||
c937ab3e | 15602 | intel_fbc_global_disable(dev_priv); |
69341a5e | 15603 | |
1630fe75 CW |
15604 | /* flush any delayed tasks or pending work */ |
15605 | flush_scheduled_work(); | |
15606 | ||
79e53945 | 15607 | drm_mode_config_cleanup(dev); |
4d7bb011 | 15608 | |
1ee8da6d | 15609 | intel_cleanup_overlay(dev_priv); |
ae48434c | 15610 | |
dc97997a | 15611 | intel_cleanup_gt_powersave(dev_priv); |
f5949141 | 15612 | |
40196446 | 15613 | intel_teardown_gmbus(dev_priv); |
79e53945 JB |
15614 | } |
15615 | ||
df0e9248 CW |
15616 | void intel_connector_attach_encoder(struct intel_connector *connector, |
15617 | struct intel_encoder *encoder) | |
15618 | { | |
15619 | connector->encoder = encoder; | |
15620 | drm_mode_connector_attach_encoder(&connector->base, | |
15621 | &encoder->base); | |
79e53945 | 15622 | } |
28d52043 DA |
15623 | |
15624 | /* | |
15625 | * set vga decode state - true == enable VGA decode | |
15626 | */ | |
6315b5d3 | 15627 | int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state) |
28d52043 | 15628 | { |
6315b5d3 | 15629 | unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
15630 | u16 gmch_ctrl; |
15631 | ||
75fa041d CW |
15632 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
15633 | DRM_ERROR("failed to read control word\n"); | |
15634 | return -EIO; | |
15635 | } | |
15636 | ||
c0cc8a55 CW |
15637 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
15638 | return 0; | |
15639 | ||
28d52043 DA |
15640 | if (state) |
15641 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
15642 | else | |
15643 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
15644 | |
15645 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
15646 | DRM_ERROR("failed to write control word\n"); | |
15647 | return -EIO; | |
15648 | } | |
15649 | ||
28d52043 DA |
15650 | return 0; |
15651 | } | |
c4a1d9e4 | 15652 | |
98a2f411 CW |
15653 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
15654 | ||
c4a1d9e4 | 15655 | struct intel_display_error_state { |
ff57f1b0 PZ |
15656 | |
15657 | u32 power_well_driver; | |
15658 | ||
63b66e5b CW |
15659 | int num_transcoders; |
15660 | ||
c4a1d9e4 CW |
15661 | struct intel_cursor_error_state { |
15662 | u32 control; | |
15663 | u32 position; | |
15664 | u32 base; | |
15665 | u32 size; | |
52331309 | 15666 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15667 | |
15668 | struct intel_pipe_error_state { | |
ddf9c536 | 15669 | bool power_domain_on; |
c4a1d9e4 | 15670 | u32 source; |
f301b1e1 | 15671 | u32 stat; |
52331309 | 15672 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15673 | |
15674 | struct intel_plane_error_state { | |
15675 | u32 control; | |
15676 | u32 stride; | |
15677 | u32 size; | |
15678 | u32 pos; | |
15679 | u32 addr; | |
15680 | u32 surface; | |
15681 | u32 tile_offset; | |
52331309 | 15682 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
15683 | |
15684 | struct intel_transcoder_error_state { | |
ddf9c536 | 15685 | bool power_domain_on; |
63b66e5b CW |
15686 | enum transcoder cpu_transcoder; |
15687 | ||
15688 | u32 conf; | |
15689 | ||
15690 | u32 htotal; | |
15691 | u32 hblank; | |
15692 | u32 hsync; | |
15693 | u32 vtotal; | |
15694 | u32 vblank; | |
15695 | u32 vsync; | |
15696 | } transcoder[4]; | |
c4a1d9e4 CW |
15697 | }; |
15698 | ||
15699 | struct intel_display_error_state * | |
c033666a | 15700 | intel_display_capture_error_state(struct drm_i915_private *dev_priv) |
c4a1d9e4 | 15701 | { |
c4a1d9e4 | 15702 | struct intel_display_error_state *error; |
63b66e5b CW |
15703 | int transcoders[] = { |
15704 | TRANSCODER_A, | |
15705 | TRANSCODER_B, | |
15706 | TRANSCODER_C, | |
15707 | TRANSCODER_EDP, | |
15708 | }; | |
c4a1d9e4 CW |
15709 | int i; |
15710 | ||
c033666a | 15711 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
63b66e5b CW |
15712 | return NULL; |
15713 | ||
9d1cb914 | 15714 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
15715 | if (error == NULL) |
15716 | return NULL; | |
15717 | ||
c033666a | 15718 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ff57f1b0 PZ |
15719 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
15720 | ||
055e393f | 15721 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 15722 | error->pipe[i].power_domain_on = |
f458ebbc DV |
15723 | __intel_display_power_is_enabled(dev_priv, |
15724 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 15725 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
15726 | continue; |
15727 | ||
5efb3e28 VS |
15728 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
15729 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
15730 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
15731 | |
15732 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
15733 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
c033666a | 15734 | if (INTEL_GEN(dev_priv) <= 3) { |
51889b35 | 15735 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
15736 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
15737 | } | |
c033666a | 15738 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
ca291363 | 15739 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
c033666a | 15740 | if (INTEL_GEN(dev_priv) >= 4) { |
c4a1d9e4 CW |
15741 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
15742 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
15743 | } | |
15744 | ||
c4a1d9e4 | 15745 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 15746 | |
c033666a | 15747 | if (HAS_GMCH_DISPLAY(dev_priv)) |
f301b1e1 | 15748 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
15749 | } |
15750 | ||
4d1de975 | 15751 | /* Note: this does not include DSI transcoders. */ |
c033666a | 15752 | error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes; |
2d1fe073 | 15753 | if (HAS_DDI(dev_priv)) |
63b66e5b CW |
15754 | error->num_transcoders++; /* Account for eDP. */ |
15755 | ||
15756 | for (i = 0; i < error->num_transcoders; i++) { | |
15757 | enum transcoder cpu_transcoder = transcoders[i]; | |
15758 | ||
ddf9c536 | 15759 | error->transcoder[i].power_domain_on = |
f458ebbc | 15760 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 15761 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 15762 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
15763 | continue; |
15764 | ||
63b66e5b CW |
15765 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
15766 | ||
15767 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
15768 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
15769 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
15770 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
15771 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
15772 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
15773 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
15774 | } |
15775 | ||
15776 | return error; | |
15777 | } | |
15778 | ||
edc3d884 MK |
15779 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
15780 | ||
c4a1d9e4 | 15781 | void |
edc3d884 | 15782 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
15783 | struct intel_display_error_state *error) |
15784 | { | |
5a4c6f1b | 15785 | struct drm_i915_private *dev_priv = m->i915; |
c4a1d9e4 CW |
15786 | int i; |
15787 | ||
63b66e5b CW |
15788 | if (!error) |
15789 | return; | |
15790 | ||
b7f05d4a | 15791 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes); |
8652744b | 15792 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
edc3d884 | 15793 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 15794 | error->power_well_driver); |
055e393f | 15795 | for_each_pipe(dev_priv, i) { |
edc3d884 | 15796 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 15797 | err_printf(m, " Power: %s\n", |
87ad3212 | 15798 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 15799 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 15800 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
15801 | |
15802 | err_printf(m, "Plane [%d]:\n", i); | |
15803 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
15804 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
5f56d5f9 | 15805 | if (INTEL_GEN(dev_priv) <= 3) { |
edc3d884 MK |
15806 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
15807 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 15808 | } |
772c2a51 | 15809 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
edc3d884 | 15810 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
5f56d5f9 | 15811 | if (INTEL_GEN(dev_priv) >= 4) { |
edc3d884 MK |
15812 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
15813 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
15814 | } |
15815 | ||
edc3d884 MK |
15816 | err_printf(m, "Cursor [%d]:\n", i); |
15817 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
15818 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
15819 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 15820 | } |
63b66e5b CW |
15821 | |
15822 | for (i = 0; i < error->num_transcoders; i++) { | |
da205630 | 15823 | err_printf(m, "CPU transcoder: %s\n", |
63b66e5b | 15824 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 15825 | err_printf(m, " Power: %s\n", |
87ad3212 | 15826 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
15827 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
15828 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
15829 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
15830 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
15831 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
15832 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
15833 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
15834 | } | |
c4a1d9e4 | 15835 | } |
98a2f411 CW |
15836 | |
15837 | #endif |