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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
319c1d42 | 40 | #include <drm/drm_atomic.h> |
c196e1d6 | 41 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
42 | #include <drm/drm_dp_helper.h> |
43 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
44 | #include <drm/drm_plane_helper.h> |
45 | #include <drm/drm_rect.h> | |
c0f372b3 | 46 | #include <linux/dma_remapping.h> |
fd8e058a AG |
47 | #include <linux/reservation.h> |
48 | #include <linux/dma-buf.h> | |
79e53945 | 49 | |
465c120c | 50 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 51 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
52 | DRM_FORMAT_C8, |
53 | DRM_FORMAT_RGB565, | |
465c120c | 54 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 55 | DRM_FORMAT_XRGB8888, |
465c120c MR |
56 | }; |
57 | ||
58 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 59 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
60 | DRM_FORMAT_C8, |
61 | DRM_FORMAT_RGB565, | |
62 | DRM_FORMAT_XRGB8888, | |
63 | DRM_FORMAT_XBGR8888, | |
64 | DRM_FORMAT_XRGB2101010, | |
65 | DRM_FORMAT_XBGR2101010, | |
66 | }; | |
67 | ||
68 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
69 | DRM_FORMAT_C8, |
70 | DRM_FORMAT_RGB565, | |
71 | DRM_FORMAT_XRGB8888, | |
465c120c | 72 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 73 | DRM_FORMAT_ARGB8888, |
465c120c MR |
74 | DRM_FORMAT_ABGR8888, |
75 | DRM_FORMAT_XRGB2101010, | |
465c120c | 76 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
77 | DRM_FORMAT_YUYV, |
78 | DRM_FORMAT_YVYU, | |
79 | DRM_FORMAT_UYVY, | |
80 | DRM_FORMAT_VYUY, | |
465c120c MR |
81 | }; |
82 | ||
3d7d6510 MR |
83 | /* Cursor formats */ |
84 | static const uint32_t intel_cursor_formats[] = { | |
85 | DRM_FORMAT_ARGB8888, | |
86 | }; | |
87 | ||
6b383a7f | 88 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 89 | |
f1f644dc | 90 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 91 | struct intel_crtc_state *pipe_config); |
18442d08 | 92 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 93 | struct intel_crtc_state *pipe_config); |
f1f644dc | 94 | |
eb1bfe80 JB |
95 | static int intel_framebuffer_init(struct drm_device *dev, |
96 | struct intel_framebuffer *ifb, | |
97 | struct drm_mode_fb_cmd2 *mode_cmd, | |
98 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
99 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
100 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 101 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
102 | struct intel_link_m_n *m_n, |
103 | struct intel_link_m_n *m2_n2); | |
29407aab | 104 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
105 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
106 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f | 107 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 108 | const struct intel_crtc_state *pipe_config); |
d288f65f | 109 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 110 | const struct intel_crtc_state *pipe_config); |
613d2b27 ML |
111 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
112 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
549e2bfb CK |
113 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
114 | struct intel_crtc_state *crtc_state); | |
5ab7b0b7 ID |
115 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
116 | int num_connectors); | |
bfd16b2a ML |
117 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
118 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
119 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 120 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
200757f5 | 121 | static void intel_pre_disable_primary(struct drm_crtc *crtc); |
e7457a9a | 122 | |
79e53945 | 123 | typedef struct { |
0206e353 | 124 | int min, max; |
79e53945 JB |
125 | } intel_range_t; |
126 | ||
127 | typedef struct { | |
0206e353 AJ |
128 | int dot_limit; |
129 | int p2_slow, p2_fast; | |
79e53945 JB |
130 | } intel_p2_t; |
131 | ||
d4906093 ML |
132 | typedef struct intel_limit intel_limit_t; |
133 | struct intel_limit { | |
0206e353 AJ |
134 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
135 | intel_p2_t p2; | |
d4906093 | 136 | }; |
79e53945 | 137 | |
bfa7df01 VS |
138 | /* returns HPLL frequency in kHz */ |
139 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) | |
140 | { | |
141 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
142 | ||
143 | /* Obtain SKU information */ | |
144 | mutex_lock(&dev_priv->sb_lock); | |
145 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
146 | CCK_FUSE_HPLL_FREQ_MASK; | |
147 | mutex_unlock(&dev_priv->sb_lock); | |
148 | ||
149 | return vco_freq[hpll_freq] * 1000; | |
150 | } | |
151 | ||
152 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
153 | const char *name, u32 reg) | |
154 | { | |
155 | u32 val; | |
156 | int divider; | |
157 | ||
158 | if (dev_priv->hpll_freq == 0) | |
159 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
160 | ||
161 | mutex_lock(&dev_priv->sb_lock); | |
162 | val = vlv_cck_read(dev_priv, reg); | |
163 | mutex_unlock(&dev_priv->sb_lock); | |
164 | ||
165 | divider = val & CCK_FREQUENCY_VALUES; | |
166 | ||
167 | WARN((val & CCK_FREQUENCY_STATUS) != | |
168 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
169 | "%s change in progress\n", name); | |
170 | ||
171 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); | |
172 | } | |
173 | ||
d2acd215 DV |
174 | int |
175 | intel_pch_rawclk(struct drm_device *dev) | |
176 | { | |
177 | struct drm_i915_private *dev_priv = dev->dev_private; | |
178 | ||
179 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
180 | ||
181 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
182 | } | |
183 | ||
79e50a4f JN |
184 | /* hrawclock is 1/4 the FSB frequency */ |
185 | int intel_hrawclk(struct drm_device *dev) | |
186 | { | |
187 | struct drm_i915_private *dev_priv = dev->dev_private; | |
188 | uint32_t clkcfg; | |
189 | ||
190 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ | |
666a4537 | 191 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
79e50a4f JN |
192 | return 200; |
193 | ||
194 | clkcfg = I915_READ(CLKCFG); | |
195 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
196 | case CLKCFG_FSB_400: | |
197 | return 100; | |
198 | case CLKCFG_FSB_533: | |
199 | return 133; | |
200 | case CLKCFG_FSB_667: | |
201 | return 166; | |
202 | case CLKCFG_FSB_800: | |
203 | return 200; | |
204 | case CLKCFG_FSB_1067: | |
205 | return 266; | |
206 | case CLKCFG_FSB_1333: | |
207 | return 333; | |
208 | /* these two are just a guess; one of them might be right */ | |
209 | case CLKCFG_FSB_1600: | |
210 | case CLKCFG_FSB_1600_ALT: | |
211 | return 400; | |
212 | default: | |
213 | return 133; | |
214 | } | |
215 | } | |
216 | ||
bfa7df01 VS |
217 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
218 | { | |
666a4537 | 219 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
220 | return; |
221 | ||
222 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
223 | CCK_CZ_CLOCK_CONTROL); | |
224 | ||
225 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
226 | } | |
227 | ||
021357ac CW |
228 | static inline u32 /* units of 100MHz */ |
229 | intel_fdi_link_freq(struct drm_device *dev) | |
230 | { | |
8b99e68c CW |
231 | if (IS_GEN5(dev)) { |
232 | struct drm_i915_private *dev_priv = dev->dev_private; | |
233 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
234 | } else | |
235 | return 27; | |
021357ac CW |
236 | } |
237 | ||
5d536e28 | 238 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 239 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 240 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 241 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
242 | .m = { .min = 96, .max = 140 }, |
243 | .m1 = { .min = 18, .max = 26 }, | |
244 | .m2 = { .min = 6, .max = 16 }, | |
245 | .p = { .min = 4, .max = 128 }, | |
246 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
247 | .p2 = { .dot_limit = 165000, |
248 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
249 | }; |
250 | ||
5d536e28 DV |
251 | static const intel_limit_t intel_limits_i8xx_dvo = { |
252 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 253 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 254 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
255 | .m = { .min = 96, .max = 140 }, |
256 | .m1 = { .min = 18, .max = 26 }, | |
257 | .m2 = { .min = 6, .max = 16 }, | |
258 | .p = { .min = 4, .max = 128 }, | |
259 | .p1 = { .min = 2, .max = 33 }, | |
260 | .p2 = { .dot_limit = 165000, | |
261 | .p2_slow = 4, .p2_fast = 4 }, | |
262 | }; | |
263 | ||
e4b36699 | 264 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 265 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 266 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 267 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
268 | .m = { .min = 96, .max = 140 }, |
269 | .m1 = { .min = 18, .max = 26 }, | |
270 | .m2 = { .min = 6, .max = 16 }, | |
271 | .p = { .min = 4, .max = 128 }, | |
272 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
273 | .p2 = { .dot_limit = 165000, |
274 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 275 | }; |
273e27ca | 276 | |
e4b36699 | 277 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
278 | .dot = { .min = 20000, .max = 400000 }, |
279 | .vco = { .min = 1400000, .max = 2800000 }, | |
280 | .n = { .min = 1, .max = 6 }, | |
281 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
282 | .m1 = { .min = 8, .max = 18 }, |
283 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
284 | .p = { .min = 5, .max = 80 }, |
285 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
286 | .p2 = { .dot_limit = 200000, |
287 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
288 | }; |
289 | ||
290 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
291 | .dot = { .min = 20000, .max = 400000 }, |
292 | .vco = { .min = 1400000, .max = 2800000 }, | |
293 | .n = { .min = 1, .max = 6 }, | |
294 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
295 | .m1 = { .min = 8, .max = 18 }, |
296 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
297 | .p = { .min = 7, .max = 98 }, |
298 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
299 | .p2 = { .dot_limit = 112000, |
300 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
301 | }; |
302 | ||
273e27ca | 303 | |
e4b36699 | 304 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
305 | .dot = { .min = 25000, .max = 270000 }, |
306 | .vco = { .min = 1750000, .max = 3500000}, | |
307 | .n = { .min = 1, .max = 4 }, | |
308 | .m = { .min = 104, .max = 138 }, | |
309 | .m1 = { .min = 17, .max = 23 }, | |
310 | .m2 = { .min = 5, .max = 11 }, | |
311 | .p = { .min = 10, .max = 30 }, | |
312 | .p1 = { .min = 1, .max = 3}, | |
313 | .p2 = { .dot_limit = 270000, | |
314 | .p2_slow = 10, | |
315 | .p2_fast = 10 | |
044c7c41 | 316 | }, |
e4b36699 KP |
317 | }; |
318 | ||
319 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
320 | .dot = { .min = 22000, .max = 400000 }, |
321 | .vco = { .min = 1750000, .max = 3500000}, | |
322 | .n = { .min = 1, .max = 4 }, | |
323 | .m = { .min = 104, .max = 138 }, | |
324 | .m1 = { .min = 16, .max = 23 }, | |
325 | .m2 = { .min = 5, .max = 11 }, | |
326 | .p = { .min = 5, .max = 80 }, | |
327 | .p1 = { .min = 1, .max = 8}, | |
328 | .p2 = { .dot_limit = 165000, | |
329 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
330 | }; |
331 | ||
332 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
333 | .dot = { .min = 20000, .max = 115000 }, |
334 | .vco = { .min = 1750000, .max = 3500000 }, | |
335 | .n = { .min = 1, .max = 3 }, | |
336 | .m = { .min = 104, .max = 138 }, | |
337 | .m1 = { .min = 17, .max = 23 }, | |
338 | .m2 = { .min = 5, .max = 11 }, | |
339 | .p = { .min = 28, .max = 112 }, | |
340 | .p1 = { .min = 2, .max = 8 }, | |
341 | .p2 = { .dot_limit = 0, | |
342 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 343 | }, |
e4b36699 KP |
344 | }; |
345 | ||
346 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
347 | .dot = { .min = 80000, .max = 224000 }, |
348 | .vco = { .min = 1750000, .max = 3500000 }, | |
349 | .n = { .min = 1, .max = 3 }, | |
350 | .m = { .min = 104, .max = 138 }, | |
351 | .m1 = { .min = 17, .max = 23 }, | |
352 | .m2 = { .min = 5, .max = 11 }, | |
353 | .p = { .min = 14, .max = 42 }, | |
354 | .p1 = { .min = 2, .max = 6 }, | |
355 | .p2 = { .dot_limit = 0, | |
356 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 357 | }, |
e4b36699 KP |
358 | }; |
359 | ||
f2b115e6 | 360 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
361 | .dot = { .min = 20000, .max = 400000}, |
362 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 363 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
364 | .n = { .min = 3, .max = 6 }, |
365 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 366 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
367 | .m1 = { .min = 0, .max = 0 }, |
368 | .m2 = { .min = 0, .max = 254 }, | |
369 | .p = { .min = 5, .max = 80 }, | |
370 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
371 | .p2 = { .dot_limit = 200000, |
372 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
373 | }; |
374 | ||
f2b115e6 | 375 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
376 | .dot = { .min = 20000, .max = 400000 }, |
377 | .vco = { .min = 1700000, .max = 3500000 }, | |
378 | .n = { .min = 3, .max = 6 }, | |
379 | .m = { .min = 2, .max = 256 }, | |
380 | .m1 = { .min = 0, .max = 0 }, | |
381 | .m2 = { .min = 0, .max = 254 }, | |
382 | .p = { .min = 7, .max = 112 }, | |
383 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
384 | .p2 = { .dot_limit = 112000, |
385 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
386 | }; |
387 | ||
273e27ca EA |
388 | /* Ironlake / Sandybridge |
389 | * | |
390 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
391 | * the range value for them is (actual_value - 2). | |
392 | */ | |
b91ad0ec | 393 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
394 | .dot = { .min = 25000, .max = 350000 }, |
395 | .vco = { .min = 1760000, .max = 3510000 }, | |
396 | .n = { .min = 1, .max = 5 }, | |
397 | .m = { .min = 79, .max = 127 }, | |
398 | .m1 = { .min = 12, .max = 22 }, | |
399 | .m2 = { .min = 5, .max = 9 }, | |
400 | .p = { .min = 5, .max = 80 }, | |
401 | .p1 = { .min = 1, .max = 8 }, | |
402 | .p2 = { .dot_limit = 225000, | |
403 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
404 | }; |
405 | ||
b91ad0ec | 406 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
407 | .dot = { .min = 25000, .max = 350000 }, |
408 | .vco = { .min = 1760000, .max = 3510000 }, | |
409 | .n = { .min = 1, .max = 3 }, | |
410 | .m = { .min = 79, .max = 118 }, | |
411 | .m1 = { .min = 12, .max = 22 }, | |
412 | .m2 = { .min = 5, .max = 9 }, | |
413 | .p = { .min = 28, .max = 112 }, | |
414 | .p1 = { .min = 2, .max = 8 }, | |
415 | .p2 = { .dot_limit = 225000, | |
416 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
417 | }; |
418 | ||
419 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
420 | .dot = { .min = 25000, .max = 350000 }, |
421 | .vco = { .min = 1760000, .max = 3510000 }, | |
422 | .n = { .min = 1, .max = 3 }, | |
423 | .m = { .min = 79, .max = 127 }, | |
424 | .m1 = { .min = 12, .max = 22 }, | |
425 | .m2 = { .min = 5, .max = 9 }, | |
426 | .p = { .min = 14, .max = 56 }, | |
427 | .p1 = { .min = 2, .max = 8 }, | |
428 | .p2 = { .dot_limit = 225000, | |
429 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
430 | }; |
431 | ||
273e27ca | 432 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 433 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
434 | .dot = { .min = 25000, .max = 350000 }, |
435 | .vco = { .min = 1760000, .max = 3510000 }, | |
436 | .n = { .min = 1, .max = 2 }, | |
437 | .m = { .min = 79, .max = 126 }, | |
438 | .m1 = { .min = 12, .max = 22 }, | |
439 | .m2 = { .min = 5, .max = 9 }, | |
440 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 441 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
442 | .p2 = { .dot_limit = 225000, |
443 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
444 | }; |
445 | ||
446 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
447 | .dot = { .min = 25000, .max = 350000 }, |
448 | .vco = { .min = 1760000, .max = 3510000 }, | |
449 | .n = { .min = 1, .max = 3 }, | |
450 | .m = { .min = 79, .max = 126 }, | |
451 | .m1 = { .min = 12, .max = 22 }, | |
452 | .m2 = { .min = 5, .max = 9 }, | |
453 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 454 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
455 | .p2 = { .dot_limit = 225000, |
456 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
457 | }; |
458 | ||
dc730512 | 459 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
460 | /* |
461 | * These are the data rate limits (measured in fast clocks) | |
462 | * since those are the strictest limits we have. The fast | |
463 | * clock and actual rate limits are more relaxed, so checking | |
464 | * them would make no difference. | |
465 | */ | |
466 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 467 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 468 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
469 | .m1 = { .min = 2, .max = 3 }, |
470 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 471 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 472 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
473 | }; |
474 | ||
ef9348c8 CML |
475 | static const intel_limit_t intel_limits_chv = { |
476 | /* | |
477 | * These are the data rate limits (measured in fast clocks) | |
478 | * since those are the strictest limits we have. The fast | |
479 | * clock and actual rate limits are more relaxed, so checking | |
480 | * them would make no difference. | |
481 | */ | |
482 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 483 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
484 | .n = { .min = 1, .max = 1 }, |
485 | .m1 = { .min = 2, .max = 2 }, | |
486 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
487 | .p1 = { .min = 2, .max = 4 }, | |
488 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
489 | }; | |
490 | ||
5ab7b0b7 ID |
491 | static const intel_limit_t intel_limits_bxt = { |
492 | /* FIXME: find real dot limits */ | |
493 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 494 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
495 | .n = { .min = 1, .max = 1 }, |
496 | .m1 = { .min = 2, .max = 2 }, | |
497 | /* FIXME: find real m2 limits */ | |
498 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
499 | .p1 = { .min = 2, .max = 4 }, | |
500 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
501 | }; | |
502 | ||
cdba954e ACO |
503 | static bool |
504 | needs_modeset(struct drm_crtc_state *state) | |
505 | { | |
fc596660 | 506 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
507 | } |
508 | ||
e0638cdf PZ |
509 | /** |
510 | * Returns whether any output on the specified pipe is of the specified type | |
511 | */ | |
4093561b | 512 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 513 | { |
409ee761 | 514 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
515 | struct intel_encoder *encoder; |
516 | ||
409ee761 | 517 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
518 | if (encoder->type == type) |
519 | return true; | |
520 | ||
521 | return false; | |
522 | } | |
523 | ||
d0737e1d ACO |
524 | /** |
525 | * Returns whether any output on the specified pipe will have the specified | |
526 | * type after a staged modeset is complete, i.e., the same as | |
527 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
528 | * encoder->crtc. | |
529 | */ | |
a93e255f ACO |
530 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
531 | int type) | |
d0737e1d | 532 | { |
a93e255f | 533 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 534 | struct drm_connector *connector; |
a93e255f | 535 | struct drm_connector_state *connector_state; |
d0737e1d | 536 | struct intel_encoder *encoder; |
a93e255f ACO |
537 | int i, num_connectors = 0; |
538 | ||
da3ced29 | 539 | for_each_connector_in_state(state, connector, connector_state, i) { |
a93e255f ACO |
540 | if (connector_state->crtc != crtc_state->base.crtc) |
541 | continue; | |
542 | ||
543 | num_connectors++; | |
d0737e1d | 544 | |
a93e255f ACO |
545 | encoder = to_intel_encoder(connector_state->best_encoder); |
546 | if (encoder->type == type) | |
d0737e1d | 547 | return true; |
a93e255f ACO |
548 | } |
549 | ||
550 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
551 | |
552 | return false; | |
553 | } | |
554 | ||
a93e255f ACO |
555 | static const intel_limit_t * |
556 | intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) | |
2c07245f | 557 | { |
a93e255f | 558 | struct drm_device *dev = crtc_state->base.crtc->dev; |
2c07245f | 559 | const intel_limit_t *limit; |
b91ad0ec | 560 | |
a93e255f | 561 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 562 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 563 | if (refclk == 100000) |
b91ad0ec ZW |
564 | limit = &intel_limits_ironlake_dual_lvds_100m; |
565 | else | |
566 | limit = &intel_limits_ironlake_dual_lvds; | |
567 | } else { | |
1b894b59 | 568 | if (refclk == 100000) |
b91ad0ec ZW |
569 | limit = &intel_limits_ironlake_single_lvds_100m; |
570 | else | |
571 | limit = &intel_limits_ironlake_single_lvds; | |
572 | } | |
c6bb3538 | 573 | } else |
b91ad0ec | 574 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
575 | |
576 | return limit; | |
577 | } | |
578 | ||
a93e255f ACO |
579 | static const intel_limit_t * |
580 | intel_g4x_limit(struct intel_crtc_state *crtc_state) | |
044c7c41 | 581 | { |
a93e255f | 582 | struct drm_device *dev = crtc_state->base.crtc->dev; |
044c7c41 ML |
583 | const intel_limit_t *limit; |
584 | ||
a93e255f | 585 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 586 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 587 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 588 | else |
e4b36699 | 589 | limit = &intel_limits_g4x_single_channel_lvds; |
a93e255f ACO |
590 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || |
591 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 592 | limit = &intel_limits_g4x_hdmi; |
a93e255f | 593 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 594 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 595 | } else /* The option is for other outputs */ |
e4b36699 | 596 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
597 | |
598 | return limit; | |
599 | } | |
600 | ||
a93e255f ACO |
601 | static const intel_limit_t * |
602 | intel_limit(struct intel_crtc_state *crtc_state, int refclk) | |
79e53945 | 603 | { |
a93e255f | 604 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 JB |
605 | const intel_limit_t *limit; |
606 | ||
5ab7b0b7 ID |
607 | if (IS_BROXTON(dev)) |
608 | limit = &intel_limits_bxt; | |
609 | else if (HAS_PCH_SPLIT(dev)) | |
a93e255f | 610 | limit = intel_ironlake_limit(crtc_state, refclk); |
2c07245f | 611 | else if (IS_G4X(dev)) { |
a93e255f | 612 | limit = intel_g4x_limit(crtc_state); |
f2b115e6 | 613 | } else if (IS_PINEVIEW(dev)) { |
a93e255f | 614 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 615 | limit = &intel_limits_pineview_lvds; |
2177832f | 616 | else |
f2b115e6 | 617 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
618 | } else if (IS_CHERRYVIEW(dev)) { |
619 | limit = &intel_limits_chv; | |
a0c4da24 | 620 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 621 | limit = &intel_limits_vlv; |
a6c45cf0 | 622 | } else if (!IS_GEN2(dev)) { |
a93e255f | 623 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
624 | limit = &intel_limits_i9xx_lvds; |
625 | else | |
626 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 627 | } else { |
a93e255f | 628 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
e4b36699 | 629 | limit = &intel_limits_i8xx_lvds; |
a93e255f | 630 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
e4b36699 | 631 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
632 | else |
633 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
634 | } |
635 | return limit; | |
636 | } | |
637 | ||
dccbea3b ID |
638 | /* |
639 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
640 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
641 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
642 | * The helpers' return value is the rate of the clock that is fed to the | |
643 | * display engine's pipe which can be the above fast dot clock rate or a | |
644 | * divided-down version of it. | |
645 | */ | |
f2b115e6 | 646 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
dccbea3b | 647 | static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock) |
79e53945 | 648 | { |
2177832f SL |
649 | clock->m = clock->m2 + 2; |
650 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 651 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 652 | return 0; |
fb03ac01 VS |
653 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
654 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
655 | |
656 | return clock->dot; | |
2177832f SL |
657 | } |
658 | ||
7429e9d4 DV |
659 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
660 | { | |
661 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
662 | } | |
663 | ||
dccbea3b | 664 | static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock) |
2177832f | 665 | { |
7429e9d4 | 666 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 667 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 668 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 669 | return 0; |
fb03ac01 VS |
670 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
671 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
672 | |
673 | return clock->dot; | |
79e53945 JB |
674 | } |
675 | ||
dccbea3b | 676 | static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock) |
589eca67 ID |
677 | { |
678 | clock->m = clock->m1 * clock->m2; | |
679 | clock->p = clock->p1 * clock->p2; | |
680 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 681 | return 0; |
589eca67 ID |
682 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
683 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
684 | |
685 | return clock->dot / 5; | |
589eca67 ID |
686 | } |
687 | ||
dccbea3b | 688 | int chv_calc_dpll_params(int refclk, intel_clock_t *clock) |
ef9348c8 CML |
689 | { |
690 | clock->m = clock->m1 * clock->m2; | |
691 | clock->p = clock->p1 * clock->p2; | |
692 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 693 | return 0; |
ef9348c8 CML |
694 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
695 | clock->n << 22); | |
696 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
697 | |
698 | return clock->dot / 5; | |
ef9348c8 CML |
699 | } |
700 | ||
7c04d1d9 | 701 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
702 | /** |
703 | * Returns whether the given set of divisors are valid for a given refclk with | |
704 | * the given connectors. | |
705 | */ | |
706 | ||
1b894b59 CW |
707 | static bool intel_PLL_is_valid(struct drm_device *dev, |
708 | const intel_limit_t *limit, | |
709 | const intel_clock_t *clock) | |
79e53945 | 710 | { |
f01b7962 VS |
711 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
712 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 713 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 714 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 715 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 716 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 717 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 718 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 719 | |
666a4537 WB |
720 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && |
721 | !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) | |
f01b7962 VS |
722 | if (clock->m1 <= clock->m2) |
723 | INTELPllInvalid("m1 <= m2\n"); | |
724 | ||
666a4537 | 725 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
726 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
727 | INTELPllInvalid("p out of range\n"); | |
728 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
729 | INTELPllInvalid("m out of range\n"); | |
730 | } | |
731 | ||
79e53945 | 732 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 733 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
734 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
735 | * connector, etc., rather than just a single range. | |
736 | */ | |
737 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 738 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
739 | |
740 | return true; | |
741 | } | |
742 | ||
3b1429d9 VS |
743 | static int |
744 | i9xx_select_p2_div(const intel_limit_t *limit, | |
745 | const struct intel_crtc_state *crtc_state, | |
746 | int target) | |
79e53945 | 747 | { |
3b1429d9 | 748 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 749 | |
a93e255f | 750 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 751 | /* |
a210b028 DV |
752 | * For LVDS just rely on its current settings for dual-channel. |
753 | * We haven't figured out how to reliably set up different | |
754 | * single/dual channel state, if we even can. | |
79e53945 | 755 | */ |
1974cad0 | 756 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 757 | return limit->p2.p2_fast; |
79e53945 | 758 | else |
3b1429d9 | 759 | return limit->p2.p2_slow; |
79e53945 JB |
760 | } else { |
761 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 762 | return limit->p2.p2_slow; |
79e53945 | 763 | else |
3b1429d9 | 764 | return limit->p2.p2_fast; |
79e53945 | 765 | } |
3b1429d9 VS |
766 | } |
767 | ||
768 | static bool | |
769 | i9xx_find_best_dpll(const intel_limit_t *limit, | |
770 | struct intel_crtc_state *crtc_state, | |
771 | int target, int refclk, intel_clock_t *match_clock, | |
772 | intel_clock_t *best_clock) | |
773 | { | |
774 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
775 | intel_clock_t clock; | |
776 | int err = target; | |
79e53945 | 777 | |
0206e353 | 778 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 779 | |
3b1429d9 VS |
780 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
781 | ||
42158660 ZY |
782 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
783 | clock.m1++) { | |
784 | for (clock.m2 = limit->m2.min; | |
785 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 786 | if (clock.m2 >= clock.m1) |
42158660 ZY |
787 | break; |
788 | for (clock.n = limit->n.min; | |
789 | clock.n <= limit->n.max; clock.n++) { | |
790 | for (clock.p1 = limit->p1.min; | |
791 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
792 | int this_err; |
793 | ||
dccbea3b | 794 | i9xx_calc_dpll_params(refclk, &clock); |
ac58c3f0 DV |
795 | if (!intel_PLL_is_valid(dev, limit, |
796 | &clock)) | |
797 | continue; | |
798 | if (match_clock && | |
799 | clock.p != match_clock->p) | |
800 | continue; | |
801 | ||
802 | this_err = abs(clock.dot - target); | |
803 | if (this_err < err) { | |
804 | *best_clock = clock; | |
805 | err = this_err; | |
806 | } | |
807 | } | |
808 | } | |
809 | } | |
810 | } | |
811 | ||
812 | return (err != target); | |
813 | } | |
814 | ||
815 | static bool | |
a93e255f ACO |
816 | pnv_find_best_dpll(const intel_limit_t *limit, |
817 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
818 | int target, int refclk, intel_clock_t *match_clock, |
819 | intel_clock_t *best_clock) | |
79e53945 | 820 | { |
3b1429d9 | 821 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 822 | intel_clock_t clock; |
79e53945 JB |
823 | int err = target; |
824 | ||
0206e353 | 825 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 826 | |
3b1429d9 VS |
827 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
828 | ||
42158660 ZY |
829 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
830 | clock.m1++) { | |
831 | for (clock.m2 = limit->m2.min; | |
832 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
833 | for (clock.n = limit->n.min; |
834 | clock.n <= limit->n.max; clock.n++) { | |
835 | for (clock.p1 = limit->p1.min; | |
836 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
837 | int this_err; |
838 | ||
dccbea3b | 839 | pnv_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
840 | if (!intel_PLL_is_valid(dev, limit, |
841 | &clock)) | |
79e53945 | 842 | continue; |
cec2f356 SP |
843 | if (match_clock && |
844 | clock.p != match_clock->p) | |
845 | continue; | |
79e53945 JB |
846 | |
847 | this_err = abs(clock.dot - target); | |
848 | if (this_err < err) { | |
849 | *best_clock = clock; | |
850 | err = this_err; | |
851 | } | |
852 | } | |
853 | } | |
854 | } | |
855 | } | |
856 | ||
857 | return (err != target); | |
858 | } | |
859 | ||
d4906093 | 860 | static bool |
a93e255f ACO |
861 | g4x_find_best_dpll(const intel_limit_t *limit, |
862 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
863 | int target, int refclk, intel_clock_t *match_clock, |
864 | intel_clock_t *best_clock) | |
d4906093 | 865 | { |
3b1429d9 | 866 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d4906093 ML |
867 | intel_clock_t clock; |
868 | int max_n; | |
3b1429d9 | 869 | bool found = false; |
6ba770dc AJ |
870 | /* approximately equals target * 0.00585 */ |
871 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
872 | |
873 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
874 | |
875 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
876 | ||
d4906093 | 877 | max_n = limit->n.max; |
f77f13e2 | 878 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 879 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 880 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
881 | for (clock.m1 = limit->m1.max; |
882 | clock.m1 >= limit->m1.min; clock.m1--) { | |
883 | for (clock.m2 = limit->m2.max; | |
884 | clock.m2 >= limit->m2.min; clock.m2--) { | |
885 | for (clock.p1 = limit->p1.max; | |
886 | clock.p1 >= limit->p1.min; clock.p1--) { | |
887 | int this_err; | |
888 | ||
dccbea3b | 889 | i9xx_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
890 | if (!intel_PLL_is_valid(dev, limit, |
891 | &clock)) | |
d4906093 | 892 | continue; |
1b894b59 CW |
893 | |
894 | this_err = abs(clock.dot - target); | |
d4906093 ML |
895 | if (this_err < err_most) { |
896 | *best_clock = clock; | |
897 | err_most = this_err; | |
898 | max_n = clock.n; | |
899 | found = true; | |
900 | } | |
901 | } | |
902 | } | |
903 | } | |
904 | } | |
2c07245f ZW |
905 | return found; |
906 | } | |
907 | ||
d5dd62bd ID |
908 | /* |
909 | * Check if the calculated PLL configuration is more optimal compared to the | |
910 | * best configuration and error found so far. Return the calculated error. | |
911 | */ | |
912 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
913 | const intel_clock_t *calculated_clock, | |
914 | const intel_clock_t *best_clock, | |
915 | unsigned int best_error_ppm, | |
916 | unsigned int *error_ppm) | |
917 | { | |
9ca3ba01 ID |
918 | /* |
919 | * For CHV ignore the error and consider only the P value. | |
920 | * Prefer a bigger P value based on HW requirements. | |
921 | */ | |
922 | if (IS_CHERRYVIEW(dev)) { | |
923 | *error_ppm = 0; | |
924 | ||
925 | return calculated_clock->p > best_clock->p; | |
926 | } | |
927 | ||
24be4e46 ID |
928 | if (WARN_ON_ONCE(!target_freq)) |
929 | return false; | |
930 | ||
d5dd62bd ID |
931 | *error_ppm = div_u64(1000000ULL * |
932 | abs(target_freq - calculated_clock->dot), | |
933 | target_freq); | |
934 | /* | |
935 | * Prefer a better P value over a better (smaller) error if the error | |
936 | * is small. Ensure this preference for future configurations too by | |
937 | * setting the error to 0. | |
938 | */ | |
939 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
940 | *error_ppm = 0; | |
941 | ||
942 | return true; | |
943 | } | |
944 | ||
945 | return *error_ppm + 10 < best_error_ppm; | |
946 | } | |
947 | ||
a0c4da24 | 948 | static bool |
a93e255f ACO |
949 | vlv_find_best_dpll(const intel_limit_t *limit, |
950 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
951 | int target, int refclk, intel_clock_t *match_clock, |
952 | intel_clock_t *best_clock) | |
a0c4da24 | 953 | { |
a93e255f | 954 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 955 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 956 | intel_clock_t clock; |
69e4f900 | 957 | unsigned int bestppm = 1000000; |
27e639bf VS |
958 | /* min update 19.2 MHz */ |
959 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 960 | bool found = false; |
a0c4da24 | 961 | |
6b4bf1c4 VS |
962 | target *= 5; /* fast clock */ |
963 | ||
964 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
965 | |
966 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 967 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 968 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 969 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 970 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 971 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 972 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 973 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 974 | unsigned int ppm; |
69e4f900 | 975 | |
6b4bf1c4 VS |
976 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
977 | refclk * clock.m1); | |
978 | ||
dccbea3b | 979 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 980 | |
f01b7962 VS |
981 | if (!intel_PLL_is_valid(dev, limit, |
982 | &clock)) | |
43b0ac53 VS |
983 | continue; |
984 | ||
d5dd62bd ID |
985 | if (!vlv_PLL_is_optimal(dev, target, |
986 | &clock, | |
987 | best_clock, | |
988 | bestppm, &ppm)) | |
989 | continue; | |
6b4bf1c4 | 990 | |
d5dd62bd ID |
991 | *best_clock = clock; |
992 | bestppm = ppm; | |
993 | found = true; | |
a0c4da24 JB |
994 | } |
995 | } | |
996 | } | |
997 | } | |
a0c4da24 | 998 | |
49e497ef | 999 | return found; |
a0c4da24 | 1000 | } |
a4fc5ed6 | 1001 | |
ef9348c8 | 1002 | static bool |
a93e255f ACO |
1003 | chv_find_best_dpll(const intel_limit_t *limit, |
1004 | struct intel_crtc_state *crtc_state, | |
ef9348c8 CML |
1005 | int target, int refclk, intel_clock_t *match_clock, |
1006 | intel_clock_t *best_clock) | |
1007 | { | |
a93e255f | 1008 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 1009 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 1010 | unsigned int best_error_ppm; |
ef9348c8 CML |
1011 | intel_clock_t clock; |
1012 | uint64_t m2; | |
1013 | int found = false; | |
1014 | ||
1015 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 1016 | best_error_ppm = 1000000; |
ef9348c8 CML |
1017 | |
1018 | /* | |
1019 | * Based on hardware doc, the n always set to 1, and m1 always | |
1020 | * set to 2. If requires to support 200Mhz refclk, we need to | |
1021 | * revisit this because n may not 1 anymore. | |
1022 | */ | |
1023 | clock.n = 1, clock.m1 = 2; | |
1024 | target *= 5; /* fast clock */ | |
1025 | ||
1026 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
1027 | for (clock.p2 = limit->p2.p2_fast; | |
1028 | clock.p2 >= limit->p2.p2_slow; | |
1029 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 1030 | unsigned int error_ppm; |
ef9348c8 CML |
1031 | |
1032 | clock.p = clock.p1 * clock.p2; | |
1033 | ||
1034 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
1035 | clock.n) << 22, refclk * clock.m1); | |
1036 | ||
1037 | if (m2 > INT_MAX/clock.m1) | |
1038 | continue; | |
1039 | ||
1040 | clock.m2 = m2; | |
1041 | ||
dccbea3b | 1042 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 CML |
1043 | |
1044 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
1045 | continue; | |
1046 | ||
9ca3ba01 ID |
1047 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
1048 | best_error_ppm, &error_ppm)) | |
1049 | continue; | |
1050 | ||
1051 | *best_clock = clock; | |
1052 | best_error_ppm = error_ppm; | |
1053 | found = true; | |
ef9348c8 CML |
1054 | } |
1055 | } | |
1056 | ||
1057 | return found; | |
1058 | } | |
1059 | ||
5ab7b0b7 ID |
1060 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
1061 | intel_clock_t *best_clock) | |
1062 | { | |
1063 | int refclk = i9xx_get_refclk(crtc_state, 0); | |
1064 | ||
1065 | return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state, | |
1066 | target_clock, refclk, NULL, best_clock); | |
1067 | } | |
1068 | ||
20ddf665 VS |
1069 | bool intel_crtc_active(struct drm_crtc *crtc) |
1070 | { | |
1071 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1072 | ||
1073 | /* Be paranoid as we can arrive here with only partial | |
1074 | * state retrieved from the hardware during setup. | |
1075 | * | |
241bfc38 | 1076 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1077 | * as Haswell has gained clock readout/fastboot support. |
1078 | * | |
66e514c1 | 1079 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1080 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1081 | * |
1082 | * FIXME: The intel_crtc->active here should be switched to | |
1083 | * crtc->state->active once we have proper CRTC states wired up | |
1084 | * for atomic. | |
20ddf665 | 1085 | */ |
c3d1f436 | 1086 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1087 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1088 | } |
1089 | ||
a5c961d1 PZ |
1090 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1091 | enum pipe pipe) | |
1092 | { | |
1093 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1094 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1095 | ||
6e3c9717 | 1096 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1097 | } |
1098 | ||
fbf49ea2 VS |
1099 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1100 | { | |
1101 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1102 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1103 | u32 line1, line2; |
1104 | u32 line_mask; | |
1105 | ||
1106 | if (IS_GEN2(dev)) | |
1107 | line_mask = DSL_LINEMASK_GEN2; | |
1108 | else | |
1109 | line_mask = DSL_LINEMASK_GEN3; | |
1110 | ||
1111 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1112 | msleep(5); |
fbf49ea2 VS |
1113 | line2 = I915_READ(reg) & line_mask; |
1114 | ||
1115 | return line1 == line2; | |
1116 | } | |
1117 | ||
ab7ad7f6 KP |
1118 | /* |
1119 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1120 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1121 | * |
1122 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1123 | * spinning on the vblank interrupt status bit, since we won't actually | |
1124 | * see an interrupt when the pipe is disabled. | |
1125 | * | |
ab7ad7f6 KP |
1126 | * On Gen4 and above: |
1127 | * wait for the pipe register state bit to turn off | |
1128 | * | |
1129 | * Otherwise: | |
1130 | * wait for the display line value to settle (it usually | |
1131 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1132 | * |
9d0498a2 | 1133 | */ |
575f7ab7 | 1134 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1135 | { |
575f7ab7 | 1136 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1137 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1138 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1139 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1140 | |
1141 | if (INTEL_INFO(dev)->gen >= 4) { | |
f0f59a00 | 1142 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1143 | |
1144 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1145 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1146 | 100)) | |
284637d9 | 1147 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1148 | } else { |
ab7ad7f6 | 1149 | /* Wait for the display line to settle */ |
fbf49ea2 | 1150 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1151 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1152 | } |
79e53945 JB |
1153 | } |
1154 | ||
b24e7179 JB |
1155 | static const char *state_string(bool enabled) |
1156 | { | |
1157 | return enabled ? "on" : "off"; | |
1158 | } | |
1159 | ||
1160 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1161 | void assert_pll(struct drm_i915_private *dev_priv, |
1162 | enum pipe pipe, bool state) | |
b24e7179 | 1163 | { |
b24e7179 JB |
1164 | u32 val; |
1165 | bool cur_state; | |
1166 | ||
649636ef | 1167 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1168 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1169 | I915_STATE_WARN(cur_state != state, |
b24e7179 JB |
1170 | "PLL state assertion failure (expected %s, current %s)\n", |
1171 | state_string(state), state_string(cur_state)); | |
1172 | } | |
b24e7179 | 1173 | |
23538ef1 JN |
1174 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1175 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1176 | { | |
1177 | u32 val; | |
1178 | bool cur_state; | |
1179 | ||
a580516d | 1180 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1181 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1182 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1183 | |
1184 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1185 | I915_STATE_WARN(cur_state != state, |
23538ef1 JN |
1186 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
1187 | state_string(state), state_string(cur_state)); | |
1188 | } | |
1189 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1190 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1191 | ||
55607e8a | 1192 | struct intel_shared_dpll * |
e2b78267 DV |
1193 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1194 | { | |
1195 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1196 | ||
6e3c9717 | 1197 | if (crtc->config->shared_dpll < 0) |
e2b78267 DV |
1198 | return NULL; |
1199 | ||
6e3c9717 | 1200 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
e2b78267 DV |
1201 | } |
1202 | ||
040484af | 1203 | /* For ILK+ */ |
55607e8a DV |
1204 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1205 | struct intel_shared_dpll *pll, | |
1206 | bool state) | |
040484af | 1207 | { |
040484af | 1208 | bool cur_state; |
5358901f | 1209 | struct intel_dpll_hw_state hw_state; |
040484af | 1210 | |
92b27b08 | 1211 | if (WARN (!pll, |
46edb027 | 1212 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1213 | return; |
ee7b9f93 | 1214 | |
5358901f | 1215 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
e2c719b7 | 1216 | I915_STATE_WARN(cur_state != state, |
5358901f DV |
1217 | "%s assertion failure (expected %s, current %s)\n", |
1218 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1219 | } |
040484af JB |
1220 | |
1221 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1222 | enum pipe pipe, bool state) | |
1223 | { | |
040484af | 1224 | bool cur_state; |
ad80a810 PZ |
1225 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1226 | pipe); | |
040484af | 1227 | |
affa9354 PZ |
1228 | if (HAS_DDI(dev_priv->dev)) { |
1229 | /* DDI does not have a specific FDI_TX register */ | |
649636ef | 1230 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1231 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1232 | } else { |
649636ef | 1233 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1234 | cur_state = !!(val & FDI_TX_ENABLE); |
1235 | } | |
e2c719b7 | 1236 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1237 | "FDI TX state assertion failure (expected %s, current %s)\n", |
1238 | state_string(state), state_string(cur_state)); | |
1239 | } | |
1240 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1241 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1242 | ||
1243 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1244 | enum pipe pipe, bool state) | |
1245 | { | |
040484af JB |
1246 | u32 val; |
1247 | bool cur_state; | |
1248 | ||
649636ef | 1249 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1250 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1251 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1252 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1253 | state_string(state), state_string(cur_state)); | |
1254 | } | |
1255 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1256 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1257 | ||
1258 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1259 | enum pipe pipe) | |
1260 | { | |
040484af JB |
1261 | u32 val; |
1262 | ||
1263 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1264 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1265 | return; |
1266 | ||
bf507ef7 | 1267 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1268 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1269 | return; |
1270 | ||
649636ef | 1271 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1272 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1273 | } |
1274 | ||
55607e8a DV |
1275 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1276 | enum pipe pipe, bool state) | |
040484af | 1277 | { |
040484af | 1278 | u32 val; |
55607e8a | 1279 | bool cur_state; |
040484af | 1280 | |
649636ef | 1281 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1282 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1283 | I915_STATE_WARN(cur_state != state, |
55607e8a DV |
1284 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
1285 | state_string(state), state_string(cur_state)); | |
040484af JB |
1286 | } |
1287 | ||
b680c37a DV |
1288 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1289 | enum pipe pipe) | |
ea0760cf | 1290 | { |
bedd4dba | 1291 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 | 1292 | i915_reg_t pp_reg; |
ea0760cf JB |
1293 | u32 val; |
1294 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1295 | bool locked = true; |
ea0760cf | 1296 | |
bedd4dba JN |
1297 | if (WARN_ON(HAS_DDI(dev))) |
1298 | return; | |
1299 | ||
1300 | if (HAS_PCH_SPLIT(dev)) { | |
1301 | u32 port_sel; | |
1302 | ||
ea0760cf | 1303 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1304 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1305 | ||
1306 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1307 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1308 | panel_pipe = PIPE_B; | |
1309 | /* XXX: else fix for eDP */ | |
666a4537 | 1310 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
bedd4dba JN |
1311 | /* presumably write lock depends on pipe, not port select */ |
1312 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1313 | panel_pipe = pipe; | |
ea0760cf JB |
1314 | } else { |
1315 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1316 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1317 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1318 | } |
1319 | ||
1320 | val = I915_READ(pp_reg); | |
1321 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1322 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1323 | locked = false; |
1324 | ||
e2c719b7 | 1325 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1326 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1327 | pipe_name(pipe)); |
ea0760cf JB |
1328 | } |
1329 | ||
93ce0ba6 JN |
1330 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1331 | enum pipe pipe, bool state) | |
1332 | { | |
1333 | struct drm_device *dev = dev_priv->dev; | |
1334 | bool cur_state; | |
1335 | ||
d9d82081 | 1336 | if (IS_845G(dev) || IS_I865G(dev)) |
0b87c24e | 1337 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1338 | else |
5efb3e28 | 1339 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1340 | |
e2c719b7 | 1341 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 JN |
1342 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
1343 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1344 | } | |
1345 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1346 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1347 | ||
b840d907 JB |
1348 | void assert_pipe(struct drm_i915_private *dev_priv, |
1349 | enum pipe pipe, bool state) | |
b24e7179 | 1350 | { |
63d7bbe9 | 1351 | bool cur_state; |
702e7a56 PZ |
1352 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1353 | pipe); | |
b24e7179 | 1354 | |
b6b5d049 VS |
1355 | /* if we need the pipe quirk it must be always on */ |
1356 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1357 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1358 | state = true; |
1359 | ||
f458ebbc | 1360 | if (!intel_display_power_is_enabled(dev_priv, |
b97186f0 | 1361 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1362 | cur_state = false; |
1363 | } else { | |
649636ef | 1364 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 PZ |
1365 | cur_state = !!(val & PIPECONF_ENABLE); |
1366 | } | |
1367 | ||
e2c719b7 | 1368 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1369 | "pipe %c assertion failure (expected %s, current %s)\n", |
9db4a9c7 | 1370 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1371 | } |
1372 | ||
931872fc CW |
1373 | static void assert_plane(struct drm_i915_private *dev_priv, |
1374 | enum plane plane, bool state) | |
b24e7179 | 1375 | { |
b24e7179 | 1376 | u32 val; |
931872fc | 1377 | bool cur_state; |
b24e7179 | 1378 | |
649636ef | 1379 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1380 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1381 | I915_STATE_WARN(cur_state != state, |
931872fc CW |
1382 | "plane %c assertion failure (expected %s, current %s)\n", |
1383 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1384 | } |
1385 | ||
931872fc CW |
1386 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1387 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1388 | ||
b24e7179 JB |
1389 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1390 | enum pipe pipe) | |
1391 | { | |
653e1026 | 1392 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1393 | int i; |
b24e7179 | 1394 | |
653e1026 VS |
1395 | /* Primary planes are fixed to pipes on gen4+ */ |
1396 | if (INTEL_INFO(dev)->gen >= 4) { | |
649636ef | 1397 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1398 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1399 | "plane %c assertion failure, should be disabled but not\n", |
1400 | plane_name(pipe)); | |
19ec1358 | 1401 | return; |
28c05794 | 1402 | } |
19ec1358 | 1403 | |
b24e7179 | 1404 | /* Need to check both planes against the pipe */ |
055e393f | 1405 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1406 | u32 val = I915_READ(DSPCNTR(i)); |
1407 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1408 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1409 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1410 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1411 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1412 | } |
1413 | } | |
1414 | ||
19332d7a JB |
1415 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1416 | enum pipe pipe) | |
1417 | { | |
20674eef | 1418 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1419 | int sprite; |
19332d7a | 1420 | |
7feb8b88 | 1421 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1422 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1423 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1424 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1425 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1426 | sprite, pipe_name(pipe)); | |
1427 | } | |
666a4537 | 1428 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
3bdcfc0c | 1429 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1430 | u32 val = I915_READ(SPCNTR(pipe, sprite)); |
e2c719b7 | 1431 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1432 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1433 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1434 | } |
1435 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
649636ef | 1436 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1437 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1438 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1439 | plane_name(pipe), pipe_name(pipe)); |
1440 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
649636ef | 1441 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1442 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1443 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1444 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1445 | } |
1446 | } | |
1447 | ||
08c71e5e VS |
1448 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1449 | { | |
e2c719b7 | 1450 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1451 | drm_crtc_vblank_put(crtc); |
1452 | } | |
1453 | ||
89eff4be | 1454 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1455 | { |
1456 | u32 val; | |
1457 | bool enabled; | |
1458 | ||
e2c719b7 | 1459 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1460 | |
92f2584a JB |
1461 | val = I915_READ(PCH_DREF_CONTROL); |
1462 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1463 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
e2c719b7 | 1464 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
92f2584a JB |
1465 | } |
1466 | ||
ab9412ba DV |
1467 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1468 | enum pipe pipe) | |
92f2584a | 1469 | { |
92f2584a JB |
1470 | u32 val; |
1471 | bool enabled; | |
1472 | ||
649636ef | 1473 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1474 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1475 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1476 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1477 | pipe_name(pipe)); | |
92f2584a JB |
1478 | } |
1479 | ||
4e634389 KP |
1480 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1481 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1482 | { |
1483 | if ((val & DP_PORT_EN) == 0) | |
1484 | return false; | |
1485 | ||
1486 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
f0f59a00 | 1487 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1488 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1489 | return false; | |
44f37d1f CML |
1490 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1491 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1492 | return false; | |
f0575e92 KP |
1493 | } else { |
1494 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1495 | return false; | |
1496 | } | |
1497 | return true; | |
1498 | } | |
1499 | ||
1519b995 KP |
1500 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1501 | enum pipe pipe, u32 val) | |
1502 | { | |
dc0fa718 | 1503 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1504 | return false; |
1505 | ||
1506 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1507 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1508 | return false; |
44f37d1f CML |
1509 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1510 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1511 | return false; | |
1519b995 | 1512 | } else { |
dc0fa718 | 1513 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1514 | return false; |
1515 | } | |
1516 | return true; | |
1517 | } | |
1518 | ||
1519 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1520 | enum pipe pipe, u32 val) | |
1521 | { | |
1522 | if ((val & LVDS_PORT_EN) == 0) | |
1523 | return false; | |
1524 | ||
1525 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1526 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1527 | return false; | |
1528 | } else { | |
1529 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1530 | return false; | |
1531 | } | |
1532 | return true; | |
1533 | } | |
1534 | ||
1535 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1536 | enum pipe pipe, u32 val) | |
1537 | { | |
1538 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1539 | return false; | |
1540 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1541 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1542 | return false; | |
1543 | } else { | |
1544 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1545 | return false; | |
1546 | } | |
1547 | return true; | |
1548 | } | |
1549 | ||
291906f1 | 1550 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1551 | enum pipe pipe, i915_reg_t reg, |
1552 | u32 port_sel) | |
291906f1 | 1553 | { |
47a05eca | 1554 | u32 val = I915_READ(reg); |
e2c719b7 | 1555 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1556 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1557 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1558 | |
e2c719b7 | 1559 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1560 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1561 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1562 | } |
1563 | ||
1564 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1565 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1566 | { |
47a05eca | 1567 | u32 val = I915_READ(reg); |
e2c719b7 | 1568 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1569 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1570 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1571 | |
e2c719b7 | 1572 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1573 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1574 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1575 | } |
1576 | ||
1577 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1578 | enum pipe pipe) | |
1579 | { | |
291906f1 | 1580 | u32 val; |
291906f1 | 1581 | |
f0575e92 KP |
1582 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1583 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1584 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1585 | |
649636ef | 1586 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1587 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1588 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1589 | pipe_name(pipe)); |
291906f1 | 1590 | |
649636ef | 1591 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1592 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1593 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1594 | pipe_name(pipe)); |
291906f1 | 1595 | |
e2debe91 PZ |
1596 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1597 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1598 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1599 | } |
1600 | ||
d288f65f | 1601 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1602 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1603 | { |
426115cf DV |
1604 | struct drm_device *dev = crtc->base.dev; |
1605 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1606 | i915_reg_t reg = DPLL(crtc->pipe); |
d288f65f | 1607 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1608 | |
426115cf | 1609 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 | 1610 | |
87442f73 | 1611 | /* PLL is protected by panel, make sure we can write it */ |
6a9e7363 | 1612 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1613 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1614 | |
426115cf DV |
1615 | I915_WRITE(reg, dpll); |
1616 | POSTING_READ(reg); | |
1617 | udelay(150); | |
1618 | ||
1619 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1620 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1621 | ||
d288f65f | 1622 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1623 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1624 | |
1625 | /* We do this three times for luck */ | |
426115cf | 1626 | I915_WRITE(reg, dpll); |
87442f73 DV |
1627 | POSTING_READ(reg); |
1628 | udelay(150); /* wait for warmup */ | |
426115cf | 1629 | I915_WRITE(reg, dpll); |
87442f73 DV |
1630 | POSTING_READ(reg); |
1631 | udelay(150); /* wait for warmup */ | |
426115cf | 1632 | I915_WRITE(reg, dpll); |
87442f73 DV |
1633 | POSTING_READ(reg); |
1634 | udelay(150); /* wait for warmup */ | |
1635 | } | |
1636 | ||
d288f65f | 1637 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1638 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1639 | { |
1640 | struct drm_device *dev = crtc->base.dev; | |
1641 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1642 | int pipe = crtc->pipe; | |
1643 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1644 | u32 tmp; |
1645 | ||
1646 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1647 | ||
a580516d | 1648 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1649 | |
1650 | /* Enable back the 10bit clock to display controller */ | |
1651 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1652 | tmp |= DPIO_DCLKP_EN; | |
1653 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1654 | ||
54433e91 VS |
1655 | mutex_unlock(&dev_priv->sb_lock); |
1656 | ||
9d556c99 CML |
1657 | /* |
1658 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1659 | */ | |
1660 | udelay(1); | |
1661 | ||
1662 | /* Enable PLL */ | |
d288f65f | 1663 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1664 | |
1665 | /* Check PLL is locked */ | |
a11b0703 | 1666 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1667 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1668 | ||
a11b0703 | 1669 | /* not sure when this should be written */ |
d288f65f | 1670 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 | 1671 | POSTING_READ(DPLL_MD(pipe)); |
9d556c99 CML |
1672 | } |
1673 | ||
1c4e0274 VS |
1674 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1675 | { | |
1676 | struct intel_crtc *crtc; | |
1677 | int count = 0; | |
1678 | ||
1679 | for_each_intel_crtc(dev, crtc) | |
3538b9df | 1680 | count += crtc->base.state->active && |
409ee761 | 1681 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1682 | |
1683 | return count; | |
1684 | } | |
1685 | ||
66e3d5c0 | 1686 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1687 | { |
66e3d5c0 DV |
1688 | struct drm_device *dev = crtc->base.dev; |
1689 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1690 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1691 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1692 | |
66e3d5c0 | 1693 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1694 | |
63d7bbe9 | 1695 | /* No really, not for ILK+ */ |
3d13ef2e | 1696 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1697 | |
1698 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1699 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1700 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1701 | |
1c4e0274 VS |
1702 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1703 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1704 | /* | |
1705 | * It appears to be important that we don't enable this | |
1706 | * for the current pipe before otherwise configuring the | |
1707 | * PLL. No idea how this should be handled if multiple | |
1708 | * DVO outputs are enabled simultaneosly. | |
1709 | */ | |
1710 | dpll |= DPLL_DVO_2X_MODE; | |
1711 | I915_WRITE(DPLL(!crtc->pipe), | |
1712 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1713 | } | |
66e3d5c0 | 1714 | |
c2b63374 VS |
1715 | /* |
1716 | * Apparently we need to have VGA mode enabled prior to changing | |
1717 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1718 | * dividers, even though the register value does change. | |
1719 | */ | |
1720 | I915_WRITE(reg, 0); | |
1721 | ||
8e7a65aa VS |
1722 | I915_WRITE(reg, dpll); |
1723 | ||
66e3d5c0 DV |
1724 | /* Wait for the clocks to stabilize. */ |
1725 | POSTING_READ(reg); | |
1726 | udelay(150); | |
1727 | ||
1728 | if (INTEL_INFO(dev)->gen >= 4) { | |
1729 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1730 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1731 | } else { |
1732 | /* The pixel multiplier can only be updated once the | |
1733 | * DPLL is enabled and the clocks are stable. | |
1734 | * | |
1735 | * So write it again. | |
1736 | */ | |
1737 | I915_WRITE(reg, dpll); | |
1738 | } | |
63d7bbe9 JB |
1739 | |
1740 | /* We do this three times for luck */ | |
66e3d5c0 | 1741 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1742 | POSTING_READ(reg); |
1743 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1744 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1745 | POSTING_READ(reg); |
1746 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1747 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1748 | POSTING_READ(reg); |
1749 | udelay(150); /* wait for warmup */ | |
1750 | } | |
1751 | ||
1752 | /** | |
50b44a44 | 1753 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1754 | * @dev_priv: i915 private structure |
1755 | * @pipe: pipe PLL to disable | |
1756 | * | |
1757 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1758 | * | |
1759 | * Note! This is for pre-ILK only. | |
1760 | */ | |
1c4e0274 | 1761 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1762 | { |
1c4e0274 VS |
1763 | struct drm_device *dev = crtc->base.dev; |
1764 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1765 | enum pipe pipe = crtc->pipe; | |
1766 | ||
1767 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1768 | if (IS_I830(dev) && | |
409ee761 | 1769 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
3538b9df | 1770 | !intel_num_dvo_pipes(dev)) { |
1c4e0274 VS |
1771 | I915_WRITE(DPLL(PIPE_B), |
1772 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1773 | I915_WRITE(DPLL(PIPE_A), | |
1774 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1775 | } | |
1776 | ||
b6b5d049 VS |
1777 | /* Don't disable pipe or pipe PLLs if needed */ |
1778 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1779 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1780 | return; |
1781 | ||
1782 | /* Make sure the pipe isn't still relying on us */ | |
1783 | assert_pipe_disabled(dev_priv, pipe); | |
1784 | ||
b8afb911 | 1785 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1786 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1787 | } |
1788 | ||
f6071166 JB |
1789 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1790 | { | |
b8afb911 | 1791 | u32 val; |
f6071166 JB |
1792 | |
1793 | /* Make sure the pipe isn't still relying on us */ | |
1794 | assert_pipe_disabled(dev_priv, pipe); | |
1795 | ||
e5cbfbfb ID |
1796 | /* |
1797 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1798 | * The latter is needed for VGA hotplug / manual detection. | |
1799 | */ | |
b8afb911 | 1800 | val = DPLL_VGA_MODE_DIS; |
f6071166 | 1801 | if (pipe == PIPE_B) |
60bfe44f | 1802 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV; |
f6071166 JB |
1803 | I915_WRITE(DPLL(pipe), val); |
1804 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1805 | |
1806 | } | |
1807 | ||
1808 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1809 | { | |
d752048d | 1810 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1811 | u32 val; |
1812 | ||
a11b0703 VS |
1813 | /* Make sure the pipe isn't still relying on us */ |
1814 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1815 | |
a11b0703 | 1816 | /* Set PLL en = 0 */ |
60bfe44f VS |
1817 | val = DPLL_SSC_REF_CLK_CHV | |
1818 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1819 | if (pipe != PIPE_A) |
1820 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1821 | I915_WRITE(DPLL(pipe), val); | |
1822 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1823 | |
a580516d | 1824 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1825 | |
1826 | /* Disable 10bit clock to display controller */ | |
1827 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1828 | val &= ~DPIO_DCLKP_EN; | |
1829 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1830 | ||
a580516d | 1831 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1832 | } |
1833 | ||
e4607fcf | 1834 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1835 | struct intel_digital_port *dport, |
1836 | unsigned int expected_mask) | |
89b667f8 JB |
1837 | { |
1838 | u32 port_mask; | |
f0f59a00 | 1839 | i915_reg_t dpll_reg; |
89b667f8 | 1840 | |
e4607fcf CML |
1841 | switch (dport->port) { |
1842 | case PORT_B: | |
89b667f8 | 1843 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1844 | dpll_reg = DPLL(0); |
e4607fcf CML |
1845 | break; |
1846 | case PORT_C: | |
89b667f8 | 1847 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1848 | dpll_reg = DPLL(0); |
9b6de0a1 | 1849 | expected_mask <<= 4; |
00fc31b7 CML |
1850 | break; |
1851 | case PORT_D: | |
1852 | port_mask = DPLL_PORTD_READY_MASK; | |
1853 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1854 | break; |
1855 | default: | |
1856 | BUG(); | |
1857 | } | |
89b667f8 | 1858 | |
9b6de0a1 VS |
1859 | if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) |
1860 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", | |
1861 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1862 | } |
1863 | ||
b14b1055 DV |
1864 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1865 | { | |
1866 | struct drm_device *dev = crtc->base.dev; | |
1867 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1868 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1869 | ||
be19f0ff CW |
1870 | if (WARN_ON(pll == NULL)) |
1871 | return; | |
1872 | ||
3e369b76 | 1873 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1874 | if (pll->active == 0) { |
1875 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1876 | WARN_ON(pll->on); | |
1877 | assert_shared_dpll_disabled(dev_priv, pll); | |
1878 | ||
1879 | pll->mode_set(dev_priv, pll); | |
1880 | } | |
1881 | } | |
1882 | ||
92f2584a | 1883 | /** |
85b3894f | 1884 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1885 | * @dev_priv: i915 private structure |
1886 | * @pipe: pipe PLL to enable | |
1887 | * | |
1888 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1889 | * drives the transcoder clock. | |
1890 | */ | |
85b3894f | 1891 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1892 | { |
3d13ef2e DL |
1893 | struct drm_device *dev = crtc->base.dev; |
1894 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1895 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1896 | |
87a875bb | 1897 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1898 | return; |
1899 | ||
3e369b76 | 1900 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1901 | return; |
ee7b9f93 | 1902 | |
74dd6928 | 1903 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1904 | pll->name, pll->active, pll->on, |
e2b78267 | 1905 | crtc->base.base.id); |
92f2584a | 1906 | |
cdbd2316 DV |
1907 | if (pll->active++) { |
1908 | WARN_ON(!pll->on); | |
e9d6944e | 1909 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1910 | return; |
1911 | } | |
f4a091c7 | 1912 | WARN_ON(pll->on); |
ee7b9f93 | 1913 | |
bd2bb1b9 PZ |
1914 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1915 | ||
46edb027 | 1916 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1917 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1918 | pll->on = true; |
92f2584a JB |
1919 | } |
1920 | ||
f6daaec2 | 1921 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1922 | { |
3d13ef2e DL |
1923 | struct drm_device *dev = crtc->base.dev; |
1924 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1925 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1926 | |
92f2584a | 1927 | /* PCH only available on ILK+ */ |
80aa9312 JB |
1928 | if (INTEL_INFO(dev)->gen < 5) |
1929 | return; | |
1930 | ||
eddfcbcd ML |
1931 | if (pll == NULL) |
1932 | return; | |
92f2584a | 1933 | |
eddfcbcd | 1934 | if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base))))) |
48da64a8 | 1935 | return; |
7a419866 | 1936 | |
46edb027 DV |
1937 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1938 | pll->name, pll->active, pll->on, | |
e2b78267 | 1939 | crtc->base.base.id); |
7a419866 | 1940 | |
48da64a8 | 1941 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1942 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1943 | return; |
1944 | } | |
1945 | ||
e9d6944e | 1946 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1947 | WARN_ON(!pll->on); |
cdbd2316 | 1948 | if (--pll->active) |
7a419866 | 1949 | return; |
ee7b9f93 | 1950 | |
46edb027 | 1951 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1952 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1953 | pll->on = false; |
bd2bb1b9 PZ |
1954 | |
1955 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1956 | } |
1957 | ||
b8a4f404 PZ |
1958 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1959 | enum pipe pipe) | |
040484af | 1960 | { |
23670b32 | 1961 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1962 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1963 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
f0f59a00 VS |
1964 | i915_reg_t reg; |
1965 | uint32_t val, pipeconf_val; | |
040484af JB |
1966 | |
1967 | /* PCH only available on ILK+ */ | |
55522f37 | 1968 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1969 | |
1970 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1971 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1972 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1973 | |
1974 | /* FDI must be feeding us bits for PCH ports */ | |
1975 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1976 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1977 | ||
23670b32 DV |
1978 | if (HAS_PCH_CPT(dev)) { |
1979 | /* Workaround: Set the timing override bit before enabling the | |
1980 | * pch transcoder. */ | |
1981 | reg = TRANS_CHICKEN2(pipe); | |
1982 | val = I915_READ(reg); | |
1983 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1984 | I915_WRITE(reg, val); | |
59c859d6 | 1985 | } |
23670b32 | 1986 | |
ab9412ba | 1987 | reg = PCH_TRANSCONF(pipe); |
040484af | 1988 | val = I915_READ(reg); |
5f7f726d | 1989 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1990 | |
1991 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1992 | /* | |
c5de7c6f VS |
1993 | * Make the BPC in transcoder be consistent with |
1994 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1995 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1996 | */ |
dfd07d72 | 1997 | val &= ~PIPECONF_BPC_MASK; |
c5de7c6f VS |
1998 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) |
1999 | val |= PIPECONF_8BPC; | |
2000 | else | |
2001 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 2002 | } |
5f7f726d PZ |
2003 | |
2004 | val &= ~TRANS_INTERLACE_MASK; | |
2005 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 2006 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 2007 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
2008 | val |= TRANS_LEGACY_INTERLACED_ILK; |
2009 | else | |
2010 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
2011 | else |
2012 | val |= TRANS_PROGRESSIVE; | |
2013 | ||
040484af JB |
2014 | I915_WRITE(reg, val | TRANS_ENABLE); |
2015 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 2016 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
2017 | } |
2018 | ||
8fb033d7 | 2019 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 2020 | enum transcoder cpu_transcoder) |
040484af | 2021 | { |
8fb033d7 | 2022 | u32 val, pipeconf_val; |
8fb033d7 PZ |
2023 | |
2024 | /* PCH only available on ILK+ */ | |
55522f37 | 2025 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 2026 | |
8fb033d7 | 2027 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 2028 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 2029 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 2030 | |
223a6fdf | 2031 | /* Workaround: set timing override bit. */ |
36c0d0cf | 2032 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 2033 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 2034 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 2035 | |
25f3ef11 | 2036 | val = TRANS_ENABLE; |
937bb610 | 2037 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 2038 | |
9a76b1c6 PZ |
2039 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
2040 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 2041 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
2042 | else |
2043 | val |= TRANS_PROGRESSIVE; | |
2044 | ||
ab9412ba DV |
2045 | I915_WRITE(LPT_TRANSCONF, val); |
2046 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 2047 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
2048 | } |
2049 | ||
b8a4f404 PZ |
2050 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
2051 | enum pipe pipe) | |
040484af | 2052 | { |
23670b32 | 2053 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 VS |
2054 | i915_reg_t reg; |
2055 | uint32_t val; | |
040484af JB |
2056 | |
2057 | /* FDI relies on the transcoder */ | |
2058 | assert_fdi_tx_disabled(dev_priv, pipe); | |
2059 | assert_fdi_rx_disabled(dev_priv, pipe); | |
2060 | ||
291906f1 JB |
2061 | /* Ports must be off as well */ |
2062 | assert_pch_ports_disabled(dev_priv, pipe); | |
2063 | ||
ab9412ba | 2064 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
2065 | val = I915_READ(reg); |
2066 | val &= ~TRANS_ENABLE; | |
2067 | I915_WRITE(reg, val); | |
2068 | /* wait for PCH transcoder off, transcoder state */ | |
2069 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 2070 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 2071 | |
c465613b | 2072 | if (HAS_PCH_CPT(dev)) { |
23670b32 DV |
2073 | /* Workaround: Clear the timing override chicken bit again. */ |
2074 | reg = TRANS_CHICKEN2(pipe); | |
2075 | val = I915_READ(reg); | |
2076 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2077 | I915_WRITE(reg, val); | |
2078 | } | |
040484af JB |
2079 | } |
2080 | ||
ab4d966c | 2081 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 2082 | { |
8fb033d7 PZ |
2083 | u32 val; |
2084 | ||
ab9412ba | 2085 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 2086 | val &= ~TRANS_ENABLE; |
ab9412ba | 2087 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 2088 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 2089 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 2090 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
2091 | |
2092 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 2093 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 2094 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 2095 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
2096 | } |
2097 | ||
b24e7179 | 2098 | /** |
309cfea8 | 2099 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2100 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2101 | * |
0372264a | 2102 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2103 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2104 | */ |
e1fdc473 | 2105 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2106 | { |
0372264a PZ |
2107 | struct drm_device *dev = crtc->base.dev; |
2108 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2109 | enum pipe pipe = crtc->pipe; | |
1a70a728 | 2110 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
1a240d4d | 2111 | enum pipe pch_transcoder; |
f0f59a00 | 2112 | i915_reg_t reg; |
b24e7179 JB |
2113 | u32 val; |
2114 | ||
9e2ee2dd VS |
2115 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
2116 | ||
58c6eaa2 | 2117 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2118 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2119 | assert_sprites_disabled(dev_priv, pipe); |
2120 | ||
681e5811 | 2121 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2122 | pch_transcoder = TRANSCODER_A; |
2123 | else | |
2124 | pch_transcoder = pipe; | |
2125 | ||
b24e7179 JB |
2126 | /* |
2127 | * A pipe without a PLL won't actually be able to drive bits from | |
2128 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2129 | * need the check. | |
2130 | */ | |
50360403 | 2131 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) |
a65347ba | 2132 | if (crtc->config->has_dsi_encoder) |
23538ef1 JN |
2133 | assert_dsi_pll_enabled(dev_priv); |
2134 | else | |
2135 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2136 | else { |
6e3c9717 | 2137 | if (crtc->config->has_pch_encoder) { |
040484af | 2138 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2139 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2140 | assert_fdi_tx_pll_enabled(dev_priv, |
2141 | (enum pipe) cpu_transcoder); | |
040484af JB |
2142 | } |
2143 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2144 | } | |
b24e7179 | 2145 | |
702e7a56 | 2146 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2147 | val = I915_READ(reg); |
7ad25d48 | 2148 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2149 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2150 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2151 | return; |
7ad25d48 | 2152 | } |
00d70b15 CW |
2153 | |
2154 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2155 | POSTING_READ(reg); |
b24e7179 JB |
2156 | } |
2157 | ||
2158 | /** | |
309cfea8 | 2159 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2160 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2161 | * |
575f7ab7 VS |
2162 | * Disable the pipe of @crtc, making sure that various hardware |
2163 | * specific requirements are met, if applicable, e.g. plane | |
2164 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2165 | * |
2166 | * Will wait until the pipe has shut down before returning. | |
2167 | */ | |
575f7ab7 | 2168 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2169 | { |
575f7ab7 | 2170 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2171 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2172 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 2173 | i915_reg_t reg; |
b24e7179 JB |
2174 | u32 val; |
2175 | ||
9e2ee2dd VS |
2176 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2177 | ||
b24e7179 JB |
2178 | /* |
2179 | * Make sure planes won't keep trying to pump pixels to us, | |
2180 | * or we might hang the display. | |
2181 | */ | |
2182 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2183 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2184 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2185 | |
702e7a56 | 2186 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2187 | val = I915_READ(reg); |
00d70b15 CW |
2188 | if ((val & PIPECONF_ENABLE) == 0) |
2189 | return; | |
2190 | ||
67adc644 VS |
2191 | /* |
2192 | * Double wide has implications for planes | |
2193 | * so best keep it disabled when not needed. | |
2194 | */ | |
6e3c9717 | 2195 | if (crtc->config->double_wide) |
67adc644 VS |
2196 | val &= ~PIPECONF_DOUBLE_WIDE; |
2197 | ||
2198 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2199 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2200 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2201 | val &= ~PIPECONF_ENABLE; |
2202 | ||
2203 | I915_WRITE(reg, val); | |
2204 | if ((val & PIPECONF_ENABLE) == 0) | |
2205 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2206 | } |
2207 | ||
693db184 CW |
2208 | static bool need_vtd_wa(struct drm_device *dev) |
2209 | { | |
2210 | #ifdef CONFIG_INTEL_IOMMU | |
2211 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2212 | return true; | |
2213 | #endif | |
2214 | return false; | |
2215 | } | |
2216 | ||
50470bb0 | 2217 | unsigned int |
6761dd31 | 2218 | intel_tile_height(struct drm_device *dev, uint32_t pixel_format, |
fe47ea0c | 2219 | uint64_t fb_format_modifier, unsigned int plane) |
a57ce0b2 | 2220 | { |
6761dd31 TU |
2221 | unsigned int tile_height; |
2222 | uint32_t pixel_bytes; | |
a57ce0b2 | 2223 | |
b5d0e9bf DL |
2224 | switch (fb_format_modifier) { |
2225 | case DRM_FORMAT_MOD_NONE: | |
2226 | tile_height = 1; | |
2227 | break; | |
2228 | case I915_FORMAT_MOD_X_TILED: | |
2229 | tile_height = IS_GEN2(dev) ? 16 : 8; | |
2230 | break; | |
2231 | case I915_FORMAT_MOD_Y_TILED: | |
2232 | tile_height = 32; | |
2233 | break; | |
2234 | case I915_FORMAT_MOD_Yf_TILED: | |
fe47ea0c | 2235 | pixel_bytes = drm_format_plane_cpp(pixel_format, plane); |
6761dd31 | 2236 | switch (pixel_bytes) { |
b5d0e9bf | 2237 | default: |
6761dd31 | 2238 | case 1: |
b5d0e9bf DL |
2239 | tile_height = 64; |
2240 | break; | |
6761dd31 TU |
2241 | case 2: |
2242 | case 4: | |
b5d0e9bf DL |
2243 | tile_height = 32; |
2244 | break; | |
6761dd31 | 2245 | case 8: |
b5d0e9bf DL |
2246 | tile_height = 16; |
2247 | break; | |
6761dd31 | 2248 | case 16: |
b5d0e9bf DL |
2249 | WARN_ONCE(1, |
2250 | "128-bit pixels are not supported for display!"); | |
2251 | tile_height = 16; | |
2252 | break; | |
2253 | } | |
2254 | break; | |
2255 | default: | |
2256 | MISSING_CASE(fb_format_modifier); | |
2257 | tile_height = 1; | |
2258 | break; | |
2259 | } | |
091df6cb | 2260 | |
6761dd31 TU |
2261 | return tile_height; |
2262 | } | |
2263 | ||
2264 | unsigned int | |
2265 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
2266 | uint32_t pixel_format, uint64_t fb_format_modifier) | |
2267 | { | |
2268 | return ALIGN(height, intel_tile_height(dev, pixel_format, | |
fe47ea0c | 2269 | fb_format_modifier, 0)); |
a57ce0b2 JB |
2270 | } |
2271 | ||
75c82a53 | 2272 | static void |
f64b98cd TU |
2273 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, |
2274 | const struct drm_plane_state *plane_state) | |
2275 | { | |
a6d09186 | 2276 | struct intel_rotation_info *info = &view->params.rotation_info; |
84fe03f7 | 2277 | unsigned int tile_height, tile_pitch; |
50470bb0 | 2278 | |
f64b98cd TU |
2279 | *view = i915_ggtt_view_normal; |
2280 | ||
50470bb0 | 2281 | if (!plane_state) |
75c82a53 | 2282 | return; |
50470bb0 | 2283 | |
121920fa | 2284 | if (!intel_rotation_90_or_270(plane_state->rotation)) |
75c82a53 | 2285 | return; |
50470bb0 | 2286 | |
9abc4648 | 2287 | *view = i915_ggtt_view_rotated; |
50470bb0 TU |
2288 | |
2289 | info->height = fb->height; | |
2290 | info->pixel_format = fb->pixel_format; | |
2291 | info->pitch = fb->pitches[0]; | |
89e3e142 | 2292 | info->uv_offset = fb->offsets[1]; |
50470bb0 TU |
2293 | info->fb_modifier = fb->modifier[0]; |
2294 | ||
84fe03f7 | 2295 | tile_height = intel_tile_height(fb->dev, fb->pixel_format, |
fe47ea0c | 2296 | fb->modifier[0], 0); |
84fe03f7 TU |
2297 | tile_pitch = PAGE_SIZE / tile_height; |
2298 | info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch); | |
2299 | info->height_pages = DIV_ROUND_UP(fb->height, tile_height); | |
2300 | info->size = info->width_pages * info->height_pages * PAGE_SIZE; | |
2301 | ||
89e3e142 TU |
2302 | if (info->pixel_format == DRM_FORMAT_NV12) { |
2303 | tile_height = intel_tile_height(fb->dev, fb->pixel_format, | |
2304 | fb->modifier[0], 1); | |
2305 | tile_pitch = PAGE_SIZE / tile_height; | |
2306 | info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch); | |
2307 | info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, | |
2308 | tile_height); | |
2309 | info->size_uv = info->width_pages_uv * info->height_pages_uv * | |
2310 | PAGE_SIZE; | |
2311 | } | |
f64b98cd TU |
2312 | } |
2313 | ||
4e9a86b6 VS |
2314 | static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv) |
2315 | { | |
2316 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2317 | return 256 * 1024; | |
985b8bb4 | 2318 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
666a4537 | 2319 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2320 | return 128 * 1024; |
2321 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2322 | return 4 * 1024; | |
2323 | else | |
44c5905e | 2324 | return 0; |
4e9a86b6 VS |
2325 | } |
2326 | ||
127bd2ac | 2327 | int |
850c4cdc TU |
2328 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2329 | struct drm_framebuffer *fb, | |
7580d774 | 2330 | const struct drm_plane_state *plane_state) |
6b95a207 | 2331 | { |
850c4cdc | 2332 | struct drm_device *dev = fb->dev; |
ce453d81 | 2333 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2334 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2335 | struct i915_ggtt_view view; |
6b95a207 KH |
2336 | u32 alignment; |
2337 | int ret; | |
2338 | ||
ebcdd39e MR |
2339 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2340 | ||
7b911adc TU |
2341 | switch (fb->modifier[0]) { |
2342 | case DRM_FORMAT_MOD_NONE: | |
4e9a86b6 | 2343 | alignment = intel_linear_alignment(dev_priv); |
6b95a207 | 2344 | break; |
7b911adc | 2345 | case I915_FORMAT_MOD_X_TILED: |
1fada4cc DL |
2346 | if (INTEL_INFO(dev)->gen >= 9) |
2347 | alignment = 256 * 1024; | |
2348 | else { | |
2349 | /* pin() will align the object as required by fence */ | |
2350 | alignment = 0; | |
2351 | } | |
6b95a207 | 2352 | break; |
7b911adc | 2353 | case I915_FORMAT_MOD_Y_TILED: |
1327b9a1 DL |
2354 | case I915_FORMAT_MOD_Yf_TILED: |
2355 | if (WARN_ONCE(INTEL_INFO(dev)->gen < 9, | |
2356 | "Y tiling bo slipped through, driver bug!\n")) | |
2357 | return -EINVAL; | |
2358 | alignment = 1 * 1024 * 1024; | |
2359 | break; | |
6b95a207 | 2360 | default: |
7b911adc TU |
2361 | MISSING_CASE(fb->modifier[0]); |
2362 | return -EINVAL; | |
6b95a207 KH |
2363 | } |
2364 | ||
75c82a53 | 2365 | intel_fill_fb_ggtt_view(&view, fb, plane_state); |
f64b98cd | 2366 | |
693db184 CW |
2367 | /* Note that the w/a also requires 64 PTE of padding following the |
2368 | * bo. We currently fill all unused PTE with the shadow page and so | |
2369 | * we should always have valid PTE following the scanout preventing | |
2370 | * the VT-d warning. | |
2371 | */ | |
2372 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2373 | alignment = 256 * 1024; | |
2374 | ||
d6dd6843 PZ |
2375 | /* |
2376 | * Global gtt pte registers are special registers which actually forward | |
2377 | * writes to a chunk of system memory. Which means that there is no risk | |
2378 | * that the register values disappear as soon as we call | |
2379 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2380 | * pin/unpin/fence and not more. | |
2381 | */ | |
2382 | intel_runtime_pm_get(dev_priv); | |
2383 | ||
7580d774 ML |
2384 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, |
2385 | &view); | |
48b956c5 | 2386 | if (ret) |
b26a6b35 | 2387 | goto err_pm; |
6b95a207 KH |
2388 | |
2389 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2390 | * fence, whereas 965+ only requires a fence if using | |
2391 | * framebuffer compression. For simplicity, we always install | |
2392 | * a fence as the cost is not that onerous. | |
2393 | */ | |
9807216f VK |
2394 | if (view.type == I915_GGTT_VIEW_NORMAL) { |
2395 | ret = i915_gem_object_get_fence(obj); | |
2396 | if (ret == -EDEADLK) { | |
2397 | /* | |
2398 | * -EDEADLK means there are no free fences | |
2399 | * no pending flips. | |
2400 | * | |
2401 | * This is propagated to atomic, but it uses | |
2402 | * -EDEADLK to force a locking recovery, so | |
2403 | * change the returned error to -EBUSY. | |
2404 | */ | |
2405 | ret = -EBUSY; | |
2406 | goto err_unpin; | |
2407 | } else if (ret) | |
2408 | goto err_unpin; | |
1690e1eb | 2409 | |
9807216f VK |
2410 | i915_gem_object_pin_fence(obj); |
2411 | } | |
6b95a207 | 2412 | |
d6dd6843 | 2413 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2414 | return 0; |
48b956c5 CW |
2415 | |
2416 | err_unpin: | |
f64b98cd | 2417 | i915_gem_object_unpin_from_display_plane(obj, &view); |
b26a6b35 | 2418 | err_pm: |
d6dd6843 | 2419 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2420 | return ret; |
6b95a207 KH |
2421 | } |
2422 | ||
82bc3b2d TU |
2423 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, |
2424 | const struct drm_plane_state *plane_state) | |
1690e1eb | 2425 | { |
82bc3b2d | 2426 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2427 | struct i915_ggtt_view view; |
82bc3b2d | 2428 | |
ebcdd39e MR |
2429 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2430 | ||
75c82a53 | 2431 | intel_fill_fb_ggtt_view(&view, fb, plane_state); |
f64b98cd | 2432 | |
9807216f VK |
2433 | if (view.type == I915_GGTT_VIEW_NORMAL) |
2434 | i915_gem_object_unpin_fence(obj); | |
2435 | ||
f64b98cd | 2436 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2437 | } |
2438 | ||
c2c75131 DV |
2439 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2440 | * is assumed to be a power-of-two. */ | |
4e9a86b6 VS |
2441 | unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv, |
2442 | int *x, int *y, | |
bc752862 CW |
2443 | unsigned int tiling_mode, |
2444 | unsigned int cpp, | |
2445 | unsigned int pitch) | |
c2c75131 | 2446 | { |
bc752862 CW |
2447 | if (tiling_mode != I915_TILING_NONE) { |
2448 | unsigned int tile_rows, tiles; | |
c2c75131 | 2449 | |
bc752862 CW |
2450 | tile_rows = *y / 8; |
2451 | *y %= 8; | |
c2c75131 | 2452 | |
bc752862 CW |
2453 | tiles = *x / (512/cpp); |
2454 | *x %= 512/cpp; | |
2455 | ||
2456 | return tile_rows * pitch * 8 + tiles * 4096; | |
2457 | } else { | |
4e9a86b6 | 2458 | unsigned int alignment = intel_linear_alignment(dev_priv) - 1; |
bc752862 CW |
2459 | unsigned int offset; |
2460 | ||
2461 | offset = *y * pitch + *x * cpp; | |
4e9a86b6 VS |
2462 | *y = (offset & alignment) / pitch; |
2463 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
2464 | return offset & ~alignment; | |
bc752862 | 2465 | } |
c2c75131 DV |
2466 | } |
2467 | ||
b35d63fa | 2468 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2469 | { |
2470 | switch (format) { | |
2471 | case DISPPLANE_8BPP: | |
2472 | return DRM_FORMAT_C8; | |
2473 | case DISPPLANE_BGRX555: | |
2474 | return DRM_FORMAT_XRGB1555; | |
2475 | case DISPPLANE_BGRX565: | |
2476 | return DRM_FORMAT_RGB565; | |
2477 | default: | |
2478 | case DISPPLANE_BGRX888: | |
2479 | return DRM_FORMAT_XRGB8888; | |
2480 | case DISPPLANE_RGBX888: | |
2481 | return DRM_FORMAT_XBGR8888; | |
2482 | case DISPPLANE_BGRX101010: | |
2483 | return DRM_FORMAT_XRGB2101010; | |
2484 | case DISPPLANE_RGBX101010: | |
2485 | return DRM_FORMAT_XBGR2101010; | |
2486 | } | |
2487 | } | |
2488 | ||
bc8d7dff DL |
2489 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2490 | { | |
2491 | switch (format) { | |
2492 | case PLANE_CTL_FORMAT_RGB_565: | |
2493 | return DRM_FORMAT_RGB565; | |
2494 | default: | |
2495 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2496 | if (rgb_order) { | |
2497 | if (alpha) | |
2498 | return DRM_FORMAT_ABGR8888; | |
2499 | else | |
2500 | return DRM_FORMAT_XBGR8888; | |
2501 | } else { | |
2502 | if (alpha) | |
2503 | return DRM_FORMAT_ARGB8888; | |
2504 | else | |
2505 | return DRM_FORMAT_XRGB8888; | |
2506 | } | |
2507 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2508 | if (rgb_order) | |
2509 | return DRM_FORMAT_XBGR2101010; | |
2510 | else | |
2511 | return DRM_FORMAT_XRGB2101010; | |
2512 | } | |
2513 | } | |
2514 | ||
5724dbd1 | 2515 | static bool |
f6936e29 DV |
2516 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2517 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2518 | { |
2519 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2520 | struct drm_i915_private *dev_priv = to_i915(dev); |
46f297fb JB |
2521 | struct drm_i915_gem_object *obj = NULL; |
2522 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2523 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2524 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2525 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2526 | PAGE_SIZE); | |
2527 | ||
2528 | size_aligned -= base_aligned; | |
46f297fb | 2529 | |
ff2652ea CW |
2530 | if (plane_config->size == 0) |
2531 | return false; | |
2532 | ||
3badb49f PZ |
2533 | /* If the FB is too big, just don't use it since fbdev is not very |
2534 | * important and we should probably use that space with FBC or other | |
2535 | * features. */ | |
2536 | if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size) | |
2537 | return false; | |
2538 | ||
f37b5c2b DV |
2539 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2540 | base_aligned, | |
2541 | base_aligned, | |
2542 | size_aligned); | |
46f297fb | 2543 | if (!obj) |
484b41dd | 2544 | return false; |
46f297fb | 2545 | |
49af449b DL |
2546 | obj->tiling_mode = plane_config->tiling; |
2547 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2548 | obj->stride = fb->pitches[0]; |
46f297fb | 2549 | |
6bf129df DL |
2550 | mode_cmd.pixel_format = fb->pixel_format; |
2551 | mode_cmd.width = fb->width; | |
2552 | mode_cmd.height = fb->height; | |
2553 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2554 | mode_cmd.modifier[0] = fb->modifier[0]; |
2555 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb JB |
2556 | |
2557 | mutex_lock(&dev->struct_mutex); | |
6bf129df | 2558 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2559 | &mode_cmd, obj)) { |
46f297fb JB |
2560 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2561 | goto out_unref_obj; | |
2562 | } | |
46f297fb | 2563 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2564 | |
f6936e29 | 2565 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2566 | return true; |
46f297fb JB |
2567 | |
2568 | out_unref_obj: | |
2569 | drm_gem_object_unreference(&obj->base); | |
2570 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2571 | return false; |
2572 | } | |
2573 | ||
afd65eb4 MR |
2574 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2575 | static void | |
2576 | update_state_fb(struct drm_plane *plane) | |
2577 | { | |
2578 | if (plane->fb == plane->state->fb) | |
2579 | return; | |
2580 | ||
2581 | if (plane->state->fb) | |
2582 | drm_framebuffer_unreference(plane->state->fb); | |
2583 | plane->state->fb = plane->fb; | |
2584 | if (plane->state->fb) | |
2585 | drm_framebuffer_reference(plane->state->fb); | |
2586 | } | |
2587 | ||
5724dbd1 | 2588 | static void |
f6936e29 DV |
2589 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2590 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2591 | { |
2592 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2593 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2594 | struct drm_crtc *c; |
2595 | struct intel_crtc *i; | |
2ff8fde1 | 2596 | struct drm_i915_gem_object *obj; |
88595ac9 | 2597 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2598 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2599 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2600 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2601 | struct intel_plane_state *intel_state = |
2602 | to_intel_plane_state(plane_state); | |
88595ac9 | 2603 | struct drm_framebuffer *fb; |
484b41dd | 2604 | |
2d14030b | 2605 | if (!plane_config->fb) |
484b41dd JB |
2606 | return; |
2607 | ||
f6936e29 | 2608 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2609 | fb = &plane_config->fb->base; |
2610 | goto valid_fb; | |
f55548b5 | 2611 | } |
484b41dd | 2612 | |
2d14030b | 2613 | kfree(plane_config->fb); |
484b41dd JB |
2614 | |
2615 | /* | |
2616 | * Failed to alloc the obj, check to see if we should share | |
2617 | * an fb with another CRTC instead | |
2618 | */ | |
70e1e0ec | 2619 | for_each_crtc(dev, c) { |
484b41dd JB |
2620 | i = to_intel_crtc(c); |
2621 | ||
2622 | if (c == &intel_crtc->base) | |
2623 | continue; | |
2624 | ||
2ff8fde1 MR |
2625 | if (!i->active) |
2626 | continue; | |
2627 | ||
88595ac9 DV |
2628 | fb = c->primary->fb; |
2629 | if (!fb) | |
484b41dd JB |
2630 | continue; |
2631 | ||
88595ac9 | 2632 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2633 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2634 | drm_framebuffer_reference(fb); |
2635 | goto valid_fb; | |
484b41dd JB |
2636 | } |
2637 | } | |
88595ac9 | 2638 | |
200757f5 MR |
2639 | /* |
2640 | * We've failed to reconstruct the BIOS FB. Current display state | |
2641 | * indicates that the primary plane is visible, but has a NULL FB, | |
2642 | * which will lead to problems later if we don't fix it up. The | |
2643 | * simplest solution is to just disable the primary plane now and | |
2644 | * pretend the BIOS never had it enabled. | |
2645 | */ | |
2646 | to_intel_plane_state(plane_state)->visible = false; | |
2647 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); | |
2648 | intel_pre_disable_primary(&intel_crtc->base); | |
2649 | intel_plane->disable_plane(primary, &intel_crtc->base); | |
2650 | ||
88595ac9 DV |
2651 | return; |
2652 | ||
2653 | valid_fb: | |
f44e2659 VS |
2654 | plane_state->src_x = 0; |
2655 | plane_state->src_y = 0; | |
be5651f2 ML |
2656 | plane_state->src_w = fb->width << 16; |
2657 | plane_state->src_h = fb->height << 16; | |
2658 | ||
f44e2659 VS |
2659 | plane_state->crtc_x = 0; |
2660 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2661 | plane_state->crtc_w = fb->width; |
2662 | plane_state->crtc_h = fb->height; | |
2663 | ||
0a8d8a86 MR |
2664 | intel_state->src.x1 = plane_state->src_x; |
2665 | intel_state->src.y1 = plane_state->src_y; | |
2666 | intel_state->src.x2 = plane_state->src_x + plane_state->src_w; | |
2667 | intel_state->src.y2 = plane_state->src_y + plane_state->src_h; | |
2668 | intel_state->dst.x1 = plane_state->crtc_x; | |
2669 | intel_state->dst.y1 = plane_state->crtc_y; | |
2670 | intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w; | |
2671 | intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h; | |
2672 | ||
88595ac9 DV |
2673 | obj = intel_fb_obj(fb); |
2674 | if (obj->tiling_mode != I915_TILING_NONE) | |
2675 | dev_priv->preserve_bios_swizzle = true; | |
2676 | ||
be5651f2 ML |
2677 | drm_framebuffer_reference(fb); |
2678 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2679 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2680 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
a9ff8714 | 2681 | obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit; |
46f297fb JB |
2682 | } |
2683 | ||
29b9bde6 DV |
2684 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2685 | struct drm_framebuffer *fb, | |
2686 | int x, int y) | |
81255565 JB |
2687 | { |
2688 | struct drm_device *dev = crtc->dev; | |
2689 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2690 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
2691 | struct drm_plane *primary = crtc->primary; |
2692 | bool visible = to_intel_plane_state(primary->state)->visible; | |
c9ba6fad | 2693 | struct drm_i915_gem_object *obj; |
81255565 | 2694 | int plane = intel_crtc->plane; |
e506a0c6 | 2695 | unsigned long linear_offset; |
81255565 | 2696 | u32 dspcntr; |
f0f59a00 | 2697 | i915_reg_t reg = DSPCNTR(plane); |
48404c1e | 2698 | int pixel_size; |
f45651ba | 2699 | |
b70709a6 | 2700 | if (!visible || !fb) { |
fdd508a6 VS |
2701 | I915_WRITE(reg, 0); |
2702 | if (INTEL_INFO(dev)->gen >= 4) | |
2703 | I915_WRITE(DSPSURF(plane), 0); | |
2704 | else | |
2705 | I915_WRITE(DSPADDR(plane), 0); | |
2706 | POSTING_READ(reg); | |
2707 | return; | |
2708 | } | |
2709 | ||
c9ba6fad VS |
2710 | obj = intel_fb_obj(fb); |
2711 | if (WARN_ON(obj == NULL)) | |
2712 | return; | |
2713 | ||
2714 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2715 | ||
f45651ba VS |
2716 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2717 | ||
fdd508a6 | 2718 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2719 | |
2720 | if (INTEL_INFO(dev)->gen < 4) { | |
2721 | if (intel_crtc->pipe == PIPE_B) | |
2722 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2723 | ||
2724 | /* pipesrc and dspsize control the size that is scaled from, | |
2725 | * which should always be the user's requested size. | |
2726 | */ | |
2727 | I915_WRITE(DSPSIZE(plane), | |
6e3c9717 ACO |
2728 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2729 | (intel_crtc->config->pipe_src_w - 1)); | |
f45651ba | 2730 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2731 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2732 | I915_WRITE(PRIMSIZE(plane), | |
6e3c9717 ACO |
2733 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2734 | (intel_crtc->config->pipe_src_w - 1)); | |
c14b0485 VS |
2735 | I915_WRITE(PRIMPOS(plane), 0); |
2736 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2737 | } |
81255565 | 2738 | |
57779d06 VS |
2739 | switch (fb->pixel_format) { |
2740 | case DRM_FORMAT_C8: | |
81255565 JB |
2741 | dspcntr |= DISPPLANE_8BPP; |
2742 | break; | |
57779d06 | 2743 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2744 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2745 | break; |
57779d06 VS |
2746 | case DRM_FORMAT_RGB565: |
2747 | dspcntr |= DISPPLANE_BGRX565; | |
2748 | break; | |
2749 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2750 | dspcntr |= DISPPLANE_BGRX888; |
2751 | break; | |
2752 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2753 | dspcntr |= DISPPLANE_RGBX888; |
2754 | break; | |
2755 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2756 | dspcntr |= DISPPLANE_BGRX101010; |
2757 | break; | |
2758 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2759 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
2760 | break; |
2761 | default: | |
baba133a | 2762 | BUG(); |
81255565 | 2763 | } |
57779d06 | 2764 | |
f45651ba VS |
2765 | if (INTEL_INFO(dev)->gen >= 4 && |
2766 | obj->tiling_mode != I915_TILING_NONE) | |
2767 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2768 | |
de1aa629 VS |
2769 | if (IS_G4X(dev)) |
2770 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2771 | ||
b9897127 | 2772 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
81255565 | 2773 | |
c2c75131 DV |
2774 | if (INTEL_INFO(dev)->gen >= 4) { |
2775 | intel_crtc->dspaddr_offset = | |
4e9a86b6 VS |
2776 | intel_gen4_compute_page_offset(dev_priv, |
2777 | &x, &y, obj->tiling_mode, | |
b9897127 | 2778 | pixel_size, |
bc752862 | 2779 | fb->pitches[0]); |
c2c75131 DV |
2780 | linear_offset -= intel_crtc->dspaddr_offset; |
2781 | } else { | |
e506a0c6 | 2782 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2783 | } |
e506a0c6 | 2784 | |
8e7d688b | 2785 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2786 | dspcntr |= DISPPLANE_ROTATE_180; |
2787 | ||
6e3c9717 ACO |
2788 | x += (intel_crtc->config->pipe_src_w - 1); |
2789 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2790 | |
2791 | /* Finding the last pixel of the last line of the display | |
2792 | data and adding to linear_offset*/ | |
2793 | linear_offset += | |
6e3c9717 ACO |
2794 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2795 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2796 | } |
2797 | ||
2db3366b PZ |
2798 | intel_crtc->adjusted_x = x; |
2799 | intel_crtc->adjusted_y = y; | |
2800 | ||
48404c1e SJ |
2801 | I915_WRITE(reg, dspcntr); |
2802 | ||
01f2c773 | 2803 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2804 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2805 | I915_WRITE(DSPSURF(plane), |
2806 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2807 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2808 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2809 | } else |
f343c5f6 | 2810 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2811 | POSTING_READ(reg); |
17638cd6 JB |
2812 | } |
2813 | ||
29b9bde6 DV |
2814 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2815 | struct drm_framebuffer *fb, | |
2816 | int x, int y) | |
17638cd6 JB |
2817 | { |
2818 | struct drm_device *dev = crtc->dev; | |
2819 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2820 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
2821 | struct drm_plane *primary = crtc->primary; |
2822 | bool visible = to_intel_plane_state(primary->state)->visible; | |
c9ba6fad | 2823 | struct drm_i915_gem_object *obj; |
17638cd6 | 2824 | int plane = intel_crtc->plane; |
e506a0c6 | 2825 | unsigned long linear_offset; |
17638cd6 | 2826 | u32 dspcntr; |
f0f59a00 | 2827 | i915_reg_t reg = DSPCNTR(plane); |
48404c1e | 2828 | int pixel_size; |
f45651ba | 2829 | |
b70709a6 | 2830 | if (!visible || !fb) { |
fdd508a6 VS |
2831 | I915_WRITE(reg, 0); |
2832 | I915_WRITE(DSPSURF(plane), 0); | |
2833 | POSTING_READ(reg); | |
2834 | return; | |
2835 | } | |
2836 | ||
c9ba6fad VS |
2837 | obj = intel_fb_obj(fb); |
2838 | if (WARN_ON(obj == NULL)) | |
2839 | return; | |
2840 | ||
2841 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2842 | ||
f45651ba VS |
2843 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2844 | ||
fdd508a6 | 2845 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2846 | |
2847 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2848 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2849 | |
57779d06 VS |
2850 | switch (fb->pixel_format) { |
2851 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2852 | dspcntr |= DISPPLANE_8BPP; |
2853 | break; | |
57779d06 VS |
2854 | case DRM_FORMAT_RGB565: |
2855 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2856 | break; |
57779d06 | 2857 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
2858 | dspcntr |= DISPPLANE_BGRX888; |
2859 | break; | |
2860 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2861 | dspcntr |= DISPPLANE_RGBX888; |
2862 | break; | |
2863 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2864 | dspcntr |= DISPPLANE_BGRX101010; |
2865 | break; | |
2866 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2867 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
2868 | break; |
2869 | default: | |
baba133a | 2870 | BUG(); |
17638cd6 JB |
2871 | } |
2872 | ||
2873 | if (obj->tiling_mode != I915_TILING_NONE) | |
2874 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2875 | |
f45651ba | 2876 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2877 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2878 | |
b9897127 | 2879 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
c2c75131 | 2880 | intel_crtc->dspaddr_offset = |
4e9a86b6 VS |
2881 | intel_gen4_compute_page_offset(dev_priv, |
2882 | &x, &y, obj->tiling_mode, | |
b9897127 | 2883 | pixel_size, |
bc752862 | 2884 | fb->pitches[0]); |
c2c75131 | 2885 | linear_offset -= intel_crtc->dspaddr_offset; |
8e7d688b | 2886 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2887 | dspcntr |= DISPPLANE_ROTATE_180; |
2888 | ||
2889 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
6e3c9717 ACO |
2890 | x += (intel_crtc->config->pipe_src_w - 1); |
2891 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2892 | |
2893 | /* Finding the last pixel of the last line of the display | |
2894 | data and adding to linear_offset*/ | |
2895 | linear_offset += | |
6e3c9717 ACO |
2896 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2897 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2898 | } |
2899 | } | |
2900 | ||
2db3366b PZ |
2901 | intel_crtc->adjusted_x = x; |
2902 | intel_crtc->adjusted_y = y; | |
2903 | ||
48404c1e | 2904 | I915_WRITE(reg, dspcntr); |
17638cd6 | 2905 | |
01f2c773 | 2906 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2907 | I915_WRITE(DSPSURF(plane), |
2908 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2909 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2910 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2911 | } else { | |
2912 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2913 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2914 | } | |
17638cd6 | 2915 | POSTING_READ(reg); |
17638cd6 JB |
2916 | } |
2917 | ||
b321803d DL |
2918 | u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, |
2919 | uint32_t pixel_format) | |
2920 | { | |
2921 | u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8; | |
2922 | ||
2923 | /* | |
2924 | * The stride is either expressed as a multiple of 64 bytes | |
2925 | * chunks for linear buffers or in number of tiles for tiled | |
2926 | * buffers. | |
2927 | */ | |
2928 | switch (fb_modifier) { | |
2929 | case DRM_FORMAT_MOD_NONE: | |
2930 | return 64; | |
2931 | case I915_FORMAT_MOD_X_TILED: | |
2932 | if (INTEL_INFO(dev)->gen == 2) | |
2933 | return 128; | |
2934 | return 512; | |
2935 | case I915_FORMAT_MOD_Y_TILED: | |
2936 | /* No need to check for old gens and Y tiling since this is | |
2937 | * about the display engine and those will be blocked before | |
2938 | * we get here. | |
2939 | */ | |
2940 | return 128; | |
2941 | case I915_FORMAT_MOD_Yf_TILED: | |
2942 | if (bits_per_pixel == 8) | |
2943 | return 64; | |
2944 | else | |
2945 | return 128; | |
2946 | default: | |
2947 | MISSING_CASE(fb_modifier); | |
2948 | return 64; | |
2949 | } | |
2950 | } | |
2951 | ||
44eb0cb9 MK |
2952 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, |
2953 | struct drm_i915_gem_object *obj, | |
2954 | unsigned int plane) | |
121920fa | 2955 | { |
ce7f1728 | 2956 | struct i915_ggtt_view view; |
dedf278c | 2957 | struct i915_vma *vma; |
44eb0cb9 | 2958 | u64 offset; |
121920fa | 2959 | |
ce7f1728 DV |
2960 | intel_fill_fb_ggtt_view(&view, intel_plane->base.fb, |
2961 | intel_plane->base.state); | |
121920fa | 2962 | |
ce7f1728 | 2963 | vma = i915_gem_obj_to_ggtt_view(obj, &view); |
dedf278c | 2964 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", |
ce7f1728 | 2965 | view.type)) |
dedf278c TU |
2966 | return -1; |
2967 | ||
44eb0cb9 | 2968 | offset = vma->node.start; |
dedf278c TU |
2969 | |
2970 | if (plane == 1) { | |
a6d09186 | 2971 | offset += vma->ggtt_view.params.rotation_info.uv_start_page * |
dedf278c TU |
2972 | PAGE_SIZE; |
2973 | } | |
2974 | ||
44eb0cb9 MK |
2975 | WARN_ON(upper_32_bits(offset)); |
2976 | ||
2977 | return lower_32_bits(offset); | |
121920fa TU |
2978 | } |
2979 | ||
e435d6e5 ML |
2980 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
2981 | { | |
2982 | struct drm_device *dev = intel_crtc->base.dev; | |
2983 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2984 | ||
2985 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
2986 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
2987 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
2988 | } |
2989 | ||
a1b2278e CK |
2990 | /* |
2991 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2992 | */ | |
0583236e | 2993 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 2994 | { |
a1b2278e CK |
2995 | struct intel_crtc_scaler_state *scaler_state; |
2996 | int i; | |
2997 | ||
a1b2278e CK |
2998 | scaler_state = &intel_crtc->config->scaler_state; |
2999 | ||
3000 | /* loop through and disable scalers that aren't in use */ | |
3001 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
3002 | if (!scaler_state->scalers[i].in_use) |
3003 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
3004 | } |
3005 | } | |
3006 | ||
6156a456 | 3007 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 3008 | { |
6156a456 | 3009 | switch (pixel_format) { |
d161cf7a | 3010 | case DRM_FORMAT_C8: |
c34ce3d1 | 3011 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 3012 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 3013 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 3014 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 3015 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 3016 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 3017 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
3018 | /* |
3019 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
3020 | * to be already pre-multiplied. We need to add a knob (or a different | |
3021 | * DRM_FORMAT) for user-space to configure that. | |
3022 | */ | |
f75fb42a | 3023 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 3024 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 3025 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 3026 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 3027 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 3028 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 3029 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 3030 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 3031 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 3032 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 3033 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 3034 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 3035 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 3036 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 3037 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 3038 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 3039 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 3040 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 3041 | default: |
4249eeef | 3042 | MISSING_CASE(pixel_format); |
70d21f0e | 3043 | } |
8cfcba41 | 3044 | |
c34ce3d1 | 3045 | return 0; |
6156a456 | 3046 | } |
70d21f0e | 3047 | |
6156a456 CK |
3048 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
3049 | { | |
6156a456 | 3050 | switch (fb_modifier) { |
30af77c4 | 3051 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 3052 | break; |
30af77c4 | 3053 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 3054 | return PLANE_CTL_TILED_X; |
b321803d | 3055 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3056 | return PLANE_CTL_TILED_Y; |
b321803d | 3057 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3058 | return PLANE_CTL_TILED_YF; |
70d21f0e | 3059 | default: |
6156a456 | 3060 | MISSING_CASE(fb_modifier); |
70d21f0e | 3061 | } |
8cfcba41 | 3062 | |
c34ce3d1 | 3063 | return 0; |
6156a456 | 3064 | } |
70d21f0e | 3065 | |
6156a456 CK |
3066 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
3067 | { | |
3b7a5119 | 3068 | switch (rotation) { |
6156a456 CK |
3069 | case BIT(DRM_ROTATE_0): |
3070 | break; | |
1e8df167 SJ |
3071 | /* |
3072 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
3073 | * while i915 HW rotation is clockwise, thats why this swapping. | |
3074 | */ | |
3b7a5119 | 3075 | case BIT(DRM_ROTATE_90): |
1e8df167 | 3076 | return PLANE_CTL_ROTATE_270; |
3b7a5119 | 3077 | case BIT(DRM_ROTATE_180): |
c34ce3d1 | 3078 | return PLANE_CTL_ROTATE_180; |
3b7a5119 | 3079 | case BIT(DRM_ROTATE_270): |
1e8df167 | 3080 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3081 | default: |
3082 | MISSING_CASE(rotation); | |
3083 | } | |
3084 | ||
c34ce3d1 | 3085 | return 0; |
6156a456 CK |
3086 | } |
3087 | ||
3088 | static void skylake_update_primary_plane(struct drm_crtc *crtc, | |
3089 | struct drm_framebuffer *fb, | |
3090 | int x, int y) | |
3091 | { | |
3092 | struct drm_device *dev = crtc->dev; | |
3093 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3094 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
3095 | struct drm_plane *plane = crtc->primary; |
3096 | bool visible = to_intel_plane_state(plane->state)->visible; | |
6156a456 CK |
3097 | struct drm_i915_gem_object *obj; |
3098 | int pipe = intel_crtc->pipe; | |
3099 | u32 plane_ctl, stride_div, stride; | |
3100 | u32 tile_height, plane_offset, plane_size; | |
3101 | unsigned int rotation; | |
3102 | int x_offset, y_offset; | |
44eb0cb9 | 3103 | u32 surf_addr; |
6156a456 CK |
3104 | struct intel_crtc_state *crtc_state = intel_crtc->config; |
3105 | struct intel_plane_state *plane_state; | |
3106 | int src_x = 0, src_y = 0, src_w = 0, src_h = 0; | |
3107 | int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0; | |
3108 | int scaler_id = -1; | |
3109 | ||
6156a456 CK |
3110 | plane_state = to_intel_plane_state(plane->state); |
3111 | ||
b70709a6 | 3112 | if (!visible || !fb) { |
6156a456 CK |
3113 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3114 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3115 | POSTING_READ(PLANE_CTL(pipe, 0)); | |
3116 | return; | |
3b7a5119 | 3117 | } |
70d21f0e | 3118 | |
6156a456 CK |
3119 | plane_ctl = PLANE_CTL_ENABLE | |
3120 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3121 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3122 | ||
3123 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3124 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3125 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
3126 | ||
3127 | rotation = plane->state->rotation; | |
3128 | plane_ctl |= skl_plane_ctl_rotation(rotation); | |
3129 | ||
b321803d DL |
3130 | obj = intel_fb_obj(fb); |
3131 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], | |
3132 | fb->pixel_format); | |
dedf278c | 3133 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); |
3b7a5119 | 3134 | |
a42e5a23 PZ |
3135 | WARN_ON(drm_rect_width(&plane_state->src) == 0); |
3136 | ||
3137 | scaler_id = plane_state->scaler_id; | |
3138 | src_x = plane_state->src.x1 >> 16; | |
3139 | src_y = plane_state->src.y1 >> 16; | |
3140 | src_w = drm_rect_width(&plane_state->src) >> 16; | |
3141 | src_h = drm_rect_height(&plane_state->src) >> 16; | |
3142 | dst_x = plane_state->dst.x1; | |
3143 | dst_y = plane_state->dst.y1; | |
3144 | dst_w = drm_rect_width(&plane_state->dst); | |
3145 | dst_h = drm_rect_height(&plane_state->dst); | |
3146 | ||
3147 | WARN_ON(x != src_x || y != src_y); | |
6156a456 | 3148 | |
3b7a5119 SJ |
3149 | if (intel_rotation_90_or_270(rotation)) { |
3150 | /* stride = Surface height in tiles */ | |
2614f17d | 3151 | tile_height = intel_tile_height(dev, fb->pixel_format, |
fe47ea0c | 3152 | fb->modifier[0], 0); |
3b7a5119 | 3153 | stride = DIV_ROUND_UP(fb->height, tile_height); |
6156a456 | 3154 | x_offset = stride * tile_height - y - src_h; |
3b7a5119 | 3155 | y_offset = x; |
6156a456 | 3156 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3157 | } else { |
3158 | stride = fb->pitches[0] / stride_div; | |
3159 | x_offset = x; | |
3160 | y_offset = y; | |
6156a456 | 3161 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3162 | } |
3163 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3164 | |
2db3366b PZ |
3165 | intel_crtc->adjusted_x = x_offset; |
3166 | intel_crtc->adjusted_y = y_offset; | |
3167 | ||
70d21f0e | 3168 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3169 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3170 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3171 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3172 | |
3173 | if (scaler_id >= 0) { | |
3174 | uint32_t ps_ctrl = 0; | |
3175 | ||
3176 | WARN_ON(!dst_w || !dst_h); | |
3177 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3178 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3179 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3180 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3181 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3182 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3183 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3184 | } else { | |
3185 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3186 | } | |
3187 | ||
121920fa | 3188 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3189 | |
3190 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3191 | } | |
3192 | ||
17638cd6 JB |
3193 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3194 | static int | |
3195 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3196 | int x, int y, enum mode_set_atomic state) | |
3197 | { | |
3198 | struct drm_device *dev = crtc->dev; | |
3199 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 3200 | |
0e631adc PZ |
3201 | if (dev_priv->fbc.deactivate) |
3202 | dev_priv->fbc.deactivate(dev_priv); | |
81255565 | 3203 | |
29b9bde6 DV |
3204 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3205 | ||
3206 | return 0; | |
81255565 JB |
3207 | } |
3208 | ||
7514747d | 3209 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 3210 | { |
96a02917 VS |
3211 | struct drm_crtc *crtc; |
3212 | ||
70e1e0ec | 3213 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3214 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3215 | enum plane plane = intel_crtc->plane; | |
3216 | ||
3217 | intel_prepare_page_flip(dev, plane); | |
3218 | intel_finish_page_flip_plane(dev, plane); | |
3219 | } | |
7514747d VS |
3220 | } |
3221 | ||
3222 | static void intel_update_primary_planes(struct drm_device *dev) | |
3223 | { | |
7514747d | 3224 | struct drm_crtc *crtc; |
96a02917 | 3225 | |
70e1e0ec | 3226 | for_each_crtc(dev, crtc) { |
11c22da6 ML |
3227 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
3228 | struct intel_plane_state *plane_state; | |
96a02917 | 3229 | |
11c22da6 | 3230 | drm_modeset_lock_crtc(crtc, &plane->base); |
11c22da6 ML |
3231 | plane_state = to_intel_plane_state(plane->base.state); |
3232 | ||
f029ee82 | 3233 | if (crtc->state->active && plane_state->base.fb) |
11c22da6 ML |
3234 | plane->commit_plane(&plane->base, plane_state); |
3235 | ||
3236 | drm_modeset_unlock_crtc(crtc); | |
96a02917 VS |
3237 | } |
3238 | } | |
3239 | ||
7514747d VS |
3240 | void intel_prepare_reset(struct drm_device *dev) |
3241 | { | |
3242 | /* no reset support for gen2 */ | |
3243 | if (IS_GEN2(dev)) | |
3244 | return; | |
3245 | ||
3246 | /* reset doesn't touch the display */ | |
3247 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3248 | return; | |
3249 | ||
3250 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3251 | /* |
3252 | * Disabling the crtcs gracefully seems nicer. Also the | |
3253 | * g33 docs say we should at least disable all the planes. | |
3254 | */ | |
6b72d486 | 3255 | intel_display_suspend(dev); |
7514747d VS |
3256 | } |
3257 | ||
3258 | void intel_finish_reset(struct drm_device *dev) | |
3259 | { | |
3260 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3261 | ||
3262 | /* | |
3263 | * Flips in the rings will be nuked by the reset, | |
3264 | * so complete all pending flips so that user space | |
3265 | * will get its events and not get stuck. | |
3266 | */ | |
3267 | intel_complete_page_flips(dev); | |
3268 | ||
3269 | /* no reset support for gen2 */ | |
3270 | if (IS_GEN2(dev)) | |
3271 | return; | |
3272 | ||
3273 | /* reset doesn't touch the display */ | |
3274 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3275 | /* | |
3276 | * Flips in the rings have been nuked by the reset, | |
3277 | * so update the base address of all primary | |
3278 | * planes to the the last fb to make sure we're | |
3279 | * showing the correct fb after a reset. | |
11c22da6 ML |
3280 | * |
3281 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3282 | * CS-based flips (which might get lost in gpu resets) any more. | |
7514747d VS |
3283 | */ |
3284 | intel_update_primary_planes(dev); | |
3285 | return; | |
3286 | } | |
3287 | ||
3288 | /* | |
3289 | * The display has been reset as well, | |
3290 | * so need a full re-initialization. | |
3291 | */ | |
3292 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3293 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3294 | ||
3295 | intel_modeset_init_hw(dev); | |
3296 | ||
3297 | spin_lock_irq(&dev_priv->irq_lock); | |
3298 | if (dev_priv->display.hpd_irq_setup) | |
3299 | dev_priv->display.hpd_irq_setup(dev); | |
3300 | spin_unlock_irq(&dev_priv->irq_lock); | |
3301 | ||
043e9bda | 3302 | intel_display_resume(dev); |
7514747d VS |
3303 | |
3304 | intel_hpd_init(dev_priv); | |
3305 | ||
3306 | drm_modeset_unlock_all(dev); | |
3307 | } | |
3308 | ||
7d5e3799 CW |
3309 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3310 | { | |
3311 | struct drm_device *dev = crtc->dev; | |
3312 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3313 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3314 | bool pending; |
3315 | ||
3316 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3317 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3318 | return false; | |
3319 | ||
5e2d7afc | 3320 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3321 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3322 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3323 | |
3324 | return pending; | |
3325 | } | |
3326 | ||
bfd16b2a ML |
3327 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3328 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 GP |
3329 | { |
3330 | struct drm_device *dev = crtc->base.dev; | |
3331 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bfd16b2a ML |
3332 | struct intel_crtc_state *pipe_config = |
3333 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3334 | |
bfd16b2a ML |
3335 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3336 | crtc->base.mode = crtc->base.state->mode; | |
3337 | ||
3338 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3339 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3340 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 | 3341 | |
44522d85 ML |
3342 | if (HAS_DDI(dev)) |
3343 | intel_set_pipe_csc(&crtc->base); | |
3344 | ||
e30e8f75 GP |
3345 | /* |
3346 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3347 | * that in compute_mode_changes we check the native mode (not the pfit | |
3348 | * mode) to see if we can flip rather than do a full mode set. In the | |
3349 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3350 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3351 | * sized surface. | |
e30e8f75 GP |
3352 | */ |
3353 | ||
e30e8f75 | 3354 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3355 | ((pipe_config->pipe_src_w - 1) << 16) | |
3356 | (pipe_config->pipe_src_h - 1)); | |
3357 | ||
3358 | /* on skylake this is done by detaching scalers */ | |
3359 | if (INTEL_INFO(dev)->gen >= 9) { | |
3360 | skl_detach_scalers(crtc); | |
3361 | ||
3362 | if (pipe_config->pch_pfit.enabled) | |
3363 | skylake_pfit_enable(crtc); | |
3364 | } else if (HAS_PCH_SPLIT(dev)) { | |
3365 | if (pipe_config->pch_pfit.enabled) | |
3366 | ironlake_pfit_enable(crtc); | |
3367 | else if (old_crtc_state->pch_pfit.enabled) | |
3368 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3369 | } |
e30e8f75 GP |
3370 | } |
3371 | ||
5e84e1a4 ZW |
3372 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3373 | { | |
3374 | struct drm_device *dev = crtc->dev; | |
3375 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3376 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3377 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3378 | i915_reg_t reg; |
3379 | u32 temp; | |
5e84e1a4 ZW |
3380 | |
3381 | /* enable normal train */ | |
3382 | reg = FDI_TX_CTL(pipe); | |
3383 | temp = I915_READ(reg); | |
61e499bf | 3384 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3385 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3386 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3387 | } else { |
3388 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3389 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3390 | } |
5e84e1a4 ZW |
3391 | I915_WRITE(reg, temp); |
3392 | ||
3393 | reg = FDI_RX_CTL(pipe); | |
3394 | temp = I915_READ(reg); | |
3395 | if (HAS_PCH_CPT(dev)) { | |
3396 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3397 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3398 | } else { | |
3399 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3400 | temp |= FDI_LINK_TRAIN_NONE; | |
3401 | } | |
3402 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3403 | ||
3404 | /* wait one idle pattern time */ | |
3405 | POSTING_READ(reg); | |
3406 | udelay(1000); | |
357555c0 JB |
3407 | |
3408 | /* IVB wants error correction enabled */ | |
3409 | if (IS_IVYBRIDGE(dev)) | |
3410 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3411 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3412 | } |
3413 | ||
8db9d77b ZW |
3414 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3415 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3416 | { | |
3417 | struct drm_device *dev = crtc->dev; | |
3418 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3419 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3420 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3421 | i915_reg_t reg; |
3422 | u32 temp, tries; | |
8db9d77b | 3423 | |
1c8562f6 | 3424 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3425 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3426 | |
e1a44743 AJ |
3427 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3428 | for train result */ | |
5eddb70b CW |
3429 | reg = FDI_RX_IMR(pipe); |
3430 | temp = I915_READ(reg); | |
e1a44743 AJ |
3431 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3432 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3433 | I915_WRITE(reg, temp); |
3434 | I915_READ(reg); | |
e1a44743 AJ |
3435 | udelay(150); |
3436 | ||
8db9d77b | 3437 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3438 | reg = FDI_TX_CTL(pipe); |
3439 | temp = I915_READ(reg); | |
627eb5a3 | 3440 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3441 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3442 | temp &= ~FDI_LINK_TRAIN_NONE; |
3443 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3444 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3445 | |
5eddb70b CW |
3446 | reg = FDI_RX_CTL(pipe); |
3447 | temp = I915_READ(reg); | |
8db9d77b ZW |
3448 | temp &= ~FDI_LINK_TRAIN_NONE; |
3449 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3450 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3451 | ||
3452 | POSTING_READ(reg); | |
8db9d77b ZW |
3453 | udelay(150); |
3454 | ||
5b2adf89 | 3455 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3456 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3457 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3458 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3459 | |
5eddb70b | 3460 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3461 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3462 | temp = I915_READ(reg); |
8db9d77b ZW |
3463 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3464 | ||
3465 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3466 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3467 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3468 | break; |
3469 | } | |
8db9d77b | 3470 | } |
e1a44743 | 3471 | if (tries == 5) |
5eddb70b | 3472 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3473 | |
3474 | /* Train 2 */ | |
5eddb70b CW |
3475 | reg = FDI_TX_CTL(pipe); |
3476 | temp = I915_READ(reg); | |
8db9d77b ZW |
3477 | temp &= ~FDI_LINK_TRAIN_NONE; |
3478 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3479 | I915_WRITE(reg, temp); |
8db9d77b | 3480 | |
5eddb70b CW |
3481 | reg = FDI_RX_CTL(pipe); |
3482 | temp = I915_READ(reg); | |
8db9d77b ZW |
3483 | temp &= ~FDI_LINK_TRAIN_NONE; |
3484 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3485 | I915_WRITE(reg, temp); |
8db9d77b | 3486 | |
5eddb70b CW |
3487 | POSTING_READ(reg); |
3488 | udelay(150); | |
8db9d77b | 3489 | |
5eddb70b | 3490 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3491 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3492 | temp = I915_READ(reg); |
8db9d77b ZW |
3493 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3494 | ||
3495 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3496 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3497 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3498 | break; | |
3499 | } | |
8db9d77b | 3500 | } |
e1a44743 | 3501 | if (tries == 5) |
5eddb70b | 3502 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3503 | |
3504 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3505 | |
8db9d77b ZW |
3506 | } |
3507 | ||
0206e353 | 3508 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3509 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3510 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3511 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3512 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3513 | }; | |
3514 | ||
3515 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3516 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3517 | { | |
3518 | struct drm_device *dev = crtc->dev; | |
3519 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3520 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3521 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3522 | i915_reg_t reg; |
3523 | u32 temp, i, retry; | |
8db9d77b | 3524 | |
e1a44743 AJ |
3525 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3526 | for train result */ | |
5eddb70b CW |
3527 | reg = FDI_RX_IMR(pipe); |
3528 | temp = I915_READ(reg); | |
e1a44743 AJ |
3529 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3530 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3531 | I915_WRITE(reg, temp); |
3532 | ||
3533 | POSTING_READ(reg); | |
e1a44743 AJ |
3534 | udelay(150); |
3535 | ||
8db9d77b | 3536 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3537 | reg = FDI_TX_CTL(pipe); |
3538 | temp = I915_READ(reg); | |
627eb5a3 | 3539 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3540 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3541 | temp &= ~FDI_LINK_TRAIN_NONE; |
3542 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3543 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3544 | /* SNB-B */ | |
3545 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3546 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3547 | |
d74cf324 DV |
3548 | I915_WRITE(FDI_RX_MISC(pipe), |
3549 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3550 | ||
5eddb70b CW |
3551 | reg = FDI_RX_CTL(pipe); |
3552 | temp = I915_READ(reg); | |
8db9d77b ZW |
3553 | if (HAS_PCH_CPT(dev)) { |
3554 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3555 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3556 | } else { | |
3557 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3558 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3559 | } | |
5eddb70b CW |
3560 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3561 | ||
3562 | POSTING_READ(reg); | |
8db9d77b ZW |
3563 | udelay(150); |
3564 | ||
0206e353 | 3565 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3566 | reg = FDI_TX_CTL(pipe); |
3567 | temp = I915_READ(reg); | |
8db9d77b ZW |
3568 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3569 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3570 | I915_WRITE(reg, temp); |
3571 | ||
3572 | POSTING_READ(reg); | |
8db9d77b ZW |
3573 | udelay(500); |
3574 | ||
fa37d39e SP |
3575 | for (retry = 0; retry < 5; retry++) { |
3576 | reg = FDI_RX_IIR(pipe); | |
3577 | temp = I915_READ(reg); | |
3578 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3579 | if (temp & FDI_RX_BIT_LOCK) { | |
3580 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3581 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3582 | break; | |
3583 | } | |
3584 | udelay(50); | |
8db9d77b | 3585 | } |
fa37d39e SP |
3586 | if (retry < 5) |
3587 | break; | |
8db9d77b ZW |
3588 | } |
3589 | if (i == 4) | |
5eddb70b | 3590 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3591 | |
3592 | /* Train 2 */ | |
5eddb70b CW |
3593 | reg = FDI_TX_CTL(pipe); |
3594 | temp = I915_READ(reg); | |
8db9d77b ZW |
3595 | temp &= ~FDI_LINK_TRAIN_NONE; |
3596 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3597 | if (IS_GEN6(dev)) { | |
3598 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3599 | /* SNB-B */ | |
3600 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3601 | } | |
5eddb70b | 3602 | I915_WRITE(reg, temp); |
8db9d77b | 3603 | |
5eddb70b CW |
3604 | reg = FDI_RX_CTL(pipe); |
3605 | temp = I915_READ(reg); | |
8db9d77b ZW |
3606 | if (HAS_PCH_CPT(dev)) { |
3607 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3608 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3609 | } else { | |
3610 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3611 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3612 | } | |
5eddb70b CW |
3613 | I915_WRITE(reg, temp); |
3614 | ||
3615 | POSTING_READ(reg); | |
8db9d77b ZW |
3616 | udelay(150); |
3617 | ||
0206e353 | 3618 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3619 | reg = FDI_TX_CTL(pipe); |
3620 | temp = I915_READ(reg); | |
8db9d77b ZW |
3621 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3622 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3623 | I915_WRITE(reg, temp); |
3624 | ||
3625 | POSTING_READ(reg); | |
8db9d77b ZW |
3626 | udelay(500); |
3627 | ||
fa37d39e SP |
3628 | for (retry = 0; retry < 5; retry++) { |
3629 | reg = FDI_RX_IIR(pipe); | |
3630 | temp = I915_READ(reg); | |
3631 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3632 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3633 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3634 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3635 | break; | |
3636 | } | |
3637 | udelay(50); | |
8db9d77b | 3638 | } |
fa37d39e SP |
3639 | if (retry < 5) |
3640 | break; | |
8db9d77b ZW |
3641 | } |
3642 | if (i == 4) | |
5eddb70b | 3643 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3644 | |
3645 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3646 | } | |
3647 | ||
357555c0 JB |
3648 | /* Manual link training for Ivy Bridge A0 parts */ |
3649 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3650 | { | |
3651 | struct drm_device *dev = crtc->dev; | |
3652 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3653 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3654 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3655 | i915_reg_t reg; |
3656 | u32 temp, i, j; | |
357555c0 JB |
3657 | |
3658 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3659 | for train result */ | |
3660 | reg = FDI_RX_IMR(pipe); | |
3661 | temp = I915_READ(reg); | |
3662 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3663 | temp &= ~FDI_RX_BIT_LOCK; | |
3664 | I915_WRITE(reg, temp); | |
3665 | ||
3666 | POSTING_READ(reg); | |
3667 | udelay(150); | |
3668 | ||
01a415fd DV |
3669 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3670 | I915_READ(FDI_RX_IIR(pipe))); | |
3671 | ||
139ccd3f JB |
3672 | /* Try each vswing and preemphasis setting twice before moving on */ |
3673 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3674 | /* disable first in case we need to retry */ | |
3675 | reg = FDI_TX_CTL(pipe); | |
3676 | temp = I915_READ(reg); | |
3677 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3678 | temp &= ~FDI_TX_ENABLE; | |
3679 | I915_WRITE(reg, temp); | |
357555c0 | 3680 | |
139ccd3f JB |
3681 | reg = FDI_RX_CTL(pipe); |
3682 | temp = I915_READ(reg); | |
3683 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3684 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3685 | temp &= ~FDI_RX_ENABLE; | |
3686 | I915_WRITE(reg, temp); | |
357555c0 | 3687 | |
139ccd3f | 3688 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3689 | reg = FDI_TX_CTL(pipe); |
3690 | temp = I915_READ(reg); | |
139ccd3f | 3691 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3692 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3693 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3694 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3695 | temp |= snb_b_fdi_train_param[j/2]; |
3696 | temp |= FDI_COMPOSITE_SYNC; | |
3697 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3698 | |
139ccd3f JB |
3699 | I915_WRITE(FDI_RX_MISC(pipe), |
3700 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3701 | |
139ccd3f | 3702 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3703 | temp = I915_READ(reg); |
139ccd3f JB |
3704 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3705 | temp |= FDI_COMPOSITE_SYNC; | |
3706 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3707 | |
139ccd3f JB |
3708 | POSTING_READ(reg); |
3709 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3710 | |
139ccd3f JB |
3711 | for (i = 0; i < 4; i++) { |
3712 | reg = FDI_RX_IIR(pipe); | |
3713 | temp = I915_READ(reg); | |
3714 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3715 | |
139ccd3f JB |
3716 | if (temp & FDI_RX_BIT_LOCK || |
3717 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3718 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3719 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3720 | i); | |
3721 | break; | |
3722 | } | |
3723 | udelay(1); /* should be 0.5us */ | |
3724 | } | |
3725 | if (i == 4) { | |
3726 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3727 | continue; | |
3728 | } | |
357555c0 | 3729 | |
139ccd3f | 3730 | /* Train 2 */ |
357555c0 JB |
3731 | reg = FDI_TX_CTL(pipe); |
3732 | temp = I915_READ(reg); | |
139ccd3f JB |
3733 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3734 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3735 | I915_WRITE(reg, temp); | |
3736 | ||
3737 | reg = FDI_RX_CTL(pipe); | |
3738 | temp = I915_READ(reg); | |
3739 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3740 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3741 | I915_WRITE(reg, temp); |
3742 | ||
3743 | POSTING_READ(reg); | |
139ccd3f | 3744 | udelay(2); /* should be 1.5us */ |
357555c0 | 3745 | |
139ccd3f JB |
3746 | for (i = 0; i < 4; i++) { |
3747 | reg = FDI_RX_IIR(pipe); | |
3748 | temp = I915_READ(reg); | |
3749 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3750 | |
139ccd3f JB |
3751 | if (temp & FDI_RX_SYMBOL_LOCK || |
3752 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3753 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3754 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3755 | i); | |
3756 | goto train_done; | |
3757 | } | |
3758 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3759 | } |
139ccd3f JB |
3760 | if (i == 4) |
3761 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3762 | } |
357555c0 | 3763 | |
139ccd3f | 3764 | train_done: |
357555c0 JB |
3765 | DRM_DEBUG_KMS("FDI train done.\n"); |
3766 | } | |
3767 | ||
88cefb6c | 3768 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3769 | { |
88cefb6c | 3770 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3771 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3772 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
3773 | i915_reg_t reg; |
3774 | u32 temp; | |
c64e311e | 3775 | |
c98e9dcf | 3776 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3777 | reg = FDI_RX_CTL(pipe); |
3778 | temp = I915_READ(reg); | |
627eb5a3 | 3779 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3780 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3781 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3782 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3783 | ||
3784 | POSTING_READ(reg); | |
c98e9dcf JB |
3785 | udelay(200); |
3786 | ||
3787 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3788 | temp = I915_READ(reg); |
3789 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3790 | ||
3791 | POSTING_READ(reg); | |
c98e9dcf JB |
3792 | udelay(200); |
3793 | ||
20749730 PZ |
3794 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3795 | reg = FDI_TX_CTL(pipe); | |
3796 | temp = I915_READ(reg); | |
3797 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3798 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3799 | |
20749730 PZ |
3800 | POSTING_READ(reg); |
3801 | udelay(100); | |
6be4a607 | 3802 | } |
0e23b99d JB |
3803 | } |
3804 | ||
88cefb6c DV |
3805 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3806 | { | |
3807 | struct drm_device *dev = intel_crtc->base.dev; | |
3808 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3809 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3810 | i915_reg_t reg; |
3811 | u32 temp; | |
88cefb6c DV |
3812 | |
3813 | /* Switch from PCDclk to Rawclk */ | |
3814 | reg = FDI_RX_CTL(pipe); | |
3815 | temp = I915_READ(reg); | |
3816 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3817 | ||
3818 | /* Disable CPU FDI TX PLL */ | |
3819 | reg = FDI_TX_CTL(pipe); | |
3820 | temp = I915_READ(reg); | |
3821 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3822 | ||
3823 | POSTING_READ(reg); | |
3824 | udelay(100); | |
3825 | ||
3826 | reg = FDI_RX_CTL(pipe); | |
3827 | temp = I915_READ(reg); | |
3828 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3829 | ||
3830 | /* Wait for the clocks to turn off. */ | |
3831 | POSTING_READ(reg); | |
3832 | udelay(100); | |
3833 | } | |
3834 | ||
0fc932b8 JB |
3835 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3836 | { | |
3837 | struct drm_device *dev = crtc->dev; | |
3838 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3839 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3840 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3841 | i915_reg_t reg; |
3842 | u32 temp; | |
0fc932b8 JB |
3843 | |
3844 | /* disable CPU FDI tx and PCH FDI rx */ | |
3845 | reg = FDI_TX_CTL(pipe); | |
3846 | temp = I915_READ(reg); | |
3847 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3848 | POSTING_READ(reg); | |
3849 | ||
3850 | reg = FDI_RX_CTL(pipe); | |
3851 | temp = I915_READ(reg); | |
3852 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3853 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3854 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3855 | ||
3856 | POSTING_READ(reg); | |
3857 | udelay(100); | |
3858 | ||
3859 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3860 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3861 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3862 | |
3863 | /* still set train pattern 1 */ | |
3864 | reg = FDI_TX_CTL(pipe); | |
3865 | temp = I915_READ(reg); | |
3866 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3867 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3868 | I915_WRITE(reg, temp); | |
3869 | ||
3870 | reg = FDI_RX_CTL(pipe); | |
3871 | temp = I915_READ(reg); | |
3872 | if (HAS_PCH_CPT(dev)) { | |
3873 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3874 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3875 | } else { | |
3876 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3877 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3878 | } | |
3879 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3880 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3881 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3882 | I915_WRITE(reg, temp); |
3883 | ||
3884 | POSTING_READ(reg); | |
3885 | udelay(100); | |
3886 | } | |
3887 | ||
5dce5b93 CW |
3888 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3889 | { | |
3890 | struct intel_crtc *crtc; | |
3891 | ||
3892 | /* Note that we don't need to be called with mode_config.lock here | |
3893 | * as our list of CRTC objects is static for the lifetime of the | |
3894 | * device and so cannot disappear as we iterate. Similarly, we can | |
3895 | * happily treat the predicates as racy, atomic checks as userspace | |
3896 | * cannot claim and pin a new fb without at least acquring the | |
3897 | * struct_mutex and so serialising with us. | |
3898 | */ | |
d3fcc808 | 3899 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3900 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3901 | continue; | |
3902 | ||
3903 | if (crtc->unpin_work) | |
3904 | intel_wait_for_vblank(dev, crtc->pipe); | |
3905 | ||
3906 | return true; | |
3907 | } | |
3908 | ||
3909 | return false; | |
3910 | } | |
3911 | ||
d6bbafa1 CW |
3912 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3913 | { | |
3914 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3915 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3916 | ||
3917 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3918 | smp_rmb(); | |
3919 | intel_crtc->unpin_work = NULL; | |
3920 | ||
3921 | if (work->event) | |
3922 | drm_send_vblank_event(intel_crtc->base.dev, | |
3923 | intel_crtc->pipe, | |
3924 | work->event); | |
3925 | ||
3926 | drm_crtc_vblank_put(&intel_crtc->base); | |
3927 | ||
3928 | wake_up_all(&dev_priv->pending_flip_queue); | |
3929 | queue_work(dev_priv->wq, &work->work); | |
3930 | ||
3931 | trace_i915_flip_complete(intel_crtc->plane, | |
3932 | work->pending_flip_obj); | |
3933 | } | |
3934 | ||
5008e874 | 3935 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3936 | { |
0f91128d | 3937 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3938 | struct drm_i915_private *dev_priv = dev->dev_private; |
5008e874 | 3939 | long ret; |
e6c3a2a6 | 3940 | |
2c10d571 | 3941 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
3942 | |
3943 | ret = wait_event_interruptible_timeout( | |
3944 | dev_priv->pending_flip_queue, | |
3945 | !intel_crtc_has_pending_flip(crtc), | |
3946 | 60*HZ); | |
3947 | ||
3948 | if (ret < 0) | |
3949 | return ret; | |
3950 | ||
3951 | if (ret == 0) { | |
9c787942 | 3952 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2c10d571 | 3953 | |
5e2d7afc | 3954 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3955 | if (intel_crtc->unpin_work) { |
3956 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3957 | page_flip_completed(intel_crtc); | |
3958 | } | |
5e2d7afc | 3959 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3960 | } |
5bb61643 | 3961 | |
5008e874 | 3962 | return 0; |
e6c3a2a6 CW |
3963 | } |
3964 | ||
060f02d8 VS |
3965 | static void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
3966 | { | |
3967 | u32 temp; | |
3968 | ||
3969 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3970 | ||
3971 | mutex_lock(&dev_priv->sb_lock); | |
3972 | ||
3973 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
3974 | temp |= SBI_SSCCTL_DISABLE; | |
3975 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
3976 | ||
3977 | mutex_unlock(&dev_priv->sb_lock); | |
3978 | } | |
3979 | ||
e615efe4 ED |
3980 | /* Program iCLKIP clock to the desired frequency */ |
3981 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3982 | { | |
3983 | struct drm_device *dev = crtc->dev; | |
3984 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3985 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3986 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3987 | u32 temp; | |
3988 | ||
060f02d8 | 3989 | lpt_disable_iclkip(dev_priv); |
e615efe4 ED |
3990 | |
3991 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3992 | if (clock == 20000) { |
e615efe4 ED |
3993 | auxdiv = 1; |
3994 | divsel = 0x41; | |
3995 | phaseinc = 0x20; | |
3996 | } else { | |
3997 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3998 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3999 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
4000 | * convert the virtual clock precision to KHz here for higher |
4001 | * precision. | |
4002 | */ | |
4003 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
4004 | u32 iclk_pi_range = 64; | |
4005 | u32 desired_divisor, msb_divisor_value, pi_value; | |
4006 | ||
a2572f5c | 4007 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, clock); |
e615efe4 ED |
4008 | msb_divisor_value = desired_divisor / iclk_pi_range; |
4009 | pi_value = desired_divisor % iclk_pi_range; | |
4010 | ||
4011 | auxdiv = 0; | |
4012 | divsel = msb_divisor_value - 2; | |
4013 | phaseinc = pi_value; | |
4014 | } | |
4015 | ||
4016 | /* This should not happen with any sane values */ | |
4017 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
4018 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
4019 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
4020 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
4021 | ||
4022 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 4023 | clock, |
e615efe4 ED |
4024 | auxdiv, |
4025 | divsel, | |
4026 | phasedir, | |
4027 | phaseinc); | |
4028 | ||
060f02d8 VS |
4029 | mutex_lock(&dev_priv->sb_lock); |
4030 | ||
e615efe4 | 4031 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 4032 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4033 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4034 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4035 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4036 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4037 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4038 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4039 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4040 | |
4041 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4042 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4043 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4044 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4045 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4046 | |
4047 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4048 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4049 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4050 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 4051 | |
060f02d8 VS |
4052 | mutex_unlock(&dev_priv->sb_lock); |
4053 | ||
e615efe4 ED |
4054 | /* Wait for initialization time */ |
4055 | udelay(24); | |
4056 | ||
4057 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
4058 | } | |
4059 | ||
275f01b2 DV |
4060 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4061 | enum pipe pch_transcoder) | |
4062 | { | |
4063 | struct drm_device *dev = crtc->base.dev; | |
4064 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4065 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4066 | |
4067 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4068 | I915_READ(HTOTAL(cpu_transcoder))); | |
4069 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4070 | I915_READ(HBLANK(cpu_transcoder))); | |
4071 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4072 | I915_READ(HSYNC(cpu_transcoder))); | |
4073 | ||
4074 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4075 | I915_READ(VTOTAL(cpu_transcoder))); | |
4076 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4077 | I915_READ(VBLANK(cpu_transcoder))); | |
4078 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4079 | I915_READ(VSYNC(cpu_transcoder))); | |
4080 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4081 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4082 | } | |
4083 | ||
003632d9 | 4084 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
4085 | { |
4086 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4087 | uint32_t temp; | |
4088 | ||
4089 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4090 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4091 | return; |
4092 | ||
4093 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4094 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4095 | ||
003632d9 ACO |
4096 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4097 | if (enable) | |
4098 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4099 | ||
4100 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4101 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4102 | POSTING_READ(SOUTH_CHICKEN1); | |
4103 | } | |
4104 | ||
4105 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4106 | { | |
4107 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4108 | |
4109 | switch (intel_crtc->pipe) { | |
4110 | case PIPE_A: | |
4111 | break; | |
4112 | case PIPE_B: | |
6e3c9717 | 4113 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4114 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4115 | else |
003632d9 | 4116 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4117 | |
4118 | break; | |
4119 | case PIPE_C: | |
003632d9 | 4120 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4121 | |
4122 | break; | |
4123 | default: | |
4124 | BUG(); | |
4125 | } | |
4126 | } | |
4127 | ||
c48b5305 VS |
4128 | /* Return which DP Port should be selected for Transcoder DP control */ |
4129 | static enum port | |
4130 | intel_trans_dp_port_sel(struct drm_crtc *crtc) | |
4131 | { | |
4132 | struct drm_device *dev = crtc->dev; | |
4133 | struct intel_encoder *encoder; | |
4134 | ||
4135 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
4136 | if (encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
4137 | encoder->type == INTEL_OUTPUT_EDP) | |
4138 | return enc_to_dig_port(&encoder->base)->port; | |
4139 | } | |
4140 | ||
4141 | return -1; | |
4142 | } | |
4143 | ||
f67a559d JB |
4144 | /* |
4145 | * Enable PCH resources required for PCH ports: | |
4146 | * - PCH PLLs | |
4147 | * - FDI training & RX/TX | |
4148 | * - update transcoder timings | |
4149 | * - DP transcoding bits | |
4150 | * - transcoder | |
4151 | */ | |
4152 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4153 | { |
4154 | struct drm_device *dev = crtc->dev; | |
4155 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4156 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4157 | int pipe = intel_crtc->pipe; | |
f0f59a00 | 4158 | u32 temp; |
2c07245f | 4159 | |
ab9412ba | 4160 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4161 | |
1fbc0d78 DV |
4162 | if (IS_IVYBRIDGE(dev)) |
4163 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4164 | ||
cd986abb DV |
4165 | /* Write the TU size bits before fdi link training, so that error |
4166 | * detection works. */ | |
4167 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4168 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4169 | ||
3860b2ec VS |
4170 | /* |
4171 | * Sometimes spurious CPU pipe underruns happen during FDI | |
4172 | * training, at least with VGA+HDMI cloning. Suppress them. | |
4173 | */ | |
4174 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4175 | ||
c98e9dcf | 4176 | /* For PCH output, training FDI link */ |
674cf967 | 4177 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4178 | |
3ad8a208 DV |
4179 | /* We need to program the right clock selection before writing the pixel |
4180 | * mutliplier into the DPLL. */ | |
303b81e0 | 4181 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4182 | u32 sel; |
4b645f14 | 4183 | |
c98e9dcf | 4184 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4185 | temp |= TRANS_DPLL_ENABLE(pipe); |
4186 | sel = TRANS_DPLLB_SEL(pipe); | |
6e3c9717 | 4187 | if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
4188 | temp |= sel; |
4189 | else | |
4190 | temp &= ~sel; | |
c98e9dcf | 4191 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4192 | } |
5eddb70b | 4193 | |
3ad8a208 DV |
4194 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4195 | * transcoder, and we actually should do this to not upset any PCH | |
4196 | * transcoder that already use the clock when we share it. | |
4197 | * | |
4198 | * Note that enable_shared_dpll tries to do the right thing, but | |
4199 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4200 | * the right LVDS enable sequence. */ | |
85b3894f | 4201 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4202 | |
d9b6cb56 JB |
4203 | /* set transcoder timing, panel must allow it */ |
4204 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4205 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4206 | |
303b81e0 | 4207 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4208 | |
3860b2ec VS |
4209 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4210 | ||
c98e9dcf | 4211 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4212 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
9c4edaee VS |
4213 | const struct drm_display_mode *adjusted_mode = |
4214 | &intel_crtc->config->base.adjusted_mode; | |
dfd07d72 | 4215 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4216 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4217 | temp = I915_READ(reg); |
4218 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4219 | TRANS_DP_SYNC_MASK | |
4220 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4221 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4222 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4223 | |
9c4edaee | 4224 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4225 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4226 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4227 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4228 | |
4229 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4230 | case PORT_B: |
5eddb70b | 4231 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4232 | break; |
c48b5305 | 4233 | case PORT_C: |
5eddb70b | 4234 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4235 | break; |
c48b5305 | 4236 | case PORT_D: |
5eddb70b | 4237 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4238 | break; |
4239 | default: | |
e95d41e1 | 4240 | BUG(); |
32f9d658 | 4241 | } |
2c07245f | 4242 | |
5eddb70b | 4243 | I915_WRITE(reg, temp); |
6be4a607 | 4244 | } |
b52eb4dc | 4245 | |
b8a4f404 | 4246 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4247 | } |
4248 | ||
1507e5bd PZ |
4249 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4250 | { | |
4251 | struct drm_device *dev = crtc->dev; | |
4252 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4253 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4254 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4255 | |
ab9412ba | 4256 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4257 | |
8c52b5e8 | 4258 | lpt_program_iclkip(crtc); |
1507e5bd | 4259 | |
0540e488 | 4260 | /* Set transcoder timing. */ |
275f01b2 | 4261 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4262 | |
937bb610 | 4263 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4264 | } |
4265 | ||
190f68c5 ACO |
4266 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
4267 | struct intel_crtc_state *crtc_state) | |
ee7b9f93 | 4268 | { |
e2b78267 | 4269 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 4270 | struct intel_shared_dpll *pll; |
de419ab6 | 4271 | struct intel_shared_dpll_config *shared_dpll; |
e2b78267 | 4272 | enum intel_dpll_id i; |
00490c22 | 4273 | int max = dev_priv->num_shared_dpll; |
ee7b9f93 | 4274 | |
de419ab6 ML |
4275 | shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state); |
4276 | ||
98b6bd99 DV |
4277 | if (HAS_PCH_IBX(dev_priv->dev)) { |
4278 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 4279 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 4280 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 4281 | |
46edb027 DV |
4282 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
4283 | crtc->base.base.id, pll->name); | |
98b6bd99 | 4284 | |
de419ab6 | 4285 | WARN_ON(shared_dpll[i].crtc_mask); |
f2a69f44 | 4286 | |
98b6bd99 DV |
4287 | goto found; |
4288 | } | |
4289 | ||
bcddf610 S |
4290 | if (IS_BROXTON(dev_priv->dev)) { |
4291 | /* PLL is attached to port in bxt */ | |
4292 | struct intel_encoder *encoder; | |
4293 | struct intel_digital_port *intel_dig_port; | |
4294 | ||
4295 | encoder = intel_ddi_get_crtc_new_encoder(crtc_state); | |
4296 | if (WARN_ON(!encoder)) | |
4297 | return NULL; | |
4298 | ||
4299 | intel_dig_port = enc_to_dig_port(&encoder->base); | |
4300 | /* 1:1 mapping between ports and PLLs */ | |
4301 | i = (enum intel_dpll_id)intel_dig_port->port; | |
4302 | pll = &dev_priv->shared_dplls[i]; | |
4303 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", | |
4304 | crtc->base.base.id, pll->name); | |
de419ab6 | 4305 | WARN_ON(shared_dpll[i].crtc_mask); |
bcddf610 S |
4306 | |
4307 | goto found; | |
00490c22 ML |
4308 | } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv)) |
4309 | /* Do not consider SPLL */ | |
4310 | max = 2; | |
bcddf610 | 4311 | |
00490c22 | 4312 | for (i = 0; i < max; i++) { |
e72f9fbf | 4313 | pll = &dev_priv->shared_dplls[i]; |
ee7b9f93 JB |
4314 | |
4315 | /* Only want to check enabled timings first */ | |
de419ab6 | 4316 | if (shared_dpll[i].crtc_mask == 0) |
ee7b9f93 JB |
4317 | continue; |
4318 | ||
190f68c5 | 4319 | if (memcmp(&crtc_state->dpll_hw_state, |
de419ab6 ML |
4320 | &shared_dpll[i].hw_state, |
4321 | sizeof(crtc_state->dpll_hw_state)) == 0) { | |
8bd31e67 | 4322 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", |
1e6f2ddc | 4323 | crtc->base.base.id, pll->name, |
de419ab6 | 4324 | shared_dpll[i].crtc_mask, |
8bd31e67 | 4325 | pll->active); |
ee7b9f93 JB |
4326 | goto found; |
4327 | } | |
4328 | } | |
4329 | ||
4330 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
4331 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4332 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4333 | if (shared_dpll[i].crtc_mask == 0) { |
46edb027 DV |
4334 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
4335 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
4336 | goto found; |
4337 | } | |
4338 | } | |
4339 | ||
4340 | return NULL; | |
4341 | ||
4342 | found: | |
de419ab6 ML |
4343 | if (shared_dpll[i].crtc_mask == 0) |
4344 | shared_dpll[i].hw_state = | |
4345 | crtc_state->dpll_hw_state; | |
f2a69f44 | 4346 | |
190f68c5 | 4347 | crtc_state->shared_dpll = i; |
46edb027 DV |
4348 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
4349 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 4350 | |
de419ab6 | 4351 | shared_dpll[i].crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 4352 | |
ee7b9f93 JB |
4353 | return pll; |
4354 | } | |
4355 | ||
de419ab6 | 4356 | static void intel_shared_dpll_commit(struct drm_atomic_state *state) |
8bd31e67 | 4357 | { |
de419ab6 ML |
4358 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
4359 | struct intel_shared_dpll_config *shared_dpll; | |
8bd31e67 ACO |
4360 | struct intel_shared_dpll *pll; |
4361 | enum intel_dpll_id i; | |
4362 | ||
de419ab6 ML |
4363 | if (!to_intel_atomic_state(state)->dpll_set) |
4364 | return; | |
8bd31e67 | 4365 | |
de419ab6 | 4366 | shared_dpll = to_intel_atomic_state(state)->shared_dpll; |
8bd31e67 ACO |
4367 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4368 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4369 | pll->config = shared_dpll[i]; |
8bd31e67 ACO |
4370 | } |
4371 | } | |
4372 | ||
a1520318 | 4373 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4374 | { |
4375 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 4376 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4377 | u32 temp; |
4378 | ||
4379 | temp = I915_READ(dslreg); | |
4380 | udelay(500); | |
4381 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4382 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4383 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4384 | } |
4385 | } | |
4386 | ||
86adf9d7 ML |
4387 | static int |
4388 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4389 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4390 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4391 | { |
86adf9d7 ML |
4392 | struct intel_crtc_scaler_state *scaler_state = |
4393 | &crtc_state->scaler_state; | |
4394 | struct intel_crtc *intel_crtc = | |
4395 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4396 | int need_scaling; |
6156a456 CK |
4397 | |
4398 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4399 | (src_h != dst_w || src_w != dst_h): | |
4400 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4401 | |
4402 | /* | |
4403 | * if plane is being disabled or scaler is no more required or force detach | |
4404 | * - free scaler binded to this plane/crtc | |
4405 | * - in order to do this, update crtc->scaler_usage | |
4406 | * | |
4407 | * Here scaler state in crtc_state is set free so that | |
4408 | * scaler can be assigned to other user. Actual register | |
4409 | * update to free the scaler is done in plane/panel-fit programming. | |
4410 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4411 | */ | |
86adf9d7 | 4412 | if (force_detach || !need_scaling) { |
a1b2278e | 4413 | if (*scaler_id >= 0) { |
86adf9d7 | 4414 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4415 | scaler_state->scalers[*scaler_id].in_use = 0; |
4416 | ||
86adf9d7 ML |
4417 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4418 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4419 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4420 | scaler_state->scaler_users); |
4421 | *scaler_id = -1; | |
4422 | } | |
4423 | return 0; | |
4424 | } | |
4425 | ||
4426 | /* range checks */ | |
4427 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4428 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4429 | ||
4430 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4431 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4432 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4433 | "size is out of scaler range\n", |
86adf9d7 | 4434 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4435 | return -EINVAL; |
4436 | } | |
4437 | ||
86adf9d7 ML |
4438 | /* mark this plane as a scaler user in crtc_state */ |
4439 | scaler_state->scaler_users |= (1 << scaler_user); | |
4440 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4441 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4442 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4443 | scaler_state->scaler_users); | |
4444 | ||
4445 | return 0; | |
4446 | } | |
4447 | ||
4448 | /** | |
4449 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4450 | * | |
4451 | * @state: crtc's scaler state | |
86adf9d7 ML |
4452 | * |
4453 | * Return | |
4454 | * 0 - scaler_usage updated successfully | |
4455 | * error - requested scaling cannot be supported or other error condition | |
4456 | */ | |
e435d6e5 | 4457 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 ML |
4458 | { |
4459 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); | |
7c5f93b0 | 4460 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 ML |
4461 | |
4462 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n", | |
4463 | intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX); | |
4464 | ||
e435d6e5 | 4465 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
86adf9d7 ML |
4466 | &state->scaler_state.scaler_id, DRM_ROTATE_0, |
4467 | state->pipe_src_w, state->pipe_src_h, | |
aad941d5 | 4468 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4469 | } |
4470 | ||
4471 | /** | |
4472 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4473 | * | |
4474 | * @state: crtc's scaler state | |
86adf9d7 ML |
4475 | * @plane_state: atomic plane state to update |
4476 | * | |
4477 | * Return | |
4478 | * 0 - scaler_usage updated successfully | |
4479 | * error - requested scaling cannot be supported or other error condition | |
4480 | */ | |
da20eabd ML |
4481 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4482 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4483 | { |
4484 | ||
4485 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
da20eabd ML |
4486 | struct intel_plane *intel_plane = |
4487 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4488 | struct drm_framebuffer *fb = plane_state->base.fb; |
4489 | int ret; | |
4490 | ||
4491 | bool force_detach = !fb || !plane_state->visible; | |
4492 | ||
4493 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n", | |
4494 | intel_plane->base.base.id, intel_crtc->pipe, | |
4495 | drm_plane_index(&intel_plane->base)); | |
4496 | ||
4497 | ret = skl_update_scaler(crtc_state, force_detach, | |
4498 | drm_plane_index(&intel_plane->base), | |
4499 | &plane_state->scaler_id, | |
4500 | plane_state->base.rotation, | |
4501 | drm_rect_width(&plane_state->src) >> 16, | |
4502 | drm_rect_height(&plane_state->src) >> 16, | |
4503 | drm_rect_width(&plane_state->dst), | |
4504 | drm_rect_height(&plane_state->dst)); | |
4505 | ||
4506 | if (ret || plane_state->scaler_id < 0) | |
4507 | return ret; | |
4508 | ||
a1b2278e | 4509 | /* check colorkey */ |
818ed961 | 4510 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
86adf9d7 | 4511 | DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed", |
818ed961 | 4512 | intel_plane->base.base.id); |
a1b2278e CK |
4513 | return -EINVAL; |
4514 | } | |
4515 | ||
4516 | /* Check src format */ | |
86adf9d7 ML |
4517 | switch (fb->pixel_format) { |
4518 | case DRM_FORMAT_RGB565: | |
4519 | case DRM_FORMAT_XBGR8888: | |
4520 | case DRM_FORMAT_XRGB8888: | |
4521 | case DRM_FORMAT_ABGR8888: | |
4522 | case DRM_FORMAT_ARGB8888: | |
4523 | case DRM_FORMAT_XRGB2101010: | |
4524 | case DRM_FORMAT_XBGR2101010: | |
4525 | case DRM_FORMAT_YUYV: | |
4526 | case DRM_FORMAT_YVYU: | |
4527 | case DRM_FORMAT_UYVY: | |
4528 | case DRM_FORMAT_VYUY: | |
4529 | break; | |
4530 | default: | |
4531 | DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n", | |
4532 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); | |
4533 | return -EINVAL; | |
a1b2278e CK |
4534 | } |
4535 | ||
a1b2278e CK |
4536 | return 0; |
4537 | } | |
4538 | ||
e435d6e5 ML |
4539 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4540 | { | |
4541 | int i; | |
4542 | ||
4543 | for (i = 0; i < crtc->num_scalers; i++) | |
4544 | skl_detach_scaler(crtc, i); | |
4545 | } | |
4546 | ||
4547 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4548 | { |
4549 | struct drm_device *dev = crtc->base.dev; | |
4550 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4551 | int pipe = crtc->pipe; | |
a1b2278e CK |
4552 | struct intel_crtc_scaler_state *scaler_state = |
4553 | &crtc->config->scaler_state; | |
4554 | ||
4555 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4556 | ||
6e3c9717 | 4557 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4558 | int id; |
4559 | ||
4560 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4561 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4562 | return; | |
4563 | } | |
4564 | ||
4565 | id = scaler_state->scaler_id; | |
4566 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4567 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4568 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4569 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4570 | ||
4571 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4572 | } |
4573 | } | |
4574 | ||
b074cec8 JB |
4575 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4576 | { | |
4577 | struct drm_device *dev = crtc->base.dev; | |
4578 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4579 | int pipe = crtc->pipe; | |
4580 | ||
6e3c9717 | 4581 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4582 | /* Force use of hard-coded filter coefficients |
4583 | * as some pre-programmed values are broken, | |
4584 | * e.g. x201. | |
4585 | */ | |
4586 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4587 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4588 | PF_PIPE_SEL_IVB(pipe)); | |
4589 | else | |
4590 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4591 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4592 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4593 | } |
4594 | } | |
4595 | ||
20bc8673 | 4596 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4597 | { |
cea165c3 VS |
4598 | struct drm_device *dev = crtc->base.dev; |
4599 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4600 | |
6e3c9717 | 4601 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4602 | return; |
4603 | ||
cea165c3 VS |
4604 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4605 | intel_wait_for_vblank(dev, crtc->pipe); | |
4606 | ||
d77e4531 | 4607 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4608 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4609 | mutex_lock(&dev_priv->rps.hw_lock); |
4610 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4611 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4612 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4613 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4614 | * mailbox." Moreover, the mailbox may return a bogus state, |
4615 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4616 | */ |
4617 | } else { | |
4618 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4619 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4620 | * is essentially intel_wait_for_vblank. If we don't have this | |
4621 | * and don't wait for vblanks until the end of crtc_enable, then | |
4622 | * the HW state readout code will complain that the expected | |
4623 | * IPS_CTL value is not the one we read. */ | |
4624 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4625 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4626 | } | |
d77e4531 PZ |
4627 | } |
4628 | ||
20bc8673 | 4629 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4630 | { |
4631 | struct drm_device *dev = crtc->base.dev; | |
4632 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4633 | ||
6e3c9717 | 4634 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4635 | return; |
4636 | ||
4637 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4638 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4639 | mutex_lock(&dev_priv->rps.hw_lock); |
4640 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4641 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4642 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4643 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4644 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4645 | } else { |
2a114cc1 | 4646 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4647 | POSTING_READ(IPS_CTL); |
4648 | } | |
d77e4531 PZ |
4649 | |
4650 | /* We need to wait for a vblank before we can disable the plane. */ | |
4651 | intel_wait_for_vblank(dev, crtc->pipe); | |
4652 | } | |
4653 | ||
4654 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4655 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4656 | { | |
4657 | struct drm_device *dev = crtc->dev; | |
4658 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4659 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4660 | enum pipe pipe = intel_crtc->pipe; | |
d77e4531 PZ |
4661 | int i; |
4662 | bool reenable_ips = false; | |
4663 | ||
4664 | /* The clocks have to be on to load the palette. */ | |
53d9f4e9 | 4665 | if (!crtc->state->active) |
d77e4531 PZ |
4666 | return; |
4667 | ||
50360403 | 4668 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) { |
a65347ba | 4669 | if (intel_crtc->config->has_dsi_encoder) |
d77e4531 PZ |
4670 | assert_dsi_pll_enabled(dev_priv); |
4671 | else | |
4672 | assert_pll_enabled(dev_priv, pipe); | |
4673 | } | |
4674 | ||
d77e4531 PZ |
4675 | /* Workaround : Do not read or write the pipe palette/gamma data while |
4676 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4677 | */ | |
6e3c9717 | 4678 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
d77e4531 PZ |
4679 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4680 | GAMMA_MODE_MODE_SPLIT)) { | |
4681 | hsw_disable_ips(intel_crtc); | |
4682 | reenable_ips = true; | |
4683 | } | |
4684 | ||
4685 | for (i = 0; i < 256; i++) { | |
f0f59a00 | 4686 | i915_reg_t palreg; |
f65a9c5b VS |
4687 | |
4688 | if (HAS_GMCH_DISPLAY(dev)) | |
4689 | palreg = PALETTE(pipe, i); | |
4690 | else | |
4691 | palreg = LGC_PALETTE(pipe, i); | |
4692 | ||
4693 | I915_WRITE(palreg, | |
d77e4531 PZ |
4694 | (intel_crtc->lut_r[i] << 16) | |
4695 | (intel_crtc->lut_g[i] << 8) | | |
4696 | intel_crtc->lut_b[i]); | |
4697 | } | |
4698 | ||
4699 | if (reenable_ips) | |
4700 | hsw_enable_ips(intel_crtc); | |
4701 | } | |
4702 | ||
7cac945f | 4703 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4704 | { |
7cac945f | 4705 | if (intel_crtc->overlay) { |
d3eedb1a VS |
4706 | struct drm_device *dev = intel_crtc->base.dev; |
4707 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4708 | ||
4709 | mutex_lock(&dev->struct_mutex); | |
4710 | dev_priv->mm.interruptible = false; | |
4711 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4712 | dev_priv->mm.interruptible = true; | |
4713 | mutex_unlock(&dev->struct_mutex); | |
4714 | } | |
4715 | ||
4716 | /* Let userspace switch the overlay on again. In most cases userspace | |
4717 | * has to recompute where to put it anyway. | |
4718 | */ | |
4719 | } | |
4720 | ||
87d4300a ML |
4721 | /** |
4722 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4723 | * @crtc: the CRTC whose primary plane was just enabled | |
4724 | * | |
4725 | * Performs potentially sleeping operations that must be done after the primary | |
4726 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4727 | * called due to an explicit primary plane update, or due to an implicit | |
4728 | * re-enable that is caused when a sprite plane is updated to no longer | |
4729 | * completely hide the primary plane. | |
4730 | */ | |
4731 | static void | |
4732 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4733 | { |
4734 | struct drm_device *dev = crtc->dev; | |
87d4300a | 4735 | struct drm_i915_private *dev_priv = dev->dev_private; |
a5c4d7bc VS |
4736 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4737 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4738 | |
87d4300a ML |
4739 | /* |
4740 | * FIXME IPS should be fine as long as one plane is | |
4741 | * enabled, but in practice it seems to have problems | |
4742 | * when going from primary only to sprite only and vice | |
4743 | * versa. | |
4744 | */ | |
a5c4d7bc VS |
4745 | hsw_enable_ips(intel_crtc); |
4746 | ||
f99d7069 | 4747 | /* |
87d4300a ML |
4748 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4749 | * So don't enable underrun reporting before at least some planes | |
4750 | * are enabled. | |
4751 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4752 | * but leave the pipe running. | |
f99d7069 | 4753 | */ |
87d4300a ML |
4754 | if (IS_GEN2(dev)) |
4755 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4756 | ||
aca7b684 VS |
4757 | /* Underruns don't always raise interrupts, so check manually. */ |
4758 | intel_check_cpu_fifo_underruns(dev_priv); | |
4759 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4760 | } |
4761 | ||
87d4300a ML |
4762 | /** |
4763 | * intel_pre_disable_primary - Perform operations before disabling primary plane | |
4764 | * @crtc: the CRTC whose primary plane is to be disabled | |
4765 | * | |
4766 | * Performs potentially sleeping operations that must be done before the | |
4767 | * primary plane is disabled, such as updating FBC and IPS. Note that this may | |
4768 | * be called due to an explicit primary plane update, or due to an implicit | |
4769 | * disable that is caused when a sprite plane completely hides the primary | |
4770 | * plane. | |
4771 | */ | |
4772 | static void | |
4773 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4774 | { |
4775 | struct drm_device *dev = crtc->dev; | |
4776 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4777 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4778 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4779 | |
87d4300a ML |
4780 | /* |
4781 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4782 | * So diasble underrun reporting before all the planes get disabled. | |
4783 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4784 | * but leave the pipe running. | |
4785 | */ | |
4786 | if (IS_GEN2(dev)) | |
4787 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4788 | |
87d4300a ML |
4789 | /* |
4790 | * Vblank time updates from the shadow to live plane control register | |
4791 | * are blocked if the memory self-refresh mode is active at that | |
4792 | * moment. So to make sure the plane gets truly disabled, disable | |
4793 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4794 | * will be checked/applied by the HW only at the next frame start | |
4795 | * event which is after the vblank start event, so we need to have a | |
4796 | * wait-for-vblank between disabling the plane and the pipe. | |
4797 | */ | |
262cd2e1 | 4798 | if (HAS_GMCH_DISPLAY(dev)) { |
87d4300a | 4799 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 VS |
4800 | dev_priv->wm.vlv.cxsr = false; |
4801 | intel_wait_for_vblank(dev, pipe); | |
4802 | } | |
87d4300a | 4803 | |
87d4300a ML |
4804 | /* |
4805 | * FIXME IPS should be fine as long as one plane is | |
4806 | * enabled, but in practice it seems to have problems | |
4807 | * when going from primary only to sprite only and vice | |
4808 | * versa. | |
4809 | */ | |
a5c4d7bc | 4810 | hsw_disable_ips(intel_crtc); |
87d4300a ML |
4811 | } |
4812 | ||
ac21b225 ML |
4813 | static void intel_post_plane_update(struct intel_crtc *crtc) |
4814 | { | |
4815 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; | |
92826fcd ML |
4816 | struct intel_crtc_state *pipe_config = |
4817 | to_intel_crtc_state(crtc->base.state); | |
ac21b225 | 4818 | struct drm_device *dev = crtc->base.dev; |
ac21b225 ML |
4819 | |
4820 | if (atomic->wait_vblank) | |
4821 | intel_wait_for_vblank(dev, crtc->pipe); | |
4822 | ||
4823 | intel_frontbuffer_flip(dev, atomic->fb_bits); | |
4824 | ||
ab1d3a0e | 4825 | crtc->wm.cxsr_allowed = true; |
852eb00d | 4826 | |
b9001114 | 4827 | if (pipe_config->wm_changed && pipe_config->base.active) |
f015c551 VS |
4828 | intel_update_watermarks(&crtc->base); |
4829 | ||
c80ac854 | 4830 | if (atomic->update_fbc) |
754d1133 | 4831 | intel_fbc_update(crtc); |
ac21b225 ML |
4832 | |
4833 | if (atomic->post_enable_primary) | |
4834 | intel_post_enable_primary(&crtc->base); | |
4835 | ||
ac21b225 ML |
4836 | memset(atomic, 0, sizeof(*atomic)); |
4837 | } | |
4838 | ||
4839 | static void intel_pre_plane_update(struct intel_crtc *crtc) | |
4840 | { | |
4841 | struct drm_device *dev = crtc->base.dev; | |
eddfcbcd | 4842 | struct drm_i915_private *dev_priv = dev->dev_private; |
ac21b225 | 4843 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; |
ab1d3a0e ML |
4844 | struct intel_crtc_state *pipe_config = |
4845 | to_intel_crtc_state(crtc->base.state); | |
ac21b225 | 4846 | |
c80ac854 | 4847 | if (atomic->disable_fbc) |
d029bcad | 4848 | intel_fbc_deactivate(crtc); |
ac21b225 | 4849 | |
066cf55b RV |
4850 | if (crtc->atomic.disable_ips) |
4851 | hsw_disable_ips(crtc); | |
4852 | ||
ac21b225 ML |
4853 | if (atomic->pre_disable_primary) |
4854 | intel_pre_disable_primary(&crtc->base); | |
852eb00d | 4855 | |
ab1d3a0e | 4856 | if (pipe_config->disable_cxsr) { |
852eb00d VS |
4857 | crtc->wm.cxsr_allowed = false; |
4858 | intel_set_memory_cxsr(dev_priv, false); | |
4859 | } | |
92826fcd ML |
4860 | |
4861 | if (!needs_modeset(&pipe_config->base) && pipe_config->wm_changed) | |
4862 | intel_update_watermarks(&crtc->base); | |
ac21b225 ML |
4863 | } |
4864 | ||
d032ffa0 | 4865 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
4866 | { |
4867 | struct drm_device *dev = crtc->dev; | |
4868 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 4869 | struct drm_plane *p; |
87d4300a ML |
4870 | int pipe = intel_crtc->pipe; |
4871 | ||
7cac945f | 4872 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 4873 | |
d032ffa0 ML |
4874 | drm_for_each_plane_mask(p, dev, plane_mask) |
4875 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 4876 | |
f99d7069 DV |
4877 | /* |
4878 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4879 | * to compute the mask of flip planes precisely. For the time being | |
4880 | * consider this a flip to a NULL plane. | |
4881 | */ | |
4882 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4883 | } |
4884 | ||
f67a559d JB |
4885 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4886 | { | |
4887 | struct drm_device *dev = crtc->dev; | |
4888 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4889 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4890 | struct intel_encoder *encoder; |
f67a559d | 4891 | int pipe = intel_crtc->pipe; |
f67a559d | 4892 | |
53d9f4e9 | 4893 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
4894 | return; |
4895 | ||
81b088ca VS |
4896 | if (intel_crtc->config->has_pch_encoder) |
4897 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
4898 | ||
6e3c9717 | 4899 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4900 | intel_prepare_shared_dpll(intel_crtc); |
4901 | ||
6e3c9717 | 4902 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4903 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4904 | |
4905 | intel_set_pipe_timings(intel_crtc); | |
4906 | ||
6e3c9717 | 4907 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4908 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4909 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4910 | } |
4911 | ||
4912 | ironlake_set_pipeconf(crtc); | |
4913 | ||
f67a559d | 4914 | intel_crtc->active = true; |
8664281b | 4915 | |
a72e4c9f | 4916 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
8664281b | 4917 | |
f6736a1a | 4918 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4919 | if (encoder->pre_enable) |
4920 | encoder->pre_enable(encoder); | |
f67a559d | 4921 | |
6e3c9717 | 4922 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4923 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4924 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4925 | * enabling. */ | |
88cefb6c | 4926 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4927 | } else { |
4928 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4929 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4930 | } | |
f67a559d | 4931 | |
b074cec8 | 4932 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4933 | |
9c54c0dd JB |
4934 | /* |
4935 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4936 | * clocks enabled | |
4937 | */ | |
4938 | intel_crtc_load_lut(crtc); | |
4939 | ||
f37fcc2a | 4940 | intel_update_watermarks(crtc); |
e1fdc473 | 4941 | intel_enable_pipe(intel_crtc); |
f67a559d | 4942 | |
6e3c9717 | 4943 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4944 | ironlake_pch_enable(crtc); |
c98e9dcf | 4945 | |
f9b61ff6 DV |
4946 | assert_vblank_disabled(crtc); |
4947 | drm_crtc_vblank_on(crtc); | |
4948 | ||
fa5c73b1 DV |
4949 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4950 | encoder->enable(encoder); | |
61b77ddd DV |
4951 | |
4952 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4953 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
4954 | |
4955 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
4956 | if (intel_crtc->config->has_pch_encoder) | |
4957 | intel_wait_for_vblank(dev, pipe); | |
4958 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
d029bcad PZ |
4959 | |
4960 | intel_fbc_enable(intel_crtc); | |
6be4a607 JB |
4961 | } |
4962 | ||
42db64ef PZ |
4963 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4964 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4965 | { | |
f5adf94e | 4966 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4967 | } |
4968 | ||
4f771f10 PZ |
4969 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4970 | { | |
4971 | struct drm_device *dev = crtc->dev; | |
4972 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4973 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4974 | struct intel_encoder *encoder; | |
99d736a2 ML |
4975 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4976 | struct intel_crtc_state *pipe_config = | |
4977 | to_intel_crtc_state(crtc->state); | |
4f771f10 | 4978 | |
53d9f4e9 | 4979 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
4980 | return; |
4981 | ||
81b088ca VS |
4982 | if (intel_crtc->config->has_pch_encoder) |
4983 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
4984 | false); | |
4985 | ||
df8ad70c DV |
4986 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4987 | intel_enable_shared_dpll(intel_crtc); | |
4988 | ||
6e3c9717 | 4989 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4990 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 DV |
4991 | |
4992 | intel_set_pipe_timings(intel_crtc); | |
4993 | ||
6e3c9717 ACO |
4994 | if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
4995 | I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), | |
4996 | intel_crtc->config->pixel_multiplier - 1); | |
ebb69c95 CT |
4997 | } |
4998 | ||
6e3c9717 | 4999 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 5000 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5001 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
5002 | } |
5003 | ||
5004 | haswell_set_pipeconf(crtc); | |
5005 | ||
5006 | intel_set_pipe_csc(crtc); | |
5007 | ||
4f771f10 | 5008 | intel_crtc->active = true; |
8664281b | 5009 | |
6b698516 DV |
5010 | if (intel_crtc->config->has_pch_encoder) |
5011 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5012 | else | |
5013 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5014 | ||
7d4aefd0 | 5015 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 PZ |
5016 | if (encoder->pre_enable) |
5017 | encoder->pre_enable(encoder); | |
7d4aefd0 | 5018 | } |
4f771f10 | 5019 | |
d2d65408 | 5020 | if (intel_crtc->config->has_pch_encoder) |
4fe9467d | 5021 | dev_priv->display.fdi_link_train(crtc); |
4fe9467d | 5022 | |
a65347ba | 5023 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5024 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 5025 | |
1c132b44 | 5026 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5027 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 5028 | else |
1c132b44 | 5029 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
5030 | |
5031 | /* | |
5032 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5033 | * clocks enabled | |
5034 | */ | |
5035 | intel_crtc_load_lut(crtc); | |
5036 | ||
1f544388 | 5037 | intel_ddi_set_pipe_settings(crtc); |
a65347ba | 5038 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5039 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 5040 | |
f37fcc2a | 5041 | intel_update_watermarks(crtc); |
e1fdc473 | 5042 | intel_enable_pipe(intel_crtc); |
42db64ef | 5043 | |
6e3c9717 | 5044 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 5045 | lpt_pch_enable(crtc); |
4f771f10 | 5046 | |
a65347ba | 5047 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
5048 | intel_ddi_set_vc_payload_alloc(crtc, true); |
5049 | ||
f9b61ff6 DV |
5050 | assert_vblank_disabled(crtc); |
5051 | drm_crtc_vblank_on(crtc); | |
5052 | ||
8807e55b | 5053 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 5054 | encoder->enable(encoder); |
8807e55b JN |
5055 | intel_opregion_notify_encoder(encoder, true); |
5056 | } | |
4f771f10 | 5057 | |
6b698516 DV |
5058 | if (intel_crtc->config->has_pch_encoder) { |
5059 | intel_wait_for_vblank(dev, pipe); | |
5060 | intel_wait_for_vblank(dev, pipe); | |
5061 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
d2d65408 VS |
5062 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5063 | true); | |
6b698516 | 5064 | } |
d2d65408 | 5065 | |
e4916946 PZ |
5066 | /* If we change the relative order between pipe/planes enabling, we need |
5067 | * to change the workaround. */ | |
99d736a2 ML |
5068 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
5069 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { | |
5070 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5071 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5072 | } | |
d029bcad PZ |
5073 | |
5074 | intel_fbc_enable(intel_crtc); | |
4f771f10 PZ |
5075 | } |
5076 | ||
bfd16b2a | 5077 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
5078 | { |
5079 | struct drm_device *dev = crtc->base.dev; | |
5080 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5081 | int pipe = crtc->pipe; | |
5082 | ||
5083 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5084 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5085 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5086 | I915_WRITE(PF_CTL(pipe), 0); |
5087 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5088 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5089 | } | |
5090 | } | |
5091 | ||
6be4a607 JB |
5092 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
5093 | { | |
5094 | struct drm_device *dev = crtc->dev; | |
5095 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5096 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5097 | struct intel_encoder *encoder; |
6be4a607 | 5098 | int pipe = intel_crtc->pipe; |
b52eb4dc | 5099 | |
37ca8d4c VS |
5100 | if (intel_crtc->config->has_pch_encoder) |
5101 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
5102 | ||
ea9d758d DV |
5103 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5104 | encoder->disable(encoder); | |
5105 | ||
f9b61ff6 DV |
5106 | drm_crtc_vblank_off(crtc); |
5107 | assert_vblank_disabled(crtc); | |
5108 | ||
3860b2ec VS |
5109 | /* |
5110 | * Sometimes spurious CPU pipe underruns happen when the | |
5111 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
5112 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
5113 | */ | |
5114 | if (intel_crtc->config->has_pch_encoder) | |
5115 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5116 | ||
575f7ab7 | 5117 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5118 | |
bfd16b2a | 5119 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5120 | |
3860b2ec | 5121 | if (intel_crtc->config->has_pch_encoder) { |
5a74f70a | 5122 | ironlake_fdi_disable(crtc); |
3860b2ec VS |
5123 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5124 | } | |
5a74f70a | 5125 | |
bf49ec8c DV |
5126 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5127 | if (encoder->post_disable) | |
5128 | encoder->post_disable(encoder); | |
2c07245f | 5129 | |
6e3c9717 | 5130 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5131 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5132 | |
d925c59a | 5133 | if (HAS_PCH_CPT(dev)) { |
f0f59a00 VS |
5134 | i915_reg_t reg; |
5135 | u32 temp; | |
5136 | ||
d925c59a DV |
5137 | /* disable TRANS_DP_CTL */ |
5138 | reg = TRANS_DP_CTL(pipe); | |
5139 | temp = I915_READ(reg); | |
5140 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5141 | TRANS_DP_PORT_SEL_MASK); | |
5142 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5143 | I915_WRITE(reg, temp); | |
5144 | ||
5145 | /* disable DPLL_SEL */ | |
5146 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5147 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5148 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5149 | } |
e3421a18 | 5150 | |
d925c59a DV |
5151 | ironlake_fdi_pll_disable(intel_crtc); |
5152 | } | |
81b088ca VS |
5153 | |
5154 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
d029bcad PZ |
5155 | |
5156 | intel_fbc_disable_crtc(intel_crtc); | |
6be4a607 | 5157 | } |
1b3c7a47 | 5158 | |
4f771f10 | 5159 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5160 | { |
4f771f10 PZ |
5161 | struct drm_device *dev = crtc->dev; |
5162 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 5163 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5164 | struct intel_encoder *encoder; |
6e3c9717 | 5165 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5166 | |
d2d65408 VS |
5167 | if (intel_crtc->config->has_pch_encoder) |
5168 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5169 | false); | |
5170 | ||
8807e55b JN |
5171 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5172 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5173 | encoder->disable(encoder); |
8807e55b | 5174 | } |
4f771f10 | 5175 | |
f9b61ff6 DV |
5176 | drm_crtc_vblank_off(crtc); |
5177 | assert_vblank_disabled(crtc); | |
5178 | ||
575f7ab7 | 5179 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5180 | |
6e3c9717 | 5181 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5182 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5183 | ||
a65347ba | 5184 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5185 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5186 | |
1c132b44 | 5187 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5188 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5189 | else |
bfd16b2a | 5190 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5191 | |
a65347ba | 5192 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5193 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5194 | |
97b040aa ID |
5195 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5196 | if (encoder->post_disable) | |
5197 | encoder->post_disable(encoder); | |
81b088ca | 5198 | |
92966a37 VS |
5199 | if (intel_crtc->config->has_pch_encoder) { |
5200 | lpt_disable_pch_transcoder(dev_priv); | |
503a74e9 | 5201 | lpt_disable_iclkip(dev_priv); |
92966a37 VS |
5202 | intel_ddi_fdi_disable(crtc); |
5203 | ||
81b088ca VS |
5204 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5205 | true); | |
92966a37 | 5206 | } |
d029bcad PZ |
5207 | |
5208 | intel_fbc_disable_crtc(intel_crtc); | |
4f771f10 PZ |
5209 | } |
5210 | ||
2dd24552 JB |
5211 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5212 | { | |
5213 | struct drm_device *dev = crtc->base.dev; | |
5214 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 5215 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5216 | |
681a8504 | 5217 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5218 | return; |
5219 | ||
2dd24552 | 5220 | /* |
c0b03411 DV |
5221 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5222 | * according to register description and PRM. | |
2dd24552 | 5223 | */ |
c0b03411 DV |
5224 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5225 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5226 | |
b074cec8 JB |
5227 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5228 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5229 | |
5230 | /* Border color in case we don't scale up to the full screen. Black by | |
5231 | * default, change to something else for debugging. */ | |
5232 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5233 | } |
5234 | ||
d05410f9 DA |
5235 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5236 | { | |
5237 | switch (port) { | |
5238 | case PORT_A: | |
6331a704 | 5239 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5240 | case PORT_B: |
6331a704 | 5241 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5242 | case PORT_C: |
6331a704 | 5243 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5244 | case PORT_D: |
6331a704 | 5245 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5246 | case PORT_E: |
6331a704 | 5247 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5248 | default: |
b9fec167 | 5249 | MISSING_CASE(port); |
d05410f9 DA |
5250 | return POWER_DOMAIN_PORT_OTHER; |
5251 | } | |
5252 | } | |
5253 | ||
25f78f58 VS |
5254 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
5255 | { | |
5256 | switch (port) { | |
5257 | case PORT_A: | |
5258 | return POWER_DOMAIN_AUX_A; | |
5259 | case PORT_B: | |
5260 | return POWER_DOMAIN_AUX_B; | |
5261 | case PORT_C: | |
5262 | return POWER_DOMAIN_AUX_C; | |
5263 | case PORT_D: | |
5264 | return POWER_DOMAIN_AUX_D; | |
5265 | case PORT_E: | |
5266 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5267 | return POWER_DOMAIN_AUX_D; | |
5268 | default: | |
b9fec167 | 5269 | MISSING_CASE(port); |
25f78f58 VS |
5270 | return POWER_DOMAIN_AUX_A; |
5271 | } | |
5272 | } | |
5273 | ||
319be8ae ID |
5274 | enum intel_display_power_domain |
5275 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5276 | { | |
5277 | struct drm_device *dev = intel_encoder->base.dev; | |
5278 | struct intel_digital_port *intel_dig_port; | |
5279 | ||
5280 | switch (intel_encoder->type) { | |
5281 | case INTEL_OUTPUT_UNKNOWN: | |
5282 | /* Only DDI platforms should ever use this output type */ | |
5283 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5284 | case INTEL_OUTPUT_DISPLAYPORT: | |
5285 | case INTEL_OUTPUT_HDMI: | |
5286 | case INTEL_OUTPUT_EDP: | |
5287 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5288 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5289 | case INTEL_OUTPUT_DP_MST: |
5290 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5291 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5292 | case INTEL_OUTPUT_ANALOG: |
5293 | return POWER_DOMAIN_PORT_CRT; | |
5294 | case INTEL_OUTPUT_DSI: | |
5295 | return POWER_DOMAIN_PORT_DSI; | |
5296 | default: | |
5297 | return POWER_DOMAIN_PORT_OTHER; | |
5298 | } | |
5299 | } | |
5300 | ||
25f78f58 VS |
5301 | enum intel_display_power_domain |
5302 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) | |
5303 | { | |
5304 | struct drm_device *dev = intel_encoder->base.dev; | |
5305 | struct intel_digital_port *intel_dig_port; | |
5306 | ||
5307 | switch (intel_encoder->type) { | |
5308 | case INTEL_OUTPUT_UNKNOWN: | |
651174a4 ID |
5309 | case INTEL_OUTPUT_HDMI: |
5310 | /* | |
5311 | * Only DDI platforms should ever use these output types. | |
5312 | * We can get here after the HDMI detect code has already set | |
5313 | * the type of the shared encoder. Since we can't be sure | |
5314 | * what's the status of the given connectors, play safe and | |
5315 | * run the DP detection too. | |
5316 | */ | |
25f78f58 VS |
5317 | WARN_ON_ONCE(!HAS_DDI(dev)); |
5318 | case INTEL_OUTPUT_DISPLAYPORT: | |
5319 | case INTEL_OUTPUT_EDP: | |
5320 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
5321 | return port_to_aux_power_domain(intel_dig_port->port); | |
5322 | case INTEL_OUTPUT_DP_MST: | |
5323 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5324 | return port_to_aux_power_domain(intel_dig_port->port); | |
5325 | default: | |
b9fec167 | 5326 | MISSING_CASE(intel_encoder->type); |
25f78f58 VS |
5327 | return POWER_DOMAIN_AUX_A; |
5328 | } | |
5329 | } | |
5330 | ||
319be8ae | 5331 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) |
77d22dca | 5332 | { |
319be8ae ID |
5333 | struct drm_device *dev = crtc->dev; |
5334 | struct intel_encoder *intel_encoder; | |
5335 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5336 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca | 5337 | unsigned long mask; |
1a70a728 | 5338 | enum transcoder transcoder = intel_crtc->config->cpu_transcoder; |
77d22dca | 5339 | |
292b990e ML |
5340 | if (!crtc->state->active) |
5341 | return 0; | |
5342 | ||
77d22dca ID |
5343 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5344 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
6e3c9717 ACO |
5345 | if (intel_crtc->config->pch_pfit.enabled || |
5346 | intel_crtc->config->pch_pfit.force_thru) | |
77d22dca ID |
5347 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5348 | ||
319be8ae ID |
5349 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
5350 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
5351 | ||
77d22dca ID |
5352 | return mask; |
5353 | } | |
5354 | ||
292b990e | 5355 | static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc) |
77d22dca | 5356 | { |
292b990e ML |
5357 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5358 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5359 | enum intel_display_power_domain domain; | |
5360 | unsigned long domains, new_domains, old_domains; | |
77d22dca | 5361 | |
292b990e ML |
5362 | old_domains = intel_crtc->enabled_power_domains; |
5363 | intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc); | |
77d22dca | 5364 | |
292b990e ML |
5365 | domains = new_domains & ~old_domains; |
5366 | ||
5367 | for_each_power_domain(domain, domains) | |
5368 | intel_display_power_get(dev_priv, domain); | |
5369 | ||
5370 | return old_domains & ~new_domains; | |
5371 | } | |
5372 | ||
5373 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5374 | unsigned long domains) | |
5375 | { | |
5376 | enum intel_display_power_domain domain; | |
5377 | ||
5378 | for_each_power_domain(domain, domains) | |
5379 | intel_display_power_put(dev_priv, domain); | |
5380 | } | |
77d22dca | 5381 | |
292b990e ML |
5382 | static void modeset_update_crtc_power_domains(struct drm_atomic_state *state) |
5383 | { | |
1a617b77 | 5384 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
292b990e ML |
5385 | struct drm_device *dev = state->dev; |
5386 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5387 | unsigned long put_domains[I915_MAX_PIPES] = {}; | |
5388 | struct drm_crtc_state *crtc_state; | |
5389 | struct drm_crtc *crtc; | |
5390 | int i; | |
77d22dca | 5391 | |
292b990e ML |
5392 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
5393 | if (needs_modeset(crtc->state)) | |
5394 | put_domains[to_intel_crtc(crtc)->pipe] = | |
5395 | modeset_get_crtc_power_domains(crtc); | |
77d22dca ID |
5396 | } |
5397 | ||
1a617b77 ML |
5398 | if (dev_priv->display.modeset_commit_cdclk && |
5399 | intel_state->dev_cdclk != dev_priv->cdclk_freq) | |
5400 | dev_priv->display.modeset_commit_cdclk(state); | |
50f6e502 | 5401 | |
292b990e ML |
5402 | for (i = 0; i < I915_MAX_PIPES; i++) |
5403 | if (put_domains[i]) | |
5404 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
77d22dca ID |
5405 | } |
5406 | ||
adafdc6f MK |
5407 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5408 | { | |
5409 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5410 | ||
5411 | if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5412 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
5413 | return max_cdclk_freq; | |
5414 | else if (IS_CHERRYVIEW(dev_priv)) | |
5415 | return max_cdclk_freq*95/100; | |
5416 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5417 | return 2*max_cdclk_freq*90/100; | |
5418 | else | |
5419 | return max_cdclk_freq*90/100; | |
5420 | } | |
5421 | ||
560a7ae4 DL |
5422 | static void intel_update_max_cdclk(struct drm_device *dev) |
5423 | { | |
5424 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5425 | ||
ef11bdb3 | 5426 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
560a7ae4 DL |
5427 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
5428 | ||
5429 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) | |
5430 | dev_priv->max_cdclk_freq = 675000; | |
5431 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) | |
5432 | dev_priv->max_cdclk_freq = 540000; | |
5433 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) | |
5434 | dev_priv->max_cdclk_freq = 450000; | |
5435 | else | |
5436 | dev_priv->max_cdclk_freq = 337500; | |
5437 | } else if (IS_BROADWELL(dev)) { | |
5438 | /* | |
5439 | * FIXME with extra cooling we can allow | |
5440 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5441 | * How can we know if extra cooling is | |
5442 | * available? PCI ID, VTB, something else? | |
5443 | */ | |
5444 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5445 | dev_priv->max_cdclk_freq = 450000; | |
5446 | else if (IS_BDW_ULX(dev)) | |
5447 | dev_priv->max_cdclk_freq = 450000; | |
5448 | else if (IS_BDW_ULT(dev)) | |
5449 | dev_priv->max_cdclk_freq = 540000; | |
5450 | else | |
5451 | dev_priv->max_cdclk_freq = 675000; | |
0904deaf MK |
5452 | } else if (IS_CHERRYVIEW(dev)) { |
5453 | dev_priv->max_cdclk_freq = 320000; | |
560a7ae4 DL |
5454 | } else if (IS_VALLEYVIEW(dev)) { |
5455 | dev_priv->max_cdclk_freq = 400000; | |
5456 | } else { | |
5457 | /* otherwise assume cdclk is fixed */ | |
5458 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5459 | } | |
5460 | ||
adafdc6f MK |
5461 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5462 | ||
560a7ae4 DL |
5463 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5464 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5465 | |
5466 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5467 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5468 | } |
5469 | ||
5470 | static void intel_update_cdclk(struct drm_device *dev) | |
5471 | { | |
5472 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5473 | ||
5474 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
5475 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5476 | dev_priv->cdclk_freq); | |
5477 | ||
5478 | /* | |
5479 | * Program the gmbus_freq based on the cdclk frequency. | |
5480 | * BSpec erroneously claims we should aim for 4MHz, but | |
5481 | * in fact 1MHz is the correct frequency. | |
5482 | */ | |
666a4537 | 5483 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
560a7ae4 DL |
5484 | /* |
5485 | * Program the gmbus_freq based on the cdclk frequency. | |
5486 | * BSpec erroneously claims we should aim for 4MHz, but | |
5487 | * in fact 1MHz is the correct frequency. | |
5488 | */ | |
5489 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); | |
5490 | } | |
5491 | ||
5492 | if (dev_priv->max_cdclk_freq == 0) | |
5493 | intel_update_max_cdclk(dev); | |
5494 | } | |
5495 | ||
70d0c574 | 5496 | static void broxton_set_cdclk(struct drm_device *dev, int frequency) |
f8437dd1 VK |
5497 | { |
5498 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5499 | uint32_t divider; | |
5500 | uint32_t ratio; | |
5501 | uint32_t current_freq; | |
5502 | int ret; | |
5503 | ||
5504 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ | |
5505 | switch (frequency) { | |
5506 | case 144000: | |
5507 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
5508 | ratio = BXT_DE_PLL_RATIO(60); | |
5509 | break; | |
5510 | case 288000: | |
5511 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
5512 | ratio = BXT_DE_PLL_RATIO(60); | |
5513 | break; | |
5514 | case 384000: | |
5515 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
5516 | ratio = BXT_DE_PLL_RATIO(60); | |
5517 | break; | |
5518 | case 576000: | |
5519 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5520 | ratio = BXT_DE_PLL_RATIO(60); | |
5521 | break; | |
5522 | case 624000: | |
5523 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5524 | ratio = BXT_DE_PLL_RATIO(65); | |
5525 | break; | |
5526 | case 19200: | |
5527 | /* | |
5528 | * Bypass frequency with DE PLL disabled. Init ratio, divider | |
5529 | * to suppress GCC warning. | |
5530 | */ | |
5531 | ratio = 0; | |
5532 | divider = 0; | |
5533 | break; | |
5534 | default: | |
5535 | DRM_ERROR("unsupported CDCLK freq %d", frequency); | |
5536 | ||
5537 | return; | |
5538 | } | |
5539 | ||
5540 | mutex_lock(&dev_priv->rps.hw_lock); | |
5541 | /* Inform power controller of upcoming frequency change */ | |
5542 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5543 | 0x80000000); | |
5544 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5545 | ||
5546 | if (ret) { | |
5547 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
5548 | ret, frequency); | |
5549 | return; | |
5550 | } | |
5551 | ||
5552 | current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; | |
5553 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ | |
5554 | current_freq = current_freq * 500 + 1000; | |
5555 | ||
5556 | /* | |
5557 | * DE PLL has to be disabled when | |
5558 | * - setting to 19.2MHz (bypass, PLL isn't used) | |
5559 | * - before setting to 624MHz (PLL needs toggling) | |
5560 | * - before setting to any frequency from 624MHz (PLL needs toggling) | |
5561 | */ | |
5562 | if (frequency == 19200 || frequency == 624000 || | |
5563 | current_freq == 624000) { | |
5564 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); | |
5565 | /* Timeout 200us */ | |
5566 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), | |
5567 | 1)) | |
5568 | DRM_ERROR("timout waiting for DE PLL unlock\n"); | |
5569 | } | |
5570 | ||
5571 | if (frequency != 19200) { | |
5572 | uint32_t val; | |
5573 | ||
5574 | val = I915_READ(BXT_DE_PLL_CTL); | |
5575 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5576 | val |= ratio; | |
5577 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
5578 | ||
5579 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5580 | /* Timeout 200us */ | |
5581 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) | |
5582 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
5583 | ||
5584 | val = I915_READ(CDCLK_CTL); | |
5585 | val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
5586 | val |= divider; | |
5587 | /* | |
5588 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5589 | * enable otherwise. | |
5590 | */ | |
5591 | val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5592 | if (frequency >= 500000) | |
5593 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5594 | ||
5595 | val &= ~CDCLK_FREQ_DECIMAL_MASK; | |
5596 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
5597 | val |= (frequency - 1000) / 500; | |
5598 | I915_WRITE(CDCLK_CTL, val); | |
5599 | } | |
5600 | ||
5601 | mutex_lock(&dev_priv->rps.hw_lock); | |
5602 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5603 | DIV_ROUND_UP(frequency, 25000)); | |
5604 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5605 | ||
5606 | if (ret) { | |
5607 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
5608 | ret, frequency); | |
5609 | return; | |
5610 | } | |
5611 | ||
a47871bd | 5612 | intel_update_cdclk(dev); |
f8437dd1 VK |
5613 | } |
5614 | ||
5615 | void broxton_init_cdclk(struct drm_device *dev) | |
5616 | { | |
5617 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5618 | uint32_t val; | |
5619 | ||
5620 | /* | |
5621 | * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT | |
5622 | * or else the reset will hang because there is no PCH to respond. | |
5623 | * Move the handshake programming to initialization sequence. | |
5624 | * Previously was left up to BIOS. | |
5625 | */ | |
5626 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5627 | val &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
5628 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val); | |
5629 | ||
5630 | /* Enable PG1 for cdclk */ | |
5631 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5632 | ||
5633 | /* check if cd clock is enabled */ | |
5634 | if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { | |
5635 | DRM_DEBUG_KMS("Display already initialized\n"); | |
5636 | return; | |
5637 | } | |
5638 | ||
5639 | /* | |
5640 | * FIXME: | |
5641 | * - The initial CDCLK needs to be read from VBT. | |
5642 | * Need to make this change after VBT has changes for BXT. | |
5643 | * - check if setting the max (or any) cdclk freq is really necessary | |
5644 | * here, it belongs to modeset time | |
5645 | */ | |
5646 | broxton_set_cdclk(dev, 624000); | |
5647 | ||
5648 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
22e02c0b VS |
5649 | POSTING_READ(DBUF_CTL); |
5650 | ||
f8437dd1 VK |
5651 | udelay(10); |
5652 | ||
5653 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5654 | DRM_ERROR("DBuf power enable timeout!\n"); | |
5655 | } | |
5656 | ||
5657 | void broxton_uninit_cdclk(struct drm_device *dev) | |
5658 | { | |
5659 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5660 | ||
5661 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
22e02c0b VS |
5662 | POSTING_READ(DBUF_CTL); |
5663 | ||
f8437dd1 VK |
5664 | udelay(10); |
5665 | ||
5666 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5667 | DRM_ERROR("DBuf power disable timeout!\n"); | |
5668 | ||
5669 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ | |
5670 | broxton_set_cdclk(dev, 19200); | |
5671 | ||
5672 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5673 | } | |
5674 | ||
5d96d8af DL |
5675 | static const struct skl_cdclk_entry { |
5676 | unsigned int freq; | |
5677 | unsigned int vco; | |
5678 | } skl_cdclk_frequencies[] = { | |
5679 | { .freq = 308570, .vco = 8640 }, | |
5680 | { .freq = 337500, .vco = 8100 }, | |
5681 | { .freq = 432000, .vco = 8640 }, | |
5682 | { .freq = 450000, .vco = 8100 }, | |
5683 | { .freq = 540000, .vco = 8100 }, | |
5684 | { .freq = 617140, .vco = 8640 }, | |
5685 | { .freq = 675000, .vco = 8100 }, | |
5686 | }; | |
5687 | ||
5688 | static unsigned int skl_cdclk_decimal(unsigned int freq) | |
5689 | { | |
5690 | return (freq - 1000) / 500; | |
5691 | } | |
5692 | ||
5693 | static unsigned int skl_cdclk_get_vco(unsigned int freq) | |
5694 | { | |
5695 | unsigned int i; | |
5696 | ||
5697 | for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) { | |
5698 | const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i]; | |
5699 | ||
5700 | if (e->freq == freq) | |
5701 | return e->vco; | |
5702 | } | |
5703 | ||
5704 | return 8100; | |
5705 | } | |
5706 | ||
5707 | static void | |
5708 | skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco) | |
5709 | { | |
5710 | unsigned int min_freq; | |
5711 | u32 val; | |
5712 | ||
5713 | /* select the minimum CDCLK before enabling DPLL 0 */ | |
5714 | val = I915_READ(CDCLK_CTL); | |
5715 | val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK; | |
5716 | val |= CDCLK_FREQ_337_308; | |
5717 | ||
5718 | if (required_vco == 8640) | |
5719 | min_freq = 308570; | |
5720 | else | |
5721 | min_freq = 337500; | |
5722 | ||
5723 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq); | |
5724 | ||
5725 | I915_WRITE(CDCLK_CTL, val); | |
5726 | POSTING_READ(CDCLK_CTL); | |
5727 | ||
5728 | /* | |
5729 | * We always enable DPLL0 with the lowest link rate possible, but still | |
5730 | * taking into account the VCO required to operate the eDP panel at the | |
5731 | * desired frequency. The usual DP link rates operate with a VCO of | |
5732 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
5733 | * The modeset code is responsible for the selection of the exact link | |
5734 | * rate later on, with the constraint of choosing a frequency that | |
5735 | * works with required_vco. | |
5736 | */ | |
5737 | val = I915_READ(DPLL_CTRL1); | |
5738 | ||
5739 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5740 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
5741 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
5742 | if (required_vco == 8640) | |
5743 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, | |
5744 | SKL_DPLL0); | |
5745 | else | |
5746 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
5747 | SKL_DPLL0); | |
5748 | ||
5749 | I915_WRITE(DPLL_CTRL1, val); | |
5750 | POSTING_READ(DPLL_CTRL1); | |
5751 | ||
5752 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
5753 | ||
5754 | if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) | |
5755 | DRM_ERROR("DPLL0 not locked\n"); | |
5756 | } | |
5757 | ||
5758 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) | |
5759 | { | |
5760 | int ret; | |
5761 | u32 val; | |
5762 | ||
5763 | /* inform PCU we want to change CDCLK */ | |
5764 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
5765 | mutex_lock(&dev_priv->rps.hw_lock); | |
5766 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
5767 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5768 | ||
5769 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
5770 | } | |
5771 | ||
5772 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
5773 | { | |
5774 | unsigned int i; | |
5775 | ||
5776 | for (i = 0; i < 15; i++) { | |
5777 | if (skl_cdclk_pcu_ready(dev_priv)) | |
5778 | return true; | |
5779 | udelay(10); | |
5780 | } | |
5781 | ||
5782 | return false; | |
5783 | } | |
5784 | ||
5785 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq) | |
5786 | { | |
560a7ae4 | 5787 | struct drm_device *dev = dev_priv->dev; |
5d96d8af DL |
5788 | u32 freq_select, pcu_ack; |
5789 | ||
5790 | DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq); | |
5791 | ||
5792 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
5793 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
5794 | return; | |
5795 | } | |
5796 | ||
5797 | /* set CDCLK_CTL */ | |
5798 | switch(freq) { | |
5799 | case 450000: | |
5800 | case 432000: | |
5801 | freq_select = CDCLK_FREQ_450_432; | |
5802 | pcu_ack = 1; | |
5803 | break; | |
5804 | case 540000: | |
5805 | freq_select = CDCLK_FREQ_540; | |
5806 | pcu_ack = 2; | |
5807 | break; | |
5808 | case 308570: | |
5809 | case 337500: | |
5810 | default: | |
5811 | freq_select = CDCLK_FREQ_337_308; | |
5812 | pcu_ack = 0; | |
5813 | break; | |
5814 | case 617140: | |
5815 | case 675000: | |
5816 | freq_select = CDCLK_FREQ_675_617; | |
5817 | pcu_ack = 3; | |
5818 | break; | |
5819 | } | |
5820 | ||
5821 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq)); | |
5822 | POSTING_READ(CDCLK_CTL); | |
5823 | ||
5824 | /* inform PCU of the change */ | |
5825 | mutex_lock(&dev_priv->rps.hw_lock); | |
5826 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
5827 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 DL |
5828 | |
5829 | intel_update_cdclk(dev); | |
5d96d8af DL |
5830 | } |
5831 | ||
5832 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
5833 | { | |
5834 | /* disable DBUF power */ | |
5835 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
5836 | POSTING_READ(DBUF_CTL); | |
5837 | ||
5838 | udelay(10); | |
5839 | ||
5840 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5841 | DRM_ERROR("DBuf power disable timeout\n"); | |
5842 | ||
ab96c1ee ID |
5843 | /* disable DPLL0 */ |
5844 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
5845 | if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) | |
5846 | DRM_ERROR("Couldn't disable DPLL0\n"); | |
5d96d8af DL |
5847 | } |
5848 | ||
5849 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
5850 | { | |
5d96d8af DL |
5851 | unsigned int required_vco; |
5852 | ||
39d9b85a GW |
5853 | /* DPLL0 not enabled (happens on early BIOS versions) */ |
5854 | if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) { | |
5855 | /* enable DPLL0 */ | |
5856 | required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); | |
5857 | skl_dpll0_enable(dev_priv, required_vco); | |
5d96d8af DL |
5858 | } |
5859 | ||
5d96d8af DL |
5860 | /* set CDCLK to the frequency the BIOS chose */ |
5861 | skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); | |
5862 | ||
5863 | /* enable DBUF power */ | |
5864 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
5865 | POSTING_READ(DBUF_CTL); | |
5866 | ||
5867 | udelay(10); | |
5868 | ||
5869 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5870 | DRM_ERROR("DBuf power enable timeout\n"); | |
5871 | } | |
5872 | ||
c73666f3 SK |
5873 | int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
5874 | { | |
5875 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
5876 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
5877 | int freq = dev_priv->skl_boot_cdclk; | |
5878 | ||
f1b391a5 SK |
5879 | /* |
5880 | * check if the pre-os intialized the display | |
5881 | * There is SWF18 scratchpad register defined which is set by the | |
5882 | * pre-os which can be used by the OS drivers to check the status | |
5883 | */ | |
5884 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
5885 | goto sanitize; | |
5886 | ||
c73666f3 SK |
5887 | /* Is PLL enabled and locked ? */ |
5888 | if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK))) | |
5889 | goto sanitize; | |
5890 | ||
5891 | /* DPLL okay; verify the cdclock | |
5892 | * | |
5893 | * Noticed in some instances that the freq selection is correct but | |
5894 | * decimal part is programmed wrong from BIOS where pre-os does not | |
5895 | * enable display. Verify the same as well. | |
5896 | */ | |
5897 | if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq))) | |
5898 | /* All well; nothing to sanitize */ | |
5899 | return false; | |
5900 | sanitize: | |
5901 | /* | |
5902 | * As of now initialize with max cdclk till | |
5903 | * we get dynamic cdclk support | |
5904 | * */ | |
5905 | dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq; | |
5906 | skl_init_cdclk(dev_priv); | |
5907 | ||
5908 | /* we did have to sanitize */ | |
5909 | return true; | |
5910 | } | |
5911 | ||
30a970c6 JB |
5912 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5913 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5914 | { | |
5915 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5916 | u32 val, cmd; | |
5917 | ||
164dfd28 VK |
5918 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5919 | != dev_priv->cdclk_freq); | |
d60c4473 | 5920 | |
dfcab17e | 5921 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5922 | cmd = 2; |
dfcab17e | 5923 | else if (cdclk == 266667) |
30a970c6 JB |
5924 | cmd = 1; |
5925 | else | |
5926 | cmd = 0; | |
5927 | ||
5928 | mutex_lock(&dev_priv->rps.hw_lock); | |
5929 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5930 | val &= ~DSPFREQGUAR_MASK; | |
5931 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5932 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5933 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5934 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5935 | 50)) { | |
5936 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5937 | } | |
5938 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5939 | ||
54433e91 VS |
5940 | mutex_lock(&dev_priv->sb_lock); |
5941 | ||
dfcab17e | 5942 | if (cdclk == 400000) { |
6bcda4f0 | 5943 | u32 divider; |
30a970c6 | 5944 | |
6bcda4f0 | 5945 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 5946 | |
30a970c6 JB |
5947 | /* adjust cdclk divider */ |
5948 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
87d5d259 | 5949 | val &= ~CCK_FREQUENCY_VALUES; |
30a970c6 JB |
5950 | val |= divider; |
5951 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5952 | |
5953 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
87d5d259 | 5954 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
a877e801 VS |
5955 | 50)) |
5956 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5957 | } |
5958 | ||
30a970c6 JB |
5959 | /* adjust self-refresh exit latency value */ |
5960 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5961 | val &= ~0x7f; | |
5962 | ||
5963 | /* | |
5964 | * For high bandwidth configs, we set a higher latency in the bunit | |
5965 | * so that the core display fetch happens in time to avoid underruns. | |
5966 | */ | |
dfcab17e | 5967 | if (cdclk == 400000) |
30a970c6 JB |
5968 | val |= 4500 / 250; /* 4.5 usec */ |
5969 | else | |
5970 | val |= 3000 / 250; /* 3.0 usec */ | |
5971 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 5972 | |
a580516d | 5973 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5974 | |
b6283055 | 5975 | intel_update_cdclk(dev); |
30a970c6 JB |
5976 | } |
5977 | ||
383c5a6a VS |
5978 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5979 | { | |
5980 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5981 | u32 val, cmd; | |
5982 | ||
164dfd28 VK |
5983 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5984 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5985 | |
5986 | switch (cdclk) { | |
383c5a6a VS |
5987 | case 333333: |
5988 | case 320000: | |
383c5a6a | 5989 | case 266667: |
383c5a6a | 5990 | case 200000: |
383c5a6a VS |
5991 | break; |
5992 | default: | |
5f77eeb0 | 5993 | MISSING_CASE(cdclk); |
383c5a6a VS |
5994 | return; |
5995 | } | |
5996 | ||
9d0d3fda VS |
5997 | /* |
5998 | * Specs are full of misinformation, but testing on actual | |
5999 | * hardware has shown that we just need to write the desired | |
6000 | * CCK divider into the Punit register. | |
6001 | */ | |
6002 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
6003 | ||
383c5a6a VS |
6004 | mutex_lock(&dev_priv->rps.hw_lock); |
6005 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
6006 | val &= ~DSPFREQGUAR_MASK_CHV; | |
6007 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
6008 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
6009 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
6010 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
6011 | 50)) { | |
6012 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
6013 | } | |
6014 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6015 | ||
b6283055 | 6016 | intel_update_cdclk(dev); |
383c5a6a VS |
6017 | } |
6018 | ||
30a970c6 JB |
6019 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
6020 | int max_pixclk) | |
6021 | { | |
6bcda4f0 | 6022 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 6023 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 6024 | |
30a970c6 JB |
6025 | /* |
6026 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
6027 | * 200MHz | |
6028 | * 267MHz | |
29dc7ef3 | 6029 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
6030 | * 400MHz (VLV only) |
6031 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
6032 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
6033 | * |
6034 | * We seem to get an unstable or solid color picture at 200MHz. | |
6035 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
6036 | * are off. | |
30a970c6 | 6037 | */ |
6cca3195 VS |
6038 | if (!IS_CHERRYVIEW(dev_priv) && |
6039 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 6040 | return 400000; |
6cca3195 | 6041 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 6042 | return freq_320; |
e37c67a1 | 6043 | else if (max_pixclk > 0) |
dfcab17e | 6044 | return 266667; |
e37c67a1 VS |
6045 | else |
6046 | return 200000; | |
30a970c6 JB |
6047 | } |
6048 | ||
f8437dd1 VK |
6049 | static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, |
6050 | int max_pixclk) | |
6051 | { | |
6052 | /* | |
6053 | * FIXME: | |
6054 | * - remove the guardband, it's not needed on BXT | |
6055 | * - set 19.2MHz bypass frequency if there are no active pipes | |
6056 | */ | |
6057 | if (max_pixclk > 576000*9/10) | |
6058 | return 624000; | |
6059 | else if (max_pixclk > 384000*9/10) | |
6060 | return 576000; | |
6061 | else if (max_pixclk > 288000*9/10) | |
6062 | return 384000; | |
6063 | else if (max_pixclk > 144000*9/10) | |
6064 | return 288000; | |
6065 | else | |
6066 | return 144000; | |
6067 | } | |
6068 | ||
a821fc46 ACO |
6069 | /* Compute the max pixel clock for new configuration. Uses atomic state if |
6070 | * that's non-NULL, look at current state otherwise. */ | |
6071 | static int intel_mode_max_pixclk(struct drm_device *dev, | |
6072 | struct drm_atomic_state *state) | |
30a970c6 | 6073 | { |
565602d7 ML |
6074 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
6075 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6076 | struct drm_crtc *crtc; | |
6077 | struct drm_crtc_state *crtc_state; | |
6078 | unsigned max_pixclk = 0, i; | |
6079 | enum pipe pipe; | |
30a970c6 | 6080 | |
565602d7 ML |
6081 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
6082 | sizeof(intel_state->min_pixclk)); | |
304603f4 | 6083 | |
565602d7 ML |
6084 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
6085 | int pixclk = 0; | |
6086 | ||
6087 | if (crtc_state->enable) | |
6088 | pixclk = crtc_state->adjusted_mode.crtc_clock; | |
304603f4 | 6089 | |
565602d7 | 6090 | intel_state->min_pixclk[i] = pixclk; |
30a970c6 JB |
6091 | } |
6092 | ||
565602d7 ML |
6093 | if (!intel_state->active_crtcs) |
6094 | return 0; | |
6095 | ||
6096 | for_each_pipe(dev_priv, pipe) | |
6097 | max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); | |
6098 | ||
30a970c6 JB |
6099 | return max_pixclk; |
6100 | } | |
6101 | ||
27c329ed | 6102 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 6103 | { |
27c329ed ML |
6104 | struct drm_device *dev = state->dev; |
6105 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6106 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
1a617b77 ML |
6107 | struct intel_atomic_state *intel_state = |
6108 | to_intel_atomic_state(state); | |
30a970c6 | 6109 | |
304603f4 ACO |
6110 | if (max_pixclk < 0) |
6111 | return max_pixclk; | |
30a970c6 | 6112 | |
1a617b77 | 6113 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 6114 | valleyview_calc_cdclk(dev_priv, max_pixclk); |
0a9ab303 | 6115 | |
1a617b77 ML |
6116 | if (!intel_state->active_crtcs) |
6117 | intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); | |
6118 | ||
27c329ed ML |
6119 | return 0; |
6120 | } | |
304603f4 | 6121 | |
27c329ed ML |
6122 | static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state) |
6123 | { | |
6124 | struct drm_device *dev = state->dev; | |
6125 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6126 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
1a617b77 ML |
6127 | struct intel_atomic_state *intel_state = |
6128 | to_intel_atomic_state(state); | |
85a96e7a | 6129 | |
27c329ed ML |
6130 | if (max_pixclk < 0) |
6131 | return max_pixclk; | |
85a96e7a | 6132 | |
1a617b77 | 6133 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 6134 | broxton_calc_cdclk(dev_priv, max_pixclk); |
85a96e7a | 6135 | |
1a617b77 ML |
6136 | if (!intel_state->active_crtcs) |
6137 | intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0); | |
6138 | ||
27c329ed | 6139 | return 0; |
30a970c6 JB |
6140 | } |
6141 | ||
1e69cd74 VS |
6142 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
6143 | { | |
6144 | unsigned int credits, default_credits; | |
6145 | ||
6146 | if (IS_CHERRYVIEW(dev_priv)) | |
6147 | default_credits = PFI_CREDIT(12); | |
6148 | else | |
6149 | default_credits = PFI_CREDIT(8); | |
6150 | ||
bfa7df01 | 6151 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
1e69cd74 VS |
6152 | /* CHV suggested value is 31 or 63 */ |
6153 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 6154 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
6155 | else |
6156 | credits = PFI_CREDIT(15); | |
6157 | } else { | |
6158 | credits = default_credits; | |
6159 | } | |
6160 | ||
6161 | /* | |
6162 | * WA - write default credits before re-programming | |
6163 | * FIXME: should we also set the resend bit here? | |
6164 | */ | |
6165 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6166 | default_credits); | |
6167 | ||
6168 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6169 | credits | PFI_CREDIT_RESEND); | |
6170 | ||
6171 | /* | |
6172 | * FIXME is this guaranteed to clear | |
6173 | * immediately or should we poll for it? | |
6174 | */ | |
6175 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6176 | } | |
6177 | ||
27c329ed | 6178 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 6179 | { |
a821fc46 | 6180 | struct drm_device *dev = old_state->dev; |
30a970c6 | 6181 | struct drm_i915_private *dev_priv = dev->dev_private; |
1a617b77 ML |
6182 | struct intel_atomic_state *old_intel_state = |
6183 | to_intel_atomic_state(old_state); | |
6184 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
30a970c6 | 6185 | |
27c329ed ML |
6186 | /* |
6187 | * FIXME: We can end up here with all power domains off, yet | |
6188 | * with a CDCLK frequency other than the minimum. To account | |
6189 | * for this take the PIPE-A power domain, which covers the HW | |
6190 | * blocks needed for the following programming. This can be | |
6191 | * removed once it's guaranteed that we get here either with | |
6192 | * the minimum CDCLK set, or the required power domains | |
6193 | * enabled. | |
6194 | */ | |
6195 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6196 | |
27c329ed ML |
6197 | if (IS_CHERRYVIEW(dev)) |
6198 | cherryview_set_cdclk(dev, req_cdclk); | |
6199 | else | |
6200 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6201 | |
27c329ed | 6202 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6203 | |
27c329ed | 6204 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6205 | } |
6206 | ||
89b667f8 JB |
6207 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
6208 | { | |
6209 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6210 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
6211 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6212 | struct intel_encoder *encoder; | |
6213 | int pipe = intel_crtc->pipe; | |
89b667f8 | 6214 | |
53d9f4e9 | 6215 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6216 | return; |
6217 | ||
6e3c9717 | 6218 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6219 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6220 | |
6221 | intel_set_pipe_timings(intel_crtc); | |
6222 | ||
c14b0485 VS |
6223 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
6224 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6225 | ||
6226 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6227 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6228 | } | |
6229 | ||
5b18e57c DV |
6230 | i9xx_set_pipeconf(intel_crtc); |
6231 | ||
89b667f8 | 6232 | intel_crtc->active = true; |
89b667f8 | 6233 | |
a72e4c9f | 6234 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6235 | |
89b667f8 JB |
6236 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6237 | if (encoder->pre_pll_enable) | |
6238 | encoder->pre_pll_enable(encoder); | |
6239 | ||
a65347ba | 6240 | if (!intel_crtc->config->has_dsi_encoder) { |
c0b4c660 VS |
6241 | if (IS_CHERRYVIEW(dev)) { |
6242 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6243 | chv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 VS |
6244 | } else { |
6245 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6246 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 | 6247 | } |
9d556c99 | 6248 | } |
89b667f8 JB |
6249 | |
6250 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6251 | if (encoder->pre_enable) | |
6252 | encoder->pre_enable(encoder); | |
6253 | ||
2dd24552 JB |
6254 | i9xx_pfit_enable(intel_crtc); |
6255 | ||
63cbb074 VS |
6256 | intel_crtc_load_lut(crtc); |
6257 | ||
e1fdc473 | 6258 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6259 | |
4b3a9526 VS |
6260 | assert_vblank_disabled(crtc); |
6261 | drm_crtc_vblank_on(crtc); | |
6262 | ||
f9b61ff6 DV |
6263 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6264 | encoder->enable(encoder); | |
89b667f8 JB |
6265 | } |
6266 | ||
f13c2ef3 DV |
6267 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6268 | { | |
6269 | struct drm_device *dev = crtc->base.dev; | |
6270 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6271 | ||
6e3c9717 ACO |
6272 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6273 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6274 | } |
6275 | ||
0b8765c6 | 6276 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
6277 | { |
6278 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6279 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6280 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6281 | struct intel_encoder *encoder; |
79e53945 | 6282 | int pipe = intel_crtc->pipe; |
79e53945 | 6283 | |
53d9f4e9 | 6284 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6285 | return; |
6286 | ||
f13c2ef3 DV |
6287 | i9xx_set_pll_dividers(intel_crtc); |
6288 | ||
6e3c9717 | 6289 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6290 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6291 | |
6292 | intel_set_pipe_timings(intel_crtc); | |
6293 | ||
5b18e57c DV |
6294 | i9xx_set_pipeconf(intel_crtc); |
6295 | ||
f7abfe8b | 6296 | intel_crtc->active = true; |
6b383a7f | 6297 | |
4a3436e8 | 6298 | if (!IS_GEN2(dev)) |
a72e4c9f | 6299 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6300 | |
9d6d9f19 MK |
6301 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6302 | if (encoder->pre_enable) | |
6303 | encoder->pre_enable(encoder); | |
6304 | ||
f6736a1a DV |
6305 | i9xx_enable_pll(intel_crtc); |
6306 | ||
2dd24552 JB |
6307 | i9xx_pfit_enable(intel_crtc); |
6308 | ||
63cbb074 VS |
6309 | intel_crtc_load_lut(crtc); |
6310 | ||
f37fcc2a | 6311 | intel_update_watermarks(crtc); |
e1fdc473 | 6312 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6313 | |
4b3a9526 VS |
6314 | assert_vblank_disabled(crtc); |
6315 | drm_crtc_vblank_on(crtc); | |
6316 | ||
f9b61ff6 DV |
6317 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6318 | encoder->enable(encoder); | |
d029bcad PZ |
6319 | |
6320 | intel_fbc_enable(intel_crtc); | |
0b8765c6 | 6321 | } |
79e53945 | 6322 | |
87476d63 DV |
6323 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6324 | { | |
6325 | struct drm_device *dev = crtc->base.dev; | |
6326 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 6327 | |
6e3c9717 | 6328 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6329 | return; |
87476d63 | 6330 | |
328d8e82 | 6331 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6332 | |
328d8e82 DV |
6333 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6334 | I915_READ(PFIT_CONTROL)); | |
6335 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6336 | } |
6337 | ||
0b8765c6 JB |
6338 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6339 | { | |
6340 | struct drm_device *dev = crtc->dev; | |
6341 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6342 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 6343 | struct intel_encoder *encoder; |
0b8765c6 | 6344 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6345 | |
6304cd91 VS |
6346 | /* |
6347 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6348 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
6349 | * We also need to wait on all gmch platforms because of the |
6350 | * self-refresh mode constraint explained above. | |
6304cd91 | 6351 | */ |
564ed191 | 6352 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 6353 | |
4b3a9526 VS |
6354 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6355 | encoder->disable(encoder); | |
6356 | ||
f9b61ff6 DV |
6357 | drm_crtc_vblank_off(crtc); |
6358 | assert_vblank_disabled(crtc); | |
6359 | ||
575f7ab7 | 6360 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6361 | |
87476d63 | 6362 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6363 | |
89b667f8 JB |
6364 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6365 | if (encoder->post_disable) | |
6366 | encoder->post_disable(encoder); | |
6367 | ||
a65347ba | 6368 | if (!intel_crtc->config->has_dsi_encoder) { |
076ed3b2 CML |
6369 | if (IS_CHERRYVIEW(dev)) |
6370 | chv_disable_pll(dev_priv, pipe); | |
6371 | else if (IS_VALLEYVIEW(dev)) | |
6372 | vlv_disable_pll(dev_priv, pipe); | |
6373 | else | |
1c4e0274 | 6374 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6375 | } |
0b8765c6 | 6376 | |
d6db995f VS |
6377 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6378 | if (encoder->post_pll_disable) | |
6379 | encoder->post_pll_disable(encoder); | |
6380 | ||
4a3436e8 | 6381 | if (!IS_GEN2(dev)) |
a72e4c9f | 6382 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
d029bcad PZ |
6383 | |
6384 | intel_fbc_disable_crtc(intel_crtc); | |
0b8765c6 JB |
6385 | } |
6386 | ||
b17d48e2 ML |
6387 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6388 | { | |
6389 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6390 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6391 | enum intel_display_power_domain domain; | |
6392 | unsigned long domains; | |
6393 | ||
6394 | if (!intel_crtc->active) | |
6395 | return; | |
6396 | ||
a539205a | 6397 | if (to_intel_plane_state(crtc->primary->state)->visible) { |
fc32b1fd ML |
6398 | WARN_ON(intel_crtc->unpin_work); |
6399 | ||
a539205a | 6400 | intel_pre_disable_primary(crtc); |
54a41961 ML |
6401 | |
6402 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); | |
6403 | to_intel_plane_state(crtc->primary->state)->visible = false; | |
a539205a ML |
6404 | } |
6405 | ||
b17d48e2 | 6406 | dev_priv->display.crtc_disable(crtc); |
37d9078b MR |
6407 | intel_crtc->active = false; |
6408 | intel_update_watermarks(crtc); | |
1f7457b1 | 6409 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6410 | |
6411 | domains = intel_crtc->enabled_power_domains; | |
6412 | for_each_power_domain(domain, domains) | |
6413 | intel_display_power_put(dev_priv, domain); | |
6414 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
6415 | |
6416 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
6417 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
6418 | } |
6419 | ||
6b72d486 ML |
6420 | /* |
6421 | * turn all crtc's off, but do not adjust state | |
6422 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6423 | */ | |
70e0bd74 | 6424 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6425 | { |
70e0bd74 ML |
6426 | struct drm_mode_config *config = &dev->mode_config; |
6427 | struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx; | |
6428 | struct drm_atomic_state *state; | |
6b72d486 | 6429 | struct drm_crtc *crtc; |
70e0bd74 ML |
6430 | unsigned crtc_mask = 0; |
6431 | int ret = 0; | |
6432 | ||
6433 | if (WARN_ON(!ctx)) | |
6434 | return 0; | |
6435 | ||
6436 | lockdep_assert_held(&ctx->ww_ctx); | |
6437 | state = drm_atomic_state_alloc(dev); | |
6438 | if (WARN_ON(!state)) | |
6439 | return -ENOMEM; | |
6440 | ||
6441 | state->acquire_ctx = ctx; | |
6442 | state->allow_modeset = true; | |
6443 | ||
6444 | for_each_crtc(dev, crtc) { | |
6445 | struct drm_crtc_state *crtc_state = | |
6446 | drm_atomic_get_crtc_state(state, crtc); | |
6b72d486 | 6447 | |
70e0bd74 ML |
6448 | ret = PTR_ERR_OR_ZERO(crtc_state); |
6449 | if (ret) | |
6450 | goto free; | |
6451 | ||
6452 | if (!crtc_state->active) | |
6453 | continue; | |
6454 | ||
6455 | crtc_state->active = false; | |
6456 | crtc_mask |= 1 << drm_crtc_index(crtc); | |
6457 | } | |
6458 | ||
6459 | if (crtc_mask) { | |
74c090b1 | 6460 | ret = drm_atomic_commit(state); |
70e0bd74 ML |
6461 | |
6462 | if (!ret) { | |
6463 | for_each_crtc(dev, crtc) | |
6464 | if (crtc_mask & (1 << drm_crtc_index(crtc))) | |
6465 | crtc->state->active = true; | |
6466 | ||
6467 | return ret; | |
6468 | } | |
6469 | } | |
6470 | ||
6471 | free: | |
6472 | if (ret) | |
6473 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
6474 | drm_atomic_state_free(state); | |
6475 | return ret; | |
ee7b9f93 JB |
6476 | } |
6477 | ||
ea5b213a | 6478 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6479 | { |
4ef69c7a | 6480 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6481 | |
ea5b213a CW |
6482 | drm_encoder_cleanup(encoder); |
6483 | kfree(intel_encoder); | |
7e7d76c3 JB |
6484 | } |
6485 | ||
0a91ca29 DV |
6486 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6487 | * internal consistency). */ | |
b980514c | 6488 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 6489 | { |
35dd3c64 ML |
6490 | struct drm_crtc *crtc = connector->base.state->crtc; |
6491 | ||
6492 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6493 | connector->base.base.id, | |
6494 | connector->base.name); | |
6495 | ||
0a91ca29 | 6496 | if (connector->get_hw_state(connector)) { |
e85376cb | 6497 | struct intel_encoder *encoder = connector->encoder; |
35dd3c64 | 6498 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 6499 | |
35dd3c64 ML |
6500 | I915_STATE_WARN(!crtc, |
6501 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6502 | |
35dd3c64 ML |
6503 | if (!crtc) |
6504 | return; | |
6505 | ||
6506 | I915_STATE_WARN(!crtc->state->active, | |
6507 | "connector is active, but attached crtc isn't\n"); | |
6508 | ||
e85376cb | 6509 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6510 | return; |
6511 | ||
e85376cb | 6512 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6513 | "atomic encoder doesn't match attached encoder\n"); |
6514 | ||
e85376cb | 6515 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6516 | "attached encoder crtc differs from connector crtc\n"); |
6517 | } else { | |
4d688a2a ML |
6518 | I915_STATE_WARN(crtc && crtc->state->active, |
6519 | "attached crtc is active, but connector isn't\n"); | |
35dd3c64 ML |
6520 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
6521 | "best encoder set without crtc!\n"); | |
0a91ca29 | 6522 | } |
79e53945 JB |
6523 | } |
6524 | ||
08d9bc92 ACO |
6525 | int intel_connector_init(struct intel_connector *connector) |
6526 | { | |
6527 | struct drm_connector_state *connector_state; | |
6528 | ||
6529 | connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL); | |
6530 | if (!connector_state) | |
6531 | return -ENOMEM; | |
6532 | ||
6533 | connector->base.state = connector_state; | |
6534 | return 0; | |
6535 | } | |
6536 | ||
6537 | struct intel_connector *intel_connector_alloc(void) | |
6538 | { | |
6539 | struct intel_connector *connector; | |
6540 | ||
6541 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6542 | if (!connector) | |
6543 | return NULL; | |
6544 | ||
6545 | if (intel_connector_init(connector) < 0) { | |
6546 | kfree(connector); | |
6547 | return NULL; | |
6548 | } | |
6549 | ||
6550 | return connector; | |
6551 | } | |
6552 | ||
f0947c37 DV |
6553 | /* Simple connector->get_hw_state implementation for encoders that support only |
6554 | * one connector and no cloning and hence the encoder state determines the state | |
6555 | * of the connector. */ | |
6556 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6557 | { |
24929352 | 6558 | enum pipe pipe = 0; |
f0947c37 | 6559 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6560 | |
f0947c37 | 6561 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6562 | } |
6563 | ||
6d293983 | 6564 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6565 | { |
6d293983 ACO |
6566 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6567 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6568 | |
6569 | return 0; | |
6570 | } | |
6571 | ||
6d293983 | 6572 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6573 | struct intel_crtc_state *pipe_config) |
1857e1da | 6574 | { |
6d293983 ACO |
6575 | struct drm_atomic_state *state = pipe_config->base.state; |
6576 | struct intel_crtc *other_crtc; | |
6577 | struct intel_crtc_state *other_crtc_state; | |
6578 | ||
1857e1da DV |
6579 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6580 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6581 | if (pipe_config->fdi_lanes > 4) { | |
6582 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6583 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6584 | return -EINVAL; |
1857e1da DV |
6585 | } |
6586 | ||
bafb6553 | 6587 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6588 | if (pipe_config->fdi_lanes > 2) { |
6589 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6590 | pipe_config->fdi_lanes); | |
6d293983 | 6591 | return -EINVAL; |
1857e1da | 6592 | } else { |
6d293983 | 6593 | return 0; |
1857e1da DV |
6594 | } |
6595 | } | |
6596 | ||
6597 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6598 | return 0; |
1857e1da DV |
6599 | |
6600 | /* Ivybridge 3 pipe is really complicated */ | |
6601 | switch (pipe) { | |
6602 | case PIPE_A: | |
6d293983 | 6603 | return 0; |
1857e1da | 6604 | case PIPE_B: |
6d293983 ACO |
6605 | if (pipe_config->fdi_lanes <= 2) |
6606 | return 0; | |
6607 | ||
6608 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6609 | other_crtc_state = | |
6610 | intel_atomic_get_crtc_state(state, other_crtc); | |
6611 | if (IS_ERR(other_crtc_state)) | |
6612 | return PTR_ERR(other_crtc_state); | |
6613 | ||
6614 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6615 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6616 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6617 | return -EINVAL; |
1857e1da | 6618 | } |
6d293983 | 6619 | return 0; |
1857e1da | 6620 | case PIPE_C: |
251cc67c VS |
6621 | if (pipe_config->fdi_lanes > 2) { |
6622 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6623 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6624 | return -EINVAL; |
251cc67c | 6625 | } |
6d293983 ACO |
6626 | |
6627 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6628 | other_crtc_state = | |
6629 | intel_atomic_get_crtc_state(state, other_crtc); | |
6630 | if (IS_ERR(other_crtc_state)) | |
6631 | return PTR_ERR(other_crtc_state); | |
6632 | ||
6633 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6634 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6635 | return -EINVAL; |
1857e1da | 6636 | } |
6d293983 | 6637 | return 0; |
1857e1da DV |
6638 | default: |
6639 | BUG(); | |
6640 | } | |
6641 | } | |
6642 | ||
e29c22c0 DV |
6643 | #define RETRY 1 |
6644 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6645 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6646 | { |
1857e1da | 6647 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6648 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6649 | int lane, link_bw, fdi_dotclock, ret; |
6650 | bool needs_recompute = false; | |
877d48d5 | 6651 | |
e29c22c0 | 6652 | retry: |
877d48d5 DV |
6653 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6654 | * each output octet as 10 bits. The actual frequency | |
6655 | * is stored as a divider into a 100MHz clock, and the | |
6656 | * mode pixel clock is stored in units of 1KHz. | |
6657 | * Hence the bw of each lane in terms of the mode signal | |
6658 | * is: | |
6659 | */ | |
6660 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
6661 | ||
241bfc38 | 6662 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6663 | |
2bd89a07 | 6664 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6665 | pipe_config->pipe_bpp); |
6666 | ||
6667 | pipe_config->fdi_lanes = lane; | |
6668 | ||
2bd89a07 | 6669 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6670 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6671 | |
6d293983 ACO |
6672 | ret = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
6673 | intel_crtc->pipe, pipe_config); | |
6674 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { | |
e29c22c0 DV |
6675 | pipe_config->pipe_bpp -= 2*3; |
6676 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6677 | pipe_config->pipe_bpp); | |
6678 | needs_recompute = true; | |
6679 | pipe_config->bw_constrained = true; | |
6680 | ||
6681 | goto retry; | |
6682 | } | |
6683 | ||
6684 | if (needs_recompute) | |
6685 | return RETRY; | |
6686 | ||
6d293983 | 6687 | return ret; |
877d48d5 DV |
6688 | } |
6689 | ||
8cfb3407 VS |
6690 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6691 | struct intel_crtc_state *pipe_config) | |
6692 | { | |
6693 | if (pipe_config->pipe_bpp > 24) | |
6694 | return false; | |
6695 | ||
6696 | /* HSW can handle pixel rate up to cdclk? */ | |
6697 | if (IS_HASWELL(dev_priv->dev)) | |
6698 | return true; | |
6699 | ||
6700 | /* | |
b432e5cf VS |
6701 | * We compare against max which means we must take |
6702 | * the increased cdclk requirement into account when | |
6703 | * calculating the new cdclk. | |
6704 | * | |
6705 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
6706 | */ |
6707 | return ilk_pipe_pixel_rate(pipe_config) <= | |
6708 | dev_priv->max_cdclk_freq * 95 / 100; | |
6709 | } | |
6710 | ||
42db64ef | 6711 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6712 | struct intel_crtc_state *pipe_config) |
42db64ef | 6713 | { |
8cfb3407 VS |
6714 | struct drm_device *dev = crtc->base.dev; |
6715 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6716 | ||
d330a953 | 6717 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
6718 | hsw_crtc_supports_ips(crtc) && |
6719 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
6720 | } |
6721 | ||
39acb4aa VS |
6722 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
6723 | { | |
6724 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
6725 | ||
6726 | /* GDG double wide on either pipe, otherwise pipe A only */ | |
6727 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6728 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
6729 | } | |
6730 | ||
a43f6e0f | 6731 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6732 | struct intel_crtc_state *pipe_config) |
79e53945 | 6733 | { |
a43f6e0f | 6734 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 6735 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c5f93b0 | 6736 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
89749350 | 6737 | |
ad3a4479 | 6738 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 6739 | if (INTEL_INFO(dev)->gen < 4) { |
39acb4aa | 6740 | int clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
cf532bb2 VS |
6741 | |
6742 | /* | |
39acb4aa | 6743 | * Enable double wide mode when the dot clock |
cf532bb2 | 6744 | * is > 90% of the (display) core speed. |
cf532bb2 | 6745 | */ |
39acb4aa VS |
6746 | if (intel_crtc_supports_double_wide(crtc) && |
6747 | adjusted_mode->crtc_clock > clock_limit) { | |
ad3a4479 | 6748 | clock_limit *= 2; |
cf532bb2 | 6749 | pipe_config->double_wide = true; |
ad3a4479 VS |
6750 | } |
6751 | ||
39acb4aa VS |
6752 | if (adjusted_mode->crtc_clock > clock_limit) { |
6753 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6754 | adjusted_mode->crtc_clock, clock_limit, | |
6755 | yesno(pipe_config->double_wide)); | |
e29c22c0 | 6756 | return -EINVAL; |
39acb4aa | 6757 | } |
2c07245f | 6758 | } |
89749350 | 6759 | |
1d1d0e27 VS |
6760 | /* |
6761 | * Pipe horizontal size must be even in: | |
6762 | * - DVO ganged mode | |
6763 | * - LVDS dual channel mode | |
6764 | * - Double wide pipe | |
6765 | */ | |
a93e255f | 6766 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6767 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6768 | pipe_config->pipe_src_w &= ~1; | |
6769 | ||
8693a824 DL |
6770 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6771 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6772 | */ |
6773 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
aad941d5 | 6774 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
e29c22c0 | 6775 | return -EINVAL; |
44f46b42 | 6776 | |
f5adf94e | 6777 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6778 | hsw_compute_ips_config(crtc, pipe_config); |
6779 | ||
877d48d5 | 6780 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6781 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6782 | |
cf5a15be | 6783 | return 0; |
79e53945 JB |
6784 | } |
6785 | ||
1652d19e VS |
6786 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6787 | { | |
6788 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6789 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
6790 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6791 | uint32_t linkrate; | |
6792 | ||
414355a7 | 6793 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) |
1652d19e | 6794 | return 24000; /* 24MHz is the cd freq with NSSC ref */ |
1652d19e VS |
6795 | |
6796 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
6797 | return 540000; | |
6798 | ||
6799 | linkrate = (I915_READ(DPLL_CTRL1) & | |
71cd8423 | 6800 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; |
1652d19e | 6801 | |
71cd8423 DL |
6802 | if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || |
6803 | linkrate == DPLL_CTRL1_LINK_RATE_1080) { | |
1652d19e VS |
6804 | /* vco 8640 */ |
6805 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6806 | case CDCLK_FREQ_450_432: | |
6807 | return 432000; | |
6808 | case CDCLK_FREQ_337_308: | |
6809 | return 308570; | |
6810 | case CDCLK_FREQ_675_617: | |
6811 | return 617140; | |
6812 | default: | |
6813 | WARN(1, "Unknown cd freq selection\n"); | |
6814 | } | |
6815 | } else { | |
6816 | /* vco 8100 */ | |
6817 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6818 | case CDCLK_FREQ_450_432: | |
6819 | return 450000; | |
6820 | case CDCLK_FREQ_337_308: | |
6821 | return 337500; | |
6822 | case CDCLK_FREQ_675_617: | |
6823 | return 675000; | |
6824 | default: | |
6825 | WARN(1, "Unknown cd freq selection\n"); | |
6826 | } | |
6827 | } | |
6828 | ||
6829 | /* error case, do as if DPLL0 isn't enabled */ | |
6830 | return 24000; | |
6831 | } | |
6832 | ||
acd3f3d3 BP |
6833 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
6834 | { | |
6835 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6836 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6837 | uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; | |
6838 | uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE); | |
6839 | int cdclk; | |
6840 | ||
6841 | if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE)) | |
6842 | return 19200; | |
6843 | ||
6844 | cdclk = 19200 * pll_ratio / 2; | |
6845 | ||
6846 | switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) { | |
6847 | case BXT_CDCLK_CD2X_DIV_SEL_1: | |
6848 | return cdclk; /* 576MHz or 624MHz */ | |
6849 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: | |
6850 | return cdclk * 2 / 3; /* 384MHz */ | |
6851 | case BXT_CDCLK_CD2X_DIV_SEL_2: | |
6852 | return cdclk / 2; /* 288MHz */ | |
6853 | case BXT_CDCLK_CD2X_DIV_SEL_4: | |
6854 | return cdclk / 4; /* 144MHz */ | |
6855 | } | |
6856 | ||
6857 | /* error case, do as if DE PLL isn't enabled */ | |
6858 | return 19200; | |
6859 | } | |
6860 | ||
1652d19e VS |
6861 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
6862 | { | |
6863 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6864 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6865 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6866 | ||
6867 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6868 | return 800000; | |
6869 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6870 | return 450000; | |
6871 | else if (freq == LCPLL_CLK_FREQ_450) | |
6872 | return 450000; | |
6873 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6874 | return 540000; | |
6875 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6876 | return 337500; | |
6877 | else | |
6878 | return 675000; | |
6879 | } | |
6880 | ||
6881 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6882 | { | |
6883 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6884 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6885 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6886 | ||
6887 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6888 | return 800000; | |
6889 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6890 | return 450000; | |
6891 | else if (freq == LCPLL_CLK_FREQ_450) | |
6892 | return 450000; | |
6893 | else if (IS_HSW_ULT(dev)) | |
6894 | return 337500; | |
6895 | else | |
6896 | return 540000; | |
79e53945 JB |
6897 | } |
6898 | ||
25eb05fc JB |
6899 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6900 | { | |
bfa7df01 VS |
6901 | return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", |
6902 | CCK_DISPLAY_CLOCK_CONTROL); | |
25eb05fc JB |
6903 | } |
6904 | ||
b37a6434 VS |
6905 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6906 | { | |
6907 | return 450000; | |
6908 | } | |
6909 | ||
e70236a8 JB |
6910 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6911 | { | |
6912 | return 400000; | |
6913 | } | |
79e53945 | 6914 | |
e70236a8 | 6915 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6916 | { |
e907f170 | 6917 | return 333333; |
e70236a8 | 6918 | } |
79e53945 | 6919 | |
e70236a8 JB |
6920 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6921 | { | |
6922 | return 200000; | |
6923 | } | |
79e53945 | 6924 | |
257a7ffc DV |
6925 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6926 | { | |
6927 | u16 gcfgc = 0; | |
6928 | ||
6929 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6930 | ||
6931 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6932 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6933 | return 266667; |
257a7ffc | 6934 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6935 | return 333333; |
257a7ffc | 6936 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6937 | return 444444; |
257a7ffc DV |
6938 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6939 | return 200000; | |
6940 | default: | |
6941 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6942 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6943 | return 133333; |
257a7ffc | 6944 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6945 | return 166667; |
257a7ffc DV |
6946 | } |
6947 | } | |
6948 | ||
e70236a8 JB |
6949 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6950 | { | |
6951 | u16 gcfgc = 0; | |
79e53945 | 6952 | |
e70236a8 JB |
6953 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6954 | ||
6955 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6956 | return 133333; |
e70236a8 JB |
6957 | else { |
6958 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6959 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6960 | return 333333; |
e70236a8 JB |
6961 | default: |
6962 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6963 | return 190000; | |
79e53945 | 6964 | } |
e70236a8 JB |
6965 | } |
6966 | } | |
6967 | ||
6968 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6969 | { | |
e907f170 | 6970 | return 266667; |
e70236a8 JB |
6971 | } |
6972 | ||
1b1d2716 | 6973 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 JB |
6974 | { |
6975 | u16 hpllcc = 0; | |
1b1d2716 | 6976 | |
65cd2b3f VS |
6977 | /* |
6978 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
6979 | * encoding is different :( | |
6980 | * FIXME is this the right way to detect 852GM/852GMV? | |
6981 | */ | |
6982 | if (dev->pdev->revision == 0x1) | |
6983 | return 133333; | |
6984 | ||
1b1d2716 VS |
6985 | pci_bus_read_config_word(dev->pdev->bus, |
6986 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
6987 | ||
e70236a8 JB |
6988 | /* Assume that the hardware is in the high speed state. This |
6989 | * should be the default. | |
6990 | */ | |
6991 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6992 | case GC_CLOCK_133_200: | |
1b1d2716 | 6993 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
6994 | case GC_CLOCK_100_200: |
6995 | return 200000; | |
6996 | case GC_CLOCK_166_250: | |
6997 | return 250000; | |
6998 | case GC_CLOCK_100_133: | |
e907f170 | 6999 | return 133333; |
1b1d2716 VS |
7000 | case GC_CLOCK_133_266: |
7001 | case GC_CLOCK_133_266_2: | |
7002 | case GC_CLOCK_166_266: | |
7003 | return 266667; | |
e70236a8 | 7004 | } |
79e53945 | 7005 | |
e70236a8 JB |
7006 | /* Shouldn't happen */ |
7007 | return 0; | |
7008 | } | |
79e53945 | 7009 | |
e70236a8 JB |
7010 | static int i830_get_display_clock_speed(struct drm_device *dev) |
7011 | { | |
e907f170 | 7012 | return 133333; |
79e53945 JB |
7013 | } |
7014 | ||
34edce2f VS |
7015 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
7016 | { | |
7017 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7018 | static const unsigned int blb_vco[8] = { | |
7019 | [0] = 3200000, | |
7020 | [1] = 4000000, | |
7021 | [2] = 5333333, | |
7022 | [3] = 4800000, | |
7023 | [4] = 6400000, | |
7024 | }; | |
7025 | static const unsigned int pnv_vco[8] = { | |
7026 | [0] = 3200000, | |
7027 | [1] = 4000000, | |
7028 | [2] = 5333333, | |
7029 | [3] = 4800000, | |
7030 | [4] = 2666667, | |
7031 | }; | |
7032 | static const unsigned int cl_vco[8] = { | |
7033 | [0] = 3200000, | |
7034 | [1] = 4000000, | |
7035 | [2] = 5333333, | |
7036 | [3] = 6400000, | |
7037 | [4] = 3333333, | |
7038 | [5] = 3566667, | |
7039 | [6] = 4266667, | |
7040 | }; | |
7041 | static const unsigned int elk_vco[8] = { | |
7042 | [0] = 3200000, | |
7043 | [1] = 4000000, | |
7044 | [2] = 5333333, | |
7045 | [3] = 4800000, | |
7046 | }; | |
7047 | static const unsigned int ctg_vco[8] = { | |
7048 | [0] = 3200000, | |
7049 | [1] = 4000000, | |
7050 | [2] = 5333333, | |
7051 | [3] = 6400000, | |
7052 | [4] = 2666667, | |
7053 | [5] = 4266667, | |
7054 | }; | |
7055 | const unsigned int *vco_table; | |
7056 | unsigned int vco; | |
7057 | uint8_t tmp = 0; | |
7058 | ||
7059 | /* FIXME other chipsets? */ | |
7060 | if (IS_GM45(dev)) | |
7061 | vco_table = ctg_vco; | |
7062 | else if (IS_G4X(dev)) | |
7063 | vco_table = elk_vco; | |
7064 | else if (IS_CRESTLINE(dev)) | |
7065 | vco_table = cl_vco; | |
7066 | else if (IS_PINEVIEW(dev)) | |
7067 | vco_table = pnv_vco; | |
7068 | else if (IS_G33(dev)) | |
7069 | vco_table = blb_vco; | |
7070 | else | |
7071 | return 0; | |
7072 | ||
7073 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
7074 | ||
7075 | vco = vco_table[tmp & 0x7]; | |
7076 | if (vco == 0) | |
7077 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
7078 | else | |
7079 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
7080 | ||
7081 | return vco; | |
7082 | } | |
7083 | ||
7084 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
7085 | { | |
7086 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7087 | uint16_t tmp = 0; | |
7088 | ||
7089 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7090 | ||
7091 | cdclk_sel = (tmp >> 12) & 0x1; | |
7092 | ||
7093 | switch (vco) { | |
7094 | case 2666667: | |
7095 | case 4000000: | |
7096 | case 5333333: | |
7097 | return cdclk_sel ? 333333 : 222222; | |
7098 | case 3200000: | |
7099 | return cdclk_sel ? 320000 : 228571; | |
7100 | default: | |
7101 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
7102 | return 222222; | |
7103 | } | |
7104 | } | |
7105 | ||
7106 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
7107 | { | |
7108 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
7109 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
7110 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
7111 | const uint8_t *div_table; | |
7112 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7113 | uint16_t tmp = 0; | |
7114 | ||
7115 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7116 | ||
7117 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
7118 | ||
7119 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7120 | goto fail; | |
7121 | ||
7122 | switch (vco) { | |
7123 | case 3200000: | |
7124 | div_table = div_3200; | |
7125 | break; | |
7126 | case 4000000: | |
7127 | div_table = div_4000; | |
7128 | break; | |
7129 | case 5333333: | |
7130 | div_table = div_5333; | |
7131 | break; | |
7132 | default: | |
7133 | goto fail; | |
7134 | } | |
7135 | ||
7136 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7137 | ||
caf4e252 | 7138 | fail: |
34edce2f VS |
7139 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
7140 | return 200000; | |
7141 | } | |
7142 | ||
7143 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
7144 | { | |
7145 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
7146 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
7147 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
7148 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
7149 | const uint8_t *div_table; | |
7150 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7151 | uint16_t tmp = 0; | |
7152 | ||
7153 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7154 | ||
7155 | cdclk_sel = (tmp >> 4) & 0x7; | |
7156 | ||
7157 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7158 | goto fail; | |
7159 | ||
7160 | switch (vco) { | |
7161 | case 3200000: | |
7162 | div_table = div_3200; | |
7163 | break; | |
7164 | case 4000000: | |
7165 | div_table = div_4000; | |
7166 | break; | |
7167 | case 4800000: | |
7168 | div_table = div_4800; | |
7169 | break; | |
7170 | case 5333333: | |
7171 | div_table = div_5333; | |
7172 | break; | |
7173 | default: | |
7174 | goto fail; | |
7175 | } | |
7176 | ||
7177 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7178 | ||
caf4e252 | 7179 | fail: |
34edce2f VS |
7180 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
7181 | return 190476; | |
7182 | } | |
7183 | ||
2c07245f | 7184 | static void |
a65851af | 7185 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 7186 | { |
a65851af VS |
7187 | while (*num > DATA_LINK_M_N_MASK || |
7188 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
7189 | *num >>= 1; |
7190 | *den >>= 1; | |
7191 | } | |
7192 | } | |
7193 | ||
a65851af VS |
7194 | static void compute_m_n(unsigned int m, unsigned int n, |
7195 | uint32_t *ret_m, uint32_t *ret_n) | |
7196 | { | |
7197 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7198 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7199 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7200 | } | |
7201 | ||
e69d0bc1 DV |
7202 | void |
7203 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7204 | int pixel_clock, int link_clock, | |
7205 | struct intel_link_m_n *m_n) | |
2c07245f | 7206 | { |
e69d0bc1 | 7207 | m_n->tu = 64; |
a65851af VS |
7208 | |
7209 | compute_m_n(bits_per_pixel * pixel_clock, | |
7210 | link_clock * nlanes * 8, | |
7211 | &m_n->gmch_m, &m_n->gmch_n); | |
7212 | ||
7213 | compute_m_n(pixel_clock, link_clock, | |
7214 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7215 | } |
7216 | ||
a7615030 CW |
7217 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7218 | { | |
d330a953 JN |
7219 | if (i915.panel_use_ssc >= 0) |
7220 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7221 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7222 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7223 | } |
7224 | ||
a93e255f ACO |
7225 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
7226 | int num_connectors) | |
c65d77d8 | 7227 | { |
a93e255f | 7228 | struct drm_device *dev = crtc_state->base.crtc->dev; |
c65d77d8 JB |
7229 | struct drm_i915_private *dev_priv = dev->dev_private; |
7230 | int refclk; | |
7231 | ||
a93e255f ACO |
7232 | WARN_ON(!crtc_state->base.state); |
7233 | ||
666a4537 | 7234 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) { |
9a0ea498 | 7235 | refclk = 100000; |
a93e255f | 7236 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 7237 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
7238 | refclk = dev_priv->vbt.lvds_ssc_freq; |
7239 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
7240 | } else if (!IS_GEN2(dev)) { |
7241 | refclk = 96000; | |
7242 | } else { | |
7243 | refclk = 48000; | |
7244 | } | |
7245 | ||
7246 | return refclk; | |
7247 | } | |
7248 | ||
7429e9d4 | 7249 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7250 | { |
7df00d7a | 7251 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7252 | } |
f47709a9 | 7253 | |
7429e9d4 DV |
7254 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7255 | { | |
7256 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7257 | } |
7258 | ||
f47709a9 | 7259 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7260 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
7261 | intel_clock_t *reduced_clock) |
7262 | { | |
f47709a9 | 7263 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
7264 | u32 fp, fp2 = 0; |
7265 | ||
7266 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 7267 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7268 | if (reduced_clock) |
7429e9d4 | 7269 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7270 | } else { |
190f68c5 | 7271 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7272 | if (reduced_clock) |
7429e9d4 | 7273 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7274 | } |
7275 | ||
190f68c5 | 7276 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7277 | |
f47709a9 | 7278 | crtc->lowfreq_avail = false; |
a93e255f | 7279 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7280 | reduced_clock) { |
190f68c5 | 7281 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7282 | crtc->lowfreq_avail = true; |
a7516a05 | 7283 | } else { |
190f68c5 | 7284 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7285 | } |
7286 | } | |
7287 | ||
5e69f97f CML |
7288 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7289 | pipe) | |
89b667f8 JB |
7290 | { |
7291 | u32 reg_val; | |
7292 | ||
7293 | /* | |
7294 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7295 | * and set it to a reasonable value instead. | |
7296 | */ | |
ab3c759a | 7297 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7298 | reg_val &= 0xffffff00; |
7299 | reg_val |= 0x00000030; | |
ab3c759a | 7300 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7301 | |
ab3c759a | 7302 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7303 | reg_val &= 0x8cffffff; |
7304 | reg_val = 0x8c000000; | |
ab3c759a | 7305 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7306 | |
ab3c759a | 7307 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7308 | reg_val &= 0xffffff00; |
ab3c759a | 7309 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7310 | |
ab3c759a | 7311 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7312 | reg_val &= 0x00ffffff; |
7313 | reg_val |= 0xb0000000; | |
ab3c759a | 7314 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7315 | } |
7316 | ||
b551842d DV |
7317 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7318 | struct intel_link_m_n *m_n) | |
7319 | { | |
7320 | struct drm_device *dev = crtc->base.dev; | |
7321 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7322 | int pipe = crtc->pipe; | |
7323 | ||
e3b95f1e DV |
7324 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7325 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7326 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7327 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7328 | } |
7329 | ||
7330 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7331 | struct intel_link_m_n *m_n, |
7332 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7333 | { |
7334 | struct drm_device *dev = crtc->base.dev; | |
7335 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7336 | int pipe = crtc->pipe; | |
6e3c9717 | 7337 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7338 | |
7339 | if (INTEL_INFO(dev)->gen >= 5) { | |
7340 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7341 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7342 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7343 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7344 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7345 | * for gen < 8) and if DRRS is supported (to make sure the | |
7346 | * registers are not unnecessarily accessed). | |
7347 | */ | |
44395bfe | 7348 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 7349 | crtc->config->has_drrs) { |
f769cd24 VK |
7350 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7351 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7352 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7353 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7354 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7355 | } | |
b551842d | 7356 | } else { |
e3b95f1e DV |
7357 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7358 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7359 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7360 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7361 | } |
7362 | } | |
7363 | ||
fe3cd48d | 7364 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7365 | { |
fe3cd48d R |
7366 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7367 | ||
7368 | if (m_n == M1_N1) { | |
7369 | dp_m_n = &crtc->config->dp_m_n; | |
7370 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7371 | } else if (m_n == M2_N2) { | |
7372 | ||
7373 | /* | |
7374 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7375 | * needs to be programmed into M1_N1. | |
7376 | */ | |
7377 | dp_m_n = &crtc->config->dp_m2_n2; | |
7378 | } else { | |
7379 | DRM_ERROR("Unsupported divider value\n"); | |
7380 | return; | |
7381 | } | |
7382 | ||
6e3c9717 ACO |
7383 | if (crtc->config->has_pch_encoder) |
7384 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7385 | else |
fe3cd48d | 7386 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7387 | } |
7388 | ||
251ac862 DV |
7389 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7390 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 DV |
7391 | { |
7392 | u32 dpll, dpll_md; | |
7393 | ||
7394 | /* | |
7395 | * Enable DPIO clock input. We should never disable the reference | |
7396 | * clock for pipe B, since VGA hotplug / manual detection depends | |
7397 | * on it. | |
7398 | */ | |
60bfe44f VS |
7399 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV | |
7400 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV; | |
bdd4b6a6 DV |
7401 | /* We should never disable this, set it here for state tracking */ |
7402 | if (crtc->pipe == PIPE_B) | |
7403 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7404 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 7405 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 7406 | |
d288f65f | 7407 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 7408 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 7409 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
7410 | } |
7411 | ||
d288f65f | 7412 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7413 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7414 | { |
f47709a9 | 7415 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 7416 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 7417 | int pipe = crtc->pipe; |
bdd4b6a6 | 7418 | u32 mdiv; |
a0c4da24 | 7419 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7420 | u32 coreclk, reg_val; |
a0c4da24 | 7421 | |
a580516d | 7422 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7423 | |
d288f65f VS |
7424 | bestn = pipe_config->dpll.n; |
7425 | bestm1 = pipe_config->dpll.m1; | |
7426 | bestm2 = pipe_config->dpll.m2; | |
7427 | bestp1 = pipe_config->dpll.p1; | |
7428 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7429 | |
89b667f8 JB |
7430 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7431 | ||
7432 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7433 | if (pipe == PIPE_B) |
5e69f97f | 7434 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7435 | |
7436 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7437 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7438 | |
7439 | /* Disable target IRef on PLL */ | |
ab3c759a | 7440 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7441 | reg_val &= 0x00ffffff; |
ab3c759a | 7442 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7443 | |
7444 | /* Disable fast lock */ | |
ab3c759a | 7445 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7446 | |
7447 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7448 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7449 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7450 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7451 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7452 | |
7453 | /* | |
7454 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7455 | * but we don't support that). | |
7456 | * Note: don't use the DAC post divider as it seems unstable. | |
7457 | */ | |
7458 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7459 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7460 | |
a0c4da24 | 7461 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7462 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7463 | |
89b667f8 | 7464 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7465 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
7466 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
7467 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7468 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7469 | 0x009f0003); |
89b667f8 | 7470 | else |
ab3c759a | 7471 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7472 | 0x00d0000f); |
7473 | ||
681a8504 | 7474 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 7475 | /* Use SSC source */ |
bdd4b6a6 | 7476 | if (pipe == PIPE_A) |
ab3c759a | 7477 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7478 | 0x0df40000); |
7479 | else | |
ab3c759a | 7480 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7481 | 0x0df70000); |
7482 | } else { /* HDMI or VGA */ | |
7483 | /* Use bend source */ | |
bdd4b6a6 | 7484 | if (pipe == PIPE_A) |
ab3c759a | 7485 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7486 | 0x0df70000); |
7487 | else | |
ab3c759a | 7488 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7489 | 0x0df40000); |
7490 | } | |
a0c4da24 | 7491 | |
ab3c759a | 7492 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7493 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
7494 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
7495 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 7496 | coreclk |= 0x01000000; |
ab3c759a | 7497 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7498 | |
ab3c759a | 7499 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7500 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7501 | } |
7502 | ||
251ac862 DV |
7503 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7504 | struct intel_crtc_state *pipe_config) | |
1ae0d137 | 7505 | { |
60bfe44f VS |
7506 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | |
7507 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | | |
1ae0d137 VS |
7508 | DPLL_VCO_ENABLE; |
7509 | if (crtc->pipe != PIPE_A) | |
d288f65f | 7510 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 7511 | |
d288f65f VS |
7512 | pipe_config->dpll_hw_state.dpll_md = |
7513 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
7514 | } |
7515 | ||
d288f65f | 7516 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7517 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7518 | { |
7519 | struct drm_device *dev = crtc->base.dev; | |
7520 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7521 | int pipe = crtc->pipe; | |
f0f59a00 | 7522 | i915_reg_t dpll_reg = DPLL(crtc->pipe); |
9d556c99 | 7523 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 7524 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7525 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7526 | u32 dpio_val; |
9cbe40c1 | 7527 | int vco; |
9d556c99 | 7528 | |
d288f65f VS |
7529 | bestn = pipe_config->dpll.n; |
7530 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7531 | bestm1 = pipe_config->dpll.m1; | |
7532 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7533 | bestp1 = pipe_config->dpll.p1; | |
7534 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7535 | vco = pipe_config->dpll.vco; |
a945ce7e | 7536 | dpio_val = 0; |
9cbe40c1 | 7537 | loopfilter = 0; |
9d556c99 CML |
7538 | |
7539 | /* | |
7540 | * Enable Refclk and SSC | |
7541 | */ | |
a11b0703 | 7542 | I915_WRITE(dpll_reg, |
d288f65f | 7543 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 | 7544 | |
a580516d | 7545 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7546 | |
9d556c99 CML |
7547 | /* p1 and p2 divider */ |
7548 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7549 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7550 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7551 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7552 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7553 | ||
7554 | /* Feedback post-divider - m2 */ | |
7555 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7556 | ||
7557 | /* Feedback refclk divider - n and m1 */ | |
7558 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7559 | DPIO_CHV_M1_DIV_BY_2 | | |
7560 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7561 | ||
7562 | /* M2 fraction division */ | |
25a25dfc | 7563 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
7564 | |
7565 | /* M2 fraction division enable */ | |
a945ce7e VP |
7566 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7567 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7568 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7569 | if (bestm2_frac) | |
7570 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7571 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7572 | |
de3a0fde VP |
7573 | /* Program digital lock detect threshold */ |
7574 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7575 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7576 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7577 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7578 | if (!bestm2_frac) | |
7579 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7580 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7581 | ||
9d556c99 | 7582 | /* Loop filter */ |
9cbe40c1 VP |
7583 | if (vco == 5400000) { |
7584 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7585 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7586 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7587 | tribuf_calcntr = 0x9; | |
7588 | } else if (vco <= 6200000) { | |
7589 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7590 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7591 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7592 | tribuf_calcntr = 0x9; | |
7593 | } else if (vco <= 6480000) { | |
7594 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7595 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7596 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7597 | tribuf_calcntr = 0x8; | |
7598 | } else { | |
7599 | /* Not supported. Apply the same limits as in the max case */ | |
7600 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7601 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7602 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7603 | tribuf_calcntr = 0; | |
7604 | } | |
9d556c99 CML |
7605 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7606 | ||
968040b2 | 7607 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7608 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7609 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7610 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7611 | ||
9d556c99 CML |
7612 | /* AFC Recal */ |
7613 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7614 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7615 | DPIO_AFC_RECAL); | |
7616 | ||
a580516d | 7617 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
7618 | } |
7619 | ||
d288f65f VS |
7620 | /** |
7621 | * vlv_force_pll_on - forcibly enable just the PLL | |
7622 | * @dev_priv: i915 private structure | |
7623 | * @pipe: pipe PLL to enable | |
7624 | * @dpll: PLL configuration | |
7625 | * | |
7626 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7627 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7628 | * be enabled. | |
7629 | */ | |
7630 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, | |
7631 | const struct dpll *dpll) | |
7632 | { | |
7633 | struct intel_crtc *crtc = | |
7634 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
5cec258b | 7635 | struct intel_crtc_state pipe_config = { |
a93e255f | 7636 | .base.crtc = &crtc->base, |
d288f65f VS |
7637 | .pixel_multiplier = 1, |
7638 | .dpll = *dpll, | |
7639 | }; | |
7640 | ||
7641 | if (IS_CHERRYVIEW(dev)) { | |
251ac862 | 7642 | chv_compute_dpll(crtc, &pipe_config); |
d288f65f VS |
7643 | chv_prepare_pll(crtc, &pipe_config); |
7644 | chv_enable_pll(crtc, &pipe_config); | |
7645 | } else { | |
251ac862 | 7646 | vlv_compute_dpll(crtc, &pipe_config); |
d288f65f VS |
7647 | vlv_prepare_pll(crtc, &pipe_config); |
7648 | vlv_enable_pll(crtc, &pipe_config); | |
7649 | } | |
7650 | } | |
7651 | ||
7652 | /** | |
7653 | * vlv_force_pll_off - forcibly disable just the PLL | |
7654 | * @dev_priv: i915 private structure | |
7655 | * @pipe: pipe PLL to disable | |
7656 | * | |
7657 | * Disable the PLL for @pipe. To be used in cases where we need | |
7658 | * the PLL enabled even when @pipe is not going to be enabled. | |
7659 | */ | |
7660 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7661 | { | |
7662 | if (IS_CHERRYVIEW(dev)) | |
7663 | chv_disable_pll(to_i915(dev), pipe); | |
7664 | else | |
7665 | vlv_disable_pll(to_i915(dev), pipe); | |
7666 | } | |
7667 | ||
251ac862 DV |
7668 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
7669 | struct intel_crtc_state *crtc_state, | |
7670 | intel_clock_t *reduced_clock, | |
7671 | int num_connectors) | |
eb1cbe48 | 7672 | { |
f47709a9 | 7673 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7674 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
7675 | u32 dpll; |
7676 | bool is_sdvo; | |
190f68c5 | 7677 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7678 | |
190f68c5 | 7679 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7680 | |
a93e255f ACO |
7681 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7682 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
7683 | |
7684 | dpll = DPLL_VGA_MODE_DIS; | |
7685 | ||
a93e255f | 7686 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7687 | dpll |= DPLLB_MODE_LVDS; |
7688 | else | |
7689 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7690 | |
ef1b460d | 7691 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7692 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7693 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7694 | } |
198a037f DV |
7695 | |
7696 | if (is_sdvo) | |
4a33e48d | 7697 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7698 | |
190f68c5 | 7699 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7700 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7701 | |
7702 | /* compute bitmask from p1 value */ | |
7703 | if (IS_PINEVIEW(dev)) | |
7704 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7705 | else { | |
7706 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7707 | if (IS_G4X(dev) && reduced_clock) | |
7708 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7709 | } | |
7710 | switch (clock->p2) { | |
7711 | case 5: | |
7712 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7713 | break; | |
7714 | case 7: | |
7715 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7716 | break; | |
7717 | case 10: | |
7718 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7719 | break; | |
7720 | case 14: | |
7721 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7722 | break; | |
7723 | } | |
7724 | if (INTEL_INFO(dev)->gen >= 4) | |
7725 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7726 | ||
190f68c5 | 7727 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7728 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 7729 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7730 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7731 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7732 | else | |
7733 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7734 | ||
7735 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7736 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7737 | |
eb1cbe48 | 7738 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7739 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7740 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7741 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7742 | } |
7743 | } | |
7744 | ||
251ac862 DV |
7745 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
7746 | struct intel_crtc_state *crtc_state, | |
7747 | intel_clock_t *reduced_clock, | |
7748 | int num_connectors) | |
eb1cbe48 | 7749 | { |
f47709a9 | 7750 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7751 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 7752 | u32 dpll; |
190f68c5 | 7753 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7754 | |
190f68c5 | 7755 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7756 | |
eb1cbe48 DV |
7757 | dpll = DPLL_VGA_MODE_DIS; |
7758 | ||
a93e255f | 7759 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7760 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7761 | } else { | |
7762 | if (clock->p1 == 2) | |
7763 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7764 | else | |
7765 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7766 | if (clock->p2 == 4) | |
7767 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7768 | } | |
7769 | ||
a93e255f | 7770 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7771 | dpll |= DPLL_DVO_2X_MODE; |
7772 | ||
a93e255f | 7773 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7774 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7775 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7776 | else | |
7777 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7778 | ||
7779 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7780 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7781 | } |
7782 | ||
8a654f3b | 7783 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7784 | { |
7785 | struct drm_device *dev = intel_crtc->base.dev; | |
7786 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7787 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 7788 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 7789 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7790 | uint32_t crtc_vtotal, crtc_vblank_end; |
7791 | int vsyncshift = 0; | |
4d8a62ea DV |
7792 | |
7793 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7794 | * the hw state checker will get angry at the mismatch. */ | |
7795 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7796 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7797 | |
609aeaca | 7798 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7799 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7800 | crtc_vtotal -= 1; |
7801 | crtc_vblank_end -= 1; | |
609aeaca | 7802 | |
409ee761 | 7803 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7804 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7805 | else | |
7806 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7807 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7808 | if (vsyncshift < 0) |
7809 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7810 | } |
7811 | ||
7812 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7813 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7814 | |
fe2b8f9d | 7815 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7816 | (adjusted_mode->crtc_hdisplay - 1) | |
7817 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7818 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7819 | (adjusted_mode->crtc_hblank_start - 1) | |
7820 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7821 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7822 | (adjusted_mode->crtc_hsync_start - 1) | |
7823 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7824 | ||
fe2b8f9d | 7825 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7826 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7827 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7828 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7829 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7830 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7831 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7832 | (adjusted_mode->crtc_vsync_start - 1) | |
7833 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7834 | ||
b5e508d4 PZ |
7835 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7836 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7837 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7838 | * bits. */ | |
7839 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7840 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7841 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7842 | ||
b0e77b9c PZ |
7843 | /* pipesrc controls the size that is scaled from, which should |
7844 | * always be the user's requested size. | |
7845 | */ | |
7846 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7847 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7848 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7849 | } |
7850 | ||
1bd1bd80 | 7851 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7852 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7853 | { |
7854 | struct drm_device *dev = crtc->base.dev; | |
7855 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7856 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7857 | uint32_t tmp; | |
7858 | ||
7859 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7860 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7861 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7862 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7863 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7864 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7865 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7866 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7867 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7868 | |
7869 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7870 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7871 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7872 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7873 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7874 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7875 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7876 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7877 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7878 | |
7879 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7880 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7881 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7882 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 DV |
7883 | } |
7884 | ||
7885 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7886 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7887 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7888 | ||
2d112de7 ACO |
7889 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7890 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7891 | } |
7892 | ||
f6a83288 | 7893 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7894 | struct intel_crtc_state *pipe_config) |
babea61d | 7895 | { |
2d112de7 ACO |
7896 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7897 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7898 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7899 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7900 | |
2d112de7 ACO |
7901 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7902 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7903 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7904 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7905 | |
2d112de7 | 7906 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7907 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7908 | |
2d112de7 ACO |
7909 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7910 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
7911 | |
7912 | mode->hsync = drm_mode_hsync(mode); | |
7913 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7914 | drm_mode_set_name(mode); | |
babea61d JB |
7915 | } |
7916 | ||
84b046f3 DV |
7917 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7918 | { | |
7919 | struct drm_device *dev = intel_crtc->base.dev; | |
7920 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7921 | uint32_t pipeconf; | |
7922 | ||
9f11a9e4 | 7923 | pipeconf = 0; |
84b046f3 | 7924 | |
b6b5d049 VS |
7925 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7926 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7927 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7928 | |
6e3c9717 | 7929 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7930 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7931 | |
ff9ce46e | 7932 | /* only g4x and later have fancy bpc/dither controls */ |
666a4537 | 7933 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
ff9ce46e | 7934 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7935 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7936 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7937 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7938 | |
6e3c9717 | 7939 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7940 | case 18: |
7941 | pipeconf |= PIPECONF_6BPC; | |
7942 | break; | |
7943 | case 24: | |
7944 | pipeconf |= PIPECONF_8BPC; | |
7945 | break; | |
7946 | case 30: | |
7947 | pipeconf |= PIPECONF_10BPC; | |
7948 | break; | |
7949 | default: | |
7950 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7951 | BUG(); | |
84b046f3 DV |
7952 | } |
7953 | } | |
7954 | ||
7955 | if (HAS_PIPE_CXSR(dev)) { | |
7956 | if (intel_crtc->lowfreq_avail) { | |
7957 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7958 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7959 | } else { | |
7960 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7961 | } |
7962 | } | |
7963 | ||
6e3c9717 | 7964 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7965 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 7966 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7967 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7968 | else | |
7969 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7970 | } else | |
84b046f3 DV |
7971 | pipeconf |= PIPECONF_PROGRESSIVE; |
7972 | ||
666a4537 WB |
7973 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
7974 | intel_crtc->config->limited_color_range) | |
9f11a9e4 | 7975 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7976 | |
84b046f3 DV |
7977 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7978 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7979 | } | |
7980 | ||
190f68c5 ACO |
7981 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7982 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7983 | { |
c7653199 | 7984 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7985 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 7986 | int refclk, num_connectors = 0; |
c329a4ec DV |
7987 | intel_clock_t clock; |
7988 | bool ok; | |
d4906093 | 7989 | const intel_limit_t *limit; |
55bb9992 | 7990 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 7991 | struct drm_connector *connector; |
55bb9992 ACO |
7992 | struct drm_connector_state *connector_state; |
7993 | int i; | |
79e53945 | 7994 | |
dd3cd74a ACO |
7995 | memset(&crtc_state->dpll_hw_state, 0, |
7996 | sizeof(crtc_state->dpll_hw_state)); | |
7997 | ||
a65347ba JN |
7998 | if (crtc_state->has_dsi_encoder) |
7999 | return 0; | |
43565a06 | 8000 | |
a65347ba JN |
8001 | for_each_connector_in_state(state, connector, connector_state, i) { |
8002 | if (connector_state->crtc == &crtc->base) | |
8003 | num_connectors++; | |
79e53945 JB |
8004 | } |
8005 | ||
190f68c5 | 8006 | if (!crtc_state->clock_set) { |
a93e255f | 8007 | refclk = i9xx_get_refclk(crtc_state, num_connectors); |
79e53945 | 8008 | |
e9fd1c02 JN |
8009 | /* |
8010 | * Returns a set of divisors for the desired target clock with | |
8011 | * the given refclk, or FALSE. The returned values represent | |
8012 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
8013 | * 2) / p1 / p2. | |
8014 | */ | |
a93e255f ACO |
8015 | limit = intel_limit(crtc_state, refclk); |
8016 | ok = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 8017 | crtc_state->port_clock, |
e9fd1c02 | 8018 | refclk, NULL, &clock); |
f2335330 | 8019 | if (!ok) { |
e9fd1c02 JN |
8020 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8021 | return -EINVAL; | |
8022 | } | |
79e53945 | 8023 | |
f2335330 | 8024 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
8025 | crtc_state->dpll.n = clock.n; |
8026 | crtc_state->dpll.m1 = clock.m1; | |
8027 | crtc_state->dpll.m2 = clock.m2; | |
8028 | crtc_state->dpll.p1 = clock.p1; | |
8029 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 8030 | } |
7026d4ac | 8031 | |
e9fd1c02 | 8032 | if (IS_GEN2(dev)) { |
c329a4ec | 8033 | i8xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 8034 | num_connectors); |
9d556c99 | 8035 | } else if (IS_CHERRYVIEW(dev)) { |
251ac862 | 8036 | chv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 8037 | } else if (IS_VALLEYVIEW(dev)) { |
251ac862 | 8038 | vlv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 8039 | } else { |
c329a4ec | 8040 | i9xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 8041 | num_connectors); |
e9fd1c02 | 8042 | } |
79e53945 | 8043 | |
c8f7a0db | 8044 | return 0; |
f564048e EA |
8045 | } |
8046 | ||
2fa2fe9a | 8047 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8048 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8049 | { |
8050 | struct drm_device *dev = crtc->base.dev; | |
8051 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8052 | uint32_t tmp; | |
8053 | ||
dc9e7dec VS |
8054 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
8055 | return; | |
8056 | ||
2fa2fe9a | 8057 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
8058 | if (!(tmp & PFIT_ENABLE)) |
8059 | return; | |
2fa2fe9a | 8060 | |
06922821 | 8061 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
8062 | if (INTEL_INFO(dev)->gen < 4) { |
8063 | if (crtc->pipe != PIPE_B) | |
8064 | return; | |
2fa2fe9a DV |
8065 | } else { |
8066 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
8067 | return; | |
8068 | } | |
8069 | ||
06922821 | 8070 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
8071 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
8072 | if (INTEL_INFO(dev)->gen < 5) | |
8073 | pipe_config->gmch_pfit.lvds_border_bits = | |
8074 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
8075 | } | |
8076 | ||
acbec814 | 8077 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8078 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
8079 | { |
8080 | struct drm_device *dev = crtc->base.dev; | |
8081 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8082 | int pipe = pipe_config->cpu_transcoder; | |
8083 | intel_clock_t clock; | |
8084 | u32 mdiv; | |
662c6ecb | 8085 | int refclk = 100000; |
acbec814 | 8086 | |
f573de5a SK |
8087 | /* In case of MIPI DPLL will not even be used */ |
8088 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
8089 | return; | |
8090 | ||
a580516d | 8091 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 8092 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 8093 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
8094 | |
8095 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
8096 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
8097 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
8098 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
8099 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
8100 | ||
dccbea3b | 8101 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
8102 | } |
8103 | ||
5724dbd1 DL |
8104 | static void |
8105 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
8106 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
8107 | { |
8108 | struct drm_device *dev = crtc->base.dev; | |
8109 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8110 | u32 val, base, offset; | |
8111 | int pipe = crtc->pipe, plane = crtc->plane; | |
8112 | int fourcc, pixel_format; | |
6761dd31 | 8113 | unsigned int aligned_height; |
b113d5ee | 8114 | struct drm_framebuffer *fb; |
1b842c89 | 8115 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 8116 | |
42a7b088 DL |
8117 | val = I915_READ(DSPCNTR(plane)); |
8118 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8119 | return; | |
8120 | ||
d9806c9f | 8121 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8122 | if (!intel_fb) { |
1ad292b5 JB |
8123 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8124 | return; | |
8125 | } | |
8126 | ||
1b842c89 DL |
8127 | fb = &intel_fb->base; |
8128 | ||
18c5247e DV |
8129 | if (INTEL_INFO(dev)->gen >= 4) { |
8130 | if (val & DISPPLANE_TILED) { | |
49af449b | 8131 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8132 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8133 | } | |
8134 | } | |
1ad292b5 JB |
8135 | |
8136 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8137 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8138 | fb->pixel_format = fourcc; |
8139 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
8140 | |
8141 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 8142 | if (plane_config->tiling) |
1ad292b5 JB |
8143 | offset = I915_READ(DSPTILEOFF(plane)); |
8144 | else | |
8145 | offset = I915_READ(DSPLINOFF(plane)); | |
8146 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8147 | } else { | |
8148 | base = I915_READ(DSPADDR(plane)); | |
8149 | } | |
8150 | plane_config->base = base; | |
8151 | ||
8152 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8153 | fb->width = ((val >> 16) & 0xfff) + 1; |
8154 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8155 | |
8156 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8157 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8158 | |
b113d5ee | 8159 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8160 | fb->pixel_format, |
8161 | fb->modifier[0]); | |
1ad292b5 | 8162 | |
f37b5c2b | 8163 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8164 | |
2844a921 DL |
8165 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8166 | pipe_name(pipe), plane, fb->width, fb->height, | |
8167 | fb->bits_per_pixel, base, fb->pitches[0], | |
8168 | plane_config->size); | |
1ad292b5 | 8169 | |
2d14030b | 8170 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8171 | } |
8172 | ||
70b23a98 | 8173 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8174 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8175 | { |
8176 | struct drm_device *dev = crtc->base.dev; | |
8177 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8178 | int pipe = pipe_config->cpu_transcoder; | |
8179 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
8180 | intel_clock_t clock; | |
0d7b6b11 | 8181 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8182 | int refclk = 100000; |
8183 | ||
a580516d | 8184 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8185 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8186 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8187 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8188 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8189 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8190 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8191 | |
8192 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8193 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8194 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8195 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8196 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8197 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8198 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8199 | ||
dccbea3b | 8200 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8201 | } |
8202 | ||
0e8ffe1b | 8203 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8204 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8205 | { |
8206 | struct drm_device *dev = crtc->base.dev; | |
8207 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8208 | uint32_t tmp; | |
8209 | ||
f458ebbc DV |
8210 | if (!intel_display_power_is_enabled(dev_priv, |
8211 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
b5482bd0 ID |
8212 | return false; |
8213 | ||
e143a21c | 8214 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 8215 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 8216 | |
0e8ffe1b DV |
8217 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8218 | if (!(tmp & PIPECONF_ENABLE)) | |
8219 | return false; | |
8220 | ||
666a4537 | 8221 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
42571aef VS |
8222 | switch (tmp & PIPECONF_BPC_MASK) { |
8223 | case PIPECONF_6BPC: | |
8224 | pipe_config->pipe_bpp = 18; | |
8225 | break; | |
8226 | case PIPECONF_8BPC: | |
8227 | pipe_config->pipe_bpp = 24; | |
8228 | break; | |
8229 | case PIPECONF_10BPC: | |
8230 | pipe_config->pipe_bpp = 30; | |
8231 | break; | |
8232 | default: | |
8233 | break; | |
8234 | } | |
8235 | } | |
8236 | ||
666a4537 WB |
8237 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
8238 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) | |
b5a9fa09 DV |
8239 | pipe_config->limited_color_range = true; |
8240 | ||
282740f7 VS |
8241 | if (INTEL_INFO(dev)->gen < 4) |
8242 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8243 | ||
1bd1bd80 DV |
8244 | intel_get_pipe_timings(crtc, pipe_config); |
8245 | ||
2fa2fe9a DV |
8246 | i9xx_get_pfit_config(crtc, pipe_config); |
8247 | ||
6c49f241 DV |
8248 | if (INTEL_INFO(dev)->gen >= 4) { |
8249 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
8250 | pipe_config->pixel_multiplier = | |
8251 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8252 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8253 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
8254 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
8255 | tmp = I915_READ(DPLL(crtc->pipe)); | |
8256 | pipe_config->pixel_multiplier = | |
8257 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8258 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8259 | } else { | |
8260 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8261 | * port and will be fixed up in the encoder->get_config | |
8262 | * function. */ | |
8263 | pipe_config->pixel_multiplier = 1; | |
8264 | } | |
8bcc2795 | 8265 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
666a4537 | 8266 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
1c4e0274 VS |
8267 | /* |
8268 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8269 | * on 830. Filter it out here so that we don't | |
8270 | * report errors due to that. | |
8271 | */ | |
8272 | if (IS_I830(dev)) | |
8273 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
8274 | ||
8bcc2795 DV |
8275 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8276 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8277 | } else { |
8278 | /* Mask out read-only status bits. */ | |
8279 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8280 | DPLL_PORTC_READY_MASK | | |
8281 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8282 | } |
6c49f241 | 8283 | |
70b23a98 VS |
8284 | if (IS_CHERRYVIEW(dev)) |
8285 | chv_crtc_clock_get(crtc, pipe_config); | |
8286 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
8287 | vlv_crtc_clock_get(crtc, pipe_config); |
8288 | else | |
8289 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8290 | |
0f64614d VS |
8291 | /* |
8292 | * Normally the dotclock is filled in by the encoder .get_config() | |
8293 | * but in case the pipe is enabled w/o any ports we need a sane | |
8294 | * default. | |
8295 | */ | |
8296 | pipe_config->base.adjusted_mode.crtc_clock = | |
8297 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8298 | ||
0e8ffe1b DV |
8299 | return true; |
8300 | } | |
8301 | ||
dde86e2d | 8302 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
8303 | { |
8304 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 8305 | struct intel_encoder *encoder; |
74cfd7ac | 8306 | u32 val, final; |
13d83a67 | 8307 | bool has_lvds = false; |
199e5d79 | 8308 | bool has_cpu_edp = false; |
199e5d79 | 8309 | bool has_panel = false; |
99eb6a01 KP |
8310 | bool has_ck505 = false; |
8311 | bool can_ssc = false; | |
13d83a67 JB |
8312 | |
8313 | /* We need to take the global config into account */ | |
b2784e15 | 8314 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8315 | switch (encoder->type) { |
8316 | case INTEL_OUTPUT_LVDS: | |
8317 | has_panel = true; | |
8318 | has_lvds = true; | |
8319 | break; | |
8320 | case INTEL_OUTPUT_EDP: | |
8321 | has_panel = true; | |
2de6905f | 8322 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8323 | has_cpu_edp = true; |
8324 | break; | |
6847d71b PZ |
8325 | default: |
8326 | break; | |
13d83a67 JB |
8327 | } |
8328 | } | |
8329 | ||
99eb6a01 | 8330 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 8331 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8332 | can_ssc = has_ck505; |
8333 | } else { | |
8334 | has_ck505 = false; | |
8335 | can_ssc = true; | |
8336 | } | |
8337 | ||
2de6905f ID |
8338 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
8339 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
8340 | |
8341 | /* Ironlake: try to setup display ref clock before DPLL | |
8342 | * enabling. This is only under driver's control after | |
8343 | * PCH B stepping, previous chipset stepping should be | |
8344 | * ignoring this setting. | |
8345 | */ | |
74cfd7ac CW |
8346 | val = I915_READ(PCH_DREF_CONTROL); |
8347 | ||
8348 | /* As we must carefully and slowly disable/enable each source in turn, | |
8349 | * compute the final state we want first and check if we need to | |
8350 | * make any changes at all. | |
8351 | */ | |
8352 | final = val; | |
8353 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8354 | if (has_ck505) | |
8355 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8356 | else | |
8357 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8358 | ||
8359 | final &= ~DREF_SSC_SOURCE_MASK; | |
8360 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
8361 | final &= ~DREF_SSC1_ENABLE; | |
8362 | ||
8363 | if (has_panel) { | |
8364 | final |= DREF_SSC_SOURCE_ENABLE; | |
8365 | ||
8366 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8367 | final |= DREF_SSC1_ENABLE; | |
8368 | ||
8369 | if (has_cpu_edp) { | |
8370 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8371 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8372 | else | |
8373 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8374 | } else | |
8375 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8376 | } else { | |
8377 | final |= DREF_SSC_SOURCE_DISABLE; | |
8378 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8379 | } | |
8380 | ||
8381 | if (final == val) | |
8382 | return; | |
8383 | ||
13d83a67 | 8384 | /* Always enable nonspread source */ |
74cfd7ac | 8385 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8386 | |
99eb6a01 | 8387 | if (has_ck505) |
74cfd7ac | 8388 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 8389 | else |
74cfd7ac | 8390 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 8391 | |
199e5d79 | 8392 | if (has_panel) { |
74cfd7ac CW |
8393 | val &= ~DREF_SSC_SOURCE_MASK; |
8394 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 8395 | |
199e5d79 | 8396 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 8397 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8398 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 8399 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 8400 | } else |
74cfd7ac | 8401 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
8402 | |
8403 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 8404 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8405 | POSTING_READ(PCH_DREF_CONTROL); |
8406 | udelay(200); | |
8407 | ||
74cfd7ac | 8408 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
8409 | |
8410 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 8411 | if (has_cpu_edp) { |
99eb6a01 | 8412 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8413 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 8414 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 8415 | } else |
74cfd7ac | 8416 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 8417 | } else |
74cfd7ac | 8418 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8419 | |
74cfd7ac | 8420 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8421 | POSTING_READ(PCH_DREF_CONTROL); |
8422 | udelay(200); | |
8423 | } else { | |
8424 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
8425 | ||
74cfd7ac | 8426 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
8427 | |
8428 | /* Turn off CPU output */ | |
74cfd7ac | 8429 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8430 | |
74cfd7ac | 8431 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8432 | POSTING_READ(PCH_DREF_CONTROL); |
8433 | udelay(200); | |
8434 | ||
8435 | /* Turn off the SSC source */ | |
74cfd7ac CW |
8436 | val &= ~DREF_SSC_SOURCE_MASK; |
8437 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
8438 | |
8439 | /* Turn off SSC1 */ | |
74cfd7ac | 8440 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 8441 | |
74cfd7ac | 8442 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
8443 | POSTING_READ(PCH_DREF_CONTROL); |
8444 | udelay(200); | |
8445 | } | |
74cfd7ac CW |
8446 | |
8447 | BUG_ON(val != final); | |
13d83a67 JB |
8448 | } |
8449 | ||
f31f2d55 | 8450 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 8451 | { |
f31f2d55 | 8452 | uint32_t tmp; |
dde86e2d | 8453 | |
0ff066a9 PZ |
8454 | tmp = I915_READ(SOUTH_CHICKEN2); |
8455 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8456 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8457 | |
0ff066a9 PZ |
8458 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
8459 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
8460 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 8461 | |
0ff066a9 PZ |
8462 | tmp = I915_READ(SOUTH_CHICKEN2); |
8463 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8464 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8465 | |
0ff066a9 PZ |
8466 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
8467 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
8468 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
8469 | } |
8470 | ||
8471 | /* WaMPhyProgramming:hsw */ | |
8472 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8473 | { | |
8474 | uint32_t tmp; | |
dde86e2d PZ |
8475 | |
8476 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8477 | tmp &= ~(0xFF << 24); | |
8478 | tmp |= (0x12 << 24); | |
8479 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8480 | ||
dde86e2d PZ |
8481 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
8482 | tmp |= (1 << 11); | |
8483 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8484 | ||
8485 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8486 | tmp |= (1 << 11); | |
8487 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8488 | ||
dde86e2d PZ |
8489 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
8490 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8491 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
8492 | ||
8493 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
8494 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8495 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8496 | ||
0ff066a9 PZ |
8497 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
8498 | tmp &= ~(7 << 13); | |
8499 | tmp |= (5 << 13); | |
8500 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 8501 | |
0ff066a9 PZ |
8502 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
8503 | tmp &= ~(7 << 13); | |
8504 | tmp |= (5 << 13); | |
8505 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
8506 | |
8507 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8508 | tmp &= ~0xFF; | |
8509 | tmp |= 0x1C; | |
8510 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8511 | ||
8512 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8513 | tmp &= ~0xFF; | |
8514 | tmp |= 0x1C; | |
8515 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8516 | ||
8517 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8518 | tmp &= ~(0xFF << 16); | |
8519 | tmp |= (0x1C << 16); | |
8520 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8521 | ||
8522 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8523 | tmp &= ~(0xFF << 16); | |
8524 | tmp |= (0x1C << 16); | |
8525 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8526 | ||
0ff066a9 PZ |
8527 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8528 | tmp |= (1 << 27); | |
8529 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8530 | |
0ff066a9 PZ |
8531 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8532 | tmp |= (1 << 27); | |
8533 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8534 | |
0ff066a9 PZ |
8535 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8536 | tmp &= ~(0xF << 28); | |
8537 | tmp |= (4 << 28); | |
8538 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8539 | |
0ff066a9 PZ |
8540 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8541 | tmp &= ~(0xF << 28); | |
8542 | tmp |= (4 << 28); | |
8543 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8544 | } |
8545 | ||
2fa86a1f PZ |
8546 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8547 | * Programming" based on the parameters passed: | |
8548 | * - Sequence to enable CLKOUT_DP | |
8549 | * - Sequence to enable CLKOUT_DP without spread | |
8550 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8551 | */ | |
8552 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8553 | bool with_fdi) | |
f31f2d55 PZ |
8554 | { |
8555 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
8556 | uint32_t reg, tmp; |
8557 | ||
8558 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8559 | with_spread = true; | |
c2699524 | 8560 | if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) |
2fa86a1f | 8561 | with_fdi = false; |
f31f2d55 | 8562 | |
a580516d | 8563 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
8564 | |
8565 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8566 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8567 | tmp |= SBI_SSCCTL_PATHALT; | |
8568 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8569 | ||
8570 | udelay(24); | |
8571 | ||
2fa86a1f PZ |
8572 | if (with_spread) { |
8573 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8574 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8575 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8576 | |
2fa86a1f PZ |
8577 | if (with_fdi) { |
8578 | lpt_reset_fdi_mphy(dev_priv); | |
8579 | lpt_program_fdi_mphy(dev_priv); | |
8580 | } | |
8581 | } | |
dde86e2d | 8582 | |
c2699524 | 8583 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
8584 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8585 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8586 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 8587 | |
a580516d | 8588 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
8589 | } |
8590 | ||
47701c3b PZ |
8591 | /* Sequence to disable CLKOUT_DP */ |
8592 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8593 | { | |
8594 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8595 | uint32_t reg, tmp; | |
8596 | ||
a580516d | 8597 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 8598 | |
c2699524 | 8599 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
8600 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8601 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8602 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8603 | ||
8604 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8605 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8606 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8607 | tmp |= SBI_SSCCTL_PATHALT; | |
8608 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8609 | udelay(32); | |
8610 | } | |
8611 | tmp |= SBI_SSCCTL_DISABLE; | |
8612 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8613 | } | |
8614 | ||
a580516d | 8615 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8616 | } |
8617 | ||
f7be2c21 VS |
8618 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
8619 | ||
8620 | static const uint16_t sscdivintphase[] = { | |
8621 | [BEND_IDX( 50)] = 0x3B23, | |
8622 | [BEND_IDX( 45)] = 0x3B23, | |
8623 | [BEND_IDX( 40)] = 0x3C23, | |
8624 | [BEND_IDX( 35)] = 0x3C23, | |
8625 | [BEND_IDX( 30)] = 0x3D23, | |
8626 | [BEND_IDX( 25)] = 0x3D23, | |
8627 | [BEND_IDX( 20)] = 0x3E23, | |
8628 | [BEND_IDX( 15)] = 0x3E23, | |
8629 | [BEND_IDX( 10)] = 0x3F23, | |
8630 | [BEND_IDX( 5)] = 0x3F23, | |
8631 | [BEND_IDX( 0)] = 0x0025, | |
8632 | [BEND_IDX( -5)] = 0x0025, | |
8633 | [BEND_IDX(-10)] = 0x0125, | |
8634 | [BEND_IDX(-15)] = 0x0125, | |
8635 | [BEND_IDX(-20)] = 0x0225, | |
8636 | [BEND_IDX(-25)] = 0x0225, | |
8637 | [BEND_IDX(-30)] = 0x0325, | |
8638 | [BEND_IDX(-35)] = 0x0325, | |
8639 | [BEND_IDX(-40)] = 0x0425, | |
8640 | [BEND_IDX(-45)] = 0x0425, | |
8641 | [BEND_IDX(-50)] = 0x0525, | |
8642 | }; | |
8643 | ||
8644 | /* | |
8645 | * Bend CLKOUT_DP | |
8646 | * steps -50 to 50 inclusive, in steps of 5 | |
8647 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
8648 | * change in clock period = -(steps / 10) * 5.787 ps | |
8649 | */ | |
8650 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
8651 | { | |
8652 | uint32_t tmp; | |
8653 | int idx = BEND_IDX(steps); | |
8654 | ||
8655 | if (WARN_ON(steps % 5 != 0)) | |
8656 | return; | |
8657 | ||
8658 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
8659 | return; | |
8660 | ||
8661 | mutex_lock(&dev_priv->sb_lock); | |
8662 | ||
8663 | if (steps % 10 != 0) | |
8664 | tmp = 0xAAAAAAAB; | |
8665 | else | |
8666 | tmp = 0x00000000; | |
8667 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
8668 | ||
8669 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
8670 | tmp &= 0xffff0000; | |
8671 | tmp |= sscdivintphase[idx]; | |
8672 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
8673 | ||
8674 | mutex_unlock(&dev_priv->sb_lock); | |
8675 | } | |
8676 | ||
8677 | #undef BEND_IDX | |
8678 | ||
bf8fa3d3 PZ |
8679 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8680 | { | |
bf8fa3d3 PZ |
8681 | struct intel_encoder *encoder; |
8682 | bool has_vga = false; | |
8683 | ||
b2784e15 | 8684 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8685 | switch (encoder->type) { |
8686 | case INTEL_OUTPUT_ANALOG: | |
8687 | has_vga = true; | |
8688 | break; | |
6847d71b PZ |
8689 | default: |
8690 | break; | |
bf8fa3d3 PZ |
8691 | } |
8692 | } | |
8693 | ||
f7be2c21 VS |
8694 | if (has_vga) { |
8695 | lpt_bend_clkout_dp(to_i915(dev), 0); | |
47701c3b | 8696 | lpt_enable_clkout_dp(dev, true, true); |
f7be2c21 | 8697 | } else { |
47701c3b | 8698 | lpt_disable_clkout_dp(dev); |
f7be2c21 | 8699 | } |
bf8fa3d3 PZ |
8700 | } |
8701 | ||
dde86e2d PZ |
8702 | /* |
8703 | * Initialize reference clocks when the driver loads | |
8704 | */ | |
8705 | void intel_init_pch_refclk(struct drm_device *dev) | |
8706 | { | |
8707 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8708 | ironlake_init_pch_refclk(dev); | |
8709 | else if (HAS_PCH_LPT(dev)) | |
8710 | lpt_init_pch_refclk(dev); | |
8711 | } | |
8712 | ||
55bb9992 | 8713 | static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) |
d9d444cb | 8714 | { |
55bb9992 | 8715 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d9d444cb | 8716 | struct drm_i915_private *dev_priv = dev->dev_private; |
55bb9992 | 8717 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8718 | struct drm_connector *connector; |
55bb9992 | 8719 | struct drm_connector_state *connector_state; |
d9d444cb | 8720 | struct intel_encoder *encoder; |
55bb9992 | 8721 | int num_connectors = 0, i; |
d9d444cb JB |
8722 | bool is_lvds = false; |
8723 | ||
da3ced29 | 8724 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8725 | if (connector_state->crtc != crtc_state->base.crtc) |
8726 | continue; | |
8727 | ||
8728 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8729 | ||
d9d444cb JB |
8730 | switch (encoder->type) { |
8731 | case INTEL_OUTPUT_LVDS: | |
8732 | is_lvds = true; | |
8733 | break; | |
6847d71b PZ |
8734 | default: |
8735 | break; | |
d9d444cb JB |
8736 | } |
8737 | num_connectors++; | |
8738 | } | |
8739 | ||
8740 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 8741 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 8742 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 8743 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
8744 | } |
8745 | ||
8746 | return 120000; | |
8747 | } | |
8748 | ||
6ff93609 | 8749 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8750 | { |
c8203565 | 8751 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
8752 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8753 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8754 | uint32_t val; |
8755 | ||
78114071 | 8756 | val = 0; |
c8203565 | 8757 | |
6e3c9717 | 8758 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8759 | case 18: |
dfd07d72 | 8760 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8761 | break; |
8762 | case 24: | |
dfd07d72 | 8763 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8764 | break; |
8765 | case 30: | |
dfd07d72 | 8766 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8767 | break; |
8768 | case 36: | |
dfd07d72 | 8769 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8770 | break; |
8771 | default: | |
cc769b62 PZ |
8772 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8773 | BUG(); | |
c8203565 PZ |
8774 | } |
8775 | ||
6e3c9717 | 8776 | if (intel_crtc->config->dither) |
c8203565 PZ |
8777 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8778 | ||
6e3c9717 | 8779 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8780 | val |= PIPECONF_INTERLACED_ILK; |
8781 | else | |
8782 | val |= PIPECONF_PROGRESSIVE; | |
8783 | ||
6e3c9717 | 8784 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8785 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8786 | |
c8203565 PZ |
8787 | I915_WRITE(PIPECONF(pipe), val); |
8788 | POSTING_READ(PIPECONF(pipe)); | |
8789 | } | |
8790 | ||
86d3efce VS |
8791 | /* |
8792 | * Set up the pipe CSC unit. | |
8793 | * | |
8794 | * Currently only full range RGB to limited range RGB conversion | |
8795 | * is supported, but eventually this should handle various | |
8796 | * RGB<->YCbCr scenarios as well. | |
8797 | */ | |
50f3b016 | 8798 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
8799 | { |
8800 | struct drm_device *dev = crtc->dev; | |
8801 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8802 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8803 | int pipe = intel_crtc->pipe; | |
8804 | uint16_t coeff = 0x7800; /* 1.0 */ | |
8805 | ||
8806 | /* | |
8807 | * TODO: Check what kind of values actually come out of the pipe | |
8808 | * with these coeff/postoff values and adjust to get the best | |
8809 | * accuracy. Perhaps we even need to take the bpc value into | |
8810 | * consideration. | |
8811 | */ | |
8812 | ||
6e3c9717 | 8813 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8814 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
8815 | ||
8816 | /* | |
8817 | * GY/GU and RY/RU should be the other way around according | |
8818 | * to BSpec, but reality doesn't agree. Just set them up in | |
8819 | * a way that results in the correct picture. | |
8820 | */ | |
8821 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
8822 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
8823 | ||
8824 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
8825 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
8826 | ||
8827 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
8828 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
8829 | ||
8830 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
8831 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
8832 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
8833 | ||
8834 | if (INTEL_INFO(dev)->gen > 6) { | |
8835 | uint16_t postoff = 0; | |
8836 | ||
6e3c9717 | 8837 | if (intel_crtc->config->limited_color_range) |
32cf0cb0 | 8838 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
8839 | |
8840 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
8841 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
8842 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
8843 | ||
8844 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
8845 | } else { | |
8846 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
8847 | ||
6e3c9717 | 8848 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8849 | mode |= CSC_BLACK_SCREEN_OFFSET; |
8850 | ||
8851 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
8852 | } | |
8853 | } | |
8854 | ||
6ff93609 | 8855 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8856 | { |
756f85cf PZ |
8857 | struct drm_device *dev = crtc->dev; |
8858 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 8859 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 8860 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 8861 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee2b0b38 PZ |
8862 | uint32_t val; |
8863 | ||
3eff4faa | 8864 | val = 0; |
ee2b0b38 | 8865 | |
6e3c9717 | 8866 | if (IS_HASWELL(dev) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8867 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8868 | ||
6e3c9717 | 8869 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8870 | val |= PIPECONF_INTERLACED_ILK; |
8871 | else | |
8872 | val |= PIPECONF_PROGRESSIVE; | |
8873 | ||
702e7a56 PZ |
8874 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8875 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
8876 | |
8877 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
8878 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 8879 | |
3cdf122c | 8880 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
8881 | val = 0; |
8882 | ||
6e3c9717 | 8883 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8884 | case 18: |
8885 | val |= PIPEMISC_DITHER_6_BPC; | |
8886 | break; | |
8887 | case 24: | |
8888 | val |= PIPEMISC_DITHER_8_BPC; | |
8889 | break; | |
8890 | case 30: | |
8891 | val |= PIPEMISC_DITHER_10_BPC; | |
8892 | break; | |
8893 | case 36: | |
8894 | val |= PIPEMISC_DITHER_12_BPC; | |
8895 | break; | |
8896 | default: | |
8897 | /* Case prevented by pipe_config_set_bpp. */ | |
8898 | BUG(); | |
8899 | } | |
8900 | ||
6e3c9717 | 8901 | if (intel_crtc->config->dither) |
756f85cf PZ |
8902 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8903 | ||
8904 | I915_WRITE(PIPEMISC(pipe), val); | |
8905 | } | |
ee2b0b38 PZ |
8906 | } |
8907 | ||
6591c6e4 | 8908 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
190f68c5 | 8909 | struct intel_crtc_state *crtc_state, |
6591c6e4 PZ |
8910 | intel_clock_t *clock, |
8911 | bool *has_reduced_clock, | |
8912 | intel_clock_t *reduced_clock) | |
8913 | { | |
8914 | struct drm_device *dev = crtc->dev; | |
8915 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6591c6e4 | 8916 | int refclk; |
d4906093 | 8917 | const intel_limit_t *limit; |
c329a4ec | 8918 | bool ret; |
79e53945 | 8919 | |
55bb9992 | 8920 | refclk = ironlake_get_refclk(crtc_state); |
79e53945 | 8921 | |
d4906093 ML |
8922 | /* |
8923 | * Returns a set of divisors for the desired target clock with the given | |
8924 | * refclk, or FALSE. The returned values represent the clock equation: | |
8925 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
8926 | */ | |
a93e255f ACO |
8927 | limit = intel_limit(crtc_state, refclk); |
8928 | ret = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 8929 | crtc_state->port_clock, |
ee9300bb | 8930 | refclk, NULL, clock); |
6591c6e4 PZ |
8931 | if (!ret) |
8932 | return false; | |
cda4b7d3 | 8933 | |
6591c6e4 PZ |
8934 | return true; |
8935 | } | |
8936 | ||
d4b1931c PZ |
8937 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8938 | { | |
8939 | /* | |
8940 | * Account for spread spectrum to avoid | |
8941 | * oversubscribing the link. Max center spread | |
8942 | * is 2.5%; use 5% for safety's sake. | |
8943 | */ | |
8944 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8945 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8946 | } |
8947 | ||
7429e9d4 | 8948 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8949 | { |
7429e9d4 | 8950 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8951 | } |
8952 | ||
de13a2e3 | 8953 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
190f68c5 | 8954 | struct intel_crtc_state *crtc_state, |
7429e9d4 | 8955 | u32 *fp, |
9a7c7890 | 8956 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 8957 | { |
de13a2e3 | 8958 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
8959 | struct drm_device *dev = crtc->dev; |
8960 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 | 8961 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8962 | struct drm_connector *connector; |
55bb9992 ACO |
8963 | struct drm_connector_state *connector_state; |
8964 | struct intel_encoder *encoder; | |
de13a2e3 | 8965 | uint32_t dpll; |
55bb9992 | 8966 | int factor, num_connectors = 0, i; |
09ede541 | 8967 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 8968 | |
da3ced29 | 8969 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8970 | if (connector_state->crtc != crtc_state->base.crtc) |
8971 | continue; | |
8972 | ||
8973 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8974 | ||
8975 | switch (encoder->type) { | |
79e53945 JB |
8976 | case INTEL_OUTPUT_LVDS: |
8977 | is_lvds = true; | |
8978 | break; | |
8979 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 8980 | case INTEL_OUTPUT_HDMI: |
79e53945 | 8981 | is_sdvo = true; |
79e53945 | 8982 | break; |
6847d71b PZ |
8983 | default: |
8984 | break; | |
79e53945 | 8985 | } |
43565a06 | 8986 | |
c751ce4f | 8987 | num_connectors++; |
79e53945 | 8988 | } |
79e53945 | 8989 | |
c1858123 | 8990 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
8991 | factor = 21; |
8992 | if (is_lvds) { | |
8993 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 8994 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 8995 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8996 | factor = 25; |
190f68c5 | 8997 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8998 | factor = 20; |
c1858123 | 8999 | |
190f68c5 | 9000 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
7d0ac5b7 | 9001 | *fp |= FP_CB_TUNE; |
2c07245f | 9002 | |
9a7c7890 DV |
9003 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
9004 | *fp2 |= FP_CB_TUNE; | |
9005 | ||
5eddb70b | 9006 | dpll = 0; |
2c07245f | 9007 | |
a07d6787 EA |
9008 | if (is_lvds) |
9009 | dpll |= DPLLB_MODE_LVDS; | |
9010 | else | |
9011 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 9012 | |
190f68c5 | 9013 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 9014 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
9015 | |
9016 | if (is_sdvo) | |
4a33e48d | 9017 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 9018 | if (crtc_state->has_dp_encoder) |
4a33e48d | 9019 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 9020 | |
a07d6787 | 9021 | /* compute bitmask from p1 value */ |
190f68c5 | 9022 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 9023 | /* also FPA1 */ |
190f68c5 | 9024 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 9025 | |
190f68c5 | 9026 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
9027 | case 5: |
9028 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
9029 | break; | |
9030 | case 7: | |
9031 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
9032 | break; | |
9033 | case 10: | |
9034 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
9035 | break; | |
9036 | case 14: | |
9037 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
9038 | break; | |
79e53945 JB |
9039 | } |
9040 | ||
b4c09f3b | 9041 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 9042 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
9043 | else |
9044 | dpll |= PLL_REF_INPUT_DREFCLK; | |
9045 | ||
959e16d6 | 9046 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
9047 | } |
9048 | ||
190f68c5 ACO |
9049 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
9050 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 9051 | { |
c7653199 | 9052 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 9053 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 9054 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 9055 | bool ok, has_reduced_clock = false; |
8b47047b | 9056 | bool is_lvds = false; |
e2b78267 | 9057 | struct intel_shared_dpll *pll; |
de13a2e3 | 9058 | |
dd3cd74a ACO |
9059 | memset(&crtc_state->dpll_hw_state, 0, |
9060 | sizeof(crtc_state->dpll_hw_state)); | |
9061 | ||
7905df29 | 9062 | is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS); |
79e53945 | 9063 | |
5dc5298b PZ |
9064 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
9065 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 9066 | |
190f68c5 | 9067 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
de13a2e3 | 9068 | &has_reduced_clock, &reduced_clock); |
190f68c5 | 9069 | if (!ok && !crtc_state->clock_set) { |
de13a2e3 PZ |
9070 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
9071 | return -EINVAL; | |
79e53945 | 9072 | } |
f47709a9 | 9073 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
9074 | if (!crtc_state->clock_set) { |
9075 | crtc_state->dpll.n = clock.n; | |
9076 | crtc_state->dpll.m1 = clock.m1; | |
9077 | crtc_state->dpll.m2 = clock.m2; | |
9078 | crtc_state->dpll.p1 = clock.p1; | |
9079 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 9080 | } |
79e53945 | 9081 | |
5dc5298b | 9082 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
190f68c5 ACO |
9083 | if (crtc_state->has_pch_encoder) { |
9084 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
cbbab5bd | 9085 | if (has_reduced_clock) |
7429e9d4 | 9086 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 9087 | |
190f68c5 | 9088 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
cbbab5bd DV |
9089 | &fp, &reduced_clock, |
9090 | has_reduced_clock ? &fp2 : NULL); | |
9091 | ||
190f68c5 ACO |
9092 | crtc_state->dpll_hw_state.dpll = dpll; |
9093 | crtc_state->dpll_hw_state.fp0 = fp; | |
66e985c0 | 9094 | if (has_reduced_clock) |
190f68c5 | 9095 | crtc_state->dpll_hw_state.fp1 = fp2; |
66e985c0 | 9096 | else |
190f68c5 | 9097 | crtc_state->dpll_hw_state.fp1 = fp; |
66e985c0 | 9098 | |
190f68c5 | 9099 | pll = intel_get_shared_dpll(crtc, crtc_state); |
ee7b9f93 | 9100 | if (pll == NULL) { |
84f44ce7 | 9101 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 9102 | pipe_name(crtc->pipe)); |
4b645f14 JB |
9103 | return -EINVAL; |
9104 | } | |
3fb37703 | 9105 | } |
79e53945 | 9106 | |
ab585dea | 9107 | if (is_lvds && has_reduced_clock) |
c7653199 | 9108 | crtc->lowfreq_avail = true; |
bcd644e0 | 9109 | else |
c7653199 | 9110 | crtc->lowfreq_avail = false; |
e2b78267 | 9111 | |
c8f7a0db | 9112 | return 0; |
79e53945 JB |
9113 | } |
9114 | ||
eb14cb74 VS |
9115 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
9116 | struct intel_link_m_n *m_n) | |
9117 | { | |
9118 | struct drm_device *dev = crtc->base.dev; | |
9119 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9120 | enum pipe pipe = crtc->pipe; | |
9121 | ||
9122 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
9123 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
9124 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9125 | & ~TU_SIZE_MASK; | |
9126 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
9127 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9128 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9129 | } | |
9130 | ||
9131 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
9132 | enum transcoder transcoder, | |
b95af8be VK |
9133 | struct intel_link_m_n *m_n, |
9134 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
9135 | { |
9136 | struct drm_device *dev = crtc->base.dev; | |
9137 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 9138 | enum pipe pipe = crtc->pipe; |
72419203 | 9139 | |
eb14cb74 VS |
9140 | if (INTEL_INFO(dev)->gen >= 5) { |
9141 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
9142 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
9143 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
9144 | & ~TU_SIZE_MASK; | |
9145 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
9146 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
9147 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
9148 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
9149 | * gen < 8) and if DRRS is supported (to make sure the | |
9150 | * registers are not unnecessarily read). | |
9151 | */ | |
9152 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 9153 | crtc->config->has_drrs) { |
b95af8be VK |
9154 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
9155 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
9156 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
9157 | & ~TU_SIZE_MASK; | |
9158 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
9159 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
9160 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9161 | } | |
eb14cb74 VS |
9162 | } else { |
9163 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
9164 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
9165 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9166 | & ~TU_SIZE_MASK; | |
9167 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
9168 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9169 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9170 | } | |
9171 | } | |
9172 | ||
9173 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 9174 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 9175 | { |
681a8504 | 9176 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
9177 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
9178 | else | |
9179 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
9180 | &pipe_config->dp_m_n, |
9181 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 9182 | } |
72419203 | 9183 | |
eb14cb74 | 9184 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 9185 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
9186 | { |
9187 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 9188 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
9189 | } |
9190 | ||
bd2e244f | 9191 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9192 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
9193 | { |
9194 | struct drm_device *dev = crtc->base.dev; | |
9195 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a1b2278e CK |
9196 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
9197 | uint32_t ps_ctrl = 0; | |
9198 | int id = -1; | |
9199 | int i; | |
bd2e244f | 9200 | |
a1b2278e CK |
9201 | /* find scaler attached to this pipe */ |
9202 | for (i = 0; i < crtc->num_scalers; i++) { | |
9203 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9204 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9205 | id = i; | |
9206 | pipe_config->pch_pfit.enabled = true; | |
9207 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9208 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9209 | break; | |
9210 | } | |
9211 | } | |
bd2e244f | 9212 | |
a1b2278e CK |
9213 | scaler_state->scaler_id = id; |
9214 | if (id >= 0) { | |
9215 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9216 | } else { | |
9217 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9218 | } |
9219 | } | |
9220 | ||
5724dbd1 DL |
9221 | static void |
9222 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9223 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9224 | { |
9225 | struct drm_device *dev = crtc->base.dev; | |
9226 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 9227 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9228 | int pipe = crtc->pipe; |
9229 | int fourcc, pixel_format; | |
6761dd31 | 9230 | unsigned int aligned_height; |
bc8d7dff | 9231 | struct drm_framebuffer *fb; |
1b842c89 | 9232 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9233 | |
d9806c9f | 9234 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9235 | if (!intel_fb) { |
bc8d7dff DL |
9236 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9237 | return; | |
9238 | } | |
9239 | ||
1b842c89 DL |
9240 | fb = &intel_fb->base; |
9241 | ||
bc8d7dff | 9242 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9243 | if (!(val & PLANE_CTL_ENABLE)) |
9244 | goto error; | |
9245 | ||
bc8d7dff DL |
9246 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9247 | fourcc = skl_format_to_fourcc(pixel_format, | |
9248 | val & PLANE_CTL_ORDER_RGBX, | |
9249 | val & PLANE_CTL_ALPHA_MASK); | |
9250 | fb->pixel_format = fourcc; | |
9251 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9252 | ||
40f46283 DL |
9253 | tiling = val & PLANE_CTL_TILED_MASK; |
9254 | switch (tiling) { | |
9255 | case PLANE_CTL_TILED_LINEAR: | |
9256 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9257 | break; | |
9258 | case PLANE_CTL_TILED_X: | |
9259 | plane_config->tiling = I915_TILING_X; | |
9260 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9261 | break; | |
9262 | case PLANE_CTL_TILED_Y: | |
9263 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9264 | break; | |
9265 | case PLANE_CTL_TILED_YF: | |
9266 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9267 | break; | |
9268 | default: | |
9269 | MISSING_CASE(tiling); | |
9270 | goto error; | |
9271 | } | |
9272 | ||
bc8d7dff DL |
9273 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9274 | plane_config->base = base; | |
9275 | ||
9276 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9277 | ||
9278 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9279 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9280 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9281 | ||
9282 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
40f46283 DL |
9283 | stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0], |
9284 | fb->pixel_format); | |
bc8d7dff DL |
9285 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9286 | ||
9287 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9288 | fb->pixel_format, |
9289 | fb->modifier[0]); | |
bc8d7dff | 9290 | |
f37b5c2b | 9291 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9292 | |
9293 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9294 | pipe_name(pipe), fb->width, fb->height, | |
9295 | fb->bits_per_pixel, base, fb->pitches[0], | |
9296 | plane_config->size); | |
9297 | ||
2d14030b | 9298 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9299 | return; |
9300 | ||
9301 | error: | |
9302 | kfree(fb); | |
9303 | } | |
9304 | ||
2fa2fe9a | 9305 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9306 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9307 | { |
9308 | struct drm_device *dev = crtc->base.dev; | |
9309 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9310 | uint32_t tmp; | |
9311 | ||
9312 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9313 | ||
9314 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9315 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9316 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9317 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9318 | |
9319 | /* We currently do not free assignements of panel fitters on | |
9320 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9321 | * differentiates them) so just WARN about this case for now. */ | |
9322 | if (IS_GEN7(dev)) { | |
9323 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
9324 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9325 | } | |
2fa2fe9a | 9326 | } |
79e53945 JB |
9327 | } |
9328 | ||
5724dbd1 DL |
9329 | static void |
9330 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9331 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9332 | { |
9333 | struct drm_device *dev = crtc->base.dev; | |
9334 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9335 | u32 val, base, offset; | |
aeee5a49 | 9336 | int pipe = crtc->pipe; |
4c6baa59 | 9337 | int fourcc, pixel_format; |
6761dd31 | 9338 | unsigned int aligned_height; |
b113d5ee | 9339 | struct drm_framebuffer *fb; |
1b842c89 | 9340 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9341 | |
42a7b088 DL |
9342 | val = I915_READ(DSPCNTR(pipe)); |
9343 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9344 | return; | |
9345 | ||
d9806c9f | 9346 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9347 | if (!intel_fb) { |
4c6baa59 JB |
9348 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9349 | return; | |
9350 | } | |
9351 | ||
1b842c89 DL |
9352 | fb = &intel_fb->base; |
9353 | ||
18c5247e DV |
9354 | if (INTEL_INFO(dev)->gen >= 4) { |
9355 | if (val & DISPPLANE_TILED) { | |
49af449b | 9356 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9357 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9358 | } | |
9359 | } | |
4c6baa59 JB |
9360 | |
9361 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9362 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9363 | fb->pixel_format = fourcc; |
9364 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9365 | |
aeee5a49 | 9366 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 9367 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 9368 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9369 | } else { |
49af449b | 9370 | if (plane_config->tiling) |
aeee5a49 | 9371 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9372 | else |
aeee5a49 | 9373 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9374 | } |
9375 | plane_config->base = base; | |
9376 | ||
9377 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9378 | fb->width = ((val >> 16) & 0xfff) + 1; |
9379 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9380 | |
9381 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9382 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9383 | |
b113d5ee | 9384 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9385 | fb->pixel_format, |
9386 | fb->modifier[0]); | |
4c6baa59 | 9387 | |
f37b5c2b | 9388 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9389 | |
2844a921 DL |
9390 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9391 | pipe_name(pipe), fb->width, fb->height, | |
9392 | fb->bits_per_pixel, base, fb->pitches[0], | |
9393 | plane_config->size); | |
b113d5ee | 9394 | |
2d14030b | 9395 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9396 | } |
9397 | ||
0e8ffe1b | 9398 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9399 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9400 | { |
9401 | struct drm_device *dev = crtc->base.dev; | |
9402 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9403 | uint32_t tmp; | |
9404 | ||
f458ebbc DV |
9405 | if (!intel_display_power_is_enabled(dev_priv, |
9406 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
930e8c9e PZ |
9407 | return false; |
9408 | ||
e143a21c | 9409 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 9410 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 9411 | |
0e8ffe1b DV |
9412 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9413 | if (!(tmp & PIPECONF_ENABLE)) | |
9414 | return false; | |
9415 | ||
42571aef VS |
9416 | switch (tmp & PIPECONF_BPC_MASK) { |
9417 | case PIPECONF_6BPC: | |
9418 | pipe_config->pipe_bpp = 18; | |
9419 | break; | |
9420 | case PIPECONF_8BPC: | |
9421 | pipe_config->pipe_bpp = 24; | |
9422 | break; | |
9423 | case PIPECONF_10BPC: | |
9424 | pipe_config->pipe_bpp = 30; | |
9425 | break; | |
9426 | case PIPECONF_12BPC: | |
9427 | pipe_config->pipe_bpp = 36; | |
9428 | break; | |
9429 | default: | |
9430 | break; | |
9431 | } | |
9432 | ||
b5a9fa09 DV |
9433 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9434 | pipe_config->limited_color_range = true; | |
9435 | ||
ab9412ba | 9436 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
9437 | struct intel_shared_dpll *pll; |
9438 | ||
88adfff1 DV |
9439 | pipe_config->has_pch_encoder = true; |
9440 | ||
627eb5a3 DV |
9441 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9442 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9443 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9444 | |
9445 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9446 | |
c0d43d62 | 9447 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
9448 | pipe_config->shared_dpll = |
9449 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
9450 | } else { |
9451 | tmp = I915_READ(PCH_DPLL_SEL); | |
9452 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
9453 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
9454 | else | |
9455 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
9456 | } | |
66e985c0 DV |
9457 | |
9458 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9459 | ||
9460 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9461 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9462 | |
9463 | tmp = pipe_config->dpll_hw_state.dpll; | |
9464 | pipe_config->pixel_multiplier = | |
9465 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9466 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9467 | |
9468 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9469 | } else { |
9470 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9471 | } |
9472 | ||
1bd1bd80 DV |
9473 | intel_get_pipe_timings(crtc, pipe_config); |
9474 | ||
2fa2fe9a DV |
9475 | ironlake_get_pfit_config(crtc, pipe_config); |
9476 | ||
0e8ffe1b DV |
9477 | return true; |
9478 | } | |
9479 | ||
be256dc7 PZ |
9480 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9481 | { | |
9482 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 9483 | struct intel_crtc *crtc; |
be256dc7 | 9484 | |
d3fcc808 | 9485 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9486 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9487 | pipe_name(crtc->pipe)); |
9488 | ||
e2c719b7 RC |
9489 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9490 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
9491 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
9492 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
e2c719b7 RC |
9493 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
9494 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 9495 | "CPU PWM1 enabled\n"); |
c5107b87 | 9496 | if (IS_HASWELL(dev)) |
e2c719b7 | 9497 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 9498 | "CPU PWM2 enabled\n"); |
e2c719b7 | 9499 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 9500 | "PCH PWM1 enabled\n"); |
e2c719b7 | 9501 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 9502 | "Utility pin enabled\n"); |
e2c719b7 | 9503 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 9504 | |
9926ada1 PZ |
9505 | /* |
9506 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9507 | * interrupts remain enabled. We used to check for that, but since it's | |
9508 | * gen-specific and since we only disable LCPLL after we fully disable | |
9509 | * the interrupts, the check below should be enough. | |
9510 | */ | |
e2c719b7 | 9511 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
9512 | } |
9513 | ||
9ccd5aeb PZ |
9514 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
9515 | { | |
9516 | struct drm_device *dev = dev_priv->dev; | |
9517 | ||
9518 | if (IS_HASWELL(dev)) | |
9519 | return I915_READ(D_COMP_HSW); | |
9520 | else | |
9521 | return I915_READ(D_COMP_BDW); | |
9522 | } | |
9523 | ||
3c4c9b81 PZ |
9524 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
9525 | { | |
9526 | struct drm_device *dev = dev_priv->dev; | |
9527 | ||
9528 | if (IS_HASWELL(dev)) { | |
9529 | mutex_lock(&dev_priv->rps.hw_lock); | |
9530 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9531 | val)) | |
f475dadf | 9532 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
9533 | mutex_unlock(&dev_priv->rps.hw_lock); |
9534 | } else { | |
9ccd5aeb PZ |
9535 | I915_WRITE(D_COMP_BDW, val); |
9536 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 9537 | } |
be256dc7 PZ |
9538 | } |
9539 | ||
9540 | /* | |
9541 | * This function implements pieces of two sequences from BSpec: | |
9542 | * - Sequence for display software to disable LCPLL | |
9543 | * - Sequence for display software to allow package C8+ | |
9544 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9545 | * register. Callers should take care of disabling all the display engine | |
9546 | * functions, doing the mode unset, fixing interrupts, etc. | |
9547 | */ | |
6ff58d53 PZ |
9548 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9549 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9550 | { |
9551 | uint32_t val; | |
9552 | ||
9553 | assert_can_disable_lcpll(dev_priv); | |
9554 | ||
9555 | val = I915_READ(LCPLL_CTL); | |
9556 | ||
9557 | if (switch_to_fclk) { | |
9558 | val |= LCPLL_CD_SOURCE_FCLK; | |
9559 | I915_WRITE(LCPLL_CTL, val); | |
9560 | ||
9561 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9562 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9563 | DRM_ERROR("Switching to FCLK failed\n"); | |
9564 | ||
9565 | val = I915_READ(LCPLL_CTL); | |
9566 | } | |
9567 | ||
9568 | val |= LCPLL_PLL_DISABLE; | |
9569 | I915_WRITE(LCPLL_CTL, val); | |
9570 | POSTING_READ(LCPLL_CTL); | |
9571 | ||
9572 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
9573 | DRM_ERROR("LCPLL still locked\n"); | |
9574 | ||
9ccd5aeb | 9575 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9576 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9577 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9578 | ndelay(100); |
9579 | ||
9ccd5aeb PZ |
9580 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9581 | 1)) | |
be256dc7 PZ |
9582 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9583 | ||
9584 | if (allow_power_down) { | |
9585 | val = I915_READ(LCPLL_CTL); | |
9586 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9587 | I915_WRITE(LCPLL_CTL, val); | |
9588 | POSTING_READ(LCPLL_CTL); | |
9589 | } | |
9590 | } | |
9591 | ||
9592 | /* | |
9593 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9594 | * source. | |
9595 | */ | |
6ff58d53 | 9596 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9597 | { |
9598 | uint32_t val; | |
9599 | ||
9600 | val = I915_READ(LCPLL_CTL); | |
9601 | ||
9602 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9603 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9604 | return; | |
9605 | ||
a8a8bd54 PZ |
9606 | /* |
9607 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9608 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9609 | */ |
59bad947 | 9610 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9611 | |
be256dc7 PZ |
9612 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9613 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9614 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9615 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9616 | } |
9617 | ||
9ccd5aeb | 9618 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9619 | val |= D_COMP_COMP_FORCE; |
9620 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9621 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9622 | |
9623 | val = I915_READ(LCPLL_CTL); | |
9624 | val &= ~LCPLL_PLL_DISABLE; | |
9625 | I915_WRITE(LCPLL_CTL, val); | |
9626 | ||
9627 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
9628 | DRM_ERROR("LCPLL not locked yet\n"); | |
9629 | ||
9630 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9631 | val = I915_READ(LCPLL_CTL); | |
9632 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9633 | I915_WRITE(LCPLL_CTL, val); | |
9634 | ||
9635 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9636 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9637 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9638 | } | |
215733fa | 9639 | |
59bad947 | 9640 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b6283055 | 9641 | intel_update_cdclk(dev_priv->dev); |
be256dc7 PZ |
9642 | } |
9643 | ||
765dab67 PZ |
9644 | /* |
9645 | * Package states C8 and deeper are really deep PC states that can only be | |
9646 | * reached when all the devices on the system allow it, so even if the graphics | |
9647 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9648 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9649 | * | |
9650 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9651 | * well is disabled and most interrupts are disabled, and these are also | |
9652 | * requirements for runtime PM. When these conditions are met, we manually do | |
9653 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9654 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9655 | * hang the machine. | |
9656 | * | |
9657 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9658 | * the state of some registers, so when we come back from PC8+ we need to | |
9659 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9660 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9661 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9662 | * because of the runtime PM support). | |
9663 | * | |
9664 | * For more, read "Display Sequences for Package C8" on the hardware | |
9665 | * documentation. | |
9666 | */ | |
a14cb6fc | 9667 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9668 | { |
c67a470b PZ |
9669 | struct drm_device *dev = dev_priv->dev; |
9670 | uint32_t val; | |
9671 | ||
c67a470b PZ |
9672 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9673 | ||
c2699524 | 9674 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9675 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9676 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9677 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9678 | } | |
9679 | ||
9680 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9681 | hsw_disable_lcpll(dev_priv, true, true); |
9682 | } | |
9683 | ||
a14cb6fc | 9684 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
9685 | { |
9686 | struct drm_device *dev = dev_priv->dev; | |
9687 | uint32_t val; | |
9688 | ||
c67a470b PZ |
9689 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9690 | ||
9691 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9692 | lpt_init_pch_refclk(dev); |
9693 | ||
c2699524 | 9694 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9695 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9696 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9697 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9698 | } | |
9699 | ||
9700 | intel_prepare_ddi(dev); | |
c67a470b PZ |
9701 | } |
9702 | ||
27c329ed | 9703 | static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 9704 | { |
a821fc46 | 9705 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9706 | struct intel_atomic_state *old_intel_state = |
9707 | to_intel_atomic_state(old_state); | |
9708 | unsigned int req_cdclk = old_intel_state->dev_cdclk; | |
f8437dd1 | 9709 | |
27c329ed | 9710 | broxton_set_cdclk(dev, req_cdclk); |
f8437dd1 VK |
9711 | } |
9712 | ||
b432e5cf | 9713 | /* compute the max rate for new configuration */ |
27c329ed | 9714 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 9715 | { |
565602d7 ML |
9716 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
9717 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
9718 | struct drm_crtc *crtc; | |
9719 | struct drm_crtc_state *cstate; | |
27c329ed | 9720 | struct intel_crtc_state *crtc_state; |
565602d7 ML |
9721 | unsigned max_pixel_rate = 0, i; |
9722 | enum pipe pipe; | |
b432e5cf | 9723 | |
565602d7 ML |
9724 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
9725 | sizeof(intel_state->min_pixclk)); | |
27c329ed | 9726 | |
565602d7 ML |
9727 | for_each_crtc_in_state(state, crtc, cstate, i) { |
9728 | int pixel_rate; | |
27c329ed | 9729 | |
565602d7 ML |
9730 | crtc_state = to_intel_crtc_state(cstate); |
9731 | if (!crtc_state->base.enable) { | |
9732 | intel_state->min_pixclk[i] = 0; | |
b432e5cf | 9733 | continue; |
565602d7 | 9734 | } |
b432e5cf | 9735 | |
27c329ed | 9736 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf VS |
9737 | |
9738 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
565602d7 | 9739 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
b432e5cf VS |
9740 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
9741 | ||
565602d7 | 9742 | intel_state->min_pixclk[i] = pixel_rate; |
b432e5cf VS |
9743 | } |
9744 | ||
565602d7 ML |
9745 | if (!intel_state->active_crtcs) |
9746 | return 0; | |
9747 | ||
9748 | for_each_pipe(dev_priv, pipe) | |
9749 | max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate); | |
9750 | ||
b432e5cf VS |
9751 | return max_pixel_rate; |
9752 | } | |
9753 | ||
9754 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
9755 | { | |
9756 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9757 | uint32_t val, data; | |
9758 | int ret; | |
9759 | ||
9760 | if (WARN((I915_READ(LCPLL_CTL) & | |
9761 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
9762 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
9763 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
9764 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
9765 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
9766 | return; | |
9767 | ||
9768 | mutex_lock(&dev_priv->rps.hw_lock); | |
9769 | ret = sandybridge_pcode_write(dev_priv, | |
9770 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
9771 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9772 | if (ret) { | |
9773 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
9774 | return; | |
9775 | } | |
9776 | ||
9777 | val = I915_READ(LCPLL_CTL); | |
9778 | val |= LCPLL_CD_SOURCE_FCLK; | |
9779 | I915_WRITE(LCPLL_CTL, val); | |
9780 | ||
9781 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9782 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9783 | DRM_ERROR("Switching to FCLK failed\n"); | |
9784 | ||
9785 | val = I915_READ(LCPLL_CTL); | |
9786 | val &= ~LCPLL_CLK_FREQ_MASK; | |
9787 | ||
9788 | switch (cdclk) { | |
9789 | case 450000: | |
9790 | val |= LCPLL_CLK_FREQ_450; | |
9791 | data = 0; | |
9792 | break; | |
9793 | case 540000: | |
9794 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
9795 | data = 1; | |
9796 | break; | |
9797 | case 337500: | |
9798 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
9799 | data = 2; | |
9800 | break; | |
9801 | case 675000: | |
9802 | val |= LCPLL_CLK_FREQ_675_BDW; | |
9803 | data = 3; | |
9804 | break; | |
9805 | default: | |
9806 | WARN(1, "invalid cdclk frequency\n"); | |
9807 | return; | |
9808 | } | |
9809 | ||
9810 | I915_WRITE(LCPLL_CTL, val); | |
9811 | ||
9812 | val = I915_READ(LCPLL_CTL); | |
9813 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9814 | I915_WRITE(LCPLL_CTL, val); | |
9815 | ||
9816 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9817 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9818 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9819 | ||
9820 | mutex_lock(&dev_priv->rps.hw_lock); | |
9821 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
9822 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9823 | ||
9824 | intel_update_cdclk(dev); | |
9825 | ||
9826 | WARN(cdclk != dev_priv->cdclk_freq, | |
9827 | "cdclk requested %d kHz but got %d kHz\n", | |
9828 | cdclk, dev_priv->cdclk_freq); | |
9829 | } | |
9830 | ||
27c329ed | 9831 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 9832 | { |
27c329ed | 9833 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
1a617b77 | 9834 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
27c329ed | 9835 | int max_pixclk = ilk_max_pixel_rate(state); |
b432e5cf VS |
9836 | int cdclk; |
9837 | ||
9838 | /* | |
9839 | * FIXME should also account for plane ratio | |
9840 | * once 64bpp pixel formats are supported. | |
9841 | */ | |
27c329ed | 9842 | if (max_pixclk > 540000) |
b432e5cf | 9843 | cdclk = 675000; |
27c329ed | 9844 | else if (max_pixclk > 450000) |
b432e5cf | 9845 | cdclk = 540000; |
27c329ed | 9846 | else if (max_pixclk > 337500) |
b432e5cf VS |
9847 | cdclk = 450000; |
9848 | else | |
9849 | cdclk = 337500; | |
9850 | ||
b432e5cf | 9851 | if (cdclk > dev_priv->max_cdclk_freq) { |
63ba534e ML |
9852 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
9853 | cdclk, dev_priv->max_cdclk_freq); | |
9854 | return -EINVAL; | |
b432e5cf VS |
9855 | } |
9856 | ||
1a617b77 ML |
9857 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
9858 | if (!intel_state->active_crtcs) | |
9859 | intel_state->dev_cdclk = 337500; | |
b432e5cf VS |
9860 | |
9861 | return 0; | |
9862 | } | |
9863 | ||
27c329ed | 9864 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 9865 | { |
27c329ed | 9866 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9867 | struct intel_atomic_state *old_intel_state = |
9868 | to_intel_atomic_state(old_state); | |
9869 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
b432e5cf | 9870 | |
27c329ed | 9871 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
9872 | } |
9873 | ||
190f68c5 ACO |
9874 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9875 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9876 | { |
190f68c5 | 9877 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
6441ab5f | 9878 | return -EINVAL; |
716c2e55 | 9879 | |
c7653199 | 9880 | crtc->lowfreq_avail = false; |
644cef34 | 9881 | |
c8f7a0db | 9882 | return 0; |
79e53945 JB |
9883 | } |
9884 | ||
3760b59c S |
9885 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9886 | enum port port, | |
9887 | struct intel_crtc_state *pipe_config) | |
9888 | { | |
9889 | switch (port) { | |
9890 | case PORT_A: | |
9891 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
9892 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9893 | break; | |
9894 | case PORT_B: | |
9895 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
9896 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9897 | break; | |
9898 | case PORT_C: | |
9899 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
9900 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9901 | break; | |
9902 | default: | |
9903 | DRM_ERROR("Incorrect port type\n"); | |
9904 | } | |
9905 | } | |
9906 | ||
96b7dfb7 S |
9907 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9908 | enum port port, | |
5cec258b | 9909 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9910 | { |
3148ade7 | 9911 | u32 temp, dpll_ctl1; |
96b7dfb7 S |
9912 | |
9913 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9914 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9915 | ||
9916 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 DL |
9917 | case SKL_DPLL0: |
9918 | /* | |
9919 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part | |
9920 | * of the shared DPLL framework and thus needs to be read out | |
9921 | * separately | |
9922 | */ | |
9923 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
9924 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; | |
9925 | break; | |
96b7dfb7 S |
9926 | case SKL_DPLL1: |
9927 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9928 | break; | |
9929 | case SKL_DPLL2: | |
9930 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9931 | break; | |
9932 | case SKL_DPLL3: | |
9933 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9934 | break; | |
96b7dfb7 S |
9935 | } |
9936 | } | |
9937 | ||
7d2c8175 DL |
9938 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9939 | enum port port, | |
5cec258b | 9940 | struct intel_crtc_state *pipe_config) |
7d2c8175 DL |
9941 | { |
9942 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
9943 | ||
9944 | switch (pipe_config->ddi_pll_sel) { | |
9945 | case PORT_CLK_SEL_WRPLL1: | |
9946 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
9947 | break; | |
9948 | case PORT_CLK_SEL_WRPLL2: | |
9949 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
9950 | break; | |
00490c22 ML |
9951 | case PORT_CLK_SEL_SPLL: |
9952 | pipe_config->shared_dpll = DPLL_ID_SPLL; | |
79bd23da | 9953 | break; |
7d2c8175 DL |
9954 | } |
9955 | } | |
9956 | ||
26804afd | 9957 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9958 | struct intel_crtc_state *pipe_config) |
26804afd DV |
9959 | { |
9960 | struct drm_device *dev = crtc->base.dev; | |
9961 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 9962 | struct intel_shared_dpll *pll; |
26804afd DV |
9963 | enum port port; |
9964 | uint32_t tmp; | |
9965 | ||
9966 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9967 | ||
9968 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9969 | ||
ef11bdb3 | 9970 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
96b7dfb7 | 9971 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
3760b59c S |
9972 | else if (IS_BROXTON(dev)) |
9973 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
9974 | else |
9975 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9976 | |
d452c5b6 DV |
9977 | if (pipe_config->shared_dpll >= 0) { |
9978 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9979 | ||
9980 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9981 | &pipe_config->dpll_hw_state)); | |
9982 | } | |
9983 | ||
26804afd DV |
9984 | /* |
9985 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9986 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9987 | * the PCH transcoder is on. | |
9988 | */ | |
ca370455 DL |
9989 | if (INTEL_INFO(dev)->gen < 9 && |
9990 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
9991 | pipe_config->has_pch_encoder = true; |
9992 | ||
9993 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9994 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9995 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9996 | ||
9997 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9998 | } | |
9999 | } | |
10000 | ||
0e8ffe1b | 10001 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 10002 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
10003 | { |
10004 | struct drm_device *dev = crtc->base.dev; | |
10005 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 10006 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
10007 | uint32_t tmp; |
10008 | ||
f458ebbc | 10009 | if (!intel_display_power_is_enabled(dev_priv, |
b5482bd0 ID |
10010 | POWER_DOMAIN_PIPE(crtc->pipe))) |
10011 | return false; | |
10012 | ||
e143a21c | 10013 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
10014 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
10015 | ||
eccb140b DV |
10016 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
10017 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
10018 | enum pipe trans_edp_pipe; | |
10019 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
10020 | default: | |
10021 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
10022 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
10023 | case TRANS_DDI_EDP_INPUT_A_ON: | |
10024 | trans_edp_pipe = PIPE_A; | |
10025 | break; | |
10026 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
10027 | trans_edp_pipe = PIPE_B; | |
10028 | break; | |
10029 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
10030 | trans_edp_pipe = PIPE_C; | |
10031 | break; | |
10032 | } | |
10033 | ||
10034 | if (trans_edp_pipe == crtc->pipe) | |
10035 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
10036 | } | |
10037 | ||
f458ebbc | 10038 | if (!intel_display_power_is_enabled(dev_priv, |
eccb140b | 10039 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
10040 | return false; |
10041 | ||
eccb140b | 10042 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
10043 | if (!(tmp & PIPECONF_ENABLE)) |
10044 | return false; | |
10045 | ||
26804afd | 10046 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 10047 | |
1bd1bd80 DV |
10048 | intel_get_pipe_timings(crtc, pipe_config); |
10049 | ||
a1b2278e CK |
10050 | if (INTEL_INFO(dev)->gen >= 9) { |
10051 | skl_init_scalers(dev, crtc, pipe_config); | |
10052 | } | |
10053 | ||
2fa2fe9a | 10054 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
af99ceda CK |
10055 | |
10056 | if (INTEL_INFO(dev)->gen >= 9) { | |
10057 | pipe_config->scaler_state.scaler_id = -1; | |
10058 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
10059 | } | |
10060 | ||
bd2e244f | 10061 | if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { |
1c132b44 | 10062 | if (INTEL_INFO(dev)->gen >= 9) |
bd2e244f | 10063 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 10064 | else |
1c132b44 | 10065 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 10066 | } |
88adfff1 | 10067 | |
e59150dc JB |
10068 | if (IS_HASWELL(dev)) |
10069 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
10070 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 10071 | |
ebb69c95 CT |
10072 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
10073 | pipe_config->pixel_multiplier = | |
10074 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
10075 | } else { | |
10076 | pipe_config->pixel_multiplier = 1; | |
10077 | } | |
6c49f241 | 10078 | |
0e8ffe1b DV |
10079 | return true; |
10080 | } | |
10081 | ||
663f3122 | 10082 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, bool on) |
560b85bb CW |
10083 | { |
10084 | struct drm_device *dev = crtc->dev; | |
10085 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10086 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 10087 | uint32_t cntl = 0, size = 0; |
560b85bb | 10088 | |
663f3122 | 10089 | if (on) { |
3dd512fb MR |
10090 | unsigned int width = intel_crtc->base.cursor->state->crtc_w; |
10091 | unsigned int height = intel_crtc->base.cursor->state->crtc_h; | |
dc41c154 VS |
10092 | unsigned int stride = roundup_pow_of_two(width) * 4; |
10093 | ||
10094 | switch (stride) { | |
10095 | default: | |
10096 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
10097 | width, stride); | |
10098 | stride = 256; | |
10099 | /* fallthrough */ | |
10100 | case 256: | |
10101 | case 512: | |
10102 | case 1024: | |
10103 | case 2048: | |
10104 | break; | |
4b0e333e CW |
10105 | } |
10106 | ||
dc41c154 VS |
10107 | cntl |= CURSOR_ENABLE | |
10108 | CURSOR_GAMMA_ENABLE | | |
10109 | CURSOR_FORMAT_ARGB | | |
10110 | CURSOR_STRIDE(stride); | |
10111 | ||
10112 | size = (height << 12) | width; | |
4b0e333e | 10113 | } |
560b85bb | 10114 | |
dc41c154 VS |
10115 | if (intel_crtc->cursor_cntl != 0 && |
10116 | (intel_crtc->cursor_base != base || | |
10117 | intel_crtc->cursor_size != size || | |
10118 | intel_crtc->cursor_cntl != cntl)) { | |
10119 | /* On these chipsets we can only modify the base/size/stride | |
10120 | * whilst the cursor is disabled. | |
10121 | */ | |
0b87c24e VS |
10122 | I915_WRITE(CURCNTR(PIPE_A), 0); |
10123 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 10124 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 10125 | } |
560b85bb | 10126 | |
99d1f387 | 10127 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 10128 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
10129 | intel_crtc->cursor_base = base; |
10130 | } | |
4726e0b0 | 10131 | |
dc41c154 VS |
10132 | if (intel_crtc->cursor_size != size) { |
10133 | I915_WRITE(CURSIZE, size); | |
10134 | intel_crtc->cursor_size = size; | |
4b0e333e | 10135 | } |
560b85bb | 10136 | |
4b0e333e | 10137 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
10138 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
10139 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 10140 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 10141 | } |
560b85bb CW |
10142 | } |
10143 | ||
663f3122 | 10144 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, bool on) |
65a21cd6 JB |
10145 | { |
10146 | struct drm_device *dev = crtc->dev; | |
10147 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10148 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10149 | int pipe = intel_crtc->pipe; | |
663f3122 | 10150 | uint32_t cntl = 0; |
4b0e333e | 10151 | |
663f3122 | 10152 | if (on) { |
4b0e333e | 10153 | cntl = MCURSOR_GAMMA_ENABLE; |
3dd512fb | 10154 | switch (intel_crtc->base.cursor->state->crtc_w) { |
4726e0b0 SK |
10155 | case 64: |
10156 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
10157 | break; | |
10158 | case 128: | |
10159 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
10160 | break; | |
10161 | case 256: | |
10162 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
10163 | break; | |
10164 | default: | |
3dd512fb | 10165 | MISSING_CASE(intel_crtc->base.cursor->state->crtc_w); |
4726e0b0 | 10166 | return; |
65a21cd6 | 10167 | } |
4b0e333e | 10168 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 10169 | |
fc6f93bc | 10170 | if (HAS_DDI(dev)) |
47bf17a7 | 10171 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
4b0e333e | 10172 | } |
65a21cd6 | 10173 | |
8e7d688b | 10174 | if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) |
4398ad45 VS |
10175 | cntl |= CURSOR_ROTATE_180; |
10176 | ||
4b0e333e CW |
10177 | if (intel_crtc->cursor_cntl != cntl) { |
10178 | I915_WRITE(CURCNTR(pipe), cntl); | |
10179 | POSTING_READ(CURCNTR(pipe)); | |
10180 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 10181 | } |
4b0e333e | 10182 | |
65a21cd6 | 10183 | /* and commit changes on next vblank */ |
5efb3e28 VS |
10184 | I915_WRITE(CURBASE(pipe), base); |
10185 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
10186 | |
10187 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
10188 | } |
10189 | ||
cda4b7d3 | 10190 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
10191 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
10192 | bool on) | |
cda4b7d3 CW |
10193 | { |
10194 | struct drm_device *dev = crtc->dev; | |
10195 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10196 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10197 | int pipe = intel_crtc->pipe; | |
9b4101be ML |
10198 | struct drm_plane_state *cursor_state = crtc->cursor->state; |
10199 | int x = cursor_state->crtc_x; | |
10200 | int y = cursor_state->crtc_y; | |
d6e4db15 | 10201 | u32 base = 0, pos = 0; |
cda4b7d3 | 10202 | |
663f3122 | 10203 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 10204 | |
6e3c9717 | 10205 | if (x >= intel_crtc->config->pipe_src_w) |
663f3122 | 10206 | on = false; |
d6e4db15 | 10207 | |
6e3c9717 | 10208 | if (y >= intel_crtc->config->pipe_src_h) |
663f3122 | 10209 | on = false; |
cda4b7d3 CW |
10210 | |
10211 | if (x < 0) { | |
9b4101be | 10212 | if (x + cursor_state->crtc_w <= 0) |
663f3122 | 10213 | on = false; |
cda4b7d3 CW |
10214 | |
10215 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10216 | x = -x; | |
10217 | } | |
10218 | pos |= x << CURSOR_X_SHIFT; | |
10219 | ||
10220 | if (y < 0) { | |
9b4101be | 10221 | if (y + cursor_state->crtc_h <= 0) |
663f3122 | 10222 | on = false; |
cda4b7d3 CW |
10223 | |
10224 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10225 | y = -y; | |
10226 | } | |
10227 | pos |= y << CURSOR_Y_SHIFT; | |
10228 | ||
5efb3e28 VS |
10229 | I915_WRITE(CURPOS(pipe), pos); |
10230 | ||
4398ad45 VS |
10231 | /* ILK+ do this automagically */ |
10232 | if (HAS_GMCH_DISPLAY(dev) && | |
8e7d688b | 10233 | crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) { |
9b4101be ML |
10234 | base += (cursor_state->crtc_h * |
10235 | cursor_state->crtc_w - 1) * 4; | |
4398ad45 VS |
10236 | } |
10237 | ||
8ac54669 | 10238 | if (IS_845G(dev) || IS_I865G(dev)) |
663f3122 | 10239 | i845_update_cursor(crtc, base, on); |
5efb3e28 | 10240 | else |
663f3122 | 10241 | i9xx_update_cursor(crtc, base, on); |
cda4b7d3 CW |
10242 | } |
10243 | ||
dc41c154 VS |
10244 | static bool cursor_size_ok(struct drm_device *dev, |
10245 | uint32_t width, uint32_t height) | |
10246 | { | |
10247 | if (width == 0 || height == 0) | |
10248 | return false; | |
10249 | ||
10250 | /* | |
10251 | * 845g/865g are special in that they are only limited by | |
10252 | * the width of their cursors, the height is arbitrary up to | |
10253 | * the precision of the register. Everything else requires | |
10254 | * square cursors, limited to a few power-of-two sizes. | |
10255 | */ | |
10256 | if (IS_845G(dev) || IS_I865G(dev)) { | |
10257 | if ((width & 63) != 0) | |
10258 | return false; | |
10259 | ||
10260 | if (width > (IS_845G(dev) ? 64 : 512)) | |
10261 | return false; | |
10262 | ||
10263 | if (height > 1023) | |
10264 | return false; | |
10265 | } else { | |
10266 | switch (width | height) { | |
10267 | case 256: | |
10268 | case 128: | |
10269 | if (IS_GEN2(dev)) | |
10270 | return false; | |
10271 | case 64: | |
10272 | break; | |
10273 | default: | |
10274 | return false; | |
10275 | } | |
10276 | } | |
10277 | ||
10278 | return true; | |
10279 | } | |
10280 | ||
79e53945 | 10281 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 10282 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 10283 | { |
7203425a | 10284 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 10285 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 10286 | |
7203425a | 10287 | for (i = start; i < end; i++) { |
79e53945 JB |
10288 | intel_crtc->lut_r[i] = red[i] >> 8; |
10289 | intel_crtc->lut_g[i] = green[i] >> 8; | |
10290 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
10291 | } | |
10292 | ||
10293 | intel_crtc_load_lut(crtc); | |
10294 | } | |
10295 | ||
79e53945 JB |
10296 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10297 | static struct drm_display_mode load_detect_mode = { | |
10298 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10299 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10300 | }; | |
10301 | ||
a8bb6818 DV |
10302 | struct drm_framebuffer * |
10303 | __intel_framebuffer_create(struct drm_device *dev, | |
10304 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10305 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10306 | { |
10307 | struct intel_framebuffer *intel_fb; | |
10308 | int ret; | |
10309 | ||
10310 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 10311 | if (!intel_fb) |
d2dff872 | 10312 | return ERR_PTR(-ENOMEM); |
d2dff872 CW |
10313 | |
10314 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10315 | if (ret) |
10316 | goto err; | |
d2dff872 CW |
10317 | |
10318 | return &intel_fb->base; | |
dcb1394e | 10319 | |
dd4916c5 | 10320 | err: |
dd4916c5 | 10321 | kfree(intel_fb); |
dd4916c5 | 10322 | return ERR_PTR(ret); |
d2dff872 CW |
10323 | } |
10324 | ||
b5ea642a | 10325 | static struct drm_framebuffer * |
a8bb6818 DV |
10326 | intel_framebuffer_create(struct drm_device *dev, |
10327 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10328 | struct drm_i915_gem_object *obj) | |
10329 | { | |
10330 | struct drm_framebuffer *fb; | |
10331 | int ret; | |
10332 | ||
10333 | ret = i915_mutex_lock_interruptible(dev); | |
10334 | if (ret) | |
10335 | return ERR_PTR(ret); | |
10336 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10337 | mutex_unlock(&dev->struct_mutex); | |
10338 | ||
10339 | return fb; | |
10340 | } | |
10341 | ||
d2dff872 CW |
10342 | static u32 |
10343 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10344 | { | |
10345 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10346 | return ALIGN(pitch, 64); | |
10347 | } | |
10348 | ||
10349 | static u32 | |
10350 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10351 | { | |
10352 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 10353 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
10354 | } |
10355 | ||
10356 | static struct drm_framebuffer * | |
10357 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10358 | struct drm_display_mode *mode, | |
10359 | int depth, int bpp) | |
10360 | { | |
dcb1394e | 10361 | struct drm_framebuffer *fb; |
d2dff872 | 10362 | struct drm_i915_gem_object *obj; |
0fed39bd | 10363 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
10364 | |
10365 | obj = i915_gem_alloc_object(dev, | |
10366 | intel_framebuffer_size_for_mode(mode, bpp)); | |
10367 | if (obj == NULL) | |
10368 | return ERR_PTR(-ENOMEM); | |
10369 | ||
10370 | mode_cmd.width = mode->hdisplay; | |
10371 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
10372 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10373 | bpp); | |
5ca0c34a | 10374 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 10375 | |
dcb1394e LW |
10376 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
10377 | if (IS_ERR(fb)) | |
10378 | drm_gem_object_unreference_unlocked(&obj->base); | |
10379 | ||
10380 | return fb; | |
d2dff872 CW |
10381 | } |
10382 | ||
10383 | static struct drm_framebuffer * | |
10384 | mode_fits_in_fbdev(struct drm_device *dev, | |
10385 | struct drm_display_mode *mode) | |
10386 | { | |
0695726e | 10387 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
d2dff872 CW |
10388 | struct drm_i915_private *dev_priv = dev->dev_private; |
10389 | struct drm_i915_gem_object *obj; | |
10390 | struct drm_framebuffer *fb; | |
10391 | ||
4c0e5528 | 10392 | if (!dev_priv->fbdev) |
d2dff872 CW |
10393 | return NULL; |
10394 | ||
4c0e5528 | 10395 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
10396 | return NULL; |
10397 | ||
4c0e5528 DV |
10398 | obj = dev_priv->fbdev->fb->obj; |
10399 | BUG_ON(!obj); | |
10400 | ||
8bcd4553 | 10401 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
10402 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
10403 | fb->bits_per_pixel)) | |
d2dff872 CW |
10404 | return NULL; |
10405 | ||
01f2c773 | 10406 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
10407 | return NULL; |
10408 | ||
10409 | return fb; | |
4520f53a DV |
10410 | #else |
10411 | return NULL; | |
10412 | #endif | |
d2dff872 CW |
10413 | } |
10414 | ||
d3a40d1b ACO |
10415 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
10416 | struct drm_crtc *crtc, | |
10417 | struct drm_display_mode *mode, | |
10418 | struct drm_framebuffer *fb, | |
10419 | int x, int y) | |
10420 | { | |
10421 | struct drm_plane_state *plane_state; | |
10422 | int hdisplay, vdisplay; | |
10423 | int ret; | |
10424 | ||
10425 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
10426 | if (IS_ERR(plane_state)) | |
10427 | return PTR_ERR(plane_state); | |
10428 | ||
10429 | if (mode) | |
10430 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
10431 | else | |
10432 | hdisplay = vdisplay = 0; | |
10433 | ||
10434 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
10435 | if (ret) | |
10436 | return ret; | |
10437 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10438 | plane_state->crtc_x = 0; | |
10439 | plane_state->crtc_y = 0; | |
10440 | plane_state->crtc_w = hdisplay; | |
10441 | plane_state->crtc_h = vdisplay; | |
10442 | plane_state->src_x = x << 16; | |
10443 | plane_state->src_y = y << 16; | |
10444 | plane_state->src_w = hdisplay << 16; | |
10445 | plane_state->src_h = vdisplay << 16; | |
10446 | ||
10447 | return 0; | |
10448 | } | |
10449 | ||
d2434ab7 | 10450 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 10451 | struct drm_display_mode *mode, |
51fd371b RC |
10452 | struct intel_load_detect_pipe *old, |
10453 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
10454 | { |
10455 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
10456 | struct intel_encoder *intel_encoder = |
10457 | intel_attached_encoder(connector); | |
79e53945 | 10458 | struct drm_crtc *possible_crtc; |
4ef69c7a | 10459 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
10460 | struct drm_crtc *crtc = NULL; |
10461 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 10462 | struct drm_framebuffer *fb; |
51fd371b | 10463 | struct drm_mode_config *config = &dev->mode_config; |
83a57153 | 10464 | struct drm_atomic_state *state = NULL; |
944b0c76 | 10465 | struct drm_connector_state *connector_state; |
4be07317 | 10466 | struct intel_crtc_state *crtc_state; |
51fd371b | 10467 | int ret, i = -1; |
79e53945 | 10468 | |
d2dff872 | 10469 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10470 | connector->base.id, connector->name, |
8e329a03 | 10471 | encoder->base.id, encoder->name); |
d2dff872 | 10472 | |
51fd371b RC |
10473 | retry: |
10474 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
10475 | if (ret) | |
ad3c558f | 10476 | goto fail; |
6e9f798d | 10477 | |
79e53945 JB |
10478 | /* |
10479 | * Algorithm gets a little messy: | |
7a5e4805 | 10480 | * |
79e53945 JB |
10481 | * - if the connector already has an assigned crtc, use it (but make |
10482 | * sure it's on first) | |
7a5e4805 | 10483 | * |
79e53945 JB |
10484 | * - try to find the first unused crtc that can drive this connector, |
10485 | * and use that if we find one | |
79e53945 JB |
10486 | */ |
10487 | ||
10488 | /* See if we already have a CRTC for this connector */ | |
10489 | if (encoder->crtc) { | |
10490 | crtc = encoder->crtc; | |
8261b191 | 10491 | |
51fd371b | 10492 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 10493 | if (ret) |
ad3c558f | 10494 | goto fail; |
4d02e2de | 10495 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
51fd371b | 10496 | if (ret) |
ad3c558f | 10497 | goto fail; |
7b24056b | 10498 | |
24218aac | 10499 | old->dpms_mode = connector->dpms; |
8261b191 CW |
10500 | old->load_detect_temp = false; |
10501 | ||
10502 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
10503 | if (connector->dpms != DRM_MODE_DPMS_ON) |
10504 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 10505 | |
7173188d | 10506 | return true; |
79e53945 JB |
10507 | } |
10508 | ||
10509 | /* Find an unused one (if possible) */ | |
70e1e0ec | 10510 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
10511 | i++; |
10512 | if (!(encoder->possible_crtcs & (1 << i))) | |
10513 | continue; | |
83d65738 | 10514 | if (possible_crtc->state->enable) |
a459249c | 10515 | continue; |
a459249c VS |
10516 | |
10517 | crtc = possible_crtc; | |
10518 | break; | |
79e53945 JB |
10519 | } |
10520 | ||
10521 | /* | |
10522 | * If we didn't find an unused CRTC, don't use any. | |
10523 | */ | |
10524 | if (!crtc) { | |
7173188d | 10525 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 10526 | goto fail; |
79e53945 JB |
10527 | } |
10528 | ||
51fd371b RC |
10529 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
10530 | if (ret) | |
ad3c558f | 10531 | goto fail; |
4d02e2de DV |
10532 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
10533 | if (ret) | |
ad3c558f | 10534 | goto fail; |
79e53945 JB |
10535 | |
10536 | intel_crtc = to_intel_crtc(crtc); | |
24218aac | 10537 | old->dpms_mode = connector->dpms; |
8261b191 | 10538 | old->load_detect_temp = true; |
d2dff872 | 10539 | old->release_fb = NULL; |
79e53945 | 10540 | |
83a57153 ACO |
10541 | state = drm_atomic_state_alloc(dev); |
10542 | if (!state) | |
10543 | return false; | |
10544 | ||
10545 | state->acquire_ctx = ctx; | |
10546 | ||
944b0c76 ACO |
10547 | connector_state = drm_atomic_get_connector_state(state, connector); |
10548 | if (IS_ERR(connector_state)) { | |
10549 | ret = PTR_ERR(connector_state); | |
10550 | goto fail; | |
10551 | } | |
10552 | ||
10553 | connector_state->crtc = crtc; | |
10554 | connector_state->best_encoder = &intel_encoder->base; | |
10555 | ||
4be07317 ACO |
10556 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10557 | if (IS_ERR(crtc_state)) { | |
10558 | ret = PTR_ERR(crtc_state); | |
10559 | goto fail; | |
10560 | } | |
10561 | ||
49d6fa21 | 10562 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 10563 | |
6492711d CW |
10564 | if (!mode) |
10565 | mode = &load_detect_mode; | |
79e53945 | 10566 | |
d2dff872 CW |
10567 | /* We need a framebuffer large enough to accommodate all accesses |
10568 | * that the plane may generate whilst we perform load detection. | |
10569 | * We can not rely on the fbcon either being present (we get called | |
10570 | * during its initialisation to detect all boot displays, or it may | |
10571 | * not even exist) or that it is large enough to satisfy the | |
10572 | * requested mode. | |
10573 | */ | |
94352cf9 DV |
10574 | fb = mode_fits_in_fbdev(dev, mode); |
10575 | if (fb == NULL) { | |
d2dff872 | 10576 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
10577 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
10578 | old->release_fb = fb; | |
d2dff872 CW |
10579 | } else |
10580 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10581 | if (IS_ERR(fb)) { |
d2dff872 | 10582 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 10583 | goto fail; |
79e53945 | 10584 | } |
79e53945 | 10585 | |
d3a40d1b ACO |
10586 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10587 | if (ret) | |
10588 | goto fail; | |
10589 | ||
8c7b5ccb ACO |
10590 | drm_mode_copy(&crtc_state->base.mode, mode); |
10591 | ||
74c090b1 | 10592 | if (drm_atomic_commit(state)) { |
6492711d | 10593 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
10594 | if (old->release_fb) |
10595 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 10596 | goto fail; |
79e53945 | 10597 | } |
9128b040 | 10598 | crtc->primary->crtc = crtc; |
7173188d | 10599 | |
79e53945 | 10600 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 10601 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 10602 | return true; |
412b61d8 | 10603 | |
ad3c558f | 10604 | fail: |
e5d958ef ACO |
10605 | drm_atomic_state_free(state); |
10606 | state = NULL; | |
83a57153 | 10607 | |
51fd371b RC |
10608 | if (ret == -EDEADLK) { |
10609 | drm_modeset_backoff(ctx); | |
10610 | goto retry; | |
10611 | } | |
10612 | ||
412b61d8 | 10613 | return false; |
79e53945 JB |
10614 | } |
10615 | ||
d2434ab7 | 10616 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10617 | struct intel_load_detect_pipe *old, |
10618 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10619 | { |
83a57153 | 10620 | struct drm_device *dev = connector->dev; |
d2434ab7 DV |
10621 | struct intel_encoder *intel_encoder = |
10622 | intel_attached_encoder(connector); | |
4ef69c7a | 10623 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 10624 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 10625 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83a57153 | 10626 | struct drm_atomic_state *state; |
944b0c76 | 10627 | struct drm_connector_state *connector_state; |
4be07317 | 10628 | struct intel_crtc_state *crtc_state; |
d3a40d1b | 10629 | int ret; |
79e53945 | 10630 | |
d2dff872 | 10631 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10632 | connector->base.id, connector->name, |
8e329a03 | 10633 | encoder->base.id, encoder->name); |
d2dff872 | 10634 | |
8261b191 | 10635 | if (old->load_detect_temp) { |
83a57153 | 10636 | state = drm_atomic_state_alloc(dev); |
944b0c76 ACO |
10637 | if (!state) |
10638 | goto fail; | |
83a57153 ACO |
10639 | |
10640 | state->acquire_ctx = ctx; | |
10641 | ||
944b0c76 ACO |
10642 | connector_state = drm_atomic_get_connector_state(state, connector); |
10643 | if (IS_ERR(connector_state)) | |
10644 | goto fail; | |
10645 | ||
4be07317 ACO |
10646 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10647 | if (IS_ERR(crtc_state)) | |
10648 | goto fail; | |
10649 | ||
944b0c76 ACO |
10650 | connector_state->best_encoder = NULL; |
10651 | connector_state->crtc = NULL; | |
10652 | ||
49d6fa21 | 10653 | crtc_state->base.enable = crtc_state->base.active = false; |
4be07317 | 10654 | |
d3a40d1b ACO |
10655 | ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL, |
10656 | 0, 0); | |
10657 | if (ret) | |
10658 | goto fail; | |
10659 | ||
74c090b1 | 10660 | ret = drm_atomic_commit(state); |
2bfb4627 ACO |
10661 | if (ret) |
10662 | goto fail; | |
d2dff872 | 10663 | |
36206361 DV |
10664 | if (old->release_fb) { |
10665 | drm_framebuffer_unregister_private(old->release_fb); | |
10666 | drm_framebuffer_unreference(old->release_fb); | |
10667 | } | |
d2dff872 | 10668 | |
0622a53c | 10669 | return; |
79e53945 JB |
10670 | } |
10671 | ||
c751ce4f | 10672 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
10673 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
10674 | connector->funcs->dpms(connector, old->dpms_mode); | |
944b0c76 ACO |
10675 | |
10676 | return; | |
10677 | fail: | |
10678 | DRM_DEBUG_KMS("Couldn't release load detect pipe.\n"); | |
10679 | drm_atomic_state_free(state); | |
79e53945 JB |
10680 | } |
10681 | ||
da4a1efa | 10682 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10683 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
10684 | { |
10685 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10686 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
10687 | ||
10688 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10689 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
10690 | else if (HAS_PCH_SPLIT(dev)) |
10691 | return 120000; | |
10692 | else if (!IS_GEN2(dev)) | |
10693 | return 96000; | |
10694 | else | |
10695 | return 48000; | |
10696 | } | |
10697 | ||
79e53945 | 10698 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10699 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10700 | struct intel_crtc_state *pipe_config) |
79e53945 | 10701 | { |
f1f644dc | 10702 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 10703 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 10704 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10705 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
10706 | u32 fp; |
10707 | intel_clock_t clock; | |
dccbea3b | 10708 | int port_clock; |
da4a1efa | 10709 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10710 | |
10711 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10712 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10713 | else |
293623f7 | 10714 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10715 | |
10716 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10717 | if (IS_PINEVIEW(dev)) { |
10718 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10719 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10720 | } else { |
10721 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10722 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10723 | } | |
10724 | ||
a6c45cf0 | 10725 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10726 | if (IS_PINEVIEW(dev)) |
10727 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10728 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10729 | else |
10730 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10731 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10732 | ||
10733 | switch (dpll & DPLL_MODE_MASK) { | |
10734 | case DPLLB_MODE_DAC_SERIAL: | |
10735 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10736 | 5 : 10; | |
10737 | break; | |
10738 | case DPLLB_MODE_LVDS: | |
10739 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10740 | 7 : 14; | |
10741 | break; | |
10742 | default: | |
28c97730 | 10743 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10744 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10745 | return; |
79e53945 JB |
10746 | } |
10747 | ||
ac58c3f0 | 10748 | if (IS_PINEVIEW(dev)) |
dccbea3b | 10749 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 10750 | else |
dccbea3b | 10751 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 10752 | } else { |
0fb58223 | 10753 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10754 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10755 | |
10756 | if (is_lvds) { | |
10757 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10758 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10759 | |
10760 | if (lvds & LVDS_CLKB_POWER_UP) | |
10761 | clock.p2 = 7; | |
10762 | else | |
10763 | clock.p2 = 14; | |
79e53945 JB |
10764 | } else { |
10765 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10766 | clock.p1 = 2; | |
10767 | else { | |
10768 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10769 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10770 | } | |
10771 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10772 | clock.p2 = 4; | |
10773 | else | |
10774 | clock.p2 = 2; | |
79e53945 | 10775 | } |
da4a1efa | 10776 | |
dccbea3b | 10777 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
10778 | } |
10779 | ||
18442d08 VS |
10780 | /* |
10781 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10782 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10783 | * encoder's get_config() function. |
10784 | */ | |
dccbea3b | 10785 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
10786 | } |
10787 | ||
6878da05 VS |
10788 | int intel_dotclock_calculate(int link_freq, |
10789 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10790 | { |
f1f644dc JB |
10791 | /* |
10792 | * The calculation for the data clock is: | |
1041a02f | 10793 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10794 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10795 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10796 | * |
10797 | * and the link clock is simpler: | |
1041a02f | 10798 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10799 | */ |
10800 | ||
6878da05 VS |
10801 | if (!m_n->link_n) |
10802 | return 0; | |
f1f644dc | 10803 | |
6878da05 VS |
10804 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10805 | } | |
f1f644dc | 10806 | |
18442d08 | 10807 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10808 | struct intel_crtc_state *pipe_config) |
6878da05 VS |
10809 | { |
10810 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 10811 | |
18442d08 VS |
10812 | /* read out port_clock from the DPLL */ |
10813 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10814 | |
f1f644dc | 10815 | /* |
18442d08 | 10816 | * This value does not include pixel_multiplier. |
241bfc38 | 10817 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
10818 | * agree once we know their relationship in the encoder's |
10819 | * get_config() function. | |
79e53945 | 10820 | */ |
2d112de7 | 10821 | pipe_config->base.adjusted_mode.crtc_clock = |
18442d08 VS |
10822 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
10823 | &pipe_config->fdi_m_n); | |
79e53945 JB |
10824 | } |
10825 | ||
10826 | /** Returns the currently programmed mode of the given pipe. */ | |
10827 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10828 | struct drm_crtc *crtc) | |
10829 | { | |
548f245b | 10830 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 10831 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10832 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10833 | struct drm_display_mode *mode; |
5cec258b | 10834 | struct intel_crtc_state pipe_config; |
fe2b8f9d PZ |
10835 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10836 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10837 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10838 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10839 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10840 | |
10841 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10842 | if (!mode) | |
10843 | return NULL; | |
10844 | ||
f1f644dc JB |
10845 | /* |
10846 | * Construct a pipe_config sufficient for getting the clock info | |
10847 | * back out of crtc_clock_get. | |
10848 | * | |
10849 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10850 | * to use a real value here instead. | |
10851 | */ | |
293623f7 | 10852 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 10853 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
10854 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
10855 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10856 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
10857 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
10858 | ||
773ae034 | 10859 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
10860 | mode->hdisplay = (htot & 0xffff) + 1; |
10861 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10862 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10863 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10864 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10865 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10866 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10867 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10868 | ||
10869 | drm_mode_set_name(mode); | |
79e53945 JB |
10870 | |
10871 | return mode; | |
10872 | } | |
10873 | ||
f047e395 CW |
10874 | void intel_mark_busy(struct drm_device *dev) |
10875 | { | |
c67a470b PZ |
10876 | struct drm_i915_private *dev_priv = dev->dev_private; |
10877 | ||
f62a0076 CW |
10878 | if (dev_priv->mm.busy) |
10879 | return; | |
10880 | ||
43694d69 | 10881 | intel_runtime_pm_get(dev_priv); |
c67a470b | 10882 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
10883 | if (INTEL_INFO(dev)->gen >= 6) |
10884 | gen6_rps_busy(dev_priv); | |
f62a0076 | 10885 | dev_priv->mm.busy = true; |
f047e395 CW |
10886 | } |
10887 | ||
10888 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 10889 | { |
c67a470b | 10890 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10891 | |
f62a0076 CW |
10892 | if (!dev_priv->mm.busy) |
10893 | return; | |
10894 | ||
10895 | dev_priv->mm.busy = false; | |
10896 | ||
3d13ef2e | 10897 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 10898 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 | 10899 | |
43694d69 | 10900 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
10901 | } |
10902 | ||
79e53945 JB |
10903 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
10904 | { | |
10905 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
10906 | struct drm_device *dev = crtc->dev; |
10907 | struct intel_unpin_work *work; | |
67e77c5a | 10908 | |
5e2d7afc | 10909 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
10910 | work = intel_crtc->unpin_work; |
10911 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 10912 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
10913 | |
10914 | if (work) { | |
10915 | cancel_work_sync(&work->work); | |
10916 | kfree(work); | |
10917 | } | |
79e53945 JB |
10918 | |
10919 | drm_crtc_cleanup(crtc); | |
67e77c5a | 10920 | |
79e53945 JB |
10921 | kfree(intel_crtc); |
10922 | } | |
10923 | ||
6b95a207 KH |
10924 | static void intel_unpin_work_fn(struct work_struct *__work) |
10925 | { | |
10926 | struct intel_unpin_work *work = | |
10927 | container_of(__work, struct intel_unpin_work, work); | |
a9ff8714 VS |
10928 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
10929 | struct drm_device *dev = crtc->base.dev; | |
10930 | struct drm_plane *primary = crtc->base.primary; | |
6b95a207 | 10931 | |
b4a98e57 | 10932 | mutex_lock(&dev->struct_mutex); |
a9ff8714 | 10933 | intel_unpin_fb_obj(work->old_fb, primary->state); |
05394f39 | 10934 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 10935 | |
f06cc1b9 | 10936 | if (work->flip_queued_req) |
146d84f0 | 10937 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
10938 | mutex_unlock(&dev->struct_mutex); |
10939 | ||
a9ff8714 | 10940 | intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit); |
89ed88ba | 10941 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 10942 | |
a9ff8714 VS |
10943 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
10944 | atomic_dec(&crtc->unpin_work_count); | |
b4a98e57 | 10945 | |
6b95a207 KH |
10946 | kfree(work); |
10947 | } | |
10948 | ||
1afe3e9d | 10949 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 10950 | struct drm_crtc *crtc) |
6b95a207 | 10951 | { |
6b95a207 KH |
10952 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10953 | struct intel_unpin_work *work; | |
6b95a207 KH |
10954 | unsigned long flags; |
10955 | ||
10956 | /* Ignore early vblank irqs */ | |
10957 | if (intel_crtc == NULL) | |
10958 | return; | |
10959 | ||
f326038a DV |
10960 | /* |
10961 | * This is called both by irq handlers and the reset code (to complete | |
10962 | * lost pageflips) so needs the full irqsave spinlocks. | |
10963 | */ | |
6b95a207 KH |
10964 | spin_lock_irqsave(&dev->event_lock, flags); |
10965 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
10966 | |
10967 | /* Ensure we don't miss a work->pending update ... */ | |
10968 | smp_rmb(); | |
10969 | ||
10970 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
10971 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10972 | return; | |
10973 | } | |
10974 | ||
d6bbafa1 | 10975 | page_flip_completed(intel_crtc); |
0af7e4df | 10976 | |
6b95a207 | 10977 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
10978 | } |
10979 | ||
1afe3e9d JB |
10980 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
10981 | { | |
fbee40df | 10982 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10983 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
10984 | ||
49b14a5c | 10985 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10986 | } |
10987 | ||
10988 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
10989 | { | |
fbee40df | 10990 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10991 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
10992 | ||
49b14a5c | 10993 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10994 | } |
10995 | ||
75f7f3ec VS |
10996 | /* Is 'a' after or equal to 'b'? */ |
10997 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
10998 | { | |
10999 | return !((a - b) & 0x80000000); | |
11000 | } | |
11001 | ||
11002 | static bool page_flip_finished(struct intel_crtc *crtc) | |
11003 | { | |
11004 | struct drm_device *dev = crtc->base.dev; | |
11005 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11006 | ||
bdfa7542 VS |
11007 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
11008 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
11009 | return true; | |
11010 | ||
75f7f3ec VS |
11011 | /* |
11012 | * The relevant registers doen't exist on pre-ctg. | |
11013 | * As the flip done interrupt doesn't trigger for mmio | |
11014 | * flips on gmch platforms, a flip count check isn't | |
11015 | * really needed there. But since ctg has the registers, | |
11016 | * include it in the check anyway. | |
11017 | */ | |
11018 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
11019 | return true; | |
11020 | ||
11021 | /* | |
11022 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
11023 | * used the same base address. In that case the mmio flip might | |
11024 | * have completed, but the CS hasn't even executed the flip yet. | |
11025 | * | |
11026 | * A flip count check isn't enough as the CS might have updated | |
11027 | * the base address just after start of vblank, but before we | |
11028 | * managed to process the interrupt. This means we'd complete the | |
11029 | * CS flip too soon. | |
11030 | * | |
11031 | * Combining both checks should get us a good enough result. It may | |
11032 | * still happen that the CS flip has been executed, but has not | |
11033 | * yet actually completed. But in case the base address is the same | |
11034 | * anyway, we don't really care. | |
11035 | */ | |
11036 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
11037 | crtc->unpin_work->gtt_offset && | |
fd8f507c | 11038 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), |
75f7f3ec VS |
11039 | crtc->unpin_work->flip_count); |
11040 | } | |
11041 | ||
6b95a207 KH |
11042 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
11043 | { | |
fbee40df | 11044 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
11045 | struct intel_crtc *intel_crtc = |
11046 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
11047 | unsigned long flags; | |
11048 | ||
f326038a DV |
11049 | |
11050 | /* | |
11051 | * This is called both by irq handlers and the reset code (to complete | |
11052 | * lost pageflips) so needs the full irqsave spinlocks. | |
11053 | * | |
11054 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
11055 | * generate a page-flip completion irq, i.e. every modeset |
11056 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
11057 | */ | |
6b95a207 | 11058 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 11059 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 11060 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
11061 | spin_unlock_irqrestore(&dev->event_lock, flags); |
11062 | } | |
11063 | ||
6042639c | 11064 | static inline void intel_mark_page_flip_active(struct intel_unpin_work *work) |
e7d841ca CW |
11065 | { |
11066 | /* Ensure that the work item is consistent when activating it ... */ | |
11067 | smp_wmb(); | |
6042639c | 11068 | atomic_set(&work->pending, INTEL_FLIP_PENDING); |
e7d841ca CW |
11069 | /* and that it is marked active as soon as the irq could fire. */ |
11070 | smp_wmb(); | |
11071 | } | |
11072 | ||
8c9f3aaf JB |
11073 | static int intel_gen2_queue_flip(struct drm_device *dev, |
11074 | struct drm_crtc *crtc, | |
11075 | struct drm_framebuffer *fb, | |
ed8d1975 | 11076 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11077 | struct drm_i915_gem_request *req, |
ed8d1975 | 11078 | uint32_t flags) |
8c9f3aaf | 11079 | { |
6258fbe2 | 11080 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf | 11081 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
11082 | u32 flip_mask; |
11083 | int ret; | |
11084 | ||
5fb9de1a | 11085 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 11086 | if (ret) |
4fa62c89 | 11087 | return ret; |
8c9f3aaf JB |
11088 | |
11089 | /* Can't queue multiple flips, so wait for the previous | |
11090 | * one to finish before executing the next. | |
11091 | */ | |
11092 | if (intel_crtc->plane) | |
11093 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11094 | else | |
11095 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
11096 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11097 | intel_ring_emit(ring, MI_NOOP); | |
11098 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
11099 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11100 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11101 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 11102 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca | 11103 | |
6042639c | 11104 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11105 | return 0; |
8c9f3aaf JB |
11106 | } |
11107 | ||
11108 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
11109 | struct drm_crtc *crtc, | |
11110 | struct drm_framebuffer *fb, | |
ed8d1975 | 11111 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11112 | struct drm_i915_gem_request *req, |
ed8d1975 | 11113 | uint32_t flags) |
8c9f3aaf | 11114 | { |
6258fbe2 | 11115 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf | 11116 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
11117 | u32 flip_mask; |
11118 | int ret; | |
11119 | ||
5fb9de1a | 11120 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 11121 | if (ret) |
4fa62c89 | 11122 | return ret; |
8c9f3aaf JB |
11123 | |
11124 | if (intel_crtc->plane) | |
11125 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11126 | else | |
11127 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
11128 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11129 | intel_ring_emit(ring, MI_NOOP); | |
11130 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
11131 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11132 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11133 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
11134 | intel_ring_emit(ring, MI_NOOP); |
11135 | ||
6042639c | 11136 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11137 | return 0; |
8c9f3aaf JB |
11138 | } |
11139 | ||
11140 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
11141 | struct drm_crtc *crtc, | |
11142 | struct drm_framebuffer *fb, | |
ed8d1975 | 11143 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11144 | struct drm_i915_gem_request *req, |
ed8d1975 | 11145 | uint32_t flags) |
8c9f3aaf | 11146 | { |
6258fbe2 | 11147 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf JB |
11148 | struct drm_i915_private *dev_priv = dev->dev_private; |
11149 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11150 | uint32_t pf, pipesrc; | |
11151 | int ret; | |
11152 | ||
5fb9de1a | 11153 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11154 | if (ret) |
4fa62c89 | 11155 | return ret; |
8c9f3aaf JB |
11156 | |
11157 | /* i965+ uses the linear or tiled offsets from the | |
11158 | * Display Registers (which do not change across a page-flip) | |
11159 | * so we need only reprogram the base address. | |
11160 | */ | |
6d90c952 DV |
11161 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
11162 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11163 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11164 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 11165 | obj->tiling_mode); |
8c9f3aaf JB |
11166 | |
11167 | /* XXX Enabling the panel-fitter across page-flip is so far | |
11168 | * untested on non-native modes, so ignore it for now. | |
11169 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
11170 | */ | |
11171 | pf = 0; | |
11172 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 11173 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca | 11174 | |
6042639c | 11175 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11176 | return 0; |
8c9f3aaf JB |
11177 | } |
11178 | ||
11179 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
11180 | struct drm_crtc *crtc, | |
11181 | struct drm_framebuffer *fb, | |
ed8d1975 | 11182 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11183 | struct drm_i915_gem_request *req, |
ed8d1975 | 11184 | uint32_t flags) |
8c9f3aaf | 11185 | { |
6258fbe2 | 11186 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf JB |
11187 | struct drm_i915_private *dev_priv = dev->dev_private; |
11188 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11189 | uint32_t pf, pipesrc; | |
11190 | int ret; | |
11191 | ||
5fb9de1a | 11192 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11193 | if (ret) |
4fa62c89 | 11194 | return ret; |
8c9f3aaf | 11195 | |
6d90c952 DV |
11196 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
11197 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11198 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 11199 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 11200 | |
dc257cf1 DV |
11201 | /* Contrary to the suggestions in the documentation, |
11202 | * "Enable Panel Fitter" does not seem to be required when page | |
11203 | * flipping with a non-native mode, and worse causes a normal | |
11204 | * modeset to fail. | |
11205 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
11206 | */ | |
11207 | pf = 0; | |
8c9f3aaf | 11208 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 11209 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca | 11210 | |
6042639c | 11211 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11212 | return 0; |
8c9f3aaf JB |
11213 | } |
11214 | ||
7c9017e5 JB |
11215 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11216 | struct drm_crtc *crtc, | |
11217 | struct drm_framebuffer *fb, | |
ed8d1975 | 11218 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11219 | struct drm_i915_gem_request *req, |
ed8d1975 | 11220 | uint32_t flags) |
7c9017e5 | 11221 | { |
6258fbe2 | 11222 | struct intel_engine_cs *ring = req->ring; |
7c9017e5 | 11223 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 11224 | uint32_t plane_bit = 0; |
ffe74d75 CW |
11225 | int len, ret; |
11226 | ||
eba905b2 | 11227 | switch (intel_crtc->plane) { |
cb05d8de DV |
11228 | case PLANE_A: |
11229 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11230 | break; | |
11231 | case PLANE_B: | |
11232 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11233 | break; | |
11234 | case PLANE_C: | |
11235 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11236 | break; | |
11237 | default: | |
11238 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 11239 | return -ENODEV; |
cb05d8de DV |
11240 | } |
11241 | ||
ffe74d75 | 11242 | len = 4; |
f476828a | 11243 | if (ring->id == RCS) { |
ffe74d75 | 11244 | len += 6; |
f476828a DL |
11245 | /* |
11246 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11247 | * 48bits addresses, and we need a NOOP for the batch size to | |
11248 | * stay even. | |
11249 | */ | |
11250 | if (IS_GEN8(dev)) | |
11251 | len += 2; | |
11252 | } | |
ffe74d75 | 11253 | |
f66fab8e VS |
11254 | /* |
11255 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11256 | * "The full packet must be contained within the same cache line." | |
11257 | * | |
11258 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11259 | * cacheline, if we ever start emitting more commands before | |
11260 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11261 | * then do the cacheline alignment, and finally emit the | |
11262 | * MI_DISPLAY_FLIP. | |
11263 | */ | |
bba09b12 | 11264 | ret = intel_ring_cacheline_align(req); |
f66fab8e | 11265 | if (ret) |
4fa62c89 | 11266 | return ret; |
f66fab8e | 11267 | |
5fb9de1a | 11268 | ret = intel_ring_begin(req, len); |
7c9017e5 | 11269 | if (ret) |
4fa62c89 | 11270 | return ret; |
7c9017e5 | 11271 | |
ffe74d75 CW |
11272 | /* Unmask the flip-done completion message. Note that the bspec says that |
11273 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11274 | * more than one flip event at any time (or ensure that one flip message | |
11275 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11276 | * Experimentation says that BCS works despite DERRMR masking all | |
11277 | * flip-done completion events and that unmasking all planes at once | |
11278 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11279 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11280 | */ | |
11281 | if (ring->id == RCS) { | |
11282 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
f92a9162 | 11283 | intel_ring_emit_reg(ring, DERRMR); |
ffe74d75 CW |
11284 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | |
11285 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
11286 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a | 11287 | if (IS_GEN8(dev)) |
f1afe24f | 11288 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 | |
f476828a DL |
11289 | MI_SRM_LRM_GLOBAL_GTT); |
11290 | else | |
f1afe24f | 11291 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM | |
f476828a | 11292 | MI_SRM_LRM_GLOBAL_GTT); |
f92a9162 | 11293 | intel_ring_emit_reg(ring, DERRMR); |
ffe74d75 | 11294 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
f476828a DL |
11295 | if (IS_GEN8(dev)) { |
11296 | intel_ring_emit(ring, 0); | |
11297 | intel_ring_emit(ring, MI_NOOP); | |
11298 | } | |
ffe74d75 CW |
11299 | } |
11300 | ||
cb05d8de | 11301 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 11302 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 11303 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 11304 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca | 11305 | |
6042639c | 11306 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11307 | return 0; |
7c9017e5 JB |
11308 | } |
11309 | ||
84c33a64 SG |
11310 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
11311 | struct drm_i915_gem_object *obj) | |
11312 | { | |
11313 | /* | |
11314 | * This is not being used for older platforms, because | |
11315 | * non-availability of flip done interrupt forces us to use | |
11316 | * CS flips. Older platforms derive flip done using some clever | |
11317 | * tricks involving the flip_pending status bits and vblank irqs. | |
11318 | * So using MMIO flips there would disrupt this mechanism. | |
11319 | */ | |
11320 | ||
8e09bf83 CW |
11321 | if (ring == NULL) |
11322 | return true; | |
11323 | ||
84c33a64 SG |
11324 | if (INTEL_INFO(ring->dev)->gen < 5) |
11325 | return false; | |
11326 | ||
11327 | if (i915.use_mmio_flip < 0) | |
11328 | return false; | |
11329 | else if (i915.use_mmio_flip > 0) | |
11330 | return true; | |
14bf993e OM |
11331 | else if (i915.enable_execlists) |
11332 | return true; | |
fd8e058a AG |
11333 | else if (obj->base.dma_buf && |
11334 | !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv, | |
11335 | false)) | |
11336 | return true; | |
84c33a64 | 11337 | else |
b4716185 | 11338 | return ring != i915_gem_request_get_ring(obj->last_write_req); |
84c33a64 SG |
11339 | } |
11340 | ||
6042639c | 11341 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, |
86efe24a | 11342 | unsigned int rotation, |
6042639c | 11343 | struct intel_unpin_work *work) |
ff944564 DL |
11344 | { |
11345 | struct drm_device *dev = intel_crtc->base.dev; | |
11346 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11347 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
ff944564 | 11348 | const enum pipe pipe = intel_crtc->pipe; |
86efe24a | 11349 | u32 ctl, stride, tile_height; |
ff944564 DL |
11350 | |
11351 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
11352 | ctl &= ~PLANE_CTL_TILED_MASK; | |
2ebef630 TU |
11353 | switch (fb->modifier[0]) { |
11354 | case DRM_FORMAT_MOD_NONE: | |
11355 | break; | |
11356 | case I915_FORMAT_MOD_X_TILED: | |
ff944564 | 11357 | ctl |= PLANE_CTL_TILED_X; |
2ebef630 TU |
11358 | break; |
11359 | case I915_FORMAT_MOD_Y_TILED: | |
11360 | ctl |= PLANE_CTL_TILED_Y; | |
11361 | break; | |
11362 | case I915_FORMAT_MOD_Yf_TILED: | |
11363 | ctl |= PLANE_CTL_TILED_YF; | |
11364 | break; | |
11365 | default: | |
11366 | MISSING_CASE(fb->modifier[0]); | |
11367 | } | |
ff944564 DL |
11368 | |
11369 | /* | |
11370 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
11371 | * linear buffers or in number of tiles for tiled buffers. | |
11372 | */ | |
86efe24a TU |
11373 | if (intel_rotation_90_or_270(rotation)) { |
11374 | /* stride = Surface height in tiles */ | |
11375 | tile_height = intel_tile_height(dev, fb->pixel_format, | |
11376 | fb->modifier[0], 0); | |
11377 | stride = DIV_ROUND_UP(fb->height, tile_height); | |
11378 | } else { | |
11379 | stride = fb->pitches[0] / | |
11380 | intel_fb_stride_alignment(dev, fb->modifier[0], | |
11381 | fb->pixel_format); | |
11382 | } | |
ff944564 DL |
11383 | |
11384 | /* | |
11385 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
11386 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
11387 | */ | |
11388 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
11389 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
11390 | ||
6042639c | 11391 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); |
ff944564 DL |
11392 | POSTING_READ(PLANE_SURF(pipe, 0)); |
11393 | } | |
11394 | ||
6042639c CW |
11395 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, |
11396 | struct intel_unpin_work *work) | |
84c33a64 SG |
11397 | { |
11398 | struct drm_device *dev = intel_crtc->base.dev; | |
11399 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11400 | struct intel_framebuffer *intel_fb = | |
11401 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
11402 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
f0f59a00 | 11403 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); |
84c33a64 | 11404 | u32 dspcntr; |
84c33a64 | 11405 | |
84c33a64 SG |
11406 | dspcntr = I915_READ(reg); |
11407 | ||
c5d97472 DL |
11408 | if (obj->tiling_mode != I915_TILING_NONE) |
11409 | dspcntr |= DISPPLANE_TILED; | |
11410 | else | |
11411 | dspcntr &= ~DISPPLANE_TILED; | |
11412 | ||
84c33a64 SG |
11413 | I915_WRITE(reg, dspcntr); |
11414 | ||
6042639c | 11415 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); |
84c33a64 | 11416 | POSTING_READ(DSPSURF(intel_crtc->plane)); |
ff944564 DL |
11417 | } |
11418 | ||
11419 | /* | |
11420 | * XXX: This is the temporary way to update the plane registers until we get | |
11421 | * around to using the usual plane update functions for MMIO flips | |
11422 | */ | |
6042639c | 11423 | static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip) |
ff944564 | 11424 | { |
6042639c CW |
11425 | struct intel_crtc *crtc = mmio_flip->crtc; |
11426 | struct intel_unpin_work *work; | |
11427 | ||
11428 | spin_lock_irq(&crtc->base.dev->event_lock); | |
11429 | work = crtc->unpin_work; | |
11430 | spin_unlock_irq(&crtc->base.dev->event_lock); | |
11431 | if (work == NULL) | |
11432 | return; | |
ff944564 | 11433 | |
6042639c | 11434 | intel_mark_page_flip_active(work); |
ff944564 | 11435 | |
6042639c | 11436 | intel_pipe_update_start(crtc); |
ff944564 | 11437 | |
6042639c | 11438 | if (INTEL_INFO(mmio_flip->i915)->gen >= 9) |
86efe24a | 11439 | skl_do_mmio_flip(crtc, mmio_flip->rotation, work); |
ff944564 DL |
11440 | else |
11441 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
6042639c | 11442 | ilk_do_mmio_flip(crtc, work); |
ff944564 | 11443 | |
6042639c | 11444 | intel_pipe_update_end(crtc); |
84c33a64 SG |
11445 | } |
11446 | ||
9362c7c5 | 11447 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 11448 | { |
b2cfe0ab CW |
11449 | struct intel_mmio_flip *mmio_flip = |
11450 | container_of(work, struct intel_mmio_flip, work); | |
fd8e058a AG |
11451 | struct intel_framebuffer *intel_fb = |
11452 | to_intel_framebuffer(mmio_flip->crtc->base.primary->fb); | |
11453 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
84c33a64 | 11454 | |
6042639c | 11455 | if (mmio_flip->req) { |
eed29a5b | 11456 | WARN_ON(__i915_wait_request(mmio_flip->req, |
b2cfe0ab | 11457 | mmio_flip->crtc->reset_counter, |
bcafc4e3 CW |
11458 | false, NULL, |
11459 | &mmio_flip->i915->rps.mmioflips)); | |
6042639c CW |
11460 | i915_gem_request_unreference__unlocked(mmio_flip->req); |
11461 | } | |
84c33a64 | 11462 | |
fd8e058a AG |
11463 | /* For framebuffer backed by dmabuf, wait for fence */ |
11464 | if (obj->base.dma_buf) | |
11465 | WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
11466 | false, false, | |
11467 | MAX_SCHEDULE_TIMEOUT) < 0); | |
11468 | ||
6042639c | 11469 | intel_do_mmio_flip(mmio_flip); |
b2cfe0ab | 11470 | kfree(mmio_flip); |
84c33a64 SG |
11471 | } |
11472 | ||
11473 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
11474 | struct drm_crtc *crtc, | |
86efe24a | 11475 | struct drm_i915_gem_object *obj) |
84c33a64 | 11476 | { |
b2cfe0ab CW |
11477 | struct intel_mmio_flip *mmio_flip; |
11478 | ||
11479 | mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); | |
11480 | if (mmio_flip == NULL) | |
11481 | return -ENOMEM; | |
84c33a64 | 11482 | |
bcafc4e3 | 11483 | mmio_flip->i915 = to_i915(dev); |
eed29a5b | 11484 | mmio_flip->req = i915_gem_request_reference(obj->last_write_req); |
b2cfe0ab | 11485 | mmio_flip->crtc = to_intel_crtc(crtc); |
86efe24a | 11486 | mmio_flip->rotation = crtc->primary->state->rotation; |
536f5b5e | 11487 | |
b2cfe0ab CW |
11488 | INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); |
11489 | schedule_work(&mmio_flip->work); | |
84c33a64 | 11490 | |
84c33a64 SG |
11491 | return 0; |
11492 | } | |
11493 | ||
8c9f3aaf JB |
11494 | static int intel_default_queue_flip(struct drm_device *dev, |
11495 | struct drm_crtc *crtc, | |
11496 | struct drm_framebuffer *fb, | |
ed8d1975 | 11497 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11498 | struct drm_i915_gem_request *req, |
ed8d1975 | 11499 | uint32_t flags) |
8c9f3aaf JB |
11500 | { |
11501 | return -ENODEV; | |
11502 | } | |
11503 | ||
d6bbafa1 CW |
11504 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
11505 | struct drm_crtc *crtc) | |
11506 | { | |
11507 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11508 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11509 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
11510 | u32 addr; | |
11511 | ||
11512 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
11513 | return true; | |
11514 | ||
908565c2 CW |
11515 | if (atomic_read(&work->pending) < INTEL_FLIP_PENDING) |
11516 | return false; | |
11517 | ||
d6bbafa1 CW |
11518 | if (!work->enable_stall_check) |
11519 | return false; | |
11520 | ||
11521 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
11522 | if (work->flip_queued_req && |
11523 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
11524 | return false; |
11525 | ||
1e3feefd | 11526 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
11527 | } |
11528 | ||
1e3feefd | 11529 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
11530 | return false; |
11531 | ||
11532 | /* Potential stall - if we see that the flip has happened, | |
11533 | * assume a missed interrupt. */ | |
11534 | if (INTEL_INFO(dev)->gen >= 4) | |
11535 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
11536 | else | |
11537 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
11538 | ||
11539 | /* There is a potential issue here with a false positive after a flip | |
11540 | * to the same address. We could address this by checking for a | |
11541 | * non-incrementing frame counter. | |
11542 | */ | |
11543 | return addr == work->gtt_offset; | |
11544 | } | |
11545 | ||
11546 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
11547 | { | |
11548 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11549 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
11550 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6ad790c0 | 11551 | struct intel_unpin_work *work; |
f326038a | 11552 | |
6c51d46f | 11553 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
11554 | |
11555 | if (crtc == NULL) | |
11556 | return; | |
11557 | ||
f326038a | 11558 | spin_lock(&dev->event_lock); |
6ad790c0 CW |
11559 | work = intel_crtc->unpin_work; |
11560 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
d6bbafa1 | 11561 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
6ad790c0 | 11562 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
d6bbafa1 | 11563 | page_flip_completed(intel_crtc); |
6ad790c0 | 11564 | work = NULL; |
d6bbafa1 | 11565 | } |
6ad790c0 CW |
11566 | if (work != NULL && |
11567 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
11568 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); | |
f326038a | 11569 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
11570 | } |
11571 | ||
6b95a207 KH |
11572 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
11573 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
11574 | struct drm_pending_vblank_event *event, |
11575 | uint32_t page_flip_flags) | |
6b95a207 KH |
11576 | { |
11577 | struct drm_device *dev = crtc->dev; | |
11578 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 11579 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 11580 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 11581 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 11582 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 11583 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 11584 | struct intel_unpin_work *work; |
a4872ba6 | 11585 | struct intel_engine_cs *ring; |
cf5d8a46 | 11586 | bool mmio_flip; |
91af127f | 11587 | struct drm_i915_gem_request *request = NULL; |
52e68630 | 11588 | int ret; |
6b95a207 | 11589 | |
2ff8fde1 MR |
11590 | /* |
11591 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
11592 | * check to be safe. In the future we may enable pageflipping from | |
11593 | * a disabled primary plane. | |
11594 | */ | |
11595 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
11596 | return -EBUSY; | |
11597 | ||
e6a595d2 | 11598 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 11599 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
11600 | return -EINVAL; |
11601 | ||
11602 | /* | |
11603 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
11604 | * Note that pitch changes could also affect these register. | |
11605 | */ | |
11606 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
11607 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
11608 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
11609 | return -EINVAL; |
11610 | ||
f900db47 CW |
11611 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
11612 | goto out_hang; | |
11613 | ||
b14c5679 | 11614 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
11615 | if (work == NULL) |
11616 | return -ENOMEM; | |
11617 | ||
6b95a207 | 11618 | work->event = event; |
b4a98e57 | 11619 | work->crtc = crtc; |
ab8d6675 | 11620 | work->old_fb = old_fb; |
6b95a207 KH |
11621 | INIT_WORK(&work->work, intel_unpin_work_fn); |
11622 | ||
87b6b101 | 11623 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
11624 | if (ret) |
11625 | goto free_work; | |
11626 | ||
6b95a207 | 11627 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 11628 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 11629 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
11630 | /* Before declaring the flip queue wedged, check if |
11631 | * the hardware completed the operation behind our backs. | |
11632 | */ | |
11633 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
11634 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
11635 | page_flip_completed(intel_crtc); | |
11636 | } else { | |
11637 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 11638 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 11639 | |
d6bbafa1 CW |
11640 | drm_crtc_vblank_put(crtc); |
11641 | kfree(work); | |
11642 | return -EBUSY; | |
11643 | } | |
6b95a207 KH |
11644 | } |
11645 | intel_crtc->unpin_work = work; | |
5e2d7afc | 11646 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 11647 | |
b4a98e57 CW |
11648 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
11649 | flush_workqueue(dev_priv->wq); | |
11650 | ||
75dfca80 | 11651 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 11652 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 11653 | drm_gem_object_reference(&obj->base); |
6b95a207 | 11654 | |
f4510a27 | 11655 | crtc->primary->fb = fb; |
afd65eb4 | 11656 | update_state_fb(crtc->primary); |
1ed1f968 | 11657 | |
e1f99ce6 | 11658 | work->pending_flip_obj = obj; |
e1f99ce6 | 11659 | |
89ed88ba CW |
11660 | ret = i915_mutex_lock_interruptible(dev); |
11661 | if (ret) | |
11662 | goto cleanup; | |
11663 | ||
b4a98e57 | 11664 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 11665 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 11666 | |
75f7f3ec | 11667 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
fd8f507c | 11668 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
75f7f3ec | 11669 | |
666a4537 | 11670 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
4fa62c89 | 11671 | ring = &dev_priv->ring[BCS]; |
ab8d6675 | 11672 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 CW |
11673 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
11674 | ring = NULL; | |
48bf5b2d | 11675 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
2a92d5bc | 11676 | ring = &dev_priv->ring[BCS]; |
4fa62c89 | 11677 | } else if (INTEL_INFO(dev)->gen >= 7) { |
b4716185 | 11678 | ring = i915_gem_request_get_ring(obj->last_write_req); |
4fa62c89 VS |
11679 | if (ring == NULL || ring->id != RCS) |
11680 | ring = &dev_priv->ring[BCS]; | |
11681 | } else { | |
11682 | ring = &dev_priv->ring[RCS]; | |
11683 | } | |
11684 | ||
cf5d8a46 CW |
11685 | mmio_flip = use_mmio_flip(ring, obj); |
11686 | ||
11687 | /* When using CS flips, we want to emit semaphores between rings. | |
11688 | * However, when using mmio flips we will create a task to do the | |
11689 | * synchronisation, so all we want here is to pin the framebuffer | |
11690 | * into the display plane and skip any waits. | |
11691 | */ | |
7580d774 ML |
11692 | if (!mmio_flip) { |
11693 | ret = i915_gem_object_sync(obj, ring, &request); | |
11694 | if (ret) | |
11695 | goto cleanup_pending; | |
11696 | } | |
11697 | ||
82bc3b2d | 11698 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, |
7580d774 | 11699 | crtc->primary->state); |
8c9f3aaf JB |
11700 | if (ret) |
11701 | goto cleanup_pending; | |
6b95a207 | 11702 | |
dedf278c TU |
11703 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), |
11704 | obj, 0); | |
11705 | work->gtt_offset += intel_crtc->dspaddr_offset; | |
4fa62c89 | 11706 | |
cf5d8a46 | 11707 | if (mmio_flip) { |
86efe24a | 11708 | ret = intel_queue_mmio_flip(dev, crtc, obj); |
d6bbafa1 CW |
11709 | if (ret) |
11710 | goto cleanup_unpin; | |
11711 | ||
f06cc1b9 JH |
11712 | i915_gem_request_assign(&work->flip_queued_req, |
11713 | obj->last_write_req); | |
d6bbafa1 | 11714 | } else { |
6258fbe2 JH |
11715 | if (!request) { |
11716 | ret = i915_gem_request_alloc(ring, ring->default_context, &request); | |
11717 | if (ret) | |
11718 | goto cleanup_unpin; | |
11719 | } | |
11720 | ||
11721 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, | |
d6bbafa1 CW |
11722 | page_flip_flags); |
11723 | if (ret) | |
11724 | goto cleanup_unpin; | |
11725 | ||
6258fbe2 | 11726 | i915_gem_request_assign(&work->flip_queued_req, request); |
d6bbafa1 CW |
11727 | } |
11728 | ||
91af127f | 11729 | if (request) |
75289874 | 11730 | i915_add_request_no_flush(request); |
91af127f | 11731 | |
1e3feefd | 11732 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 11733 | work->enable_stall_check = true; |
4fa62c89 | 11734 | |
ab8d6675 | 11735 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a9ff8714 | 11736 | to_intel_plane(primary)->frontbuffer_bit); |
c80ac854 | 11737 | mutex_unlock(&dev->struct_mutex); |
a071fa00 | 11738 | |
d029bcad | 11739 | intel_fbc_deactivate(intel_crtc); |
a9ff8714 VS |
11740 | intel_frontbuffer_flip_prepare(dev, |
11741 | to_intel_plane(primary)->frontbuffer_bit); | |
6b95a207 | 11742 | |
e5510fac JB |
11743 | trace_i915_flip_request(intel_crtc->plane, obj); |
11744 | ||
6b95a207 | 11745 | return 0; |
96b099fd | 11746 | |
4fa62c89 | 11747 | cleanup_unpin: |
82bc3b2d | 11748 | intel_unpin_fb_obj(fb, crtc->primary->state); |
8c9f3aaf | 11749 | cleanup_pending: |
91af127f JH |
11750 | if (request) |
11751 | i915_gem_request_cancel(request); | |
b4a98e57 | 11752 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
11753 | mutex_unlock(&dev->struct_mutex); |
11754 | cleanup: | |
f4510a27 | 11755 | crtc->primary->fb = old_fb; |
afd65eb4 | 11756 | update_state_fb(crtc->primary); |
89ed88ba CW |
11757 | |
11758 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 11759 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 11760 | |
5e2d7afc | 11761 | spin_lock_irq(&dev->event_lock); |
96b099fd | 11762 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 11763 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 11764 | |
87b6b101 | 11765 | drm_crtc_vblank_put(crtc); |
7317c75e | 11766 | free_work: |
96b099fd CW |
11767 | kfree(work); |
11768 | ||
f900db47 | 11769 | if (ret == -EIO) { |
02e0efb5 ML |
11770 | struct drm_atomic_state *state; |
11771 | struct drm_plane_state *plane_state; | |
11772 | ||
f900db47 | 11773 | out_hang: |
02e0efb5 ML |
11774 | state = drm_atomic_state_alloc(dev); |
11775 | if (!state) | |
11776 | return -ENOMEM; | |
11777 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
11778 | ||
11779 | retry: | |
11780 | plane_state = drm_atomic_get_plane_state(state, primary); | |
11781 | ret = PTR_ERR_OR_ZERO(plane_state); | |
11782 | if (!ret) { | |
11783 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11784 | ||
11785 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
11786 | if (!ret) | |
11787 | ret = drm_atomic_commit(state); | |
11788 | } | |
11789 | ||
11790 | if (ret == -EDEADLK) { | |
11791 | drm_modeset_backoff(state->acquire_ctx); | |
11792 | drm_atomic_state_clear(state); | |
11793 | goto retry; | |
11794 | } | |
11795 | ||
11796 | if (ret) | |
11797 | drm_atomic_state_free(state); | |
11798 | ||
f0d3dad3 | 11799 | if (ret == 0 && event) { |
5e2d7afc | 11800 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 11801 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 11802 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 11803 | } |
f900db47 | 11804 | } |
96b099fd | 11805 | return ret; |
6b95a207 KH |
11806 | } |
11807 | ||
da20eabd ML |
11808 | |
11809 | /** | |
11810 | * intel_wm_need_update - Check whether watermarks need updating | |
11811 | * @plane: drm plane | |
11812 | * @state: new plane state | |
11813 | * | |
11814 | * Check current plane state versus the new one to determine whether | |
11815 | * watermarks need to be recalculated. | |
11816 | * | |
11817 | * Returns true or false. | |
11818 | */ | |
11819 | static bool intel_wm_need_update(struct drm_plane *plane, | |
11820 | struct drm_plane_state *state) | |
11821 | { | |
d21fbe87 MR |
11822 | struct intel_plane_state *new = to_intel_plane_state(state); |
11823 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
11824 | ||
11825 | /* Update watermarks on tiling or size changes. */ | |
92826fcd ML |
11826 | if (new->visible != cur->visible) |
11827 | return true; | |
11828 | ||
11829 | if (!cur->base.fb || !new->base.fb) | |
11830 | return false; | |
11831 | ||
11832 | if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] || | |
11833 | cur->base.rotation != new->base.rotation || | |
d21fbe87 MR |
11834 | drm_rect_width(&new->src) != drm_rect_width(&cur->src) || |
11835 | drm_rect_height(&new->src) != drm_rect_height(&cur->src) || | |
11836 | drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) || | |
11837 | drm_rect_height(&new->dst) != drm_rect_height(&cur->dst)) | |
2791a16c | 11838 | return true; |
7809e5ae | 11839 | |
2791a16c | 11840 | return false; |
7809e5ae MR |
11841 | } |
11842 | ||
d21fbe87 MR |
11843 | static bool needs_scaling(struct intel_plane_state *state) |
11844 | { | |
11845 | int src_w = drm_rect_width(&state->src) >> 16; | |
11846 | int src_h = drm_rect_height(&state->src) >> 16; | |
11847 | int dst_w = drm_rect_width(&state->dst); | |
11848 | int dst_h = drm_rect_height(&state->dst); | |
11849 | ||
11850 | return (src_w != dst_w || src_h != dst_h); | |
11851 | } | |
11852 | ||
da20eabd ML |
11853 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
11854 | struct drm_plane_state *plane_state) | |
11855 | { | |
ab1d3a0e | 11856 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
11857 | struct drm_crtc *crtc = crtc_state->crtc; |
11858 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11859 | struct drm_plane *plane = plane_state->plane; | |
11860 | struct drm_device *dev = crtc->dev; | |
11861 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11862 | struct intel_plane_state *old_plane_state = | |
11863 | to_intel_plane_state(plane->state); | |
11864 | int idx = intel_crtc->base.base.id, ret; | |
11865 | int i = drm_plane_index(plane); | |
11866 | bool mode_changed = needs_modeset(crtc_state); | |
11867 | bool was_crtc_enabled = crtc->state->active; | |
11868 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
11869 | bool turn_off, turn_on, visible, was_visible; |
11870 | struct drm_framebuffer *fb = plane_state->fb; | |
11871 | ||
11872 | if (crtc_state && INTEL_INFO(dev)->gen >= 9 && | |
11873 | plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11874 | ret = skl_update_scaler_plane( | |
11875 | to_intel_crtc_state(crtc_state), | |
11876 | to_intel_plane_state(plane_state)); | |
11877 | if (ret) | |
11878 | return ret; | |
11879 | } | |
11880 | ||
da20eabd ML |
11881 | was_visible = old_plane_state->visible; |
11882 | visible = to_intel_plane_state(plane_state)->visible; | |
11883 | ||
11884 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
11885 | was_visible = false; | |
11886 | ||
35c08f43 ML |
11887 | /* |
11888 | * Visibility is calculated as if the crtc was on, but | |
11889 | * after scaler setup everything depends on it being off | |
11890 | * when the crtc isn't active. | |
11891 | */ | |
11892 | if (!is_crtc_enabled) | |
11893 | to_intel_plane_state(plane_state)->visible = visible = false; | |
da20eabd ML |
11894 | |
11895 | if (!was_visible && !visible) | |
11896 | return 0; | |
11897 | ||
11898 | turn_off = was_visible && (!visible || mode_changed); | |
11899 | turn_on = visible && (!was_visible || mode_changed); | |
11900 | ||
11901 | DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx, | |
11902 | plane->base.id, fb ? fb->base.id : -1); | |
11903 | ||
11904 | DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n", | |
11905 | plane->base.id, was_visible, visible, | |
11906 | turn_off, turn_on, mode_changed); | |
11907 | ||
92826fcd ML |
11908 | if (turn_on || turn_off) { |
11909 | pipe_config->wm_changed = true; | |
11910 | ||
852eb00d VS |
11911 | /* must disable cxsr around plane enable/disable */ |
11912 | if (plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11913 | if (is_crtc_enabled) | |
11914 | intel_crtc->atomic.wait_vblank = true; | |
ab1d3a0e | 11915 | pipe_config->disable_cxsr = true; |
852eb00d VS |
11916 | } |
11917 | } else if (intel_wm_need_update(plane, plane_state)) { | |
92826fcd | 11918 | pipe_config->wm_changed = true; |
852eb00d | 11919 | } |
da20eabd | 11920 | |
8be6ca85 | 11921 | if (visible || was_visible) |
a9ff8714 VS |
11922 | intel_crtc->atomic.fb_bits |= |
11923 | to_intel_plane(plane)->frontbuffer_bit; | |
11924 | ||
da20eabd ML |
11925 | switch (plane->type) { |
11926 | case DRM_PLANE_TYPE_PRIMARY: | |
da20eabd ML |
11927 | intel_crtc->atomic.pre_disable_primary = turn_off; |
11928 | intel_crtc->atomic.post_enable_primary = turn_on; | |
11929 | ||
066cf55b RV |
11930 | if (turn_off) { |
11931 | /* | |
11932 | * FIXME: Actually if we will still have any other | |
11933 | * plane enabled on the pipe we could let IPS enabled | |
11934 | * still, but for now lets consider that when we make | |
11935 | * primary invisible by setting DSPCNTR to 0 on | |
11936 | * update_primary_plane function IPS needs to be | |
11937 | * disable. | |
11938 | */ | |
11939 | intel_crtc->atomic.disable_ips = true; | |
11940 | ||
da20eabd | 11941 | intel_crtc->atomic.disable_fbc = true; |
066cf55b | 11942 | } |
da20eabd ML |
11943 | |
11944 | /* | |
11945 | * FBC does not work on some platforms for rotated | |
11946 | * planes, so disable it when rotation is not 0 and | |
11947 | * update it when rotation is set back to 0. | |
11948 | * | |
11949 | * FIXME: This is redundant with the fbc update done in | |
11950 | * the primary plane enable function except that that | |
11951 | * one is done too late. We eventually need to unify | |
11952 | * this. | |
11953 | */ | |
11954 | ||
11955 | if (visible && | |
11956 | INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && | |
11957 | dev_priv->fbc.crtc == intel_crtc && | |
11958 | plane_state->rotation != BIT(DRM_ROTATE_0)) | |
11959 | intel_crtc->atomic.disable_fbc = true; | |
11960 | ||
11961 | /* | |
11962 | * BDW signals flip done immediately if the plane | |
11963 | * is disabled, even if the plane enable is already | |
11964 | * armed to occur at the next vblank :( | |
11965 | */ | |
11966 | if (turn_on && IS_BROADWELL(dev)) | |
11967 | intel_crtc->atomic.wait_vblank = true; | |
11968 | ||
11969 | intel_crtc->atomic.update_fbc |= visible || mode_changed; | |
11970 | break; | |
11971 | case DRM_PLANE_TYPE_CURSOR: | |
da20eabd ML |
11972 | break; |
11973 | case DRM_PLANE_TYPE_OVERLAY: | |
d21fbe87 MR |
11974 | /* |
11975 | * WaCxSRDisabledForSpriteScaling:ivb | |
11976 | * | |
11977 | * cstate->update_wm was already set above, so this flag will | |
11978 | * take effect when we commit and program watermarks. | |
11979 | */ | |
11980 | if (IS_IVYBRIDGE(dev) && | |
11981 | needs_scaling(to_intel_plane_state(plane_state)) && | |
11982 | !needs_scaling(old_plane_state)) { | |
11983 | to_intel_crtc_state(crtc_state)->disable_lp_wm = true; | |
11984 | } else if (turn_off && !mode_changed) { | |
da20eabd ML |
11985 | intel_crtc->atomic.wait_vblank = true; |
11986 | intel_crtc->atomic.update_sprite_watermarks |= | |
11987 | 1 << i; | |
11988 | } | |
d21fbe87 MR |
11989 | |
11990 | break; | |
da20eabd ML |
11991 | } |
11992 | return 0; | |
11993 | } | |
11994 | ||
6d3a1ce7 ML |
11995 | static bool encoders_cloneable(const struct intel_encoder *a, |
11996 | const struct intel_encoder *b) | |
11997 | { | |
11998 | /* masks could be asymmetric, so check both ways */ | |
11999 | return a == b || (a->cloneable & (1 << b->type) && | |
12000 | b->cloneable & (1 << a->type)); | |
12001 | } | |
12002 | ||
12003 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
12004 | struct intel_crtc *crtc, | |
12005 | struct intel_encoder *encoder) | |
12006 | { | |
12007 | struct intel_encoder *source_encoder; | |
12008 | struct drm_connector *connector; | |
12009 | struct drm_connector_state *connector_state; | |
12010 | int i; | |
12011 | ||
12012 | for_each_connector_in_state(state, connector, connector_state, i) { | |
12013 | if (connector_state->crtc != &crtc->base) | |
12014 | continue; | |
12015 | ||
12016 | source_encoder = | |
12017 | to_intel_encoder(connector_state->best_encoder); | |
12018 | if (!encoders_cloneable(encoder, source_encoder)) | |
12019 | return false; | |
12020 | } | |
12021 | ||
12022 | return true; | |
12023 | } | |
12024 | ||
12025 | static bool check_encoder_cloning(struct drm_atomic_state *state, | |
12026 | struct intel_crtc *crtc) | |
12027 | { | |
12028 | struct intel_encoder *encoder; | |
12029 | struct drm_connector *connector; | |
12030 | struct drm_connector_state *connector_state; | |
12031 | int i; | |
12032 | ||
12033 | for_each_connector_in_state(state, connector, connector_state, i) { | |
12034 | if (connector_state->crtc != &crtc->base) | |
12035 | continue; | |
12036 | ||
12037 | encoder = to_intel_encoder(connector_state->best_encoder); | |
12038 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
12039 | return false; | |
12040 | } | |
12041 | ||
12042 | return true; | |
12043 | } | |
12044 | ||
12045 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, | |
12046 | struct drm_crtc_state *crtc_state) | |
12047 | { | |
cf5a15be | 12048 | struct drm_device *dev = crtc->dev; |
ad421372 | 12049 | struct drm_i915_private *dev_priv = dev->dev_private; |
6d3a1ce7 | 12050 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
12051 | struct intel_crtc_state *pipe_config = |
12052 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 12053 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 12054 | int ret; |
6d3a1ce7 ML |
12055 | bool mode_changed = needs_modeset(crtc_state); |
12056 | ||
12057 | if (mode_changed && !check_encoder_cloning(state, intel_crtc)) { | |
12058 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
12059 | return -EINVAL; | |
12060 | } | |
12061 | ||
852eb00d | 12062 | if (mode_changed && !crtc_state->active) |
92826fcd | 12063 | pipe_config->wm_changed = true; |
eddfcbcd | 12064 | |
ad421372 ML |
12065 | if (mode_changed && crtc_state->enable && |
12066 | dev_priv->display.crtc_compute_clock && | |
12067 | !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) { | |
12068 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, | |
12069 | pipe_config); | |
12070 | if (ret) | |
12071 | return ret; | |
12072 | } | |
12073 | ||
e435d6e5 | 12074 | ret = 0; |
86c8bbbe MR |
12075 | if (dev_priv->display.compute_pipe_wm) { |
12076 | ret = dev_priv->display.compute_pipe_wm(intel_crtc, state); | |
12077 | if (ret) | |
12078 | return ret; | |
12079 | } | |
12080 | ||
e435d6e5 ML |
12081 | if (INTEL_INFO(dev)->gen >= 9) { |
12082 | if (mode_changed) | |
12083 | ret = skl_update_scaler_crtc(pipe_config); | |
12084 | ||
12085 | if (!ret) | |
12086 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
12087 | pipe_config); | |
12088 | } | |
12089 | ||
12090 | return ret; | |
6d3a1ce7 ML |
12091 | } |
12092 | ||
65b38e0d | 12093 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
12094 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
12095 | .load_lut = intel_crtc_load_lut, | |
ea2c67bb MR |
12096 | .atomic_begin = intel_begin_crtc_commit, |
12097 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 12098 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
12099 | }; |
12100 | ||
d29b2f9d ACO |
12101 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
12102 | { | |
12103 | struct intel_connector *connector; | |
12104 | ||
12105 | for_each_intel_connector(dev, connector) { | |
12106 | if (connector->base.encoder) { | |
12107 | connector->base.state->best_encoder = | |
12108 | connector->base.encoder; | |
12109 | connector->base.state->crtc = | |
12110 | connector->base.encoder->crtc; | |
12111 | } else { | |
12112 | connector->base.state->best_encoder = NULL; | |
12113 | connector->base.state->crtc = NULL; | |
12114 | } | |
12115 | } | |
12116 | } | |
12117 | ||
050f7aeb | 12118 | static void |
eba905b2 | 12119 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 12120 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
12121 | { |
12122 | int bpp = pipe_config->pipe_bpp; | |
12123 | ||
12124 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
12125 | connector->base.base.id, | |
c23cc417 | 12126 | connector->base.name); |
050f7aeb DV |
12127 | |
12128 | /* Don't use an invalid EDID bpc value */ | |
12129 | if (connector->base.display_info.bpc && | |
12130 | connector->base.display_info.bpc * 3 < bpp) { | |
12131 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
12132 | bpp, connector->base.display_info.bpc*3); | |
12133 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
12134 | } | |
12135 | ||
12136 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
12137 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
12138 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
12139 | bpp); | |
12140 | pipe_config->pipe_bpp = 24; | |
12141 | } | |
12142 | } | |
12143 | ||
4e53c2e0 | 12144 | static int |
050f7aeb | 12145 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 12146 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 12147 | { |
050f7aeb | 12148 | struct drm_device *dev = crtc->base.dev; |
1486017f | 12149 | struct drm_atomic_state *state; |
da3ced29 ACO |
12150 | struct drm_connector *connector; |
12151 | struct drm_connector_state *connector_state; | |
1486017f | 12152 | int bpp, i; |
4e53c2e0 | 12153 | |
666a4537 | 12154 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) |
4e53c2e0 | 12155 | bpp = 10*3; |
d328c9d7 DV |
12156 | else if (INTEL_INFO(dev)->gen >= 5) |
12157 | bpp = 12*3; | |
12158 | else | |
12159 | bpp = 8*3; | |
12160 | ||
4e53c2e0 | 12161 | |
4e53c2e0 DV |
12162 | pipe_config->pipe_bpp = bpp; |
12163 | ||
1486017f ACO |
12164 | state = pipe_config->base.state; |
12165 | ||
4e53c2e0 | 12166 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
12167 | for_each_connector_in_state(state, connector, connector_state, i) { |
12168 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
12169 | continue; |
12170 | ||
da3ced29 ACO |
12171 | connected_sink_compute_bpp(to_intel_connector(connector), |
12172 | pipe_config); | |
4e53c2e0 DV |
12173 | } |
12174 | ||
12175 | return bpp; | |
12176 | } | |
12177 | ||
644db711 DV |
12178 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
12179 | { | |
12180 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
12181 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 12182 | mode->crtc_clock, |
644db711 DV |
12183 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
12184 | mode->crtc_hsync_end, mode->crtc_htotal, | |
12185 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
12186 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
12187 | } | |
12188 | ||
c0b03411 | 12189 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 12190 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
12191 | const char *context) |
12192 | { | |
6a60cd87 CK |
12193 | struct drm_device *dev = crtc->base.dev; |
12194 | struct drm_plane *plane; | |
12195 | struct intel_plane *intel_plane; | |
12196 | struct intel_plane_state *state; | |
12197 | struct drm_framebuffer *fb; | |
12198 | ||
12199 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
12200 | context, pipe_config, pipe_name(crtc->pipe)); | |
c0b03411 DV |
12201 | |
12202 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
12203 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
12204 | pipe_config->pipe_bpp, pipe_config->dither); | |
12205 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
12206 | pipe_config->has_pch_encoder, | |
12207 | pipe_config->fdi_lanes, | |
12208 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
12209 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
12210 | pipe_config->fdi_m_n.tu); | |
90a6b7b0 | 12211 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
eb14cb74 | 12212 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12213 | pipe_config->lane_count, |
eb14cb74 VS |
12214 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
12215 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
12216 | pipe_config->dp_m_n.tu); | |
b95af8be | 12217 | |
90a6b7b0 | 12218 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
b95af8be | 12219 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12220 | pipe_config->lane_count, |
b95af8be VK |
12221 | pipe_config->dp_m2_n2.gmch_m, |
12222 | pipe_config->dp_m2_n2.gmch_n, | |
12223 | pipe_config->dp_m2_n2.link_m, | |
12224 | pipe_config->dp_m2_n2.link_n, | |
12225 | pipe_config->dp_m2_n2.tu); | |
12226 | ||
55072d19 DV |
12227 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
12228 | pipe_config->has_audio, | |
12229 | pipe_config->has_infoframe); | |
12230 | ||
c0b03411 | 12231 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 12232 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 12233 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
12234 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
12235 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 12236 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
12237 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
12238 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
12239 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
12240 | crtc->num_scalers, | |
12241 | pipe_config->scaler_state.scaler_users, | |
12242 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
12243 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
12244 | pipe_config->gmch_pfit.control, | |
12245 | pipe_config->gmch_pfit.pgm_ratios, | |
12246 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 12247 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 12248 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
12249 | pipe_config->pch_pfit.size, |
12250 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 12251 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 12252 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 12253 | |
415ff0f6 | 12254 | if (IS_BROXTON(dev)) { |
05712c15 | 12255 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 12256 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 12257 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 TU |
12258 | pipe_config->ddi_pll_sel, |
12259 | pipe_config->dpll_hw_state.ebb0, | |
05712c15 | 12260 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
12261 | pipe_config->dpll_hw_state.pll0, |
12262 | pipe_config->dpll_hw_state.pll1, | |
12263 | pipe_config->dpll_hw_state.pll2, | |
12264 | pipe_config->dpll_hw_state.pll3, | |
12265 | pipe_config->dpll_hw_state.pll6, | |
12266 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 12267 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 12268 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 | 12269 | pipe_config->dpll_hw_state.pcsdw12); |
ef11bdb3 | 12270 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
415ff0f6 TU |
12271 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " |
12272 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
12273 | pipe_config->ddi_pll_sel, | |
12274 | pipe_config->dpll_hw_state.ctrl1, | |
12275 | pipe_config->dpll_hw_state.cfgcr1, | |
12276 | pipe_config->dpll_hw_state.cfgcr2); | |
12277 | } else if (HAS_DDI(dev)) { | |
00490c22 | 12278 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
415ff0f6 | 12279 | pipe_config->ddi_pll_sel, |
00490c22 ML |
12280 | pipe_config->dpll_hw_state.wrpll, |
12281 | pipe_config->dpll_hw_state.spll); | |
415ff0f6 TU |
12282 | } else { |
12283 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12284 | "fp0: 0x%x, fp1: 0x%x\n", | |
12285 | pipe_config->dpll_hw_state.dpll, | |
12286 | pipe_config->dpll_hw_state.dpll_md, | |
12287 | pipe_config->dpll_hw_state.fp0, | |
12288 | pipe_config->dpll_hw_state.fp1); | |
12289 | } | |
12290 | ||
6a60cd87 CK |
12291 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12292 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
12293 | intel_plane = to_intel_plane(plane); | |
12294 | if (intel_plane->pipe != crtc->pipe) | |
12295 | continue; | |
12296 | ||
12297 | state = to_intel_plane_state(plane->state); | |
12298 | fb = state->base.fb; | |
12299 | if (!fb) { | |
12300 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
12301 | "disabled, scaler_id = %d\n", | |
12302 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12303 | plane->base.id, intel_plane->pipe, | |
12304 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
12305 | drm_plane_index(plane), state->scaler_id); | |
12306 | continue; | |
12307 | } | |
12308 | ||
12309 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
12310 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12311 | plane->base.id, intel_plane->pipe, | |
12312 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
12313 | drm_plane_index(plane)); | |
12314 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
12315 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
12316 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
12317 | state->scaler_id, | |
12318 | state->src.x1 >> 16, state->src.y1 >> 16, | |
12319 | drm_rect_width(&state->src) >> 16, | |
12320 | drm_rect_height(&state->src) >> 16, | |
12321 | state->dst.x1, state->dst.y1, | |
12322 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
12323 | } | |
c0b03411 DV |
12324 | } |
12325 | ||
5448a00d | 12326 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12327 | { |
5448a00d | 12328 | struct drm_device *dev = state->dev; |
da3ced29 | 12329 | struct drm_connector *connector; |
00f0b378 VS |
12330 | unsigned int used_ports = 0; |
12331 | ||
12332 | /* | |
12333 | * Walk the connector list instead of the encoder | |
12334 | * list to detect the problem on ddi platforms | |
12335 | * where there's just one encoder per digital port. | |
12336 | */ | |
0bff4858 VS |
12337 | drm_for_each_connector(connector, dev) { |
12338 | struct drm_connector_state *connector_state; | |
12339 | struct intel_encoder *encoder; | |
12340 | ||
12341 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
12342 | if (!connector_state) | |
12343 | connector_state = connector->state; | |
12344 | ||
5448a00d | 12345 | if (!connector_state->best_encoder) |
00f0b378 VS |
12346 | continue; |
12347 | ||
5448a00d ACO |
12348 | encoder = to_intel_encoder(connector_state->best_encoder); |
12349 | ||
12350 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12351 | |
12352 | switch (encoder->type) { | |
12353 | unsigned int port_mask; | |
12354 | case INTEL_OUTPUT_UNKNOWN: | |
12355 | if (WARN_ON(!HAS_DDI(dev))) | |
12356 | break; | |
12357 | case INTEL_OUTPUT_DISPLAYPORT: | |
12358 | case INTEL_OUTPUT_HDMI: | |
12359 | case INTEL_OUTPUT_EDP: | |
12360 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12361 | ||
12362 | /* the same port mustn't appear more than once */ | |
12363 | if (used_ports & port_mask) | |
12364 | return false; | |
12365 | ||
12366 | used_ports |= port_mask; | |
12367 | default: | |
12368 | break; | |
12369 | } | |
12370 | } | |
12371 | ||
12372 | return true; | |
12373 | } | |
12374 | ||
83a57153 ACO |
12375 | static void |
12376 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12377 | { | |
12378 | struct drm_crtc_state tmp_state; | |
663a3640 | 12379 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 ACO |
12380 | struct intel_dpll_hw_state dpll_hw_state; |
12381 | enum intel_dpll_id shared_dpll; | |
8504c74c | 12382 | uint32_t ddi_pll_sel; |
c4e2d043 | 12383 | bool force_thru; |
83a57153 | 12384 | |
7546a384 ACO |
12385 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12386 | * kzalloc'd. Code that depends on any field being zero should be | |
12387 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12388 | * only fields that are know to not cause problems are preserved. */ | |
12389 | ||
83a57153 | 12390 | tmp_state = crtc_state->base; |
663a3640 | 12391 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12392 | shared_dpll = crtc_state->shared_dpll; |
12393 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 12394 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
c4e2d043 | 12395 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 12396 | |
83a57153 | 12397 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12398 | |
83a57153 | 12399 | crtc_state->base = tmp_state; |
663a3640 | 12400 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12401 | crtc_state->shared_dpll = shared_dpll; |
12402 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 12403 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
c4e2d043 | 12404 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
12405 | } |
12406 | ||
548ee15b | 12407 | static int |
b8cecdf5 | 12408 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12409 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12410 | { |
b359283a | 12411 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12412 | struct intel_encoder *encoder; |
da3ced29 | 12413 | struct drm_connector *connector; |
0b901879 | 12414 | struct drm_connector_state *connector_state; |
d328c9d7 | 12415 | int base_bpp, ret = -EINVAL; |
0b901879 | 12416 | int i; |
e29c22c0 | 12417 | bool retry = true; |
ee7b9f93 | 12418 | |
83a57153 | 12419 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12420 | |
e143a21c DV |
12421 | pipe_config->cpu_transcoder = |
12422 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12423 | |
2960bc9c ID |
12424 | /* |
12425 | * Sanitize sync polarity flags based on requested ones. If neither | |
12426 | * positive or negative polarity is requested, treat this as meaning | |
12427 | * negative polarity. | |
12428 | */ | |
2d112de7 | 12429 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12430 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12431 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 12432 | |
2d112de7 | 12433 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12434 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 12435 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 12436 | |
d328c9d7 DV |
12437 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
12438 | pipe_config); | |
12439 | if (base_bpp < 0) | |
4e53c2e0 DV |
12440 | goto fail; |
12441 | ||
e41a56be VS |
12442 | /* |
12443 | * Determine the real pipe dimensions. Note that stereo modes can | |
12444 | * increase the actual pipe size due to the frame doubling and | |
12445 | * insertion of additional space for blanks between the frame. This | |
12446 | * is stored in the crtc timings. We use the requested mode to do this | |
12447 | * computation to clearly distinguish it from the adjusted mode, which | |
12448 | * can be changed by the connectors in the below retry loop. | |
12449 | */ | |
2d112de7 | 12450 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
12451 | &pipe_config->pipe_src_w, |
12452 | &pipe_config->pipe_src_h); | |
e41a56be | 12453 | |
e29c22c0 | 12454 | encoder_retry: |
ef1b460d | 12455 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 12456 | pipe_config->port_clock = 0; |
ef1b460d | 12457 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 12458 | |
135c81b8 | 12459 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
12460 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
12461 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 12462 | |
7758a113 DV |
12463 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
12464 | * adjust it according to limitations or connector properties, and also | |
12465 | * a chance to reject the mode entirely. | |
47f1c6c9 | 12466 | */ |
da3ced29 | 12467 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 12468 | if (connector_state->crtc != crtc) |
7758a113 | 12469 | continue; |
7ae89233 | 12470 | |
0b901879 ACO |
12471 | encoder = to_intel_encoder(connector_state->best_encoder); |
12472 | ||
efea6e8e DV |
12473 | if (!(encoder->compute_config(encoder, pipe_config))) { |
12474 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
12475 | goto fail; |
12476 | } | |
ee7b9f93 | 12477 | } |
47f1c6c9 | 12478 | |
ff9a6750 DV |
12479 | /* Set default port clock if not overwritten by the encoder. Needs to be |
12480 | * done afterwards in case the encoder adjusts the mode. */ | |
12481 | if (!pipe_config->port_clock) | |
2d112de7 | 12482 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 12483 | * pipe_config->pixel_multiplier; |
ff9a6750 | 12484 | |
a43f6e0f | 12485 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 12486 | if (ret < 0) { |
7758a113 DV |
12487 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
12488 | goto fail; | |
ee7b9f93 | 12489 | } |
e29c22c0 DV |
12490 | |
12491 | if (ret == RETRY) { | |
12492 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
12493 | ret = -EINVAL; | |
12494 | goto fail; | |
12495 | } | |
12496 | ||
12497 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
12498 | retry = false; | |
12499 | goto encoder_retry; | |
12500 | } | |
12501 | ||
e8fa4270 DV |
12502 | /* Dithering seems to not pass-through bits correctly when it should, so |
12503 | * only enable it on 6bpc panels. */ | |
12504 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 12505 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 12506 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 12507 | |
7758a113 | 12508 | fail: |
548ee15b | 12509 | return ret; |
ee7b9f93 | 12510 | } |
47f1c6c9 | 12511 | |
ea9d758d | 12512 | static void |
4740b0f2 | 12513 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 12514 | { |
0a9ab303 ACO |
12515 | struct drm_crtc *crtc; |
12516 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 12517 | int i; |
ea9d758d | 12518 | |
7668851f | 12519 | /* Double check state. */ |
8a75d157 | 12520 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 12521 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
12522 | |
12523 | /* Update hwmode for vblank functions */ | |
12524 | if (crtc->state->active) | |
12525 | crtc->hwmode = crtc->state->adjusted_mode; | |
12526 | else | |
12527 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
12528 | |
12529 | /* | |
12530 | * Update legacy state to satisfy fbc code. This can | |
12531 | * be removed when fbc uses the atomic state. | |
12532 | */ | |
12533 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12534 | struct drm_plane_state *plane_state = crtc->primary->state; | |
12535 | ||
12536 | crtc->primary->fb = plane_state->fb; | |
12537 | crtc->x = plane_state->src_x >> 16; | |
12538 | crtc->y = plane_state->src_y >> 16; | |
12539 | } | |
ea9d758d | 12540 | } |
ea9d758d DV |
12541 | } |
12542 | ||
3bd26263 | 12543 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 12544 | { |
3bd26263 | 12545 | int diff; |
f1f644dc JB |
12546 | |
12547 | if (clock1 == clock2) | |
12548 | return true; | |
12549 | ||
12550 | if (!clock1 || !clock2) | |
12551 | return false; | |
12552 | ||
12553 | diff = abs(clock1 - clock2); | |
12554 | ||
12555 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
12556 | return true; | |
12557 | ||
12558 | return false; | |
12559 | } | |
12560 | ||
25c5b266 DV |
12561 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
12562 | list_for_each_entry((intel_crtc), \ | |
12563 | &(dev)->mode_config.crtc_list, \ | |
12564 | base.head) \ | |
95150bdf | 12565 | for_each_if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 12566 | |
cfb23ed6 ML |
12567 | static bool |
12568 | intel_compare_m_n(unsigned int m, unsigned int n, | |
12569 | unsigned int m2, unsigned int n2, | |
12570 | bool exact) | |
12571 | { | |
12572 | if (m == m2 && n == n2) | |
12573 | return true; | |
12574 | ||
12575 | if (exact || !m || !n || !m2 || !n2) | |
12576 | return false; | |
12577 | ||
12578 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
12579 | ||
31d10b57 ML |
12580 | if (n > n2) { |
12581 | while (n > n2) { | |
cfb23ed6 ML |
12582 | m2 <<= 1; |
12583 | n2 <<= 1; | |
12584 | } | |
31d10b57 ML |
12585 | } else if (n < n2) { |
12586 | while (n < n2) { | |
cfb23ed6 ML |
12587 | m <<= 1; |
12588 | n <<= 1; | |
12589 | } | |
12590 | } | |
12591 | ||
31d10b57 ML |
12592 | if (n != n2) |
12593 | return false; | |
12594 | ||
12595 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
12596 | } |
12597 | ||
12598 | static bool | |
12599 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
12600 | struct intel_link_m_n *m2_n2, | |
12601 | bool adjust) | |
12602 | { | |
12603 | if (m_n->tu == m2_n2->tu && | |
12604 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
12605 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
12606 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
12607 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
12608 | if (adjust) | |
12609 | *m2_n2 = *m_n; | |
12610 | ||
12611 | return true; | |
12612 | } | |
12613 | ||
12614 | return false; | |
12615 | } | |
12616 | ||
0e8ffe1b | 12617 | static bool |
2fa2fe9a | 12618 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b | 12619 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
12620 | struct intel_crtc_state *pipe_config, |
12621 | bool adjust) | |
0e8ffe1b | 12622 | { |
cfb23ed6 ML |
12623 | bool ret = true; |
12624 | ||
12625 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
12626 | do { \ | |
12627 | if (!adjust) \ | |
12628 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
12629 | else \ | |
12630 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
12631 | } while (0) | |
12632 | ||
66e985c0 DV |
12633 | #define PIPE_CONF_CHECK_X(name) \ |
12634 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12635 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
12636 | "(expected 0x%08x, found 0x%08x)\n", \ |
12637 | current_config->name, \ | |
12638 | pipe_config->name); \ | |
cfb23ed6 | 12639 | ret = false; \ |
66e985c0 DV |
12640 | } |
12641 | ||
08a24034 DV |
12642 | #define PIPE_CONF_CHECK_I(name) \ |
12643 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12644 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
12645 | "(expected %i, found %i)\n", \ |
12646 | current_config->name, \ | |
12647 | pipe_config->name); \ | |
cfb23ed6 ML |
12648 | ret = false; \ |
12649 | } | |
12650 | ||
12651 | #define PIPE_CONF_CHECK_M_N(name) \ | |
12652 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12653 | &pipe_config->name,\ | |
12654 | adjust)) { \ | |
12655 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12656 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12657 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12658 | current_config->name.tu, \ | |
12659 | current_config->name.gmch_m, \ | |
12660 | current_config->name.gmch_n, \ | |
12661 | current_config->name.link_m, \ | |
12662 | current_config->name.link_n, \ | |
12663 | pipe_config->name.tu, \ | |
12664 | pipe_config->name.gmch_m, \ | |
12665 | pipe_config->name.gmch_n, \ | |
12666 | pipe_config->name.link_m, \ | |
12667 | pipe_config->name.link_n); \ | |
12668 | ret = false; \ | |
12669 | } | |
12670 | ||
12671 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ | |
12672 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12673 | &pipe_config->name, adjust) && \ | |
12674 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
12675 | &pipe_config->name, adjust)) { \ | |
12676 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12677 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12678 | "or tu %i gmch %i/%i link %i/%i, " \ | |
12679 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12680 | current_config->name.tu, \ | |
12681 | current_config->name.gmch_m, \ | |
12682 | current_config->name.gmch_n, \ | |
12683 | current_config->name.link_m, \ | |
12684 | current_config->name.link_n, \ | |
12685 | current_config->alt_name.tu, \ | |
12686 | current_config->alt_name.gmch_m, \ | |
12687 | current_config->alt_name.gmch_n, \ | |
12688 | current_config->alt_name.link_m, \ | |
12689 | current_config->alt_name.link_n, \ | |
12690 | pipe_config->name.tu, \ | |
12691 | pipe_config->name.gmch_m, \ | |
12692 | pipe_config->name.gmch_n, \ | |
12693 | pipe_config->name.link_m, \ | |
12694 | pipe_config->name.link_n); \ | |
12695 | ret = false; \ | |
88adfff1 DV |
12696 | } |
12697 | ||
b95af8be VK |
12698 | /* This is required for BDW+ where there is only one set of registers for |
12699 | * switching between high and low RR. | |
12700 | * This macro can be used whenever a comparison has to be made between one | |
12701 | * hw state and multiple sw state variables. | |
12702 | */ | |
12703 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
12704 | if ((current_config->name != pipe_config->name) && \ | |
12705 | (current_config->alt_name != pipe_config->name)) { \ | |
cfb23ed6 | 12706 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
b95af8be VK |
12707 | "(expected %i or %i, found %i)\n", \ |
12708 | current_config->name, \ | |
12709 | current_config->alt_name, \ | |
12710 | pipe_config->name); \ | |
cfb23ed6 | 12711 | ret = false; \ |
b95af8be VK |
12712 | } |
12713 | ||
1bd1bd80 DV |
12714 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
12715 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 12716 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
12717 | "(expected %i, found %i)\n", \ |
12718 | current_config->name & (mask), \ | |
12719 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 12720 | ret = false; \ |
1bd1bd80 DV |
12721 | } |
12722 | ||
5e550656 VS |
12723 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
12724 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 12725 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
12726 | "(expected %i, found %i)\n", \ |
12727 | current_config->name, \ | |
12728 | pipe_config->name); \ | |
cfb23ed6 | 12729 | ret = false; \ |
5e550656 VS |
12730 | } |
12731 | ||
bb760063 DV |
12732 | #define PIPE_CONF_QUIRK(quirk) \ |
12733 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
12734 | ||
eccb140b DV |
12735 | PIPE_CONF_CHECK_I(cpu_transcoder); |
12736 | ||
08a24034 DV |
12737 | PIPE_CONF_CHECK_I(has_pch_encoder); |
12738 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 12739 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 12740 | |
eb14cb74 | 12741 | PIPE_CONF_CHECK_I(has_dp_encoder); |
90a6b7b0 | 12742 | PIPE_CONF_CHECK_I(lane_count); |
b95af8be VK |
12743 | |
12744 | if (INTEL_INFO(dev)->gen < 8) { | |
cfb23ed6 ML |
12745 | PIPE_CONF_CHECK_M_N(dp_m_n); |
12746 | ||
cfb23ed6 ML |
12747 | if (current_config->has_drrs) |
12748 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
12749 | } else | |
12750 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 12751 | |
a65347ba JN |
12752 | PIPE_CONF_CHECK_I(has_dsi_encoder); |
12753 | ||
2d112de7 ACO |
12754 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12755 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
12756 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
12757 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
12758 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
12759 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 12760 | |
2d112de7 ACO |
12761 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
12762 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
12763 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
12764 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
12765 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
12766 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 12767 | |
c93f54cf | 12768 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 12769 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 | 12770 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
666a4537 | 12771 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
b5a9fa09 | 12772 | PIPE_CONF_CHECK_I(limited_color_range); |
e43823ec | 12773 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 12774 | |
9ed109a7 DV |
12775 | PIPE_CONF_CHECK_I(has_audio); |
12776 | ||
2d112de7 | 12777 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
12778 | DRM_MODE_FLAG_INTERLACE); |
12779 | ||
bb760063 | 12780 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 12781 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12782 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 12783 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12784 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 12785 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12786 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 12787 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
12788 | DRM_MODE_FLAG_NVSYNC); |
12789 | } | |
045ac3b5 | 12790 | |
333b8ca8 | 12791 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a DV |
12792 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
12793 | if (INTEL_INFO(dev)->gen < 4) | |
12794 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
333b8ca8 | 12795 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 12796 | |
bfd16b2a ML |
12797 | if (!adjust) { |
12798 | PIPE_CONF_CHECK_I(pipe_src_w); | |
12799 | PIPE_CONF_CHECK_I(pipe_src_h); | |
12800 | ||
12801 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
12802 | if (current_config->pch_pfit.enabled) { | |
12803 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
12804 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
12805 | } | |
2fa2fe9a | 12806 | |
7aefe2b5 ML |
12807 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
12808 | } | |
a1b2278e | 12809 | |
e59150dc JB |
12810 | /* BDW+ don't expose a synchronous way to read the state */ |
12811 | if (IS_HASWELL(dev)) | |
12812 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 12813 | |
282740f7 VS |
12814 | PIPE_CONF_CHECK_I(double_wide); |
12815 | ||
26804afd DV |
12816 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
12817 | ||
c0d43d62 | 12818 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 12819 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 12820 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
12821 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
12822 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 12823 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 12824 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
12825 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
12826 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
12827 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 12828 | |
42571aef VS |
12829 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
12830 | PIPE_CONF_CHECK_I(pipe_bpp); | |
12831 | ||
2d112de7 | 12832 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 12833 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 12834 | |
66e985c0 | 12835 | #undef PIPE_CONF_CHECK_X |
08a24034 | 12836 | #undef PIPE_CONF_CHECK_I |
b95af8be | 12837 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 12838 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 12839 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 12840 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 12841 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 12842 | |
cfb23ed6 | 12843 | return ret; |
0e8ffe1b DV |
12844 | } |
12845 | ||
08db6652 DL |
12846 | static void check_wm_state(struct drm_device *dev) |
12847 | { | |
12848 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12849 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
12850 | struct intel_crtc *intel_crtc; | |
12851 | int plane; | |
12852 | ||
12853 | if (INTEL_INFO(dev)->gen < 9) | |
12854 | return; | |
12855 | ||
12856 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
12857 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
12858 | ||
12859 | for_each_intel_crtc(dev, intel_crtc) { | |
12860 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
12861 | const enum pipe pipe = intel_crtc->pipe; | |
12862 | ||
12863 | if (!intel_crtc->active) | |
12864 | continue; | |
12865 | ||
12866 | /* planes */ | |
dd740780 | 12867 | for_each_plane(dev_priv, pipe, plane) { |
08db6652 DL |
12868 | hw_entry = &hw_ddb.plane[pipe][plane]; |
12869 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
12870 | ||
12871 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12872 | continue; | |
12873 | ||
12874 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
12875 | "(expected (%u,%u), found (%u,%u))\n", | |
12876 | pipe_name(pipe), plane + 1, | |
12877 | sw_entry->start, sw_entry->end, | |
12878 | hw_entry->start, hw_entry->end); | |
12879 | } | |
12880 | ||
12881 | /* cursor */ | |
4969d33e MR |
12882 | hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; |
12883 | sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
08db6652 DL |
12884 | |
12885 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12886 | continue; | |
12887 | ||
12888 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
12889 | "(expected (%u,%u), found (%u,%u))\n", | |
12890 | pipe_name(pipe), | |
12891 | sw_entry->start, sw_entry->end, | |
12892 | hw_entry->start, hw_entry->end); | |
12893 | } | |
12894 | } | |
12895 | ||
91d1b4bd | 12896 | static void |
35dd3c64 ML |
12897 | check_connector_state(struct drm_device *dev, |
12898 | struct drm_atomic_state *old_state) | |
8af6cf88 | 12899 | { |
35dd3c64 ML |
12900 | struct drm_connector_state *old_conn_state; |
12901 | struct drm_connector *connector; | |
12902 | int i; | |
8af6cf88 | 12903 | |
35dd3c64 ML |
12904 | for_each_connector_in_state(old_state, connector, old_conn_state, i) { |
12905 | struct drm_encoder *encoder = connector->encoder; | |
12906 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 12907 | |
8af6cf88 DV |
12908 | /* This also checks the encoder/connector hw state with the |
12909 | * ->get_hw_state callbacks. */ | |
35dd3c64 | 12910 | intel_connector_check_state(to_intel_connector(connector)); |
8af6cf88 | 12911 | |
ad3c558f | 12912 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 12913 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 12914 | } |
91d1b4bd DV |
12915 | } |
12916 | ||
12917 | static void | |
12918 | check_encoder_state(struct drm_device *dev) | |
12919 | { | |
12920 | struct intel_encoder *encoder; | |
12921 | struct intel_connector *connector; | |
8af6cf88 | 12922 | |
b2784e15 | 12923 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 12924 | bool enabled = false; |
4d20cd86 | 12925 | enum pipe pipe; |
8af6cf88 DV |
12926 | |
12927 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
12928 | encoder->base.base.id, | |
8e329a03 | 12929 | encoder->base.name); |
8af6cf88 | 12930 | |
3a3371ff | 12931 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 12932 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
12933 | continue; |
12934 | enabled = true; | |
ad3c558f ML |
12935 | |
12936 | I915_STATE_WARN(connector->base.state->crtc != | |
12937 | encoder->base.crtc, | |
12938 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 12939 | } |
0e32b39c | 12940 | |
e2c719b7 | 12941 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
12942 | "encoder's enabled state mismatch " |
12943 | "(expected %i, found %i)\n", | |
12944 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
12945 | |
12946 | if (!encoder->base.crtc) { | |
4d20cd86 | 12947 | bool active; |
7c60d198 | 12948 | |
4d20cd86 ML |
12949 | active = encoder->get_hw_state(encoder, &pipe); |
12950 | I915_STATE_WARN(active, | |
12951 | "encoder detached but still enabled on pipe %c.\n", | |
12952 | pipe_name(pipe)); | |
7c60d198 | 12953 | } |
8af6cf88 | 12954 | } |
91d1b4bd DV |
12955 | } |
12956 | ||
12957 | static void | |
4d20cd86 | 12958 | check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state) |
91d1b4bd | 12959 | { |
fbee40df | 12960 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd | 12961 | struct intel_encoder *encoder; |
4d20cd86 ML |
12962 | struct drm_crtc_state *old_crtc_state; |
12963 | struct drm_crtc *crtc; | |
12964 | int i; | |
8af6cf88 | 12965 | |
4d20cd86 ML |
12966 | for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) { |
12967 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12968 | struct intel_crtc_state *pipe_config, *sw_config; | |
7b89b8de | 12969 | bool active; |
8af6cf88 | 12970 | |
bfd16b2a ML |
12971 | if (!needs_modeset(crtc->state) && |
12972 | !to_intel_crtc_state(crtc->state)->update_pipe) | |
4d20cd86 | 12973 | continue; |
045ac3b5 | 12974 | |
4d20cd86 ML |
12975 | __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state); |
12976 | pipe_config = to_intel_crtc_state(old_crtc_state); | |
12977 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
12978 | pipe_config->base.crtc = crtc; | |
12979 | pipe_config->base.state = old_state; | |
8af6cf88 | 12980 | |
4d20cd86 ML |
12981 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
12982 | crtc->base.id); | |
8af6cf88 | 12983 | |
4d20cd86 ML |
12984 | active = dev_priv->display.get_pipe_config(intel_crtc, |
12985 | pipe_config); | |
d62cf62a | 12986 | |
b6b5d049 | 12987 | /* hw state is inconsistent with the pipe quirk */ |
4d20cd86 ML |
12988 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
12989 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
12990 | active = crtc->state->active; | |
6c49f241 | 12991 | |
4d20cd86 | 12992 | I915_STATE_WARN(crtc->state->active != active, |
0e8ffe1b | 12993 | "crtc active state doesn't match with hw state " |
4d20cd86 | 12994 | "(expected %i, found %i)\n", crtc->state->active, active); |
0e8ffe1b | 12995 | |
4d20cd86 | 12996 | I915_STATE_WARN(intel_crtc->active != crtc->state->active, |
53d9f4e9 | 12997 | "transitional active state does not match atomic hw state " |
4d20cd86 ML |
12998 | "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active); |
12999 | ||
13000 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
13001 | enum pipe pipe; | |
13002 | ||
13003 | active = encoder->get_hw_state(encoder, &pipe); | |
13004 | I915_STATE_WARN(active != crtc->state->active, | |
13005 | "[ENCODER:%i] active %i with crtc active %i\n", | |
13006 | encoder->base.base.id, active, crtc->state->active); | |
13007 | ||
13008 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, | |
13009 | "Encoder connected to wrong pipe %c\n", | |
13010 | pipe_name(pipe)); | |
13011 | ||
13012 | if (active) | |
13013 | encoder->get_config(encoder, pipe_config); | |
13014 | } | |
53d9f4e9 | 13015 | |
4d20cd86 | 13016 | if (!crtc->state->active) |
cfb23ed6 ML |
13017 | continue; |
13018 | ||
4d20cd86 ML |
13019 | sw_config = to_intel_crtc_state(crtc->state); |
13020 | if (!intel_pipe_config_compare(dev, sw_config, | |
13021 | pipe_config, false)) { | |
e2c719b7 | 13022 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
4d20cd86 | 13023 | intel_dump_pipe_config(intel_crtc, pipe_config, |
c0b03411 | 13024 | "[hw state]"); |
4d20cd86 | 13025 | intel_dump_pipe_config(intel_crtc, sw_config, |
c0b03411 DV |
13026 | "[sw state]"); |
13027 | } | |
8af6cf88 DV |
13028 | } |
13029 | } | |
13030 | ||
91d1b4bd DV |
13031 | static void |
13032 | check_shared_dpll_state(struct drm_device *dev) | |
13033 | { | |
fbee40df | 13034 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
13035 | struct intel_crtc *crtc; |
13036 | struct intel_dpll_hw_state dpll_hw_state; | |
13037 | int i; | |
5358901f DV |
13038 | |
13039 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
13040 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
13041 | int enabled_crtcs = 0, active_crtcs = 0; | |
13042 | bool active; | |
13043 | ||
13044 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
13045 | ||
13046 | DRM_DEBUG_KMS("%s\n", pll->name); | |
13047 | ||
13048 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
13049 | ||
e2c719b7 | 13050 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 13051 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 13052 | pll->active, hweight32(pll->config.crtc_mask)); |
e2c719b7 | 13053 | I915_STATE_WARN(pll->active && !pll->on, |
5358901f | 13054 | "pll in active use but not on in sw tracking\n"); |
e2c719b7 | 13055 | I915_STATE_WARN(pll->on && !pll->active, |
35c95375 | 13056 | "pll in on but not on in use in sw tracking\n"); |
e2c719b7 | 13057 | I915_STATE_WARN(pll->on != active, |
5358901f DV |
13058 | "pll on state mismatch (expected %i, found %i)\n", |
13059 | pll->on, active); | |
13060 | ||
d3fcc808 | 13061 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 13062 | if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
5358901f DV |
13063 | enabled_crtcs++; |
13064 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
13065 | active_crtcs++; | |
13066 | } | |
e2c719b7 | 13067 | I915_STATE_WARN(pll->active != active_crtcs, |
5358901f DV |
13068 | "pll active crtcs mismatch (expected %i, found %i)\n", |
13069 | pll->active, active_crtcs); | |
e2c719b7 | 13070 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 13071 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 13072 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 13073 | |
e2c719b7 | 13074 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
13075 | sizeof(dpll_hw_state)), |
13076 | "pll hw state mismatch\n"); | |
5358901f | 13077 | } |
8af6cf88 DV |
13078 | } |
13079 | ||
ee165b1a ML |
13080 | static void |
13081 | intel_modeset_check_state(struct drm_device *dev, | |
13082 | struct drm_atomic_state *old_state) | |
91d1b4bd | 13083 | { |
08db6652 | 13084 | check_wm_state(dev); |
35dd3c64 | 13085 | check_connector_state(dev, old_state); |
91d1b4bd | 13086 | check_encoder_state(dev); |
4d20cd86 | 13087 | check_crtc_state(dev, old_state); |
91d1b4bd DV |
13088 | check_shared_dpll_state(dev); |
13089 | } | |
13090 | ||
5cec258b | 13091 | void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
18442d08 VS |
13092 | int dotclock) |
13093 | { | |
13094 | /* | |
13095 | * FDI already provided one idea for the dotclock. | |
13096 | * Yell if the encoder disagrees. | |
13097 | */ | |
2d112de7 | 13098 | WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), |
18442d08 | 13099 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
2d112de7 | 13100 | pipe_config->base.adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
13101 | } |
13102 | ||
80715b2f VS |
13103 | static void update_scanline_offset(struct intel_crtc *crtc) |
13104 | { | |
13105 | struct drm_device *dev = crtc->base.dev; | |
13106 | ||
13107 | /* | |
13108 | * The scanline counter increments at the leading edge of hsync. | |
13109 | * | |
13110 | * On most platforms it starts counting from vtotal-1 on the | |
13111 | * first active line. That means the scanline counter value is | |
13112 | * always one less than what we would expect. Ie. just after | |
13113 | * start of vblank, which also occurs at start of hsync (on the | |
13114 | * last active line), the scanline counter will read vblank_start-1. | |
13115 | * | |
13116 | * On gen2 the scanline counter starts counting from 1 instead | |
13117 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
13118 | * to keep the value positive), instead of adding one. | |
13119 | * | |
13120 | * On HSW+ the behaviour of the scanline counter depends on the output | |
13121 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
13122 | * there's an extra 1 line difference. So we need to add two instead of | |
13123 | * one to the value. | |
13124 | */ | |
13125 | if (IS_GEN2(dev)) { | |
124abe07 | 13126 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
13127 | int vtotal; |
13128 | ||
124abe07 VS |
13129 | vtotal = adjusted_mode->crtc_vtotal; |
13130 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
13131 | vtotal /= 2; |
13132 | ||
13133 | crtc->scanline_offset = vtotal - 1; | |
13134 | } else if (HAS_DDI(dev) && | |
409ee761 | 13135 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
13136 | crtc->scanline_offset = 2; |
13137 | } else | |
13138 | crtc->scanline_offset = 1; | |
13139 | } | |
13140 | ||
ad421372 | 13141 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 13142 | { |
225da59b | 13143 | struct drm_device *dev = state->dev; |
ed6739ef | 13144 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 13145 | struct intel_shared_dpll_config *shared_dpll = NULL; |
ed6739ef | 13146 | struct intel_crtc *intel_crtc; |
0a9ab303 ACO |
13147 | struct intel_crtc_state *intel_crtc_state; |
13148 | struct drm_crtc *crtc; | |
13149 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 13150 | int i; |
ed6739ef ACO |
13151 | |
13152 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 13153 | return; |
ed6739ef | 13154 | |
0a9ab303 | 13155 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
ad421372 ML |
13156 | int dpll; |
13157 | ||
0a9ab303 | 13158 | intel_crtc = to_intel_crtc(crtc); |
4978cc93 | 13159 | intel_crtc_state = to_intel_crtc_state(crtc_state); |
ad421372 | 13160 | dpll = intel_crtc_state->shared_dpll; |
0a9ab303 | 13161 | |
ad421372 | 13162 | if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE) |
225da59b ACO |
13163 | continue; |
13164 | ||
ad421372 | 13165 | intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE; |
0a9ab303 | 13166 | |
ad421372 ML |
13167 | if (!shared_dpll) |
13168 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 13169 | |
ad421372 ML |
13170 | shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe); |
13171 | } | |
ed6739ef ACO |
13172 | } |
13173 | ||
99d736a2 ML |
13174 | /* |
13175 | * This implements the workaround described in the "notes" section of the mode | |
13176 | * set sequence documentation. When going from no pipes or single pipe to | |
13177 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
13178 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
13179 | */ | |
13180 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
13181 | { | |
13182 | struct drm_crtc_state *crtc_state; | |
13183 | struct intel_crtc *intel_crtc; | |
13184 | struct drm_crtc *crtc; | |
13185 | struct intel_crtc_state *first_crtc_state = NULL; | |
13186 | struct intel_crtc_state *other_crtc_state = NULL; | |
13187 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
13188 | int i; | |
13189 | ||
13190 | /* look at all crtc's that are going to be enabled in during modeset */ | |
13191 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13192 | intel_crtc = to_intel_crtc(crtc); | |
13193 | ||
13194 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
13195 | continue; | |
13196 | ||
13197 | if (first_crtc_state) { | |
13198 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
13199 | break; | |
13200 | } else { | |
13201 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
13202 | first_pipe = intel_crtc->pipe; | |
13203 | } | |
13204 | } | |
13205 | ||
13206 | /* No workaround needed? */ | |
13207 | if (!first_crtc_state) | |
13208 | return 0; | |
13209 | ||
13210 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
13211 | for_each_intel_crtc(state->dev, intel_crtc) { | |
13212 | struct intel_crtc_state *pipe_config; | |
13213 | ||
13214 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
13215 | if (IS_ERR(pipe_config)) | |
13216 | return PTR_ERR(pipe_config); | |
13217 | ||
13218 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
13219 | ||
13220 | if (!pipe_config->base.active || | |
13221 | needs_modeset(&pipe_config->base)) | |
13222 | continue; | |
13223 | ||
13224 | /* 2 or more enabled crtcs means no need for w/a */ | |
13225 | if (enabled_pipe != INVALID_PIPE) | |
13226 | return 0; | |
13227 | ||
13228 | enabled_pipe = intel_crtc->pipe; | |
13229 | } | |
13230 | ||
13231 | if (enabled_pipe != INVALID_PIPE) | |
13232 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
13233 | else if (other_crtc_state) | |
13234 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
13235 | ||
13236 | return 0; | |
13237 | } | |
13238 | ||
27c329ed ML |
13239 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
13240 | { | |
13241 | struct drm_crtc *crtc; | |
13242 | struct drm_crtc_state *crtc_state; | |
13243 | int ret = 0; | |
13244 | ||
13245 | /* add all active pipes to the state */ | |
13246 | for_each_crtc(state->dev, crtc) { | |
13247 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13248 | if (IS_ERR(crtc_state)) | |
13249 | return PTR_ERR(crtc_state); | |
13250 | ||
13251 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
13252 | continue; | |
13253 | ||
13254 | crtc_state->mode_changed = true; | |
13255 | ||
13256 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
13257 | if (ret) | |
13258 | break; | |
13259 | ||
13260 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13261 | if (ret) | |
13262 | break; | |
13263 | } | |
13264 | ||
13265 | return ret; | |
13266 | } | |
13267 | ||
c347a676 | 13268 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 13269 | { |
565602d7 ML |
13270 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
13271 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
13272 | struct drm_crtc *crtc; | |
13273 | struct drm_crtc_state *crtc_state; | |
13274 | int ret = 0, i; | |
054518dd | 13275 | |
b359283a ML |
13276 | if (!check_digital_port_conflicts(state)) { |
13277 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
13278 | return -EINVAL; | |
13279 | } | |
13280 | ||
565602d7 ML |
13281 | intel_state->modeset = true; |
13282 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
13283 | ||
13284 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13285 | if (crtc_state->active) | |
13286 | intel_state->active_crtcs |= 1 << i; | |
13287 | else | |
13288 | intel_state->active_crtcs &= ~(1 << i); | |
13289 | } | |
13290 | ||
054518dd ACO |
13291 | /* |
13292 | * See if the config requires any additional preparation, e.g. | |
13293 | * to adjust global state with pipes off. We need to do this | |
13294 | * here so we can get the modeset_pipe updated config for the new | |
13295 | * mode set on this crtc. For other crtcs we need to use the | |
13296 | * adjusted_mode bits in the crtc directly. | |
13297 | */ | |
27c329ed | 13298 | if (dev_priv->display.modeset_calc_cdclk) { |
27c329ed ML |
13299 | ret = dev_priv->display.modeset_calc_cdclk(state); |
13300 | ||
1a617b77 | 13301 | if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq) |
27c329ed ML |
13302 | ret = intel_modeset_all_pipes(state); |
13303 | ||
13304 | if (ret < 0) | |
054518dd | 13305 | return ret; |
27c329ed | 13306 | } else |
1a617b77 | 13307 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; |
054518dd | 13308 | |
ad421372 | 13309 | intel_modeset_clear_plls(state); |
054518dd | 13310 | |
565602d7 | 13311 | if (IS_HASWELL(dev_priv)) |
ad421372 | 13312 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 13313 | |
ad421372 | 13314 | return 0; |
c347a676 ACO |
13315 | } |
13316 | ||
aa363136 MR |
13317 | /* |
13318 | * Handle calculation of various watermark data at the end of the atomic check | |
13319 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
13320 | * handlers to ensure that all derived state has been updated. | |
13321 | */ | |
13322 | static void calc_watermark_data(struct drm_atomic_state *state) | |
13323 | { | |
13324 | struct drm_device *dev = state->dev; | |
13325 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
13326 | struct drm_crtc *crtc; | |
13327 | struct drm_crtc_state *cstate; | |
13328 | struct drm_plane *plane; | |
13329 | struct drm_plane_state *pstate; | |
13330 | ||
13331 | /* | |
13332 | * Calculate watermark configuration details now that derived | |
13333 | * plane/crtc state is all properly updated. | |
13334 | */ | |
13335 | drm_for_each_crtc(crtc, dev) { | |
13336 | cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?: | |
13337 | crtc->state; | |
13338 | ||
13339 | if (cstate->active) | |
13340 | intel_state->wm_config.num_pipes_active++; | |
13341 | } | |
13342 | drm_for_each_legacy_plane(plane, dev) { | |
13343 | pstate = drm_atomic_get_existing_plane_state(state, plane) ?: | |
13344 | plane->state; | |
13345 | ||
13346 | if (!to_intel_plane_state(pstate)->visible) | |
13347 | continue; | |
13348 | ||
13349 | intel_state->wm_config.sprites_enabled = true; | |
13350 | if (pstate->crtc_w != pstate->src_w >> 16 || | |
13351 | pstate->crtc_h != pstate->src_h >> 16) | |
13352 | intel_state->wm_config.sprites_scaled = true; | |
13353 | } | |
13354 | } | |
13355 | ||
74c090b1 ML |
13356 | /** |
13357 | * intel_atomic_check - validate state object | |
13358 | * @dev: drm device | |
13359 | * @state: state to validate | |
13360 | */ | |
13361 | static int intel_atomic_check(struct drm_device *dev, | |
13362 | struct drm_atomic_state *state) | |
c347a676 | 13363 | { |
aa363136 | 13364 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
13365 | struct drm_crtc *crtc; |
13366 | struct drm_crtc_state *crtc_state; | |
13367 | int ret, i; | |
61333b60 | 13368 | bool any_ms = false; |
c347a676 | 13369 | |
74c090b1 | 13370 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
13371 | if (ret) |
13372 | return ret; | |
13373 | ||
c347a676 | 13374 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
13375 | struct intel_crtc_state *pipe_config = |
13376 | to_intel_crtc_state(crtc_state); | |
1ed51de9 | 13377 | |
ba8af3e5 ML |
13378 | memset(&to_intel_crtc(crtc)->atomic, 0, |
13379 | sizeof(struct intel_crtc_atomic_commit)); | |
13380 | ||
1ed51de9 DV |
13381 | /* Catch I915_MODE_FLAG_INHERITED */ |
13382 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
13383 | crtc_state->mode_changed = true; | |
cfb23ed6 | 13384 | |
61333b60 ML |
13385 | if (!crtc_state->enable) { |
13386 | if (needs_modeset(crtc_state)) | |
13387 | any_ms = true; | |
c347a676 | 13388 | continue; |
61333b60 | 13389 | } |
c347a676 | 13390 | |
26495481 | 13391 | if (!needs_modeset(crtc_state)) |
cfb23ed6 ML |
13392 | continue; |
13393 | ||
26495481 DV |
13394 | /* FIXME: For only active_changed we shouldn't need to do any |
13395 | * state recomputation at all. */ | |
13396 | ||
1ed51de9 DV |
13397 | ret = drm_atomic_add_affected_connectors(state, crtc); |
13398 | if (ret) | |
13399 | return ret; | |
b359283a | 13400 | |
cfb23ed6 | 13401 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
c347a676 ACO |
13402 | if (ret) |
13403 | return ret; | |
13404 | ||
73831236 JN |
13405 | if (i915.fastboot && |
13406 | intel_pipe_config_compare(state->dev, | |
cfb23ed6 | 13407 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 13408 | pipe_config, true)) { |
26495481 | 13409 | crtc_state->mode_changed = false; |
bfd16b2a | 13410 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
13411 | } |
13412 | ||
13413 | if (needs_modeset(crtc_state)) { | |
13414 | any_ms = true; | |
cfb23ed6 ML |
13415 | |
13416 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13417 | if (ret) | |
13418 | return ret; | |
13419 | } | |
61333b60 | 13420 | |
26495481 DV |
13421 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
13422 | needs_modeset(crtc_state) ? | |
13423 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
13424 | } |
13425 | ||
61333b60 ML |
13426 | if (any_ms) { |
13427 | ret = intel_modeset_checks(state); | |
13428 | ||
13429 | if (ret) | |
13430 | return ret; | |
27c329ed | 13431 | } else |
aa363136 | 13432 | intel_state->cdclk = to_i915(state->dev)->cdclk_freq; |
76305b1a | 13433 | |
aa363136 MR |
13434 | ret = drm_atomic_helper_check_planes(state->dev, state); |
13435 | if (ret) | |
13436 | return ret; | |
13437 | ||
13438 | calc_watermark_data(state); | |
13439 | ||
13440 | return 0; | |
054518dd ACO |
13441 | } |
13442 | ||
5008e874 ML |
13443 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
13444 | struct drm_atomic_state *state, | |
13445 | bool async) | |
13446 | { | |
7580d774 ML |
13447 | struct drm_i915_private *dev_priv = dev->dev_private; |
13448 | struct drm_plane_state *plane_state; | |
5008e874 | 13449 | struct drm_crtc_state *crtc_state; |
7580d774 | 13450 | struct drm_plane *plane; |
5008e874 ML |
13451 | struct drm_crtc *crtc; |
13452 | int i, ret; | |
13453 | ||
13454 | if (async) { | |
13455 | DRM_DEBUG_KMS("i915 does not yet support async commit\n"); | |
13456 | return -EINVAL; | |
13457 | } | |
13458 | ||
13459 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13460 | ret = intel_crtc_wait_for_pending_flips(crtc); | |
13461 | if (ret) | |
13462 | return ret; | |
7580d774 ML |
13463 | |
13464 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) | |
13465 | flush_workqueue(dev_priv->wq); | |
5008e874 ML |
13466 | } |
13467 | ||
f935675f ML |
13468 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
13469 | if (ret) | |
13470 | return ret; | |
13471 | ||
5008e874 | 13472 | ret = drm_atomic_helper_prepare_planes(dev, state); |
7580d774 ML |
13473 | if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) { |
13474 | u32 reset_counter; | |
13475 | ||
13476 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); | |
13477 | mutex_unlock(&dev->struct_mutex); | |
13478 | ||
13479 | for_each_plane_in_state(state, plane, plane_state, i) { | |
13480 | struct intel_plane_state *intel_plane_state = | |
13481 | to_intel_plane_state(plane_state); | |
13482 | ||
13483 | if (!intel_plane_state->wait_req) | |
13484 | continue; | |
13485 | ||
13486 | ret = __i915_wait_request(intel_plane_state->wait_req, | |
13487 | reset_counter, true, | |
13488 | NULL, NULL); | |
13489 | ||
13490 | /* Swallow -EIO errors to allow updates during hw lockup. */ | |
13491 | if (ret == -EIO) | |
13492 | ret = 0; | |
13493 | ||
13494 | if (ret) | |
13495 | break; | |
13496 | } | |
13497 | ||
13498 | if (!ret) | |
13499 | return 0; | |
13500 | ||
13501 | mutex_lock(&dev->struct_mutex); | |
13502 | drm_atomic_helper_cleanup_planes(dev, state); | |
13503 | } | |
5008e874 | 13504 | |
f935675f | 13505 | mutex_unlock(&dev->struct_mutex); |
5008e874 ML |
13506 | return ret; |
13507 | } | |
13508 | ||
74c090b1 ML |
13509 | /** |
13510 | * intel_atomic_commit - commit validated state object | |
13511 | * @dev: DRM device | |
13512 | * @state: the top-level driver state object | |
13513 | * @async: asynchronous commit | |
13514 | * | |
13515 | * This function commits a top-level state object that has been validated | |
13516 | * with drm_atomic_helper_check(). | |
13517 | * | |
13518 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment | |
13519 | * we can only handle plane-related operations and do not yet support | |
13520 | * asynchronous commit. | |
13521 | * | |
13522 | * RETURNS | |
13523 | * Zero for success or -errno. | |
13524 | */ | |
13525 | static int intel_atomic_commit(struct drm_device *dev, | |
13526 | struct drm_atomic_state *state, | |
13527 | bool async) | |
a6778b3c | 13528 | { |
565602d7 | 13529 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fbee40df | 13530 | struct drm_i915_private *dev_priv = dev->dev_private; |
0a9ab303 | 13531 | struct drm_crtc_state *crtc_state; |
7580d774 | 13532 | struct drm_crtc *crtc; |
565602d7 ML |
13533 | int ret = 0, i; |
13534 | bool hw_check = intel_state->modeset; | |
a6778b3c | 13535 | |
5008e874 | 13536 | ret = intel_atomic_prepare_commit(dev, state, async); |
7580d774 ML |
13537 | if (ret) { |
13538 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
d4afb8cc | 13539 | return ret; |
7580d774 | 13540 | } |
d4afb8cc | 13541 | |
1c5e19f8 | 13542 | drm_atomic_helper_swap_state(dev, state); |
aa363136 | 13543 | dev_priv->wm.config = to_intel_atomic_state(state)->wm_config; |
1c5e19f8 | 13544 | |
565602d7 ML |
13545 | if (intel_state->modeset) { |
13546 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
13547 | sizeof(intel_state->min_pixclk)); | |
13548 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
1a617b77 | 13549 | dev_priv->atomic_cdclk_freq = intel_state->cdclk; |
565602d7 ML |
13550 | } |
13551 | ||
0a9ab303 | 13552 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
a539205a ML |
13553 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13554 | ||
61333b60 ML |
13555 | if (!needs_modeset(crtc->state)) |
13556 | continue; | |
13557 | ||
a539205a | 13558 | intel_pre_plane_update(intel_crtc); |
460da916 | 13559 | |
a539205a ML |
13560 | if (crtc_state->active) { |
13561 | intel_crtc_disable_planes(crtc, crtc_state->plane_mask); | |
13562 | dev_priv->display.crtc_disable(crtc); | |
eddfcbcd ML |
13563 | intel_crtc->active = false; |
13564 | intel_disable_shared_dpll(intel_crtc); | |
9bbc8258 VS |
13565 | |
13566 | /* | |
13567 | * Underruns don't always raise | |
13568 | * interrupts, so check manually. | |
13569 | */ | |
13570 | intel_check_cpu_fifo_underruns(dev_priv); | |
13571 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 ML |
13572 | |
13573 | if (!crtc->state->active) | |
13574 | intel_update_watermarks(crtc); | |
a539205a | 13575 | } |
b8cecdf5 | 13576 | } |
7758a113 | 13577 | |
ea9d758d DV |
13578 | /* Only after disabling all output pipelines that will be changed can we |
13579 | * update the the output configuration. */ | |
4740b0f2 | 13580 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 13581 | |
565602d7 | 13582 | if (intel_state->modeset) { |
4740b0f2 ML |
13583 | intel_shared_dpll_commit(state); |
13584 | ||
13585 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); | |
61333b60 | 13586 | modeset_update_crtc_power_domains(state); |
4740b0f2 | 13587 | } |
47fab737 | 13588 | |
a6778b3c | 13589 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
0a9ab303 | 13590 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
f6ac4b2a ML |
13591 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13592 | bool modeset = needs_modeset(crtc->state); | |
bfd16b2a ML |
13593 | bool update_pipe = !modeset && |
13594 | to_intel_crtc_state(crtc->state)->update_pipe; | |
13595 | unsigned long put_domains = 0; | |
f6ac4b2a | 13596 | |
9f836f90 PJ |
13597 | if (modeset) |
13598 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); | |
13599 | ||
f6ac4b2a | 13600 | if (modeset && crtc->state->active) { |
a539205a ML |
13601 | update_scanline_offset(to_intel_crtc(crtc)); |
13602 | dev_priv->display.crtc_enable(crtc); | |
13603 | } | |
80715b2f | 13604 | |
bfd16b2a ML |
13605 | if (update_pipe) { |
13606 | put_domains = modeset_get_crtc_power_domains(crtc); | |
13607 | ||
13608 | /* make sure intel_modeset_check_state runs */ | |
565602d7 | 13609 | hw_check = true; |
bfd16b2a ML |
13610 | } |
13611 | ||
f6ac4b2a ML |
13612 | if (!modeset) |
13613 | intel_pre_plane_update(intel_crtc); | |
13614 | ||
6173ee28 ML |
13615 | if (crtc->state->active && |
13616 | (crtc->state->planes_changed || update_pipe)) | |
62852622 | 13617 | drm_atomic_helper_commit_planes_on_crtc(crtc_state); |
bfd16b2a ML |
13618 | |
13619 | if (put_domains) | |
13620 | modeset_put_power_domains(dev_priv, put_domains); | |
13621 | ||
f6ac4b2a | 13622 | intel_post_plane_update(intel_crtc); |
9f836f90 PJ |
13623 | |
13624 | if (modeset) | |
13625 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
80715b2f | 13626 | } |
a6778b3c | 13627 | |
a6778b3c | 13628 | /* FIXME: add subpixel order */ |
83a57153 | 13629 | |
74c090b1 | 13630 | drm_atomic_helper_wait_for_vblanks(dev, state); |
f935675f ML |
13631 | |
13632 | mutex_lock(&dev->struct_mutex); | |
d4afb8cc | 13633 | drm_atomic_helper_cleanup_planes(dev, state); |
f935675f | 13634 | mutex_unlock(&dev->struct_mutex); |
2bfb4627 | 13635 | |
565602d7 | 13636 | if (hw_check) |
ee165b1a ML |
13637 | intel_modeset_check_state(dev, state); |
13638 | ||
13639 | drm_atomic_state_free(state); | |
f30da187 | 13640 | |
74c090b1 | 13641 | return 0; |
7f27126e JB |
13642 | } |
13643 | ||
c0c36b94 CW |
13644 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13645 | { | |
83a57153 ACO |
13646 | struct drm_device *dev = crtc->dev; |
13647 | struct drm_atomic_state *state; | |
e694eb02 | 13648 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 13649 | int ret; |
83a57153 ACO |
13650 | |
13651 | state = drm_atomic_state_alloc(dev); | |
13652 | if (!state) { | |
e694eb02 | 13653 | DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory", |
83a57153 ACO |
13654 | crtc->base.id); |
13655 | return; | |
13656 | } | |
13657 | ||
e694eb02 | 13658 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 13659 | |
e694eb02 ML |
13660 | retry: |
13661 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13662 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
13663 | if (!ret) { | |
13664 | if (!crtc_state->active) | |
13665 | goto out; | |
83a57153 | 13666 | |
e694eb02 | 13667 | crtc_state->mode_changed = true; |
74c090b1 | 13668 | ret = drm_atomic_commit(state); |
83a57153 ACO |
13669 | } |
13670 | ||
e694eb02 ML |
13671 | if (ret == -EDEADLK) { |
13672 | drm_atomic_state_clear(state); | |
13673 | drm_modeset_backoff(state->acquire_ctx); | |
13674 | goto retry; | |
4ed9fb37 | 13675 | } |
4be07317 | 13676 | |
2bfb4627 | 13677 | if (ret) |
e694eb02 | 13678 | out: |
2bfb4627 | 13679 | drm_atomic_state_free(state); |
c0c36b94 CW |
13680 | } |
13681 | ||
25c5b266 DV |
13682 | #undef for_each_intel_crtc_masked |
13683 | ||
f6e5b160 | 13684 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
f6e5b160 | 13685 | .gamma_set = intel_crtc_gamma_set, |
74c090b1 | 13686 | .set_config = drm_atomic_helper_set_config, |
f6e5b160 CW |
13687 | .destroy = intel_crtc_destroy, |
13688 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
13689 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13690 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
13691 | }; |
13692 | ||
5358901f DV |
13693 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
13694 | struct intel_shared_dpll *pll, | |
13695 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 13696 | { |
5358901f | 13697 | uint32_t val; |
ee7b9f93 | 13698 | |
f458ebbc | 13699 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
13700 | return false; |
13701 | ||
5358901f | 13702 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
13703 | hw_state->dpll = val; |
13704 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
13705 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
13706 | |
13707 | return val & DPLL_VCO_ENABLE; | |
13708 | } | |
13709 | ||
15bdd4cf DV |
13710 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
13711 | struct intel_shared_dpll *pll) | |
13712 | { | |
3e369b76 ACO |
13713 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
13714 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
13715 | } |
13716 | ||
e7b903d2 DV |
13717 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
13718 | struct intel_shared_dpll *pll) | |
13719 | { | |
e7b903d2 | 13720 | /* PCH refclock must be enabled first */ |
89eff4be | 13721 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 13722 | |
3e369b76 | 13723 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
13724 | |
13725 | /* Wait for the clocks to stabilize. */ | |
13726 | POSTING_READ(PCH_DPLL(pll->id)); | |
13727 | udelay(150); | |
13728 | ||
13729 | /* The pixel multiplier can only be updated once the | |
13730 | * DPLL is enabled and the clocks are stable. | |
13731 | * | |
13732 | * So write it again. | |
13733 | */ | |
3e369b76 | 13734 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 13735 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
13736 | udelay(200); |
13737 | } | |
13738 | ||
13739 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
13740 | struct intel_shared_dpll *pll) | |
13741 | { | |
13742 | struct drm_device *dev = dev_priv->dev; | |
13743 | struct intel_crtc *crtc; | |
e7b903d2 DV |
13744 | |
13745 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 13746 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
13747 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
13748 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
13749 | } |
13750 | ||
15bdd4cf DV |
13751 | I915_WRITE(PCH_DPLL(pll->id), 0); |
13752 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
13753 | udelay(200); |
13754 | } | |
13755 | ||
46edb027 DV |
13756 | static char *ibx_pch_dpll_names[] = { |
13757 | "PCH DPLL A", | |
13758 | "PCH DPLL B", | |
13759 | }; | |
13760 | ||
7c74ade1 | 13761 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 13762 | { |
e7b903d2 | 13763 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
13764 | int i; |
13765 | ||
7c74ade1 | 13766 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 13767 | |
e72f9fbf | 13768 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
13769 | dev_priv->shared_dplls[i].id = i; |
13770 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 13771 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
13772 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
13773 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
13774 | dev_priv->shared_dplls[i].get_hw_state = |
13775 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
13776 | } |
13777 | } | |
13778 | ||
7c74ade1 DV |
13779 | static void intel_shared_dpll_init(struct drm_device *dev) |
13780 | { | |
e7b903d2 | 13781 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 13782 | |
9cd86933 DV |
13783 | if (HAS_DDI(dev)) |
13784 | intel_ddi_pll_init(dev); | |
13785 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
13786 | ibx_pch_dpll_init(dev); |
13787 | else | |
13788 | dev_priv->num_shared_dpll = 0; | |
13789 | ||
13790 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
13791 | } |
13792 | ||
6beb8c23 MR |
13793 | /** |
13794 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13795 | * @plane: drm plane to prepare for | |
13796 | * @fb: framebuffer to prepare for presentation | |
13797 | * | |
13798 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13799 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13800 | * bits. Some older platforms need special physical address handling for | |
13801 | * cursor planes. | |
13802 | * | |
f935675f ML |
13803 | * Must be called with struct_mutex held. |
13804 | * | |
6beb8c23 MR |
13805 | * Returns 0 on success, negative error code on failure. |
13806 | */ | |
13807 | int | |
13808 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee | 13809 | const struct drm_plane_state *new_state) |
465c120c MR |
13810 | { |
13811 | struct drm_device *dev = plane->dev; | |
844f9111 | 13812 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 13813 | struct intel_plane *intel_plane = to_intel_plane(plane); |
6beb8c23 | 13814 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 13815 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
6beb8c23 | 13816 | int ret = 0; |
465c120c | 13817 | |
1ee49399 | 13818 | if (!obj && !old_obj) |
465c120c MR |
13819 | return 0; |
13820 | ||
5008e874 ML |
13821 | if (old_obj) { |
13822 | struct drm_crtc_state *crtc_state = | |
13823 | drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc); | |
13824 | ||
13825 | /* Big Hammer, we also need to ensure that any pending | |
13826 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
13827 | * current scanout is retired before unpinning the old | |
13828 | * framebuffer. Note that we rely on userspace rendering | |
13829 | * into the buffer attached to the pipe they are waiting | |
13830 | * on. If not, userspace generates a GPU hang with IPEHR | |
13831 | * point to the MI_WAIT_FOR_EVENT. | |
13832 | * | |
13833 | * This should only fail upon a hung GPU, in which case we | |
13834 | * can safely continue. | |
13835 | */ | |
13836 | if (needs_modeset(crtc_state)) | |
13837 | ret = i915_gem_object_wait_rendering(old_obj, true); | |
13838 | ||
13839 | /* Swallow -EIO errors to allow updates during hw lockup. */ | |
13840 | if (ret && ret != -EIO) | |
f935675f | 13841 | return ret; |
5008e874 ML |
13842 | } |
13843 | ||
3c28ff22 AG |
13844 | /* For framebuffer backed by dmabuf, wait for fence */ |
13845 | if (obj && obj->base.dma_buf) { | |
13846 | ret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
13847 | false, true, | |
13848 | MAX_SCHEDULE_TIMEOUT); | |
13849 | if (ret == -ERESTARTSYS) | |
13850 | return ret; | |
13851 | ||
13852 | WARN_ON(ret < 0); | |
13853 | } | |
13854 | ||
1ee49399 ML |
13855 | if (!obj) { |
13856 | ret = 0; | |
13857 | } else if (plane->type == DRM_PLANE_TYPE_CURSOR && | |
6beb8c23 MR |
13858 | INTEL_INFO(dev)->cursor_needs_physical) { |
13859 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
13860 | ret = i915_gem_object_attach_phys(obj, align); | |
13861 | if (ret) | |
13862 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13863 | } else { | |
7580d774 | 13864 | ret = intel_pin_and_fence_fb_obj(plane, fb, new_state); |
6beb8c23 | 13865 | } |
465c120c | 13866 | |
7580d774 ML |
13867 | if (ret == 0) { |
13868 | if (obj) { | |
13869 | struct intel_plane_state *plane_state = | |
13870 | to_intel_plane_state(new_state); | |
13871 | ||
13872 | i915_gem_request_assign(&plane_state->wait_req, | |
13873 | obj->last_write_req); | |
13874 | } | |
13875 | ||
a9ff8714 | 13876 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); |
7580d774 | 13877 | } |
fdd508a6 | 13878 | |
6beb8c23 MR |
13879 | return ret; |
13880 | } | |
13881 | ||
38f3ce3a MR |
13882 | /** |
13883 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13884 | * @plane: drm plane to clean up for | |
13885 | * @fb: old framebuffer that was on plane | |
13886 | * | |
13887 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
13888 | * |
13889 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
13890 | */ |
13891 | void | |
13892 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee | 13893 | const struct drm_plane_state *old_state) |
38f3ce3a MR |
13894 | { |
13895 | struct drm_device *dev = plane->dev; | |
1ee49399 | 13896 | struct intel_plane *intel_plane = to_intel_plane(plane); |
7580d774 | 13897 | struct intel_plane_state *old_intel_state; |
1ee49399 ML |
13898 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
13899 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); | |
38f3ce3a | 13900 | |
7580d774 ML |
13901 | old_intel_state = to_intel_plane_state(old_state); |
13902 | ||
1ee49399 | 13903 | if (!obj && !old_obj) |
38f3ce3a MR |
13904 | return; |
13905 | ||
1ee49399 ML |
13906 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
13907 | !INTEL_INFO(dev)->cursor_needs_physical)) | |
844f9111 | 13908 | intel_unpin_fb_obj(old_state->fb, old_state); |
1ee49399 ML |
13909 | |
13910 | /* prepare_fb aborted? */ | |
13911 | if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) || | |
13912 | (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit))) | |
13913 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); | |
7580d774 ML |
13914 | |
13915 | i915_gem_request_assign(&old_intel_state->wait_req, NULL); | |
13916 | ||
465c120c MR |
13917 | } |
13918 | ||
6156a456 CK |
13919 | int |
13920 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
13921 | { | |
13922 | int max_scale; | |
13923 | struct drm_device *dev; | |
13924 | struct drm_i915_private *dev_priv; | |
13925 | int crtc_clock, cdclk; | |
13926 | ||
bf8a0af0 | 13927 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
13928 | return DRM_PLANE_HELPER_NO_SCALING; |
13929 | ||
13930 | dev = intel_crtc->base.dev; | |
13931 | dev_priv = dev->dev_private; | |
13932 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; | |
27c329ed | 13933 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 | 13934 | |
54bf1ce6 | 13935 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
6156a456 CK |
13936 | return DRM_PLANE_HELPER_NO_SCALING; |
13937 | ||
13938 | /* | |
13939 | * skl max scale is lower of: | |
13940 | * close to 3 but not 3, -1 is for that purpose | |
13941 | * or | |
13942 | * cdclk/crtc_clock | |
13943 | */ | |
13944 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
13945 | ||
13946 | return max_scale; | |
13947 | } | |
13948 | ||
465c120c | 13949 | static int |
3c692a41 | 13950 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 13951 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
13952 | struct intel_plane_state *state) |
13953 | { | |
2b875c22 MR |
13954 | struct drm_crtc *crtc = state->base.crtc; |
13955 | struct drm_framebuffer *fb = state->base.fb; | |
6156a456 | 13956 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
13957 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
13958 | bool can_position = false; | |
465c120c | 13959 | |
061e4b8d ML |
13960 | /* use scaler when colorkey is not required */ |
13961 | if (INTEL_INFO(plane->dev)->gen >= 9 && | |
818ed961 | 13962 | state->ckey.flags == I915_SET_COLORKEY_NONE) { |
061e4b8d ML |
13963 | min_scale = 1; |
13964 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
d8106366 | 13965 | can_position = true; |
6156a456 | 13966 | } |
d8106366 | 13967 | |
061e4b8d ML |
13968 | return drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
13969 | &state->dst, &state->clip, | |
da20eabd ML |
13970 | min_scale, max_scale, |
13971 | can_position, true, | |
13972 | &state->visible); | |
14af293f GP |
13973 | } |
13974 | ||
13975 | static void | |
13976 | intel_commit_primary_plane(struct drm_plane *plane, | |
13977 | struct intel_plane_state *state) | |
13978 | { | |
2b875c22 MR |
13979 | struct drm_crtc *crtc = state->base.crtc; |
13980 | struct drm_framebuffer *fb = state->base.fb; | |
13981 | struct drm_device *dev = plane->dev; | |
14af293f | 13982 | struct drm_i915_private *dev_priv = dev->dev_private; |
14af293f | 13983 | |
ea2c67bb | 13984 | crtc = crtc ? crtc : plane->crtc; |
ccc759dc | 13985 | |
d4b08630 ML |
13986 | dev_priv->display.update_primary_plane(crtc, fb, |
13987 | state->src.x1 >> 16, | |
13988 | state->src.y1 >> 16); | |
465c120c MR |
13989 | } |
13990 | ||
a8ad0d8e ML |
13991 | static void |
13992 | intel_disable_primary_plane(struct drm_plane *plane, | |
7fabf5ef | 13993 | struct drm_crtc *crtc) |
a8ad0d8e ML |
13994 | { |
13995 | struct drm_device *dev = plane->dev; | |
13996 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13997 | ||
a8ad0d8e ML |
13998 | dev_priv->display.update_primary_plane(crtc, NULL, 0, 0); |
13999 | } | |
14000 | ||
613d2b27 ML |
14001 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
14002 | struct drm_crtc_state *old_crtc_state) | |
3c692a41 | 14003 | { |
32b7eeec | 14004 | struct drm_device *dev = crtc->dev; |
3c692a41 | 14005 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
bfd16b2a ML |
14006 | struct intel_crtc_state *old_intel_state = |
14007 | to_intel_crtc_state(old_crtc_state); | |
14008 | bool modeset = needs_modeset(crtc->state); | |
3c692a41 | 14009 | |
c34c9ee4 | 14010 | /* Perform vblank evasion around commit operation */ |
62852622 | 14011 | intel_pipe_update_start(intel_crtc); |
0583236e | 14012 | |
bfd16b2a ML |
14013 | if (modeset) |
14014 | return; | |
14015 | ||
14016 | if (to_intel_crtc_state(crtc->state)->update_pipe) | |
14017 | intel_update_pipe_config(intel_crtc, old_intel_state); | |
14018 | else if (INTEL_INFO(dev)->gen >= 9) | |
0583236e | 14019 | skl_detach_scalers(intel_crtc); |
32b7eeec MR |
14020 | } |
14021 | ||
613d2b27 ML |
14022 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, |
14023 | struct drm_crtc_state *old_crtc_state) | |
32b7eeec | 14024 | { |
32b7eeec | 14025 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
32b7eeec | 14026 | |
62852622 | 14027 | intel_pipe_update_end(intel_crtc); |
3c692a41 GP |
14028 | } |
14029 | ||
cf4c7c12 | 14030 | /** |
4a3b8769 MR |
14031 | * intel_plane_destroy - destroy a plane |
14032 | * @plane: plane to destroy | |
cf4c7c12 | 14033 | * |
4a3b8769 MR |
14034 | * Common destruction function for all types of planes (primary, cursor, |
14035 | * sprite). | |
cf4c7c12 | 14036 | */ |
4a3b8769 | 14037 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
14038 | { |
14039 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
14040 | drm_plane_cleanup(plane); | |
14041 | kfree(intel_plane); | |
14042 | } | |
14043 | ||
65a3fea0 | 14044 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
14045 | .update_plane = drm_atomic_helper_update_plane, |
14046 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 14047 | .destroy = intel_plane_destroy, |
c196e1d6 | 14048 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
14049 | .atomic_get_property = intel_plane_atomic_get_property, |
14050 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
14051 | .atomic_duplicate_state = intel_plane_duplicate_state, |
14052 | .atomic_destroy_state = intel_plane_destroy_state, | |
14053 | ||
465c120c MR |
14054 | }; |
14055 | ||
14056 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
14057 | int pipe) | |
14058 | { | |
14059 | struct intel_plane *primary; | |
8e7d688b | 14060 | struct intel_plane_state *state; |
465c120c | 14061 | const uint32_t *intel_primary_formats; |
45e3743a | 14062 | unsigned int num_formats; |
465c120c MR |
14063 | |
14064 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
14065 | if (primary == NULL) | |
14066 | return NULL; | |
14067 | ||
8e7d688b MR |
14068 | state = intel_create_plane_state(&primary->base); |
14069 | if (!state) { | |
ea2c67bb MR |
14070 | kfree(primary); |
14071 | return NULL; | |
14072 | } | |
8e7d688b | 14073 | primary->base.state = &state->base; |
ea2c67bb | 14074 | |
465c120c MR |
14075 | primary->can_scale = false; |
14076 | primary->max_downscale = 1; | |
6156a456 CK |
14077 | if (INTEL_INFO(dev)->gen >= 9) { |
14078 | primary->can_scale = true; | |
af99ceda | 14079 | state->scaler_id = -1; |
6156a456 | 14080 | } |
465c120c MR |
14081 | primary->pipe = pipe; |
14082 | primary->plane = pipe; | |
a9ff8714 | 14083 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 MR |
14084 | primary->check_plane = intel_check_primary_plane; |
14085 | primary->commit_plane = intel_commit_primary_plane; | |
a8ad0d8e | 14086 | primary->disable_plane = intel_disable_primary_plane; |
465c120c MR |
14087 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
14088 | primary->plane = !pipe; | |
14089 | ||
6c0fd451 DL |
14090 | if (INTEL_INFO(dev)->gen >= 9) { |
14091 | intel_primary_formats = skl_primary_formats; | |
14092 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
14093 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
568db4f2 DL |
14094 | intel_primary_formats = i965_primary_formats; |
14095 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
6c0fd451 DL |
14096 | } else { |
14097 | intel_primary_formats = i8xx_primary_formats; | |
14098 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
465c120c MR |
14099 | } |
14100 | ||
14101 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 14102 | &intel_plane_funcs, |
465c120c MR |
14103 | intel_primary_formats, num_formats, |
14104 | DRM_PLANE_TYPE_PRIMARY); | |
48404c1e | 14105 | |
3b7a5119 SJ |
14106 | if (INTEL_INFO(dev)->gen >= 4) |
14107 | intel_create_rotation_property(dev, primary); | |
48404c1e | 14108 | |
ea2c67bb MR |
14109 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
14110 | ||
465c120c MR |
14111 | return &primary->base; |
14112 | } | |
14113 | ||
3b7a5119 SJ |
14114 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
14115 | { | |
14116 | if (!dev->mode_config.rotation_property) { | |
14117 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
14118 | BIT(DRM_ROTATE_180); | |
14119 | ||
14120 | if (INTEL_INFO(dev)->gen >= 9) | |
14121 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
14122 | ||
14123 | dev->mode_config.rotation_property = | |
14124 | drm_mode_create_rotation_property(dev, flags); | |
14125 | } | |
14126 | if (dev->mode_config.rotation_property) | |
14127 | drm_object_attach_property(&plane->base.base, | |
14128 | dev->mode_config.rotation_property, | |
14129 | plane->base.state->rotation); | |
14130 | } | |
14131 | ||
3d7d6510 | 14132 | static int |
852e787c | 14133 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 14134 | struct intel_crtc_state *crtc_state, |
852e787c | 14135 | struct intel_plane_state *state) |
3d7d6510 | 14136 | { |
061e4b8d | 14137 | struct drm_crtc *crtc = crtc_state->base.crtc; |
2b875c22 | 14138 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 14139 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
b29ec92c | 14140 | enum pipe pipe = to_intel_plane(plane)->pipe; |
757f9a3e GP |
14141 | unsigned stride; |
14142 | int ret; | |
3d7d6510 | 14143 | |
061e4b8d ML |
14144 | ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
14145 | &state->dst, &state->clip, | |
3d7d6510 MR |
14146 | DRM_PLANE_HELPER_NO_SCALING, |
14147 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 14148 | true, true, &state->visible); |
757f9a3e GP |
14149 | if (ret) |
14150 | return ret; | |
14151 | ||
757f9a3e GP |
14152 | /* if we want to turn off the cursor ignore width and height */ |
14153 | if (!obj) | |
da20eabd | 14154 | return 0; |
757f9a3e | 14155 | |
757f9a3e | 14156 | /* Check for which cursor types we support */ |
061e4b8d | 14157 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
ea2c67bb MR |
14158 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
14159 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
14160 | return -EINVAL; |
14161 | } | |
14162 | ||
ea2c67bb MR |
14163 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
14164 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
14165 | DRM_DEBUG_KMS("buffer is too small\n"); |
14166 | return -ENOMEM; | |
14167 | } | |
14168 | ||
3a656b54 | 14169 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 14170 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 14171 | return -EINVAL; |
32b7eeec MR |
14172 | } |
14173 | ||
b29ec92c VS |
14174 | /* |
14175 | * There's something wrong with the cursor on CHV pipe C. | |
14176 | * If it straddles the left edge of the screen then | |
14177 | * moving it away from the edge or disabling it often | |
14178 | * results in a pipe underrun, and often that can lead to | |
14179 | * dead pipe (constant underrun reported, and it scans | |
14180 | * out just a solid color). To recover from that, the | |
14181 | * display power well must be turned off and on again. | |
14182 | * Refuse the put the cursor into that compromised position. | |
14183 | */ | |
14184 | if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C && | |
14185 | state->visible && state->base.crtc_x < 0) { | |
14186 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); | |
14187 | return -EINVAL; | |
14188 | } | |
14189 | ||
da20eabd | 14190 | return 0; |
852e787c | 14191 | } |
3d7d6510 | 14192 | |
a8ad0d8e ML |
14193 | static void |
14194 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 14195 | struct drm_crtc *crtc) |
a8ad0d8e | 14196 | { |
a8ad0d8e ML |
14197 | intel_crtc_update_cursor(crtc, false); |
14198 | } | |
14199 | ||
f4a2cf29 | 14200 | static void |
852e787c GP |
14201 | intel_commit_cursor_plane(struct drm_plane *plane, |
14202 | struct intel_plane_state *state) | |
14203 | { | |
2b875c22 | 14204 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb MR |
14205 | struct drm_device *dev = plane->dev; |
14206 | struct intel_crtc *intel_crtc; | |
2b875c22 | 14207 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 14208 | uint32_t addr; |
852e787c | 14209 | |
ea2c67bb MR |
14210 | crtc = crtc ? crtc : plane->crtc; |
14211 | intel_crtc = to_intel_crtc(crtc); | |
14212 | ||
f4a2cf29 | 14213 | if (!obj) |
a912f12f | 14214 | addr = 0; |
f4a2cf29 | 14215 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 14216 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 14217 | else |
a912f12f | 14218 | addr = obj->phys_handle->busaddr; |
852e787c | 14219 | |
a912f12f | 14220 | intel_crtc->cursor_addr = addr; |
852e787c | 14221 | |
62852622 | 14222 | intel_crtc_update_cursor(crtc, state->visible); |
852e787c GP |
14223 | } |
14224 | ||
3d7d6510 MR |
14225 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
14226 | int pipe) | |
14227 | { | |
14228 | struct intel_plane *cursor; | |
8e7d688b | 14229 | struct intel_plane_state *state; |
3d7d6510 MR |
14230 | |
14231 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
14232 | if (cursor == NULL) | |
14233 | return NULL; | |
14234 | ||
8e7d688b MR |
14235 | state = intel_create_plane_state(&cursor->base); |
14236 | if (!state) { | |
ea2c67bb MR |
14237 | kfree(cursor); |
14238 | return NULL; | |
14239 | } | |
8e7d688b | 14240 | cursor->base.state = &state->base; |
ea2c67bb | 14241 | |
3d7d6510 MR |
14242 | cursor->can_scale = false; |
14243 | cursor->max_downscale = 1; | |
14244 | cursor->pipe = pipe; | |
14245 | cursor->plane = pipe; | |
a9ff8714 | 14246 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 MR |
14247 | cursor->check_plane = intel_check_cursor_plane; |
14248 | cursor->commit_plane = intel_commit_cursor_plane; | |
a8ad0d8e | 14249 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 MR |
14250 | |
14251 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 14252 | &intel_plane_funcs, |
3d7d6510 MR |
14253 | intel_cursor_formats, |
14254 | ARRAY_SIZE(intel_cursor_formats), | |
14255 | DRM_PLANE_TYPE_CURSOR); | |
4398ad45 VS |
14256 | |
14257 | if (INTEL_INFO(dev)->gen >= 4) { | |
14258 | if (!dev->mode_config.rotation_property) | |
14259 | dev->mode_config.rotation_property = | |
14260 | drm_mode_create_rotation_property(dev, | |
14261 | BIT(DRM_ROTATE_0) | | |
14262 | BIT(DRM_ROTATE_180)); | |
14263 | if (dev->mode_config.rotation_property) | |
14264 | drm_object_attach_property(&cursor->base.base, | |
14265 | dev->mode_config.rotation_property, | |
8e7d688b | 14266 | state->base.rotation); |
4398ad45 VS |
14267 | } |
14268 | ||
af99ceda CK |
14269 | if (INTEL_INFO(dev)->gen >=9) |
14270 | state->scaler_id = -1; | |
14271 | ||
ea2c67bb MR |
14272 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
14273 | ||
3d7d6510 MR |
14274 | return &cursor->base; |
14275 | } | |
14276 | ||
549e2bfb CK |
14277 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
14278 | struct intel_crtc_state *crtc_state) | |
14279 | { | |
14280 | int i; | |
14281 | struct intel_scaler *intel_scaler; | |
14282 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
14283 | ||
14284 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
14285 | intel_scaler = &scaler_state->scalers[i]; | |
14286 | intel_scaler->in_use = 0; | |
549e2bfb CK |
14287 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
14288 | } | |
14289 | ||
14290 | scaler_state->scaler_id = -1; | |
14291 | } | |
14292 | ||
b358d0a6 | 14293 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 14294 | { |
fbee40df | 14295 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 14296 | struct intel_crtc *intel_crtc; |
f5de6e07 | 14297 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
14298 | struct drm_plane *primary = NULL; |
14299 | struct drm_plane *cursor = NULL; | |
465c120c | 14300 | int i, ret; |
79e53945 | 14301 | |
955382f3 | 14302 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
14303 | if (intel_crtc == NULL) |
14304 | return; | |
14305 | ||
f5de6e07 ACO |
14306 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
14307 | if (!crtc_state) | |
14308 | goto fail; | |
550acefd ACO |
14309 | intel_crtc->config = crtc_state; |
14310 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 14311 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 14312 | |
549e2bfb CK |
14313 | /* initialize shared scalers */ |
14314 | if (INTEL_INFO(dev)->gen >= 9) { | |
14315 | if (pipe == PIPE_C) | |
14316 | intel_crtc->num_scalers = 1; | |
14317 | else | |
14318 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
14319 | ||
14320 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
14321 | } | |
14322 | ||
465c120c | 14323 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
14324 | if (!primary) |
14325 | goto fail; | |
14326 | ||
14327 | cursor = intel_cursor_plane_create(dev, pipe); | |
14328 | if (!cursor) | |
14329 | goto fail; | |
14330 | ||
465c120c | 14331 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
14332 | cursor, &intel_crtc_funcs); |
14333 | if (ret) | |
14334 | goto fail; | |
79e53945 JB |
14335 | |
14336 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
14337 | for (i = 0; i < 256; i++) { |
14338 | intel_crtc->lut_r[i] = i; | |
14339 | intel_crtc->lut_g[i] = i; | |
14340 | intel_crtc->lut_b[i] = i; | |
14341 | } | |
14342 | ||
1f1c2e24 VS |
14343 | /* |
14344 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 14345 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 14346 | */ |
80824003 JB |
14347 | intel_crtc->pipe = pipe; |
14348 | intel_crtc->plane = pipe; | |
3a77c4c4 | 14349 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 14350 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 14351 | intel_crtc->plane = !pipe; |
80824003 JB |
14352 | } |
14353 | ||
4b0e333e CW |
14354 | intel_crtc->cursor_base = ~0; |
14355 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 14356 | intel_crtc->cursor_size = ~0; |
8d7849db | 14357 | |
852eb00d VS |
14358 | intel_crtc->wm.cxsr_allowed = true; |
14359 | ||
22fd0fab JB |
14360 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
14361 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
14362 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
14363 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
14364 | ||
79e53945 | 14365 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
14366 | |
14367 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
14368 | return; |
14369 | ||
14370 | fail: | |
14371 | if (primary) | |
14372 | drm_plane_cleanup(primary); | |
14373 | if (cursor) | |
14374 | drm_plane_cleanup(cursor); | |
f5de6e07 | 14375 | kfree(crtc_state); |
3d7d6510 | 14376 | kfree(intel_crtc); |
79e53945 JB |
14377 | } |
14378 | ||
752aa88a JB |
14379 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
14380 | { | |
14381 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 14382 | struct drm_device *dev = connector->base.dev; |
752aa88a | 14383 | |
51fd371b | 14384 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 14385 | |
d3babd3f | 14386 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
14387 | return INVALID_PIPE; |
14388 | ||
14389 | return to_intel_crtc(encoder->crtc)->pipe; | |
14390 | } | |
14391 | ||
08d7b3d1 | 14392 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 14393 | struct drm_file *file) |
08d7b3d1 | 14394 | { |
08d7b3d1 | 14395 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 14396 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 14397 | struct intel_crtc *crtc; |
08d7b3d1 | 14398 | |
7707e653 | 14399 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 14400 | |
7707e653 | 14401 | if (!drmmode_crtc) { |
08d7b3d1 | 14402 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 14403 | return -ENOENT; |
08d7b3d1 CW |
14404 | } |
14405 | ||
7707e653 | 14406 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 14407 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 14408 | |
c05422d5 | 14409 | return 0; |
08d7b3d1 CW |
14410 | } |
14411 | ||
66a9278e | 14412 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 14413 | { |
66a9278e DV |
14414 | struct drm_device *dev = encoder->base.dev; |
14415 | struct intel_encoder *source_encoder; | |
79e53945 | 14416 | int index_mask = 0; |
79e53945 JB |
14417 | int entry = 0; |
14418 | ||
b2784e15 | 14419 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 14420 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
14421 | index_mask |= (1 << entry); |
14422 | ||
79e53945 JB |
14423 | entry++; |
14424 | } | |
4ef69c7a | 14425 | |
79e53945 JB |
14426 | return index_mask; |
14427 | } | |
14428 | ||
4d302442 CW |
14429 | static bool has_edp_a(struct drm_device *dev) |
14430 | { | |
14431 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14432 | ||
14433 | if (!IS_MOBILE(dev)) | |
14434 | return false; | |
14435 | ||
14436 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
14437 | return false; | |
14438 | ||
e3589908 | 14439 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
14440 | return false; |
14441 | ||
14442 | return true; | |
14443 | } | |
14444 | ||
84b4e042 JB |
14445 | static bool intel_crt_present(struct drm_device *dev) |
14446 | { | |
14447 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14448 | ||
884497ed DL |
14449 | if (INTEL_INFO(dev)->gen >= 9) |
14450 | return false; | |
14451 | ||
cf404ce4 | 14452 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
14453 | return false; |
14454 | ||
14455 | if (IS_CHERRYVIEW(dev)) | |
14456 | return false; | |
14457 | ||
65e472e4 VS |
14458 | if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) |
14459 | return false; | |
14460 | ||
70ac54d0 VS |
14461 | /* DDI E can't be used if DDI A requires 4 lanes */ |
14462 | if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) | |
14463 | return false; | |
14464 | ||
e4abb733 | 14465 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
14466 | return false; |
14467 | ||
14468 | return true; | |
14469 | } | |
14470 | ||
79e53945 JB |
14471 | static void intel_setup_outputs(struct drm_device *dev) |
14472 | { | |
725e30ad | 14473 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 14474 | struct intel_encoder *encoder; |
cb0953d7 | 14475 | bool dpd_is_edp = false; |
79e53945 | 14476 | |
c9093354 | 14477 | intel_lvds_init(dev); |
79e53945 | 14478 | |
84b4e042 | 14479 | if (intel_crt_present(dev)) |
79935fca | 14480 | intel_crt_init(dev); |
cb0953d7 | 14481 | |
c776eb2e VK |
14482 | if (IS_BROXTON(dev)) { |
14483 | /* | |
14484 | * FIXME: Broxton doesn't support port detection via the | |
14485 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14486 | * detect the ports. | |
14487 | */ | |
14488 | intel_ddi_init(dev, PORT_A); | |
14489 | intel_ddi_init(dev, PORT_B); | |
14490 | intel_ddi_init(dev, PORT_C); | |
14491 | } else if (HAS_DDI(dev)) { | |
0e72a5b5 ED |
14492 | int found; |
14493 | ||
de31facd JB |
14494 | /* |
14495 | * Haswell uses DDI functions to detect digital outputs. | |
14496 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14497 | * it's there. | |
14498 | */ | |
77179400 | 14499 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 14500 | /* WaIgnoreDDIAStrap: skl */ |
ef11bdb3 | 14501 | if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
0e72a5b5 ED |
14502 | intel_ddi_init(dev, PORT_A); |
14503 | ||
14504 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14505 | * register */ | |
14506 | found = I915_READ(SFUSE_STRAP); | |
14507 | ||
14508 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
14509 | intel_ddi_init(dev, PORT_B); | |
14510 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
14511 | intel_ddi_init(dev, PORT_C); | |
14512 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
14513 | intel_ddi_init(dev, PORT_D); | |
2800e4c2 RV |
14514 | /* |
14515 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
14516 | */ | |
ef11bdb3 | 14517 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && |
2800e4c2 RV |
14518 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
14519 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
14520 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
14521 | intel_ddi_init(dev, PORT_E); | |
14522 | ||
0e72a5b5 | 14523 | } else if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 14524 | int found; |
5d8a7752 | 14525 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
14526 | |
14527 | if (has_edp_a(dev)) | |
14528 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 14529 | |
dc0fa718 | 14530 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14531 | /* PCH SDVOB multiplex with HDMIB */ |
2a5c0832 | 14532 | found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); |
30ad48b7 | 14533 | if (!found) |
e2debe91 | 14534 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 14535 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 14536 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14537 | } |
14538 | ||
dc0fa718 | 14539 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 14540 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 14541 | |
dc0fa718 | 14542 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 14543 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 14544 | |
5eb08b69 | 14545 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 14546 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 14547 | |
270b3042 | 14548 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 14549 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
666a4537 | 14550 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
e17ac6db VS |
14551 | /* |
14552 | * The DP_DETECTED bit is the latched state of the DDC | |
14553 | * SDA pin at boot. However since eDP doesn't require DDC | |
14554 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14555 | * eDP ports may have been muxed to an alternate function. | |
14556 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14557 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14558 | * detect eDP ports. | |
14559 | */ | |
e66eb81d | 14560 | if (I915_READ(VLV_HDMIB) & SDVO_DETECTED && |
d2182a66 | 14561 | !intel_dp_is_edp(dev, PORT_B)) |
e66eb81d VS |
14562 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
14563 | if (I915_READ(VLV_DP_B) & DP_DETECTED || | |
e17ac6db | 14564 | intel_dp_is_edp(dev, PORT_B)) |
e66eb81d | 14565 | intel_dp_init(dev, VLV_DP_B, PORT_B); |
585a94b8 | 14566 | |
e66eb81d | 14567 | if (I915_READ(VLV_HDMIC) & SDVO_DETECTED && |
d2182a66 | 14568 | !intel_dp_is_edp(dev, PORT_C)) |
e66eb81d VS |
14569 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
14570 | if (I915_READ(VLV_DP_C) & DP_DETECTED || | |
e17ac6db | 14571 | intel_dp_is_edp(dev, PORT_C)) |
e66eb81d | 14572 | intel_dp_init(dev, VLV_DP_C, PORT_C); |
19c03924 | 14573 | |
9418c1f1 | 14574 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 14575 | /* eDP not supported on port D, so don't check VBT */ |
e66eb81d VS |
14576 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED) |
14577 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); | |
14578 | if (I915_READ(CHV_DP_D) & DP_DETECTED) | |
14579 | intel_dp_init(dev, CHV_DP_D, PORT_D); | |
9418c1f1 VS |
14580 | } |
14581 | ||
3cfca973 | 14582 | intel_dsi_init(dev); |
09da55dc | 14583 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
27185ae1 | 14584 | bool found = false; |
7d57382e | 14585 | |
e2debe91 | 14586 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14587 | DRM_DEBUG_KMS("probing SDVOB\n"); |
2a5c0832 | 14588 | found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B); |
3fec3d2f | 14589 | if (!found && IS_G4X(dev)) { |
b01f2c3a | 14590 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
e2debe91 | 14591 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14592 | } |
27185ae1 | 14593 | |
3fec3d2f | 14594 | if (!found && IS_G4X(dev)) |
ab9d7c30 | 14595 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 14596 | } |
13520b05 KH |
14597 | |
14598 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14599 | |
e2debe91 | 14600 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14601 | DRM_DEBUG_KMS("probing SDVOC\n"); |
2a5c0832 | 14602 | found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); |
b01f2c3a | 14603 | } |
27185ae1 | 14604 | |
e2debe91 | 14605 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14606 | |
3fec3d2f | 14607 | if (IS_G4X(dev)) { |
b01f2c3a | 14608 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
e2debe91 | 14609 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14610 | } |
3fec3d2f | 14611 | if (IS_G4X(dev)) |
ab9d7c30 | 14612 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 14613 | } |
27185ae1 | 14614 | |
3fec3d2f | 14615 | if (IS_G4X(dev) && |
e7281eab | 14616 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 14617 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 14618 | } else if (IS_GEN2(dev)) |
79e53945 JB |
14619 | intel_dvo_init(dev); |
14620 | ||
103a196f | 14621 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
14622 | intel_tv_init(dev); |
14623 | ||
0bc12bcb | 14624 | intel_psr_init(dev); |
7c8f8a70 | 14625 | |
b2784e15 | 14626 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
14627 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14628 | encoder->base.possible_clones = | |
66a9278e | 14629 | intel_encoder_clones(encoder); |
79e53945 | 14630 | } |
47356eb6 | 14631 | |
dde86e2d | 14632 | intel_init_pch_refclk(dev); |
270b3042 DV |
14633 | |
14634 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
14635 | } |
14636 | ||
14637 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14638 | { | |
60a5ca01 | 14639 | struct drm_device *dev = fb->dev; |
79e53945 | 14640 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 14641 | |
ef2d633e | 14642 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 14643 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 14644 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
14645 | drm_gem_object_unreference(&intel_fb->obj->base); |
14646 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14647 | kfree(intel_fb); |
14648 | } | |
14649 | ||
14650 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14651 | struct drm_file *file, |
79e53945 JB |
14652 | unsigned int *handle) |
14653 | { | |
14654 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14655 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14656 | |
cc917ab4 CW |
14657 | if (obj->userptr.mm) { |
14658 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
14659 | return -EINVAL; | |
14660 | } | |
14661 | ||
05394f39 | 14662 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14663 | } |
14664 | ||
86c98588 RV |
14665 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
14666 | struct drm_file *file, | |
14667 | unsigned flags, unsigned color, | |
14668 | struct drm_clip_rect *clips, | |
14669 | unsigned num_clips) | |
14670 | { | |
14671 | struct drm_device *dev = fb->dev; | |
14672 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
14673 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
14674 | ||
14675 | mutex_lock(&dev->struct_mutex); | |
74b4ea1e | 14676 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
14677 | mutex_unlock(&dev->struct_mutex); |
14678 | ||
14679 | return 0; | |
14680 | } | |
14681 | ||
79e53945 JB |
14682 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
14683 | .destroy = intel_user_framebuffer_destroy, | |
14684 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 14685 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
14686 | }; |
14687 | ||
b321803d DL |
14688 | static |
14689 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
14690 | uint32_t pixel_format) | |
14691 | { | |
14692 | u32 gen = INTEL_INFO(dev)->gen; | |
14693 | ||
14694 | if (gen >= 9) { | |
14695 | /* "The stride in bytes must not exceed the of the size of 8K | |
14696 | * pixels and 32K bytes." | |
14697 | */ | |
14698 | return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768); | |
666a4537 | 14699 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
b321803d DL |
14700 | return 32*1024; |
14701 | } else if (gen >= 4) { | |
14702 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14703 | return 16*1024; | |
14704 | else | |
14705 | return 32*1024; | |
14706 | } else if (gen >= 3) { | |
14707 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14708 | return 8*1024; | |
14709 | else | |
14710 | return 16*1024; | |
14711 | } else { | |
14712 | /* XXX DSPC is limited to 4k tiled */ | |
14713 | return 8*1024; | |
14714 | } | |
14715 | } | |
14716 | ||
b5ea642a DV |
14717 | static int intel_framebuffer_init(struct drm_device *dev, |
14718 | struct intel_framebuffer *intel_fb, | |
14719 | struct drm_mode_fb_cmd2 *mode_cmd, | |
14720 | struct drm_i915_gem_object *obj) | |
79e53945 | 14721 | { |
6761dd31 | 14722 | unsigned int aligned_height; |
79e53945 | 14723 | int ret; |
b321803d | 14724 | u32 pitch_limit, stride_alignment; |
79e53945 | 14725 | |
dd4916c5 DV |
14726 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
14727 | ||
2a80eada DV |
14728 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
14729 | /* Enforce that fb modifier and tiling mode match, but only for | |
14730 | * X-tiled. This is needed for FBC. */ | |
14731 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
14732 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
14733 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
14734 | return -EINVAL; | |
14735 | } | |
14736 | } else { | |
14737 | if (obj->tiling_mode == I915_TILING_X) | |
14738 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
14739 | else if (obj->tiling_mode == I915_TILING_Y) { | |
14740 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
14741 | return -EINVAL; | |
14742 | } | |
14743 | } | |
14744 | ||
9a8f0a12 TU |
14745 | /* Passed in modifier sanity checking. */ |
14746 | switch (mode_cmd->modifier[0]) { | |
14747 | case I915_FORMAT_MOD_Y_TILED: | |
14748 | case I915_FORMAT_MOD_Yf_TILED: | |
14749 | if (INTEL_INFO(dev)->gen < 9) { | |
14750 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
14751 | mode_cmd->modifier[0]); | |
14752 | return -EINVAL; | |
14753 | } | |
14754 | case DRM_FORMAT_MOD_NONE: | |
14755 | case I915_FORMAT_MOD_X_TILED: | |
14756 | break; | |
14757 | default: | |
c0f40428 JB |
14758 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14759 | mode_cmd->modifier[0]); | |
57cd6508 | 14760 | return -EINVAL; |
c16ed4be | 14761 | } |
57cd6508 | 14762 | |
b321803d DL |
14763 | stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0], |
14764 | mode_cmd->pixel_format); | |
14765 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
14766 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
14767 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 14768 | return -EINVAL; |
c16ed4be | 14769 | } |
57cd6508 | 14770 | |
b321803d DL |
14771 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
14772 | mode_cmd->pixel_format); | |
a35cdaa0 | 14773 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
14774 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
14775 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 14776 | "tiled" : "linear", |
a35cdaa0 | 14777 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 14778 | return -EINVAL; |
c16ed4be | 14779 | } |
5d7bd705 | 14780 | |
2a80eada | 14781 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
14782 | mode_cmd->pitches[0] != obj->stride) { |
14783 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
14784 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 14785 | return -EINVAL; |
c16ed4be | 14786 | } |
5d7bd705 | 14787 | |
57779d06 | 14788 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14789 | switch (mode_cmd->pixel_format) { |
57779d06 | 14790 | case DRM_FORMAT_C8: |
04b3924d VS |
14791 | case DRM_FORMAT_RGB565: |
14792 | case DRM_FORMAT_XRGB8888: | |
14793 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14794 | break; |
14795 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 14796 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
14797 | DRM_DEBUG("unsupported pixel format: %s\n", |
14798 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14799 | return -EINVAL; |
c16ed4be | 14800 | } |
57779d06 | 14801 | break; |
57779d06 | 14802 | case DRM_FORMAT_ABGR8888: |
666a4537 WB |
14803 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
14804 | INTEL_INFO(dev)->gen < 9) { | |
6c0fd451 DL |
14805 | DRM_DEBUG("unsupported pixel format: %s\n", |
14806 | drm_get_format_name(mode_cmd->pixel_format)); | |
14807 | return -EINVAL; | |
14808 | } | |
14809 | break; | |
14810 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 14811 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 14812 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 14813 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
14814 | DRM_DEBUG("unsupported pixel format: %s\n", |
14815 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14816 | return -EINVAL; |
c16ed4be | 14817 | } |
b5626747 | 14818 | break; |
7531208b | 14819 | case DRM_FORMAT_ABGR2101010: |
666a4537 | 14820 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
7531208b DL |
14821 | DRM_DEBUG("unsupported pixel format: %s\n", |
14822 | drm_get_format_name(mode_cmd->pixel_format)); | |
14823 | return -EINVAL; | |
14824 | } | |
14825 | break; | |
04b3924d VS |
14826 | case DRM_FORMAT_YUYV: |
14827 | case DRM_FORMAT_UYVY: | |
14828 | case DRM_FORMAT_YVYU: | |
14829 | case DRM_FORMAT_VYUY: | |
c16ed4be | 14830 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
14831 | DRM_DEBUG("unsupported pixel format: %s\n", |
14832 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14833 | return -EINVAL; |
c16ed4be | 14834 | } |
57cd6508 CW |
14835 | break; |
14836 | default: | |
4ee62c76 VS |
14837 | DRM_DEBUG("unsupported pixel format: %s\n", |
14838 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
14839 | return -EINVAL; |
14840 | } | |
14841 | ||
90f9a336 VS |
14842 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14843 | if (mode_cmd->offsets[0] != 0) | |
14844 | return -EINVAL; | |
14845 | ||
ec2c981e | 14846 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
14847 | mode_cmd->pixel_format, |
14848 | mode_cmd->modifier[0]); | |
53155c0a DV |
14849 | /* FIXME drm helper for size checks (especially planar formats)? */ |
14850 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
14851 | return -EINVAL; | |
14852 | ||
c7d73f6a DV |
14853 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
14854 | intel_fb->obj = obj; | |
80075d49 | 14855 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 14856 | |
79e53945 JB |
14857 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
14858 | if (ret) { | |
14859 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
14860 | return ret; | |
14861 | } | |
14862 | ||
79e53945 JB |
14863 | return 0; |
14864 | } | |
14865 | ||
79e53945 JB |
14866 | static struct drm_framebuffer * |
14867 | intel_user_framebuffer_create(struct drm_device *dev, | |
14868 | struct drm_file *filp, | |
1eb83451 | 14869 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 14870 | { |
dcb1394e | 14871 | struct drm_framebuffer *fb; |
05394f39 | 14872 | struct drm_i915_gem_object *obj; |
76dc3769 | 14873 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 14874 | |
308e5bcb | 14875 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
76dc3769 | 14876 | mode_cmd.handles[0])); |
c8725226 | 14877 | if (&obj->base == NULL) |
cce13ff7 | 14878 | return ERR_PTR(-ENOENT); |
79e53945 | 14879 | |
92907cbb | 14880 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
dcb1394e LW |
14881 | if (IS_ERR(fb)) |
14882 | drm_gem_object_unreference_unlocked(&obj->base); | |
14883 | ||
14884 | return fb; | |
79e53945 JB |
14885 | } |
14886 | ||
0695726e | 14887 | #ifndef CONFIG_DRM_FBDEV_EMULATION |
0632fef6 | 14888 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
14889 | { |
14890 | } | |
14891 | #endif | |
14892 | ||
79e53945 | 14893 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14894 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14895 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14896 | .atomic_check = intel_atomic_check, |
14897 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
14898 | .atomic_state_alloc = intel_atomic_state_alloc, |
14899 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
14900 | }; |
14901 | ||
e70236a8 JB |
14902 | /* Set up chip specific display functions */ |
14903 | static void intel_init_display(struct drm_device *dev) | |
14904 | { | |
14905 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14906 | ||
ee9300bb DV |
14907 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
14908 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
14909 | else if (IS_CHERRYVIEW(dev)) |
14910 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
14911 | else if (IS_VALLEYVIEW(dev)) |
14912 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
14913 | else if (IS_PINEVIEW(dev)) | |
14914 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
14915 | else | |
14916 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
14917 | ||
bc8d7dff DL |
14918 | if (INTEL_INFO(dev)->gen >= 9) { |
14919 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; | |
5724dbd1 DL |
14920 | dev_priv->display.get_initial_plane_config = |
14921 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14922 | dev_priv->display.crtc_compute_clock = |
14923 | haswell_crtc_compute_clock; | |
14924 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14925 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
bc8d7dff DL |
14926 | dev_priv->display.update_primary_plane = |
14927 | skylake_update_primary_plane; | |
14928 | } else if (HAS_DDI(dev)) { | |
0e8ffe1b | 14929 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14930 | dev_priv->display.get_initial_plane_config = |
14931 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14932 | dev_priv->display.crtc_compute_clock = |
14933 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14934 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14935 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
bc8d7dff DL |
14936 | dev_priv->display.update_primary_plane = |
14937 | ironlake_update_primary_plane; | |
09b4ddf9 | 14938 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 14939 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14940 | dev_priv->display.get_initial_plane_config = |
14941 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14942 | dev_priv->display.crtc_compute_clock = |
14943 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14944 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14945 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
262ca2b0 MR |
14946 | dev_priv->display.update_primary_plane = |
14947 | ironlake_update_primary_plane; | |
666a4537 | 14948 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
89b667f8 | 14949 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14950 | dev_priv->display.get_initial_plane_config = |
14951 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14952 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
14953 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14954 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
262ca2b0 MR |
14955 | dev_priv->display.update_primary_plane = |
14956 | i9xx_update_primary_plane; | |
f564048e | 14957 | } else { |
0e8ffe1b | 14958 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14959 | dev_priv->display.get_initial_plane_config = |
14960 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14961 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14962 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14963 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
262ca2b0 MR |
14964 | dev_priv->display.update_primary_plane = |
14965 | i9xx_update_primary_plane; | |
f564048e | 14966 | } |
e70236a8 | 14967 | |
e70236a8 | 14968 | /* Returns the core display clock speed */ |
ef11bdb3 | 14969 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
1652d19e VS |
14970 | dev_priv->display.get_display_clock_speed = |
14971 | skylake_get_display_clock_speed; | |
acd3f3d3 BP |
14972 | else if (IS_BROXTON(dev)) |
14973 | dev_priv->display.get_display_clock_speed = | |
14974 | broxton_get_display_clock_speed; | |
1652d19e VS |
14975 | else if (IS_BROADWELL(dev)) |
14976 | dev_priv->display.get_display_clock_speed = | |
14977 | broadwell_get_display_clock_speed; | |
14978 | else if (IS_HASWELL(dev)) | |
14979 | dev_priv->display.get_display_clock_speed = | |
14980 | haswell_get_display_clock_speed; | |
666a4537 | 14981 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
25eb05fc JB |
14982 | dev_priv->display.get_display_clock_speed = |
14983 | valleyview_get_display_clock_speed; | |
b37a6434 VS |
14984 | else if (IS_GEN5(dev)) |
14985 | dev_priv->display.get_display_clock_speed = | |
14986 | ilk_get_display_clock_speed; | |
a7c66cd8 | 14987 | else if (IS_I945G(dev) || IS_BROADWATER(dev) || |
34edce2f | 14988 | IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
e70236a8 JB |
14989 | dev_priv->display.get_display_clock_speed = |
14990 | i945_get_display_clock_speed; | |
34edce2f VS |
14991 | else if (IS_GM45(dev)) |
14992 | dev_priv->display.get_display_clock_speed = | |
14993 | gm45_get_display_clock_speed; | |
14994 | else if (IS_CRESTLINE(dev)) | |
14995 | dev_priv->display.get_display_clock_speed = | |
14996 | i965gm_get_display_clock_speed; | |
14997 | else if (IS_PINEVIEW(dev)) | |
14998 | dev_priv->display.get_display_clock_speed = | |
14999 | pnv_get_display_clock_speed; | |
15000 | else if (IS_G33(dev) || IS_G4X(dev)) | |
15001 | dev_priv->display.get_display_clock_speed = | |
15002 | g33_get_display_clock_speed; | |
e70236a8 JB |
15003 | else if (IS_I915G(dev)) |
15004 | dev_priv->display.get_display_clock_speed = | |
15005 | i915_get_display_clock_speed; | |
257a7ffc | 15006 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
15007 | dev_priv->display.get_display_clock_speed = |
15008 | i9xx_misc_get_display_clock_speed; | |
15009 | else if (IS_I915GM(dev)) | |
15010 | dev_priv->display.get_display_clock_speed = | |
15011 | i915gm_get_display_clock_speed; | |
15012 | else if (IS_I865G(dev)) | |
15013 | dev_priv->display.get_display_clock_speed = | |
15014 | i865_get_display_clock_speed; | |
f0f8a9ce | 15015 | else if (IS_I85X(dev)) |
e70236a8 | 15016 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 15017 | i85x_get_display_clock_speed; |
623e01e5 VS |
15018 | else { /* 830 */ |
15019 | WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n"); | |
e70236a8 JB |
15020 | dev_priv->display.get_display_clock_speed = |
15021 | i830_get_display_clock_speed; | |
623e01e5 | 15022 | } |
e70236a8 | 15023 | |
7c10a2b5 | 15024 | if (IS_GEN5(dev)) { |
3bb11b53 | 15025 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
15026 | } else if (IS_GEN6(dev)) { |
15027 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
15028 | } else if (IS_IVYBRIDGE(dev)) { |
15029 | /* FIXME: detect B0+ stepping and use auto training */ | |
15030 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
059b2fe9 | 15031 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 15032 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
27c329ed ML |
15033 | if (IS_BROADWELL(dev)) { |
15034 | dev_priv->display.modeset_commit_cdclk = | |
15035 | broadwell_modeset_commit_cdclk; | |
15036 | dev_priv->display.modeset_calc_cdclk = | |
15037 | broadwell_modeset_calc_cdclk; | |
15038 | } | |
666a4537 | 15039 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
27c329ed ML |
15040 | dev_priv->display.modeset_commit_cdclk = |
15041 | valleyview_modeset_commit_cdclk; | |
15042 | dev_priv->display.modeset_calc_cdclk = | |
15043 | valleyview_modeset_calc_cdclk; | |
f8437dd1 | 15044 | } else if (IS_BROXTON(dev)) { |
27c329ed ML |
15045 | dev_priv->display.modeset_commit_cdclk = |
15046 | broxton_modeset_commit_cdclk; | |
15047 | dev_priv->display.modeset_calc_cdclk = | |
15048 | broxton_modeset_calc_cdclk; | |
e70236a8 | 15049 | } |
8c9f3aaf | 15050 | |
8c9f3aaf JB |
15051 | switch (INTEL_INFO(dev)->gen) { |
15052 | case 2: | |
15053 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
15054 | break; | |
15055 | ||
15056 | case 3: | |
15057 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
15058 | break; | |
15059 | ||
15060 | case 4: | |
15061 | case 5: | |
15062 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
15063 | break; | |
15064 | ||
15065 | case 6: | |
15066 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
15067 | break; | |
7c9017e5 | 15068 | case 7: |
4e0bbc31 | 15069 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
15070 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
15071 | break; | |
830c81db | 15072 | case 9: |
ba343e02 TU |
15073 | /* Drop through - unsupported since execlist only. */ |
15074 | default: | |
15075 | /* Default just returns -ENODEV to indicate unsupported */ | |
15076 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 15077 | } |
7bd688cd | 15078 | |
e39b999a | 15079 | mutex_init(&dev_priv->pps_mutex); |
e70236a8 JB |
15080 | } |
15081 | ||
b690e96c JB |
15082 | /* |
15083 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
15084 | * resume, or other times. This quirk makes sure that's the case for | |
15085 | * affected systems. | |
15086 | */ | |
0206e353 | 15087 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
15088 | { |
15089 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15090 | ||
15091 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 15092 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
15093 | } |
15094 | ||
b6b5d049 VS |
15095 | static void quirk_pipeb_force(struct drm_device *dev) |
15096 | { | |
15097 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15098 | ||
15099 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
15100 | DRM_INFO("applying pipe b force quirk\n"); | |
15101 | } | |
15102 | ||
435793df KP |
15103 | /* |
15104 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
15105 | */ | |
15106 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
15107 | { | |
15108 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15109 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 15110 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
15111 | } |
15112 | ||
4dca20ef | 15113 | /* |
5a15ab5b CE |
15114 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
15115 | * brightness value | |
4dca20ef CE |
15116 | */ |
15117 | static void quirk_invert_brightness(struct drm_device *dev) | |
15118 | { | |
15119 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15120 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 15121 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
15122 | } |
15123 | ||
9c72cc6f SD |
15124 | /* Some VBT's incorrectly indicate no backlight is present */ |
15125 | static void quirk_backlight_present(struct drm_device *dev) | |
15126 | { | |
15127 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15128 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
15129 | DRM_INFO("applying backlight present quirk\n"); | |
15130 | } | |
15131 | ||
b690e96c JB |
15132 | struct intel_quirk { |
15133 | int device; | |
15134 | int subsystem_vendor; | |
15135 | int subsystem_device; | |
15136 | void (*hook)(struct drm_device *dev); | |
15137 | }; | |
15138 | ||
5f85f176 EE |
15139 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
15140 | struct intel_dmi_quirk { | |
15141 | void (*hook)(struct drm_device *dev); | |
15142 | const struct dmi_system_id (*dmi_id_list)[]; | |
15143 | }; | |
15144 | ||
15145 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
15146 | { | |
15147 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
15148 | return 1; | |
15149 | } | |
15150 | ||
15151 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
15152 | { | |
15153 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
15154 | { | |
15155 | .callback = intel_dmi_reverse_brightness, | |
15156 | .ident = "NCR Corporation", | |
15157 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
15158 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
15159 | }, | |
15160 | }, | |
15161 | { } /* terminating entry */ | |
15162 | }, | |
15163 | .hook = quirk_invert_brightness, | |
15164 | }, | |
15165 | }; | |
15166 | ||
c43b5634 | 15167 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
15168 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
15169 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
15170 | ||
b690e96c JB |
15171 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
15172 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
15173 | ||
5f080c0f VS |
15174 | /* 830 needs to leave pipe A & dpll A up */ |
15175 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
15176 | ||
b6b5d049 VS |
15177 | /* 830 needs to leave pipe B & dpll B up */ |
15178 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
15179 | ||
435793df KP |
15180 | /* Lenovo U160 cannot use SSC on LVDS */ |
15181 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
15182 | |
15183 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
15184 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 15185 | |
be505f64 AH |
15186 | /* Acer Aspire 5734Z must invert backlight brightness */ |
15187 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
15188 | ||
15189 | /* Acer/eMachines G725 */ | |
15190 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
15191 | ||
15192 | /* Acer/eMachines e725 */ | |
15193 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
15194 | ||
15195 | /* Acer/Packard Bell NCL20 */ | |
15196 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
15197 | ||
15198 | /* Acer Aspire 4736Z */ | |
15199 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
15200 | |
15201 | /* Acer Aspire 5336 */ | |
15202 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
15203 | |
15204 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
15205 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 15206 | |
dfb3d47b SD |
15207 | /* Acer C720 Chromebook (Core i3 4005U) */ |
15208 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
15209 | ||
b2a9601c | 15210 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
15211 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
15212 | ||
1b9448b0 JN |
15213 | /* Apple Macbook 4,1 */ |
15214 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
15215 | ||
d4967d8c SD |
15216 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
15217 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
15218 | |
15219 | /* HP Chromebook 14 (Celeron 2955U) */ | |
15220 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
15221 | |
15222 | /* Dell Chromebook 11 */ | |
15223 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
15224 | |
15225 | /* Dell Chromebook 11 (2015 version) */ | |
15226 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
15227 | }; |
15228 | ||
15229 | static void intel_init_quirks(struct drm_device *dev) | |
15230 | { | |
15231 | struct pci_dev *d = dev->pdev; | |
15232 | int i; | |
15233 | ||
15234 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
15235 | struct intel_quirk *q = &intel_quirks[i]; | |
15236 | ||
15237 | if (d->device == q->device && | |
15238 | (d->subsystem_vendor == q->subsystem_vendor || | |
15239 | q->subsystem_vendor == PCI_ANY_ID) && | |
15240 | (d->subsystem_device == q->subsystem_device || | |
15241 | q->subsystem_device == PCI_ANY_ID)) | |
15242 | q->hook(dev); | |
15243 | } | |
5f85f176 EE |
15244 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
15245 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
15246 | intel_dmi_quirks[i].hook(dev); | |
15247 | } | |
b690e96c JB |
15248 | } |
15249 | ||
9cce37f4 JB |
15250 | /* Disable the VGA plane that we never use */ |
15251 | static void i915_disable_vga(struct drm_device *dev) | |
15252 | { | |
15253 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15254 | u8 sr1; | |
f0f59a00 | 15255 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 15256 | |
2b37c616 | 15257 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 15258 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 15259 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
15260 | sr1 = inb(VGA_SR_DATA); |
15261 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
15262 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
15263 | udelay(300); | |
15264 | ||
01f5a626 | 15265 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
15266 | POSTING_READ(vga_reg); |
15267 | } | |
15268 | ||
f817586c DV |
15269 | void intel_modeset_init_hw(struct drm_device *dev) |
15270 | { | |
1a617b77 ML |
15271 | struct drm_i915_private *dev_priv = dev->dev_private; |
15272 | ||
b6283055 | 15273 | intel_update_cdclk(dev); |
1a617b77 ML |
15274 | |
15275 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; | |
15276 | ||
a8f78b58 | 15277 | intel_prepare_ddi(dev); |
f817586c | 15278 | intel_init_clock_gating(dev); |
8090c6b9 | 15279 | intel_enable_gt_powersave(dev); |
f817586c DV |
15280 | } |
15281 | ||
d93c0372 MR |
15282 | /* |
15283 | * Calculate what we think the watermarks should be for the state we've read | |
15284 | * out of the hardware and then immediately program those watermarks so that | |
15285 | * we ensure the hardware settings match our internal state. | |
15286 | * | |
15287 | * We can calculate what we think WM's should be by creating a duplicate of the | |
15288 | * current state (which was constructed during hardware readout) and running it | |
15289 | * through the atomic check code to calculate new watermark values in the | |
15290 | * state object. | |
15291 | */ | |
15292 | static void sanitize_watermarks(struct drm_device *dev) | |
15293 | { | |
15294 | struct drm_i915_private *dev_priv = to_i915(dev); | |
15295 | struct drm_atomic_state *state; | |
15296 | struct drm_crtc *crtc; | |
15297 | struct drm_crtc_state *cstate; | |
15298 | struct drm_modeset_acquire_ctx ctx; | |
15299 | int ret; | |
15300 | int i; | |
15301 | ||
15302 | /* Only supported on platforms that use atomic watermark design */ | |
15303 | if (!dev_priv->display.program_watermarks) | |
15304 | return; | |
15305 | ||
15306 | /* | |
15307 | * We need to hold connection_mutex before calling duplicate_state so | |
15308 | * that the connector loop is protected. | |
15309 | */ | |
15310 | drm_modeset_acquire_init(&ctx, 0); | |
15311 | retry: | |
15312 | ret = drm_modeset_lock(&dev->mode_config.connection_mutex, &ctx); | |
15313 | if (ret == -EDEADLK) { | |
15314 | drm_modeset_backoff(&ctx); | |
15315 | goto retry; | |
15316 | } else if (WARN_ON(ret)) { | |
15317 | return; | |
15318 | } | |
15319 | ||
15320 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
15321 | if (WARN_ON(IS_ERR(state))) | |
15322 | return; | |
15323 | ||
15324 | ret = intel_atomic_check(dev, state); | |
15325 | if (ret) { | |
15326 | /* | |
15327 | * If we fail here, it means that the hardware appears to be | |
15328 | * programmed in a way that shouldn't be possible, given our | |
15329 | * understanding of watermark requirements. This might mean a | |
15330 | * mistake in the hardware readout code or a mistake in the | |
15331 | * watermark calculations for a given platform. Raise a WARN | |
15332 | * so that this is noticeable. | |
15333 | * | |
15334 | * If this actually happens, we'll have to just leave the | |
15335 | * BIOS-programmed watermarks untouched and hope for the best. | |
15336 | */ | |
15337 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
15338 | return; | |
15339 | } | |
15340 | ||
15341 | /* Write calculated watermark values back */ | |
15342 | to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config; | |
15343 | for_each_crtc_in_state(state, crtc, cstate, i) { | |
15344 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); | |
15345 | ||
15346 | dev_priv->display.program_watermarks(cs); | |
15347 | } | |
15348 | ||
15349 | drm_atomic_state_free(state); | |
15350 | drm_modeset_drop_locks(&ctx); | |
15351 | drm_modeset_acquire_fini(&ctx); | |
15352 | } | |
15353 | ||
79e53945 JB |
15354 | void intel_modeset_init(struct drm_device *dev) |
15355 | { | |
652c393a | 15356 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 15357 | int sprite, ret; |
8cc87b75 | 15358 | enum pipe pipe; |
46f297fb | 15359 | struct intel_crtc *crtc; |
79e53945 JB |
15360 | |
15361 | drm_mode_config_init(dev); | |
15362 | ||
15363 | dev->mode_config.min_width = 0; | |
15364 | dev->mode_config.min_height = 0; | |
15365 | ||
019d96cb DA |
15366 | dev->mode_config.preferred_depth = 24; |
15367 | dev->mode_config.prefer_shadow = 1; | |
15368 | ||
25bab385 TU |
15369 | dev->mode_config.allow_fb_modifiers = true; |
15370 | ||
e6ecefaa | 15371 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 15372 | |
b690e96c JB |
15373 | intel_init_quirks(dev); |
15374 | ||
1fa61106 ED |
15375 | intel_init_pm(dev); |
15376 | ||
e3c74757 BW |
15377 | if (INTEL_INFO(dev)->num_pipes == 0) |
15378 | return; | |
15379 | ||
69f92f67 LW |
15380 | /* |
15381 | * There may be no VBT; and if the BIOS enabled SSC we can | |
15382 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
15383 | * BIOS isn't using it, don't assume it will work even if the VBT | |
15384 | * indicates as much. | |
15385 | */ | |
15386 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { | |
15387 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
15388 | DREF_SSC1_ENABLE); | |
15389 | ||
15390 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
15391 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
15392 | bios_lvds_use_ssc ? "en" : "dis", | |
15393 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
15394 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
15395 | } | |
15396 | } | |
15397 | ||
e70236a8 | 15398 | intel_init_display(dev); |
7c10a2b5 | 15399 | intel_init_audio(dev); |
e70236a8 | 15400 | |
a6c45cf0 CW |
15401 | if (IS_GEN2(dev)) { |
15402 | dev->mode_config.max_width = 2048; | |
15403 | dev->mode_config.max_height = 2048; | |
15404 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
15405 | dev->mode_config.max_width = 4096; |
15406 | dev->mode_config.max_height = 4096; | |
79e53945 | 15407 | } else { |
a6c45cf0 CW |
15408 | dev->mode_config.max_width = 8192; |
15409 | dev->mode_config.max_height = 8192; | |
79e53945 | 15410 | } |
068be561 | 15411 | |
dc41c154 VS |
15412 | if (IS_845G(dev) || IS_I865G(dev)) { |
15413 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
15414 | dev->mode_config.cursor_height = 1023; | |
15415 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
15416 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
15417 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
15418 | } else { | |
15419 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
15420 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
15421 | } | |
15422 | ||
5d4545ae | 15423 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 15424 | |
28c97730 | 15425 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
15426 | INTEL_INFO(dev)->num_pipes, |
15427 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 15428 | |
055e393f | 15429 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 15430 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 15431 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 15432 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 15433 | if (ret) |
06da8da2 | 15434 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 15435 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 15436 | } |
79e53945 JB |
15437 | } |
15438 | ||
bfa7df01 VS |
15439 | intel_update_czclk(dev_priv); |
15440 | intel_update_cdclk(dev); | |
15441 | ||
e72f9fbf | 15442 | intel_shared_dpll_init(dev); |
ee7b9f93 | 15443 | |
9cce37f4 JB |
15444 | /* Just disable it once at startup */ |
15445 | i915_disable_vga(dev); | |
79e53945 | 15446 | intel_setup_outputs(dev); |
11be49eb | 15447 | |
6e9f798d | 15448 | drm_modeset_lock_all(dev); |
043e9bda | 15449 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 15450 | drm_modeset_unlock_all(dev); |
46f297fb | 15451 | |
d3fcc808 | 15452 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
15453 | struct intel_initial_plane_config plane_config = {}; |
15454 | ||
46f297fb JB |
15455 | if (!crtc->active) |
15456 | continue; | |
15457 | ||
46f297fb | 15458 | /* |
46f297fb JB |
15459 | * Note that reserving the BIOS fb up front prevents us |
15460 | * from stuffing other stolen allocations like the ring | |
15461 | * on top. This prevents some ugliness at boot time, and | |
15462 | * can even allow for smooth boot transitions if the BIOS | |
15463 | * fb is large enough for the active pipe configuration. | |
15464 | */ | |
eeebeac5 ML |
15465 | dev_priv->display.get_initial_plane_config(crtc, |
15466 | &plane_config); | |
15467 | ||
15468 | /* | |
15469 | * If the fb is shared between multiple heads, we'll | |
15470 | * just get the first one. | |
15471 | */ | |
15472 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 15473 | } |
d93c0372 MR |
15474 | |
15475 | /* | |
15476 | * Make sure hardware watermarks really match the state we read out. | |
15477 | * Note that we need to do this after reconstructing the BIOS fb's | |
15478 | * since the watermark calculation done here will use pstate->fb. | |
15479 | */ | |
15480 | sanitize_watermarks(dev); | |
2c7111db CW |
15481 | } |
15482 | ||
7fad798e DV |
15483 | static void intel_enable_pipe_a(struct drm_device *dev) |
15484 | { | |
15485 | struct intel_connector *connector; | |
15486 | struct drm_connector *crt = NULL; | |
15487 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 15488 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
15489 | |
15490 | /* We can't just switch on the pipe A, we need to set things up with a | |
15491 | * proper mode and output configuration. As a gross hack, enable pipe A | |
15492 | * by enabling the load detect pipe once. */ | |
3a3371ff | 15493 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
15494 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
15495 | crt = &connector->base; | |
15496 | break; | |
15497 | } | |
15498 | } | |
15499 | ||
15500 | if (!crt) | |
15501 | return; | |
15502 | ||
208bf9fd | 15503 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 15504 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
15505 | } |
15506 | ||
fa555837 DV |
15507 | static bool |
15508 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15509 | { | |
7eb552ae BW |
15510 | struct drm_device *dev = crtc->base.dev; |
15511 | struct drm_i915_private *dev_priv = dev->dev_private; | |
649636ef | 15512 | u32 val; |
fa555837 | 15513 | |
7eb552ae | 15514 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
15515 | return true; |
15516 | ||
649636ef | 15517 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
15518 | |
15519 | if ((val & DISPLAY_PLANE_ENABLE) && | |
15520 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
15521 | return false; | |
15522 | ||
15523 | return true; | |
15524 | } | |
15525 | ||
02e93c35 VS |
15526 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
15527 | { | |
15528 | struct drm_device *dev = crtc->base.dev; | |
15529 | struct intel_encoder *encoder; | |
15530 | ||
15531 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
15532 | return true; | |
15533 | ||
15534 | return false; | |
15535 | } | |
15536 | ||
24929352 DV |
15537 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15538 | { | |
15539 | struct drm_device *dev = crtc->base.dev; | |
15540 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 15541 | i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder); |
24929352 | 15542 | |
24929352 | 15543 | /* Clear any frame start delays used for debugging left by the BIOS */ |
24929352 DV |
15544 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
15545 | ||
d3eaf884 | 15546 | /* restore vblank interrupts to correct state */ |
9625604c | 15547 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 15548 | if (crtc->active) { |
f9cd7b88 VS |
15549 | struct intel_plane *plane; |
15550 | ||
9625604c | 15551 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
15552 | |
15553 | /* Disable everything but the primary plane */ | |
15554 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
15555 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
15556 | continue; | |
15557 | ||
15558 | plane->disable_plane(&plane->base, &crtc->base); | |
15559 | } | |
9625604c | 15560 | } |
d3eaf884 | 15561 | |
24929352 | 15562 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
15563 | * disable the crtc (and hence change the state) if it is wrong. Note |
15564 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
15565 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
15566 | bool plane; |
15567 | ||
24929352 DV |
15568 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
15569 | crtc->base.base.id); | |
15570 | ||
15571 | /* Pipe has the wrong plane attached and the plane is active. | |
15572 | * Temporarily change the plane mapping and disable everything | |
15573 | * ... */ | |
15574 | plane = crtc->plane; | |
b70709a6 | 15575 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 15576 | crtc->plane = !plane; |
b17d48e2 | 15577 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15578 | crtc->plane = plane; |
24929352 | 15579 | } |
24929352 | 15580 | |
7fad798e DV |
15581 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
15582 | crtc->pipe == PIPE_A && !crtc->active) { | |
15583 | /* BIOS forgot to enable pipe A, this mostly happens after | |
15584 | * resume. Force-enable the pipe to fix this, the update_dpms | |
15585 | * call below we restore the pipe to the right state, but leave | |
15586 | * the required bits on. */ | |
15587 | intel_enable_pipe_a(dev); | |
15588 | } | |
15589 | ||
24929352 DV |
15590 | /* Adjust the state of the output pipe according to whether we |
15591 | * have active connectors/encoders. */ | |
02e93c35 | 15592 | if (!intel_crtc_has_encoders(crtc)) |
b17d48e2 | 15593 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15594 | |
53d9f4e9 | 15595 | if (crtc->active != crtc->base.state->active) { |
02e93c35 | 15596 | struct intel_encoder *encoder; |
24929352 DV |
15597 | |
15598 | /* This can happen either due to bugs in the get_hw_state | |
b17d48e2 ML |
15599 | * functions or because of calls to intel_crtc_disable_noatomic, |
15600 | * or because the pipe is force-enabled due to the | |
24929352 DV |
15601 | * pipe A quirk. */ |
15602 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
15603 | crtc->base.base.id, | |
83d65738 | 15604 | crtc->base.state->enable ? "enabled" : "disabled", |
24929352 DV |
15605 | crtc->active ? "enabled" : "disabled"); |
15606 | ||
4be40c98 | 15607 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0); |
49d6fa21 | 15608 | crtc->base.state->active = crtc->active; |
24929352 DV |
15609 | crtc->base.enabled = crtc->active; |
15610 | ||
15611 | /* Because we only establish the connector -> encoder -> | |
15612 | * crtc links if something is active, this means the | |
15613 | * crtc is now deactivated. Break the links. connector | |
15614 | * -> encoder links are only establish when things are | |
15615 | * actually up, hence no need to break them. */ | |
15616 | WARN_ON(crtc->active); | |
15617 | ||
2d406bb0 | 15618 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
24929352 | 15619 | encoder->base.crtc = NULL; |
24929352 | 15620 | } |
c5ab3bc0 | 15621 | |
a3ed6aad | 15622 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
15623 | /* |
15624 | * We start out with underrun reporting disabled to avoid races. | |
15625 | * For correct bookkeeping mark this on active crtcs. | |
15626 | * | |
c5ab3bc0 DV |
15627 | * Also on gmch platforms we dont have any hardware bits to |
15628 | * disable the underrun reporting. Which means we need to start | |
15629 | * out with underrun reporting disabled also on inactive pipes, | |
15630 | * since otherwise we'll complain about the garbage we read when | |
15631 | * e.g. coming up after runtime pm. | |
15632 | * | |
4cc31489 DV |
15633 | * No protection against concurrent access is required - at |
15634 | * worst a fifo underrun happens which also sets this to false. | |
15635 | */ | |
15636 | crtc->cpu_fifo_underrun_disabled = true; | |
15637 | crtc->pch_fifo_underrun_disabled = true; | |
15638 | } | |
24929352 DV |
15639 | } |
15640 | ||
15641 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15642 | { | |
15643 | struct intel_connector *connector; | |
15644 | struct drm_device *dev = encoder->base.dev; | |
873ffe69 | 15645 | bool active = false; |
24929352 DV |
15646 | |
15647 | /* We need to check both for a crtc link (meaning that the | |
15648 | * encoder is active and trying to read from a pipe) and the | |
15649 | * pipe itself being active. */ | |
15650 | bool has_active_crtc = encoder->base.crtc && | |
15651 | to_intel_crtc(encoder->base.crtc)->active; | |
15652 | ||
873ffe69 ML |
15653 | for_each_intel_connector(dev, connector) { |
15654 | if (connector->base.encoder != &encoder->base) | |
15655 | continue; | |
15656 | ||
15657 | active = true; | |
15658 | break; | |
15659 | } | |
15660 | ||
15661 | if (active && !has_active_crtc) { | |
24929352 DV |
15662 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
15663 | encoder->base.base.id, | |
8e329a03 | 15664 | encoder->base.name); |
24929352 DV |
15665 | |
15666 | /* Connector is active, but has no active pipe. This is | |
15667 | * fallout from our resume register restoring. Disable | |
15668 | * the encoder manually again. */ | |
15669 | if (encoder->base.crtc) { | |
15670 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
15671 | encoder->base.base.id, | |
8e329a03 | 15672 | encoder->base.name); |
24929352 | 15673 | encoder->disable(encoder); |
a62d1497 VS |
15674 | if (encoder->post_disable) |
15675 | encoder->post_disable(encoder); | |
24929352 | 15676 | } |
7f1950fb | 15677 | encoder->base.crtc = NULL; |
24929352 DV |
15678 | |
15679 | /* Inconsistent output/port/pipe state happens presumably due to | |
15680 | * a bug in one of the get_hw_state functions. Or someplace else | |
15681 | * in our code, like the register restore mess on resume. Clamp | |
15682 | * things to off as a safer default. */ | |
3a3371ff | 15683 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15684 | if (connector->encoder != encoder) |
15685 | continue; | |
7f1950fb EE |
15686 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
15687 | connector->base.encoder = NULL; | |
24929352 DV |
15688 | } |
15689 | } | |
15690 | /* Enabled encoders without active connectors will be fixed in | |
15691 | * the crtc fixup. */ | |
15692 | } | |
15693 | ||
04098753 | 15694 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
15695 | { |
15696 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 15697 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 15698 | |
04098753 ID |
15699 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15700 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
15701 | i915_disable_vga(dev); | |
15702 | } | |
15703 | } | |
15704 | ||
15705 | void i915_redisable_vga(struct drm_device *dev) | |
15706 | { | |
15707 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15708 | ||
8dc8a27c PZ |
15709 | /* This function can be called both from intel_modeset_setup_hw_state or |
15710 | * at a very early point in our resume sequence, where the power well | |
15711 | * structures are not yet restored. Since this function is at a very | |
15712 | * paranoid "someone might have enabled VGA while we were not looking" | |
15713 | * level, just check if the power well is enabled instead of trying to | |
15714 | * follow the "don't touch the power well if we don't need it" policy | |
15715 | * the rest of the driver uses. */ | |
f458ebbc | 15716 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15717 | return; |
15718 | ||
04098753 | 15719 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
15720 | } |
15721 | ||
f9cd7b88 | 15722 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 15723 | { |
f9cd7b88 | 15724 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 15725 | |
f9cd7b88 | 15726 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
15727 | } |
15728 | ||
f9cd7b88 VS |
15729 | /* FIXME read out full plane state for all planes */ |
15730 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 15731 | { |
b26d3ea3 | 15732 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 15733 | struct intel_plane_state *plane_state = |
b26d3ea3 | 15734 | to_intel_plane_state(primary->state); |
d032ffa0 | 15735 | |
19b8d387 | 15736 | plane_state->visible = crtc->active && |
b26d3ea3 ML |
15737 | primary_get_hw_state(to_intel_plane(primary)); |
15738 | ||
15739 | if (plane_state->visible) | |
15740 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); | |
98ec7739 VS |
15741 | } |
15742 | ||
30e984df | 15743 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
15744 | { |
15745 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15746 | enum pipe pipe; | |
24929352 DV |
15747 | struct intel_crtc *crtc; |
15748 | struct intel_encoder *encoder; | |
15749 | struct intel_connector *connector; | |
5358901f | 15750 | int i; |
24929352 | 15751 | |
565602d7 ML |
15752 | dev_priv->active_crtcs = 0; |
15753 | ||
d3fcc808 | 15754 | for_each_intel_crtc(dev, crtc) { |
565602d7 ML |
15755 | struct intel_crtc_state *crtc_state = crtc->config; |
15756 | int pixclk = 0; | |
3b117c8f | 15757 | |
565602d7 ML |
15758 | __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base); |
15759 | memset(crtc_state, 0, sizeof(*crtc_state)); | |
15760 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 15761 | |
565602d7 ML |
15762 | crtc_state->base.active = crtc_state->base.enable = |
15763 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
15764 | ||
15765 | crtc->base.enabled = crtc_state->base.enable; | |
15766 | crtc->active = crtc_state->base.active; | |
15767 | ||
15768 | if (crtc_state->base.active) { | |
15769 | dev_priv->active_crtcs |= 1 << crtc->pipe; | |
15770 | ||
15771 | if (IS_BROADWELL(dev_priv)) { | |
15772 | pixclk = ilk_pipe_pixel_rate(crtc_state); | |
15773 | ||
15774 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
15775 | if (crtc_state->ips_enabled) | |
15776 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); | |
15777 | } else if (IS_VALLEYVIEW(dev_priv) || | |
15778 | IS_CHERRYVIEW(dev_priv) || | |
15779 | IS_BROXTON(dev_priv)) | |
15780 | pixclk = crtc_state->base.adjusted_mode.crtc_clock; | |
15781 | else | |
15782 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
15783 | } | |
15784 | ||
15785 | dev_priv->min_pixclk[crtc->pipe] = pixclk; | |
b70709a6 | 15786 | |
f9cd7b88 | 15787 | readout_plane_state(crtc); |
24929352 DV |
15788 | |
15789 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
15790 | crtc->base.base.id, | |
15791 | crtc->active ? "enabled" : "disabled"); | |
15792 | } | |
15793 | ||
5358901f DV |
15794 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15795 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15796 | ||
3e369b76 ACO |
15797 | pll->on = pll->get_hw_state(dev_priv, pll, |
15798 | &pll->config.hw_state); | |
5358901f | 15799 | pll->active = 0; |
3e369b76 | 15800 | pll->config.crtc_mask = 0; |
d3fcc808 | 15801 | for_each_intel_crtc(dev, crtc) { |
1e6f2ddc | 15802 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
5358901f | 15803 | pll->active++; |
3e369b76 | 15804 | pll->config.crtc_mask |= 1 << crtc->pipe; |
1e6f2ddc | 15805 | } |
5358901f | 15806 | } |
5358901f | 15807 | |
1e6f2ddc | 15808 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 15809 | pll->name, pll->config.crtc_mask, pll->on); |
bd2bb1b9 | 15810 | |
3e369b76 | 15811 | if (pll->config.crtc_mask) |
bd2bb1b9 | 15812 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
15813 | } |
15814 | ||
b2784e15 | 15815 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15816 | pipe = 0; |
15817 | ||
15818 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
15819 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15820 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 15821 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
15822 | } else { |
15823 | encoder->base.crtc = NULL; | |
15824 | } | |
15825 | ||
6f2bcceb | 15826 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 15827 | encoder->base.base.id, |
8e329a03 | 15828 | encoder->base.name, |
24929352 | 15829 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 15830 | pipe_name(pipe)); |
24929352 DV |
15831 | } |
15832 | ||
3a3371ff | 15833 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15834 | if (connector->get_hw_state(connector)) { |
15835 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
24929352 DV |
15836 | connector->base.encoder = &connector->encoder->base; |
15837 | } else { | |
15838 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15839 | connector->base.encoder = NULL; | |
15840 | } | |
15841 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
15842 | connector->base.base.id, | |
c23cc417 | 15843 | connector->base.name, |
24929352 DV |
15844 | connector->base.encoder ? "enabled" : "disabled"); |
15845 | } | |
7f4c6284 VS |
15846 | |
15847 | for_each_intel_crtc(dev, crtc) { | |
15848 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
15849 | ||
15850 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
15851 | if (crtc->base.state->active) { | |
15852 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
15853 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
15854 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
15855 | ||
15856 | /* | |
15857 | * The initial mode needs to be set in order to keep | |
15858 | * the atomic core happy. It wants a valid mode if the | |
15859 | * crtc's enabled, so we do the above call. | |
15860 | * | |
15861 | * At this point some state updated by the connectors | |
15862 | * in their ->detect() callback has not run yet, so | |
15863 | * no recalculation can be done yet. | |
15864 | * | |
15865 | * Even if we could do a recalculation and modeset | |
15866 | * right now it would cause a double modeset if | |
15867 | * fbdev or userspace chooses a different initial mode. | |
15868 | * | |
15869 | * If that happens, someone indicated they wanted a | |
15870 | * mode change, which means it's safe to do a full | |
15871 | * recalculation. | |
15872 | */ | |
15873 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
15874 | |
15875 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
15876 | update_scanline_offset(crtc); | |
7f4c6284 VS |
15877 | } |
15878 | } | |
30e984df DV |
15879 | } |
15880 | ||
043e9bda ML |
15881 | /* Scan out the current hw modeset state, |
15882 | * and sanitizes it to the current state | |
15883 | */ | |
15884 | static void | |
15885 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df DV |
15886 | { |
15887 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15888 | enum pipe pipe; | |
30e984df DV |
15889 | struct intel_crtc *crtc; |
15890 | struct intel_encoder *encoder; | |
35c95375 | 15891 | int i; |
30e984df DV |
15892 | |
15893 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
15894 | |
15895 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 15896 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15897 | intel_sanitize_encoder(encoder); |
15898 | } | |
15899 | ||
055e393f | 15900 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
15901 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15902 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
15903 | intel_dump_pipe_config(crtc, crtc->config, |
15904 | "[setup_hw_state]"); | |
24929352 | 15905 | } |
9a935856 | 15906 | |
d29b2f9d ACO |
15907 | intel_modeset_update_connector_atomic_state(dev); |
15908 | ||
35c95375 DV |
15909 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15910 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15911 | ||
15912 | if (!pll->on || pll->active) | |
15913 | continue; | |
15914 | ||
15915 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15916 | ||
15917 | pll->disable(dev_priv, pll); | |
15918 | pll->on = false; | |
15919 | } | |
15920 | ||
666a4537 | 15921 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6eb1a681 VS |
15922 | vlv_wm_get_hw_state(dev); |
15923 | else if (IS_GEN9(dev)) | |
3078999f PB |
15924 | skl_wm_get_hw_state(dev); |
15925 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 | 15926 | ilk_wm_get_hw_state(dev); |
292b990e ML |
15927 | |
15928 | for_each_intel_crtc(dev, crtc) { | |
15929 | unsigned long put_domains; | |
15930 | ||
15931 | put_domains = modeset_get_crtc_power_domains(&crtc->base); | |
15932 | if (WARN_ON(put_domains)) | |
15933 | modeset_put_power_domains(dev_priv, put_domains); | |
15934 | } | |
15935 | intel_display_set_init_power(dev_priv, false); | |
043e9bda | 15936 | } |
7d0bc1ea | 15937 | |
043e9bda ML |
15938 | void intel_display_resume(struct drm_device *dev) |
15939 | { | |
15940 | struct drm_atomic_state *state = drm_atomic_state_alloc(dev); | |
15941 | struct intel_connector *conn; | |
15942 | struct intel_plane *plane; | |
15943 | struct drm_crtc *crtc; | |
15944 | int ret; | |
f30da187 | 15945 | |
043e9bda ML |
15946 | if (!state) |
15947 | return; | |
15948 | ||
15949 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
15950 | ||
15951 | /* preserve complete old state, including dpll */ | |
15952 | intel_atomic_get_shared_dpll_state(state); | |
15953 | ||
15954 | for_each_crtc(dev, crtc) { | |
15955 | struct drm_crtc_state *crtc_state = | |
15956 | drm_atomic_get_crtc_state(state, crtc); | |
15957 | ||
15958 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
15959 | if (ret) | |
15960 | goto err; | |
15961 | ||
15962 | /* force a restore */ | |
15963 | crtc_state->mode_changed = true; | |
45e2b5f6 | 15964 | } |
8af6cf88 | 15965 | |
043e9bda ML |
15966 | for_each_intel_plane(dev, plane) { |
15967 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base)); | |
15968 | if (ret) | |
15969 | goto err; | |
15970 | } | |
15971 | ||
15972 | for_each_intel_connector(dev, conn) { | |
15973 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base)); | |
15974 | if (ret) | |
15975 | goto err; | |
15976 | } | |
15977 | ||
15978 | intel_modeset_setup_hw_state(dev); | |
15979 | ||
15980 | i915_redisable_vga(dev); | |
74c090b1 | 15981 | ret = drm_atomic_commit(state); |
043e9bda ML |
15982 | if (!ret) |
15983 | return; | |
15984 | ||
15985 | err: | |
15986 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
15987 | drm_atomic_state_free(state); | |
2c7111db CW |
15988 | } |
15989 | ||
15990 | void intel_modeset_gem_init(struct drm_device *dev) | |
15991 | { | |
484b41dd | 15992 | struct drm_crtc *c; |
2ff8fde1 | 15993 | struct drm_i915_gem_object *obj; |
e0d6149b | 15994 | int ret; |
484b41dd | 15995 | |
ae48434c ID |
15996 | mutex_lock(&dev->struct_mutex); |
15997 | intel_init_gt_powersave(dev); | |
15998 | mutex_unlock(&dev->struct_mutex); | |
15999 | ||
1833b134 | 16000 | intel_modeset_init_hw(dev); |
02e792fb DV |
16001 | |
16002 | intel_setup_overlay(dev); | |
484b41dd JB |
16003 | |
16004 | /* | |
16005 | * Make sure any fbs we allocated at startup are properly | |
16006 | * pinned & fenced. When we do the allocation it's too early | |
16007 | * for this. | |
16008 | */ | |
70e1e0ec | 16009 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
16010 | obj = intel_fb_obj(c->primary->fb); |
16011 | if (obj == NULL) | |
484b41dd JB |
16012 | continue; |
16013 | ||
e0d6149b TU |
16014 | mutex_lock(&dev->struct_mutex); |
16015 | ret = intel_pin_and_fence_fb_obj(c->primary, | |
16016 | c->primary->fb, | |
7580d774 | 16017 | c->primary->state); |
e0d6149b TU |
16018 | mutex_unlock(&dev->struct_mutex); |
16019 | if (ret) { | |
484b41dd JB |
16020 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
16021 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
16022 | drm_framebuffer_unreference(c->primary->fb); |
16023 | c->primary->fb = NULL; | |
36750f28 | 16024 | c->primary->crtc = c->primary->state->crtc = NULL; |
afd65eb4 | 16025 | update_state_fb(c->primary); |
36750f28 | 16026 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
16027 | } |
16028 | } | |
0962c3c9 VS |
16029 | |
16030 | intel_backlight_register(dev); | |
79e53945 JB |
16031 | } |
16032 | ||
4932e2c3 ID |
16033 | void intel_connector_unregister(struct intel_connector *intel_connector) |
16034 | { | |
16035 | struct drm_connector *connector = &intel_connector->base; | |
16036 | ||
16037 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 16038 | drm_connector_unregister(connector); |
4932e2c3 ID |
16039 | } |
16040 | ||
79e53945 JB |
16041 | void intel_modeset_cleanup(struct drm_device *dev) |
16042 | { | |
652c393a | 16043 | struct drm_i915_private *dev_priv = dev->dev_private; |
19c8054c | 16044 | struct intel_connector *connector; |
652c393a | 16045 | |
2eb5252e ID |
16046 | intel_disable_gt_powersave(dev); |
16047 | ||
0962c3c9 VS |
16048 | intel_backlight_unregister(dev); |
16049 | ||
fd0c0642 DV |
16050 | /* |
16051 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 16052 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
16053 | * experience fancy races otherwise. |
16054 | */ | |
2aeb7d3a | 16055 | intel_irq_uninstall(dev_priv); |
eb21b92b | 16056 | |
fd0c0642 DV |
16057 | /* |
16058 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
16059 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
16060 | */ | |
f87ea761 | 16061 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 16062 | |
723bfd70 JB |
16063 | intel_unregister_dsm_handler(); |
16064 | ||
7733b49b | 16065 | intel_fbc_disable(dev_priv); |
69341a5e | 16066 | |
1630fe75 CW |
16067 | /* flush any delayed tasks or pending work */ |
16068 | flush_scheduled_work(); | |
16069 | ||
db31af1d | 16070 | /* destroy the backlight and sysfs files before encoders/connectors */ |
19c8054c JN |
16071 | for_each_intel_connector(dev, connector) |
16072 | connector->unregister(connector); | |
d9255d57 | 16073 | |
79e53945 | 16074 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
16075 | |
16076 | intel_cleanup_overlay(dev); | |
ae48434c ID |
16077 | |
16078 | mutex_lock(&dev->struct_mutex); | |
16079 | intel_cleanup_gt_powersave(dev); | |
16080 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
16081 | } |
16082 | ||
f1c79df3 ZW |
16083 | /* |
16084 | * Return which encoder is currently attached for connector. | |
16085 | */ | |
df0e9248 | 16086 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 16087 | { |
df0e9248 CW |
16088 | return &intel_attached_encoder(connector)->base; |
16089 | } | |
f1c79df3 | 16090 | |
df0e9248 CW |
16091 | void intel_connector_attach_encoder(struct intel_connector *connector, |
16092 | struct intel_encoder *encoder) | |
16093 | { | |
16094 | connector->encoder = encoder; | |
16095 | drm_mode_connector_attach_encoder(&connector->base, | |
16096 | &encoder->base); | |
79e53945 | 16097 | } |
28d52043 DA |
16098 | |
16099 | /* | |
16100 | * set vga decode state - true == enable VGA decode | |
16101 | */ | |
16102 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
16103 | { | |
16104 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 16105 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
16106 | u16 gmch_ctrl; |
16107 | ||
75fa041d CW |
16108 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
16109 | DRM_ERROR("failed to read control word\n"); | |
16110 | return -EIO; | |
16111 | } | |
16112 | ||
c0cc8a55 CW |
16113 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
16114 | return 0; | |
16115 | ||
28d52043 DA |
16116 | if (state) |
16117 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
16118 | else | |
16119 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
16120 | |
16121 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
16122 | DRM_ERROR("failed to write control word\n"); | |
16123 | return -EIO; | |
16124 | } | |
16125 | ||
28d52043 DA |
16126 | return 0; |
16127 | } | |
c4a1d9e4 | 16128 | |
c4a1d9e4 | 16129 | struct intel_display_error_state { |
ff57f1b0 PZ |
16130 | |
16131 | u32 power_well_driver; | |
16132 | ||
63b66e5b CW |
16133 | int num_transcoders; |
16134 | ||
c4a1d9e4 CW |
16135 | struct intel_cursor_error_state { |
16136 | u32 control; | |
16137 | u32 position; | |
16138 | u32 base; | |
16139 | u32 size; | |
52331309 | 16140 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16141 | |
16142 | struct intel_pipe_error_state { | |
ddf9c536 | 16143 | bool power_domain_on; |
c4a1d9e4 | 16144 | u32 source; |
f301b1e1 | 16145 | u32 stat; |
52331309 | 16146 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16147 | |
16148 | struct intel_plane_error_state { | |
16149 | u32 control; | |
16150 | u32 stride; | |
16151 | u32 size; | |
16152 | u32 pos; | |
16153 | u32 addr; | |
16154 | u32 surface; | |
16155 | u32 tile_offset; | |
52331309 | 16156 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
16157 | |
16158 | struct intel_transcoder_error_state { | |
ddf9c536 | 16159 | bool power_domain_on; |
63b66e5b CW |
16160 | enum transcoder cpu_transcoder; |
16161 | ||
16162 | u32 conf; | |
16163 | ||
16164 | u32 htotal; | |
16165 | u32 hblank; | |
16166 | u32 hsync; | |
16167 | u32 vtotal; | |
16168 | u32 vblank; | |
16169 | u32 vsync; | |
16170 | } transcoder[4]; | |
c4a1d9e4 CW |
16171 | }; |
16172 | ||
16173 | struct intel_display_error_state * | |
16174 | intel_display_capture_error_state(struct drm_device *dev) | |
16175 | { | |
fbee40df | 16176 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 16177 | struct intel_display_error_state *error; |
63b66e5b CW |
16178 | int transcoders[] = { |
16179 | TRANSCODER_A, | |
16180 | TRANSCODER_B, | |
16181 | TRANSCODER_C, | |
16182 | TRANSCODER_EDP, | |
16183 | }; | |
c4a1d9e4 CW |
16184 | int i; |
16185 | ||
63b66e5b CW |
16186 | if (INTEL_INFO(dev)->num_pipes == 0) |
16187 | return NULL; | |
16188 | ||
9d1cb914 | 16189 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
16190 | if (error == NULL) |
16191 | return NULL; | |
16192 | ||
190be112 | 16193 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
16194 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
16195 | ||
055e393f | 16196 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 16197 | error->pipe[i].power_domain_on = |
f458ebbc DV |
16198 | __intel_display_power_is_enabled(dev_priv, |
16199 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 16200 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
16201 | continue; |
16202 | ||
5efb3e28 VS |
16203 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
16204 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
16205 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
16206 | |
16207 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
16208 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 16209 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 16210 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
16211 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
16212 | } | |
ca291363 PZ |
16213 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
16214 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
16215 | if (INTEL_INFO(dev)->gen >= 4) { |
16216 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
16217 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
16218 | } | |
16219 | ||
c4a1d9e4 | 16220 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 16221 | |
3abfce77 | 16222 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 16223 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
16224 | } |
16225 | ||
16226 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
16227 | if (HAS_DDI(dev_priv->dev)) | |
16228 | error->num_transcoders++; /* Account for eDP. */ | |
16229 | ||
16230 | for (i = 0; i < error->num_transcoders; i++) { | |
16231 | enum transcoder cpu_transcoder = transcoders[i]; | |
16232 | ||
ddf9c536 | 16233 | error->transcoder[i].power_domain_on = |
f458ebbc | 16234 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 16235 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 16236 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
16237 | continue; |
16238 | ||
63b66e5b CW |
16239 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
16240 | ||
16241 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
16242 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
16243 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
16244 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
16245 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
16246 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
16247 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
16248 | } |
16249 | ||
16250 | return error; | |
16251 | } | |
16252 | ||
edc3d884 MK |
16253 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
16254 | ||
c4a1d9e4 | 16255 | void |
edc3d884 | 16256 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
16257 | struct drm_device *dev, |
16258 | struct intel_display_error_state *error) | |
16259 | { | |
055e393f | 16260 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
16261 | int i; |
16262 | ||
63b66e5b CW |
16263 | if (!error) |
16264 | return; | |
16265 | ||
edc3d884 | 16266 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 16267 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 16268 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 16269 | error->power_well_driver); |
055e393f | 16270 | for_each_pipe(dev_priv, i) { |
edc3d884 | 16271 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
16272 | err_printf(m, " Power: %s\n", |
16273 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 16274 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 16275 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
16276 | |
16277 | err_printf(m, "Plane [%d]:\n", i); | |
16278 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
16279 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 16280 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
16281 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
16282 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 16283 | } |
4b71a570 | 16284 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 16285 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 16286 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
16287 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
16288 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
16289 | } |
16290 | ||
edc3d884 MK |
16291 | err_printf(m, "Cursor [%d]:\n", i); |
16292 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
16293 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
16294 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 16295 | } |
63b66e5b CW |
16296 | |
16297 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 16298 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 16299 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
16300 | err_printf(m, " Power: %s\n", |
16301 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
16302 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
16303 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
16304 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
16305 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
16306 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
16307 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
16308 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
16309 | } | |
c4a1d9e4 | 16310 | } |
e2fcdaa9 VS |
16311 | |
16312 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) | |
16313 | { | |
16314 | struct intel_crtc *crtc; | |
16315 | ||
16316 | for_each_intel_crtc(dev, crtc) { | |
16317 | struct intel_unpin_work *work; | |
e2fcdaa9 | 16318 | |
5e2d7afc | 16319 | spin_lock_irq(&dev->event_lock); |
e2fcdaa9 VS |
16320 | |
16321 | work = crtc->unpin_work; | |
16322 | ||
16323 | if (work && work->event && | |
16324 | work->event->base.file_priv == file) { | |
16325 | kfree(work->event); | |
16326 | work->event = NULL; | |
16327 | } | |
16328 | ||
5e2d7afc | 16329 | spin_unlock_irq(&dev->event_lock); |
e2fcdaa9 VS |
16330 | } |
16331 | } |