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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
5d723d7a | 37 | #include "intel_frontbuffer.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
79e53945 | 39 | #include "i915_drv.h" |
57822dc6 | 40 | #include "i915_gem_clflush.h" |
db18b6a6 | 41 | #include "intel_dsi.h" |
e5510fac | 42 | #include "i915_trace.h" |
319c1d42 | 43 | #include <drm/drm_atomic.h> |
c196e1d6 | 44 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
45 | #include <drm/drm_dp_helper.h> |
46 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
47 | #include <drm/drm_plane_helper.h> |
48 | #include <drm/drm_rect.h> | |
c0f372b3 | 49 | #include <linux/dma_remapping.h> |
fd8e058a | 50 | #include <linux/reservation.h> |
79e53945 | 51 | |
465c120c | 52 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 53 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
54 | DRM_FORMAT_C8, |
55 | DRM_FORMAT_RGB565, | |
465c120c | 56 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 57 | DRM_FORMAT_XRGB8888, |
465c120c MR |
58 | }; |
59 | ||
60 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 61 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
62 | DRM_FORMAT_C8, |
63 | DRM_FORMAT_RGB565, | |
64 | DRM_FORMAT_XRGB8888, | |
65 | DRM_FORMAT_XBGR8888, | |
66 | DRM_FORMAT_XRGB2101010, | |
67 | DRM_FORMAT_XBGR2101010, | |
68 | }; | |
69 | ||
70 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
71 | DRM_FORMAT_C8, |
72 | DRM_FORMAT_RGB565, | |
73 | DRM_FORMAT_XRGB8888, | |
465c120c | 74 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 75 | DRM_FORMAT_ARGB8888, |
465c120c MR |
76 | DRM_FORMAT_ABGR8888, |
77 | DRM_FORMAT_XRGB2101010, | |
465c120c | 78 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
79 | DRM_FORMAT_YUYV, |
80 | DRM_FORMAT_YVYU, | |
81 | DRM_FORMAT_UYVY, | |
82 | DRM_FORMAT_VYUY, | |
465c120c MR |
83 | }; |
84 | ||
3d7d6510 MR |
85 | /* Cursor formats */ |
86 | static const uint32_t intel_cursor_formats[] = { | |
87 | DRM_FORMAT_ARGB8888, | |
88 | }; | |
89 | ||
f1f644dc | 90 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 91 | struct intel_crtc_state *pipe_config); |
18442d08 | 92 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 93 | struct intel_crtc_state *pipe_config); |
f1f644dc | 94 | |
24dbf51a CW |
95 | static int intel_framebuffer_init(struct intel_framebuffer *ifb, |
96 | struct drm_i915_gem_object *obj, | |
97 | struct drm_mode_fb_cmd2 *mode_cmd); | |
5b18e57c DV |
98 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
99 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
bc58be60 | 100 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc); |
29407aab | 101 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
102 | struct intel_link_m_n *m_n, |
103 | struct intel_link_m_n *m2_n2); | |
29407aab | 104 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 | 105 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
391bf048 | 106 | static void haswell_set_pipemisc(struct drm_crtc *crtc); |
d288f65f | 107 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 108 | const struct intel_crtc_state *pipe_config); |
d288f65f | 109 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 110 | const struct intel_crtc_state *pipe_config); |
5a21b665 DV |
111 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
112 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
1c74eeaf NM |
113 | static void intel_crtc_init_scalers(struct intel_crtc *crtc, |
114 | struct intel_crtc_state *crtc_state); | |
bfd16b2a ML |
115 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
116 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
117 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
aecd36b8 VS |
118 | static void intel_modeset_setup_hw_state(struct drm_device *dev, |
119 | struct drm_modeset_acquire_ctx *ctx); | |
2622a081 | 120 | static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); |
e7457a9a | 121 | |
d4906093 | 122 | struct intel_limit { |
4c5def93 ACO |
123 | struct { |
124 | int min, max; | |
125 | } dot, vco, n, m, m1, m2, p, p1; | |
126 | ||
127 | struct { | |
128 | int dot_limit; | |
129 | int p2_slow, p2_fast; | |
130 | } p2; | |
d4906093 | 131 | }; |
79e53945 | 132 | |
bfa7df01 | 133 | /* returns HPLL frequency in kHz */ |
49cd97a3 | 134 | int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) |
bfa7df01 VS |
135 | { |
136 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
137 | ||
138 | /* Obtain SKU information */ | |
139 | mutex_lock(&dev_priv->sb_lock); | |
140 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
141 | CCK_FUSE_HPLL_FREQ_MASK; | |
142 | mutex_unlock(&dev_priv->sb_lock); | |
143 | ||
144 | return vco_freq[hpll_freq] * 1000; | |
145 | } | |
146 | ||
c30fec65 VS |
147 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
148 | const char *name, u32 reg, int ref_freq) | |
bfa7df01 VS |
149 | { |
150 | u32 val; | |
151 | int divider; | |
152 | ||
bfa7df01 VS |
153 | mutex_lock(&dev_priv->sb_lock); |
154 | val = vlv_cck_read(dev_priv, reg); | |
155 | mutex_unlock(&dev_priv->sb_lock); | |
156 | ||
157 | divider = val & CCK_FREQUENCY_VALUES; | |
158 | ||
159 | WARN((val & CCK_FREQUENCY_STATUS) != | |
160 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
161 | "%s change in progress\n", name); | |
162 | ||
c30fec65 VS |
163 | return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); |
164 | } | |
165 | ||
7ff89ca2 VS |
166 | int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, |
167 | const char *name, u32 reg) | |
c30fec65 VS |
168 | { |
169 | if (dev_priv->hpll_freq == 0) | |
49cd97a3 | 170 | dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); |
c30fec65 VS |
171 | |
172 | return vlv_get_cck_clock(dev_priv, name, reg, | |
173 | dev_priv->hpll_freq); | |
bfa7df01 VS |
174 | } |
175 | ||
bfa7df01 VS |
176 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
177 | { | |
666a4537 | 178 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
179 | return; |
180 | ||
181 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
182 | CCK_CZ_CLOCK_CONTROL); | |
183 | ||
184 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
185 | } | |
186 | ||
021357ac | 187 | static inline u32 /* units of 100MHz */ |
21a727b3 VS |
188 | intel_fdi_link_freq(struct drm_i915_private *dev_priv, |
189 | const struct intel_crtc_state *pipe_config) | |
021357ac | 190 | { |
21a727b3 VS |
191 | if (HAS_DDI(dev_priv)) |
192 | return pipe_config->port_clock; /* SPLL */ | |
193 | else if (IS_GEN5(dev_priv)) | |
194 | return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; | |
e3b247da | 195 | else |
21a727b3 | 196 | return 270000; |
021357ac CW |
197 | } |
198 | ||
1b6f4958 | 199 | static const struct intel_limit intel_limits_i8xx_dac = { |
0206e353 | 200 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 201 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 202 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
203 | .m = { .min = 96, .max = 140 }, |
204 | .m1 = { .min = 18, .max = 26 }, | |
205 | .m2 = { .min = 6, .max = 16 }, | |
206 | .p = { .min = 4, .max = 128 }, | |
207 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
208 | .p2 = { .dot_limit = 165000, |
209 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
210 | }; |
211 | ||
1b6f4958 | 212 | static const struct intel_limit intel_limits_i8xx_dvo = { |
5d536e28 | 213 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 214 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 215 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
216 | .m = { .min = 96, .max = 140 }, |
217 | .m1 = { .min = 18, .max = 26 }, | |
218 | .m2 = { .min = 6, .max = 16 }, | |
219 | .p = { .min = 4, .max = 128 }, | |
220 | .p1 = { .min = 2, .max = 33 }, | |
221 | .p2 = { .dot_limit = 165000, | |
222 | .p2_slow = 4, .p2_fast = 4 }, | |
223 | }; | |
224 | ||
1b6f4958 | 225 | static const struct intel_limit intel_limits_i8xx_lvds = { |
0206e353 | 226 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 227 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 228 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
229 | .m = { .min = 96, .max = 140 }, |
230 | .m1 = { .min = 18, .max = 26 }, | |
231 | .m2 = { .min = 6, .max = 16 }, | |
232 | .p = { .min = 4, .max = 128 }, | |
233 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
234 | .p2 = { .dot_limit = 165000, |
235 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 236 | }; |
273e27ca | 237 | |
1b6f4958 | 238 | static const struct intel_limit intel_limits_i9xx_sdvo = { |
0206e353 AJ |
239 | .dot = { .min = 20000, .max = 400000 }, |
240 | .vco = { .min = 1400000, .max = 2800000 }, | |
241 | .n = { .min = 1, .max = 6 }, | |
242 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
243 | .m1 = { .min = 8, .max = 18 }, |
244 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
245 | .p = { .min = 5, .max = 80 }, |
246 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
247 | .p2 = { .dot_limit = 200000, |
248 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
249 | }; |
250 | ||
1b6f4958 | 251 | static const struct intel_limit intel_limits_i9xx_lvds = { |
0206e353 AJ |
252 | .dot = { .min = 20000, .max = 400000 }, |
253 | .vco = { .min = 1400000, .max = 2800000 }, | |
254 | .n = { .min = 1, .max = 6 }, | |
255 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
256 | .m1 = { .min = 8, .max = 18 }, |
257 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
258 | .p = { .min = 7, .max = 98 }, |
259 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
260 | .p2 = { .dot_limit = 112000, |
261 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
262 | }; |
263 | ||
273e27ca | 264 | |
1b6f4958 | 265 | static const struct intel_limit intel_limits_g4x_sdvo = { |
273e27ca EA |
266 | .dot = { .min = 25000, .max = 270000 }, |
267 | .vco = { .min = 1750000, .max = 3500000}, | |
268 | .n = { .min = 1, .max = 4 }, | |
269 | .m = { .min = 104, .max = 138 }, | |
270 | .m1 = { .min = 17, .max = 23 }, | |
271 | .m2 = { .min = 5, .max = 11 }, | |
272 | .p = { .min = 10, .max = 30 }, | |
273 | .p1 = { .min = 1, .max = 3}, | |
274 | .p2 = { .dot_limit = 270000, | |
275 | .p2_slow = 10, | |
276 | .p2_fast = 10 | |
044c7c41 | 277 | }, |
e4b36699 KP |
278 | }; |
279 | ||
1b6f4958 | 280 | static const struct intel_limit intel_limits_g4x_hdmi = { |
273e27ca EA |
281 | .dot = { .min = 22000, .max = 400000 }, |
282 | .vco = { .min = 1750000, .max = 3500000}, | |
283 | .n = { .min = 1, .max = 4 }, | |
284 | .m = { .min = 104, .max = 138 }, | |
285 | .m1 = { .min = 16, .max = 23 }, | |
286 | .m2 = { .min = 5, .max = 11 }, | |
287 | .p = { .min = 5, .max = 80 }, | |
288 | .p1 = { .min = 1, .max = 8}, | |
289 | .p2 = { .dot_limit = 165000, | |
290 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
291 | }; |
292 | ||
1b6f4958 | 293 | static const struct intel_limit intel_limits_g4x_single_channel_lvds = { |
273e27ca EA |
294 | .dot = { .min = 20000, .max = 115000 }, |
295 | .vco = { .min = 1750000, .max = 3500000 }, | |
296 | .n = { .min = 1, .max = 3 }, | |
297 | .m = { .min = 104, .max = 138 }, | |
298 | .m1 = { .min = 17, .max = 23 }, | |
299 | .m2 = { .min = 5, .max = 11 }, | |
300 | .p = { .min = 28, .max = 112 }, | |
301 | .p1 = { .min = 2, .max = 8 }, | |
302 | .p2 = { .dot_limit = 0, | |
303 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 304 | }, |
e4b36699 KP |
305 | }; |
306 | ||
1b6f4958 | 307 | static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { |
273e27ca EA |
308 | .dot = { .min = 80000, .max = 224000 }, |
309 | .vco = { .min = 1750000, .max = 3500000 }, | |
310 | .n = { .min = 1, .max = 3 }, | |
311 | .m = { .min = 104, .max = 138 }, | |
312 | .m1 = { .min = 17, .max = 23 }, | |
313 | .m2 = { .min = 5, .max = 11 }, | |
314 | .p = { .min = 14, .max = 42 }, | |
315 | .p1 = { .min = 2, .max = 6 }, | |
316 | .p2 = { .dot_limit = 0, | |
317 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 318 | }, |
e4b36699 KP |
319 | }; |
320 | ||
1b6f4958 | 321 | static const struct intel_limit intel_limits_pineview_sdvo = { |
0206e353 AJ |
322 | .dot = { .min = 20000, .max = 400000}, |
323 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 324 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
325 | .n = { .min = 3, .max = 6 }, |
326 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 327 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
328 | .m1 = { .min = 0, .max = 0 }, |
329 | .m2 = { .min = 0, .max = 254 }, | |
330 | .p = { .min = 5, .max = 80 }, | |
331 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
332 | .p2 = { .dot_limit = 200000, |
333 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
334 | }; |
335 | ||
1b6f4958 | 336 | static const struct intel_limit intel_limits_pineview_lvds = { |
0206e353 AJ |
337 | .dot = { .min = 20000, .max = 400000 }, |
338 | .vco = { .min = 1700000, .max = 3500000 }, | |
339 | .n = { .min = 3, .max = 6 }, | |
340 | .m = { .min = 2, .max = 256 }, | |
341 | .m1 = { .min = 0, .max = 0 }, | |
342 | .m2 = { .min = 0, .max = 254 }, | |
343 | .p = { .min = 7, .max = 112 }, | |
344 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
345 | .p2 = { .dot_limit = 112000, |
346 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
347 | }; |
348 | ||
273e27ca EA |
349 | /* Ironlake / Sandybridge |
350 | * | |
351 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
352 | * the range value for them is (actual_value - 2). | |
353 | */ | |
1b6f4958 | 354 | static const struct intel_limit intel_limits_ironlake_dac = { |
273e27ca EA |
355 | .dot = { .min = 25000, .max = 350000 }, |
356 | .vco = { .min = 1760000, .max = 3510000 }, | |
357 | .n = { .min = 1, .max = 5 }, | |
358 | .m = { .min = 79, .max = 127 }, | |
359 | .m1 = { .min = 12, .max = 22 }, | |
360 | .m2 = { .min = 5, .max = 9 }, | |
361 | .p = { .min = 5, .max = 80 }, | |
362 | .p1 = { .min = 1, .max = 8 }, | |
363 | .p2 = { .dot_limit = 225000, | |
364 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
365 | }; |
366 | ||
1b6f4958 | 367 | static const struct intel_limit intel_limits_ironlake_single_lvds = { |
273e27ca EA |
368 | .dot = { .min = 25000, .max = 350000 }, |
369 | .vco = { .min = 1760000, .max = 3510000 }, | |
370 | .n = { .min = 1, .max = 3 }, | |
371 | .m = { .min = 79, .max = 118 }, | |
372 | .m1 = { .min = 12, .max = 22 }, | |
373 | .m2 = { .min = 5, .max = 9 }, | |
374 | .p = { .min = 28, .max = 112 }, | |
375 | .p1 = { .min = 2, .max = 8 }, | |
376 | .p2 = { .dot_limit = 225000, | |
377 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
378 | }; |
379 | ||
1b6f4958 | 380 | static const struct intel_limit intel_limits_ironlake_dual_lvds = { |
273e27ca EA |
381 | .dot = { .min = 25000, .max = 350000 }, |
382 | .vco = { .min = 1760000, .max = 3510000 }, | |
383 | .n = { .min = 1, .max = 3 }, | |
384 | .m = { .min = 79, .max = 127 }, | |
385 | .m1 = { .min = 12, .max = 22 }, | |
386 | .m2 = { .min = 5, .max = 9 }, | |
387 | .p = { .min = 14, .max = 56 }, | |
388 | .p1 = { .min = 2, .max = 8 }, | |
389 | .p2 = { .dot_limit = 225000, | |
390 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
391 | }; |
392 | ||
273e27ca | 393 | /* LVDS 100mhz refclk limits. */ |
1b6f4958 | 394 | static const struct intel_limit intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
395 | .dot = { .min = 25000, .max = 350000 }, |
396 | .vco = { .min = 1760000, .max = 3510000 }, | |
397 | .n = { .min = 1, .max = 2 }, | |
398 | .m = { .min = 79, .max = 126 }, | |
399 | .m1 = { .min = 12, .max = 22 }, | |
400 | .m2 = { .min = 5, .max = 9 }, | |
401 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 402 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
403 | .p2 = { .dot_limit = 225000, |
404 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
405 | }; |
406 | ||
1b6f4958 | 407 | static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = { |
273e27ca EA |
408 | .dot = { .min = 25000, .max = 350000 }, |
409 | .vco = { .min = 1760000, .max = 3510000 }, | |
410 | .n = { .min = 1, .max = 3 }, | |
411 | .m = { .min = 79, .max = 126 }, | |
412 | .m1 = { .min = 12, .max = 22 }, | |
413 | .m2 = { .min = 5, .max = 9 }, | |
414 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 415 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
416 | .p2 = { .dot_limit = 225000, |
417 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
418 | }; |
419 | ||
1b6f4958 | 420 | static const struct intel_limit intel_limits_vlv = { |
f01b7962 VS |
421 | /* |
422 | * These are the data rate limits (measured in fast clocks) | |
423 | * since those are the strictest limits we have. The fast | |
424 | * clock and actual rate limits are more relaxed, so checking | |
425 | * them would make no difference. | |
426 | */ | |
427 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 428 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 429 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
430 | .m1 = { .min = 2, .max = 3 }, |
431 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 432 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 433 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
434 | }; |
435 | ||
1b6f4958 | 436 | static const struct intel_limit intel_limits_chv = { |
ef9348c8 CML |
437 | /* |
438 | * These are the data rate limits (measured in fast clocks) | |
439 | * since those are the strictest limits we have. The fast | |
440 | * clock and actual rate limits are more relaxed, so checking | |
441 | * them would make no difference. | |
442 | */ | |
443 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 444 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
445 | .n = { .min = 1, .max = 1 }, |
446 | .m1 = { .min = 2, .max = 2 }, | |
447 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
448 | .p1 = { .min = 2, .max = 4 }, | |
449 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
450 | }; | |
451 | ||
1b6f4958 | 452 | static const struct intel_limit intel_limits_bxt = { |
5ab7b0b7 ID |
453 | /* FIXME: find real dot limits */ |
454 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 455 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
456 | .n = { .min = 1, .max = 1 }, |
457 | .m1 = { .min = 2, .max = 2 }, | |
458 | /* FIXME: find real m2 limits */ | |
459 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
460 | .p1 = { .min = 2, .max = 4 }, | |
461 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
462 | }; | |
463 | ||
cdba954e ACO |
464 | static bool |
465 | needs_modeset(struct drm_crtc_state *state) | |
466 | { | |
fc596660 | 467 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
468 | } |
469 | ||
dccbea3b ID |
470 | /* |
471 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
472 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
473 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
474 | * The helpers' return value is the rate of the clock that is fed to the | |
475 | * display engine's pipe which can be the above fast dot clock rate or a | |
476 | * divided-down version of it. | |
477 | */ | |
f2b115e6 | 478 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
9e2c8475 | 479 | static int pnv_calc_dpll_params(int refclk, struct dpll *clock) |
79e53945 | 480 | { |
2177832f SL |
481 | clock->m = clock->m2 + 2; |
482 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 483 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 484 | return 0; |
fb03ac01 VS |
485 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
486 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
487 | |
488 | return clock->dot; | |
2177832f SL |
489 | } |
490 | ||
7429e9d4 DV |
491 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
492 | { | |
493 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
494 | } | |
495 | ||
9e2c8475 | 496 | static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) |
2177832f | 497 | { |
7429e9d4 | 498 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 499 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 500 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 501 | return 0; |
fb03ac01 VS |
502 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
503 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
504 | |
505 | return clock->dot; | |
79e53945 JB |
506 | } |
507 | ||
9e2c8475 | 508 | static int vlv_calc_dpll_params(int refclk, struct dpll *clock) |
589eca67 ID |
509 | { |
510 | clock->m = clock->m1 * clock->m2; | |
511 | clock->p = clock->p1 * clock->p2; | |
512 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 513 | return 0; |
589eca67 ID |
514 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
515 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
516 | |
517 | return clock->dot / 5; | |
589eca67 ID |
518 | } |
519 | ||
9e2c8475 | 520 | int chv_calc_dpll_params(int refclk, struct dpll *clock) |
ef9348c8 CML |
521 | { |
522 | clock->m = clock->m1 * clock->m2; | |
523 | clock->p = clock->p1 * clock->p2; | |
524 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 525 | return 0; |
ef9348c8 CML |
526 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
527 | clock->n << 22); | |
528 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
529 | |
530 | return clock->dot / 5; | |
ef9348c8 CML |
531 | } |
532 | ||
7c04d1d9 | 533 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
534 | /** |
535 | * Returns whether the given set of divisors are valid for a given refclk with | |
536 | * the given connectors. | |
537 | */ | |
538 | ||
e2d214ae | 539 | static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv, |
1b6f4958 | 540 | const struct intel_limit *limit, |
9e2c8475 | 541 | const struct dpll *clock) |
79e53945 | 542 | { |
f01b7962 VS |
543 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
544 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 545 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 546 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 547 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 548 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 549 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 550 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 551 | |
e2d214ae | 552 | if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) && |
cc3f90f0 | 553 | !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv)) |
f01b7962 VS |
554 | if (clock->m1 <= clock->m2) |
555 | INTELPllInvalid("m1 <= m2\n"); | |
556 | ||
e2d214ae | 557 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
cc3f90f0 | 558 | !IS_GEN9_LP(dev_priv)) { |
f01b7962 VS |
559 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
560 | INTELPllInvalid("p out of range\n"); | |
561 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
562 | INTELPllInvalid("m out of range\n"); | |
563 | } | |
564 | ||
79e53945 | 565 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 566 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
567 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
568 | * connector, etc., rather than just a single range. | |
569 | */ | |
570 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 571 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
572 | |
573 | return true; | |
574 | } | |
575 | ||
3b1429d9 | 576 | static int |
1b6f4958 | 577 | i9xx_select_p2_div(const struct intel_limit *limit, |
3b1429d9 VS |
578 | const struct intel_crtc_state *crtc_state, |
579 | int target) | |
79e53945 | 580 | { |
3b1429d9 | 581 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 582 | |
2d84d2b3 | 583 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 584 | /* |
a210b028 DV |
585 | * For LVDS just rely on its current settings for dual-channel. |
586 | * We haven't figured out how to reliably set up different | |
587 | * single/dual channel state, if we even can. | |
79e53945 | 588 | */ |
1974cad0 | 589 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 590 | return limit->p2.p2_fast; |
79e53945 | 591 | else |
3b1429d9 | 592 | return limit->p2.p2_slow; |
79e53945 JB |
593 | } else { |
594 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 595 | return limit->p2.p2_slow; |
79e53945 | 596 | else |
3b1429d9 | 597 | return limit->p2.p2_fast; |
79e53945 | 598 | } |
3b1429d9 VS |
599 | } |
600 | ||
70e8aa21 ACO |
601 | /* |
602 | * Returns a set of divisors for the desired target clock with the given | |
603 | * refclk, or FALSE. The returned values represent the clock equation: | |
604 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
605 | * | |
606 | * Target and reference clocks are specified in kHz. | |
607 | * | |
608 | * If match_clock is provided, then best_clock P divider must match the P | |
609 | * divider from @match_clock used for LVDS downclocking. | |
610 | */ | |
3b1429d9 | 611 | static bool |
1b6f4958 | 612 | i9xx_find_best_dpll(const struct intel_limit *limit, |
3b1429d9 | 613 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
614 | int target, int refclk, struct dpll *match_clock, |
615 | struct dpll *best_clock) | |
3b1429d9 VS |
616 | { |
617 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
9e2c8475 | 618 | struct dpll clock; |
3b1429d9 | 619 | int err = target; |
79e53945 | 620 | |
0206e353 | 621 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 622 | |
3b1429d9 VS |
623 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
624 | ||
42158660 ZY |
625 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
626 | clock.m1++) { | |
627 | for (clock.m2 = limit->m2.min; | |
628 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 629 | if (clock.m2 >= clock.m1) |
42158660 ZY |
630 | break; |
631 | for (clock.n = limit->n.min; | |
632 | clock.n <= limit->n.max; clock.n++) { | |
633 | for (clock.p1 = limit->p1.min; | |
634 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
635 | int this_err; |
636 | ||
dccbea3b | 637 | i9xx_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
638 | if (!intel_PLL_is_valid(to_i915(dev), |
639 | limit, | |
ac58c3f0 DV |
640 | &clock)) |
641 | continue; | |
642 | if (match_clock && | |
643 | clock.p != match_clock->p) | |
644 | continue; | |
645 | ||
646 | this_err = abs(clock.dot - target); | |
647 | if (this_err < err) { | |
648 | *best_clock = clock; | |
649 | err = this_err; | |
650 | } | |
651 | } | |
652 | } | |
653 | } | |
654 | } | |
655 | ||
656 | return (err != target); | |
657 | } | |
658 | ||
70e8aa21 ACO |
659 | /* |
660 | * Returns a set of divisors for the desired target clock with the given | |
661 | * refclk, or FALSE. The returned values represent the clock equation: | |
662 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
663 | * | |
664 | * Target and reference clocks are specified in kHz. | |
665 | * | |
666 | * If match_clock is provided, then best_clock P divider must match the P | |
667 | * divider from @match_clock used for LVDS downclocking. | |
668 | */ | |
ac58c3f0 | 669 | static bool |
1b6f4958 | 670 | pnv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 671 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
672 | int target, int refclk, struct dpll *match_clock, |
673 | struct dpll *best_clock) | |
79e53945 | 674 | { |
3b1429d9 | 675 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 676 | struct dpll clock; |
79e53945 JB |
677 | int err = target; |
678 | ||
0206e353 | 679 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 680 | |
3b1429d9 VS |
681 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
682 | ||
42158660 ZY |
683 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
684 | clock.m1++) { | |
685 | for (clock.m2 = limit->m2.min; | |
686 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
687 | for (clock.n = limit->n.min; |
688 | clock.n <= limit->n.max; clock.n++) { | |
689 | for (clock.p1 = limit->p1.min; | |
690 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
691 | int this_err; |
692 | ||
dccbea3b | 693 | pnv_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
694 | if (!intel_PLL_is_valid(to_i915(dev), |
695 | limit, | |
1b894b59 | 696 | &clock)) |
79e53945 | 697 | continue; |
cec2f356 SP |
698 | if (match_clock && |
699 | clock.p != match_clock->p) | |
700 | continue; | |
79e53945 JB |
701 | |
702 | this_err = abs(clock.dot - target); | |
703 | if (this_err < err) { | |
704 | *best_clock = clock; | |
705 | err = this_err; | |
706 | } | |
707 | } | |
708 | } | |
709 | } | |
710 | } | |
711 | ||
712 | return (err != target); | |
713 | } | |
714 | ||
997c030c ACO |
715 | /* |
716 | * Returns a set of divisors for the desired target clock with the given | |
717 | * refclk, or FALSE. The returned values represent the clock equation: | |
718 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
70e8aa21 ACO |
719 | * |
720 | * Target and reference clocks are specified in kHz. | |
721 | * | |
722 | * If match_clock is provided, then best_clock P divider must match the P | |
723 | * divider from @match_clock used for LVDS downclocking. | |
997c030c | 724 | */ |
d4906093 | 725 | static bool |
1b6f4958 | 726 | g4x_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 727 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
728 | int target, int refclk, struct dpll *match_clock, |
729 | struct dpll *best_clock) | |
d4906093 | 730 | { |
3b1429d9 | 731 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 732 | struct dpll clock; |
d4906093 | 733 | int max_n; |
3b1429d9 | 734 | bool found = false; |
6ba770dc AJ |
735 | /* approximately equals target * 0.00585 */ |
736 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
737 | |
738 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
739 | |
740 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
741 | ||
d4906093 | 742 | max_n = limit->n.max; |
f77f13e2 | 743 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 744 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 745 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
746 | for (clock.m1 = limit->m1.max; |
747 | clock.m1 >= limit->m1.min; clock.m1--) { | |
748 | for (clock.m2 = limit->m2.max; | |
749 | clock.m2 >= limit->m2.min; clock.m2--) { | |
750 | for (clock.p1 = limit->p1.max; | |
751 | clock.p1 >= limit->p1.min; clock.p1--) { | |
752 | int this_err; | |
753 | ||
dccbea3b | 754 | i9xx_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
755 | if (!intel_PLL_is_valid(to_i915(dev), |
756 | limit, | |
1b894b59 | 757 | &clock)) |
d4906093 | 758 | continue; |
1b894b59 CW |
759 | |
760 | this_err = abs(clock.dot - target); | |
d4906093 ML |
761 | if (this_err < err_most) { |
762 | *best_clock = clock; | |
763 | err_most = this_err; | |
764 | max_n = clock.n; | |
765 | found = true; | |
766 | } | |
767 | } | |
768 | } | |
769 | } | |
770 | } | |
2c07245f ZW |
771 | return found; |
772 | } | |
773 | ||
d5dd62bd ID |
774 | /* |
775 | * Check if the calculated PLL configuration is more optimal compared to the | |
776 | * best configuration and error found so far. Return the calculated error. | |
777 | */ | |
778 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
9e2c8475 ACO |
779 | const struct dpll *calculated_clock, |
780 | const struct dpll *best_clock, | |
d5dd62bd ID |
781 | unsigned int best_error_ppm, |
782 | unsigned int *error_ppm) | |
783 | { | |
9ca3ba01 ID |
784 | /* |
785 | * For CHV ignore the error and consider only the P value. | |
786 | * Prefer a bigger P value based on HW requirements. | |
787 | */ | |
920a14b2 | 788 | if (IS_CHERRYVIEW(to_i915(dev))) { |
9ca3ba01 ID |
789 | *error_ppm = 0; |
790 | ||
791 | return calculated_clock->p > best_clock->p; | |
792 | } | |
793 | ||
24be4e46 ID |
794 | if (WARN_ON_ONCE(!target_freq)) |
795 | return false; | |
796 | ||
d5dd62bd ID |
797 | *error_ppm = div_u64(1000000ULL * |
798 | abs(target_freq - calculated_clock->dot), | |
799 | target_freq); | |
800 | /* | |
801 | * Prefer a better P value over a better (smaller) error if the error | |
802 | * is small. Ensure this preference for future configurations too by | |
803 | * setting the error to 0. | |
804 | */ | |
805 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
806 | *error_ppm = 0; | |
807 | ||
808 | return true; | |
809 | } | |
810 | ||
811 | return *error_ppm + 10 < best_error_ppm; | |
812 | } | |
813 | ||
65b3d6a9 ACO |
814 | /* |
815 | * Returns a set of divisors for the desired target clock with the given | |
816 | * refclk, or FALSE. The returned values represent the clock equation: | |
817 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
818 | */ | |
a0c4da24 | 819 | static bool |
1b6f4958 | 820 | vlv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 821 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
822 | int target, int refclk, struct dpll *match_clock, |
823 | struct dpll *best_clock) | |
a0c4da24 | 824 | { |
a93e255f | 825 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 826 | struct drm_device *dev = crtc->base.dev; |
9e2c8475 | 827 | struct dpll clock; |
69e4f900 | 828 | unsigned int bestppm = 1000000; |
27e639bf VS |
829 | /* min update 19.2 MHz */ |
830 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 831 | bool found = false; |
a0c4da24 | 832 | |
6b4bf1c4 VS |
833 | target *= 5; /* fast clock */ |
834 | ||
835 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
836 | |
837 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 838 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 839 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 840 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 841 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 842 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 843 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 844 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 845 | unsigned int ppm; |
69e4f900 | 846 | |
6b4bf1c4 VS |
847 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
848 | refclk * clock.m1); | |
849 | ||
dccbea3b | 850 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 851 | |
e2d214ae TU |
852 | if (!intel_PLL_is_valid(to_i915(dev), |
853 | limit, | |
f01b7962 | 854 | &clock)) |
43b0ac53 VS |
855 | continue; |
856 | ||
d5dd62bd ID |
857 | if (!vlv_PLL_is_optimal(dev, target, |
858 | &clock, | |
859 | best_clock, | |
860 | bestppm, &ppm)) | |
861 | continue; | |
6b4bf1c4 | 862 | |
d5dd62bd ID |
863 | *best_clock = clock; |
864 | bestppm = ppm; | |
865 | found = true; | |
a0c4da24 JB |
866 | } |
867 | } | |
868 | } | |
869 | } | |
a0c4da24 | 870 | |
49e497ef | 871 | return found; |
a0c4da24 | 872 | } |
a4fc5ed6 | 873 | |
65b3d6a9 ACO |
874 | /* |
875 | * Returns a set of divisors for the desired target clock with the given | |
876 | * refclk, or FALSE. The returned values represent the clock equation: | |
877 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
878 | */ | |
ef9348c8 | 879 | static bool |
1b6f4958 | 880 | chv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 881 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
882 | int target, int refclk, struct dpll *match_clock, |
883 | struct dpll *best_clock) | |
ef9348c8 | 884 | { |
a93e255f | 885 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 886 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 887 | unsigned int best_error_ppm; |
9e2c8475 | 888 | struct dpll clock; |
ef9348c8 CML |
889 | uint64_t m2; |
890 | int found = false; | |
891 | ||
892 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 893 | best_error_ppm = 1000000; |
ef9348c8 CML |
894 | |
895 | /* | |
896 | * Based on hardware doc, the n always set to 1, and m1 always | |
897 | * set to 2. If requires to support 200Mhz refclk, we need to | |
898 | * revisit this because n may not 1 anymore. | |
899 | */ | |
900 | clock.n = 1, clock.m1 = 2; | |
901 | target *= 5; /* fast clock */ | |
902 | ||
903 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
904 | for (clock.p2 = limit->p2.p2_fast; | |
905 | clock.p2 >= limit->p2.p2_slow; | |
906 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 907 | unsigned int error_ppm; |
ef9348c8 CML |
908 | |
909 | clock.p = clock.p1 * clock.p2; | |
910 | ||
911 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
912 | clock.n) << 22, refclk * clock.m1); | |
913 | ||
914 | if (m2 > INT_MAX/clock.m1) | |
915 | continue; | |
916 | ||
917 | clock.m2 = m2; | |
918 | ||
dccbea3b | 919 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 | 920 | |
e2d214ae | 921 | if (!intel_PLL_is_valid(to_i915(dev), limit, &clock)) |
ef9348c8 CML |
922 | continue; |
923 | ||
9ca3ba01 ID |
924 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
925 | best_error_ppm, &error_ppm)) | |
926 | continue; | |
927 | ||
928 | *best_clock = clock; | |
929 | best_error_ppm = error_ppm; | |
930 | found = true; | |
ef9348c8 CML |
931 | } |
932 | } | |
933 | ||
934 | return found; | |
935 | } | |
936 | ||
5ab7b0b7 | 937 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
9e2c8475 | 938 | struct dpll *best_clock) |
5ab7b0b7 | 939 | { |
65b3d6a9 | 940 | int refclk = 100000; |
1b6f4958 | 941 | const struct intel_limit *limit = &intel_limits_bxt; |
5ab7b0b7 | 942 | |
65b3d6a9 | 943 | return chv_find_best_dpll(limit, crtc_state, |
5ab7b0b7 ID |
944 | target_clock, refclk, NULL, best_clock); |
945 | } | |
946 | ||
525b9311 | 947 | bool intel_crtc_active(struct intel_crtc *crtc) |
20ddf665 | 948 | { |
20ddf665 VS |
949 | /* Be paranoid as we can arrive here with only partial |
950 | * state retrieved from the hardware during setup. | |
951 | * | |
241bfc38 | 952 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
953 | * as Haswell has gained clock readout/fastboot support. |
954 | * | |
66e514c1 | 955 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 956 | * properly reconstruct framebuffers. |
c3d1f436 MR |
957 | * |
958 | * FIXME: The intel_crtc->active here should be switched to | |
959 | * crtc->state->active once we have proper CRTC states wired up | |
960 | * for atomic. | |
20ddf665 | 961 | */ |
525b9311 VS |
962 | return crtc->active && crtc->base.primary->state->fb && |
963 | crtc->config->base.adjusted_mode.crtc_clock; | |
20ddf665 VS |
964 | } |
965 | ||
a5c961d1 PZ |
966 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
967 | enum pipe pipe) | |
968 | { | |
98187836 | 969 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
a5c961d1 | 970 | |
e2af48c6 | 971 | return crtc->config->cpu_transcoder; |
a5c961d1 PZ |
972 | } |
973 | ||
6315b5d3 | 974 | static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe) |
fbf49ea2 | 975 | { |
f0f59a00 | 976 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
977 | u32 line1, line2; |
978 | u32 line_mask; | |
979 | ||
5db94019 | 980 | if (IS_GEN2(dev_priv)) |
fbf49ea2 VS |
981 | line_mask = DSL_LINEMASK_GEN2; |
982 | else | |
983 | line_mask = DSL_LINEMASK_GEN3; | |
984 | ||
985 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 986 | msleep(5); |
fbf49ea2 VS |
987 | line2 = I915_READ(reg) & line_mask; |
988 | ||
989 | return line1 == line2; | |
990 | } | |
991 | ||
ab7ad7f6 KP |
992 | /* |
993 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 994 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
995 | * |
996 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
997 | * spinning on the vblank interrupt status bit, since we won't actually | |
998 | * see an interrupt when the pipe is disabled. | |
999 | * | |
ab7ad7f6 KP |
1000 | * On Gen4 and above: |
1001 | * wait for the pipe register state bit to turn off | |
1002 | * | |
1003 | * Otherwise: | |
1004 | * wait for the display line value to settle (it usually | |
1005 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1006 | * |
9d0498a2 | 1007 | */ |
575f7ab7 | 1008 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1009 | { |
6315b5d3 | 1010 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 1011 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1012 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 | 1013 | |
6315b5d3 | 1014 | if (INTEL_GEN(dev_priv) >= 4) { |
f0f59a00 | 1015 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1016 | |
1017 | /* Wait for the Pipe State to go off */ | |
b8511f53 CW |
1018 | if (intel_wait_for_register(dev_priv, |
1019 | reg, I965_PIPECONF_ACTIVE, 0, | |
1020 | 100)) | |
284637d9 | 1021 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1022 | } else { |
ab7ad7f6 | 1023 | /* Wait for the display line to settle */ |
6315b5d3 | 1024 | if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100)) |
284637d9 | 1025 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1026 | } |
79e53945 JB |
1027 | } |
1028 | ||
b24e7179 | 1029 | /* Only for pre-ILK configs */ |
55607e8a DV |
1030 | void assert_pll(struct drm_i915_private *dev_priv, |
1031 | enum pipe pipe, bool state) | |
b24e7179 | 1032 | { |
b24e7179 JB |
1033 | u32 val; |
1034 | bool cur_state; | |
1035 | ||
649636ef | 1036 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1037 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1038 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1039 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1040 | onoff(state), onoff(cur_state)); |
b24e7179 | 1041 | } |
b24e7179 | 1042 | |
23538ef1 | 1043 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
8563b1e8 | 1044 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
23538ef1 JN |
1045 | { |
1046 | u32 val; | |
1047 | bool cur_state; | |
1048 | ||
a580516d | 1049 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1050 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1051 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1052 | |
1053 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1054 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1055 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1056 | onoff(state), onoff(cur_state)); |
23538ef1 | 1057 | } |
23538ef1 | 1058 | |
040484af JB |
1059 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1060 | enum pipe pipe, bool state) | |
1061 | { | |
040484af | 1062 | bool cur_state; |
ad80a810 PZ |
1063 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1064 | pipe); | |
040484af | 1065 | |
2d1fe073 | 1066 | if (HAS_DDI(dev_priv)) { |
affa9354 | 1067 | /* DDI does not have a specific FDI_TX register */ |
649636ef | 1068 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1069 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1070 | } else { |
649636ef | 1071 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1072 | cur_state = !!(val & FDI_TX_ENABLE); |
1073 | } | |
e2c719b7 | 1074 | I915_STATE_WARN(cur_state != state, |
040484af | 1075 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1076 | onoff(state), onoff(cur_state)); |
040484af JB |
1077 | } |
1078 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1079 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1080 | ||
1081 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1082 | enum pipe pipe, bool state) | |
1083 | { | |
040484af JB |
1084 | u32 val; |
1085 | bool cur_state; | |
1086 | ||
649636ef | 1087 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1088 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1089 | I915_STATE_WARN(cur_state != state, |
040484af | 1090 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1091 | onoff(state), onoff(cur_state)); |
040484af JB |
1092 | } |
1093 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1094 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1095 | ||
1096 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1097 | enum pipe pipe) | |
1098 | { | |
040484af JB |
1099 | u32 val; |
1100 | ||
1101 | /* ILK FDI PLL is always enabled */ | |
7e22dbbb | 1102 | if (IS_GEN5(dev_priv)) |
040484af JB |
1103 | return; |
1104 | ||
bf507ef7 | 1105 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
2d1fe073 | 1106 | if (HAS_DDI(dev_priv)) |
bf507ef7 ED |
1107 | return; |
1108 | ||
649636ef | 1109 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1110 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1111 | } |
1112 | ||
55607e8a DV |
1113 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1114 | enum pipe pipe, bool state) | |
040484af | 1115 | { |
040484af | 1116 | u32 val; |
55607e8a | 1117 | bool cur_state; |
040484af | 1118 | |
649636ef | 1119 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1120 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1121 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1122 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1123 | onoff(state), onoff(cur_state)); |
040484af JB |
1124 | } |
1125 | ||
4f8036a2 | 1126 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) |
ea0760cf | 1127 | { |
f0f59a00 | 1128 | i915_reg_t pp_reg; |
ea0760cf JB |
1129 | u32 val; |
1130 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1131 | bool locked = true; |
ea0760cf | 1132 | |
4f8036a2 | 1133 | if (WARN_ON(HAS_DDI(dev_priv))) |
bedd4dba JN |
1134 | return; |
1135 | ||
4f8036a2 | 1136 | if (HAS_PCH_SPLIT(dev_priv)) { |
bedd4dba JN |
1137 | u32 port_sel; |
1138 | ||
44cb734c ID |
1139 | pp_reg = PP_CONTROL(0); |
1140 | port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; | |
bedd4dba JN |
1141 | |
1142 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1143 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1144 | panel_pipe = PIPE_B; | |
1145 | /* XXX: else fix for eDP */ | |
4f8036a2 | 1146 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
bedd4dba | 1147 | /* presumably write lock depends on pipe, not port select */ |
44cb734c | 1148 | pp_reg = PP_CONTROL(pipe); |
bedd4dba | 1149 | panel_pipe = pipe; |
ea0760cf | 1150 | } else { |
44cb734c | 1151 | pp_reg = PP_CONTROL(0); |
bedd4dba JN |
1152 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1153 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1154 | } |
1155 | ||
1156 | val = I915_READ(pp_reg); | |
1157 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1158 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1159 | locked = false; |
1160 | ||
e2c719b7 | 1161 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1162 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1163 | pipe_name(pipe)); |
ea0760cf JB |
1164 | } |
1165 | ||
93ce0ba6 JN |
1166 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1167 | enum pipe pipe, bool state) | |
1168 | { | |
93ce0ba6 JN |
1169 | bool cur_state; |
1170 | ||
2a307c2e | 1171 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
0b87c24e | 1172 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1173 | else |
5efb3e28 | 1174 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1175 | |
e2c719b7 | 1176 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1177 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1178 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1179 | } |
1180 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1181 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1182 | ||
b840d907 JB |
1183 | void assert_pipe(struct drm_i915_private *dev_priv, |
1184 | enum pipe pipe, bool state) | |
b24e7179 | 1185 | { |
63d7bbe9 | 1186 | bool cur_state; |
702e7a56 PZ |
1187 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1188 | pipe); | |
4feed0eb | 1189 | enum intel_display_power_domain power_domain; |
b24e7179 | 1190 | |
e56134bc VS |
1191 | /* we keep both pipes enabled on 830 */ |
1192 | if (IS_I830(dev_priv)) | |
8e636784 DV |
1193 | state = true; |
1194 | ||
4feed0eb ID |
1195 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1196 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
649636ef | 1197 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 | 1198 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb ID |
1199 | |
1200 | intel_display_power_put(dev_priv, power_domain); | |
1201 | } else { | |
1202 | cur_state = false; | |
69310161 PZ |
1203 | } |
1204 | ||
e2c719b7 | 1205 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1206 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1207 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1208 | } |
1209 | ||
931872fc CW |
1210 | static void assert_plane(struct drm_i915_private *dev_priv, |
1211 | enum plane plane, bool state) | |
b24e7179 | 1212 | { |
b24e7179 | 1213 | u32 val; |
931872fc | 1214 | bool cur_state; |
b24e7179 | 1215 | |
649636ef | 1216 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1217 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1218 | I915_STATE_WARN(cur_state != state, |
931872fc | 1219 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1220 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1221 | } |
1222 | ||
931872fc CW |
1223 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1224 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1225 | ||
b24e7179 JB |
1226 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1227 | enum pipe pipe) | |
1228 | { | |
649636ef | 1229 | int i; |
b24e7179 | 1230 | |
653e1026 | 1231 | /* Primary planes are fixed to pipes on gen4+ */ |
6315b5d3 | 1232 | if (INTEL_GEN(dev_priv) >= 4) { |
649636ef | 1233 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1234 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1235 | "plane %c assertion failure, should be disabled but not\n", |
1236 | plane_name(pipe)); | |
19ec1358 | 1237 | return; |
28c05794 | 1238 | } |
19ec1358 | 1239 | |
b24e7179 | 1240 | /* Need to check both planes against the pipe */ |
055e393f | 1241 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1242 | u32 val = I915_READ(DSPCNTR(i)); |
1243 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1244 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1245 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1246 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1247 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1248 | } |
1249 | } | |
1250 | ||
19332d7a JB |
1251 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1252 | enum pipe pipe) | |
1253 | { | |
649636ef | 1254 | int sprite; |
19332d7a | 1255 | |
6315b5d3 | 1256 | if (INTEL_GEN(dev_priv) >= 9) { |
3bdcfc0c | 1257 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1258 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1259 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1260 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1261 | sprite, pipe_name(pipe)); | |
1262 | } | |
920a14b2 | 1263 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
3bdcfc0c | 1264 | for_each_sprite(dev_priv, pipe, sprite) { |
83c04a62 | 1265 | u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite)); |
e2c719b7 | 1266 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1267 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1268 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef | 1269 | } |
6315b5d3 | 1270 | } else if (INTEL_GEN(dev_priv) >= 7) { |
649636ef | 1271 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1272 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1273 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1274 | plane_name(pipe), pipe_name(pipe)); |
ab33081a | 1275 | } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) { |
649636ef | 1276 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1277 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1278 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1279 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1280 | } |
1281 | } | |
1282 | ||
08c71e5e VS |
1283 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1284 | { | |
e2c719b7 | 1285 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1286 | drm_crtc_vblank_put(crtc); |
1287 | } | |
1288 | ||
7abd4b35 ACO |
1289 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1290 | enum pipe pipe) | |
92f2584a | 1291 | { |
92f2584a JB |
1292 | u32 val; |
1293 | bool enabled; | |
1294 | ||
649636ef | 1295 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1296 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1297 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1298 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1299 | pipe_name(pipe)); | |
92f2584a JB |
1300 | } |
1301 | ||
4e634389 KP |
1302 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1303 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1304 | { |
1305 | if ((val & DP_PORT_EN) == 0) | |
1306 | return false; | |
1307 | ||
2d1fe073 | 1308 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 | 1309 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1310 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1311 | return false; | |
2d1fe073 | 1312 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1313 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
1314 | return false; | |
f0575e92 KP |
1315 | } else { |
1316 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1317 | return false; | |
1318 | } | |
1319 | return true; | |
1320 | } | |
1321 | ||
1519b995 KP |
1322 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1323 | enum pipe pipe, u32 val) | |
1324 | { | |
dc0fa718 | 1325 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1326 | return false; |
1327 | ||
2d1fe073 | 1328 | if (HAS_PCH_CPT(dev_priv)) { |
dc0fa718 | 1329 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1330 | return false; |
2d1fe073 | 1331 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1332 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) |
1333 | return false; | |
1519b995 | 1334 | } else { |
dc0fa718 | 1335 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1336 | return false; |
1337 | } | |
1338 | return true; | |
1339 | } | |
1340 | ||
1341 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1342 | enum pipe pipe, u32 val) | |
1343 | { | |
1344 | if ((val & LVDS_PORT_EN) == 0) | |
1345 | return false; | |
1346 | ||
2d1fe073 | 1347 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1348 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1349 | return false; | |
1350 | } else { | |
1351 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1352 | return false; | |
1353 | } | |
1354 | return true; | |
1355 | } | |
1356 | ||
1357 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1358 | enum pipe pipe, u32 val) | |
1359 | { | |
1360 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1361 | return false; | |
2d1fe073 | 1362 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1363 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1364 | return false; | |
1365 | } else { | |
1366 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1367 | return false; | |
1368 | } | |
1369 | return true; | |
1370 | } | |
1371 | ||
291906f1 | 1372 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1373 | enum pipe pipe, i915_reg_t reg, |
1374 | u32 port_sel) | |
291906f1 | 1375 | { |
47a05eca | 1376 | u32 val = I915_READ(reg); |
e2c719b7 | 1377 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1378 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1379 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1380 | |
2d1fe073 | 1381 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1382 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1383 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1384 | } |
1385 | ||
1386 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1387 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1388 | { |
47a05eca | 1389 | u32 val = I915_READ(reg); |
e2c719b7 | 1390 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1391 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1392 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1393 | |
2d1fe073 | 1394 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1395 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1396 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1397 | } |
1398 | ||
1399 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1400 | enum pipe pipe) | |
1401 | { | |
291906f1 | 1402 | u32 val; |
291906f1 | 1403 | |
f0575e92 KP |
1404 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1405 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1406 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1407 | |
649636ef | 1408 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1409 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1410 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1411 | pipe_name(pipe)); |
291906f1 | 1412 | |
649636ef | 1413 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1414 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1415 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1416 | pipe_name(pipe)); |
291906f1 | 1417 | |
e2debe91 PZ |
1418 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1419 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1420 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1421 | } |
1422 | ||
cd2d34d9 VS |
1423 | static void _vlv_enable_pll(struct intel_crtc *crtc, |
1424 | const struct intel_crtc_state *pipe_config) | |
1425 | { | |
1426 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1427 | enum pipe pipe = crtc->pipe; | |
1428 | ||
1429 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); | |
1430 | POSTING_READ(DPLL(pipe)); | |
1431 | udelay(150); | |
1432 | ||
2c30b43b CW |
1433 | if (intel_wait_for_register(dev_priv, |
1434 | DPLL(pipe), | |
1435 | DPLL_LOCK_VLV, | |
1436 | DPLL_LOCK_VLV, | |
1437 | 1)) | |
cd2d34d9 VS |
1438 | DRM_ERROR("DPLL %d failed to lock\n", pipe); |
1439 | } | |
1440 | ||
d288f65f | 1441 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1442 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1443 | { |
cd2d34d9 | 1444 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1445 | enum pipe pipe = crtc->pipe; |
87442f73 | 1446 | |
8bd3f301 | 1447 | assert_pipe_disabled(dev_priv, pipe); |
87442f73 | 1448 | |
87442f73 | 1449 | /* PLL is protected by panel, make sure we can write it */ |
7d1a83cb | 1450 | assert_panel_unlocked(dev_priv, pipe); |
87442f73 | 1451 | |
cd2d34d9 VS |
1452 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) |
1453 | _vlv_enable_pll(crtc, pipe_config); | |
426115cf | 1454 | |
8bd3f301 VS |
1455 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
1456 | POSTING_READ(DPLL_MD(pipe)); | |
87442f73 DV |
1457 | } |
1458 | ||
cd2d34d9 VS |
1459 | |
1460 | static void _chv_enable_pll(struct intel_crtc *crtc, | |
1461 | const struct intel_crtc_state *pipe_config) | |
9d556c99 | 1462 | { |
cd2d34d9 | 1463 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1464 | enum pipe pipe = crtc->pipe; |
9d556c99 | 1465 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9d556c99 CML |
1466 | u32 tmp; |
1467 | ||
a580516d | 1468 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1469 | |
1470 | /* Enable back the 10bit clock to display controller */ | |
1471 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1472 | tmp |= DPIO_DCLKP_EN; | |
1473 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1474 | ||
54433e91 VS |
1475 | mutex_unlock(&dev_priv->sb_lock); |
1476 | ||
9d556c99 CML |
1477 | /* |
1478 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1479 | */ | |
1480 | udelay(1); | |
1481 | ||
1482 | /* Enable PLL */ | |
d288f65f | 1483 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1484 | |
1485 | /* Check PLL is locked */ | |
6b18826a CW |
1486 | if (intel_wait_for_register(dev_priv, |
1487 | DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV, | |
1488 | 1)) | |
9d556c99 | 1489 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
cd2d34d9 VS |
1490 | } |
1491 | ||
1492 | static void chv_enable_pll(struct intel_crtc *crtc, | |
1493 | const struct intel_crtc_state *pipe_config) | |
1494 | { | |
1495 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1496 | enum pipe pipe = crtc->pipe; | |
1497 | ||
1498 | assert_pipe_disabled(dev_priv, pipe); | |
1499 | ||
1500 | /* PLL is protected by panel, make sure we can write it */ | |
1501 | assert_panel_unlocked(dev_priv, pipe); | |
1502 | ||
1503 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) | |
1504 | _chv_enable_pll(crtc, pipe_config); | |
9d556c99 | 1505 | |
c231775c VS |
1506 | if (pipe != PIPE_A) { |
1507 | /* | |
1508 | * WaPixelRepeatModeFixForC0:chv | |
1509 | * | |
1510 | * DPLLCMD is AWOL. Use chicken bits to propagate | |
1511 | * the value from DPLLBMD to either pipe B or C. | |
1512 | */ | |
1513 | I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C); | |
1514 | I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); | |
1515 | I915_WRITE(CBR4_VLV, 0); | |
1516 | dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; | |
1517 | ||
1518 | /* | |
1519 | * DPLLB VGA mode also seems to cause problems. | |
1520 | * We should always have it disabled. | |
1521 | */ | |
1522 | WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); | |
1523 | } else { | |
1524 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); | |
1525 | POSTING_READ(DPLL_MD(pipe)); | |
1526 | } | |
9d556c99 CML |
1527 | } |
1528 | ||
6315b5d3 | 1529 | static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv) |
1c4e0274 VS |
1530 | { |
1531 | struct intel_crtc *crtc; | |
1532 | int count = 0; | |
1533 | ||
6315b5d3 | 1534 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
3538b9df | 1535 | count += crtc->base.state->active && |
2d84d2b3 VS |
1536 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO); |
1537 | } | |
1c4e0274 VS |
1538 | |
1539 | return count; | |
1540 | } | |
1541 | ||
66e3d5c0 | 1542 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1543 | { |
6315b5d3 | 1544 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
f0f59a00 | 1545 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1546 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
bb408dd2 | 1547 | int i; |
63d7bbe9 | 1548 | |
66e3d5c0 | 1549 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1550 | |
63d7bbe9 | 1551 | /* PLL is protected by panel, make sure we can write it */ |
50a0bc90 | 1552 | if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv)) |
66e3d5c0 | 1553 | assert_panel_unlocked(dev_priv, crtc->pipe); |
63d7bbe9 | 1554 | |
1c4e0274 | 1555 | /* Enable DVO 2x clock on both PLLs if necessary */ |
6315b5d3 | 1556 | if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) { |
1c4e0274 VS |
1557 | /* |
1558 | * It appears to be important that we don't enable this | |
1559 | * for the current pipe before otherwise configuring the | |
1560 | * PLL. No idea how this should be handled if multiple | |
1561 | * DVO outputs are enabled simultaneosly. | |
1562 | */ | |
1563 | dpll |= DPLL_DVO_2X_MODE; | |
1564 | I915_WRITE(DPLL(!crtc->pipe), | |
1565 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1566 | } | |
66e3d5c0 | 1567 | |
c2b63374 VS |
1568 | /* |
1569 | * Apparently we need to have VGA mode enabled prior to changing | |
1570 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1571 | * dividers, even though the register value does change. | |
1572 | */ | |
1573 | I915_WRITE(reg, 0); | |
1574 | ||
8e7a65aa VS |
1575 | I915_WRITE(reg, dpll); |
1576 | ||
66e3d5c0 DV |
1577 | /* Wait for the clocks to stabilize. */ |
1578 | POSTING_READ(reg); | |
1579 | udelay(150); | |
1580 | ||
6315b5d3 | 1581 | if (INTEL_GEN(dev_priv) >= 4) { |
66e3d5c0 | 1582 | I915_WRITE(DPLL_MD(crtc->pipe), |
6e3c9717 | 1583 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1584 | } else { |
1585 | /* The pixel multiplier can only be updated once the | |
1586 | * DPLL is enabled and the clocks are stable. | |
1587 | * | |
1588 | * So write it again. | |
1589 | */ | |
1590 | I915_WRITE(reg, dpll); | |
1591 | } | |
63d7bbe9 JB |
1592 | |
1593 | /* We do this three times for luck */ | |
bb408dd2 VS |
1594 | for (i = 0; i < 3; i++) { |
1595 | I915_WRITE(reg, dpll); | |
1596 | POSTING_READ(reg); | |
1597 | udelay(150); /* wait for warmup */ | |
1598 | } | |
63d7bbe9 JB |
1599 | } |
1600 | ||
1601 | /** | |
50b44a44 | 1602 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1603 | * @dev_priv: i915 private structure |
1604 | * @pipe: pipe PLL to disable | |
1605 | * | |
1606 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1607 | * | |
1608 | * Note! This is for pre-ILK only. | |
1609 | */ | |
1c4e0274 | 1610 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1611 | { |
6315b5d3 | 1612 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1c4e0274 VS |
1613 | enum pipe pipe = crtc->pipe; |
1614 | ||
1615 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
50a0bc90 | 1616 | if (IS_I830(dev_priv) && |
2d84d2b3 | 1617 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) && |
6315b5d3 | 1618 | !intel_num_dvo_pipes(dev_priv)) { |
1c4e0274 VS |
1619 | I915_WRITE(DPLL(PIPE_B), |
1620 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1621 | I915_WRITE(DPLL(PIPE_A), | |
1622 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1623 | } | |
1624 | ||
b6b5d049 | 1625 | /* Don't disable pipe or pipe PLLs if needed */ |
e56134bc | 1626 | if (IS_I830(dev_priv)) |
63d7bbe9 JB |
1627 | return; |
1628 | ||
1629 | /* Make sure the pipe isn't still relying on us */ | |
1630 | assert_pipe_disabled(dev_priv, pipe); | |
1631 | ||
b8afb911 | 1632 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1633 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1634 | } |
1635 | ||
f6071166 JB |
1636 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1637 | { | |
b8afb911 | 1638 | u32 val; |
f6071166 JB |
1639 | |
1640 | /* Make sure the pipe isn't still relying on us */ | |
1641 | assert_pipe_disabled(dev_priv, pipe); | |
1642 | ||
03ed5cbf VS |
1643 | val = DPLL_INTEGRATED_REF_CLK_VLV | |
1644 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
1645 | if (pipe != PIPE_A) | |
1646 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1647 | ||
f6071166 JB |
1648 | I915_WRITE(DPLL(pipe), val); |
1649 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1650 | } |
1651 | ||
1652 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1653 | { | |
d752048d | 1654 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1655 | u32 val; |
1656 | ||
a11b0703 VS |
1657 | /* Make sure the pipe isn't still relying on us */ |
1658 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1659 | |
60bfe44f VS |
1660 | val = DPLL_SSC_REF_CLK_CHV | |
1661 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1662 | if (pipe != PIPE_A) |
1663 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
03ed5cbf | 1664 | |
a11b0703 VS |
1665 | I915_WRITE(DPLL(pipe), val); |
1666 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1667 | |
a580516d | 1668 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1669 | |
1670 | /* Disable 10bit clock to display controller */ | |
1671 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1672 | val &= ~DPIO_DCLKP_EN; | |
1673 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1674 | ||
a580516d | 1675 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1676 | } |
1677 | ||
e4607fcf | 1678 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1679 | struct intel_digital_port *dport, |
1680 | unsigned int expected_mask) | |
89b667f8 JB |
1681 | { |
1682 | u32 port_mask; | |
f0f59a00 | 1683 | i915_reg_t dpll_reg; |
89b667f8 | 1684 | |
e4607fcf CML |
1685 | switch (dport->port) { |
1686 | case PORT_B: | |
89b667f8 | 1687 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1688 | dpll_reg = DPLL(0); |
e4607fcf CML |
1689 | break; |
1690 | case PORT_C: | |
89b667f8 | 1691 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1692 | dpll_reg = DPLL(0); |
9b6de0a1 | 1693 | expected_mask <<= 4; |
00fc31b7 CML |
1694 | break; |
1695 | case PORT_D: | |
1696 | port_mask = DPLL_PORTD_READY_MASK; | |
1697 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1698 | break; |
1699 | default: | |
1700 | BUG(); | |
1701 | } | |
89b667f8 | 1702 | |
370004d3 CW |
1703 | if (intel_wait_for_register(dev_priv, |
1704 | dpll_reg, port_mask, expected_mask, | |
1705 | 1000)) | |
9b6de0a1 VS |
1706 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", |
1707 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1708 | } |
1709 | ||
b8a4f404 PZ |
1710 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1711 | enum pipe pipe) | |
040484af | 1712 | { |
98187836 VS |
1713 | struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv, |
1714 | pipe); | |
f0f59a00 VS |
1715 | i915_reg_t reg; |
1716 | uint32_t val, pipeconf_val; | |
040484af | 1717 | |
040484af | 1718 | /* Make sure PCH DPLL is enabled */ |
8106ddbd | 1719 | assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll); |
040484af JB |
1720 | |
1721 | /* FDI must be feeding us bits for PCH ports */ | |
1722 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1723 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1724 | ||
6e266956 | 1725 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 DV |
1726 | /* Workaround: Set the timing override bit before enabling the |
1727 | * pch transcoder. */ | |
1728 | reg = TRANS_CHICKEN2(pipe); | |
1729 | val = I915_READ(reg); | |
1730 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1731 | I915_WRITE(reg, val); | |
59c859d6 | 1732 | } |
23670b32 | 1733 | |
ab9412ba | 1734 | reg = PCH_TRANSCONF(pipe); |
040484af | 1735 | val = I915_READ(reg); |
5f7f726d | 1736 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c | 1737 | |
2d1fe073 | 1738 | if (HAS_PCH_IBX(dev_priv)) { |
e9bcff5c | 1739 | /* |
c5de7c6f VS |
1740 | * Make the BPC in transcoder be consistent with |
1741 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1742 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1743 | */ |
dfd07d72 | 1744 | val &= ~PIPECONF_BPC_MASK; |
2d84d2b3 | 1745 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI)) |
c5de7c6f VS |
1746 | val |= PIPECONF_8BPC; |
1747 | else | |
1748 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1749 | } |
5f7f726d PZ |
1750 | |
1751 | val &= ~TRANS_INTERLACE_MASK; | |
1752 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
2d1fe073 | 1753 | if (HAS_PCH_IBX(dev_priv) && |
2d84d2b3 | 1754 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1755 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1756 | else | |
1757 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1758 | else |
1759 | val |= TRANS_PROGRESSIVE; | |
1760 | ||
040484af | 1761 | I915_WRITE(reg, val | TRANS_ENABLE); |
650fbd84 CW |
1762 | if (intel_wait_for_register(dev_priv, |
1763 | reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE, | |
1764 | 100)) | |
4bb6f1f3 | 1765 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1766 | } |
1767 | ||
8fb033d7 | 1768 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1769 | enum transcoder cpu_transcoder) |
040484af | 1770 | { |
8fb033d7 | 1771 | u32 val, pipeconf_val; |
8fb033d7 | 1772 | |
8fb033d7 | 1773 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1774 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
a2196033 | 1775 | assert_fdi_rx_enabled(dev_priv, PIPE_A); |
8fb033d7 | 1776 | |
223a6fdf | 1777 | /* Workaround: set timing override bit. */ |
36c0d0cf | 1778 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1779 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1780 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 1781 | |
25f3ef11 | 1782 | val = TRANS_ENABLE; |
937bb610 | 1783 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1784 | |
9a76b1c6 PZ |
1785 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1786 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1787 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1788 | else |
1789 | val |= TRANS_PROGRESSIVE; | |
1790 | ||
ab9412ba | 1791 | I915_WRITE(LPT_TRANSCONF, val); |
d9f96244 CW |
1792 | if (intel_wait_for_register(dev_priv, |
1793 | LPT_TRANSCONF, | |
1794 | TRANS_STATE_ENABLE, | |
1795 | TRANS_STATE_ENABLE, | |
1796 | 100)) | |
937bb610 | 1797 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1798 | } |
1799 | ||
b8a4f404 PZ |
1800 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1801 | enum pipe pipe) | |
040484af | 1802 | { |
f0f59a00 VS |
1803 | i915_reg_t reg; |
1804 | uint32_t val; | |
040484af JB |
1805 | |
1806 | /* FDI relies on the transcoder */ | |
1807 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1808 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1809 | ||
291906f1 JB |
1810 | /* Ports must be off as well */ |
1811 | assert_pch_ports_disabled(dev_priv, pipe); | |
1812 | ||
ab9412ba | 1813 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1814 | val = I915_READ(reg); |
1815 | val &= ~TRANS_ENABLE; | |
1816 | I915_WRITE(reg, val); | |
1817 | /* wait for PCH transcoder off, transcoder state */ | |
a7d04662 CW |
1818 | if (intel_wait_for_register(dev_priv, |
1819 | reg, TRANS_STATE_ENABLE, 0, | |
1820 | 50)) | |
4bb6f1f3 | 1821 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 1822 | |
6e266956 | 1823 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 DV |
1824 | /* Workaround: Clear the timing override chicken bit again. */ |
1825 | reg = TRANS_CHICKEN2(pipe); | |
1826 | val = I915_READ(reg); | |
1827 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1828 | I915_WRITE(reg, val); | |
1829 | } | |
040484af JB |
1830 | } |
1831 | ||
b7076546 | 1832 | void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1833 | { |
8fb033d7 PZ |
1834 | u32 val; |
1835 | ||
ab9412ba | 1836 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1837 | val &= ~TRANS_ENABLE; |
ab9412ba | 1838 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1839 | /* wait for PCH transcoder off, transcoder state */ |
dfdb4749 CW |
1840 | if (intel_wait_for_register(dev_priv, |
1841 | LPT_TRANSCONF, TRANS_STATE_ENABLE, 0, | |
1842 | 50)) | |
8a52fd9f | 1843 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1844 | |
1845 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 1846 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1847 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1848 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
1849 | } |
1850 | ||
a2196033 | 1851 | enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc) |
65f2130c VS |
1852 | { |
1853 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1854 | ||
1855 | WARN_ON(!crtc->config->has_pch_encoder); | |
1856 | ||
1857 | if (HAS_PCH_LPT(dev_priv)) | |
a2196033 | 1858 | return PIPE_A; |
65f2130c | 1859 | else |
a2196033 | 1860 | return crtc->pipe; |
65f2130c VS |
1861 | } |
1862 | ||
b24e7179 | 1863 | /** |
309cfea8 | 1864 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1865 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1866 | * |
0372264a | 1867 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1868 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1869 | */ |
e1fdc473 | 1870 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1871 | { |
0372264a | 1872 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1873 | struct drm_i915_private *dev_priv = to_i915(dev); |
0372264a | 1874 | enum pipe pipe = crtc->pipe; |
1a70a728 | 1875 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
f0f59a00 | 1876 | i915_reg_t reg; |
b24e7179 JB |
1877 | u32 val; |
1878 | ||
9e2ee2dd VS |
1879 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
1880 | ||
58c6eaa2 | 1881 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1882 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1883 | assert_sprites_disabled(dev_priv, pipe); |
1884 | ||
b24e7179 JB |
1885 | /* |
1886 | * A pipe without a PLL won't actually be able to drive bits from | |
1887 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1888 | * need the check. | |
1889 | */ | |
09fa8bb9 | 1890 | if (HAS_GMCH_DISPLAY(dev_priv)) { |
d7edc4e5 | 1891 | if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
1892 | assert_dsi_pll_enabled(dev_priv); |
1893 | else | |
1894 | assert_pll_enabled(dev_priv, pipe); | |
09fa8bb9 | 1895 | } else { |
6e3c9717 | 1896 | if (crtc->config->has_pch_encoder) { |
040484af | 1897 | /* if driving the PCH, we need FDI enabled */ |
65f2130c | 1898 | assert_fdi_rx_pll_enabled(dev_priv, |
a2196033 | 1899 | intel_crtc_pch_transcoder(crtc)); |
1a240d4d DV |
1900 | assert_fdi_tx_pll_enabled(dev_priv, |
1901 | (enum pipe) cpu_transcoder); | |
040484af JB |
1902 | } |
1903 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1904 | } | |
b24e7179 | 1905 | |
702e7a56 | 1906 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1907 | val = I915_READ(reg); |
7ad25d48 | 1908 | if (val & PIPECONF_ENABLE) { |
e56134bc VS |
1909 | /* we keep both pipes enabled on 830 */ |
1910 | WARN_ON(!IS_I830(dev_priv)); | |
00d70b15 | 1911 | return; |
7ad25d48 | 1912 | } |
00d70b15 CW |
1913 | |
1914 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 1915 | POSTING_READ(reg); |
b7792d8b VS |
1916 | |
1917 | /* | |
1918 | * Until the pipe starts DSL will read as 0, which would cause | |
1919 | * an apparent vblank timestamp jump, which messes up also the | |
1920 | * frame count when it's derived from the timestamps. So let's | |
1921 | * wait for the pipe to start properly before we call | |
1922 | * drm_crtc_vblank_on() | |
1923 | */ | |
1924 | if (dev->max_vblank_count == 0 && | |
1925 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
1926 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
1927 | } |
1928 | ||
1929 | /** | |
309cfea8 | 1930 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 1931 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 1932 | * |
575f7ab7 VS |
1933 | * Disable the pipe of @crtc, making sure that various hardware |
1934 | * specific requirements are met, if applicable, e.g. plane | |
1935 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
1936 | * |
1937 | * Will wait until the pipe has shut down before returning. | |
1938 | */ | |
575f7ab7 | 1939 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1940 | { |
fac5e23e | 1941 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 1942 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1943 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 1944 | i915_reg_t reg; |
b24e7179 JB |
1945 | u32 val; |
1946 | ||
9e2ee2dd VS |
1947 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
1948 | ||
b24e7179 JB |
1949 | /* |
1950 | * Make sure planes won't keep trying to pump pixels to us, | |
1951 | * or we might hang the display. | |
1952 | */ | |
1953 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 1954 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 1955 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 1956 | |
702e7a56 | 1957 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1958 | val = I915_READ(reg); |
00d70b15 CW |
1959 | if ((val & PIPECONF_ENABLE) == 0) |
1960 | return; | |
1961 | ||
67adc644 VS |
1962 | /* |
1963 | * Double wide has implications for planes | |
1964 | * so best keep it disabled when not needed. | |
1965 | */ | |
6e3c9717 | 1966 | if (crtc->config->double_wide) |
67adc644 VS |
1967 | val &= ~PIPECONF_DOUBLE_WIDE; |
1968 | ||
1969 | /* Don't disable pipe or pipe PLLs if needed */ | |
e56134bc | 1970 | if (!IS_I830(dev_priv)) |
67adc644 VS |
1971 | val &= ~PIPECONF_ENABLE; |
1972 | ||
1973 | I915_WRITE(reg, val); | |
1974 | if ((val & PIPECONF_ENABLE) == 0) | |
1975 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
1976 | } |
1977 | ||
832be82f VS |
1978 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
1979 | { | |
1980 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
1981 | } | |
1982 | ||
d88c4afd VS |
1983 | static unsigned int |
1984 | intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane) | |
7b49f948 | 1985 | { |
d88c4afd VS |
1986 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
1987 | unsigned int cpp = fb->format->cpp[plane]; | |
1988 | ||
1989 | switch (fb->modifier) { | |
2f075565 | 1990 | case DRM_FORMAT_MOD_LINEAR: |
7b49f948 VS |
1991 | return cpp; |
1992 | case I915_FORMAT_MOD_X_TILED: | |
1993 | if (IS_GEN2(dev_priv)) | |
1994 | return 128; | |
1995 | else | |
1996 | return 512; | |
2e2adb05 VS |
1997 | case I915_FORMAT_MOD_Y_TILED_CCS: |
1998 | if (plane == 1) | |
1999 | return 128; | |
2000 | /* fall through */ | |
7b49f948 VS |
2001 | case I915_FORMAT_MOD_Y_TILED: |
2002 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2003 | return 128; | |
2004 | else | |
2005 | return 512; | |
2e2adb05 VS |
2006 | case I915_FORMAT_MOD_Yf_TILED_CCS: |
2007 | if (plane == 1) | |
2008 | return 128; | |
2009 | /* fall through */ | |
7b49f948 VS |
2010 | case I915_FORMAT_MOD_Yf_TILED: |
2011 | switch (cpp) { | |
2012 | case 1: | |
2013 | return 64; | |
2014 | case 2: | |
2015 | case 4: | |
2016 | return 128; | |
2017 | case 8: | |
2018 | case 16: | |
2019 | return 256; | |
2020 | default: | |
2021 | MISSING_CASE(cpp); | |
2022 | return cpp; | |
2023 | } | |
2024 | break; | |
2025 | default: | |
d88c4afd | 2026 | MISSING_CASE(fb->modifier); |
7b49f948 VS |
2027 | return cpp; |
2028 | } | |
2029 | } | |
2030 | ||
d88c4afd VS |
2031 | static unsigned int |
2032 | intel_tile_height(const struct drm_framebuffer *fb, int plane) | |
a57ce0b2 | 2033 | { |
2f075565 | 2034 | if (fb->modifier == DRM_FORMAT_MOD_LINEAR) |
832be82f VS |
2035 | return 1; |
2036 | else | |
d88c4afd VS |
2037 | return intel_tile_size(to_i915(fb->dev)) / |
2038 | intel_tile_width_bytes(fb, plane); | |
6761dd31 TU |
2039 | } |
2040 | ||
8d0deca8 | 2041 | /* Return the tile dimensions in pixel units */ |
d88c4afd | 2042 | static void intel_tile_dims(const struct drm_framebuffer *fb, int plane, |
8d0deca8 | 2043 | unsigned int *tile_width, |
d88c4afd | 2044 | unsigned int *tile_height) |
8d0deca8 | 2045 | { |
d88c4afd VS |
2046 | unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane); |
2047 | unsigned int cpp = fb->format->cpp[plane]; | |
8d0deca8 VS |
2048 | |
2049 | *tile_width = tile_width_bytes / cpp; | |
d88c4afd | 2050 | *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes; |
8d0deca8 VS |
2051 | } |
2052 | ||
6761dd31 | 2053 | unsigned int |
d88c4afd VS |
2054 | intel_fb_align_height(const struct drm_framebuffer *fb, |
2055 | int plane, unsigned int height) | |
6761dd31 | 2056 | { |
d88c4afd | 2057 | unsigned int tile_height = intel_tile_height(fb, plane); |
832be82f VS |
2058 | |
2059 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2060 | } |
2061 | ||
1663b9d6 VS |
2062 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
2063 | { | |
2064 | unsigned int size = 0; | |
2065 | int i; | |
2066 | ||
2067 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2068 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2069 | ||
2070 | return size; | |
2071 | } | |
2072 | ||
75c82a53 | 2073 | static void |
3465c580 VS |
2074 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
2075 | const struct drm_framebuffer *fb, | |
2076 | unsigned int rotation) | |
f64b98cd | 2077 | { |
7b92c047 | 2078 | view->type = I915_GGTT_VIEW_NORMAL; |
bd2ef25d | 2079 | if (drm_rotation_90_or_270(rotation)) { |
7b92c047 | 2080 | view->type = I915_GGTT_VIEW_ROTATED; |
8bab1193 | 2081 | view->rotated = to_intel_framebuffer(fb)->rot_info; |
2d7a215f VS |
2082 | } |
2083 | } | |
50470bb0 | 2084 | |
fabac484 VS |
2085 | static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv) |
2086 | { | |
2087 | if (IS_I830(dev_priv)) | |
2088 | return 16 * 1024; | |
2089 | else if (IS_I85X(dev_priv)) | |
2090 | return 256; | |
d9e1551e VS |
2091 | else if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
2092 | return 32; | |
fabac484 VS |
2093 | else |
2094 | return 4 * 1024; | |
2095 | } | |
2096 | ||
603525d7 | 2097 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2098 | { |
2099 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2100 | return 256 * 1024; | |
c0f86832 | 2101 | else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) || |
666a4537 | 2102 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2103 | return 128 * 1024; |
2104 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2105 | return 4 * 1024; | |
2106 | else | |
44c5905e | 2107 | return 0; |
4e9a86b6 VS |
2108 | } |
2109 | ||
d88c4afd VS |
2110 | static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, |
2111 | int plane) | |
603525d7 | 2112 | { |
d88c4afd VS |
2113 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
2114 | ||
b90c1ee1 | 2115 | /* AUX_DIST needs only 4K alignment */ |
2e2adb05 | 2116 | if (plane == 1) |
b90c1ee1 VS |
2117 | return 4096; |
2118 | ||
d88c4afd | 2119 | switch (fb->modifier) { |
2f075565 | 2120 | case DRM_FORMAT_MOD_LINEAR: |
603525d7 VS |
2121 | return intel_linear_alignment(dev_priv); |
2122 | case I915_FORMAT_MOD_X_TILED: | |
d88c4afd | 2123 | if (INTEL_GEN(dev_priv) >= 9) |
603525d7 VS |
2124 | return 256 * 1024; |
2125 | return 0; | |
2e2adb05 VS |
2126 | case I915_FORMAT_MOD_Y_TILED_CCS: |
2127 | case I915_FORMAT_MOD_Yf_TILED_CCS: | |
603525d7 VS |
2128 | case I915_FORMAT_MOD_Y_TILED: |
2129 | case I915_FORMAT_MOD_Yf_TILED: | |
2130 | return 1 * 1024 * 1024; | |
2131 | default: | |
d88c4afd | 2132 | MISSING_CASE(fb->modifier); |
603525d7 VS |
2133 | return 0; |
2134 | } | |
2135 | } | |
2136 | ||
058d88c4 CW |
2137 | struct i915_vma * |
2138 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) | |
6b95a207 | 2139 | { |
850c4cdc | 2140 | struct drm_device *dev = fb->dev; |
fac5e23e | 2141 | struct drm_i915_private *dev_priv = to_i915(dev); |
850c4cdc | 2142 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2143 | struct i915_ggtt_view view; |
058d88c4 | 2144 | struct i915_vma *vma; |
6b95a207 | 2145 | u32 alignment; |
6b95a207 | 2146 | |
ebcdd39e MR |
2147 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2148 | ||
d88c4afd | 2149 | alignment = intel_surf_alignment(fb, 0); |
6b95a207 | 2150 | |
3465c580 | 2151 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2152 | |
693db184 CW |
2153 | /* Note that the w/a also requires 64 PTE of padding following the |
2154 | * bo. We currently fill all unused PTE with the shadow page and so | |
2155 | * we should always have valid PTE following the scanout preventing | |
2156 | * the VT-d warning. | |
2157 | */ | |
48f112fe | 2158 | if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024) |
693db184 CW |
2159 | alignment = 256 * 1024; |
2160 | ||
d6dd6843 PZ |
2161 | /* |
2162 | * Global gtt pte registers are special registers which actually forward | |
2163 | * writes to a chunk of system memory. Which means that there is no risk | |
2164 | * that the register values disappear as soon as we call | |
2165 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2166 | * pin/unpin/fence and not more. | |
2167 | */ | |
2168 | intel_runtime_pm_get(dev_priv); | |
2169 | ||
058d88c4 | 2170 | vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view); |
49ef5294 CW |
2171 | if (IS_ERR(vma)) |
2172 | goto err; | |
6b95a207 | 2173 | |
05a20d09 | 2174 | if (i915_vma_is_map_and_fenceable(vma)) { |
49ef5294 CW |
2175 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
2176 | * fence, whereas 965+ only requires a fence if using | |
2177 | * framebuffer compression. For simplicity, we always, when | |
2178 | * possible, install a fence as the cost is not that onerous. | |
2179 | * | |
2180 | * If we fail to fence the tiled scanout, then either the | |
2181 | * modeset will reject the change (which is highly unlikely as | |
2182 | * the affected systems, all but one, do not have unmappable | |
2183 | * space) or we will not be able to enable full powersaving | |
2184 | * techniques (also likely not to apply due to various limits | |
2185 | * FBC and the like impose on the size of the buffer, which | |
2186 | * presumably we violated anyway with this unmappable buffer). | |
2187 | * Anyway, it is presumably better to stumble onwards with | |
2188 | * something and try to run the system in a "less than optimal" | |
2189 | * mode that matches the user configuration. | |
2190 | */ | |
2191 | if (i915_vma_get_fence(vma) == 0) | |
2192 | i915_vma_pin_fence(vma); | |
9807216f | 2193 | } |
6b95a207 | 2194 | |
be1e3415 | 2195 | i915_vma_get(vma); |
49ef5294 | 2196 | err: |
d6dd6843 | 2197 | intel_runtime_pm_put(dev_priv); |
058d88c4 | 2198 | return vma; |
6b95a207 KH |
2199 | } |
2200 | ||
be1e3415 | 2201 | void intel_unpin_fb_vma(struct i915_vma *vma) |
1690e1eb | 2202 | { |
be1e3415 | 2203 | lockdep_assert_held(&vma->vm->i915->drm.struct_mutex); |
f64b98cd | 2204 | |
49ef5294 | 2205 | i915_vma_unpin_fence(vma); |
058d88c4 | 2206 | i915_gem_object_unpin_from_display_plane(vma); |
be1e3415 | 2207 | i915_vma_put(vma); |
1690e1eb CW |
2208 | } |
2209 | ||
ef78ec94 VS |
2210 | static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane, |
2211 | unsigned int rotation) | |
2212 | { | |
bd2ef25d | 2213 | if (drm_rotation_90_or_270(rotation)) |
ef78ec94 VS |
2214 | return to_intel_framebuffer(fb)->rotated[plane].pitch; |
2215 | else | |
2216 | return fb->pitches[plane]; | |
2217 | } | |
2218 | ||
6687c906 VS |
2219 | /* |
2220 | * Convert the x/y offsets into a linear offset. | |
2221 | * Only valid with 0/180 degree rotation, which is fine since linear | |
2222 | * offset is only used with linear buffers on pre-hsw and tiled buffers | |
2223 | * with gen2/3, and 90/270 degree rotations isn't supported on any of them. | |
2224 | */ | |
2225 | u32 intel_fb_xy_to_linear(int x, int y, | |
2949056c VS |
2226 | const struct intel_plane_state *state, |
2227 | int plane) | |
6687c906 | 2228 | { |
2949056c | 2229 | const struct drm_framebuffer *fb = state->base.fb; |
353c8598 | 2230 | unsigned int cpp = fb->format->cpp[plane]; |
6687c906 VS |
2231 | unsigned int pitch = fb->pitches[plane]; |
2232 | ||
2233 | return y * pitch + x * cpp; | |
2234 | } | |
2235 | ||
2236 | /* | |
2237 | * Add the x/y offsets derived from fb->offsets[] to the user | |
2238 | * specified plane src x/y offsets. The resulting x/y offsets | |
2239 | * specify the start of scanout from the beginning of the gtt mapping. | |
2240 | */ | |
2241 | void intel_add_fb_offsets(int *x, int *y, | |
2949056c VS |
2242 | const struct intel_plane_state *state, |
2243 | int plane) | |
6687c906 VS |
2244 | |
2245 | { | |
2949056c VS |
2246 | const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb); |
2247 | unsigned int rotation = state->base.rotation; | |
6687c906 | 2248 | |
bd2ef25d | 2249 | if (drm_rotation_90_or_270(rotation)) { |
6687c906 VS |
2250 | *x += intel_fb->rotated[plane].x; |
2251 | *y += intel_fb->rotated[plane].y; | |
2252 | } else { | |
2253 | *x += intel_fb->normal[plane].x; | |
2254 | *y += intel_fb->normal[plane].y; | |
2255 | } | |
2256 | } | |
2257 | ||
29cf9491 | 2258 | /* |
29cf9491 VS |
2259 | * Input tile dimensions and pitch must already be |
2260 | * rotated to match x and y, and in pixel units. | |
2261 | */ | |
66a2d927 VS |
2262 | static u32 _intel_adjust_tile_offset(int *x, int *y, |
2263 | unsigned int tile_width, | |
2264 | unsigned int tile_height, | |
2265 | unsigned int tile_size, | |
2266 | unsigned int pitch_tiles, | |
2267 | u32 old_offset, | |
2268 | u32 new_offset) | |
29cf9491 | 2269 | { |
b9b24038 | 2270 | unsigned int pitch_pixels = pitch_tiles * tile_width; |
29cf9491 VS |
2271 | unsigned int tiles; |
2272 | ||
2273 | WARN_ON(old_offset & (tile_size - 1)); | |
2274 | WARN_ON(new_offset & (tile_size - 1)); | |
2275 | WARN_ON(new_offset > old_offset); | |
2276 | ||
2277 | tiles = (old_offset - new_offset) / tile_size; | |
2278 | ||
2279 | *y += tiles / pitch_tiles * tile_height; | |
2280 | *x += tiles % pitch_tiles * tile_width; | |
2281 | ||
b9b24038 VS |
2282 | /* minimize x in case it got needlessly big */ |
2283 | *y += *x / pitch_pixels * tile_height; | |
2284 | *x %= pitch_pixels; | |
2285 | ||
29cf9491 VS |
2286 | return new_offset; |
2287 | } | |
2288 | ||
66a2d927 VS |
2289 | /* |
2290 | * Adjust the tile offset by moving the difference into | |
2291 | * the x/y offsets. | |
2292 | */ | |
2293 | static u32 intel_adjust_tile_offset(int *x, int *y, | |
2294 | const struct intel_plane_state *state, int plane, | |
2295 | u32 old_offset, u32 new_offset) | |
2296 | { | |
2297 | const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev); | |
2298 | const struct drm_framebuffer *fb = state->base.fb; | |
353c8598 | 2299 | unsigned int cpp = fb->format->cpp[plane]; |
66a2d927 VS |
2300 | unsigned int rotation = state->base.rotation; |
2301 | unsigned int pitch = intel_fb_pitch(fb, plane, rotation); | |
2302 | ||
2303 | WARN_ON(new_offset > old_offset); | |
2304 | ||
2f075565 | 2305 | if (fb->modifier != DRM_FORMAT_MOD_LINEAR) { |
66a2d927 VS |
2306 | unsigned int tile_size, tile_width, tile_height; |
2307 | unsigned int pitch_tiles; | |
2308 | ||
2309 | tile_size = intel_tile_size(dev_priv); | |
d88c4afd | 2310 | intel_tile_dims(fb, plane, &tile_width, &tile_height); |
66a2d927 | 2311 | |
bd2ef25d | 2312 | if (drm_rotation_90_or_270(rotation)) { |
66a2d927 VS |
2313 | pitch_tiles = pitch / tile_height; |
2314 | swap(tile_width, tile_height); | |
2315 | } else { | |
2316 | pitch_tiles = pitch / (tile_width * cpp); | |
2317 | } | |
2318 | ||
2319 | _intel_adjust_tile_offset(x, y, tile_width, tile_height, | |
2320 | tile_size, pitch_tiles, | |
2321 | old_offset, new_offset); | |
2322 | } else { | |
2323 | old_offset += *y * pitch + *x * cpp; | |
2324 | ||
2325 | *y = (old_offset - new_offset) / pitch; | |
2326 | *x = ((old_offset - new_offset) - *y * pitch) / cpp; | |
2327 | } | |
2328 | ||
2329 | return new_offset; | |
2330 | } | |
2331 | ||
8d0deca8 VS |
2332 | /* |
2333 | * Computes the linear offset to the base tile and adjusts | |
2334 | * x, y. bytes per pixel is assumed to be a power-of-two. | |
2335 | * | |
2336 | * In the 90/270 rotated case, x and y are assumed | |
2337 | * to be already rotated to match the rotated GTT view, and | |
2338 | * pitch is the tile_height aligned framebuffer height. | |
6687c906 VS |
2339 | * |
2340 | * This function is used when computing the derived information | |
2341 | * under intel_framebuffer, so using any of that information | |
2342 | * here is not allowed. Anything under drm_framebuffer can be | |
2343 | * used. This is why the user has to pass in the pitch since it | |
2344 | * is specified in the rotated orientation. | |
8d0deca8 | 2345 | */ |
6687c906 VS |
2346 | static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv, |
2347 | int *x, int *y, | |
2348 | const struct drm_framebuffer *fb, int plane, | |
2349 | unsigned int pitch, | |
2350 | unsigned int rotation, | |
2351 | u32 alignment) | |
c2c75131 | 2352 | { |
bae781b2 | 2353 | uint64_t fb_modifier = fb->modifier; |
353c8598 | 2354 | unsigned int cpp = fb->format->cpp[plane]; |
6687c906 | 2355 | u32 offset, offset_aligned; |
29cf9491 | 2356 | |
29cf9491 VS |
2357 | if (alignment) |
2358 | alignment--; | |
2359 | ||
2f075565 | 2360 | if (fb_modifier != DRM_FORMAT_MOD_LINEAR) { |
8d0deca8 VS |
2361 | unsigned int tile_size, tile_width, tile_height; |
2362 | unsigned int tile_rows, tiles, pitch_tiles; | |
c2c75131 | 2363 | |
d843310d | 2364 | tile_size = intel_tile_size(dev_priv); |
d88c4afd | 2365 | intel_tile_dims(fb, plane, &tile_width, &tile_height); |
8d0deca8 | 2366 | |
bd2ef25d | 2367 | if (drm_rotation_90_or_270(rotation)) { |
8d0deca8 VS |
2368 | pitch_tiles = pitch / tile_height; |
2369 | swap(tile_width, tile_height); | |
2370 | } else { | |
2371 | pitch_tiles = pitch / (tile_width * cpp); | |
2372 | } | |
d843310d VS |
2373 | |
2374 | tile_rows = *y / tile_height; | |
2375 | *y %= tile_height; | |
c2c75131 | 2376 | |
8d0deca8 VS |
2377 | tiles = *x / tile_width; |
2378 | *x %= tile_width; | |
bc752862 | 2379 | |
29cf9491 VS |
2380 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
2381 | offset_aligned = offset & ~alignment; | |
bc752862 | 2382 | |
66a2d927 VS |
2383 | _intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2384 | tile_size, pitch_tiles, | |
2385 | offset, offset_aligned); | |
29cf9491 | 2386 | } else { |
bc752862 | 2387 | offset = *y * pitch + *x * cpp; |
29cf9491 VS |
2388 | offset_aligned = offset & ~alignment; |
2389 | ||
4e9a86b6 VS |
2390 | *y = (offset & alignment) / pitch; |
2391 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
bc752862 | 2392 | } |
29cf9491 VS |
2393 | |
2394 | return offset_aligned; | |
c2c75131 DV |
2395 | } |
2396 | ||
6687c906 | 2397 | u32 intel_compute_tile_offset(int *x, int *y, |
2949056c VS |
2398 | const struct intel_plane_state *state, |
2399 | int plane) | |
6687c906 | 2400 | { |
1e7b4fd8 VS |
2401 | struct intel_plane *intel_plane = to_intel_plane(state->base.plane); |
2402 | struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev); | |
2949056c VS |
2403 | const struct drm_framebuffer *fb = state->base.fb; |
2404 | unsigned int rotation = state->base.rotation; | |
ef78ec94 | 2405 | int pitch = intel_fb_pitch(fb, plane, rotation); |
1e7b4fd8 VS |
2406 | u32 alignment; |
2407 | ||
2408 | if (intel_plane->id == PLANE_CURSOR) | |
2409 | alignment = intel_cursor_alignment(dev_priv); | |
2410 | else | |
2411 | alignment = intel_surf_alignment(fb, plane); | |
6687c906 VS |
2412 | |
2413 | return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch, | |
2414 | rotation, alignment); | |
2415 | } | |
2416 | ||
2417 | /* Convert the fb->offset[] linear offset into x/y offsets */ | |
2418 | static void intel_fb_offset_to_xy(int *x, int *y, | |
2419 | const struct drm_framebuffer *fb, int plane) | |
2420 | { | |
353c8598 | 2421 | unsigned int cpp = fb->format->cpp[plane]; |
6687c906 VS |
2422 | unsigned int pitch = fb->pitches[plane]; |
2423 | u32 linear_offset = fb->offsets[plane]; | |
2424 | ||
2425 | *y = linear_offset / pitch; | |
2426 | *x = linear_offset % pitch / cpp; | |
2427 | } | |
2428 | ||
72618ebf VS |
2429 | static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier) |
2430 | { | |
2431 | switch (fb_modifier) { | |
2432 | case I915_FORMAT_MOD_X_TILED: | |
2433 | return I915_TILING_X; | |
2434 | case I915_FORMAT_MOD_Y_TILED: | |
2e2adb05 | 2435 | case I915_FORMAT_MOD_Y_TILED_CCS: |
72618ebf VS |
2436 | return I915_TILING_Y; |
2437 | default: | |
2438 | return I915_TILING_NONE; | |
2439 | } | |
2440 | } | |
2441 | ||
bbfb6ce8 VS |
2442 | static const struct drm_format_info ccs_formats[] = { |
2443 | { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, | |
2444 | { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, | |
2445 | { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, | |
2446 | { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, | |
2447 | }; | |
2448 | ||
2449 | static const struct drm_format_info * | |
2450 | lookup_format_info(const struct drm_format_info formats[], | |
2451 | int num_formats, u32 format) | |
2452 | { | |
2453 | int i; | |
2454 | ||
2455 | for (i = 0; i < num_formats; i++) { | |
2456 | if (formats[i].format == format) | |
2457 | return &formats[i]; | |
2458 | } | |
2459 | ||
2460 | return NULL; | |
2461 | } | |
2462 | ||
2463 | static const struct drm_format_info * | |
2464 | intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd) | |
2465 | { | |
2466 | switch (cmd->modifier[0]) { | |
2467 | case I915_FORMAT_MOD_Y_TILED_CCS: | |
2468 | case I915_FORMAT_MOD_Yf_TILED_CCS: | |
2469 | return lookup_format_info(ccs_formats, | |
2470 | ARRAY_SIZE(ccs_formats), | |
2471 | cmd->pixel_format); | |
2472 | default: | |
2473 | return NULL; | |
2474 | } | |
2475 | } | |
2476 | ||
6687c906 VS |
2477 | static int |
2478 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
2479 | struct drm_framebuffer *fb) | |
2480 | { | |
2481 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
2482 | struct intel_rotation_info *rot_info = &intel_fb->rot_info; | |
2483 | u32 gtt_offset_rotated = 0; | |
2484 | unsigned int max_size = 0; | |
bcb0b461 | 2485 | int i, num_planes = fb->format->num_planes; |
6687c906 VS |
2486 | unsigned int tile_size = intel_tile_size(dev_priv); |
2487 | ||
2488 | for (i = 0; i < num_planes; i++) { | |
2489 | unsigned int width, height; | |
2490 | unsigned int cpp, size; | |
2491 | u32 offset; | |
2492 | int x, y; | |
2493 | ||
353c8598 | 2494 | cpp = fb->format->cpp[i]; |
145fcb11 VS |
2495 | width = drm_framebuffer_plane_width(fb->width, fb, i); |
2496 | height = drm_framebuffer_plane_height(fb->height, fb, i); | |
6687c906 VS |
2497 | |
2498 | intel_fb_offset_to_xy(&x, &y, fb, i); | |
2499 | ||
2e2adb05 VS |
2500 | if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || |
2501 | fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) && i == 1) { | |
2502 | int hsub = fb->format->hsub; | |
2503 | int vsub = fb->format->vsub; | |
2504 | int tile_width, tile_height; | |
2505 | int main_x, main_y; | |
2506 | int ccs_x, ccs_y; | |
2507 | ||
2508 | intel_tile_dims(fb, i, &tile_width, &tile_height); | |
2509 | ||
2510 | ccs_x = (x * hsub) % (tile_width * hsub); | |
2511 | ccs_y = (y * vsub) % (tile_height * vsub); | |
2512 | main_x = intel_fb->normal[0].x % (tile_width * hsub); | |
2513 | main_y = intel_fb->normal[0].y % (tile_height * vsub); | |
2514 | ||
2515 | /* | |
2516 | * CCS doesn't have its own x/y offset register, so the intra CCS tile | |
2517 | * x/y offsets must match between CCS and the main surface. | |
2518 | */ | |
2519 | if (main_x != ccs_x || main_y != ccs_y) { | |
2520 | DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n", | |
2521 | main_x, main_y, | |
2522 | ccs_x, ccs_y, | |
2523 | intel_fb->normal[0].x, | |
2524 | intel_fb->normal[0].y, | |
2525 | x, y); | |
2526 | return -EINVAL; | |
2527 | } | |
2528 | } | |
2529 | ||
60d5f2a4 VS |
2530 | /* |
2531 | * The fence (if used) is aligned to the start of the object | |
2532 | * so having the framebuffer wrap around across the edge of the | |
2533 | * fenced region doesn't really work. We have no API to configure | |
2534 | * the fence start offset within the object (nor could we probably | |
2535 | * on gen2/3). So it's just easier if we just require that the | |
2536 | * fb layout agrees with the fence layout. We already check that the | |
2537 | * fb stride matches the fence stride elsewhere. | |
2538 | */ | |
2539 | if (i915_gem_object_is_tiled(intel_fb->obj) && | |
2540 | (x + width) * cpp > fb->pitches[i]) { | |
144cc143 VS |
2541 | DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n", |
2542 | i, fb->offsets[i]); | |
60d5f2a4 VS |
2543 | return -EINVAL; |
2544 | } | |
2545 | ||
6687c906 VS |
2546 | /* |
2547 | * First pixel of the framebuffer from | |
2548 | * the start of the normal gtt mapping. | |
2549 | */ | |
2550 | intel_fb->normal[i].x = x; | |
2551 | intel_fb->normal[i].y = y; | |
2552 | ||
2553 | offset = _intel_compute_tile_offset(dev_priv, &x, &y, | |
3ca46c0a | 2554 | fb, i, fb->pitches[i], |
c2c446ad | 2555 | DRM_MODE_ROTATE_0, tile_size); |
6687c906 VS |
2556 | offset /= tile_size; |
2557 | ||
2f075565 | 2558 | if (fb->modifier != DRM_FORMAT_MOD_LINEAR) { |
6687c906 VS |
2559 | unsigned int tile_width, tile_height; |
2560 | unsigned int pitch_tiles; | |
2561 | struct drm_rect r; | |
2562 | ||
d88c4afd | 2563 | intel_tile_dims(fb, i, &tile_width, &tile_height); |
6687c906 VS |
2564 | |
2565 | rot_info->plane[i].offset = offset; | |
2566 | rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp); | |
2567 | rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width); | |
2568 | rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height); | |
2569 | ||
2570 | intel_fb->rotated[i].pitch = | |
2571 | rot_info->plane[i].height * tile_height; | |
2572 | ||
2573 | /* how many tiles does this plane need */ | |
2574 | size = rot_info->plane[i].stride * rot_info->plane[i].height; | |
2575 | /* | |
2576 | * If the plane isn't horizontally tile aligned, | |
2577 | * we need one more tile. | |
2578 | */ | |
2579 | if (x != 0) | |
2580 | size++; | |
2581 | ||
2582 | /* rotate the x/y offsets to match the GTT view */ | |
2583 | r.x1 = x; | |
2584 | r.y1 = y; | |
2585 | r.x2 = x + width; | |
2586 | r.y2 = y + height; | |
2587 | drm_rect_rotate(&r, | |
2588 | rot_info->plane[i].width * tile_width, | |
2589 | rot_info->plane[i].height * tile_height, | |
c2c446ad | 2590 | DRM_MODE_ROTATE_270); |
6687c906 VS |
2591 | x = r.x1; |
2592 | y = r.y1; | |
2593 | ||
2594 | /* rotate the tile dimensions to match the GTT view */ | |
2595 | pitch_tiles = intel_fb->rotated[i].pitch / tile_height; | |
2596 | swap(tile_width, tile_height); | |
2597 | ||
2598 | /* | |
2599 | * We only keep the x/y offsets, so push all of the | |
2600 | * gtt offset into the x/y offsets. | |
2601 | */ | |
46a1bd28 ACO |
2602 | _intel_adjust_tile_offset(&x, &y, |
2603 | tile_width, tile_height, | |
2604 | tile_size, pitch_tiles, | |
66a2d927 | 2605 | gtt_offset_rotated * tile_size, 0); |
6687c906 VS |
2606 | |
2607 | gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height; | |
2608 | ||
2609 | /* | |
2610 | * First pixel of the framebuffer from | |
2611 | * the start of the rotated gtt mapping. | |
2612 | */ | |
2613 | intel_fb->rotated[i].x = x; | |
2614 | intel_fb->rotated[i].y = y; | |
2615 | } else { | |
2616 | size = DIV_ROUND_UP((y + height) * fb->pitches[i] + | |
2617 | x * cpp, tile_size); | |
2618 | } | |
2619 | ||
2620 | /* how many tiles in total needed in the bo */ | |
2621 | max_size = max(max_size, offset + size); | |
2622 | } | |
2623 | ||
144cc143 VS |
2624 | if (max_size * tile_size > intel_fb->obj->base.size) { |
2625 | DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n", | |
2626 | max_size * tile_size, intel_fb->obj->base.size); | |
6687c906 VS |
2627 | return -EINVAL; |
2628 | } | |
2629 | ||
2630 | return 0; | |
2631 | } | |
2632 | ||
b35d63fa | 2633 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2634 | { |
2635 | switch (format) { | |
2636 | case DISPPLANE_8BPP: | |
2637 | return DRM_FORMAT_C8; | |
2638 | case DISPPLANE_BGRX555: | |
2639 | return DRM_FORMAT_XRGB1555; | |
2640 | case DISPPLANE_BGRX565: | |
2641 | return DRM_FORMAT_RGB565; | |
2642 | default: | |
2643 | case DISPPLANE_BGRX888: | |
2644 | return DRM_FORMAT_XRGB8888; | |
2645 | case DISPPLANE_RGBX888: | |
2646 | return DRM_FORMAT_XBGR8888; | |
2647 | case DISPPLANE_BGRX101010: | |
2648 | return DRM_FORMAT_XRGB2101010; | |
2649 | case DISPPLANE_RGBX101010: | |
2650 | return DRM_FORMAT_XBGR2101010; | |
2651 | } | |
2652 | } | |
2653 | ||
bc8d7dff DL |
2654 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2655 | { | |
2656 | switch (format) { | |
2657 | case PLANE_CTL_FORMAT_RGB_565: | |
2658 | return DRM_FORMAT_RGB565; | |
2659 | default: | |
2660 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2661 | if (rgb_order) { | |
2662 | if (alpha) | |
2663 | return DRM_FORMAT_ABGR8888; | |
2664 | else | |
2665 | return DRM_FORMAT_XBGR8888; | |
2666 | } else { | |
2667 | if (alpha) | |
2668 | return DRM_FORMAT_ARGB8888; | |
2669 | else | |
2670 | return DRM_FORMAT_XRGB8888; | |
2671 | } | |
2672 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2673 | if (rgb_order) | |
2674 | return DRM_FORMAT_XBGR2101010; | |
2675 | else | |
2676 | return DRM_FORMAT_XRGB2101010; | |
2677 | } | |
2678 | } | |
2679 | ||
5724dbd1 | 2680 | static bool |
f6936e29 DV |
2681 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2682 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2683 | { |
2684 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2685 | struct drm_i915_private *dev_priv = to_i915(dev); |
72e96d64 | 2686 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
46f297fb JB |
2687 | struct drm_i915_gem_object *obj = NULL; |
2688 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2689 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2690 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2691 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2692 | PAGE_SIZE); | |
2693 | ||
2694 | size_aligned -= base_aligned; | |
46f297fb | 2695 | |
ff2652ea CW |
2696 | if (plane_config->size == 0) |
2697 | return false; | |
2698 | ||
3badb49f PZ |
2699 | /* If the FB is too big, just don't use it since fbdev is not very |
2700 | * important and we should probably use that space with FBC or other | |
2701 | * features. */ | |
72e96d64 | 2702 | if (size_aligned * 2 > ggtt->stolen_usable_size) |
3badb49f PZ |
2703 | return false; |
2704 | ||
12c83d99 | 2705 | mutex_lock(&dev->struct_mutex); |
187685cb | 2706 | obj = i915_gem_object_create_stolen_for_preallocated(dev_priv, |
f37b5c2b DV |
2707 | base_aligned, |
2708 | base_aligned, | |
2709 | size_aligned); | |
24dbf51a CW |
2710 | mutex_unlock(&dev->struct_mutex); |
2711 | if (!obj) | |
484b41dd | 2712 | return false; |
46f297fb | 2713 | |
3e510a8e CW |
2714 | if (plane_config->tiling == I915_TILING_X) |
2715 | obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X; | |
46f297fb | 2716 | |
438b74a5 | 2717 | mode_cmd.pixel_format = fb->format->format; |
6bf129df DL |
2718 | mode_cmd.width = fb->width; |
2719 | mode_cmd.height = fb->height; | |
2720 | mode_cmd.pitches[0] = fb->pitches[0]; | |
bae781b2 | 2721 | mode_cmd.modifier[0] = fb->modifier; |
18c5247e | 2722 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; |
46f297fb | 2723 | |
24dbf51a | 2724 | if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) { |
46f297fb JB |
2725 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2726 | goto out_unref_obj; | |
2727 | } | |
12c83d99 | 2728 | |
484b41dd | 2729 | |
f6936e29 | 2730 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2731 | return true; |
46f297fb JB |
2732 | |
2733 | out_unref_obj: | |
f8c417cd | 2734 | i915_gem_object_put(obj); |
484b41dd JB |
2735 | return false; |
2736 | } | |
2737 | ||
e9728bd8 VS |
2738 | static void |
2739 | intel_set_plane_visible(struct intel_crtc_state *crtc_state, | |
2740 | struct intel_plane_state *plane_state, | |
2741 | bool visible) | |
2742 | { | |
2743 | struct intel_plane *plane = to_intel_plane(plane_state->base.plane); | |
2744 | ||
2745 | plane_state->base.visible = visible; | |
2746 | ||
2747 | /* FIXME pre-g4x don't work like this */ | |
2748 | if (visible) { | |
2749 | crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base)); | |
2750 | crtc_state->active_planes |= BIT(plane->id); | |
2751 | } else { | |
2752 | crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base)); | |
2753 | crtc_state->active_planes &= ~BIT(plane->id); | |
2754 | } | |
2755 | ||
2756 | DRM_DEBUG_KMS("%s active planes 0x%x\n", | |
2757 | crtc_state->base.crtc->name, | |
2758 | crtc_state->active_planes); | |
2759 | } | |
2760 | ||
5724dbd1 | 2761 | static void |
f6936e29 DV |
2762 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2763 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2764 | { |
2765 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 2766 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 2767 | struct drm_crtc *c; |
2ff8fde1 | 2768 | struct drm_i915_gem_object *obj; |
88595ac9 | 2769 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2770 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2771 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2772 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2773 | struct intel_plane_state *intel_state = |
2774 | to_intel_plane_state(plane_state); | |
88595ac9 | 2775 | struct drm_framebuffer *fb; |
484b41dd | 2776 | |
2d14030b | 2777 | if (!plane_config->fb) |
484b41dd JB |
2778 | return; |
2779 | ||
f6936e29 | 2780 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2781 | fb = &plane_config->fb->base; |
2782 | goto valid_fb; | |
f55548b5 | 2783 | } |
484b41dd | 2784 | |
2d14030b | 2785 | kfree(plane_config->fb); |
484b41dd JB |
2786 | |
2787 | /* | |
2788 | * Failed to alloc the obj, check to see if we should share | |
2789 | * an fb with another CRTC instead | |
2790 | */ | |
70e1e0ec | 2791 | for_each_crtc(dev, c) { |
be1e3415 | 2792 | struct intel_plane_state *state; |
484b41dd JB |
2793 | |
2794 | if (c == &intel_crtc->base) | |
2795 | continue; | |
2796 | ||
be1e3415 | 2797 | if (!to_intel_crtc(c)->active) |
2ff8fde1 MR |
2798 | continue; |
2799 | ||
be1e3415 CW |
2800 | state = to_intel_plane_state(c->primary->state); |
2801 | if (!state->vma) | |
484b41dd JB |
2802 | continue; |
2803 | ||
be1e3415 CW |
2804 | if (intel_plane_ggtt_offset(state) == plane_config->base) { |
2805 | fb = c->primary->fb; | |
88595ac9 DV |
2806 | drm_framebuffer_reference(fb); |
2807 | goto valid_fb; | |
484b41dd JB |
2808 | } |
2809 | } | |
88595ac9 | 2810 | |
200757f5 MR |
2811 | /* |
2812 | * We've failed to reconstruct the BIOS FB. Current display state | |
2813 | * indicates that the primary plane is visible, but has a NULL FB, | |
2814 | * which will lead to problems later if we don't fix it up. The | |
2815 | * simplest solution is to just disable the primary plane now and | |
2816 | * pretend the BIOS never had it enabled. | |
2817 | */ | |
e9728bd8 VS |
2818 | intel_set_plane_visible(to_intel_crtc_state(crtc_state), |
2819 | to_intel_plane_state(plane_state), | |
2820 | false); | |
2622a081 | 2821 | intel_pre_disable_primary_noatomic(&intel_crtc->base); |
72259536 | 2822 | trace_intel_disable_plane(primary, intel_crtc); |
282dbf9b | 2823 | intel_plane->disable_plane(intel_plane, intel_crtc); |
200757f5 | 2824 | |
88595ac9 DV |
2825 | return; |
2826 | ||
2827 | valid_fb: | |
be1e3415 CW |
2828 | mutex_lock(&dev->struct_mutex); |
2829 | intel_state->vma = | |
2830 | intel_pin_and_fence_fb_obj(fb, primary->state->rotation); | |
2831 | mutex_unlock(&dev->struct_mutex); | |
2832 | if (IS_ERR(intel_state->vma)) { | |
2833 | DRM_ERROR("failed to pin boot fb on pipe %d: %li\n", | |
2834 | intel_crtc->pipe, PTR_ERR(intel_state->vma)); | |
2835 | ||
2836 | intel_state->vma = NULL; | |
2837 | drm_framebuffer_unreference(fb); | |
2838 | return; | |
2839 | } | |
2840 | ||
f44e2659 VS |
2841 | plane_state->src_x = 0; |
2842 | plane_state->src_y = 0; | |
be5651f2 ML |
2843 | plane_state->src_w = fb->width << 16; |
2844 | plane_state->src_h = fb->height << 16; | |
2845 | ||
f44e2659 VS |
2846 | plane_state->crtc_x = 0; |
2847 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2848 | plane_state->crtc_w = fb->width; |
2849 | plane_state->crtc_h = fb->height; | |
2850 | ||
1638d30c RC |
2851 | intel_state->base.src = drm_plane_state_src(plane_state); |
2852 | intel_state->base.dst = drm_plane_state_dest(plane_state); | |
0a8d8a86 | 2853 | |
88595ac9 | 2854 | obj = intel_fb_obj(fb); |
3e510a8e | 2855 | if (i915_gem_object_is_tiled(obj)) |
88595ac9 DV |
2856 | dev_priv->preserve_bios_swizzle = true; |
2857 | ||
be5651f2 ML |
2858 | drm_framebuffer_reference(fb); |
2859 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2860 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
e9728bd8 VS |
2861 | |
2862 | intel_set_plane_visible(to_intel_crtc_state(crtc_state), | |
2863 | to_intel_plane_state(plane_state), | |
2864 | true); | |
2865 | ||
faf5bf0a CW |
2866 | atomic_or(to_intel_plane(primary)->frontbuffer_bit, |
2867 | &obj->frontbuffer_bits); | |
46f297fb JB |
2868 | } |
2869 | ||
b63a16f6 VS |
2870 | static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane, |
2871 | unsigned int rotation) | |
2872 | { | |
353c8598 | 2873 | int cpp = fb->format->cpp[plane]; |
b63a16f6 | 2874 | |
bae781b2 | 2875 | switch (fb->modifier) { |
2f075565 | 2876 | case DRM_FORMAT_MOD_LINEAR: |
b63a16f6 VS |
2877 | case I915_FORMAT_MOD_X_TILED: |
2878 | switch (cpp) { | |
2879 | case 8: | |
2880 | return 4096; | |
2881 | case 4: | |
2882 | case 2: | |
2883 | case 1: | |
2884 | return 8192; | |
2885 | default: | |
2886 | MISSING_CASE(cpp); | |
2887 | break; | |
2888 | } | |
2889 | break; | |
2e2adb05 VS |
2890 | case I915_FORMAT_MOD_Y_TILED_CCS: |
2891 | case I915_FORMAT_MOD_Yf_TILED_CCS: | |
2892 | /* FIXME AUX plane? */ | |
b63a16f6 VS |
2893 | case I915_FORMAT_MOD_Y_TILED: |
2894 | case I915_FORMAT_MOD_Yf_TILED: | |
2895 | switch (cpp) { | |
2896 | case 8: | |
2897 | return 2048; | |
2898 | case 4: | |
2899 | return 4096; | |
2900 | case 2: | |
2901 | case 1: | |
2902 | return 8192; | |
2903 | default: | |
2904 | MISSING_CASE(cpp); | |
2905 | break; | |
2906 | } | |
2907 | break; | |
2908 | default: | |
bae781b2 | 2909 | MISSING_CASE(fb->modifier); |
b63a16f6 VS |
2910 | } |
2911 | ||
2912 | return 2048; | |
2913 | } | |
2914 | ||
2e2adb05 VS |
2915 | static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state, |
2916 | int main_x, int main_y, u32 main_offset) | |
2917 | { | |
2918 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2919 | int hsub = fb->format->hsub; | |
2920 | int vsub = fb->format->vsub; | |
2921 | int aux_x = plane_state->aux.x; | |
2922 | int aux_y = plane_state->aux.y; | |
2923 | u32 aux_offset = plane_state->aux.offset; | |
2924 | u32 alignment = intel_surf_alignment(fb, 1); | |
2925 | ||
2926 | while (aux_offset >= main_offset && aux_y <= main_y) { | |
2927 | int x, y; | |
2928 | ||
2929 | if (aux_x == main_x && aux_y == main_y) | |
2930 | break; | |
2931 | ||
2932 | if (aux_offset == 0) | |
2933 | break; | |
2934 | ||
2935 | x = aux_x / hsub; | |
2936 | y = aux_y / vsub; | |
2937 | aux_offset = intel_adjust_tile_offset(&x, &y, plane_state, 1, | |
2938 | aux_offset, aux_offset - alignment); | |
2939 | aux_x = x * hsub + aux_x % hsub; | |
2940 | aux_y = y * vsub + aux_y % vsub; | |
2941 | } | |
2942 | ||
2943 | if (aux_x != main_x || aux_y != main_y) | |
2944 | return false; | |
2945 | ||
2946 | plane_state->aux.offset = aux_offset; | |
2947 | plane_state->aux.x = aux_x; | |
2948 | plane_state->aux.y = aux_y; | |
2949 | ||
2950 | return true; | |
2951 | } | |
2952 | ||
b63a16f6 VS |
2953 | static int skl_check_main_surface(struct intel_plane_state *plane_state) |
2954 | { | |
b63a16f6 VS |
2955 | const struct drm_framebuffer *fb = plane_state->base.fb; |
2956 | unsigned int rotation = plane_state->base.rotation; | |
cc926387 DV |
2957 | int x = plane_state->base.src.x1 >> 16; |
2958 | int y = plane_state->base.src.y1 >> 16; | |
2959 | int w = drm_rect_width(&plane_state->base.src) >> 16; | |
2960 | int h = drm_rect_height(&plane_state->base.src) >> 16; | |
b63a16f6 VS |
2961 | int max_width = skl_max_plane_width(fb, 0, rotation); |
2962 | int max_height = 4096; | |
8d970654 | 2963 | u32 alignment, offset, aux_offset = plane_state->aux.offset; |
b63a16f6 VS |
2964 | |
2965 | if (w > max_width || h > max_height) { | |
2966 | DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n", | |
2967 | w, h, max_width, max_height); | |
2968 | return -EINVAL; | |
2969 | } | |
2970 | ||
2971 | intel_add_fb_offsets(&x, &y, plane_state, 0); | |
2972 | offset = intel_compute_tile_offset(&x, &y, plane_state, 0); | |
d88c4afd | 2973 | alignment = intel_surf_alignment(fb, 0); |
b63a16f6 | 2974 | |
8d970654 VS |
2975 | /* |
2976 | * AUX surface offset is specified as the distance from the | |
2977 | * main surface offset, and it must be non-negative. Make | |
2978 | * sure that is what we will get. | |
2979 | */ | |
2980 | if (offset > aux_offset) | |
2981 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
2982 | offset, aux_offset & ~(alignment - 1)); | |
2983 | ||
b63a16f6 VS |
2984 | /* |
2985 | * When using an X-tiled surface, the plane blows up | |
2986 | * if the x offset + width exceed the stride. | |
2987 | * | |
2988 | * TODO: linear and Y-tiled seem fine, Yf untested, | |
2989 | */ | |
bae781b2 | 2990 | if (fb->modifier == I915_FORMAT_MOD_X_TILED) { |
353c8598 | 2991 | int cpp = fb->format->cpp[0]; |
b63a16f6 VS |
2992 | |
2993 | while ((x + w) * cpp > fb->pitches[0]) { | |
2994 | if (offset == 0) { | |
2e2adb05 | 2995 | DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n"); |
b63a16f6 VS |
2996 | return -EINVAL; |
2997 | } | |
2998 | ||
2999 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
3000 | offset, offset - alignment); | |
3001 | } | |
3002 | } | |
3003 | ||
2e2adb05 VS |
3004 | /* |
3005 | * CCS AUX surface doesn't have its own x/y offsets, we must make sure | |
3006 | * they match with the main surface x/y offsets. | |
3007 | */ | |
3008 | if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || | |
3009 | fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) { | |
3010 | while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) { | |
3011 | if (offset == 0) | |
3012 | break; | |
3013 | ||
3014 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
3015 | offset, offset - alignment); | |
3016 | } | |
3017 | ||
3018 | if (x != plane_state->aux.x || y != plane_state->aux.y) { | |
3019 | DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n"); | |
3020 | return -EINVAL; | |
3021 | } | |
3022 | } | |
3023 | ||
b63a16f6 VS |
3024 | plane_state->main.offset = offset; |
3025 | plane_state->main.x = x; | |
3026 | plane_state->main.y = y; | |
3027 | ||
3028 | return 0; | |
3029 | } | |
3030 | ||
8d970654 VS |
3031 | static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) |
3032 | { | |
3033 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3034 | unsigned int rotation = plane_state->base.rotation; | |
3035 | int max_width = skl_max_plane_width(fb, 1, rotation); | |
3036 | int max_height = 4096; | |
cc926387 DV |
3037 | int x = plane_state->base.src.x1 >> 17; |
3038 | int y = plane_state->base.src.y1 >> 17; | |
3039 | int w = drm_rect_width(&plane_state->base.src) >> 17; | |
3040 | int h = drm_rect_height(&plane_state->base.src) >> 17; | |
8d970654 VS |
3041 | u32 offset; |
3042 | ||
3043 | intel_add_fb_offsets(&x, &y, plane_state, 1); | |
3044 | offset = intel_compute_tile_offset(&x, &y, plane_state, 1); | |
3045 | ||
3046 | /* FIXME not quite sure how/if these apply to the chroma plane */ | |
3047 | if (w > max_width || h > max_height) { | |
3048 | DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n", | |
3049 | w, h, max_width, max_height); | |
3050 | return -EINVAL; | |
3051 | } | |
3052 | ||
3053 | plane_state->aux.offset = offset; | |
3054 | plane_state->aux.x = x; | |
3055 | plane_state->aux.y = y; | |
3056 | ||
3057 | return 0; | |
3058 | } | |
3059 | ||
2e2adb05 VS |
3060 | static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state) |
3061 | { | |
3062 | struct intel_plane *plane = to_intel_plane(plane_state->base.plane); | |
3063 | struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc); | |
3064 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3065 | int src_x = plane_state->base.src.x1 >> 16; | |
3066 | int src_y = plane_state->base.src.y1 >> 16; | |
3067 | int hsub = fb->format->hsub; | |
3068 | int vsub = fb->format->vsub; | |
3069 | int x = src_x / hsub; | |
3070 | int y = src_y / vsub; | |
3071 | u32 offset; | |
3072 | ||
3073 | switch (plane->id) { | |
3074 | case PLANE_PRIMARY: | |
3075 | case PLANE_SPRITE0: | |
3076 | break; | |
3077 | default: | |
3078 | DRM_DEBUG_KMS("RC support only on plane 1 and 2\n"); | |
3079 | return -EINVAL; | |
3080 | } | |
3081 | ||
3082 | if (crtc->pipe == PIPE_C) { | |
3083 | DRM_DEBUG_KMS("No RC support on pipe C\n"); | |
3084 | return -EINVAL; | |
3085 | } | |
3086 | ||
3087 | if (plane_state->base.rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180)) { | |
3088 | DRM_DEBUG_KMS("RC support only with 0/180 degree rotation %x\n", | |
3089 | plane_state->base.rotation); | |
3090 | return -EINVAL; | |
3091 | } | |
3092 | ||
3093 | intel_add_fb_offsets(&x, &y, plane_state, 1); | |
3094 | offset = intel_compute_tile_offset(&x, &y, plane_state, 1); | |
3095 | ||
3096 | plane_state->aux.offset = offset; | |
3097 | plane_state->aux.x = x * hsub + src_x % hsub; | |
3098 | plane_state->aux.y = y * vsub + src_y % vsub; | |
3099 | ||
3100 | return 0; | |
3101 | } | |
3102 | ||
b63a16f6 VS |
3103 | int skl_check_plane_surface(struct intel_plane_state *plane_state) |
3104 | { | |
3105 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3106 | unsigned int rotation = plane_state->base.rotation; | |
3107 | int ret; | |
3108 | ||
a5e4c7d0 VS |
3109 | if (!plane_state->base.visible) |
3110 | return 0; | |
3111 | ||
b63a16f6 | 3112 | /* Rotate src coordinates to match rotated GTT view */ |
bd2ef25d | 3113 | if (drm_rotation_90_or_270(rotation)) |
cc926387 | 3114 | drm_rect_rotate(&plane_state->base.src, |
da064b47 | 3115 | fb->width << 16, fb->height << 16, |
c2c446ad | 3116 | DRM_MODE_ROTATE_270); |
b63a16f6 | 3117 | |
8d970654 VS |
3118 | /* |
3119 | * Handle the AUX surface first since | |
3120 | * the main surface setup depends on it. | |
3121 | */ | |
438b74a5 | 3122 | if (fb->format->format == DRM_FORMAT_NV12) { |
8d970654 VS |
3123 | ret = skl_check_nv12_aux_surface(plane_state); |
3124 | if (ret) | |
3125 | return ret; | |
2e2adb05 VS |
3126 | } else if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || |
3127 | fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) { | |
3128 | ret = skl_check_ccs_aux_surface(plane_state); | |
3129 | if (ret) | |
3130 | return ret; | |
8d970654 VS |
3131 | } else { |
3132 | plane_state->aux.offset = ~0xfff; | |
3133 | plane_state->aux.x = 0; | |
3134 | plane_state->aux.y = 0; | |
3135 | } | |
3136 | ||
b63a16f6 VS |
3137 | ret = skl_check_main_surface(plane_state); |
3138 | if (ret) | |
3139 | return ret; | |
3140 | ||
3141 | return 0; | |
3142 | } | |
3143 | ||
7145f60a VS |
3144 | static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, |
3145 | const struct intel_plane_state *plane_state) | |
81255565 | 3146 | { |
7145f60a VS |
3147 | struct drm_i915_private *dev_priv = |
3148 | to_i915(plane_state->base.plane->dev); | |
3149 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
3150 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
8d0deca8 | 3151 | unsigned int rotation = plane_state->base.rotation; |
7145f60a | 3152 | u32 dspcntr; |
c9ba6fad | 3153 | |
7145f60a | 3154 | dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE; |
f45651ba | 3155 | |
6a4407a6 VS |
3156 | if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) || |
3157 | IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) | |
7145f60a | 3158 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
f45651ba | 3159 | |
6a4407a6 VS |
3160 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
3161 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
f45651ba | 3162 | |
d509e28b VS |
3163 | if (INTEL_GEN(dev_priv) < 4) |
3164 | dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe); | |
81255565 | 3165 | |
438b74a5 | 3166 | switch (fb->format->format) { |
57779d06 | 3167 | case DRM_FORMAT_C8: |
81255565 JB |
3168 | dspcntr |= DISPPLANE_8BPP; |
3169 | break; | |
57779d06 | 3170 | case DRM_FORMAT_XRGB1555: |
57779d06 | 3171 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 3172 | break; |
57779d06 VS |
3173 | case DRM_FORMAT_RGB565: |
3174 | dspcntr |= DISPPLANE_BGRX565; | |
3175 | break; | |
3176 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
3177 | dspcntr |= DISPPLANE_BGRX888; |
3178 | break; | |
3179 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
3180 | dspcntr |= DISPPLANE_RGBX888; |
3181 | break; | |
3182 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
3183 | dspcntr |= DISPPLANE_BGRX101010; |
3184 | break; | |
3185 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 3186 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
3187 | break; |
3188 | default: | |
7145f60a VS |
3189 | MISSING_CASE(fb->format->format); |
3190 | return 0; | |
81255565 | 3191 | } |
57779d06 | 3192 | |
72618ebf | 3193 | if (INTEL_GEN(dev_priv) >= 4 && |
bae781b2 | 3194 | fb->modifier == I915_FORMAT_MOD_X_TILED) |
f45651ba | 3195 | dspcntr |= DISPPLANE_TILED; |
81255565 | 3196 | |
c2c446ad | 3197 | if (rotation & DRM_MODE_ROTATE_180) |
df0cd455 VS |
3198 | dspcntr |= DISPPLANE_ROTATE_180; |
3199 | ||
c2c446ad | 3200 | if (rotation & DRM_MODE_REFLECT_X) |
4ea7be2b VS |
3201 | dspcntr |= DISPPLANE_MIRROR; |
3202 | ||
7145f60a VS |
3203 | return dspcntr; |
3204 | } | |
de1aa629 | 3205 | |
f9407ae1 | 3206 | int i9xx_check_plane_surface(struct intel_plane_state *plane_state) |
5b7fcc44 VS |
3207 | { |
3208 | struct drm_i915_private *dev_priv = | |
3209 | to_i915(plane_state->base.plane->dev); | |
3210 | int src_x = plane_state->base.src.x1 >> 16; | |
3211 | int src_y = plane_state->base.src.y1 >> 16; | |
3212 | u32 offset; | |
81255565 | 3213 | |
5b7fcc44 | 3214 | intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); |
e506a0c6 | 3215 | |
5b7fcc44 VS |
3216 | if (INTEL_GEN(dev_priv) >= 4) |
3217 | offset = intel_compute_tile_offset(&src_x, &src_y, | |
3218 | plane_state, 0); | |
3219 | else | |
3220 | offset = 0; | |
3221 | ||
3222 | /* HSW/BDW do this automagically in hardware */ | |
3223 | if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) { | |
3224 | unsigned int rotation = plane_state->base.rotation; | |
3225 | int src_w = drm_rect_width(&plane_state->base.src) >> 16; | |
3226 | int src_h = drm_rect_height(&plane_state->base.src) >> 16; | |
3227 | ||
c2c446ad | 3228 | if (rotation & DRM_MODE_ROTATE_180) { |
5b7fcc44 VS |
3229 | src_x += src_w - 1; |
3230 | src_y += src_h - 1; | |
c2c446ad | 3231 | } else if (rotation & DRM_MODE_REFLECT_X) { |
5b7fcc44 VS |
3232 | src_x += src_w - 1; |
3233 | } | |
48404c1e SJ |
3234 | } |
3235 | ||
5b7fcc44 VS |
3236 | plane_state->main.offset = offset; |
3237 | plane_state->main.x = src_x; | |
3238 | plane_state->main.y = src_y; | |
3239 | ||
3240 | return 0; | |
3241 | } | |
3242 | ||
282dbf9b | 3243 | static void i9xx_update_primary_plane(struct intel_plane *primary, |
7145f60a VS |
3244 | const struct intel_crtc_state *crtc_state, |
3245 | const struct intel_plane_state *plane_state) | |
3246 | { | |
282dbf9b VS |
3247 | struct drm_i915_private *dev_priv = to_i915(primary->base.dev); |
3248 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
3249 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3250 | enum plane plane = primary->plane; | |
7145f60a | 3251 | u32 linear_offset; |
a0864d59 | 3252 | u32 dspcntr = plane_state->ctl; |
7145f60a | 3253 | i915_reg_t reg = DSPCNTR(plane); |
5b7fcc44 VS |
3254 | int x = plane_state->main.x; |
3255 | int y = plane_state->main.y; | |
7145f60a VS |
3256 | unsigned long irqflags; |
3257 | ||
2949056c | 3258 | linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); |
6687c906 | 3259 | |
5b7fcc44 | 3260 | if (INTEL_GEN(dev_priv) >= 4) |
282dbf9b | 3261 | crtc->dspaddr_offset = plane_state->main.offset; |
5b7fcc44 | 3262 | else |
282dbf9b | 3263 | crtc->dspaddr_offset = linear_offset; |
6687c906 | 3264 | |
282dbf9b VS |
3265 | crtc->adjusted_x = x; |
3266 | crtc->adjusted_y = y; | |
2db3366b | 3267 | |
dd584fc0 VS |
3268 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
3269 | ||
78587de2 VS |
3270 | if (INTEL_GEN(dev_priv) < 4) { |
3271 | /* pipesrc and dspsize control the size that is scaled from, | |
3272 | * which should always be the user's requested size. | |
3273 | */ | |
dd584fc0 VS |
3274 | I915_WRITE_FW(DSPSIZE(plane), |
3275 | ((crtc_state->pipe_src_h - 1) << 16) | | |
3276 | (crtc_state->pipe_src_w - 1)); | |
3277 | I915_WRITE_FW(DSPPOS(plane), 0); | |
78587de2 | 3278 | } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) { |
dd584fc0 VS |
3279 | I915_WRITE_FW(PRIMSIZE(plane), |
3280 | ((crtc_state->pipe_src_h - 1) << 16) | | |
3281 | (crtc_state->pipe_src_w - 1)); | |
3282 | I915_WRITE_FW(PRIMPOS(plane), 0); | |
3283 | I915_WRITE_FW(PRIMCNSTALPHA(plane), 0); | |
78587de2 VS |
3284 | } |
3285 | ||
dd584fc0 | 3286 | I915_WRITE_FW(reg, dspcntr); |
48404c1e | 3287 | |
dd584fc0 | 3288 | I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]); |
3ba35e53 VS |
3289 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3290 | I915_WRITE_FW(DSPSURF(plane), | |
3291 | intel_plane_ggtt_offset(plane_state) + | |
282dbf9b | 3292 | crtc->dspaddr_offset); |
3ba35e53 VS |
3293 | I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x); |
3294 | } else if (INTEL_GEN(dev_priv) >= 4) { | |
dd584fc0 VS |
3295 | I915_WRITE_FW(DSPSURF(plane), |
3296 | intel_plane_ggtt_offset(plane_state) + | |
282dbf9b | 3297 | crtc->dspaddr_offset); |
dd584fc0 VS |
3298 | I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x); |
3299 | I915_WRITE_FW(DSPLINOFF(plane), linear_offset); | |
bfb81049 | 3300 | } else { |
dd584fc0 VS |
3301 | I915_WRITE_FW(DSPADDR(plane), |
3302 | intel_plane_ggtt_offset(plane_state) + | |
282dbf9b | 3303 | crtc->dspaddr_offset); |
bfb81049 | 3304 | } |
dd584fc0 VS |
3305 | POSTING_READ_FW(reg); |
3306 | ||
3307 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
17638cd6 JB |
3308 | } |
3309 | ||
282dbf9b VS |
3310 | static void i9xx_disable_primary_plane(struct intel_plane *primary, |
3311 | struct intel_crtc *crtc) | |
17638cd6 | 3312 | { |
282dbf9b VS |
3313 | struct drm_i915_private *dev_priv = to_i915(primary->base.dev); |
3314 | enum plane plane = primary->plane; | |
dd584fc0 VS |
3315 | unsigned long irqflags; |
3316 | ||
3317 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
f45651ba | 3318 | |
dd584fc0 | 3319 | I915_WRITE_FW(DSPCNTR(plane), 0); |
a8d201af | 3320 | if (INTEL_INFO(dev_priv)->gen >= 4) |
dd584fc0 | 3321 | I915_WRITE_FW(DSPSURF(plane), 0); |
a8d201af | 3322 | else |
dd584fc0 VS |
3323 | I915_WRITE_FW(DSPADDR(plane), 0); |
3324 | POSTING_READ_FW(DSPCNTR(plane)); | |
3325 | ||
3326 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
a8d201af | 3327 | } |
c9ba6fad | 3328 | |
d88c4afd VS |
3329 | static u32 |
3330 | intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane) | |
b321803d | 3331 | { |
2f075565 | 3332 | if (fb->modifier == DRM_FORMAT_MOD_LINEAR) |
b321803d | 3333 | return 64; |
d88c4afd VS |
3334 | else |
3335 | return intel_tile_width_bytes(fb, plane); | |
b321803d DL |
3336 | } |
3337 | ||
e435d6e5 ML |
3338 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
3339 | { | |
3340 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 3341 | struct drm_i915_private *dev_priv = to_i915(dev); |
e435d6e5 ML |
3342 | |
3343 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
3344 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
3345 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
3346 | } |
3347 | ||
a1b2278e CK |
3348 | /* |
3349 | * This function detaches (aka. unbinds) unused scalers in hardware | |
3350 | */ | |
0583236e | 3351 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 3352 | { |
a1b2278e CK |
3353 | struct intel_crtc_scaler_state *scaler_state; |
3354 | int i; | |
3355 | ||
a1b2278e CK |
3356 | scaler_state = &intel_crtc->config->scaler_state; |
3357 | ||
3358 | /* loop through and disable scalers that aren't in use */ | |
3359 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
3360 | if (!scaler_state->scalers[i].in_use) |
3361 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
3362 | } |
3363 | } | |
3364 | ||
d2196774 VS |
3365 | u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane, |
3366 | unsigned int rotation) | |
3367 | { | |
1b500535 VS |
3368 | u32 stride; |
3369 | ||
3370 | if (plane >= fb->format->num_planes) | |
3371 | return 0; | |
3372 | ||
3373 | stride = intel_fb_pitch(fb, plane, rotation); | |
d2196774 VS |
3374 | |
3375 | /* | |
3376 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
3377 | * linear buffers or in number of tiles for tiled buffers. | |
3378 | */ | |
d88c4afd VS |
3379 | if (drm_rotation_90_or_270(rotation)) |
3380 | stride /= intel_tile_height(fb, plane); | |
3381 | else | |
3382 | stride /= intel_fb_stride_alignment(fb, plane); | |
d2196774 VS |
3383 | |
3384 | return stride; | |
3385 | } | |
3386 | ||
2e881264 | 3387 | static u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 3388 | { |
6156a456 | 3389 | switch (pixel_format) { |
d161cf7a | 3390 | case DRM_FORMAT_C8: |
c34ce3d1 | 3391 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 3392 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 3393 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 3394 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 3395 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 3396 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 3397 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
3398 | /* |
3399 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
3400 | * to be already pre-multiplied. We need to add a knob (or a different | |
3401 | * DRM_FORMAT) for user-space to configure that. | |
3402 | */ | |
f75fb42a | 3403 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 3404 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 3405 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 3406 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 3407 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 3408 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 3409 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 3410 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 3411 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 3412 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 3413 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 3414 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 3415 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 3416 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 3417 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 3418 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 3419 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 3420 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 3421 | default: |
4249eeef | 3422 | MISSING_CASE(pixel_format); |
70d21f0e | 3423 | } |
8cfcba41 | 3424 | |
c34ce3d1 | 3425 | return 0; |
6156a456 | 3426 | } |
70d21f0e | 3427 | |
2e881264 | 3428 | static u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
6156a456 | 3429 | { |
6156a456 | 3430 | switch (fb_modifier) { |
2f075565 | 3431 | case DRM_FORMAT_MOD_LINEAR: |
70d21f0e | 3432 | break; |
30af77c4 | 3433 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 3434 | return PLANE_CTL_TILED_X; |
b321803d | 3435 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3436 | return PLANE_CTL_TILED_Y; |
2e2adb05 VS |
3437 | case I915_FORMAT_MOD_Y_TILED_CCS: |
3438 | return PLANE_CTL_TILED_Y | PLANE_CTL_DECOMPRESSION_ENABLE; | |
b321803d | 3439 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3440 | return PLANE_CTL_TILED_YF; |
2e2adb05 VS |
3441 | case I915_FORMAT_MOD_Yf_TILED_CCS: |
3442 | return PLANE_CTL_TILED_YF | PLANE_CTL_DECOMPRESSION_ENABLE; | |
70d21f0e | 3443 | default: |
6156a456 | 3444 | MISSING_CASE(fb_modifier); |
70d21f0e | 3445 | } |
8cfcba41 | 3446 | |
c34ce3d1 | 3447 | return 0; |
6156a456 | 3448 | } |
70d21f0e | 3449 | |
2e881264 | 3450 | static u32 skl_plane_ctl_rotation(unsigned int rotation) |
6156a456 | 3451 | { |
3b7a5119 | 3452 | switch (rotation) { |
c2c446ad | 3453 | case DRM_MODE_ROTATE_0: |
6156a456 | 3454 | break; |
1e8df167 | 3455 | /* |
c2c446ad | 3456 | * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr |
1e8df167 SJ |
3457 | * while i915 HW rotation is clockwise, thats why this swapping. |
3458 | */ | |
c2c446ad | 3459 | case DRM_MODE_ROTATE_90: |
1e8df167 | 3460 | return PLANE_CTL_ROTATE_270; |
c2c446ad | 3461 | case DRM_MODE_ROTATE_180: |
c34ce3d1 | 3462 | return PLANE_CTL_ROTATE_180; |
c2c446ad | 3463 | case DRM_MODE_ROTATE_270: |
1e8df167 | 3464 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3465 | default: |
3466 | MISSING_CASE(rotation); | |
3467 | } | |
3468 | ||
c34ce3d1 | 3469 | return 0; |
6156a456 CK |
3470 | } |
3471 | ||
2e881264 VS |
3472 | u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, |
3473 | const struct intel_plane_state *plane_state) | |
46f788ba VS |
3474 | { |
3475 | struct drm_i915_private *dev_priv = | |
3476 | to_i915(plane_state->base.plane->dev); | |
3477 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3478 | unsigned int rotation = plane_state->base.rotation; | |
2e881264 | 3479 | const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; |
46f788ba VS |
3480 | u32 plane_ctl; |
3481 | ||
3482 | plane_ctl = PLANE_CTL_ENABLE; | |
3483 | ||
6602be0e | 3484 | if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) { |
46f788ba VS |
3485 | plane_ctl |= |
3486 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3487 | PLANE_CTL_PIPE_CSC_ENABLE | | |
3488 | PLANE_CTL_PLANE_GAMMA_DISABLE; | |
3489 | } | |
3490 | ||
3491 | plane_ctl |= skl_plane_ctl_format(fb->format->format); | |
3492 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier); | |
3493 | plane_ctl |= skl_plane_ctl_rotation(rotation); | |
3494 | ||
2e881264 VS |
3495 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
3496 | plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION; | |
3497 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
3498 | plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; | |
3499 | ||
46f788ba VS |
3500 | return plane_ctl; |
3501 | } | |
3502 | ||
282dbf9b | 3503 | static void skylake_update_primary_plane(struct intel_plane *plane, |
a8d201af ML |
3504 | const struct intel_crtc_state *crtc_state, |
3505 | const struct intel_plane_state *plane_state) | |
6156a456 | 3506 | { |
282dbf9b VS |
3507 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
3508 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
3509 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3510 | enum plane_id plane_id = plane->id; | |
3511 | enum pipe pipe = plane->pipe; | |
a0864d59 | 3512 | u32 plane_ctl = plane_state->ctl; |
a8d201af | 3513 | unsigned int rotation = plane_state->base.rotation; |
d2196774 | 3514 | u32 stride = skl_plane_stride(fb, 0, rotation); |
2e2adb05 | 3515 | u32 aux_stride = skl_plane_stride(fb, 1, rotation); |
b63a16f6 | 3516 | u32 surf_addr = plane_state->main.offset; |
a8d201af | 3517 | int scaler_id = plane_state->scaler_id; |
b63a16f6 VS |
3518 | int src_x = plane_state->main.x; |
3519 | int src_y = plane_state->main.y; | |
936e71e3 VS |
3520 | int src_w = drm_rect_width(&plane_state->base.src) >> 16; |
3521 | int src_h = drm_rect_height(&plane_state->base.src) >> 16; | |
3522 | int dst_x = plane_state->base.dst.x1; | |
3523 | int dst_y = plane_state->base.dst.y1; | |
3524 | int dst_w = drm_rect_width(&plane_state->base.dst); | |
3525 | int dst_h = drm_rect_height(&plane_state->base.dst); | |
dd584fc0 | 3526 | unsigned long irqflags; |
70d21f0e | 3527 | |
6687c906 VS |
3528 | /* Sizes are 0 based */ |
3529 | src_w--; | |
3530 | src_h--; | |
3531 | dst_w--; | |
3532 | dst_h--; | |
3533 | ||
282dbf9b | 3534 | crtc->dspaddr_offset = surf_addr; |
4c0b8a8b | 3535 | |
282dbf9b VS |
3536 | crtc->adjusted_x = src_x; |
3537 | crtc->adjusted_y = src_y; | |
2db3366b | 3538 | |
dd584fc0 VS |
3539 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
3540 | ||
6602be0e | 3541 | if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) { |
dd584fc0 VS |
3542 | I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), |
3543 | PLANE_COLOR_PIPE_GAMMA_ENABLE | | |
3544 | PLANE_COLOR_PIPE_CSC_ENABLE | | |
3545 | PLANE_COLOR_PLANE_GAMMA_DISABLE); | |
78587de2 VS |
3546 | } |
3547 | ||
dd584fc0 VS |
3548 | I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl); |
3549 | I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x); | |
3550 | I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride); | |
3551 | I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); | |
2e2adb05 VS |
3552 | I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), |
3553 | (plane_state->aux.offset - surf_addr) | aux_stride); | |
3554 | I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id), | |
3555 | (plane_state->aux.y << 16) | plane_state->aux.x); | |
6156a456 CK |
3556 | |
3557 | if (scaler_id >= 0) { | |
3558 | uint32_t ps_ctrl = 0; | |
3559 | ||
3560 | WARN_ON(!dst_w || !dst_h); | |
8e816bb4 | 3561 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) | |
6156a456 | 3562 | crtc_state->scaler_state.scalers[scaler_id].mode; |
dd584fc0 VS |
3563 | I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); |
3564 | I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3565 | I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3566 | I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3567 | I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0); | |
6156a456 | 3568 | } else { |
dd584fc0 | 3569 | I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x); |
6156a456 CK |
3570 | } |
3571 | ||
dd584fc0 VS |
3572 | I915_WRITE_FW(PLANE_SURF(pipe, plane_id), |
3573 | intel_plane_ggtt_offset(plane_state) + surf_addr); | |
70d21f0e | 3574 | |
dd584fc0 VS |
3575 | POSTING_READ_FW(PLANE_SURF(pipe, plane_id)); |
3576 | ||
3577 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
70d21f0e DL |
3578 | } |
3579 | ||
282dbf9b VS |
3580 | static void skylake_disable_primary_plane(struct intel_plane *primary, |
3581 | struct intel_crtc *crtc) | |
17638cd6 | 3582 | { |
282dbf9b VS |
3583 | struct drm_i915_private *dev_priv = to_i915(primary->base.dev); |
3584 | enum plane_id plane_id = primary->id; | |
3585 | enum pipe pipe = primary->pipe; | |
dd584fc0 VS |
3586 | unsigned long irqflags; |
3587 | ||
3588 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
62e0fb88 | 3589 | |
dd584fc0 VS |
3590 | I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0); |
3591 | I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0); | |
3592 | POSTING_READ_FW(PLANE_SURF(pipe, plane_id)); | |
3593 | ||
3594 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
a8d201af | 3595 | } |
29b9bde6 | 3596 | |
73974893 ML |
3597 | static int |
3598 | __intel_display_resume(struct drm_device *dev, | |
581e49fe ML |
3599 | struct drm_atomic_state *state, |
3600 | struct drm_modeset_acquire_ctx *ctx) | |
73974893 ML |
3601 | { |
3602 | struct drm_crtc_state *crtc_state; | |
3603 | struct drm_crtc *crtc; | |
3604 | int i, ret; | |
11c22da6 | 3605 | |
aecd36b8 | 3606 | intel_modeset_setup_hw_state(dev, ctx); |
29b74b7f | 3607 | i915_redisable_vga(to_i915(dev)); |
73974893 ML |
3608 | |
3609 | if (!state) | |
3610 | return 0; | |
3611 | ||
aa5e9b47 ML |
3612 | /* |
3613 | * We've duplicated the state, pointers to the old state are invalid. | |
3614 | * | |
3615 | * Don't attempt to use the old state until we commit the duplicated state. | |
3616 | */ | |
3617 | for_each_new_crtc_in_state(state, crtc, crtc_state, i) { | |
73974893 ML |
3618 | /* |
3619 | * Force recalculation even if we restore | |
3620 | * current state. With fast modeset this may not result | |
3621 | * in a modeset when the state is compatible. | |
3622 | */ | |
3623 | crtc_state->mode_changed = true; | |
96a02917 | 3624 | } |
73974893 ML |
3625 | |
3626 | /* ignore any reset values/BIOS leftovers in the WM registers */ | |
602ae835 VS |
3627 | if (!HAS_GMCH_DISPLAY(to_i915(dev))) |
3628 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
73974893 | 3629 | |
581e49fe | 3630 | ret = drm_atomic_helper_commit_duplicated_state(state, ctx); |
73974893 ML |
3631 | |
3632 | WARN_ON(ret == -EDEADLK); | |
3633 | return ret; | |
96a02917 VS |
3634 | } |
3635 | ||
4ac2ba2f VS |
3636 | static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) |
3637 | { | |
ae98104b VS |
3638 | return intel_has_gpu_reset(dev_priv) && |
3639 | INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv); | |
4ac2ba2f VS |
3640 | } |
3641 | ||
c033666a | 3642 | void intel_prepare_reset(struct drm_i915_private *dev_priv) |
7514747d | 3643 | { |
73974893 ML |
3644 | struct drm_device *dev = &dev_priv->drm; |
3645 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3646 | struct drm_atomic_state *state; | |
3647 | int ret; | |
3648 | ||
ce87ea15 DV |
3649 | |
3650 | /* reset doesn't touch the display */ | |
3651 | if (!i915.force_reset_modeset_test && | |
3652 | !gpu_reset_clobbers_display(dev_priv)) | |
3653 | return; | |
3654 | ||
73974893 ML |
3655 | /* |
3656 | * Need mode_config.mutex so that we don't | |
3657 | * trample ongoing ->detect() and whatnot. | |
3658 | */ | |
3659 | mutex_lock(&dev->mode_config.mutex); | |
3660 | drm_modeset_acquire_init(ctx, 0); | |
3661 | while (1) { | |
3662 | ret = drm_modeset_lock_all_ctx(dev, ctx); | |
3663 | if (ret != -EDEADLK) | |
3664 | break; | |
3665 | ||
3666 | drm_modeset_backoff(ctx); | |
3667 | } | |
f98ce92f VS |
3668 | /* |
3669 | * Disabling the crtcs gracefully seems nicer. Also the | |
3670 | * g33 docs say we should at least disable all the planes. | |
3671 | */ | |
73974893 ML |
3672 | state = drm_atomic_helper_duplicate_state(dev, ctx); |
3673 | if (IS_ERR(state)) { | |
3674 | ret = PTR_ERR(state); | |
73974893 | 3675 | DRM_ERROR("Duplicating state failed with %i\n", ret); |
1e5a15d6 | 3676 | return; |
73974893 ML |
3677 | } |
3678 | ||
3679 | ret = drm_atomic_helper_disable_all(dev, ctx); | |
3680 | if (ret) { | |
3681 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
1e5a15d6 ACO |
3682 | drm_atomic_state_put(state); |
3683 | return; | |
73974893 ML |
3684 | } |
3685 | ||
3686 | dev_priv->modeset_restore_state = state; | |
3687 | state->acquire_ctx = ctx; | |
7514747d VS |
3688 | } |
3689 | ||
c033666a | 3690 | void intel_finish_reset(struct drm_i915_private *dev_priv) |
7514747d | 3691 | { |
73974893 ML |
3692 | struct drm_device *dev = &dev_priv->drm; |
3693 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3694 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
3695 | int ret; | |
3696 | ||
ce87ea15 DV |
3697 | /* reset doesn't touch the display */ |
3698 | if (!i915.force_reset_modeset_test && | |
3699 | !gpu_reset_clobbers_display(dev_priv)) | |
3700 | return; | |
3701 | ||
3702 | if (!state) | |
3703 | goto unlock; | |
3704 | ||
73974893 ML |
3705 | dev_priv->modeset_restore_state = NULL; |
3706 | ||
7514747d | 3707 | /* reset doesn't touch the display */ |
4ac2ba2f | 3708 | if (!gpu_reset_clobbers_display(dev_priv)) { |
ce87ea15 DV |
3709 | /* for testing only restore the display */ |
3710 | ret = __intel_display_resume(dev, state, ctx); | |
522a63de ML |
3711 | if (ret) |
3712 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
73974893 ML |
3713 | } else { |
3714 | /* | |
3715 | * The display has been reset as well, | |
3716 | * so need a full re-initialization. | |
3717 | */ | |
3718 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3719 | intel_runtime_pm_enable_interrupts(dev_priv); | |
7514747d | 3720 | |
51f59205 | 3721 | intel_pps_unlock_regs_wa(dev_priv); |
73974893 | 3722 | intel_modeset_init_hw(dev); |
7514747d | 3723 | |
73974893 ML |
3724 | spin_lock_irq(&dev_priv->irq_lock); |
3725 | if (dev_priv->display.hpd_irq_setup) | |
3726 | dev_priv->display.hpd_irq_setup(dev_priv); | |
3727 | spin_unlock_irq(&dev_priv->irq_lock); | |
7514747d | 3728 | |
581e49fe | 3729 | ret = __intel_display_resume(dev, state, ctx); |
73974893 ML |
3730 | if (ret) |
3731 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
7514747d | 3732 | |
73974893 ML |
3733 | intel_hpd_init(dev_priv); |
3734 | } | |
7514747d | 3735 | |
ce87ea15 DV |
3736 | drm_atomic_state_put(state); |
3737 | unlock: | |
73974893 ML |
3738 | drm_modeset_drop_locks(ctx); |
3739 | drm_modeset_acquire_fini(ctx); | |
3740 | mutex_unlock(&dev->mode_config.mutex); | |
7514747d VS |
3741 | } |
3742 | ||
bfd16b2a ML |
3743 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3744 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 | 3745 | { |
6315b5d3 | 3746 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
bfd16b2a ML |
3747 | struct intel_crtc_state *pipe_config = |
3748 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3749 | |
bfd16b2a ML |
3750 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3751 | crtc->base.mode = crtc->base.state->mode; | |
3752 | ||
e30e8f75 GP |
3753 | /* |
3754 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3755 | * that in compute_mode_changes we check the native mode (not the pfit | |
3756 | * mode) to see if we can flip rather than do a full mode set. In the | |
3757 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3758 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3759 | * sized surface. | |
e30e8f75 GP |
3760 | */ |
3761 | ||
e30e8f75 | 3762 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3763 | ((pipe_config->pipe_src_w - 1) << 16) | |
3764 | (pipe_config->pipe_src_h - 1)); | |
3765 | ||
3766 | /* on skylake this is done by detaching scalers */ | |
6315b5d3 | 3767 | if (INTEL_GEN(dev_priv) >= 9) { |
bfd16b2a ML |
3768 | skl_detach_scalers(crtc); |
3769 | ||
3770 | if (pipe_config->pch_pfit.enabled) | |
3771 | skylake_pfit_enable(crtc); | |
6e266956 | 3772 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
bfd16b2a ML |
3773 | if (pipe_config->pch_pfit.enabled) |
3774 | ironlake_pfit_enable(crtc); | |
3775 | else if (old_crtc_state->pch_pfit.enabled) | |
3776 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3777 | } |
e30e8f75 GP |
3778 | } |
3779 | ||
4cbe4b2b | 3780 | static void intel_fdi_normal_train(struct intel_crtc *crtc) |
5e84e1a4 | 3781 | { |
4cbe4b2b | 3782 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3783 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3784 | int pipe = crtc->pipe; |
f0f59a00 VS |
3785 | i915_reg_t reg; |
3786 | u32 temp; | |
5e84e1a4 ZW |
3787 | |
3788 | /* enable normal train */ | |
3789 | reg = FDI_TX_CTL(pipe); | |
3790 | temp = I915_READ(reg); | |
fd6b8f43 | 3791 | if (IS_IVYBRIDGE(dev_priv)) { |
357555c0 JB |
3792 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3793 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3794 | } else { |
3795 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3796 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3797 | } |
5e84e1a4 ZW |
3798 | I915_WRITE(reg, temp); |
3799 | ||
3800 | reg = FDI_RX_CTL(pipe); | |
3801 | temp = I915_READ(reg); | |
6e266956 | 3802 | if (HAS_PCH_CPT(dev_priv)) { |
5e84e1a4 ZW |
3803 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3804 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3805 | } else { | |
3806 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3807 | temp |= FDI_LINK_TRAIN_NONE; | |
3808 | } | |
3809 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3810 | ||
3811 | /* wait one idle pattern time */ | |
3812 | POSTING_READ(reg); | |
3813 | udelay(1000); | |
357555c0 JB |
3814 | |
3815 | /* IVB wants error correction enabled */ | |
fd6b8f43 | 3816 | if (IS_IVYBRIDGE(dev_priv)) |
357555c0 JB |
3817 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
3818 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3819 | } |
3820 | ||
8db9d77b | 3821 | /* The FDI link training functions for ILK/Ibexpeak. */ |
dc4a1094 ACO |
3822 | static void ironlake_fdi_link_train(struct intel_crtc *crtc, |
3823 | const struct intel_crtc_state *crtc_state) | |
8db9d77b | 3824 | { |
4cbe4b2b | 3825 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3826 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3827 | int pipe = crtc->pipe; |
f0f59a00 VS |
3828 | i915_reg_t reg; |
3829 | u32 temp, tries; | |
8db9d77b | 3830 | |
1c8562f6 | 3831 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3832 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3833 | |
e1a44743 AJ |
3834 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3835 | for train result */ | |
5eddb70b CW |
3836 | reg = FDI_RX_IMR(pipe); |
3837 | temp = I915_READ(reg); | |
e1a44743 AJ |
3838 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3839 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3840 | I915_WRITE(reg, temp); |
3841 | I915_READ(reg); | |
e1a44743 AJ |
3842 | udelay(150); |
3843 | ||
8db9d77b | 3844 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3845 | reg = FDI_TX_CTL(pipe); |
3846 | temp = I915_READ(reg); | |
627eb5a3 | 3847 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 3848 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
8db9d77b ZW |
3849 | temp &= ~FDI_LINK_TRAIN_NONE; |
3850 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3851 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3852 | |
5eddb70b CW |
3853 | reg = FDI_RX_CTL(pipe); |
3854 | temp = I915_READ(reg); | |
8db9d77b ZW |
3855 | temp &= ~FDI_LINK_TRAIN_NONE; |
3856 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3857 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3858 | ||
3859 | POSTING_READ(reg); | |
8db9d77b ZW |
3860 | udelay(150); |
3861 | ||
5b2adf89 | 3862 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3863 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3864 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3865 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3866 | |
5eddb70b | 3867 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3868 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3869 | temp = I915_READ(reg); |
8db9d77b ZW |
3870 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3871 | ||
3872 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3873 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3874 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3875 | break; |
3876 | } | |
8db9d77b | 3877 | } |
e1a44743 | 3878 | if (tries == 5) |
5eddb70b | 3879 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3880 | |
3881 | /* Train 2 */ | |
5eddb70b CW |
3882 | reg = FDI_TX_CTL(pipe); |
3883 | temp = I915_READ(reg); | |
8db9d77b ZW |
3884 | temp &= ~FDI_LINK_TRAIN_NONE; |
3885 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3886 | I915_WRITE(reg, temp); |
8db9d77b | 3887 | |
5eddb70b CW |
3888 | reg = FDI_RX_CTL(pipe); |
3889 | temp = I915_READ(reg); | |
8db9d77b ZW |
3890 | temp &= ~FDI_LINK_TRAIN_NONE; |
3891 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3892 | I915_WRITE(reg, temp); |
8db9d77b | 3893 | |
5eddb70b CW |
3894 | POSTING_READ(reg); |
3895 | udelay(150); | |
8db9d77b | 3896 | |
5eddb70b | 3897 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3898 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3899 | temp = I915_READ(reg); |
8db9d77b ZW |
3900 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3901 | ||
3902 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3903 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3904 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3905 | break; | |
3906 | } | |
8db9d77b | 3907 | } |
e1a44743 | 3908 | if (tries == 5) |
5eddb70b | 3909 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3910 | |
3911 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3912 | |
8db9d77b ZW |
3913 | } |
3914 | ||
0206e353 | 3915 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3916 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3917 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3918 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3919 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3920 | }; | |
3921 | ||
3922 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
dc4a1094 ACO |
3923 | static void gen6_fdi_link_train(struct intel_crtc *crtc, |
3924 | const struct intel_crtc_state *crtc_state) | |
8db9d77b | 3925 | { |
4cbe4b2b | 3926 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3927 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3928 | int pipe = crtc->pipe; |
f0f59a00 VS |
3929 | i915_reg_t reg; |
3930 | u32 temp, i, retry; | |
8db9d77b | 3931 | |
e1a44743 AJ |
3932 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3933 | for train result */ | |
5eddb70b CW |
3934 | reg = FDI_RX_IMR(pipe); |
3935 | temp = I915_READ(reg); | |
e1a44743 AJ |
3936 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3937 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3938 | I915_WRITE(reg, temp); |
3939 | ||
3940 | POSTING_READ(reg); | |
e1a44743 AJ |
3941 | udelay(150); |
3942 | ||
8db9d77b | 3943 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3944 | reg = FDI_TX_CTL(pipe); |
3945 | temp = I915_READ(reg); | |
627eb5a3 | 3946 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 3947 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
8db9d77b ZW |
3948 | temp &= ~FDI_LINK_TRAIN_NONE; |
3949 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3950 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3951 | /* SNB-B */ | |
3952 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3953 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3954 | |
d74cf324 DV |
3955 | I915_WRITE(FDI_RX_MISC(pipe), |
3956 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3957 | ||
5eddb70b CW |
3958 | reg = FDI_RX_CTL(pipe); |
3959 | temp = I915_READ(reg); | |
6e266956 | 3960 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
3961 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3962 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3963 | } else { | |
3964 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3965 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3966 | } | |
5eddb70b CW |
3967 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3968 | ||
3969 | POSTING_READ(reg); | |
8db9d77b ZW |
3970 | udelay(150); |
3971 | ||
0206e353 | 3972 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3973 | reg = FDI_TX_CTL(pipe); |
3974 | temp = I915_READ(reg); | |
8db9d77b ZW |
3975 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3976 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3977 | I915_WRITE(reg, temp); |
3978 | ||
3979 | POSTING_READ(reg); | |
8db9d77b ZW |
3980 | udelay(500); |
3981 | ||
fa37d39e SP |
3982 | for (retry = 0; retry < 5; retry++) { |
3983 | reg = FDI_RX_IIR(pipe); | |
3984 | temp = I915_READ(reg); | |
3985 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3986 | if (temp & FDI_RX_BIT_LOCK) { | |
3987 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3988 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3989 | break; | |
3990 | } | |
3991 | udelay(50); | |
8db9d77b | 3992 | } |
fa37d39e SP |
3993 | if (retry < 5) |
3994 | break; | |
8db9d77b ZW |
3995 | } |
3996 | if (i == 4) | |
5eddb70b | 3997 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3998 | |
3999 | /* Train 2 */ | |
5eddb70b CW |
4000 | reg = FDI_TX_CTL(pipe); |
4001 | temp = I915_READ(reg); | |
8db9d77b ZW |
4002 | temp &= ~FDI_LINK_TRAIN_NONE; |
4003 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5db94019 | 4004 | if (IS_GEN6(dev_priv)) { |
8db9d77b ZW |
4005 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
4006 | /* SNB-B */ | |
4007 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
4008 | } | |
5eddb70b | 4009 | I915_WRITE(reg, temp); |
8db9d77b | 4010 | |
5eddb70b CW |
4011 | reg = FDI_RX_CTL(pipe); |
4012 | temp = I915_READ(reg); | |
6e266956 | 4013 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
4014 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
4015 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
4016 | } else { | |
4017 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4018 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
4019 | } | |
5eddb70b CW |
4020 | I915_WRITE(reg, temp); |
4021 | ||
4022 | POSTING_READ(reg); | |
8db9d77b ZW |
4023 | udelay(150); |
4024 | ||
0206e353 | 4025 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
4026 | reg = FDI_TX_CTL(pipe); |
4027 | temp = I915_READ(reg); | |
8db9d77b ZW |
4028 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
4029 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
4030 | I915_WRITE(reg, temp); |
4031 | ||
4032 | POSTING_READ(reg); | |
8db9d77b ZW |
4033 | udelay(500); |
4034 | ||
fa37d39e SP |
4035 | for (retry = 0; retry < 5; retry++) { |
4036 | reg = FDI_RX_IIR(pipe); | |
4037 | temp = I915_READ(reg); | |
4038 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
4039 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
4040 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
4041 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
4042 | break; | |
4043 | } | |
4044 | udelay(50); | |
8db9d77b | 4045 | } |
fa37d39e SP |
4046 | if (retry < 5) |
4047 | break; | |
8db9d77b ZW |
4048 | } |
4049 | if (i == 4) | |
5eddb70b | 4050 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
4051 | |
4052 | DRM_DEBUG_KMS("FDI train done.\n"); | |
4053 | } | |
4054 | ||
357555c0 | 4055 | /* Manual link training for Ivy Bridge A0 parts */ |
dc4a1094 ACO |
4056 | static void ivb_manual_fdi_link_train(struct intel_crtc *crtc, |
4057 | const struct intel_crtc_state *crtc_state) | |
357555c0 | 4058 | { |
4cbe4b2b | 4059 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4060 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 4061 | int pipe = crtc->pipe; |
f0f59a00 VS |
4062 | i915_reg_t reg; |
4063 | u32 temp, i, j; | |
357555c0 JB |
4064 | |
4065 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
4066 | for train result */ | |
4067 | reg = FDI_RX_IMR(pipe); | |
4068 | temp = I915_READ(reg); | |
4069 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
4070 | temp &= ~FDI_RX_BIT_LOCK; | |
4071 | I915_WRITE(reg, temp); | |
4072 | ||
4073 | POSTING_READ(reg); | |
4074 | udelay(150); | |
4075 | ||
01a415fd DV |
4076 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
4077 | I915_READ(FDI_RX_IIR(pipe))); | |
4078 | ||
139ccd3f JB |
4079 | /* Try each vswing and preemphasis setting twice before moving on */ |
4080 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
4081 | /* disable first in case we need to retry */ | |
4082 | reg = FDI_TX_CTL(pipe); | |
4083 | temp = I915_READ(reg); | |
4084 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
4085 | temp &= ~FDI_TX_ENABLE; | |
4086 | I915_WRITE(reg, temp); | |
357555c0 | 4087 | |
139ccd3f JB |
4088 | reg = FDI_RX_CTL(pipe); |
4089 | temp = I915_READ(reg); | |
4090 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
4091 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
4092 | temp &= ~FDI_RX_ENABLE; | |
4093 | I915_WRITE(reg, temp); | |
357555c0 | 4094 | |
139ccd3f | 4095 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
4096 | reg = FDI_TX_CTL(pipe); |
4097 | temp = I915_READ(reg); | |
139ccd3f | 4098 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 4099 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
139ccd3f | 4100 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 4101 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
4102 | temp |= snb_b_fdi_train_param[j/2]; |
4103 | temp |= FDI_COMPOSITE_SYNC; | |
4104 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 4105 | |
139ccd3f JB |
4106 | I915_WRITE(FDI_RX_MISC(pipe), |
4107 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 4108 | |
139ccd3f | 4109 | reg = FDI_RX_CTL(pipe); |
357555c0 | 4110 | temp = I915_READ(reg); |
139ccd3f JB |
4111 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
4112 | temp |= FDI_COMPOSITE_SYNC; | |
4113 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 4114 | |
139ccd3f JB |
4115 | POSTING_READ(reg); |
4116 | udelay(1); /* should be 0.5us */ | |
357555c0 | 4117 | |
139ccd3f JB |
4118 | for (i = 0; i < 4; i++) { |
4119 | reg = FDI_RX_IIR(pipe); | |
4120 | temp = I915_READ(reg); | |
4121 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 4122 | |
139ccd3f JB |
4123 | if (temp & FDI_RX_BIT_LOCK || |
4124 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
4125 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
4126 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
4127 | i); | |
4128 | break; | |
4129 | } | |
4130 | udelay(1); /* should be 0.5us */ | |
4131 | } | |
4132 | if (i == 4) { | |
4133 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
4134 | continue; | |
4135 | } | |
357555c0 | 4136 | |
139ccd3f | 4137 | /* Train 2 */ |
357555c0 JB |
4138 | reg = FDI_TX_CTL(pipe); |
4139 | temp = I915_READ(reg); | |
139ccd3f JB |
4140 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
4141 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
4142 | I915_WRITE(reg, temp); | |
4143 | ||
4144 | reg = FDI_RX_CTL(pipe); | |
4145 | temp = I915_READ(reg); | |
4146 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
4147 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
4148 | I915_WRITE(reg, temp); |
4149 | ||
4150 | POSTING_READ(reg); | |
139ccd3f | 4151 | udelay(2); /* should be 1.5us */ |
357555c0 | 4152 | |
139ccd3f JB |
4153 | for (i = 0; i < 4; i++) { |
4154 | reg = FDI_RX_IIR(pipe); | |
4155 | temp = I915_READ(reg); | |
4156 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 4157 | |
139ccd3f JB |
4158 | if (temp & FDI_RX_SYMBOL_LOCK || |
4159 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
4160 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
4161 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
4162 | i); | |
4163 | goto train_done; | |
4164 | } | |
4165 | udelay(2); /* should be 1.5us */ | |
357555c0 | 4166 | } |
139ccd3f JB |
4167 | if (i == 4) |
4168 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 4169 | } |
357555c0 | 4170 | |
139ccd3f | 4171 | train_done: |
357555c0 JB |
4172 | DRM_DEBUG_KMS("FDI train done.\n"); |
4173 | } | |
4174 | ||
88cefb6c | 4175 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 4176 | { |
88cefb6c | 4177 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 4178 | struct drm_i915_private *dev_priv = to_i915(dev); |
2c07245f | 4179 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
4180 | i915_reg_t reg; |
4181 | u32 temp; | |
c64e311e | 4182 | |
c98e9dcf | 4183 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
4184 | reg = FDI_RX_CTL(pipe); |
4185 | temp = I915_READ(reg); | |
627eb5a3 | 4186 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 4187 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 4188 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
4189 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
4190 | ||
4191 | POSTING_READ(reg); | |
c98e9dcf JB |
4192 | udelay(200); |
4193 | ||
4194 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
4195 | temp = I915_READ(reg); |
4196 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
4197 | ||
4198 | POSTING_READ(reg); | |
c98e9dcf JB |
4199 | udelay(200); |
4200 | ||
20749730 PZ |
4201 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
4202 | reg = FDI_TX_CTL(pipe); | |
4203 | temp = I915_READ(reg); | |
4204 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
4205 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 4206 | |
20749730 PZ |
4207 | POSTING_READ(reg); |
4208 | udelay(100); | |
6be4a607 | 4209 | } |
0e23b99d JB |
4210 | } |
4211 | ||
88cefb6c DV |
4212 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
4213 | { | |
4214 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 4215 | struct drm_i915_private *dev_priv = to_i915(dev); |
88cefb6c | 4216 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
4217 | i915_reg_t reg; |
4218 | u32 temp; | |
88cefb6c DV |
4219 | |
4220 | /* Switch from PCDclk to Rawclk */ | |
4221 | reg = FDI_RX_CTL(pipe); | |
4222 | temp = I915_READ(reg); | |
4223 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
4224 | ||
4225 | /* Disable CPU FDI TX PLL */ | |
4226 | reg = FDI_TX_CTL(pipe); | |
4227 | temp = I915_READ(reg); | |
4228 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
4229 | ||
4230 | POSTING_READ(reg); | |
4231 | udelay(100); | |
4232 | ||
4233 | reg = FDI_RX_CTL(pipe); | |
4234 | temp = I915_READ(reg); | |
4235 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
4236 | ||
4237 | /* Wait for the clocks to turn off. */ | |
4238 | POSTING_READ(reg); | |
4239 | udelay(100); | |
4240 | } | |
4241 | ||
0fc932b8 JB |
4242 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
4243 | { | |
4244 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4245 | struct drm_i915_private *dev_priv = to_i915(dev); |
0fc932b8 JB |
4246 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4247 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
4248 | i915_reg_t reg; |
4249 | u32 temp; | |
0fc932b8 JB |
4250 | |
4251 | /* disable CPU FDI tx and PCH FDI rx */ | |
4252 | reg = FDI_TX_CTL(pipe); | |
4253 | temp = I915_READ(reg); | |
4254 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
4255 | POSTING_READ(reg); | |
4256 | ||
4257 | reg = FDI_RX_CTL(pipe); | |
4258 | temp = I915_READ(reg); | |
4259 | temp &= ~(0x7 << 16); | |
dfd07d72 | 4260 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
4261 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
4262 | ||
4263 | POSTING_READ(reg); | |
4264 | udelay(100); | |
4265 | ||
4266 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6e266956 | 4267 | if (HAS_PCH_IBX(dev_priv)) |
6f06ce18 | 4268 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
4269 | |
4270 | /* still set train pattern 1 */ | |
4271 | reg = FDI_TX_CTL(pipe); | |
4272 | temp = I915_READ(reg); | |
4273 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4274 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4275 | I915_WRITE(reg, temp); | |
4276 | ||
4277 | reg = FDI_RX_CTL(pipe); | |
4278 | temp = I915_READ(reg); | |
6e266956 | 4279 | if (HAS_PCH_CPT(dev_priv)) { |
0fc932b8 JB |
4280 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
4281 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
4282 | } else { | |
4283 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4284 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4285 | } | |
4286 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
4287 | temp &= ~(0x07 << 16); | |
dfd07d72 | 4288 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
4289 | I915_WRITE(reg, temp); |
4290 | ||
4291 | POSTING_READ(reg); | |
4292 | udelay(100); | |
4293 | } | |
4294 | ||
49d73912 | 4295 | bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) |
5dce5b93 | 4296 | { |
fa05887a DV |
4297 | struct drm_crtc *crtc; |
4298 | bool cleanup_done; | |
4299 | ||
4300 | drm_for_each_crtc(crtc, &dev_priv->drm) { | |
4301 | struct drm_crtc_commit *commit; | |
4302 | spin_lock(&crtc->commit_lock); | |
4303 | commit = list_first_entry_or_null(&crtc->commit_list, | |
4304 | struct drm_crtc_commit, commit_entry); | |
4305 | cleanup_done = commit ? | |
4306 | try_wait_for_completion(&commit->cleanup_done) : true; | |
4307 | spin_unlock(&crtc->commit_lock); | |
4308 | ||
4309 | if (cleanup_done) | |
5dce5b93 CW |
4310 | continue; |
4311 | ||
fa05887a | 4312 | drm_crtc_wait_one_vblank(crtc); |
5dce5b93 CW |
4313 | |
4314 | return true; | |
4315 | } | |
4316 | ||
4317 | return false; | |
4318 | } | |
4319 | ||
b7076546 | 4320 | void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
060f02d8 VS |
4321 | { |
4322 | u32 temp; | |
4323 | ||
4324 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
4325 | ||
4326 | mutex_lock(&dev_priv->sb_lock); | |
4327 | ||
4328 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4329 | temp |= SBI_SSCCTL_DISABLE; | |
4330 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
4331 | ||
4332 | mutex_unlock(&dev_priv->sb_lock); | |
4333 | } | |
4334 | ||
e615efe4 | 4335 | /* Program iCLKIP clock to the desired frequency */ |
0dcdc382 | 4336 | static void lpt_program_iclkip(struct intel_crtc *crtc) |
e615efe4 | 4337 | { |
0dcdc382 ACO |
4338 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
4339 | int clock = crtc->config->base.adjusted_mode.crtc_clock; | |
e615efe4 ED |
4340 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
4341 | u32 temp; | |
4342 | ||
060f02d8 | 4343 | lpt_disable_iclkip(dev_priv); |
e615efe4 | 4344 | |
64b46a06 VS |
4345 | /* The iCLK virtual clock root frequency is in MHz, |
4346 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
4347 | * divisors, it is necessary to divide one by another, so we | |
4348 | * convert the virtual clock precision to KHz here for higher | |
4349 | * precision. | |
4350 | */ | |
4351 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
e615efe4 ED |
4352 | u32 iclk_virtual_root_freq = 172800 * 1000; |
4353 | u32 iclk_pi_range = 64; | |
64b46a06 | 4354 | u32 desired_divisor; |
e615efe4 | 4355 | |
64b46a06 VS |
4356 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
4357 | clock << auxdiv); | |
4358 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
4359 | phaseinc = desired_divisor % iclk_pi_range; | |
e615efe4 | 4360 | |
64b46a06 VS |
4361 | /* |
4362 | * Near 20MHz is a corner case which is | |
4363 | * out of range for the 7-bit divisor | |
4364 | */ | |
4365 | if (divsel <= 0x7f) | |
4366 | break; | |
e615efe4 ED |
4367 | } |
4368 | ||
4369 | /* This should not happen with any sane values */ | |
4370 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
4371 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
4372 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
4373 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
4374 | ||
4375 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 4376 | clock, |
e615efe4 ED |
4377 | auxdiv, |
4378 | divsel, | |
4379 | phasedir, | |
4380 | phaseinc); | |
4381 | ||
060f02d8 VS |
4382 | mutex_lock(&dev_priv->sb_lock); |
4383 | ||
e615efe4 | 4384 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 4385 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4386 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4387 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4388 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4389 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4390 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4391 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4392 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4393 | |
4394 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4395 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4396 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4397 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4398 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4399 | |
4400 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4401 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4402 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4403 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 4404 | |
060f02d8 VS |
4405 | mutex_unlock(&dev_priv->sb_lock); |
4406 | ||
e615efe4 ED |
4407 | /* Wait for initialization time */ |
4408 | udelay(24); | |
4409 | ||
4410 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
4411 | } | |
4412 | ||
8802e5b6 VS |
4413 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
4414 | { | |
4415 | u32 divsel, phaseinc, auxdiv; | |
4416 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
4417 | u32 iclk_pi_range = 64; | |
4418 | u32 desired_divisor; | |
4419 | u32 temp; | |
4420 | ||
4421 | if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) | |
4422 | return 0; | |
4423 | ||
4424 | mutex_lock(&dev_priv->sb_lock); | |
4425 | ||
4426 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4427 | if (temp & SBI_SSCCTL_DISABLE) { | |
4428 | mutex_unlock(&dev_priv->sb_lock); | |
4429 | return 0; | |
4430 | } | |
4431 | ||
4432 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
4433 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
4434 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
4435 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
4436 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
4437 | ||
4438 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
4439 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
4440 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
4441 | ||
4442 | mutex_unlock(&dev_priv->sb_lock); | |
4443 | ||
4444 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
4445 | ||
4446 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
4447 | desired_divisor << auxdiv); | |
4448 | } | |
4449 | ||
275f01b2 DV |
4450 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4451 | enum pipe pch_transcoder) | |
4452 | { | |
4453 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4454 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 4455 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4456 | |
4457 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4458 | I915_READ(HTOTAL(cpu_transcoder))); | |
4459 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4460 | I915_READ(HBLANK(cpu_transcoder))); | |
4461 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4462 | I915_READ(HSYNC(cpu_transcoder))); | |
4463 | ||
4464 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4465 | I915_READ(VTOTAL(cpu_transcoder))); | |
4466 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4467 | I915_READ(VBLANK(cpu_transcoder))); | |
4468 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4469 | I915_READ(VSYNC(cpu_transcoder))); | |
4470 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4471 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4472 | } | |
4473 | ||
003632d9 | 4474 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 | 4475 | { |
fac5e23e | 4476 | struct drm_i915_private *dev_priv = to_i915(dev); |
1fbc0d78 DV |
4477 | uint32_t temp; |
4478 | ||
4479 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4480 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4481 | return; |
4482 | ||
4483 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4484 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4485 | ||
003632d9 ACO |
4486 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4487 | if (enable) | |
4488 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4489 | ||
4490 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4491 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4492 | POSTING_READ(SOUTH_CHICKEN1); | |
4493 | } | |
4494 | ||
4495 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4496 | { | |
4497 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4498 | |
4499 | switch (intel_crtc->pipe) { | |
4500 | case PIPE_A: | |
4501 | break; | |
4502 | case PIPE_B: | |
6e3c9717 | 4503 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4504 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4505 | else |
003632d9 | 4506 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4507 | |
4508 | break; | |
4509 | case PIPE_C: | |
003632d9 | 4510 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4511 | |
4512 | break; | |
4513 | default: | |
4514 | BUG(); | |
4515 | } | |
4516 | } | |
4517 | ||
c48b5305 VS |
4518 | /* Return which DP Port should be selected for Transcoder DP control */ |
4519 | static enum port | |
4cbe4b2b | 4520 | intel_trans_dp_port_sel(struct intel_crtc *crtc) |
c48b5305 | 4521 | { |
4cbe4b2b | 4522 | struct drm_device *dev = crtc->base.dev; |
c48b5305 VS |
4523 | struct intel_encoder *encoder; |
4524 | ||
4cbe4b2b | 4525 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
cca0502b | 4526 | if (encoder->type == INTEL_OUTPUT_DP || |
c48b5305 VS |
4527 | encoder->type == INTEL_OUTPUT_EDP) |
4528 | return enc_to_dig_port(&encoder->base)->port; | |
4529 | } | |
4530 | ||
4531 | return -1; | |
4532 | } | |
4533 | ||
f67a559d JB |
4534 | /* |
4535 | * Enable PCH resources required for PCH ports: | |
4536 | * - PCH PLLs | |
4537 | * - FDI training & RX/TX | |
4538 | * - update transcoder timings | |
4539 | * - DP transcoding bits | |
4540 | * - transcoder | |
4541 | */ | |
2ce42273 | 4542 | static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state) |
0e23b99d | 4543 | { |
2ce42273 | 4544 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
4cbe4b2b | 4545 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4546 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 4547 | int pipe = crtc->pipe; |
f0f59a00 | 4548 | u32 temp; |
2c07245f | 4549 | |
ab9412ba | 4550 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4551 | |
fd6b8f43 | 4552 | if (IS_IVYBRIDGE(dev_priv)) |
4cbe4b2b | 4553 | ivybridge_update_fdi_bc_bifurcation(crtc); |
1fbc0d78 | 4554 | |
cd986abb DV |
4555 | /* Write the TU size bits before fdi link training, so that error |
4556 | * detection works. */ | |
4557 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4558 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4559 | ||
c98e9dcf | 4560 | /* For PCH output, training FDI link */ |
dc4a1094 | 4561 | dev_priv->display.fdi_link_train(crtc, crtc_state); |
2c07245f | 4562 | |
3ad8a208 DV |
4563 | /* We need to program the right clock selection before writing the pixel |
4564 | * mutliplier into the DPLL. */ | |
6e266956 | 4565 | if (HAS_PCH_CPT(dev_priv)) { |
ee7b9f93 | 4566 | u32 sel; |
4b645f14 | 4567 | |
c98e9dcf | 4568 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4569 | temp |= TRANS_DPLL_ENABLE(pipe); |
4570 | sel = TRANS_DPLLB_SEL(pipe); | |
2ce42273 | 4571 | if (crtc_state->shared_dpll == |
8106ddbd | 4572 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) |
ee7b9f93 JB |
4573 | temp |= sel; |
4574 | else | |
4575 | temp &= ~sel; | |
c98e9dcf | 4576 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4577 | } |
5eddb70b | 4578 | |
3ad8a208 DV |
4579 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4580 | * transcoder, and we actually should do this to not upset any PCH | |
4581 | * transcoder that already use the clock when we share it. | |
4582 | * | |
4583 | * Note that enable_shared_dpll tries to do the right thing, but | |
4584 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4585 | * the right LVDS enable sequence. */ | |
4cbe4b2b | 4586 | intel_enable_shared_dpll(crtc); |
3ad8a208 | 4587 | |
d9b6cb56 JB |
4588 | /* set transcoder timing, panel must allow it */ |
4589 | assert_panel_unlocked(dev_priv, pipe); | |
4cbe4b2b | 4590 | ironlake_pch_transcoder_set_timings(crtc, pipe); |
8db9d77b | 4591 | |
303b81e0 | 4592 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4593 | |
c98e9dcf | 4594 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e266956 | 4595 | if (HAS_PCH_CPT(dev_priv) && |
2ce42273 | 4596 | intel_crtc_has_dp_encoder(crtc_state)) { |
9c4edaee | 4597 | const struct drm_display_mode *adjusted_mode = |
2ce42273 | 4598 | &crtc_state->base.adjusted_mode; |
dfd07d72 | 4599 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4600 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4601 | temp = I915_READ(reg); |
4602 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4603 | TRANS_DP_SYNC_MASK | |
4604 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4605 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4606 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4607 | |
9c4edaee | 4608 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4609 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4610 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4611 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4612 | |
4613 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4614 | case PORT_B: |
5eddb70b | 4615 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4616 | break; |
c48b5305 | 4617 | case PORT_C: |
5eddb70b | 4618 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4619 | break; |
c48b5305 | 4620 | case PORT_D: |
5eddb70b | 4621 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4622 | break; |
4623 | default: | |
e95d41e1 | 4624 | BUG(); |
32f9d658 | 4625 | } |
2c07245f | 4626 | |
5eddb70b | 4627 | I915_WRITE(reg, temp); |
6be4a607 | 4628 | } |
b52eb4dc | 4629 | |
b8a4f404 | 4630 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4631 | } |
4632 | ||
2ce42273 | 4633 | static void lpt_pch_enable(const struct intel_crtc_state *crtc_state) |
1507e5bd | 4634 | { |
2ce42273 | 4635 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
0dcdc382 | 4636 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2ce42273 | 4637 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
1507e5bd | 4638 | |
a2196033 | 4639 | assert_pch_transcoder_disabled(dev_priv, PIPE_A); |
1507e5bd | 4640 | |
8c52b5e8 | 4641 | lpt_program_iclkip(crtc); |
1507e5bd | 4642 | |
0540e488 | 4643 | /* Set transcoder timing. */ |
0dcdc382 | 4644 | ironlake_pch_transcoder_set_timings(crtc, PIPE_A); |
1507e5bd | 4645 | |
937bb610 | 4646 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4647 | } |
4648 | ||
a1520318 | 4649 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 | 4650 | { |
fac5e23e | 4651 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 4652 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4653 | u32 temp; |
4654 | ||
4655 | temp = I915_READ(dslreg); | |
4656 | udelay(500); | |
4657 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4658 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4659 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4660 | } |
4661 | } | |
4662 | ||
86adf9d7 ML |
4663 | static int |
4664 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
d96a7d2a | 4665 | unsigned int scaler_user, int *scaler_id, |
86adf9d7 | 4666 | int src_w, int src_h, int dst_w, int dst_h) |
a1b2278e | 4667 | { |
86adf9d7 ML |
4668 | struct intel_crtc_scaler_state *scaler_state = |
4669 | &crtc_state->scaler_state; | |
4670 | struct intel_crtc *intel_crtc = | |
4671 | to_intel_crtc(crtc_state->base.crtc); | |
7f58cbb1 MK |
4672 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
4673 | const struct drm_display_mode *adjusted_mode = | |
4674 | &crtc_state->base.adjusted_mode; | |
a1b2278e | 4675 | int need_scaling; |
6156a456 | 4676 | |
d96a7d2a VS |
4677 | /* |
4678 | * Src coordinates are already rotated by 270 degrees for | |
4679 | * the 90/270 degree plane rotation cases (to match the | |
4680 | * GTT mapping), hence no need to account for rotation here. | |
4681 | */ | |
4682 | need_scaling = src_w != dst_w || src_h != dst_h; | |
a1b2278e | 4683 | |
e5c05931 SS |
4684 | if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX) |
4685 | need_scaling = true; | |
4686 | ||
7f58cbb1 MK |
4687 | /* |
4688 | * Scaling/fitting not supported in IF-ID mode in GEN9+ | |
4689 | * TODO: Interlace fetch mode doesn't support YUV420 planar formats. | |
4690 | * Once NV12 is enabled, handle it here while allocating scaler | |
4691 | * for NV12. | |
4692 | */ | |
4693 | if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable && | |
4694 | need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
4695 | DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n"); | |
4696 | return -EINVAL; | |
4697 | } | |
4698 | ||
a1b2278e CK |
4699 | /* |
4700 | * if plane is being disabled or scaler is no more required or force detach | |
4701 | * - free scaler binded to this plane/crtc | |
4702 | * - in order to do this, update crtc->scaler_usage | |
4703 | * | |
4704 | * Here scaler state in crtc_state is set free so that | |
4705 | * scaler can be assigned to other user. Actual register | |
4706 | * update to free the scaler is done in plane/panel-fit programming. | |
4707 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4708 | */ | |
86adf9d7 | 4709 | if (force_detach || !need_scaling) { |
a1b2278e | 4710 | if (*scaler_id >= 0) { |
86adf9d7 | 4711 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4712 | scaler_state->scalers[*scaler_id].in_use = 0; |
4713 | ||
86adf9d7 ML |
4714 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4715 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4716 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4717 | scaler_state->scaler_users); |
4718 | *scaler_id = -1; | |
4719 | } | |
4720 | return 0; | |
4721 | } | |
4722 | ||
4723 | /* range checks */ | |
4724 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4725 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4726 | ||
4727 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4728 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4729 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4730 | "size is out of scaler range\n", |
86adf9d7 | 4731 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4732 | return -EINVAL; |
4733 | } | |
4734 | ||
86adf9d7 ML |
4735 | /* mark this plane as a scaler user in crtc_state */ |
4736 | scaler_state->scaler_users |= (1 << scaler_user); | |
4737 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4738 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4739 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4740 | scaler_state->scaler_users); | |
4741 | ||
4742 | return 0; | |
4743 | } | |
4744 | ||
4745 | /** | |
4746 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4747 | * | |
4748 | * @state: crtc's scaler state | |
86adf9d7 ML |
4749 | * |
4750 | * Return | |
4751 | * 0 - scaler_usage updated successfully | |
4752 | * error - requested scaling cannot be supported or other error condition | |
4753 | */ | |
e435d6e5 | 4754 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 | 4755 | { |
7c5f93b0 | 4756 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 | 4757 | |
e435d6e5 | 4758 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
d96a7d2a | 4759 | &state->scaler_state.scaler_id, |
86adf9d7 | 4760 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4761 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4762 | } |
4763 | ||
4764 | /** | |
4765 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4766 | * | |
4767 | * @state: crtc's scaler state | |
86adf9d7 ML |
4768 | * @plane_state: atomic plane state to update |
4769 | * | |
4770 | * Return | |
4771 | * 0 - scaler_usage updated successfully | |
4772 | * error - requested scaling cannot be supported or other error condition | |
4773 | */ | |
da20eabd ML |
4774 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4775 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4776 | { |
4777 | ||
da20eabd ML |
4778 | struct intel_plane *intel_plane = |
4779 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4780 | struct drm_framebuffer *fb = plane_state->base.fb; |
4781 | int ret; | |
4782 | ||
936e71e3 | 4783 | bool force_detach = !fb || !plane_state->base.visible; |
86adf9d7 | 4784 | |
86adf9d7 ML |
4785 | ret = skl_update_scaler(crtc_state, force_detach, |
4786 | drm_plane_index(&intel_plane->base), | |
4787 | &plane_state->scaler_id, | |
936e71e3 VS |
4788 | drm_rect_width(&plane_state->base.src) >> 16, |
4789 | drm_rect_height(&plane_state->base.src) >> 16, | |
4790 | drm_rect_width(&plane_state->base.dst), | |
4791 | drm_rect_height(&plane_state->base.dst)); | |
86adf9d7 ML |
4792 | |
4793 | if (ret || plane_state->scaler_id < 0) | |
4794 | return ret; | |
4795 | ||
a1b2278e | 4796 | /* check colorkey */ |
818ed961 | 4797 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
72660ce0 VS |
4798 | DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed", |
4799 | intel_plane->base.base.id, | |
4800 | intel_plane->base.name); | |
a1b2278e CK |
4801 | return -EINVAL; |
4802 | } | |
4803 | ||
4804 | /* Check src format */ | |
438b74a5 | 4805 | switch (fb->format->format) { |
86adf9d7 ML |
4806 | case DRM_FORMAT_RGB565: |
4807 | case DRM_FORMAT_XBGR8888: | |
4808 | case DRM_FORMAT_XRGB8888: | |
4809 | case DRM_FORMAT_ABGR8888: | |
4810 | case DRM_FORMAT_ARGB8888: | |
4811 | case DRM_FORMAT_XRGB2101010: | |
4812 | case DRM_FORMAT_XBGR2101010: | |
4813 | case DRM_FORMAT_YUYV: | |
4814 | case DRM_FORMAT_YVYU: | |
4815 | case DRM_FORMAT_UYVY: | |
4816 | case DRM_FORMAT_VYUY: | |
4817 | break; | |
4818 | default: | |
72660ce0 VS |
4819 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", |
4820 | intel_plane->base.base.id, intel_plane->base.name, | |
438b74a5 | 4821 | fb->base.id, fb->format->format); |
86adf9d7 | 4822 | return -EINVAL; |
a1b2278e CK |
4823 | } |
4824 | ||
a1b2278e CK |
4825 | return 0; |
4826 | } | |
4827 | ||
e435d6e5 ML |
4828 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4829 | { | |
4830 | int i; | |
4831 | ||
4832 | for (i = 0; i < crtc->num_scalers; i++) | |
4833 | skl_detach_scaler(crtc, i); | |
4834 | } | |
4835 | ||
4836 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4837 | { |
4838 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4839 | struct drm_i915_private *dev_priv = to_i915(dev); |
bd2e244f | 4840 | int pipe = crtc->pipe; |
a1b2278e CK |
4841 | struct intel_crtc_scaler_state *scaler_state = |
4842 | &crtc->config->scaler_state; | |
4843 | ||
6e3c9717 | 4844 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4845 | int id; |
4846 | ||
c3f8ad57 | 4847 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) |
a1b2278e | 4848 | return; |
a1b2278e CK |
4849 | |
4850 | id = scaler_state->scaler_id; | |
4851 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4852 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4853 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4854 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
bd2e244f JB |
4855 | } |
4856 | } | |
4857 | ||
b074cec8 JB |
4858 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4859 | { | |
4860 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4861 | struct drm_i915_private *dev_priv = to_i915(dev); |
b074cec8 JB |
4862 | int pipe = crtc->pipe; |
4863 | ||
6e3c9717 | 4864 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4865 | /* Force use of hard-coded filter coefficients |
4866 | * as some pre-programmed values are broken, | |
4867 | * e.g. x201. | |
4868 | */ | |
fd6b8f43 | 4869 | if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) |
b074cec8 JB |
4870 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | |
4871 | PF_PIPE_SEL_IVB(pipe)); | |
4872 | else | |
4873 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4874 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4875 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4876 | } |
4877 | } | |
4878 | ||
20bc8673 | 4879 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4880 | { |
cea165c3 | 4881 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4882 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4883 | |
6e3c9717 | 4884 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4885 | return; |
4886 | ||
307e4498 ML |
4887 | /* |
4888 | * We can only enable IPS after we enable a plane and wait for a vblank | |
4889 | * This function is called from post_plane_update, which is run after | |
4890 | * a vblank wait. | |
4891 | */ | |
cea165c3 | 4892 | |
d77e4531 | 4893 | assert_plane_enabled(dev_priv, crtc->plane); |
8652744b | 4894 | if (IS_BROADWELL(dev_priv)) { |
2a114cc1 BW |
4895 | mutex_lock(&dev_priv->rps.hw_lock); |
4896 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4897 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4898 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4899 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4900 | * mailbox." Moreover, the mailbox may return a bogus state, |
4901 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4902 | */ |
4903 | } else { | |
4904 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4905 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4906 | * is essentially intel_wait_for_vblank. If we don't have this | |
4907 | * and don't wait for vblanks until the end of crtc_enable, then | |
4908 | * the HW state readout code will complain that the expected | |
4909 | * IPS_CTL value is not the one we read. */ | |
2ec9ba3c CW |
4910 | if (intel_wait_for_register(dev_priv, |
4911 | IPS_CTL, IPS_ENABLE, IPS_ENABLE, | |
4912 | 50)) | |
2a114cc1 BW |
4913 | DRM_ERROR("Timed out waiting for IPS enable\n"); |
4914 | } | |
d77e4531 PZ |
4915 | } |
4916 | ||
20bc8673 | 4917 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4918 | { |
4919 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4920 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4921 | |
6e3c9717 | 4922 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4923 | return; |
4924 | ||
4925 | assert_plane_enabled(dev_priv, crtc->plane); | |
8652744b | 4926 | if (IS_BROADWELL(dev_priv)) { |
2a114cc1 BW |
4927 | mutex_lock(&dev_priv->rps.hw_lock); |
4928 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4929 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 | 4930 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
b85c1ecf CW |
4931 | if (intel_wait_for_register(dev_priv, |
4932 | IPS_CTL, IPS_ENABLE, 0, | |
4933 | 42)) | |
23d0b130 | 4934 | DRM_ERROR("Timed out waiting for IPS disable\n"); |
e59150dc | 4935 | } else { |
2a114cc1 | 4936 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4937 | POSTING_READ(IPS_CTL); |
4938 | } | |
d77e4531 PZ |
4939 | |
4940 | /* We need to wait for a vblank before we can disable the plane. */ | |
0f0f74bc | 4941 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
d77e4531 PZ |
4942 | } |
4943 | ||
7cac945f | 4944 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4945 | { |
7cac945f | 4946 | if (intel_crtc->overlay) { |
d3eedb1a | 4947 | struct drm_device *dev = intel_crtc->base.dev; |
d3eedb1a VS |
4948 | |
4949 | mutex_lock(&dev->struct_mutex); | |
d3eedb1a | 4950 | (void) intel_overlay_switch_off(intel_crtc->overlay); |
d3eedb1a VS |
4951 | mutex_unlock(&dev->struct_mutex); |
4952 | } | |
4953 | ||
4954 | /* Let userspace switch the overlay on again. In most cases userspace | |
4955 | * has to recompute where to put it anyway. | |
4956 | */ | |
4957 | } | |
4958 | ||
87d4300a ML |
4959 | /** |
4960 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4961 | * @crtc: the CRTC whose primary plane was just enabled | |
4962 | * | |
4963 | * Performs potentially sleeping operations that must be done after the primary | |
4964 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4965 | * called due to an explicit primary plane update, or due to an implicit | |
4966 | * re-enable that is caused when a sprite plane is updated to no longer | |
4967 | * completely hide the primary plane. | |
4968 | */ | |
4969 | static void | |
4970 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4971 | { |
4972 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4973 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4974 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4975 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4976 | |
87d4300a ML |
4977 | /* |
4978 | * FIXME IPS should be fine as long as one plane is | |
4979 | * enabled, but in practice it seems to have problems | |
4980 | * when going from primary only to sprite only and vice | |
4981 | * versa. | |
4982 | */ | |
a5c4d7bc VS |
4983 | hsw_enable_ips(intel_crtc); |
4984 | ||
f99d7069 | 4985 | /* |
87d4300a ML |
4986 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4987 | * So don't enable underrun reporting before at least some planes | |
4988 | * are enabled. | |
4989 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4990 | * but leave the pipe running. | |
f99d7069 | 4991 | */ |
5db94019 | 4992 | if (IS_GEN2(dev_priv)) |
87d4300a ML |
4993 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4994 | ||
aca7b684 VS |
4995 | /* Underruns don't always raise interrupts, so check manually. */ |
4996 | intel_check_cpu_fifo_underruns(dev_priv); | |
4997 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4998 | } |
4999 | ||
2622a081 | 5000 | /* FIXME move all this to pre_plane_update() with proper state tracking */ |
87d4300a ML |
5001 | static void |
5002 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
5003 | { |
5004 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 5005 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
5006 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5007 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 5008 | |
87d4300a ML |
5009 | /* |
5010 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
5011 | * So diasble underrun reporting before all the planes get disabled. | |
5012 | * FIXME: Need to fix the logic to work when we turn off all planes | |
5013 | * but leave the pipe running. | |
5014 | */ | |
5db94019 | 5015 | if (IS_GEN2(dev_priv)) |
87d4300a | 5016 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
a5c4d7bc | 5017 | |
2622a081 VS |
5018 | /* |
5019 | * FIXME IPS should be fine as long as one plane is | |
5020 | * enabled, but in practice it seems to have problems | |
5021 | * when going from primary only to sprite only and vice | |
5022 | * versa. | |
5023 | */ | |
5024 | hsw_disable_ips(intel_crtc); | |
5025 | } | |
5026 | ||
5027 | /* FIXME get rid of this and use pre_plane_update */ | |
5028 | static void | |
5029 | intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) | |
5030 | { | |
5031 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 5032 | struct drm_i915_private *dev_priv = to_i915(dev); |
2622a081 VS |
5033 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5034 | int pipe = intel_crtc->pipe; | |
5035 | ||
5036 | intel_pre_disable_primary(crtc); | |
5037 | ||
87d4300a ML |
5038 | /* |
5039 | * Vblank time updates from the shadow to live plane control register | |
5040 | * are blocked if the memory self-refresh mode is active at that | |
5041 | * moment. So to make sure the plane gets truly disabled, disable | |
5042 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5043 | * will be checked/applied by the HW only at the next frame start | |
5044 | * event which is after the vblank start event, so we need to have a | |
5045 | * wait-for-vblank between disabling the plane and the pipe. | |
5046 | */ | |
11a85d6a VS |
5047 | if (HAS_GMCH_DISPLAY(dev_priv) && |
5048 | intel_set_memory_cxsr(dev_priv, false)) | |
0f0f74bc | 5049 | intel_wait_for_vblank(dev_priv, pipe); |
87d4300a ML |
5050 | } |
5051 | ||
5a21b665 DV |
5052 | static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) |
5053 | { | |
5054 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); | |
5055 | struct drm_atomic_state *old_state = old_crtc_state->base.state; | |
5056 | struct intel_crtc_state *pipe_config = | |
5057 | to_intel_crtc_state(crtc->base.state); | |
5a21b665 DV |
5058 | struct drm_plane *primary = crtc->base.primary; |
5059 | struct drm_plane_state *old_pri_state = | |
5060 | drm_atomic_get_existing_plane_state(old_state, primary); | |
5061 | ||
5748b6a1 | 5062 | intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits); |
5a21b665 | 5063 | |
5a21b665 | 5064 | if (pipe_config->update_wm_post && pipe_config->base.active) |
432081bc | 5065 | intel_update_watermarks(crtc); |
5a21b665 DV |
5066 | |
5067 | if (old_pri_state) { | |
5068 | struct intel_plane_state *primary_state = | |
5069 | to_intel_plane_state(primary->state); | |
5070 | struct intel_plane_state *old_primary_state = | |
5071 | to_intel_plane_state(old_pri_state); | |
5072 | ||
5073 | intel_fbc_post_update(crtc); | |
5074 | ||
936e71e3 | 5075 | if (primary_state->base.visible && |
5a21b665 | 5076 | (needs_modeset(&pipe_config->base) || |
936e71e3 | 5077 | !old_primary_state->base.visible)) |
5a21b665 DV |
5078 | intel_post_enable_primary(&crtc->base); |
5079 | } | |
5080 | } | |
5081 | ||
aa5e9b47 ML |
5082 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state, |
5083 | struct intel_crtc_state *pipe_config) | |
ac21b225 | 5084 | { |
5c74cd73 | 5085 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 5086 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 5087 | struct drm_i915_private *dev_priv = to_i915(dev); |
5c74cd73 ML |
5088 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
5089 | struct drm_plane *primary = crtc->base.primary; | |
5090 | struct drm_plane_state *old_pri_state = | |
5091 | drm_atomic_get_existing_plane_state(old_state, primary); | |
5092 | bool modeset = needs_modeset(&pipe_config->base); | |
ccf010fb ML |
5093 | struct intel_atomic_state *old_intel_state = |
5094 | to_intel_atomic_state(old_state); | |
ac21b225 | 5095 | |
5c74cd73 ML |
5096 | if (old_pri_state) { |
5097 | struct intel_plane_state *primary_state = | |
5098 | to_intel_plane_state(primary->state); | |
5099 | struct intel_plane_state *old_primary_state = | |
5100 | to_intel_plane_state(old_pri_state); | |
5101 | ||
faf68d92 | 5102 | intel_fbc_pre_update(crtc, pipe_config, primary_state); |
31ae71fc | 5103 | |
936e71e3 VS |
5104 | if (old_primary_state->base.visible && |
5105 | (modeset || !primary_state->base.visible)) | |
5c74cd73 ML |
5106 | intel_pre_disable_primary(&crtc->base); |
5107 | } | |
852eb00d | 5108 | |
5eeb798b VS |
5109 | /* |
5110 | * Vblank time updates from the shadow to live plane control register | |
5111 | * are blocked if the memory self-refresh mode is active at that | |
5112 | * moment. So to make sure the plane gets truly disabled, disable | |
5113 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5114 | * will be checked/applied by the HW only at the next frame start | |
5115 | * event which is after the vblank start event, so we need to have a | |
5116 | * wait-for-vblank between disabling the plane and the pipe. | |
5117 | */ | |
5118 | if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active && | |
5119 | pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) | |
5120 | intel_wait_for_vblank(dev_priv, crtc->pipe); | |
92826fcd | 5121 | |
ed4a6a7c MR |
5122 | /* |
5123 | * IVB workaround: must disable low power watermarks for at least | |
5124 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
5125 | * when scaling is disabled. | |
5126 | * | |
5127 | * WaCxSRDisabledForSpriteScaling:ivb | |
5128 | */ | |
ddd2b792 | 5129 | if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev)) |
0f0f74bc | 5130 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
ed4a6a7c MR |
5131 | |
5132 | /* | |
5133 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
5134 | * watermark programming here. | |
5135 | */ | |
5136 | if (needs_modeset(&pipe_config->base)) | |
5137 | return; | |
5138 | ||
5139 | /* | |
5140 | * For platforms that support atomic watermarks, program the | |
5141 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
5142 | * will be the intermediate values that are safe for both pre- and | |
5143 | * post- vblank; when vblank happens, the 'active' values will be set | |
5144 | * to the final 'target' values and we'll do this again to get the | |
5145 | * optimal watermarks. For gen9+ platforms, the values we program here | |
5146 | * will be the final target values which will get automatically latched | |
5147 | * at vblank time; no further programming will be necessary. | |
5148 | * | |
5149 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
5150 | * we'll continue to update watermarks the old way, if flags tell | |
5151 | * us to. | |
5152 | */ | |
5153 | if (dev_priv->display.initial_watermarks != NULL) | |
ccf010fb ML |
5154 | dev_priv->display.initial_watermarks(old_intel_state, |
5155 | pipe_config); | |
caed361d | 5156 | else if (pipe_config->update_wm_pre) |
432081bc | 5157 | intel_update_watermarks(crtc); |
ac21b225 ML |
5158 | } |
5159 | ||
d032ffa0 | 5160 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
5161 | { |
5162 | struct drm_device *dev = crtc->dev; | |
5163 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 5164 | struct drm_plane *p; |
87d4300a ML |
5165 | int pipe = intel_crtc->pipe; |
5166 | ||
7cac945f | 5167 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 5168 | |
d032ffa0 | 5169 | drm_for_each_plane_mask(p, dev, plane_mask) |
282dbf9b | 5170 | to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc); |
f98551ae | 5171 | |
f99d7069 DV |
5172 | /* |
5173 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
5174 | * to compute the mask of flip planes precisely. For the time being | |
5175 | * consider this a flip to a NULL plane. | |
5176 | */ | |
5748b6a1 | 5177 | intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe)); |
a5c4d7bc VS |
5178 | } |
5179 | ||
fb1c98b1 | 5180 | static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc, |
fd6bbda9 | 5181 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5182 | struct drm_atomic_state *old_state) |
5183 | { | |
aa5e9b47 | 5184 | struct drm_connector_state *conn_state; |
fb1c98b1 ML |
5185 | struct drm_connector *conn; |
5186 | int i; | |
5187 | ||
aa5e9b47 | 5188 | for_each_new_connector_in_state(old_state, conn, conn_state, i) { |
fb1c98b1 ML |
5189 | struct intel_encoder *encoder = |
5190 | to_intel_encoder(conn_state->best_encoder); | |
5191 | ||
5192 | if (conn_state->crtc != crtc) | |
5193 | continue; | |
5194 | ||
5195 | if (encoder->pre_pll_enable) | |
fd6bbda9 | 5196 | encoder->pre_pll_enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5197 | } |
5198 | } | |
5199 | ||
5200 | static void intel_encoders_pre_enable(struct drm_crtc *crtc, | |
fd6bbda9 | 5201 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5202 | struct drm_atomic_state *old_state) |
5203 | { | |
aa5e9b47 | 5204 | struct drm_connector_state *conn_state; |
fb1c98b1 ML |
5205 | struct drm_connector *conn; |
5206 | int i; | |
5207 | ||
aa5e9b47 | 5208 | for_each_new_connector_in_state(old_state, conn, conn_state, i) { |
fb1c98b1 ML |
5209 | struct intel_encoder *encoder = |
5210 | to_intel_encoder(conn_state->best_encoder); | |
5211 | ||
5212 | if (conn_state->crtc != crtc) | |
5213 | continue; | |
5214 | ||
5215 | if (encoder->pre_enable) | |
fd6bbda9 | 5216 | encoder->pre_enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5217 | } |
5218 | } | |
5219 | ||
5220 | static void intel_encoders_enable(struct drm_crtc *crtc, | |
fd6bbda9 | 5221 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5222 | struct drm_atomic_state *old_state) |
5223 | { | |
aa5e9b47 | 5224 | struct drm_connector_state *conn_state; |
fb1c98b1 ML |
5225 | struct drm_connector *conn; |
5226 | int i; | |
5227 | ||
aa5e9b47 | 5228 | for_each_new_connector_in_state(old_state, conn, conn_state, i) { |
fb1c98b1 ML |
5229 | struct intel_encoder *encoder = |
5230 | to_intel_encoder(conn_state->best_encoder); | |
5231 | ||
5232 | if (conn_state->crtc != crtc) | |
5233 | continue; | |
5234 | ||
fd6bbda9 | 5235 | encoder->enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5236 | intel_opregion_notify_encoder(encoder, true); |
5237 | } | |
5238 | } | |
5239 | ||
5240 | static void intel_encoders_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5241 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5242 | struct drm_atomic_state *old_state) |
5243 | { | |
5244 | struct drm_connector_state *old_conn_state; | |
5245 | struct drm_connector *conn; | |
5246 | int i; | |
5247 | ||
aa5e9b47 | 5248 | for_each_old_connector_in_state(old_state, conn, old_conn_state, i) { |
fb1c98b1 ML |
5249 | struct intel_encoder *encoder = |
5250 | to_intel_encoder(old_conn_state->best_encoder); | |
5251 | ||
5252 | if (old_conn_state->crtc != crtc) | |
5253 | continue; | |
5254 | ||
5255 | intel_opregion_notify_encoder(encoder, false); | |
fd6bbda9 | 5256 | encoder->disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5257 | } |
5258 | } | |
5259 | ||
5260 | static void intel_encoders_post_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5261 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5262 | struct drm_atomic_state *old_state) |
5263 | { | |
5264 | struct drm_connector_state *old_conn_state; | |
5265 | struct drm_connector *conn; | |
5266 | int i; | |
5267 | ||
aa5e9b47 | 5268 | for_each_old_connector_in_state(old_state, conn, old_conn_state, i) { |
fb1c98b1 ML |
5269 | struct intel_encoder *encoder = |
5270 | to_intel_encoder(old_conn_state->best_encoder); | |
5271 | ||
5272 | if (old_conn_state->crtc != crtc) | |
5273 | continue; | |
5274 | ||
5275 | if (encoder->post_disable) | |
fd6bbda9 | 5276 | encoder->post_disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5277 | } |
5278 | } | |
5279 | ||
5280 | static void intel_encoders_post_pll_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5281 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5282 | struct drm_atomic_state *old_state) |
5283 | { | |
5284 | struct drm_connector_state *old_conn_state; | |
5285 | struct drm_connector *conn; | |
5286 | int i; | |
5287 | ||
aa5e9b47 | 5288 | for_each_old_connector_in_state(old_state, conn, old_conn_state, i) { |
fb1c98b1 ML |
5289 | struct intel_encoder *encoder = |
5290 | to_intel_encoder(old_conn_state->best_encoder); | |
5291 | ||
5292 | if (old_conn_state->crtc != crtc) | |
5293 | continue; | |
5294 | ||
5295 | if (encoder->post_pll_disable) | |
fd6bbda9 | 5296 | encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5297 | } |
5298 | } | |
5299 | ||
4a806558 ML |
5300 | static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config, |
5301 | struct drm_atomic_state *old_state) | |
f67a559d | 5302 | { |
4a806558 | 5303 | struct drm_crtc *crtc = pipe_config->base.crtc; |
f67a559d | 5304 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5305 | struct drm_i915_private *dev_priv = to_i915(dev); |
f67a559d JB |
5306 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5307 | int pipe = intel_crtc->pipe; | |
ccf010fb ML |
5308 | struct intel_atomic_state *old_intel_state = |
5309 | to_intel_atomic_state(old_state); | |
f67a559d | 5310 | |
53d9f4e9 | 5311 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
5312 | return; |
5313 | ||
b2c0593a VS |
5314 | /* |
5315 | * Sometimes spurious CPU pipe underruns happen during FDI | |
5316 | * training, at least with VGA+HDMI cloning. Suppress them. | |
5317 | * | |
5318 | * On ILK we get an occasional spurious CPU pipe underruns | |
5319 | * between eDP port A enable and vdd enable. Also PCH port | |
5320 | * enable seems to result in the occasional CPU pipe underrun. | |
5321 | * | |
5322 | * Spurious PCH underruns also occur during PCH enabling. | |
5323 | */ | |
5324 | if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv)) | |
5325 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
81b088ca VS |
5326 | if (intel_crtc->config->has_pch_encoder) |
5327 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
5328 | ||
6e3c9717 | 5329 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
5330 | intel_prepare_shared_dpll(intel_crtc); |
5331 | ||
37a5650b | 5332 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5333 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
5334 | |
5335 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 5336 | intel_set_pipe_src_size(intel_crtc); |
29407aab | 5337 | |
6e3c9717 | 5338 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 5339 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5340 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
5341 | } |
5342 | ||
5343 | ironlake_set_pipeconf(crtc); | |
5344 | ||
f67a559d | 5345 | intel_crtc->active = true; |
8664281b | 5346 | |
fd6bbda9 | 5347 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
f67a559d | 5348 | |
6e3c9717 | 5349 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
5350 | /* Note: FDI PLL enabling _must_ be done before we enable the |
5351 | * cpu pipes, hence this is separate from all the other fdi/pch | |
5352 | * enabling. */ | |
88cefb6c | 5353 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
5354 | } else { |
5355 | assert_fdi_tx_disabled(dev_priv, pipe); | |
5356 | assert_fdi_rx_disabled(dev_priv, pipe); | |
5357 | } | |
f67a559d | 5358 | |
b074cec8 | 5359 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 5360 | |
9c54c0dd JB |
5361 | /* |
5362 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5363 | * clocks enabled | |
5364 | */ | |
b95c5321 | 5365 | intel_color_load_luts(&pipe_config->base); |
9c54c0dd | 5366 | |
1d5bf5d9 | 5367 | if (dev_priv->display.initial_watermarks != NULL) |
ccf010fb | 5368 | dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config); |
e1fdc473 | 5369 | intel_enable_pipe(intel_crtc); |
f67a559d | 5370 | |
6e3c9717 | 5371 | if (intel_crtc->config->has_pch_encoder) |
2ce42273 | 5372 | ironlake_pch_enable(pipe_config); |
c98e9dcf | 5373 | |
f9b61ff6 DV |
5374 | assert_vblank_disabled(crtc); |
5375 | drm_crtc_vblank_on(crtc); | |
5376 | ||
fd6bbda9 | 5377 | intel_encoders_enable(crtc, pipe_config, old_state); |
61b77ddd | 5378 | |
6e266956 | 5379 | if (HAS_PCH_CPT(dev_priv)) |
a1520318 | 5380 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
5381 | |
5382 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
5383 | if (intel_crtc->config->has_pch_encoder) | |
0f0f74bc | 5384 | intel_wait_for_vblank(dev_priv, pipe); |
b2c0593a | 5385 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
37ca8d4c | 5386 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 JB |
5387 | } |
5388 | ||
42db64ef PZ |
5389 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
5390 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
5391 | { | |
50a0bc90 | 5392 | return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A; |
42db64ef PZ |
5393 | } |
5394 | ||
4a806558 ML |
5395 | static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, |
5396 | struct drm_atomic_state *old_state) | |
4f771f10 | 5397 | { |
4a806558 | 5398 | struct drm_crtc *crtc = pipe_config->base.crtc; |
6315b5d3 | 5399 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
4f771f10 | 5400 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
99d736a2 | 5401 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4d1de975 | 5402 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ccf010fb ML |
5403 | struct intel_atomic_state *old_intel_state = |
5404 | to_intel_atomic_state(old_state); | |
4f771f10 | 5405 | |
53d9f4e9 | 5406 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
5407 | return; |
5408 | ||
81b088ca | 5409 | if (intel_crtc->config->has_pch_encoder) |
29012159 | 5410 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); |
81b088ca | 5411 | |
fd6bbda9 | 5412 | intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); |
95a7a2ae | 5413 | |
8106ddbd | 5414 | if (intel_crtc->config->shared_dpll) |
df8ad70c DV |
5415 | intel_enable_shared_dpll(intel_crtc); |
5416 | ||
37a5650b | 5417 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5418 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 | 5419 | |
d7edc4e5 | 5420 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5421 | intel_set_pipe_timings(intel_crtc); |
5422 | ||
bc58be60 | 5423 | intel_set_pipe_src_size(intel_crtc); |
229fca97 | 5424 | |
4d1de975 JN |
5425 | if (cpu_transcoder != TRANSCODER_EDP && |
5426 | !transcoder_is_dsi(cpu_transcoder)) { | |
5427 | I915_WRITE(PIPE_MULT(cpu_transcoder), | |
6e3c9717 | 5428 | intel_crtc->config->pixel_multiplier - 1); |
ebb69c95 CT |
5429 | } |
5430 | ||
6e3c9717 | 5431 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 5432 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5433 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
5434 | } |
5435 | ||
d7edc4e5 | 5436 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5437 | haswell_set_pipeconf(crtc); |
5438 | ||
391bf048 | 5439 | haswell_set_pipemisc(crtc); |
229fca97 | 5440 | |
b95c5321 | 5441 | intel_color_set_csc(&pipe_config->base); |
229fca97 | 5442 | |
4f771f10 | 5443 | intel_crtc->active = true; |
8664281b | 5444 | |
6b698516 DV |
5445 | if (intel_crtc->config->has_pch_encoder) |
5446 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5447 | else | |
5448 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5449 | ||
fd6bbda9 | 5450 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
4f771f10 | 5451 | |
d2d65408 | 5452 | if (intel_crtc->config->has_pch_encoder) |
dc4a1094 | 5453 | dev_priv->display.fdi_link_train(intel_crtc, pipe_config); |
4fe9467d | 5454 | |
d7edc4e5 | 5455 | if (!transcoder_is_dsi(cpu_transcoder)) |
3dc38eea | 5456 | intel_ddi_enable_pipe_clock(pipe_config); |
4f771f10 | 5457 | |
6315b5d3 | 5458 | if (INTEL_GEN(dev_priv) >= 9) |
e435d6e5 | 5459 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 5460 | else |
1c132b44 | 5461 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
5462 | |
5463 | /* | |
5464 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5465 | * clocks enabled | |
5466 | */ | |
b95c5321 | 5467 | intel_color_load_luts(&pipe_config->base); |
4f771f10 | 5468 | |
3dc38eea | 5469 | intel_ddi_set_pipe_settings(pipe_config); |
d7edc4e5 | 5470 | if (!transcoder_is_dsi(cpu_transcoder)) |
3dc38eea | 5471 | intel_ddi_enable_transcoder_func(pipe_config); |
4f771f10 | 5472 | |
1d5bf5d9 | 5473 | if (dev_priv->display.initial_watermarks != NULL) |
3125d39f | 5474 | dev_priv->display.initial_watermarks(old_intel_state, pipe_config); |
4d1de975 JN |
5475 | |
5476 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ | |
d7edc4e5 | 5477 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5478 | intel_enable_pipe(intel_crtc); |
42db64ef | 5479 | |
6e3c9717 | 5480 | if (intel_crtc->config->has_pch_encoder) |
2ce42273 | 5481 | lpt_pch_enable(pipe_config); |
4f771f10 | 5482 | |
0037071d | 5483 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST)) |
3dc38eea | 5484 | intel_ddi_set_vc_payload_alloc(pipe_config, true); |
0e32b39c | 5485 | |
f9b61ff6 DV |
5486 | assert_vblank_disabled(crtc); |
5487 | drm_crtc_vblank_on(crtc); | |
5488 | ||
fd6bbda9 | 5489 | intel_encoders_enable(crtc, pipe_config, old_state); |
4f771f10 | 5490 | |
6b698516 | 5491 | if (intel_crtc->config->has_pch_encoder) { |
0f0f74bc VS |
5492 | intel_wait_for_vblank(dev_priv, pipe); |
5493 | intel_wait_for_vblank(dev_priv, pipe); | |
6b698516 | 5494 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
29012159 | 5495 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
6b698516 | 5496 | } |
d2d65408 | 5497 | |
e4916946 PZ |
5498 | /* If we change the relative order between pipe/planes enabling, we need |
5499 | * to change the workaround. */ | |
99d736a2 | 5500 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
772c2a51 | 5501 | if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { |
0f0f74bc VS |
5502 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); |
5503 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); | |
99d736a2 | 5504 | } |
4f771f10 PZ |
5505 | } |
5506 | ||
bfd16b2a | 5507 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
5508 | { |
5509 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5510 | struct drm_i915_private *dev_priv = to_i915(dev); |
3f8dce3a DV |
5511 | int pipe = crtc->pipe; |
5512 | ||
5513 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5514 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5515 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5516 | I915_WRITE(PF_CTL(pipe), 0); |
5517 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5518 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5519 | } | |
5520 | } | |
5521 | ||
4a806558 ML |
5522 | static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5523 | struct drm_atomic_state *old_state) | |
6be4a607 | 5524 | { |
4a806558 | 5525 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
6be4a607 | 5526 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5527 | struct drm_i915_private *dev_priv = to_i915(dev); |
6be4a607 JB |
5528 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5529 | int pipe = intel_crtc->pipe; | |
b52eb4dc | 5530 | |
b2c0593a VS |
5531 | /* |
5532 | * Sometimes spurious CPU pipe underruns happen when the | |
5533 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
5534 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
5535 | */ | |
5536 | if (intel_crtc->config->has_pch_encoder) { | |
5537 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
37ca8d4c | 5538 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
b2c0593a | 5539 | } |
37ca8d4c | 5540 | |
fd6bbda9 | 5541 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
ea9d758d | 5542 | |
f9b61ff6 DV |
5543 | drm_crtc_vblank_off(crtc); |
5544 | assert_vblank_disabled(crtc); | |
5545 | ||
575f7ab7 | 5546 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5547 | |
bfd16b2a | 5548 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5549 | |
b2c0593a | 5550 | if (intel_crtc->config->has_pch_encoder) |
5a74f70a VS |
5551 | ironlake_fdi_disable(crtc); |
5552 | ||
fd6bbda9 | 5553 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
2c07245f | 5554 | |
6e3c9717 | 5555 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5556 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5557 | |
6e266956 | 5558 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 VS |
5559 | i915_reg_t reg; |
5560 | u32 temp; | |
5561 | ||
d925c59a DV |
5562 | /* disable TRANS_DP_CTL */ |
5563 | reg = TRANS_DP_CTL(pipe); | |
5564 | temp = I915_READ(reg); | |
5565 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5566 | TRANS_DP_PORT_SEL_MASK); | |
5567 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5568 | I915_WRITE(reg, temp); | |
5569 | ||
5570 | /* disable DPLL_SEL */ | |
5571 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5572 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5573 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5574 | } |
e3421a18 | 5575 | |
d925c59a DV |
5576 | ironlake_fdi_pll_disable(intel_crtc); |
5577 | } | |
81b088ca | 5578 | |
b2c0593a | 5579 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
81b088ca | 5580 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 | 5581 | } |
1b3c7a47 | 5582 | |
4a806558 ML |
5583 | static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5584 | struct drm_atomic_state *old_state) | |
ee7b9f93 | 5585 | { |
4a806558 | 5586 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
6315b5d3 | 5587 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee7b9f93 | 5588 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 5589 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5590 | |
d2d65408 | 5591 | if (intel_crtc->config->has_pch_encoder) |
29012159 | 5592 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); |
d2d65408 | 5593 | |
fd6bbda9 | 5594 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
4f771f10 | 5595 | |
f9b61ff6 DV |
5596 | drm_crtc_vblank_off(crtc); |
5597 | assert_vblank_disabled(crtc); | |
5598 | ||
4d1de975 | 5599 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ |
d7edc4e5 | 5600 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5601 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5602 | |
0037071d | 5603 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST)) |
3dc38eea | 5604 | intel_ddi_set_vc_payload_alloc(intel_crtc->config, false); |
a4bf214f | 5605 | |
d7edc4e5 | 5606 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5607 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5608 | |
6315b5d3 | 5609 | if (INTEL_GEN(dev_priv) >= 9) |
e435d6e5 | 5610 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5611 | else |
bfd16b2a | 5612 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5613 | |
d7edc4e5 | 5614 | if (!transcoder_is_dsi(cpu_transcoder)) |
3dc38eea | 5615 | intel_ddi_disable_pipe_clock(intel_crtc->config); |
4f771f10 | 5616 | |
fd6bbda9 | 5617 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
81b088ca | 5618 | |
b7076546 | 5619 | if (old_crtc_state->has_pch_encoder) |
29012159 | 5620 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
4f771f10 PZ |
5621 | } |
5622 | ||
2dd24552 JB |
5623 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5624 | { | |
5625 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5626 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 5627 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5628 | |
681a8504 | 5629 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5630 | return; |
5631 | ||
2dd24552 | 5632 | /* |
c0b03411 DV |
5633 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5634 | * according to register description and PRM. | |
2dd24552 | 5635 | */ |
c0b03411 DV |
5636 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5637 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5638 | |
b074cec8 JB |
5639 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5640 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5641 | |
5642 | /* Border color in case we don't scale up to the full screen. Black by | |
5643 | * default, change to something else for debugging. */ | |
5644 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5645 | } |
5646 | ||
79f255a0 | 5647 | enum intel_display_power_domain intel_port_to_power_domain(enum port port) |
d05410f9 DA |
5648 | { |
5649 | switch (port) { | |
5650 | case PORT_A: | |
6331a704 | 5651 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5652 | case PORT_B: |
6331a704 | 5653 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5654 | case PORT_C: |
6331a704 | 5655 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5656 | case PORT_D: |
6331a704 | 5657 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5658 | case PORT_E: |
6331a704 | 5659 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5660 | default: |
b9fec167 | 5661 | MISSING_CASE(port); |
d05410f9 DA |
5662 | return POWER_DOMAIN_PORT_OTHER; |
5663 | } | |
5664 | } | |
5665 | ||
d8fc70b7 ACO |
5666 | static u64 get_crtc_power_domains(struct drm_crtc *crtc, |
5667 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5668 | { |
319be8ae | 5669 | struct drm_device *dev = crtc->dev; |
37255d8d | 5670 | struct drm_i915_private *dev_priv = to_i915(dev); |
74bff5f9 | 5671 | struct drm_encoder *encoder; |
319be8ae ID |
5672 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5673 | enum pipe pipe = intel_crtc->pipe; | |
d8fc70b7 | 5674 | u64 mask; |
74bff5f9 | 5675 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 5676 | |
74bff5f9 | 5677 | if (!crtc_state->base.active) |
292b990e ML |
5678 | return 0; |
5679 | ||
77d22dca ID |
5680 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5681 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
5682 | if (crtc_state->pch_pfit.enabled || |
5683 | crtc_state->pch_pfit.force_thru) | |
d8fc70b7 | 5684 | mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
77d22dca | 5685 | |
74bff5f9 ML |
5686 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
5687 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5688 | ||
79f255a0 | 5689 | mask |= BIT_ULL(intel_encoder->power_domain); |
74bff5f9 | 5690 | } |
319be8ae | 5691 | |
37255d8d ML |
5692 | if (HAS_DDI(dev_priv) && crtc_state->has_audio) |
5693 | mask |= BIT(POWER_DOMAIN_AUDIO); | |
5694 | ||
15e7ec29 | 5695 | if (crtc_state->shared_dpll) |
d8fc70b7 | 5696 | mask |= BIT_ULL(POWER_DOMAIN_PLLS); |
15e7ec29 | 5697 | |
77d22dca ID |
5698 | return mask; |
5699 | } | |
5700 | ||
d2d15016 | 5701 | static u64 |
74bff5f9 ML |
5702 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, |
5703 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5704 | { |
fac5e23e | 5705 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
292b990e ML |
5706 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5707 | enum intel_display_power_domain domain; | |
d8fc70b7 | 5708 | u64 domains, new_domains, old_domains; |
77d22dca | 5709 | |
292b990e | 5710 | old_domains = intel_crtc->enabled_power_domains; |
74bff5f9 ML |
5711 | intel_crtc->enabled_power_domains = new_domains = |
5712 | get_crtc_power_domains(crtc, crtc_state); | |
77d22dca | 5713 | |
5a21b665 | 5714 | domains = new_domains & ~old_domains; |
292b990e ML |
5715 | |
5716 | for_each_power_domain(domain, domains) | |
5717 | intel_display_power_get(dev_priv, domain); | |
5718 | ||
5a21b665 | 5719 | return old_domains & ~new_domains; |
292b990e ML |
5720 | } |
5721 | ||
5722 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
d8fc70b7 | 5723 | u64 domains) |
292b990e ML |
5724 | { |
5725 | enum intel_display_power_domain domain; | |
5726 | ||
5727 | for_each_power_domain(domain, domains) | |
5728 | intel_display_power_put(dev_priv, domain); | |
5729 | } | |
77d22dca | 5730 | |
7ff89ca2 VS |
5731 | static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config, |
5732 | struct drm_atomic_state *old_state) | |
adafdc6f | 5733 | { |
ff32c54e VS |
5734 | struct intel_atomic_state *old_intel_state = |
5735 | to_intel_atomic_state(old_state); | |
7ff89ca2 VS |
5736 | struct drm_crtc *crtc = pipe_config->base.crtc; |
5737 | struct drm_device *dev = crtc->dev; | |
5738 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5739 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5740 | int pipe = intel_crtc->pipe; | |
adafdc6f | 5741 | |
7ff89ca2 VS |
5742 | if (WARN_ON(intel_crtc->active)) |
5743 | return; | |
adafdc6f | 5744 | |
7ff89ca2 VS |
5745 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
5746 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
b2045352 | 5747 | |
7ff89ca2 VS |
5748 | intel_set_pipe_timings(intel_crtc); |
5749 | intel_set_pipe_src_size(intel_crtc); | |
b2045352 | 5750 | |
7ff89ca2 VS |
5751 | if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { |
5752 | struct drm_i915_private *dev_priv = to_i915(dev); | |
560a7ae4 | 5753 | |
7ff89ca2 VS |
5754 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); |
5755 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
560a7ae4 DL |
5756 | } |
5757 | ||
7ff89ca2 | 5758 | i9xx_set_pipeconf(intel_crtc); |
560a7ae4 | 5759 | |
7ff89ca2 | 5760 | intel_crtc->active = true; |
92891e45 | 5761 | |
7ff89ca2 | 5762 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5f199dfa | 5763 | |
7ff89ca2 | 5764 | intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); |
5f199dfa | 5765 | |
7ff89ca2 VS |
5766 | if (IS_CHERRYVIEW(dev_priv)) { |
5767 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
5768 | chv_enable_pll(intel_crtc, intel_crtc->config); | |
5769 | } else { | |
5770 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
5771 | vlv_enable_pll(intel_crtc, intel_crtc->config); | |
5f199dfa VS |
5772 | } |
5773 | ||
7ff89ca2 | 5774 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
5f199dfa | 5775 | |
7ff89ca2 | 5776 | i9xx_pfit_enable(intel_crtc); |
89b3c3c7 | 5777 | |
7ff89ca2 | 5778 | intel_color_load_luts(&pipe_config->base); |
89b3c3c7 | 5779 | |
ff32c54e VS |
5780 | dev_priv->display.initial_watermarks(old_intel_state, |
5781 | pipe_config); | |
7ff89ca2 VS |
5782 | intel_enable_pipe(intel_crtc); |
5783 | ||
5784 | assert_vblank_disabled(crtc); | |
5785 | drm_crtc_vblank_on(crtc); | |
89b3c3c7 | 5786 | |
7ff89ca2 | 5787 | intel_encoders_enable(crtc, pipe_config, old_state); |
89b3c3c7 ACO |
5788 | } |
5789 | ||
7ff89ca2 | 5790 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
2b73001e | 5791 | { |
7ff89ca2 VS |
5792 | struct drm_device *dev = crtc->base.dev; |
5793 | struct drm_i915_private *dev_priv = to_i915(dev); | |
83d7c81f | 5794 | |
7ff89ca2 VS |
5795 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
5796 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
2b73001e VS |
5797 | } |
5798 | ||
7ff89ca2 VS |
5799 | static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config, |
5800 | struct drm_atomic_state *old_state) | |
2b73001e | 5801 | { |
04548cba VS |
5802 | struct intel_atomic_state *old_intel_state = |
5803 | to_intel_atomic_state(old_state); | |
7ff89ca2 VS |
5804 | struct drm_crtc *crtc = pipe_config->base.crtc; |
5805 | struct drm_device *dev = crtc->dev; | |
5806 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5807 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5808 | enum pipe pipe = intel_crtc->pipe; | |
2b73001e | 5809 | |
7ff89ca2 VS |
5810 | if (WARN_ON(intel_crtc->active)) |
5811 | return; | |
2b73001e | 5812 | |
7ff89ca2 | 5813 | i9xx_set_pll_dividers(intel_crtc); |
2b73001e | 5814 | |
7ff89ca2 VS |
5815 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
5816 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
83d7c81f | 5817 | |
7ff89ca2 VS |
5818 | intel_set_pipe_timings(intel_crtc); |
5819 | intel_set_pipe_src_size(intel_crtc); | |
2b73001e | 5820 | |
7ff89ca2 | 5821 | i9xx_set_pipeconf(intel_crtc); |
f8437dd1 | 5822 | |
7ff89ca2 | 5823 | intel_crtc->active = true; |
5f199dfa | 5824 | |
7ff89ca2 VS |
5825 | if (!IS_GEN2(dev_priv)) |
5826 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5f199dfa | 5827 | |
7ff89ca2 | 5828 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
f8437dd1 | 5829 | |
7ff89ca2 | 5830 | i9xx_enable_pll(intel_crtc); |
f8437dd1 | 5831 | |
7ff89ca2 | 5832 | i9xx_pfit_enable(intel_crtc); |
f8437dd1 | 5833 | |
7ff89ca2 | 5834 | intel_color_load_luts(&pipe_config->base); |
f8437dd1 | 5835 | |
04548cba VS |
5836 | if (dev_priv->display.initial_watermarks != NULL) |
5837 | dev_priv->display.initial_watermarks(old_intel_state, | |
5838 | intel_crtc->config); | |
5839 | else | |
5840 | intel_update_watermarks(intel_crtc); | |
7ff89ca2 | 5841 | intel_enable_pipe(intel_crtc); |
f8437dd1 | 5842 | |
7ff89ca2 VS |
5843 | assert_vblank_disabled(crtc); |
5844 | drm_crtc_vblank_on(crtc); | |
f8437dd1 | 5845 | |
7ff89ca2 VS |
5846 | intel_encoders_enable(crtc, pipe_config, old_state); |
5847 | } | |
f8437dd1 | 5848 | |
7ff89ca2 VS |
5849 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
5850 | { | |
5851 | struct drm_device *dev = crtc->base.dev; | |
5852 | struct drm_i915_private *dev_priv = to_i915(dev); | |
f8437dd1 | 5853 | |
7ff89ca2 | 5854 | if (!crtc->config->gmch_pfit.control) |
f8437dd1 | 5855 | return; |
f8437dd1 | 5856 | |
7ff89ca2 VS |
5857 | assert_pipe_disabled(dev_priv, crtc->pipe); |
5858 | ||
5859 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", | |
5860 | I915_READ(PFIT_CONTROL)); | |
5861 | I915_WRITE(PFIT_CONTROL, 0); | |
f8437dd1 VK |
5862 | } |
5863 | ||
7ff89ca2 VS |
5864 | static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5865 | struct drm_atomic_state *old_state) | |
f8437dd1 | 5866 | { |
7ff89ca2 VS |
5867 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
5868 | struct drm_device *dev = crtc->dev; | |
5869 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5870 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5871 | int pipe = intel_crtc->pipe; | |
d66a2194 | 5872 | |
d66a2194 | 5873 | /* |
7ff89ca2 VS |
5874 | * On gen2 planes are double buffered but the pipe isn't, so we must |
5875 | * wait for planes to fully turn off before disabling the pipe. | |
d66a2194 | 5876 | */ |
7ff89ca2 VS |
5877 | if (IS_GEN2(dev_priv)) |
5878 | intel_wait_for_vblank(dev_priv, pipe); | |
d66a2194 | 5879 | |
7ff89ca2 | 5880 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
d66a2194 | 5881 | |
7ff89ca2 VS |
5882 | drm_crtc_vblank_off(crtc); |
5883 | assert_vblank_disabled(crtc); | |
d66a2194 | 5884 | |
7ff89ca2 | 5885 | intel_disable_pipe(intel_crtc); |
d66a2194 | 5886 | |
7ff89ca2 | 5887 | i9xx_pfit_disable(intel_crtc); |
89b3c3c7 | 5888 | |
7ff89ca2 | 5889 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
d66a2194 | 5890 | |
7ff89ca2 VS |
5891 | if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) { |
5892 | if (IS_CHERRYVIEW(dev_priv)) | |
5893 | chv_disable_pll(dev_priv, pipe); | |
5894 | else if (IS_VALLEYVIEW(dev_priv)) | |
5895 | vlv_disable_pll(dev_priv, pipe); | |
5896 | else | |
5897 | i9xx_disable_pll(intel_crtc); | |
5898 | } | |
c2e001ef | 5899 | |
7ff89ca2 | 5900 | intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state); |
89b3c3c7 | 5901 | |
7ff89ca2 VS |
5902 | if (!IS_GEN2(dev_priv)) |
5903 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
ff32c54e VS |
5904 | |
5905 | if (!dev_priv->display.initial_watermarks) | |
5906 | intel_update_watermarks(intel_crtc); | |
2ee0da16 VS |
5907 | |
5908 | /* clock the pipe down to 640x480@60 to potentially save power */ | |
5909 | if (IS_I830(dev_priv)) | |
5910 | i830_enable_pipe(dev_priv, pipe); | |
f8437dd1 VK |
5911 | } |
5912 | ||
da1d0e26 VS |
5913 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc, |
5914 | struct drm_modeset_acquire_ctx *ctx) | |
f8437dd1 | 5915 | { |
7ff89ca2 VS |
5916 | struct intel_encoder *encoder; |
5917 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5918 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
5919 | enum intel_display_power_domain domain; | |
d2d15016 | 5920 | u64 domains; |
7ff89ca2 VS |
5921 | struct drm_atomic_state *state; |
5922 | struct intel_crtc_state *crtc_state; | |
5923 | int ret; | |
f8437dd1 | 5924 | |
7ff89ca2 VS |
5925 | if (!intel_crtc->active) |
5926 | return; | |
a8ca4934 | 5927 | |
7ff89ca2 | 5928 | if (crtc->primary->state->visible) { |
7ff89ca2 | 5929 | intel_pre_disable_primary_noatomic(crtc); |
709e05c3 | 5930 | |
7ff89ca2 VS |
5931 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); |
5932 | crtc->primary->state->visible = false; | |
5933 | } | |
5d96d8af | 5934 | |
7ff89ca2 VS |
5935 | state = drm_atomic_state_alloc(crtc->dev); |
5936 | if (!state) { | |
5937 | DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory", | |
5938 | crtc->base.id, crtc->name); | |
1c3f7700 | 5939 | return; |
7ff89ca2 | 5940 | } |
9f7eb31a | 5941 | |
da1d0e26 | 5942 | state->acquire_ctx = ctx; |
ea61791e | 5943 | |
7ff89ca2 VS |
5944 | /* Everything's already locked, -EDEADLK can't happen. */ |
5945 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); | |
5946 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
9f7eb31a | 5947 | |
7ff89ca2 | 5948 | WARN_ON(IS_ERR(crtc_state) || ret); |
5d96d8af | 5949 | |
7ff89ca2 | 5950 | dev_priv->display.crtc_disable(crtc_state, state); |
4a806558 | 5951 | |
0853695c | 5952 | drm_atomic_state_put(state); |
842e0307 | 5953 | |
78108b7c VS |
5954 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", |
5955 | crtc->base.id, crtc->name); | |
842e0307 ML |
5956 | |
5957 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0); | |
5958 | crtc->state->active = false; | |
37d9078b | 5959 | intel_crtc->active = false; |
842e0307 ML |
5960 | crtc->enabled = false; |
5961 | crtc->state->connector_mask = 0; | |
5962 | crtc->state->encoder_mask = 0; | |
5963 | ||
5964 | for_each_encoder_on_crtc(crtc->dev, crtc, encoder) | |
5965 | encoder->base.crtc = NULL; | |
5966 | ||
58f9c0bc | 5967 | intel_fbc_disable(intel_crtc); |
432081bc | 5968 | intel_update_watermarks(intel_crtc); |
1f7457b1 | 5969 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
5970 | |
5971 | domains = intel_crtc->enabled_power_domains; | |
5972 | for_each_power_domain(domain, domains) | |
5973 | intel_display_power_put(dev_priv, domain); | |
5974 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
5975 | |
5976 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
5977 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
5978 | } |
5979 | ||
6b72d486 ML |
5980 | /* |
5981 | * turn all crtc's off, but do not adjust state | |
5982 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
5983 | */ | |
70e0bd74 | 5984 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 5985 | { |
e2c8b870 | 5986 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 5987 | struct drm_atomic_state *state; |
e2c8b870 | 5988 | int ret; |
70e0bd74 | 5989 | |
e2c8b870 ML |
5990 | state = drm_atomic_helper_suspend(dev); |
5991 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
5992 | if (ret) |
5993 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
5994 | else |
5995 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 5996 | return ret; |
ee7b9f93 JB |
5997 | } |
5998 | ||
ea5b213a | 5999 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6000 | { |
4ef69c7a | 6001 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6002 | |
ea5b213a CW |
6003 | drm_encoder_cleanup(encoder); |
6004 | kfree(intel_encoder); | |
7e7d76c3 JB |
6005 | } |
6006 | ||
0a91ca29 DV |
6007 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6008 | * internal consistency). */ | |
749d98b8 ML |
6009 | static void intel_connector_verify_state(struct drm_crtc_state *crtc_state, |
6010 | struct drm_connector_state *conn_state) | |
79e53945 | 6011 | { |
749d98b8 | 6012 | struct intel_connector *connector = to_intel_connector(conn_state->connector); |
35dd3c64 ML |
6013 | |
6014 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6015 | connector->base.base.id, | |
6016 | connector->base.name); | |
6017 | ||
0a91ca29 | 6018 | if (connector->get_hw_state(connector)) { |
e85376cb | 6019 | struct intel_encoder *encoder = connector->encoder; |
0a91ca29 | 6020 | |
749d98b8 | 6021 | I915_STATE_WARN(!crtc_state, |
35dd3c64 | 6022 | "connector enabled without attached crtc\n"); |
0a91ca29 | 6023 | |
749d98b8 | 6024 | if (!crtc_state) |
35dd3c64 ML |
6025 | return; |
6026 | ||
749d98b8 | 6027 | I915_STATE_WARN(!crtc_state->active, |
35dd3c64 ML |
6028 | "connector is active, but attached crtc isn't\n"); |
6029 | ||
e85376cb | 6030 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6031 | return; |
6032 | ||
e85376cb | 6033 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6034 | "atomic encoder doesn't match attached encoder\n"); |
6035 | ||
e85376cb | 6036 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6037 | "attached encoder crtc differs from connector crtc\n"); |
6038 | } else { | |
749d98b8 | 6039 | I915_STATE_WARN(crtc_state && crtc_state->active, |
4d688a2a | 6040 | "attached crtc is active, but connector isn't\n"); |
749d98b8 | 6041 | I915_STATE_WARN(!crtc_state && conn_state->best_encoder, |
35dd3c64 | 6042 | "best encoder set without crtc!\n"); |
0a91ca29 | 6043 | } |
79e53945 JB |
6044 | } |
6045 | ||
08d9bc92 ACO |
6046 | int intel_connector_init(struct intel_connector *connector) |
6047 | { | |
11c1a9ec | 6048 | struct intel_digital_connector_state *conn_state; |
08d9bc92 | 6049 | |
11c1a9ec ML |
6050 | /* |
6051 | * Allocate enough memory to hold intel_digital_connector_state, | |
6052 | * This might be a few bytes too many, but for connectors that don't | |
6053 | * need it we'll free the state and allocate a smaller one on the first | |
6054 | * succesful commit anyway. | |
6055 | */ | |
6056 | conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL); | |
6057 | if (!conn_state) | |
08d9bc92 ACO |
6058 | return -ENOMEM; |
6059 | ||
11c1a9ec ML |
6060 | __drm_atomic_helper_connector_reset(&connector->base, |
6061 | &conn_state->base); | |
6062 | ||
08d9bc92 ACO |
6063 | return 0; |
6064 | } | |
6065 | ||
6066 | struct intel_connector *intel_connector_alloc(void) | |
6067 | { | |
6068 | struct intel_connector *connector; | |
6069 | ||
6070 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6071 | if (!connector) | |
6072 | return NULL; | |
6073 | ||
6074 | if (intel_connector_init(connector) < 0) { | |
6075 | kfree(connector); | |
6076 | return NULL; | |
6077 | } | |
6078 | ||
6079 | return connector; | |
6080 | } | |
6081 | ||
f0947c37 DV |
6082 | /* Simple connector->get_hw_state implementation for encoders that support only |
6083 | * one connector and no cloning and hence the encoder state determines the state | |
6084 | * of the connector. */ | |
6085 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6086 | { |
24929352 | 6087 | enum pipe pipe = 0; |
f0947c37 | 6088 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6089 | |
f0947c37 | 6090 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6091 | } |
6092 | ||
6d293983 | 6093 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6094 | { |
6d293983 ACO |
6095 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6096 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6097 | |
6098 | return 0; | |
6099 | } | |
6100 | ||
6d293983 | 6101 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6102 | struct intel_crtc_state *pipe_config) |
1857e1da | 6103 | { |
8652744b | 6104 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d293983 ACO |
6105 | struct drm_atomic_state *state = pipe_config->base.state; |
6106 | struct intel_crtc *other_crtc; | |
6107 | struct intel_crtc_state *other_crtc_state; | |
6108 | ||
1857e1da DV |
6109 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6110 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6111 | if (pipe_config->fdi_lanes > 4) { | |
6112 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6113 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6114 | return -EINVAL; |
1857e1da DV |
6115 | } |
6116 | ||
8652744b | 6117 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
1857e1da DV |
6118 | if (pipe_config->fdi_lanes > 2) { |
6119 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6120 | pipe_config->fdi_lanes); | |
6d293983 | 6121 | return -EINVAL; |
1857e1da | 6122 | } else { |
6d293983 | 6123 | return 0; |
1857e1da DV |
6124 | } |
6125 | } | |
6126 | ||
b7f05d4a | 6127 | if (INTEL_INFO(dev_priv)->num_pipes == 2) |
6d293983 | 6128 | return 0; |
1857e1da DV |
6129 | |
6130 | /* Ivybridge 3 pipe is really complicated */ | |
6131 | switch (pipe) { | |
6132 | case PIPE_A: | |
6d293983 | 6133 | return 0; |
1857e1da | 6134 | case PIPE_B: |
6d293983 ACO |
6135 | if (pipe_config->fdi_lanes <= 2) |
6136 | return 0; | |
6137 | ||
b91eb5cc | 6138 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C); |
6d293983 ACO |
6139 | other_crtc_state = |
6140 | intel_atomic_get_crtc_state(state, other_crtc); | |
6141 | if (IS_ERR(other_crtc_state)) | |
6142 | return PTR_ERR(other_crtc_state); | |
6143 | ||
6144 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6145 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6146 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6147 | return -EINVAL; |
1857e1da | 6148 | } |
6d293983 | 6149 | return 0; |
1857e1da | 6150 | case PIPE_C: |
251cc67c VS |
6151 | if (pipe_config->fdi_lanes > 2) { |
6152 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6153 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6154 | return -EINVAL; |
251cc67c | 6155 | } |
6d293983 | 6156 | |
b91eb5cc | 6157 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B); |
6d293983 ACO |
6158 | other_crtc_state = |
6159 | intel_atomic_get_crtc_state(state, other_crtc); | |
6160 | if (IS_ERR(other_crtc_state)) | |
6161 | return PTR_ERR(other_crtc_state); | |
6162 | ||
6163 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6164 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6165 | return -EINVAL; |
1857e1da | 6166 | } |
6d293983 | 6167 | return 0; |
1857e1da DV |
6168 | default: |
6169 | BUG(); | |
6170 | } | |
6171 | } | |
6172 | ||
e29c22c0 DV |
6173 | #define RETRY 1 |
6174 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6175 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6176 | { |
1857e1da | 6177 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6178 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6179 | int lane, link_bw, fdi_dotclock, ret; |
6180 | bool needs_recompute = false; | |
877d48d5 | 6181 | |
e29c22c0 | 6182 | retry: |
877d48d5 DV |
6183 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6184 | * each output octet as 10 bits. The actual frequency | |
6185 | * is stored as a divider into a 100MHz clock, and the | |
6186 | * mode pixel clock is stored in units of 1KHz. | |
6187 | * Hence the bw of each lane in terms of the mode signal | |
6188 | * is: | |
6189 | */ | |
21a727b3 | 6190 | link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); |
877d48d5 | 6191 | |
241bfc38 | 6192 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6193 | |
2bd89a07 | 6194 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6195 | pipe_config->pipe_bpp); |
6196 | ||
6197 | pipe_config->fdi_lanes = lane; | |
6198 | ||
2bd89a07 | 6199 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
b31e85ed | 6200 | link_bw, &pipe_config->fdi_m_n, false); |
1857e1da | 6201 | |
e3b247da | 6202 | ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
6d293983 | 6203 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
e29c22c0 | 6204 | pipe_config->pipe_bpp -= 2*3; |
7ff89ca2 VS |
6205 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", |
6206 | pipe_config->pipe_bpp); | |
6207 | needs_recompute = true; | |
6208 | pipe_config->bw_constrained = true; | |
257a7ffc | 6209 | |
7ff89ca2 | 6210 | goto retry; |
257a7ffc | 6211 | } |
79e53945 | 6212 | |
7ff89ca2 VS |
6213 | if (needs_recompute) |
6214 | return RETRY; | |
e70236a8 | 6215 | |
7ff89ca2 | 6216 | return ret; |
e70236a8 JB |
6217 | } |
6218 | ||
7ff89ca2 VS |
6219 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6220 | struct intel_crtc_state *pipe_config) | |
e70236a8 | 6221 | { |
7ff89ca2 VS |
6222 | if (pipe_config->pipe_bpp > 24) |
6223 | return false; | |
e70236a8 | 6224 | |
7ff89ca2 VS |
6225 | /* HSW can handle pixel rate up to cdclk? */ |
6226 | if (IS_HASWELL(dev_priv)) | |
6227 | return true; | |
1b1d2716 | 6228 | |
65cd2b3f | 6229 | /* |
7ff89ca2 VS |
6230 | * We compare against max which means we must take |
6231 | * the increased cdclk requirement into account when | |
6232 | * calculating the new cdclk. | |
6233 | * | |
6234 | * Should measure whether using a lower cdclk w/o IPS | |
e70236a8 | 6235 | */ |
7ff89ca2 VS |
6236 | return pipe_config->pixel_rate <= |
6237 | dev_priv->max_cdclk_freq * 95 / 100; | |
e70236a8 | 6238 | } |
79e53945 | 6239 | |
7ff89ca2 VS |
6240 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
6241 | struct intel_crtc_state *pipe_config) | |
6242 | { | |
6243 | struct drm_device *dev = crtc->base.dev; | |
6244 | struct drm_i915_private *dev_priv = to_i915(dev); | |
34edce2f | 6245 | |
7ff89ca2 VS |
6246 | pipe_config->ips_enabled = i915.enable_ips && |
6247 | hsw_crtc_supports_ips(crtc) && | |
6248 | pipe_config_supports_ips(dev_priv, pipe_config); | |
34edce2f VS |
6249 | } |
6250 | ||
7ff89ca2 | 6251 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
34edce2f | 6252 | { |
7ff89ca2 | 6253 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
34edce2f | 6254 | |
7ff89ca2 VS |
6255 | /* GDG double wide on either pipe, otherwise pipe A only */ |
6256 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6257 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
34edce2f VS |
6258 | } |
6259 | ||
ceb99320 VS |
6260 | static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) |
6261 | { | |
6262 | uint32_t pixel_rate; | |
6263 | ||
6264 | pixel_rate = pipe_config->base.adjusted_mode.crtc_clock; | |
6265 | ||
6266 | /* | |
6267 | * We only use IF-ID interlacing. If we ever use | |
6268 | * PF-ID we'll need to adjust the pixel_rate here. | |
6269 | */ | |
6270 | ||
6271 | if (pipe_config->pch_pfit.enabled) { | |
6272 | uint64_t pipe_w, pipe_h, pfit_w, pfit_h; | |
6273 | uint32_t pfit_size = pipe_config->pch_pfit.size; | |
6274 | ||
6275 | pipe_w = pipe_config->pipe_src_w; | |
6276 | pipe_h = pipe_config->pipe_src_h; | |
6277 | ||
6278 | pfit_w = (pfit_size >> 16) & 0xFFFF; | |
6279 | pfit_h = pfit_size & 0xFFFF; | |
6280 | if (pipe_w < pfit_w) | |
6281 | pipe_w = pfit_w; | |
6282 | if (pipe_h < pfit_h) | |
6283 | pipe_h = pfit_h; | |
6284 | ||
6285 | if (WARN_ON(!pfit_w || !pfit_h)) | |
6286 | return pixel_rate; | |
6287 | ||
6288 | pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, | |
6289 | pfit_w * pfit_h); | |
6290 | } | |
6291 | ||
6292 | return pixel_rate; | |
6293 | } | |
6294 | ||
7ff89ca2 | 6295 | static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) |
34edce2f | 6296 | { |
7ff89ca2 | 6297 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); |
34edce2f | 6298 | |
7ff89ca2 VS |
6299 | if (HAS_GMCH_DISPLAY(dev_priv)) |
6300 | /* FIXME calculate proper pipe pixel rate for GMCH pfit */ | |
6301 | crtc_state->pixel_rate = | |
6302 | crtc_state->base.adjusted_mode.crtc_clock; | |
6303 | else | |
6304 | crtc_state->pixel_rate = | |
6305 | ilk_pipe_pixel_rate(crtc_state); | |
6306 | } | |
34edce2f | 6307 | |
7ff89ca2 VS |
6308 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
6309 | struct intel_crtc_state *pipe_config) | |
6310 | { | |
6311 | struct drm_device *dev = crtc->base.dev; | |
6312 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6313 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; | |
6314 | int clock_limit = dev_priv->max_dotclk_freq; | |
34edce2f | 6315 | |
7ff89ca2 VS |
6316 | if (INTEL_GEN(dev_priv) < 4) { |
6317 | clock_limit = dev_priv->max_cdclk_freq * 9 / 10; | |
34edce2f | 6318 | |
7ff89ca2 VS |
6319 | /* |
6320 | * Enable double wide mode when the dot clock | |
6321 | * is > 90% of the (display) core speed. | |
6322 | */ | |
6323 | if (intel_crtc_supports_double_wide(crtc) && | |
6324 | adjusted_mode->crtc_clock > clock_limit) { | |
6325 | clock_limit = dev_priv->max_dotclk_freq; | |
6326 | pipe_config->double_wide = true; | |
6327 | } | |
34edce2f VS |
6328 | } |
6329 | ||
7ff89ca2 VS |
6330 | if (adjusted_mode->crtc_clock > clock_limit) { |
6331 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6332 | adjusted_mode->crtc_clock, clock_limit, | |
6333 | yesno(pipe_config->double_wide)); | |
6334 | return -EINVAL; | |
6335 | } | |
34edce2f | 6336 | |
25edf915 SS |
6337 | if (pipe_config->ycbcr420 && pipe_config->base.ctm) { |
6338 | /* | |
6339 | * There is only one pipe CSC unit per pipe, and we need that | |
6340 | * for output conversion from RGB->YCBCR. So if CTM is already | |
6341 | * applied we can't support YCBCR420 output. | |
6342 | */ | |
6343 | DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n"); | |
6344 | return -EINVAL; | |
6345 | } | |
6346 | ||
7ff89ca2 VS |
6347 | /* |
6348 | * Pipe horizontal size must be even in: | |
6349 | * - DVO ganged mode | |
6350 | * - LVDS dual channel mode | |
6351 | * - Double wide pipe | |
6352 | */ | |
6353 | if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) && | |
6354 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) | |
6355 | pipe_config->pipe_src_w &= ~1; | |
34edce2f | 6356 | |
7ff89ca2 VS |
6357 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6358 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
6359 | */ | |
6360 | if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) && | |
6361 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) | |
6362 | return -EINVAL; | |
34edce2f | 6363 | |
7ff89ca2 | 6364 | intel_crtc_compute_pixel_rate(pipe_config); |
34edce2f | 6365 | |
7ff89ca2 VS |
6366 | if (HAS_IPS(dev_priv)) |
6367 | hsw_compute_ips_config(crtc, pipe_config); | |
34edce2f | 6368 | |
7ff89ca2 VS |
6369 | if (pipe_config->has_pch_encoder) |
6370 | return ironlake_fdi_compute_config(crtc, pipe_config); | |
34edce2f | 6371 | |
7ff89ca2 | 6372 | return 0; |
34edce2f VS |
6373 | } |
6374 | ||
2c07245f | 6375 | static void |
a65851af | 6376 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 6377 | { |
a65851af VS |
6378 | while (*num > DATA_LINK_M_N_MASK || |
6379 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
6380 | *num >>= 1; |
6381 | *den >>= 1; | |
6382 | } | |
6383 | } | |
6384 | ||
a65851af | 6385 | static void compute_m_n(unsigned int m, unsigned int n, |
b31e85ed JN |
6386 | uint32_t *ret_m, uint32_t *ret_n, |
6387 | bool reduce_m_n) | |
a65851af | 6388 | { |
9a86cda0 JN |
6389 | /* |
6390 | * Reduce M/N as much as possible without loss in precision. Several DP | |
6391 | * dongles in particular seem to be fussy about too large *link* M/N | |
6392 | * values. The passed in values are more likely to have the least | |
6393 | * significant bits zero than M after rounding below, so do this first. | |
6394 | */ | |
b31e85ed JN |
6395 | if (reduce_m_n) { |
6396 | while ((m & 1) == 0 && (n & 1) == 0) { | |
6397 | m >>= 1; | |
6398 | n >>= 1; | |
6399 | } | |
9a86cda0 JN |
6400 | } |
6401 | ||
a65851af VS |
6402 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); |
6403 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
6404 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
6405 | } | |
6406 | ||
e69d0bc1 DV |
6407 | void |
6408 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
6409 | int pixel_clock, int link_clock, | |
b31e85ed JN |
6410 | struct intel_link_m_n *m_n, |
6411 | bool reduce_m_n) | |
2c07245f | 6412 | { |
e69d0bc1 | 6413 | m_n->tu = 64; |
a65851af VS |
6414 | |
6415 | compute_m_n(bits_per_pixel * pixel_clock, | |
6416 | link_clock * nlanes * 8, | |
b31e85ed JN |
6417 | &m_n->gmch_m, &m_n->gmch_n, |
6418 | reduce_m_n); | |
a65851af VS |
6419 | |
6420 | compute_m_n(pixel_clock, link_clock, | |
b31e85ed JN |
6421 | &m_n->link_m, &m_n->link_n, |
6422 | reduce_m_n); | |
2c07245f ZW |
6423 | } |
6424 | ||
a7615030 CW |
6425 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
6426 | { | |
d330a953 JN |
6427 | if (i915.panel_use_ssc >= 0) |
6428 | return i915.panel_use_ssc != 0; | |
41aa3448 | 6429 | return dev_priv->vbt.lvds_use_ssc |
435793df | 6430 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
6431 | } |
6432 | ||
7429e9d4 | 6433 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 6434 | { |
7df00d7a | 6435 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 6436 | } |
f47709a9 | 6437 | |
7429e9d4 DV |
6438 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
6439 | { | |
6440 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
6441 | } |
6442 | ||
f47709a9 | 6443 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 6444 | struct intel_crtc_state *crtc_state, |
9e2c8475 | 6445 | struct dpll *reduced_clock) |
a7516a05 | 6446 | { |
9b1e14f4 | 6447 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
a7516a05 JB |
6448 | u32 fp, fp2 = 0; |
6449 | ||
9b1e14f4 | 6450 | if (IS_PINEVIEW(dev_priv)) { |
190f68c5 | 6451 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6452 | if (reduced_clock) |
7429e9d4 | 6453 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 6454 | } else { |
190f68c5 | 6455 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6456 | if (reduced_clock) |
7429e9d4 | 6457 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
6458 | } |
6459 | ||
190f68c5 | 6460 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 6461 | |
f47709a9 | 6462 | crtc->lowfreq_avail = false; |
2d84d2b3 | 6463 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 6464 | reduced_clock) { |
190f68c5 | 6465 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 6466 | crtc->lowfreq_avail = true; |
a7516a05 | 6467 | } else { |
190f68c5 | 6468 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
6469 | } |
6470 | } | |
6471 | ||
5e69f97f CML |
6472 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
6473 | pipe) | |
89b667f8 JB |
6474 | { |
6475 | u32 reg_val; | |
6476 | ||
6477 | /* | |
6478 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
6479 | * and set it to a reasonable value instead. | |
6480 | */ | |
ab3c759a | 6481 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
6482 | reg_val &= 0xffffff00; |
6483 | reg_val |= 0x00000030; | |
ab3c759a | 6484 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6485 | |
ab3c759a | 6486 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
ed58570f ID |
6487 | reg_val &= 0x00ffffff; |
6488 | reg_val |= 0x8c000000; | |
ab3c759a | 6489 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 6490 | |
ab3c759a | 6491 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 6492 | reg_val &= 0xffffff00; |
ab3c759a | 6493 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6494 | |
ab3c759a | 6495 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6496 | reg_val &= 0x00ffffff; |
6497 | reg_val |= 0xb0000000; | |
ab3c759a | 6498 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
6499 | } |
6500 | ||
b551842d DV |
6501 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
6502 | struct intel_link_m_n *m_n) | |
6503 | { | |
6504 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6505 | struct drm_i915_private *dev_priv = to_i915(dev); |
b551842d DV |
6506 | int pipe = crtc->pipe; |
6507 | ||
e3b95f1e DV |
6508 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6509 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
6510 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
6511 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
6512 | } |
6513 | ||
6514 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
6515 | struct intel_link_m_n *m_n, |
6516 | struct intel_link_m_n *m2_n2) | |
b551842d | 6517 | { |
6315b5d3 | 6518 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
b551842d | 6519 | int pipe = crtc->pipe; |
6e3c9717 | 6520 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d | 6521 | |
6315b5d3 | 6522 | if (INTEL_GEN(dev_priv) >= 5) { |
b551842d DV |
6523 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6524 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
6525 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
6526 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
6527 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
6528 | * for gen < 8) and if DRRS is supported (to make sure the | |
6529 | * registers are not unnecessarily accessed). | |
6530 | */ | |
920a14b2 TU |
6531 | if (m2_n2 && (IS_CHERRYVIEW(dev_priv) || |
6532 | INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) { | |
f769cd24 VK |
6533 | I915_WRITE(PIPE_DATA_M2(transcoder), |
6534 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
6535 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
6536 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
6537 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
6538 | } | |
b551842d | 6539 | } else { |
e3b95f1e DV |
6540 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6541 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
6542 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
6543 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
6544 | } |
6545 | } | |
6546 | ||
fe3cd48d | 6547 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 6548 | { |
fe3cd48d R |
6549 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
6550 | ||
6551 | if (m_n == M1_N1) { | |
6552 | dp_m_n = &crtc->config->dp_m_n; | |
6553 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
6554 | } else if (m_n == M2_N2) { | |
6555 | ||
6556 | /* | |
6557 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
6558 | * needs to be programmed into M1_N1. | |
6559 | */ | |
6560 | dp_m_n = &crtc->config->dp_m2_n2; | |
6561 | } else { | |
6562 | DRM_ERROR("Unsupported divider value\n"); | |
6563 | return; | |
6564 | } | |
6565 | ||
6e3c9717 ACO |
6566 | if (crtc->config->has_pch_encoder) |
6567 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 6568 | else |
fe3cd48d | 6569 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
6570 | } |
6571 | ||
251ac862 DV |
6572 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
6573 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 | 6574 | { |
03ed5cbf | 6575 | pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | |
cd2d34d9 | 6576 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
6577 | if (crtc->pipe != PIPE_A) |
6578 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
bdd4b6a6 | 6579 | |
cd2d34d9 | 6580 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 6581 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
6582 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | |
6583 | DPLL_EXT_BUFFER_ENABLE_VLV; | |
6584 | ||
03ed5cbf VS |
6585 | pipe_config->dpll_hw_state.dpll_md = |
6586 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
6587 | } | |
bdd4b6a6 | 6588 | |
03ed5cbf VS |
6589 | static void chv_compute_dpll(struct intel_crtc *crtc, |
6590 | struct intel_crtc_state *pipe_config) | |
6591 | { | |
6592 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | | |
cd2d34d9 | 6593 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
6594 | if (crtc->pipe != PIPE_A) |
6595 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
6596 | ||
cd2d34d9 | 6597 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 6598 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
6599 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; |
6600 | ||
03ed5cbf VS |
6601 | pipe_config->dpll_hw_state.dpll_md = |
6602 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
bdd4b6a6 DV |
6603 | } |
6604 | ||
d288f65f | 6605 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6606 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 6607 | { |
f47709a9 | 6608 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6609 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 6610 | enum pipe pipe = crtc->pipe; |
bdd4b6a6 | 6611 | u32 mdiv; |
a0c4da24 | 6612 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 6613 | u32 coreclk, reg_val; |
a0c4da24 | 6614 | |
cd2d34d9 VS |
6615 | /* Enable Refclk */ |
6616 | I915_WRITE(DPLL(pipe), | |
6617 | pipe_config->dpll_hw_state.dpll & | |
6618 | ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); | |
6619 | ||
6620 | /* No need to actually set up the DPLL with DSI */ | |
6621 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
6622 | return; | |
6623 | ||
a580516d | 6624 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 6625 | |
d288f65f VS |
6626 | bestn = pipe_config->dpll.n; |
6627 | bestm1 = pipe_config->dpll.m1; | |
6628 | bestm2 = pipe_config->dpll.m2; | |
6629 | bestp1 = pipe_config->dpll.p1; | |
6630 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 6631 | |
89b667f8 JB |
6632 | /* See eDP HDMI DPIO driver vbios notes doc */ |
6633 | ||
6634 | /* PLL B needs special handling */ | |
bdd4b6a6 | 6635 | if (pipe == PIPE_B) |
5e69f97f | 6636 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
6637 | |
6638 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 6639 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
6640 | |
6641 | /* Disable target IRef on PLL */ | |
ab3c759a | 6642 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 6643 | reg_val &= 0x00ffffff; |
ab3c759a | 6644 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
6645 | |
6646 | /* Disable fast lock */ | |
ab3c759a | 6647 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
6648 | |
6649 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
6650 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
6651 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
6652 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 6653 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
6654 | |
6655 | /* | |
6656 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
6657 | * but we don't support that). | |
6658 | * Note: don't use the DAC post divider as it seems unstable. | |
6659 | */ | |
6660 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 6661 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6662 | |
a0c4da24 | 6663 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 6664 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6665 | |
89b667f8 | 6666 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 6667 | if (pipe_config->port_clock == 162000 || |
2d84d2b3 VS |
6668 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) || |
6669 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 6670 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 6671 | 0x009f0003); |
89b667f8 | 6672 | else |
ab3c759a | 6673 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
6674 | 0x00d0000f); |
6675 | ||
37a5650b | 6676 | if (intel_crtc_has_dp_encoder(pipe_config)) { |
89b667f8 | 6677 | /* Use SSC source */ |
bdd4b6a6 | 6678 | if (pipe == PIPE_A) |
ab3c759a | 6679 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6680 | 0x0df40000); |
6681 | else | |
ab3c759a | 6682 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6683 | 0x0df70000); |
6684 | } else { /* HDMI or VGA */ | |
6685 | /* Use bend source */ | |
bdd4b6a6 | 6686 | if (pipe == PIPE_A) |
ab3c759a | 6687 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6688 | 0x0df70000); |
6689 | else | |
ab3c759a | 6690 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6691 | 0x0df40000); |
6692 | } | |
a0c4da24 | 6693 | |
ab3c759a | 6694 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 6695 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
2210ce7f | 6696 | if (intel_crtc_has_dp_encoder(crtc->config)) |
89b667f8 | 6697 | coreclk |= 0x01000000; |
ab3c759a | 6698 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 6699 | |
ab3c759a | 6700 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 6701 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
6702 | } |
6703 | ||
d288f65f | 6704 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6705 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
6706 | { |
6707 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6708 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 6709 | enum pipe pipe = crtc->pipe; |
9d556c99 | 6710 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 6711 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 6712 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 6713 | u32 dpio_val; |
9cbe40c1 | 6714 | int vco; |
9d556c99 | 6715 | |
cd2d34d9 VS |
6716 | /* Enable Refclk and SSC */ |
6717 | I915_WRITE(DPLL(pipe), | |
6718 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
6719 | ||
6720 | /* No need to actually set up the DPLL with DSI */ | |
6721 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
6722 | return; | |
6723 | ||
d288f65f VS |
6724 | bestn = pipe_config->dpll.n; |
6725 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
6726 | bestm1 = pipe_config->dpll.m1; | |
6727 | bestm2 = pipe_config->dpll.m2 >> 22; | |
6728 | bestp1 = pipe_config->dpll.p1; | |
6729 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 6730 | vco = pipe_config->dpll.vco; |
a945ce7e | 6731 | dpio_val = 0; |
9cbe40c1 | 6732 | loopfilter = 0; |
9d556c99 | 6733 | |
a580516d | 6734 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 6735 | |
9d556c99 CML |
6736 | /* p1 and p2 divider */ |
6737 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
6738 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
6739 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
6740 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
6741 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
6742 | ||
6743 | /* Feedback post-divider - m2 */ | |
6744 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
6745 | ||
6746 | /* Feedback refclk divider - n and m1 */ | |
6747 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
6748 | DPIO_CHV_M1_DIV_BY_2 | | |
6749 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
6750 | ||
6751 | /* M2 fraction division */ | |
25a25dfc | 6752 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
6753 | |
6754 | /* M2 fraction division enable */ | |
a945ce7e VP |
6755 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
6756 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
6757 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
6758 | if (bestm2_frac) | |
6759 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
6760 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 6761 | |
de3a0fde VP |
6762 | /* Program digital lock detect threshold */ |
6763 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
6764 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
6765 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
6766 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
6767 | if (!bestm2_frac) | |
6768 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
6769 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
6770 | ||
9d556c99 | 6771 | /* Loop filter */ |
9cbe40c1 VP |
6772 | if (vco == 5400000) { |
6773 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6774 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
6775 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6776 | tribuf_calcntr = 0x9; | |
6777 | } else if (vco <= 6200000) { | |
6778 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6779 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
6780 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6781 | tribuf_calcntr = 0x9; | |
6782 | } else if (vco <= 6480000) { | |
6783 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6784 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6785 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6786 | tribuf_calcntr = 0x8; | |
6787 | } else { | |
6788 | /* Not supported. Apply the same limits as in the max case */ | |
6789 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6790 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6791 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6792 | tribuf_calcntr = 0; | |
6793 | } | |
9d556c99 CML |
6794 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
6795 | ||
968040b2 | 6796 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
6797 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
6798 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
6799 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
6800 | ||
9d556c99 CML |
6801 | /* AFC Recal */ |
6802 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
6803 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
6804 | DPIO_AFC_RECAL); | |
6805 | ||
a580516d | 6806 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
6807 | } |
6808 | ||
d288f65f VS |
6809 | /** |
6810 | * vlv_force_pll_on - forcibly enable just the PLL | |
6811 | * @dev_priv: i915 private structure | |
6812 | * @pipe: pipe PLL to enable | |
6813 | * @dpll: PLL configuration | |
6814 | * | |
6815 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
6816 | * in cases where we need the PLL enabled even when @pipe is not going to | |
6817 | * be enabled. | |
6818 | */ | |
30ad9814 | 6819 | int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, |
3f36b937 | 6820 | const struct dpll *dpll) |
d288f65f | 6821 | { |
b91eb5cc | 6822 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
3f36b937 TU |
6823 | struct intel_crtc_state *pipe_config; |
6824 | ||
6825 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
6826 | if (!pipe_config) | |
6827 | return -ENOMEM; | |
6828 | ||
6829 | pipe_config->base.crtc = &crtc->base; | |
6830 | pipe_config->pixel_multiplier = 1; | |
6831 | pipe_config->dpll = *dpll; | |
d288f65f | 6832 | |
30ad9814 | 6833 | if (IS_CHERRYVIEW(dev_priv)) { |
3f36b937 TU |
6834 | chv_compute_dpll(crtc, pipe_config); |
6835 | chv_prepare_pll(crtc, pipe_config); | |
6836 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 6837 | } else { |
3f36b937 TU |
6838 | vlv_compute_dpll(crtc, pipe_config); |
6839 | vlv_prepare_pll(crtc, pipe_config); | |
6840 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 6841 | } |
3f36b937 TU |
6842 | |
6843 | kfree(pipe_config); | |
6844 | ||
6845 | return 0; | |
d288f65f VS |
6846 | } |
6847 | ||
6848 | /** | |
6849 | * vlv_force_pll_off - forcibly disable just the PLL | |
6850 | * @dev_priv: i915 private structure | |
6851 | * @pipe: pipe PLL to disable | |
6852 | * | |
6853 | * Disable the PLL for @pipe. To be used in cases where we need | |
6854 | * the PLL enabled even when @pipe is not going to be enabled. | |
6855 | */ | |
30ad9814 | 6856 | void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe) |
d288f65f | 6857 | { |
30ad9814 VS |
6858 | if (IS_CHERRYVIEW(dev_priv)) |
6859 | chv_disable_pll(dev_priv, pipe); | |
d288f65f | 6860 | else |
30ad9814 | 6861 | vlv_disable_pll(dev_priv, pipe); |
d288f65f VS |
6862 | } |
6863 | ||
251ac862 DV |
6864 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
6865 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 6866 | struct dpll *reduced_clock) |
eb1cbe48 | 6867 | { |
9b1e14f4 | 6868 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
eb1cbe48 | 6869 | u32 dpll; |
190f68c5 | 6870 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 6871 | |
190f68c5 | 6872 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 6873 | |
eb1cbe48 DV |
6874 | dpll = DPLL_VGA_MODE_DIS; |
6875 | ||
2d84d2b3 | 6876 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
6877 | dpll |= DPLLB_MODE_LVDS; |
6878 | else | |
6879 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 6880 | |
73f67aa8 JN |
6881 | if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || |
6882 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { | |
190f68c5 | 6883 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 6884 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 6885 | } |
198a037f | 6886 | |
3d6e9ee0 VS |
6887 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
6888 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 6889 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 6890 | |
37a5650b | 6891 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 6892 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
6893 | |
6894 | /* compute bitmask from p1 value */ | |
9b1e14f4 | 6895 | if (IS_PINEVIEW(dev_priv)) |
eb1cbe48 DV |
6896 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
6897 | else { | |
6898 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
9beb5fea | 6899 | if (IS_G4X(dev_priv) && reduced_clock) |
eb1cbe48 DV |
6900 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
6901 | } | |
6902 | switch (clock->p2) { | |
6903 | case 5: | |
6904 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6905 | break; | |
6906 | case 7: | |
6907 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
6908 | break; | |
6909 | case 10: | |
6910 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
6911 | break; | |
6912 | case 14: | |
6913 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
6914 | break; | |
6915 | } | |
9b1e14f4 | 6916 | if (INTEL_GEN(dev_priv) >= 4) |
eb1cbe48 DV |
6917 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
6918 | ||
190f68c5 | 6919 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 6920 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
2d84d2b3 | 6921 | else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 6922 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
6923 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
6924 | else | |
6925 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6926 | ||
6927 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 6928 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 6929 | |
9b1e14f4 | 6930 | if (INTEL_GEN(dev_priv) >= 4) { |
190f68c5 | 6931 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 6932 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 6933 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
6934 | } |
6935 | } | |
6936 | ||
251ac862 DV |
6937 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
6938 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 6939 | struct dpll *reduced_clock) |
eb1cbe48 | 6940 | { |
f47709a9 | 6941 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6942 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb1cbe48 | 6943 | u32 dpll; |
190f68c5 | 6944 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 6945 | |
190f68c5 | 6946 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 6947 | |
eb1cbe48 DV |
6948 | dpll = DPLL_VGA_MODE_DIS; |
6949 | ||
2d84d2b3 | 6950 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
6951 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
6952 | } else { | |
6953 | if (clock->p1 == 2) | |
6954 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
6955 | else | |
6956 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
6957 | if (clock->p2 == 4) | |
6958 | dpll |= PLL_P2_DIVIDE_BY_4; | |
6959 | } | |
6960 | ||
50a0bc90 TU |
6961 | if (!IS_I830(dev_priv) && |
6962 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) | |
4a33e48d DV |
6963 | dpll |= DPLL_DVO_2X_MODE; |
6964 | ||
2d84d2b3 | 6965 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 6966 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
6967 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
6968 | else | |
6969 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6970 | ||
6971 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 6972 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
6973 | } |
6974 | ||
8a654f3b | 6975 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c | 6976 | { |
6315b5d3 | 6977 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
b0e77b9c | 6978 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 6979 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 6980 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
6981 | uint32_t crtc_vtotal, crtc_vblank_end; |
6982 | int vsyncshift = 0; | |
4d8a62ea DV |
6983 | |
6984 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
6985 | * the hw state checker will get angry at the mismatch. */ | |
6986 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
6987 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 6988 | |
609aeaca | 6989 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 6990 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
6991 | crtc_vtotal -= 1; |
6992 | crtc_vblank_end -= 1; | |
609aeaca | 6993 | |
2d84d2b3 | 6994 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
6995 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
6996 | else | |
6997 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
6998 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
6999 | if (vsyncshift < 0) |
7000 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7001 | } |
7002 | ||
6315b5d3 | 7003 | if (INTEL_GEN(dev_priv) > 3) |
fe2b8f9d | 7004 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7005 | |
fe2b8f9d | 7006 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7007 | (adjusted_mode->crtc_hdisplay - 1) | |
7008 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7009 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7010 | (adjusted_mode->crtc_hblank_start - 1) | |
7011 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7012 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7013 | (adjusted_mode->crtc_hsync_start - 1) | |
7014 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7015 | ||
fe2b8f9d | 7016 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7017 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7018 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7019 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7020 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7021 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7022 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7023 | (adjusted_mode->crtc_vsync_start - 1) | |
7024 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7025 | ||
b5e508d4 PZ |
7026 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7027 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7028 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7029 | * bits. */ | |
772c2a51 | 7030 | if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && |
b5e508d4 PZ |
7031 | (pipe == PIPE_B || pipe == PIPE_C)) |
7032 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7033 | ||
bc58be60 JN |
7034 | } |
7035 | ||
7036 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) | |
7037 | { | |
7038 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 7039 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 JN |
7040 | enum pipe pipe = intel_crtc->pipe; |
7041 | ||
b0e77b9c PZ |
7042 | /* pipesrc controls the size that is scaled from, which should |
7043 | * always be the user's requested size. | |
7044 | */ | |
7045 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7046 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7047 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7048 | } |
7049 | ||
1bd1bd80 | 7050 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7051 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7052 | { |
7053 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7054 | struct drm_i915_private *dev_priv = to_i915(dev); |
1bd1bd80 DV |
7055 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
7056 | uint32_t tmp; | |
7057 | ||
7058 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7059 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7060 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7061 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7062 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7063 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7064 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7065 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7066 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7067 | |
7068 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7069 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7070 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7071 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7072 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7073 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7074 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7075 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7076 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7077 | |
7078 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7079 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7080 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7081 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 | 7082 | } |
bc58be60 JN |
7083 | } |
7084 | ||
7085 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, | |
7086 | struct intel_crtc_state *pipe_config) | |
7087 | { | |
7088 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7089 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 | 7090 | u32 tmp; |
1bd1bd80 DV |
7091 | |
7092 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7093 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7094 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7095 | ||
2d112de7 ACO |
7096 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7097 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7098 | } |
7099 | ||
f6a83288 | 7100 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7101 | struct intel_crtc_state *pipe_config) |
babea61d | 7102 | { |
2d112de7 ACO |
7103 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7104 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7105 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7106 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7107 | |
2d112de7 ACO |
7108 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7109 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7110 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7111 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7112 | |
2d112de7 | 7113 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7114 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7115 | |
2d112de7 | 7116 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
cd13f5ab ML |
7117 | |
7118 | mode->hsync = drm_mode_hsync(mode); | |
7119 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7120 | drm_mode_set_name(mode); | |
babea61d JB |
7121 | } |
7122 | ||
84b046f3 DV |
7123 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7124 | { | |
6315b5d3 | 7125 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
84b046f3 DV |
7126 | uint32_t pipeconf; |
7127 | ||
9f11a9e4 | 7128 | pipeconf = 0; |
84b046f3 | 7129 | |
e56134bc VS |
7130 | /* we keep both pipes enabled on 830 */ |
7131 | if (IS_I830(dev_priv)) | |
b6b5d049 | 7132 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; |
67c72a12 | 7133 | |
6e3c9717 | 7134 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7135 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7136 | |
ff9ce46e | 7137 | /* only g4x and later have fancy bpc/dither controls */ |
9beb5fea TU |
7138 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
7139 | IS_CHERRYVIEW(dev_priv)) { | |
ff9ce46e | 7140 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7141 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7142 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7143 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7144 | |
6e3c9717 | 7145 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7146 | case 18: |
7147 | pipeconf |= PIPECONF_6BPC; | |
7148 | break; | |
7149 | case 24: | |
7150 | pipeconf |= PIPECONF_8BPC; | |
7151 | break; | |
7152 | case 30: | |
7153 | pipeconf |= PIPECONF_10BPC; | |
7154 | break; | |
7155 | default: | |
7156 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7157 | BUG(); | |
84b046f3 DV |
7158 | } |
7159 | } | |
7160 | ||
56b857a5 | 7161 | if (HAS_PIPE_CXSR(dev_priv)) { |
84b046f3 DV |
7162 | if (intel_crtc->lowfreq_avail) { |
7163 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7164 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7165 | } else { | |
7166 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7167 | } |
7168 | } | |
7169 | ||
6e3c9717 | 7170 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
6315b5d3 | 7171 | if (INTEL_GEN(dev_priv) < 4 || |
2d84d2b3 | 7172 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7173 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7174 | else | |
7175 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7176 | } else | |
84b046f3 DV |
7177 | pipeconf |= PIPECONF_PROGRESSIVE; |
7178 | ||
920a14b2 | 7179 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 7180 | intel_crtc->config->limited_color_range) |
9f11a9e4 | 7181 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7182 | |
84b046f3 DV |
7183 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7184 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7185 | } | |
7186 | ||
81c97f52 ACO |
7187 | static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, |
7188 | struct intel_crtc_state *crtc_state) | |
7189 | { | |
7190 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7191 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7192 | const struct intel_limit *limit; |
81c97f52 ACO |
7193 | int refclk = 48000; |
7194 | ||
7195 | memset(&crtc_state->dpll_hw_state, 0, | |
7196 | sizeof(crtc_state->dpll_hw_state)); | |
7197 | ||
2d84d2b3 | 7198 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
81c97f52 ACO |
7199 | if (intel_panel_use_ssc(dev_priv)) { |
7200 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7201 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7202 | } | |
7203 | ||
7204 | limit = &intel_limits_i8xx_lvds; | |
2d84d2b3 | 7205 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { |
81c97f52 ACO |
7206 | limit = &intel_limits_i8xx_dvo; |
7207 | } else { | |
7208 | limit = &intel_limits_i8xx_dac; | |
7209 | } | |
7210 | ||
7211 | if (!crtc_state->clock_set && | |
7212 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7213 | refclk, NULL, &crtc_state->dpll)) { | |
7214 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7215 | return -EINVAL; | |
7216 | } | |
7217 | ||
7218 | i8xx_compute_dpll(crtc, crtc_state, NULL); | |
7219 | ||
7220 | return 0; | |
7221 | } | |
7222 | ||
19ec6693 ACO |
7223 | static int g4x_crtc_compute_clock(struct intel_crtc *crtc, |
7224 | struct intel_crtc_state *crtc_state) | |
7225 | { | |
7226 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7227 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7228 | const struct intel_limit *limit; |
19ec6693 ACO |
7229 | int refclk = 96000; |
7230 | ||
7231 | memset(&crtc_state->dpll_hw_state, 0, | |
7232 | sizeof(crtc_state->dpll_hw_state)); | |
7233 | ||
2d84d2b3 | 7234 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
19ec6693 ACO |
7235 | if (intel_panel_use_ssc(dev_priv)) { |
7236 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7237 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7238 | } | |
7239 | ||
7240 | if (intel_is_dual_link_lvds(dev)) | |
7241 | limit = &intel_limits_g4x_dual_channel_lvds; | |
7242 | else | |
7243 | limit = &intel_limits_g4x_single_channel_lvds; | |
2d84d2b3 VS |
7244 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || |
7245 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
19ec6693 | 7246 | limit = &intel_limits_g4x_hdmi; |
2d84d2b3 | 7247 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
19ec6693 ACO |
7248 | limit = &intel_limits_g4x_sdvo; |
7249 | } else { | |
7250 | /* The option is for other outputs */ | |
7251 | limit = &intel_limits_i9xx_sdvo; | |
7252 | } | |
7253 | ||
7254 | if (!crtc_state->clock_set && | |
7255 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7256 | refclk, NULL, &crtc_state->dpll)) { | |
7257 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7258 | return -EINVAL; | |
7259 | } | |
7260 | ||
7261 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7262 | ||
7263 | return 0; | |
7264 | } | |
7265 | ||
70e8aa21 ACO |
7266 | static int pnv_crtc_compute_clock(struct intel_crtc *crtc, |
7267 | struct intel_crtc_state *crtc_state) | |
7268 | { | |
7269 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7270 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7271 | const struct intel_limit *limit; |
70e8aa21 ACO |
7272 | int refclk = 96000; |
7273 | ||
7274 | memset(&crtc_state->dpll_hw_state, 0, | |
7275 | sizeof(crtc_state->dpll_hw_state)); | |
7276 | ||
2d84d2b3 | 7277 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
7278 | if (intel_panel_use_ssc(dev_priv)) { |
7279 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7280 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7281 | } | |
7282 | ||
7283 | limit = &intel_limits_pineview_lvds; | |
7284 | } else { | |
7285 | limit = &intel_limits_pineview_sdvo; | |
7286 | } | |
7287 | ||
7288 | if (!crtc_state->clock_set && | |
7289 | !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7290 | refclk, NULL, &crtc_state->dpll)) { | |
7291 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7292 | return -EINVAL; | |
7293 | } | |
7294 | ||
7295 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7296 | ||
7297 | return 0; | |
7298 | } | |
7299 | ||
190f68c5 ACO |
7300 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7301 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7302 | { |
c7653199 | 7303 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7304 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7305 | const struct intel_limit *limit; |
81c97f52 | 7306 | int refclk = 96000; |
79e53945 | 7307 | |
dd3cd74a ACO |
7308 | memset(&crtc_state->dpll_hw_state, 0, |
7309 | sizeof(crtc_state->dpll_hw_state)); | |
7310 | ||
2d84d2b3 | 7311 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
7312 | if (intel_panel_use_ssc(dev_priv)) { |
7313 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7314 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7315 | } | |
43565a06 | 7316 | |
70e8aa21 ACO |
7317 | limit = &intel_limits_i9xx_lvds; |
7318 | } else { | |
7319 | limit = &intel_limits_i9xx_sdvo; | |
81c97f52 | 7320 | } |
79e53945 | 7321 | |
70e8aa21 ACO |
7322 | if (!crtc_state->clock_set && |
7323 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7324 | refclk, NULL, &crtc_state->dpll)) { | |
7325 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7326 | return -EINVAL; | |
f47709a9 | 7327 | } |
7026d4ac | 7328 | |
81c97f52 | 7329 | i9xx_compute_dpll(crtc, crtc_state, NULL); |
79e53945 | 7330 | |
c8f7a0db | 7331 | return 0; |
f564048e EA |
7332 | } |
7333 | ||
65b3d6a9 ACO |
7334 | static int chv_crtc_compute_clock(struct intel_crtc *crtc, |
7335 | struct intel_crtc_state *crtc_state) | |
7336 | { | |
7337 | int refclk = 100000; | |
1b6f4958 | 7338 | const struct intel_limit *limit = &intel_limits_chv; |
65b3d6a9 ACO |
7339 | |
7340 | memset(&crtc_state->dpll_hw_state, 0, | |
7341 | sizeof(crtc_state->dpll_hw_state)); | |
7342 | ||
65b3d6a9 ACO |
7343 | if (!crtc_state->clock_set && |
7344 | !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7345 | refclk, NULL, &crtc_state->dpll)) { | |
7346 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7347 | return -EINVAL; | |
7348 | } | |
7349 | ||
7350 | chv_compute_dpll(crtc, crtc_state); | |
7351 | ||
7352 | return 0; | |
7353 | } | |
7354 | ||
7355 | static int vlv_crtc_compute_clock(struct intel_crtc *crtc, | |
7356 | struct intel_crtc_state *crtc_state) | |
7357 | { | |
7358 | int refclk = 100000; | |
1b6f4958 | 7359 | const struct intel_limit *limit = &intel_limits_vlv; |
65b3d6a9 ACO |
7360 | |
7361 | memset(&crtc_state->dpll_hw_state, 0, | |
7362 | sizeof(crtc_state->dpll_hw_state)); | |
7363 | ||
65b3d6a9 ACO |
7364 | if (!crtc_state->clock_set && |
7365 | !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7366 | refclk, NULL, &crtc_state->dpll)) { | |
7367 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7368 | return -EINVAL; | |
7369 | } | |
7370 | ||
7371 | vlv_compute_dpll(crtc, crtc_state); | |
7372 | ||
7373 | return 0; | |
7374 | } | |
7375 | ||
2fa2fe9a | 7376 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7377 | struct intel_crtc_state *pipe_config) |
2fa2fe9a | 7378 | { |
6315b5d3 | 7379 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2fa2fe9a DV |
7380 | uint32_t tmp; |
7381 | ||
50a0bc90 TU |
7382 | if (INTEL_GEN(dev_priv) <= 3 && |
7383 | (IS_I830(dev_priv) || !IS_MOBILE(dev_priv))) | |
dc9e7dec VS |
7384 | return; |
7385 | ||
2fa2fe9a | 7386 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7387 | if (!(tmp & PFIT_ENABLE)) |
7388 | return; | |
2fa2fe9a | 7389 | |
06922821 | 7390 | /* Check whether the pfit is attached to our pipe. */ |
6315b5d3 | 7391 | if (INTEL_GEN(dev_priv) < 4) { |
2fa2fe9a DV |
7392 | if (crtc->pipe != PIPE_B) |
7393 | return; | |
2fa2fe9a DV |
7394 | } else { |
7395 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
7396 | return; | |
7397 | } | |
7398 | ||
06922821 | 7399 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a | 7400 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
2fa2fe9a DV |
7401 | } |
7402 | ||
acbec814 | 7403 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7404 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
7405 | { |
7406 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7407 | struct drm_i915_private *dev_priv = to_i915(dev); |
acbec814 | 7408 | int pipe = pipe_config->cpu_transcoder; |
9e2c8475 | 7409 | struct dpll clock; |
acbec814 | 7410 | u32 mdiv; |
662c6ecb | 7411 | int refclk = 100000; |
acbec814 | 7412 | |
b521973b VS |
7413 | /* In case of DSI, DPLL will not be used */ |
7414 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
f573de5a SK |
7415 | return; |
7416 | ||
a580516d | 7417 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 7418 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 7419 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
7420 | |
7421 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
7422 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
7423 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
7424 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
7425 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
7426 | ||
dccbea3b | 7427 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
7428 | } |
7429 | ||
5724dbd1 DL |
7430 | static void |
7431 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
7432 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
7433 | { |
7434 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7435 | struct drm_i915_private *dev_priv = to_i915(dev); |
1ad292b5 JB |
7436 | u32 val, base, offset; |
7437 | int pipe = crtc->pipe, plane = crtc->plane; | |
7438 | int fourcc, pixel_format; | |
6761dd31 | 7439 | unsigned int aligned_height; |
b113d5ee | 7440 | struct drm_framebuffer *fb; |
1b842c89 | 7441 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 7442 | |
42a7b088 DL |
7443 | val = I915_READ(DSPCNTR(plane)); |
7444 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
7445 | return; | |
7446 | ||
d9806c9f | 7447 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 7448 | if (!intel_fb) { |
1ad292b5 JB |
7449 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7450 | return; | |
7451 | } | |
7452 | ||
1b842c89 DL |
7453 | fb = &intel_fb->base; |
7454 | ||
d2e9f5fc VS |
7455 | fb->dev = dev; |
7456 | ||
6315b5d3 | 7457 | if (INTEL_GEN(dev_priv) >= 4) { |
18c5247e | 7458 | if (val & DISPPLANE_TILED) { |
49af449b | 7459 | plane_config->tiling = I915_TILING_X; |
bae781b2 | 7460 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
18c5247e DV |
7461 | } |
7462 | } | |
1ad292b5 JB |
7463 | |
7464 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 7465 | fourcc = i9xx_format_to_fourcc(pixel_format); |
2f3f4763 | 7466 | fb->format = drm_format_info(fourcc); |
1ad292b5 | 7467 | |
6315b5d3 | 7468 | if (INTEL_GEN(dev_priv) >= 4) { |
49af449b | 7469 | if (plane_config->tiling) |
1ad292b5 JB |
7470 | offset = I915_READ(DSPTILEOFF(plane)); |
7471 | else | |
7472 | offset = I915_READ(DSPLINOFF(plane)); | |
7473 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7474 | } else { | |
7475 | base = I915_READ(DSPADDR(plane)); | |
7476 | } | |
7477 | plane_config->base = base; | |
7478 | ||
7479 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
7480 | fb->width = ((val >> 16) & 0xfff) + 1; |
7481 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
7482 | |
7483 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 7484 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 7485 | |
d88c4afd | 7486 | aligned_height = intel_fb_align_height(fb, 0, fb->height); |
1ad292b5 | 7487 | |
f37b5c2b | 7488 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 7489 | |
2844a921 DL |
7490 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
7491 | pipe_name(pipe), plane, fb->width, fb->height, | |
272725c7 | 7492 | fb->format->cpp[0] * 8, base, fb->pitches[0], |
2844a921 | 7493 | plane_config->size); |
1ad292b5 | 7494 | |
2d14030b | 7495 | plane_config->fb = intel_fb; |
1ad292b5 JB |
7496 | } |
7497 | ||
70b23a98 | 7498 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7499 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
7500 | { |
7501 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7502 | struct drm_i915_private *dev_priv = to_i915(dev); |
70b23a98 VS |
7503 | int pipe = pipe_config->cpu_transcoder; |
7504 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9e2c8475 | 7505 | struct dpll clock; |
0d7b6b11 | 7506 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
7507 | int refclk = 100000; |
7508 | ||
b521973b VS |
7509 | /* In case of DSI, DPLL will not be used */ |
7510 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7511 | return; | |
7512 | ||
a580516d | 7513 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
7514 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
7515 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
7516 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
7517 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 7518 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 7519 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
7520 | |
7521 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
7522 | clock.m2 = (pll_dw0 & 0xff) << 22; |
7523 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
7524 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
7525 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
7526 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
7527 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
7528 | ||
dccbea3b | 7529 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
7530 | } |
7531 | ||
0e8ffe1b | 7532 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 7533 | struct intel_crtc_state *pipe_config) |
0e8ffe1b | 7534 | { |
6315b5d3 | 7535 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1729050e | 7536 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 7537 | uint32_t tmp; |
1729050e | 7538 | bool ret; |
0e8ffe1b | 7539 | |
1729050e ID |
7540 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
7541 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 ID |
7542 | return false; |
7543 | ||
e143a21c | 7544 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 7545 | pipe_config->shared_dpll = NULL; |
eccb140b | 7546 | |
1729050e ID |
7547 | ret = false; |
7548 | ||
0e8ffe1b DV |
7549 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7550 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 7551 | goto out; |
0e8ffe1b | 7552 | |
9beb5fea TU |
7553 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
7554 | IS_CHERRYVIEW(dev_priv)) { | |
42571aef VS |
7555 | switch (tmp & PIPECONF_BPC_MASK) { |
7556 | case PIPECONF_6BPC: | |
7557 | pipe_config->pipe_bpp = 18; | |
7558 | break; | |
7559 | case PIPECONF_8BPC: | |
7560 | pipe_config->pipe_bpp = 24; | |
7561 | break; | |
7562 | case PIPECONF_10BPC: | |
7563 | pipe_config->pipe_bpp = 30; | |
7564 | break; | |
7565 | default: | |
7566 | break; | |
7567 | } | |
7568 | } | |
7569 | ||
920a14b2 | 7570 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 7571 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
b5a9fa09 DV |
7572 | pipe_config->limited_color_range = true; |
7573 | ||
6315b5d3 | 7574 | if (INTEL_GEN(dev_priv) < 4) |
282740f7 VS |
7575 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; |
7576 | ||
1bd1bd80 | 7577 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 7578 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 7579 | |
2fa2fe9a DV |
7580 | i9xx_get_pfit_config(crtc, pipe_config); |
7581 | ||
6315b5d3 | 7582 | if (INTEL_GEN(dev_priv) >= 4) { |
c231775c | 7583 | /* No way to read it out on pipes B and C */ |
920a14b2 | 7584 | if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) |
c231775c VS |
7585 | tmp = dev_priv->chv_dpll_md[crtc->pipe]; |
7586 | else | |
7587 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6c49f241 DV |
7588 | pipe_config->pixel_multiplier = |
7589 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
7590 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 7591 | pipe_config->dpll_hw_state.dpll_md = tmp; |
50a0bc90 | 7592 | } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || |
73f67aa8 | 7593 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { |
6c49f241 DV |
7594 | tmp = I915_READ(DPLL(crtc->pipe)); |
7595 | pipe_config->pixel_multiplier = | |
7596 | ((tmp & SDVO_MULTIPLIER_MASK) | |
7597 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
7598 | } else { | |
7599 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
7600 | * port and will be fixed up in the encoder->get_config | |
7601 | * function. */ | |
7602 | pipe_config->pixel_multiplier = 1; | |
7603 | } | |
8bcc2795 | 7604 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
920a14b2 | 7605 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
1c4e0274 VS |
7606 | /* |
7607 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
7608 | * on 830. Filter it out here so that we don't | |
7609 | * report errors due to that. | |
7610 | */ | |
50a0bc90 | 7611 | if (IS_I830(dev_priv)) |
1c4e0274 VS |
7612 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; |
7613 | ||
8bcc2795 DV |
7614 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
7615 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
7616 | } else { |
7617 | /* Mask out read-only status bits. */ | |
7618 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
7619 | DPLL_PORTC_READY_MASK | | |
7620 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 7621 | } |
6c49f241 | 7622 | |
920a14b2 | 7623 | if (IS_CHERRYVIEW(dev_priv)) |
70b23a98 | 7624 | chv_crtc_clock_get(crtc, pipe_config); |
11a914c2 | 7625 | else if (IS_VALLEYVIEW(dev_priv)) |
acbec814 JB |
7626 | vlv_crtc_clock_get(crtc, pipe_config); |
7627 | else | |
7628 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 7629 | |
0f64614d VS |
7630 | /* |
7631 | * Normally the dotclock is filled in by the encoder .get_config() | |
7632 | * but in case the pipe is enabled w/o any ports we need a sane | |
7633 | * default. | |
7634 | */ | |
7635 | pipe_config->base.adjusted_mode.crtc_clock = | |
7636 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
7637 | ||
1729050e ID |
7638 | ret = true; |
7639 | ||
7640 | out: | |
7641 | intel_display_power_put(dev_priv, power_domain); | |
7642 | ||
7643 | return ret; | |
0e8ffe1b DV |
7644 | } |
7645 | ||
c39055b0 | 7646 | static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv) |
13d83a67 | 7647 | { |
13d83a67 | 7648 | struct intel_encoder *encoder; |
1c1a24d2 | 7649 | int i; |
74cfd7ac | 7650 | u32 val, final; |
13d83a67 | 7651 | bool has_lvds = false; |
199e5d79 | 7652 | bool has_cpu_edp = false; |
199e5d79 | 7653 | bool has_panel = false; |
99eb6a01 KP |
7654 | bool has_ck505 = false; |
7655 | bool can_ssc = false; | |
1c1a24d2 | 7656 | bool using_ssc_source = false; |
13d83a67 JB |
7657 | |
7658 | /* We need to take the global config into account */ | |
c39055b0 | 7659 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
199e5d79 KP |
7660 | switch (encoder->type) { |
7661 | case INTEL_OUTPUT_LVDS: | |
7662 | has_panel = true; | |
7663 | has_lvds = true; | |
7664 | break; | |
7665 | case INTEL_OUTPUT_EDP: | |
7666 | has_panel = true; | |
2de6905f | 7667 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
7668 | has_cpu_edp = true; |
7669 | break; | |
6847d71b PZ |
7670 | default: |
7671 | break; | |
13d83a67 JB |
7672 | } |
7673 | } | |
7674 | ||
6e266956 | 7675 | if (HAS_PCH_IBX(dev_priv)) { |
41aa3448 | 7676 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
7677 | can_ssc = has_ck505; |
7678 | } else { | |
7679 | has_ck505 = false; | |
7680 | can_ssc = true; | |
7681 | } | |
7682 | ||
1c1a24d2 L |
7683 | /* Check if any DPLLs are using the SSC source */ |
7684 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
7685 | u32 temp = I915_READ(PCH_DPLL(i)); | |
7686 | ||
7687 | if (!(temp & DPLL_VCO_ENABLE)) | |
7688 | continue; | |
7689 | ||
7690 | if ((temp & PLL_REF_INPUT_MASK) == | |
7691 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
7692 | using_ssc_source = true; | |
7693 | break; | |
7694 | } | |
7695 | } | |
7696 | ||
7697 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n", | |
7698 | has_panel, has_lvds, has_ck505, using_ssc_source); | |
13d83a67 JB |
7699 | |
7700 | /* Ironlake: try to setup display ref clock before DPLL | |
7701 | * enabling. This is only under driver's control after | |
7702 | * PCH B stepping, previous chipset stepping should be | |
7703 | * ignoring this setting. | |
7704 | */ | |
74cfd7ac CW |
7705 | val = I915_READ(PCH_DREF_CONTROL); |
7706 | ||
7707 | /* As we must carefully and slowly disable/enable each source in turn, | |
7708 | * compute the final state we want first and check if we need to | |
7709 | * make any changes at all. | |
7710 | */ | |
7711 | final = val; | |
7712 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
7713 | if (has_ck505) | |
7714 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
7715 | else | |
7716 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
7717 | ||
8c07eb68 | 7718 | final &= ~DREF_SSC_SOURCE_MASK; |
74cfd7ac | 7719 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
8c07eb68 | 7720 | final &= ~DREF_SSC1_ENABLE; |
74cfd7ac CW |
7721 | |
7722 | if (has_panel) { | |
7723 | final |= DREF_SSC_SOURCE_ENABLE; | |
7724 | ||
7725 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7726 | final |= DREF_SSC1_ENABLE; | |
7727 | ||
7728 | if (has_cpu_edp) { | |
7729 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7730 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
7731 | else | |
7732 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
7733 | } else | |
7734 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
1c1a24d2 L |
7735 | } else if (using_ssc_source) { |
7736 | final |= DREF_SSC_SOURCE_ENABLE; | |
7737 | final |= DREF_SSC1_ENABLE; | |
74cfd7ac CW |
7738 | } |
7739 | ||
7740 | if (final == val) | |
7741 | return; | |
7742 | ||
13d83a67 | 7743 | /* Always enable nonspread source */ |
74cfd7ac | 7744 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 7745 | |
99eb6a01 | 7746 | if (has_ck505) |
74cfd7ac | 7747 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 7748 | else |
74cfd7ac | 7749 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 7750 | |
199e5d79 | 7751 | if (has_panel) { |
74cfd7ac CW |
7752 | val &= ~DREF_SSC_SOURCE_MASK; |
7753 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 7754 | |
199e5d79 | 7755 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 7756 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7757 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 7758 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 7759 | } else |
74cfd7ac | 7760 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
7761 | |
7762 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 7763 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7764 | POSTING_READ(PCH_DREF_CONTROL); |
7765 | udelay(200); | |
7766 | ||
74cfd7ac | 7767 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
7768 | |
7769 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 7770 | if (has_cpu_edp) { |
99eb6a01 | 7771 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7772 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 7773 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 7774 | } else |
74cfd7ac | 7775 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 7776 | } else |
74cfd7ac | 7777 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7778 | |
74cfd7ac | 7779 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7780 | POSTING_READ(PCH_DREF_CONTROL); |
7781 | udelay(200); | |
7782 | } else { | |
1c1a24d2 | 7783 | DRM_DEBUG_KMS("Disabling CPU source output\n"); |
199e5d79 | 7784 | |
74cfd7ac | 7785 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
7786 | |
7787 | /* Turn off CPU output */ | |
74cfd7ac | 7788 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7789 | |
74cfd7ac | 7790 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7791 | POSTING_READ(PCH_DREF_CONTROL); |
7792 | udelay(200); | |
7793 | ||
1c1a24d2 L |
7794 | if (!using_ssc_source) { |
7795 | DRM_DEBUG_KMS("Disabling SSC source\n"); | |
199e5d79 | 7796 | |
1c1a24d2 L |
7797 | /* Turn off the SSC source */ |
7798 | val &= ~DREF_SSC_SOURCE_MASK; | |
7799 | val |= DREF_SSC_SOURCE_DISABLE; | |
f165d283 | 7800 | |
1c1a24d2 L |
7801 | /* Turn off SSC1 */ |
7802 | val &= ~DREF_SSC1_ENABLE; | |
7803 | ||
7804 | I915_WRITE(PCH_DREF_CONTROL, val); | |
7805 | POSTING_READ(PCH_DREF_CONTROL); | |
7806 | udelay(200); | |
7807 | } | |
13d83a67 | 7808 | } |
74cfd7ac CW |
7809 | |
7810 | BUG_ON(val != final); | |
13d83a67 JB |
7811 | } |
7812 | ||
f31f2d55 | 7813 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 7814 | { |
f31f2d55 | 7815 | uint32_t tmp; |
dde86e2d | 7816 | |
0ff066a9 PZ |
7817 | tmp = I915_READ(SOUTH_CHICKEN2); |
7818 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
7819 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7820 | |
cf3598c2 ID |
7821 | if (wait_for_us(I915_READ(SOUTH_CHICKEN2) & |
7822 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
0ff066a9 | 7823 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
dde86e2d | 7824 | |
0ff066a9 PZ |
7825 | tmp = I915_READ(SOUTH_CHICKEN2); |
7826 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
7827 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7828 | |
cf3598c2 ID |
7829 | if (wait_for_us((I915_READ(SOUTH_CHICKEN2) & |
7830 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
0ff066a9 | 7831 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
f31f2d55 PZ |
7832 | } |
7833 | ||
7834 | /* WaMPhyProgramming:hsw */ | |
7835 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
7836 | { | |
7837 | uint32_t tmp; | |
dde86e2d PZ |
7838 | |
7839 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
7840 | tmp &= ~(0xFF << 24); | |
7841 | tmp |= (0x12 << 24); | |
7842 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
7843 | ||
dde86e2d PZ |
7844 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
7845 | tmp |= (1 << 11); | |
7846 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
7847 | ||
7848 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
7849 | tmp |= (1 << 11); | |
7850 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
7851 | ||
dde86e2d PZ |
7852 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
7853 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7854 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
7855 | ||
7856 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
7857 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7858 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
7859 | ||
0ff066a9 PZ |
7860 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
7861 | tmp &= ~(7 << 13); | |
7862 | tmp |= (5 << 13); | |
7863 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 7864 | |
0ff066a9 PZ |
7865 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
7866 | tmp &= ~(7 << 13); | |
7867 | tmp |= (5 << 13); | |
7868 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
7869 | |
7870 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
7871 | tmp &= ~0xFF; | |
7872 | tmp |= 0x1C; | |
7873 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
7874 | ||
7875 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
7876 | tmp &= ~0xFF; | |
7877 | tmp |= 0x1C; | |
7878 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
7879 | ||
7880 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
7881 | tmp &= ~(0xFF << 16); | |
7882 | tmp |= (0x1C << 16); | |
7883 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
7884 | ||
7885 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
7886 | tmp &= ~(0xFF << 16); | |
7887 | tmp |= (0x1C << 16); | |
7888 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
7889 | ||
0ff066a9 PZ |
7890 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
7891 | tmp |= (1 << 27); | |
7892 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 7893 | |
0ff066a9 PZ |
7894 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
7895 | tmp |= (1 << 27); | |
7896 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 7897 | |
0ff066a9 PZ |
7898 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
7899 | tmp &= ~(0xF << 28); | |
7900 | tmp |= (4 << 28); | |
7901 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 7902 | |
0ff066a9 PZ |
7903 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
7904 | tmp &= ~(0xF << 28); | |
7905 | tmp |= (4 << 28); | |
7906 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
7907 | } |
7908 | ||
2fa86a1f PZ |
7909 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
7910 | * Programming" based on the parameters passed: | |
7911 | * - Sequence to enable CLKOUT_DP | |
7912 | * - Sequence to enable CLKOUT_DP without spread | |
7913 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
7914 | */ | |
c39055b0 ACO |
7915 | static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv, |
7916 | bool with_spread, bool with_fdi) | |
f31f2d55 | 7917 | { |
2fa86a1f PZ |
7918 | uint32_t reg, tmp; |
7919 | ||
7920 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
7921 | with_spread = true; | |
4f8036a2 TU |
7922 | if (WARN(HAS_PCH_LPT_LP(dev_priv) && |
7923 | with_fdi, "LP PCH doesn't have FDI\n")) | |
2fa86a1f | 7924 | with_fdi = false; |
f31f2d55 | 7925 | |
a580516d | 7926 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
7927 | |
7928 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7929 | tmp &= ~SBI_SSCCTL_DISABLE; | |
7930 | tmp |= SBI_SSCCTL_PATHALT; | |
7931 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7932 | ||
7933 | udelay(24); | |
7934 | ||
2fa86a1f PZ |
7935 | if (with_spread) { |
7936 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7937 | tmp &= ~SBI_SSCCTL_PATHALT; | |
7938 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 7939 | |
2fa86a1f PZ |
7940 | if (with_fdi) { |
7941 | lpt_reset_fdi_mphy(dev_priv); | |
7942 | lpt_program_fdi_mphy(dev_priv); | |
7943 | } | |
7944 | } | |
dde86e2d | 7945 | |
4f8036a2 | 7946 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
7947 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
7948 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7949 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 7950 | |
a580516d | 7951 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
7952 | } |
7953 | ||
47701c3b | 7954 | /* Sequence to disable CLKOUT_DP */ |
c39055b0 | 7955 | static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv) |
47701c3b | 7956 | { |
47701c3b PZ |
7957 | uint32_t reg, tmp; |
7958 | ||
a580516d | 7959 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 7960 | |
4f8036a2 | 7961 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
7962 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
7963 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7964 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
7965 | ||
7966 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7967 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
7968 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
7969 | tmp |= SBI_SSCCTL_PATHALT; | |
7970 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7971 | udelay(32); | |
7972 | } | |
7973 | tmp |= SBI_SSCCTL_DISABLE; | |
7974 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7975 | } | |
7976 | ||
a580516d | 7977 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
7978 | } |
7979 | ||
f7be2c21 VS |
7980 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
7981 | ||
7982 | static const uint16_t sscdivintphase[] = { | |
7983 | [BEND_IDX( 50)] = 0x3B23, | |
7984 | [BEND_IDX( 45)] = 0x3B23, | |
7985 | [BEND_IDX( 40)] = 0x3C23, | |
7986 | [BEND_IDX( 35)] = 0x3C23, | |
7987 | [BEND_IDX( 30)] = 0x3D23, | |
7988 | [BEND_IDX( 25)] = 0x3D23, | |
7989 | [BEND_IDX( 20)] = 0x3E23, | |
7990 | [BEND_IDX( 15)] = 0x3E23, | |
7991 | [BEND_IDX( 10)] = 0x3F23, | |
7992 | [BEND_IDX( 5)] = 0x3F23, | |
7993 | [BEND_IDX( 0)] = 0x0025, | |
7994 | [BEND_IDX( -5)] = 0x0025, | |
7995 | [BEND_IDX(-10)] = 0x0125, | |
7996 | [BEND_IDX(-15)] = 0x0125, | |
7997 | [BEND_IDX(-20)] = 0x0225, | |
7998 | [BEND_IDX(-25)] = 0x0225, | |
7999 | [BEND_IDX(-30)] = 0x0325, | |
8000 | [BEND_IDX(-35)] = 0x0325, | |
8001 | [BEND_IDX(-40)] = 0x0425, | |
8002 | [BEND_IDX(-45)] = 0x0425, | |
8003 | [BEND_IDX(-50)] = 0x0525, | |
8004 | }; | |
8005 | ||
8006 | /* | |
8007 | * Bend CLKOUT_DP | |
8008 | * steps -50 to 50 inclusive, in steps of 5 | |
8009 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
8010 | * change in clock period = -(steps / 10) * 5.787 ps | |
8011 | */ | |
8012 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
8013 | { | |
8014 | uint32_t tmp; | |
8015 | int idx = BEND_IDX(steps); | |
8016 | ||
8017 | if (WARN_ON(steps % 5 != 0)) | |
8018 | return; | |
8019 | ||
8020 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
8021 | return; | |
8022 | ||
8023 | mutex_lock(&dev_priv->sb_lock); | |
8024 | ||
8025 | if (steps % 10 != 0) | |
8026 | tmp = 0xAAAAAAAB; | |
8027 | else | |
8028 | tmp = 0x00000000; | |
8029 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
8030 | ||
8031 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
8032 | tmp &= 0xffff0000; | |
8033 | tmp |= sscdivintphase[idx]; | |
8034 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
8035 | ||
8036 | mutex_unlock(&dev_priv->sb_lock); | |
8037 | } | |
8038 | ||
8039 | #undef BEND_IDX | |
8040 | ||
c39055b0 | 8041 | static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv) |
bf8fa3d3 | 8042 | { |
bf8fa3d3 PZ |
8043 | struct intel_encoder *encoder; |
8044 | bool has_vga = false; | |
8045 | ||
c39055b0 | 8046 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
bf8fa3d3 PZ |
8047 | switch (encoder->type) { |
8048 | case INTEL_OUTPUT_ANALOG: | |
8049 | has_vga = true; | |
8050 | break; | |
6847d71b PZ |
8051 | default: |
8052 | break; | |
bf8fa3d3 PZ |
8053 | } |
8054 | } | |
8055 | ||
f7be2c21 | 8056 | if (has_vga) { |
c39055b0 ACO |
8057 | lpt_bend_clkout_dp(dev_priv, 0); |
8058 | lpt_enable_clkout_dp(dev_priv, true, true); | |
f7be2c21 | 8059 | } else { |
c39055b0 | 8060 | lpt_disable_clkout_dp(dev_priv); |
f7be2c21 | 8061 | } |
bf8fa3d3 PZ |
8062 | } |
8063 | ||
dde86e2d PZ |
8064 | /* |
8065 | * Initialize reference clocks when the driver loads | |
8066 | */ | |
c39055b0 | 8067 | void intel_init_pch_refclk(struct drm_i915_private *dev_priv) |
dde86e2d | 8068 | { |
6e266956 | 8069 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) |
c39055b0 | 8070 | ironlake_init_pch_refclk(dev_priv); |
6e266956 | 8071 | else if (HAS_PCH_LPT(dev_priv)) |
c39055b0 | 8072 | lpt_init_pch_refclk(dev_priv); |
dde86e2d PZ |
8073 | } |
8074 | ||
6ff93609 | 8075 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8076 | { |
fac5e23e | 8077 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
79e53945 JB |
8078 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8079 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8080 | uint32_t val; |
8081 | ||
78114071 | 8082 | val = 0; |
c8203565 | 8083 | |
6e3c9717 | 8084 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8085 | case 18: |
dfd07d72 | 8086 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8087 | break; |
8088 | case 24: | |
dfd07d72 | 8089 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8090 | break; |
8091 | case 30: | |
dfd07d72 | 8092 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8093 | break; |
8094 | case 36: | |
dfd07d72 | 8095 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8096 | break; |
8097 | default: | |
cc769b62 PZ |
8098 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8099 | BUG(); | |
c8203565 PZ |
8100 | } |
8101 | ||
6e3c9717 | 8102 | if (intel_crtc->config->dither) |
c8203565 PZ |
8103 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8104 | ||
6e3c9717 | 8105 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8106 | val |= PIPECONF_INTERLACED_ILK; |
8107 | else | |
8108 | val |= PIPECONF_PROGRESSIVE; | |
8109 | ||
6e3c9717 | 8110 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8111 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8112 | |
c8203565 PZ |
8113 | I915_WRITE(PIPECONF(pipe), val); |
8114 | POSTING_READ(PIPECONF(pipe)); | |
8115 | } | |
8116 | ||
6ff93609 | 8117 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8118 | { |
fac5e23e | 8119 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee2b0b38 | 8120 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 8121 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
391bf048 | 8122 | u32 val = 0; |
ee2b0b38 | 8123 | |
391bf048 | 8124 | if (IS_HASWELL(dev_priv) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8125 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8126 | ||
6e3c9717 | 8127 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8128 | val |= PIPECONF_INTERLACED_ILK; |
8129 | else | |
8130 | val |= PIPECONF_PROGRESSIVE; | |
8131 | ||
702e7a56 PZ |
8132 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8133 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
391bf048 JN |
8134 | } |
8135 | ||
391bf048 JN |
8136 | static void haswell_set_pipemisc(struct drm_crtc *crtc) |
8137 | { | |
fac5e23e | 8138 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
391bf048 | 8139 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b22ca995 | 8140 | struct intel_crtc_state *config = intel_crtc->config; |
756f85cf | 8141 | |
391bf048 JN |
8142 | if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { |
8143 | u32 val = 0; | |
756f85cf | 8144 | |
6e3c9717 | 8145 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8146 | case 18: |
8147 | val |= PIPEMISC_DITHER_6_BPC; | |
8148 | break; | |
8149 | case 24: | |
8150 | val |= PIPEMISC_DITHER_8_BPC; | |
8151 | break; | |
8152 | case 30: | |
8153 | val |= PIPEMISC_DITHER_10_BPC; | |
8154 | break; | |
8155 | case 36: | |
8156 | val |= PIPEMISC_DITHER_12_BPC; | |
8157 | break; | |
8158 | default: | |
8159 | /* Case prevented by pipe_config_set_bpp. */ | |
8160 | BUG(); | |
8161 | } | |
8162 | ||
6e3c9717 | 8163 | if (intel_crtc->config->dither) |
756f85cf PZ |
8164 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8165 | ||
b22ca995 SS |
8166 | if (config->ycbcr420) { |
8167 | val |= PIPEMISC_OUTPUT_COLORSPACE_YUV | | |
8168 | PIPEMISC_YUV420_ENABLE | | |
8169 | PIPEMISC_YUV420_MODE_FULL_BLEND; | |
8170 | } | |
8171 | ||
391bf048 | 8172 | I915_WRITE(PIPEMISC(intel_crtc->pipe), val); |
756f85cf | 8173 | } |
ee2b0b38 PZ |
8174 | } |
8175 | ||
d4b1931c PZ |
8176 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8177 | { | |
8178 | /* | |
8179 | * Account for spread spectrum to avoid | |
8180 | * oversubscribing the link. Max center spread | |
8181 | * is 2.5%; use 5% for safety's sake. | |
8182 | */ | |
8183 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8184 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8185 | } |
8186 | ||
7429e9d4 | 8187 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8188 | { |
7429e9d4 | 8189 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8190 | } |
8191 | ||
b75ca6f6 ACO |
8192 | static void ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
8193 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 8194 | struct dpll *reduced_clock) |
79e53945 | 8195 | { |
de13a2e3 | 8196 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 | 8197 | struct drm_device *dev = crtc->dev; |
fac5e23e | 8198 | struct drm_i915_private *dev_priv = to_i915(dev); |
b75ca6f6 | 8199 | u32 dpll, fp, fp2; |
3d6e9ee0 | 8200 | int factor; |
79e53945 | 8201 | |
c1858123 | 8202 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 | 8203 | factor = 21; |
3d6e9ee0 | 8204 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
8febb297 | 8205 | if ((intel_panel_use_ssc(dev_priv) && |
e91e941b | 8206 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
6e266956 | 8207 | (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8208 | factor = 25; |
190f68c5 | 8209 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8210 | factor = 20; |
c1858123 | 8211 | |
b75ca6f6 ACO |
8212 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
8213 | ||
190f68c5 | 8214 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
b75ca6f6 ACO |
8215 | fp |= FP_CB_TUNE; |
8216 | ||
8217 | if (reduced_clock) { | |
8218 | fp2 = i9xx_dpll_compute_fp(reduced_clock); | |
2c07245f | 8219 | |
b75ca6f6 ACO |
8220 | if (reduced_clock->m < factor * reduced_clock->n) |
8221 | fp2 |= FP_CB_TUNE; | |
8222 | } else { | |
8223 | fp2 = fp; | |
8224 | } | |
9a7c7890 | 8225 | |
5eddb70b | 8226 | dpll = 0; |
2c07245f | 8227 | |
3d6e9ee0 | 8228 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a07d6787 EA |
8229 | dpll |= DPLLB_MODE_LVDS; |
8230 | else | |
8231 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8232 | |
190f68c5 | 8233 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8234 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f | 8235 | |
3d6e9ee0 VS |
8236 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
8237 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 8238 | dpll |= DPLL_SDVO_HIGH_SPEED; |
3d6e9ee0 | 8239 | |
37a5650b | 8240 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 8241 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8242 | |
7d7f8633 VS |
8243 | /* |
8244 | * The high speed IO clock is only really required for | |
8245 | * SDVO/HDMI/DP, but we also enable it for CRT to make it | |
8246 | * possible to share the DPLL between CRT and HDMI. Enabling | |
8247 | * the clock needlessly does no real harm, except use up a | |
8248 | * bit of power potentially. | |
8249 | * | |
8250 | * We'll limit this to IVB with 3 pipes, since it has only two | |
8251 | * DPLLs and so DPLL sharing is the only way to get three pipes | |
8252 | * driving PCH ports at the same time. On SNB we could do this, | |
8253 | * and potentially avoid enabling the second DPLL, but it's not | |
8254 | * clear if it''s a win or loss power wise. No point in doing | |
8255 | * this on ILK at all since it has a fixed DPLL<->pipe mapping. | |
8256 | */ | |
8257 | if (INTEL_INFO(dev_priv)->num_pipes == 3 && | |
8258 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) | |
8259 | dpll |= DPLL_SDVO_HIGH_SPEED; | |
8260 | ||
a07d6787 | 8261 | /* compute bitmask from p1 value */ |
190f68c5 | 8262 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8263 | /* also FPA1 */ |
190f68c5 | 8264 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8265 | |
190f68c5 | 8266 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8267 | case 5: |
8268 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8269 | break; | |
8270 | case 7: | |
8271 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8272 | break; | |
8273 | case 10: | |
8274 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8275 | break; | |
8276 | case 14: | |
8277 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8278 | break; | |
79e53945 JB |
8279 | } |
8280 | ||
3d6e9ee0 VS |
8281 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
8282 | intel_panel_use_ssc(dev_priv)) | |
43565a06 | 8283 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8284 | else |
8285 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8286 | ||
b75ca6f6 ACO |
8287 | dpll |= DPLL_VCO_ENABLE; |
8288 | ||
8289 | crtc_state->dpll_hw_state.dpll = dpll; | |
8290 | crtc_state->dpll_hw_state.fp0 = fp; | |
8291 | crtc_state->dpll_hw_state.fp1 = fp2; | |
de13a2e3 PZ |
8292 | } |
8293 | ||
190f68c5 ACO |
8294 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8295 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8296 | { |
997c030c | 8297 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8298 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8299 | const struct intel_limit *limit; |
997c030c | 8300 | int refclk = 120000; |
de13a2e3 | 8301 | |
dd3cd74a ACO |
8302 | memset(&crtc_state->dpll_hw_state, 0, |
8303 | sizeof(crtc_state->dpll_hw_state)); | |
8304 | ||
ded220e2 ACO |
8305 | crtc->lowfreq_avail = false; |
8306 | ||
8307 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ | |
8308 | if (!crtc_state->has_pch_encoder) | |
8309 | return 0; | |
79e53945 | 8310 | |
2d84d2b3 | 8311 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
997c030c ACO |
8312 | if (intel_panel_use_ssc(dev_priv)) { |
8313 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", | |
8314 | dev_priv->vbt.lvds_ssc_freq); | |
8315 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8316 | } | |
8317 | ||
8318 | if (intel_is_dual_link_lvds(dev)) { | |
8319 | if (refclk == 100000) | |
8320 | limit = &intel_limits_ironlake_dual_lvds_100m; | |
8321 | else | |
8322 | limit = &intel_limits_ironlake_dual_lvds; | |
8323 | } else { | |
8324 | if (refclk == 100000) | |
8325 | limit = &intel_limits_ironlake_single_lvds_100m; | |
8326 | else | |
8327 | limit = &intel_limits_ironlake_single_lvds; | |
8328 | } | |
8329 | } else { | |
8330 | limit = &intel_limits_ironlake_dac; | |
8331 | } | |
8332 | ||
364ee29d | 8333 | if (!crtc_state->clock_set && |
997c030c ACO |
8334 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
8335 | refclk, NULL, &crtc_state->dpll)) { | |
364ee29d ACO |
8336 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8337 | return -EINVAL; | |
f47709a9 | 8338 | } |
79e53945 | 8339 | |
cbaa3315 | 8340 | ironlake_compute_dpll(crtc, crtc_state, NULL); |
66e985c0 | 8341 | |
efd38b68 | 8342 | if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) { |
ded220e2 ACO |
8343 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
8344 | pipe_name(crtc->pipe)); | |
8345 | return -EINVAL; | |
3fb37703 | 8346 | } |
79e53945 | 8347 | |
c8f7a0db | 8348 | return 0; |
79e53945 JB |
8349 | } |
8350 | ||
eb14cb74 VS |
8351 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
8352 | struct intel_link_m_n *m_n) | |
8353 | { | |
8354 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8355 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb14cb74 VS |
8356 | enum pipe pipe = crtc->pipe; |
8357 | ||
8358 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
8359 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
8360 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8361 | & ~TU_SIZE_MASK; | |
8362 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
8363 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8364 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8365 | } | |
8366 | ||
8367 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
8368 | enum transcoder transcoder, | |
b95af8be VK |
8369 | struct intel_link_m_n *m_n, |
8370 | struct intel_link_m_n *m2_n2) | |
72419203 | 8371 | { |
6315b5d3 | 8372 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
eb14cb74 | 8373 | enum pipe pipe = crtc->pipe; |
72419203 | 8374 | |
6315b5d3 | 8375 | if (INTEL_GEN(dev_priv) >= 5) { |
eb14cb74 VS |
8376 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); |
8377 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
8378 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
8379 | & ~TU_SIZE_MASK; | |
8380 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
8381 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
8382 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
8383 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
8384 | * gen < 8) and if DRRS is supported (to make sure the | |
8385 | * registers are not unnecessarily read). | |
8386 | */ | |
6315b5d3 | 8387 | if (m2_n2 && INTEL_GEN(dev_priv) < 8 && |
6e3c9717 | 8388 | crtc->config->has_drrs) { |
b95af8be VK |
8389 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
8390 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
8391 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
8392 | & ~TU_SIZE_MASK; | |
8393 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
8394 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
8395 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8396 | } | |
eb14cb74 VS |
8397 | } else { |
8398 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
8399 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
8400 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8401 | & ~TU_SIZE_MASK; | |
8402 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
8403 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8404 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8405 | } | |
8406 | } | |
8407 | ||
8408 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 8409 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 8410 | { |
681a8504 | 8411 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
8412 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
8413 | else | |
8414 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
8415 | &pipe_config->dp_m_n, |
8416 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 8417 | } |
72419203 | 8418 | |
eb14cb74 | 8419 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 8420 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
8421 | { |
8422 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 8423 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
8424 | } |
8425 | ||
bd2e244f | 8426 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8427 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
8428 | { |
8429 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8430 | struct drm_i915_private *dev_priv = to_i915(dev); |
a1b2278e CK |
8431 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
8432 | uint32_t ps_ctrl = 0; | |
8433 | int id = -1; | |
8434 | int i; | |
bd2e244f | 8435 | |
a1b2278e CK |
8436 | /* find scaler attached to this pipe */ |
8437 | for (i = 0; i < crtc->num_scalers; i++) { | |
8438 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
8439 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
8440 | id = i; | |
8441 | pipe_config->pch_pfit.enabled = true; | |
8442 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
8443 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
8444 | break; | |
8445 | } | |
8446 | } | |
bd2e244f | 8447 | |
a1b2278e CK |
8448 | scaler_state->scaler_id = id; |
8449 | if (id >= 0) { | |
8450 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
8451 | } else { | |
8452 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
8453 | } |
8454 | } | |
8455 | ||
5724dbd1 DL |
8456 | static void |
8457 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
8458 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
8459 | { |
8460 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8461 | struct drm_i915_private *dev_priv = to_i915(dev); |
40f46283 | 8462 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
8463 | int pipe = crtc->pipe; |
8464 | int fourcc, pixel_format; | |
6761dd31 | 8465 | unsigned int aligned_height; |
bc8d7dff | 8466 | struct drm_framebuffer *fb; |
1b842c89 | 8467 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 8468 | |
d9806c9f | 8469 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8470 | if (!intel_fb) { |
bc8d7dff DL |
8471 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8472 | return; | |
8473 | } | |
8474 | ||
1b842c89 DL |
8475 | fb = &intel_fb->base; |
8476 | ||
d2e9f5fc VS |
8477 | fb->dev = dev; |
8478 | ||
bc8d7dff | 8479 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
8480 | if (!(val & PLANE_CTL_ENABLE)) |
8481 | goto error; | |
8482 | ||
bc8d7dff DL |
8483 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
8484 | fourcc = skl_format_to_fourcc(pixel_format, | |
8485 | val & PLANE_CTL_ORDER_RGBX, | |
8486 | val & PLANE_CTL_ALPHA_MASK); | |
2f3f4763 | 8487 | fb->format = drm_format_info(fourcc); |
bc8d7dff | 8488 | |
40f46283 DL |
8489 | tiling = val & PLANE_CTL_TILED_MASK; |
8490 | switch (tiling) { | |
8491 | case PLANE_CTL_TILED_LINEAR: | |
2f075565 | 8492 | fb->modifier = DRM_FORMAT_MOD_LINEAR; |
40f46283 DL |
8493 | break; |
8494 | case PLANE_CTL_TILED_X: | |
8495 | plane_config->tiling = I915_TILING_X; | |
bae781b2 | 8496 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
40f46283 DL |
8497 | break; |
8498 | case PLANE_CTL_TILED_Y: | |
2e2adb05 VS |
8499 | if (val & PLANE_CTL_DECOMPRESSION_ENABLE) |
8500 | fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS; | |
8501 | else | |
8502 | fb->modifier = I915_FORMAT_MOD_Y_TILED; | |
40f46283 DL |
8503 | break; |
8504 | case PLANE_CTL_TILED_YF: | |
2e2adb05 VS |
8505 | if (val & PLANE_CTL_DECOMPRESSION_ENABLE) |
8506 | fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; | |
8507 | else | |
8508 | fb->modifier = I915_FORMAT_MOD_Yf_TILED; | |
40f46283 DL |
8509 | break; |
8510 | default: | |
8511 | MISSING_CASE(tiling); | |
8512 | goto error; | |
8513 | } | |
8514 | ||
bc8d7dff DL |
8515 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
8516 | plane_config->base = base; | |
8517 | ||
8518 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
8519 | ||
8520 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
8521 | fb->height = ((val >> 16) & 0xfff) + 1; | |
8522 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
8523 | ||
8524 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
d88c4afd | 8525 | stride_mult = intel_fb_stride_alignment(fb, 0); |
bc8d7dff DL |
8526 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
8527 | ||
d88c4afd | 8528 | aligned_height = intel_fb_align_height(fb, 0, fb->height); |
bc8d7dff | 8529 | |
f37b5c2b | 8530 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
8531 | |
8532 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
8533 | pipe_name(pipe), fb->width, fb->height, | |
272725c7 | 8534 | fb->format->cpp[0] * 8, base, fb->pitches[0], |
bc8d7dff DL |
8535 | plane_config->size); |
8536 | ||
2d14030b | 8537 | plane_config->fb = intel_fb; |
bc8d7dff DL |
8538 | return; |
8539 | ||
8540 | error: | |
d1a3a036 | 8541 | kfree(intel_fb); |
bc8d7dff DL |
8542 | } |
8543 | ||
2fa2fe9a | 8544 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8545 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8546 | { |
8547 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8548 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa2fe9a DV |
8549 | uint32_t tmp; |
8550 | ||
8551 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
8552 | ||
8553 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 8554 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
8555 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
8556 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
8557 | |
8558 | /* We currently do not free assignements of panel fitters on | |
8559 | * ivb/hsw (since we don't use the higher upscaling modes which | |
8560 | * differentiates them) so just WARN about this case for now. */ | |
5db94019 | 8561 | if (IS_GEN7(dev_priv)) { |
cb8b2a30 DV |
8562 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != |
8563 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
8564 | } | |
2fa2fe9a | 8565 | } |
79e53945 JB |
8566 | } |
8567 | ||
5724dbd1 DL |
8568 | static void |
8569 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
8570 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
8571 | { |
8572 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8573 | struct drm_i915_private *dev_priv = to_i915(dev); |
4c6baa59 | 8574 | u32 val, base, offset; |
aeee5a49 | 8575 | int pipe = crtc->pipe; |
4c6baa59 | 8576 | int fourcc, pixel_format; |
6761dd31 | 8577 | unsigned int aligned_height; |
b113d5ee | 8578 | struct drm_framebuffer *fb; |
1b842c89 | 8579 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 8580 | |
42a7b088 DL |
8581 | val = I915_READ(DSPCNTR(pipe)); |
8582 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8583 | return; | |
8584 | ||
d9806c9f | 8585 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8586 | if (!intel_fb) { |
4c6baa59 JB |
8587 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8588 | return; | |
8589 | } | |
8590 | ||
1b842c89 DL |
8591 | fb = &intel_fb->base; |
8592 | ||
d2e9f5fc VS |
8593 | fb->dev = dev; |
8594 | ||
6315b5d3 | 8595 | if (INTEL_GEN(dev_priv) >= 4) { |
18c5247e | 8596 | if (val & DISPPLANE_TILED) { |
49af449b | 8597 | plane_config->tiling = I915_TILING_X; |
bae781b2 | 8598 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
18c5247e DV |
8599 | } |
8600 | } | |
4c6baa59 JB |
8601 | |
8602 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8603 | fourcc = i9xx_format_to_fourcc(pixel_format); |
2f3f4763 | 8604 | fb->format = drm_format_info(fourcc); |
4c6baa59 | 8605 | |
aeee5a49 | 8606 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
8652744b | 8607 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
aeee5a49 | 8608 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 8609 | } else { |
49af449b | 8610 | if (plane_config->tiling) |
aeee5a49 | 8611 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 8612 | else |
aeee5a49 | 8613 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
8614 | } |
8615 | plane_config->base = base; | |
8616 | ||
8617 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8618 | fb->width = ((val >> 16) & 0xfff) + 1; |
8619 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
8620 | |
8621 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8622 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 8623 | |
d88c4afd | 8624 | aligned_height = intel_fb_align_height(fb, 0, fb->height); |
4c6baa59 | 8625 | |
f37b5c2b | 8626 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 8627 | |
2844a921 DL |
8628 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8629 | pipe_name(pipe), fb->width, fb->height, | |
272725c7 | 8630 | fb->format->cpp[0] * 8, base, fb->pitches[0], |
2844a921 | 8631 | plane_config->size); |
b113d5ee | 8632 | |
2d14030b | 8633 | plane_config->fb = intel_fb; |
4c6baa59 JB |
8634 | } |
8635 | ||
0e8ffe1b | 8636 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8637 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8638 | { |
8639 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8640 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e | 8641 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 8642 | uint32_t tmp; |
1729050e | 8643 | bool ret; |
0e8ffe1b | 8644 | |
1729050e ID |
8645 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8646 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
930e8c9e PZ |
8647 | return false; |
8648 | ||
e143a21c | 8649 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 8650 | pipe_config->shared_dpll = NULL; |
eccb140b | 8651 | |
1729050e | 8652 | ret = false; |
0e8ffe1b DV |
8653 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8654 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 8655 | goto out; |
0e8ffe1b | 8656 | |
42571aef VS |
8657 | switch (tmp & PIPECONF_BPC_MASK) { |
8658 | case PIPECONF_6BPC: | |
8659 | pipe_config->pipe_bpp = 18; | |
8660 | break; | |
8661 | case PIPECONF_8BPC: | |
8662 | pipe_config->pipe_bpp = 24; | |
8663 | break; | |
8664 | case PIPECONF_10BPC: | |
8665 | pipe_config->pipe_bpp = 30; | |
8666 | break; | |
8667 | case PIPECONF_12BPC: | |
8668 | pipe_config->pipe_bpp = 36; | |
8669 | break; | |
8670 | default: | |
8671 | break; | |
8672 | } | |
8673 | ||
b5a9fa09 DV |
8674 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
8675 | pipe_config->limited_color_range = true; | |
8676 | ||
ab9412ba | 8677 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 | 8678 | struct intel_shared_dpll *pll; |
8106ddbd | 8679 | enum intel_dpll_id pll_id; |
66e985c0 | 8680 | |
88adfff1 DV |
8681 | pipe_config->has_pch_encoder = true; |
8682 | ||
627eb5a3 DV |
8683 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
8684 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
8685 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
8686 | |
8687 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 8688 | |
2d1fe073 | 8689 | if (HAS_PCH_IBX(dev_priv)) { |
d9a7bc67 ID |
8690 | /* |
8691 | * The pipe->pch transcoder and pch transcoder->pll | |
8692 | * mapping is fixed. | |
8693 | */ | |
8106ddbd | 8694 | pll_id = (enum intel_dpll_id) crtc->pipe; |
c0d43d62 DV |
8695 | } else { |
8696 | tmp = I915_READ(PCH_DPLL_SEL); | |
8697 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8106ddbd | 8698 | pll_id = DPLL_ID_PCH_PLL_B; |
c0d43d62 | 8699 | else |
8106ddbd | 8700 | pll_id= DPLL_ID_PCH_PLL_A; |
c0d43d62 | 8701 | } |
66e985c0 | 8702 | |
8106ddbd ACO |
8703 | pipe_config->shared_dpll = |
8704 | intel_get_shared_dpll_by_id(dev_priv, pll_id); | |
8705 | pll = pipe_config->shared_dpll; | |
66e985c0 | 8706 | |
2edd6443 ACO |
8707 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
8708 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
8709 | |
8710 | tmp = pipe_config->dpll_hw_state.dpll; | |
8711 | pipe_config->pixel_multiplier = | |
8712 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
8713 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
8714 | |
8715 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
8716 | } else { |
8717 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
8718 | } |
8719 | ||
1bd1bd80 | 8720 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 8721 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 8722 | |
2fa2fe9a DV |
8723 | ironlake_get_pfit_config(crtc, pipe_config); |
8724 | ||
1729050e ID |
8725 | ret = true; |
8726 | ||
8727 | out: | |
8728 | intel_display_power_put(dev_priv, power_domain); | |
8729 | ||
8730 | return ret; | |
0e8ffe1b DV |
8731 | } |
8732 | ||
be256dc7 PZ |
8733 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
8734 | { | |
91c8a326 | 8735 | struct drm_device *dev = &dev_priv->drm; |
be256dc7 | 8736 | struct intel_crtc *crtc; |
be256dc7 | 8737 | |
d3fcc808 | 8738 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 8739 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
8740 | pipe_name(crtc->pipe)); |
8741 | ||
e2c719b7 RC |
8742 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
8743 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
8744 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
8745 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
44cb734c | 8746 | I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n"); |
e2c719b7 | 8747 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
be256dc7 | 8748 | "CPU PWM1 enabled\n"); |
772c2a51 | 8749 | if (IS_HASWELL(dev_priv)) |
e2c719b7 | 8750 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 8751 | "CPU PWM2 enabled\n"); |
e2c719b7 | 8752 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 8753 | "PCH PWM1 enabled\n"); |
e2c719b7 | 8754 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 8755 | "Utility pin enabled\n"); |
e2c719b7 | 8756 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 8757 | |
9926ada1 PZ |
8758 | /* |
8759 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
8760 | * interrupts remain enabled. We used to check for that, but since it's | |
8761 | * gen-specific and since we only disable LCPLL after we fully disable | |
8762 | * the interrupts, the check below should be enough. | |
8763 | */ | |
e2c719b7 | 8764 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
8765 | } |
8766 | ||
9ccd5aeb PZ |
8767 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
8768 | { | |
772c2a51 | 8769 | if (IS_HASWELL(dev_priv)) |
9ccd5aeb PZ |
8770 | return I915_READ(D_COMP_HSW); |
8771 | else | |
8772 | return I915_READ(D_COMP_BDW); | |
8773 | } | |
8774 | ||
3c4c9b81 PZ |
8775 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
8776 | { | |
772c2a51 | 8777 | if (IS_HASWELL(dev_priv)) { |
3c4c9b81 PZ |
8778 | mutex_lock(&dev_priv->rps.hw_lock); |
8779 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
8780 | val)) | |
79cf219a | 8781 | DRM_DEBUG_KMS("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
8782 | mutex_unlock(&dev_priv->rps.hw_lock); |
8783 | } else { | |
9ccd5aeb PZ |
8784 | I915_WRITE(D_COMP_BDW, val); |
8785 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 8786 | } |
be256dc7 PZ |
8787 | } |
8788 | ||
8789 | /* | |
8790 | * This function implements pieces of two sequences from BSpec: | |
8791 | * - Sequence for display software to disable LCPLL | |
8792 | * - Sequence for display software to allow package C8+ | |
8793 | * The steps implemented here are just the steps that actually touch the LCPLL | |
8794 | * register. Callers should take care of disabling all the display engine | |
8795 | * functions, doing the mode unset, fixing interrupts, etc. | |
8796 | */ | |
6ff58d53 PZ |
8797 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
8798 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
8799 | { |
8800 | uint32_t val; | |
8801 | ||
8802 | assert_can_disable_lcpll(dev_priv); | |
8803 | ||
8804 | val = I915_READ(LCPLL_CTL); | |
8805 | ||
8806 | if (switch_to_fclk) { | |
8807 | val |= LCPLL_CD_SOURCE_FCLK; | |
8808 | I915_WRITE(LCPLL_CTL, val); | |
8809 | ||
f53dd63f ID |
8810 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
8811 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
be256dc7 PZ |
8812 | DRM_ERROR("Switching to FCLK failed\n"); |
8813 | ||
8814 | val = I915_READ(LCPLL_CTL); | |
8815 | } | |
8816 | ||
8817 | val |= LCPLL_PLL_DISABLE; | |
8818 | I915_WRITE(LCPLL_CTL, val); | |
8819 | POSTING_READ(LCPLL_CTL); | |
8820 | ||
24d8441d | 8821 | if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1)) |
be256dc7 PZ |
8822 | DRM_ERROR("LCPLL still locked\n"); |
8823 | ||
9ccd5aeb | 8824 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 8825 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 8826 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8827 | ndelay(100); |
8828 | ||
9ccd5aeb PZ |
8829 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
8830 | 1)) | |
be256dc7 PZ |
8831 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
8832 | ||
8833 | if (allow_power_down) { | |
8834 | val = I915_READ(LCPLL_CTL); | |
8835 | val |= LCPLL_POWER_DOWN_ALLOW; | |
8836 | I915_WRITE(LCPLL_CTL, val); | |
8837 | POSTING_READ(LCPLL_CTL); | |
8838 | } | |
8839 | } | |
8840 | ||
8841 | /* | |
8842 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
8843 | * source. | |
8844 | */ | |
6ff58d53 | 8845 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
8846 | { |
8847 | uint32_t val; | |
8848 | ||
8849 | val = I915_READ(LCPLL_CTL); | |
8850 | ||
8851 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
8852 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
8853 | return; | |
8854 | ||
a8a8bd54 PZ |
8855 | /* |
8856 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
8857 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 8858 | */ |
59bad947 | 8859 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 8860 | |
be256dc7 PZ |
8861 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
8862 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
8863 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 8864 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
8865 | } |
8866 | ||
9ccd5aeb | 8867 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
8868 | val |= D_COMP_COMP_FORCE; |
8869 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 8870 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8871 | |
8872 | val = I915_READ(LCPLL_CTL); | |
8873 | val &= ~LCPLL_PLL_DISABLE; | |
8874 | I915_WRITE(LCPLL_CTL, val); | |
8875 | ||
93220c08 CW |
8876 | if (intel_wait_for_register(dev_priv, |
8877 | LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
8878 | 5)) | |
be256dc7 PZ |
8879 | DRM_ERROR("LCPLL not locked yet\n"); |
8880 | ||
8881 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
8882 | val = I915_READ(LCPLL_CTL); | |
8883 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
8884 | I915_WRITE(LCPLL_CTL, val); | |
8885 | ||
f53dd63f ID |
8886 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
8887 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
be256dc7 PZ |
8888 | DRM_ERROR("Switching back to LCPLL failed\n"); |
8889 | } | |
215733fa | 8890 | |
59bad947 | 8891 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
4c75b940 | 8892 | intel_update_cdclk(dev_priv); |
be256dc7 PZ |
8893 | } |
8894 | ||
765dab67 PZ |
8895 | /* |
8896 | * Package states C8 and deeper are really deep PC states that can only be | |
8897 | * reached when all the devices on the system allow it, so even if the graphics | |
8898 | * device allows PC8+, it doesn't mean the system will actually get to these | |
8899 | * states. Our driver only allows PC8+ when going into runtime PM. | |
8900 | * | |
8901 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
8902 | * well is disabled and most interrupts are disabled, and these are also | |
8903 | * requirements for runtime PM. When these conditions are met, we manually do | |
8904 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
8905 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
8906 | * hang the machine. | |
8907 | * | |
8908 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
8909 | * the state of some registers, so when we come back from PC8+ we need to | |
8910 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
8911 | * need to take care of the registers kept by RC6. Notice that this happens even | |
8912 | * if we don't put the device in PCI D3 state (which is what currently happens | |
8913 | * because of the runtime PM support). | |
8914 | * | |
8915 | * For more, read "Display Sequences for Package C8" on the hardware | |
8916 | * documentation. | |
8917 | */ | |
a14cb6fc | 8918 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 8919 | { |
c67a470b PZ |
8920 | uint32_t val; |
8921 | ||
c67a470b PZ |
8922 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
8923 | ||
4f8036a2 | 8924 | if (HAS_PCH_LPT_LP(dev_priv)) { |
c67a470b PZ |
8925 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
8926 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
8927 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8928 | } | |
8929 | ||
c39055b0 | 8930 | lpt_disable_clkout_dp(dev_priv); |
c67a470b PZ |
8931 | hsw_disable_lcpll(dev_priv, true, true); |
8932 | } | |
8933 | ||
a14cb6fc | 8934 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 8935 | { |
c67a470b PZ |
8936 | uint32_t val; |
8937 | ||
c67a470b PZ |
8938 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
8939 | ||
8940 | hsw_restore_lcpll(dev_priv); | |
c39055b0 | 8941 | lpt_init_pch_refclk(dev_priv); |
c67a470b | 8942 | |
4f8036a2 | 8943 | if (HAS_PCH_LPT_LP(dev_priv)) { |
c67a470b PZ |
8944 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
8945 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
8946 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8947 | } | |
c67a470b PZ |
8948 | } |
8949 | ||
190f68c5 ACO |
8950 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
8951 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 8952 | { |
d7edc4e5 | 8953 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) { |
44a126ba PZ |
8954 | struct intel_encoder *encoder = |
8955 | intel_ddi_get_crtc_new_encoder(crtc_state); | |
8956 | ||
8957 | if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) { | |
8958 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
8959 | pipe_name(crtc->pipe)); | |
af3997b5 | 8960 | return -EINVAL; |
44a126ba | 8961 | } |
af3997b5 | 8962 | } |
716c2e55 | 8963 | |
c7653199 | 8964 | crtc->lowfreq_avail = false; |
644cef34 | 8965 | |
c8f7a0db | 8966 | return 0; |
79e53945 JB |
8967 | } |
8968 | ||
8b0f7e06 KM |
8969 | static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv, |
8970 | enum port port, | |
8971 | struct intel_crtc_state *pipe_config) | |
8972 | { | |
8973 | enum intel_dpll_id id; | |
8974 | u32 temp; | |
8975 | ||
8976 | temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); | |
8977 | id = temp >> (port * 2); | |
8978 | ||
8979 | if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2)) | |
8980 | return; | |
8981 | ||
8982 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
8983 | } | |
8984 | ||
3760b59c S |
8985 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
8986 | enum port port, | |
8987 | struct intel_crtc_state *pipe_config) | |
8988 | { | |
8106ddbd ACO |
8989 | enum intel_dpll_id id; |
8990 | ||
3760b59c S |
8991 | switch (port) { |
8992 | case PORT_A: | |
08250c4b | 8993 | id = DPLL_ID_SKL_DPLL0; |
3760b59c S |
8994 | break; |
8995 | case PORT_B: | |
08250c4b | 8996 | id = DPLL_ID_SKL_DPLL1; |
3760b59c S |
8997 | break; |
8998 | case PORT_C: | |
08250c4b | 8999 | id = DPLL_ID_SKL_DPLL2; |
3760b59c S |
9000 | break; |
9001 | default: | |
9002 | DRM_ERROR("Incorrect port type\n"); | |
8106ddbd | 9003 | return; |
3760b59c | 9004 | } |
8106ddbd ACO |
9005 | |
9006 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
3760b59c S |
9007 | } |
9008 | ||
96b7dfb7 S |
9009 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9010 | enum port port, | |
5cec258b | 9011 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9012 | { |
8106ddbd | 9013 | enum intel_dpll_id id; |
a3c988ea | 9014 | u32 temp; |
96b7dfb7 S |
9015 | |
9016 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
c856052a | 9017 | id = temp >> (port * 3 + 1); |
96b7dfb7 | 9018 | |
c856052a | 9019 | if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3)) |
8106ddbd | 9020 | return; |
8106ddbd ACO |
9021 | |
9022 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
96b7dfb7 S |
9023 | } |
9024 | ||
7d2c8175 DL |
9025 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9026 | enum port port, | |
5cec258b | 9027 | struct intel_crtc_state *pipe_config) |
7d2c8175 | 9028 | { |
8106ddbd | 9029 | enum intel_dpll_id id; |
c856052a | 9030 | uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
8106ddbd | 9031 | |
c856052a | 9032 | switch (ddi_pll_sel) { |
7d2c8175 | 9033 | case PORT_CLK_SEL_WRPLL1: |
8106ddbd | 9034 | id = DPLL_ID_WRPLL1; |
7d2c8175 DL |
9035 | break; |
9036 | case PORT_CLK_SEL_WRPLL2: | |
8106ddbd | 9037 | id = DPLL_ID_WRPLL2; |
7d2c8175 | 9038 | break; |
00490c22 | 9039 | case PORT_CLK_SEL_SPLL: |
8106ddbd | 9040 | id = DPLL_ID_SPLL; |
79bd23da | 9041 | break; |
9d16da65 ACO |
9042 | case PORT_CLK_SEL_LCPLL_810: |
9043 | id = DPLL_ID_LCPLL_810; | |
9044 | break; | |
9045 | case PORT_CLK_SEL_LCPLL_1350: | |
9046 | id = DPLL_ID_LCPLL_1350; | |
9047 | break; | |
9048 | case PORT_CLK_SEL_LCPLL_2700: | |
9049 | id = DPLL_ID_LCPLL_2700; | |
9050 | break; | |
8106ddbd | 9051 | default: |
c856052a | 9052 | MISSING_CASE(ddi_pll_sel); |
8106ddbd ACO |
9053 | /* fall through */ |
9054 | case PORT_CLK_SEL_NONE: | |
8106ddbd | 9055 | return; |
7d2c8175 | 9056 | } |
8106ddbd ACO |
9057 | |
9058 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
7d2c8175 DL |
9059 | } |
9060 | ||
cf30429e JN |
9061 | static bool hsw_get_transcoder_state(struct intel_crtc *crtc, |
9062 | struct intel_crtc_state *pipe_config, | |
d8fc70b7 | 9063 | u64 *power_domain_mask) |
cf30429e JN |
9064 | { |
9065 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9066 | struct drm_i915_private *dev_priv = to_i915(dev); |
cf30429e JN |
9067 | enum intel_display_power_domain power_domain; |
9068 | u32 tmp; | |
9069 | ||
d9a7bc67 ID |
9070 | /* |
9071 | * The pipe->transcoder mapping is fixed with the exception of the eDP | |
9072 | * transcoder handled below. | |
9073 | */ | |
cf30429e JN |
9074 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
9075 | ||
9076 | /* | |
9077 | * XXX: Do intel_display_power_get_if_enabled before reading this (for | |
9078 | * consistency and less surprising code; it's in always on power). | |
9079 | */ | |
9080 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
9081 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9082 | enum pipe trans_edp_pipe; | |
9083 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9084 | default: | |
9085 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9086 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9087 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9088 | trans_edp_pipe = PIPE_A; | |
9089 | break; | |
9090 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9091 | trans_edp_pipe = PIPE_B; | |
9092 | break; | |
9093 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9094 | trans_edp_pipe = PIPE_C; | |
9095 | break; | |
9096 | } | |
9097 | ||
9098 | if (trans_edp_pipe == crtc->pipe) | |
9099 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
9100 | } | |
9101 | ||
9102 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); | |
9103 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
9104 | return false; | |
d8fc70b7 | 9105 | *power_domain_mask |= BIT_ULL(power_domain); |
cf30429e JN |
9106 | |
9107 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); | |
9108 | ||
9109 | return tmp & PIPECONF_ENABLE; | |
9110 | } | |
9111 | ||
4d1de975 JN |
9112 | static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, |
9113 | struct intel_crtc_state *pipe_config, | |
d8fc70b7 | 9114 | u64 *power_domain_mask) |
4d1de975 JN |
9115 | { |
9116 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9117 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 JN |
9118 | enum intel_display_power_domain power_domain; |
9119 | enum port port; | |
9120 | enum transcoder cpu_transcoder; | |
9121 | u32 tmp; | |
9122 | ||
4d1de975 JN |
9123 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { |
9124 | if (port == PORT_A) | |
9125 | cpu_transcoder = TRANSCODER_DSI_A; | |
9126 | else | |
9127 | cpu_transcoder = TRANSCODER_DSI_C; | |
9128 | ||
9129 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
9130 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
9131 | continue; | |
d8fc70b7 | 9132 | *power_domain_mask |= BIT_ULL(power_domain); |
4d1de975 | 9133 | |
db18b6a6 ID |
9134 | /* |
9135 | * The PLL needs to be enabled with a valid divider | |
9136 | * configuration, otherwise accessing DSI registers will hang | |
9137 | * the machine. See BSpec North Display Engine | |
9138 | * registers/MIPI[BXT]. We can break out here early, since we | |
9139 | * need the same DSI PLL to be enabled for both DSI ports. | |
9140 | */ | |
9141 | if (!intel_dsi_pll_is_enabled(dev_priv)) | |
9142 | break; | |
9143 | ||
4d1de975 JN |
9144 | /* XXX: this works for video mode only */ |
9145 | tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
9146 | if (!(tmp & DPI_ENABLE)) | |
9147 | continue; | |
9148 | ||
9149 | tmp = I915_READ(MIPI_CTRL(port)); | |
9150 | if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) | |
9151 | continue; | |
9152 | ||
9153 | pipe_config->cpu_transcoder = cpu_transcoder; | |
4d1de975 JN |
9154 | break; |
9155 | } | |
9156 | ||
d7edc4e5 | 9157 | return transcoder_is_dsi(pipe_config->cpu_transcoder); |
4d1de975 JN |
9158 | } |
9159 | ||
26804afd | 9160 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9161 | struct intel_crtc_state *pipe_config) |
26804afd | 9162 | { |
6315b5d3 | 9163 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
d452c5b6 | 9164 | struct intel_shared_dpll *pll; |
26804afd DV |
9165 | enum port port; |
9166 | uint32_t tmp; | |
9167 | ||
9168 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9169 | ||
9170 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9171 | ||
8b0f7e06 KM |
9172 | if (IS_CANNONLAKE(dev_priv)) |
9173 | cannonlake_get_ddi_pll(dev_priv, port, pipe_config); | |
9174 | else if (IS_GEN9_BC(dev_priv)) | |
96b7dfb7 | 9175 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
cc3f90f0 | 9176 | else if (IS_GEN9_LP(dev_priv)) |
3760b59c | 9177 | bxt_get_ddi_pll(dev_priv, port, pipe_config); |
96b7dfb7 S |
9178 | else |
9179 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9180 | |
8106ddbd ACO |
9181 | pll = pipe_config->shared_dpll; |
9182 | if (pll) { | |
2edd6443 ACO |
9183 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
9184 | &pipe_config->dpll_hw_state)); | |
d452c5b6 DV |
9185 | } |
9186 | ||
26804afd DV |
9187 | /* |
9188 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9189 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9190 | * the PCH transcoder is on. | |
9191 | */ | |
6315b5d3 | 9192 | if (INTEL_GEN(dev_priv) < 9 && |
ca370455 | 9193 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
26804afd DV |
9194 | pipe_config->has_pch_encoder = true; |
9195 | ||
9196 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9197 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9198 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9199 | ||
9200 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9201 | } | |
9202 | } | |
9203 | ||
0e8ffe1b | 9204 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9205 | struct intel_crtc_state *pipe_config) |
0e8ffe1b | 9206 | { |
6315b5d3 | 9207 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1729050e | 9208 | enum intel_display_power_domain power_domain; |
d8fc70b7 | 9209 | u64 power_domain_mask; |
cf30429e | 9210 | bool active; |
0e8ffe1b | 9211 | |
e79dfb51 | 9212 | intel_crtc_init_scalers(crtc, pipe_config); |
5fb9dadf | 9213 | |
1729050e ID |
9214 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9215 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 | 9216 | return false; |
d8fc70b7 | 9217 | power_domain_mask = BIT_ULL(power_domain); |
1729050e | 9218 | |
8106ddbd | 9219 | pipe_config->shared_dpll = NULL; |
c0d43d62 | 9220 | |
cf30429e | 9221 | active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); |
eccb140b | 9222 | |
cc3f90f0 | 9223 | if (IS_GEN9_LP(dev_priv) && |
d7edc4e5 VS |
9224 | bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) { |
9225 | WARN_ON(active); | |
9226 | active = true; | |
4d1de975 JN |
9227 | } |
9228 | ||
cf30429e | 9229 | if (!active) |
1729050e | 9230 | goto out; |
0e8ffe1b | 9231 | |
d7edc4e5 | 9232 | if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { |
4d1de975 JN |
9233 | haswell_get_ddi_port_state(crtc, pipe_config); |
9234 | intel_get_pipe_timings(crtc, pipe_config); | |
9235 | } | |
627eb5a3 | 9236 | |
bc58be60 | 9237 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 9238 | |
05dc698c LL |
9239 | pipe_config->gamma_mode = |
9240 | I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; | |
9241 | ||
b22ca995 SS |
9242 | if (IS_BROADWELL(dev_priv) || dev_priv->info.gen >= 9) { |
9243 | u32 tmp = I915_READ(PIPEMISC(crtc->pipe)); | |
9244 | bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV; | |
9245 | ||
9246 | if (IS_GEMINILAKE(dev_priv) || dev_priv->info.gen >= 10) { | |
9247 | bool blend_mode_420 = tmp & | |
9248 | PIPEMISC_YUV420_MODE_FULL_BLEND; | |
9249 | ||
9250 | pipe_config->ycbcr420 = tmp & PIPEMISC_YUV420_ENABLE; | |
9251 | if (pipe_config->ycbcr420 != clrspace_yuv || | |
9252 | pipe_config->ycbcr420 != blend_mode_420) | |
9253 | DRM_DEBUG_KMS("Bad 4:2:0 mode (%08x)\n", tmp); | |
9254 | } else if (clrspace_yuv) { | |
9255 | DRM_DEBUG_KMS("YCbCr 4:2:0 Unsupported\n"); | |
9256 | } | |
9257 | } | |
9258 | ||
1729050e ID |
9259 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
9260 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
d8fc70b7 | 9261 | power_domain_mask |= BIT_ULL(power_domain); |
6315b5d3 | 9262 | if (INTEL_GEN(dev_priv) >= 9) |
bd2e244f | 9263 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 9264 | else |
1c132b44 | 9265 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 9266 | } |
88adfff1 | 9267 | |
772c2a51 | 9268 | if (IS_HASWELL(dev_priv)) |
e59150dc JB |
9269 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
9270 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 9271 | |
4d1de975 JN |
9272 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && |
9273 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { | |
ebb69c95 CT |
9274 | pipe_config->pixel_multiplier = |
9275 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
9276 | } else { | |
9277 | pipe_config->pixel_multiplier = 1; | |
9278 | } | |
6c49f241 | 9279 | |
1729050e ID |
9280 | out: |
9281 | for_each_power_domain(power_domain, power_domain_mask) | |
9282 | intel_display_power_put(dev_priv, power_domain); | |
9283 | ||
cf30429e | 9284 | return active; |
0e8ffe1b DV |
9285 | } |
9286 | ||
cd5dcbf1 | 9287 | static u32 intel_cursor_base(const struct intel_plane_state *plane_state) |
1cecc830 VS |
9288 | { |
9289 | struct drm_i915_private *dev_priv = | |
9290 | to_i915(plane_state->base.plane->dev); | |
9291 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
9292 | const struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
9293 | u32 base; | |
9294 | ||
9295 | if (INTEL_INFO(dev_priv)->cursor_needs_physical) | |
9296 | base = obj->phys_handle->busaddr; | |
9297 | else | |
9298 | base = intel_plane_ggtt_offset(plane_state); | |
9299 | ||
1e7b4fd8 VS |
9300 | base += plane_state->main.offset; |
9301 | ||
1cecc830 VS |
9302 | /* ILK+ do this automagically */ |
9303 | if (HAS_GMCH_DISPLAY(dev_priv) && | |
a82256bc | 9304 | plane_state->base.rotation & DRM_MODE_ROTATE_180) |
1cecc830 VS |
9305 | base += (plane_state->base.crtc_h * |
9306 | plane_state->base.crtc_w - 1) * fb->format->cpp[0]; | |
9307 | ||
9308 | return base; | |
9309 | } | |
9310 | ||
ed270223 VS |
9311 | static u32 intel_cursor_position(const struct intel_plane_state *plane_state) |
9312 | { | |
9313 | int x = plane_state->base.crtc_x; | |
9314 | int y = plane_state->base.crtc_y; | |
9315 | u32 pos = 0; | |
9316 | ||
9317 | if (x < 0) { | |
9318 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
9319 | x = -x; | |
9320 | } | |
9321 | pos |= x << CURSOR_X_SHIFT; | |
9322 | ||
9323 | if (y < 0) { | |
9324 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
9325 | y = -y; | |
9326 | } | |
9327 | pos |= y << CURSOR_Y_SHIFT; | |
9328 | ||
9329 | return pos; | |
9330 | } | |
9331 | ||
3637ecf0 VS |
9332 | static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state) |
9333 | { | |
9334 | const struct drm_mode_config *config = | |
9335 | &plane_state->base.plane->dev->mode_config; | |
9336 | int width = plane_state->base.crtc_w; | |
9337 | int height = plane_state->base.crtc_h; | |
9338 | ||
9339 | return width > 0 && width <= config->cursor_width && | |
9340 | height > 0 && height <= config->cursor_height; | |
9341 | } | |
9342 | ||
659056f2 VS |
9343 | static int intel_check_cursor(struct intel_crtc_state *crtc_state, |
9344 | struct intel_plane_state *plane_state) | |
9345 | { | |
9346 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
1e7b4fd8 VS |
9347 | int src_x, src_y; |
9348 | u32 offset; | |
659056f2 VS |
9349 | int ret; |
9350 | ||
9351 | ret = drm_plane_helper_check_state(&plane_state->base, | |
9352 | &plane_state->clip, | |
9353 | DRM_PLANE_HELPER_NO_SCALING, | |
9354 | DRM_PLANE_HELPER_NO_SCALING, | |
9355 | true, true); | |
9356 | if (ret) | |
9357 | return ret; | |
9358 | ||
9359 | if (!fb) | |
9360 | return 0; | |
9361 | ||
9362 | if (fb->modifier != DRM_FORMAT_MOD_LINEAR) { | |
9363 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); | |
9364 | return -EINVAL; | |
9365 | } | |
9366 | ||
1e7b4fd8 VS |
9367 | src_x = plane_state->base.src_x >> 16; |
9368 | src_y = plane_state->base.src_y >> 16; | |
9369 | ||
9370 | intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); | |
9371 | offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0); | |
9372 | ||
9373 | if (src_x != 0 || src_y != 0) { | |
9374 | DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n"); | |
9375 | return -EINVAL; | |
9376 | } | |
9377 | ||
9378 | plane_state->main.offset = offset; | |
9379 | ||
659056f2 VS |
9380 | return 0; |
9381 | } | |
9382 | ||
292889e1 VS |
9383 | static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state, |
9384 | const struct intel_plane_state *plane_state) | |
9385 | { | |
1e1bb871 | 9386 | const struct drm_framebuffer *fb = plane_state->base.fb; |
292889e1 | 9387 | |
292889e1 VS |
9388 | return CURSOR_ENABLE | |
9389 | CURSOR_GAMMA_ENABLE | | |
9390 | CURSOR_FORMAT_ARGB | | |
1e1bb871 | 9391 | CURSOR_STRIDE(fb->pitches[0]); |
292889e1 VS |
9392 | } |
9393 | ||
659056f2 VS |
9394 | static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state) |
9395 | { | |
659056f2 | 9396 | int width = plane_state->base.crtc_w; |
659056f2 VS |
9397 | |
9398 | /* | |
9399 | * 845g/865g are only limited by the width of their cursors, | |
9400 | * the height is arbitrary up to the precision of the register. | |
9401 | */ | |
3637ecf0 | 9402 | return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64); |
659056f2 VS |
9403 | } |
9404 | ||
9405 | static int i845_check_cursor(struct intel_plane *plane, | |
9406 | struct intel_crtc_state *crtc_state, | |
9407 | struct intel_plane_state *plane_state) | |
9408 | { | |
9409 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
659056f2 VS |
9410 | int ret; |
9411 | ||
9412 | ret = intel_check_cursor(crtc_state, plane_state); | |
9413 | if (ret) | |
9414 | return ret; | |
9415 | ||
9416 | /* if we want to turn off the cursor ignore width and height */ | |
1e1bb871 | 9417 | if (!fb) |
659056f2 VS |
9418 | return 0; |
9419 | ||
9420 | /* Check for which cursor types we support */ | |
9421 | if (!i845_cursor_size_ok(plane_state)) { | |
9422 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", | |
9423 | plane_state->base.crtc_w, | |
9424 | plane_state->base.crtc_h); | |
9425 | return -EINVAL; | |
9426 | } | |
9427 | ||
1e1bb871 | 9428 | switch (fb->pitches[0]) { |
292889e1 VS |
9429 | case 256: |
9430 | case 512: | |
9431 | case 1024: | |
9432 | case 2048: | |
9433 | break; | |
1e1bb871 VS |
9434 | default: |
9435 | DRM_DEBUG_KMS("Invalid cursor stride (%u)\n", | |
9436 | fb->pitches[0]); | |
9437 | return -EINVAL; | |
292889e1 VS |
9438 | } |
9439 | ||
659056f2 VS |
9440 | plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state); |
9441 | ||
9442 | return 0; | |
292889e1 VS |
9443 | } |
9444 | ||
b2d03b0d VS |
9445 | static void i845_update_cursor(struct intel_plane *plane, |
9446 | const struct intel_crtc_state *crtc_state, | |
55a08b3f | 9447 | const struct intel_plane_state *plane_state) |
560b85bb | 9448 | { |
cd5dcbf1 | 9449 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
b2d03b0d VS |
9450 | u32 cntl = 0, base = 0, pos = 0, size = 0; |
9451 | unsigned long irqflags; | |
560b85bb | 9452 | |
936e71e3 | 9453 | if (plane_state && plane_state->base.visible) { |
55a08b3f ML |
9454 | unsigned int width = plane_state->base.crtc_w; |
9455 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 | 9456 | |
a0864d59 | 9457 | cntl = plane_state->ctl; |
dc41c154 | 9458 | size = (height << 12) | width; |
560b85bb | 9459 | |
b2d03b0d VS |
9460 | base = intel_cursor_base(plane_state); |
9461 | pos = intel_cursor_position(plane_state); | |
4b0e333e | 9462 | } |
560b85bb | 9463 | |
b2d03b0d | 9464 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
4726e0b0 | 9465 | |
e11ffddb VS |
9466 | /* On these chipsets we can only modify the base/size/stride |
9467 | * whilst the cursor is disabled. | |
9468 | */ | |
9469 | if (plane->cursor.base != base || | |
9470 | plane->cursor.size != size || | |
9471 | plane->cursor.cntl != cntl) { | |
dd584fc0 | 9472 | I915_WRITE_FW(CURCNTR(PIPE_A), 0); |
dd584fc0 | 9473 | I915_WRITE_FW(CURBASE(PIPE_A), base); |
dd584fc0 | 9474 | I915_WRITE_FW(CURSIZE, size); |
b2d03b0d | 9475 | I915_WRITE_FW(CURPOS(PIPE_A), pos); |
dd584fc0 | 9476 | I915_WRITE_FW(CURCNTR(PIPE_A), cntl); |
75343a44 | 9477 | |
e11ffddb VS |
9478 | plane->cursor.base = base; |
9479 | plane->cursor.size = size; | |
9480 | plane->cursor.cntl = cntl; | |
9481 | } else { | |
9482 | I915_WRITE_FW(CURPOS(PIPE_A), pos); | |
560b85bb | 9483 | } |
e11ffddb | 9484 | |
75343a44 | 9485 | POSTING_READ_FW(CURCNTR(PIPE_A)); |
b2d03b0d VS |
9486 | |
9487 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
9488 | } | |
9489 | ||
9490 | static void i845_disable_cursor(struct intel_plane *plane, | |
9491 | struct intel_crtc *crtc) | |
9492 | { | |
9493 | i845_update_cursor(plane, NULL, NULL); | |
560b85bb CW |
9494 | } |
9495 | ||
292889e1 VS |
9496 | static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, |
9497 | const struct intel_plane_state *plane_state) | |
9498 | { | |
9499 | struct drm_i915_private *dev_priv = | |
9500 | to_i915(plane_state->base.plane->dev); | |
9501 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
292889e1 VS |
9502 | u32 cntl; |
9503 | ||
9504 | cntl = MCURSOR_GAMMA_ENABLE; | |
9505 | ||
9506 | if (HAS_DDI(dev_priv)) | |
9507 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
9508 | ||
d509e28b | 9509 | cntl |= MCURSOR_PIPE_SELECT(crtc->pipe); |
292889e1 VS |
9510 | |
9511 | switch (plane_state->base.crtc_w) { | |
9512 | case 64: | |
9513 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
9514 | break; | |
9515 | case 128: | |
9516 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
9517 | break; | |
9518 | case 256: | |
9519 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
9520 | break; | |
9521 | default: | |
9522 | MISSING_CASE(plane_state->base.crtc_w); | |
9523 | return 0; | |
9524 | } | |
9525 | ||
c2c446ad | 9526 | if (plane_state->base.rotation & DRM_MODE_ROTATE_180) |
292889e1 VS |
9527 | cntl |= CURSOR_ROTATE_180; |
9528 | ||
9529 | return cntl; | |
9530 | } | |
9531 | ||
659056f2 | 9532 | static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state) |
65a21cd6 | 9533 | { |
024faac7 VS |
9534 | struct drm_i915_private *dev_priv = |
9535 | to_i915(plane_state->base.plane->dev); | |
659056f2 VS |
9536 | int width = plane_state->base.crtc_w; |
9537 | int height = plane_state->base.crtc_h; | |
4b0e333e | 9538 | |
3637ecf0 | 9539 | if (!intel_cursor_size_ok(plane_state)) |
659056f2 | 9540 | return false; |
4398ad45 | 9541 | |
024faac7 VS |
9542 | /* Cursor width is limited to a few power-of-two sizes */ |
9543 | switch (width) { | |
659056f2 VS |
9544 | case 256: |
9545 | case 128: | |
659056f2 VS |
9546 | case 64: |
9547 | break; | |
9548 | default: | |
9549 | return false; | |
65a21cd6 | 9550 | } |
4b0e333e | 9551 | |
024faac7 VS |
9552 | /* |
9553 | * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor | |
9554 | * height from 8 lines up to the cursor width, when the | |
9555 | * cursor is not rotated. Everything else requires square | |
9556 | * cursors. | |
9557 | */ | |
9558 | if (HAS_CUR_FBC(dev_priv) && | |
a82256bc | 9559 | plane_state->base.rotation & DRM_MODE_ROTATE_0) { |
024faac7 VS |
9560 | if (height < 8 || height > width) |
9561 | return false; | |
9562 | } else { | |
9563 | if (height != width) | |
9564 | return false; | |
9565 | } | |
99d1f387 | 9566 | |
659056f2 | 9567 | return true; |
65a21cd6 JB |
9568 | } |
9569 | ||
659056f2 VS |
9570 | static int i9xx_check_cursor(struct intel_plane *plane, |
9571 | struct intel_crtc_state *crtc_state, | |
9572 | struct intel_plane_state *plane_state) | |
cda4b7d3 | 9573 | { |
659056f2 VS |
9574 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
9575 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
659056f2 | 9576 | enum pipe pipe = plane->pipe; |
659056f2 | 9577 | int ret; |
cda4b7d3 | 9578 | |
659056f2 VS |
9579 | ret = intel_check_cursor(crtc_state, plane_state); |
9580 | if (ret) | |
9581 | return ret; | |
cda4b7d3 | 9582 | |
659056f2 | 9583 | /* if we want to turn off the cursor ignore width and height */ |
1e1bb871 | 9584 | if (!fb) |
659056f2 | 9585 | return 0; |
55a08b3f | 9586 | |
659056f2 VS |
9587 | /* Check for which cursor types we support */ |
9588 | if (!i9xx_cursor_size_ok(plane_state)) { | |
9589 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", | |
9590 | plane_state->base.crtc_w, | |
9591 | plane_state->base.crtc_h); | |
9592 | return -EINVAL; | |
cda4b7d3 | 9593 | } |
cda4b7d3 | 9594 | |
1e1bb871 VS |
9595 | if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) { |
9596 | DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n", | |
9597 | fb->pitches[0], plane_state->base.crtc_w); | |
9598 | return -EINVAL; | |
659056f2 | 9599 | } |
dd584fc0 | 9600 | |
659056f2 VS |
9601 | /* |
9602 | * There's something wrong with the cursor on CHV pipe C. | |
9603 | * If it straddles the left edge of the screen then | |
9604 | * moving it away from the edge or disabling it often | |
9605 | * results in a pipe underrun, and often that can lead to | |
9606 | * dead pipe (constant underrun reported, and it scans | |
9607 | * out just a solid color). To recover from that, the | |
9608 | * display power well must be turned off and on again. | |
9609 | * Refuse the put the cursor into that compromised position. | |
9610 | */ | |
9611 | if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C && | |
9612 | plane_state->base.visible && plane_state->base.crtc_x < 0) { | |
9613 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); | |
9614 | return -EINVAL; | |
9615 | } | |
5efb3e28 | 9616 | |
659056f2 | 9617 | plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state); |
dd584fc0 | 9618 | |
659056f2 | 9619 | return 0; |
cda4b7d3 CW |
9620 | } |
9621 | ||
b2d03b0d VS |
9622 | static void i9xx_update_cursor(struct intel_plane *plane, |
9623 | const struct intel_crtc_state *crtc_state, | |
55a08b3f | 9624 | const struct intel_plane_state *plane_state) |
dc41c154 | 9625 | { |
cd5dcbf1 VS |
9626 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
9627 | enum pipe pipe = plane->pipe; | |
024faac7 | 9628 | u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0; |
b2d03b0d | 9629 | unsigned long irqflags; |
dc41c154 | 9630 | |
b2d03b0d | 9631 | if (plane_state && plane_state->base.visible) { |
a0864d59 | 9632 | cntl = plane_state->ctl; |
dc41c154 | 9633 | |
024faac7 VS |
9634 | if (plane_state->base.crtc_h != plane_state->base.crtc_w) |
9635 | fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1); | |
dc41c154 | 9636 | |
b2d03b0d VS |
9637 | base = intel_cursor_base(plane_state); |
9638 | pos = intel_cursor_position(plane_state); | |
9639 | } | |
9640 | ||
9641 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
9642 | ||
e11ffddb VS |
9643 | /* |
9644 | * On some platforms writing CURCNTR first will also | |
9645 | * cause CURPOS to be armed by the CURBASE write. | |
9646 | * Without the CURCNTR write the CURPOS write would | |
8753d2bc VS |
9647 | * arm itself. Thus we always start the full update |
9648 | * with a CURCNTR write. | |
9649 | * | |
9650 | * On other platforms CURPOS always requires the | |
9651 | * CURBASE write to arm the update. Additonally | |
9652 | * a write to any of the cursor register will cancel | |
9653 | * an already armed cursor update. Thus leaving out | |
9654 | * the CURBASE write after CURPOS could lead to a | |
9655 | * cursor that doesn't appear to move, or even change | |
9656 | * shape. Thus we always write CURBASE. | |
e11ffddb VS |
9657 | * |
9658 | * CURCNTR and CUR_FBC_CTL are always | |
9659 | * armed by the CURBASE write only. | |
9660 | */ | |
9661 | if (plane->cursor.base != base || | |
9662 | plane->cursor.size != fbc_ctl || | |
9663 | plane->cursor.cntl != cntl) { | |
dd584fc0 | 9664 | I915_WRITE_FW(CURCNTR(pipe), cntl); |
e11ffddb VS |
9665 | if (HAS_CUR_FBC(dev_priv)) |
9666 | I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl); | |
b2d03b0d | 9667 | I915_WRITE_FW(CURPOS(pipe), pos); |
75343a44 VS |
9668 | I915_WRITE_FW(CURBASE(pipe), base); |
9669 | ||
e11ffddb VS |
9670 | plane->cursor.base = base; |
9671 | plane->cursor.size = fbc_ctl; | |
9672 | plane->cursor.cntl = cntl; | |
dc41c154 | 9673 | } else { |
e11ffddb | 9674 | I915_WRITE_FW(CURPOS(pipe), pos); |
8753d2bc | 9675 | I915_WRITE_FW(CURBASE(pipe), base); |
dc41c154 VS |
9676 | } |
9677 | ||
dd584fc0 | 9678 | POSTING_READ_FW(CURBASE(pipe)); |
99d1f387 | 9679 | |
b2d03b0d | 9680 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
65a21cd6 JB |
9681 | } |
9682 | ||
b2d03b0d VS |
9683 | static void i9xx_disable_cursor(struct intel_plane *plane, |
9684 | struct intel_crtc *crtc) | |
cda4b7d3 | 9685 | { |
b2d03b0d | 9686 | i9xx_update_cursor(plane, NULL, NULL); |
dc41c154 VS |
9687 | } |
9688 | ||
dc41c154 | 9689 | |
79e53945 JB |
9690 | /* VESA 640x480x72Hz mode to set on the pipe */ |
9691 | static struct drm_display_mode load_detect_mode = { | |
9692 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
9693 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
9694 | }; | |
9695 | ||
a8bb6818 | 9696 | struct drm_framebuffer * |
24dbf51a CW |
9697 | intel_framebuffer_create(struct drm_i915_gem_object *obj, |
9698 | struct drm_mode_fb_cmd2 *mode_cmd) | |
d2dff872 CW |
9699 | { |
9700 | struct intel_framebuffer *intel_fb; | |
9701 | int ret; | |
9702 | ||
9703 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 9704 | if (!intel_fb) |
d2dff872 | 9705 | return ERR_PTR(-ENOMEM); |
d2dff872 | 9706 | |
24dbf51a | 9707 | ret = intel_framebuffer_init(intel_fb, obj, mode_cmd); |
dd4916c5 DV |
9708 | if (ret) |
9709 | goto err; | |
d2dff872 CW |
9710 | |
9711 | return &intel_fb->base; | |
dcb1394e | 9712 | |
dd4916c5 | 9713 | err: |
dd4916c5 | 9714 | kfree(intel_fb); |
dd4916c5 | 9715 | return ERR_PTR(ret); |
d2dff872 CW |
9716 | } |
9717 | ||
9718 | static u32 | |
9719 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
9720 | { | |
9721 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
9722 | return ALIGN(pitch, 64); | |
9723 | } | |
9724 | ||
9725 | static u32 | |
9726 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
9727 | { | |
9728 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 9729 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
9730 | } |
9731 | ||
9732 | static struct drm_framebuffer * | |
9733 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
9734 | struct drm_display_mode *mode, | |
9735 | int depth, int bpp) | |
9736 | { | |
dcb1394e | 9737 | struct drm_framebuffer *fb; |
d2dff872 | 9738 | struct drm_i915_gem_object *obj; |
0fed39bd | 9739 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 | 9740 | |
12d79d78 | 9741 | obj = i915_gem_object_create(to_i915(dev), |
d2dff872 | 9742 | intel_framebuffer_size_for_mode(mode, bpp)); |
fe3db79b CW |
9743 | if (IS_ERR(obj)) |
9744 | return ERR_CAST(obj); | |
d2dff872 CW |
9745 | |
9746 | mode_cmd.width = mode->hdisplay; | |
9747 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
9748 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
9749 | bpp); | |
5ca0c34a | 9750 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 9751 | |
24dbf51a | 9752 | fb = intel_framebuffer_create(obj, &mode_cmd); |
dcb1394e | 9753 | if (IS_ERR(fb)) |
f0cd5182 | 9754 | i915_gem_object_put(obj); |
dcb1394e LW |
9755 | |
9756 | return fb; | |
d2dff872 CW |
9757 | } |
9758 | ||
9759 | static struct drm_framebuffer * | |
9760 | mode_fits_in_fbdev(struct drm_device *dev, | |
9761 | struct drm_display_mode *mode) | |
9762 | { | |
0695726e | 9763 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
fac5e23e | 9764 | struct drm_i915_private *dev_priv = to_i915(dev); |
d2dff872 CW |
9765 | struct drm_i915_gem_object *obj; |
9766 | struct drm_framebuffer *fb; | |
9767 | ||
4c0e5528 | 9768 | if (!dev_priv->fbdev) |
d2dff872 CW |
9769 | return NULL; |
9770 | ||
4c0e5528 | 9771 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
9772 | return NULL; |
9773 | ||
4c0e5528 DV |
9774 | obj = dev_priv->fbdev->fb->obj; |
9775 | BUG_ON(!obj); | |
9776 | ||
8bcd4553 | 9777 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 | 9778 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
272725c7 | 9779 | fb->format->cpp[0] * 8)) |
d2dff872 CW |
9780 | return NULL; |
9781 | ||
01f2c773 | 9782 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
9783 | return NULL; |
9784 | ||
edde3617 | 9785 | drm_framebuffer_reference(fb); |
d2dff872 | 9786 | return fb; |
4520f53a DV |
9787 | #else |
9788 | return NULL; | |
9789 | #endif | |
d2dff872 CW |
9790 | } |
9791 | ||
d3a40d1b ACO |
9792 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
9793 | struct drm_crtc *crtc, | |
9794 | struct drm_display_mode *mode, | |
9795 | struct drm_framebuffer *fb, | |
9796 | int x, int y) | |
9797 | { | |
9798 | struct drm_plane_state *plane_state; | |
9799 | int hdisplay, vdisplay; | |
9800 | int ret; | |
9801 | ||
9802 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
9803 | if (IS_ERR(plane_state)) | |
9804 | return PTR_ERR(plane_state); | |
9805 | ||
9806 | if (mode) | |
196cd5d3 | 9807 | drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay); |
d3a40d1b ACO |
9808 | else |
9809 | hdisplay = vdisplay = 0; | |
9810 | ||
9811 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
9812 | if (ret) | |
9813 | return ret; | |
9814 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
9815 | plane_state->crtc_x = 0; | |
9816 | plane_state->crtc_y = 0; | |
9817 | plane_state->crtc_w = hdisplay; | |
9818 | plane_state->crtc_h = vdisplay; | |
9819 | plane_state->src_x = x << 16; | |
9820 | plane_state->src_y = y << 16; | |
9821 | plane_state->src_w = hdisplay << 16; | |
9822 | plane_state->src_h = vdisplay << 16; | |
9823 | ||
9824 | return 0; | |
9825 | } | |
9826 | ||
6c5ed5ae ML |
9827 | int intel_get_load_detect_pipe(struct drm_connector *connector, |
9828 | struct drm_display_mode *mode, | |
9829 | struct intel_load_detect_pipe *old, | |
9830 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
9831 | { |
9832 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
9833 | struct intel_encoder *intel_encoder = |
9834 | intel_attached_encoder(connector); | |
79e53945 | 9835 | struct drm_crtc *possible_crtc; |
4ef69c7a | 9836 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
9837 | struct drm_crtc *crtc = NULL; |
9838 | struct drm_device *dev = encoder->dev; | |
0f0f74bc | 9839 | struct drm_i915_private *dev_priv = to_i915(dev); |
94352cf9 | 9840 | struct drm_framebuffer *fb; |
51fd371b | 9841 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 9842 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 9843 | struct drm_connector_state *connector_state; |
4be07317 | 9844 | struct intel_crtc_state *crtc_state; |
51fd371b | 9845 | int ret, i = -1; |
79e53945 | 9846 | |
d2dff872 | 9847 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9848 | connector->base.id, connector->name, |
8e329a03 | 9849 | encoder->base.id, encoder->name); |
d2dff872 | 9850 | |
edde3617 ML |
9851 | old->restore_state = NULL; |
9852 | ||
6c5ed5ae | 9853 | WARN_ON(!drm_modeset_is_locked(&config->connection_mutex)); |
6e9f798d | 9854 | |
79e53945 JB |
9855 | /* |
9856 | * Algorithm gets a little messy: | |
7a5e4805 | 9857 | * |
79e53945 JB |
9858 | * - if the connector already has an assigned crtc, use it (but make |
9859 | * sure it's on first) | |
7a5e4805 | 9860 | * |
79e53945 JB |
9861 | * - try to find the first unused crtc that can drive this connector, |
9862 | * and use that if we find one | |
79e53945 JB |
9863 | */ |
9864 | ||
9865 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
9866 | if (connector->state->crtc) { |
9867 | crtc = connector->state->crtc; | |
8261b191 | 9868 | |
51fd371b | 9869 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 9870 | if (ret) |
ad3c558f | 9871 | goto fail; |
8261b191 CW |
9872 | |
9873 | /* Make sure the crtc and connector are running */ | |
edde3617 | 9874 | goto found; |
79e53945 JB |
9875 | } |
9876 | ||
9877 | /* Find an unused one (if possible) */ | |
70e1e0ec | 9878 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
9879 | i++; |
9880 | if (!(encoder->possible_crtcs & (1 << i))) | |
9881 | continue; | |
edde3617 ML |
9882 | |
9883 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
9884 | if (ret) | |
9885 | goto fail; | |
9886 | ||
9887 | if (possible_crtc->state->enable) { | |
9888 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 9889 | continue; |
edde3617 | 9890 | } |
a459249c VS |
9891 | |
9892 | crtc = possible_crtc; | |
9893 | break; | |
79e53945 JB |
9894 | } |
9895 | ||
9896 | /* | |
9897 | * If we didn't find an unused CRTC, don't use any. | |
9898 | */ | |
9899 | if (!crtc) { | |
7173188d | 9900 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
f4bf77b4 | 9901 | ret = -ENODEV; |
ad3c558f | 9902 | goto fail; |
79e53945 JB |
9903 | } |
9904 | ||
edde3617 ML |
9905 | found: |
9906 | intel_crtc = to_intel_crtc(crtc); | |
9907 | ||
4d02e2de DV |
9908 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
9909 | if (ret) | |
ad3c558f | 9910 | goto fail; |
79e53945 | 9911 | |
83a57153 | 9912 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
9913 | restore_state = drm_atomic_state_alloc(dev); |
9914 | if (!state || !restore_state) { | |
9915 | ret = -ENOMEM; | |
9916 | goto fail; | |
9917 | } | |
83a57153 ACO |
9918 | |
9919 | state->acquire_ctx = ctx; | |
edde3617 | 9920 | restore_state->acquire_ctx = ctx; |
83a57153 | 9921 | |
944b0c76 ACO |
9922 | connector_state = drm_atomic_get_connector_state(state, connector); |
9923 | if (IS_ERR(connector_state)) { | |
9924 | ret = PTR_ERR(connector_state); | |
9925 | goto fail; | |
9926 | } | |
9927 | ||
edde3617 ML |
9928 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
9929 | if (ret) | |
9930 | goto fail; | |
944b0c76 | 9931 | |
4be07317 ACO |
9932 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
9933 | if (IS_ERR(crtc_state)) { | |
9934 | ret = PTR_ERR(crtc_state); | |
9935 | goto fail; | |
9936 | } | |
9937 | ||
49d6fa21 | 9938 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 9939 | |
6492711d CW |
9940 | if (!mode) |
9941 | mode = &load_detect_mode; | |
79e53945 | 9942 | |
d2dff872 CW |
9943 | /* We need a framebuffer large enough to accommodate all accesses |
9944 | * that the plane may generate whilst we perform load detection. | |
9945 | * We can not rely on the fbcon either being present (we get called | |
9946 | * during its initialisation to detect all boot displays, or it may | |
9947 | * not even exist) or that it is large enough to satisfy the | |
9948 | * requested mode. | |
9949 | */ | |
94352cf9 DV |
9950 | fb = mode_fits_in_fbdev(dev, mode); |
9951 | if (fb == NULL) { | |
d2dff872 | 9952 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 | 9953 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
d2dff872 CW |
9954 | } else |
9955 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 9956 | if (IS_ERR(fb)) { |
d2dff872 | 9957 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
f4bf77b4 | 9958 | ret = PTR_ERR(fb); |
412b61d8 | 9959 | goto fail; |
79e53945 | 9960 | } |
79e53945 | 9961 | |
d3a40d1b ACO |
9962 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
9963 | if (ret) | |
9964 | goto fail; | |
9965 | ||
edde3617 ML |
9966 | drm_framebuffer_unreference(fb); |
9967 | ||
9968 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
9969 | if (ret) | |
9970 | goto fail; | |
9971 | ||
9972 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
9973 | if (!ret) | |
9974 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
9975 | if (!ret) | |
9976 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
9977 | if (ret) { | |
9978 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
9979 | goto fail; | |
9980 | } | |
8c7b5ccb | 9981 | |
3ba86073 ML |
9982 | ret = drm_atomic_commit(state); |
9983 | if (ret) { | |
6492711d | 9984 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
412b61d8 | 9985 | goto fail; |
79e53945 | 9986 | } |
edde3617 ML |
9987 | |
9988 | old->restore_state = restore_state; | |
7abbd11f | 9989 | drm_atomic_state_put(state); |
7173188d | 9990 | |
79e53945 | 9991 | /* let the connector get through one full cycle before testing */ |
0f0f74bc | 9992 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
7173188d | 9993 | return true; |
412b61d8 | 9994 | |
ad3c558f | 9995 | fail: |
7fb71c8f CW |
9996 | if (state) { |
9997 | drm_atomic_state_put(state); | |
9998 | state = NULL; | |
9999 | } | |
10000 | if (restore_state) { | |
10001 | drm_atomic_state_put(restore_state); | |
10002 | restore_state = NULL; | |
10003 | } | |
83a57153 | 10004 | |
6c5ed5ae ML |
10005 | if (ret == -EDEADLK) |
10006 | return ret; | |
51fd371b | 10007 | |
412b61d8 | 10008 | return false; |
79e53945 JB |
10009 | } |
10010 | ||
d2434ab7 | 10011 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10012 | struct intel_load_detect_pipe *old, |
10013 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10014 | { |
d2434ab7 DV |
10015 | struct intel_encoder *intel_encoder = |
10016 | intel_attached_encoder(connector); | |
4ef69c7a | 10017 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 10018 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 10019 | int ret; |
79e53945 | 10020 | |
d2dff872 | 10021 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10022 | connector->base.id, connector->name, |
8e329a03 | 10023 | encoder->base.id, encoder->name); |
d2dff872 | 10024 | |
edde3617 | 10025 | if (!state) |
0622a53c | 10026 | return; |
79e53945 | 10027 | |
581e49fe | 10028 | ret = drm_atomic_helper_commit_duplicated_state(state, ctx); |
0853695c | 10029 | if (ret) |
edde3617 | 10030 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); |
0853695c | 10031 | drm_atomic_state_put(state); |
79e53945 JB |
10032 | } |
10033 | ||
da4a1efa | 10034 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10035 | const struct intel_crtc_state *pipe_config) |
da4a1efa | 10036 | { |
fac5e23e | 10037 | struct drm_i915_private *dev_priv = to_i915(dev); |
da4a1efa VS |
10038 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
10039 | ||
10040 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10041 | return dev_priv->vbt.lvds_ssc_freq; |
6e266956 | 10042 | else if (HAS_PCH_SPLIT(dev_priv)) |
da4a1efa | 10043 | return 120000; |
5db94019 | 10044 | else if (!IS_GEN2(dev_priv)) |
da4a1efa VS |
10045 | return 96000; |
10046 | else | |
10047 | return 48000; | |
10048 | } | |
10049 | ||
79e53945 | 10050 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10051 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10052 | struct intel_crtc_state *pipe_config) |
79e53945 | 10053 | { |
f1f644dc | 10054 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 10055 | struct drm_i915_private *dev_priv = to_i915(dev); |
f1f644dc | 10056 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10057 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 | 10058 | u32 fp; |
9e2c8475 | 10059 | struct dpll clock; |
dccbea3b | 10060 | int port_clock; |
da4a1efa | 10061 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10062 | |
10063 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10064 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10065 | else |
293623f7 | 10066 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10067 | |
10068 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
9b1e14f4 | 10069 | if (IS_PINEVIEW(dev_priv)) { |
f2b115e6 AJ |
10070 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
10071 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10072 | } else { |
10073 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10074 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10075 | } | |
10076 | ||
5db94019 | 10077 | if (!IS_GEN2(dev_priv)) { |
9b1e14f4 | 10078 | if (IS_PINEVIEW(dev_priv)) |
f2b115e6 AJ |
10079 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
10080 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10081 | else |
10082 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10083 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10084 | ||
10085 | switch (dpll & DPLL_MODE_MASK) { | |
10086 | case DPLLB_MODE_DAC_SERIAL: | |
10087 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10088 | 5 : 10; | |
10089 | break; | |
10090 | case DPLLB_MODE_LVDS: | |
10091 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10092 | 7 : 14; | |
10093 | break; | |
10094 | default: | |
28c97730 | 10095 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10096 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10097 | return; |
79e53945 JB |
10098 | } |
10099 | ||
9b1e14f4 | 10100 | if (IS_PINEVIEW(dev_priv)) |
dccbea3b | 10101 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 10102 | else |
dccbea3b | 10103 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 10104 | } else { |
50a0bc90 | 10105 | u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10106 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10107 | |
10108 | if (is_lvds) { | |
10109 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10110 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10111 | |
10112 | if (lvds & LVDS_CLKB_POWER_UP) | |
10113 | clock.p2 = 7; | |
10114 | else | |
10115 | clock.p2 = 14; | |
79e53945 JB |
10116 | } else { |
10117 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10118 | clock.p1 = 2; | |
10119 | else { | |
10120 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10121 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10122 | } | |
10123 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10124 | clock.p2 = 4; | |
10125 | else | |
10126 | clock.p2 = 2; | |
79e53945 | 10127 | } |
da4a1efa | 10128 | |
dccbea3b | 10129 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
10130 | } |
10131 | ||
18442d08 VS |
10132 | /* |
10133 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10134 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10135 | * encoder's get_config() function. |
10136 | */ | |
dccbea3b | 10137 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
10138 | } |
10139 | ||
6878da05 VS |
10140 | int intel_dotclock_calculate(int link_freq, |
10141 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10142 | { |
f1f644dc JB |
10143 | /* |
10144 | * The calculation for the data clock is: | |
1041a02f | 10145 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10146 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10147 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10148 | * |
10149 | * and the link clock is simpler: | |
1041a02f | 10150 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10151 | */ |
10152 | ||
6878da05 VS |
10153 | if (!m_n->link_n) |
10154 | return 0; | |
f1f644dc | 10155 | |
6878da05 VS |
10156 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10157 | } | |
f1f644dc | 10158 | |
18442d08 | 10159 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10160 | struct intel_crtc_state *pipe_config) |
6878da05 | 10161 | { |
e3b247da | 10162 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
79e53945 | 10163 | |
18442d08 VS |
10164 | /* read out port_clock from the DPLL */ |
10165 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10166 | |
f1f644dc | 10167 | /* |
e3b247da VS |
10168 | * In case there is an active pipe without active ports, |
10169 | * we may need some idea for the dotclock anyway. | |
10170 | * Calculate one based on the FDI configuration. | |
79e53945 | 10171 | */ |
2d112de7 | 10172 | pipe_config->base.adjusted_mode.crtc_clock = |
21a727b3 | 10173 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
18442d08 | 10174 | &pipe_config->fdi_m_n); |
79e53945 JB |
10175 | } |
10176 | ||
10177 | /** Returns the currently programmed mode of the given pipe. */ | |
10178 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10179 | struct drm_crtc *crtc) | |
10180 | { | |
fac5e23e | 10181 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 10182 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10183 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10184 | struct drm_display_mode *mode; |
3f36b937 | 10185 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
10186 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10187 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10188 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10189 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10190 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10191 | |
10192 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10193 | if (!mode) | |
10194 | return NULL; | |
10195 | ||
3f36b937 TU |
10196 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
10197 | if (!pipe_config) { | |
10198 | kfree(mode); | |
10199 | return NULL; | |
10200 | } | |
10201 | ||
f1f644dc JB |
10202 | /* |
10203 | * Construct a pipe_config sufficient for getting the clock info | |
10204 | * back out of crtc_clock_get. | |
10205 | * | |
10206 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10207 | * to use a real value here instead. | |
10208 | */ | |
3f36b937 TU |
10209 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
10210 | pipe_config->pixel_multiplier = 1; | |
10211 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
10212 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10213 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
10214 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
10215 | ||
10216 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
10217 | mode->hdisplay = (htot & 0xffff) + 1; |
10218 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10219 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10220 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10221 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10222 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10223 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10224 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10225 | ||
10226 | drm_mode_set_name(mode); | |
79e53945 | 10227 | |
3f36b937 TU |
10228 | kfree(pipe_config); |
10229 | ||
79e53945 JB |
10230 | return mode; |
10231 | } | |
10232 | ||
10233 | static void intel_crtc_destroy(struct drm_crtc *crtc) | |
10234 | { | |
10235 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10236 | ||
10237 | drm_crtc_cleanup(crtc); | |
10238 | kfree(intel_crtc); | |
10239 | } | |
10240 | ||
5a21b665 DV |
10241 | /** |
10242 | * intel_wm_need_update - Check whether watermarks need updating | |
10243 | * @plane: drm plane | |
10244 | * @state: new plane state | |
10245 | * | |
10246 | * Check current plane state versus the new one to determine whether | |
10247 | * watermarks need to be recalculated. | |
10248 | * | |
10249 | * Returns true or false. | |
10250 | */ | |
10251 | static bool intel_wm_need_update(struct drm_plane *plane, | |
10252 | struct drm_plane_state *state) | |
10253 | { | |
10254 | struct intel_plane_state *new = to_intel_plane_state(state); | |
10255 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
10256 | ||
10257 | /* Update watermarks on tiling or size changes. */ | |
936e71e3 | 10258 | if (new->base.visible != cur->base.visible) |
5a21b665 DV |
10259 | return true; |
10260 | ||
10261 | if (!cur->base.fb || !new->base.fb) | |
10262 | return false; | |
10263 | ||
bae781b2 | 10264 | if (cur->base.fb->modifier != new->base.fb->modifier || |
5a21b665 | 10265 | cur->base.rotation != new->base.rotation || |
936e71e3 VS |
10266 | drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) || |
10267 | drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) || | |
10268 | drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) || | |
10269 | drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst)) | |
5a21b665 DV |
10270 | return true; |
10271 | ||
10272 | return false; | |
10273 | } | |
10274 | ||
10275 | static bool needs_scaling(struct intel_plane_state *state) | |
10276 | { | |
936e71e3 VS |
10277 | int src_w = drm_rect_width(&state->base.src) >> 16; |
10278 | int src_h = drm_rect_height(&state->base.src) >> 16; | |
10279 | int dst_w = drm_rect_width(&state->base.dst); | |
10280 | int dst_h = drm_rect_height(&state->base.dst); | |
5a21b665 DV |
10281 | |
10282 | return (src_w != dst_w || src_h != dst_h); | |
10283 | } | |
d21fbe87 | 10284 | |
da20eabd ML |
10285 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
10286 | struct drm_plane_state *plane_state) | |
10287 | { | |
ab1d3a0e | 10288 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
10289 | struct drm_crtc *crtc = crtc_state->crtc; |
10290 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e9728bd8 | 10291 | struct intel_plane *plane = to_intel_plane(plane_state->plane); |
da20eabd | 10292 | struct drm_device *dev = crtc->dev; |
ed4a6a7c | 10293 | struct drm_i915_private *dev_priv = to_i915(dev); |
da20eabd | 10294 | struct intel_plane_state *old_plane_state = |
e9728bd8 | 10295 | to_intel_plane_state(plane->base.state); |
da20eabd ML |
10296 | bool mode_changed = needs_modeset(crtc_state); |
10297 | bool was_crtc_enabled = crtc->state->active; | |
10298 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
10299 | bool turn_off, turn_on, visible, was_visible; |
10300 | struct drm_framebuffer *fb = plane_state->fb; | |
78108b7c | 10301 | int ret; |
da20eabd | 10302 | |
e9728bd8 | 10303 | if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) { |
da20eabd ML |
10304 | ret = skl_update_scaler_plane( |
10305 | to_intel_crtc_state(crtc_state), | |
10306 | to_intel_plane_state(plane_state)); | |
10307 | if (ret) | |
10308 | return ret; | |
10309 | } | |
10310 | ||
936e71e3 | 10311 | was_visible = old_plane_state->base.visible; |
1d4258db | 10312 | visible = plane_state->visible; |
da20eabd ML |
10313 | |
10314 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
10315 | was_visible = false; | |
10316 | ||
35c08f43 ML |
10317 | /* |
10318 | * Visibility is calculated as if the crtc was on, but | |
10319 | * after scaler setup everything depends on it being off | |
10320 | * when the crtc isn't active. | |
f818ffea VS |
10321 | * |
10322 | * FIXME this is wrong for watermarks. Watermarks should also | |
10323 | * be computed as if the pipe would be active. Perhaps move | |
10324 | * per-plane wm computation to the .check_plane() hook, and | |
10325 | * only combine the results from all planes in the current place? | |
35c08f43 | 10326 | */ |
e9728bd8 | 10327 | if (!is_crtc_enabled) { |
1d4258db | 10328 | plane_state->visible = visible = false; |
e9728bd8 VS |
10329 | to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id); |
10330 | } | |
da20eabd ML |
10331 | |
10332 | if (!was_visible && !visible) | |
10333 | return 0; | |
10334 | ||
e8861675 ML |
10335 | if (fb != old_plane_state->base.fb) |
10336 | pipe_config->fb_changed = true; | |
10337 | ||
da20eabd ML |
10338 | turn_off = was_visible && (!visible || mode_changed); |
10339 | turn_on = visible && (!was_visible || mode_changed); | |
10340 | ||
72660ce0 | 10341 | DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n", |
e9728bd8 VS |
10342 | intel_crtc->base.base.id, intel_crtc->base.name, |
10343 | plane->base.base.id, plane->base.name, | |
72660ce0 | 10344 | fb ? fb->base.id : -1); |
da20eabd | 10345 | |
72660ce0 | 10346 | DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n", |
e9728bd8 | 10347 | plane->base.base.id, plane->base.name, |
72660ce0 | 10348 | was_visible, visible, |
da20eabd ML |
10349 | turn_off, turn_on, mode_changed); |
10350 | ||
caed361d | 10351 | if (turn_on) { |
04548cba | 10352 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
b4ede6df | 10353 | pipe_config->update_wm_pre = true; |
caed361d VS |
10354 | |
10355 | /* must disable cxsr around plane enable/disable */ | |
e9728bd8 | 10356 | if (plane->id != PLANE_CURSOR) |
caed361d VS |
10357 | pipe_config->disable_cxsr = true; |
10358 | } else if (turn_off) { | |
04548cba | 10359 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
b4ede6df | 10360 | pipe_config->update_wm_post = true; |
92826fcd | 10361 | |
852eb00d | 10362 | /* must disable cxsr around plane enable/disable */ |
e9728bd8 | 10363 | if (plane->id != PLANE_CURSOR) |
ab1d3a0e | 10364 | pipe_config->disable_cxsr = true; |
e9728bd8 | 10365 | } else if (intel_wm_need_update(&plane->base, plane_state)) { |
04548cba | 10366 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) { |
b4ede6df VS |
10367 | /* FIXME bollocks */ |
10368 | pipe_config->update_wm_pre = true; | |
10369 | pipe_config->update_wm_post = true; | |
10370 | } | |
852eb00d | 10371 | } |
da20eabd | 10372 | |
8be6ca85 | 10373 | if (visible || was_visible) |
e9728bd8 | 10374 | pipe_config->fb_bits |= plane->frontbuffer_bit; |
a9ff8714 | 10375 | |
31ae71fc ML |
10376 | /* |
10377 | * WaCxSRDisabledForSpriteScaling:ivb | |
10378 | * | |
10379 | * cstate->update_wm was already set above, so this flag will | |
10380 | * take effect when we commit and program watermarks. | |
10381 | */ | |
e9728bd8 | 10382 | if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) && |
31ae71fc ML |
10383 | needs_scaling(to_intel_plane_state(plane_state)) && |
10384 | !needs_scaling(old_plane_state)) | |
10385 | pipe_config->disable_lp_wm = true; | |
d21fbe87 | 10386 | |
da20eabd ML |
10387 | return 0; |
10388 | } | |
10389 | ||
6d3a1ce7 ML |
10390 | static bool encoders_cloneable(const struct intel_encoder *a, |
10391 | const struct intel_encoder *b) | |
10392 | { | |
10393 | /* masks could be asymmetric, so check both ways */ | |
10394 | return a == b || (a->cloneable & (1 << b->type) && | |
10395 | b->cloneable & (1 << a->type)); | |
10396 | } | |
10397 | ||
10398 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
10399 | struct intel_crtc *crtc, | |
10400 | struct intel_encoder *encoder) | |
10401 | { | |
10402 | struct intel_encoder *source_encoder; | |
10403 | struct drm_connector *connector; | |
10404 | struct drm_connector_state *connector_state; | |
10405 | int i; | |
10406 | ||
aa5e9b47 | 10407 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
6d3a1ce7 ML |
10408 | if (connector_state->crtc != &crtc->base) |
10409 | continue; | |
10410 | ||
10411 | source_encoder = | |
10412 | to_intel_encoder(connector_state->best_encoder); | |
10413 | if (!encoders_cloneable(encoder, source_encoder)) | |
10414 | return false; | |
10415 | } | |
10416 | ||
10417 | return true; | |
10418 | } | |
10419 | ||
6d3a1ce7 ML |
10420 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, |
10421 | struct drm_crtc_state *crtc_state) | |
10422 | { | |
cf5a15be | 10423 | struct drm_device *dev = crtc->dev; |
fac5e23e | 10424 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d3a1ce7 | 10425 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
10426 | struct intel_crtc_state *pipe_config = |
10427 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 10428 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 10429 | int ret; |
6d3a1ce7 ML |
10430 | bool mode_changed = needs_modeset(crtc_state); |
10431 | ||
852eb00d | 10432 | if (mode_changed && !crtc_state->active) |
caed361d | 10433 | pipe_config->update_wm_post = true; |
eddfcbcd | 10434 | |
ad421372 ML |
10435 | if (mode_changed && crtc_state->enable && |
10436 | dev_priv->display.crtc_compute_clock && | |
8106ddbd | 10437 | !WARN_ON(pipe_config->shared_dpll)) { |
ad421372 ML |
10438 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
10439 | pipe_config); | |
10440 | if (ret) | |
10441 | return ret; | |
10442 | } | |
10443 | ||
82cf435b LL |
10444 | if (crtc_state->color_mgmt_changed) { |
10445 | ret = intel_color_check(crtc, crtc_state); | |
10446 | if (ret) | |
10447 | return ret; | |
e7852a4b LL |
10448 | |
10449 | /* | |
10450 | * Changing color management on Intel hardware is | |
10451 | * handled as part of planes update. | |
10452 | */ | |
10453 | crtc_state->planes_changed = true; | |
82cf435b LL |
10454 | } |
10455 | ||
e435d6e5 | 10456 | ret = 0; |
86c8bbbe | 10457 | if (dev_priv->display.compute_pipe_wm) { |
e3bddded | 10458 | ret = dev_priv->display.compute_pipe_wm(pipe_config); |
ed4a6a7c MR |
10459 | if (ret) { |
10460 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
10461 | return ret; | |
10462 | } | |
10463 | } | |
10464 | ||
10465 | if (dev_priv->display.compute_intermediate_wm && | |
10466 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
10467 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
10468 | return 0; | |
10469 | ||
10470 | /* | |
10471 | * Calculate 'intermediate' watermarks that satisfy both the | |
10472 | * old state and the new state. We can program these | |
10473 | * immediately. | |
10474 | */ | |
6315b5d3 | 10475 | ret = dev_priv->display.compute_intermediate_wm(dev, |
ed4a6a7c MR |
10476 | intel_crtc, |
10477 | pipe_config); | |
10478 | if (ret) { | |
10479 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 10480 | return ret; |
ed4a6a7c | 10481 | } |
e3d5457c VS |
10482 | } else if (dev_priv->display.compute_intermediate_wm) { |
10483 | if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9) | |
10484 | pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; | |
86c8bbbe MR |
10485 | } |
10486 | ||
6315b5d3 | 10487 | if (INTEL_GEN(dev_priv) >= 9) { |
e435d6e5 ML |
10488 | if (mode_changed) |
10489 | ret = skl_update_scaler_crtc(pipe_config); | |
10490 | ||
73b0ca8e MK |
10491 | if (!ret) |
10492 | ret = skl_check_pipe_max_pixel_rate(intel_crtc, | |
10493 | pipe_config); | |
e435d6e5 | 10494 | if (!ret) |
6ebc6923 | 10495 | ret = intel_atomic_setup_scalers(dev_priv, intel_crtc, |
e435d6e5 ML |
10496 | pipe_config); |
10497 | } | |
10498 | ||
10499 | return ret; | |
6d3a1ce7 ML |
10500 | } |
10501 | ||
65b38e0d | 10502 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
5a21b665 DV |
10503 | .atomic_begin = intel_begin_crtc_commit, |
10504 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 10505 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
10506 | }; |
10507 | ||
d29b2f9d ACO |
10508 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
10509 | { | |
10510 | struct intel_connector *connector; | |
f9e905ca | 10511 | struct drm_connector_list_iter conn_iter; |
d29b2f9d | 10512 | |
f9e905ca DV |
10513 | drm_connector_list_iter_begin(dev, &conn_iter); |
10514 | for_each_intel_connector_iter(connector, &conn_iter) { | |
8863dc7f DV |
10515 | if (connector->base.state->crtc) |
10516 | drm_connector_unreference(&connector->base); | |
10517 | ||
d29b2f9d ACO |
10518 | if (connector->base.encoder) { |
10519 | connector->base.state->best_encoder = | |
10520 | connector->base.encoder; | |
10521 | connector->base.state->crtc = | |
10522 | connector->base.encoder->crtc; | |
8863dc7f DV |
10523 | |
10524 | drm_connector_reference(&connector->base); | |
d29b2f9d ACO |
10525 | } else { |
10526 | connector->base.state->best_encoder = NULL; | |
10527 | connector->base.state->crtc = NULL; | |
10528 | } | |
10529 | } | |
f9e905ca | 10530 | drm_connector_list_iter_end(&conn_iter); |
d29b2f9d ACO |
10531 | } |
10532 | ||
050f7aeb | 10533 | static void |
eba905b2 | 10534 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 10535 | struct intel_crtc_state *pipe_config) |
050f7aeb | 10536 | { |
6a2a5c5d | 10537 | const struct drm_display_info *info = &connector->base.display_info; |
050f7aeb DV |
10538 | int bpp = pipe_config->pipe_bpp; |
10539 | ||
10540 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
6a2a5c5d VS |
10541 | connector->base.base.id, |
10542 | connector->base.name); | |
050f7aeb DV |
10543 | |
10544 | /* Don't use an invalid EDID bpc value */ | |
6a2a5c5d | 10545 | if (info->bpc != 0 && info->bpc * 3 < bpp) { |
050f7aeb | 10546 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", |
6a2a5c5d VS |
10547 | bpp, info->bpc * 3); |
10548 | pipe_config->pipe_bpp = info->bpc * 3; | |
050f7aeb DV |
10549 | } |
10550 | ||
196f954e | 10551 | /* Clamp bpp to 8 on screens without EDID 1.4 */ |
6a2a5c5d | 10552 | if (info->bpc == 0 && bpp > 24) { |
196f954e MK |
10553 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", |
10554 | bpp); | |
10555 | pipe_config->pipe_bpp = 24; | |
050f7aeb DV |
10556 | } |
10557 | } | |
10558 | ||
4e53c2e0 | 10559 | static int |
050f7aeb | 10560 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 10561 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 10562 | { |
9beb5fea | 10563 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1486017f | 10564 | struct drm_atomic_state *state; |
da3ced29 ACO |
10565 | struct drm_connector *connector; |
10566 | struct drm_connector_state *connector_state; | |
1486017f | 10567 | int bpp, i; |
4e53c2e0 | 10568 | |
9beb5fea TU |
10569 | if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
10570 | IS_CHERRYVIEW(dev_priv))) | |
4e53c2e0 | 10571 | bpp = 10*3; |
9beb5fea | 10572 | else if (INTEL_GEN(dev_priv) >= 5) |
d328c9d7 DV |
10573 | bpp = 12*3; |
10574 | else | |
10575 | bpp = 8*3; | |
10576 | ||
4e53c2e0 | 10577 | |
4e53c2e0 DV |
10578 | pipe_config->pipe_bpp = bpp; |
10579 | ||
1486017f ACO |
10580 | state = pipe_config->base.state; |
10581 | ||
4e53c2e0 | 10582 | /* Clamp display bpp to EDID value */ |
aa5e9b47 | 10583 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
da3ced29 | 10584 | if (connector_state->crtc != &crtc->base) |
4e53c2e0 DV |
10585 | continue; |
10586 | ||
da3ced29 ACO |
10587 | connected_sink_compute_bpp(to_intel_connector(connector), |
10588 | pipe_config); | |
4e53c2e0 DV |
10589 | } |
10590 | ||
10591 | return bpp; | |
10592 | } | |
10593 | ||
644db711 DV |
10594 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
10595 | { | |
10596 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
10597 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 10598 | mode->crtc_clock, |
644db711 DV |
10599 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
10600 | mode->crtc_hsync_end, mode->crtc_htotal, | |
10601 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
10602 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
10603 | } | |
10604 | ||
f6982332 TU |
10605 | static inline void |
10606 | intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id, | |
a4309657 | 10607 | unsigned int lane_count, struct intel_link_m_n *m_n) |
f6982332 | 10608 | { |
a4309657 TU |
10609 | DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
10610 | id, lane_count, | |
f6982332 TU |
10611 | m_n->gmch_m, m_n->gmch_n, |
10612 | m_n->link_m, m_n->link_n, m_n->tu); | |
10613 | } | |
10614 | ||
c0b03411 | 10615 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 10616 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
10617 | const char *context) |
10618 | { | |
6a60cd87 | 10619 | struct drm_device *dev = crtc->base.dev; |
4f8036a2 | 10620 | struct drm_i915_private *dev_priv = to_i915(dev); |
6a60cd87 CK |
10621 | struct drm_plane *plane; |
10622 | struct intel_plane *intel_plane; | |
10623 | struct intel_plane_state *state; | |
10624 | struct drm_framebuffer *fb; | |
10625 | ||
66766e4f TU |
10626 | DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n", |
10627 | crtc->base.base.id, crtc->base.name, context); | |
c0b03411 | 10628 | |
2c89429e TU |
10629 | DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", |
10630 | transcoder_name(pipe_config->cpu_transcoder), | |
c0b03411 | 10631 | pipe_config->pipe_bpp, pipe_config->dither); |
a4309657 TU |
10632 | |
10633 | if (pipe_config->has_pch_encoder) | |
10634 | intel_dump_m_n_config(pipe_config, "fdi", | |
10635 | pipe_config->fdi_lanes, | |
10636 | &pipe_config->fdi_m_n); | |
f6982332 | 10637 | |
b22ca995 SS |
10638 | if (pipe_config->ycbcr420) |
10639 | DRM_DEBUG_KMS("YCbCr 4:2:0 output enabled\n"); | |
10640 | ||
f6982332 | 10641 | if (intel_crtc_has_dp_encoder(pipe_config)) { |
a4309657 TU |
10642 | intel_dump_m_n_config(pipe_config, "dp m_n", |
10643 | pipe_config->lane_count, &pipe_config->dp_m_n); | |
d806e682 TU |
10644 | if (pipe_config->has_drrs) |
10645 | intel_dump_m_n_config(pipe_config, "dp m2_n2", | |
10646 | pipe_config->lane_count, | |
10647 | &pipe_config->dp_m2_n2); | |
f6982332 | 10648 | } |
b95af8be | 10649 | |
55072d19 | 10650 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
2c89429e | 10651 | pipe_config->has_audio, pipe_config->has_infoframe); |
55072d19 | 10652 | |
c0b03411 | 10653 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 10654 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 10655 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
10656 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
10657 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
a7d1b3f4 | 10658 | DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n", |
2c89429e | 10659 | pipe_config->port_clock, |
a7d1b3f4 VS |
10660 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
10661 | pipe_config->pixel_rate); | |
dd2f616d TU |
10662 | |
10663 | if (INTEL_GEN(dev_priv) >= 9) | |
10664 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", | |
10665 | crtc->num_scalers, | |
10666 | pipe_config->scaler_state.scaler_users, | |
10667 | pipe_config->scaler_state.scaler_id); | |
a74f8375 TU |
10668 | |
10669 | if (HAS_GMCH_DISPLAY(dev_priv)) | |
10670 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", | |
10671 | pipe_config->gmch_pfit.control, | |
10672 | pipe_config->gmch_pfit.pgm_ratios, | |
10673 | pipe_config->gmch_pfit.lvds_border_bits); | |
10674 | else | |
10675 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", | |
10676 | pipe_config->pch_pfit.pos, | |
10677 | pipe_config->pch_pfit.size, | |
08c4d7fc | 10678 | enableddisabled(pipe_config->pch_pfit.enabled)); |
a74f8375 | 10679 | |
2c89429e TU |
10680 | DRM_DEBUG_KMS("ips: %i, double wide: %i\n", |
10681 | pipe_config->ips_enabled, pipe_config->double_wide); | |
6a60cd87 | 10682 | |
f50b79f0 | 10683 | intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state); |
415ff0f6 | 10684 | |
6a60cd87 CK |
10685 | DRM_DEBUG_KMS("planes on this crtc\n"); |
10686 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
b3c11ac2 | 10687 | struct drm_format_name_buf format_name; |
6a60cd87 CK |
10688 | intel_plane = to_intel_plane(plane); |
10689 | if (intel_plane->pipe != crtc->pipe) | |
10690 | continue; | |
10691 | ||
10692 | state = to_intel_plane_state(plane->state); | |
10693 | fb = state->base.fb; | |
10694 | if (!fb) { | |
1d577e02 VS |
10695 | DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n", |
10696 | plane->base.id, plane->name, state->scaler_id); | |
6a60cd87 CK |
10697 | continue; |
10698 | } | |
10699 | ||
dd2f616d TU |
10700 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n", |
10701 | plane->base.id, plane->name, | |
b3c11ac2 | 10702 | fb->base.id, fb->width, fb->height, |
438b74a5 | 10703 | drm_get_format_name(fb->format->format, &format_name)); |
dd2f616d TU |
10704 | if (INTEL_GEN(dev_priv) >= 9) |
10705 | DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n", | |
10706 | state->scaler_id, | |
10707 | state->base.src.x1 >> 16, | |
10708 | state->base.src.y1 >> 16, | |
10709 | drm_rect_width(&state->base.src) >> 16, | |
10710 | drm_rect_height(&state->base.src) >> 16, | |
10711 | state->base.dst.x1, state->base.dst.y1, | |
10712 | drm_rect_width(&state->base.dst), | |
10713 | drm_rect_height(&state->base.dst)); | |
6a60cd87 | 10714 | } |
c0b03411 DV |
10715 | } |
10716 | ||
5448a00d | 10717 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 10718 | { |
5448a00d | 10719 | struct drm_device *dev = state->dev; |
da3ced29 | 10720 | struct drm_connector *connector; |
2fd96b41 | 10721 | struct drm_connector_list_iter conn_iter; |
00f0b378 | 10722 | unsigned int used_ports = 0; |
477321e0 | 10723 | unsigned int used_mst_ports = 0; |
00f0b378 VS |
10724 | |
10725 | /* | |
10726 | * Walk the connector list instead of the encoder | |
10727 | * list to detect the problem on ddi platforms | |
10728 | * where there's just one encoder per digital port. | |
10729 | */ | |
2fd96b41 GP |
10730 | drm_connector_list_iter_begin(dev, &conn_iter); |
10731 | drm_for_each_connector_iter(connector, &conn_iter) { | |
0bff4858 VS |
10732 | struct drm_connector_state *connector_state; |
10733 | struct intel_encoder *encoder; | |
10734 | ||
10735 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
10736 | if (!connector_state) | |
10737 | connector_state = connector->state; | |
10738 | ||
5448a00d | 10739 | if (!connector_state->best_encoder) |
00f0b378 VS |
10740 | continue; |
10741 | ||
5448a00d ACO |
10742 | encoder = to_intel_encoder(connector_state->best_encoder); |
10743 | ||
10744 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
10745 | |
10746 | switch (encoder->type) { | |
10747 | unsigned int port_mask; | |
10748 | case INTEL_OUTPUT_UNKNOWN: | |
4f8036a2 | 10749 | if (WARN_ON(!HAS_DDI(to_i915(dev)))) |
00f0b378 | 10750 | break; |
cca0502b | 10751 | case INTEL_OUTPUT_DP: |
00f0b378 VS |
10752 | case INTEL_OUTPUT_HDMI: |
10753 | case INTEL_OUTPUT_EDP: | |
10754 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
10755 | ||
10756 | /* the same port mustn't appear more than once */ | |
10757 | if (used_ports & port_mask) | |
10758 | return false; | |
10759 | ||
10760 | used_ports |= port_mask; | |
477321e0 VS |
10761 | break; |
10762 | case INTEL_OUTPUT_DP_MST: | |
10763 | used_mst_ports |= | |
10764 | 1 << enc_to_mst(&encoder->base)->primary->port; | |
10765 | break; | |
00f0b378 VS |
10766 | default: |
10767 | break; | |
10768 | } | |
10769 | } | |
2fd96b41 | 10770 | drm_connector_list_iter_end(&conn_iter); |
00f0b378 | 10771 | |
477321e0 VS |
10772 | /* can't mix MST and SST/HDMI on the same port */ |
10773 | if (used_ports & used_mst_ports) | |
10774 | return false; | |
10775 | ||
00f0b378 VS |
10776 | return true; |
10777 | } | |
10778 | ||
83a57153 ACO |
10779 | static void |
10780 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
10781 | { | |
ff32c54e VS |
10782 | struct drm_i915_private *dev_priv = |
10783 | to_i915(crtc_state->base.crtc->dev); | |
663a3640 | 10784 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 | 10785 | struct intel_dpll_hw_state dpll_hw_state; |
8106ddbd | 10786 | struct intel_shared_dpll *shared_dpll; |
ff32c54e | 10787 | struct intel_crtc_wm_state wm_state; |
c4e2d043 | 10788 | bool force_thru; |
83a57153 | 10789 | |
7546a384 ACO |
10790 | /* FIXME: before the switch to atomic started, a new pipe_config was |
10791 | * kzalloc'd. Code that depends on any field being zero should be | |
10792 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
10793 | * only fields that are know to not cause problems are preserved. */ | |
10794 | ||
663a3640 | 10795 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
10796 | shared_dpll = crtc_state->shared_dpll; |
10797 | dpll_hw_state = crtc_state->dpll_hw_state; | |
c4e2d043 | 10798 | force_thru = crtc_state->pch_pfit.force_thru; |
04548cba VS |
10799 | if (IS_G4X(dev_priv) || |
10800 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
ff32c54e | 10801 | wm_state = crtc_state->wm; |
4978cc93 | 10802 | |
d2fa80a5 CW |
10803 | /* Keep base drm_crtc_state intact, only clear our extended struct */ |
10804 | BUILD_BUG_ON(offsetof(struct intel_crtc_state, base)); | |
10805 | memset(&crtc_state->base + 1, 0, | |
10806 | sizeof(*crtc_state) - sizeof(crtc_state->base)); | |
4978cc93 | 10807 | |
663a3640 | 10808 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
10809 | crtc_state->shared_dpll = shared_dpll; |
10810 | crtc_state->dpll_hw_state = dpll_hw_state; | |
c4e2d043 | 10811 | crtc_state->pch_pfit.force_thru = force_thru; |
04548cba VS |
10812 | if (IS_G4X(dev_priv) || |
10813 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
ff32c54e | 10814 | crtc_state->wm = wm_state; |
83a57153 ACO |
10815 | } |
10816 | ||
548ee15b | 10817 | static int |
b8cecdf5 | 10818 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 10819 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 10820 | { |
b359283a | 10821 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 10822 | struct intel_encoder *encoder; |
da3ced29 | 10823 | struct drm_connector *connector; |
0b901879 | 10824 | struct drm_connector_state *connector_state; |
d328c9d7 | 10825 | int base_bpp, ret = -EINVAL; |
0b901879 | 10826 | int i; |
e29c22c0 | 10827 | bool retry = true; |
ee7b9f93 | 10828 | |
83a57153 | 10829 | clear_intel_crtc_state(pipe_config); |
7758a113 | 10830 | |
e143a21c DV |
10831 | pipe_config->cpu_transcoder = |
10832 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 10833 | |
2960bc9c ID |
10834 | /* |
10835 | * Sanitize sync polarity flags based on requested ones. If neither | |
10836 | * positive or negative polarity is requested, treat this as meaning | |
10837 | * negative polarity. | |
10838 | */ | |
2d112de7 | 10839 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 10840 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 10841 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 10842 | |
2d112de7 | 10843 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 10844 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 10845 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 10846 | |
d328c9d7 DV |
10847 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
10848 | pipe_config); | |
10849 | if (base_bpp < 0) | |
4e53c2e0 DV |
10850 | goto fail; |
10851 | ||
e41a56be VS |
10852 | /* |
10853 | * Determine the real pipe dimensions. Note that stereo modes can | |
10854 | * increase the actual pipe size due to the frame doubling and | |
10855 | * insertion of additional space for blanks between the frame. This | |
10856 | * is stored in the crtc timings. We use the requested mode to do this | |
10857 | * computation to clearly distinguish it from the adjusted mode, which | |
10858 | * can be changed by the connectors in the below retry loop. | |
10859 | */ | |
196cd5d3 | 10860 | drm_mode_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
10861 | &pipe_config->pipe_src_w, |
10862 | &pipe_config->pipe_src_h); | |
e41a56be | 10863 | |
aa5e9b47 | 10864 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
253c84c8 VS |
10865 | if (connector_state->crtc != crtc) |
10866 | continue; | |
10867 | ||
10868 | encoder = to_intel_encoder(connector_state->best_encoder); | |
10869 | ||
e25148d0 VS |
10870 | if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) { |
10871 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
10872 | goto fail; | |
10873 | } | |
10874 | ||
253c84c8 VS |
10875 | /* |
10876 | * Determine output_types before calling the .compute_config() | |
10877 | * hooks so that the hooks can use this information safely. | |
10878 | */ | |
10879 | pipe_config->output_types |= 1 << encoder->type; | |
10880 | } | |
10881 | ||
e29c22c0 | 10882 | encoder_retry: |
ef1b460d | 10883 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 10884 | pipe_config->port_clock = 0; |
ef1b460d | 10885 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 10886 | |
135c81b8 | 10887 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
10888 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
10889 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 10890 | |
7758a113 DV |
10891 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
10892 | * adjust it according to limitations or connector properties, and also | |
10893 | * a chance to reject the mode entirely. | |
47f1c6c9 | 10894 | */ |
aa5e9b47 | 10895 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 10896 | if (connector_state->crtc != crtc) |
7758a113 | 10897 | continue; |
7ae89233 | 10898 | |
0b901879 ACO |
10899 | encoder = to_intel_encoder(connector_state->best_encoder); |
10900 | ||
0a478c27 | 10901 | if (!(encoder->compute_config(encoder, pipe_config, connector_state))) { |
efea6e8e | 10902 | DRM_DEBUG_KMS("Encoder config failure\n"); |
7758a113 DV |
10903 | goto fail; |
10904 | } | |
ee7b9f93 | 10905 | } |
47f1c6c9 | 10906 | |
ff9a6750 DV |
10907 | /* Set default port clock if not overwritten by the encoder. Needs to be |
10908 | * done afterwards in case the encoder adjusts the mode. */ | |
10909 | if (!pipe_config->port_clock) | |
2d112de7 | 10910 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 10911 | * pipe_config->pixel_multiplier; |
ff9a6750 | 10912 | |
a43f6e0f | 10913 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 10914 | if (ret < 0) { |
7758a113 DV |
10915 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
10916 | goto fail; | |
ee7b9f93 | 10917 | } |
e29c22c0 DV |
10918 | |
10919 | if (ret == RETRY) { | |
10920 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
10921 | ret = -EINVAL; | |
10922 | goto fail; | |
10923 | } | |
10924 | ||
10925 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
10926 | retry = false; | |
10927 | goto encoder_retry; | |
10928 | } | |
10929 | ||
e8fa4270 | 10930 | /* Dithering seems to not pass-through bits correctly when it should, so |
611032bf MN |
10931 | * only enable it on 6bpc panels and when its not a compliance |
10932 | * test requesting 6bpc video pattern. | |
10933 | */ | |
10934 | pipe_config->dither = (pipe_config->pipe_bpp == 6*3) && | |
10935 | !pipe_config->dither_force_disable; | |
62f0ace5 | 10936 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 10937 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 10938 | |
7758a113 | 10939 | fail: |
548ee15b | 10940 | return ret; |
ee7b9f93 | 10941 | } |
47f1c6c9 | 10942 | |
ea9d758d | 10943 | static void |
4740b0f2 | 10944 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 10945 | { |
0a9ab303 | 10946 | struct drm_crtc *crtc; |
aa5e9b47 | 10947 | struct drm_crtc_state *new_crtc_state; |
8a75d157 | 10948 | int i; |
ea9d758d | 10949 | |
7668851f | 10950 | /* Double check state. */ |
aa5e9b47 ML |
10951 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
10952 | to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state); | |
fc467a22 | 10953 | |
61067a5e ML |
10954 | /* |
10955 | * Update legacy state to satisfy fbc code. This can | |
10956 | * be removed when fbc uses the atomic state. | |
10957 | */ | |
10958 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
10959 | struct drm_plane_state *plane_state = crtc->primary->state; | |
10960 | ||
10961 | crtc->primary->fb = plane_state->fb; | |
10962 | crtc->x = plane_state->src_x >> 16; | |
10963 | crtc->y = plane_state->src_y >> 16; | |
10964 | } | |
ea9d758d | 10965 | } |
ea9d758d DV |
10966 | } |
10967 | ||
3bd26263 | 10968 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 10969 | { |
3bd26263 | 10970 | int diff; |
f1f644dc JB |
10971 | |
10972 | if (clock1 == clock2) | |
10973 | return true; | |
10974 | ||
10975 | if (!clock1 || !clock2) | |
10976 | return false; | |
10977 | ||
10978 | diff = abs(clock1 - clock2); | |
10979 | ||
10980 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
10981 | return true; | |
10982 | ||
10983 | return false; | |
10984 | } | |
10985 | ||
cfb23ed6 ML |
10986 | static bool |
10987 | intel_compare_m_n(unsigned int m, unsigned int n, | |
10988 | unsigned int m2, unsigned int n2, | |
10989 | bool exact) | |
10990 | { | |
10991 | if (m == m2 && n == n2) | |
10992 | return true; | |
10993 | ||
10994 | if (exact || !m || !n || !m2 || !n2) | |
10995 | return false; | |
10996 | ||
10997 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
10998 | ||
31d10b57 ML |
10999 | if (n > n2) { |
11000 | while (n > n2) { | |
cfb23ed6 ML |
11001 | m2 <<= 1; |
11002 | n2 <<= 1; | |
11003 | } | |
31d10b57 ML |
11004 | } else if (n < n2) { |
11005 | while (n < n2) { | |
cfb23ed6 ML |
11006 | m <<= 1; |
11007 | n <<= 1; | |
11008 | } | |
11009 | } | |
11010 | ||
31d10b57 ML |
11011 | if (n != n2) |
11012 | return false; | |
11013 | ||
11014 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
11015 | } |
11016 | ||
11017 | static bool | |
11018 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
11019 | struct intel_link_m_n *m2_n2, | |
11020 | bool adjust) | |
11021 | { | |
11022 | if (m_n->tu == m2_n2->tu && | |
11023 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
11024 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
11025 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
11026 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
11027 | if (adjust) | |
11028 | *m2_n2 = *m_n; | |
11029 | ||
11030 | return true; | |
11031 | } | |
11032 | ||
11033 | return false; | |
11034 | } | |
11035 | ||
4e8048f8 TU |
11036 | static void __printf(3, 4) |
11037 | pipe_config_err(bool adjust, const char *name, const char *format, ...) | |
11038 | { | |
11039 | char *level; | |
11040 | unsigned int category; | |
11041 | struct va_format vaf; | |
11042 | va_list args; | |
11043 | ||
11044 | if (adjust) { | |
11045 | level = KERN_DEBUG; | |
11046 | category = DRM_UT_KMS; | |
11047 | } else { | |
11048 | level = KERN_ERR; | |
11049 | category = DRM_UT_NONE; | |
11050 | } | |
11051 | ||
11052 | va_start(args, format); | |
11053 | vaf.fmt = format; | |
11054 | vaf.va = &args; | |
11055 | ||
11056 | drm_printk(level, category, "mismatch in %s %pV", name, &vaf); | |
11057 | ||
11058 | va_end(args); | |
11059 | } | |
11060 | ||
0e8ffe1b | 11061 | static bool |
6315b5d3 | 11062 | intel_pipe_config_compare(struct drm_i915_private *dev_priv, |
5cec258b | 11063 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
11064 | struct intel_crtc_state *pipe_config, |
11065 | bool adjust) | |
0e8ffe1b | 11066 | { |
cfb23ed6 ML |
11067 | bool ret = true; |
11068 | ||
66e985c0 DV |
11069 | #define PIPE_CONF_CHECK_X(name) \ |
11070 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 11071 | pipe_config_err(adjust, __stringify(name), \ |
66e985c0 DV |
11072 | "(expected 0x%08x, found 0x%08x)\n", \ |
11073 | current_config->name, \ | |
11074 | pipe_config->name); \ | |
cfb23ed6 | 11075 | ret = false; \ |
66e985c0 DV |
11076 | } |
11077 | ||
08a24034 DV |
11078 | #define PIPE_CONF_CHECK_I(name) \ |
11079 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 11080 | pipe_config_err(adjust, __stringify(name), \ |
08a24034 DV |
11081 | "(expected %i, found %i)\n", \ |
11082 | current_config->name, \ | |
11083 | pipe_config->name); \ | |
cfb23ed6 ML |
11084 | ret = false; \ |
11085 | } | |
11086 | ||
8106ddbd ACO |
11087 | #define PIPE_CONF_CHECK_P(name) \ |
11088 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 11089 | pipe_config_err(adjust, __stringify(name), \ |
8106ddbd ACO |
11090 | "(expected %p, found %p)\n", \ |
11091 | current_config->name, \ | |
11092 | pipe_config->name); \ | |
11093 | ret = false; \ | |
11094 | } | |
11095 | ||
cfb23ed6 ML |
11096 | #define PIPE_CONF_CHECK_M_N(name) \ |
11097 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
11098 | &pipe_config->name,\ | |
11099 | adjust)) { \ | |
4e8048f8 | 11100 | pipe_config_err(adjust, __stringify(name), \ |
cfb23ed6 ML |
11101 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
11102 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
11103 | current_config->name.tu, \ | |
11104 | current_config->name.gmch_m, \ | |
11105 | current_config->name.gmch_n, \ | |
11106 | current_config->name.link_m, \ | |
11107 | current_config->name.link_n, \ | |
11108 | pipe_config->name.tu, \ | |
11109 | pipe_config->name.gmch_m, \ | |
11110 | pipe_config->name.gmch_n, \ | |
11111 | pipe_config->name.link_m, \ | |
11112 | pipe_config->name.link_n); \ | |
11113 | ret = false; \ | |
11114 | } | |
11115 | ||
55c561a7 DV |
11116 | /* This is required for BDW+ where there is only one set of registers for |
11117 | * switching between high and low RR. | |
11118 | * This macro can be used whenever a comparison has to be made between one | |
11119 | * hw state and multiple sw state variables. | |
11120 | */ | |
cfb23ed6 ML |
11121 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ |
11122 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
11123 | &pipe_config->name, adjust) && \ | |
11124 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
11125 | &pipe_config->name, adjust)) { \ | |
4e8048f8 | 11126 | pipe_config_err(adjust, __stringify(name), \ |
cfb23ed6 ML |
11127 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
11128 | "or tu %i gmch %i/%i link %i/%i, " \ | |
11129 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
11130 | current_config->name.tu, \ | |
11131 | current_config->name.gmch_m, \ | |
11132 | current_config->name.gmch_n, \ | |
11133 | current_config->name.link_m, \ | |
11134 | current_config->name.link_n, \ | |
11135 | current_config->alt_name.tu, \ | |
11136 | current_config->alt_name.gmch_m, \ | |
11137 | current_config->alt_name.gmch_n, \ | |
11138 | current_config->alt_name.link_m, \ | |
11139 | current_config->alt_name.link_n, \ | |
11140 | pipe_config->name.tu, \ | |
11141 | pipe_config->name.gmch_m, \ | |
11142 | pipe_config->name.gmch_n, \ | |
11143 | pipe_config->name.link_m, \ | |
11144 | pipe_config->name.link_n); \ | |
11145 | ret = false; \ | |
88adfff1 DV |
11146 | } |
11147 | ||
1bd1bd80 DV |
11148 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
11149 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
4e8048f8 TU |
11150 | pipe_config_err(adjust, __stringify(name), \ |
11151 | "(%x) (expected %i, found %i)\n", \ | |
11152 | (mask), \ | |
1bd1bd80 DV |
11153 | current_config->name & (mask), \ |
11154 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 11155 | ret = false; \ |
1bd1bd80 DV |
11156 | } |
11157 | ||
5e550656 VS |
11158 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
11159 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
4e8048f8 | 11160 | pipe_config_err(adjust, __stringify(name), \ |
5e550656 VS |
11161 | "(expected %i, found %i)\n", \ |
11162 | current_config->name, \ | |
11163 | pipe_config->name); \ | |
cfb23ed6 | 11164 | ret = false; \ |
5e550656 VS |
11165 | } |
11166 | ||
bb760063 DV |
11167 | #define PIPE_CONF_QUIRK(quirk) \ |
11168 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
11169 | ||
eccb140b DV |
11170 | PIPE_CONF_CHECK_I(cpu_transcoder); |
11171 | ||
08a24034 DV |
11172 | PIPE_CONF_CHECK_I(has_pch_encoder); |
11173 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 11174 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 11175 | |
90a6b7b0 | 11176 | PIPE_CONF_CHECK_I(lane_count); |
95a7a2ae | 11177 | PIPE_CONF_CHECK_X(lane_lat_optim_mask); |
b95af8be | 11178 | |
6315b5d3 | 11179 | if (INTEL_GEN(dev_priv) < 8) { |
cfb23ed6 ML |
11180 | PIPE_CONF_CHECK_M_N(dp_m_n); |
11181 | ||
cfb23ed6 ML |
11182 | if (current_config->has_drrs) |
11183 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
11184 | } else | |
11185 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 11186 | |
253c84c8 | 11187 | PIPE_CONF_CHECK_X(output_types); |
a65347ba | 11188 | |
2d112de7 ACO |
11189 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
11190 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
11191 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
11192 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
11193 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
11194 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 11195 | |
2d112de7 ACO |
11196 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
11197 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
11198 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
11199 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
11200 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
11201 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 11202 | |
c93f54cf | 11203 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 11204 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
772c2a51 | 11205 | if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || |
920a14b2 | 11206 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
b5a9fa09 | 11207 | PIPE_CONF_CHECK_I(limited_color_range); |
15953637 SS |
11208 | |
11209 | PIPE_CONF_CHECK_I(hdmi_scrambling); | |
11210 | PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio); | |
e43823ec | 11211 | PIPE_CONF_CHECK_I(has_infoframe); |
60436fd4 | 11212 | PIPE_CONF_CHECK_I(ycbcr420); |
6c49f241 | 11213 | |
9ed109a7 DV |
11214 | PIPE_CONF_CHECK_I(has_audio); |
11215 | ||
2d112de7 | 11216 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
11217 | DRM_MODE_FLAG_INTERLACE); |
11218 | ||
bb760063 | 11219 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 11220 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11221 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 11222 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11223 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 11224 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11225 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 11226 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
11227 | DRM_MODE_FLAG_NVSYNC); |
11228 | } | |
045ac3b5 | 11229 | |
333b8ca8 | 11230 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a | 11231 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
6315b5d3 | 11232 | if (INTEL_GEN(dev_priv) < 4) |
7f7d8dd6 | 11233 | PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); |
333b8ca8 | 11234 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 11235 | |
bfd16b2a ML |
11236 | if (!adjust) { |
11237 | PIPE_CONF_CHECK_I(pipe_src_w); | |
11238 | PIPE_CONF_CHECK_I(pipe_src_h); | |
11239 | ||
11240 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
11241 | if (current_config->pch_pfit.enabled) { | |
11242 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
11243 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
11244 | } | |
2fa2fe9a | 11245 | |
7aefe2b5 | 11246 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
a7d1b3f4 | 11247 | PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate); |
7aefe2b5 | 11248 | } |
a1b2278e | 11249 | |
e59150dc | 11250 | /* BDW+ don't expose a synchronous way to read the state */ |
772c2a51 | 11251 | if (IS_HASWELL(dev_priv)) |
e59150dc | 11252 | PIPE_CONF_CHECK_I(ips_enabled); |
42db64ef | 11253 | |
282740f7 VS |
11254 | PIPE_CONF_CHECK_I(double_wide); |
11255 | ||
8106ddbd | 11256 | PIPE_CONF_CHECK_P(shared_dpll); |
66e985c0 | 11257 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 11258 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
11259 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
11260 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 11261 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 11262 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
11263 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
11264 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
11265 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 11266 | |
47eacbab VS |
11267 | PIPE_CONF_CHECK_X(dsi_pll.ctrl); |
11268 | PIPE_CONF_CHECK_X(dsi_pll.div); | |
11269 | ||
9beb5fea | 11270 | if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) |
42571aef VS |
11271 | PIPE_CONF_CHECK_I(pipe_bpp); |
11272 | ||
2d112de7 | 11273 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 11274 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 11275 | |
66e985c0 | 11276 | #undef PIPE_CONF_CHECK_X |
08a24034 | 11277 | #undef PIPE_CONF_CHECK_I |
8106ddbd | 11278 | #undef PIPE_CONF_CHECK_P |
1bd1bd80 | 11279 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 11280 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 11281 | #undef PIPE_CONF_QUIRK |
88adfff1 | 11282 | |
cfb23ed6 | 11283 | return ret; |
0e8ffe1b DV |
11284 | } |
11285 | ||
e3b247da VS |
11286 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
11287 | const struct intel_crtc_state *pipe_config) | |
11288 | { | |
11289 | if (pipe_config->has_pch_encoder) { | |
21a727b3 | 11290 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
e3b247da VS |
11291 | &pipe_config->fdi_m_n); |
11292 | int dotclock = pipe_config->base.adjusted_mode.crtc_clock; | |
11293 | ||
11294 | /* | |
11295 | * FDI already provided one idea for the dotclock. | |
11296 | * Yell if the encoder disagrees. | |
11297 | */ | |
11298 | WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
11299 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
11300 | fdi_dotclock, dotclock); | |
11301 | } | |
11302 | } | |
11303 | ||
c0ead703 ML |
11304 | static void verify_wm_state(struct drm_crtc *crtc, |
11305 | struct drm_crtc_state *new_state) | |
08db6652 | 11306 | { |
6315b5d3 | 11307 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
08db6652 | 11308 | struct skl_ddb_allocation hw_ddb, *sw_ddb; |
3de8a14c | 11309 | struct skl_pipe_wm hw_wm, *sw_wm; |
11310 | struct skl_plane_wm *hw_plane_wm, *sw_plane_wm; | |
11311 | struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; | |
e7c84544 ML |
11312 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11313 | const enum pipe pipe = intel_crtc->pipe; | |
3de8a14c | 11314 | int plane, level, max_level = ilk_wm_max_level(dev_priv); |
08db6652 | 11315 | |
6315b5d3 | 11316 | if (INTEL_GEN(dev_priv) < 9 || !new_state->active) |
08db6652 DL |
11317 | return; |
11318 | ||
3de8a14c | 11319 | skl_pipe_wm_get_hw_state(crtc, &hw_wm); |
03af79e0 | 11320 | sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal; |
3de8a14c | 11321 | |
08db6652 DL |
11322 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); |
11323 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
11324 | ||
e7c84544 | 11325 | /* planes */ |
8b364b41 | 11326 | for_each_universal_plane(dev_priv, pipe, plane) { |
3de8a14c | 11327 | hw_plane_wm = &hw_wm.planes[plane]; |
11328 | sw_plane_wm = &sw_wm->planes[plane]; | |
08db6652 | 11329 | |
3de8a14c | 11330 | /* Watermarks */ |
11331 | for (level = 0; level <= max_level; level++) { | |
11332 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
11333 | &sw_plane_wm->wm[level])) | |
11334 | continue; | |
11335 | ||
11336 | DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11337 | pipe_name(pipe), plane + 1, level, | |
11338 | sw_plane_wm->wm[level].plane_en, | |
11339 | sw_plane_wm->wm[level].plane_res_b, | |
11340 | sw_plane_wm->wm[level].plane_res_l, | |
11341 | hw_plane_wm->wm[level].plane_en, | |
11342 | hw_plane_wm->wm[level].plane_res_b, | |
11343 | hw_plane_wm->wm[level].plane_res_l); | |
11344 | } | |
08db6652 | 11345 | |
3de8a14c | 11346 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, |
11347 | &sw_plane_wm->trans_wm)) { | |
11348 | DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11349 | pipe_name(pipe), plane + 1, | |
11350 | sw_plane_wm->trans_wm.plane_en, | |
11351 | sw_plane_wm->trans_wm.plane_res_b, | |
11352 | sw_plane_wm->trans_wm.plane_res_l, | |
11353 | hw_plane_wm->trans_wm.plane_en, | |
11354 | hw_plane_wm->trans_wm.plane_res_b, | |
11355 | hw_plane_wm->trans_wm.plane_res_l); | |
11356 | } | |
11357 | ||
11358 | /* DDB */ | |
11359 | hw_ddb_entry = &hw_ddb.plane[pipe][plane]; | |
11360 | sw_ddb_entry = &sw_ddb->plane[pipe][plane]; | |
11361 | ||
11362 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { | |
faccd994 | 11363 | DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n", |
3de8a14c | 11364 | pipe_name(pipe), plane + 1, |
11365 | sw_ddb_entry->start, sw_ddb_entry->end, | |
11366 | hw_ddb_entry->start, hw_ddb_entry->end); | |
11367 | } | |
e7c84544 | 11368 | } |
08db6652 | 11369 | |
27082493 L |
11370 | /* |
11371 | * cursor | |
11372 | * If the cursor plane isn't active, we may not have updated it's ddb | |
11373 | * allocation. In that case since the ddb allocation will be updated | |
11374 | * once the plane becomes visible, we can skip this check | |
11375 | */ | |
cd5dcbf1 | 11376 | if (1) { |
3de8a14c | 11377 | hw_plane_wm = &hw_wm.planes[PLANE_CURSOR]; |
11378 | sw_plane_wm = &sw_wm->planes[PLANE_CURSOR]; | |
11379 | ||
11380 | /* Watermarks */ | |
11381 | for (level = 0; level <= max_level; level++) { | |
11382 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
11383 | &sw_plane_wm->wm[level])) | |
11384 | continue; | |
11385 | ||
11386 | DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11387 | pipe_name(pipe), level, | |
11388 | sw_plane_wm->wm[level].plane_en, | |
11389 | sw_plane_wm->wm[level].plane_res_b, | |
11390 | sw_plane_wm->wm[level].plane_res_l, | |
11391 | hw_plane_wm->wm[level].plane_en, | |
11392 | hw_plane_wm->wm[level].plane_res_b, | |
11393 | hw_plane_wm->wm[level].plane_res_l); | |
11394 | } | |
11395 | ||
11396 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, | |
11397 | &sw_plane_wm->trans_wm)) { | |
11398 | DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11399 | pipe_name(pipe), | |
11400 | sw_plane_wm->trans_wm.plane_en, | |
11401 | sw_plane_wm->trans_wm.plane_res_b, | |
11402 | sw_plane_wm->trans_wm.plane_res_l, | |
11403 | hw_plane_wm->trans_wm.plane_en, | |
11404 | hw_plane_wm->trans_wm.plane_res_b, | |
11405 | hw_plane_wm->trans_wm.plane_res_l); | |
11406 | } | |
11407 | ||
11408 | /* DDB */ | |
11409 | hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; | |
11410 | sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
27082493 | 11411 | |
3de8a14c | 11412 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { |
faccd994 | 11413 | DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n", |
27082493 | 11414 | pipe_name(pipe), |
3de8a14c | 11415 | sw_ddb_entry->start, sw_ddb_entry->end, |
11416 | hw_ddb_entry->start, hw_ddb_entry->end); | |
27082493 | 11417 | } |
08db6652 DL |
11418 | } |
11419 | } | |
11420 | ||
91d1b4bd | 11421 | static void |
677100ce ML |
11422 | verify_connector_state(struct drm_device *dev, |
11423 | struct drm_atomic_state *state, | |
11424 | struct drm_crtc *crtc) | |
8af6cf88 | 11425 | { |
35dd3c64 | 11426 | struct drm_connector *connector; |
aa5e9b47 | 11427 | struct drm_connector_state *new_conn_state; |
677100ce | 11428 | int i; |
8af6cf88 | 11429 | |
aa5e9b47 | 11430 | for_each_new_connector_in_state(state, connector, new_conn_state, i) { |
35dd3c64 | 11431 | struct drm_encoder *encoder = connector->encoder; |
749d98b8 | 11432 | struct drm_crtc_state *crtc_state = NULL; |
ad3c558f | 11433 | |
aa5e9b47 | 11434 | if (new_conn_state->crtc != crtc) |
e7c84544 ML |
11435 | continue; |
11436 | ||
749d98b8 ML |
11437 | if (crtc) |
11438 | crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc); | |
11439 | ||
11440 | intel_connector_verify_state(crtc_state, new_conn_state); | |
8af6cf88 | 11441 | |
aa5e9b47 | 11442 | I915_STATE_WARN(new_conn_state->best_encoder != encoder, |
35dd3c64 | 11443 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 11444 | } |
91d1b4bd DV |
11445 | } |
11446 | ||
11447 | static void | |
86b04268 | 11448 | verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state) |
91d1b4bd DV |
11449 | { |
11450 | struct intel_encoder *encoder; | |
86b04268 DV |
11451 | struct drm_connector *connector; |
11452 | struct drm_connector_state *old_conn_state, *new_conn_state; | |
11453 | int i; | |
8af6cf88 | 11454 | |
b2784e15 | 11455 | for_each_intel_encoder(dev, encoder) { |
86b04268 | 11456 | bool enabled = false, found = false; |
4d20cd86 | 11457 | enum pipe pipe; |
8af6cf88 DV |
11458 | |
11459 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
11460 | encoder->base.base.id, | |
8e329a03 | 11461 | encoder->base.name); |
8af6cf88 | 11462 | |
86b04268 DV |
11463 | for_each_oldnew_connector_in_state(state, connector, old_conn_state, |
11464 | new_conn_state, i) { | |
11465 | if (old_conn_state->best_encoder == &encoder->base) | |
11466 | found = true; | |
11467 | ||
11468 | if (new_conn_state->best_encoder != &encoder->base) | |
8af6cf88 | 11469 | continue; |
86b04268 | 11470 | found = enabled = true; |
ad3c558f | 11471 | |
86b04268 | 11472 | I915_STATE_WARN(new_conn_state->crtc != |
ad3c558f ML |
11473 | encoder->base.crtc, |
11474 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 11475 | } |
86b04268 DV |
11476 | |
11477 | if (!found) | |
11478 | continue; | |
0e32b39c | 11479 | |
e2c719b7 | 11480 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
11481 | "encoder's enabled state mismatch " |
11482 | "(expected %i, found %i)\n", | |
11483 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
11484 | |
11485 | if (!encoder->base.crtc) { | |
4d20cd86 | 11486 | bool active; |
7c60d198 | 11487 | |
4d20cd86 ML |
11488 | active = encoder->get_hw_state(encoder, &pipe); |
11489 | I915_STATE_WARN(active, | |
11490 | "encoder detached but still enabled on pipe %c.\n", | |
11491 | pipe_name(pipe)); | |
7c60d198 | 11492 | } |
8af6cf88 | 11493 | } |
91d1b4bd DV |
11494 | } |
11495 | ||
11496 | static void | |
c0ead703 ML |
11497 | verify_crtc_state(struct drm_crtc *crtc, |
11498 | struct drm_crtc_state *old_crtc_state, | |
11499 | struct drm_crtc_state *new_crtc_state) | |
91d1b4bd | 11500 | { |
e7c84544 | 11501 | struct drm_device *dev = crtc->dev; |
fac5e23e | 11502 | struct drm_i915_private *dev_priv = to_i915(dev); |
91d1b4bd | 11503 | struct intel_encoder *encoder; |
e7c84544 ML |
11504 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11505 | struct intel_crtc_state *pipe_config, *sw_config; | |
11506 | struct drm_atomic_state *old_state; | |
11507 | bool active; | |
045ac3b5 | 11508 | |
e7c84544 | 11509 | old_state = old_crtc_state->state; |
ec2dc6a0 | 11510 | __drm_atomic_helper_crtc_destroy_state(old_crtc_state); |
e7c84544 ML |
11511 | pipe_config = to_intel_crtc_state(old_crtc_state); |
11512 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
11513 | pipe_config->base.crtc = crtc; | |
11514 | pipe_config->base.state = old_state; | |
8af6cf88 | 11515 | |
78108b7c | 11516 | DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); |
8af6cf88 | 11517 | |
e7c84544 | 11518 | active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config); |
d62cf62a | 11519 | |
e56134bc VS |
11520 | /* we keep both pipes enabled on 830 */ |
11521 | if (IS_I830(dev_priv)) | |
e7c84544 | 11522 | active = new_crtc_state->active; |
6c49f241 | 11523 | |
e7c84544 ML |
11524 | I915_STATE_WARN(new_crtc_state->active != active, |
11525 | "crtc active state doesn't match with hw state " | |
11526 | "(expected %i, found %i)\n", new_crtc_state->active, active); | |
0e8ffe1b | 11527 | |
e7c84544 ML |
11528 | I915_STATE_WARN(intel_crtc->active != new_crtc_state->active, |
11529 | "transitional active state does not match atomic hw state " | |
11530 | "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active); | |
4d20cd86 | 11531 | |
e7c84544 ML |
11532 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
11533 | enum pipe pipe; | |
4d20cd86 | 11534 | |
e7c84544 ML |
11535 | active = encoder->get_hw_state(encoder, &pipe); |
11536 | I915_STATE_WARN(active != new_crtc_state->active, | |
11537 | "[ENCODER:%i] active %i with crtc active %i\n", | |
11538 | encoder->base.base.id, active, new_crtc_state->active); | |
4d20cd86 | 11539 | |
e7c84544 ML |
11540 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, |
11541 | "Encoder connected to wrong pipe %c\n", | |
11542 | pipe_name(pipe)); | |
4d20cd86 | 11543 | |
253c84c8 VS |
11544 | if (active) { |
11545 | pipe_config->output_types |= 1 << encoder->type; | |
e7c84544 | 11546 | encoder->get_config(encoder, pipe_config); |
253c84c8 | 11547 | } |
e7c84544 | 11548 | } |
53d9f4e9 | 11549 | |
a7d1b3f4 VS |
11550 | intel_crtc_compute_pixel_rate(pipe_config); |
11551 | ||
e7c84544 ML |
11552 | if (!new_crtc_state->active) |
11553 | return; | |
cfb23ed6 | 11554 | |
e7c84544 | 11555 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
e3b247da | 11556 | |
749d98b8 | 11557 | sw_config = to_intel_crtc_state(new_crtc_state); |
6315b5d3 | 11558 | if (!intel_pipe_config_compare(dev_priv, sw_config, |
e7c84544 ML |
11559 | pipe_config, false)) { |
11560 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); | |
11561 | intel_dump_pipe_config(intel_crtc, pipe_config, | |
11562 | "[hw state]"); | |
11563 | intel_dump_pipe_config(intel_crtc, sw_config, | |
11564 | "[sw state]"); | |
8af6cf88 DV |
11565 | } |
11566 | } | |
11567 | ||
91d1b4bd | 11568 | static void |
c0ead703 ML |
11569 | verify_single_dpll_state(struct drm_i915_private *dev_priv, |
11570 | struct intel_shared_dpll *pll, | |
11571 | struct drm_crtc *crtc, | |
11572 | struct drm_crtc_state *new_state) | |
91d1b4bd | 11573 | { |
91d1b4bd | 11574 | struct intel_dpll_hw_state dpll_hw_state; |
e7c84544 ML |
11575 | unsigned crtc_mask; |
11576 | bool active; | |
5358901f | 11577 | |
e7c84544 | 11578 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
5358901f | 11579 | |
e7c84544 | 11580 | DRM_DEBUG_KMS("%s\n", pll->name); |
5358901f | 11581 | |
e7c84544 | 11582 | active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state); |
5358901f | 11583 | |
e7c84544 ML |
11584 | if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) { |
11585 | I915_STATE_WARN(!pll->on && pll->active_mask, | |
11586 | "pll in active use but not on in sw tracking\n"); | |
11587 | I915_STATE_WARN(pll->on && !pll->active_mask, | |
11588 | "pll is on but not used by any active crtc\n"); | |
11589 | I915_STATE_WARN(pll->on != active, | |
11590 | "pll on state mismatch (expected %i, found %i)\n", | |
11591 | pll->on, active); | |
11592 | } | |
5358901f | 11593 | |
e7c84544 | 11594 | if (!crtc) { |
2c42e535 | 11595 | I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask, |
e7c84544 | 11596 | "more active pll users than references: %x vs %x\n", |
2c42e535 | 11597 | pll->active_mask, pll->state.crtc_mask); |
5358901f | 11598 | |
e7c84544 ML |
11599 | return; |
11600 | } | |
11601 | ||
11602 | crtc_mask = 1 << drm_crtc_index(crtc); | |
11603 | ||
11604 | if (new_state->active) | |
11605 | I915_STATE_WARN(!(pll->active_mask & crtc_mask), | |
11606 | "pll active mismatch (expected pipe %c in active mask 0x%02x)\n", | |
11607 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
11608 | else | |
11609 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
11610 | "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n", | |
11611 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
2dd66ebd | 11612 | |
2c42e535 | 11613 | I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask), |
e7c84544 | 11614 | "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", |
2c42e535 | 11615 | crtc_mask, pll->state.crtc_mask); |
66e985c0 | 11616 | |
2c42e535 | 11617 | I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state, |
e7c84544 ML |
11618 | &dpll_hw_state, |
11619 | sizeof(dpll_hw_state)), | |
11620 | "pll hw state mismatch\n"); | |
11621 | } | |
11622 | ||
11623 | static void | |
c0ead703 ML |
11624 | verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc, |
11625 | struct drm_crtc_state *old_crtc_state, | |
11626 | struct drm_crtc_state *new_crtc_state) | |
e7c84544 | 11627 | { |
fac5e23e | 11628 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
11629 | struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state); |
11630 | struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state); | |
11631 | ||
11632 | if (new_state->shared_dpll) | |
c0ead703 | 11633 | verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state); |
e7c84544 ML |
11634 | |
11635 | if (old_state->shared_dpll && | |
11636 | old_state->shared_dpll != new_state->shared_dpll) { | |
11637 | unsigned crtc_mask = 1 << drm_crtc_index(crtc); | |
11638 | struct intel_shared_dpll *pll = old_state->shared_dpll; | |
11639 | ||
11640 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
11641 | "pll active mismatch (didn't expect pipe %c in active mask)\n", | |
11642 | pipe_name(drm_crtc_index(crtc))); | |
2c42e535 | 11643 | I915_STATE_WARN(pll->state.crtc_mask & crtc_mask, |
e7c84544 ML |
11644 | "pll enabled crtcs mismatch (found %x in enabled mask)\n", |
11645 | pipe_name(drm_crtc_index(crtc))); | |
5358901f | 11646 | } |
8af6cf88 DV |
11647 | } |
11648 | ||
e7c84544 | 11649 | static void |
c0ead703 | 11650 | intel_modeset_verify_crtc(struct drm_crtc *crtc, |
677100ce ML |
11651 | struct drm_atomic_state *state, |
11652 | struct drm_crtc_state *old_state, | |
11653 | struct drm_crtc_state *new_state) | |
e7c84544 | 11654 | { |
5a21b665 DV |
11655 | if (!needs_modeset(new_state) && |
11656 | !to_intel_crtc_state(new_state)->update_pipe) | |
11657 | return; | |
11658 | ||
c0ead703 | 11659 | verify_wm_state(crtc, new_state); |
677100ce | 11660 | verify_connector_state(crtc->dev, state, crtc); |
c0ead703 ML |
11661 | verify_crtc_state(crtc, old_state, new_state); |
11662 | verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state); | |
e7c84544 ML |
11663 | } |
11664 | ||
11665 | static void | |
c0ead703 | 11666 | verify_disabled_dpll_state(struct drm_device *dev) |
e7c84544 | 11667 | { |
fac5e23e | 11668 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
11669 | int i; |
11670 | ||
11671 | for (i = 0; i < dev_priv->num_shared_dpll; i++) | |
c0ead703 | 11672 | verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL); |
e7c84544 ML |
11673 | } |
11674 | ||
11675 | static void | |
677100ce ML |
11676 | intel_modeset_verify_disabled(struct drm_device *dev, |
11677 | struct drm_atomic_state *state) | |
e7c84544 | 11678 | { |
86b04268 | 11679 | verify_encoder_state(dev, state); |
677100ce | 11680 | verify_connector_state(dev, state, NULL); |
c0ead703 | 11681 | verify_disabled_dpll_state(dev); |
e7c84544 ML |
11682 | } |
11683 | ||
80715b2f VS |
11684 | static void update_scanline_offset(struct intel_crtc *crtc) |
11685 | { | |
4f8036a2 | 11686 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
80715b2f VS |
11687 | |
11688 | /* | |
11689 | * The scanline counter increments at the leading edge of hsync. | |
11690 | * | |
11691 | * On most platforms it starts counting from vtotal-1 on the | |
11692 | * first active line. That means the scanline counter value is | |
11693 | * always one less than what we would expect. Ie. just after | |
11694 | * start of vblank, which also occurs at start of hsync (on the | |
11695 | * last active line), the scanline counter will read vblank_start-1. | |
11696 | * | |
11697 | * On gen2 the scanline counter starts counting from 1 instead | |
11698 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
11699 | * to keep the value positive), instead of adding one. | |
11700 | * | |
11701 | * On HSW+ the behaviour of the scanline counter depends on the output | |
11702 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
11703 | * there's an extra 1 line difference. So we need to add two instead of | |
11704 | * one to the value. | |
ec1b4ee2 VS |
11705 | * |
11706 | * On VLV/CHV DSI the scanline counter would appear to increment | |
11707 | * approx. 1/3 of a scanline before start of vblank. Unfortunately | |
11708 | * that means we can't tell whether we're in vblank or not while | |
11709 | * we're on that particular line. We must still set scanline_offset | |
11710 | * to 1 so that the vblank timestamps come out correct when we query | |
11711 | * the scanline counter from within the vblank interrupt handler. | |
11712 | * However if queried just before the start of vblank we'll get an | |
11713 | * answer that's slightly in the future. | |
80715b2f | 11714 | */ |
4f8036a2 | 11715 | if (IS_GEN2(dev_priv)) { |
124abe07 | 11716 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
11717 | int vtotal; |
11718 | ||
124abe07 VS |
11719 | vtotal = adjusted_mode->crtc_vtotal; |
11720 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
11721 | vtotal /= 2; |
11722 | ||
11723 | crtc->scanline_offset = vtotal - 1; | |
4f8036a2 | 11724 | } else if (HAS_DDI(dev_priv) && |
2d84d2b3 | 11725 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
11726 | crtc->scanline_offset = 2; |
11727 | } else | |
11728 | crtc->scanline_offset = 1; | |
11729 | } | |
11730 | ||
ad421372 | 11731 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 11732 | { |
225da59b | 11733 | struct drm_device *dev = state->dev; |
ed6739ef | 11734 | struct drm_i915_private *dev_priv = to_i915(dev); |
0a9ab303 | 11735 | struct drm_crtc *crtc; |
aa5e9b47 | 11736 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
0a9ab303 | 11737 | int i; |
ed6739ef ACO |
11738 | |
11739 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 11740 | return; |
ed6739ef | 11741 | |
aa5e9b47 | 11742 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
fb1a38a9 | 11743 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8106ddbd | 11744 | struct intel_shared_dpll *old_dpll = |
aa5e9b47 | 11745 | to_intel_crtc_state(old_crtc_state)->shared_dpll; |
0a9ab303 | 11746 | |
aa5e9b47 | 11747 | if (!needs_modeset(new_crtc_state)) |
225da59b ACO |
11748 | continue; |
11749 | ||
aa5e9b47 | 11750 | to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL; |
fb1a38a9 | 11751 | |
8106ddbd | 11752 | if (!old_dpll) |
fb1a38a9 | 11753 | continue; |
0a9ab303 | 11754 | |
a1c414ee | 11755 | intel_release_shared_dpll(old_dpll, intel_crtc, state); |
ad421372 | 11756 | } |
ed6739ef ACO |
11757 | } |
11758 | ||
99d736a2 ML |
11759 | /* |
11760 | * This implements the workaround described in the "notes" section of the mode | |
11761 | * set sequence documentation. When going from no pipes or single pipe to | |
11762 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
11763 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
11764 | */ | |
11765 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
11766 | { | |
11767 | struct drm_crtc_state *crtc_state; | |
11768 | struct intel_crtc *intel_crtc; | |
11769 | struct drm_crtc *crtc; | |
11770 | struct intel_crtc_state *first_crtc_state = NULL; | |
11771 | struct intel_crtc_state *other_crtc_state = NULL; | |
11772 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
11773 | int i; | |
11774 | ||
11775 | /* look at all crtc's that are going to be enabled in during modeset */ | |
aa5e9b47 | 11776 | for_each_new_crtc_in_state(state, crtc, crtc_state, i) { |
99d736a2 ML |
11777 | intel_crtc = to_intel_crtc(crtc); |
11778 | ||
11779 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
11780 | continue; | |
11781 | ||
11782 | if (first_crtc_state) { | |
11783 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
11784 | break; | |
11785 | } else { | |
11786 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
11787 | first_pipe = intel_crtc->pipe; | |
11788 | } | |
11789 | } | |
11790 | ||
11791 | /* No workaround needed? */ | |
11792 | if (!first_crtc_state) | |
11793 | return 0; | |
11794 | ||
11795 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
11796 | for_each_intel_crtc(state->dev, intel_crtc) { | |
11797 | struct intel_crtc_state *pipe_config; | |
11798 | ||
11799 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
11800 | if (IS_ERR(pipe_config)) | |
11801 | return PTR_ERR(pipe_config); | |
11802 | ||
11803 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
11804 | ||
11805 | if (!pipe_config->base.active || | |
11806 | needs_modeset(&pipe_config->base)) | |
11807 | continue; | |
11808 | ||
11809 | /* 2 or more enabled crtcs means no need for w/a */ | |
11810 | if (enabled_pipe != INVALID_PIPE) | |
11811 | return 0; | |
11812 | ||
11813 | enabled_pipe = intel_crtc->pipe; | |
11814 | } | |
11815 | ||
11816 | if (enabled_pipe != INVALID_PIPE) | |
11817 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
11818 | else if (other_crtc_state) | |
11819 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
11820 | ||
11821 | return 0; | |
11822 | } | |
11823 | ||
8d96561a VS |
11824 | static int intel_lock_all_pipes(struct drm_atomic_state *state) |
11825 | { | |
11826 | struct drm_crtc *crtc; | |
11827 | ||
11828 | /* Add all pipes to the state */ | |
11829 | for_each_crtc(state->dev, crtc) { | |
11830 | struct drm_crtc_state *crtc_state; | |
11831 | ||
11832 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
11833 | if (IS_ERR(crtc_state)) | |
11834 | return PTR_ERR(crtc_state); | |
11835 | } | |
11836 | ||
11837 | return 0; | |
11838 | } | |
11839 | ||
27c329ed ML |
11840 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
11841 | { | |
11842 | struct drm_crtc *crtc; | |
27c329ed | 11843 | |
8d96561a VS |
11844 | /* |
11845 | * Add all pipes to the state, and force | |
11846 | * a modeset on all the active ones. | |
11847 | */ | |
27c329ed | 11848 | for_each_crtc(state->dev, crtc) { |
9780aad5 VS |
11849 | struct drm_crtc_state *crtc_state; |
11850 | int ret; | |
11851 | ||
27c329ed ML |
11852 | crtc_state = drm_atomic_get_crtc_state(state, crtc); |
11853 | if (IS_ERR(crtc_state)) | |
11854 | return PTR_ERR(crtc_state); | |
11855 | ||
11856 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
11857 | continue; | |
11858 | ||
11859 | crtc_state->mode_changed = true; | |
11860 | ||
11861 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
11862 | if (ret) | |
9780aad5 | 11863 | return ret; |
27c329ed ML |
11864 | |
11865 | ret = drm_atomic_add_affected_planes(state, crtc); | |
11866 | if (ret) | |
9780aad5 | 11867 | return ret; |
27c329ed ML |
11868 | } |
11869 | ||
9780aad5 | 11870 | return 0; |
27c329ed ML |
11871 | } |
11872 | ||
c347a676 | 11873 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 11874 | { |
565602d7 | 11875 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 11876 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
565602d7 | 11877 | struct drm_crtc *crtc; |
aa5e9b47 | 11878 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
565602d7 | 11879 | int ret = 0, i; |
054518dd | 11880 | |
b359283a ML |
11881 | if (!check_digital_port_conflicts(state)) { |
11882 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
11883 | return -EINVAL; | |
11884 | } | |
11885 | ||
565602d7 ML |
11886 | intel_state->modeset = true; |
11887 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
bb0f4aab VS |
11888 | intel_state->cdclk.logical = dev_priv->cdclk.logical; |
11889 | intel_state->cdclk.actual = dev_priv->cdclk.actual; | |
565602d7 | 11890 | |
aa5e9b47 ML |
11891 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
11892 | if (new_crtc_state->active) | |
565602d7 ML |
11893 | intel_state->active_crtcs |= 1 << i; |
11894 | else | |
11895 | intel_state->active_crtcs &= ~(1 << i); | |
8b4a7d05 | 11896 | |
aa5e9b47 | 11897 | if (old_crtc_state->active != new_crtc_state->active) |
8b4a7d05 | 11898 | intel_state->active_pipe_changes |= drm_crtc_mask(crtc); |
565602d7 ML |
11899 | } |
11900 | ||
054518dd ACO |
11901 | /* |
11902 | * See if the config requires any additional preparation, e.g. | |
11903 | * to adjust global state with pipes off. We need to do this | |
11904 | * here so we can get the modeset_pipe updated config for the new | |
11905 | * mode set on this crtc. For other crtcs we need to use the | |
11906 | * adjusted_mode bits in the crtc directly. | |
11907 | */ | |
27c329ed | 11908 | if (dev_priv->display.modeset_calc_cdclk) { |
27c329ed | 11909 | ret = dev_priv->display.modeset_calc_cdclk(state); |
c89e39f3 CT |
11910 | if (ret < 0) |
11911 | return ret; | |
27c329ed | 11912 | |
8d96561a | 11913 | /* |
bb0f4aab | 11914 | * Writes to dev_priv->cdclk.logical must protected by |
8d96561a VS |
11915 | * holding all the crtc locks, even if we don't end up |
11916 | * touching the hardware | |
11917 | */ | |
bb0f4aab VS |
11918 | if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical, |
11919 | &intel_state->cdclk.logical)) { | |
8d96561a VS |
11920 | ret = intel_lock_all_pipes(state); |
11921 | if (ret < 0) | |
11922 | return ret; | |
11923 | } | |
11924 | ||
11925 | /* All pipes must be switched off while we change the cdclk. */ | |
bb0f4aab VS |
11926 | if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual, |
11927 | &intel_state->cdclk.actual)) { | |
27c329ed | 11928 | ret = intel_modeset_all_pipes(state); |
8d96561a VS |
11929 | if (ret < 0) |
11930 | return ret; | |
11931 | } | |
e8788cbc | 11932 | |
bb0f4aab VS |
11933 | DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n", |
11934 | intel_state->cdclk.logical.cdclk, | |
11935 | intel_state->cdclk.actual.cdclk); | |
e0ca7a6b | 11936 | } else { |
bb0f4aab | 11937 | to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical; |
e0ca7a6b | 11938 | } |
054518dd | 11939 | |
ad421372 | 11940 | intel_modeset_clear_plls(state); |
054518dd | 11941 | |
565602d7 | 11942 | if (IS_HASWELL(dev_priv)) |
ad421372 | 11943 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 11944 | |
ad421372 | 11945 | return 0; |
c347a676 ACO |
11946 | } |
11947 | ||
aa363136 MR |
11948 | /* |
11949 | * Handle calculation of various watermark data at the end of the atomic check | |
11950 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
11951 | * handlers to ensure that all derived state has been updated. | |
11952 | */ | |
55994c2c | 11953 | static int calc_watermark_data(struct drm_atomic_state *state) |
aa363136 MR |
11954 | { |
11955 | struct drm_device *dev = state->dev; | |
98d39494 | 11956 | struct drm_i915_private *dev_priv = to_i915(dev); |
98d39494 MR |
11957 | |
11958 | /* Is there platform-specific watermark information to calculate? */ | |
11959 | if (dev_priv->display.compute_global_watermarks) | |
55994c2c MR |
11960 | return dev_priv->display.compute_global_watermarks(state); |
11961 | ||
11962 | return 0; | |
aa363136 MR |
11963 | } |
11964 | ||
74c090b1 ML |
11965 | /** |
11966 | * intel_atomic_check - validate state object | |
11967 | * @dev: drm device | |
11968 | * @state: state to validate | |
11969 | */ | |
11970 | static int intel_atomic_check(struct drm_device *dev, | |
11971 | struct drm_atomic_state *state) | |
c347a676 | 11972 | { |
dd8b3bdb | 11973 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 11974 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 | 11975 | struct drm_crtc *crtc; |
aa5e9b47 | 11976 | struct drm_crtc_state *old_crtc_state, *crtc_state; |
c347a676 | 11977 | int ret, i; |
61333b60 | 11978 | bool any_ms = false; |
c347a676 | 11979 | |
74c090b1 | 11980 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
11981 | if (ret) |
11982 | return ret; | |
11983 | ||
aa5e9b47 | 11984 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) { |
cfb23ed6 ML |
11985 | struct intel_crtc_state *pipe_config = |
11986 | to_intel_crtc_state(crtc_state); | |
1ed51de9 DV |
11987 | |
11988 | /* Catch I915_MODE_FLAG_INHERITED */ | |
aa5e9b47 | 11989 | if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags) |
1ed51de9 | 11990 | crtc_state->mode_changed = true; |
cfb23ed6 | 11991 | |
af4a879e | 11992 | if (!needs_modeset(crtc_state)) |
c347a676 ACO |
11993 | continue; |
11994 | ||
af4a879e DV |
11995 | if (!crtc_state->enable) { |
11996 | any_ms = true; | |
cfb23ed6 | 11997 | continue; |
af4a879e | 11998 | } |
cfb23ed6 | 11999 | |
26495481 DV |
12000 | /* FIXME: For only active_changed we shouldn't need to do any |
12001 | * state recomputation at all. */ | |
12002 | ||
1ed51de9 DV |
12003 | ret = drm_atomic_add_affected_connectors(state, crtc); |
12004 | if (ret) | |
12005 | return ret; | |
b359283a | 12006 | |
cfb23ed6 | 12007 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
25aa1c39 ML |
12008 | if (ret) { |
12009 | intel_dump_pipe_config(to_intel_crtc(crtc), | |
12010 | pipe_config, "[failed]"); | |
c347a676 | 12011 | return ret; |
25aa1c39 | 12012 | } |
c347a676 | 12013 | |
73831236 | 12014 | if (i915.fastboot && |
6315b5d3 | 12015 | intel_pipe_config_compare(dev_priv, |
aa5e9b47 | 12016 | to_intel_crtc_state(old_crtc_state), |
1ed51de9 | 12017 | pipe_config, true)) { |
26495481 | 12018 | crtc_state->mode_changed = false; |
aa5e9b47 | 12019 | pipe_config->update_pipe = true; |
26495481 DV |
12020 | } |
12021 | ||
af4a879e | 12022 | if (needs_modeset(crtc_state)) |
26495481 | 12023 | any_ms = true; |
cfb23ed6 | 12024 | |
af4a879e DV |
12025 | ret = drm_atomic_add_affected_planes(state, crtc); |
12026 | if (ret) | |
12027 | return ret; | |
61333b60 | 12028 | |
26495481 DV |
12029 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
12030 | needs_modeset(crtc_state) ? | |
12031 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
12032 | } |
12033 | ||
61333b60 ML |
12034 | if (any_ms) { |
12035 | ret = intel_modeset_checks(state); | |
12036 | ||
12037 | if (ret) | |
12038 | return ret; | |
e0ca7a6b | 12039 | } else { |
bb0f4aab | 12040 | intel_state->cdclk.logical = dev_priv->cdclk.logical; |
e0ca7a6b | 12041 | } |
76305b1a | 12042 | |
dd8b3bdb | 12043 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
12044 | if (ret) |
12045 | return ret; | |
12046 | ||
f51be2e0 | 12047 | intel_fbc_choose_crtc(dev_priv, state); |
55994c2c | 12048 | return calc_watermark_data(state); |
054518dd ACO |
12049 | } |
12050 | ||
5008e874 | 12051 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
d07f0e59 | 12052 | struct drm_atomic_state *state) |
5008e874 | 12053 | { |
fd70075f | 12054 | return drm_atomic_helper_prepare_planes(dev, state); |
5008e874 ML |
12055 | } |
12056 | ||
a2991414 ML |
12057 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) |
12058 | { | |
12059 | struct drm_device *dev = crtc->base.dev; | |
12060 | ||
12061 | if (!dev->max_vblank_count) | |
ca814b25 | 12062 | return drm_crtc_accurate_vblank_count(&crtc->base); |
a2991414 ML |
12063 | |
12064 | return dev->driver->get_vblank_counter(dev, crtc->pipe); | |
12065 | } | |
12066 | ||
5a21b665 DV |
12067 | static void intel_atomic_wait_for_vblanks(struct drm_device *dev, |
12068 | struct drm_i915_private *dev_priv, | |
12069 | unsigned crtc_mask) | |
e8861675 | 12070 | { |
5a21b665 DV |
12071 | unsigned last_vblank_count[I915_MAX_PIPES]; |
12072 | enum pipe pipe; | |
12073 | int ret; | |
e8861675 | 12074 | |
5a21b665 DV |
12075 | if (!crtc_mask) |
12076 | return; | |
e8861675 | 12077 | |
5a21b665 | 12078 | for_each_pipe(dev_priv, pipe) { |
98187836 VS |
12079 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, |
12080 | pipe); | |
e8861675 | 12081 | |
5a21b665 | 12082 | if (!((1 << pipe) & crtc_mask)) |
e8861675 ML |
12083 | continue; |
12084 | ||
e2af48c6 | 12085 | ret = drm_crtc_vblank_get(&crtc->base); |
5a21b665 DV |
12086 | if (WARN_ON(ret != 0)) { |
12087 | crtc_mask &= ~(1 << pipe); | |
12088 | continue; | |
e8861675 ML |
12089 | } |
12090 | ||
e2af48c6 | 12091 | last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base); |
e8861675 ML |
12092 | } |
12093 | ||
5a21b665 | 12094 | for_each_pipe(dev_priv, pipe) { |
98187836 VS |
12095 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, |
12096 | pipe); | |
5a21b665 | 12097 | long lret; |
e8861675 | 12098 | |
5a21b665 DV |
12099 | if (!((1 << pipe) & crtc_mask)) |
12100 | continue; | |
d55dbd06 | 12101 | |
5a21b665 DV |
12102 | lret = wait_event_timeout(dev->vblank[pipe].queue, |
12103 | last_vblank_count[pipe] != | |
e2af48c6 | 12104 | drm_crtc_vblank_count(&crtc->base), |
5a21b665 | 12105 | msecs_to_jiffies(50)); |
d55dbd06 | 12106 | |
5a21b665 | 12107 | WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe)); |
d55dbd06 | 12108 | |
e2af48c6 | 12109 | drm_crtc_vblank_put(&crtc->base); |
d55dbd06 ML |
12110 | } |
12111 | } | |
12112 | ||
5a21b665 | 12113 | static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) |
a6747b73 | 12114 | { |
5a21b665 DV |
12115 | /* fb updated, need to unpin old fb */ |
12116 | if (crtc_state->fb_changed) | |
12117 | return true; | |
a6747b73 | 12118 | |
5a21b665 DV |
12119 | /* wm changes, need vblank before final wm's */ |
12120 | if (crtc_state->update_wm_post) | |
12121 | return true; | |
a6747b73 | 12122 | |
5eeb798b | 12123 | if (crtc_state->wm.need_postvbl_update) |
5a21b665 | 12124 | return true; |
a6747b73 | 12125 | |
5a21b665 | 12126 | return false; |
e8861675 ML |
12127 | } |
12128 | ||
896e5bb0 L |
12129 | static void intel_update_crtc(struct drm_crtc *crtc, |
12130 | struct drm_atomic_state *state, | |
12131 | struct drm_crtc_state *old_crtc_state, | |
aa5e9b47 | 12132 | struct drm_crtc_state *new_crtc_state, |
896e5bb0 L |
12133 | unsigned int *crtc_vblank_mask) |
12134 | { | |
12135 | struct drm_device *dev = crtc->dev; | |
12136 | struct drm_i915_private *dev_priv = to_i915(dev); | |
12137 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
aa5e9b47 ML |
12138 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state); |
12139 | bool modeset = needs_modeset(new_crtc_state); | |
896e5bb0 L |
12140 | |
12141 | if (modeset) { | |
12142 | update_scanline_offset(intel_crtc); | |
12143 | dev_priv->display.crtc_enable(pipe_config, state); | |
12144 | } else { | |
aa5e9b47 ML |
12145 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state), |
12146 | pipe_config); | |
896e5bb0 L |
12147 | } |
12148 | ||
12149 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12150 | intel_fbc_enable( | |
12151 | intel_crtc, pipe_config, | |
12152 | to_intel_plane_state(crtc->primary->state)); | |
12153 | } | |
12154 | ||
12155 | drm_atomic_helper_commit_planes_on_crtc(old_crtc_state); | |
12156 | ||
12157 | if (needs_vblank_wait(pipe_config)) | |
12158 | *crtc_vblank_mask |= drm_crtc_mask(crtc); | |
12159 | } | |
12160 | ||
12161 | static void intel_update_crtcs(struct drm_atomic_state *state, | |
12162 | unsigned int *crtc_vblank_mask) | |
12163 | { | |
12164 | struct drm_crtc *crtc; | |
aa5e9b47 | 12165 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
896e5bb0 L |
12166 | int i; |
12167 | ||
aa5e9b47 ML |
12168 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
12169 | if (!new_crtc_state->active) | |
896e5bb0 L |
12170 | continue; |
12171 | ||
12172 | intel_update_crtc(crtc, state, old_crtc_state, | |
aa5e9b47 | 12173 | new_crtc_state, crtc_vblank_mask); |
896e5bb0 L |
12174 | } |
12175 | } | |
12176 | ||
27082493 L |
12177 | static void skl_update_crtcs(struct drm_atomic_state *state, |
12178 | unsigned int *crtc_vblank_mask) | |
12179 | { | |
0f0f74bc | 12180 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
27082493 L |
12181 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
12182 | struct drm_crtc *crtc; | |
ce0ba283 | 12183 | struct intel_crtc *intel_crtc; |
aa5e9b47 | 12184 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
ce0ba283 | 12185 | struct intel_crtc_state *cstate; |
27082493 L |
12186 | unsigned int updated = 0; |
12187 | bool progress; | |
12188 | enum pipe pipe; | |
5eff503b ML |
12189 | int i; |
12190 | ||
12191 | const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {}; | |
12192 | ||
aa5e9b47 | 12193 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) |
5eff503b | 12194 | /* ignore allocations for crtc's that have been turned off. */ |
aa5e9b47 | 12195 | if (new_crtc_state->active) |
5eff503b | 12196 | entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb; |
27082493 L |
12197 | |
12198 | /* | |
12199 | * Whenever the number of active pipes changes, we need to make sure we | |
12200 | * update the pipes in the right order so that their ddb allocations | |
12201 | * never overlap with eachother inbetween CRTC updates. Otherwise we'll | |
12202 | * cause pipe underruns and other bad stuff. | |
12203 | */ | |
12204 | do { | |
27082493 L |
12205 | progress = false; |
12206 | ||
aa5e9b47 | 12207 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
27082493 L |
12208 | bool vbl_wait = false; |
12209 | unsigned int cmask = drm_crtc_mask(crtc); | |
ce0ba283 L |
12210 | |
12211 | intel_crtc = to_intel_crtc(crtc); | |
12212 | cstate = to_intel_crtc_state(crtc->state); | |
12213 | pipe = intel_crtc->pipe; | |
27082493 | 12214 | |
5eff503b | 12215 | if (updated & cmask || !cstate->base.active) |
27082493 | 12216 | continue; |
5eff503b ML |
12217 | |
12218 | if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i)) | |
27082493 L |
12219 | continue; |
12220 | ||
12221 | updated |= cmask; | |
5eff503b | 12222 | entries[i] = &cstate->wm.skl.ddb; |
27082493 L |
12223 | |
12224 | /* | |
12225 | * If this is an already active pipe, it's DDB changed, | |
12226 | * and this isn't the last pipe that needs updating | |
12227 | * then we need to wait for a vblank to pass for the | |
12228 | * new ddb allocation to take effect. | |
12229 | */ | |
ce0ba283 | 12230 | if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb, |
512b5527 | 12231 | &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) && |
aa5e9b47 | 12232 | !new_crtc_state->active_changed && |
27082493 L |
12233 | intel_state->wm_results.dirty_pipes != updated) |
12234 | vbl_wait = true; | |
12235 | ||
12236 | intel_update_crtc(crtc, state, old_crtc_state, | |
aa5e9b47 | 12237 | new_crtc_state, crtc_vblank_mask); |
27082493 L |
12238 | |
12239 | if (vbl_wait) | |
0f0f74bc | 12240 | intel_wait_for_vblank(dev_priv, pipe); |
27082493 L |
12241 | |
12242 | progress = true; | |
12243 | } | |
12244 | } while (progress); | |
12245 | } | |
12246 | ||
ba318c61 CW |
12247 | static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) |
12248 | { | |
12249 | struct intel_atomic_state *state, *next; | |
12250 | struct llist_node *freed; | |
12251 | ||
12252 | freed = llist_del_all(&dev_priv->atomic_helper.free_list); | |
12253 | llist_for_each_entry_safe(state, next, freed, freed) | |
12254 | drm_atomic_state_put(&state->base); | |
12255 | } | |
12256 | ||
12257 | static void intel_atomic_helper_free_state_worker(struct work_struct *work) | |
12258 | { | |
12259 | struct drm_i915_private *dev_priv = | |
12260 | container_of(work, typeof(*dev_priv), atomic_helper.free_work); | |
12261 | ||
12262 | intel_atomic_helper_free_state(dev_priv); | |
12263 | } | |
12264 | ||
94f05024 | 12265 | static void intel_atomic_commit_tail(struct drm_atomic_state *state) |
a6778b3c | 12266 | { |
94f05024 | 12267 | struct drm_device *dev = state->dev; |
565602d7 | 12268 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 12269 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa5e9b47 | 12270 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
7580d774 | 12271 | struct drm_crtc *crtc; |
5a21b665 | 12272 | struct intel_crtc_state *intel_cstate; |
5a21b665 | 12273 | bool hw_check = intel_state->modeset; |
d8fc70b7 | 12274 | u64 put_domains[I915_MAX_PIPES] = {}; |
5a21b665 | 12275 | unsigned crtc_vblank_mask = 0; |
e95433c7 | 12276 | int i; |
a6778b3c | 12277 | |
ea0000f0 DV |
12278 | drm_atomic_helper_wait_for_dependencies(state); |
12279 | ||
c3b32658 | 12280 | if (intel_state->modeset) |
5a21b665 | 12281 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); |
565602d7 | 12282 | |
aa5e9b47 | 12283 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
a539205a ML |
12284 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
12285 | ||
aa5e9b47 ML |
12286 | if (needs_modeset(new_crtc_state) || |
12287 | to_intel_crtc_state(new_crtc_state)->update_pipe) { | |
5a21b665 DV |
12288 | hw_check = true; |
12289 | ||
12290 | put_domains[to_intel_crtc(crtc)->pipe] = | |
12291 | modeset_get_crtc_power_domains(crtc, | |
aa5e9b47 | 12292 | to_intel_crtc_state(new_crtc_state)); |
5a21b665 DV |
12293 | } |
12294 | ||
aa5e9b47 | 12295 | if (!needs_modeset(new_crtc_state)) |
61333b60 ML |
12296 | continue; |
12297 | ||
aa5e9b47 ML |
12298 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state), |
12299 | to_intel_crtc_state(new_crtc_state)); | |
460da916 | 12300 | |
29ceb0e6 VS |
12301 | if (old_crtc_state->active) { |
12302 | intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); | |
4a806558 | 12303 | dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state); |
eddfcbcd | 12304 | intel_crtc->active = false; |
58f9c0bc | 12305 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 12306 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
12307 | |
12308 | /* | |
12309 | * Underruns don't always raise | |
12310 | * interrupts, so check manually. | |
12311 | */ | |
12312 | intel_check_cpu_fifo_underruns(dev_priv); | |
12313 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 | 12314 | |
e62929b3 ML |
12315 | if (!crtc->state->active) { |
12316 | /* | |
12317 | * Make sure we don't call initial_watermarks | |
12318 | * for ILK-style watermark updates. | |
ff32c54e VS |
12319 | * |
12320 | * No clue what this is supposed to achieve. | |
e62929b3 | 12321 | */ |
ff32c54e | 12322 | if (INTEL_GEN(dev_priv) >= 9) |
e62929b3 ML |
12323 | dev_priv->display.initial_watermarks(intel_state, |
12324 | to_intel_crtc_state(crtc->state)); | |
e62929b3 | 12325 | } |
a539205a | 12326 | } |
b8cecdf5 | 12327 | } |
7758a113 | 12328 | |
ea9d758d DV |
12329 | /* Only after disabling all output pipelines that will be changed can we |
12330 | * update the the output configuration. */ | |
4740b0f2 | 12331 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 12332 | |
565602d7 | 12333 | if (intel_state->modeset) { |
4740b0f2 | 12334 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
33c8df89 | 12335 | |
b0587e4d | 12336 | intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual); |
f6d1973d | 12337 | |
656d1b89 L |
12338 | /* |
12339 | * SKL workaround: bspec recommends we disable the SAGV when we | |
12340 | * have more then one pipe enabled | |
12341 | */ | |
56feca91 | 12342 | if (!intel_can_enable_sagv(state)) |
16dcdc4e | 12343 | intel_disable_sagv(dev_priv); |
656d1b89 | 12344 | |
677100ce | 12345 | intel_modeset_verify_disabled(dev, state); |
4740b0f2 | 12346 | } |
47fab737 | 12347 | |
896e5bb0 | 12348 | /* Complete the events for pipes that have now been disabled */ |
aa5e9b47 ML |
12349 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
12350 | bool modeset = needs_modeset(new_crtc_state); | |
80715b2f | 12351 | |
1f7528c4 | 12352 | /* Complete events for now disable pipes here. */ |
aa5e9b47 | 12353 | if (modeset && !new_crtc_state->active && new_crtc_state->event) { |
1f7528c4 | 12354 | spin_lock_irq(&dev->event_lock); |
aa5e9b47 | 12355 | drm_crtc_send_vblank_event(crtc, new_crtc_state->event); |
1f7528c4 DV |
12356 | spin_unlock_irq(&dev->event_lock); |
12357 | ||
aa5e9b47 | 12358 | new_crtc_state->event = NULL; |
1f7528c4 | 12359 | } |
177246a8 MR |
12360 | } |
12361 | ||
896e5bb0 L |
12362 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
12363 | dev_priv->display.update_crtcs(state, &crtc_vblank_mask); | |
12364 | ||
94f05024 DV |
12365 | /* FIXME: We should call drm_atomic_helper_commit_hw_done() here |
12366 | * already, but still need the state for the delayed optimization. To | |
12367 | * fix this: | |
12368 | * - wrap the optimization/post_plane_update stuff into a per-crtc work. | |
12369 | * - schedule that vblank worker _before_ calling hw_done | |
12370 | * - at the start of commit_tail, cancel it _synchrously | |
12371 | * - switch over to the vblank wait helper in the core after that since | |
12372 | * we don't need out special handling any more. | |
12373 | */ | |
5a21b665 DV |
12374 | if (!state->legacy_cursor_update) |
12375 | intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); | |
12376 | ||
12377 | /* | |
12378 | * Now that the vblank has passed, we can go ahead and program the | |
12379 | * optimal watermarks on platforms that need two-step watermark | |
12380 | * programming. | |
12381 | * | |
12382 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
12383 | */ | |
aa5e9b47 ML |
12384 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
12385 | intel_cstate = to_intel_crtc_state(new_crtc_state); | |
5a21b665 DV |
12386 | |
12387 | if (dev_priv->display.optimize_watermarks) | |
ccf010fb ML |
12388 | dev_priv->display.optimize_watermarks(intel_state, |
12389 | intel_cstate); | |
5a21b665 DV |
12390 | } |
12391 | ||
aa5e9b47 | 12392 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
5a21b665 DV |
12393 | intel_post_plane_update(to_intel_crtc_state(old_crtc_state)); |
12394 | ||
12395 | if (put_domains[i]) | |
12396 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
12397 | ||
aa5e9b47 | 12398 | intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); |
5a21b665 DV |
12399 | } |
12400 | ||
56feca91 | 12401 | if (intel_state->modeset && intel_can_enable_sagv(state)) |
16dcdc4e | 12402 | intel_enable_sagv(dev_priv); |
656d1b89 | 12403 | |
94f05024 DV |
12404 | drm_atomic_helper_commit_hw_done(state); |
12405 | ||
d5553c09 CW |
12406 | if (intel_state->modeset) { |
12407 | /* As one of the primary mmio accessors, KMS has a high | |
12408 | * likelihood of triggering bugs in unclaimed access. After we | |
12409 | * finish modesetting, see if an error has been flagged, and if | |
12410 | * so enable debugging for the next modeset - and hope we catch | |
12411 | * the culprit. | |
12412 | */ | |
12413 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
5a21b665 | 12414 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); |
d5553c09 | 12415 | } |
5a21b665 | 12416 | |
5a21b665 | 12417 | drm_atomic_helper_cleanup_planes(dev, state); |
5a21b665 | 12418 | |
ea0000f0 DV |
12419 | drm_atomic_helper_commit_cleanup_done(state); |
12420 | ||
0853695c | 12421 | drm_atomic_state_put(state); |
f30da187 | 12422 | |
ba318c61 | 12423 | intel_atomic_helper_free_state(dev_priv); |
94f05024 DV |
12424 | } |
12425 | ||
12426 | static void intel_atomic_commit_work(struct work_struct *work) | |
12427 | { | |
c004a90b CW |
12428 | struct drm_atomic_state *state = |
12429 | container_of(work, struct drm_atomic_state, commit_work); | |
12430 | ||
94f05024 DV |
12431 | intel_atomic_commit_tail(state); |
12432 | } | |
12433 | ||
c004a90b CW |
12434 | static int __i915_sw_fence_call |
12435 | intel_atomic_commit_ready(struct i915_sw_fence *fence, | |
12436 | enum i915_sw_fence_notify notify) | |
12437 | { | |
12438 | struct intel_atomic_state *state = | |
12439 | container_of(fence, struct intel_atomic_state, commit_ready); | |
12440 | ||
12441 | switch (notify) { | |
12442 | case FENCE_COMPLETE: | |
12443 | if (state->base.commit_work.func) | |
12444 | queue_work(system_unbound_wq, &state->base.commit_work); | |
12445 | break; | |
12446 | ||
12447 | case FENCE_FREE: | |
eb955eee CW |
12448 | { |
12449 | struct intel_atomic_helper *helper = | |
12450 | &to_i915(state->base.dev)->atomic_helper; | |
12451 | ||
12452 | if (llist_add(&state->freed, &helper->free_list)) | |
12453 | schedule_work(&helper->free_work); | |
12454 | break; | |
12455 | } | |
c004a90b CW |
12456 | } |
12457 | ||
12458 | return NOTIFY_DONE; | |
12459 | } | |
12460 | ||
6c9c1b38 DV |
12461 | static void intel_atomic_track_fbs(struct drm_atomic_state *state) |
12462 | { | |
aa5e9b47 | 12463 | struct drm_plane_state *old_plane_state, *new_plane_state; |
6c9c1b38 | 12464 | struct drm_plane *plane; |
6c9c1b38 DV |
12465 | int i; |
12466 | ||
aa5e9b47 | 12467 | for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) |
faf5bf0a | 12468 | i915_gem_track_fb(intel_fb_obj(old_plane_state->fb), |
aa5e9b47 | 12469 | intel_fb_obj(new_plane_state->fb), |
faf5bf0a | 12470 | to_intel_plane(plane)->frontbuffer_bit); |
6c9c1b38 DV |
12471 | } |
12472 | ||
94f05024 DV |
12473 | /** |
12474 | * intel_atomic_commit - commit validated state object | |
12475 | * @dev: DRM device | |
12476 | * @state: the top-level driver state object | |
12477 | * @nonblock: nonblocking commit | |
12478 | * | |
12479 | * This function commits a top-level state object that has been validated | |
12480 | * with drm_atomic_helper_check(). | |
12481 | * | |
94f05024 DV |
12482 | * RETURNS |
12483 | * Zero for success or -errno. | |
12484 | */ | |
12485 | static int intel_atomic_commit(struct drm_device *dev, | |
12486 | struct drm_atomic_state *state, | |
12487 | bool nonblock) | |
12488 | { | |
12489 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
fac5e23e | 12490 | struct drm_i915_private *dev_priv = to_i915(dev); |
94f05024 DV |
12491 | int ret = 0; |
12492 | ||
94f05024 DV |
12493 | ret = drm_atomic_helper_setup_commit(state, nonblock); |
12494 | if (ret) | |
12495 | return ret; | |
12496 | ||
c004a90b CW |
12497 | drm_atomic_state_get(state); |
12498 | i915_sw_fence_init(&intel_state->commit_ready, | |
12499 | intel_atomic_commit_ready); | |
94f05024 | 12500 | |
d07f0e59 | 12501 | ret = intel_atomic_prepare_commit(dev, state); |
94f05024 DV |
12502 | if (ret) { |
12503 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
c004a90b | 12504 | i915_sw_fence_commit(&intel_state->commit_ready); |
94f05024 DV |
12505 | return ret; |
12506 | } | |
12507 | ||
440df938 VS |
12508 | /* |
12509 | * The intel_legacy_cursor_update() fast path takes care | |
12510 | * of avoiding the vblank waits for simple cursor | |
12511 | * movement and flips. For cursor on/off and size changes, | |
12512 | * we want to perform the vblank waits so that watermark | |
12513 | * updates happen during the correct frames. Gen9+ have | |
12514 | * double buffered watermarks and so shouldn't need this. | |
12515 | * | |
12516 | * Do this after drm_atomic_helper_setup_commit() and | |
12517 | * intel_atomic_prepare_commit() because we still want | |
12518 | * to skip the flip and fb cleanup waits. Although that | |
12519 | * does risk yanking the mapping from under the display | |
12520 | * engine. | |
12521 | * | |
12522 | * FIXME doing watermarks and fb cleanup from a vblank worker | |
12523 | * (assuming we had any) would solve these problems. | |
12524 | */ | |
12525 | if (INTEL_GEN(dev_priv) < 9) | |
12526 | state->legacy_cursor_update = false; | |
12527 | ||
0806f4ee ML |
12528 | ret = drm_atomic_helper_swap_state(state, true); |
12529 | if (ret) { | |
12530 | i915_sw_fence_commit(&intel_state->commit_ready); | |
12531 | ||
0806f4ee | 12532 | drm_atomic_helper_cleanup_planes(dev, state); |
0806f4ee ML |
12533 | return ret; |
12534 | } | |
94f05024 | 12535 | dev_priv->wm.distrust_bios_wm = false; |
3c0fb588 | 12536 | intel_shared_dpll_swap_state(state); |
6c9c1b38 | 12537 | intel_atomic_track_fbs(state); |
94f05024 | 12538 | |
c3b32658 ML |
12539 | if (intel_state->modeset) { |
12540 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
12541 | sizeof(intel_state->min_pixclk)); | |
12542 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
bb0f4aab VS |
12543 | dev_priv->cdclk.logical = intel_state->cdclk.logical; |
12544 | dev_priv->cdclk.actual = intel_state->cdclk.actual; | |
c3b32658 ML |
12545 | } |
12546 | ||
0853695c | 12547 | drm_atomic_state_get(state); |
c004a90b CW |
12548 | INIT_WORK(&state->commit_work, |
12549 | nonblock ? intel_atomic_commit_work : NULL); | |
12550 | ||
12551 | i915_sw_fence_commit(&intel_state->commit_ready); | |
12552 | if (!nonblock) { | |
12553 | i915_sw_fence_wait(&intel_state->commit_ready); | |
94f05024 | 12554 | intel_atomic_commit_tail(state); |
c004a90b | 12555 | } |
75714940 | 12556 | |
74c090b1 | 12557 | return 0; |
7f27126e JB |
12558 | } |
12559 | ||
f6e5b160 | 12560 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
3fab2f09 | 12561 | .gamma_set = drm_atomic_helper_legacy_gamma_set, |
74c090b1 | 12562 | .set_config = drm_atomic_helper_set_config, |
f6e5b160 | 12563 | .destroy = intel_crtc_destroy, |
4c01ded5 | 12564 | .page_flip = drm_atomic_helper_page_flip, |
1356837e MR |
12565 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
12566 | .atomic_destroy_state = intel_crtc_destroy_state, | |
8c6b709d | 12567 | .set_crc_source = intel_crtc_set_crc_source, |
f6e5b160 CW |
12568 | }; |
12569 | ||
6beb8c23 MR |
12570 | /** |
12571 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
12572 | * @plane: drm plane to prepare for | |
12573 | * @fb: framebuffer to prepare for presentation | |
12574 | * | |
12575 | * Prepares a framebuffer for usage on a display plane. Generally this | |
12576 | * involves pinning the underlying object and updating the frontbuffer tracking | |
12577 | * bits. Some older platforms need special physical address handling for | |
12578 | * cursor planes. | |
12579 | * | |
f935675f ML |
12580 | * Must be called with struct_mutex held. |
12581 | * | |
6beb8c23 MR |
12582 | * Returns 0 on success, negative error code on failure. |
12583 | */ | |
12584 | int | |
12585 | intel_prepare_plane_fb(struct drm_plane *plane, | |
1832040d | 12586 | struct drm_plane_state *new_state) |
465c120c | 12587 | { |
c004a90b CW |
12588 | struct intel_atomic_state *intel_state = |
12589 | to_intel_atomic_state(new_state->state); | |
b7f05d4a | 12590 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
844f9111 | 12591 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 12592 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 12593 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
c004a90b | 12594 | int ret; |
465c120c | 12595 | |
5008e874 ML |
12596 | if (old_obj) { |
12597 | struct drm_crtc_state *crtc_state = | |
c004a90b CW |
12598 | drm_atomic_get_existing_crtc_state(new_state->state, |
12599 | plane->state->crtc); | |
5008e874 ML |
12600 | |
12601 | /* Big Hammer, we also need to ensure that any pending | |
12602 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
12603 | * current scanout is retired before unpinning the old | |
12604 | * framebuffer. Note that we rely on userspace rendering | |
12605 | * into the buffer attached to the pipe they are waiting | |
12606 | * on. If not, userspace generates a GPU hang with IPEHR | |
12607 | * point to the MI_WAIT_FOR_EVENT. | |
12608 | * | |
12609 | * This should only fail upon a hung GPU, in which case we | |
12610 | * can safely continue. | |
12611 | */ | |
c004a90b CW |
12612 | if (needs_modeset(crtc_state)) { |
12613 | ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, | |
12614 | old_obj->resv, NULL, | |
12615 | false, 0, | |
12616 | GFP_KERNEL); | |
12617 | if (ret < 0) | |
12618 | return ret; | |
f4457ae7 | 12619 | } |
5008e874 ML |
12620 | } |
12621 | ||
c004a90b CW |
12622 | if (new_state->fence) { /* explicit fencing */ |
12623 | ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready, | |
12624 | new_state->fence, | |
12625 | I915_FENCE_TIMEOUT, | |
12626 | GFP_KERNEL); | |
12627 | if (ret < 0) | |
12628 | return ret; | |
12629 | } | |
12630 | ||
c37efb99 CW |
12631 | if (!obj) |
12632 | return 0; | |
12633 | ||
4d3088c7 | 12634 | ret = i915_gem_object_pin_pages(obj); |
fd70075f CW |
12635 | if (ret) |
12636 | return ret; | |
12637 | ||
4d3088c7 CW |
12638 | ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex); |
12639 | if (ret) { | |
12640 | i915_gem_object_unpin_pages(obj); | |
12641 | return ret; | |
12642 | } | |
12643 | ||
fd70075f CW |
12644 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
12645 | INTEL_INFO(dev_priv)->cursor_needs_physical) { | |
12646 | const int align = intel_cursor_alignment(dev_priv); | |
12647 | ||
12648 | ret = i915_gem_object_attach_phys(obj, align); | |
12649 | } else { | |
12650 | struct i915_vma *vma; | |
12651 | ||
12652 | vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation); | |
12653 | if (!IS_ERR(vma)) | |
12654 | to_intel_plane_state(new_state)->vma = vma; | |
12655 | else | |
12656 | ret = PTR_ERR(vma); | |
12657 | } | |
12658 | ||
12659 | i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); | |
12660 | ||
12661 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
4d3088c7 | 12662 | i915_gem_object_unpin_pages(obj); |
fd70075f CW |
12663 | if (ret) |
12664 | return ret; | |
12665 | ||
c004a90b CW |
12666 | if (!new_state->fence) { /* implicit fencing */ |
12667 | ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, | |
12668 | obj->resv, NULL, | |
12669 | false, I915_FENCE_TIMEOUT, | |
12670 | GFP_KERNEL); | |
12671 | if (ret < 0) | |
12672 | return ret; | |
12673 | } | |
5a21b665 | 12674 | |
d07f0e59 | 12675 | return 0; |
6beb8c23 MR |
12676 | } |
12677 | ||
38f3ce3a MR |
12678 | /** |
12679 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
12680 | * @plane: drm plane to clean up for | |
12681 | * @fb: old framebuffer that was on plane | |
12682 | * | |
12683 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
12684 | * |
12685 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
12686 | */ |
12687 | void | |
12688 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
1832040d | 12689 | struct drm_plane_state *old_state) |
38f3ce3a | 12690 | { |
be1e3415 | 12691 | struct i915_vma *vma; |
38f3ce3a | 12692 | |
be1e3415 CW |
12693 | /* Should only be called after a successful intel_prepare_plane_fb()! */ |
12694 | vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma); | |
fd70075f CW |
12695 | if (vma) { |
12696 | mutex_lock(&plane->dev->struct_mutex); | |
be1e3415 | 12697 | intel_unpin_fb_vma(vma); |
fd70075f CW |
12698 | mutex_unlock(&plane->dev->struct_mutex); |
12699 | } | |
465c120c MR |
12700 | } |
12701 | ||
6156a456 CK |
12702 | int |
12703 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
12704 | { | |
5b7280f0 | 12705 | struct drm_i915_private *dev_priv; |
6156a456 | 12706 | int max_scale; |
5b7280f0 | 12707 | int crtc_clock, max_dotclk; |
6156a456 | 12708 | |
bf8a0af0 | 12709 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
12710 | return DRM_PLANE_HELPER_NO_SCALING; |
12711 | ||
5b7280f0 ACO |
12712 | dev_priv = to_i915(intel_crtc->base.dev); |
12713 | ||
6156a456 | 12714 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; |
5b7280f0 ACO |
12715 | max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk; |
12716 | ||
12717 | if (IS_GEMINILAKE(dev_priv)) | |
12718 | max_dotclk *= 2; | |
6156a456 | 12719 | |
5b7280f0 | 12720 | if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock)) |
6156a456 CK |
12721 | return DRM_PLANE_HELPER_NO_SCALING; |
12722 | ||
12723 | /* | |
12724 | * skl max scale is lower of: | |
12725 | * close to 3 but not 3, -1 is for that purpose | |
12726 | * or | |
12727 | * cdclk/crtc_clock | |
12728 | */ | |
5b7280f0 ACO |
12729 | max_scale = min((1 << 16) * 3 - 1, |
12730 | (1 << 8) * ((max_dotclk << 8) / crtc_clock)); | |
6156a456 CK |
12731 | |
12732 | return max_scale; | |
12733 | } | |
12734 | ||
465c120c | 12735 | static int |
282dbf9b | 12736 | intel_check_primary_plane(struct intel_plane *plane, |
061e4b8d | 12737 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
12738 | struct intel_plane_state *state) |
12739 | { | |
282dbf9b | 12740 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
2b875c22 | 12741 | struct drm_crtc *crtc = state->base.crtc; |
6156a456 | 12742 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
12743 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
12744 | bool can_position = false; | |
b63a16f6 | 12745 | int ret; |
465c120c | 12746 | |
b63a16f6 | 12747 | if (INTEL_GEN(dev_priv) >= 9) { |
693bdc28 VS |
12748 | /* use scaler when colorkey is not required */ |
12749 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
12750 | min_scale = 1; | |
12751 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
12752 | } | |
d8106366 | 12753 | can_position = true; |
6156a456 | 12754 | } |
d8106366 | 12755 | |
cc926387 DV |
12756 | ret = drm_plane_helper_check_state(&state->base, |
12757 | &state->clip, | |
12758 | min_scale, max_scale, | |
12759 | can_position, true); | |
b63a16f6 VS |
12760 | if (ret) |
12761 | return ret; | |
12762 | ||
cc926387 | 12763 | if (!state->base.fb) |
b63a16f6 VS |
12764 | return 0; |
12765 | ||
12766 | if (INTEL_GEN(dev_priv) >= 9) { | |
12767 | ret = skl_check_plane_surface(state); | |
12768 | if (ret) | |
12769 | return ret; | |
a0864d59 VS |
12770 | |
12771 | state->ctl = skl_plane_ctl(crtc_state, state); | |
12772 | } else { | |
5b7fcc44 VS |
12773 | ret = i9xx_check_plane_surface(state); |
12774 | if (ret) | |
12775 | return ret; | |
12776 | ||
a0864d59 | 12777 | state->ctl = i9xx_plane_ctl(crtc_state, state); |
b63a16f6 VS |
12778 | } |
12779 | ||
12780 | return 0; | |
14af293f GP |
12781 | } |
12782 | ||
5a21b665 DV |
12783 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
12784 | struct drm_crtc_state *old_crtc_state) | |
12785 | { | |
12786 | struct drm_device *dev = crtc->dev; | |
62e0fb88 | 12787 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 12788 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b707aa50 L |
12789 | struct intel_crtc_state *intel_cstate = |
12790 | to_intel_crtc_state(crtc->state); | |
ccf010fb | 12791 | struct intel_crtc_state *old_intel_cstate = |
5a21b665 | 12792 | to_intel_crtc_state(old_crtc_state); |
ccf010fb ML |
12793 | struct intel_atomic_state *old_intel_state = |
12794 | to_intel_atomic_state(old_crtc_state->state); | |
5a21b665 DV |
12795 | bool modeset = needs_modeset(crtc->state); |
12796 | ||
567f0792 ML |
12797 | if (!modeset && |
12798 | (intel_cstate->base.color_mgmt_changed || | |
12799 | intel_cstate->update_pipe)) { | |
12800 | intel_color_set_csc(crtc->state); | |
12801 | intel_color_load_luts(crtc->state); | |
12802 | } | |
12803 | ||
5a21b665 DV |
12804 | /* Perform vblank evasion around commit operation */ |
12805 | intel_pipe_update_start(intel_crtc); | |
12806 | ||
12807 | if (modeset) | |
e62929b3 | 12808 | goto out; |
5a21b665 | 12809 | |
ccf010fb ML |
12810 | if (intel_cstate->update_pipe) |
12811 | intel_update_pipe_config(intel_crtc, old_intel_cstate); | |
12812 | else if (INTEL_GEN(dev_priv) >= 9) | |
5a21b665 | 12813 | skl_detach_scalers(intel_crtc); |
62e0fb88 | 12814 | |
e62929b3 | 12815 | out: |
ccf010fb ML |
12816 | if (dev_priv->display.atomic_update_watermarks) |
12817 | dev_priv->display.atomic_update_watermarks(old_intel_state, | |
12818 | intel_cstate); | |
5a21b665 DV |
12819 | } |
12820 | ||
12821 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, | |
12822 | struct drm_crtc_state *old_crtc_state) | |
12823 | { | |
12824 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12825 | ||
8b5d27b9 | 12826 | intel_pipe_update_end(intel_crtc); |
5a21b665 DV |
12827 | } |
12828 | ||
cf4c7c12 | 12829 | /** |
4a3b8769 MR |
12830 | * intel_plane_destroy - destroy a plane |
12831 | * @plane: plane to destroy | |
cf4c7c12 | 12832 | * |
4a3b8769 MR |
12833 | * Common destruction function for all types of planes (primary, cursor, |
12834 | * sprite). | |
cf4c7c12 | 12835 | */ |
4a3b8769 | 12836 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c | 12837 | { |
465c120c | 12838 | drm_plane_cleanup(plane); |
69ae561f | 12839 | kfree(to_intel_plane(plane)); |
465c120c MR |
12840 | } |
12841 | ||
65a3fea0 | 12842 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
12843 | .update_plane = drm_atomic_helper_update_plane, |
12844 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 12845 | .destroy = intel_plane_destroy, |
a98b3431 MR |
12846 | .atomic_get_property = intel_plane_atomic_get_property, |
12847 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
12848 | .atomic_duplicate_state = intel_plane_duplicate_state, |
12849 | .atomic_destroy_state = intel_plane_destroy_state, | |
465c120c MR |
12850 | }; |
12851 | ||
f79f2692 ML |
12852 | static int |
12853 | intel_legacy_cursor_update(struct drm_plane *plane, | |
12854 | struct drm_crtc *crtc, | |
12855 | struct drm_framebuffer *fb, | |
12856 | int crtc_x, int crtc_y, | |
12857 | unsigned int crtc_w, unsigned int crtc_h, | |
12858 | uint32_t src_x, uint32_t src_y, | |
34a2ab5e DV |
12859 | uint32_t src_w, uint32_t src_h, |
12860 | struct drm_modeset_acquire_ctx *ctx) | |
f79f2692 ML |
12861 | { |
12862 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
12863 | int ret; | |
12864 | struct drm_plane_state *old_plane_state, *new_plane_state; | |
12865 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
12866 | struct drm_framebuffer *old_fb; | |
12867 | struct drm_crtc_state *crtc_state = crtc->state; | |
fd70075f | 12868 | struct i915_vma *old_vma, *vma; |
f79f2692 ML |
12869 | |
12870 | /* | |
12871 | * When crtc is inactive or there is a modeset pending, | |
12872 | * wait for it to complete in the slowpath | |
12873 | */ | |
12874 | if (!crtc_state->active || needs_modeset(crtc_state) || | |
12875 | to_intel_crtc_state(crtc_state)->update_pipe) | |
12876 | goto slow; | |
12877 | ||
12878 | old_plane_state = plane->state; | |
12879 | ||
12880 | /* | |
12881 | * If any parameters change that may affect watermarks, | |
12882 | * take the slowpath. Only changing fb or position should be | |
12883 | * in the fastpath. | |
12884 | */ | |
12885 | if (old_plane_state->crtc != crtc || | |
12886 | old_plane_state->src_w != src_w || | |
12887 | old_plane_state->src_h != src_h || | |
12888 | old_plane_state->crtc_w != crtc_w || | |
12889 | old_plane_state->crtc_h != crtc_h || | |
a5509abd | 12890 | !old_plane_state->fb != !fb) |
f79f2692 ML |
12891 | goto slow; |
12892 | ||
12893 | new_plane_state = intel_plane_duplicate_state(plane); | |
12894 | if (!new_plane_state) | |
12895 | return -ENOMEM; | |
12896 | ||
12897 | drm_atomic_set_fb_for_plane(new_plane_state, fb); | |
12898 | ||
12899 | new_plane_state->src_x = src_x; | |
12900 | new_plane_state->src_y = src_y; | |
12901 | new_plane_state->src_w = src_w; | |
12902 | new_plane_state->src_h = src_h; | |
12903 | new_plane_state->crtc_x = crtc_x; | |
12904 | new_plane_state->crtc_y = crtc_y; | |
12905 | new_plane_state->crtc_w = crtc_w; | |
12906 | new_plane_state->crtc_h = crtc_h; | |
12907 | ||
12908 | ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state), | |
12909 | to_intel_plane_state(new_plane_state)); | |
12910 | if (ret) | |
12911 | goto out_free; | |
12912 | ||
f79f2692 ML |
12913 | ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex); |
12914 | if (ret) | |
12915 | goto out_free; | |
12916 | ||
12917 | if (INTEL_INFO(dev_priv)->cursor_needs_physical) { | |
fabac484 | 12918 | int align = intel_cursor_alignment(dev_priv); |
f79f2692 ML |
12919 | |
12920 | ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align); | |
12921 | if (ret) { | |
12922 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
12923 | goto out_unlock; | |
12924 | } | |
12925 | } else { | |
f79f2692 ML |
12926 | vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation); |
12927 | if (IS_ERR(vma)) { | |
12928 | DRM_DEBUG_KMS("failed to pin object\n"); | |
12929 | ||
12930 | ret = PTR_ERR(vma); | |
12931 | goto out_unlock; | |
12932 | } | |
be1e3415 CW |
12933 | |
12934 | to_intel_plane_state(new_plane_state)->vma = vma; | |
f79f2692 ML |
12935 | } |
12936 | ||
12937 | old_fb = old_plane_state->fb; | |
be1e3415 | 12938 | old_vma = to_intel_plane_state(old_plane_state)->vma; |
f79f2692 ML |
12939 | |
12940 | i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb), | |
12941 | intel_plane->frontbuffer_bit); | |
12942 | ||
12943 | /* Swap plane state */ | |
12944 | new_plane_state->fence = old_plane_state->fence; | |
12945 | *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state); | |
12946 | new_plane_state->fence = NULL; | |
12947 | new_plane_state->fb = old_fb; | |
fd70075f | 12948 | to_intel_plane_state(new_plane_state)->vma = NULL; |
f79f2692 | 12949 | |
72259536 VS |
12950 | if (plane->state->visible) { |
12951 | trace_intel_update_plane(plane, to_intel_crtc(crtc)); | |
282dbf9b | 12952 | intel_plane->update_plane(intel_plane, |
a5509abd VS |
12953 | to_intel_crtc_state(crtc->state), |
12954 | to_intel_plane_state(plane->state)); | |
72259536 VS |
12955 | } else { |
12956 | trace_intel_disable_plane(plane, to_intel_crtc(crtc)); | |
282dbf9b | 12957 | intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc)); |
72259536 | 12958 | } |
f79f2692 | 12959 | |
fd70075f CW |
12960 | if (old_vma) |
12961 | intel_unpin_fb_vma(old_vma); | |
f79f2692 ML |
12962 | |
12963 | out_unlock: | |
12964 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
12965 | out_free: | |
12966 | intel_plane_destroy_state(plane, new_plane_state); | |
12967 | return ret; | |
12968 | ||
f79f2692 ML |
12969 | slow: |
12970 | return drm_atomic_helper_update_plane(plane, crtc, fb, | |
12971 | crtc_x, crtc_y, crtc_w, crtc_h, | |
34a2ab5e | 12972 | src_x, src_y, src_w, src_h, ctx); |
f79f2692 ML |
12973 | } |
12974 | ||
12975 | static const struct drm_plane_funcs intel_cursor_plane_funcs = { | |
12976 | .update_plane = intel_legacy_cursor_update, | |
12977 | .disable_plane = drm_atomic_helper_disable_plane, | |
12978 | .destroy = intel_plane_destroy, | |
f79f2692 ML |
12979 | .atomic_get_property = intel_plane_atomic_get_property, |
12980 | .atomic_set_property = intel_plane_atomic_set_property, | |
12981 | .atomic_duplicate_state = intel_plane_duplicate_state, | |
12982 | .atomic_destroy_state = intel_plane_destroy_state, | |
12983 | }; | |
12984 | ||
b079bd17 | 12985 | static struct intel_plane * |
580503c7 | 12986 | intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) |
465c120c | 12987 | { |
fca0ce2a VS |
12988 | struct intel_plane *primary = NULL; |
12989 | struct intel_plane_state *state = NULL; | |
465c120c | 12990 | const uint32_t *intel_primary_formats; |
93ca7e00 | 12991 | unsigned int supported_rotations; |
45e3743a | 12992 | unsigned int num_formats; |
fca0ce2a | 12993 | int ret; |
465c120c MR |
12994 | |
12995 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
b079bd17 VS |
12996 | if (!primary) { |
12997 | ret = -ENOMEM; | |
fca0ce2a | 12998 | goto fail; |
b079bd17 | 12999 | } |
465c120c | 13000 | |
8e7d688b | 13001 | state = intel_create_plane_state(&primary->base); |
b079bd17 VS |
13002 | if (!state) { |
13003 | ret = -ENOMEM; | |
fca0ce2a | 13004 | goto fail; |
b079bd17 VS |
13005 | } |
13006 | ||
8e7d688b | 13007 | primary->base.state = &state->base; |
ea2c67bb | 13008 | |
465c120c MR |
13009 | primary->can_scale = false; |
13010 | primary->max_downscale = 1; | |
580503c7 | 13011 | if (INTEL_GEN(dev_priv) >= 9) { |
6156a456 | 13012 | primary->can_scale = true; |
af99ceda | 13013 | state->scaler_id = -1; |
6156a456 | 13014 | } |
465c120c | 13015 | primary->pipe = pipe; |
e3c566df VS |
13016 | /* |
13017 | * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS | |
13018 | * port is hooked to pipe B. Hence we want plane A feeding pipe B. | |
13019 | */ | |
13020 | if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4) | |
13021 | primary->plane = (enum plane) !pipe; | |
13022 | else | |
13023 | primary->plane = (enum plane) pipe; | |
b14e5848 | 13024 | primary->id = PLANE_PRIMARY; |
a9ff8714 | 13025 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 13026 | primary->check_plane = intel_check_primary_plane; |
465c120c | 13027 | |
580503c7 | 13028 | if (INTEL_GEN(dev_priv) >= 9) { |
6c0fd451 DL |
13029 | intel_primary_formats = skl_primary_formats; |
13030 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
a8d201af ML |
13031 | |
13032 | primary->update_plane = skylake_update_primary_plane; | |
13033 | primary->disable_plane = skylake_disable_primary_plane; | |
580503c7 | 13034 | } else if (INTEL_GEN(dev_priv) >= 4) { |
568db4f2 DL |
13035 | intel_primary_formats = i965_primary_formats; |
13036 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
a8d201af ML |
13037 | |
13038 | primary->update_plane = i9xx_update_primary_plane; | |
13039 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
13040 | } else { |
13041 | intel_primary_formats = i8xx_primary_formats; | |
13042 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
a8d201af ML |
13043 | |
13044 | primary->update_plane = i9xx_update_primary_plane; | |
13045 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
13046 | } |
13047 | ||
580503c7 VS |
13048 | if (INTEL_GEN(dev_priv) >= 9) |
13049 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, | |
13050 | 0, &intel_plane_funcs, | |
38573dc1 | 13051 | intel_primary_formats, num_formats, |
e6fc3b68 | 13052 | NULL, |
38573dc1 VS |
13053 | DRM_PLANE_TYPE_PRIMARY, |
13054 | "plane 1%c", pipe_name(pipe)); | |
9beb5fea | 13055 | else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
580503c7 VS |
13056 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, |
13057 | 0, &intel_plane_funcs, | |
38573dc1 | 13058 | intel_primary_formats, num_formats, |
e6fc3b68 | 13059 | NULL, |
38573dc1 VS |
13060 | DRM_PLANE_TYPE_PRIMARY, |
13061 | "primary %c", pipe_name(pipe)); | |
13062 | else | |
580503c7 VS |
13063 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, |
13064 | 0, &intel_plane_funcs, | |
38573dc1 | 13065 | intel_primary_formats, num_formats, |
e6fc3b68 | 13066 | NULL, |
38573dc1 VS |
13067 | DRM_PLANE_TYPE_PRIMARY, |
13068 | "plane %c", plane_name(primary->plane)); | |
fca0ce2a VS |
13069 | if (ret) |
13070 | goto fail; | |
48404c1e | 13071 | |
5481e27f | 13072 | if (INTEL_GEN(dev_priv) >= 9) { |
93ca7e00 | 13073 | supported_rotations = |
c2c446ad RF |
13074 | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | |
13075 | DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270; | |
4ea7be2b VS |
13076 | } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { |
13077 | supported_rotations = | |
c2c446ad RF |
13078 | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | |
13079 | DRM_MODE_REFLECT_X; | |
5481e27f | 13080 | } else if (INTEL_GEN(dev_priv) >= 4) { |
93ca7e00 | 13081 | supported_rotations = |
c2c446ad | 13082 | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; |
93ca7e00 | 13083 | } else { |
c2c446ad | 13084 | supported_rotations = DRM_MODE_ROTATE_0; |
93ca7e00 VS |
13085 | } |
13086 | ||
5481e27f | 13087 | if (INTEL_GEN(dev_priv) >= 4) |
93ca7e00 | 13088 | drm_plane_create_rotation_property(&primary->base, |
c2c446ad | 13089 | DRM_MODE_ROTATE_0, |
93ca7e00 | 13090 | supported_rotations); |
48404c1e | 13091 | |
ea2c67bb MR |
13092 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
13093 | ||
b079bd17 | 13094 | return primary; |
fca0ce2a VS |
13095 | |
13096 | fail: | |
13097 | kfree(state); | |
13098 | kfree(primary); | |
13099 | ||
b079bd17 | 13100 | return ERR_PTR(ret); |
465c120c MR |
13101 | } |
13102 | ||
b079bd17 | 13103 | static struct intel_plane * |
b2d03b0d VS |
13104 | intel_cursor_plane_create(struct drm_i915_private *dev_priv, |
13105 | enum pipe pipe) | |
3d7d6510 | 13106 | { |
fca0ce2a VS |
13107 | struct intel_plane *cursor = NULL; |
13108 | struct intel_plane_state *state = NULL; | |
13109 | int ret; | |
3d7d6510 MR |
13110 | |
13111 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
b079bd17 VS |
13112 | if (!cursor) { |
13113 | ret = -ENOMEM; | |
fca0ce2a | 13114 | goto fail; |
b079bd17 | 13115 | } |
3d7d6510 | 13116 | |
8e7d688b | 13117 | state = intel_create_plane_state(&cursor->base); |
b079bd17 VS |
13118 | if (!state) { |
13119 | ret = -ENOMEM; | |
fca0ce2a | 13120 | goto fail; |
b079bd17 VS |
13121 | } |
13122 | ||
8e7d688b | 13123 | cursor->base.state = &state->base; |
ea2c67bb | 13124 | |
3d7d6510 MR |
13125 | cursor->can_scale = false; |
13126 | cursor->max_downscale = 1; | |
13127 | cursor->pipe = pipe; | |
13128 | cursor->plane = pipe; | |
b14e5848 | 13129 | cursor->id = PLANE_CURSOR; |
a9ff8714 | 13130 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
b2d03b0d VS |
13131 | |
13132 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { | |
13133 | cursor->update_plane = i845_update_cursor; | |
13134 | cursor->disable_plane = i845_disable_cursor; | |
659056f2 | 13135 | cursor->check_plane = i845_check_cursor; |
b2d03b0d VS |
13136 | } else { |
13137 | cursor->update_plane = i9xx_update_cursor; | |
13138 | cursor->disable_plane = i9xx_disable_cursor; | |
659056f2 | 13139 | cursor->check_plane = i9xx_check_cursor; |
b2d03b0d | 13140 | } |
3d7d6510 | 13141 | |
cd5dcbf1 VS |
13142 | cursor->cursor.base = ~0; |
13143 | cursor->cursor.cntl = ~0; | |
024faac7 VS |
13144 | |
13145 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv)) | |
13146 | cursor->cursor.size = ~0; | |
3d7d6510 | 13147 | |
580503c7 | 13148 | ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, |
f79f2692 | 13149 | 0, &intel_cursor_plane_funcs, |
fca0ce2a VS |
13150 | intel_cursor_formats, |
13151 | ARRAY_SIZE(intel_cursor_formats), | |
e6fc3b68 | 13152 | NULL, DRM_PLANE_TYPE_CURSOR, |
38573dc1 | 13153 | "cursor %c", pipe_name(pipe)); |
fca0ce2a VS |
13154 | if (ret) |
13155 | goto fail; | |
4398ad45 | 13156 | |
5481e27f | 13157 | if (INTEL_GEN(dev_priv) >= 4) |
93ca7e00 | 13158 | drm_plane_create_rotation_property(&cursor->base, |
c2c446ad RF |
13159 | DRM_MODE_ROTATE_0, |
13160 | DRM_MODE_ROTATE_0 | | |
13161 | DRM_MODE_ROTATE_180); | |
4398ad45 | 13162 | |
580503c7 | 13163 | if (INTEL_GEN(dev_priv) >= 9) |
af99ceda CK |
13164 | state->scaler_id = -1; |
13165 | ||
ea2c67bb MR |
13166 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
13167 | ||
b079bd17 | 13168 | return cursor; |
fca0ce2a VS |
13169 | |
13170 | fail: | |
13171 | kfree(state); | |
13172 | kfree(cursor); | |
13173 | ||
b079bd17 | 13174 | return ERR_PTR(ret); |
3d7d6510 MR |
13175 | } |
13176 | ||
1c74eeaf NM |
13177 | static void intel_crtc_init_scalers(struct intel_crtc *crtc, |
13178 | struct intel_crtc_state *crtc_state) | |
549e2bfb | 13179 | { |
65edccce VS |
13180 | struct intel_crtc_scaler_state *scaler_state = |
13181 | &crtc_state->scaler_state; | |
1c74eeaf | 13182 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
549e2bfb | 13183 | int i; |
549e2bfb | 13184 | |
1c74eeaf NM |
13185 | crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe]; |
13186 | if (!crtc->num_scalers) | |
13187 | return; | |
13188 | ||
65edccce VS |
13189 | for (i = 0; i < crtc->num_scalers; i++) { |
13190 | struct intel_scaler *scaler = &scaler_state->scalers[i]; | |
13191 | ||
13192 | scaler->in_use = 0; | |
13193 | scaler->mode = PS_SCALER_MODE_DYN; | |
549e2bfb CK |
13194 | } |
13195 | ||
13196 | scaler_state->scaler_id = -1; | |
13197 | } | |
13198 | ||
5ab0d85b | 13199 | static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) |
79e53945 JB |
13200 | { |
13201 | struct intel_crtc *intel_crtc; | |
f5de6e07 | 13202 | struct intel_crtc_state *crtc_state = NULL; |
b079bd17 VS |
13203 | struct intel_plane *primary = NULL; |
13204 | struct intel_plane *cursor = NULL; | |
a81d6fa0 | 13205 | int sprite, ret; |
79e53945 | 13206 | |
955382f3 | 13207 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
b079bd17 VS |
13208 | if (!intel_crtc) |
13209 | return -ENOMEM; | |
79e53945 | 13210 | |
f5de6e07 | 13211 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
b079bd17 VS |
13212 | if (!crtc_state) { |
13213 | ret = -ENOMEM; | |
f5de6e07 | 13214 | goto fail; |
b079bd17 | 13215 | } |
550acefd ACO |
13216 | intel_crtc->config = crtc_state; |
13217 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 13218 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 13219 | |
580503c7 | 13220 | primary = intel_primary_plane_create(dev_priv, pipe); |
b079bd17 VS |
13221 | if (IS_ERR(primary)) { |
13222 | ret = PTR_ERR(primary); | |
3d7d6510 | 13223 | goto fail; |
b079bd17 | 13224 | } |
d97d7b48 | 13225 | intel_crtc->plane_ids_mask |= BIT(primary->id); |
3d7d6510 | 13226 | |
a81d6fa0 | 13227 | for_each_sprite(dev_priv, pipe, sprite) { |
b079bd17 VS |
13228 | struct intel_plane *plane; |
13229 | ||
580503c7 | 13230 | plane = intel_sprite_plane_create(dev_priv, pipe, sprite); |
d2b2cbce | 13231 | if (IS_ERR(plane)) { |
b079bd17 VS |
13232 | ret = PTR_ERR(plane); |
13233 | goto fail; | |
13234 | } | |
d97d7b48 | 13235 | intel_crtc->plane_ids_mask |= BIT(plane->id); |
a81d6fa0 VS |
13236 | } |
13237 | ||
580503c7 | 13238 | cursor = intel_cursor_plane_create(dev_priv, pipe); |
d2b2cbce | 13239 | if (IS_ERR(cursor)) { |
b079bd17 | 13240 | ret = PTR_ERR(cursor); |
3d7d6510 | 13241 | goto fail; |
b079bd17 | 13242 | } |
d97d7b48 | 13243 | intel_crtc->plane_ids_mask |= BIT(cursor->id); |
3d7d6510 | 13244 | |
5ab0d85b | 13245 | ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base, |
b079bd17 VS |
13246 | &primary->base, &cursor->base, |
13247 | &intel_crtc_funcs, | |
4d5d72b7 | 13248 | "pipe %c", pipe_name(pipe)); |
3d7d6510 MR |
13249 | if (ret) |
13250 | goto fail; | |
79e53945 | 13251 | |
80824003 | 13252 | intel_crtc->pipe = pipe; |
e3c566df | 13253 | intel_crtc->plane = primary->plane; |
80824003 | 13254 | |
1c74eeaf NM |
13255 | /* initialize shared scalers */ |
13256 | intel_crtc_init_scalers(intel_crtc, crtc_state); | |
13257 | ||
22fd0fab JB |
13258 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
13259 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
e2af48c6 VS |
13260 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc; |
13261 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc; | |
22fd0fab | 13262 | |
79e53945 | 13263 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 | 13264 | |
8563b1e8 LL |
13265 | intel_color_init(&intel_crtc->base); |
13266 | ||
87b6b101 | 13267 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
b079bd17 VS |
13268 | |
13269 | return 0; | |
3d7d6510 MR |
13270 | |
13271 | fail: | |
b079bd17 VS |
13272 | /* |
13273 | * drm_mode_config_cleanup() will free up any | |
13274 | * crtcs/planes already initialized. | |
13275 | */ | |
f5de6e07 | 13276 | kfree(crtc_state); |
3d7d6510 | 13277 | kfree(intel_crtc); |
b079bd17 VS |
13278 | |
13279 | return ret; | |
79e53945 JB |
13280 | } |
13281 | ||
752aa88a JB |
13282 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
13283 | { | |
6e9f798d | 13284 | struct drm_device *dev = connector->base.dev; |
752aa88a | 13285 | |
51fd371b | 13286 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 13287 | |
51ec53da | 13288 | if (!connector->base.state->crtc) |
752aa88a JB |
13289 | return INVALID_PIPE; |
13290 | ||
51ec53da | 13291 | return to_intel_crtc(connector->base.state->crtc)->pipe; |
752aa88a JB |
13292 | } |
13293 | ||
08d7b3d1 | 13294 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 13295 | struct drm_file *file) |
08d7b3d1 | 13296 | { |
08d7b3d1 | 13297 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 13298 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 13299 | struct intel_crtc *crtc; |
08d7b3d1 | 13300 | |
7707e653 | 13301 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
71240ed2 | 13302 | if (!drmmode_crtc) |
3f2c2057 | 13303 | return -ENOENT; |
08d7b3d1 | 13304 | |
7707e653 | 13305 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 13306 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 13307 | |
c05422d5 | 13308 | return 0; |
08d7b3d1 CW |
13309 | } |
13310 | ||
66a9278e | 13311 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 13312 | { |
66a9278e DV |
13313 | struct drm_device *dev = encoder->base.dev; |
13314 | struct intel_encoder *source_encoder; | |
79e53945 | 13315 | int index_mask = 0; |
79e53945 JB |
13316 | int entry = 0; |
13317 | ||
b2784e15 | 13318 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 13319 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
13320 | index_mask |= (1 << entry); |
13321 | ||
79e53945 JB |
13322 | entry++; |
13323 | } | |
4ef69c7a | 13324 | |
79e53945 JB |
13325 | return index_mask; |
13326 | } | |
13327 | ||
646d5772 | 13328 | static bool has_edp_a(struct drm_i915_private *dev_priv) |
4d302442 | 13329 | { |
646d5772 | 13330 | if (!IS_MOBILE(dev_priv)) |
4d302442 CW |
13331 | return false; |
13332 | ||
13333 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
13334 | return false; | |
13335 | ||
5db94019 | 13336 | if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
13337 | return false; |
13338 | ||
13339 | return true; | |
13340 | } | |
13341 | ||
6315b5d3 | 13342 | static bool intel_crt_present(struct drm_i915_private *dev_priv) |
84b4e042 | 13343 | { |
6315b5d3 | 13344 | if (INTEL_GEN(dev_priv) >= 9) |
884497ed DL |
13345 | return false; |
13346 | ||
50a0bc90 | 13347 | if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) |
84b4e042 JB |
13348 | return false; |
13349 | ||
920a14b2 | 13350 | if (IS_CHERRYVIEW(dev_priv)) |
84b4e042 JB |
13351 | return false; |
13352 | ||
4f8036a2 TU |
13353 | if (HAS_PCH_LPT_H(dev_priv) && |
13354 | I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) | |
65e472e4 VS |
13355 | return false; |
13356 | ||
70ac54d0 | 13357 | /* DDI E can't be used if DDI A requires 4 lanes */ |
4f8036a2 | 13358 | if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) |
70ac54d0 VS |
13359 | return false; |
13360 | ||
e4abb733 | 13361 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
13362 | return false; |
13363 | ||
13364 | return true; | |
13365 | } | |
13366 | ||
8090ba8c ID |
13367 | void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv) |
13368 | { | |
13369 | int pps_num; | |
13370 | int pps_idx; | |
13371 | ||
13372 | if (HAS_DDI(dev_priv)) | |
13373 | return; | |
13374 | /* | |
13375 | * This w/a is needed at least on CPT/PPT, but to be sure apply it | |
13376 | * everywhere where registers can be write protected. | |
13377 | */ | |
13378 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
13379 | pps_num = 2; | |
13380 | else | |
13381 | pps_num = 1; | |
13382 | ||
13383 | for (pps_idx = 0; pps_idx < pps_num; pps_idx++) { | |
13384 | u32 val = I915_READ(PP_CONTROL(pps_idx)); | |
13385 | ||
13386 | val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS; | |
13387 | I915_WRITE(PP_CONTROL(pps_idx), val); | |
13388 | } | |
13389 | } | |
13390 | ||
44cb734c ID |
13391 | static void intel_pps_init(struct drm_i915_private *dev_priv) |
13392 | { | |
cc3f90f0 | 13393 | if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv)) |
44cb734c ID |
13394 | dev_priv->pps_mmio_base = PCH_PPS_BASE; |
13395 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
13396 | dev_priv->pps_mmio_base = VLV_PPS_BASE; | |
13397 | else | |
13398 | dev_priv->pps_mmio_base = PPS_BASE; | |
8090ba8c ID |
13399 | |
13400 | intel_pps_unlock_regs_wa(dev_priv); | |
44cb734c ID |
13401 | } |
13402 | ||
c39055b0 | 13403 | static void intel_setup_outputs(struct drm_i915_private *dev_priv) |
79e53945 | 13404 | { |
4ef69c7a | 13405 | struct intel_encoder *encoder; |
cb0953d7 | 13406 | bool dpd_is_edp = false; |
79e53945 | 13407 | |
44cb734c ID |
13408 | intel_pps_init(dev_priv); |
13409 | ||
97a824e1 ID |
13410 | /* |
13411 | * intel_edp_init_connector() depends on this completing first, to | |
13412 | * prevent the registeration of both eDP and LVDS and the incorrect | |
13413 | * sharing of the PPS. | |
13414 | */ | |
c39055b0 | 13415 | intel_lvds_init(dev_priv); |
79e53945 | 13416 | |
6315b5d3 | 13417 | if (intel_crt_present(dev_priv)) |
c39055b0 | 13418 | intel_crt_init(dev_priv); |
cb0953d7 | 13419 | |
cc3f90f0 | 13420 | if (IS_GEN9_LP(dev_priv)) { |
c776eb2e VK |
13421 | /* |
13422 | * FIXME: Broxton doesn't support port detection via the | |
13423 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
13424 | * detect the ports. | |
13425 | */ | |
c39055b0 ACO |
13426 | intel_ddi_init(dev_priv, PORT_A); |
13427 | intel_ddi_init(dev_priv, PORT_B); | |
13428 | intel_ddi_init(dev_priv, PORT_C); | |
c6c794a2 | 13429 | |
c39055b0 | 13430 | intel_dsi_init(dev_priv); |
4f8036a2 | 13431 | } else if (HAS_DDI(dev_priv)) { |
0e72a5b5 ED |
13432 | int found; |
13433 | ||
de31facd JB |
13434 | /* |
13435 | * Haswell uses DDI functions to detect digital outputs. | |
13436 | * On SKL pre-D0 the strap isn't connected, so we assume | |
13437 | * it's there. | |
13438 | */ | |
77179400 | 13439 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 13440 | /* WaIgnoreDDIAStrap: skl */ |
b976dc53 | 13441 | if (found || IS_GEN9_BC(dev_priv)) |
c39055b0 | 13442 | intel_ddi_init(dev_priv, PORT_A); |
0e72a5b5 ED |
13443 | |
13444 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
13445 | * register */ | |
13446 | found = I915_READ(SFUSE_STRAP); | |
13447 | ||
13448 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
c39055b0 | 13449 | intel_ddi_init(dev_priv, PORT_B); |
0e72a5b5 | 13450 | if (found & SFUSE_STRAP_DDIC_DETECTED) |
c39055b0 | 13451 | intel_ddi_init(dev_priv, PORT_C); |
0e72a5b5 | 13452 | if (found & SFUSE_STRAP_DDID_DETECTED) |
c39055b0 | 13453 | intel_ddi_init(dev_priv, PORT_D); |
2800e4c2 RV |
13454 | /* |
13455 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
13456 | */ | |
b976dc53 | 13457 | if (IS_GEN9_BC(dev_priv) && |
2800e4c2 RV |
13458 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
13459 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
13460 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
c39055b0 | 13461 | intel_ddi_init(dev_priv, PORT_E); |
2800e4c2 | 13462 | |
6e266956 | 13463 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
cb0953d7 | 13464 | int found; |
dd11bc10 | 13465 | dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D); |
270b3042 | 13466 | |
646d5772 | 13467 | if (has_edp_a(dev_priv)) |
c39055b0 | 13468 | intel_dp_init(dev_priv, DP_A, PORT_A); |
cb0953d7 | 13469 | |
dc0fa718 | 13470 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 13471 | /* PCH SDVOB multiplex with HDMIB */ |
c39055b0 | 13472 | found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); |
30ad48b7 | 13473 | if (!found) |
c39055b0 | 13474 | intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); |
5eb08b69 | 13475 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
c39055b0 | 13476 | intel_dp_init(dev_priv, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
13477 | } |
13478 | ||
dc0fa718 | 13479 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
c39055b0 | 13480 | intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); |
30ad48b7 | 13481 | |
dc0fa718 | 13482 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
c39055b0 | 13483 | intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D); |
30ad48b7 | 13484 | |
5eb08b69 | 13485 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
c39055b0 | 13486 | intel_dp_init(dev_priv, PCH_DP_C, PORT_C); |
5eb08b69 | 13487 | |
270b3042 | 13488 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
c39055b0 | 13489 | intel_dp_init(dev_priv, PCH_DP_D, PORT_D); |
920a14b2 | 13490 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
22f35042 | 13491 | bool has_edp, has_port; |
457c52d8 | 13492 | |
e17ac6db VS |
13493 | /* |
13494 | * The DP_DETECTED bit is the latched state of the DDC | |
13495 | * SDA pin at boot. However since eDP doesn't require DDC | |
13496 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
13497 | * eDP ports may have been muxed to an alternate function. | |
13498 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
13499 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
13500 | * detect eDP ports. | |
22f35042 VS |
13501 | * |
13502 | * Sadly the straps seem to be missing sometimes even for HDMI | |
13503 | * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap | |
13504 | * and VBT for the presence of the port. Additionally we can't | |
13505 | * trust the port type the VBT declares as we've seen at least | |
13506 | * HDMI ports that the VBT claim are DP or eDP. | |
e17ac6db | 13507 | */ |
dd11bc10 | 13508 | has_edp = intel_dp_is_edp(dev_priv, PORT_B); |
22f35042 VS |
13509 | has_port = intel_bios_is_port_present(dev_priv, PORT_B); |
13510 | if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port) | |
c39055b0 | 13511 | has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B); |
22f35042 | 13512 | if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) |
c39055b0 | 13513 | intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); |
585a94b8 | 13514 | |
dd11bc10 | 13515 | has_edp = intel_dp_is_edp(dev_priv, PORT_C); |
22f35042 VS |
13516 | has_port = intel_bios_is_port_present(dev_priv, PORT_C); |
13517 | if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port) | |
c39055b0 | 13518 | has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C); |
22f35042 | 13519 | if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) |
c39055b0 | 13520 | intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); |
19c03924 | 13521 | |
920a14b2 | 13522 | if (IS_CHERRYVIEW(dev_priv)) { |
22f35042 VS |
13523 | /* |
13524 | * eDP not supported on port D, | |
13525 | * so no need to worry about it | |
13526 | */ | |
13527 | has_port = intel_bios_is_port_present(dev_priv, PORT_D); | |
13528 | if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port) | |
c39055b0 | 13529 | intel_dp_init(dev_priv, CHV_DP_D, PORT_D); |
22f35042 | 13530 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port) |
c39055b0 | 13531 | intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D); |
9418c1f1 VS |
13532 | } |
13533 | ||
c39055b0 | 13534 | intel_dsi_init(dev_priv); |
5db94019 | 13535 | } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) { |
27185ae1 | 13536 | bool found = false; |
7d57382e | 13537 | |
e2debe91 | 13538 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 13539 | DRM_DEBUG_KMS("probing SDVOB\n"); |
c39055b0 | 13540 | found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); |
9beb5fea | 13541 | if (!found && IS_G4X(dev_priv)) { |
b01f2c3a | 13542 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
c39055b0 | 13543 | intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); |
b01f2c3a | 13544 | } |
27185ae1 | 13545 | |
9beb5fea | 13546 | if (!found && IS_G4X(dev_priv)) |
c39055b0 | 13547 | intel_dp_init(dev_priv, DP_B, PORT_B); |
725e30ad | 13548 | } |
13520b05 KH |
13549 | |
13550 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 13551 | |
e2debe91 | 13552 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 13553 | DRM_DEBUG_KMS("probing SDVOC\n"); |
c39055b0 | 13554 | found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); |
b01f2c3a | 13555 | } |
27185ae1 | 13556 | |
e2debe91 | 13557 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 13558 | |
9beb5fea | 13559 | if (IS_G4X(dev_priv)) { |
b01f2c3a | 13560 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
c39055b0 | 13561 | intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); |
b01f2c3a | 13562 | } |
9beb5fea | 13563 | if (IS_G4X(dev_priv)) |
c39055b0 | 13564 | intel_dp_init(dev_priv, DP_C, PORT_C); |
725e30ad | 13565 | } |
27185ae1 | 13566 | |
9beb5fea | 13567 | if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED)) |
c39055b0 | 13568 | intel_dp_init(dev_priv, DP_D, PORT_D); |
5db94019 | 13569 | } else if (IS_GEN2(dev_priv)) |
c39055b0 | 13570 | intel_dvo_init(dev_priv); |
79e53945 | 13571 | |
56b857a5 | 13572 | if (SUPPORTS_TV(dev_priv)) |
c39055b0 | 13573 | intel_tv_init(dev_priv); |
79e53945 | 13574 | |
c39055b0 | 13575 | intel_psr_init(dev_priv); |
7c8f8a70 | 13576 | |
c39055b0 | 13577 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
4ef69c7a CW |
13578 | encoder->base.possible_crtcs = encoder->crtc_mask; |
13579 | encoder->base.possible_clones = | |
66a9278e | 13580 | intel_encoder_clones(encoder); |
79e53945 | 13581 | } |
47356eb6 | 13582 | |
c39055b0 | 13583 | intel_init_pch_refclk(dev_priv); |
270b3042 | 13584 | |
c39055b0 | 13585 | drm_helper_move_panel_connectors_to_head(&dev_priv->drm); |
79e53945 JB |
13586 | } |
13587 | ||
13588 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
13589 | { | |
13590 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 | 13591 | |
ef2d633e | 13592 | drm_framebuffer_cleanup(fb); |
70001cd2 | 13593 | |
dd689287 CW |
13594 | i915_gem_object_lock(intel_fb->obj); |
13595 | WARN_ON(!intel_fb->obj->framebuffer_references--); | |
13596 | i915_gem_object_unlock(intel_fb->obj); | |
13597 | ||
f8c417cd | 13598 | i915_gem_object_put(intel_fb->obj); |
70001cd2 | 13599 | |
79e53945 JB |
13600 | kfree(intel_fb); |
13601 | } | |
13602 | ||
13603 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 13604 | struct drm_file *file, |
79e53945 JB |
13605 | unsigned int *handle) |
13606 | { | |
13607 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 13608 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 13609 | |
cc917ab4 CW |
13610 | if (obj->userptr.mm) { |
13611 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
13612 | return -EINVAL; | |
13613 | } | |
13614 | ||
05394f39 | 13615 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
13616 | } |
13617 | ||
86c98588 RV |
13618 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
13619 | struct drm_file *file, | |
13620 | unsigned flags, unsigned color, | |
13621 | struct drm_clip_rect *clips, | |
13622 | unsigned num_clips) | |
13623 | { | |
5a97bcc6 | 13624 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
86c98588 | 13625 | |
5a97bcc6 | 13626 | i915_gem_object_flush_if_display(obj); |
d59b21ec | 13627 | intel_fb_obj_flush(obj, ORIGIN_DIRTYFB); |
86c98588 RV |
13628 | |
13629 | return 0; | |
13630 | } | |
13631 | ||
79e53945 JB |
13632 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
13633 | .destroy = intel_user_framebuffer_destroy, | |
13634 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 13635 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
13636 | }; |
13637 | ||
b321803d | 13638 | static |
920a14b2 TU |
13639 | u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv, |
13640 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 13641 | { |
24dbf51a | 13642 | u32 gen = INTEL_GEN(dev_priv); |
b321803d DL |
13643 | |
13644 | if (gen >= 9) { | |
ac484963 VS |
13645 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
13646 | ||
b321803d DL |
13647 | /* "The stride in bytes must not exceed the of the size of 8K |
13648 | * pixels and 32K bytes." | |
13649 | */ | |
ac484963 | 13650 | return min(8192 * cpp, 32768); |
6401c37d | 13651 | } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) { |
b321803d DL |
13652 | return 32*1024; |
13653 | } else if (gen >= 4) { | |
13654 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
13655 | return 16*1024; | |
13656 | else | |
13657 | return 32*1024; | |
13658 | } else if (gen >= 3) { | |
13659 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
13660 | return 8*1024; | |
13661 | else | |
13662 | return 16*1024; | |
13663 | } else { | |
13664 | /* XXX DSPC is limited to 4k tiled */ | |
13665 | return 8*1024; | |
13666 | } | |
13667 | } | |
13668 | ||
24dbf51a CW |
13669 | static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, |
13670 | struct drm_i915_gem_object *obj, | |
13671 | struct drm_mode_fb_cmd2 *mode_cmd) | |
79e53945 | 13672 | { |
24dbf51a | 13673 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
2e2adb05 | 13674 | struct drm_framebuffer *fb = &intel_fb->base; |
b3c11ac2 | 13675 | struct drm_format_name_buf format_name; |
2e2adb05 | 13676 | u32 pitch_limit; |
dd689287 | 13677 | unsigned int tiling, stride; |
24dbf51a | 13678 | int ret = -EINVAL; |
2e2adb05 | 13679 | int i; |
79e53945 | 13680 | |
dd689287 CW |
13681 | i915_gem_object_lock(obj); |
13682 | obj->framebuffer_references++; | |
13683 | tiling = i915_gem_object_get_tiling(obj); | |
13684 | stride = i915_gem_object_get_stride(obj); | |
13685 | i915_gem_object_unlock(obj); | |
dd4916c5 | 13686 | |
2a80eada | 13687 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
c2ff7370 VS |
13688 | /* |
13689 | * If there's a fence, enforce that | |
13690 | * the fb modifier and tiling mode match. | |
13691 | */ | |
13692 | if (tiling != I915_TILING_NONE && | |
13693 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
144cc143 | 13694 | DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n"); |
24dbf51a | 13695 | goto err; |
2a80eada DV |
13696 | } |
13697 | } else { | |
c2ff7370 | 13698 | if (tiling == I915_TILING_X) { |
2a80eada | 13699 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; |
c2ff7370 | 13700 | } else if (tiling == I915_TILING_Y) { |
144cc143 | 13701 | DRM_DEBUG_KMS("No Y tiling for legacy addfb\n"); |
24dbf51a | 13702 | goto err; |
2a80eada DV |
13703 | } |
13704 | } | |
13705 | ||
9a8f0a12 TU |
13706 | /* Passed in modifier sanity checking. */ |
13707 | switch (mode_cmd->modifier[0]) { | |
2e2adb05 VS |
13708 | case I915_FORMAT_MOD_Y_TILED_CCS: |
13709 | case I915_FORMAT_MOD_Yf_TILED_CCS: | |
13710 | switch (mode_cmd->pixel_format) { | |
13711 | case DRM_FORMAT_XBGR8888: | |
13712 | case DRM_FORMAT_ABGR8888: | |
13713 | case DRM_FORMAT_XRGB8888: | |
13714 | case DRM_FORMAT_ARGB8888: | |
13715 | break; | |
13716 | default: | |
13717 | DRM_DEBUG_KMS("RC supported only with RGB8888 formats\n"); | |
13718 | goto err; | |
13719 | } | |
13720 | /* fall through */ | |
9a8f0a12 TU |
13721 | case I915_FORMAT_MOD_Y_TILED: |
13722 | case I915_FORMAT_MOD_Yf_TILED: | |
6315b5d3 | 13723 | if (INTEL_GEN(dev_priv) < 9) { |
144cc143 VS |
13724 | DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n", |
13725 | mode_cmd->modifier[0]); | |
24dbf51a | 13726 | goto err; |
9a8f0a12 | 13727 | } |
2f075565 | 13728 | case DRM_FORMAT_MOD_LINEAR: |
9a8f0a12 TU |
13729 | case I915_FORMAT_MOD_X_TILED: |
13730 | break; | |
13731 | default: | |
144cc143 VS |
13732 | DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n", |
13733 | mode_cmd->modifier[0]); | |
24dbf51a | 13734 | goto err; |
c16ed4be | 13735 | } |
57cd6508 | 13736 | |
c2ff7370 VS |
13737 | /* |
13738 | * gen2/3 display engine uses the fence if present, | |
13739 | * so the tiling mode must match the fb modifier exactly. | |
13740 | */ | |
13741 | if (INTEL_INFO(dev_priv)->gen < 4 && | |
13742 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
144cc143 | 13743 | DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n"); |
9aceb5c1 | 13744 | goto err; |
c2ff7370 VS |
13745 | } |
13746 | ||
920a14b2 | 13747 | pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0], |
b321803d | 13748 | mode_cmd->pixel_format); |
a35cdaa0 | 13749 | if (mode_cmd->pitches[0] > pitch_limit) { |
144cc143 | 13750 | DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n", |
2f075565 | 13751 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ? |
144cc143 VS |
13752 | "tiled" : "linear", |
13753 | mode_cmd->pitches[0], pitch_limit); | |
24dbf51a | 13754 | goto err; |
c16ed4be | 13755 | } |
5d7bd705 | 13756 | |
c2ff7370 VS |
13757 | /* |
13758 | * If there's a fence, enforce that | |
13759 | * the fb pitch and fence stride match. | |
13760 | */ | |
144cc143 VS |
13761 | if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) { |
13762 | DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n", | |
13763 | mode_cmd->pitches[0], stride); | |
24dbf51a | 13764 | goto err; |
c16ed4be | 13765 | } |
5d7bd705 | 13766 | |
57779d06 | 13767 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 13768 | switch (mode_cmd->pixel_format) { |
57779d06 | 13769 | case DRM_FORMAT_C8: |
04b3924d VS |
13770 | case DRM_FORMAT_RGB565: |
13771 | case DRM_FORMAT_XRGB8888: | |
13772 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
13773 | break; |
13774 | case DRM_FORMAT_XRGB1555: | |
6315b5d3 | 13775 | if (INTEL_GEN(dev_priv) > 3) { |
144cc143 VS |
13776 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
13777 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 13778 | goto err; |
c16ed4be | 13779 | } |
57779d06 | 13780 | break; |
57779d06 | 13781 | case DRM_FORMAT_ABGR8888: |
920a14b2 | 13782 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
6315b5d3 | 13783 | INTEL_GEN(dev_priv) < 9) { |
144cc143 VS |
13784 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
13785 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 13786 | goto err; |
6c0fd451 DL |
13787 | } |
13788 | break; | |
13789 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 13790 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 13791 | case DRM_FORMAT_XBGR2101010: |
6315b5d3 | 13792 | if (INTEL_GEN(dev_priv) < 4) { |
144cc143 VS |
13793 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
13794 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 13795 | goto err; |
c16ed4be | 13796 | } |
b5626747 | 13797 | break; |
7531208b | 13798 | case DRM_FORMAT_ABGR2101010: |
920a14b2 | 13799 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
144cc143 VS |
13800 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
13801 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 13802 | goto err; |
7531208b DL |
13803 | } |
13804 | break; | |
04b3924d VS |
13805 | case DRM_FORMAT_YUYV: |
13806 | case DRM_FORMAT_UYVY: | |
13807 | case DRM_FORMAT_YVYU: | |
13808 | case DRM_FORMAT_VYUY: | |
ab33081a | 13809 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) { |
144cc143 VS |
13810 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
13811 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 13812 | goto err; |
c16ed4be | 13813 | } |
57cd6508 CW |
13814 | break; |
13815 | default: | |
144cc143 VS |
13816 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
13817 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 13818 | goto err; |
57cd6508 CW |
13819 | } |
13820 | ||
90f9a336 VS |
13821 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
13822 | if (mode_cmd->offsets[0] != 0) | |
24dbf51a | 13823 | goto err; |
90f9a336 | 13824 | |
2e2adb05 | 13825 | drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd); |
d88c4afd | 13826 | |
2e2adb05 VS |
13827 | for (i = 0; i < fb->format->num_planes; i++) { |
13828 | u32 stride_alignment; | |
13829 | ||
13830 | if (mode_cmd->handles[i] != mode_cmd->handles[0]) { | |
13831 | DRM_DEBUG_KMS("bad plane %d handle\n", i); | |
13832 | return -EINVAL; | |
13833 | } | |
13834 | ||
13835 | stride_alignment = intel_fb_stride_alignment(fb, i); | |
13836 | ||
13837 | /* | |
13838 | * Display WA #0531: skl,bxt,kbl,glk | |
13839 | * | |
13840 | * Render decompression and plane width > 3840 | |
13841 | * combined with horizontal panning requires the | |
13842 | * plane stride to be a multiple of 4. We'll just | |
13843 | * require the entire fb to accommodate that to avoid | |
13844 | * potential runtime errors at plane configuration time. | |
13845 | */ | |
13846 | if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 && | |
13847 | (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || | |
13848 | fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) | |
13849 | stride_alignment *= 4; | |
13850 | ||
13851 | if (fb->pitches[i] & (stride_alignment - 1)) { | |
13852 | DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n", | |
13853 | i, fb->pitches[i], stride_alignment); | |
13854 | goto err; | |
13855 | } | |
d88c4afd VS |
13856 | } |
13857 | ||
c7d73f6a DV |
13858 | intel_fb->obj = obj; |
13859 | ||
2e2adb05 | 13860 | ret = intel_fill_fb_info(dev_priv, fb); |
6687c906 | 13861 | if (ret) |
9aceb5c1 | 13862 | goto err; |
2d7a215f | 13863 | |
2e2adb05 | 13864 | ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs); |
79e53945 JB |
13865 | if (ret) { |
13866 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
24dbf51a | 13867 | goto err; |
79e53945 JB |
13868 | } |
13869 | ||
79e53945 | 13870 | return 0; |
24dbf51a CW |
13871 | |
13872 | err: | |
dd689287 CW |
13873 | i915_gem_object_lock(obj); |
13874 | obj->framebuffer_references--; | |
13875 | i915_gem_object_unlock(obj); | |
24dbf51a | 13876 | return ret; |
79e53945 JB |
13877 | } |
13878 | ||
79e53945 JB |
13879 | static struct drm_framebuffer * |
13880 | intel_user_framebuffer_create(struct drm_device *dev, | |
13881 | struct drm_file *filp, | |
1eb83451 | 13882 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 13883 | { |
dcb1394e | 13884 | struct drm_framebuffer *fb; |
05394f39 | 13885 | struct drm_i915_gem_object *obj; |
76dc3769 | 13886 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 13887 | |
03ac0642 CW |
13888 | obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]); |
13889 | if (!obj) | |
cce13ff7 | 13890 | return ERR_PTR(-ENOENT); |
79e53945 | 13891 | |
24dbf51a | 13892 | fb = intel_framebuffer_create(obj, &mode_cmd); |
dcb1394e | 13893 | if (IS_ERR(fb)) |
f0cd5182 | 13894 | i915_gem_object_put(obj); |
dcb1394e LW |
13895 | |
13896 | return fb; | |
79e53945 JB |
13897 | } |
13898 | ||
778e23a9 CW |
13899 | static void intel_atomic_state_free(struct drm_atomic_state *state) |
13900 | { | |
13901 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
13902 | ||
13903 | drm_atomic_state_default_release(state); | |
13904 | ||
13905 | i915_sw_fence_fini(&intel_state->commit_ready); | |
13906 | ||
13907 | kfree(state); | |
13908 | } | |
13909 | ||
79e53945 | 13910 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 13911 | .fb_create = intel_user_framebuffer_create, |
bbfb6ce8 | 13912 | .get_format_info = intel_get_format_info, |
0632fef6 | 13913 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
13914 | .atomic_check = intel_atomic_check, |
13915 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
13916 | .atomic_state_alloc = intel_atomic_state_alloc, |
13917 | .atomic_state_clear = intel_atomic_state_clear, | |
778e23a9 | 13918 | .atomic_state_free = intel_atomic_state_free, |
79e53945 JB |
13919 | }; |
13920 | ||
88212941 ID |
13921 | /** |
13922 | * intel_init_display_hooks - initialize the display modesetting hooks | |
13923 | * @dev_priv: device private | |
13924 | */ | |
13925 | void intel_init_display_hooks(struct drm_i915_private *dev_priv) | |
e70236a8 | 13926 | { |
7ff89ca2 VS |
13927 | intel_init_cdclk_hooks(dev_priv); |
13928 | ||
88212941 | 13929 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
bc8d7dff | 13930 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
13931 | dev_priv->display.get_initial_plane_config = |
13932 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
13933 | dev_priv->display.crtc_compute_clock = |
13934 | haswell_crtc_compute_clock; | |
13935 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
13936 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 13937 | } else if (HAS_DDI(dev_priv)) { |
0e8ffe1b | 13938 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
13939 | dev_priv->display.get_initial_plane_config = |
13940 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
13941 | dev_priv->display.crtc_compute_clock = |
13942 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
13943 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
13944 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 13945 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
0e8ffe1b | 13946 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
13947 | dev_priv->display.get_initial_plane_config = |
13948 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
13949 | dev_priv->display.crtc_compute_clock = |
13950 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
13951 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
13952 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
65b3d6a9 | 13953 | } else if (IS_CHERRYVIEW(dev_priv)) { |
89b667f8 | 13954 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
13955 | dev_priv->display.get_initial_plane_config = |
13956 | i9xx_get_initial_plane_config; | |
65b3d6a9 ACO |
13957 | dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; |
13958 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
13959 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
13960 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
13961 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
13962 | dev_priv->display.get_initial_plane_config = | |
13963 | i9xx_get_initial_plane_config; | |
13964 | dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; | |
89b667f8 JB |
13965 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
13966 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
19ec6693 ACO |
13967 | } else if (IS_G4X(dev_priv)) { |
13968 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
13969 | dev_priv->display.get_initial_plane_config = | |
13970 | i9xx_get_initial_plane_config; | |
13971 | dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; | |
13972 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
13973 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
70e8aa21 ACO |
13974 | } else if (IS_PINEVIEW(dev_priv)) { |
13975 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
13976 | dev_priv->display.get_initial_plane_config = | |
13977 | i9xx_get_initial_plane_config; | |
13978 | dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; | |
13979 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
13980 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 | 13981 | } else if (!IS_GEN2(dev_priv)) { |
0e8ffe1b | 13982 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
13983 | dev_priv->display.get_initial_plane_config = |
13984 | i9xx_get_initial_plane_config; | |
d6dfee7a | 13985 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
13986 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
13987 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 ACO |
13988 | } else { |
13989 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
13990 | dev_priv->display.get_initial_plane_config = | |
13991 | i9xx_get_initial_plane_config; | |
13992 | dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; | |
13993 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
13994 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 13995 | } |
e70236a8 | 13996 | |
88212941 | 13997 | if (IS_GEN5(dev_priv)) { |
3bb11b53 | 13998 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
88212941 | 13999 | } else if (IS_GEN6(dev_priv)) { |
3bb11b53 | 14000 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
88212941 | 14001 | } else if (IS_IVYBRIDGE(dev_priv)) { |
3bb11b53 SJ |
14002 | /* FIXME: detect B0+ stepping and use auto training */ |
14003 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
88212941 | 14004 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3bb11b53 | 14005 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
445e780b VS |
14006 | } |
14007 | ||
27082493 L |
14008 | if (dev_priv->info.gen >= 9) |
14009 | dev_priv->display.update_crtcs = skl_update_crtcs; | |
14010 | else | |
14011 | dev_priv->display.update_crtcs = intel_update_crtcs; | |
e70236a8 JB |
14012 | } |
14013 | ||
435793df KP |
14014 | /* |
14015 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
14016 | */ | |
14017 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
14018 | { | |
fac5e23e | 14019 | struct drm_i915_private *dev_priv = to_i915(dev); |
435793df | 14020 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
bc0daf48 | 14021 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
14022 | } |
14023 | ||
4dca20ef | 14024 | /* |
5a15ab5b CE |
14025 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
14026 | * brightness value | |
4dca20ef CE |
14027 | */ |
14028 | static void quirk_invert_brightness(struct drm_device *dev) | |
14029 | { | |
fac5e23e | 14030 | struct drm_i915_private *dev_priv = to_i915(dev); |
4dca20ef | 14031 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
bc0daf48 | 14032 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
14033 | } |
14034 | ||
9c72cc6f SD |
14035 | /* Some VBT's incorrectly indicate no backlight is present */ |
14036 | static void quirk_backlight_present(struct drm_device *dev) | |
14037 | { | |
fac5e23e | 14038 | struct drm_i915_private *dev_priv = to_i915(dev); |
9c72cc6f SD |
14039 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; |
14040 | DRM_INFO("applying backlight present quirk\n"); | |
14041 | } | |
14042 | ||
c99a259b MN |
14043 | /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms |
14044 | * which is 300 ms greater than eDP spec T12 min. | |
14045 | */ | |
14046 | static void quirk_increase_t12_delay(struct drm_device *dev) | |
14047 | { | |
14048 | struct drm_i915_private *dev_priv = to_i915(dev); | |
14049 | ||
14050 | dev_priv->quirks |= QUIRK_INCREASE_T12_DELAY; | |
14051 | DRM_INFO("Applying T12 delay quirk\n"); | |
14052 | } | |
14053 | ||
b690e96c JB |
14054 | struct intel_quirk { |
14055 | int device; | |
14056 | int subsystem_vendor; | |
14057 | int subsystem_device; | |
14058 | void (*hook)(struct drm_device *dev); | |
14059 | }; | |
14060 | ||
5f85f176 EE |
14061 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
14062 | struct intel_dmi_quirk { | |
14063 | void (*hook)(struct drm_device *dev); | |
14064 | const struct dmi_system_id (*dmi_id_list)[]; | |
14065 | }; | |
14066 | ||
14067 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
14068 | { | |
14069 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
14070 | return 1; | |
14071 | } | |
14072 | ||
14073 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
14074 | { | |
14075 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
14076 | { | |
14077 | .callback = intel_dmi_reverse_brightness, | |
14078 | .ident = "NCR Corporation", | |
14079 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
14080 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
14081 | }, | |
14082 | }, | |
14083 | { } /* terminating entry */ | |
14084 | }, | |
14085 | .hook = quirk_invert_brightness, | |
14086 | }, | |
14087 | }; | |
14088 | ||
c43b5634 | 14089 | static struct intel_quirk intel_quirks[] = { |
435793df KP |
14090 | /* Lenovo U160 cannot use SSC on LVDS */ |
14091 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
14092 | |
14093 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
14094 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 14095 | |
be505f64 AH |
14096 | /* Acer Aspire 5734Z must invert backlight brightness */ |
14097 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
14098 | ||
14099 | /* Acer/eMachines G725 */ | |
14100 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
14101 | ||
14102 | /* Acer/eMachines e725 */ | |
14103 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
14104 | ||
14105 | /* Acer/Packard Bell NCL20 */ | |
14106 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
14107 | ||
14108 | /* Acer Aspire 4736Z */ | |
14109 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
14110 | |
14111 | /* Acer Aspire 5336 */ | |
14112 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
14113 | |
14114 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
14115 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 14116 | |
dfb3d47b SD |
14117 | /* Acer C720 Chromebook (Core i3 4005U) */ |
14118 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
14119 | ||
b2a9601c | 14120 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
14121 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
14122 | ||
1b9448b0 JN |
14123 | /* Apple Macbook 4,1 */ |
14124 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
14125 | ||
d4967d8c SD |
14126 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
14127 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
14128 | |
14129 | /* HP Chromebook 14 (Celeron 2955U) */ | |
14130 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
14131 | |
14132 | /* Dell Chromebook 11 */ | |
14133 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
14134 | |
14135 | /* Dell Chromebook 11 (2015 version) */ | |
14136 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
c99a259b MN |
14137 | |
14138 | /* Toshiba Satellite P50-C-18C */ | |
14139 | { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay }, | |
b690e96c JB |
14140 | }; |
14141 | ||
14142 | static void intel_init_quirks(struct drm_device *dev) | |
14143 | { | |
14144 | struct pci_dev *d = dev->pdev; | |
14145 | int i; | |
14146 | ||
14147 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
14148 | struct intel_quirk *q = &intel_quirks[i]; | |
14149 | ||
14150 | if (d->device == q->device && | |
14151 | (d->subsystem_vendor == q->subsystem_vendor || | |
14152 | q->subsystem_vendor == PCI_ANY_ID) && | |
14153 | (d->subsystem_device == q->subsystem_device || | |
14154 | q->subsystem_device == PCI_ANY_ID)) | |
14155 | q->hook(dev); | |
14156 | } | |
5f85f176 EE |
14157 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
14158 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
14159 | intel_dmi_quirks[i].hook(dev); | |
14160 | } | |
b690e96c JB |
14161 | } |
14162 | ||
9cce37f4 | 14163 | /* Disable the VGA plane that we never use */ |
29b74b7f | 14164 | static void i915_disable_vga(struct drm_i915_private *dev_priv) |
9cce37f4 | 14165 | { |
52a05c30 | 14166 | struct pci_dev *pdev = dev_priv->drm.pdev; |
9cce37f4 | 14167 | u8 sr1; |
920a14b2 | 14168 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); |
9cce37f4 | 14169 | |
2b37c616 | 14170 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
52a05c30 | 14171 | vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 14172 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
14173 | sr1 = inb(VGA_SR_DATA); |
14174 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
52a05c30 | 14175 | vga_put(pdev, VGA_RSRC_LEGACY_IO); |
9cce37f4 JB |
14176 | udelay(300); |
14177 | ||
01f5a626 | 14178 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
14179 | POSTING_READ(vga_reg); |
14180 | } | |
14181 | ||
f817586c DV |
14182 | void intel_modeset_init_hw(struct drm_device *dev) |
14183 | { | |
fac5e23e | 14184 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a617b77 | 14185 | |
4c75b940 | 14186 | intel_update_cdclk(dev_priv); |
bb0f4aab | 14187 | dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw; |
1a617b77 | 14188 | |
46f16e63 | 14189 | intel_init_clock_gating(dev_priv); |
f817586c DV |
14190 | } |
14191 | ||
d93c0372 MR |
14192 | /* |
14193 | * Calculate what we think the watermarks should be for the state we've read | |
14194 | * out of the hardware and then immediately program those watermarks so that | |
14195 | * we ensure the hardware settings match our internal state. | |
14196 | * | |
14197 | * We can calculate what we think WM's should be by creating a duplicate of the | |
14198 | * current state (which was constructed during hardware readout) and running it | |
14199 | * through the atomic check code to calculate new watermark values in the | |
14200 | * state object. | |
14201 | */ | |
14202 | static void sanitize_watermarks(struct drm_device *dev) | |
14203 | { | |
14204 | struct drm_i915_private *dev_priv = to_i915(dev); | |
14205 | struct drm_atomic_state *state; | |
ccf010fb | 14206 | struct intel_atomic_state *intel_state; |
d93c0372 MR |
14207 | struct drm_crtc *crtc; |
14208 | struct drm_crtc_state *cstate; | |
14209 | struct drm_modeset_acquire_ctx ctx; | |
14210 | int ret; | |
14211 | int i; | |
14212 | ||
14213 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 14214 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
14215 | return; |
14216 | ||
14217 | /* | |
14218 | * We need to hold connection_mutex before calling duplicate_state so | |
14219 | * that the connector loop is protected. | |
14220 | */ | |
14221 | drm_modeset_acquire_init(&ctx, 0); | |
14222 | retry: | |
0cd1262d | 14223 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
14224 | if (ret == -EDEADLK) { |
14225 | drm_modeset_backoff(&ctx); | |
14226 | goto retry; | |
14227 | } else if (WARN_ON(ret)) { | |
0cd1262d | 14228 | goto fail; |
d93c0372 MR |
14229 | } |
14230 | ||
14231 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
14232 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 14233 | goto fail; |
d93c0372 | 14234 | |
ccf010fb ML |
14235 | intel_state = to_intel_atomic_state(state); |
14236 | ||
ed4a6a7c MR |
14237 | /* |
14238 | * Hardware readout is the only time we don't want to calculate | |
14239 | * intermediate watermarks (since we don't trust the current | |
14240 | * watermarks). | |
14241 | */ | |
602ae835 VS |
14242 | if (!HAS_GMCH_DISPLAY(dev_priv)) |
14243 | intel_state->skip_intermediate_wm = true; | |
ed4a6a7c | 14244 | |
d93c0372 MR |
14245 | ret = intel_atomic_check(dev, state); |
14246 | if (ret) { | |
14247 | /* | |
14248 | * If we fail here, it means that the hardware appears to be | |
14249 | * programmed in a way that shouldn't be possible, given our | |
14250 | * understanding of watermark requirements. This might mean a | |
14251 | * mistake in the hardware readout code or a mistake in the | |
14252 | * watermark calculations for a given platform. Raise a WARN | |
14253 | * so that this is noticeable. | |
14254 | * | |
14255 | * If this actually happens, we'll have to just leave the | |
14256 | * BIOS-programmed watermarks untouched and hope for the best. | |
14257 | */ | |
14258 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
b9a1b717 | 14259 | goto put_state; |
d93c0372 MR |
14260 | } |
14261 | ||
14262 | /* Write calculated watermark values back */ | |
aa5e9b47 | 14263 | for_each_new_crtc_in_state(state, crtc, cstate, i) { |
d93c0372 MR |
14264 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); |
14265 | ||
ed4a6a7c | 14266 | cs->wm.need_postvbl_update = true; |
ccf010fb | 14267 | dev_priv->display.optimize_watermarks(intel_state, cs); |
d93c0372 MR |
14268 | } |
14269 | ||
b9a1b717 | 14270 | put_state: |
0853695c | 14271 | drm_atomic_state_put(state); |
0cd1262d | 14272 | fail: |
d93c0372 MR |
14273 | drm_modeset_drop_locks(&ctx); |
14274 | drm_modeset_acquire_fini(&ctx); | |
14275 | } | |
14276 | ||
b079bd17 | 14277 | int intel_modeset_init(struct drm_device *dev) |
79e53945 | 14278 | { |
72e96d64 JL |
14279 | struct drm_i915_private *dev_priv = to_i915(dev); |
14280 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
8cc87b75 | 14281 | enum pipe pipe; |
46f297fb | 14282 | struct intel_crtc *crtc; |
79e53945 JB |
14283 | |
14284 | drm_mode_config_init(dev); | |
14285 | ||
14286 | dev->mode_config.min_width = 0; | |
14287 | dev->mode_config.min_height = 0; | |
14288 | ||
019d96cb DA |
14289 | dev->mode_config.preferred_depth = 24; |
14290 | dev->mode_config.prefer_shadow = 1; | |
14291 | ||
25bab385 TU |
14292 | dev->mode_config.allow_fb_modifiers = true; |
14293 | ||
e6ecefaa | 14294 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 14295 | |
400c19d9 | 14296 | init_llist_head(&dev_priv->atomic_helper.free_list); |
eb955eee | 14297 | INIT_WORK(&dev_priv->atomic_helper.free_work, |
ba318c61 | 14298 | intel_atomic_helper_free_state_worker); |
eb955eee | 14299 | |
b690e96c JB |
14300 | intel_init_quirks(dev); |
14301 | ||
62d75df7 | 14302 | intel_init_pm(dev_priv); |
1fa61106 | 14303 | |
b7f05d4a | 14304 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
b079bd17 | 14305 | return 0; |
e3c74757 | 14306 | |
69f92f67 LW |
14307 | /* |
14308 | * There may be no VBT; and if the BIOS enabled SSC we can | |
14309 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
14310 | * BIOS isn't using it, don't assume it will work even if the VBT | |
14311 | * indicates as much. | |
14312 | */ | |
6e266956 | 14313 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { |
69f92f67 LW |
14314 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & |
14315 | DREF_SSC1_ENABLE); | |
14316 | ||
14317 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
14318 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
14319 | bios_lvds_use_ssc ? "en" : "dis", | |
14320 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
14321 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
14322 | } | |
14323 | } | |
14324 | ||
5db94019 | 14325 | if (IS_GEN2(dev_priv)) { |
a6c45cf0 CW |
14326 | dev->mode_config.max_width = 2048; |
14327 | dev->mode_config.max_height = 2048; | |
5db94019 | 14328 | } else if (IS_GEN3(dev_priv)) { |
5e4d6fa7 KP |
14329 | dev->mode_config.max_width = 4096; |
14330 | dev->mode_config.max_height = 4096; | |
79e53945 | 14331 | } else { |
a6c45cf0 CW |
14332 | dev->mode_config.max_width = 8192; |
14333 | dev->mode_config.max_height = 8192; | |
79e53945 | 14334 | } |
068be561 | 14335 | |
2a307c2e JN |
14336 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { |
14337 | dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512; | |
dc41c154 | 14338 | dev->mode_config.cursor_height = 1023; |
5db94019 | 14339 | } else if (IS_GEN2(dev_priv)) { |
068be561 DL |
14340 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
14341 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
14342 | } else { | |
14343 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
14344 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
14345 | } | |
14346 | ||
72e96d64 | 14347 | dev->mode_config.fb_base = ggtt->mappable_base; |
79e53945 | 14348 | |
28c97730 | 14349 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
b7f05d4a TU |
14350 | INTEL_INFO(dev_priv)->num_pipes, |
14351 | INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 14352 | |
055e393f | 14353 | for_each_pipe(dev_priv, pipe) { |
b079bd17 VS |
14354 | int ret; |
14355 | ||
5ab0d85b | 14356 | ret = intel_crtc_init(dev_priv, pipe); |
b079bd17 VS |
14357 | if (ret) { |
14358 | drm_mode_config_cleanup(dev); | |
14359 | return ret; | |
14360 | } | |
79e53945 JB |
14361 | } |
14362 | ||
e72f9fbf | 14363 | intel_shared_dpll_init(dev); |
ee7b9f93 | 14364 | |
5be6e334 VS |
14365 | intel_update_czclk(dev_priv); |
14366 | intel_modeset_init_hw(dev); | |
14367 | ||
b2045352 | 14368 | if (dev_priv->max_cdclk_freq == 0) |
4c75b940 | 14369 | intel_update_max_cdclk(dev_priv); |
b2045352 | 14370 | |
9cce37f4 | 14371 | /* Just disable it once at startup */ |
29b74b7f | 14372 | i915_disable_vga(dev_priv); |
c39055b0 | 14373 | intel_setup_outputs(dev_priv); |
11be49eb | 14374 | |
6e9f798d | 14375 | drm_modeset_lock_all(dev); |
aecd36b8 | 14376 | intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx); |
6e9f798d | 14377 | drm_modeset_unlock_all(dev); |
46f297fb | 14378 | |
d3fcc808 | 14379 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
14380 | struct intel_initial_plane_config plane_config = {}; |
14381 | ||
46f297fb JB |
14382 | if (!crtc->active) |
14383 | continue; | |
14384 | ||
46f297fb | 14385 | /* |
46f297fb JB |
14386 | * Note that reserving the BIOS fb up front prevents us |
14387 | * from stuffing other stolen allocations like the ring | |
14388 | * on top. This prevents some ugliness at boot time, and | |
14389 | * can even allow for smooth boot transitions if the BIOS | |
14390 | * fb is large enough for the active pipe configuration. | |
14391 | */ | |
eeebeac5 ML |
14392 | dev_priv->display.get_initial_plane_config(crtc, |
14393 | &plane_config); | |
14394 | ||
14395 | /* | |
14396 | * If the fb is shared between multiple heads, we'll | |
14397 | * just get the first one. | |
14398 | */ | |
14399 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 14400 | } |
d93c0372 MR |
14401 | |
14402 | /* | |
14403 | * Make sure hardware watermarks really match the state we read out. | |
14404 | * Note that we need to do this after reconstructing the BIOS fb's | |
14405 | * since the watermark calculation done here will use pstate->fb. | |
14406 | */ | |
602ae835 VS |
14407 | if (!HAS_GMCH_DISPLAY(dev_priv)) |
14408 | sanitize_watermarks(dev); | |
b079bd17 VS |
14409 | |
14410 | return 0; | |
2c7111db CW |
14411 | } |
14412 | ||
2ee0da16 VS |
14413 | void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) |
14414 | { | |
14415 | /* 640x480@60Hz, ~25175 kHz */ | |
14416 | struct dpll clock = { | |
14417 | .m1 = 18, | |
14418 | .m2 = 7, | |
14419 | .p1 = 13, | |
14420 | .p2 = 4, | |
14421 | .n = 2, | |
14422 | }; | |
14423 | u32 dpll, fp; | |
14424 | int i; | |
14425 | ||
14426 | WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154); | |
14427 | ||
14428 | DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n", | |
14429 | pipe_name(pipe), clock.vco, clock.dot); | |
14430 | ||
14431 | fp = i9xx_dpll_compute_fp(&clock); | |
14432 | dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) | | |
14433 | DPLL_VGA_MODE_DIS | | |
14434 | ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | | |
14435 | PLL_P2_DIVIDE_BY_4 | | |
14436 | PLL_REF_INPUT_DREFCLK | | |
14437 | DPLL_VCO_ENABLE; | |
14438 | ||
14439 | I915_WRITE(FP0(pipe), fp); | |
14440 | I915_WRITE(FP1(pipe), fp); | |
14441 | ||
14442 | I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16)); | |
14443 | I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16)); | |
14444 | I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16)); | |
14445 | I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16)); | |
14446 | I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16)); | |
14447 | I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16)); | |
14448 | I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1)); | |
14449 | ||
14450 | /* | |
14451 | * Apparently we need to have VGA mode enabled prior to changing | |
14452 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
14453 | * dividers, even though the register value does change. | |
14454 | */ | |
14455 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); | |
14456 | I915_WRITE(DPLL(pipe), dpll); | |
14457 | ||
14458 | /* Wait for the clocks to stabilize. */ | |
14459 | POSTING_READ(DPLL(pipe)); | |
14460 | udelay(150); | |
14461 | ||
14462 | /* The pixel multiplier can only be updated once the | |
14463 | * DPLL is enabled and the clocks are stable. | |
14464 | * | |
14465 | * So write it again. | |
14466 | */ | |
14467 | I915_WRITE(DPLL(pipe), dpll); | |
14468 | ||
14469 | /* We do this three times for luck */ | |
14470 | for (i = 0; i < 3 ; i++) { | |
14471 | I915_WRITE(DPLL(pipe), dpll); | |
14472 | POSTING_READ(DPLL(pipe)); | |
14473 | udelay(150); /* wait for warmup */ | |
14474 | } | |
14475 | ||
14476 | I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE); | |
14477 | POSTING_READ(PIPECONF(pipe)); | |
14478 | } | |
14479 | ||
14480 | void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) | |
14481 | { | |
14482 | DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n", | |
14483 | pipe_name(pipe)); | |
14484 | ||
14485 | assert_plane_disabled(dev_priv, PLANE_A); | |
14486 | assert_plane_disabled(dev_priv, PLANE_B); | |
14487 | ||
14488 | I915_WRITE(PIPECONF(pipe), 0); | |
14489 | POSTING_READ(PIPECONF(pipe)); | |
14490 | ||
14491 | if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100)) | |
14492 | DRM_ERROR("pipe %c off wait timed out\n", pipe_name(pipe)); | |
14493 | ||
14494 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); | |
14495 | POSTING_READ(DPLL(pipe)); | |
14496 | } | |
14497 | ||
fa555837 DV |
14498 | static bool |
14499 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
14500 | { | |
b7f05d4a | 14501 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
649636ef | 14502 | u32 val; |
fa555837 | 14503 | |
b7f05d4a | 14504 | if (INTEL_INFO(dev_priv)->num_pipes == 1) |
fa555837 DV |
14505 | return true; |
14506 | ||
649636ef | 14507 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
14508 | |
14509 | if ((val & DISPLAY_PLANE_ENABLE) && | |
14510 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
14511 | return false; | |
14512 | ||
14513 | return true; | |
14514 | } | |
14515 | ||
02e93c35 VS |
14516 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
14517 | { | |
14518 | struct drm_device *dev = crtc->base.dev; | |
14519 | struct intel_encoder *encoder; | |
14520 | ||
14521 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
14522 | return true; | |
14523 | ||
14524 | return false; | |
14525 | } | |
14526 | ||
496b0fc3 ML |
14527 | static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) |
14528 | { | |
14529 | struct drm_device *dev = encoder->base.dev; | |
14530 | struct intel_connector *connector; | |
14531 | ||
14532 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
14533 | return connector; | |
14534 | ||
14535 | return NULL; | |
14536 | } | |
14537 | ||
a168f5b3 VS |
14538 | static bool has_pch_trancoder(struct drm_i915_private *dev_priv, |
14539 | enum transcoder pch_transcoder) | |
14540 | { | |
14541 | return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || | |
14542 | (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A); | |
14543 | } | |
14544 | ||
aecd36b8 VS |
14545 | static void intel_sanitize_crtc(struct intel_crtc *crtc, |
14546 | struct drm_modeset_acquire_ctx *ctx) | |
24929352 DV |
14547 | { |
14548 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 14549 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 | 14550 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
24929352 | 14551 | |
24929352 | 14552 | /* Clear any frame start delays used for debugging left by the BIOS */ |
4d1de975 JN |
14553 | if (!transcoder_is_dsi(cpu_transcoder)) { |
14554 | i915_reg_t reg = PIPECONF(cpu_transcoder); | |
14555 | ||
14556 | I915_WRITE(reg, | |
14557 | I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | |
14558 | } | |
24929352 | 14559 | |
d3eaf884 | 14560 | /* restore vblank interrupts to correct state */ |
9625604c | 14561 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 14562 | if (crtc->active) { |
f9cd7b88 VS |
14563 | struct intel_plane *plane; |
14564 | ||
9625604c | 14565 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
14566 | |
14567 | /* Disable everything but the primary plane */ | |
14568 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
14569 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
14570 | continue; | |
14571 | ||
72259536 | 14572 | trace_intel_disable_plane(&plane->base, crtc); |
282dbf9b | 14573 | plane->disable_plane(plane, crtc); |
f9cd7b88 | 14574 | } |
9625604c | 14575 | } |
d3eaf884 | 14576 | |
24929352 | 14577 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
14578 | * disable the crtc (and hence change the state) if it is wrong. Note |
14579 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
6315b5d3 | 14580 | if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) { |
24929352 DV |
14581 | bool plane; |
14582 | ||
78108b7c VS |
14583 | DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n", |
14584 | crtc->base.base.id, crtc->base.name); | |
24929352 DV |
14585 | |
14586 | /* Pipe has the wrong plane attached and the plane is active. | |
14587 | * Temporarily change the plane mapping and disable everything | |
14588 | * ... */ | |
14589 | plane = crtc->plane; | |
1d4258db | 14590 | crtc->base.primary->state->visible = true; |
24929352 | 14591 | crtc->plane = !plane; |
da1d0e26 | 14592 | intel_crtc_disable_noatomic(&crtc->base, ctx); |
24929352 | 14593 | crtc->plane = plane; |
24929352 | 14594 | } |
24929352 DV |
14595 | |
14596 | /* Adjust the state of the output pipe according to whether we | |
14597 | * have active connectors/encoders. */ | |
842e0307 | 14598 | if (crtc->active && !intel_crtc_has_encoders(crtc)) |
da1d0e26 | 14599 | intel_crtc_disable_noatomic(&crtc->base, ctx); |
24929352 | 14600 | |
49cff963 | 14601 | if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) { |
4cc31489 DV |
14602 | /* |
14603 | * We start out with underrun reporting disabled to avoid races. | |
14604 | * For correct bookkeeping mark this on active crtcs. | |
14605 | * | |
c5ab3bc0 DV |
14606 | * Also on gmch platforms we dont have any hardware bits to |
14607 | * disable the underrun reporting. Which means we need to start | |
14608 | * out with underrun reporting disabled also on inactive pipes, | |
14609 | * since otherwise we'll complain about the garbage we read when | |
14610 | * e.g. coming up after runtime pm. | |
14611 | * | |
4cc31489 DV |
14612 | * No protection against concurrent access is required - at |
14613 | * worst a fifo underrun happens which also sets this to false. | |
14614 | */ | |
14615 | crtc->cpu_fifo_underrun_disabled = true; | |
a168f5b3 VS |
14616 | /* |
14617 | * We track the PCH trancoder underrun reporting state | |
14618 | * within the crtc. With crtc for pipe A housing the underrun | |
14619 | * reporting state for PCH transcoder A, crtc for pipe B housing | |
14620 | * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, | |
14621 | * and marking underrun reporting as disabled for the non-existing | |
14622 | * PCH transcoders B and C would prevent enabling the south | |
14623 | * error interrupt (see cpt_can_enable_serr_int()). | |
14624 | */ | |
14625 | if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe)) | |
14626 | crtc->pch_fifo_underrun_disabled = true; | |
4cc31489 | 14627 | } |
24929352 DV |
14628 | } |
14629 | ||
14630 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
14631 | { | |
14632 | struct intel_connector *connector; | |
24929352 DV |
14633 | |
14634 | /* We need to check both for a crtc link (meaning that the | |
14635 | * encoder is active and trying to read from a pipe) and the | |
14636 | * pipe itself being active. */ | |
14637 | bool has_active_crtc = encoder->base.crtc && | |
14638 | to_intel_crtc(encoder->base.crtc)->active; | |
14639 | ||
496b0fc3 ML |
14640 | connector = intel_encoder_find_connector(encoder); |
14641 | if (connector && !has_active_crtc) { | |
24929352 DV |
14642 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
14643 | encoder->base.base.id, | |
8e329a03 | 14644 | encoder->base.name); |
24929352 DV |
14645 | |
14646 | /* Connector is active, but has no active pipe. This is | |
14647 | * fallout from our resume register restoring. Disable | |
14648 | * the encoder manually again. */ | |
14649 | if (encoder->base.crtc) { | |
fd6bbda9 ML |
14650 | struct drm_crtc_state *crtc_state = encoder->base.crtc->state; |
14651 | ||
24929352 DV |
14652 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", |
14653 | encoder->base.base.id, | |
8e329a03 | 14654 | encoder->base.name); |
fd6bbda9 | 14655 | encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); |
a62d1497 | 14656 | if (encoder->post_disable) |
fd6bbda9 | 14657 | encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); |
24929352 | 14658 | } |
7f1950fb | 14659 | encoder->base.crtc = NULL; |
24929352 DV |
14660 | |
14661 | /* Inconsistent output/port/pipe state happens presumably due to | |
14662 | * a bug in one of the get_hw_state functions. Or someplace else | |
14663 | * in our code, like the register restore mess on resume. Clamp | |
14664 | * things to off as a safer default. */ | |
fd6bbda9 ML |
14665 | |
14666 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
14667 | connector->base.encoder = NULL; | |
24929352 DV |
14668 | } |
14669 | /* Enabled encoders without active connectors will be fixed in | |
14670 | * the crtc fixup. */ | |
14671 | } | |
14672 | ||
29b74b7f | 14673 | void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv) |
0fde901f | 14674 | { |
920a14b2 | 14675 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); |
0fde901f | 14676 | |
04098753 ID |
14677 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
14678 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
29b74b7f | 14679 | i915_disable_vga(dev_priv); |
04098753 ID |
14680 | } |
14681 | } | |
14682 | ||
29b74b7f | 14683 | void i915_redisable_vga(struct drm_i915_private *dev_priv) |
04098753 | 14684 | { |
8dc8a27c PZ |
14685 | /* This function can be called both from intel_modeset_setup_hw_state or |
14686 | * at a very early point in our resume sequence, where the power well | |
14687 | * structures are not yet restored. Since this function is at a very | |
14688 | * paranoid "someone might have enabled VGA while we were not looking" | |
14689 | * level, just check if the power well is enabled instead of trying to | |
14690 | * follow the "don't touch the power well if we don't need it" policy | |
14691 | * the rest of the driver uses. */ | |
6392f847 | 14692 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
14693 | return; |
14694 | ||
29b74b7f | 14695 | i915_redisable_vga_power_on(dev_priv); |
6392f847 ID |
14696 | |
14697 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
0fde901f KM |
14698 | } |
14699 | ||
f9cd7b88 | 14700 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 14701 | { |
f9cd7b88 | 14702 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 14703 | |
f9cd7b88 | 14704 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
14705 | } |
14706 | ||
f9cd7b88 VS |
14707 | /* FIXME read out full plane state for all planes */ |
14708 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 14709 | { |
e9728bd8 VS |
14710 | struct intel_plane *primary = to_intel_plane(crtc->base.primary); |
14711 | bool visible; | |
d032ffa0 | 14712 | |
e9728bd8 | 14713 | visible = crtc->active && primary_get_hw_state(primary); |
b26d3ea3 | 14714 | |
e9728bd8 VS |
14715 | intel_set_plane_visible(to_intel_crtc_state(crtc->base.state), |
14716 | to_intel_plane_state(primary->base.state), | |
14717 | visible); | |
98ec7739 VS |
14718 | } |
14719 | ||
30e984df | 14720 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 | 14721 | { |
fac5e23e | 14722 | struct drm_i915_private *dev_priv = to_i915(dev); |
24929352 | 14723 | enum pipe pipe; |
24929352 DV |
14724 | struct intel_crtc *crtc; |
14725 | struct intel_encoder *encoder; | |
14726 | struct intel_connector *connector; | |
f9e905ca | 14727 | struct drm_connector_list_iter conn_iter; |
5358901f | 14728 | int i; |
24929352 | 14729 | |
565602d7 ML |
14730 | dev_priv->active_crtcs = 0; |
14731 | ||
d3fcc808 | 14732 | for_each_intel_crtc(dev, crtc) { |
a8cd6da0 VS |
14733 | struct intel_crtc_state *crtc_state = |
14734 | to_intel_crtc_state(crtc->base.state); | |
3b117c8f | 14735 | |
ec2dc6a0 | 14736 | __drm_atomic_helper_crtc_destroy_state(&crtc_state->base); |
565602d7 ML |
14737 | memset(crtc_state, 0, sizeof(*crtc_state)); |
14738 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 14739 | |
565602d7 ML |
14740 | crtc_state->base.active = crtc_state->base.enable = |
14741 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
14742 | ||
14743 | crtc->base.enabled = crtc_state->base.enable; | |
14744 | crtc->active = crtc_state->base.active; | |
14745 | ||
aca1ebf4 | 14746 | if (crtc_state->base.active) |
565602d7 ML |
14747 | dev_priv->active_crtcs |= 1 << crtc->pipe; |
14748 | ||
f9cd7b88 | 14749 | readout_plane_state(crtc); |
24929352 | 14750 | |
78108b7c VS |
14751 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n", |
14752 | crtc->base.base.id, crtc->base.name, | |
a8cd6da0 | 14753 | enableddisabled(crtc_state->base.active)); |
24929352 DV |
14754 | } |
14755 | ||
5358901f DV |
14756 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
14757 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
14758 | ||
2edd6443 | 14759 | pll->on = pll->funcs.get_hw_state(dev_priv, pll, |
2c42e535 ACO |
14760 | &pll->state.hw_state); |
14761 | pll->state.crtc_mask = 0; | |
d3fcc808 | 14762 | for_each_intel_crtc(dev, crtc) { |
a8cd6da0 VS |
14763 | struct intel_crtc_state *crtc_state = |
14764 | to_intel_crtc_state(crtc->base.state); | |
14765 | ||
14766 | if (crtc_state->base.active && | |
14767 | crtc_state->shared_dpll == pll) | |
2c42e535 | 14768 | pll->state.crtc_mask |= 1 << crtc->pipe; |
5358901f | 14769 | } |
2c42e535 | 14770 | pll->active_mask = pll->state.crtc_mask; |
5358901f | 14771 | |
1e6f2ddc | 14772 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
2c42e535 | 14773 | pll->name, pll->state.crtc_mask, pll->on); |
5358901f DV |
14774 | } |
14775 | ||
b2784e15 | 14776 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
14777 | pipe = 0; |
14778 | ||
14779 | if (encoder->get_hw_state(encoder, &pipe)) { | |
a8cd6da0 VS |
14780 | struct intel_crtc_state *crtc_state; |
14781 | ||
98187836 | 14782 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
a8cd6da0 | 14783 | crtc_state = to_intel_crtc_state(crtc->base.state); |
e2af48c6 | 14784 | |
045ac3b5 | 14785 | encoder->base.crtc = &crtc->base; |
a8cd6da0 VS |
14786 | crtc_state->output_types |= 1 << encoder->type; |
14787 | encoder->get_config(encoder, crtc_state); | |
24929352 DV |
14788 | } else { |
14789 | encoder->base.crtc = NULL; | |
14790 | } | |
14791 | ||
6f2bcceb | 14792 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
08c4d7fc TU |
14793 | encoder->base.base.id, encoder->base.name, |
14794 | enableddisabled(encoder->base.crtc), | |
6f2bcceb | 14795 | pipe_name(pipe)); |
24929352 DV |
14796 | } |
14797 | ||
f9e905ca DV |
14798 | drm_connector_list_iter_begin(dev, &conn_iter); |
14799 | for_each_intel_connector_iter(connector, &conn_iter) { | |
24929352 DV |
14800 | if (connector->get_hw_state(connector)) { |
14801 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
14802 | |
14803 | encoder = connector->encoder; | |
14804 | connector->base.encoder = &encoder->base; | |
14805 | ||
14806 | if (encoder->base.crtc && | |
14807 | encoder->base.crtc->state->active) { | |
14808 | /* | |
14809 | * This has to be done during hardware readout | |
14810 | * because anything calling .crtc_disable may | |
14811 | * rely on the connector_mask being accurate. | |
14812 | */ | |
14813 | encoder->base.crtc->state->connector_mask |= | |
14814 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
14815 | encoder->base.crtc->state->encoder_mask |= |
14816 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
14817 | } |
14818 | ||
24929352 DV |
14819 | } else { |
14820 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
14821 | connector->base.encoder = NULL; | |
14822 | } | |
14823 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
08c4d7fc TU |
14824 | connector->base.base.id, connector->base.name, |
14825 | enableddisabled(connector->base.encoder)); | |
24929352 | 14826 | } |
f9e905ca | 14827 | drm_connector_list_iter_end(&conn_iter); |
7f4c6284 VS |
14828 | |
14829 | for_each_intel_crtc(dev, crtc) { | |
a8cd6da0 VS |
14830 | struct intel_crtc_state *crtc_state = |
14831 | to_intel_crtc_state(crtc->base.state); | |
aca1ebf4 VS |
14832 | int pixclk = 0; |
14833 | ||
7f4c6284 | 14834 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); |
a8cd6da0 VS |
14835 | if (crtc_state->base.active) { |
14836 | intel_mode_from_pipe_config(&crtc->base.mode, crtc_state); | |
14837 | intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state); | |
7f4c6284 VS |
14838 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); |
14839 | ||
14840 | /* | |
14841 | * The initial mode needs to be set in order to keep | |
14842 | * the atomic core happy. It wants a valid mode if the | |
14843 | * crtc's enabled, so we do the above call. | |
14844 | * | |
7800fb69 DV |
14845 | * But we don't set all the derived state fully, hence |
14846 | * set a flag to indicate that a full recalculation is | |
14847 | * needed on the next commit. | |
7f4c6284 | 14848 | */ |
a8cd6da0 | 14849 | crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED; |
9eca6832 | 14850 | |
a7d1b3f4 VS |
14851 | intel_crtc_compute_pixel_rate(crtc_state); |
14852 | ||
14853 | if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) || | |
14854 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
14855 | pixclk = crtc_state->pixel_rate; | |
aca1ebf4 VS |
14856 | else |
14857 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
14858 | ||
14859 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
a8cd6da0 | 14860 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
aca1ebf4 VS |
14861 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); |
14862 | ||
5caa0fea DV |
14863 | drm_calc_timestamping_constants(&crtc->base, |
14864 | &crtc_state->base.adjusted_mode); | |
9eca6832 | 14865 | update_scanline_offset(crtc); |
7f4c6284 | 14866 | } |
e3b247da | 14867 | |
aca1ebf4 VS |
14868 | dev_priv->min_pixclk[crtc->pipe] = pixclk; |
14869 | ||
a8cd6da0 | 14870 | intel_pipe_config_sanity_check(dev_priv, crtc_state); |
7f4c6284 | 14871 | } |
30e984df DV |
14872 | } |
14873 | ||
62b69566 ACO |
14874 | static void |
14875 | get_encoder_power_domains(struct drm_i915_private *dev_priv) | |
14876 | { | |
14877 | struct intel_encoder *encoder; | |
14878 | ||
14879 | for_each_intel_encoder(&dev_priv->drm, encoder) { | |
14880 | u64 get_domains; | |
14881 | enum intel_display_power_domain domain; | |
14882 | ||
14883 | if (!encoder->get_power_domains) | |
14884 | continue; | |
14885 | ||
14886 | get_domains = encoder->get_power_domains(encoder); | |
14887 | for_each_power_domain(domain, get_domains) | |
14888 | intel_display_power_get(dev_priv, domain); | |
14889 | } | |
14890 | } | |
14891 | ||
043e9bda ML |
14892 | /* Scan out the current hw modeset state, |
14893 | * and sanitizes it to the current state | |
14894 | */ | |
14895 | static void | |
aecd36b8 VS |
14896 | intel_modeset_setup_hw_state(struct drm_device *dev, |
14897 | struct drm_modeset_acquire_ctx *ctx) | |
30e984df | 14898 | { |
fac5e23e | 14899 | struct drm_i915_private *dev_priv = to_i915(dev); |
30e984df | 14900 | enum pipe pipe; |
30e984df DV |
14901 | struct intel_crtc *crtc; |
14902 | struct intel_encoder *encoder; | |
35c95375 | 14903 | int i; |
30e984df DV |
14904 | |
14905 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
14906 | |
14907 | /* HW state is read out, now we need to sanitize this mess. */ | |
62b69566 ACO |
14908 | get_encoder_power_domains(dev_priv); |
14909 | ||
b2784e15 | 14910 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
14911 | intel_sanitize_encoder(encoder); |
14912 | } | |
14913 | ||
055e393f | 14914 | for_each_pipe(dev_priv, pipe) { |
98187836 | 14915 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
e2af48c6 | 14916 | |
aecd36b8 | 14917 | intel_sanitize_crtc(crtc, ctx); |
6e3c9717 ACO |
14918 | intel_dump_pipe_config(crtc, crtc->config, |
14919 | "[setup_hw_state]"); | |
24929352 | 14920 | } |
9a935856 | 14921 | |
d29b2f9d ACO |
14922 | intel_modeset_update_connector_atomic_state(dev); |
14923 | ||
35c95375 DV |
14924 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
14925 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
14926 | ||
2dd66ebd | 14927 | if (!pll->on || pll->active_mask) |
35c95375 DV |
14928 | continue; |
14929 | ||
14930 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
14931 | ||
2edd6443 | 14932 | pll->funcs.disable(dev_priv, pll); |
35c95375 DV |
14933 | pll->on = false; |
14934 | } | |
14935 | ||
04548cba VS |
14936 | if (IS_G4X(dev_priv)) { |
14937 | g4x_wm_get_hw_state(dev); | |
14938 | g4x_wm_sanitize(dev_priv); | |
14939 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
6eb1a681 | 14940 | vlv_wm_get_hw_state(dev); |
602ae835 VS |
14941 | vlv_wm_sanitize(dev_priv); |
14942 | } else if (IS_GEN9(dev_priv)) { | |
3078999f | 14943 | skl_wm_get_hw_state(dev); |
602ae835 | 14944 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
243e6a44 | 14945 | ilk_wm_get_hw_state(dev); |
602ae835 | 14946 | } |
292b990e ML |
14947 | |
14948 | for_each_intel_crtc(dev, crtc) { | |
d8fc70b7 | 14949 | u64 put_domains; |
292b990e | 14950 | |
74bff5f9 | 14951 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
292b990e ML |
14952 | if (WARN_ON(put_domains)) |
14953 | modeset_put_power_domains(dev_priv, put_domains); | |
14954 | } | |
14955 | intel_display_set_init_power(dev_priv, false); | |
010cf73d | 14956 | |
8d8c386c ID |
14957 | intel_power_domains_verify_state(dev_priv); |
14958 | ||
010cf73d | 14959 | intel_fbc_init_pipe_state(dev_priv); |
043e9bda | 14960 | } |
7d0bc1ea | 14961 | |
043e9bda ML |
14962 | void intel_display_resume(struct drm_device *dev) |
14963 | { | |
e2c8b870 ML |
14964 | struct drm_i915_private *dev_priv = to_i915(dev); |
14965 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
14966 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 14967 | int ret; |
f30da187 | 14968 | |
e2c8b870 | 14969 | dev_priv->modeset_restore_state = NULL; |
73974893 ML |
14970 | if (state) |
14971 | state->acquire_ctx = &ctx; | |
043e9bda | 14972 | |
e2c8b870 | 14973 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 14974 | |
73974893 ML |
14975 | while (1) { |
14976 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
14977 | if (ret != -EDEADLK) | |
14978 | break; | |
043e9bda | 14979 | |
e2c8b870 | 14980 | drm_modeset_backoff(&ctx); |
e2c8b870 | 14981 | } |
043e9bda | 14982 | |
73974893 | 14983 | if (!ret) |
581e49fe | 14984 | ret = __intel_display_resume(dev, state, &ctx); |
73974893 | 14985 | |
e2c8b870 ML |
14986 | drm_modeset_drop_locks(&ctx); |
14987 | drm_modeset_acquire_fini(&ctx); | |
043e9bda | 14988 | |
0853695c | 14989 | if (ret) |
e2c8b870 | 14990 | DRM_ERROR("Restoring old state failed with %i\n", ret); |
3c5e37f1 CW |
14991 | if (state) |
14992 | drm_atomic_state_put(state); | |
2c7111db CW |
14993 | } |
14994 | ||
14995 | void intel_modeset_gem_init(struct drm_device *dev) | |
14996 | { | |
dc97997a | 14997 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 14998 | |
dc97997a | 14999 | intel_init_gt_powersave(dev_priv); |
ae48434c | 15000 | |
1ee8da6d | 15001 | intel_setup_overlay(dev_priv); |
1ebaa0b9 CW |
15002 | } |
15003 | ||
15004 | int intel_connector_register(struct drm_connector *connector) | |
15005 | { | |
15006 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
15007 | int ret; | |
15008 | ||
15009 | ret = intel_backlight_device_register(intel_connector); | |
15010 | if (ret) | |
15011 | goto err; | |
15012 | ||
15013 | return 0; | |
0962c3c9 | 15014 | |
1ebaa0b9 CW |
15015 | err: |
15016 | return ret; | |
79e53945 JB |
15017 | } |
15018 | ||
c191eca1 | 15019 | void intel_connector_unregister(struct drm_connector *connector) |
4932e2c3 | 15020 | { |
e63d87c0 | 15021 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4932e2c3 | 15022 | |
e63d87c0 | 15023 | intel_backlight_device_unregister(intel_connector); |
4932e2c3 | 15024 | intel_panel_destroy_backlight(connector); |
4932e2c3 ID |
15025 | } |
15026 | ||
79e53945 JB |
15027 | void intel_modeset_cleanup(struct drm_device *dev) |
15028 | { | |
fac5e23e | 15029 | struct drm_i915_private *dev_priv = to_i915(dev); |
652c393a | 15030 | |
eb955eee CW |
15031 | flush_work(&dev_priv->atomic_helper.free_work); |
15032 | WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list)); | |
15033 | ||
dc97997a | 15034 | intel_disable_gt_powersave(dev_priv); |
2eb5252e | 15035 | |
fd0c0642 DV |
15036 | /* |
15037 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 15038 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
15039 | * experience fancy races otherwise. |
15040 | */ | |
2aeb7d3a | 15041 | intel_irq_uninstall(dev_priv); |
eb21b92b | 15042 | |
fd0c0642 DV |
15043 | /* |
15044 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
15045 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
15046 | */ | |
f87ea761 | 15047 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 15048 | |
4f256d82 DV |
15049 | /* poll work can call into fbdev, hence clean that up afterwards */ |
15050 | intel_fbdev_fini(dev_priv); | |
15051 | ||
723bfd70 JB |
15052 | intel_unregister_dsm_handler(); |
15053 | ||
c937ab3e | 15054 | intel_fbc_global_disable(dev_priv); |
69341a5e | 15055 | |
1630fe75 CW |
15056 | /* flush any delayed tasks or pending work */ |
15057 | flush_scheduled_work(); | |
15058 | ||
79e53945 | 15059 | drm_mode_config_cleanup(dev); |
4d7bb011 | 15060 | |
1ee8da6d | 15061 | intel_cleanup_overlay(dev_priv); |
ae48434c | 15062 | |
dc97997a | 15063 | intel_cleanup_gt_powersave(dev_priv); |
f5949141 | 15064 | |
40196446 | 15065 | intel_teardown_gmbus(dev_priv); |
79e53945 JB |
15066 | } |
15067 | ||
df0e9248 CW |
15068 | void intel_connector_attach_encoder(struct intel_connector *connector, |
15069 | struct intel_encoder *encoder) | |
15070 | { | |
15071 | connector->encoder = encoder; | |
15072 | drm_mode_connector_attach_encoder(&connector->base, | |
15073 | &encoder->base); | |
79e53945 | 15074 | } |
28d52043 DA |
15075 | |
15076 | /* | |
15077 | * set vga decode state - true == enable VGA decode | |
15078 | */ | |
6315b5d3 | 15079 | int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state) |
28d52043 | 15080 | { |
6315b5d3 | 15081 | unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
15082 | u16 gmch_ctrl; |
15083 | ||
75fa041d CW |
15084 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
15085 | DRM_ERROR("failed to read control word\n"); | |
15086 | return -EIO; | |
15087 | } | |
15088 | ||
c0cc8a55 CW |
15089 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
15090 | return 0; | |
15091 | ||
28d52043 DA |
15092 | if (state) |
15093 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
15094 | else | |
15095 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
15096 | |
15097 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
15098 | DRM_ERROR("failed to write control word\n"); | |
15099 | return -EIO; | |
15100 | } | |
15101 | ||
28d52043 DA |
15102 | return 0; |
15103 | } | |
c4a1d9e4 | 15104 | |
98a2f411 CW |
15105 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
15106 | ||
c4a1d9e4 | 15107 | struct intel_display_error_state { |
ff57f1b0 PZ |
15108 | |
15109 | u32 power_well_driver; | |
15110 | ||
63b66e5b CW |
15111 | int num_transcoders; |
15112 | ||
c4a1d9e4 CW |
15113 | struct intel_cursor_error_state { |
15114 | u32 control; | |
15115 | u32 position; | |
15116 | u32 base; | |
15117 | u32 size; | |
52331309 | 15118 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15119 | |
15120 | struct intel_pipe_error_state { | |
ddf9c536 | 15121 | bool power_domain_on; |
c4a1d9e4 | 15122 | u32 source; |
f301b1e1 | 15123 | u32 stat; |
52331309 | 15124 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15125 | |
15126 | struct intel_plane_error_state { | |
15127 | u32 control; | |
15128 | u32 stride; | |
15129 | u32 size; | |
15130 | u32 pos; | |
15131 | u32 addr; | |
15132 | u32 surface; | |
15133 | u32 tile_offset; | |
52331309 | 15134 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
15135 | |
15136 | struct intel_transcoder_error_state { | |
ddf9c536 | 15137 | bool power_domain_on; |
63b66e5b CW |
15138 | enum transcoder cpu_transcoder; |
15139 | ||
15140 | u32 conf; | |
15141 | ||
15142 | u32 htotal; | |
15143 | u32 hblank; | |
15144 | u32 hsync; | |
15145 | u32 vtotal; | |
15146 | u32 vblank; | |
15147 | u32 vsync; | |
15148 | } transcoder[4]; | |
c4a1d9e4 CW |
15149 | }; |
15150 | ||
15151 | struct intel_display_error_state * | |
c033666a | 15152 | intel_display_capture_error_state(struct drm_i915_private *dev_priv) |
c4a1d9e4 | 15153 | { |
c4a1d9e4 | 15154 | struct intel_display_error_state *error; |
63b66e5b CW |
15155 | int transcoders[] = { |
15156 | TRANSCODER_A, | |
15157 | TRANSCODER_B, | |
15158 | TRANSCODER_C, | |
15159 | TRANSCODER_EDP, | |
15160 | }; | |
c4a1d9e4 CW |
15161 | int i; |
15162 | ||
c033666a | 15163 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
63b66e5b CW |
15164 | return NULL; |
15165 | ||
9d1cb914 | 15166 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
15167 | if (error == NULL) |
15168 | return NULL; | |
15169 | ||
c033666a | 15170 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ff57f1b0 PZ |
15171 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
15172 | ||
055e393f | 15173 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 15174 | error->pipe[i].power_domain_on = |
f458ebbc DV |
15175 | __intel_display_power_is_enabled(dev_priv, |
15176 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 15177 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
15178 | continue; |
15179 | ||
5efb3e28 VS |
15180 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
15181 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
15182 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
15183 | |
15184 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
15185 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
c033666a | 15186 | if (INTEL_GEN(dev_priv) <= 3) { |
51889b35 | 15187 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
15188 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
15189 | } | |
c033666a | 15190 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
ca291363 | 15191 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
c033666a | 15192 | if (INTEL_GEN(dev_priv) >= 4) { |
c4a1d9e4 CW |
15193 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
15194 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
15195 | } | |
15196 | ||
c4a1d9e4 | 15197 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 15198 | |
c033666a | 15199 | if (HAS_GMCH_DISPLAY(dev_priv)) |
f301b1e1 | 15200 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
15201 | } |
15202 | ||
4d1de975 | 15203 | /* Note: this does not include DSI transcoders. */ |
c033666a | 15204 | error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes; |
2d1fe073 | 15205 | if (HAS_DDI(dev_priv)) |
63b66e5b CW |
15206 | error->num_transcoders++; /* Account for eDP. */ |
15207 | ||
15208 | for (i = 0; i < error->num_transcoders; i++) { | |
15209 | enum transcoder cpu_transcoder = transcoders[i]; | |
15210 | ||
ddf9c536 | 15211 | error->transcoder[i].power_domain_on = |
f458ebbc | 15212 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 15213 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 15214 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
15215 | continue; |
15216 | ||
63b66e5b CW |
15217 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
15218 | ||
15219 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
15220 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
15221 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
15222 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
15223 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
15224 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
15225 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
15226 | } |
15227 | ||
15228 | return error; | |
15229 | } | |
15230 | ||
edc3d884 MK |
15231 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
15232 | ||
c4a1d9e4 | 15233 | void |
edc3d884 | 15234 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
15235 | struct intel_display_error_state *error) |
15236 | { | |
5a4c6f1b | 15237 | struct drm_i915_private *dev_priv = m->i915; |
c4a1d9e4 CW |
15238 | int i; |
15239 | ||
63b66e5b CW |
15240 | if (!error) |
15241 | return; | |
15242 | ||
b7f05d4a | 15243 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes); |
8652744b | 15244 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
edc3d884 | 15245 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 15246 | error->power_well_driver); |
055e393f | 15247 | for_each_pipe(dev_priv, i) { |
edc3d884 | 15248 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 15249 | err_printf(m, " Power: %s\n", |
87ad3212 | 15250 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 15251 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 15252 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
15253 | |
15254 | err_printf(m, "Plane [%d]:\n", i); | |
15255 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
15256 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
5f56d5f9 | 15257 | if (INTEL_GEN(dev_priv) <= 3) { |
edc3d884 MK |
15258 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
15259 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 15260 | } |
772c2a51 | 15261 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
edc3d884 | 15262 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
5f56d5f9 | 15263 | if (INTEL_GEN(dev_priv) >= 4) { |
edc3d884 MK |
15264 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
15265 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
15266 | } |
15267 | ||
edc3d884 MK |
15268 | err_printf(m, "Cursor [%d]:\n", i); |
15269 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
15270 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
15271 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 15272 | } |
63b66e5b CW |
15273 | |
15274 | for (i = 0; i < error->num_transcoders; i++) { | |
da205630 | 15275 | err_printf(m, "CPU transcoder: %s\n", |
63b66e5b | 15276 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 15277 | err_printf(m, " Power: %s\n", |
87ad3212 | 15278 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
15279 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
15280 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
15281 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
15282 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
15283 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
15284 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
15285 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
15286 | } | |
c4a1d9e4 | 15287 | } |
98a2f411 CW |
15288 | |
15289 | #endif |