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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
5d723d7a | 37 | #include "intel_frontbuffer.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
79e53945 | 39 | #include "i915_drv.h" |
57822dc6 | 40 | #include "i915_gem_clflush.h" |
db18b6a6 | 41 | #include "intel_dsi.h" |
e5510fac | 42 | #include "i915_trace.h" |
319c1d42 | 43 | #include <drm/drm_atomic.h> |
c196e1d6 | 44 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
45 | #include <drm/drm_dp_helper.h> |
46 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
47 | #include <drm/drm_plane_helper.h> |
48 | #include <drm/drm_rect.h> | |
c0f372b3 | 49 | #include <linux/dma_remapping.h> |
fd8e058a | 50 | #include <linux/reservation.h> |
79e53945 | 51 | |
465c120c | 52 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 53 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
54 | DRM_FORMAT_C8, |
55 | DRM_FORMAT_RGB565, | |
465c120c | 56 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 57 | DRM_FORMAT_XRGB8888, |
465c120c MR |
58 | }; |
59 | ||
60 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 61 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
62 | DRM_FORMAT_C8, |
63 | DRM_FORMAT_RGB565, | |
64 | DRM_FORMAT_XRGB8888, | |
65 | DRM_FORMAT_XBGR8888, | |
66 | DRM_FORMAT_XRGB2101010, | |
67 | DRM_FORMAT_XBGR2101010, | |
68 | }; | |
69 | ||
714244e2 BW |
70 | static const uint64_t i9xx_format_modifiers[] = { |
71 | I915_FORMAT_MOD_X_TILED, | |
72 | DRM_FORMAT_MOD_LINEAR, | |
73 | DRM_FORMAT_MOD_INVALID | |
74 | }; | |
75 | ||
6c0fd451 | 76 | static const uint32_t skl_primary_formats[] = { |
67fe7dc5 DL |
77 | DRM_FORMAT_C8, |
78 | DRM_FORMAT_RGB565, | |
79 | DRM_FORMAT_XRGB8888, | |
465c120c | 80 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 81 | DRM_FORMAT_ARGB8888, |
465c120c MR |
82 | DRM_FORMAT_ABGR8888, |
83 | DRM_FORMAT_XRGB2101010, | |
465c120c | 84 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
85 | DRM_FORMAT_YUYV, |
86 | DRM_FORMAT_YVYU, | |
87 | DRM_FORMAT_UYVY, | |
88 | DRM_FORMAT_VYUY, | |
465c120c MR |
89 | }; |
90 | ||
714244e2 BW |
91 | static const uint64_t skl_format_modifiers_noccs[] = { |
92 | I915_FORMAT_MOD_Yf_TILED, | |
93 | I915_FORMAT_MOD_Y_TILED, | |
94 | I915_FORMAT_MOD_X_TILED, | |
95 | DRM_FORMAT_MOD_LINEAR, | |
96 | DRM_FORMAT_MOD_INVALID | |
97 | }; | |
98 | ||
99 | static const uint64_t skl_format_modifiers_ccs[] = { | |
100 | I915_FORMAT_MOD_Yf_TILED_CCS, | |
101 | I915_FORMAT_MOD_Y_TILED_CCS, | |
102 | I915_FORMAT_MOD_Yf_TILED, | |
103 | I915_FORMAT_MOD_Y_TILED, | |
104 | I915_FORMAT_MOD_X_TILED, | |
105 | DRM_FORMAT_MOD_LINEAR, | |
106 | DRM_FORMAT_MOD_INVALID | |
107 | }; | |
108 | ||
3d7d6510 MR |
109 | /* Cursor formats */ |
110 | static const uint32_t intel_cursor_formats[] = { | |
111 | DRM_FORMAT_ARGB8888, | |
112 | }; | |
113 | ||
714244e2 BW |
114 | static const uint64_t cursor_format_modifiers[] = { |
115 | DRM_FORMAT_MOD_LINEAR, | |
116 | DRM_FORMAT_MOD_INVALID | |
117 | }; | |
118 | ||
f1f644dc | 119 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 120 | struct intel_crtc_state *pipe_config); |
18442d08 | 121 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 122 | struct intel_crtc_state *pipe_config); |
f1f644dc | 123 | |
24dbf51a CW |
124 | static int intel_framebuffer_init(struct intel_framebuffer *ifb, |
125 | struct drm_i915_gem_object *obj, | |
126 | struct drm_mode_fb_cmd2 *mode_cmd); | |
5b18e57c DV |
127 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
128 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
bc58be60 | 129 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc); |
29407aab | 130 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
131 | struct intel_link_m_n *m_n, |
132 | struct intel_link_m_n *m2_n2); | |
29407aab | 133 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 | 134 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
391bf048 | 135 | static void haswell_set_pipemisc(struct drm_crtc *crtc); |
d288f65f | 136 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 137 | const struct intel_crtc_state *pipe_config); |
d288f65f | 138 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 139 | const struct intel_crtc_state *pipe_config); |
5a21b665 DV |
140 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
141 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
1c74eeaf NM |
142 | static void intel_crtc_init_scalers(struct intel_crtc *crtc, |
143 | struct intel_crtc_state *crtc_state); | |
bfd16b2a ML |
144 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
145 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
146 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
aecd36b8 VS |
147 | static void intel_modeset_setup_hw_state(struct drm_device *dev, |
148 | struct drm_modeset_acquire_ctx *ctx); | |
2622a081 | 149 | static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); |
e7457a9a | 150 | |
d4906093 | 151 | struct intel_limit { |
4c5def93 ACO |
152 | struct { |
153 | int min, max; | |
154 | } dot, vco, n, m, m1, m2, p, p1; | |
155 | ||
156 | struct { | |
157 | int dot_limit; | |
158 | int p2_slow, p2_fast; | |
159 | } p2; | |
d4906093 | 160 | }; |
79e53945 | 161 | |
bfa7df01 | 162 | /* returns HPLL frequency in kHz */ |
49cd97a3 | 163 | int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) |
bfa7df01 VS |
164 | { |
165 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
166 | ||
167 | /* Obtain SKU information */ | |
168 | mutex_lock(&dev_priv->sb_lock); | |
169 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
170 | CCK_FUSE_HPLL_FREQ_MASK; | |
171 | mutex_unlock(&dev_priv->sb_lock); | |
172 | ||
173 | return vco_freq[hpll_freq] * 1000; | |
174 | } | |
175 | ||
c30fec65 VS |
176 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
177 | const char *name, u32 reg, int ref_freq) | |
bfa7df01 VS |
178 | { |
179 | u32 val; | |
180 | int divider; | |
181 | ||
bfa7df01 VS |
182 | mutex_lock(&dev_priv->sb_lock); |
183 | val = vlv_cck_read(dev_priv, reg); | |
184 | mutex_unlock(&dev_priv->sb_lock); | |
185 | ||
186 | divider = val & CCK_FREQUENCY_VALUES; | |
187 | ||
188 | WARN((val & CCK_FREQUENCY_STATUS) != | |
189 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
190 | "%s change in progress\n", name); | |
191 | ||
c30fec65 VS |
192 | return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); |
193 | } | |
194 | ||
7ff89ca2 VS |
195 | int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, |
196 | const char *name, u32 reg) | |
c30fec65 VS |
197 | { |
198 | if (dev_priv->hpll_freq == 0) | |
49cd97a3 | 199 | dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); |
c30fec65 VS |
200 | |
201 | return vlv_get_cck_clock(dev_priv, name, reg, | |
202 | dev_priv->hpll_freq); | |
bfa7df01 VS |
203 | } |
204 | ||
bfa7df01 VS |
205 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
206 | { | |
666a4537 | 207 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
208 | return; |
209 | ||
210 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
211 | CCK_CZ_CLOCK_CONTROL); | |
212 | ||
213 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
214 | } | |
215 | ||
021357ac | 216 | static inline u32 /* units of 100MHz */ |
21a727b3 VS |
217 | intel_fdi_link_freq(struct drm_i915_private *dev_priv, |
218 | const struct intel_crtc_state *pipe_config) | |
021357ac | 219 | { |
21a727b3 VS |
220 | if (HAS_DDI(dev_priv)) |
221 | return pipe_config->port_clock; /* SPLL */ | |
222 | else if (IS_GEN5(dev_priv)) | |
223 | return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; | |
e3b247da | 224 | else |
21a727b3 | 225 | return 270000; |
021357ac CW |
226 | } |
227 | ||
1b6f4958 | 228 | static const struct intel_limit intel_limits_i8xx_dac = { |
0206e353 | 229 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 230 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 231 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
232 | .m = { .min = 96, .max = 140 }, |
233 | .m1 = { .min = 18, .max = 26 }, | |
234 | .m2 = { .min = 6, .max = 16 }, | |
235 | .p = { .min = 4, .max = 128 }, | |
236 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
237 | .p2 = { .dot_limit = 165000, |
238 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
239 | }; |
240 | ||
1b6f4958 | 241 | static const struct intel_limit intel_limits_i8xx_dvo = { |
5d536e28 | 242 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 243 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 244 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
245 | .m = { .min = 96, .max = 140 }, |
246 | .m1 = { .min = 18, .max = 26 }, | |
247 | .m2 = { .min = 6, .max = 16 }, | |
248 | .p = { .min = 4, .max = 128 }, | |
249 | .p1 = { .min = 2, .max = 33 }, | |
250 | .p2 = { .dot_limit = 165000, | |
251 | .p2_slow = 4, .p2_fast = 4 }, | |
252 | }; | |
253 | ||
1b6f4958 | 254 | static const struct intel_limit intel_limits_i8xx_lvds = { |
0206e353 | 255 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 256 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 257 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
258 | .m = { .min = 96, .max = 140 }, |
259 | .m1 = { .min = 18, .max = 26 }, | |
260 | .m2 = { .min = 6, .max = 16 }, | |
261 | .p = { .min = 4, .max = 128 }, | |
262 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
263 | .p2 = { .dot_limit = 165000, |
264 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 265 | }; |
273e27ca | 266 | |
1b6f4958 | 267 | static const struct intel_limit intel_limits_i9xx_sdvo = { |
0206e353 AJ |
268 | .dot = { .min = 20000, .max = 400000 }, |
269 | .vco = { .min = 1400000, .max = 2800000 }, | |
270 | .n = { .min = 1, .max = 6 }, | |
271 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
272 | .m1 = { .min = 8, .max = 18 }, |
273 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
274 | .p = { .min = 5, .max = 80 }, |
275 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
276 | .p2 = { .dot_limit = 200000, |
277 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
278 | }; |
279 | ||
1b6f4958 | 280 | static const struct intel_limit intel_limits_i9xx_lvds = { |
0206e353 AJ |
281 | .dot = { .min = 20000, .max = 400000 }, |
282 | .vco = { .min = 1400000, .max = 2800000 }, | |
283 | .n = { .min = 1, .max = 6 }, | |
284 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
285 | .m1 = { .min = 8, .max = 18 }, |
286 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
287 | .p = { .min = 7, .max = 98 }, |
288 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
289 | .p2 = { .dot_limit = 112000, |
290 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
291 | }; |
292 | ||
273e27ca | 293 | |
1b6f4958 | 294 | static const struct intel_limit intel_limits_g4x_sdvo = { |
273e27ca EA |
295 | .dot = { .min = 25000, .max = 270000 }, |
296 | .vco = { .min = 1750000, .max = 3500000}, | |
297 | .n = { .min = 1, .max = 4 }, | |
298 | .m = { .min = 104, .max = 138 }, | |
299 | .m1 = { .min = 17, .max = 23 }, | |
300 | .m2 = { .min = 5, .max = 11 }, | |
301 | .p = { .min = 10, .max = 30 }, | |
302 | .p1 = { .min = 1, .max = 3}, | |
303 | .p2 = { .dot_limit = 270000, | |
304 | .p2_slow = 10, | |
305 | .p2_fast = 10 | |
044c7c41 | 306 | }, |
e4b36699 KP |
307 | }; |
308 | ||
1b6f4958 | 309 | static const struct intel_limit intel_limits_g4x_hdmi = { |
273e27ca EA |
310 | .dot = { .min = 22000, .max = 400000 }, |
311 | .vco = { .min = 1750000, .max = 3500000}, | |
312 | .n = { .min = 1, .max = 4 }, | |
313 | .m = { .min = 104, .max = 138 }, | |
314 | .m1 = { .min = 16, .max = 23 }, | |
315 | .m2 = { .min = 5, .max = 11 }, | |
316 | .p = { .min = 5, .max = 80 }, | |
317 | .p1 = { .min = 1, .max = 8}, | |
318 | .p2 = { .dot_limit = 165000, | |
319 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
320 | }; |
321 | ||
1b6f4958 | 322 | static const struct intel_limit intel_limits_g4x_single_channel_lvds = { |
273e27ca EA |
323 | .dot = { .min = 20000, .max = 115000 }, |
324 | .vco = { .min = 1750000, .max = 3500000 }, | |
325 | .n = { .min = 1, .max = 3 }, | |
326 | .m = { .min = 104, .max = 138 }, | |
327 | .m1 = { .min = 17, .max = 23 }, | |
328 | .m2 = { .min = 5, .max = 11 }, | |
329 | .p = { .min = 28, .max = 112 }, | |
330 | .p1 = { .min = 2, .max = 8 }, | |
331 | .p2 = { .dot_limit = 0, | |
332 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 333 | }, |
e4b36699 KP |
334 | }; |
335 | ||
1b6f4958 | 336 | static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { |
273e27ca EA |
337 | .dot = { .min = 80000, .max = 224000 }, |
338 | .vco = { .min = 1750000, .max = 3500000 }, | |
339 | .n = { .min = 1, .max = 3 }, | |
340 | .m = { .min = 104, .max = 138 }, | |
341 | .m1 = { .min = 17, .max = 23 }, | |
342 | .m2 = { .min = 5, .max = 11 }, | |
343 | .p = { .min = 14, .max = 42 }, | |
344 | .p1 = { .min = 2, .max = 6 }, | |
345 | .p2 = { .dot_limit = 0, | |
346 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 347 | }, |
e4b36699 KP |
348 | }; |
349 | ||
1b6f4958 | 350 | static const struct intel_limit intel_limits_pineview_sdvo = { |
0206e353 AJ |
351 | .dot = { .min = 20000, .max = 400000}, |
352 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 353 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
354 | .n = { .min = 3, .max = 6 }, |
355 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 356 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
357 | .m1 = { .min = 0, .max = 0 }, |
358 | .m2 = { .min = 0, .max = 254 }, | |
359 | .p = { .min = 5, .max = 80 }, | |
360 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
361 | .p2 = { .dot_limit = 200000, |
362 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
363 | }; |
364 | ||
1b6f4958 | 365 | static const struct intel_limit intel_limits_pineview_lvds = { |
0206e353 AJ |
366 | .dot = { .min = 20000, .max = 400000 }, |
367 | .vco = { .min = 1700000, .max = 3500000 }, | |
368 | .n = { .min = 3, .max = 6 }, | |
369 | .m = { .min = 2, .max = 256 }, | |
370 | .m1 = { .min = 0, .max = 0 }, | |
371 | .m2 = { .min = 0, .max = 254 }, | |
372 | .p = { .min = 7, .max = 112 }, | |
373 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
374 | .p2 = { .dot_limit = 112000, |
375 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
376 | }; |
377 | ||
273e27ca EA |
378 | /* Ironlake / Sandybridge |
379 | * | |
380 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
381 | * the range value for them is (actual_value - 2). | |
382 | */ | |
1b6f4958 | 383 | static const struct intel_limit intel_limits_ironlake_dac = { |
273e27ca EA |
384 | .dot = { .min = 25000, .max = 350000 }, |
385 | .vco = { .min = 1760000, .max = 3510000 }, | |
386 | .n = { .min = 1, .max = 5 }, | |
387 | .m = { .min = 79, .max = 127 }, | |
388 | .m1 = { .min = 12, .max = 22 }, | |
389 | .m2 = { .min = 5, .max = 9 }, | |
390 | .p = { .min = 5, .max = 80 }, | |
391 | .p1 = { .min = 1, .max = 8 }, | |
392 | .p2 = { .dot_limit = 225000, | |
393 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
394 | }; |
395 | ||
1b6f4958 | 396 | static const struct intel_limit intel_limits_ironlake_single_lvds = { |
273e27ca EA |
397 | .dot = { .min = 25000, .max = 350000 }, |
398 | .vco = { .min = 1760000, .max = 3510000 }, | |
399 | .n = { .min = 1, .max = 3 }, | |
400 | .m = { .min = 79, .max = 118 }, | |
401 | .m1 = { .min = 12, .max = 22 }, | |
402 | .m2 = { .min = 5, .max = 9 }, | |
403 | .p = { .min = 28, .max = 112 }, | |
404 | .p1 = { .min = 2, .max = 8 }, | |
405 | .p2 = { .dot_limit = 225000, | |
406 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
407 | }; |
408 | ||
1b6f4958 | 409 | static const struct intel_limit intel_limits_ironlake_dual_lvds = { |
273e27ca EA |
410 | .dot = { .min = 25000, .max = 350000 }, |
411 | .vco = { .min = 1760000, .max = 3510000 }, | |
412 | .n = { .min = 1, .max = 3 }, | |
413 | .m = { .min = 79, .max = 127 }, | |
414 | .m1 = { .min = 12, .max = 22 }, | |
415 | .m2 = { .min = 5, .max = 9 }, | |
416 | .p = { .min = 14, .max = 56 }, | |
417 | .p1 = { .min = 2, .max = 8 }, | |
418 | .p2 = { .dot_limit = 225000, | |
419 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
420 | }; |
421 | ||
273e27ca | 422 | /* LVDS 100mhz refclk limits. */ |
1b6f4958 | 423 | static const struct intel_limit intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
424 | .dot = { .min = 25000, .max = 350000 }, |
425 | .vco = { .min = 1760000, .max = 3510000 }, | |
426 | .n = { .min = 1, .max = 2 }, | |
427 | .m = { .min = 79, .max = 126 }, | |
428 | .m1 = { .min = 12, .max = 22 }, | |
429 | .m2 = { .min = 5, .max = 9 }, | |
430 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 431 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
432 | .p2 = { .dot_limit = 225000, |
433 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
434 | }; |
435 | ||
1b6f4958 | 436 | static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = { |
273e27ca EA |
437 | .dot = { .min = 25000, .max = 350000 }, |
438 | .vco = { .min = 1760000, .max = 3510000 }, | |
439 | .n = { .min = 1, .max = 3 }, | |
440 | .m = { .min = 79, .max = 126 }, | |
441 | .m1 = { .min = 12, .max = 22 }, | |
442 | .m2 = { .min = 5, .max = 9 }, | |
443 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 444 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
445 | .p2 = { .dot_limit = 225000, |
446 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
447 | }; |
448 | ||
1b6f4958 | 449 | static const struct intel_limit intel_limits_vlv = { |
f01b7962 VS |
450 | /* |
451 | * These are the data rate limits (measured in fast clocks) | |
452 | * since those are the strictest limits we have. The fast | |
453 | * clock and actual rate limits are more relaxed, so checking | |
454 | * them would make no difference. | |
455 | */ | |
456 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 457 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 458 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
459 | .m1 = { .min = 2, .max = 3 }, |
460 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 461 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 462 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
463 | }; |
464 | ||
1b6f4958 | 465 | static const struct intel_limit intel_limits_chv = { |
ef9348c8 CML |
466 | /* |
467 | * These are the data rate limits (measured in fast clocks) | |
468 | * since those are the strictest limits we have. The fast | |
469 | * clock and actual rate limits are more relaxed, so checking | |
470 | * them would make no difference. | |
471 | */ | |
472 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 473 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
474 | .n = { .min = 1, .max = 1 }, |
475 | .m1 = { .min = 2, .max = 2 }, | |
476 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
477 | .p1 = { .min = 2, .max = 4 }, | |
478 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
479 | }; | |
480 | ||
1b6f4958 | 481 | static const struct intel_limit intel_limits_bxt = { |
5ab7b0b7 ID |
482 | /* FIXME: find real dot limits */ |
483 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 484 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
485 | .n = { .min = 1, .max = 1 }, |
486 | .m1 = { .min = 2, .max = 2 }, | |
487 | /* FIXME: find real m2 limits */ | |
488 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
489 | .p1 = { .min = 2, .max = 4 }, | |
490 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
491 | }; | |
492 | ||
cdba954e ACO |
493 | static bool |
494 | needs_modeset(struct drm_crtc_state *state) | |
495 | { | |
fc596660 | 496 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
497 | } |
498 | ||
dccbea3b ID |
499 | /* |
500 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
501 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
502 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
503 | * The helpers' return value is the rate of the clock that is fed to the | |
504 | * display engine's pipe which can be the above fast dot clock rate or a | |
505 | * divided-down version of it. | |
506 | */ | |
f2b115e6 | 507 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
9e2c8475 | 508 | static int pnv_calc_dpll_params(int refclk, struct dpll *clock) |
79e53945 | 509 | { |
2177832f SL |
510 | clock->m = clock->m2 + 2; |
511 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 512 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 513 | return 0; |
fb03ac01 VS |
514 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
515 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
516 | |
517 | return clock->dot; | |
2177832f SL |
518 | } |
519 | ||
7429e9d4 DV |
520 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
521 | { | |
522 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
523 | } | |
524 | ||
9e2c8475 | 525 | static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) |
2177832f | 526 | { |
7429e9d4 | 527 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 528 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 529 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 530 | return 0; |
fb03ac01 VS |
531 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
532 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
533 | |
534 | return clock->dot; | |
79e53945 JB |
535 | } |
536 | ||
9e2c8475 | 537 | static int vlv_calc_dpll_params(int refclk, struct dpll *clock) |
589eca67 ID |
538 | { |
539 | clock->m = clock->m1 * clock->m2; | |
540 | clock->p = clock->p1 * clock->p2; | |
541 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 542 | return 0; |
589eca67 ID |
543 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
544 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
545 | |
546 | return clock->dot / 5; | |
589eca67 ID |
547 | } |
548 | ||
9e2c8475 | 549 | int chv_calc_dpll_params(int refclk, struct dpll *clock) |
ef9348c8 CML |
550 | { |
551 | clock->m = clock->m1 * clock->m2; | |
552 | clock->p = clock->p1 * clock->p2; | |
553 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 554 | return 0; |
ef9348c8 CML |
555 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
556 | clock->n << 22); | |
557 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
558 | |
559 | return clock->dot / 5; | |
ef9348c8 CML |
560 | } |
561 | ||
7c04d1d9 | 562 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
563 | /** |
564 | * Returns whether the given set of divisors are valid for a given refclk with | |
565 | * the given connectors. | |
566 | */ | |
567 | ||
e2d214ae | 568 | static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv, |
1b6f4958 | 569 | const struct intel_limit *limit, |
9e2c8475 | 570 | const struct dpll *clock) |
79e53945 | 571 | { |
f01b7962 VS |
572 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
573 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 574 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 575 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 576 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 577 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 578 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 579 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 580 | |
e2d214ae | 581 | if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) && |
cc3f90f0 | 582 | !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv)) |
f01b7962 VS |
583 | if (clock->m1 <= clock->m2) |
584 | INTELPllInvalid("m1 <= m2\n"); | |
585 | ||
e2d214ae | 586 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
cc3f90f0 | 587 | !IS_GEN9_LP(dev_priv)) { |
f01b7962 VS |
588 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
589 | INTELPllInvalid("p out of range\n"); | |
590 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
591 | INTELPllInvalid("m out of range\n"); | |
592 | } | |
593 | ||
79e53945 | 594 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 595 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
596 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
597 | * connector, etc., rather than just a single range. | |
598 | */ | |
599 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 600 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
601 | |
602 | return true; | |
603 | } | |
604 | ||
3b1429d9 | 605 | static int |
1b6f4958 | 606 | i9xx_select_p2_div(const struct intel_limit *limit, |
3b1429d9 VS |
607 | const struct intel_crtc_state *crtc_state, |
608 | int target) | |
79e53945 | 609 | { |
3b1429d9 | 610 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 611 | |
2d84d2b3 | 612 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 613 | /* |
a210b028 DV |
614 | * For LVDS just rely on its current settings for dual-channel. |
615 | * We haven't figured out how to reliably set up different | |
616 | * single/dual channel state, if we even can. | |
79e53945 | 617 | */ |
1974cad0 | 618 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 619 | return limit->p2.p2_fast; |
79e53945 | 620 | else |
3b1429d9 | 621 | return limit->p2.p2_slow; |
79e53945 JB |
622 | } else { |
623 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 624 | return limit->p2.p2_slow; |
79e53945 | 625 | else |
3b1429d9 | 626 | return limit->p2.p2_fast; |
79e53945 | 627 | } |
3b1429d9 VS |
628 | } |
629 | ||
70e8aa21 ACO |
630 | /* |
631 | * Returns a set of divisors for the desired target clock with the given | |
632 | * refclk, or FALSE. The returned values represent the clock equation: | |
633 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
634 | * | |
635 | * Target and reference clocks are specified in kHz. | |
636 | * | |
637 | * If match_clock is provided, then best_clock P divider must match the P | |
638 | * divider from @match_clock used for LVDS downclocking. | |
639 | */ | |
3b1429d9 | 640 | static bool |
1b6f4958 | 641 | i9xx_find_best_dpll(const struct intel_limit *limit, |
3b1429d9 | 642 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
643 | int target, int refclk, struct dpll *match_clock, |
644 | struct dpll *best_clock) | |
3b1429d9 VS |
645 | { |
646 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
9e2c8475 | 647 | struct dpll clock; |
3b1429d9 | 648 | int err = target; |
79e53945 | 649 | |
0206e353 | 650 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 651 | |
3b1429d9 VS |
652 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
653 | ||
42158660 ZY |
654 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
655 | clock.m1++) { | |
656 | for (clock.m2 = limit->m2.min; | |
657 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 658 | if (clock.m2 >= clock.m1) |
42158660 ZY |
659 | break; |
660 | for (clock.n = limit->n.min; | |
661 | clock.n <= limit->n.max; clock.n++) { | |
662 | for (clock.p1 = limit->p1.min; | |
663 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
664 | int this_err; |
665 | ||
dccbea3b | 666 | i9xx_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
667 | if (!intel_PLL_is_valid(to_i915(dev), |
668 | limit, | |
ac58c3f0 DV |
669 | &clock)) |
670 | continue; | |
671 | if (match_clock && | |
672 | clock.p != match_clock->p) | |
673 | continue; | |
674 | ||
675 | this_err = abs(clock.dot - target); | |
676 | if (this_err < err) { | |
677 | *best_clock = clock; | |
678 | err = this_err; | |
679 | } | |
680 | } | |
681 | } | |
682 | } | |
683 | } | |
684 | ||
685 | return (err != target); | |
686 | } | |
687 | ||
70e8aa21 ACO |
688 | /* |
689 | * Returns a set of divisors for the desired target clock with the given | |
690 | * refclk, or FALSE. The returned values represent the clock equation: | |
691 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
692 | * | |
693 | * Target and reference clocks are specified in kHz. | |
694 | * | |
695 | * If match_clock is provided, then best_clock P divider must match the P | |
696 | * divider from @match_clock used for LVDS downclocking. | |
697 | */ | |
ac58c3f0 | 698 | static bool |
1b6f4958 | 699 | pnv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 700 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
701 | int target, int refclk, struct dpll *match_clock, |
702 | struct dpll *best_clock) | |
79e53945 | 703 | { |
3b1429d9 | 704 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 705 | struct dpll clock; |
79e53945 JB |
706 | int err = target; |
707 | ||
0206e353 | 708 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 709 | |
3b1429d9 VS |
710 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
711 | ||
42158660 ZY |
712 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
713 | clock.m1++) { | |
714 | for (clock.m2 = limit->m2.min; | |
715 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
716 | for (clock.n = limit->n.min; |
717 | clock.n <= limit->n.max; clock.n++) { | |
718 | for (clock.p1 = limit->p1.min; | |
719 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
720 | int this_err; |
721 | ||
dccbea3b | 722 | pnv_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
723 | if (!intel_PLL_is_valid(to_i915(dev), |
724 | limit, | |
1b894b59 | 725 | &clock)) |
79e53945 | 726 | continue; |
cec2f356 SP |
727 | if (match_clock && |
728 | clock.p != match_clock->p) | |
729 | continue; | |
79e53945 JB |
730 | |
731 | this_err = abs(clock.dot - target); | |
732 | if (this_err < err) { | |
733 | *best_clock = clock; | |
734 | err = this_err; | |
735 | } | |
736 | } | |
737 | } | |
738 | } | |
739 | } | |
740 | ||
741 | return (err != target); | |
742 | } | |
743 | ||
997c030c ACO |
744 | /* |
745 | * Returns a set of divisors for the desired target clock with the given | |
746 | * refclk, or FALSE. The returned values represent the clock equation: | |
747 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
70e8aa21 ACO |
748 | * |
749 | * Target and reference clocks are specified in kHz. | |
750 | * | |
751 | * If match_clock is provided, then best_clock P divider must match the P | |
752 | * divider from @match_clock used for LVDS downclocking. | |
997c030c | 753 | */ |
d4906093 | 754 | static bool |
1b6f4958 | 755 | g4x_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 756 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
757 | int target, int refclk, struct dpll *match_clock, |
758 | struct dpll *best_clock) | |
d4906093 | 759 | { |
3b1429d9 | 760 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 761 | struct dpll clock; |
d4906093 | 762 | int max_n; |
3b1429d9 | 763 | bool found = false; |
6ba770dc AJ |
764 | /* approximately equals target * 0.00585 */ |
765 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
766 | |
767 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
768 | |
769 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
770 | ||
d4906093 | 771 | max_n = limit->n.max; |
f77f13e2 | 772 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 773 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 774 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
775 | for (clock.m1 = limit->m1.max; |
776 | clock.m1 >= limit->m1.min; clock.m1--) { | |
777 | for (clock.m2 = limit->m2.max; | |
778 | clock.m2 >= limit->m2.min; clock.m2--) { | |
779 | for (clock.p1 = limit->p1.max; | |
780 | clock.p1 >= limit->p1.min; clock.p1--) { | |
781 | int this_err; | |
782 | ||
dccbea3b | 783 | i9xx_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
784 | if (!intel_PLL_is_valid(to_i915(dev), |
785 | limit, | |
1b894b59 | 786 | &clock)) |
d4906093 | 787 | continue; |
1b894b59 CW |
788 | |
789 | this_err = abs(clock.dot - target); | |
d4906093 ML |
790 | if (this_err < err_most) { |
791 | *best_clock = clock; | |
792 | err_most = this_err; | |
793 | max_n = clock.n; | |
794 | found = true; | |
795 | } | |
796 | } | |
797 | } | |
798 | } | |
799 | } | |
2c07245f ZW |
800 | return found; |
801 | } | |
802 | ||
d5dd62bd ID |
803 | /* |
804 | * Check if the calculated PLL configuration is more optimal compared to the | |
805 | * best configuration and error found so far. Return the calculated error. | |
806 | */ | |
807 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
9e2c8475 ACO |
808 | const struct dpll *calculated_clock, |
809 | const struct dpll *best_clock, | |
d5dd62bd ID |
810 | unsigned int best_error_ppm, |
811 | unsigned int *error_ppm) | |
812 | { | |
9ca3ba01 ID |
813 | /* |
814 | * For CHV ignore the error and consider only the P value. | |
815 | * Prefer a bigger P value based on HW requirements. | |
816 | */ | |
920a14b2 | 817 | if (IS_CHERRYVIEW(to_i915(dev))) { |
9ca3ba01 ID |
818 | *error_ppm = 0; |
819 | ||
820 | return calculated_clock->p > best_clock->p; | |
821 | } | |
822 | ||
24be4e46 ID |
823 | if (WARN_ON_ONCE(!target_freq)) |
824 | return false; | |
825 | ||
d5dd62bd ID |
826 | *error_ppm = div_u64(1000000ULL * |
827 | abs(target_freq - calculated_clock->dot), | |
828 | target_freq); | |
829 | /* | |
830 | * Prefer a better P value over a better (smaller) error if the error | |
831 | * is small. Ensure this preference for future configurations too by | |
832 | * setting the error to 0. | |
833 | */ | |
834 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
835 | *error_ppm = 0; | |
836 | ||
837 | return true; | |
838 | } | |
839 | ||
840 | return *error_ppm + 10 < best_error_ppm; | |
841 | } | |
842 | ||
65b3d6a9 ACO |
843 | /* |
844 | * Returns a set of divisors for the desired target clock with the given | |
845 | * refclk, or FALSE. The returned values represent the clock equation: | |
846 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
847 | */ | |
a0c4da24 | 848 | static bool |
1b6f4958 | 849 | vlv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 850 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
851 | int target, int refclk, struct dpll *match_clock, |
852 | struct dpll *best_clock) | |
a0c4da24 | 853 | { |
a93e255f | 854 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 855 | struct drm_device *dev = crtc->base.dev; |
9e2c8475 | 856 | struct dpll clock; |
69e4f900 | 857 | unsigned int bestppm = 1000000; |
27e639bf VS |
858 | /* min update 19.2 MHz */ |
859 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 860 | bool found = false; |
a0c4da24 | 861 | |
6b4bf1c4 VS |
862 | target *= 5; /* fast clock */ |
863 | ||
864 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
865 | |
866 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 867 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 868 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 869 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 870 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 871 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 872 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 873 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 874 | unsigned int ppm; |
69e4f900 | 875 | |
6b4bf1c4 VS |
876 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
877 | refclk * clock.m1); | |
878 | ||
dccbea3b | 879 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 880 | |
e2d214ae TU |
881 | if (!intel_PLL_is_valid(to_i915(dev), |
882 | limit, | |
f01b7962 | 883 | &clock)) |
43b0ac53 VS |
884 | continue; |
885 | ||
d5dd62bd ID |
886 | if (!vlv_PLL_is_optimal(dev, target, |
887 | &clock, | |
888 | best_clock, | |
889 | bestppm, &ppm)) | |
890 | continue; | |
6b4bf1c4 | 891 | |
d5dd62bd ID |
892 | *best_clock = clock; |
893 | bestppm = ppm; | |
894 | found = true; | |
a0c4da24 JB |
895 | } |
896 | } | |
897 | } | |
898 | } | |
a0c4da24 | 899 | |
49e497ef | 900 | return found; |
a0c4da24 | 901 | } |
a4fc5ed6 | 902 | |
65b3d6a9 ACO |
903 | /* |
904 | * Returns a set of divisors for the desired target clock with the given | |
905 | * refclk, or FALSE. The returned values represent the clock equation: | |
906 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
907 | */ | |
ef9348c8 | 908 | static bool |
1b6f4958 | 909 | chv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 910 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
911 | int target, int refclk, struct dpll *match_clock, |
912 | struct dpll *best_clock) | |
ef9348c8 | 913 | { |
a93e255f | 914 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 915 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 916 | unsigned int best_error_ppm; |
9e2c8475 | 917 | struct dpll clock; |
ef9348c8 CML |
918 | uint64_t m2; |
919 | int found = false; | |
920 | ||
921 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 922 | best_error_ppm = 1000000; |
ef9348c8 CML |
923 | |
924 | /* | |
925 | * Based on hardware doc, the n always set to 1, and m1 always | |
926 | * set to 2. If requires to support 200Mhz refclk, we need to | |
927 | * revisit this because n may not 1 anymore. | |
928 | */ | |
929 | clock.n = 1, clock.m1 = 2; | |
930 | target *= 5; /* fast clock */ | |
931 | ||
932 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
933 | for (clock.p2 = limit->p2.p2_fast; | |
934 | clock.p2 >= limit->p2.p2_slow; | |
935 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 936 | unsigned int error_ppm; |
ef9348c8 CML |
937 | |
938 | clock.p = clock.p1 * clock.p2; | |
939 | ||
940 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
941 | clock.n) << 22, refclk * clock.m1); | |
942 | ||
943 | if (m2 > INT_MAX/clock.m1) | |
944 | continue; | |
945 | ||
946 | clock.m2 = m2; | |
947 | ||
dccbea3b | 948 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 | 949 | |
e2d214ae | 950 | if (!intel_PLL_is_valid(to_i915(dev), limit, &clock)) |
ef9348c8 CML |
951 | continue; |
952 | ||
9ca3ba01 ID |
953 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
954 | best_error_ppm, &error_ppm)) | |
955 | continue; | |
956 | ||
957 | *best_clock = clock; | |
958 | best_error_ppm = error_ppm; | |
959 | found = true; | |
ef9348c8 CML |
960 | } |
961 | } | |
962 | ||
963 | return found; | |
964 | } | |
965 | ||
5ab7b0b7 | 966 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
9e2c8475 | 967 | struct dpll *best_clock) |
5ab7b0b7 | 968 | { |
65b3d6a9 | 969 | int refclk = 100000; |
1b6f4958 | 970 | const struct intel_limit *limit = &intel_limits_bxt; |
5ab7b0b7 | 971 | |
65b3d6a9 | 972 | return chv_find_best_dpll(limit, crtc_state, |
5ab7b0b7 ID |
973 | target_clock, refclk, NULL, best_clock); |
974 | } | |
975 | ||
525b9311 | 976 | bool intel_crtc_active(struct intel_crtc *crtc) |
20ddf665 | 977 | { |
20ddf665 VS |
978 | /* Be paranoid as we can arrive here with only partial |
979 | * state retrieved from the hardware during setup. | |
980 | * | |
241bfc38 | 981 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
982 | * as Haswell has gained clock readout/fastboot support. |
983 | * | |
66e514c1 | 984 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 985 | * properly reconstruct framebuffers. |
c3d1f436 MR |
986 | * |
987 | * FIXME: The intel_crtc->active here should be switched to | |
988 | * crtc->state->active once we have proper CRTC states wired up | |
989 | * for atomic. | |
20ddf665 | 990 | */ |
525b9311 VS |
991 | return crtc->active && crtc->base.primary->state->fb && |
992 | crtc->config->base.adjusted_mode.crtc_clock; | |
20ddf665 VS |
993 | } |
994 | ||
a5c961d1 PZ |
995 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
996 | enum pipe pipe) | |
997 | { | |
98187836 | 998 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
a5c961d1 | 999 | |
e2af48c6 | 1000 | return crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1001 | } |
1002 | ||
6315b5d3 | 1003 | static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe) |
fbf49ea2 | 1004 | { |
f0f59a00 | 1005 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1006 | u32 line1, line2; |
1007 | u32 line_mask; | |
1008 | ||
5db94019 | 1009 | if (IS_GEN2(dev_priv)) |
fbf49ea2 VS |
1010 | line_mask = DSL_LINEMASK_GEN2; |
1011 | else | |
1012 | line_mask = DSL_LINEMASK_GEN3; | |
1013 | ||
1014 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1015 | msleep(5); |
fbf49ea2 VS |
1016 | line2 = I915_READ(reg) & line_mask; |
1017 | ||
1018 | return line1 == line2; | |
1019 | } | |
1020 | ||
ab7ad7f6 KP |
1021 | /* |
1022 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1023 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1024 | * |
1025 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1026 | * spinning on the vblank interrupt status bit, since we won't actually | |
1027 | * see an interrupt when the pipe is disabled. | |
1028 | * | |
ab7ad7f6 KP |
1029 | * On Gen4 and above: |
1030 | * wait for the pipe register state bit to turn off | |
1031 | * | |
1032 | * Otherwise: | |
1033 | * wait for the display line value to settle (it usually | |
1034 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1035 | * |
9d0498a2 | 1036 | */ |
575f7ab7 | 1037 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1038 | { |
6315b5d3 | 1039 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 1040 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1041 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 | 1042 | |
6315b5d3 | 1043 | if (INTEL_GEN(dev_priv) >= 4) { |
f0f59a00 | 1044 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1045 | |
1046 | /* Wait for the Pipe State to go off */ | |
b8511f53 CW |
1047 | if (intel_wait_for_register(dev_priv, |
1048 | reg, I965_PIPECONF_ACTIVE, 0, | |
1049 | 100)) | |
284637d9 | 1050 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1051 | } else { |
ab7ad7f6 | 1052 | /* Wait for the display line to settle */ |
6315b5d3 | 1053 | if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100)) |
284637d9 | 1054 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1055 | } |
79e53945 JB |
1056 | } |
1057 | ||
b24e7179 | 1058 | /* Only for pre-ILK configs */ |
55607e8a DV |
1059 | void assert_pll(struct drm_i915_private *dev_priv, |
1060 | enum pipe pipe, bool state) | |
b24e7179 | 1061 | { |
b24e7179 JB |
1062 | u32 val; |
1063 | bool cur_state; | |
1064 | ||
649636ef | 1065 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1066 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1067 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1068 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1069 | onoff(state), onoff(cur_state)); |
b24e7179 | 1070 | } |
b24e7179 | 1071 | |
23538ef1 | 1072 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
8563b1e8 | 1073 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
23538ef1 JN |
1074 | { |
1075 | u32 val; | |
1076 | bool cur_state; | |
1077 | ||
a580516d | 1078 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1079 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1080 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1081 | |
1082 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1083 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1084 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1085 | onoff(state), onoff(cur_state)); |
23538ef1 | 1086 | } |
23538ef1 | 1087 | |
040484af JB |
1088 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1089 | enum pipe pipe, bool state) | |
1090 | { | |
040484af | 1091 | bool cur_state; |
ad80a810 PZ |
1092 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1093 | pipe); | |
040484af | 1094 | |
2d1fe073 | 1095 | if (HAS_DDI(dev_priv)) { |
affa9354 | 1096 | /* DDI does not have a specific FDI_TX register */ |
649636ef | 1097 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1098 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1099 | } else { |
649636ef | 1100 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1101 | cur_state = !!(val & FDI_TX_ENABLE); |
1102 | } | |
e2c719b7 | 1103 | I915_STATE_WARN(cur_state != state, |
040484af | 1104 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1105 | onoff(state), onoff(cur_state)); |
040484af JB |
1106 | } |
1107 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1108 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1109 | ||
1110 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1111 | enum pipe pipe, bool state) | |
1112 | { | |
040484af JB |
1113 | u32 val; |
1114 | bool cur_state; | |
1115 | ||
649636ef | 1116 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1117 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1118 | I915_STATE_WARN(cur_state != state, |
040484af | 1119 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1120 | onoff(state), onoff(cur_state)); |
040484af JB |
1121 | } |
1122 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1123 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1124 | ||
1125 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1126 | enum pipe pipe) | |
1127 | { | |
040484af JB |
1128 | u32 val; |
1129 | ||
1130 | /* ILK FDI PLL is always enabled */ | |
7e22dbbb | 1131 | if (IS_GEN5(dev_priv)) |
040484af JB |
1132 | return; |
1133 | ||
bf507ef7 | 1134 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
2d1fe073 | 1135 | if (HAS_DDI(dev_priv)) |
bf507ef7 ED |
1136 | return; |
1137 | ||
649636ef | 1138 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1139 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1140 | } |
1141 | ||
55607e8a DV |
1142 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1143 | enum pipe pipe, bool state) | |
040484af | 1144 | { |
040484af | 1145 | u32 val; |
55607e8a | 1146 | bool cur_state; |
040484af | 1147 | |
649636ef | 1148 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1149 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1150 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1151 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1152 | onoff(state), onoff(cur_state)); |
040484af JB |
1153 | } |
1154 | ||
4f8036a2 | 1155 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) |
ea0760cf | 1156 | { |
f0f59a00 | 1157 | i915_reg_t pp_reg; |
ea0760cf JB |
1158 | u32 val; |
1159 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1160 | bool locked = true; |
ea0760cf | 1161 | |
4f8036a2 | 1162 | if (WARN_ON(HAS_DDI(dev_priv))) |
bedd4dba JN |
1163 | return; |
1164 | ||
4f8036a2 | 1165 | if (HAS_PCH_SPLIT(dev_priv)) { |
bedd4dba JN |
1166 | u32 port_sel; |
1167 | ||
44cb734c ID |
1168 | pp_reg = PP_CONTROL(0); |
1169 | port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; | |
bedd4dba JN |
1170 | |
1171 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1172 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1173 | panel_pipe = PIPE_B; | |
1174 | /* XXX: else fix for eDP */ | |
4f8036a2 | 1175 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
bedd4dba | 1176 | /* presumably write lock depends on pipe, not port select */ |
44cb734c | 1177 | pp_reg = PP_CONTROL(pipe); |
bedd4dba | 1178 | panel_pipe = pipe; |
ea0760cf | 1179 | } else { |
44cb734c | 1180 | pp_reg = PP_CONTROL(0); |
bedd4dba JN |
1181 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1182 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1183 | } |
1184 | ||
1185 | val = I915_READ(pp_reg); | |
1186 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1187 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1188 | locked = false; |
1189 | ||
e2c719b7 | 1190 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1191 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1192 | pipe_name(pipe)); |
ea0760cf JB |
1193 | } |
1194 | ||
93ce0ba6 JN |
1195 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1196 | enum pipe pipe, bool state) | |
1197 | { | |
93ce0ba6 JN |
1198 | bool cur_state; |
1199 | ||
2a307c2e | 1200 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
0b87c24e | 1201 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1202 | else |
5efb3e28 | 1203 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1204 | |
e2c719b7 | 1205 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1206 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1207 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1208 | } |
1209 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1210 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1211 | ||
b840d907 JB |
1212 | void assert_pipe(struct drm_i915_private *dev_priv, |
1213 | enum pipe pipe, bool state) | |
b24e7179 | 1214 | { |
63d7bbe9 | 1215 | bool cur_state; |
702e7a56 PZ |
1216 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1217 | pipe); | |
4feed0eb | 1218 | enum intel_display_power_domain power_domain; |
b24e7179 | 1219 | |
e56134bc VS |
1220 | /* we keep both pipes enabled on 830 */ |
1221 | if (IS_I830(dev_priv)) | |
8e636784 DV |
1222 | state = true; |
1223 | ||
4feed0eb ID |
1224 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1225 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
649636ef | 1226 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 | 1227 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb ID |
1228 | |
1229 | intel_display_power_put(dev_priv, power_domain); | |
1230 | } else { | |
1231 | cur_state = false; | |
69310161 PZ |
1232 | } |
1233 | ||
e2c719b7 | 1234 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1235 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1236 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1237 | } |
1238 | ||
931872fc CW |
1239 | static void assert_plane(struct drm_i915_private *dev_priv, |
1240 | enum plane plane, bool state) | |
b24e7179 | 1241 | { |
b24e7179 | 1242 | u32 val; |
931872fc | 1243 | bool cur_state; |
b24e7179 | 1244 | |
649636ef | 1245 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1246 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1247 | I915_STATE_WARN(cur_state != state, |
931872fc | 1248 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1249 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1250 | } |
1251 | ||
931872fc CW |
1252 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1253 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1254 | ||
b24e7179 JB |
1255 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1256 | enum pipe pipe) | |
1257 | { | |
649636ef | 1258 | int i; |
b24e7179 | 1259 | |
653e1026 | 1260 | /* Primary planes are fixed to pipes on gen4+ */ |
6315b5d3 | 1261 | if (INTEL_GEN(dev_priv) >= 4) { |
649636ef | 1262 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1263 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1264 | "plane %c assertion failure, should be disabled but not\n", |
1265 | plane_name(pipe)); | |
19ec1358 | 1266 | return; |
28c05794 | 1267 | } |
19ec1358 | 1268 | |
b24e7179 | 1269 | /* Need to check both planes against the pipe */ |
055e393f | 1270 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1271 | u32 val = I915_READ(DSPCNTR(i)); |
1272 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1273 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1274 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1275 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1276 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1277 | } |
1278 | } | |
1279 | ||
19332d7a JB |
1280 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1281 | enum pipe pipe) | |
1282 | { | |
649636ef | 1283 | int sprite; |
19332d7a | 1284 | |
6315b5d3 | 1285 | if (INTEL_GEN(dev_priv) >= 9) { |
3bdcfc0c | 1286 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1287 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1288 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1289 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1290 | sprite, pipe_name(pipe)); | |
1291 | } | |
920a14b2 | 1292 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
3bdcfc0c | 1293 | for_each_sprite(dev_priv, pipe, sprite) { |
83c04a62 | 1294 | u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite)); |
e2c719b7 | 1295 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1296 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1297 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef | 1298 | } |
6315b5d3 | 1299 | } else if (INTEL_GEN(dev_priv) >= 7) { |
649636ef | 1300 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1301 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1302 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1303 | plane_name(pipe), pipe_name(pipe)); |
ab33081a | 1304 | } else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) { |
649636ef | 1305 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1306 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1307 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1308 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1309 | } |
1310 | } | |
1311 | ||
08c71e5e VS |
1312 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1313 | { | |
e2c719b7 | 1314 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1315 | drm_crtc_vblank_put(crtc); |
1316 | } | |
1317 | ||
7abd4b35 ACO |
1318 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1319 | enum pipe pipe) | |
92f2584a | 1320 | { |
92f2584a JB |
1321 | u32 val; |
1322 | bool enabled; | |
1323 | ||
649636ef | 1324 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1325 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1326 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1327 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1328 | pipe_name(pipe)); | |
92f2584a JB |
1329 | } |
1330 | ||
4e634389 KP |
1331 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1332 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1333 | { |
1334 | if ((val & DP_PORT_EN) == 0) | |
1335 | return false; | |
1336 | ||
2d1fe073 | 1337 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 | 1338 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1339 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1340 | return false; | |
2d1fe073 | 1341 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1342 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
1343 | return false; | |
f0575e92 KP |
1344 | } else { |
1345 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1346 | return false; | |
1347 | } | |
1348 | return true; | |
1349 | } | |
1350 | ||
1519b995 KP |
1351 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1352 | enum pipe pipe, u32 val) | |
1353 | { | |
dc0fa718 | 1354 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1355 | return false; |
1356 | ||
2d1fe073 | 1357 | if (HAS_PCH_CPT(dev_priv)) { |
dc0fa718 | 1358 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1359 | return false; |
2d1fe073 | 1360 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1361 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) |
1362 | return false; | |
1519b995 | 1363 | } else { |
dc0fa718 | 1364 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1365 | return false; |
1366 | } | |
1367 | return true; | |
1368 | } | |
1369 | ||
1370 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1371 | enum pipe pipe, u32 val) | |
1372 | { | |
1373 | if ((val & LVDS_PORT_EN) == 0) | |
1374 | return false; | |
1375 | ||
2d1fe073 | 1376 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1377 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1378 | return false; | |
1379 | } else { | |
1380 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1381 | return false; | |
1382 | } | |
1383 | return true; | |
1384 | } | |
1385 | ||
1386 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1387 | enum pipe pipe, u32 val) | |
1388 | { | |
1389 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1390 | return false; | |
2d1fe073 | 1391 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1392 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1393 | return false; | |
1394 | } else { | |
1395 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1396 | return false; | |
1397 | } | |
1398 | return true; | |
1399 | } | |
1400 | ||
291906f1 | 1401 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1402 | enum pipe pipe, i915_reg_t reg, |
1403 | u32 port_sel) | |
291906f1 | 1404 | { |
47a05eca | 1405 | u32 val = I915_READ(reg); |
e2c719b7 | 1406 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1407 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1408 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1409 | |
2d1fe073 | 1410 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1411 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1412 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1413 | } |
1414 | ||
1415 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1416 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1417 | { |
47a05eca | 1418 | u32 val = I915_READ(reg); |
e2c719b7 | 1419 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1420 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1421 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1422 | |
2d1fe073 | 1423 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1424 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1425 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1426 | } |
1427 | ||
1428 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1429 | enum pipe pipe) | |
1430 | { | |
291906f1 | 1431 | u32 val; |
291906f1 | 1432 | |
f0575e92 KP |
1433 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1434 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1435 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1436 | |
649636ef | 1437 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1438 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1439 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1440 | pipe_name(pipe)); |
291906f1 | 1441 | |
649636ef | 1442 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1443 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1444 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1445 | pipe_name(pipe)); |
291906f1 | 1446 | |
e2debe91 PZ |
1447 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1448 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1449 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1450 | } |
1451 | ||
cd2d34d9 VS |
1452 | static void _vlv_enable_pll(struct intel_crtc *crtc, |
1453 | const struct intel_crtc_state *pipe_config) | |
1454 | { | |
1455 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1456 | enum pipe pipe = crtc->pipe; | |
1457 | ||
1458 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); | |
1459 | POSTING_READ(DPLL(pipe)); | |
1460 | udelay(150); | |
1461 | ||
2c30b43b CW |
1462 | if (intel_wait_for_register(dev_priv, |
1463 | DPLL(pipe), | |
1464 | DPLL_LOCK_VLV, | |
1465 | DPLL_LOCK_VLV, | |
1466 | 1)) | |
cd2d34d9 VS |
1467 | DRM_ERROR("DPLL %d failed to lock\n", pipe); |
1468 | } | |
1469 | ||
d288f65f | 1470 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1471 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1472 | { |
cd2d34d9 | 1473 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1474 | enum pipe pipe = crtc->pipe; |
87442f73 | 1475 | |
8bd3f301 | 1476 | assert_pipe_disabled(dev_priv, pipe); |
87442f73 | 1477 | |
87442f73 | 1478 | /* PLL is protected by panel, make sure we can write it */ |
7d1a83cb | 1479 | assert_panel_unlocked(dev_priv, pipe); |
87442f73 | 1480 | |
cd2d34d9 VS |
1481 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) |
1482 | _vlv_enable_pll(crtc, pipe_config); | |
426115cf | 1483 | |
8bd3f301 VS |
1484 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
1485 | POSTING_READ(DPLL_MD(pipe)); | |
87442f73 DV |
1486 | } |
1487 | ||
cd2d34d9 VS |
1488 | |
1489 | static void _chv_enable_pll(struct intel_crtc *crtc, | |
1490 | const struct intel_crtc_state *pipe_config) | |
9d556c99 | 1491 | { |
cd2d34d9 | 1492 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1493 | enum pipe pipe = crtc->pipe; |
9d556c99 | 1494 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9d556c99 CML |
1495 | u32 tmp; |
1496 | ||
a580516d | 1497 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1498 | |
1499 | /* Enable back the 10bit clock to display controller */ | |
1500 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1501 | tmp |= DPIO_DCLKP_EN; | |
1502 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1503 | ||
54433e91 VS |
1504 | mutex_unlock(&dev_priv->sb_lock); |
1505 | ||
9d556c99 CML |
1506 | /* |
1507 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1508 | */ | |
1509 | udelay(1); | |
1510 | ||
1511 | /* Enable PLL */ | |
d288f65f | 1512 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1513 | |
1514 | /* Check PLL is locked */ | |
6b18826a CW |
1515 | if (intel_wait_for_register(dev_priv, |
1516 | DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV, | |
1517 | 1)) | |
9d556c99 | 1518 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
cd2d34d9 VS |
1519 | } |
1520 | ||
1521 | static void chv_enable_pll(struct intel_crtc *crtc, | |
1522 | const struct intel_crtc_state *pipe_config) | |
1523 | { | |
1524 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1525 | enum pipe pipe = crtc->pipe; | |
1526 | ||
1527 | assert_pipe_disabled(dev_priv, pipe); | |
1528 | ||
1529 | /* PLL is protected by panel, make sure we can write it */ | |
1530 | assert_panel_unlocked(dev_priv, pipe); | |
1531 | ||
1532 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) | |
1533 | _chv_enable_pll(crtc, pipe_config); | |
9d556c99 | 1534 | |
c231775c VS |
1535 | if (pipe != PIPE_A) { |
1536 | /* | |
1537 | * WaPixelRepeatModeFixForC0:chv | |
1538 | * | |
1539 | * DPLLCMD is AWOL. Use chicken bits to propagate | |
1540 | * the value from DPLLBMD to either pipe B or C. | |
1541 | */ | |
1542 | I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C); | |
1543 | I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); | |
1544 | I915_WRITE(CBR4_VLV, 0); | |
1545 | dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; | |
1546 | ||
1547 | /* | |
1548 | * DPLLB VGA mode also seems to cause problems. | |
1549 | * We should always have it disabled. | |
1550 | */ | |
1551 | WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); | |
1552 | } else { | |
1553 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); | |
1554 | POSTING_READ(DPLL_MD(pipe)); | |
1555 | } | |
9d556c99 CML |
1556 | } |
1557 | ||
6315b5d3 | 1558 | static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv) |
1c4e0274 VS |
1559 | { |
1560 | struct intel_crtc *crtc; | |
1561 | int count = 0; | |
1562 | ||
6315b5d3 | 1563 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
3538b9df | 1564 | count += crtc->base.state->active && |
2d84d2b3 VS |
1565 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO); |
1566 | } | |
1c4e0274 VS |
1567 | |
1568 | return count; | |
1569 | } | |
1570 | ||
66e3d5c0 | 1571 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1572 | { |
6315b5d3 | 1573 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
f0f59a00 | 1574 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1575 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
bb408dd2 | 1576 | int i; |
63d7bbe9 | 1577 | |
66e3d5c0 | 1578 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1579 | |
63d7bbe9 | 1580 | /* PLL is protected by panel, make sure we can write it */ |
50a0bc90 | 1581 | if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv)) |
66e3d5c0 | 1582 | assert_panel_unlocked(dev_priv, crtc->pipe); |
63d7bbe9 | 1583 | |
1c4e0274 | 1584 | /* Enable DVO 2x clock on both PLLs if necessary */ |
6315b5d3 | 1585 | if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) { |
1c4e0274 VS |
1586 | /* |
1587 | * It appears to be important that we don't enable this | |
1588 | * for the current pipe before otherwise configuring the | |
1589 | * PLL. No idea how this should be handled if multiple | |
1590 | * DVO outputs are enabled simultaneosly. | |
1591 | */ | |
1592 | dpll |= DPLL_DVO_2X_MODE; | |
1593 | I915_WRITE(DPLL(!crtc->pipe), | |
1594 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1595 | } | |
66e3d5c0 | 1596 | |
c2b63374 VS |
1597 | /* |
1598 | * Apparently we need to have VGA mode enabled prior to changing | |
1599 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1600 | * dividers, even though the register value does change. | |
1601 | */ | |
1602 | I915_WRITE(reg, 0); | |
1603 | ||
8e7a65aa VS |
1604 | I915_WRITE(reg, dpll); |
1605 | ||
66e3d5c0 DV |
1606 | /* Wait for the clocks to stabilize. */ |
1607 | POSTING_READ(reg); | |
1608 | udelay(150); | |
1609 | ||
6315b5d3 | 1610 | if (INTEL_GEN(dev_priv) >= 4) { |
66e3d5c0 | 1611 | I915_WRITE(DPLL_MD(crtc->pipe), |
6e3c9717 | 1612 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1613 | } else { |
1614 | /* The pixel multiplier can only be updated once the | |
1615 | * DPLL is enabled and the clocks are stable. | |
1616 | * | |
1617 | * So write it again. | |
1618 | */ | |
1619 | I915_WRITE(reg, dpll); | |
1620 | } | |
63d7bbe9 JB |
1621 | |
1622 | /* We do this three times for luck */ | |
bb408dd2 VS |
1623 | for (i = 0; i < 3; i++) { |
1624 | I915_WRITE(reg, dpll); | |
1625 | POSTING_READ(reg); | |
1626 | udelay(150); /* wait for warmup */ | |
1627 | } | |
63d7bbe9 JB |
1628 | } |
1629 | ||
1630 | /** | |
50b44a44 | 1631 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1632 | * @dev_priv: i915 private structure |
1633 | * @pipe: pipe PLL to disable | |
1634 | * | |
1635 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1636 | * | |
1637 | * Note! This is for pre-ILK only. | |
1638 | */ | |
1c4e0274 | 1639 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1640 | { |
6315b5d3 | 1641 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1c4e0274 VS |
1642 | enum pipe pipe = crtc->pipe; |
1643 | ||
1644 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
50a0bc90 | 1645 | if (IS_I830(dev_priv) && |
2d84d2b3 | 1646 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) && |
6315b5d3 | 1647 | !intel_num_dvo_pipes(dev_priv)) { |
1c4e0274 VS |
1648 | I915_WRITE(DPLL(PIPE_B), |
1649 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1650 | I915_WRITE(DPLL(PIPE_A), | |
1651 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1652 | } | |
1653 | ||
b6b5d049 | 1654 | /* Don't disable pipe or pipe PLLs if needed */ |
e56134bc | 1655 | if (IS_I830(dev_priv)) |
63d7bbe9 JB |
1656 | return; |
1657 | ||
1658 | /* Make sure the pipe isn't still relying on us */ | |
1659 | assert_pipe_disabled(dev_priv, pipe); | |
1660 | ||
b8afb911 | 1661 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1662 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1663 | } |
1664 | ||
f6071166 JB |
1665 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1666 | { | |
b8afb911 | 1667 | u32 val; |
f6071166 JB |
1668 | |
1669 | /* Make sure the pipe isn't still relying on us */ | |
1670 | assert_pipe_disabled(dev_priv, pipe); | |
1671 | ||
03ed5cbf VS |
1672 | val = DPLL_INTEGRATED_REF_CLK_VLV | |
1673 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
1674 | if (pipe != PIPE_A) | |
1675 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1676 | ||
f6071166 JB |
1677 | I915_WRITE(DPLL(pipe), val); |
1678 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1679 | } |
1680 | ||
1681 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1682 | { | |
d752048d | 1683 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1684 | u32 val; |
1685 | ||
a11b0703 VS |
1686 | /* Make sure the pipe isn't still relying on us */ |
1687 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1688 | |
60bfe44f VS |
1689 | val = DPLL_SSC_REF_CLK_CHV | |
1690 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1691 | if (pipe != PIPE_A) |
1692 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
03ed5cbf | 1693 | |
a11b0703 VS |
1694 | I915_WRITE(DPLL(pipe), val); |
1695 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1696 | |
a580516d | 1697 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1698 | |
1699 | /* Disable 10bit clock to display controller */ | |
1700 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1701 | val &= ~DPIO_DCLKP_EN; | |
1702 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1703 | ||
a580516d | 1704 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1705 | } |
1706 | ||
e4607fcf | 1707 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1708 | struct intel_digital_port *dport, |
1709 | unsigned int expected_mask) | |
89b667f8 JB |
1710 | { |
1711 | u32 port_mask; | |
f0f59a00 | 1712 | i915_reg_t dpll_reg; |
89b667f8 | 1713 | |
e4607fcf CML |
1714 | switch (dport->port) { |
1715 | case PORT_B: | |
89b667f8 | 1716 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1717 | dpll_reg = DPLL(0); |
e4607fcf CML |
1718 | break; |
1719 | case PORT_C: | |
89b667f8 | 1720 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1721 | dpll_reg = DPLL(0); |
9b6de0a1 | 1722 | expected_mask <<= 4; |
00fc31b7 CML |
1723 | break; |
1724 | case PORT_D: | |
1725 | port_mask = DPLL_PORTD_READY_MASK; | |
1726 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1727 | break; |
1728 | default: | |
1729 | BUG(); | |
1730 | } | |
89b667f8 | 1731 | |
370004d3 CW |
1732 | if (intel_wait_for_register(dev_priv, |
1733 | dpll_reg, port_mask, expected_mask, | |
1734 | 1000)) | |
9b6de0a1 VS |
1735 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", |
1736 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1737 | } |
1738 | ||
b8a4f404 PZ |
1739 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1740 | enum pipe pipe) | |
040484af | 1741 | { |
98187836 VS |
1742 | struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv, |
1743 | pipe); | |
f0f59a00 VS |
1744 | i915_reg_t reg; |
1745 | uint32_t val, pipeconf_val; | |
040484af | 1746 | |
040484af | 1747 | /* Make sure PCH DPLL is enabled */ |
8106ddbd | 1748 | assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll); |
040484af JB |
1749 | |
1750 | /* FDI must be feeding us bits for PCH ports */ | |
1751 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1752 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1753 | ||
6e266956 | 1754 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 DV |
1755 | /* Workaround: Set the timing override bit before enabling the |
1756 | * pch transcoder. */ | |
1757 | reg = TRANS_CHICKEN2(pipe); | |
1758 | val = I915_READ(reg); | |
1759 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1760 | I915_WRITE(reg, val); | |
59c859d6 | 1761 | } |
23670b32 | 1762 | |
ab9412ba | 1763 | reg = PCH_TRANSCONF(pipe); |
040484af | 1764 | val = I915_READ(reg); |
5f7f726d | 1765 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c | 1766 | |
2d1fe073 | 1767 | if (HAS_PCH_IBX(dev_priv)) { |
e9bcff5c | 1768 | /* |
c5de7c6f VS |
1769 | * Make the BPC in transcoder be consistent with |
1770 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1771 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1772 | */ |
dfd07d72 | 1773 | val &= ~PIPECONF_BPC_MASK; |
2d84d2b3 | 1774 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI)) |
c5de7c6f VS |
1775 | val |= PIPECONF_8BPC; |
1776 | else | |
1777 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1778 | } |
5f7f726d PZ |
1779 | |
1780 | val &= ~TRANS_INTERLACE_MASK; | |
1781 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
2d1fe073 | 1782 | if (HAS_PCH_IBX(dev_priv) && |
2d84d2b3 | 1783 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1784 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1785 | else | |
1786 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1787 | else |
1788 | val |= TRANS_PROGRESSIVE; | |
1789 | ||
040484af | 1790 | I915_WRITE(reg, val | TRANS_ENABLE); |
650fbd84 CW |
1791 | if (intel_wait_for_register(dev_priv, |
1792 | reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE, | |
1793 | 100)) | |
4bb6f1f3 | 1794 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1795 | } |
1796 | ||
8fb033d7 | 1797 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1798 | enum transcoder cpu_transcoder) |
040484af | 1799 | { |
8fb033d7 | 1800 | u32 val, pipeconf_val; |
8fb033d7 | 1801 | |
8fb033d7 | 1802 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1803 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
a2196033 | 1804 | assert_fdi_rx_enabled(dev_priv, PIPE_A); |
8fb033d7 | 1805 | |
223a6fdf | 1806 | /* Workaround: set timing override bit. */ |
36c0d0cf | 1807 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1808 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1809 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 1810 | |
25f3ef11 | 1811 | val = TRANS_ENABLE; |
937bb610 | 1812 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1813 | |
9a76b1c6 PZ |
1814 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1815 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1816 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1817 | else |
1818 | val |= TRANS_PROGRESSIVE; | |
1819 | ||
ab9412ba | 1820 | I915_WRITE(LPT_TRANSCONF, val); |
d9f96244 CW |
1821 | if (intel_wait_for_register(dev_priv, |
1822 | LPT_TRANSCONF, | |
1823 | TRANS_STATE_ENABLE, | |
1824 | TRANS_STATE_ENABLE, | |
1825 | 100)) | |
937bb610 | 1826 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1827 | } |
1828 | ||
b8a4f404 PZ |
1829 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1830 | enum pipe pipe) | |
040484af | 1831 | { |
f0f59a00 VS |
1832 | i915_reg_t reg; |
1833 | uint32_t val; | |
040484af JB |
1834 | |
1835 | /* FDI relies on the transcoder */ | |
1836 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1837 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1838 | ||
291906f1 JB |
1839 | /* Ports must be off as well */ |
1840 | assert_pch_ports_disabled(dev_priv, pipe); | |
1841 | ||
ab9412ba | 1842 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1843 | val = I915_READ(reg); |
1844 | val &= ~TRANS_ENABLE; | |
1845 | I915_WRITE(reg, val); | |
1846 | /* wait for PCH transcoder off, transcoder state */ | |
a7d04662 CW |
1847 | if (intel_wait_for_register(dev_priv, |
1848 | reg, TRANS_STATE_ENABLE, 0, | |
1849 | 50)) | |
4bb6f1f3 | 1850 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 1851 | |
6e266956 | 1852 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 DV |
1853 | /* Workaround: Clear the timing override chicken bit again. */ |
1854 | reg = TRANS_CHICKEN2(pipe); | |
1855 | val = I915_READ(reg); | |
1856 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1857 | I915_WRITE(reg, val); | |
1858 | } | |
040484af JB |
1859 | } |
1860 | ||
b7076546 | 1861 | void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1862 | { |
8fb033d7 PZ |
1863 | u32 val; |
1864 | ||
ab9412ba | 1865 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1866 | val &= ~TRANS_ENABLE; |
ab9412ba | 1867 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1868 | /* wait for PCH transcoder off, transcoder state */ |
dfdb4749 CW |
1869 | if (intel_wait_for_register(dev_priv, |
1870 | LPT_TRANSCONF, TRANS_STATE_ENABLE, 0, | |
1871 | 50)) | |
8a52fd9f | 1872 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1873 | |
1874 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 1875 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1876 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1877 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
1878 | } |
1879 | ||
a2196033 | 1880 | enum pipe intel_crtc_pch_transcoder(struct intel_crtc *crtc) |
65f2130c VS |
1881 | { |
1882 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1883 | ||
1884 | WARN_ON(!crtc->config->has_pch_encoder); | |
1885 | ||
1886 | if (HAS_PCH_LPT(dev_priv)) | |
a2196033 | 1887 | return PIPE_A; |
65f2130c | 1888 | else |
a2196033 | 1889 | return crtc->pipe; |
65f2130c VS |
1890 | } |
1891 | ||
b24e7179 | 1892 | /** |
309cfea8 | 1893 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1894 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1895 | * |
0372264a | 1896 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1897 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1898 | */ |
e1fdc473 | 1899 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1900 | { |
0372264a | 1901 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1902 | struct drm_i915_private *dev_priv = to_i915(dev); |
0372264a | 1903 | enum pipe pipe = crtc->pipe; |
1a70a728 | 1904 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
f0f59a00 | 1905 | i915_reg_t reg; |
b24e7179 JB |
1906 | u32 val; |
1907 | ||
9e2ee2dd VS |
1908 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
1909 | ||
58c6eaa2 | 1910 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1911 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1912 | assert_sprites_disabled(dev_priv, pipe); |
1913 | ||
b24e7179 JB |
1914 | /* |
1915 | * A pipe without a PLL won't actually be able to drive bits from | |
1916 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1917 | * need the check. | |
1918 | */ | |
09fa8bb9 | 1919 | if (HAS_GMCH_DISPLAY(dev_priv)) { |
d7edc4e5 | 1920 | if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
1921 | assert_dsi_pll_enabled(dev_priv); |
1922 | else | |
1923 | assert_pll_enabled(dev_priv, pipe); | |
09fa8bb9 | 1924 | } else { |
6e3c9717 | 1925 | if (crtc->config->has_pch_encoder) { |
040484af | 1926 | /* if driving the PCH, we need FDI enabled */ |
65f2130c | 1927 | assert_fdi_rx_pll_enabled(dev_priv, |
a2196033 | 1928 | intel_crtc_pch_transcoder(crtc)); |
1a240d4d DV |
1929 | assert_fdi_tx_pll_enabled(dev_priv, |
1930 | (enum pipe) cpu_transcoder); | |
040484af JB |
1931 | } |
1932 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1933 | } | |
b24e7179 | 1934 | |
702e7a56 | 1935 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1936 | val = I915_READ(reg); |
7ad25d48 | 1937 | if (val & PIPECONF_ENABLE) { |
e56134bc VS |
1938 | /* we keep both pipes enabled on 830 */ |
1939 | WARN_ON(!IS_I830(dev_priv)); | |
00d70b15 | 1940 | return; |
7ad25d48 | 1941 | } |
00d70b15 CW |
1942 | |
1943 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 1944 | POSTING_READ(reg); |
b7792d8b VS |
1945 | |
1946 | /* | |
1947 | * Until the pipe starts DSL will read as 0, which would cause | |
1948 | * an apparent vblank timestamp jump, which messes up also the | |
1949 | * frame count when it's derived from the timestamps. So let's | |
1950 | * wait for the pipe to start properly before we call | |
1951 | * drm_crtc_vblank_on() | |
1952 | */ | |
1953 | if (dev->max_vblank_count == 0 && | |
1954 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
1955 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
1956 | } |
1957 | ||
1958 | /** | |
309cfea8 | 1959 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 1960 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 1961 | * |
575f7ab7 VS |
1962 | * Disable the pipe of @crtc, making sure that various hardware |
1963 | * specific requirements are met, if applicable, e.g. plane | |
1964 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
1965 | * |
1966 | * Will wait until the pipe has shut down before returning. | |
1967 | */ | |
575f7ab7 | 1968 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1969 | { |
fac5e23e | 1970 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 1971 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1972 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 1973 | i915_reg_t reg; |
b24e7179 JB |
1974 | u32 val; |
1975 | ||
9e2ee2dd VS |
1976 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
1977 | ||
b24e7179 JB |
1978 | /* |
1979 | * Make sure planes won't keep trying to pump pixels to us, | |
1980 | * or we might hang the display. | |
1981 | */ | |
1982 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 1983 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 1984 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 1985 | |
702e7a56 | 1986 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1987 | val = I915_READ(reg); |
00d70b15 CW |
1988 | if ((val & PIPECONF_ENABLE) == 0) |
1989 | return; | |
1990 | ||
67adc644 VS |
1991 | /* |
1992 | * Double wide has implications for planes | |
1993 | * so best keep it disabled when not needed. | |
1994 | */ | |
6e3c9717 | 1995 | if (crtc->config->double_wide) |
67adc644 VS |
1996 | val &= ~PIPECONF_DOUBLE_WIDE; |
1997 | ||
1998 | /* Don't disable pipe or pipe PLLs if needed */ | |
e56134bc | 1999 | if (!IS_I830(dev_priv)) |
67adc644 VS |
2000 | val &= ~PIPECONF_ENABLE; |
2001 | ||
2002 | I915_WRITE(reg, val); | |
2003 | if ((val & PIPECONF_ENABLE) == 0) | |
2004 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2005 | } |
2006 | ||
832be82f VS |
2007 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
2008 | { | |
2009 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
2010 | } | |
2011 | ||
d88c4afd VS |
2012 | static unsigned int |
2013 | intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane) | |
7b49f948 | 2014 | { |
d88c4afd VS |
2015 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
2016 | unsigned int cpp = fb->format->cpp[plane]; | |
2017 | ||
2018 | switch (fb->modifier) { | |
2f075565 | 2019 | case DRM_FORMAT_MOD_LINEAR: |
7b49f948 VS |
2020 | return cpp; |
2021 | case I915_FORMAT_MOD_X_TILED: | |
2022 | if (IS_GEN2(dev_priv)) | |
2023 | return 128; | |
2024 | else | |
2025 | return 512; | |
2e2adb05 VS |
2026 | case I915_FORMAT_MOD_Y_TILED_CCS: |
2027 | if (plane == 1) | |
2028 | return 128; | |
2029 | /* fall through */ | |
7b49f948 VS |
2030 | case I915_FORMAT_MOD_Y_TILED: |
2031 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2032 | return 128; | |
2033 | else | |
2034 | return 512; | |
2e2adb05 VS |
2035 | case I915_FORMAT_MOD_Yf_TILED_CCS: |
2036 | if (plane == 1) | |
2037 | return 128; | |
2038 | /* fall through */ | |
7b49f948 VS |
2039 | case I915_FORMAT_MOD_Yf_TILED: |
2040 | switch (cpp) { | |
2041 | case 1: | |
2042 | return 64; | |
2043 | case 2: | |
2044 | case 4: | |
2045 | return 128; | |
2046 | case 8: | |
2047 | case 16: | |
2048 | return 256; | |
2049 | default: | |
2050 | MISSING_CASE(cpp); | |
2051 | return cpp; | |
2052 | } | |
2053 | break; | |
2054 | default: | |
d88c4afd | 2055 | MISSING_CASE(fb->modifier); |
7b49f948 VS |
2056 | return cpp; |
2057 | } | |
2058 | } | |
2059 | ||
d88c4afd VS |
2060 | static unsigned int |
2061 | intel_tile_height(const struct drm_framebuffer *fb, int plane) | |
a57ce0b2 | 2062 | { |
2f075565 | 2063 | if (fb->modifier == DRM_FORMAT_MOD_LINEAR) |
832be82f VS |
2064 | return 1; |
2065 | else | |
d88c4afd VS |
2066 | return intel_tile_size(to_i915(fb->dev)) / |
2067 | intel_tile_width_bytes(fb, plane); | |
6761dd31 TU |
2068 | } |
2069 | ||
8d0deca8 | 2070 | /* Return the tile dimensions in pixel units */ |
d88c4afd | 2071 | static void intel_tile_dims(const struct drm_framebuffer *fb, int plane, |
8d0deca8 | 2072 | unsigned int *tile_width, |
d88c4afd | 2073 | unsigned int *tile_height) |
8d0deca8 | 2074 | { |
d88c4afd VS |
2075 | unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane); |
2076 | unsigned int cpp = fb->format->cpp[plane]; | |
8d0deca8 VS |
2077 | |
2078 | *tile_width = tile_width_bytes / cpp; | |
d88c4afd | 2079 | *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes; |
8d0deca8 VS |
2080 | } |
2081 | ||
6761dd31 | 2082 | unsigned int |
d88c4afd VS |
2083 | intel_fb_align_height(const struct drm_framebuffer *fb, |
2084 | int plane, unsigned int height) | |
6761dd31 | 2085 | { |
d88c4afd | 2086 | unsigned int tile_height = intel_tile_height(fb, plane); |
832be82f VS |
2087 | |
2088 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2089 | } |
2090 | ||
1663b9d6 VS |
2091 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
2092 | { | |
2093 | unsigned int size = 0; | |
2094 | int i; | |
2095 | ||
2096 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2097 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2098 | ||
2099 | return size; | |
2100 | } | |
2101 | ||
75c82a53 | 2102 | static void |
3465c580 VS |
2103 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
2104 | const struct drm_framebuffer *fb, | |
2105 | unsigned int rotation) | |
f64b98cd | 2106 | { |
7b92c047 | 2107 | view->type = I915_GGTT_VIEW_NORMAL; |
bd2ef25d | 2108 | if (drm_rotation_90_or_270(rotation)) { |
7b92c047 | 2109 | view->type = I915_GGTT_VIEW_ROTATED; |
8bab1193 | 2110 | view->rotated = to_intel_framebuffer(fb)->rot_info; |
2d7a215f VS |
2111 | } |
2112 | } | |
50470bb0 | 2113 | |
fabac484 VS |
2114 | static unsigned int intel_cursor_alignment(const struct drm_i915_private *dev_priv) |
2115 | { | |
2116 | if (IS_I830(dev_priv)) | |
2117 | return 16 * 1024; | |
2118 | else if (IS_I85X(dev_priv)) | |
2119 | return 256; | |
d9e1551e VS |
2120 | else if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
2121 | return 32; | |
fabac484 VS |
2122 | else |
2123 | return 4 * 1024; | |
2124 | } | |
2125 | ||
603525d7 | 2126 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2127 | { |
2128 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2129 | return 256 * 1024; | |
c0f86832 | 2130 | else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) || |
666a4537 | 2131 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2132 | return 128 * 1024; |
2133 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2134 | return 4 * 1024; | |
2135 | else | |
44c5905e | 2136 | return 0; |
4e9a86b6 VS |
2137 | } |
2138 | ||
d88c4afd VS |
2139 | static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, |
2140 | int plane) | |
603525d7 | 2141 | { |
d88c4afd VS |
2142 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
2143 | ||
b90c1ee1 | 2144 | /* AUX_DIST needs only 4K alignment */ |
2e2adb05 | 2145 | if (plane == 1) |
b90c1ee1 VS |
2146 | return 4096; |
2147 | ||
d88c4afd | 2148 | switch (fb->modifier) { |
2f075565 | 2149 | case DRM_FORMAT_MOD_LINEAR: |
603525d7 VS |
2150 | return intel_linear_alignment(dev_priv); |
2151 | case I915_FORMAT_MOD_X_TILED: | |
d88c4afd | 2152 | if (INTEL_GEN(dev_priv) >= 9) |
603525d7 VS |
2153 | return 256 * 1024; |
2154 | return 0; | |
2e2adb05 VS |
2155 | case I915_FORMAT_MOD_Y_TILED_CCS: |
2156 | case I915_FORMAT_MOD_Yf_TILED_CCS: | |
603525d7 VS |
2157 | case I915_FORMAT_MOD_Y_TILED: |
2158 | case I915_FORMAT_MOD_Yf_TILED: | |
2159 | return 1 * 1024 * 1024; | |
2160 | default: | |
d88c4afd | 2161 | MISSING_CASE(fb->modifier); |
603525d7 VS |
2162 | return 0; |
2163 | } | |
2164 | } | |
2165 | ||
058d88c4 CW |
2166 | struct i915_vma * |
2167 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) | |
6b95a207 | 2168 | { |
850c4cdc | 2169 | struct drm_device *dev = fb->dev; |
fac5e23e | 2170 | struct drm_i915_private *dev_priv = to_i915(dev); |
850c4cdc | 2171 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2172 | struct i915_ggtt_view view; |
058d88c4 | 2173 | struct i915_vma *vma; |
6b95a207 | 2174 | u32 alignment; |
6b95a207 | 2175 | |
ebcdd39e MR |
2176 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2177 | ||
d88c4afd | 2178 | alignment = intel_surf_alignment(fb, 0); |
6b95a207 | 2179 | |
3465c580 | 2180 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2181 | |
693db184 CW |
2182 | /* Note that the w/a also requires 64 PTE of padding following the |
2183 | * bo. We currently fill all unused PTE with the shadow page and so | |
2184 | * we should always have valid PTE following the scanout preventing | |
2185 | * the VT-d warning. | |
2186 | */ | |
48f112fe | 2187 | if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024) |
693db184 CW |
2188 | alignment = 256 * 1024; |
2189 | ||
d6dd6843 PZ |
2190 | /* |
2191 | * Global gtt pte registers are special registers which actually forward | |
2192 | * writes to a chunk of system memory. Which means that there is no risk | |
2193 | * that the register values disappear as soon as we call | |
2194 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2195 | * pin/unpin/fence and not more. | |
2196 | */ | |
2197 | intel_runtime_pm_get(dev_priv); | |
2198 | ||
058d88c4 | 2199 | vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view); |
49ef5294 CW |
2200 | if (IS_ERR(vma)) |
2201 | goto err; | |
6b95a207 | 2202 | |
05a20d09 | 2203 | if (i915_vma_is_map_and_fenceable(vma)) { |
49ef5294 CW |
2204 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
2205 | * fence, whereas 965+ only requires a fence if using | |
2206 | * framebuffer compression. For simplicity, we always, when | |
2207 | * possible, install a fence as the cost is not that onerous. | |
2208 | * | |
2209 | * If we fail to fence the tiled scanout, then either the | |
2210 | * modeset will reject the change (which is highly unlikely as | |
2211 | * the affected systems, all but one, do not have unmappable | |
2212 | * space) or we will not be able to enable full powersaving | |
2213 | * techniques (also likely not to apply due to various limits | |
2214 | * FBC and the like impose on the size of the buffer, which | |
2215 | * presumably we violated anyway with this unmappable buffer). | |
2216 | * Anyway, it is presumably better to stumble onwards with | |
2217 | * something and try to run the system in a "less than optimal" | |
2218 | * mode that matches the user configuration. | |
2219 | */ | |
2220 | if (i915_vma_get_fence(vma) == 0) | |
2221 | i915_vma_pin_fence(vma); | |
9807216f | 2222 | } |
6b95a207 | 2223 | |
be1e3415 | 2224 | i915_vma_get(vma); |
49ef5294 | 2225 | err: |
d6dd6843 | 2226 | intel_runtime_pm_put(dev_priv); |
058d88c4 | 2227 | return vma; |
6b95a207 KH |
2228 | } |
2229 | ||
be1e3415 | 2230 | void intel_unpin_fb_vma(struct i915_vma *vma) |
1690e1eb | 2231 | { |
be1e3415 | 2232 | lockdep_assert_held(&vma->vm->i915->drm.struct_mutex); |
f64b98cd | 2233 | |
49ef5294 | 2234 | i915_vma_unpin_fence(vma); |
058d88c4 | 2235 | i915_gem_object_unpin_from_display_plane(vma); |
be1e3415 | 2236 | i915_vma_put(vma); |
1690e1eb CW |
2237 | } |
2238 | ||
ef78ec94 VS |
2239 | static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane, |
2240 | unsigned int rotation) | |
2241 | { | |
bd2ef25d | 2242 | if (drm_rotation_90_or_270(rotation)) |
ef78ec94 VS |
2243 | return to_intel_framebuffer(fb)->rotated[plane].pitch; |
2244 | else | |
2245 | return fb->pitches[plane]; | |
2246 | } | |
2247 | ||
6687c906 VS |
2248 | /* |
2249 | * Convert the x/y offsets into a linear offset. | |
2250 | * Only valid with 0/180 degree rotation, which is fine since linear | |
2251 | * offset is only used with linear buffers on pre-hsw and tiled buffers | |
2252 | * with gen2/3, and 90/270 degree rotations isn't supported on any of them. | |
2253 | */ | |
2254 | u32 intel_fb_xy_to_linear(int x, int y, | |
2949056c VS |
2255 | const struct intel_plane_state *state, |
2256 | int plane) | |
6687c906 | 2257 | { |
2949056c | 2258 | const struct drm_framebuffer *fb = state->base.fb; |
353c8598 | 2259 | unsigned int cpp = fb->format->cpp[plane]; |
6687c906 VS |
2260 | unsigned int pitch = fb->pitches[plane]; |
2261 | ||
2262 | return y * pitch + x * cpp; | |
2263 | } | |
2264 | ||
2265 | /* | |
2266 | * Add the x/y offsets derived from fb->offsets[] to the user | |
2267 | * specified plane src x/y offsets. The resulting x/y offsets | |
2268 | * specify the start of scanout from the beginning of the gtt mapping. | |
2269 | */ | |
2270 | void intel_add_fb_offsets(int *x, int *y, | |
2949056c VS |
2271 | const struct intel_plane_state *state, |
2272 | int plane) | |
6687c906 VS |
2273 | |
2274 | { | |
2949056c VS |
2275 | const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb); |
2276 | unsigned int rotation = state->base.rotation; | |
6687c906 | 2277 | |
bd2ef25d | 2278 | if (drm_rotation_90_or_270(rotation)) { |
6687c906 VS |
2279 | *x += intel_fb->rotated[plane].x; |
2280 | *y += intel_fb->rotated[plane].y; | |
2281 | } else { | |
2282 | *x += intel_fb->normal[plane].x; | |
2283 | *y += intel_fb->normal[plane].y; | |
2284 | } | |
2285 | } | |
2286 | ||
29cf9491 | 2287 | /* |
29cf9491 VS |
2288 | * Input tile dimensions and pitch must already be |
2289 | * rotated to match x and y, and in pixel units. | |
2290 | */ | |
66a2d927 VS |
2291 | static u32 _intel_adjust_tile_offset(int *x, int *y, |
2292 | unsigned int tile_width, | |
2293 | unsigned int tile_height, | |
2294 | unsigned int tile_size, | |
2295 | unsigned int pitch_tiles, | |
2296 | u32 old_offset, | |
2297 | u32 new_offset) | |
29cf9491 | 2298 | { |
b9b24038 | 2299 | unsigned int pitch_pixels = pitch_tiles * tile_width; |
29cf9491 VS |
2300 | unsigned int tiles; |
2301 | ||
2302 | WARN_ON(old_offset & (tile_size - 1)); | |
2303 | WARN_ON(new_offset & (tile_size - 1)); | |
2304 | WARN_ON(new_offset > old_offset); | |
2305 | ||
2306 | tiles = (old_offset - new_offset) / tile_size; | |
2307 | ||
2308 | *y += tiles / pitch_tiles * tile_height; | |
2309 | *x += tiles % pitch_tiles * tile_width; | |
2310 | ||
b9b24038 VS |
2311 | /* minimize x in case it got needlessly big */ |
2312 | *y += *x / pitch_pixels * tile_height; | |
2313 | *x %= pitch_pixels; | |
2314 | ||
29cf9491 VS |
2315 | return new_offset; |
2316 | } | |
2317 | ||
66a2d927 VS |
2318 | /* |
2319 | * Adjust the tile offset by moving the difference into | |
2320 | * the x/y offsets. | |
2321 | */ | |
2322 | static u32 intel_adjust_tile_offset(int *x, int *y, | |
2323 | const struct intel_plane_state *state, int plane, | |
2324 | u32 old_offset, u32 new_offset) | |
2325 | { | |
2326 | const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev); | |
2327 | const struct drm_framebuffer *fb = state->base.fb; | |
353c8598 | 2328 | unsigned int cpp = fb->format->cpp[plane]; |
66a2d927 VS |
2329 | unsigned int rotation = state->base.rotation; |
2330 | unsigned int pitch = intel_fb_pitch(fb, plane, rotation); | |
2331 | ||
2332 | WARN_ON(new_offset > old_offset); | |
2333 | ||
2f075565 | 2334 | if (fb->modifier != DRM_FORMAT_MOD_LINEAR) { |
66a2d927 VS |
2335 | unsigned int tile_size, tile_width, tile_height; |
2336 | unsigned int pitch_tiles; | |
2337 | ||
2338 | tile_size = intel_tile_size(dev_priv); | |
d88c4afd | 2339 | intel_tile_dims(fb, plane, &tile_width, &tile_height); |
66a2d927 | 2340 | |
bd2ef25d | 2341 | if (drm_rotation_90_or_270(rotation)) { |
66a2d927 VS |
2342 | pitch_tiles = pitch / tile_height; |
2343 | swap(tile_width, tile_height); | |
2344 | } else { | |
2345 | pitch_tiles = pitch / (tile_width * cpp); | |
2346 | } | |
2347 | ||
2348 | _intel_adjust_tile_offset(x, y, tile_width, tile_height, | |
2349 | tile_size, pitch_tiles, | |
2350 | old_offset, new_offset); | |
2351 | } else { | |
2352 | old_offset += *y * pitch + *x * cpp; | |
2353 | ||
2354 | *y = (old_offset - new_offset) / pitch; | |
2355 | *x = ((old_offset - new_offset) - *y * pitch) / cpp; | |
2356 | } | |
2357 | ||
2358 | return new_offset; | |
2359 | } | |
2360 | ||
8d0deca8 VS |
2361 | /* |
2362 | * Computes the linear offset to the base tile and adjusts | |
2363 | * x, y. bytes per pixel is assumed to be a power-of-two. | |
2364 | * | |
2365 | * In the 90/270 rotated case, x and y are assumed | |
2366 | * to be already rotated to match the rotated GTT view, and | |
2367 | * pitch is the tile_height aligned framebuffer height. | |
6687c906 VS |
2368 | * |
2369 | * This function is used when computing the derived information | |
2370 | * under intel_framebuffer, so using any of that information | |
2371 | * here is not allowed. Anything under drm_framebuffer can be | |
2372 | * used. This is why the user has to pass in the pitch since it | |
2373 | * is specified in the rotated orientation. | |
8d0deca8 | 2374 | */ |
6687c906 VS |
2375 | static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv, |
2376 | int *x, int *y, | |
2377 | const struct drm_framebuffer *fb, int plane, | |
2378 | unsigned int pitch, | |
2379 | unsigned int rotation, | |
2380 | u32 alignment) | |
c2c75131 | 2381 | { |
bae781b2 | 2382 | uint64_t fb_modifier = fb->modifier; |
353c8598 | 2383 | unsigned int cpp = fb->format->cpp[plane]; |
6687c906 | 2384 | u32 offset, offset_aligned; |
29cf9491 | 2385 | |
29cf9491 VS |
2386 | if (alignment) |
2387 | alignment--; | |
2388 | ||
2f075565 | 2389 | if (fb_modifier != DRM_FORMAT_MOD_LINEAR) { |
8d0deca8 VS |
2390 | unsigned int tile_size, tile_width, tile_height; |
2391 | unsigned int tile_rows, tiles, pitch_tiles; | |
c2c75131 | 2392 | |
d843310d | 2393 | tile_size = intel_tile_size(dev_priv); |
d88c4afd | 2394 | intel_tile_dims(fb, plane, &tile_width, &tile_height); |
8d0deca8 | 2395 | |
bd2ef25d | 2396 | if (drm_rotation_90_or_270(rotation)) { |
8d0deca8 VS |
2397 | pitch_tiles = pitch / tile_height; |
2398 | swap(tile_width, tile_height); | |
2399 | } else { | |
2400 | pitch_tiles = pitch / (tile_width * cpp); | |
2401 | } | |
d843310d VS |
2402 | |
2403 | tile_rows = *y / tile_height; | |
2404 | *y %= tile_height; | |
c2c75131 | 2405 | |
8d0deca8 VS |
2406 | tiles = *x / tile_width; |
2407 | *x %= tile_width; | |
bc752862 | 2408 | |
29cf9491 VS |
2409 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
2410 | offset_aligned = offset & ~alignment; | |
bc752862 | 2411 | |
66a2d927 VS |
2412 | _intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2413 | tile_size, pitch_tiles, | |
2414 | offset, offset_aligned); | |
29cf9491 | 2415 | } else { |
bc752862 | 2416 | offset = *y * pitch + *x * cpp; |
29cf9491 VS |
2417 | offset_aligned = offset & ~alignment; |
2418 | ||
4e9a86b6 VS |
2419 | *y = (offset & alignment) / pitch; |
2420 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
bc752862 | 2421 | } |
29cf9491 VS |
2422 | |
2423 | return offset_aligned; | |
c2c75131 DV |
2424 | } |
2425 | ||
6687c906 | 2426 | u32 intel_compute_tile_offset(int *x, int *y, |
2949056c VS |
2427 | const struct intel_plane_state *state, |
2428 | int plane) | |
6687c906 | 2429 | { |
1e7b4fd8 VS |
2430 | struct intel_plane *intel_plane = to_intel_plane(state->base.plane); |
2431 | struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev); | |
2949056c VS |
2432 | const struct drm_framebuffer *fb = state->base.fb; |
2433 | unsigned int rotation = state->base.rotation; | |
ef78ec94 | 2434 | int pitch = intel_fb_pitch(fb, plane, rotation); |
1e7b4fd8 VS |
2435 | u32 alignment; |
2436 | ||
2437 | if (intel_plane->id == PLANE_CURSOR) | |
2438 | alignment = intel_cursor_alignment(dev_priv); | |
2439 | else | |
2440 | alignment = intel_surf_alignment(fb, plane); | |
6687c906 VS |
2441 | |
2442 | return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch, | |
2443 | rotation, alignment); | |
2444 | } | |
2445 | ||
2446 | /* Convert the fb->offset[] linear offset into x/y offsets */ | |
2447 | static void intel_fb_offset_to_xy(int *x, int *y, | |
2448 | const struct drm_framebuffer *fb, int plane) | |
2449 | { | |
353c8598 | 2450 | unsigned int cpp = fb->format->cpp[plane]; |
6687c906 VS |
2451 | unsigned int pitch = fb->pitches[plane]; |
2452 | u32 linear_offset = fb->offsets[plane]; | |
2453 | ||
2454 | *y = linear_offset / pitch; | |
2455 | *x = linear_offset % pitch / cpp; | |
2456 | } | |
2457 | ||
72618ebf VS |
2458 | static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier) |
2459 | { | |
2460 | switch (fb_modifier) { | |
2461 | case I915_FORMAT_MOD_X_TILED: | |
2462 | return I915_TILING_X; | |
2463 | case I915_FORMAT_MOD_Y_TILED: | |
2e2adb05 | 2464 | case I915_FORMAT_MOD_Y_TILED_CCS: |
72618ebf VS |
2465 | return I915_TILING_Y; |
2466 | default: | |
2467 | return I915_TILING_NONE; | |
2468 | } | |
2469 | } | |
2470 | ||
bbfb6ce8 VS |
2471 | static const struct drm_format_info ccs_formats[] = { |
2472 | { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, | |
2473 | { .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, | |
2474 | { .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, | |
2475 | { .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2, .cpp = { 4, 1, }, .hsub = 8, .vsub = 16, }, | |
2476 | }; | |
2477 | ||
2478 | static const struct drm_format_info * | |
2479 | lookup_format_info(const struct drm_format_info formats[], | |
2480 | int num_formats, u32 format) | |
2481 | { | |
2482 | int i; | |
2483 | ||
2484 | for (i = 0; i < num_formats; i++) { | |
2485 | if (formats[i].format == format) | |
2486 | return &formats[i]; | |
2487 | } | |
2488 | ||
2489 | return NULL; | |
2490 | } | |
2491 | ||
2492 | static const struct drm_format_info * | |
2493 | intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd) | |
2494 | { | |
2495 | switch (cmd->modifier[0]) { | |
2496 | case I915_FORMAT_MOD_Y_TILED_CCS: | |
2497 | case I915_FORMAT_MOD_Yf_TILED_CCS: | |
2498 | return lookup_format_info(ccs_formats, | |
2499 | ARRAY_SIZE(ccs_formats), | |
2500 | cmd->pixel_format); | |
2501 | default: | |
2502 | return NULL; | |
2503 | } | |
2504 | } | |
2505 | ||
6687c906 VS |
2506 | static int |
2507 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
2508 | struct drm_framebuffer *fb) | |
2509 | { | |
2510 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
2511 | struct intel_rotation_info *rot_info = &intel_fb->rot_info; | |
2512 | u32 gtt_offset_rotated = 0; | |
2513 | unsigned int max_size = 0; | |
bcb0b461 | 2514 | int i, num_planes = fb->format->num_planes; |
6687c906 VS |
2515 | unsigned int tile_size = intel_tile_size(dev_priv); |
2516 | ||
2517 | for (i = 0; i < num_planes; i++) { | |
2518 | unsigned int width, height; | |
2519 | unsigned int cpp, size; | |
2520 | u32 offset; | |
2521 | int x, y; | |
2522 | ||
353c8598 | 2523 | cpp = fb->format->cpp[i]; |
145fcb11 VS |
2524 | width = drm_framebuffer_plane_width(fb->width, fb, i); |
2525 | height = drm_framebuffer_plane_height(fb->height, fb, i); | |
6687c906 VS |
2526 | |
2527 | intel_fb_offset_to_xy(&x, &y, fb, i); | |
2528 | ||
2e2adb05 VS |
2529 | if ((fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || |
2530 | fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) && i == 1) { | |
2531 | int hsub = fb->format->hsub; | |
2532 | int vsub = fb->format->vsub; | |
2533 | int tile_width, tile_height; | |
2534 | int main_x, main_y; | |
2535 | int ccs_x, ccs_y; | |
2536 | ||
2537 | intel_tile_dims(fb, i, &tile_width, &tile_height); | |
2538 | ||
2539 | ccs_x = (x * hsub) % (tile_width * hsub); | |
2540 | ccs_y = (y * vsub) % (tile_height * vsub); | |
2541 | main_x = intel_fb->normal[0].x % (tile_width * hsub); | |
2542 | main_y = intel_fb->normal[0].y % (tile_height * vsub); | |
2543 | ||
2544 | /* | |
2545 | * CCS doesn't have its own x/y offset register, so the intra CCS tile | |
2546 | * x/y offsets must match between CCS and the main surface. | |
2547 | */ | |
2548 | if (main_x != ccs_x || main_y != ccs_y) { | |
2549 | DRM_DEBUG_KMS("Bad CCS x/y (main %d,%d ccs %d,%d) full (main %d,%d ccs %d,%d)\n", | |
2550 | main_x, main_y, | |
2551 | ccs_x, ccs_y, | |
2552 | intel_fb->normal[0].x, | |
2553 | intel_fb->normal[0].y, | |
2554 | x, y); | |
2555 | return -EINVAL; | |
2556 | } | |
2557 | } | |
2558 | ||
60d5f2a4 VS |
2559 | /* |
2560 | * The fence (if used) is aligned to the start of the object | |
2561 | * so having the framebuffer wrap around across the edge of the | |
2562 | * fenced region doesn't really work. We have no API to configure | |
2563 | * the fence start offset within the object (nor could we probably | |
2564 | * on gen2/3). So it's just easier if we just require that the | |
2565 | * fb layout agrees with the fence layout. We already check that the | |
2566 | * fb stride matches the fence stride elsewhere. | |
2567 | */ | |
2568 | if (i915_gem_object_is_tiled(intel_fb->obj) && | |
2569 | (x + width) * cpp > fb->pitches[i]) { | |
144cc143 VS |
2570 | DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n", |
2571 | i, fb->offsets[i]); | |
60d5f2a4 VS |
2572 | return -EINVAL; |
2573 | } | |
2574 | ||
6687c906 VS |
2575 | /* |
2576 | * First pixel of the framebuffer from | |
2577 | * the start of the normal gtt mapping. | |
2578 | */ | |
2579 | intel_fb->normal[i].x = x; | |
2580 | intel_fb->normal[i].y = y; | |
2581 | ||
2582 | offset = _intel_compute_tile_offset(dev_priv, &x, &y, | |
3ca46c0a | 2583 | fb, i, fb->pitches[i], |
c2c446ad | 2584 | DRM_MODE_ROTATE_0, tile_size); |
6687c906 VS |
2585 | offset /= tile_size; |
2586 | ||
2f075565 | 2587 | if (fb->modifier != DRM_FORMAT_MOD_LINEAR) { |
6687c906 VS |
2588 | unsigned int tile_width, tile_height; |
2589 | unsigned int pitch_tiles; | |
2590 | struct drm_rect r; | |
2591 | ||
d88c4afd | 2592 | intel_tile_dims(fb, i, &tile_width, &tile_height); |
6687c906 VS |
2593 | |
2594 | rot_info->plane[i].offset = offset; | |
2595 | rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp); | |
2596 | rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width); | |
2597 | rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height); | |
2598 | ||
2599 | intel_fb->rotated[i].pitch = | |
2600 | rot_info->plane[i].height * tile_height; | |
2601 | ||
2602 | /* how many tiles does this plane need */ | |
2603 | size = rot_info->plane[i].stride * rot_info->plane[i].height; | |
2604 | /* | |
2605 | * If the plane isn't horizontally tile aligned, | |
2606 | * we need one more tile. | |
2607 | */ | |
2608 | if (x != 0) | |
2609 | size++; | |
2610 | ||
2611 | /* rotate the x/y offsets to match the GTT view */ | |
2612 | r.x1 = x; | |
2613 | r.y1 = y; | |
2614 | r.x2 = x + width; | |
2615 | r.y2 = y + height; | |
2616 | drm_rect_rotate(&r, | |
2617 | rot_info->plane[i].width * tile_width, | |
2618 | rot_info->plane[i].height * tile_height, | |
c2c446ad | 2619 | DRM_MODE_ROTATE_270); |
6687c906 VS |
2620 | x = r.x1; |
2621 | y = r.y1; | |
2622 | ||
2623 | /* rotate the tile dimensions to match the GTT view */ | |
2624 | pitch_tiles = intel_fb->rotated[i].pitch / tile_height; | |
2625 | swap(tile_width, tile_height); | |
2626 | ||
2627 | /* | |
2628 | * We only keep the x/y offsets, so push all of the | |
2629 | * gtt offset into the x/y offsets. | |
2630 | */ | |
46a1bd28 ACO |
2631 | _intel_adjust_tile_offset(&x, &y, |
2632 | tile_width, tile_height, | |
2633 | tile_size, pitch_tiles, | |
66a2d927 | 2634 | gtt_offset_rotated * tile_size, 0); |
6687c906 VS |
2635 | |
2636 | gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height; | |
2637 | ||
2638 | /* | |
2639 | * First pixel of the framebuffer from | |
2640 | * the start of the rotated gtt mapping. | |
2641 | */ | |
2642 | intel_fb->rotated[i].x = x; | |
2643 | intel_fb->rotated[i].y = y; | |
2644 | } else { | |
2645 | size = DIV_ROUND_UP((y + height) * fb->pitches[i] + | |
2646 | x * cpp, tile_size); | |
2647 | } | |
2648 | ||
2649 | /* how many tiles in total needed in the bo */ | |
2650 | max_size = max(max_size, offset + size); | |
2651 | } | |
2652 | ||
144cc143 VS |
2653 | if (max_size * tile_size > intel_fb->obj->base.size) { |
2654 | DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n", | |
2655 | max_size * tile_size, intel_fb->obj->base.size); | |
6687c906 VS |
2656 | return -EINVAL; |
2657 | } | |
2658 | ||
2659 | return 0; | |
2660 | } | |
2661 | ||
b35d63fa | 2662 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2663 | { |
2664 | switch (format) { | |
2665 | case DISPPLANE_8BPP: | |
2666 | return DRM_FORMAT_C8; | |
2667 | case DISPPLANE_BGRX555: | |
2668 | return DRM_FORMAT_XRGB1555; | |
2669 | case DISPPLANE_BGRX565: | |
2670 | return DRM_FORMAT_RGB565; | |
2671 | default: | |
2672 | case DISPPLANE_BGRX888: | |
2673 | return DRM_FORMAT_XRGB8888; | |
2674 | case DISPPLANE_RGBX888: | |
2675 | return DRM_FORMAT_XBGR8888; | |
2676 | case DISPPLANE_BGRX101010: | |
2677 | return DRM_FORMAT_XRGB2101010; | |
2678 | case DISPPLANE_RGBX101010: | |
2679 | return DRM_FORMAT_XBGR2101010; | |
2680 | } | |
2681 | } | |
2682 | ||
bc8d7dff DL |
2683 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2684 | { | |
2685 | switch (format) { | |
2686 | case PLANE_CTL_FORMAT_RGB_565: | |
2687 | return DRM_FORMAT_RGB565; | |
2688 | default: | |
2689 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2690 | if (rgb_order) { | |
2691 | if (alpha) | |
2692 | return DRM_FORMAT_ABGR8888; | |
2693 | else | |
2694 | return DRM_FORMAT_XBGR8888; | |
2695 | } else { | |
2696 | if (alpha) | |
2697 | return DRM_FORMAT_ARGB8888; | |
2698 | else | |
2699 | return DRM_FORMAT_XRGB8888; | |
2700 | } | |
2701 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2702 | if (rgb_order) | |
2703 | return DRM_FORMAT_XBGR2101010; | |
2704 | else | |
2705 | return DRM_FORMAT_XRGB2101010; | |
2706 | } | |
2707 | } | |
2708 | ||
5724dbd1 | 2709 | static bool |
f6936e29 DV |
2710 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2711 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2712 | { |
2713 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2714 | struct drm_i915_private *dev_priv = to_i915(dev); |
72e96d64 | 2715 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
46f297fb JB |
2716 | struct drm_i915_gem_object *obj = NULL; |
2717 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2718 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2719 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2720 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2721 | PAGE_SIZE); | |
2722 | ||
2723 | size_aligned -= base_aligned; | |
46f297fb | 2724 | |
ff2652ea CW |
2725 | if (plane_config->size == 0) |
2726 | return false; | |
2727 | ||
3badb49f PZ |
2728 | /* If the FB is too big, just don't use it since fbdev is not very |
2729 | * important and we should probably use that space with FBC or other | |
2730 | * features. */ | |
72e96d64 | 2731 | if (size_aligned * 2 > ggtt->stolen_usable_size) |
3badb49f PZ |
2732 | return false; |
2733 | ||
12c83d99 | 2734 | mutex_lock(&dev->struct_mutex); |
187685cb | 2735 | obj = i915_gem_object_create_stolen_for_preallocated(dev_priv, |
f37b5c2b DV |
2736 | base_aligned, |
2737 | base_aligned, | |
2738 | size_aligned); | |
24dbf51a CW |
2739 | mutex_unlock(&dev->struct_mutex); |
2740 | if (!obj) | |
484b41dd | 2741 | return false; |
46f297fb | 2742 | |
3e510a8e CW |
2743 | if (plane_config->tiling == I915_TILING_X) |
2744 | obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X; | |
46f297fb | 2745 | |
438b74a5 | 2746 | mode_cmd.pixel_format = fb->format->format; |
6bf129df DL |
2747 | mode_cmd.width = fb->width; |
2748 | mode_cmd.height = fb->height; | |
2749 | mode_cmd.pitches[0] = fb->pitches[0]; | |
bae781b2 | 2750 | mode_cmd.modifier[0] = fb->modifier; |
18c5247e | 2751 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; |
46f297fb | 2752 | |
24dbf51a | 2753 | if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) { |
46f297fb JB |
2754 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2755 | goto out_unref_obj; | |
2756 | } | |
12c83d99 | 2757 | |
484b41dd | 2758 | |
f6936e29 | 2759 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2760 | return true; |
46f297fb JB |
2761 | |
2762 | out_unref_obj: | |
f8c417cd | 2763 | i915_gem_object_put(obj); |
484b41dd JB |
2764 | return false; |
2765 | } | |
2766 | ||
e9728bd8 VS |
2767 | static void |
2768 | intel_set_plane_visible(struct intel_crtc_state *crtc_state, | |
2769 | struct intel_plane_state *plane_state, | |
2770 | bool visible) | |
2771 | { | |
2772 | struct intel_plane *plane = to_intel_plane(plane_state->base.plane); | |
2773 | ||
2774 | plane_state->base.visible = visible; | |
2775 | ||
2776 | /* FIXME pre-g4x don't work like this */ | |
2777 | if (visible) { | |
2778 | crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base)); | |
2779 | crtc_state->active_planes |= BIT(plane->id); | |
2780 | } else { | |
2781 | crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base)); | |
2782 | crtc_state->active_planes &= ~BIT(plane->id); | |
2783 | } | |
2784 | ||
2785 | DRM_DEBUG_KMS("%s active planes 0x%x\n", | |
2786 | crtc_state->base.crtc->name, | |
2787 | crtc_state->active_planes); | |
2788 | } | |
2789 | ||
5724dbd1 | 2790 | static void |
f6936e29 DV |
2791 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2792 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2793 | { |
2794 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 2795 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 2796 | struct drm_crtc *c; |
2ff8fde1 | 2797 | struct drm_i915_gem_object *obj; |
88595ac9 | 2798 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2799 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2800 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2801 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2802 | struct intel_plane_state *intel_state = |
2803 | to_intel_plane_state(plane_state); | |
88595ac9 | 2804 | struct drm_framebuffer *fb; |
484b41dd | 2805 | |
2d14030b | 2806 | if (!plane_config->fb) |
484b41dd JB |
2807 | return; |
2808 | ||
f6936e29 | 2809 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2810 | fb = &plane_config->fb->base; |
2811 | goto valid_fb; | |
f55548b5 | 2812 | } |
484b41dd | 2813 | |
2d14030b | 2814 | kfree(plane_config->fb); |
484b41dd JB |
2815 | |
2816 | /* | |
2817 | * Failed to alloc the obj, check to see if we should share | |
2818 | * an fb with another CRTC instead | |
2819 | */ | |
70e1e0ec | 2820 | for_each_crtc(dev, c) { |
be1e3415 | 2821 | struct intel_plane_state *state; |
484b41dd JB |
2822 | |
2823 | if (c == &intel_crtc->base) | |
2824 | continue; | |
2825 | ||
be1e3415 | 2826 | if (!to_intel_crtc(c)->active) |
2ff8fde1 MR |
2827 | continue; |
2828 | ||
be1e3415 CW |
2829 | state = to_intel_plane_state(c->primary->state); |
2830 | if (!state->vma) | |
484b41dd JB |
2831 | continue; |
2832 | ||
be1e3415 CW |
2833 | if (intel_plane_ggtt_offset(state) == plane_config->base) { |
2834 | fb = c->primary->fb; | |
88595ac9 DV |
2835 | drm_framebuffer_reference(fb); |
2836 | goto valid_fb; | |
484b41dd JB |
2837 | } |
2838 | } | |
88595ac9 | 2839 | |
200757f5 MR |
2840 | /* |
2841 | * We've failed to reconstruct the BIOS FB. Current display state | |
2842 | * indicates that the primary plane is visible, but has a NULL FB, | |
2843 | * which will lead to problems later if we don't fix it up. The | |
2844 | * simplest solution is to just disable the primary plane now and | |
2845 | * pretend the BIOS never had it enabled. | |
2846 | */ | |
e9728bd8 VS |
2847 | intel_set_plane_visible(to_intel_crtc_state(crtc_state), |
2848 | to_intel_plane_state(plane_state), | |
2849 | false); | |
2622a081 | 2850 | intel_pre_disable_primary_noatomic(&intel_crtc->base); |
72259536 | 2851 | trace_intel_disable_plane(primary, intel_crtc); |
282dbf9b | 2852 | intel_plane->disable_plane(intel_plane, intel_crtc); |
200757f5 | 2853 | |
88595ac9 DV |
2854 | return; |
2855 | ||
2856 | valid_fb: | |
be1e3415 CW |
2857 | mutex_lock(&dev->struct_mutex); |
2858 | intel_state->vma = | |
2859 | intel_pin_and_fence_fb_obj(fb, primary->state->rotation); | |
2860 | mutex_unlock(&dev->struct_mutex); | |
2861 | if (IS_ERR(intel_state->vma)) { | |
2862 | DRM_ERROR("failed to pin boot fb on pipe %d: %li\n", | |
2863 | intel_crtc->pipe, PTR_ERR(intel_state->vma)); | |
2864 | ||
2865 | intel_state->vma = NULL; | |
2866 | drm_framebuffer_unreference(fb); | |
2867 | return; | |
2868 | } | |
2869 | ||
f44e2659 VS |
2870 | plane_state->src_x = 0; |
2871 | plane_state->src_y = 0; | |
be5651f2 ML |
2872 | plane_state->src_w = fb->width << 16; |
2873 | plane_state->src_h = fb->height << 16; | |
2874 | ||
f44e2659 VS |
2875 | plane_state->crtc_x = 0; |
2876 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2877 | plane_state->crtc_w = fb->width; |
2878 | plane_state->crtc_h = fb->height; | |
2879 | ||
1638d30c RC |
2880 | intel_state->base.src = drm_plane_state_src(plane_state); |
2881 | intel_state->base.dst = drm_plane_state_dest(plane_state); | |
0a8d8a86 | 2882 | |
88595ac9 | 2883 | obj = intel_fb_obj(fb); |
3e510a8e | 2884 | if (i915_gem_object_is_tiled(obj)) |
88595ac9 DV |
2885 | dev_priv->preserve_bios_swizzle = true; |
2886 | ||
be5651f2 ML |
2887 | drm_framebuffer_reference(fb); |
2888 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2889 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
e9728bd8 VS |
2890 | |
2891 | intel_set_plane_visible(to_intel_crtc_state(crtc_state), | |
2892 | to_intel_plane_state(plane_state), | |
2893 | true); | |
2894 | ||
faf5bf0a CW |
2895 | atomic_or(to_intel_plane(primary)->frontbuffer_bit, |
2896 | &obj->frontbuffer_bits); | |
46f297fb JB |
2897 | } |
2898 | ||
b63a16f6 VS |
2899 | static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane, |
2900 | unsigned int rotation) | |
2901 | { | |
353c8598 | 2902 | int cpp = fb->format->cpp[plane]; |
b63a16f6 | 2903 | |
bae781b2 | 2904 | switch (fb->modifier) { |
2f075565 | 2905 | case DRM_FORMAT_MOD_LINEAR: |
b63a16f6 VS |
2906 | case I915_FORMAT_MOD_X_TILED: |
2907 | switch (cpp) { | |
2908 | case 8: | |
2909 | return 4096; | |
2910 | case 4: | |
2911 | case 2: | |
2912 | case 1: | |
2913 | return 8192; | |
2914 | default: | |
2915 | MISSING_CASE(cpp); | |
2916 | break; | |
2917 | } | |
2918 | break; | |
2e2adb05 VS |
2919 | case I915_FORMAT_MOD_Y_TILED_CCS: |
2920 | case I915_FORMAT_MOD_Yf_TILED_CCS: | |
2921 | /* FIXME AUX plane? */ | |
b63a16f6 VS |
2922 | case I915_FORMAT_MOD_Y_TILED: |
2923 | case I915_FORMAT_MOD_Yf_TILED: | |
2924 | switch (cpp) { | |
2925 | case 8: | |
2926 | return 2048; | |
2927 | case 4: | |
2928 | return 4096; | |
2929 | case 2: | |
2930 | case 1: | |
2931 | return 8192; | |
2932 | default: | |
2933 | MISSING_CASE(cpp); | |
2934 | break; | |
2935 | } | |
2936 | break; | |
2937 | default: | |
bae781b2 | 2938 | MISSING_CASE(fb->modifier); |
b63a16f6 VS |
2939 | } |
2940 | ||
2941 | return 2048; | |
2942 | } | |
2943 | ||
2e2adb05 VS |
2944 | static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state, |
2945 | int main_x, int main_y, u32 main_offset) | |
2946 | { | |
2947 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2948 | int hsub = fb->format->hsub; | |
2949 | int vsub = fb->format->vsub; | |
2950 | int aux_x = plane_state->aux.x; | |
2951 | int aux_y = plane_state->aux.y; | |
2952 | u32 aux_offset = plane_state->aux.offset; | |
2953 | u32 alignment = intel_surf_alignment(fb, 1); | |
2954 | ||
2955 | while (aux_offset >= main_offset && aux_y <= main_y) { | |
2956 | int x, y; | |
2957 | ||
2958 | if (aux_x == main_x && aux_y == main_y) | |
2959 | break; | |
2960 | ||
2961 | if (aux_offset == 0) | |
2962 | break; | |
2963 | ||
2964 | x = aux_x / hsub; | |
2965 | y = aux_y / vsub; | |
2966 | aux_offset = intel_adjust_tile_offset(&x, &y, plane_state, 1, | |
2967 | aux_offset, aux_offset - alignment); | |
2968 | aux_x = x * hsub + aux_x % hsub; | |
2969 | aux_y = y * vsub + aux_y % vsub; | |
2970 | } | |
2971 | ||
2972 | if (aux_x != main_x || aux_y != main_y) | |
2973 | return false; | |
2974 | ||
2975 | plane_state->aux.offset = aux_offset; | |
2976 | plane_state->aux.x = aux_x; | |
2977 | plane_state->aux.y = aux_y; | |
2978 | ||
2979 | return true; | |
2980 | } | |
2981 | ||
b63a16f6 VS |
2982 | static int skl_check_main_surface(struct intel_plane_state *plane_state) |
2983 | { | |
b63a16f6 VS |
2984 | const struct drm_framebuffer *fb = plane_state->base.fb; |
2985 | unsigned int rotation = plane_state->base.rotation; | |
cc926387 DV |
2986 | int x = plane_state->base.src.x1 >> 16; |
2987 | int y = plane_state->base.src.y1 >> 16; | |
2988 | int w = drm_rect_width(&plane_state->base.src) >> 16; | |
2989 | int h = drm_rect_height(&plane_state->base.src) >> 16; | |
b63a16f6 VS |
2990 | int max_width = skl_max_plane_width(fb, 0, rotation); |
2991 | int max_height = 4096; | |
8d970654 | 2992 | u32 alignment, offset, aux_offset = plane_state->aux.offset; |
b63a16f6 VS |
2993 | |
2994 | if (w > max_width || h > max_height) { | |
2995 | DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n", | |
2996 | w, h, max_width, max_height); | |
2997 | return -EINVAL; | |
2998 | } | |
2999 | ||
3000 | intel_add_fb_offsets(&x, &y, plane_state, 0); | |
3001 | offset = intel_compute_tile_offset(&x, &y, plane_state, 0); | |
d88c4afd | 3002 | alignment = intel_surf_alignment(fb, 0); |
b63a16f6 | 3003 | |
8d970654 VS |
3004 | /* |
3005 | * AUX surface offset is specified as the distance from the | |
3006 | * main surface offset, and it must be non-negative. Make | |
3007 | * sure that is what we will get. | |
3008 | */ | |
3009 | if (offset > aux_offset) | |
3010 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
3011 | offset, aux_offset & ~(alignment - 1)); | |
3012 | ||
b63a16f6 VS |
3013 | /* |
3014 | * When using an X-tiled surface, the plane blows up | |
3015 | * if the x offset + width exceed the stride. | |
3016 | * | |
3017 | * TODO: linear and Y-tiled seem fine, Yf untested, | |
3018 | */ | |
bae781b2 | 3019 | if (fb->modifier == I915_FORMAT_MOD_X_TILED) { |
353c8598 | 3020 | int cpp = fb->format->cpp[0]; |
b63a16f6 VS |
3021 | |
3022 | while ((x + w) * cpp > fb->pitches[0]) { | |
3023 | if (offset == 0) { | |
2e2adb05 | 3024 | DRM_DEBUG_KMS("Unable to find suitable display surface offset due to X-tiling\n"); |
b63a16f6 VS |
3025 | return -EINVAL; |
3026 | } | |
3027 | ||
3028 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
3029 | offset, offset - alignment); | |
3030 | } | |
3031 | } | |
3032 | ||
2e2adb05 VS |
3033 | /* |
3034 | * CCS AUX surface doesn't have its own x/y offsets, we must make sure | |
3035 | * they match with the main surface x/y offsets. | |
3036 | */ | |
3037 | if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || | |
3038 | fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) { | |
3039 | while (!skl_check_main_ccs_coordinates(plane_state, x, y, offset)) { | |
3040 | if (offset == 0) | |
3041 | break; | |
3042 | ||
3043 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
3044 | offset, offset - alignment); | |
3045 | } | |
3046 | ||
3047 | if (x != plane_state->aux.x || y != plane_state->aux.y) { | |
3048 | DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n"); | |
3049 | return -EINVAL; | |
3050 | } | |
3051 | } | |
3052 | ||
b63a16f6 VS |
3053 | plane_state->main.offset = offset; |
3054 | plane_state->main.x = x; | |
3055 | plane_state->main.y = y; | |
3056 | ||
3057 | return 0; | |
3058 | } | |
3059 | ||
8d970654 VS |
3060 | static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) |
3061 | { | |
3062 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3063 | unsigned int rotation = plane_state->base.rotation; | |
3064 | int max_width = skl_max_plane_width(fb, 1, rotation); | |
3065 | int max_height = 4096; | |
cc926387 DV |
3066 | int x = plane_state->base.src.x1 >> 17; |
3067 | int y = plane_state->base.src.y1 >> 17; | |
3068 | int w = drm_rect_width(&plane_state->base.src) >> 17; | |
3069 | int h = drm_rect_height(&plane_state->base.src) >> 17; | |
8d970654 VS |
3070 | u32 offset; |
3071 | ||
3072 | intel_add_fb_offsets(&x, &y, plane_state, 1); | |
3073 | offset = intel_compute_tile_offset(&x, &y, plane_state, 1); | |
3074 | ||
3075 | /* FIXME not quite sure how/if these apply to the chroma plane */ | |
3076 | if (w > max_width || h > max_height) { | |
3077 | DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n", | |
3078 | w, h, max_width, max_height); | |
3079 | return -EINVAL; | |
3080 | } | |
3081 | ||
3082 | plane_state->aux.offset = offset; | |
3083 | plane_state->aux.x = x; | |
3084 | plane_state->aux.y = y; | |
3085 | ||
3086 | return 0; | |
3087 | } | |
3088 | ||
2e2adb05 VS |
3089 | static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state) |
3090 | { | |
3091 | struct intel_plane *plane = to_intel_plane(plane_state->base.plane); | |
3092 | struct intel_crtc *crtc = to_intel_crtc(plane_state->base.crtc); | |
3093 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3094 | int src_x = plane_state->base.src.x1 >> 16; | |
3095 | int src_y = plane_state->base.src.y1 >> 16; | |
3096 | int hsub = fb->format->hsub; | |
3097 | int vsub = fb->format->vsub; | |
3098 | int x = src_x / hsub; | |
3099 | int y = src_y / vsub; | |
3100 | u32 offset; | |
3101 | ||
3102 | switch (plane->id) { | |
3103 | case PLANE_PRIMARY: | |
3104 | case PLANE_SPRITE0: | |
3105 | break; | |
3106 | default: | |
3107 | DRM_DEBUG_KMS("RC support only on plane 1 and 2\n"); | |
3108 | return -EINVAL; | |
3109 | } | |
3110 | ||
3111 | if (crtc->pipe == PIPE_C) { | |
3112 | DRM_DEBUG_KMS("No RC support on pipe C\n"); | |
3113 | return -EINVAL; | |
3114 | } | |
3115 | ||
3116 | if (plane_state->base.rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180)) { | |
3117 | DRM_DEBUG_KMS("RC support only with 0/180 degree rotation %x\n", | |
3118 | plane_state->base.rotation); | |
3119 | return -EINVAL; | |
3120 | } | |
3121 | ||
3122 | intel_add_fb_offsets(&x, &y, plane_state, 1); | |
3123 | offset = intel_compute_tile_offset(&x, &y, plane_state, 1); | |
3124 | ||
3125 | plane_state->aux.offset = offset; | |
3126 | plane_state->aux.x = x * hsub + src_x % hsub; | |
3127 | plane_state->aux.y = y * vsub + src_y % vsub; | |
3128 | ||
3129 | return 0; | |
3130 | } | |
3131 | ||
b63a16f6 VS |
3132 | int skl_check_plane_surface(struct intel_plane_state *plane_state) |
3133 | { | |
3134 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3135 | unsigned int rotation = plane_state->base.rotation; | |
3136 | int ret; | |
3137 | ||
a5e4c7d0 VS |
3138 | if (!plane_state->base.visible) |
3139 | return 0; | |
3140 | ||
b63a16f6 | 3141 | /* Rotate src coordinates to match rotated GTT view */ |
bd2ef25d | 3142 | if (drm_rotation_90_or_270(rotation)) |
cc926387 | 3143 | drm_rect_rotate(&plane_state->base.src, |
da064b47 | 3144 | fb->width << 16, fb->height << 16, |
c2c446ad | 3145 | DRM_MODE_ROTATE_270); |
b63a16f6 | 3146 | |
8d970654 VS |
3147 | /* |
3148 | * Handle the AUX surface first since | |
3149 | * the main surface setup depends on it. | |
3150 | */ | |
438b74a5 | 3151 | if (fb->format->format == DRM_FORMAT_NV12) { |
8d970654 VS |
3152 | ret = skl_check_nv12_aux_surface(plane_state); |
3153 | if (ret) | |
3154 | return ret; | |
2e2adb05 VS |
3155 | } else if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || |
3156 | fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS) { | |
3157 | ret = skl_check_ccs_aux_surface(plane_state); | |
3158 | if (ret) | |
3159 | return ret; | |
8d970654 VS |
3160 | } else { |
3161 | plane_state->aux.offset = ~0xfff; | |
3162 | plane_state->aux.x = 0; | |
3163 | plane_state->aux.y = 0; | |
3164 | } | |
3165 | ||
b63a16f6 VS |
3166 | ret = skl_check_main_surface(plane_state); |
3167 | if (ret) | |
3168 | return ret; | |
3169 | ||
3170 | return 0; | |
3171 | } | |
3172 | ||
7145f60a VS |
3173 | static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state, |
3174 | const struct intel_plane_state *plane_state) | |
81255565 | 3175 | { |
7145f60a VS |
3176 | struct drm_i915_private *dev_priv = |
3177 | to_i915(plane_state->base.plane->dev); | |
3178 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
3179 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
8d0deca8 | 3180 | unsigned int rotation = plane_state->base.rotation; |
7145f60a | 3181 | u32 dspcntr; |
c9ba6fad | 3182 | |
7145f60a | 3183 | dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE; |
f45651ba | 3184 | |
6a4407a6 VS |
3185 | if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) || |
3186 | IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) | |
7145f60a | 3187 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
f45651ba | 3188 | |
6a4407a6 VS |
3189 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
3190 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
f45651ba | 3191 | |
d509e28b VS |
3192 | if (INTEL_GEN(dev_priv) < 4) |
3193 | dspcntr |= DISPPLANE_SEL_PIPE(crtc->pipe); | |
81255565 | 3194 | |
438b74a5 | 3195 | switch (fb->format->format) { |
57779d06 | 3196 | case DRM_FORMAT_C8: |
81255565 JB |
3197 | dspcntr |= DISPPLANE_8BPP; |
3198 | break; | |
57779d06 | 3199 | case DRM_FORMAT_XRGB1555: |
57779d06 | 3200 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 3201 | break; |
57779d06 VS |
3202 | case DRM_FORMAT_RGB565: |
3203 | dspcntr |= DISPPLANE_BGRX565; | |
3204 | break; | |
3205 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
3206 | dspcntr |= DISPPLANE_BGRX888; |
3207 | break; | |
3208 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
3209 | dspcntr |= DISPPLANE_RGBX888; |
3210 | break; | |
3211 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
3212 | dspcntr |= DISPPLANE_BGRX101010; |
3213 | break; | |
3214 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 3215 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
3216 | break; |
3217 | default: | |
7145f60a VS |
3218 | MISSING_CASE(fb->format->format); |
3219 | return 0; | |
81255565 | 3220 | } |
57779d06 | 3221 | |
72618ebf | 3222 | if (INTEL_GEN(dev_priv) >= 4 && |
bae781b2 | 3223 | fb->modifier == I915_FORMAT_MOD_X_TILED) |
f45651ba | 3224 | dspcntr |= DISPPLANE_TILED; |
81255565 | 3225 | |
c2c446ad | 3226 | if (rotation & DRM_MODE_ROTATE_180) |
df0cd455 VS |
3227 | dspcntr |= DISPPLANE_ROTATE_180; |
3228 | ||
c2c446ad | 3229 | if (rotation & DRM_MODE_REFLECT_X) |
4ea7be2b VS |
3230 | dspcntr |= DISPPLANE_MIRROR; |
3231 | ||
7145f60a VS |
3232 | return dspcntr; |
3233 | } | |
de1aa629 | 3234 | |
f9407ae1 | 3235 | int i9xx_check_plane_surface(struct intel_plane_state *plane_state) |
5b7fcc44 VS |
3236 | { |
3237 | struct drm_i915_private *dev_priv = | |
3238 | to_i915(plane_state->base.plane->dev); | |
3239 | int src_x = plane_state->base.src.x1 >> 16; | |
3240 | int src_y = plane_state->base.src.y1 >> 16; | |
3241 | u32 offset; | |
81255565 | 3242 | |
5b7fcc44 | 3243 | intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); |
e506a0c6 | 3244 | |
5b7fcc44 VS |
3245 | if (INTEL_GEN(dev_priv) >= 4) |
3246 | offset = intel_compute_tile_offset(&src_x, &src_y, | |
3247 | plane_state, 0); | |
3248 | else | |
3249 | offset = 0; | |
3250 | ||
3251 | /* HSW/BDW do this automagically in hardware */ | |
3252 | if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) { | |
3253 | unsigned int rotation = plane_state->base.rotation; | |
3254 | int src_w = drm_rect_width(&plane_state->base.src) >> 16; | |
3255 | int src_h = drm_rect_height(&plane_state->base.src) >> 16; | |
3256 | ||
c2c446ad | 3257 | if (rotation & DRM_MODE_ROTATE_180) { |
5b7fcc44 VS |
3258 | src_x += src_w - 1; |
3259 | src_y += src_h - 1; | |
c2c446ad | 3260 | } else if (rotation & DRM_MODE_REFLECT_X) { |
5b7fcc44 VS |
3261 | src_x += src_w - 1; |
3262 | } | |
48404c1e SJ |
3263 | } |
3264 | ||
5b7fcc44 VS |
3265 | plane_state->main.offset = offset; |
3266 | plane_state->main.x = src_x; | |
3267 | plane_state->main.y = src_y; | |
3268 | ||
3269 | return 0; | |
3270 | } | |
3271 | ||
282dbf9b | 3272 | static void i9xx_update_primary_plane(struct intel_plane *primary, |
7145f60a VS |
3273 | const struct intel_crtc_state *crtc_state, |
3274 | const struct intel_plane_state *plane_state) | |
3275 | { | |
282dbf9b VS |
3276 | struct drm_i915_private *dev_priv = to_i915(primary->base.dev); |
3277 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
3278 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3279 | enum plane plane = primary->plane; | |
7145f60a | 3280 | u32 linear_offset; |
a0864d59 | 3281 | u32 dspcntr = plane_state->ctl; |
7145f60a | 3282 | i915_reg_t reg = DSPCNTR(plane); |
5b7fcc44 VS |
3283 | int x = plane_state->main.x; |
3284 | int y = plane_state->main.y; | |
7145f60a VS |
3285 | unsigned long irqflags; |
3286 | ||
2949056c | 3287 | linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); |
6687c906 | 3288 | |
5b7fcc44 | 3289 | if (INTEL_GEN(dev_priv) >= 4) |
282dbf9b | 3290 | crtc->dspaddr_offset = plane_state->main.offset; |
5b7fcc44 | 3291 | else |
282dbf9b | 3292 | crtc->dspaddr_offset = linear_offset; |
6687c906 | 3293 | |
282dbf9b VS |
3294 | crtc->adjusted_x = x; |
3295 | crtc->adjusted_y = y; | |
2db3366b | 3296 | |
dd584fc0 VS |
3297 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
3298 | ||
78587de2 VS |
3299 | if (INTEL_GEN(dev_priv) < 4) { |
3300 | /* pipesrc and dspsize control the size that is scaled from, | |
3301 | * which should always be the user's requested size. | |
3302 | */ | |
dd584fc0 VS |
3303 | I915_WRITE_FW(DSPSIZE(plane), |
3304 | ((crtc_state->pipe_src_h - 1) << 16) | | |
3305 | (crtc_state->pipe_src_w - 1)); | |
3306 | I915_WRITE_FW(DSPPOS(plane), 0); | |
78587de2 | 3307 | } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) { |
dd584fc0 VS |
3308 | I915_WRITE_FW(PRIMSIZE(plane), |
3309 | ((crtc_state->pipe_src_h - 1) << 16) | | |
3310 | (crtc_state->pipe_src_w - 1)); | |
3311 | I915_WRITE_FW(PRIMPOS(plane), 0); | |
3312 | I915_WRITE_FW(PRIMCNSTALPHA(plane), 0); | |
78587de2 VS |
3313 | } |
3314 | ||
dd584fc0 | 3315 | I915_WRITE_FW(reg, dspcntr); |
48404c1e | 3316 | |
dd584fc0 | 3317 | I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]); |
3ba35e53 VS |
3318 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3319 | I915_WRITE_FW(DSPSURF(plane), | |
3320 | intel_plane_ggtt_offset(plane_state) + | |
282dbf9b | 3321 | crtc->dspaddr_offset); |
3ba35e53 VS |
3322 | I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x); |
3323 | } else if (INTEL_GEN(dev_priv) >= 4) { | |
dd584fc0 VS |
3324 | I915_WRITE_FW(DSPSURF(plane), |
3325 | intel_plane_ggtt_offset(plane_state) + | |
282dbf9b | 3326 | crtc->dspaddr_offset); |
dd584fc0 VS |
3327 | I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x); |
3328 | I915_WRITE_FW(DSPLINOFF(plane), linear_offset); | |
bfb81049 | 3329 | } else { |
dd584fc0 VS |
3330 | I915_WRITE_FW(DSPADDR(plane), |
3331 | intel_plane_ggtt_offset(plane_state) + | |
282dbf9b | 3332 | crtc->dspaddr_offset); |
bfb81049 | 3333 | } |
dd584fc0 VS |
3334 | POSTING_READ_FW(reg); |
3335 | ||
3336 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
17638cd6 JB |
3337 | } |
3338 | ||
282dbf9b VS |
3339 | static void i9xx_disable_primary_plane(struct intel_plane *primary, |
3340 | struct intel_crtc *crtc) | |
17638cd6 | 3341 | { |
282dbf9b VS |
3342 | struct drm_i915_private *dev_priv = to_i915(primary->base.dev); |
3343 | enum plane plane = primary->plane; | |
dd584fc0 VS |
3344 | unsigned long irqflags; |
3345 | ||
3346 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
f45651ba | 3347 | |
dd584fc0 | 3348 | I915_WRITE_FW(DSPCNTR(plane), 0); |
a8d201af | 3349 | if (INTEL_INFO(dev_priv)->gen >= 4) |
dd584fc0 | 3350 | I915_WRITE_FW(DSPSURF(plane), 0); |
a8d201af | 3351 | else |
dd584fc0 VS |
3352 | I915_WRITE_FW(DSPADDR(plane), 0); |
3353 | POSTING_READ_FW(DSPCNTR(plane)); | |
3354 | ||
3355 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
a8d201af | 3356 | } |
c9ba6fad | 3357 | |
d88c4afd VS |
3358 | static u32 |
3359 | intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane) | |
b321803d | 3360 | { |
2f075565 | 3361 | if (fb->modifier == DRM_FORMAT_MOD_LINEAR) |
b321803d | 3362 | return 64; |
d88c4afd VS |
3363 | else |
3364 | return intel_tile_width_bytes(fb, plane); | |
b321803d DL |
3365 | } |
3366 | ||
e435d6e5 ML |
3367 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
3368 | { | |
3369 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 3370 | struct drm_i915_private *dev_priv = to_i915(dev); |
e435d6e5 ML |
3371 | |
3372 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
3373 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
3374 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
3375 | } |
3376 | ||
a1b2278e CK |
3377 | /* |
3378 | * This function detaches (aka. unbinds) unused scalers in hardware | |
3379 | */ | |
0583236e | 3380 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 3381 | { |
a1b2278e CK |
3382 | struct intel_crtc_scaler_state *scaler_state; |
3383 | int i; | |
3384 | ||
a1b2278e CK |
3385 | scaler_state = &intel_crtc->config->scaler_state; |
3386 | ||
3387 | /* loop through and disable scalers that aren't in use */ | |
3388 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
3389 | if (!scaler_state->scalers[i].in_use) |
3390 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
3391 | } |
3392 | } | |
3393 | ||
d2196774 VS |
3394 | u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane, |
3395 | unsigned int rotation) | |
3396 | { | |
1b500535 VS |
3397 | u32 stride; |
3398 | ||
3399 | if (plane >= fb->format->num_planes) | |
3400 | return 0; | |
3401 | ||
3402 | stride = intel_fb_pitch(fb, plane, rotation); | |
d2196774 VS |
3403 | |
3404 | /* | |
3405 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
3406 | * linear buffers or in number of tiles for tiled buffers. | |
3407 | */ | |
d88c4afd VS |
3408 | if (drm_rotation_90_or_270(rotation)) |
3409 | stride /= intel_tile_height(fb, plane); | |
3410 | else | |
3411 | stride /= intel_fb_stride_alignment(fb, plane); | |
d2196774 VS |
3412 | |
3413 | return stride; | |
3414 | } | |
3415 | ||
2e881264 | 3416 | static u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 3417 | { |
6156a456 | 3418 | switch (pixel_format) { |
d161cf7a | 3419 | case DRM_FORMAT_C8: |
c34ce3d1 | 3420 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 3421 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 3422 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 3423 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 3424 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 3425 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 3426 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
3427 | /* |
3428 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
3429 | * to be already pre-multiplied. We need to add a knob (or a different | |
3430 | * DRM_FORMAT) for user-space to configure that. | |
3431 | */ | |
f75fb42a | 3432 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 3433 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 3434 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 3435 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 3436 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 3437 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 3438 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 3439 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 3440 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 3441 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 3442 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 3443 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 3444 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 3445 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 3446 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 3447 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 3448 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 3449 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 3450 | default: |
4249eeef | 3451 | MISSING_CASE(pixel_format); |
70d21f0e | 3452 | } |
8cfcba41 | 3453 | |
c34ce3d1 | 3454 | return 0; |
6156a456 | 3455 | } |
70d21f0e | 3456 | |
2e881264 | 3457 | static u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
6156a456 | 3458 | { |
6156a456 | 3459 | switch (fb_modifier) { |
2f075565 | 3460 | case DRM_FORMAT_MOD_LINEAR: |
70d21f0e | 3461 | break; |
30af77c4 | 3462 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 3463 | return PLANE_CTL_TILED_X; |
b321803d | 3464 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3465 | return PLANE_CTL_TILED_Y; |
2e2adb05 VS |
3466 | case I915_FORMAT_MOD_Y_TILED_CCS: |
3467 | return PLANE_CTL_TILED_Y | PLANE_CTL_DECOMPRESSION_ENABLE; | |
b321803d | 3468 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3469 | return PLANE_CTL_TILED_YF; |
2e2adb05 VS |
3470 | case I915_FORMAT_MOD_Yf_TILED_CCS: |
3471 | return PLANE_CTL_TILED_YF | PLANE_CTL_DECOMPRESSION_ENABLE; | |
70d21f0e | 3472 | default: |
6156a456 | 3473 | MISSING_CASE(fb_modifier); |
70d21f0e | 3474 | } |
8cfcba41 | 3475 | |
c34ce3d1 | 3476 | return 0; |
6156a456 | 3477 | } |
70d21f0e | 3478 | |
2e881264 | 3479 | static u32 skl_plane_ctl_rotation(unsigned int rotation) |
6156a456 | 3480 | { |
3b7a5119 | 3481 | switch (rotation) { |
c2c446ad | 3482 | case DRM_MODE_ROTATE_0: |
6156a456 | 3483 | break; |
1e8df167 | 3484 | /* |
c2c446ad | 3485 | * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr |
1e8df167 SJ |
3486 | * while i915 HW rotation is clockwise, thats why this swapping. |
3487 | */ | |
c2c446ad | 3488 | case DRM_MODE_ROTATE_90: |
1e8df167 | 3489 | return PLANE_CTL_ROTATE_270; |
c2c446ad | 3490 | case DRM_MODE_ROTATE_180: |
c34ce3d1 | 3491 | return PLANE_CTL_ROTATE_180; |
c2c446ad | 3492 | case DRM_MODE_ROTATE_270: |
1e8df167 | 3493 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3494 | default: |
3495 | MISSING_CASE(rotation); | |
3496 | } | |
3497 | ||
c34ce3d1 | 3498 | return 0; |
6156a456 CK |
3499 | } |
3500 | ||
2e881264 VS |
3501 | u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state, |
3502 | const struct intel_plane_state *plane_state) | |
46f788ba VS |
3503 | { |
3504 | struct drm_i915_private *dev_priv = | |
3505 | to_i915(plane_state->base.plane->dev); | |
3506 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3507 | unsigned int rotation = plane_state->base.rotation; | |
2e881264 | 3508 | const struct drm_intel_sprite_colorkey *key = &plane_state->ckey; |
46f788ba VS |
3509 | u32 plane_ctl; |
3510 | ||
3511 | plane_ctl = PLANE_CTL_ENABLE; | |
3512 | ||
6602be0e | 3513 | if (!IS_GEMINILAKE(dev_priv) && !IS_CANNONLAKE(dev_priv)) { |
46f788ba VS |
3514 | plane_ctl |= |
3515 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3516 | PLANE_CTL_PIPE_CSC_ENABLE | | |
3517 | PLANE_CTL_PLANE_GAMMA_DISABLE; | |
3518 | } | |
3519 | ||
3520 | plane_ctl |= skl_plane_ctl_format(fb->format->format); | |
3521 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier); | |
3522 | plane_ctl |= skl_plane_ctl_rotation(rotation); | |
3523 | ||
2e881264 VS |
3524 | if (key->flags & I915_SET_COLORKEY_DESTINATION) |
3525 | plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION; | |
3526 | else if (key->flags & I915_SET_COLORKEY_SOURCE) | |
3527 | plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE; | |
3528 | ||
46f788ba VS |
3529 | return plane_ctl; |
3530 | } | |
3531 | ||
282dbf9b | 3532 | static void skylake_update_primary_plane(struct intel_plane *plane, |
a8d201af ML |
3533 | const struct intel_crtc_state *crtc_state, |
3534 | const struct intel_plane_state *plane_state) | |
6156a456 | 3535 | { |
282dbf9b VS |
3536 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
3537 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
3538 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
3539 | enum plane_id plane_id = plane->id; | |
3540 | enum pipe pipe = plane->pipe; | |
a0864d59 | 3541 | u32 plane_ctl = plane_state->ctl; |
a8d201af | 3542 | unsigned int rotation = plane_state->base.rotation; |
d2196774 | 3543 | u32 stride = skl_plane_stride(fb, 0, rotation); |
2e2adb05 | 3544 | u32 aux_stride = skl_plane_stride(fb, 1, rotation); |
b63a16f6 | 3545 | u32 surf_addr = plane_state->main.offset; |
a8d201af | 3546 | int scaler_id = plane_state->scaler_id; |
b63a16f6 VS |
3547 | int src_x = plane_state->main.x; |
3548 | int src_y = plane_state->main.y; | |
936e71e3 VS |
3549 | int src_w = drm_rect_width(&plane_state->base.src) >> 16; |
3550 | int src_h = drm_rect_height(&plane_state->base.src) >> 16; | |
3551 | int dst_x = plane_state->base.dst.x1; | |
3552 | int dst_y = plane_state->base.dst.y1; | |
3553 | int dst_w = drm_rect_width(&plane_state->base.dst); | |
3554 | int dst_h = drm_rect_height(&plane_state->base.dst); | |
dd584fc0 | 3555 | unsigned long irqflags; |
70d21f0e | 3556 | |
6687c906 VS |
3557 | /* Sizes are 0 based */ |
3558 | src_w--; | |
3559 | src_h--; | |
3560 | dst_w--; | |
3561 | dst_h--; | |
3562 | ||
282dbf9b | 3563 | crtc->dspaddr_offset = surf_addr; |
4c0b8a8b | 3564 | |
282dbf9b VS |
3565 | crtc->adjusted_x = src_x; |
3566 | crtc->adjusted_y = src_y; | |
2db3366b | 3567 | |
dd584fc0 VS |
3568 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
3569 | ||
6602be0e | 3570 | if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) { |
dd584fc0 VS |
3571 | I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id), |
3572 | PLANE_COLOR_PIPE_GAMMA_ENABLE | | |
3573 | PLANE_COLOR_PIPE_CSC_ENABLE | | |
3574 | PLANE_COLOR_PLANE_GAMMA_DISABLE); | |
78587de2 VS |
3575 | } |
3576 | ||
dd584fc0 VS |
3577 | I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl); |
3578 | I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x); | |
3579 | I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride); | |
3580 | I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); | |
2e2adb05 VS |
3581 | I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id), |
3582 | (plane_state->aux.offset - surf_addr) | aux_stride); | |
3583 | I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id), | |
3584 | (plane_state->aux.y << 16) | plane_state->aux.x); | |
6156a456 CK |
3585 | |
3586 | if (scaler_id >= 0) { | |
3587 | uint32_t ps_ctrl = 0; | |
3588 | ||
3589 | WARN_ON(!dst_w || !dst_h); | |
8e816bb4 | 3590 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) | |
6156a456 | 3591 | crtc_state->scaler_state.scalers[scaler_id].mode; |
dd584fc0 VS |
3592 | I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); |
3593 | I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3594 | I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3595 | I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3596 | I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0); | |
6156a456 | 3597 | } else { |
dd584fc0 | 3598 | I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x); |
6156a456 CK |
3599 | } |
3600 | ||
dd584fc0 VS |
3601 | I915_WRITE_FW(PLANE_SURF(pipe, plane_id), |
3602 | intel_plane_ggtt_offset(plane_state) + surf_addr); | |
70d21f0e | 3603 | |
dd584fc0 VS |
3604 | POSTING_READ_FW(PLANE_SURF(pipe, plane_id)); |
3605 | ||
3606 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
70d21f0e DL |
3607 | } |
3608 | ||
282dbf9b VS |
3609 | static void skylake_disable_primary_plane(struct intel_plane *primary, |
3610 | struct intel_crtc *crtc) | |
17638cd6 | 3611 | { |
282dbf9b VS |
3612 | struct drm_i915_private *dev_priv = to_i915(primary->base.dev); |
3613 | enum plane_id plane_id = primary->id; | |
3614 | enum pipe pipe = primary->pipe; | |
dd584fc0 VS |
3615 | unsigned long irqflags; |
3616 | ||
3617 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
62e0fb88 | 3618 | |
dd584fc0 VS |
3619 | I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0); |
3620 | I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0); | |
3621 | POSTING_READ_FW(PLANE_SURF(pipe, plane_id)); | |
3622 | ||
3623 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
a8d201af | 3624 | } |
29b9bde6 | 3625 | |
73974893 ML |
3626 | static int |
3627 | __intel_display_resume(struct drm_device *dev, | |
581e49fe ML |
3628 | struct drm_atomic_state *state, |
3629 | struct drm_modeset_acquire_ctx *ctx) | |
73974893 ML |
3630 | { |
3631 | struct drm_crtc_state *crtc_state; | |
3632 | struct drm_crtc *crtc; | |
3633 | int i, ret; | |
11c22da6 | 3634 | |
aecd36b8 | 3635 | intel_modeset_setup_hw_state(dev, ctx); |
29b74b7f | 3636 | i915_redisable_vga(to_i915(dev)); |
73974893 ML |
3637 | |
3638 | if (!state) | |
3639 | return 0; | |
3640 | ||
aa5e9b47 ML |
3641 | /* |
3642 | * We've duplicated the state, pointers to the old state are invalid. | |
3643 | * | |
3644 | * Don't attempt to use the old state until we commit the duplicated state. | |
3645 | */ | |
3646 | for_each_new_crtc_in_state(state, crtc, crtc_state, i) { | |
73974893 ML |
3647 | /* |
3648 | * Force recalculation even if we restore | |
3649 | * current state. With fast modeset this may not result | |
3650 | * in a modeset when the state is compatible. | |
3651 | */ | |
3652 | crtc_state->mode_changed = true; | |
96a02917 | 3653 | } |
73974893 ML |
3654 | |
3655 | /* ignore any reset values/BIOS leftovers in the WM registers */ | |
602ae835 VS |
3656 | if (!HAS_GMCH_DISPLAY(to_i915(dev))) |
3657 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
73974893 | 3658 | |
581e49fe | 3659 | ret = drm_atomic_helper_commit_duplicated_state(state, ctx); |
73974893 ML |
3660 | |
3661 | WARN_ON(ret == -EDEADLK); | |
3662 | return ret; | |
96a02917 VS |
3663 | } |
3664 | ||
4ac2ba2f VS |
3665 | static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) |
3666 | { | |
ae98104b VS |
3667 | return intel_has_gpu_reset(dev_priv) && |
3668 | INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv); | |
4ac2ba2f VS |
3669 | } |
3670 | ||
c033666a | 3671 | void intel_prepare_reset(struct drm_i915_private *dev_priv) |
7514747d | 3672 | { |
73974893 ML |
3673 | struct drm_device *dev = &dev_priv->drm; |
3674 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3675 | struct drm_atomic_state *state; | |
3676 | int ret; | |
3677 | ||
ce87ea15 DV |
3678 | |
3679 | /* reset doesn't touch the display */ | |
3680 | if (!i915.force_reset_modeset_test && | |
3681 | !gpu_reset_clobbers_display(dev_priv)) | |
3682 | return; | |
3683 | ||
97154ec2 DV |
3684 | /* We have a modeset vs reset deadlock, defensively unbreak it. |
3685 | * | |
3686 | * FIXME: We can do a _lot_ better, this is just a first iteration. | |
3687 | */ | |
3688 | i915_gem_set_wedged(dev_priv); | |
3689 | DRM_DEBUG_DRIVER("Wedging GPU to avoid deadlocks with pending modeset updates\n"); | |
3690 | ||
73974893 ML |
3691 | /* |
3692 | * Need mode_config.mutex so that we don't | |
3693 | * trample ongoing ->detect() and whatnot. | |
3694 | */ | |
3695 | mutex_lock(&dev->mode_config.mutex); | |
3696 | drm_modeset_acquire_init(ctx, 0); | |
3697 | while (1) { | |
3698 | ret = drm_modeset_lock_all_ctx(dev, ctx); | |
3699 | if (ret != -EDEADLK) | |
3700 | break; | |
3701 | ||
3702 | drm_modeset_backoff(ctx); | |
3703 | } | |
f98ce92f VS |
3704 | /* |
3705 | * Disabling the crtcs gracefully seems nicer. Also the | |
3706 | * g33 docs say we should at least disable all the planes. | |
3707 | */ | |
73974893 ML |
3708 | state = drm_atomic_helper_duplicate_state(dev, ctx); |
3709 | if (IS_ERR(state)) { | |
3710 | ret = PTR_ERR(state); | |
73974893 | 3711 | DRM_ERROR("Duplicating state failed with %i\n", ret); |
1e5a15d6 | 3712 | return; |
73974893 ML |
3713 | } |
3714 | ||
3715 | ret = drm_atomic_helper_disable_all(dev, ctx); | |
3716 | if (ret) { | |
3717 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
1e5a15d6 ACO |
3718 | drm_atomic_state_put(state); |
3719 | return; | |
73974893 ML |
3720 | } |
3721 | ||
3722 | dev_priv->modeset_restore_state = state; | |
3723 | state->acquire_ctx = ctx; | |
7514747d VS |
3724 | } |
3725 | ||
c033666a | 3726 | void intel_finish_reset(struct drm_i915_private *dev_priv) |
7514747d | 3727 | { |
73974893 ML |
3728 | struct drm_device *dev = &dev_priv->drm; |
3729 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3730 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
3731 | int ret; | |
3732 | ||
ce87ea15 DV |
3733 | /* reset doesn't touch the display */ |
3734 | if (!i915.force_reset_modeset_test && | |
3735 | !gpu_reset_clobbers_display(dev_priv)) | |
3736 | return; | |
3737 | ||
3738 | if (!state) | |
3739 | goto unlock; | |
3740 | ||
73974893 ML |
3741 | dev_priv->modeset_restore_state = NULL; |
3742 | ||
7514747d | 3743 | /* reset doesn't touch the display */ |
4ac2ba2f | 3744 | if (!gpu_reset_clobbers_display(dev_priv)) { |
ce87ea15 DV |
3745 | /* for testing only restore the display */ |
3746 | ret = __intel_display_resume(dev, state, ctx); | |
522a63de ML |
3747 | if (ret) |
3748 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
73974893 ML |
3749 | } else { |
3750 | /* | |
3751 | * The display has been reset as well, | |
3752 | * so need a full re-initialization. | |
3753 | */ | |
3754 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3755 | intel_runtime_pm_enable_interrupts(dev_priv); | |
7514747d | 3756 | |
51f59205 | 3757 | intel_pps_unlock_regs_wa(dev_priv); |
73974893 | 3758 | intel_modeset_init_hw(dev); |
7514747d | 3759 | |
73974893 ML |
3760 | spin_lock_irq(&dev_priv->irq_lock); |
3761 | if (dev_priv->display.hpd_irq_setup) | |
3762 | dev_priv->display.hpd_irq_setup(dev_priv); | |
3763 | spin_unlock_irq(&dev_priv->irq_lock); | |
7514747d | 3764 | |
581e49fe | 3765 | ret = __intel_display_resume(dev, state, ctx); |
73974893 ML |
3766 | if (ret) |
3767 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
7514747d | 3768 | |
73974893 ML |
3769 | intel_hpd_init(dev_priv); |
3770 | } | |
7514747d | 3771 | |
ce87ea15 DV |
3772 | drm_atomic_state_put(state); |
3773 | unlock: | |
73974893 ML |
3774 | drm_modeset_drop_locks(ctx); |
3775 | drm_modeset_acquire_fini(ctx); | |
3776 | mutex_unlock(&dev->mode_config.mutex); | |
7514747d VS |
3777 | } |
3778 | ||
bfd16b2a ML |
3779 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3780 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 | 3781 | { |
6315b5d3 | 3782 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
bfd16b2a ML |
3783 | struct intel_crtc_state *pipe_config = |
3784 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3785 | |
bfd16b2a ML |
3786 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3787 | crtc->base.mode = crtc->base.state->mode; | |
3788 | ||
e30e8f75 GP |
3789 | /* |
3790 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3791 | * that in compute_mode_changes we check the native mode (not the pfit | |
3792 | * mode) to see if we can flip rather than do a full mode set. In the | |
3793 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3794 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3795 | * sized surface. | |
e30e8f75 GP |
3796 | */ |
3797 | ||
e30e8f75 | 3798 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3799 | ((pipe_config->pipe_src_w - 1) << 16) | |
3800 | (pipe_config->pipe_src_h - 1)); | |
3801 | ||
3802 | /* on skylake this is done by detaching scalers */ | |
6315b5d3 | 3803 | if (INTEL_GEN(dev_priv) >= 9) { |
bfd16b2a ML |
3804 | skl_detach_scalers(crtc); |
3805 | ||
3806 | if (pipe_config->pch_pfit.enabled) | |
3807 | skylake_pfit_enable(crtc); | |
6e266956 | 3808 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
bfd16b2a ML |
3809 | if (pipe_config->pch_pfit.enabled) |
3810 | ironlake_pfit_enable(crtc); | |
3811 | else if (old_crtc_state->pch_pfit.enabled) | |
3812 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3813 | } |
e30e8f75 GP |
3814 | } |
3815 | ||
4cbe4b2b | 3816 | static void intel_fdi_normal_train(struct intel_crtc *crtc) |
5e84e1a4 | 3817 | { |
4cbe4b2b | 3818 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3819 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3820 | int pipe = crtc->pipe; |
f0f59a00 VS |
3821 | i915_reg_t reg; |
3822 | u32 temp; | |
5e84e1a4 ZW |
3823 | |
3824 | /* enable normal train */ | |
3825 | reg = FDI_TX_CTL(pipe); | |
3826 | temp = I915_READ(reg); | |
fd6b8f43 | 3827 | if (IS_IVYBRIDGE(dev_priv)) { |
357555c0 JB |
3828 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3829 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3830 | } else { |
3831 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3832 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3833 | } |
5e84e1a4 ZW |
3834 | I915_WRITE(reg, temp); |
3835 | ||
3836 | reg = FDI_RX_CTL(pipe); | |
3837 | temp = I915_READ(reg); | |
6e266956 | 3838 | if (HAS_PCH_CPT(dev_priv)) { |
5e84e1a4 ZW |
3839 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3840 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3841 | } else { | |
3842 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3843 | temp |= FDI_LINK_TRAIN_NONE; | |
3844 | } | |
3845 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3846 | ||
3847 | /* wait one idle pattern time */ | |
3848 | POSTING_READ(reg); | |
3849 | udelay(1000); | |
357555c0 JB |
3850 | |
3851 | /* IVB wants error correction enabled */ | |
fd6b8f43 | 3852 | if (IS_IVYBRIDGE(dev_priv)) |
357555c0 JB |
3853 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
3854 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3855 | } |
3856 | ||
8db9d77b | 3857 | /* The FDI link training functions for ILK/Ibexpeak. */ |
dc4a1094 ACO |
3858 | static void ironlake_fdi_link_train(struct intel_crtc *crtc, |
3859 | const struct intel_crtc_state *crtc_state) | |
8db9d77b | 3860 | { |
4cbe4b2b | 3861 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3862 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3863 | int pipe = crtc->pipe; |
f0f59a00 VS |
3864 | i915_reg_t reg; |
3865 | u32 temp, tries; | |
8db9d77b | 3866 | |
1c8562f6 | 3867 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3868 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3869 | |
e1a44743 AJ |
3870 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3871 | for train result */ | |
5eddb70b CW |
3872 | reg = FDI_RX_IMR(pipe); |
3873 | temp = I915_READ(reg); | |
e1a44743 AJ |
3874 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3875 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3876 | I915_WRITE(reg, temp); |
3877 | I915_READ(reg); | |
e1a44743 AJ |
3878 | udelay(150); |
3879 | ||
8db9d77b | 3880 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3881 | reg = FDI_TX_CTL(pipe); |
3882 | temp = I915_READ(reg); | |
627eb5a3 | 3883 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 3884 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
8db9d77b ZW |
3885 | temp &= ~FDI_LINK_TRAIN_NONE; |
3886 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3887 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3888 | |
5eddb70b CW |
3889 | reg = FDI_RX_CTL(pipe); |
3890 | temp = I915_READ(reg); | |
8db9d77b ZW |
3891 | temp &= ~FDI_LINK_TRAIN_NONE; |
3892 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3893 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3894 | ||
3895 | POSTING_READ(reg); | |
8db9d77b ZW |
3896 | udelay(150); |
3897 | ||
5b2adf89 | 3898 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3899 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3900 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3901 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3902 | |
5eddb70b | 3903 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3904 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3905 | temp = I915_READ(reg); |
8db9d77b ZW |
3906 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3907 | ||
3908 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3909 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3910 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3911 | break; |
3912 | } | |
8db9d77b | 3913 | } |
e1a44743 | 3914 | if (tries == 5) |
5eddb70b | 3915 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3916 | |
3917 | /* Train 2 */ | |
5eddb70b CW |
3918 | reg = FDI_TX_CTL(pipe); |
3919 | temp = I915_READ(reg); | |
8db9d77b ZW |
3920 | temp &= ~FDI_LINK_TRAIN_NONE; |
3921 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3922 | I915_WRITE(reg, temp); |
8db9d77b | 3923 | |
5eddb70b CW |
3924 | reg = FDI_RX_CTL(pipe); |
3925 | temp = I915_READ(reg); | |
8db9d77b ZW |
3926 | temp &= ~FDI_LINK_TRAIN_NONE; |
3927 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3928 | I915_WRITE(reg, temp); |
8db9d77b | 3929 | |
5eddb70b CW |
3930 | POSTING_READ(reg); |
3931 | udelay(150); | |
8db9d77b | 3932 | |
5eddb70b | 3933 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3934 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3935 | temp = I915_READ(reg); |
8db9d77b ZW |
3936 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3937 | ||
3938 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3939 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3940 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3941 | break; | |
3942 | } | |
8db9d77b | 3943 | } |
e1a44743 | 3944 | if (tries == 5) |
5eddb70b | 3945 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3946 | |
3947 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3948 | |
8db9d77b ZW |
3949 | } |
3950 | ||
0206e353 | 3951 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3952 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3953 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3954 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3955 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3956 | }; | |
3957 | ||
3958 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
dc4a1094 ACO |
3959 | static void gen6_fdi_link_train(struct intel_crtc *crtc, |
3960 | const struct intel_crtc_state *crtc_state) | |
8db9d77b | 3961 | { |
4cbe4b2b | 3962 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3963 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3964 | int pipe = crtc->pipe; |
f0f59a00 VS |
3965 | i915_reg_t reg; |
3966 | u32 temp, i, retry; | |
8db9d77b | 3967 | |
e1a44743 AJ |
3968 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3969 | for train result */ | |
5eddb70b CW |
3970 | reg = FDI_RX_IMR(pipe); |
3971 | temp = I915_READ(reg); | |
e1a44743 AJ |
3972 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3973 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3974 | I915_WRITE(reg, temp); |
3975 | ||
3976 | POSTING_READ(reg); | |
e1a44743 AJ |
3977 | udelay(150); |
3978 | ||
8db9d77b | 3979 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3980 | reg = FDI_TX_CTL(pipe); |
3981 | temp = I915_READ(reg); | |
627eb5a3 | 3982 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 3983 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
8db9d77b ZW |
3984 | temp &= ~FDI_LINK_TRAIN_NONE; |
3985 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3986 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3987 | /* SNB-B */ | |
3988 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3989 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3990 | |
d74cf324 DV |
3991 | I915_WRITE(FDI_RX_MISC(pipe), |
3992 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3993 | ||
5eddb70b CW |
3994 | reg = FDI_RX_CTL(pipe); |
3995 | temp = I915_READ(reg); | |
6e266956 | 3996 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
3997 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3998 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3999 | } else { | |
4000 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4001 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4002 | } | |
5eddb70b CW |
4003 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
4004 | ||
4005 | POSTING_READ(reg); | |
8db9d77b ZW |
4006 | udelay(150); |
4007 | ||
0206e353 | 4008 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
4009 | reg = FDI_TX_CTL(pipe); |
4010 | temp = I915_READ(reg); | |
8db9d77b ZW |
4011 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
4012 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
4013 | I915_WRITE(reg, temp); |
4014 | ||
4015 | POSTING_READ(reg); | |
8db9d77b ZW |
4016 | udelay(500); |
4017 | ||
fa37d39e SP |
4018 | for (retry = 0; retry < 5; retry++) { |
4019 | reg = FDI_RX_IIR(pipe); | |
4020 | temp = I915_READ(reg); | |
4021 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
4022 | if (temp & FDI_RX_BIT_LOCK) { | |
4023 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
4024 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
4025 | break; | |
4026 | } | |
4027 | udelay(50); | |
8db9d77b | 4028 | } |
fa37d39e SP |
4029 | if (retry < 5) |
4030 | break; | |
8db9d77b ZW |
4031 | } |
4032 | if (i == 4) | |
5eddb70b | 4033 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
4034 | |
4035 | /* Train 2 */ | |
5eddb70b CW |
4036 | reg = FDI_TX_CTL(pipe); |
4037 | temp = I915_READ(reg); | |
8db9d77b ZW |
4038 | temp &= ~FDI_LINK_TRAIN_NONE; |
4039 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5db94019 | 4040 | if (IS_GEN6(dev_priv)) { |
8db9d77b ZW |
4041 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
4042 | /* SNB-B */ | |
4043 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
4044 | } | |
5eddb70b | 4045 | I915_WRITE(reg, temp); |
8db9d77b | 4046 | |
5eddb70b CW |
4047 | reg = FDI_RX_CTL(pipe); |
4048 | temp = I915_READ(reg); | |
6e266956 | 4049 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
4050 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
4051 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
4052 | } else { | |
4053 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4054 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
4055 | } | |
5eddb70b CW |
4056 | I915_WRITE(reg, temp); |
4057 | ||
4058 | POSTING_READ(reg); | |
8db9d77b ZW |
4059 | udelay(150); |
4060 | ||
0206e353 | 4061 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
4062 | reg = FDI_TX_CTL(pipe); |
4063 | temp = I915_READ(reg); | |
8db9d77b ZW |
4064 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
4065 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
4066 | I915_WRITE(reg, temp); |
4067 | ||
4068 | POSTING_READ(reg); | |
8db9d77b ZW |
4069 | udelay(500); |
4070 | ||
fa37d39e SP |
4071 | for (retry = 0; retry < 5; retry++) { |
4072 | reg = FDI_RX_IIR(pipe); | |
4073 | temp = I915_READ(reg); | |
4074 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
4075 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
4076 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
4077 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
4078 | break; | |
4079 | } | |
4080 | udelay(50); | |
8db9d77b | 4081 | } |
fa37d39e SP |
4082 | if (retry < 5) |
4083 | break; | |
8db9d77b ZW |
4084 | } |
4085 | if (i == 4) | |
5eddb70b | 4086 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
4087 | |
4088 | DRM_DEBUG_KMS("FDI train done.\n"); | |
4089 | } | |
4090 | ||
357555c0 | 4091 | /* Manual link training for Ivy Bridge A0 parts */ |
dc4a1094 ACO |
4092 | static void ivb_manual_fdi_link_train(struct intel_crtc *crtc, |
4093 | const struct intel_crtc_state *crtc_state) | |
357555c0 | 4094 | { |
4cbe4b2b | 4095 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4096 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 4097 | int pipe = crtc->pipe; |
f0f59a00 VS |
4098 | i915_reg_t reg; |
4099 | u32 temp, i, j; | |
357555c0 JB |
4100 | |
4101 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
4102 | for train result */ | |
4103 | reg = FDI_RX_IMR(pipe); | |
4104 | temp = I915_READ(reg); | |
4105 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
4106 | temp &= ~FDI_RX_BIT_LOCK; | |
4107 | I915_WRITE(reg, temp); | |
4108 | ||
4109 | POSTING_READ(reg); | |
4110 | udelay(150); | |
4111 | ||
01a415fd DV |
4112 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
4113 | I915_READ(FDI_RX_IIR(pipe))); | |
4114 | ||
139ccd3f JB |
4115 | /* Try each vswing and preemphasis setting twice before moving on */ |
4116 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
4117 | /* disable first in case we need to retry */ | |
4118 | reg = FDI_TX_CTL(pipe); | |
4119 | temp = I915_READ(reg); | |
4120 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
4121 | temp &= ~FDI_TX_ENABLE; | |
4122 | I915_WRITE(reg, temp); | |
357555c0 | 4123 | |
139ccd3f JB |
4124 | reg = FDI_RX_CTL(pipe); |
4125 | temp = I915_READ(reg); | |
4126 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
4127 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
4128 | temp &= ~FDI_RX_ENABLE; | |
4129 | I915_WRITE(reg, temp); | |
357555c0 | 4130 | |
139ccd3f | 4131 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
4132 | reg = FDI_TX_CTL(pipe); |
4133 | temp = I915_READ(reg); | |
139ccd3f | 4134 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 4135 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
139ccd3f | 4136 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 4137 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
4138 | temp |= snb_b_fdi_train_param[j/2]; |
4139 | temp |= FDI_COMPOSITE_SYNC; | |
4140 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 4141 | |
139ccd3f JB |
4142 | I915_WRITE(FDI_RX_MISC(pipe), |
4143 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 4144 | |
139ccd3f | 4145 | reg = FDI_RX_CTL(pipe); |
357555c0 | 4146 | temp = I915_READ(reg); |
139ccd3f JB |
4147 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
4148 | temp |= FDI_COMPOSITE_SYNC; | |
4149 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 4150 | |
139ccd3f JB |
4151 | POSTING_READ(reg); |
4152 | udelay(1); /* should be 0.5us */ | |
357555c0 | 4153 | |
139ccd3f JB |
4154 | for (i = 0; i < 4; i++) { |
4155 | reg = FDI_RX_IIR(pipe); | |
4156 | temp = I915_READ(reg); | |
4157 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 4158 | |
139ccd3f JB |
4159 | if (temp & FDI_RX_BIT_LOCK || |
4160 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
4161 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
4162 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
4163 | i); | |
4164 | break; | |
4165 | } | |
4166 | udelay(1); /* should be 0.5us */ | |
4167 | } | |
4168 | if (i == 4) { | |
4169 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
4170 | continue; | |
4171 | } | |
357555c0 | 4172 | |
139ccd3f | 4173 | /* Train 2 */ |
357555c0 JB |
4174 | reg = FDI_TX_CTL(pipe); |
4175 | temp = I915_READ(reg); | |
139ccd3f JB |
4176 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
4177 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
4178 | I915_WRITE(reg, temp); | |
4179 | ||
4180 | reg = FDI_RX_CTL(pipe); | |
4181 | temp = I915_READ(reg); | |
4182 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
4183 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
4184 | I915_WRITE(reg, temp); |
4185 | ||
4186 | POSTING_READ(reg); | |
139ccd3f | 4187 | udelay(2); /* should be 1.5us */ |
357555c0 | 4188 | |
139ccd3f JB |
4189 | for (i = 0; i < 4; i++) { |
4190 | reg = FDI_RX_IIR(pipe); | |
4191 | temp = I915_READ(reg); | |
4192 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 4193 | |
139ccd3f JB |
4194 | if (temp & FDI_RX_SYMBOL_LOCK || |
4195 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
4196 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
4197 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
4198 | i); | |
4199 | goto train_done; | |
4200 | } | |
4201 | udelay(2); /* should be 1.5us */ | |
357555c0 | 4202 | } |
139ccd3f JB |
4203 | if (i == 4) |
4204 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 4205 | } |
357555c0 | 4206 | |
139ccd3f | 4207 | train_done: |
357555c0 JB |
4208 | DRM_DEBUG_KMS("FDI train done.\n"); |
4209 | } | |
4210 | ||
88cefb6c | 4211 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 4212 | { |
88cefb6c | 4213 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 4214 | struct drm_i915_private *dev_priv = to_i915(dev); |
2c07245f | 4215 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
4216 | i915_reg_t reg; |
4217 | u32 temp; | |
c64e311e | 4218 | |
c98e9dcf | 4219 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
4220 | reg = FDI_RX_CTL(pipe); |
4221 | temp = I915_READ(reg); | |
627eb5a3 | 4222 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 4223 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 4224 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
4225 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
4226 | ||
4227 | POSTING_READ(reg); | |
c98e9dcf JB |
4228 | udelay(200); |
4229 | ||
4230 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
4231 | temp = I915_READ(reg); |
4232 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
4233 | ||
4234 | POSTING_READ(reg); | |
c98e9dcf JB |
4235 | udelay(200); |
4236 | ||
20749730 PZ |
4237 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
4238 | reg = FDI_TX_CTL(pipe); | |
4239 | temp = I915_READ(reg); | |
4240 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
4241 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 4242 | |
20749730 PZ |
4243 | POSTING_READ(reg); |
4244 | udelay(100); | |
6be4a607 | 4245 | } |
0e23b99d JB |
4246 | } |
4247 | ||
88cefb6c DV |
4248 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
4249 | { | |
4250 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 4251 | struct drm_i915_private *dev_priv = to_i915(dev); |
88cefb6c | 4252 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
4253 | i915_reg_t reg; |
4254 | u32 temp; | |
88cefb6c DV |
4255 | |
4256 | /* Switch from PCDclk to Rawclk */ | |
4257 | reg = FDI_RX_CTL(pipe); | |
4258 | temp = I915_READ(reg); | |
4259 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
4260 | ||
4261 | /* Disable CPU FDI TX PLL */ | |
4262 | reg = FDI_TX_CTL(pipe); | |
4263 | temp = I915_READ(reg); | |
4264 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
4265 | ||
4266 | POSTING_READ(reg); | |
4267 | udelay(100); | |
4268 | ||
4269 | reg = FDI_RX_CTL(pipe); | |
4270 | temp = I915_READ(reg); | |
4271 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
4272 | ||
4273 | /* Wait for the clocks to turn off. */ | |
4274 | POSTING_READ(reg); | |
4275 | udelay(100); | |
4276 | } | |
4277 | ||
0fc932b8 JB |
4278 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
4279 | { | |
4280 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4281 | struct drm_i915_private *dev_priv = to_i915(dev); |
0fc932b8 JB |
4282 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4283 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
4284 | i915_reg_t reg; |
4285 | u32 temp; | |
0fc932b8 JB |
4286 | |
4287 | /* disable CPU FDI tx and PCH FDI rx */ | |
4288 | reg = FDI_TX_CTL(pipe); | |
4289 | temp = I915_READ(reg); | |
4290 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
4291 | POSTING_READ(reg); | |
4292 | ||
4293 | reg = FDI_RX_CTL(pipe); | |
4294 | temp = I915_READ(reg); | |
4295 | temp &= ~(0x7 << 16); | |
dfd07d72 | 4296 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
4297 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
4298 | ||
4299 | POSTING_READ(reg); | |
4300 | udelay(100); | |
4301 | ||
4302 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6e266956 | 4303 | if (HAS_PCH_IBX(dev_priv)) |
6f06ce18 | 4304 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
4305 | |
4306 | /* still set train pattern 1 */ | |
4307 | reg = FDI_TX_CTL(pipe); | |
4308 | temp = I915_READ(reg); | |
4309 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4310 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4311 | I915_WRITE(reg, temp); | |
4312 | ||
4313 | reg = FDI_RX_CTL(pipe); | |
4314 | temp = I915_READ(reg); | |
6e266956 | 4315 | if (HAS_PCH_CPT(dev_priv)) { |
0fc932b8 JB |
4316 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
4317 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
4318 | } else { | |
4319 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4320 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4321 | } | |
4322 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
4323 | temp &= ~(0x07 << 16); | |
dfd07d72 | 4324 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
4325 | I915_WRITE(reg, temp); |
4326 | ||
4327 | POSTING_READ(reg); | |
4328 | udelay(100); | |
4329 | } | |
4330 | ||
49d73912 | 4331 | bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) |
5dce5b93 | 4332 | { |
fa05887a DV |
4333 | struct drm_crtc *crtc; |
4334 | bool cleanup_done; | |
4335 | ||
4336 | drm_for_each_crtc(crtc, &dev_priv->drm) { | |
4337 | struct drm_crtc_commit *commit; | |
4338 | spin_lock(&crtc->commit_lock); | |
4339 | commit = list_first_entry_or_null(&crtc->commit_list, | |
4340 | struct drm_crtc_commit, commit_entry); | |
4341 | cleanup_done = commit ? | |
4342 | try_wait_for_completion(&commit->cleanup_done) : true; | |
4343 | spin_unlock(&crtc->commit_lock); | |
4344 | ||
4345 | if (cleanup_done) | |
5dce5b93 CW |
4346 | continue; |
4347 | ||
fa05887a | 4348 | drm_crtc_wait_one_vblank(crtc); |
5dce5b93 CW |
4349 | |
4350 | return true; | |
4351 | } | |
4352 | ||
4353 | return false; | |
4354 | } | |
4355 | ||
b7076546 | 4356 | void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
060f02d8 VS |
4357 | { |
4358 | u32 temp; | |
4359 | ||
4360 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
4361 | ||
4362 | mutex_lock(&dev_priv->sb_lock); | |
4363 | ||
4364 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4365 | temp |= SBI_SSCCTL_DISABLE; | |
4366 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
4367 | ||
4368 | mutex_unlock(&dev_priv->sb_lock); | |
4369 | } | |
4370 | ||
e615efe4 | 4371 | /* Program iCLKIP clock to the desired frequency */ |
0dcdc382 | 4372 | static void lpt_program_iclkip(struct intel_crtc *crtc) |
e615efe4 | 4373 | { |
0dcdc382 ACO |
4374 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
4375 | int clock = crtc->config->base.adjusted_mode.crtc_clock; | |
e615efe4 ED |
4376 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
4377 | u32 temp; | |
4378 | ||
060f02d8 | 4379 | lpt_disable_iclkip(dev_priv); |
e615efe4 | 4380 | |
64b46a06 VS |
4381 | /* The iCLK virtual clock root frequency is in MHz, |
4382 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
4383 | * divisors, it is necessary to divide one by another, so we | |
4384 | * convert the virtual clock precision to KHz here for higher | |
4385 | * precision. | |
4386 | */ | |
4387 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
e615efe4 ED |
4388 | u32 iclk_virtual_root_freq = 172800 * 1000; |
4389 | u32 iclk_pi_range = 64; | |
64b46a06 | 4390 | u32 desired_divisor; |
e615efe4 | 4391 | |
64b46a06 VS |
4392 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
4393 | clock << auxdiv); | |
4394 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
4395 | phaseinc = desired_divisor % iclk_pi_range; | |
e615efe4 | 4396 | |
64b46a06 VS |
4397 | /* |
4398 | * Near 20MHz is a corner case which is | |
4399 | * out of range for the 7-bit divisor | |
4400 | */ | |
4401 | if (divsel <= 0x7f) | |
4402 | break; | |
e615efe4 ED |
4403 | } |
4404 | ||
4405 | /* This should not happen with any sane values */ | |
4406 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
4407 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
4408 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
4409 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
4410 | ||
4411 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 4412 | clock, |
e615efe4 ED |
4413 | auxdiv, |
4414 | divsel, | |
4415 | phasedir, | |
4416 | phaseinc); | |
4417 | ||
060f02d8 VS |
4418 | mutex_lock(&dev_priv->sb_lock); |
4419 | ||
e615efe4 | 4420 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 4421 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4422 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4423 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4424 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4425 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4426 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4427 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4428 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4429 | |
4430 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4431 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4432 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4433 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4434 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4435 | |
4436 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4437 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4438 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4439 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 4440 | |
060f02d8 VS |
4441 | mutex_unlock(&dev_priv->sb_lock); |
4442 | ||
e615efe4 ED |
4443 | /* Wait for initialization time */ |
4444 | udelay(24); | |
4445 | ||
4446 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
4447 | } | |
4448 | ||
8802e5b6 VS |
4449 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
4450 | { | |
4451 | u32 divsel, phaseinc, auxdiv; | |
4452 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
4453 | u32 iclk_pi_range = 64; | |
4454 | u32 desired_divisor; | |
4455 | u32 temp; | |
4456 | ||
4457 | if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) | |
4458 | return 0; | |
4459 | ||
4460 | mutex_lock(&dev_priv->sb_lock); | |
4461 | ||
4462 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4463 | if (temp & SBI_SSCCTL_DISABLE) { | |
4464 | mutex_unlock(&dev_priv->sb_lock); | |
4465 | return 0; | |
4466 | } | |
4467 | ||
4468 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
4469 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
4470 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
4471 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
4472 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
4473 | ||
4474 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
4475 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
4476 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
4477 | ||
4478 | mutex_unlock(&dev_priv->sb_lock); | |
4479 | ||
4480 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
4481 | ||
4482 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
4483 | desired_divisor << auxdiv); | |
4484 | } | |
4485 | ||
275f01b2 DV |
4486 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4487 | enum pipe pch_transcoder) | |
4488 | { | |
4489 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4490 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 4491 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4492 | |
4493 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4494 | I915_READ(HTOTAL(cpu_transcoder))); | |
4495 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4496 | I915_READ(HBLANK(cpu_transcoder))); | |
4497 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4498 | I915_READ(HSYNC(cpu_transcoder))); | |
4499 | ||
4500 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4501 | I915_READ(VTOTAL(cpu_transcoder))); | |
4502 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4503 | I915_READ(VBLANK(cpu_transcoder))); | |
4504 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4505 | I915_READ(VSYNC(cpu_transcoder))); | |
4506 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4507 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4508 | } | |
4509 | ||
003632d9 | 4510 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 | 4511 | { |
fac5e23e | 4512 | struct drm_i915_private *dev_priv = to_i915(dev); |
1fbc0d78 DV |
4513 | uint32_t temp; |
4514 | ||
4515 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4516 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4517 | return; |
4518 | ||
4519 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4520 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4521 | ||
003632d9 ACO |
4522 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4523 | if (enable) | |
4524 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4525 | ||
4526 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4527 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4528 | POSTING_READ(SOUTH_CHICKEN1); | |
4529 | } | |
4530 | ||
4531 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4532 | { | |
4533 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4534 | |
4535 | switch (intel_crtc->pipe) { | |
4536 | case PIPE_A: | |
4537 | break; | |
4538 | case PIPE_B: | |
6e3c9717 | 4539 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4540 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4541 | else |
003632d9 | 4542 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4543 | |
4544 | break; | |
4545 | case PIPE_C: | |
003632d9 | 4546 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4547 | |
4548 | break; | |
4549 | default: | |
4550 | BUG(); | |
4551 | } | |
4552 | } | |
4553 | ||
c48b5305 VS |
4554 | /* Return which DP Port should be selected for Transcoder DP control */ |
4555 | static enum port | |
4cbe4b2b | 4556 | intel_trans_dp_port_sel(struct intel_crtc *crtc) |
c48b5305 | 4557 | { |
4cbe4b2b | 4558 | struct drm_device *dev = crtc->base.dev; |
c48b5305 VS |
4559 | struct intel_encoder *encoder; |
4560 | ||
4cbe4b2b | 4561 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
cca0502b | 4562 | if (encoder->type == INTEL_OUTPUT_DP || |
c48b5305 VS |
4563 | encoder->type == INTEL_OUTPUT_EDP) |
4564 | return enc_to_dig_port(&encoder->base)->port; | |
4565 | } | |
4566 | ||
4567 | return -1; | |
4568 | } | |
4569 | ||
f67a559d JB |
4570 | /* |
4571 | * Enable PCH resources required for PCH ports: | |
4572 | * - PCH PLLs | |
4573 | * - FDI training & RX/TX | |
4574 | * - update transcoder timings | |
4575 | * - DP transcoding bits | |
4576 | * - transcoder | |
4577 | */ | |
2ce42273 | 4578 | static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state) |
0e23b99d | 4579 | { |
2ce42273 | 4580 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
4cbe4b2b | 4581 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4582 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 4583 | int pipe = crtc->pipe; |
f0f59a00 | 4584 | u32 temp; |
2c07245f | 4585 | |
ab9412ba | 4586 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4587 | |
fd6b8f43 | 4588 | if (IS_IVYBRIDGE(dev_priv)) |
4cbe4b2b | 4589 | ivybridge_update_fdi_bc_bifurcation(crtc); |
1fbc0d78 | 4590 | |
cd986abb DV |
4591 | /* Write the TU size bits before fdi link training, so that error |
4592 | * detection works. */ | |
4593 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4594 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4595 | ||
c98e9dcf | 4596 | /* For PCH output, training FDI link */ |
dc4a1094 | 4597 | dev_priv->display.fdi_link_train(crtc, crtc_state); |
2c07245f | 4598 | |
3ad8a208 DV |
4599 | /* We need to program the right clock selection before writing the pixel |
4600 | * mutliplier into the DPLL. */ | |
6e266956 | 4601 | if (HAS_PCH_CPT(dev_priv)) { |
ee7b9f93 | 4602 | u32 sel; |
4b645f14 | 4603 | |
c98e9dcf | 4604 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4605 | temp |= TRANS_DPLL_ENABLE(pipe); |
4606 | sel = TRANS_DPLLB_SEL(pipe); | |
2ce42273 | 4607 | if (crtc_state->shared_dpll == |
8106ddbd | 4608 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) |
ee7b9f93 JB |
4609 | temp |= sel; |
4610 | else | |
4611 | temp &= ~sel; | |
c98e9dcf | 4612 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4613 | } |
5eddb70b | 4614 | |
3ad8a208 DV |
4615 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4616 | * transcoder, and we actually should do this to not upset any PCH | |
4617 | * transcoder that already use the clock when we share it. | |
4618 | * | |
4619 | * Note that enable_shared_dpll tries to do the right thing, but | |
4620 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4621 | * the right LVDS enable sequence. */ | |
4cbe4b2b | 4622 | intel_enable_shared_dpll(crtc); |
3ad8a208 | 4623 | |
d9b6cb56 JB |
4624 | /* set transcoder timing, panel must allow it */ |
4625 | assert_panel_unlocked(dev_priv, pipe); | |
4cbe4b2b | 4626 | ironlake_pch_transcoder_set_timings(crtc, pipe); |
8db9d77b | 4627 | |
303b81e0 | 4628 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4629 | |
c98e9dcf | 4630 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e266956 | 4631 | if (HAS_PCH_CPT(dev_priv) && |
2ce42273 | 4632 | intel_crtc_has_dp_encoder(crtc_state)) { |
9c4edaee | 4633 | const struct drm_display_mode *adjusted_mode = |
2ce42273 | 4634 | &crtc_state->base.adjusted_mode; |
dfd07d72 | 4635 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4636 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4637 | temp = I915_READ(reg); |
4638 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4639 | TRANS_DP_SYNC_MASK | |
4640 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4641 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4642 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4643 | |
9c4edaee | 4644 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4645 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4646 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4647 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4648 | |
4649 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4650 | case PORT_B: |
5eddb70b | 4651 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4652 | break; |
c48b5305 | 4653 | case PORT_C: |
5eddb70b | 4654 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4655 | break; |
c48b5305 | 4656 | case PORT_D: |
5eddb70b | 4657 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4658 | break; |
4659 | default: | |
e95d41e1 | 4660 | BUG(); |
32f9d658 | 4661 | } |
2c07245f | 4662 | |
5eddb70b | 4663 | I915_WRITE(reg, temp); |
6be4a607 | 4664 | } |
b52eb4dc | 4665 | |
b8a4f404 | 4666 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4667 | } |
4668 | ||
2ce42273 | 4669 | static void lpt_pch_enable(const struct intel_crtc_state *crtc_state) |
1507e5bd | 4670 | { |
2ce42273 | 4671 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
0dcdc382 | 4672 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2ce42273 | 4673 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
1507e5bd | 4674 | |
a2196033 | 4675 | assert_pch_transcoder_disabled(dev_priv, PIPE_A); |
1507e5bd | 4676 | |
8c52b5e8 | 4677 | lpt_program_iclkip(crtc); |
1507e5bd | 4678 | |
0540e488 | 4679 | /* Set transcoder timing. */ |
0dcdc382 | 4680 | ironlake_pch_transcoder_set_timings(crtc, PIPE_A); |
1507e5bd | 4681 | |
937bb610 | 4682 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4683 | } |
4684 | ||
a1520318 | 4685 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 | 4686 | { |
fac5e23e | 4687 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 4688 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4689 | u32 temp; |
4690 | ||
4691 | temp = I915_READ(dslreg); | |
4692 | udelay(500); | |
4693 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4694 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4695 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4696 | } |
4697 | } | |
4698 | ||
86adf9d7 ML |
4699 | static int |
4700 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
d96a7d2a | 4701 | unsigned int scaler_user, int *scaler_id, |
86adf9d7 | 4702 | int src_w, int src_h, int dst_w, int dst_h) |
a1b2278e | 4703 | { |
86adf9d7 ML |
4704 | struct intel_crtc_scaler_state *scaler_state = |
4705 | &crtc_state->scaler_state; | |
4706 | struct intel_crtc *intel_crtc = | |
4707 | to_intel_crtc(crtc_state->base.crtc); | |
7f58cbb1 MK |
4708 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
4709 | const struct drm_display_mode *adjusted_mode = | |
4710 | &crtc_state->base.adjusted_mode; | |
a1b2278e | 4711 | int need_scaling; |
6156a456 | 4712 | |
d96a7d2a VS |
4713 | /* |
4714 | * Src coordinates are already rotated by 270 degrees for | |
4715 | * the 90/270 degree plane rotation cases (to match the | |
4716 | * GTT mapping), hence no need to account for rotation here. | |
4717 | */ | |
4718 | need_scaling = src_w != dst_w || src_h != dst_h; | |
a1b2278e | 4719 | |
e5c05931 SS |
4720 | if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX) |
4721 | need_scaling = true; | |
4722 | ||
7f58cbb1 MK |
4723 | /* |
4724 | * Scaling/fitting not supported in IF-ID mode in GEN9+ | |
4725 | * TODO: Interlace fetch mode doesn't support YUV420 planar formats. | |
4726 | * Once NV12 is enabled, handle it here while allocating scaler | |
4727 | * for NV12. | |
4728 | */ | |
4729 | if (INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable && | |
4730 | need_scaling && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { | |
4731 | DRM_DEBUG_KMS("Pipe/Plane scaling not supported with IF-ID mode\n"); | |
4732 | return -EINVAL; | |
4733 | } | |
4734 | ||
a1b2278e CK |
4735 | /* |
4736 | * if plane is being disabled or scaler is no more required or force detach | |
4737 | * - free scaler binded to this plane/crtc | |
4738 | * - in order to do this, update crtc->scaler_usage | |
4739 | * | |
4740 | * Here scaler state in crtc_state is set free so that | |
4741 | * scaler can be assigned to other user. Actual register | |
4742 | * update to free the scaler is done in plane/panel-fit programming. | |
4743 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4744 | */ | |
86adf9d7 | 4745 | if (force_detach || !need_scaling) { |
a1b2278e | 4746 | if (*scaler_id >= 0) { |
86adf9d7 | 4747 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4748 | scaler_state->scalers[*scaler_id].in_use = 0; |
4749 | ||
86adf9d7 ML |
4750 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4751 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4752 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4753 | scaler_state->scaler_users); |
4754 | *scaler_id = -1; | |
4755 | } | |
4756 | return 0; | |
4757 | } | |
4758 | ||
4759 | /* range checks */ | |
4760 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4761 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4762 | ||
4763 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4764 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4765 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4766 | "size is out of scaler range\n", |
86adf9d7 | 4767 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4768 | return -EINVAL; |
4769 | } | |
4770 | ||
86adf9d7 ML |
4771 | /* mark this plane as a scaler user in crtc_state */ |
4772 | scaler_state->scaler_users |= (1 << scaler_user); | |
4773 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4774 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4775 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4776 | scaler_state->scaler_users); | |
4777 | ||
4778 | return 0; | |
4779 | } | |
4780 | ||
4781 | /** | |
4782 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4783 | * | |
4784 | * @state: crtc's scaler state | |
86adf9d7 ML |
4785 | * |
4786 | * Return | |
4787 | * 0 - scaler_usage updated successfully | |
4788 | * error - requested scaling cannot be supported or other error condition | |
4789 | */ | |
e435d6e5 | 4790 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 | 4791 | { |
7c5f93b0 | 4792 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 | 4793 | |
e435d6e5 | 4794 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
d96a7d2a | 4795 | &state->scaler_state.scaler_id, |
86adf9d7 | 4796 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4797 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4798 | } |
4799 | ||
4800 | /** | |
4801 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4802 | * | |
4803 | * @state: crtc's scaler state | |
86adf9d7 ML |
4804 | * @plane_state: atomic plane state to update |
4805 | * | |
4806 | * Return | |
4807 | * 0 - scaler_usage updated successfully | |
4808 | * error - requested scaling cannot be supported or other error condition | |
4809 | */ | |
da20eabd ML |
4810 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4811 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4812 | { |
4813 | ||
da20eabd ML |
4814 | struct intel_plane *intel_plane = |
4815 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4816 | struct drm_framebuffer *fb = plane_state->base.fb; |
4817 | int ret; | |
4818 | ||
936e71e3 | 4819 | bool force_detach = !fb || !plane_state->base.visible; |
86adf9d7 | 4820 | |
86adf9d7 ML |
4821 | ret = skl_update_scaler(crtc_state, force_detach, |
4822 | drm_plane_index(&intel_plane->base), | |
4823 | &plane_state->scaler_id, | |
936e71e3 VS |
4824 | drm_rect_width(&plane_state->base.src) >> 16, |
4825 | drm_rect_height(&plane_state->base.src) >> 16, | |
4826 | drm_rect_width(&plane_state->base.dst), | |
4827 | drm_rect_height(&plane_state->base.dst)); | |
86adf9d7 ML |
4828 | |
4829 | if (ret || plane_state->scaler_id < 0) | |
4830 | return ret; | |
4831 | ||
a1b2278e | 4832 | /* check colorkey */ |
818ed961 | 4833 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
72660ce0 VS |
4834 | DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed", |
4835 | intel_plane->base.base.id, | |
4836 | intel_plane->base.name); | |
a1b2278e CK |
4837 | return -EINVAL; |
4838 | } | |
4839 | ||
4840 | /* Check src format */ | |
438b74a5 | 4841 | switch (fb->format->format) { |
86adf9d7 ML |
4842 | case DRM_FORMAT_RGB565: |
4843 | case DRM_FORMAT_XBGR8888: | |
4844 | case DRM_FORMAT_XRGB8888: | |
4845 | case DRM_FORMAT_ABGR8888: | |
4846 | case DRM_FORMAT_ARGB8888: | |
4847 | case DRM_FORMAT_XRGB2101010: | |
4848 | case DRM_FORMAT_XBGR2101010: | |
4849 | case DRM_FORMAT_YUYV: | |
4850 | case DRM_FORMAT_YVYU: | |
4851 | case DRM_FORMAT_UYVY: | |
4852 | case DRM_FORMAT_VYUY: | |
4853 | break; | |
4854 | default: | |
72660ce0 VS |
4855 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", |
4856 | intel_plane->base.base.id, intel_plane->base.name, | |
438b74a5 | 4857 | fb->base.id, fb->format->format); |
86adf9d7 | 4858 | return -EINVAL; |
a1b2278e CK |
4859 | } |
4860 | ||
a1b2278e CK |
4861 | return 0; |
4862 | } | |
4863 | ||
e435d6e5 ML |
4864 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4865 | { | |
4866 | int i; | |
4867 | ||
4868 | for (i = 0; i < crtc->num_scalers; i++) | |
4869 | skl_detach_scaler(crtc, i); | |
4870 | } | |
4871 | ||
4872 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4873 | { |
4874 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4875 | struct drm_i915_private *dev_priv = to_i915(dev); |
bd2e244f | 4876 | int pipe = crtc->pipe; |
a1b2278e CK |
4877 | struct intel_crtc_scaler_state *scaler_state = |
4878 | &crtc->config->scaler_state; | |
4879 | ||
6e3c9717 | 4880 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4881 | int id; |
4882 | ||
c3f8ad57 | 4883 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) |
a1b2278e | 4884 | return; |
a1b2278e CK |
4885 | |
4886 | id = scaler_state->scaler_id; | |
4887 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4888 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4889 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4890 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
bd2e244f JB |
4891 | } |
4892 | } | |
4893 | ||
b074cec8 JB |
4894 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4895 | { | |
4896 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4897 | struct drm_i915_private *dev_priv = to_i915(dev); |
b074cec8 JB |
4898 | int pipe = crtc->pipe; |
4899 | ||
6e3c9717 | 4900 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4901 | /* Force use of hard-coded filter coefficients |
4902 | * as some pre-programmed values are broken, | |
4903 | * e.g. x201. | |
4904 | */ | |
fd6b8f43 | 4905 | if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) |
b074cec8 JB |
4906 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | |
4907 | PF_PIPE_SEL_IVB(pipe)); | |
4908 | else | |
4909 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4910 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4911 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4912 | } |
4913 | } | |
4914 | ||
20bc8673 | 4915 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4916 | { |
cea165c3 | 4917 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4918 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4919 | |
6e3c9717 | 4920 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4921 | return; |
4922 | ||
307e4498 ML |
4923 | /* |
4924 | * We can only enable IPS after we enable a plane and wait for a vblank | |
4925 | * This function is called from post_plane_update, which is run after | |
4926 | * a vblank wait. | |
4927 | */ | |
cea165c3 | 4928 | |
d77e4531 | 4929 | assert_plane_enabled(dev_priv, crtc->plane); |
8652744b | 4930 | if (IS_BROADWELL(dev_priv)) { |
2a114cc1 BW |
4931 | mutex_lock(&dev_priv->rps.hw_lock); |
4932 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4933 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4934 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4935 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4936 | * mailbox." Moreover, the mailbox may return a bogus state, |
4937 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4938 | */ |
4939 | } else { | |
4940 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4941 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4942 | * is essentially intel_wait_for_vblank. If we don't have this | |
4943 | * and don't wait for vblanks until the end of crtc_enable, then | |
4944 | * the HW state readout code will complain that the expected | |
4945 | * IPS_CTL value is not the one we read. */ | |
2ec9ba3c CW |
4946 | if (intel_wait_for_register(dev_priv, |
4947 | IPS_CTL, IPS_ENABLE, IPS_ENABLE, | |
4948 | 50)) | |
2a114cc1 BW |
4949 | DRM_ERROR("Timed out waiting for IPS enable\n"); |
4950 | } | |
d77e4531 PZ |
4951 | } |
4952 | ||
20bc8673 | 4953 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4954 | { |
4955 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4956 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4957 | |
6e3c9717 | 4958 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4959 | return; |
4960 | ||
4961 | assert_plane_enabled(dev_priv, crtc->plane); | |
8652744b | 4962 | if (IS_BROADWELL(dev_priv)) { |
2a114cc1 BW |
4963 | mutex_lock(&dev_priv->rps.hw_lock); |
4964 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4965 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 | 4966 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
b85c1ecf CW |
4967 | if (intel_wait_for_register(dev_priv, |
4968 | IPS_CTL, IPS_ENABLE, 0, | |
4969 | 42)) | |
23d0b130 | 4970 | DRM_ERROR("Timed out waiting for IPS disable\n"); |
e59150dc | 4971 | } else { |
2a114cc1 | 4972 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4973 | POSTING_READ(IPS_CTL); |
4974 | } | |
d77e4531 PZ |
4975 | |
4976 | /* We need to wait for a vblank before we can disable the plane. */ | |
0f0f74bc | 4977 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
d77e4531 PZ |
4978 | } |
4979 | ||
7cac945f | 4980 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4981 | { |
7cac945f | 4982 | if (intel_crtc->overlay) { |
d3eedb1a | 4983 | struct drm_device *dev = intel_crtc->base.dev; |
d3eedb1a VS |
4984 | |
4985 | mutex_lock(&dev->struct_mutex); | |
d3eedb1a | 4986 | (void) intel_overlay_switch_off(intel_crtc->overlay); |
d3eedb1a VS |
4987 | mutex_unlock(&dev->struct_mutex); |
4988 | } | |
4989 | ||
4990 | /* Let userspace switch the overlay on again. In most cases userspace | |
4991 | * has to recompute where to put it anyway. | |
4992 | */ | |
4993 | } | |
4994 | ||
87d4300a ML |
4995 | /** |
4996 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4997 | * @crtc: the CRTC whose primary plane was just enabled | |
4998 | * | |
4999 | * Performs potentially sleeping operations that must be done after the primary | |
5000 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
5001 | * called due to an explicit primary plane update, or due to an implicit | |
5002 | * re-enable that is caused when a sprite plane is updated to no longer | |
5003 | * completely hide the primary plane. | |
5004 | */ | |
5005 | static void | |
5006 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
5007 | { |
5008 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 5009 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
5010 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5011 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 5012 | |
87d4300a ML |
5013 | /* |
5014 | * FIXME IPS should be fine as long as one plane is | |
5015 | * enabled, but in practice it seems to have problems | |
5016 | * when going from primary only to sprite only and vice | |
5017 | * versa. | |
5018 | */ | |
a5c4d7bc VS |
5019 | hsw_enable_ips(intel_crtc); |
5020 | ||
f99d7069 | 5021 | /* |
87d4300a ML |
5022 | * Gen2 reports pipe underruns whenever all planes are disabled. |
5023 | * So don't enable underrun reporting before at least some planes | |
5024 | * are enabled. | |
5025 | * FIXME: Need to fix the logic to work when we turn off all planes | |
5026 | * but leave the pipe running. | |
f99d7069 | 5027 | */ |
5db94019 | 5028 | if (IS_GEN2(dev_priv)) |
87d4300a ML |
5029 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5030 | ||
aca7b684 VS |
5031 | /* Underruns don't always raise interrupts, so check manually. */ |
5032 | intel_check_cpu_fifo_underruns(dev_priv); | |
5033 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
5034 | } |
5035 | ||
2622a081 | 5036 | /* FIXME move all this to pre_plane_update() with proper state tracking */ |
87d4300a ML |
5037 | static void |
5038 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
5039 | { |
5040 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 5041 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
5042 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5043 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 5044 | |
87d4300a ML |
5045 | /* |
5046 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
5047 | * So diasble underrun reporting before all the planes get disabled. | |
5048 | * FIXME: Need to fix the logic to work when we turn off all planes | |
5049 | * but leave the pipe running. | |
5050 | */ | |
5db94019 | 5051 | if (IS_GEN2(dev_priv)) |
87d4300a | 5052 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
a5c4d7bc | 5053 | |
2622a081 VS |
5054 | /* |
5055 | * FIXME IPS should be fine as long as one plane is | |
5056 | * enabled, but in practice it seems to have problems | |
5057 | * when going from primary only to sprite only and vice | |
5058 | * versa. | |
5059 | */ | |
5060 | hsw_disable_ips(intel_crtc); | |
5061 | } | |
5062 | ||
5063 | /* FIXME get rid of this and use pre_plane_update */ | |
5064 | static void | |
5065 | intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) | |
5066 | { | |
5067 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 5068 | struct drm_i915_private *dev_priv = to_i915(dev); |
2622a081 VS |
5069 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5070 | int pipe = intel_crtc->pipe; | |
5071 | ||
5072 | intel_pre_disable_primary(crtc); | |
5073 | ||
87d4300a ML |
5074 | /* |
5075 | * Vblank time updates from the shadow to live plane control register | |
5076 | * are blocked if the memory self-refresh mode is active at that | |
5077 | * moment. So to make sure the plane gets truly disabled, disable | |
5078 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5079 | * will be checked/applied by the HW only at the next frame start | |
5080 | * event which is after the vblank start event, so we need to have a | |
5081 | * wait-for-vblank between disabling the plane and the pipe. | |
5082 | */ | |
11a85d6a VS |
5083 | if (HAS_GMCH_DISPLAY(dev_priv) && |
5084 | intel_set_memory_cxsr(dev_priv, false)) | |
0f0f74bc | 5085 | intel_wait_for_vblank(dev_priv, pipe); |
87d4300a ML |
5086 | } |
5087 | ||
5a21b665 DV |
5088 | static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) |
5089 | { | |
5090 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); | |
5091 | struct drm_atomic_state *old_state = old_crtc_state->base.state; | |
5092 | struct intel_crtc_state *pipe_config = | |
5093 | to_intel_crtc_state(crtc->base.state); | |
5a21b665 DV |
5094 | struct drm_plane *primary = crtc->base.primary; |
5095 | struct drm_plane_state *old_pri_state = | |
5096 | drm_atomic_get_existing_plane_state(old_state, primary); | |
5097 | ||
5748b6a1 | 5098 | intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits); |
5a21b665 | 5099 | |
5a21b665 | 5100 | if (pipe_config->update_wm_post && pipe_config->base.active) |
432081bc | 5101 | intel_update_watermarks(crtc); |
5a21b665 DV |
5102 | |
5103 | if (old_pri_state) { | |
5104 | struct intel_plane_state *primary_state = | |
5105 | to_intel_plane_state(primary->state); | |
5106 | struct intel_plane_state *old_primary_state = | |
5107 | to_intel_plane_state(old_pri_state); | |
5108 | ||
5109 | intel_fbc_post_update(crtc); | |
5110 | ||
936e71e3 | 5111 | if (primary_state->base.visible && |
5a21b665 | 5112 | (needs_modeset(&pipe_config->base) || |
936e71e3 | 5113 | !old_primary_state->base.visible)) |
5a21b665 DV |
5114 | intel_post_enable_primary(&crtc->base); |
5115 | } | |
5116 | } | |
5117 | ||
aa5e9b47 ML |
5118 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state, |
5119 | struct intel_crtc_state *pipe_config) | |
ac21b225 | 5120 | { |
5c74cd73 | 5121 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 5122 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 5123 | struct drm_i915_private *dev_priv = to_i915(dev); |
5c74cd73 ML |
5124 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
5125 | struct drm_plane *primary = crtc->base.primary; | |
5126 | struct drm_plane_state *old_pri_state = | |
5127 | drm_atomic_get_existing_plane_state(old_state, primary); | |
5128 | bool modeset = needs_modeset(&pipe_config->base); | |
ccf010fb ML |
5129 | struct intel_atomic_state *old_intel_state = |
5130 | to_intel_atomic_state(old_state); | |
ac21b225 | 5131 | |
5c74cd73 ML |
5132 | if (old_pri_state) { |
5133 | struct intel_plane_state *primary_state = | |
5134 | to_intel_plane_state(primary->state); | |
5135 | struct intel_plane_state *old_primary_state = | |
5136 | to_intel_plane_state(old_pri_state); | |
5137 | ||
faf68d92 | 5138 | intel_fbc_pre_update(crtc, pipe_config, primary_state); |
31ae71fc | 5139 | |
936e71e3 VS |
5140 | if (old_primary_state->base.visible && |
5141 | (modeset || !primary_state->base.visible)) | |
5c74cd73 ML |
5142 | intel_pre_disable_primary(&crtc->base); |
5143 | } | |
852eb00d | 5144 | |
5eeb798b VS |
5145 | /* |
5146 | * Vblank time updates from the shadow to live plane control register | |
5147 | * are blocked if the memory self-refresh mode is active at that | |
5148 | * moment. So to make sure the plane gets truly disabled, disable | |
5149 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5150 | * will be checked/applied by the HW only at the next frame start | |
5151 | * event which is after the vblank start event, so we need to have a | |
5152 | * wait-for-vblank between disabling the plane and the pipe. | |
5153 | */ | |
5154 | if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active && | |
5155 | pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) | |
5156 | intel_wait_for_vblank(dev_priv, crtc->pipe); | |
92826fcd | 5157 | |
ed4a6a7c MR |
5158 | /* |
5159 | * IVB workaround: must disable low power watermarks for at least | |
5160 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
5161 | * when scaling is disabled. | |
5162 | * | |
5163 | * WaCxSRDisabledForSpriteScaling:ivb | |
5164 | */ | |
ddd2b792 | 5165 | if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev)) |
0f0f74bc | 5166 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
ed4a6a7c MR |
5167 | |
5168 | /* | |
5169 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
5170 | * watermark programming here. | |
5171 | */ | |
5172 | if (needs_modeset(&pipe_config->base)) | |
5173 | return; | |
5174 | ||
5175 | /* | |
5176 | * For platforms that support atomic watermarks, program the | |
5177 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
5178 | * will be the intermediate values that are safe for both pre- and | |
5179 | * post- vblank; when vblank happens, the 'active' values will be set | |
5180 | * to the final 'target' values and we'll do this again to get the | |
5181 | * optimal watermarks. For gen9+ platforms, the values we program here | |
5182 | * will be the final target values which will get automatically latched | |
5183 | * at vblank time; no further programming will be necessary. | |
5184 | * | |
5185 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
5186 | * we'll continue to update watermarks the old way, if flags tell | |
5187 | * us to. | |
5188 | */ | |
5189 | if (dev_priv->display.initial_watermarks != NULL) | |
ccf010fb ML |
5190 | dev_priv->display.initial_watermarks(old_intel_state, |
5191 | pipe_config); | |
caed361d | 5192 | else if (pipe_config->update_wm_pre) |
432081bc | 5193 | intel_update_watermarks(crtc); |
ac21b225 ML |
5194 | } |
5195 | ||
d032ffa0 | 5196 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
5197 | { |
5198 | struct drm_device *dev = crtc->dev; | |
5199 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 5200 | struct drm_plane *p; |
87d4300a ML |
5201 | int pipe = intel_crtc->pipe; |
5202 | ||
7cac945f | 5203 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 5204 | |
d032ffa0 | 5205 | drm_for_each_plane_mask(p, dev, plane_mask) |
282dbf9b | 5206 | to_intel_plane(p)->disable_plane(to_intel_plane(p), intel_crtc); |
f98551ae | 5207 | |
f99d7069 DV |
5208 | /* |
5209 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
5210 | * to compute the mask of flip planes precisely. For the time being | |
5211 | * consider this a flip to a NULL plane. | |
5212 | */ | |
5748b6a1 | 5213 | intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe)); |
a5c4d7bc VS |
5214 | } |
5215 | ||
fb1c98b1 | 5216 | static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc, |
fd6bbda9 | 5217 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5218 | struct drm_atomic_state *old_state) |
5219 | { | |
aa5e9b47 | 5220 | struct drm_connector_state *conn_state; |
fb1c98b1 ML |
5221 | struct drm_connector *conn; |
5222 | int i; | |
5223 | ||
aa5e9b47 | 5224 | for_each_new_connector_in_state(old_state, conn, conn_state, i) { |
fb1c98b1 ML |
5225 | struct intel_encoder *encoder = |
5226 | to_intel_encoder(conn_state->best_encoder); | |
5227 | ||
5228 | if (conn_state->crtc != crtc) | |
5229 | continue; | |
5230 | ||
5231 | if (encoder->pre_pll_enable) | |
fd6bbda9 | 5232 | encoder->pre_pll_enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5233 | } |
5234 | } | |
5235 | ||
5236 | static void intel_encoders_pre_enable(struct drm_crtc *crtc, | |
fd6bbda9 | 5237 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5238 | struct drm_atomic_state *old_state) |
5239 | { | |
aa5e9b47 | 5240 | struct drm_connector_state *conn_state; |
fb1c98b1 ML |
5241 | struct drm_connector *conn; |
5242 | int i; | |
5243 | ||
aa5e9b47 | 5244 | for_each_new_connector_in_state(old_state, conn, conn_state, i) { |
fb1c98b1 ML |
5245 | struct intel_encoder *encoder = |
5246 | to_intel_encoder(conn_state->best_encoder); | |
5247 | ||
5248 | if (conn_state->crtc != crtc) | |
5249 | continue; | |
5250 | ||
5251 | if (encoder->pre_enable) | |
fd6bbda9 | 5252 | encoder->pre_enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5253 | } |
5254 | } | |
5255 | ||
5256 | static void intel_encoders_enable(struct drm_crtc *crtc, | |
fd6bbda9 | 5257 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5258 | struct drm_atomic_state *old_state) |
5259 | { | |
aa5e9b47 | 5260 | struct drm_connector_state *conn_state; |
fb1c98b1 ML |
5261 | struct drm_connector *conn; |
5262 | int i; | |
5263 | ||
aa5e9b47 | 5264 | for_each_new_connector_in_state(old_state, conn, conn_state, i) { |
fb1c98b1 ML |
5265 | struct intel_encoder *encoder = |
5266 | to_intel_encoder(conn_state->best_encoder); | |
5267 | ||
5268 | if (conn_state->crtc != crtc) | |
5269 | continue; | |
5270 | ||
fd6bbda9 | 5271 | encoder->enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5272 | intel_opregion_notify_encoder(encoder, true); |
5273 | } | |
5274 | } | |
5275 | ||
5276 | static void intel_encoders_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5277 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5278 | struct drm_atomic_state *old_state) |
5279 | { | |
5280 | struct drm_connector_state *old_conn_state; | |
5281 | struct drm_connector *conn; | |
5282 | int i; | |
5283 | ||
aa5e9b47 | 5284 | for_each_old_connector_in_state(old_state, conn, old_conn_state, i) { |
fb1c98b1 ML |
5285 | struct intel_encoder *encoder = |
5286 | to_intel_encoder(old_conn_state->best_encoder); | |
5287 | ||
5288 | if (old_conn_state->crtc != crtc) | |
5289 | continue; | |
5290 | ||
5291 | intel_opregion_notify_encoder(encoder, false); | |
fd6bbda9 | 5292 | encoder->disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5293 | } |
5294 | } | |
5295 | ||
5296 | static void intel_encoders_post_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5297 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5298 | struct drm_atomic_state *old_state) |
5299 | { | |
5300 | struct drm_connector_state *old_conn_state; | |
5301 | struct drm_connector *conn; | |
5302 | int i; | |
5303 | ||
aa5e9b47 | 5304 | for_each_old_connector_in_state(old_state, conn, old_conn_state, i) { |
fb1c98b1 ML |
5305 | struct intel_encoder *encoder = |
5306 | to_intel_encoder(old_conn_state->best_encoder); | |
5307 | ||
5308 | if (old_conn_state->crtc != crtc) | |
5309 | continue; | |
5310 | ||
5311 | if (encoder->post_disable) | |
fd6bbda9 | 5312 | encoder->post_disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5313 | } |
5314 | } | |
5315 | ||
5316 | static void intel_encoders_post_pll_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5317 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5318 | struct drm_atomic_state *old_state) |
5319 | { | |
5320 | struct drm_connector_state *old_conn_state; | |
5321 | struct drm_connector *conn; | |
5322 | int i; | |
5323 | ||
aa5e9b47 | 5324 | for_each_old_connector_in_state(old_state, conn, old_conn_state, i) { |
fb1c98b1 ML |
5325 | struct intel_encoder *encoder = |
5326 | to_intel_encoder(old_conn_state->best_encoder); | |
5327 | ||
5328 | if (old_conn_state->crtc != crtc) | |
5329 | continue; | |
5330 | ||
5331 | if (encoder->post_pll_disable) | |
fd6bbda9 | 5332 | encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5333 | } |
5334 | } | |
5335 | ||
4a806558 ML |
5336 | static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config, |
5337 | struct drm_atomic_state *old_state) | |
f67a559d | 5338 | { |
4a806558 | 5339 | struct drm_crtc *crtc = pipe_config->base.crtc; |
f67a559d | 5340 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5341 | struct drm_i915_private *dev_priv = to_i915(dev); |
f67a559d JB |
5342 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5343 | int pipe = intel_crtc->pipe; | |
ccf010fb ML |
5344 | struct intel_atomic_state *old_intel_state = |
5345 | to_intel_atomic_state(old_state); | |
f67a559d | 5346 | |
53d9f4e9 | 5347 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
5348 | return; |
5349 | ||
b2c0593a VS |
5350 | /* |
5351 | * Sometimes spurious CPU pipe underruns happen during FDI | |
5352 | * training, at least with VGA+HDMI cloning. Suppress them. | |
5353 | * | |
5354 | * On ILK we get an occasional spurious CPU pipe underruns | |
5355 | * between eDP port A enable and vdd enable. Also PCH port | |
5356 | * enable seems to result in the occasional CPU pipe underrun. | |
5357 | * | |
5358 | * Spurious PCH underruns also occur during PCH enabling. | |
5359 | */ | |
5360 | if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv)) | |
5361 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
81b088ca VS |
5362 | if (intel_crtc->config->has_pch_encoder) |
5363 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
5364 | ||
6e3c9717 | 5365 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
5366 | intel_prepare_shared_dpll(intel_crtc); |
5367 | ||
37a5650b | 5368 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5369 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
5370 | |
5371 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 5372 | intel_set_pipe_src_size(intel_crtc); |
29407aab | 5373 | |
6e3c9717 | 5374 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 5375 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5376 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
5377 | } |
5378 | ||
5379 | ironlake_set_pipeconf(crtc); | |
5380 | ||
f67a559d | 5381 | intel_crtc->active = true; |
8664281b | 5382 | |
fd6bbda9 | 5383 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
f67a559d | 5384 | |
6e3c9717 | 5385 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
5386 | /* Note: FDI PLL enabling _must_ be done before we enable the |
5387 | * cpu pipes, hence this is separate from all the other fdi/pch | |
5388 | * enabling. */ | |
88cefb6c | 5389 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
5390 | } else { |
5391 | assert_fdi_tx_disabled(dev_priv, pipe); | |
5392 | assert_fdi_rx_disabled(dev_priv, pipe); | |
5393 | } | |
f67a559d | 5394 | |
b074cec8 | 5395 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 5396 | |
9c54c0dd JB |
5397 | /* |
5398 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5399 | * clocks enabled | |
5400 | */ | |
b95c5321 | 5401 | intel_color_load_luts(&pipe_config->base); |
9c54c0dd | 5402 | |
1d5bf5d9 | 5403 | if (dev_priv->display.initial_watermarks != NULL) |
ccf010fb | 5404 | dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config); |
e1fdc473 | 5405 | intel_enable_pipe(intel_crtc); |
f67a559d | 5406 | |
6e3c9717 | 5407 | if (intel_crtc->config->has_pch_encoder) |
2ce42273 | 5408 | ironlake_pch_enable(pipe_config); |
c98e9dcf | 5409 | |
f9b61ff6 DV |
5410 | assert_vblank_disabled(crtc); |
5411 | drm_crtc_vblank_on(crtc); | |
5412 | ||
fd6bbda9 | 5413 | intel_encoders_enable(crtc, pipe_config, old_state); |
61b77ddd | 5414 | |
6e266956 | 5415 | if (HAS_PCH_CPT(dev_priv)) |
a1520318 | 5416 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
5417 | |
5418 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
5419 | if (intel_crtc->config->has_pch_encoder) | |
0f0f74bc | 5420 | intel_wait_for_vblank(dev_priv, pipe); |
b2c0593a | 5421 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
37ca8d4c | 5422 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 JB |
5423 | } |
5424 | ||
42db64ef PZ |
5425 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
5426 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
5427 | { | |
50a0bc90 | 5428 | return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A; |
42db64ef PZ |
5429 | } |
5430 | ||
4a806558 ML |
5431 | static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, |
5432 | struct drm_atomic_state *old_state) | |
4f771f10 | 5433 | { |
4a806558 | 5434 | struct drm_crtc *crtc = pipe_config->base.crtc; |
6315b5d3 | 5435 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
4f771f10 | 5436 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
99d736a2 | 5437 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4d1de975 | 5438 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ccf010fb ML |
5439 | struct intel_atomic_state *old_intel_state = |
5440 | to_intel_atomic_state(old_state); | |
4f771f10 | 5441 | |
53d9f4e9 | 5442 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
5443 | return; |
5444 | ||
81b088ca | 5445 | if (intel_crtc->config->has_pch_encoder) |
29012159 | 5446 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); |
81b088ca | 5447 | |
fd6bbda9 | 5448 | intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); |
95a7a2ae | 5449 | |
8106ddbd | 5450 | if (intel_crtc->config->shared_dpll) |
df8ad70c DV |
5451 | intel_enable_shared_dpll(intel_crtc); |
5452 | ||
37a5650b | 5453 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5454 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 | 5455 | |
d7edc4e5 | 5456 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5457 | intel_set_pipe_timings(intel_crtc); |
5458 | ||
bc58be60 | 5459 | intel_set_pipe_src_size(intel_crtc); |
229fca97 | 5460 | |
4d1de975 JN |
5461 | if (cpu_transcoder != TRANSCODER_EDP && |
5462 | !transcoder_is_dsi(cpu_transcoder)) { | |
5463 | I915_WRITE(PIPE_MULT(cpu_transcoder), | |
6e3c9717 | 5464 | intel_crtc->config->pixel_multiplier - 1); |
ebb69c95 CT |
5465 | } |
5466 | ||
6e3c9717 | 5467 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 5468 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5469 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
5470 | } |
5471 | ||
d7edc4e5 | 5472 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5473 | haswell_set_pipeconf(crtc); |
5474 | ||
391bf048 | 5475 | haswell_set_pipemisc(crtc); |
229fca97 | 5476 | |
b95c5321 | 5477 | intel_color_set_csc(&pipe_config->base); |
229fca97 | 5478 | |
4f771f10 | 5479 | intel_crtc->active = true; |
8664281b | 5480 | |
6b698516 DV |
5481 | if (intel_crtc->config->has_pch_encoder) |
5482 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5483 | else | |
5484 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5485 | ||
fd6bbda9 | 5486 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
4f771f10 | 5487 | |
d2d65408 | 5488 | if (intel_crtc->config->has_pch_encoder) |
dc4a1094 | 5489 | dev_priv->display.fdi_link_train(intel_crtc, pipe_config); |
4fe9467d | 5490 | |
d7edc4e5 | 5491 | if (!transcoder_is_dsi(cpu_transcoder)) |
3dc38eea | 5492 | intel_ddi_enable_pipe_clock(pipe_config); |
4f771f10 | 5493 | |
6315b5d3 | 5494 | if (INTEL_GEN(dev_priv) >= 9) |
e435d6e5 | 5495 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 5496 | else |
1c132b44 | 5497 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
5498 | |
5499 | /* | |
5500 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5501 | * clocks enabled | |
5502 | */ | |
b95c5321 | 5503 | intel_color_load_luts(&pipe_config->base); |
4f771f10 | 5504 | |
3dc38eea | 5505 | intel_ddi_set_pipe_settings(pipe_config); |
d7edc4e5 | 5506 | if (!transcoder_is_dsi(cpu_transcoder)) |
3dc38eea | 5507 | intel_ddi_enable_transcoder_func(pipe_config); |
4f771f10 | 5508 | |
1d5bf5d9 | 5509 | if (dev_priv->display.initial_watermarks != NULL) |
3125d39f | 5510 | dev_priv->display.initial_watermarks(old_intel_state, pipe_config); |
4d1de975 JN |
5511 | |
5512 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ | |
d7edc4e5 | 5513 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5514 | intel_enable_pipe(intel_crtc); |
42db64ef | 5515 | |
6e3c9717 | 5516 | if (intel_crtc->config->has_pch_encoder) |
2ce42273 | 5517 | lpt_pch_enable(pipe_config); |
4f771f10 | 5518 | |
0037071d | 5519 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST)) |
3dc38eea | 5520 | intel_ddi_set_vc_payload_alloc(pipe_config, true); |
0e32b39c | 5521 | |
f9b61ff6 DV |
5522 | assert_vblank_disabled(crtc); |
5523 | drm_crtc_vblank_on(crtc); | |
5524 | ||
fd6bbda9 | 5525 | intel_encoders_enable(crtc, pipe_config, old_state); |
4f771f10 | 5526 | |
6b698516 | 5527 | if (intel_crtc->config->has_pch_encoder) { |
0f0f74bc VS |
5528 | intel_wait_for_vblank(dev_priv, pipe); |
5529 | intel_wait_for_vblank(dev_priv, pipe); | |
6b698516 | 5530 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
29012159 | 5531 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
6b698516 | 5532 | } |
d2d65408 | 5533 | |
e4916946 PZ |
5534 | /* If we change the relative order between pipe/planes enabling, we need |
5535 | * to change the workaround. */ | |
99d736a2 | 5536 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
772c2a51 | 5537 | if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { |
0f0f74bc VS |
5538 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); |
5539 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); | |
99d736a2 | 5540 | } |
4f771f10 PZ |
5541 | } |
5542 | ||
bfd16b2a | 5543 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
5544 | { |
5545 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5546 | struct drm_i915_private *dev_priv = to_i915(dev); |
3f8dce3a DV |
5547 | int pipe = crtc->pipe; |
5548 | ||
5549 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5550 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5551 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5552 | I915_WRITE(PF_CTL(pipe), 0); |
5553 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5554 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5555 | } | |
5556 | } | |
5557 | ||
4a806558 ML |
5558 | static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5559 | struct drm_atomic_state *old_state) | |
6be4a607 | 5560 | { |
4a806558 | 5561 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
6be4a607 | 5562 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5563 | struct drm_i915_private *dev_priv = to_i915(dev); |
6be4a607 JB |
5564 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5565 | int pipe = intel_crtc->pipe; | |
b52eb4dc | 5566 | |
b2c0593a VS |
5567 | /* |
5568 | * Sometimes spurious CPU pipe underruns happen when the | |
5569 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
5570 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
5571 | */ | |
5572 | if (intel_crtc->config->has_pch_encoder) { | |
5573 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
37ca8d4c | 5574 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
b2c0593a | 5575 | } |
37ca8d4c | 5576 | |
fd6bbda9 | 5577 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
ea9d758d | 5578 | |
f9b61ff6 DV |
5579 | drm_crtc_vblank_off(crtc); |
5580 | assert_vblank_disabled(crtc); | |
5581 | ||
575f7ab7 | 5582 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5583 | |
bfd16b2a | 5584 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5585 | |
b2c0593a | 5586 | if (intel_crtc->config->has_pch_encoder) |
5a74f70a VS |
5587 | ironlake_fdi_disable(crtc); |
5588 | ||
fd6bbda9 | 5589 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
2c07245f | 5590 | |
6e3c9717 | 5591 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5592 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5593 | |
6e266956 | 5594 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 VS |
5595 | i915_reg_t reg; |
5596 | u32 temp; | |
5597 | ||
d925c59a DV |
5598 | /* disable TRANS_DP_CTL */ |
5599 | reg = TRANS_DP_CTL(pipe); | |
5600 | temp = I915_READ(reg); | |
5601 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5602 | TRANS_DP_PORT_SEL_MASK); | |
5603 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5604 | I915_WRITE(reg, temp); | |
5605 | ||
5606 | /* disable DPLL_SEL */ | |
5607 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5608 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5609 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5610 | } |
e3421a18 | 5611 | |
d925c59a DV |
5612 | ironlake_fdi_pll_disable(intel_crtc); |
5613 | } | |
81b088ca | 5614 | |
b2c0593a | 5615 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
81b088ca | 5616 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 | 5617 | } |
1b3c7a47 | 5618 | |
4a806558 ML |
5619 | static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5620 | struct drm_atomic_state *old_state) | |
ee7b9f93 | 5621 | { |
4a806558 | 5622 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
6315b5d3 | 5623 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee7b9f93 | 5624 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 5625 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5626 | |
d2d65408 | 5627 | if (intel_crtc->config->has_pch_encoder) |
29012159 | 5628 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); |
d2d65408 | 5629 | |
fd6bbda9 | 5630 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
4f771f10 | 5631 | |
f9b61ff6 DV |
5632 | drm_crtc_vblank_off(crtc); |
5633 | assert_vblank_disabled(crtc); | |
5634 | ||
4d1de975 | 5635 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ |
d7edc4e5 | 5636 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5637 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5638 | |
0037071d | 5639 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST)) |
3dc38eea | 5640 | intel_ddi_set_vc_payload_alloc(intel_crtc->config, false); |
a4bf214f | 5641 | |
d7edc4e5 | 5642 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5643 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5644 | |
6315b5d3 | 5645 | if (INTEL_GEN(dev_priv) >= 9) |
e435d6e5 | 5646 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5647 | else |
bfd16b2a | 5648 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5649 | |
d7edc4e5 | 5650 | if (!transcoder_is_dsi(cpu_transcoder)) |
3dc38eea | 5651 | intel_ddi_disable_pipe_clock(intel_crtc->config); |
4f771f10 | 5652 | |
fd6bbda9 | 5653 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
81b088ca | 5654 | |
b7076546 | 5655 | if (old_crtc_state->has_pch_encoder) |
29012159 | 5656 | intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); |
4f771f10 PZ |
5657 | } |
5658 | ||
2dd24552 JB |
5659 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5660 | { | |
5661 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5662 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 5663 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5664 | |
681a8504 | 5665 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5666 | return; |
5667 | ||
2dd24552 | 5668 | /* |
c0b03411 DV |
5669 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5670 | * according to register description and PRM. | |
2dd24552 | 5671 | */ |
c0b03411 DV |
5672 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5673 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5674 | |
b074cec8 JB |
5675 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5676 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5677 | |
5678 | /* Border color in case we don't scale up to the full screen. Black by | |
5679 | * default, change to something else for debugging. */ | |
5680 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5681 | } |
5682 | ||
79f255a0 | 5683 | enum intel_display_power_domain intel_port_to_power_domain(enum port port) |
d05410f9 DA |
5684 | { |
5685 | switch (port) { | |
5686 | case PORT_A: | |
6331a704 | 5687 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5688 | case PORT_B: |
6331a704 | 5689 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5690 | case PORT_C: |
6331a704 | 5691 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5692 | case PORT_D: |
6331a704 | 5693 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5694 | case PORT_E: |
6331a704 | 5695 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5696 | default: |
b9fec167 | 5697 | MISSING_CASE(port); |
d05410f9 DA |
5698 | return POWER_DOMAIN_PORT_OTHER; |
5699 | } | |
5700 | } | |
5701 | ||
d8fc70b7 ACO |
5702 | static u64 get_crtc_power_domains(struct drm_crtc *crtc, |
5703 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5704 | { |
319be8ae | 5705 | struct drm_device *dev = crtc->dev; |
37255d8d | 5706 | struct drm_i915_private *dev_priv = to_i915(dev); |
74bff5f9 | 5707 | struct drm_encoder *encoder; |
319be8ae ID |
5708 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5709 | enum pipe pipe = intel_crtc->pipe; | |
d8fc70b7 | 5710 | u64 mask; |
74bff5f9 | 5711 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 5712 | |
74bff5f9 | 5713 | if (!crtc_state->base.active) |
292b990e ML |
5714 | return 0; |
5715 | ||
77d22dca ID |
5716 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5717 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
5718 | if (crtc_state->pch_pfit.enabled || |
5719 | crtc_state->pch_pfit.force_thru) | |
d8fc70b7 | 5720 | mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
77d22dca | 5721 | |
74bff5f9 ML |
5722 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
5723 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5724 | ||
79f255a0 | 5725 | mask |= BIT_ULL(intel_encoder->power_domain); |
74bff5f9 | 5726 | } |
319be8ae | 5727 | |
37255d8d ML |
5728 | if (HAS_DDI(dev_priv) && crtc_state->has_audio) |
5729 | mask |= BIT(POWER_DOMAIN_AUDIO); | |
5730 | ||
15e7ec29 | 5731 | if (crtc_state->shared_dpll) |
d8fc70b7 | 5732 | mask |= BIT_ULL(POWER_DOMAIN_PLLS); |
15e7ec29 | 5733 | |
77d22dca ID |
5734 | return mask; |
5735 | } | |
5736 | ||
d2d15016 | 5737 | static u64 |
74bff5f9 ML |
5738 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, |
5739 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5740 | { |
fac5e23e | 5741 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
292b990e ML |
5742 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5743 | enum intel_display_power_domain domain; | |
d8fc70b7 | 5744 | u64 domains, new_domains, old_domains; |
77d22dca | 5745 | |
292b990e | 5746 | old_domains = intel_crtc->enabled_power_domains; |
74bff5f9 ML |
5747 | intel_crtc->enabled_power_domains = new_domains = |
5748 | get_crtc_power_domains(crtc, crtc_state); | |
77d22dca | 5749 | |
5a21b665 | 5750 | domains = new_domains & ~old_domains; |
292b990e ML |
5751 | |
5752 | for_each_power_domain(domain, domains) | |
5753 | intel_display_power_get(dev_priv, domain); | |
5754 | ||
5a21b665 | 5755 | return old_domains & ~new_domains; |
292b990e ML |
5756 | } |
5757 | ||
5758 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
d8fc70b7 | 5759 | u64 domains) |
292b990e ML |
5760 | { |
5761 | enum intel_display_power_domain domain; | |
5762 | ||
5763 | for_each_power_domain(domain, domains) | |
5764 | intel_display_power_put(dev_priv, domain); | |
5765 | } | |
77d22dca | 5766 | |
7ff89ca2 VS |
5767 | static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config, |
5768 | struct drm_atomic_state *old_state) | |
adafdc6f | 5769 | { |
ff32c54e VS |
5770 | struct intel_atomic_state *old_intel_state = |
5771 | to_intel_atomic_state(old_state); | |
7ff89ca2 VS |
5772 | struct drm_crtc *crtc = pipe_config->base.crtc; |
5773 | struct drm_device *dev = crtc->dev; | |
5774 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5775 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5776 | int pipe = intel_crtc->pipe; | |
adafdc6f | 5777 | |
7ff89ca2 VS |
5778 | if (WARN_ON(intel_crtc->active)) |
5779 | return; | |
adafdc6f | 5780 | |
7ff89ca2 VS |
5781 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
5782 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
b2045352 | 5783 | |
7ff89ca2 VS |
5784 | intel_set_pipe_timings(intel_crtc); |
5785 | intel_set_pipe_src_size(intel_crtc); | |
b2045352 | 5786 | |
7ff89ca2 VS |
5787 | if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { |
5788 | struct drm_i915_private *dev_priv = to_i915(dev); | |
560a7ae4 | 5789 | |
7ff89ca2 VS |
5790 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); |
5791 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
560a7ae4 DL |
5792 | } |
5793 | ||
7ff89ca2 | 5794 | i9xx_set_pipeconf(intel_crtc); |
560a7ae4 | 5795 | |
7ff89ca2 | 5796 | intel_crtc->active = true; |
92891e45 | 5797 | |
7ff89ca2 | 5798 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5f199dfa | 5799 | |
7ff89ca2 | 5800 | intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); |
5f199dfa | 5801 | |
7ff89ca2 VS |
5802 | if (IS_CHERRYVIEW(dev_priv)) { |
5803 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
5804 | chv_enable_pll(intel_crtc, intel_crtc->config); | |
5805 | } else { | |
5806 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
5807 | vlv_enable_pll(intel_crtc, intel_crtc->config); | |
5f199dfa VS |
5808 | } |
5809 | ||
7ff89ca2 | 5810 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
5f199dfa | 5811 | |
7ff89ca2 | 5812 | i9xx_pfit_enable(intel_crtc); |
89b3c3c7 | 5813 | |
7ff89ca2 | 5814 | intel_color_load_luts(&pipe_config->base); |
89b3c3c7 | 5815 | |
ff32c54e VS |
5816 | dev_priv->display.initial_watermarks(old_intel_state, |
5817 | pipe_config); | |
7ff89ca2 VS |
5818 | intel_enable_pipe(intel_crtc); |
5819 | ||
5820 | assert_vblank_disabled(crtc); | |
5821 | drm_crtc_vblank_on(crtc); | |
89b3c3c7 | 5822 | |
7ff89ca2 | 5823 | intel_encoders_enable(crtc, pipe_config, old_state); |
89b3c3c7 ACO |
5824 | } |
5825 | ||
7ff89ca2 | 5826 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
2b73001e | 5827 | { |
7ff89ca2 VS |
5828 | struct drm_device *dev = crtc->base.dev; |
5829 | struct drm_i915_private *dev_priv = to_i915(dev); | |
83d7c81f | 5830 | |
7ff89ca2 VS |
5831 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
5832 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
2b73001e VS |
5833 | } |
5834 | ||
7ff89ca2 VS |
5835 | static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config, |
5836 | struct drm_atomic_state *old_state) | |
2b73001e | 5837 | { |
04548cba VS |
5838 | struct intel_atomic_state *old_intel_state = |
5839 | to_intel_atomic_state(old_state); | |
7ff89ca2 VS |
5840 | struct drm_crtc *crtc = pipe_config->base.crtc; |
5841 | struct drm_device *dev = crtc->dev; | |
5842 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5843 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5844 | enum pipe pipe = intel_crtc->pipe; | |
2b73001e | 5845 | |
7ff89ca2 VS |
5846 | if (WARN_ON(intel_crtc->active)) |
5847 | return; | |
2b73001e | 5848 | |
7ff89ca2 | 5849 | i9xx_set_pll_dividers(intel_crtc); |
2b73001e | 5850 | |
7ff89ca2 VS |
5851 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
5852 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
83d7c81f | 5853 | |
7ff89ca2 VS |
5854 | intel_set_pipe_timings(intel_crtc); |
5855 | intel_set_pipe_src_size(intel_crtc); | |
2b73001e | 5856 | |
7ff89ca2 | 5857 | i9xx_set_pipeconf(intel_crtc); |
f8437dd1 | 5858 | |
7ff89ca2 | 5859 | intel_crtc->active = true; |
5f199dfa | 5860 | |
7ff89ca2 VS |
5861 | if (!IS_GEN2(dev_priv)) |
5862 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5f199dfa | 5863 | |
7ff89ca2 | 5864 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
f8437dd1 | 5865 | |
7ff89ca2 | 5866 | i9xx_enable_pll(intel_crtc); |
f8437dd1 | 5867 | |
7ff89ca2 | 5868 | i9xx_pfit_enable(intel_crtc); |
f8437dd1 | 5869 | |
7ff89ca2 | 5870 | intel_color_load_luts(&pipe_config->base); |
f8437dd1 | 5871 | |
04548cba VS |
5872 | if (dev_priv->display.initial_watermarks != NULL) |
5873 | dev_priv->display.initial_watermarks(old_intel_state, | |
5874 | intel_crtc->config); | |
5875 | else | |
5876 | intel_update_watermarks(intel_crtc); | |
7ff89ca2 | 5877 | intel_enable_pipe(intel_crtc); |
f8437dd1 | 5878 | |
7ff89ca2 VS |
5879 | assert_vblank_disabled(crtc); |
5880 | drm_crtc_vblank_on(crtc); | |
f8437dd1 | 5881 | |
7ff89ca2 VS |
5882 | intel_encoders_enable(crtc, pipe_config, old_state); |
5883 | } | |
f8437dd1 | 5884 | |
7ff89ca2 VS |
5885 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
5886 | { | |
5887 | struct drm_device *dev = crtc->base.dev; | |
5888 | struct drm_i915_private *dev_priv = to_i915(dev); | |
f8437dd1 | 5889 | |
7ff89ca2 | 5890 | if (!crtc->config->gmch_pfit.control) |
f8437dd1 | 5891 | return; |
f8437dd1 | 5892 | |
7ff89ca2 VS |
5893 | assert_pipe_disabled(dev_priv, crtc->pipe); |
5894 | ||
5895 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", | |
5896 | I915_READ(PFIT_CONTROL)); | |
5897 | I915_WRITE(PFIT_CONTROL, 0); | |
f8437dd1 VK |
5898 | } |
5899 | ||
7ff89ca2 VS |
5900 | static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5901 | struct drm_atomic_state *old_state) | |
f8437dd1 | 5902 | { |
7ff89ca2 VS |
5903 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
5904 | struct drm_device *dev = crtc->dev; | |
5905 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5906 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5907 | int pipe = intel_crtc->pipe; | |
d66a2194 | 5908 | |
d66a2194 | 5909 | /* |
7ff89ca2 VS |
5910 | * On gen2 planes are double buffered but the pipe isn't, so we must |
5911 | * wait for planes to fully turn off before disabling the pipe. | |
d66a2194 | 5912 | */ |
7ff89ca2 VS |
5913 | if (IS_GEN2(dev_priv)) |
5914 | intel_wait_for_vblank(dev_priv, pipe); | |
d66a2194 | 5915 | |
7ff89ca2 | 5916 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
d66a2194 | 5917 | |
7ff89ca2 VS |
5918 | drm_crtc_vblank_off(crtc); |
5919 | assert_vblank_disabled(crtc); | |
d66a2194 | 5920 | |
7ff89ca2 | 5921 | intel_disable_pipe(intel_crtc); |
d66a2194 | 5922 | |
7ff89ca2 | 5923 | i9xx_pfit_disable(intel_crtc); |
89b3c3c7 | 5924 | |
7ff89ca2 | 5925 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
d66a2194 | 5926 | |
7ff89ca2 VS |
5927 | if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) { |
5928 | if (IS_CHERRYVIEW(dev_priv)) | |
5929 | chv_disable_pll(dev_priv, pipe); | |
5930 | else if (IS_VALLEYVIEW(dev_priv)) | |
5931 | vlv_disable_pll(dev_priv, pipe); | |
5932 | else | |
5933 | i9xx_disable_pll(intel_crtc); | |
5934 | } | |
c2e001ef | 5935 | |
7ff89ca2 | 5936 | intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state); |
89b3c3c7 | 5937 | |
7ff89ca2 VS |
5938 | if (!IS_GEN2(dev_priv)) |
5939 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
ff32c54e VS |
5940 | |
5941 | if (!dev_priv->display.initial_watermarks) | |
5942 | intel_update_watermarks(intel_crtc); | |
2ee0da16 VS |
5943 | |
5944 | /* clock the pipe down to 640x480@60 to potentially save power */ | |
5945 | if (IS_I830(dev_priv)) | |
5946 | i830_enable_pipe(dev_priv, pipe); | |
f8437dd1 VK |
5947 | } |
5948 | ||
da1d0e26 VS |
5949 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc, |
5950 | struct drm_modeset_acquire_ctx *ctx) | |
f8437dd1 | 5951 | { |
7ff89ca2 VS |
5952 | struct intel_encoder *encoder; |
5953 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5954 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
5955 | enum intel_display_power_domain domain; | |
d2d15016 | 5956 | u64 domains; |
7ff89ca2 VS |
5957 | struct drm_atomic_state *state; |
5958 | struct intel_crtc_state *crtc_state; | |
5959 | int ret; | |
f8437dd1 | 5960 | |
7ff89ca2 VS |
5961 | if (!intel_crtc->active) |
5962 | return; | |
a8ca4934 | 5963 | |
7ff89ca2 | 5964 | if (crtc->primary->state->visible) { |
7ff89ca2 | 5965 | intel_pre_disable_primary_noatomic(crtc); |
709e05c3 | 5966 | |
7ff89ca2 VS |
5967 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); |
5968 | crtc->primary->state->visible = false; | |
5969 | } | |
5d96d8af | 5970 | |
7ff89ca2 VS |
5971 | state = drm_atomic_state_alloc(crtc->dev); |
5972 | if (!state) { | |
5973 | DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory", | |
5974 | crtc->base.id, crtc->name); | |
1c3f7700 | 5975 | return; |
7ff89ca2 | 5976 | } |
9f7eb31a | 5977 | |
da1d0e26 | 5978 | state->acquire_ctx = ctx; |
ea61791e | 5979 | |
7ff89ca2 VS |
5980 | /* Everything's already locked, -EDEADLK can't happen. */ |
5981 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); | |
5982 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
9f7eb31a | 5983 | |
7ff89ca2 | 5984 | WARN_ON(IS_ERR(crtc_state) || ret); |
5d96d8af | 5985 | |
7ff89ca2 | 5986 | dev_priv->display.crtc_disable(crtc_state, state); |
4a806558 | 5987 | |
0853695c | 5988 | drm_atomic_state_put(state); |
842e0307 | 5989 | |
78108b7c VS |
5990 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", |
5991 | crtc->base.id, crtc->name); | |
842e0307 ML |
5992 | |
5993 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0); | |
5994 | crtc->state->active = false; | |
37d9078b | 5995 | intel_crtc->active = false; |
842e0307 ML |
5996 | crtc->enabled = false; |
5997 | crtc->state->connector_mask = 0; | |
5998 | crtc->state->encoder_mask = 0; | |
5999 | ||
6000 | for_each_encoder_on_crtc(crtc->dev, crtc, encoder) | |
6001 | encoder->base.crtc = NULL; | |
6002 | ||
58f9c0bc | 6003 | intel_fbc_disable(intel_crtc); |
432081bc | 6004 | intel_update_watermarks(intel_crtc); |
1f7457b1 | 6005 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6006 | |
6007 | domains = intel_crtc->enabled_power_domains; | |
6008 | for_each_power_domain(domain, domains) | |
6009 | intel_display_power_put(dev_priv, domain); | |
6010 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
6011 | |
6012 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
6013 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
6014 | } |
6015 | ||
6b72d486 ML |
6016 | /* |
6017 | * turn all crtc's off, but do not adjust state | |
6018 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6019 | */ | |
70e0bd74 | 6020 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6021 | { |
e2c8b870 | 6022 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 6023 | struct drm_atomic_state *state; |
e2c8b870 | 6024 | int ret; |
70e0bd74 | 6025 | |
e2c8b870 ML |
6026 | state = drm_atomic_helper_suspend(dev); |
6027 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
6028 | if (ret) |
6029 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
6030 | else |
6031 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 6032 | return ret; |
ee7b9f93 JB |
6033 | } |
6034 | ||
ea5b213a | 6035 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6036 | { |
4ef69c7a | 6037 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6038 | |
ea5b213a CW |
6039 | drm_encoder_cleanup(encoder); |
6040 | kfree(intel_encoder); | |
7e7d76c3 JB |
6041 | } |
6042 | ||
0a91ca29 DV |
6043 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6044 | * internal consistency). */ | |
749d98b8 ML |
6045 | static void intel_connector_verify_state(struct drm_crtc_state *crtc_state, |
6046 | struct drm_connector_state *conn_state) | |
79e53945 | 6047 | { |
749d98b8 | 6048 | struct intel_connector *connector = to_intel_connector(conn_state->connector); |
35dd3c64 ML |
6049 | |
6050 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6051 | connector->base.base.id, | |
6052 | connector->base.name); | |
6053 | ||
0a91ca29 | 6054 | if (connector->get_hw_state(connector)) { |
e85376cb | 6055 | struct intel_encoder *encoder = connector->encoder; |
0a91ca29 | 6056 | |
749d98b8 | 6057 | I915_STATE_WARN(!crtc_state, |
35dd3c64 | 6058 | "connector enabled without attached crtc\n"); |
0a91ca29 | 6059 | |
749d98b8 | 6060 | if (!crtc_state) |
35dd3c64 ML |
6061 | return; |
6062 | ||
749d98b8 | 6063 | I915_STATE_WARN(!crtc_state->active, |
35dd3c64 ML |
6064 | "connector is active, but attached crtc isn't\n"); |
6065 | ||
e85376cb | 6066 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6067 | return; |
6068 | ||
e85376cb | 6069 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6070 | "atomic encoder doesn't match attached encoder\n"); |
6071 | ||
e85376cb | 6072 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6073 | "attached encoder crtc differs from connector crtc\n"); |
6074 | } else { | |
749d98b8 | 6075 | I915_STATE_WARN(crtc_state && crtc_state->active, |
4d688a2a | 6076 | "attached crtc is active, but connector isn't\n"); |
749d98b8 | 6077 | I915_STATE_WARN(!crtc_state && conn_state->best_encoder, |
35dd3c64 | 6078 | "best encoder set without crtc!\n"); |
0a91ca29 | 6079 | } |
79e53945 JB |
6080 | } |
6081 | ||
08d9bc92 ACO |
6082 | int intel_connector_init(struct intel_connector *connector) |
6083 | { | |
11c1a9ec | 6084 | struct intel_digital_connector_state *conn_state; |
08d9bc92 | 6085 | |
11c1a9ec ML |
6086 | /* |
6087 | * Allocate enough memory to hold intel_digital_connector_state, | |
6088 | * This might be a few bytes too many, but for connectors that don't | |
6089 | * need it we'll free the state and allocate a smaller one on the first | |
6090 | * succesful commit anyway. | |
6091 | */ | |
6092 | conn_state = kzalloc(sizeof(*conn_state), GFP_KERNEL); | |
6093 | if (!conn_state) | |
08d9bc92 ACO |
6094 | return -ENOMEM; |
6095 | ||
11c1a9ec ML |
6096 | __drm_atomic_helper_connector_reset(&connector->base, |
6097 | &conn_state->base); | |
6098 | ||
08d9bc92 ACO |
6099 | return 0; |
6100 | } | |
6101 | ||
6102 | struct intel_connector *intel_connector_alloc(void) | |
6103 | { | |
6104 | struct intel_connector *connector; | |
6105 | ||
6106 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6107 | if (!connector) | |
6108 | return NULL; | |
6109 | ||
6110 | if (intel_connector_init(connector) < 0) { | |
6111 | kfree(connector); | |
6112 | return NULL; | |
6113 | } | |
6114 | ||
6115 | return connector; | |
6116 | } | |
6117 | ||
f0947c37 DV |
6118 | /* Simple connector->get_hw_state implementation for encoders that support only |
6119 | * one connector and no cloning and hence the encoder state determines the state | |
6120 | * of the connector. */ | |
6121 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6122 | { |
24929352 | 6123 | enum pipe pipe = 0; |
f0947c37 | 6124 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6125 | |
f0947c37 | 6126 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6127 | } |
6128 | ||
6d293983 | 6129 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6130 | { |
6d293983 ACO |
6131 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6132 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6133 | |
6134 | return 0; | |
6135 | } | |
6136 | ||
6d293983 | 6137 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6138 | struct intel_crtc_state *pipe_config) |
1857e1da | 6139 | { |
8652744b | 6140 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d293983 ACO |
6141 | struct drm_atomic_state *state = pipe_config->base.state; |
6142 | struct intel_crtc *other_crtc; | |
6143 | struct intel_crtc_state *other_crtc_state; | |
6144 | ||
1857e1da DV |
6145 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6146 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6147 | if (pipe_config->fdi_lanes > 4) { | |
6148 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6149 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6150 | return -EINVAL; |
1857e1da DV |
6151 | } |
6152 | ||
8652744b | 6153 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
1857e1da DV |
6154 | if (pipe_config->fdi_lanes > 2) { |
6155 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6156 | pipe_config->fdi_lanes); | |
6d293983 | 6157 | return -EINVAL; |
1857e1da | 6158 | } else { |
6d293983 | 6159 | return 0; |
1857e1da DV |
6160 | } |
6161 | } | |
6162 | ||
b7f05d4a | 6163 | if (INTEL_INFO(dev_priv)->num_pipes == 2) |
6d293983 | 6164 | return 0; |
1857e1da DV |
6165 | |
6166 | /* Ivybridge 3 pipe is really complicated */ | |
6167 | switch (pipe) { | |
6168 | case PIPE_A: | |
6d293983 | 6169 | return 0; |
1857e1da | 6170 | case PIPE_B: |
6d293983 ACO |
6171 | if (pipe_config->fdi_lanes <= 2) |
6172 | return 0; | |
6173 | ||
b91eb5cc | 6174 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C); |
6d293983 ACO |
6175 | other_crtc_state = |
6176 | intel_atomic_get_crtc_state(state, other_crtc); | |
6177 | if (IS_ERR(other_crtc_state)) | |
6178 | return PTR_ERR(other_crtc_state); | |
6179 | ||
6180 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6181 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6182 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6183 | return -EINVAL; |
1857e1da | 6184 | } |
6d293983 | 6185 | return 0; |
1857e1da | 6186 | case PIPE_C: |
251cc67c VS |
6187 | if (pipe_config->fdi_lanes > 2) { |
6188 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6189 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6190 | return -EINVAL; |
251cc67c | 6191 | } |
6d293983 | 6192 | |
b91eb5cc | 6193 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B); |
6d293983 ACO |
6194 | other_crtc_state = |
6195 | intel_atomic_get_crtc_state(state, other_crtc); | |
6196 | if (IS_ERR(other_crtc_state)) | |
6197 | return PTR_ERR(other_crtc_state); | |
6198 | ||
6199 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6200 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6201 | return -EINVAL; |
1857e1da | 6202 | } |
6d293983 | 6203 | return 0; |
1857e1da DV |
6204 | default: |
6205 | BUG(); | |
6206 | } | |
6207 | } | |
6208 | ||
e29c22c0 DV |
6209 | #define RETRY 1 |
6210 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6211 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6212 | { |
1857e1da | 6213 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6214 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6215 | int lane, link_bw, fdi_dotclock, ret; |
6216 | bool needs_recompute = false; | |
877d48d5 | 6217 | |
e29c22c0 | 6218 | retry: |
877d48d5 DV |
6219 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6220 | * each output octet as 10 bits. The actual frequency | |
6221 | * is stored as a divider into a 100MHz clock, and the | |
6222 | * mode pixel clock is stored in units of 1KHz. | |
6223 | * Hence the bw of each lane in terms of the mode signal | |
6224 | * is: | |
6225 | */ | |
21a727b3 | 6226 | link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); |
877d48d5 | 6227 | |
241bfc38 | 6228 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6229 | |
2bd89a07 | 6230 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6231 | pipe_config->pipe_bpp); |
6232 | ||
6233 | pipe_config->fdi_lanes = lane; | |
6234 | ||
2bd89a07 | 6235 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
b31e85ed | 6236 | link_bw, &pipe_config->fdi_m_n, false); |
1857e1da | 6237 | |
e3b247da | 6238 | ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
6d293983 | 6239 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
e29c22c0 | 6240 | pipe_config->pipe_bpp -= 2*3; |
7ff89ca2 VS |
6241 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", |
6242 | pipe_config->pipe_bpp); | |
6243 | needs_recompute = true; | |
6244 | pipe_config->bw_constrained = true; | |
257a7ffc | 6245 | |
7ff89ca2 | 6246 | goto retry; |
257a7ffc | 6247 | } |
79e53945 | 6248 | |
7ff89ca2 VS |
6249 | if (needs_recompute) |
6250 | return RETRY; | |
e70236a8 | 6251 | |
7ff89ca2 | 6252 | return ret; |
e70236a8 JB |
6253 | } |
6254 | ||
7ff89ca2 VS |
6255 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6256 | struct intel_crtc_state *pipe_config) | |
e70236a8 | 6257 | { |
7ff89ca2 VS |
6258 | if (pipe_config->pipe_bpp > 24) |
6259 | return false; | |
e70236a8 | 6260 | |
7ff89ca2 VS |
6261 | /* HSW can handle pixel rate up to cdclk? */ |
6262 | if (IS_HASWELL(dev_priv)) | |
6263 | return true; | |
1b1d2716 | 6264 | |
65cd2b3f | 6265 | /* |
7ff89ca2 VS |
6266 | * We compare against max which means we must take |
6267 | * the increased cdclk requirement into account when | |
6268 | * calculating the new cdclk. | |
6269 | * | |
6270 | * Should measure whether using a lower cdclk w/o IPS | |
e70236a8 | 6271 | */ |
7ff89ca2 VS |
6272 | return pipe_config->pixel_rate <= |
6273 | dev_priv->max_cdclk_freq * 95 / 100; | |
e70236a8 | 6274 | } |
79e53945 | 6275 | |
7ff89ca2 VS |
6276 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
6277 | struct intel_crtc_state *pipe_config) | |
6278 | { | |
6279 | struct drm_device *dev = crtc->base.dev; | |
6280 | struct drm_i915_private *dev_priv = to_i915(dev); | |
34edce2f | 6281 | |
7ff89ca2 VS |
6282 | pipe_config->ips_enabled = i915.enable_ips && |
6283 | hsw_crtc_supports_ips(crtc) && | |
6284 | pipe_config_supports_ips(dev_priv, pipe_config); | |
34edce2f VS |
6285 | } |
6286 | ||
7ff89ca2 | 6287 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
34edce2f | 6288 | { |
7ff89ca2 | 6289 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
34edce2f | 6290 | |
7ff89ca2 VS |
6291 | /* GDG double wide on either pipe, otherwise pipe A only */ |
6292 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6293 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
34edce2f VS |
6294 | } |
6295 | ||
ceb99320 VS |
6296 | static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) |
6297 | { | |
6298 | uint32_t pixel_rate; | |
6299 | ||
6300 | pixel_rate = pipe_config->base.adjusted_mode.crtc_clock; | |
6301 | ||
6302 | /* | |
6303 | * We only use IF-ID interlacing. If we ever use | |
6304 | * PF-ID we'll need to adjust the pixel_rate here. | |
6305 | */ | |
6306 | ||
6307 | if (pipe_config->pch_pfit.enabled) { | |
6308 | uint64_t pipe_w, pipe_h, pfit_w, pfit_h; | |
6309 | uint32_t pfit_size = pipe_config->pch_pfit.size; | |
6310 | ||
6311 | pipe_w = pipe_config->pipe_src_w; | |
6312 | pipe_h = pipe_config->pipe_src_h; | |
6313 | ||
6314 | pfit_w = (pfit_size >> 16) & 0xFFFF; | |
6315 | pfit_h = pfit_size & 0xFFFF; | |
6316 | if (pipe_w < pfit_w) | |
6317 | pipe_w = pfit_w; | |
6318 | if (pipe_h < pfit_h) | |
6319 | pipe_h = pfit_h; | |
6320 | ||
6321 | if (WARN_ON(!pfit_w || !pfit_h)) | |
6322 | return pixel_rate; | |
6323 | ||
6324 | pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, | |
6325 | pfit_w * pfit_h); | |
6326 | } | |
6327 | ||
6328 | return pixel_rate; | |
6329 | } | |
6330 | ||
7ff89ca2 | 6331 | static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) |
34edce2f | 6332 | { |
7ff89ca2 | 6333 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); |
34edce2f | 6334 | |
7ff89ca2 VS |
6335 | if (HAS_GMCH_DISPLAY(dev_priv)) |
6336 | /* FIXME calculate proper pipe pixel rate for GMCH pfit */ | |
6337 | crtc_state->pixel_rate = | |
6338 | crtc_state->base.adjusted_mode.crtc_clock; | |
6339 | else | |
6340 | crtc_state->pixel_rate = | |
6341 | ilk_pipe_pixel_rate(crtc_state); | |
6342 | } | |
34edce2f | 6343 | |
7ff89ca2 VS |
6344 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
6345 | struct intel_crtc_state *pipe_config) | |
6346 | { | |
6347 | struct drm_device *dev = crtc->base.dev; | |
6348 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6349 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; | |
6350 | int clock_limit = dev_priv->max_dotclk_freq; | |
34edce2f | 6351 | |
7ff89ca2 VS |
6352 | if (INTEL_GEN(dev_priv) < 4) { |
6353 | clock_limit = dev_priv->max_cdclk_freq * 9 / 10; | |
34edce2f | 6354 | |
7ff89ca2 VS |
6355 | /* |
6356 | * Enable double wide mode when the dot clock | |
6357 | * is > 90% of the (display) core speed. | |
6358 | */ | |
6359 | if (intel_crtc_supports_double_wide(crtc) && | |
6360 | adjusted_mode->crtc_clock > clock_limit) { | |
6361 | clock_limit = dev_priv->max_dotclk_freq; | |
6362 | pipe_config->double_wide = true; | |
6363 | } | |
34edce2f VS |
6364 | } |
6365 | ||
7ff89ca2 VS |
6366 | if (adjusted_mode->crtc_clock > clock_limit) { |
6367 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6368 | adjusted_mode->crtc_clock, clock_limit, | |
6369 | yesno(pipe_config->double_wide)); | |
6370 | return -EINVAL; | |
6371 | } | |
34edce2f | 6372 | |
25edf915 SS |
6373 | if (pipe_config->ycbcr420 && pipe_config->base.ctm) { |
6374 | /* | |
6375 | * There is only one pipe CSC unit per pipe, and we need that | |
6376 | * for output conversion from RGB->YCBCR. So if CTM is already | |
6377 | * applied we can't support YCBCR420 output. | |
6378 | */ | |
6379 | DRM_DEBUG_KMS("YCBCR420 and CTM together are not possible\n"); | |
6380 | return -EINVAL; | |
6381 | } | |
6382 | ||
7ff89ca2 VS |
6383 | /* |
6384 | * Pipe horizontal size must be even in: | |
6385 | * - DVO ganged mode | |
6386 | * - LVDS dual channel mode | |
6387 | * - Double wide pipe | |
6388 | */ | |
6389 | if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) && | |
6390 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) | |
6391 | pipe_config->pipe_src_w &= ~1; | |
34edce2f | 6392 | |
7ff89ca2 VS |
6393 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6394 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
6395 | */ | |
6396 | if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) && | |
6397 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) | |
6398 | return -EINVAL; | |
34edce2f | 6399 | |
7ff89ca2 | 6400 | intel_crtc_compute_pixel_rate(pipe_config); |
34edce2f | 6401 | |
7ff89ca2 VS |
6402 | if (HAS_IPS(dev_priv)) |
6403 | hsw_compute_ips_config(crtc, pipe_config); | |
34edce2f | 6404 | |
7ff89ca2 VS |
6405 | if (pipe_config->has_pch_encoder) |
6406 | return ironlake_fdi_compute_config(crtc, pipe_config); | |
34edce2f | 6407 | |
7ff89ca2 | 6408 | return 0; |
34edce2f VS |
6409 | } |
6410 | ||
2c07245f | 6411 | static void |
a65851af | 6412 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 6413 | { |
a65851af VS |
6414 | while (*num > DATA_LINK_M_N_MASK || |
6415 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
6416 | *num >>= 1; |
6417 | *den >>= 1; | |
6418 | } | |
6419 | } | |
6420 | ||
a65851af | 6421 | static void compute_m_n(unsigned int m, unsigned int n, |
b31e85ed JN |
6422 | uint32_t *ret_m, uint32_t *ret_n, |
6423 | bool reduce_m_n) | |
a65851af | 6424 | { |
9a86cda0 JN |
6425 | /* |
6426 | * Reduce M/N as much as possible without loss in precision. Several DP | |
6427 | * dongles in particular seem to be fussy about too large *link* M/N | |
6428 | * values. The passed in values are more likely to have the least | |
6429 | * significant bits zero than M after rounding below, so do this first. | |
6430 | */ | |
b31e85ed JN |
6431 | if (reduce_m_n) { |
6432 | while ((m & 1) == 0 && (n & 1) == 0) { | |
6433 | m >>= 1; | |
6434 | n >>= 1; | |
6435 | } | |
9a86cda0 JN |
6436 | } |
6437 | ||
a65851af VS |
6438 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); |
6439 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
6440 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
6441 | } | |
6442 | ||
e69d0bc1 DV |
6443 | void |
6444 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
6445 | int pixel_clock, int link_clock, | |
b31e85ed JN |
6446 | struct intel_link_m_n *m_n, |
6447 | bool reduce_m_n) | |
2c07245f | 6448 | { |
e69d0bc1 | 6449 | m_n->tu = 64; |
a65851af VS |
6450 | |
6451 | compute_m_n(bits_per_pixel * pixel_clock, | |
6452 | link_clock * nlanes * 8, | |
b31e85ed JN |
6453 | &m_n->gmch_m, &m_n->gmch_n, |
6454 | reduce_m_n); | |
a65851af VS |
6455 | |
6456 | compute_m_n(pixel_clock, link_clock, | |
b31e85ed JN |
6457 | &m_n->link_m, &m_n->link_n, |
6458 | reduce_m_n); | |
2c07245f ZW |
6459 | } |
6460 | ||
a7615030 CW |
6461 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
6462 | { | |
d330a953 JN |
6463 | if (i915.panel_use_ssc >= 0) |
6464 | return i915.panel_use_ssc != 0; | |
41aa3448 | 6465 | return dev_priv->vbt.lvds_use_ssc |
435793df | 6466 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
6467 | } |
6468 | ||
7429e9d4 | 6469 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 6470 | { |
7df00d7a | 6471 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 6472 | } |
f47709a9 | 6473 | |
7429e9d4 DV |
6474 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
6475 | { | |
6476 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
6477 | } |
6478 | ||
f47709a9 | 6479 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 6480 | struct intel_crtc_state *crtc_state, |
9e2c8475 | 6481 | struct dpll *reduced_clock) |
a7516a05 | 6482 | { |
9b1e14f4 | 6483 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
a7516a05 JB |
6484 | u32 fp, fp2 = 0; |
6485 | ||
9b1e14f4 | 6486 | if (IS_PINEVIEW(dev_priv)) { |
190f68c5 | 6487 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6488 | if (reduced_clock) |
7429e9d4 | 6489 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 6490 | } else { |
190f68c5 | 6491 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6492 | if (reduced_clock) |
7429e9d4 | 6493 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
6494 | } |
6495 | ||
190f68c5 | 6496 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 6497 | |
f47709a9 | 6498 | crtc->lowfreq_avail = false; |
2d84d2b3 | 6499 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 6500 | reduced_clock) { |
190f68c5 | 6501 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 6502 | crtc->lowfreq_avail = true; |
a7516a05 | 6503 | } else { |
190f68c5 | 6504 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
6505 | } |
6506 | } | |
6507 | ||
5e69f97f CML |
6508 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
6509 | pipe) | |
89b667f8 JB |
6510 | { |
6511 | u32 reg_val; | |
6512 | ||
6513 | /* | |
6514 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
6515 | * and set it to a reasonable value instead. | |
6516 | */ | |
ab3c759a | 6517 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
6518 | reg_val &= 0xffffff00; |
6519 | reg_val |= 0x00000030; | |
ab3c759a | 6520 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6521 | |
ab3c759a | 6522 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
ed58570f ID |
6523 | reg_val &= 0x00ffffff; |
6524 | reg_val |= 0x8c000000; | |
ab3c759a | 6525 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 6526 | |
ab3c759a | 6527 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 6528 | reg_val &= 0xffffff00; |
ab3c759a | 6529 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6530 | |
ab3c759a | 6531 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6532 | reg_val &= 0x00ffffff; |
6533 | reg_val |= 0xb0000000; | |
ab3c759a | 6534 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
6535 | } |
6536 | ||
b551842d DV |
6537 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
6538 | struct intel_link_m_n *m_n) | |
6539 | { | |
6540 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6541 | struct drm_i915_private *dev_priv = to_i915(dev); |
b551842d DV |
6542 | int pipe = crtc->pipe; |
6543 | ||
e3b95f1e DV |
6544 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6545 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
6546 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
6547 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
6548 | } |
6549 | ||
6550 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
6551 | struct intel_link_m_n *m_n, |
6552 | struct intel_link_m_n *m2_n2) | |
b551842d | 6553 | { |
6315b5d3 | 6554 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
b551842d | 6555 | int pipe = crtc->pipe; |
6e3c9717 | 6556 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d | 6557 | |
6315b5d3 | 6558 | if (INTEL_GEN(dev_priv) >= 5) { |
b551842d DV |
6559 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6560 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
6561 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
6562 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
6563 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
6564 | * for gen < 8) and if DRRS is supported (to make sure the | |
6565 | * registers are not unnecessarily accessed). | |
6566 | */ | |
920a14b2 TU |
6567 | if (m2_n2 && (IS_CHERRYVIEW(dev_priv) || |
6568 | INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) { | |
f769cd24 VK |
6569 | I915_WRITE(PIPE_DATA_M2(transcoder), |
6570 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
6571 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
6572 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
6573 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
6574 | } | |
b551842d | 6575 | } else { |
e3b95f1e DV |
6576 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6577 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
6578 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
6579 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
6580 | } |
6581 | } | |
6582 | ||
fe3cd48d | 6583 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 6584 | { |
fe3cd48d R |
6585 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
6586 | ||
6587 | if (m_n == M1_N1) { | |
6588 | dp_m_n = &crtc->config->dp_m_n; | |
6589 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
6590 | } else if (m_n == M2_N2) { | |
6591 | ||
6592 | /* | |
6593 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
6594 | * needs to be programmed into M1_N1. | |
6595 | */ | |
6596 | dp_m_n = &crtc->config->dp_m2_n2; | |
6597 | } else { | |
6598 | DRM_ERROR("Unsupported divider value\n"); | |
6599 | return; | |
6600 | } | |
6601 | ||
6e3c9717 ACO |
6602 | if (crtc->config->has_pch_encoder) |
6603 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 6604 | else |
fe3cd48d | 6605 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
6606 | } |
6607 | ||
251ac862 DV |
6608 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
6609 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 | 6610 | { |
03ed5cbf | 6611 | pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | |
cd2d34d9 | 6612 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
6613 | if (crtc->pipe != PIPE_A) |
6614 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
bdd4b6a6 | 6615 | |
cd2d34d9 | 6616 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 6617 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
6618 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | |
6619 | DPLL_EXT_BUFFER_ENABLE_VLV; | |
6620 | ||
03ed5cbf VS |
6621 | pipe_config->dpll_hw_state.dpll_md = |
6622 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
6623 | } | |
bdd4b6a6 | 6624 | |
03ed5cbf VS |
6625 | static void chv_compute_dpll(struct intel_crtc *crtc, |
6626 | struct intel_crtc_state *pipe_config) | |
6627 | { | |
6628 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | | |
cd2d34d9 | 6629 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
6630 | if (crtc->pipe != PIPE_A) |
6631 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
6632 | ||
cd2d34d9 | 6633 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 6634 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
6635 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; |
6636 | ||
03ed5cbf VS |
6637 | pipe_config->dpll_hw_state.dpll_md = |
6638 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
bdd4b6a6 DV |
6639 | } |
6640 | ||
d288f65f | 6641 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6642 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 6643 | { |
f47709a9 | 6644 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6645 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 6646 | enum pipe pipe = crtc->pipe; |
bdd4b6a6 | 6647 | u32 mdiv; |
a0c4da24 | 6648 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 6649 | u32 coreclk, reg_val; |
a0c4da24 | 6650 | |
cd2d34d9 VS |
6651 | /* Enable Refclk */ |
6652 | I915_WRITE(DPLL(pipe), | |
6653 | pipe_config->dpll_hw_state.dpll & | |
6654 | ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); | |
6655 | ||
6656 | /* No need to actually set up the DPLL with DSI */ | |
6657 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
6658 | return; | |
6659 | ||
a580516d | 6660 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 6661 | |
d288f65f VS |
6662 | bestn = pipe_config->dpll.n; |
6663 | bestm1 = pipe_config->dpll.m1; | |
6664 | bestm2 = pipe_config->dpll.m2; | |
6665 | bestp1 = pipe_config->dpll.p1; | |
6666 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 6667 | |
89b667f8 JB |
6668 | /* See eDP HDMI DPIO driver vbios notes doc */ |
6669 | ||
6670 | /* PLL B needs special handling */ | |
bdd4b6a6 | 6671 | if (pipe == PIPE_B) |
5e69f97f | 6672 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
6673 | |
6674 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 6675 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
6676 | |
6677 | /* Disable target IRef on PLL */ | |
ab3c759a | 6678 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 6679 | reg_val &= 0x00ffffff; |
ab3c759a | 6680 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
6681 | |
6682 | /* Disable fast lock */ | |
ab3c759a | 6683 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
6684 | |
6685 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
6686 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
6687 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
6688 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 6689 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
6690 | |
6691 | /* | |
6692 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
6693 | * but we don't support that). | |
6694 | * Note: don't use the DAC post divider as it seems unstable. | |
6695 | */ | |
6696 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 6697 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6698 | |
a0c4da24 | 6699 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 6700 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6701 | |
89b667f8 | 6702 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 6703 | if (pipe_config->port_clock == 162000 || |
2d84d2b3 VS |
6704 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) || |
6705 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 6706 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 6707 | 0x009f0003); |
89b667f8 | 6708 | else |
ab3c759a | 6709 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
6710 | 0x00d0000f); |
6711 | ||
37a5650b | 6712 | if (intel_crtc_has_dp_encoder(pipe_config)) { |
89b667f8 | 6713 | /* Use SSC source */ |
bdd4b6a6 | 6714 | if (pipe == PIPE_A) |
ab3c759a | 6715 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6716 | 0x0df40000); |
6717 | else | |
ab3c759a | 6718 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6719 | 0x0df70000); |
6720 | } else { /* HDMI or VGA */ | |
6721 | /* Use bend source */ | |
bdd4b6a6 | 6722 | if (pipe == PIPE_A) |
ab3c759a | 6723 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6724 | 0x0df70000); |
6725 | else | |
ab3c759a | 6726 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6727 | 0x0df40000); |
6728 | } | |
a0c4da24 | 6729 | |
ab3c759a | 6730 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 6731 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
2210ce7f | 6732 | if (intel_crtc_has_dp_encoder(crtc->config)) |
89b667f8 | 6733 | coreclk |= 0x01000000; |
ab3c759a | 6734 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 6735 | |
ab3c759a | 6736 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 6737 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
6738 | } |
6739 | ||
d288f65f | 6740 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6741 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
6742 | { |
6743 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6744 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 6745 | enum pipe pipe = crtc->pipe; |
9d556c99 | 6746 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 6747 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 6748 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 6749 | u32 dpio_val; |
9cbe40c1 | 6750 | int vco; |
9d556c99 | 6751 | |
cd2d34d9 VS |
6752 | /* Enable Refclk and SSC */ |
6753 | I915_WRITE(DPLL(pipe), | |
6754 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
6755 | ||
6756 | /* No need to actually set up the DPLL with DSI */ | |
6757 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
6758 | return; | |
6759 | ||
d288f65f VS |
6760 | bestn = pipe_config->dpll.n; |
6761 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
6762 | bestm1 = pipe_config->dpll.m1; | |
6763 | bestm2 = pipe_config->dpll.m2 >> 22; | |
6764 | bestp1 = pipe_config->dpll.p1; | |
6765 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 6766 | vco = pipe_config->dpll.vco; |
a945ce7e | 6767 | dpio_val = 0; |
9cbe40c1 | 6768 | loopfilter = 0; |
9d556c99 | 6769 | |
a580516d | 6770 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 6771 | |
9d556c99 CML |
6772 | /* p1 and p2 divider */ |
6773 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
6774 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
6775 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
6776 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
6777 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
6778 | ||
6779 | /* Feedback post-divider - m2 */ | |
6780 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
6781 | ||
6782 | /* Feedback refclk divider - n and m1 */ | |
6783 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
6784 | DPIO_CHV_M1_DIV_BY_2 | | |
6785 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
6786 | ||
6787 | /* M2 fraction division */ | |
25a25dfc | 6788 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
6789 | |
6790 | /* M2 fraction division enable */ | |
a945ce7e VP |
6791 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
6792 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
6793 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
6794 | if (bestm2_frac) | |
6795 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
6796 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 6797 | |
de3a0fde VP |
6798 | /* Program digital lock detect threshold */ |
6799 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
6800 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
6801 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
6802 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
6803 | if (!bestm2_frac) | |
6804 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
6805 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
6806 | ||
9d556c99 | 6807 | /* Loop filter */ |
9cbe40c1 VP |
6808 | if (vco == 5400000) { |
6809 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6810 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
6811 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6812 | tribuf_calcntr = 0x9; | |
6813 | } else if (vco <= 6200000) { | |
6814 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6815 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
6816 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6817 | tribuf_calcntr = 0x9; | |
6818 | } else if (vco <= 6480000) { | |
6819 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6820 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6821 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6822 | tribuf_calcntr = 0x8; | |
6823 | } else { | |
6824 | /* Not supported. Apply the same limits as in the max case */ | |
6825 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6826 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6827 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6828 | tribuf_calcntr = 0; | |
6829 | } | |
9d556c99 CML |
6830 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
6831 | ||
968040b2 | 6832 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
6833 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
6834 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
6835 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
6836 | ||
9d556c99 CML |
6837 | /* AFC Recal */ |
6838 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
6839 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
6840 | DPIO_AFC_RECAL); | |
6841 | ||
a580516d | 6842 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
6843 | } |
6844 | ||
d288f65f VS |
6845 | /** |
6846 | * vlv_force_pll_on - forcibly enable just the PLL | |
6847 | * @dev_priv: i915 private structure | |
6848 | * @pipe: pipe PLL to enable | |
6849 | * @dpll: PLL configuration | |
6850 | * | |
6851 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
6852 | * in cases where we need the PLL enabled even when @pipe is not going to | |
6853 | * be enabled. | |
6854 | */ | |
30ad9814 | 6855 | int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, |
3f36b937 | 6856 | const struct dpll *dpll) |
d288f65f | 6857 | { |
b91eb5cc | 6858 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
3f36b937 TU |
6859 | struct intel_crtc_state *pipe_config; |
6860 | ||
6861 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
6862 | if (!pipe_config) | |
6863 | return -ENOMEM; | |
6864 | ||
6865 | pipe_config->base.crtc = &crtc->base; | |
6866 | pipe_config->pixel_multiplier = 1; | |
6867 | pipe_config->dpll = *dpll; | |
d288f65f | 6868 | |
30ad9814 | 6869 | if (IS_CHERRYVIEW(dev_priv)) { |
3f36b937 TU |
6870 | chv_compute_dpll(crtc, pipe_config); |
6871 | chv_prepare_pll(crtc, pipe_config); | |
6872 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 6873 | } else { |
3f36b937 TU |
6874 | vlv_compute_dpll(crtc, pipe_config); |
6875 | vlv_prepare_pll(crtc, pipe_config); | |
6876 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 6877 | } |
3f36b937 TU |
6878 | |
6879 | kfree(pipe_config); | |
6880 | ||
6881 | return 0; | |
d288f65f VS |
6882 | } |
6883 | ||
6884 | /** | |
6885 | * vlv_force_pll_off - forcibly disable just the PLL | |
6886 | * @dev_priv: i915 private structure | |
6887 | * @pipe: pipe PLL to disable | |
6888 | * | |
6889 | * Disable the PLL for @pipe. To be used in cases where we need | |
6890 | * the PLL enabled even when @pipe is not going to be enabled. | |
6891 | */ | |
30ad9814 | 6892 | void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe) |
d288f65f | 6893 | { |
30ad9814 VS |
6894 | if (IS_CHERRYVIEW(dev_priv)) |
6895 | chv_disable_pll(dev_priv, pipe); | |
d288f65f | 6896 | else |
30ad9814 | 6897 | vlv_disable_pll(dev_priv, pipe); |
d288f65f VS |
6898 | } |
6899 | ||
251ac862 DV |
6900 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
6901 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 6902 | struct dpll *reduced_clock) |
eb1cbe48 | 6903 | { |
9b1e14f4 | 6904 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
eb1cbe48 | 6905 | u32 dpll; |
190f68c5 | 6906 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 6907 | |
190f68c5 | 6908 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 6909 | |
eb1cbe48 DV |
6910 | dpll = DPLL_VGA_MODE_DIS; |
6911 | ||
2d84d2b3 | 6912 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
6913 | dpll |= DPLLB_MODE_LVDS; |
6914 | else | |
6915 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 6916 | |
73f67aa8 JN |
6917 | if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || |
6918 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { | |
190f68c5 | 6919 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 6920 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 6921 | } |
198a037f | 6922 | |
3d6e9ee0 VS |
6923 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
6924 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 6925 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 6926 | |
37a5650b | 6927 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 6928 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
6929 | |
6930 | /* compute bitmask from p1 value */ | |
9b1e14f4 | 6931 | if (IS_PINEVIEW(dev_priv)) |
eb1cbe48 DV |
6932 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
6933 | else { | |
6934 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
9beb5fea | 6935 | if (IS_G4X(dev_priv) && reduced_clock) |
eb1cbe48 DV |
6936 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
6937 | } | |
6938 | switch (clock->p2) { | |
6939 | case 5: | |
6940 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6941 | break; | |
6942 | case 7: | |
6943 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
6944 | break; | |
6945 | case 10: | |
6946 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
6947 | break; | |
6948 | case 14: | |
6949 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
6950 | break; | |
6951 | } | |
9b1e14f4 | 6952 | if (INTEL_GEN(dev_priv) >= 4) |
eb1cbe48 DV |
6953 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
6954 | ||
190f68c5 | 6955 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 6956 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
2d84d2b3 | 6957 | else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 6958 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
6959 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
6960 | else | |
6961 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6962 | ||
6963 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 6964 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 6965 | |
9b1e14f4 | 6966 | if (INTEL_GEN(dev_priv) >= 4) { |
190f68c5 | 6967 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 6968 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 6969 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
6970 | } |
6971 | } | |
6972 | ||
251ac862 DV |
6973 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
6974 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 6975 | struct dpll *reduced_clock) |
eb1cbe48 | 6976 | { |
f47709a9 | 6977 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6978 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb1cbe48 | 6979 | u32 dpll; |
190f68c5 | 6980 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 6981 | |
190f68c5 | 6982 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 6983 | |
eb1cbe48 DV |
6984 | dpll = DPLL_VGA_MODE_DIS; |
6985 | ||
2d84d2b3 | 6986 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
6987 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
6988 | } else { | |
6989 | if (clock->p1 == 2) | |
6990 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
6991 | else | |
6992 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
6993 | if (clock->p2 == 4) | |
6994 | dpll |= PLL_P2_DIVIDE_BY_4; | |
6995 | } | |
6996 | ||
50a0bc90 TU |
6997 | if (!IS_I830(dev_priv) && |
6998 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) | |
4a33e48d DV |
6999 | dpll |= DPLL_DVO_2X_MODE; |
7000 | ||
2d84d2b3 | 7001 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 7002 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
7003 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
7004 | else | |
7005 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7006 | ||
7007 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7008 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7009 | } |
7010 | ||
8a654f3b | 7011 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c | 7012 | { |
6315b5d3 | 7013 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
b0e77b9c | 7014 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 7015 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 7016 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7017 | uint32_t crtc_vtotal, crtc_vblank_end; |
7018 | int vsyncshift = 0; | |
4d8a62ea DV |
7019 | |
7020 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7021 | * the hw state checker will get angry at the mismatch. */ | |
7022 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7023 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7024 | |
609aeaca | 7025 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7026 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7027 | crtc_vtotal -= 1; |
7028 | crtc_vblank_end -= 1; | |
609aeaca | 7029 | |
2d84d2b3 | 7030 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7031 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7032 | else | |
7033 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7034 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7035 | if (vsyncshift < 0) |
7036 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7037 | } |
7038 | ||
6315b5d3 | 7039 | if (INTEL_GEN(dev_priv) > 3) |
fe2b8f9d | 7040 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7041 | |
fe2b8f9d | 7042 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7043 | (adjusted_mode->crtc_hdisplay - 1) | |
7044 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7045 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7046 | (adjusted_mode->crtc_hblank_start - 1) | |
7047 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7048 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7049 | (adjusted_mode->crtc_hsync_start - 1) | |
7050 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7051 | ||
fe2b8f9d | 7052 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7053 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7054 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7055 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7056 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7057 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7058 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7059 | (adjusted_mode->crtc_vsync_start - 1) | |
7060 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7061 | ||
b5e508d4 PZ |
7062 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7063 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7064 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7065 | * bits. */ | |
772c2a51 | 7066 | if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && |
b5e508d4 PZ |
7067 | (pipe == PIPE_B || pipe == PIPE_C)) |
7068 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7069 | ||
bc58be60 JN |
7070 | } |
7071 | ||
7072 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) | |
7073 | { | |
7074 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 7075 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 JN |
7076 | enum pipe pipe = intel_crtc->pipe; |
7077 | ||
b0e77b9c PZ |
7078 | /* pipesrc controls the size that is scaled from, which should |
7079 | * always be the user's requested size. | |
7080 | */ | |
7081 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7082 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7083 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7084 | } |
7085 | ||
1bd1bd80 | 7086 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7087 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7088 | { |
7089 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7090 | struct drm_i915_private *dev_priv = to_i915(dev); |
1bd1bd80 DV |
7091 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
7092 | uint32_t tmp; | |
7093 | ||
7094 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7095 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7096 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7097 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7098 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7099 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7100 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7101 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7102 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7103 | |
7104 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7105 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7106 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7107 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7108 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7109 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7110 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7111 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7112 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7113 | |
7114 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7115 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7116 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7117 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 | 7118 | } |
bc58be60 JN |
7119 | } |
7120 | ||
7121 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, | |
7122 | struct intel_crtc_state *pipe_config) | |
7123 | { | |
7124 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7125 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 | 7126 | u32 tmp; |
1bd1bd80 DV |
7127 | |
7128 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7129 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7130 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7131 | ||
2d112de7 ACO |
7132 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7133 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7134 | } |
7135 | ||
f6a83288 | 7136 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7137 | struct intel_crtc_state *pipe_config) |
babea61d | 7138 | { |
2d112de7 ACO |
7139 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7140 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7141 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7142 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7143 | |
2d112de7 ACO |
7144 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7145 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7146 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7147 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7148 | |
2d112de7 | 7149 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7150 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7151 | |
2d112de7 | 7152 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
cd13f5ab ML |
7153 | |
7154 | mode->hsync = drm_mode_hsync(mode); | |
7155 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7156 | drm_mode_set_name(mode); | |
babea61d JB |
7157 | } |
7158 | ||
84b046f3 DV |
7159 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7160 | { | |
6315b5d3 | 7161 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
84b046f3 DV |
7162 | uint32_t pipeconf; |
7163 | ||
9f11a9e4 | 7164 | pipeconf = 0; |
84b046f3 | 7165 | |
e56134bc VS |
7166 | /* we keep both pipes enabled on 830 */ |
7167 | if (IS_I830(dev_priv)) | |
b6b5d049 | 7168 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; |
67c72a12 | 7169 | |
6e3c9717 | 7170 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7171 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7172 | |
ff9ce46e | 7173 | /* only g4x and later have fancy bpc/dither controls */ |
9beb5fea TU |
7174 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
7175 | IS_CHERRYVIEW(dev_priv)) { | |
ff9ce46e | 7176 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7177 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7178 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7179 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7180 | |
6e3c9717 | 7181 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7182 | case 18: |
7183 | pipeconf |= PIPECONF_6BPC; | |
7184 | break; | |
7185 | case 24: | |
7186 | pipeconf |= PIPECONF_8BPC; | |
7187 | break; | |
7188 | case 30: | |
7189 | pipeconf |= PIPECONF_10BPC; | |
7190 | break; | |
7191 | default: | |
7192 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7193 | BUG(); | |
84b046f3 DV |
7194 | } |
7195 | } | |
7196 | ||
56b857a5 | 7197 | if (HAS_PIPE_CXSR(dev_priv)) { |
84b046f3 DV |
7198 | if (intel_crtc->lowfreq_avail) { |
7199 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7200 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7201 | } else { | |
7202 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7203 | } |
7204 | } | |
7205 | ||
6e3c9717 | 7206 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
6315b5d3 | 7207 | if (INTEL_GEN(dev_priv) < 4 || |
2d84d2b3 | 7208 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7209 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7210 | else | |
7211 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7212 | } else | |
84b046f3 DV |
7213 | pipeconf |= PIPECONF_PROGRESSIVE; |
7214 | ||
920a14b2 | 7215 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 7216 | intel_crtc->config->limited_color_range) |
9f11a9e4 | 7217 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7218 | |
84b046f3 DV |
7219 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7220 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7221 | } | |
7222 | ||
81c97f52 ACO |
7223 | static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, |
7224 | struct intel_crtc_state *crtc_state) | |
7225 | { | |
7226 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7227 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7228 | const struct intel_limit *limit; |
81c97f52 ACO |
7229 | int refclk = 48000; |
7230 | ||
7231 | memset(&crtc_state->dpll_hw_state, 0, | |
7232 | sizeof(crtc_state->dpll_hw_state)); | |
7233 | ||
2d84d2b3 | 7234 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
81c97f52 ACO |
7235 | if (intel_panel_use_ssc(dev_priv)) { |
7236 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7237 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7238 | } | |
7239 | ||
7240 | limit = &intel_limits_i8xx_lvds; | |
2d84d2b3 | 7241 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { |
81c97f52 ACO |
7242 | limit = &intel_limits_i8xx_dvo; |
7243 | } else { | |
7244 | limit = &intel_limits_i8xx_dac; | |
7245 | } | |
7246 | ||
7247 | if (!crtc_state->clock_set && | |
7248 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7249 | refclk, NULL, &crtc_state->dpll)) { | |
7250 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7251 | return -EINVAL; | |
7252 | } | |
7253 | ||
7254 | i8xx_compute_dpll(crtc, crtc_state, NULL); | |
7255 | ||
7256 | return 0; | |
7257 | } | |
7258 | ||
19ec6693 ACO |
7259 | static int g4x_crtc_compute_clock(struct intel_crtc *crtc, |
7260 | struct intel_crtc_state *crtc_state) | |
7261 | { | |
7262 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7263 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7264 | const struct intel_limit *limit; |
19ec6693 ACO |
7265 | int refclk = 96000; |
7266 | ||
7267 | memset(&crtc_state->dpll_hw_state, 0, | |
7268 | sizeof(crtc_state->dpll_hw_state)); | |
7269 | ||
2d84d2b3 | 7270 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
19ec6693 ACO |
7271 | if (intel_panel_use_ssc(dev_priv)) { |
7272 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7273 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7274 | } | |
7275 | ||
7276 | if (intel_is_dual_link_lvds(dev)) | |
7277 | limit = &intel_limits_g4x_dual_channel_lvds; | |
7278 | else | |
7279 | limit = &intel_limits_g4x_single_channel_lvds; | |
2d84d2b3 VS |
7280 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || |
7281 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
19ec6693 | 7282 | limit = &intel_limits_g4x_hdmi; |
2d84d2b3 | 7283 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
19ec6693 ACO |
7284 | limit = &intel_limits_g4x_sdvo; |
7285 | } else { | |
7286 | /* The option is for other outputs */ | |
7287 | limit = &intel_limits_i9xx_sdvo; | |
7288 | } | |
7289 | ||
7290 | if (!crtc_state->clock_set && | |
7291 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7292 | refclk, NULL, &crtc_state->dpll)) { | |
7293 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7294 | return -EINVAL; | |
7295 | } | |
7296 | ||
7297 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7298 | ||
7299 | return 0; | |
7300 | } | |
7301 | ||
70e8aa21 ACO |
7302 | static int pnv_crtc_compute_clock(struct intel_crtc *crtc, |
7303 | struct intel_crtc_state *crtc_state) | |
7304 | { | |
7305 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7306 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7307 | const struct intel_limit *limit; |
70e8aa21 ACO |
7308 | int refclk = 96000; |
7309 | ||
7310 | memset(&crtc_state->dpll_hw_state, 0, | |
7311 | sizeof(crtc_state->dpll_hw_state)); | |
7312 | ||
2d84d2b3 | 7313 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
7314 | if (intel_panel_use_ssc(dev_priv)) { |
7315 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7316 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7317 | } | |
7318 | ||
7319 | limit = &intel_limits_pineview_lvds; | |
7320 | } else { | |
7321 | limit = &intel_limits_pineview_sdvo; | |
7322 | } | |
7323 | ||
7324 | if (!crtc_state->clock_set && | |
7325 | !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7326 | refclk, NULL, &crtc_state->dpll)) { | |
7327 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7328 | return -EINVAL; | |
7329 | } | |
7330 | ||
7331 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7332 | ||
7333 | return 0; | |
7334 | } | |
7335 | ||
190f68c5 ACO |
7336 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7337 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7338 | { |
c7653199 | 7339 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7340 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7341 | const struct intel_limit *limit; |
81c97f52 | 7342 | int refclk = 96000; |
79e53945 | 7343 | |
dd3cd74a ACO |
7344 | memset(&crtc_state->dpll_hw_state, 0, |
7345 | sizeof(crtc_state->dpll_hw_state)); | |
7346 | ||
2d84d2b3 | 7347 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
7348 | if (intel_panel_use_ssc(dev_priv)) { |
7349 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7350 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7351 | } | |
43565a06 | 7352 | |
70e8aa21 ACO |
7353 | limit = &intel_limits_i9xx_lvds; |
7354 | } else { | |
7355 | limit = &intel_limits_i9xx_sdvo; | |
81c97f52 | 7356 | } |
79e53945 | 7357 | |
70e8aa21 ACO |
7358 | if (!crtc_state->clock_set && |
7359 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7360 | refclk, NULL, &crtc_state->dpll)) { | |
7361 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7362 | return -EINVAL; | |
f47709a9 | 7363 | } |
7026d4ac | 7364 | |
81c97f52 | 7365 | i9xx_compute_dpll(crtc, crtc_state, NULL); |
79e53945 | 7366 | |
c8f7a0db | 7367 | return 0; |
f564048e EA |
7368 | } |
7369 | ||
65b3d6a9 ACO |
7370 | static int chv_crtc_compute_clock(struct intel_crtc *crtc, |
7371 | struct intel_crtc_state *crtc_state) | |
7372 | { | |
7373 | int refclk = 100000; | |
1b6f4958 | 7374 | const struct intel_limit *limit = &intel_limits_chv; |
65b3d6a9 ACO |
7375 | |
7376 | memset(&crtc_state->dpll_hw_state, 0, | |
7377 | sizeof(crtc_state->dpll_hw_state)); | |
7378 | ||
65b3d6a9 ACO |
7379 | if (!crtc_state->clock_set && |
7380 | !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7381 | refclk, NULL, &crtc_state->dpll)) { | |
7382 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7383 | return -EINVAL; | |
7384 | } | |
7385 | ||
7386 | chv_compute_dpll(crtc, crtc_state); | |
7387 | ||
7388 | return 0; | |
7389 | } | |
7390 | ||
7391 | static int vlv_crtc_compute_clock(struct intel_crtc *crtc, | |
7392 | struct intel_crtc_state *crtc_state) | |
7393 | { | |
7394 | int refclk = 100000; | |
1b6f4958 | 7395 | const struct intel_limit *limit = &intel_limits_vlv; |
65b3d6a9 ACO |
7396 | |
7397 | memset(&crtc_state->dpll_hw_state, 0, | |
7398 | sizeof(crtc_state->dpll_hw_state)); | |
7399 | ||
65b3d6a9 ACO |
7400 | if (!crtc_state->clock_set && |
7401 | !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7402 | refclk, NULL, &crtc_state->dpll)) { | |
7403 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7404 | return -EINVAL; | |
7405 | } | |
7406 | ||
7407 | vlv_compute_dpll(crtc, crtc_state); | |
7408 | ||
7409 | return 0; | |
7410 | } | |
7411 | ||
2fa2fe9a | 7412 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7413 | struct intel_crtc_state *pipe_config) |
2fa2fe9a | 7414 | { |
6315b5d3 | 7415 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2fa2fe9a DV |
7416 | uint32_t tmp; |
7417 | ||
50a0bc90 TU |
7418 | if (INTEL_GEN(dev_priv) <= 3 && |
7419 | (IS_I830(dev_priv) || !IS_MOBILE(dev_priv))) | |
dc9e7dec VS |
7420 | return; |
7421 | ||
2fa2fe9a | 7422 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7423 | if (!(tmp & PFIT_ENABLE)) |
7424 | return; | |
2fa2fe9a | 7425 | |
06922821 | 7426 | /* Check whether the pfit is attached to our pipe. */ |
6315b5d3 | 7427 | if (INTEL_GEN(dev_priv) < 4) { |
2fa2fe9a DV |
7428 | if (crtc->pipe != PIPE_B) |
7429 | return; | |
2fa2fe9a DV |
7430 | } else { |
7431 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
7432 | return; | |
7433 | } | |
7434 | ||
06922821 | 7435 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a | 7436 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
2fa2fe9a DV |
7437 | } |
7438 | ||
acbec814 | 7439 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7440 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
7441 | { |
7442 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7443 | struct drm_i915_private *dev_priv = to_i915(dev); |
acbec814 | 7444 | int pipe = pipe_config->cpu_transcoder; |
9e2c8475 | 7445 | struct dpll clock; |
acbec814 | 7446 | u32 mdiv; |
662c6ecb | 7447 | int refclk = 100000; |
acbec814 | 7448 | |
b521973b VS |
7449 | /* In case of DSI, DPLL will not be used */ |
7450 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
f573de5a SK |
7451 | return; |
7452 | ||
a580516d | 7453 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 7454 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 7455 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
7456 | |
7457 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
7458 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
7459 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
7460 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
7461 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
7462 | ||
dccbea3b | 7463 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
7464 | } |
7465 | ||
5724dbd1 DL |
7466 | static void |
7467 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
7468 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
7469 | { |
7470 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7471 | struct drm_i915_private *dev_priv = to_i915(dev); |
1ad292b5 JB |
7472 | u32 val, base, offset; |
7473 | int pipe = crtc->pipe, plane = crtc->plane; | |
7474 | int fourcc, pixel_format; | |
6761dd31 | 7475 | unsigned int aligned_height; |
b113d5ee | 7476 | struct drm_framebuffer *fb; |
1b842c89 | 7477 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 7478 | |
42a7b088 DL |
7479 | val = I915_READ(DSPCNTR(plane)); |
7480 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
7481 | return; | |
7482 | ||
d9806c9f | 7483 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 7484 | if (!intel_fb) { |
1ad292b5 JB |
7485 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7486 | return; | |
7487 | } | |
7488 | ||
1b842c89 DL |
7489 | fb = &intel_fb->base; |
7490 | ||
d2e9f5fc VS |
7491 | fb->dev = dev; |
7492 | ||
6315b5d3 | 7493 | if (INTEL_GEN(dev_priv) >= 4) { |
18c5247e | 7494 | if (val & DISPPLANE_TILED) { |
49af449b | 7495 | plane_config->tiling = I915_TILING_X; |
bae781b2 | 7496 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
18c5247e DV |
7497 | } |
7498 | } | |
1ad292b5 JB |
7499 | |
7500 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 7501 | fourcc = i9xx_format_to_fourcc(pixel_format); |
2f3f4763 | 7502 | fb->format = drm_format_info(fourcc); |
1ad292b5 | 7503 | |
6315b5d3 | 7504 | if (INTEL_GEN(dev_priv) >= 4) { |
49af449b | 7505 | if (plane_config->tiling) |
1ad292b5 JB |
7506 | offset = I915_READ(DSPTILEOFF(plane)); |
7507 | else | |
7508 | offset = I915_READ(DSPLINOFF(plane)); | |
7509 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7510 | } else { | |
7511 | base = I915_READ(DSPADDR(plane)); | |
7512 | } | |
7513 | plane_config->base = base; | |
7514 | ||
7515 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
7516 | fb->width = ((val >> 16) & 0xfff) + 1; |
7517 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
7518 | |
7519 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 7520 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 7521 | |
d88c4afd | 7522 | aligned_height = intel_fb_align_height(fb, 0, fb->height); |
1ad292b5 | 7523 | |
f37b5c2b | 7524 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 7525 | |
2844a921 DL |
7526 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
7527 | pipe_name(pipe), plane, fb->width, fb->height, | |
272725c7 | 7528 | fb->format->cpp[0] * 8, base, fb->pitches[0], |
2844a921 | 7529 | plane_config->size); |
1ad292b5 | 7530 | |
2d14030b | 7531 | plane_config->fb = intel_fb; |
1ad292b5 JB |
7532 | } |
7533 | ||
70b23a98 | 7534 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7535 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
7536 | { |
7537 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7538 | struct drm_i915_private *dev_priv = to_i915(dev); |
70b23a98 VS |
7539 | int pipe = pipe_config->cpu_transcoder; |
7540 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9e2c8475 | 7541 | struct dpll clock; |
0d7b6b11 | 7542 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
7543 | int refclk = 100000; |
7544 | ||
b521973b VS |
7545 | /* In case of DSI, DPLL will not be used */ |
7546 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7547 | return; | |
7548 | ||
a580516d | 7549 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
7550 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
7551 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
7552 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
7553 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 7554 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 7555 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
7556 | |
7557 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
7558 | clock.m2 = (pll_dw0 & 0xff) << 22; |
7559 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
7560 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
7561 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
7562 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
7563 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
7564 | ||
dccbea3b | 7565 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
7566 | } |
7567 | ||
0e8ffe1b | 7568 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 7569 | struct intel_crtc_state *pipe_config) |
0e8ffe1b | 7570 | { |
6315b5d3 | 7571 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1729050e | 7572 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 7573 | uint32_t tmp; |
1729050e | 7574 | bool ret; |
0e8ffe1b | 7575 | |
1729050e ID |
7576 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
7577 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 ID |
7578 | return false; |
7579 | ||
e143a21c | 7580 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 7581 | pipe_config->shared_dpll = NULL; |
eccb140b | 7582 | |
1729050e ID |
7583 | ret = false; |
7584 | ||
0e8ffe1b DV |
7585 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7586 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 7587 | goto out; |
0e8ffe1b | 7588 | |
9beb5fea TU |
7589 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
7590 | IS_CHERRYVIEW(dev_priv)) { | |
42571aef VS |
7591 | switch (tmp & PIPECONF_BPC_MASK) { |
7592 | case PIPECONF_6BPC: | |
7593 | pipe_config->pipe_bpp = 18; | |
7594 | break; | |
7595 | case PIPECONF_8BPC: | |
7596 | pipe_config->pipe_bpp = 24; | |
7597 | break; | |
7598 | case PIPECONF_10BPC: | |
7599 | pipe_config->pipe_bpp = 30; | |
7600 | break; | |
7601 | default: | |
7602 | break; | |
7603 | } | |
7604 | } | |
7605 | ||
920a14b2 | 7606 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 7607 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
b5a9fa09 DV |
7608 | pipe_config->limited_color_range = true; |
7609 | ||
6315b5d3 | 7610 | if (INTEL_GEN(dev_priv) < 4) |
282740f7 VS |
7611 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; |
7612 | ||
1bd1bd80 | 7613 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 7614 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 7615 | |
2fa2fe9a DV |
7616 | i9xx_get_pfit_config(crtc, pipe_config); |
7617 | ||
6315b5d3 | 7618 | if (INTEL_GEN(dev_priv) >= 4) { |
c231775c | 7619 | /* No way to read it out on pipes B and C */ |
920a14b2 | 7620 | if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) |
c231775c VS |
7621 | tmp = dev_priv->chv_dpll_md[crtc->pipe]; |
7622 | else | |
7623 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6c49f241 DV |
7624 | pipe_config->pixel_multiplier = |
7625 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
7626 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 7627 | pipe_config->dpll_hw_state.dpll_md = tmp; |
50a0bc90 | 7628 | } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || |
73f67aa8 | 7629 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { |
6c49f241 DV |
7630 | tmp = I915_READ(DPLL(crtc->pipe)); |
7631 | pipe_config->pixel_multiplier = | |
7632 | ((tmp & SDVO_MULTIPLIER_MASK) | |
7633 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
7634 | } else { | |
7635 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
7636 | * port and will be fixed up in the encoder->get_config | |
7637 | * function. */ | |
7638 | pipe_config->pixel_multiplier = 1; | |
7639 | } | |
8bcc2795 | 7640 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
920a14b2 | 7641 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
1c4e0274 VS |
7642 | /* |
7643 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
7644 | * on 830. Filter it out here so that we don't | |
7645 | * report errors due to that. | |
7646 | */ | |
50a0bc90 | 7647 | if (IS_I830(dev_priv)) |
1c4e0274 VS |
7648 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; |
7649 | ||
8bcc2795 DV |
7650 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
7651 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
7652 | } else { |
7653 | /* Mask out read-only status bits. */ | |
7654 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
7655 | DPLL_PORTC_READY_MASK | | |
7656 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 7657 | } |
6c49f241 | 7658 | |
920a14b2 | 7659 | if (IS_CHERRYVIEW(dev_priv)) |
70b23a98 | 7660 | chv_crtc_clock_get(crtc, pipe_config); |
11a914c2 | 7661 | else if (IS_VALLEYVIEW(dev_priv)) |
acbec814 JB |
7662 | vlv_crtc_clock_get(crtc, pipe_config); |
7663 | else | |
7664 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 7665 | |
0f64614d VS |
7666 | /* |
7667 | * Normally the dotclock is filled in by the encoder .get_config() | |
7668 | * but in case the pipe is enabled w/o any ports we need a sane | |
7669 | * default. | |
7670 | */ | |
7671 | pipe_config->base.adjusted_mode.crtc_clock = | |
7672 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
7673 | ||
1729050e ID |
7674 | ret = true; |
7675 | ||
7676 | out: | |
7677 | intel_display_power_put(dev_priv, power_domain); | |
7678 | ||
7679 | return ret; | |
0e8ffe1b DV |
7680 | } |
7681 | ||
c39055b0 | 7682 | static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv) |
13d83a67 | 7683 | { |
13d83a67 | 7684 | struct intel_encoder *encoder; |
1c1a24d2 | 7685 | int i; |
74cfd7ac | 7686 | u32 val, final; |
13d83a67 | 7687 | bool has_lvds = false; |
199e5d79 | 7688 | bool has_cpu_edp = false; |
199e5d79 | 7689 | bool has_panel = false; |
99eb6a01 KP |
7690 | bool has_ck505 = false; |
7691 | bool can_ssc = false; | |
1c1a24d2 | 7692 | bool using_ssc_source = false; |
13d83a67 JB |
7693 | |
7694 | /* We need to take the global config into account */ | |
c39055b0 | 7695 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
199e5d79 KP |
7696 | switch (encoder->type) { |
7697 | case INTEL_OUTPUT_LVDS: | |
7698 | has_panel = true; | |
7699 | has_lvds = true; | |
7700 | break; | |
7701 | case INTEL_OUTPUT_EDP: | |
7702 | has_panel = true; | |
2de6905f | 7703 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
7704 | has_cpu_edp = true; |
7705 | break; | |
6847d71b PZ |
7706 | default: |
7707 | break; | |
13d83a67 JB |
7708 | } |
7709 | } | |
7710 | ||
6e266956 | 7711 | if (HAS_PCH_IBX(dev_priv)) { |
41aa3448 | 7712 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
7713 | can_ssc = has_ck505; |
7714 | } else { | |
7715 | has_ck505 = false; | |
7716 | can_ssc = true; | |
7717 | } | |
7718 | ||
1c1a24d2 L |
7719 | /* Check if any DPLLs are using the SSC source */ |
7720 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
7721 | u32 temp = I915_READ(PCH_DPLL(i)); | |
7722 | ||
7723 | if (!(temp & DPLL_VCO_ENABLE)) | |
7724 | continue; | |
7725 | ||
7726 | if ((temp & PLL_REF_INPUT_MASK) == | |
7727 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
7728 | using_ssc_source = true; | |
7729 | break; | |
7730 | } | |
7731 | } | |
7732 | ||
7733 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n", | |
7734 | has_panel, has_lvds, has_ck505, using_ssc_source); | |
13d83a67 JB |
7735 | |
7736 | /* Ironlake: try to setup display ref clock before DPLL | |
7737 | * enabling. This is only under driver's control after | |
7738 | * PCH B stepping, previous chipset stepping should be | |
7739 | * ignoring this setting. | |
7740 | */ | |
74cfd7ac CW |
7741 | val = I915_READ(PCH_DREF_CONTROL); |
7742 | ||
7743 | /* As we must carefully and slowly disable/enable each source in turn, | |
7744 | * compute the final state we want first and check if we need to | |
7745 | * make any changes at all. | |
7746 | */ | |
7747 | final = val; | |
7748 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
7749 | if (has_ck505) | |
7750 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
7751 | else | |
7752 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
7753 | ||
8c07eb68 | 7754 | final &= ~DREF_SSC_SOURCE_MASK; |
74cfd7ac | 7755 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
8c07eb68 | 7756 | final &= ~DREF_SSC1_ENABLE; |
74cfd7ac CW |
7757 | |
7758 | if (has_panel) { | |
7759 | final |= DREF_SSC_SOURCE_ENABLE; | |
7760 | ||
7761 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7762 | final |= DREF_SSC1_ENABLE; | |
7763 | ||
7764 | if (has_cpu_edp) { | |
7765 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7766 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
7767 | else | |
7768 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
7769 | } else | |
7770 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
1c1a24d2 L |
7771 | } else if (using_ssc_source) { |
7772 | final |= DREF_SSC_SOURCE_ENABLE; | |
7773 | final |= DREF_SSC1_ENABLE; | |
74cfd7ac CW |
7774 | } |
7775 | ||
7776 | if (final == val) | |
7777 | return; | |
7778 | ||
13d83a67 | 7779 | /* Always enable nonspread source */ |
74cfd7ac | 7780 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 7781 | |
99eb6a01 | 7782 | if (has_ck505) |
74cfd7ac | 7783 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 7784 | else |
74cfd7ac | 7785 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 7786 | |
199e5d79 | 7787 | if (has_panel) { |
74cfd7ac CW |
7788 | val &= ~DREF_SSC_SOURCE_MASK; |
7789 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 7790 | |
199e5d79 | 7791 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 7792 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7793 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 7794 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 7795 | } else |
74cfd7ac | 7796 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
7797 | |
7798 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 7799 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7800 | POSTING_READ(PCH_DREF_CONTROL); |
7801 | udelay(200); | |
7802 | ||
74cfd7ac | 7803 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
7804 | |
7805 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 7806 | if (has_cpu_edp) { |
99eb6a01 | 7807 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7808 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 7809 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 7810 | } else |
74cfd7ac | 7811 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 7812 | } else |
74cfd7ac | 7813 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7814 | |
74cfd7ac | 7815 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7816 | POSTING_READ(PCH_DREF_CONTROL); |
7817 | udelay(200); | |
7818 | } else { | |
1c1a24d2 | 7819 | DRM_DEBUG_KMS("Disabling CPU source output\n"); |
199e5d79 | 7820 | |
74cfd7ac | 7821 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
7822 | |
7823 | /* Turn off CPU output */ | |
74cfd7ac | 7824 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7825 | |
74cfd7ac | 7826 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7827 | POSTING_READ(PCH_DREF_CONTROL); |
7828 | udelay(200); | |
7829 | ||
1c1a24d2 L |
7830 | if (!using_ssc_source) { |
7831 | DRM_DEBUG_KMS("Disabling SSC source\n"); | |
199e5d79 | 7832 | |
1c1a24d2 L |
7833 | /* Turn off the SSC source */ |
7834 | val &= ~DREF_SSC_SOURCE_MASK; | |
7835 | val |= DREF_SSC_SOURCE_DISABLE; | |
f165d283 | 7836 | |
1c1a24d2 L |
7837 | /* Turn off SSC1 */ |
7838 | val &= ~DREF_SSC1_ENABLE; | |
7839 | ||
7840 | I915_WRITE(PCH_DREF_CONTROL, val); | |
7841 | POSTING_READ(PCH_DREF_CONTROL); | |
7842 | udelay(200); | |
7843 | } | |
13d83a67 | 7844 | } |
74cfd7ac CW |
7845 | |
7846 | BUG_ON(val != final); | |
13d83a67 JB |
7847 | } |
7848 | ||
f31f2d55 | 7849 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 7850 | { |
f31f2d55 | 7851 | uint32_t tmp; |
dde86e2d | 7852 | |
0ff066a9 PZ |
7853 | tmp = I915_READ(SOUTH_CHICKEN2); |
7854 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
7855 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7856 | |
cf3598c2 ID |
7857 | if (wait_for_us(I915_READ(SOUTH_CHICKEN2) & |
7858 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
0ff066a9 | 7859 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
dde86e2d | 7860 | |
0ff066a9 PZ |
7861 | tmp = I915_READ(SOUTH_CHICKEN2); |
7862 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
7863 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7864 | |
cf3598c2 ID |
7865 | if (wait_for_us((I915_READ(SOUTH_CHICKEN2) & |
7866 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
0ff066a9 | 7867 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
f31f2d55 PZ |
7868 | } |
7869 | ||
7870 | /* WaMPhyProgramming:hsw */ | |
7871 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
7872 | { | |
7873 | uint32_t tmp; | |
dde86e2d PZ |
7874 | |
7875 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
7876 | tmp &= ~(0xFF << 24); | |
7877 | tmp |= (0x12 << 24); | |
7878 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
7879 | ||
dde86e2d PZ |
7880 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
7881 | tmp |= (1 << 11); | |
7882 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
7883 | ||
7884 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
7885 | tmp |= (1 << 11); | |
7886 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
7887 | ||
dde86e2d PZ |
7888 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
7889 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7890 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
7891 | ||
7892 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
7893 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7894 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
7895 | ||
0ff066a9 PZ |
7896 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
7897 | tmp &= ~(7 << 13); | |
7898 | tmp |= (5 << 13); | |
7899 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 7900 | |
0ff066a9 PZ |
7901 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
7902 | tmp &= ~(7 << 13); | |
7903 | tmp |= (5 << 13); | |
7904 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
7905 | |
7906 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
7907 | tmp &= ~0xFF; | |
7908 | tmp |= 0x1C; | |
7909 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
7910 | ||
7911 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
7912 | tmp &= ~0xFF; | |
7913 | tmp |= 0x1C; | |
7914 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
7915 | ||
7916 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
7917 | tmp &= ~(0xFF << 16); | |
7918 | tmp |= (0x1C << 16); | |
7919 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
7920 | ||
7921 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
7922 | tmp &= ~(0xFF << 16); | |
7923 | tmp |= (0x1C << 16); | |
7924 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
7925 | ||
0ff066a9 PZ |
7926 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
7927 | tmp |= (1 << 27); | |
7928 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 7929 | |
0ff066a9 PZ |
7930 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
7931 | tmp |= (1 << 27); | |
7932 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 7933 | |
0ff066a9 PZ |
7934 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
7935 | tmp &= ~(0xF << 28); | |
7936 | tmp |= (4 << 28); | |
7937 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 7938 | |
0ff066a9 PZ |
7939 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
7940 | tmp &= ~(0xF << 28); | |
7941 | tmp |= (4 << 28); | |
7942 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
7943 | } |
7944 | ||
2fa86a1f PZ |
7945 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
7946 | * Programming" based on the parameters passed: | |
7947 | * - Sequence to enable CLKOUT_DP | |
7948 | * - Sequence to enable CLKOUT_DP without spread | |
7949 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
7950 | */ | |
c39055b0 ACO |
7951 | static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv, |
7952 | bool with_spread, bool with_fdi) | |
f31f2d55 | 7953 | { |
2fa86a1f PZ |
7954 | uint32_t reg, tmp; |
7955 | ||
7956 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
7957 | with_spread = true; | |
4f8036a2 TU |
7958 | if (WARN(HAS_PCH_LPT_LP(dev_priv) && |
7959 | with_fdi, "LP PCH doesn't have FDI\n")) | |
2fa86a1f | 7960 | with_fdi = false; |
f31f2d55 | 7961 | |
a580516d | 7962 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
7963 | |
7964 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7965 | tmp &= ~SBI_SSCCTL_DISABLE; | |
7966 | tmp |= SBI_SSCCTL_PATHALT; | |
7967 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7968 | ||
7969 | udelay(24); | |
7970 | ||
2fa86a1f PZ |
7971 | if (with_spread) { |
7972 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7973 | tmp &= ~SBI_SSCCTL_PATHALT; | |
7974 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 7975 | |
2fa86a1f PZ |
7976 | if (with_fdi) { |
7977 | lpt_reset_fdi_mphy(dev_priv); | |
7978 | lpt_program_fdi_mphy(dev_priv); | |
7979 | } | |
7980 | } | |
dde86e2d | 7981 | |
4f8036a2 | 7982 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
7983 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
7984 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7985 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 7986 | |
a580516d | 7987 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
7988 | } |
7989 | ||
47701c3b | 7990 | /* Sequence to disable CLKOUT_DP */ |
c39055b0 | 7991 | static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv) |
47701c3b | 7992 | { |
47701c3b PZ |
7993 | uint32_t reg, tmp; |
7994 | ||
a580516d | 7995 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 7996 | |
4f8036a2 | 7997 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
7998 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
7999 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8000 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8001 | ||
8002 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8003 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8004 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8005 | tmp |= SBI_SSCCTL_PATHALT; | |
8006 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8007 | udelay(32); | |
8008 | } | |
8009 | tmp |= SBI_SSCCTL_DISABLE; | |
8010 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8011 | } | |
8012 | ||
a580516d | 8013 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8014 | } |
8015 | ||
f7be2c21 VS |
8016 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
8017 | ||
8018 | static const uint16_t sscdivintphase[] = { | |
8019 | [BEND_IDX( 50)] = 0x3B23, | |
8020 | [BEND_IDX( 45)] = 0x3B23, | |
8021 | [BEND_IDX( 40)] = 0x3C23, | |
8022 | [BEND_IDX( 35)] = 0x3C23, | |
8023 | [BEND_IDX( 30)] = 0x3D23, | |
8024 | [BEND_IDX( 25)] = 0x3D23, | |
8025 | [BEND_IDX( 20)] = 0x3E23, | |
8026 | [BEND_IDX( 15)] = 0x3E23, | |
8027 | [BEND_IDX( 10)] = 0x3F23, | |
8028 | [BEND_IDX( 5)] = 0x3F23, | |
8029 | [BEND_IDX( 0)] = 0x0025, | |
8030 | [BEND_IDX( -5)] = 0x0025, | |
8031 | [BEND_IDX(-10)] = 0x0125, | |
8032 | [BEND_IDX(-15)] = 0x0125, | |
8033 | [BEND_IDX(-20)] = 0x0225, | |
8034 | [BEND_IDX(-25)] = 0x0225, | |
8035 | [BEND_IDX(-30)] = 0x0325, | |
8036 | [BEND_IDX(-35)] = 0x0325, | |
8037 | [BEND_IDX(-40)] = 0x0425, | |
8038 | [BEND_IDX(-45)] = 0x0425, | |
8039 | [BEND_IDX(-50)] = 0x0525, | |
8040 | }; | |
8041 | ||
8042 | /* | |
8043 | * Bend CLKOUT_DP | |
8044 | * steps -50 to 50 inclusive, in steps of 5 | |
8045 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
8046 | * change in clock period = -(steps / 10) * 5.787 ps | |
8047 | */ | |
8048 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
8049 | { | |
8050 | uint32_t tmp; | |
8051 | int idx = BEND_IDX(steps); | |
8052 | ||
8053 | if (WARN_ON(steps % 5 != 0)) | |
8054 | return; | |
8055 | ||
8056 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
8057 | return; | |
8058 | ||
8059 | mutex_lock(&dev_priv->sb_lock); | |
8060 | ||
8061 | if (steps % 10 != 0) | |
8062 | tmp = 0xAAAAAAAB; | |
8063 | else | |
8064 | tmp = 0x00000000; | |
8065 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
8066 | ||
8067 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
8068 | tmp &= 0xffff0000; | |
8069 | tmp |= sscdivintphase[idx]; | |
8070 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
8071 | ||
8072 | mutex_unlock(&dev_priv->sb_lock); | |
8073 | } | |
8074 | ||
8075 | #undef BEND_IDX | |
8076 | ||
c39055b0 | 8077 | static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv) |
bf8fa3d3 | 8078 | { |
bf8fa3d3 PZ |
8079 | struct intel_encoder *encoder; |
8080 | bool has_vga = false; | |
8081 | ||
c39055b0 | 8082 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
bf8fa3d3 PZ |
8083 | switch (encoder->type) { |
8084 | case INTEL_OUTPUT_ANALOG: | |
8085 | has_vga = true; | |
8086 | break; | |
6847d71b PZ |
8087 | default: |
8088 | break; | |
bf8fa3d3 PZ |
8089 | } |
8090 | } | |
8091 | ||
f7be2c21 | 8092 | if (has_vga) { |
c39055b0 ACO |
8093 | lpt_bend_clkout_dp(dev_priv, 0); |
8094 | lpt_enable_clkout_dp(dev_priv, true, true); | |
f7be2c21 | 8095 | } else { |
c39055b0 | 8096 | lpt_disable_clkout_dp(dev_priv); |
f7be2c21 | 8097 | } |
bf8fa3d3 PZ |
8098 | } |
8099 | ||
dde86e2d PZ |
8100 | /* |
8101 | * Initialize reference clocks when the driver loads | |
8102 | */ | |
c39055b0 | 8103 | void intel_init_pch_refclk(struct drm_i915_private *dev_priv) |
dde86e2d | 8104 | { |
6e266956 | 8105 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) |
c39055b0 | 8106 | ironlake_init_pch_refclk(dev_priv); |
6e266956 | 8107 | else if (HAS_PCH_LPT(dev_priv)) |
c39055b0 | 8108 | lpt_init_pch_refclk(dev_priv); |
dde86e2d PZ |
8109 | } |
8110 | ||
6ff93609 | 8111 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8112 | { |
fac5e23e | 8113 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
79e53945 JB |
8114 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8115 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8116 | uint32_t val; |
8117 | ||
78114071 | 8118 | val = 0; |
c8203565 | 8119 | |
6e3c9717 | 8120 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8121 | case 18: |
dfd07d72 | 8122 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8123 | break; |
8124 | case 24: | |
dfd07d72 | 8125 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8126 | break; |
8127 | case 30: | |
dfd07d72 | 8128 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8129 | break; |
8130 | case 36: | |
dfd07d72 | 8131 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8132 | break; |
8133 | default: | |
cc769b62 PZ |
8134 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8135 | BUG(); | |
c8203565 PZ |
8136 | } |
8137 | ||
6e3c9717 | 8138 | if (intel_crtc->config->dither) |
c8203565 PZ |
8139 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8140 | ||
6e3c9717 | 8141 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8142 | val |= PIPECONF_INTERLACED_ILK; |
8143 | else | |
8144 | val |= PIPECONF_PROGRESSIVE; | |
8145 | ||
6e3c9717 | 8146 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8147 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8148 | |
c8203565 PZ |
8149 | I915_WRITE(PIPECONF(pipe), val); |
8150 | POSTING_READ(PIPECONF(pipe)); | |
8151 | } | |
8152 | ||
6ff93609 | 8153 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8154 | { |
fac5e23e | 8155 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee2b0b38 | 8156 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 8157 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
391bf048 | 8158 | u32 val = 0; |
ee2b0b38 | 8159 | |
391bf048 | 8160 | if (IS_HASWELL(dev_priv) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8161 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8162 | ||
6e3c9717 | 8163 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8164 | val |= PIPECONF_INTERLACED_ILK; |
8165 | else | |
8166 | val |= PIPECONF_PROGRESSIVE; | |
8167 | ||
702e7a56 PZ |
8168 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8169 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
391bf048 JN |
8170 | } |
8171 | ||
391bf048 JN |
8172 | static void haswell_set_pipemisc(struct drm_crtc *crtc) |
8173 | { | |
fac5e23e | 8174 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
391bf048 | 8175 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b22ca995 | 8176 | struct intel_crtc_state *config = intel_crtc->config; |
756f85cf | 8177 | |
391bf048 JN |
8178 | if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { |
8179 | u32 val = 0; | |
756f85cf | 8180 | |
6e3c9717 | 8181 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8182 | case 18: |
8183 | val |= PIPEMISC_DITHER_6_BPC; | |
8184 | break; | |
8185 | case 24: | |
8186 | val |= PIPEMISC_DITHER_8_BPC; | |
8187 | break; | |
8188 | case 30: | |
8189 | val |= PIPEMISC_DITHER_10_BPC; | |
8190 | break; | |
8191 | case 36: | |
8192 | val |= PIPEMISC_DITHER_12_BPC; | |
8193 | break; | |
8194 | default: | |
8195 | /* Case prevented by pipe_config_set_bpp. */ | |
8196 | BUG(); | |
8197 | } | |
8198 | ||
6e3c9717 | 8199 | if (intel_crtc->config->dither) |
756f85cf PZ |
8200 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8201 | ||
b22ca995 SS |
8202 | if (config->ycbcr420) { |
8203 | val |= PIPEMISC_OUTPUT_COLORSPACE_YUV | | |
8204 | PIPEMISC_YUV420_ENABLE | | |
8205 | PIPEMISC_YUV420_MODE_FULL_BLEND; | |
8206 | } | |
8207 | ||
391bf048 | 8208 | I915_WRITE(PIPEMISC(intel_crtc->pipe), val); |
756f85cf | 8209 | } |
ee2b0b38 PZ |
8210 | } |
8211 | ||
d4b1931c PZ |
8212 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8213 | { | |
8214 | /* | |
8215 | * Account for spread spectrum to avoid | |
8216 | * oversubscribing the link. Max center spread | |
8217 | * is 2.5%; use 5% for safety's sake. | |
8218 | */ | |
8219 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8220 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8221 | } |
8222 | ||
7429e9d4 | 8223 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8224 | { |
7429e9d4 | 8225 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8226 | } |
8227 | ||
b75ca6f6 ACO |
8228 | static void ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
8229 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 8230 | struct dpll *reduced_clock) |
79e53945 | 8231 | { |
de13a2e3 | 8232 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 | 8233 | struct drm_device *dev = crtc->dev; |
fac5e23e | 8234 | struct drm_i915_private *dev_priv = to_i915(dev); |
b75ca6f6 | 8235 | u32 dpll, fp, fp2; |
3d6e9ee0 | 8236 | int factor; |
79e53945 | 8237 | |
c1858123 | 8238 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 | 8239 | factor = 21; |
3d6e9ee0 | 8240 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
8febb297 | 8241 | if ((intel_panel_use_ssc(dev_priv) && |
e91e941b | 8242 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
6e266956 | 8243 | (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8244 | factor = 25; |
190f68c5 | 8245 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8246 | factor = 20; |
c1858123 | 8247 | |
b75ca6f6 ACO |
8248 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
8249 | ||
190f68c5 | 8250 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
b75ca6f6 ACO |
8251 | fp |= FP_CB_TUNE; |
8252 | ||
8253 | if (reduced_clock) { | |
8254 | fp2 = i9xx_dpll_compute_fp(reduced_clock); | |
2c07245f | 8255 | |
b75ca6f6 ACO |
8256 | if (reduced_clock->m < factor * reduced_clock->n) |
8257 | fp2 |= FP_CB_TUNE; | |
8258 | } else { | |
8259 | fp2 = fp; | |
8260 | } | |
9a7c7890 | 8261 | |
5eddb70b | 8262 | dpll = 0; |
2c07245f | 8263 | |
3d6e9ee0 | 8264 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a07d6787 EA |
8265 | dpll |= DPLLB_MODE_LVDS; |
8266 | else | |
8267 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8268 | |
190f68c5 | 8269 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8270 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f | 8271 | |
3d6e9ee0 VS |
8272 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
8273 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 8274 | dpll |= DPLL_SDVO_HIGH_SPEED; |
3d6e9ee0 | 8275 | |
37a5650b | 8276 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 8277 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8278 | |
7d7f8633 VS |
8279 | /* |
8280 | * The high speed IO clock is only really required for | |
8281 | * SDVO/HDMI/DP, but we also enable it for CRT to make it | |
8282 | * possible to share the DPLL between CRT and HDMI. Enabling | |
8283 | * the clock needlessly does no real harm, except use up a | |
8284 | * bit of power potentially. | |
8285 | * | |
8286 | * We'll limit this to IVB with 3 pipes, since it has only two | |
8287 | * DPLLs and so DPLL sharing is the only way to get three pipes | |
8288 | * driving PCH ports at the same time. On SNB we could do this, | |
8289 | * and potentially avoid enabling the second DPLL, but it's not | |
8290 | * clear if it''s a win or loss power wise. No point in doing | |
8291 | * this on ILK at all since it has a fixed DPLL<->pipe mapping. | |
8292 | */ | |
8293 | if (INTEL_INFO(dev_priv)->num_pipes == 3 && | |
8294 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) | |
8295 | dpll |= DPLL_SDVO_HIGH_SPEED; | |
8296 | ||
a07d6787 | 8297 | /* compute bitmask from p1 value */ |
190f68c5 | 8298 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8299 | /* also FPA1 */ |
190f68c5 | 8300 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8301 | |
190f68c5 | 8302 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8303 | case 5: |
8304 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8305 | break; | |
8306 | case 7: | |
8307 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8308 | break; | |
8309 | case 10: | |
8310 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8311 | break; | |
8312 | case 14: | |
8313 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8314 | break; | |
79e53945 JB |
8315 | } |
8316 | ||
3d6e9ee0 VS |
8317 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
8318 | intel_panel_use_ssc(dev_priv)) | |
43565a06 | 8319 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8320 | else |
8321 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8322 | ||
b75ca6f6 ACO |
8323 | dpll |= DPLL_VCO_ENABLE; |
8324 | ||
8325 | crtc_state->dpll_hw_state.dpll = dpll; | |
8326 | crtc_state->dpll_hw_state.fp0 = fp; | |
8327 | crtc_state->dpll_hw_state.fp1 = fp2; | |
de13a2e3 PZ |
8328 | } |
8329 | ||
190f68c5 ACO |
8330 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8331 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8332 | { |
997c030c | 8333 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8334 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 8335 | const struct intel_limit *limit; |
997c030c | 8336 | int refclk = 120000; |
de13a2e3 | 8337 | |
dd3cd74a ACO |
8338 | memset(&crtc_state->dpll_hw_state, 0, |
8339 | sizeof(crtc_state->dpll_hw_state)); | |
8340 | ||
ded220e2 ACO |
8341 | crtc->lowfreq_avail = false; |
8342 | ||
8343 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ | |
8344 | if (!crtc_state->has_pch_encoder) | |
8345 | return 0; | |
79e53945 | 8346 | |
2d84d2b3 | 8347 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
997c030c ACO |
8348 | if (intel_panel_use_ssc(dev_priv)) { |
8349 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", | |
8350 | dev_priv->vbt.lvds_ssc_freq); | |
8351 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8352 | } | |
8353 | ||
8354 | if (intel_is_dual_link_lvds(dev)) { | |
8355 | if (refclk == 100000) | |
8356 | limit = &intel_limits_ironlake_dual_lvds_100m; | |
8357 | else | |
8358 | limit = &intel_limits_ironlake_dual_lvds; | |
8359 | } else { | |
8360 | if (refclk == 100000) | |
8361 | limit = &intel_limits_ironlake_single_lvds_100m; | |
8362 | else | |
8363 | limit = &intel_limits_ironlake_single_lvds; | |
8364 | } | |
8365 | } else { | |
8366 | limit = &intel_limits_ironlake_dac; | |
8367 | } | |
8368 | ||
364ee29d | 8369 | if (!crtc_state->clock_set && |
997c030c ACO |
8370 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
8371 | refclk, NULL, &crtc_state->dpll)) { | |
364ee29d ACO |
8372 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8373 | return -EINVAL; | |
f47709a9 | 8374 | } |
79e53945 | 8375 | |
cbaa3315 | 8376 | ironlake_compute_dpll(crtc, crtc_state, NULL); |
66e985c0 | 8377 | |
efd38b68 | 8378 | if (!intel_get_shared_dpll(crtc, crtc_state, NULL)) { |
ded220e2 ACO |
8379 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
8380 | pipe_name(crtc->pipe)); | |
8381 | return -EINVAL; | |
3fb37703 | 8382 | } |
79e53945 | 8383 | |
c8f7a0db | 8384 | return 0; |
79e53945 JB |
8385 | } |
8386 | ||
eb14cb74 VS |
8387 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
8388 | struct intel_link_m_n *m_n) | |
8389 | { | |
8390 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8391 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb14cb74 VS |
8392 | enum pipe pipe = crtc->pipe; |
8393 | ||
8394 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
8395 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
8396 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8397 | & ~TU_SIZE_MASK; | |
8398 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
8399 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8400 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8401 | } | |
8402 | ||
8403 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
8404 | enum transcoder transcoder, | |
b95af8be VK |
8405 | struct intel_link_m_n *m_n, |
8406 | struct intel_link_m_n *m2_n2) | |
72419203 | 8407 | { |
6315b5d3 | 8408 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
eb14cb74 | 8409 | enum pipe pipe = crtc->pipe; |
72419203 | 8410 | |
6315b5d3 | 8411 | if (INTEL_GEN(dev_priv) >= 5) { |
eb14cb74 VS |
8412 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); |
8413 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
8414 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
8415 | & ~TU_SIZE_MASK; | |
8416 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
8417 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
8418 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
8419 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
8420 | * gen < 8) and if DRRS is supported (to make sure the | |
8421 | * registers are not unnecessarily read). | |
8422 | */ | |
6315b5d3 | 8423 | if (m2_n2 && INTEL_GEN(dev_priv) < 8 && |
6e3c9717 | 8424 | crtc->config->has_drrs) { |
b95af8be VK |
8425 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
8426 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
8427 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
8428 | & ~TU_SIZE_MASK; | |
8429 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
8430 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
8431 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8432 | } | |
eb14cb74 VS |
8433 | } else { |
8434 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
8435 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
8436 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8437 | & ~TU_SIZE_MASK; | |
8438 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
8439 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8440 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8441 | } | |
8442 | } | |
8443 | ||
8444 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 8445 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 8446 | { |
681a8504 | 8447 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
8448 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
8449 | else | |
8450 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
8451 | &pipe_config->dp_m_n, |
8452 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 8453 | } |
72419203 | 8454 | |
eb14cb74 | 8455 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 8456 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
8457 | { |
8458 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 8459 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
8460 | } |
8461 | ||
bd2e244f | 8462 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8463 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
8464 | { |
8465 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8466 | struct drm_i915_private *dev_priv = to_i915(dev); |
a1b2278e CK |
8467 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
8468 | uint32_t ps_ctrl = 0; | |
8469 | int id = -1; | |
8470 | int i; | |
bd2e244f | 8471 | |
a1b2278e CK |
8472 | /* find scaler attached to this pipe */ |
8473 | for (i = 0; i < crtc->num_scalers; i++) { | |
8474 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
8475 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
8476 | id = i; | |
8477 | pipe_config->pch_pfit.enabled = true; | |
8478 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
8479 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
8480 | break; | |
8481 | } | |
8482 | } | |
bd2e244f | 8483 | |
a1b2278e CK |
8484 | scaler_state->scaler_id = id; |
8485 | if (id >= 0) { | |
8486 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
8487 | } else { | |
8488 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
8489 | } |
8490 | } | |
8491 | ||
5724dbd1 DL |
8492 | static void |
8493 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
8494 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
8495 | { |
8496 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8497 | struct drm_i915_private *dev_priv = to_i915(dev); |
40f46283 | 8498 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
8499 | int pipe = crtc->pipe; |
8500 | int fourcc, pixel_format; | |
6761dd31 | 8501 | unsigned int aligned_height; |
bc8d7dff | 8502 | struct drm_framebuffer *fb; |
1b842c89 | 8503 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 8504 | |
d9806c9f | 8505 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8506 | if (!intel_fb) { |
bc8d7dff DL |
8507 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8508 | return; | |
8509 | } | |
8510 | ||
1b842c89 DL |
8511 | fb = &intel_fb->base; |
8512 | ||
d2e9f5fc VS |
8513 | fb->dev = dev; |
8514 | ||
bc8d7dff | 8515 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
8516 | if (!(val & PLANE_CTL_ENABLE)) |
8517 | goto error; | |
8518 | ||
bc8d7dff DL |
8519 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
8520 | fourcc = skl_format_to_fourcc(pixel_format, | |
8521 | val & PLANE_CTL_ORDER_RGBX, | |
8522 | val & PLANE_CTL_ALPHA_MASK); | |
2f3f4763 | 8523 | fb->format = drm_format_info(fourcc); |
bc8d7dff | 8524 | |
40f46283 DL |
8525 | tiling = val & PLANE_CTL_TILED_MASK; |
8526 | switch (tiling) { | |
8527 | case PLANE_CTL_TILED_LINEAR: | |
2f075565 | 8528 | fb->modifier = DRM_FORMAT_MOD_LINEAR; |
40f46283 DL |
8529 | break; |
8530 | case PLANE_CTL_TILED_X: | |
8531 | plane_config->tiling = I915_TILING_X; | |
bae781b2 | 8532 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
40f46283 DL |
8533 | break; |
8534 | case PLANE_CTL_TILED_Y: | |
2e2adb05 VS |
8535 | if (val & PLANE_CTL_DECOMPRESSION_ENABLE) |
8536 | fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS; | |
8537 | else | |
8538 | fb->modifier = I915_FORMAT_MOD_Y_TILED; | |
40f46283 DL |
8539 | break; |
8540 | case PLANE_CTL_TILED_YF: | |
2e2adb05 VS |
8541 | if (val & PLANE_CTL_DECOMPRESSION_ENABLE) |
8542 | fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS; | |
8543 | else | |
8544 | fb->modifier = I915_FORMAT_MOD_Yf_TILED; | |
40f46283 DL |
8545 | break; |
8546 | default: | |
8547 | MISSING_CASE(tiling); | |
8548 | goto error; | |
8549 | } | |
8550 | ||
bc8d7dff DL |
8551 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
8552 | plane_config->base = base; | |
8553 | ||
8554 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
8555 | ||
8556 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
8557 | fb->height = ((val >> 16) & 0xfff) + 1; | |
8558 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
8559 | ||
8560 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
d88c4afd | 8561 | stride_mult = intel_fb_stride_alignment(fb, 0); |
bc8d7dff DL |
8562 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
8563 | ||
d88c4afd | 8564 | aligned_height = intel_fb_align_height(fb, 0, fb->height); |
bc8d7dff | 8565 | |
f37b5c2b | 8566 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
8567 | |
8568 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
8569 | pipe_name(pipe), fb->width, fb->height, | |
272725c7 | 8570 | fb->format->cpp[0] * 8, base, fb->pitches[0], |
bc8d7dff DL |
8571 | plane_config->size); |
8572 | ||
2d14030b | 8573 | plane_config->fb = intel_fb; |
bc8d7dff DL |
8574 | return; |
8575 | ||
8576 | error: | |
d1a3a036 | 8577 | kfree(intel_fb); |
bc8d7dff DL |
8578 | } |
8579 | ||
2fa2fe9a | 8580 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8581 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8582 | { |
8583 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8584 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa2fe9a DV |
8585 | uint32_t tmp; |
8586 | ||
8587 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
8588 | ||
8589 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 8590 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
8591 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
8592 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
8593 | |
8594 | /* We currently do not free assignements of panel fitters on | |
8595 | * ivb/hsw (since we don't use the higher upscaling modes which | |
8596 | * differentiates them) so just WARN about this case for now. */ | |
5db94019 | 8597 | if (IS_GEN7(dev_priv)) { |
cb8b2a30 DV |
8598 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != |
8599 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
8600 | } | |
2fa2fe9a | 8601 | } |
79e53945 JB |
8602 | } |
8603 | ||
5724dbd1 DL |
8604 | static void |
8605 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
8606 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
8607 | { |
8608 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8609 | struct drm_i915_private *dev_priv = to_i915(dev); |
4c6baa59 | 8610 | u32 val, base, offset; |
aeee5a49 | 8611 | int pipe = crtc->pipe; |
4c6baa59 | 8612 | int fourcc, pixel_format; |
6761dd31 | 8613 | unsigned int aligned_height; |
b113d5ee | 8614 | struct drm_framebuffer *fb; |
1b842c89 | 8615 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 8616 | |
42a7b088 DL |
8617 | val = I915_READ(DSPCNTR(pipe)); |
8618 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8619 | return; | |
8620 | ||
d9806c9f | 8621 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8622 | if (!intel_fb) { |
4c6baa59 JB |
8623 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8624 | return; | |
8625 | } | |
8626 | ||
1b842c89 DL |
8627 | fb = &intel_fb->base; |
8628 | ||
d2e9f5fc VS |
8629 | fb->dev = dev; |
8630 | ||
6315b5d3 | 8631 | if (INTEL_GEN(dev_priv) >= 4) { |
18c5247e | 8632 | if (val & DISPPLANE_TILED) { |
49af449b | 8633 | plane_config->tiling = I915_TILING_X; |
bae781b2 | 8634 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
18c5247e DV |
8635 | } |
8636 | } | |
4c6baa59 JB |
8637 | |
8638 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8639 | fourcc = i9xx_format_to_fourcc(pixel_format); |
2f3f4763 | 8640 | fb->format = drm_format_info(fourcc); |
4c6baa59 | 8641 | |
aeee5a49 | 8642 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
8652744b | 8643 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
aeee5a49 | 8644 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 8645 | } else { |
49af449b | 8646 | if (plane_config->tiling) |
aeee5a49 | 8647 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 8648 | else |
aeee5a49 | 8649 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
8650 | } |
8651 | plane_config->base = base; | |
8652 | ||
8653 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8654 | fb->width = ((val >> 16) & 0xfff) + 1; |
8655 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
8656 | |
8657 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8658 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 8659 | |
d88c4afd | 8660 | aligned_height = intel_fb_align_height(fb, 0, fb->height); |
4c6baa59 | 8661 | |
f37b5c2b | 8662 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 8663 | |
2844a921 DL |
8664 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8665 | pipe_name(pipe), fb->width, fb->height, | |
272725c7 | 8666 | fb->format->cpp[0] * 8, base, fb->pitches[0], |
2844a921 | 8667 | plane_config->size); |
b113d5ee | 8668 | |
2d14030b | 8669 | plane_config->fb = intel_fb; |
4c6baa59 JB |
8670 | } |
8671 | ||
0e8ffe1b | 8672 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8673 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8674 | { |
8675 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8676 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e | 8677 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 8678 | uint32_t tmp; |
1729050e | 8679 | bool ret; |
0e8ffe1b | 8680 | |
1729050e ID |
8681 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8682 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
930e8c9e PZ |
8683 | return false; |
8684 | ||
e143a21c | 8685 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 8686 | pipe_config->shared_dpll = NULL; |
eccb140b | 8687 | |
1729050e | 8688 | ret = false; |
0e8ffe1b DV |
8689 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8690 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 8691 | goto out; |
0e8ffe1b | 8692 | |
42571aef VS |
8693 | switch (tmp & PIPECONF_BPC_MASK) { |
8694 | case PIPECONF_6BPC: | |
8695 | pipe_config->pipe_bpp = 18; | |
8696 | break; | |
8697 | case PIPECONF_8BPC: | |
8698 | pipe_config->pipe_bpp = 24; | |
8699 | break; | |
8700 | case PIPECONF_10BPC: | |
8701 | pipe_config->pipe_bpp = 30; | |
8702 | break; | |
8703 | case PIPECONF_12BPC: | |
8704 | pipe_config->pipe_bpp = 36; | |
8705 | break; | |
8706 | default: | |
8707 | break; | |
8708 | } | |
8709 | ||
b5a9fa09 DV |
8710 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
8711 | pipe_config->limited_color_range = true; | |
8712 | ||
ab9412ba | 8713 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 | 8714 | struct intel_shared_dpll *pll; |
8106ddbd | 8715 | enum intel_dpll_id pll_id; |
66e985c0 | 8716 | |
88adfff1 DV |
8717 | pipe_config->has_pch_encoder = true; |
8718 | ||
627eb5a3 DV |
8719 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
8720 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
8721 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
8722 | |
8723 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 8724 | |
2d1fe073 | 8725 | if (HAS_PCH_IBX(dev_priv)) { |
d9a7bc67 ID |
8726 | /* |
8727 | * The pipe->pch transcoder and pch transcoder->pll | |
8728 | * mapping is fixed. | |
8729 | */ | |
8106ddbd | 8730 | pll_id = (enum intel_dpll_id) crtc->pipe; |
c0d43d62 DV |
8731 | } else { |
8732 | tmp = I915_READ(PCH_DPLL_SEL); | |
8733 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8106ddbd | 8734 | pll_id = DPLL_ID_PCH_PLL_B; |
c0d43d62 | 8735 | else |
8106ddbd | 8736 | pll_id= DPLL_ID_PCH_PLL_A; |
c0d43d62 | 8737 | } |
66e985c0 | 8738 | |
8106ddbd ACO |
8739 | pipe_config->shared_dpll = |
8740 | intel_get_shared_dpll_by_id(dev_priv, pll_id); | |
8741 | pll = pipe_config->shared_dpll; | |
66e985c0 | 8742 | |
2edd6443 ACO |
8743 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
8744 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
8745 | |
8746 | tmp = pipe_config->dpll_hw_state.dpll; | |
8747 | pipe_config->pixel_multiplier = | |
8748 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
8749 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
8750 | |
8751 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
8752 | } else { |
8753 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
8754 | } |
8755 | ||
1bd1bd80 | 8756 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 8757 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 8758 | |
2fa2fe9a DV |
8759 | ironlake_get_pfit_config(crtc, pipe_config); |
8760 | ||
1729050e ID |
8761 | ret = true; |
8762 | ||
8763 | out: | |
8764 | intel_display_power_put(dev_priv, power_domain); | |
8765 | ||
8766 | return ret; | |
0e8ffe1b DV |
8767 | } |
8768 | ||
be256dc7 PZ |
8769 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
8770 | { | |
91c8a326 | 8771 | struct drm_device *dev = &dev_priv->drm; |
be256dc7 | 8772 | struct intel_crtc *crtc; |
be256dc7 | 8773 | |
d3fcc808 | 8774 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 8775 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
8776 | pipe_name(crtc->pipe)); |
8777 | ||
e2c719b7 RC |
8778 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
8779 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
8780 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
8781 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
44cb734c | 8782 | I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n"); |
e2c719b7 | 8783 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
be256dc7 | 8784 | "CPU PWM1 enabled\n"); |
772c2a51 | 8785 | if (IS_HASWELL(dev_priv)) |
e2c719b7 | 8786 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 8787 | "CPU PWM2 enabled\n"); |
e2c719b7 | 8788 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 8789 | "PCH PWM1 enabled\n"); |
e2c719b7 | 8790 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 8791 | "Utility pin enabled\n"); |
e2c719b7 | 8792 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 8793 | |
9926ada1 PZ |
8794 | /* |
8795 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
8796 | * interrupts remain enabled. We used to check for that, but since it's | |
8797 | * gen-specific and since we only disable LCPLL after we fully disable | |
8798 | * the interrupts, the check below should be enough. | |
8799 | */ | |
e2c719b7 | 8800 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
8801 | } |
8802 | ||
9ccd5aeb PZ |
8803 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
8804 | { | |
772c2a51 | 8805 | if (IS_HASWELL(dev_priv)) |
9ccd5aeb PZ |
8806 | return I915_READ(D_COMP_HSW); |
8807 | else | |
8808 | return I915_READ(D_COMP_BDW); | |
8809 | } | |
8810 | ||
3c4c9b81 PZ |
8811 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
8812 | { | |
772c2a51 | 8813 | if (IS_HASWELL(dev_priv)) { |
3c4c9b81 PZ |
8814 | mutex_lock(&dev_priv->rps.hw_lock); |
8815 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
8816 | val)) | |
79cf219a | 8817 | DRM_DEBUG_KMS("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
8818 | mutex_unlock(&dev_priv->rps.hw_lock); |
8819 | } else { | |
9ccd5aeb PZ |
8820 | I915_WRITE(D_COMP_BDW, val); |
8821 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 8822 | } |
be256dc7 PZ |
8823 | } |
8824 | ||
8825 | /* | |
8826 | * This function implements pieces of two sequences from BSpec: | |
8827 | * - Sequence for display software to disable LCPLL | |
8828 | * - Sequence for display software to allow package C8+ | |
8829 | * The steps implemented here are just the steps that actually touch the LCPLL | |
8830 | * register. Callers should take care of disabling all the display engine | |
8831 | * functions, doing the mode unset, fixing interrupts, etc. | |
8832 | */ | |
6ff58d53 PZ |
8833 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
8834 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
8835 | { |
8836 | uint32_t val; | |
8837 | ||
8838 | assert_can_disable_lcpll(dev_priv); | |
8839 | ||
8840 | val = I915_READ(LCPLL_CTL); | |
8841 | ||
8842 | if (switch_to_fclk) { | |
8843 | val |= LCPLL_CD_SOURCE_FCLK; | |
8844 | I915_WRITE(LCPLL_CTL, val); | |
8845 | ||
f53dd63f ID |
8846 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
8847 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
be256dc7 PZ |
8848 | DRM_ERROR("Switching to FCLK failed\n"); |
8849 | ||
8850 | val = I915_READ(LCPLL_CTL); | |
8851 | } | |
8852 | ||
8853 | val |= LCPLL_PLL_DISABLE; | |
8854 | I915_WRITE(LCPLL_CTL, val); | |
8855 | POSTING_READ(LCPLL_CTL); | |
8856 | ||
24d8441d | 8857 | if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1)) |
be256dc7 PZ |
8858 | DRM_ERROR("LCPLL still locked\n"); |
8859 | ||
9ccd5aeb | 8860 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 8861 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 8862 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8863 | ndelay(100); |
8864 | ||
9ccd5aeb PZ |
8865 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
8866 | 1)) | |
be256dc7 PZ |
8867 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
8868 | ||
8869 | if (allow_power_down) { | |
8870 | val = I915_READ(LCPLL_CTL); | |
8871 | val |= LCPLL_POWER_DOWN_ALLOW; | |
8872 | I915_WRITE(LCPLL_CTL, val); | |
8873 | POSTING_READ(LCPLL_CTL); | |
8874 | } | |
8875 | } | |
8876 | ||
8877 | /* | |
8878 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
8879 | * source. | |
8880 | */ | |
6ff58d53 | 8881 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
8882 | { |
8883 | uint32_t val; | |
8884 | ||
8885 | val = I915_READ(LCPLL_CTL); | |
8886 | ||
8887 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
8888 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
8889 | return; | |
8890 | ||
a8a8bd54 PZ |
8891 | /* |
8892 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
8893 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 8894 | */ |
59bad947 | 8895 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 8896 | |
be256dc7 PZ |
8897 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
8898 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
8899 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 8900 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
8901 | } |
8902 | ||
9ccd5aeb | 8903 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
8904 | val |= D_COMP_COMP_FORCE; |
8905 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 8906 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8907 | |
8908 | val = I915_READ(LCPLL_CTL); | |
8909 | val &= ~LCPLL_PLL_DISABLE; | |
8910 | I915_WRITE(LCPLL_CTL, val); | |
8911 | ||
93220c08 CW |
8912 | if (intel_wait_for_register(dev_priv, |
8913 | LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
8914 | 5)) | |
be256dc7 PZ |
8915 | DRM_ERROR("LCPLL not locked yet\n"); |
8916 | ||
8917 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
8918 | val = I915_READ(LCPLL_CTL); | |
8919 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
8920 | I915_WRITE(LCPLL_CTL, val); | |
8921 | ||
f53dd63f ID |
8922 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
8923 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
be256dc7 PZ |
8924 | DRM_ERROR("Switching back to LCPLL failed\n"); |
8925 | } | |
215733fa | 8926 | |
59bad947 | 8927 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
4c75b940 | 8928 | intel_update_cdclk(dev_priv); |
be256dc7 PZ |
8929 | } |
8930 | ||
765dab67 PZ |
8931 | /* |
8932 | * Package states C8 and deeper are really deep PC states that can only be | |
8933 | * reached when all the devices on the system allow it, so even if the graphics | |
8934 | * device allows PC8+, it doesn't mean the system will actually get to these | |
8935 | * states. Our driver only allows PC8+ when going into runtime PM. | |
8936 | * | |
8937 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
8938 | * well is disabled and most interrupts are disabled, and these are also | |
8939 | * requirements for runtime PM. When these conditions are met, we manually do | |
8940 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
8941 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
8942 | * hang the machine. | |
8943 | * | |
8944 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
8945 | * the state of some registers, so when we come back from PC8+ we need to | |
8946 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
8947 | * need to take care of the registers kept by RC6. Notice that this happens even | |
8948 | * if we don't put the device in PCI D3 state (which is what currently happens | |
8949 | * because of the runtime PM support). | |
8950 | * | |
8951 | * For more, read "Display Sequences for Package C8" on the hardware | |
8952 | * documentation. | |
8953 | */ | |
a14cb6fc | 8954 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 8955 | { |
c67a470b PZ |
8956 | uint32_t val; |
8957 | ||
c67a470b PZ |
8958 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
8959 | ||
4f8036a2 | 8960 | if (HAS_PCH_LPT_LP(dev_priv)) { |
c67a470b PZ |
8961 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
8962 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
8963 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8964 | } | |
8965 | ||
c39055b0 | 8966 | lpt_disable_clkout_dp(dev_priv); |
c67a470b PZ |
8967 | hsw_disable_lcpll(dev_priv, true, true); |
8968 | } | |
8969 | ||
a14cb6fc | 8970 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 8971 | { |
c67a470b PZ |
8972 | uint32_t val; |
8973 | ||
c67a470b PZ |
8974 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
8975 | ||
8976 | hsw_restore_lcpll(dev_priv); | |
c39055b0 | 8977 | lpt_init_pch_refclk(dev_priv); |
c67a470b | 8978 | |
4f8036a2 | 8979 | if (HAS_PCH_LPT_LP(dev_priv)) { |
c67a470b PZ |
8980 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
8981 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
8982 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8983 | } | |
c67a470b PZ |
8984 | } |
8985 | ||
190f68c5 ACO |
8986 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
8987 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 8988 | { |
d7edc4e5 | 8989 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) { |
44a126ba PZ |
8990 | struct intel_encoder *encoder = |
8991 | intel_ddi_get_crtc_new_encoder(crtc_state); | |
8992 | ||
8993 | if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) { | |
8994 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
8995 | pipe_name(crtc->pipe)); | |
af3997b5 | 8996 | return -EINVAL; |
44a126ba | 8997 | } |
af3997b5 | 8998 | } |
716c2e55 | 8999 | |
c7653199 | 9000 | crtc->lowfreq_avail = false; |
644cef34 | 9001 | |
c8f7a0db | 9002 | return 0; |
79e53945 JB |
9003 | } |
9004 | ||
8b0f7e06 KM |
9005 | static void cannonlake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9006 | enum port port, | |
9007 | struct intel_crtc_state *pipe_config) | |
9008 | { | |
9009 | enum intel_dpll_id id; | |
9010 | u32 temp; | |
9011 | ||
9012 | temp = I915_READ(DPCLKA_CFGCR0) & DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port); | |
9013 | id = temp >> (port * 2); | |
9014 | ||
9015 | if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL2)) | |
9016 | return; | |
9017 | ||
9018 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
9019 | } | |
9020 | ||
3760b59c S |
9021 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9022 | enum port port, | |
9023 | struct intel_crtc_state *pipe_config) | |
9024 | { | |
8106ddbd ACO |
9025 | enum intel_dpll_id id; |
9026 | ||
3760b59c S |
9027 | switch (port) { |
9028 | case PORT_A: | |
08250c4b | 9029 | id = DPLL_ID_SKL_DPLL0; |
3760b59c S |
9030 | break; |
9031 | case PORT_B: | |
08250c4b | 9032 | id = DPLL_ID_SKL_DPLL1; |
3760b59c S |
9033 | break; |
9034 | case PORT_C: | |
08250c4b | 9035 | id = DPLL_ID_SKL_DPLL2; |
3760b59c S |
9036 | break; |
9037 | default: | |
9038 | DRM_ERROR("Incorrect port type\n"); | |
8106ddbd | 9039 | return; |
3760b59c | 9040 | } |
8106ddbd ACO |
9041 | |
9042 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
3760b59c S |
9043 | } |
9044 | ||
96b7dfb7 S |
9045 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9046 | enum port port, | |
5cec258b | 9047 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9048 | { |
8106ddbd | 9049 | enum intel_dpll_id id; |
a3c988ea | 9050 | u32 temp; |
96b7dfb7 S |
9051 | |
9052 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
c856052a | 9053 | id = temp >> (port * 3 + 1); |
96b7dfb7 | 9054 | |
c856052a | 9055 | if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3)) |
8106ddbd | 9056 | return; |
8106ddbd ACO |
9057 | |
9058 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
96b7dfb7 S |
9059 | } |
9060 | ||
7d2c8175 DL |
9061 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9062 | enum port port, | |
5cec258b | 9063 | struct intel_crtc_state *pipe_config) |
7d2c8175 | 9064 | { |
8106ddbd | 9065 | enum intel_dpll_id id; |
c856052a | 9066 | uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
8106ddbd | 9067 | |
c856052a | 9068 | switch (ddi_pll_sel) { |
7d2c8175 | 9069 | case PORT_CLK_SEL_WRPLL1: |
8106ddbd | 9070 | id = DPLL_ID_WRPLL1; |
7d2c8175 DL |
9071 | break; |
9072 | case PORT_CLK_SEL_WRPLL2: | |
8106ddbd | 9073 | id = DPLL_ID_WRPLL2; |
7d2c8175 | 9074 | break; |
00490c22 | 9075 | case PORT_CLK_SEL_SPLL: |
8106ddbd | 9076 | id = DPLL_ID_SPLL; |
79bd23da | 9077 | break; |
9d16da65 ACO |
9078 | case PORT_CLK_SEL_LCPLL_810: |
9079 | id = DPLL_ID_LCPLL_810; | |
9080 | break; | |
9081 | case PORT_CLK_SEL_LCPLL_1350: | |
9082 | id = DPLL_ID_LCPLL_1350; | |
9083 | break; | |
9084 | case PORT_CLK_SEL_LCPLL_2700: | |
9085 | id = DPLL_ID_LCPLL_2700; | |
9086 | break; | |
8106ddbd | 9087 | default: |
c856052a | 9088 | MISSING_CASE(ddi_pll_sel); |
8106ddbd ACO |
9089 | /* fall through */ |
9090 | case PORT_CLK_SEL_NONE: | |
8106ddbd | 9091 | return; |
7d2c8175 | 9092 | } |
8106ddbd ACO |
9093 | |
9094 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
7d2c8175 DL |
9095 | } |
9096 | ||
cf30429e JN |
9097 | static bool hsw_get_transcoder_state(struct intel_crtc *crtc, |
9098 | struct intel_crtc_state *pipe_config, | |
d8fc70b7 | 9099 | u64 *power_domain_mask) |
cf30429e JN |
9100 | { |
9101 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9102 | struct drm_i915_private *dev_priv = to_i915(dev); |
cf30429e JN |
9103 | enum intel_display_power_domain power_domain; |
9104 | u32 tmp; | |
9105 | ||
d9a7bc67 ID |
9106 | /* |
9107 | * The pipe->transcoder mapping is fixed with the exception of the eDP | |
9108 | * transcoder handled below. | |
9109 | */ | |
cf30429e JN |
9110 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
9111 | ||
9112 | /* | |
9113 | * XXX: Do intel_display_power_get_if_enabled before reading this (for | |
9114 | * consistency and less surprising code; it's in always on power). | |
9115 | */ | |
9116 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
9117 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9118 | enum pipe trans_edp_pipe; | |
9119 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9120 | default: | |
9121 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9122 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9123 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9124 | trans_edp_pipe = PIPE_A; | |
9125 | break; | |
9126 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9127 | trans_edp_pipe = PIPE_B; | |
9128 | break; | |
9129 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9130 | trans_edp_pipe = PIPE_C; | |
9131 | break; | |
9132 | } | |
9133 | ||
9134 | if (trans_edp_pipe == crtc->pipe) | |
9135 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
9136 | } | |
9137 | ||
9138 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); | |
9139 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
9140 | return false; | |
d8fc70b7 | 9141 | *power_domain_mask |= BIT_ULL(power_domain); |
cf30429e JN |
9142 | |
9143 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); | |
9144 | ||
9145 | return tmp & PIPECONF_ENABLE; | |
9146 | } | |
9147 | ||
4d1de975 JN |
9148 | static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, |
9149 | struct intel_crtc_state *pipe_config, | |
d8fc70b7 | 9150 | u64 *power_domain_mask) |
4d1de975 JN |
9151 | { |
9152 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9153 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 JN |
9154 | enum intel_display_power_domain power_domain; |
9155 | enum port port; | |
9156 | enum transcoder cpu_transcoder; | |
9157 | u32 tmp; | |
9158 | ||
4d1de975 JN |
9159 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { |
9160 | if (port == PORT_A) | |
9161 | cpu_transcoder = TRANSCODER_DSI_A; | |
9162 | else | |
9163 | cpu_transcoder = TRANSCODER_DSI_C; | |
9164 | ||
9165 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
9166 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
9167 | continue; | |
d8fc70b7 | 9168 | *power_domain_mask |= BIT_ULL(power_domain); |
4d1de975 | 9169 | |
db18b6a6 ID |
9170 | /* |
9171 | * The PLL needs to be enabled with a valid divider | |
9172 | * configuration, otherwise accessing DSI registers will hang | |
9173 | * the machine. See BSpec North Display Engine | |
9174 | * registers/MIPI[BXT]. We can break out here early, since we | |
9175 | * need the same DSI PLL to be enabled for both DSI ports. | |
9176 | */ | |
9177 | if (!intel_dsi_pll_is_enabled(dev_priv)) | |
9178 | break; | |
9179 | ||
4d1de975 JN |
9180 | /* XXX: this works for video mode only */ |
9181 | tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
9182 | if (!(tmp & DPI_ENABLE)) | |
9183 | continue; | |
9184 | ||
9185 | tmp = I915_READ(MIPI_CTRL(port)); | |
9186 | if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) | |
9187 | continue; | |
9188 | ||
9189 | pipe_config->cpu_transcoder = cpu_transcoder; | |
4d1de975 JN |
9190 | break; |
9191 | } | |
9192 | ||
d7edc4e5 | 9193 | return transcoder_is_dsi(pipe_config->cpu_transcoder); |
4d1de975 JN |
9194 | } |
9195 | ||
26804afd | 9196 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9197 | struct intel_crtc_state *pipe_config) |
26804afd | 9198 | { |
6315b5d3 | 9199 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
d452c5b6 | 9200 | struct intel_shared_dpll *pll; |
26804afd DV |
9201 | enum port port; |
9202 | uint32_t tmp; | |
9203 | ||
9204 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9205 | ||
9206 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9207 | ||
8b0f7e06 KM |
9208 | if (IS_CANNONLAKE(dev_priv)) |
9209 | cannonlake_get_ddi_pll(dev_priv, port, pipe_config); | |
9210 | else if (IS_GEN9_BC(dev_priv)) | |
96b7dfb7 | 9211 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
cc3f90f0 | 9212 | else if (IS_GEN9_LP(dev_priv)) |
3760b59c | 9213 | bxt_get_ddi_pll(dev_priv, port, pipe_config); |
96b7dfb7 S |
9214 | else |
9215 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9216 | |
8106ddbd ACO |
9217 | pll = pipe_config->shared_dpll; |
9218 | if (pll) { | |
2edd6443 ACO |
9219 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
9220 | &pipe_config->dpll_hw_state)); | |
d452c5b6 DV |
9221 | } |
9222 | ||
26804afd DV |
9223 | /* |
9224 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9225 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9226 | * the PCH transcoder is on. | |
9227 | */ | |
6315b5d3 | 9228 | if (INTEL_GEN(dev_priv) < 9 && |
ca370455 | 9229 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
26804afd DV |
9230 | pipe_config->has_pch_encoder = true; |
9231 | ||
9232 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9233 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9234 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9235 | ||
9236 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9237 | } | |
9238 | } | |
9239 | ||
0e8ffe1b | 9240 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9241 | struct intel_crtc_state *pipe_config) |
0e8ffe1b | 9242 | { |
6315b5d3 | 9243 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1729050e | 9244 | enum intel_display_power_domain power_domain; |
d8fc70b7 | 9245 | u64 power_domain_mask; |
cf30429e | 9246 | bool active; |
0e8ffe1b | 9247 | |
e79dfb51 | 9248 | intel_crtc_init_scalers(crtc, pipe_config); |
5fb9dadf | 9249 | |
1729050e ID |
9250 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9251 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 | 9252 | return false; |
d8fc70b7 | 9253 | power_domain_mask = BIT_ULL(power_domain); |
1729050e | 9254 | |
8106ddbd | 9255 | pipe_config->shared_dpll = NULL; |
c0d43d62 | 9256 | |
cf30429e | 9257 | active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); |
eccb140b | 9258 | |
cc3f90f0 | 9259 | if (IS_GEN9_LP(dev_priv) && |
d7edc4e5 VS |
9260 | bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) { |
9261 | WARN_ON(active); | |
9262 | active = true; | |
4d1de975 JN |
9263 | } |
9264 | ||
cf30429e | 9265 | if (!active) |
1729050e | 9266 | goto out; |
0e8ffe1b | 9267 | |
d7edc4e5 | 9268 | if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { |
4d1de975 JN |
9269 | haswell_get_ddi_port_state(crtc, pipe_config); |
9270 | intel_get_pipe_timings(crtc, pipe_config); | |
9271 | } | |
627eb5a3 | 9272 | |
bc58be60 | 9273 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 9274 | |
05dc698c LL |
9275 | pipe_config->gamma_mode = |
9276 | I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; | |
9277 | ||
b22ca995 SS |
9278 | if (IS_BROADWELL(dev_priv) || dev_priv->info.gen >= 9) { |
9279 | u32 tmp = I915_READ(PIPEMISC(crtc->pipe)); | |
9280 | bool clrspace_yuv = tmp & PIPEMISC_OUTPUT_COLORSPACE_YUV; | |
9281 | ||
9282 | if (IS_GEMINILAKE(dev_priv) || dev_priv->info.gen >= 10) { | |
9283 | bool blend_mode_420 = tmp & | |
9284 | PIPEMISC_YUV420_MODE_FULL_BLEND; | |
9285 | ||
9286 | pipe_config->ycbcr420 = tmp & PIPEMISC_YUV420_ENABLE; | |
9287 | if (pipe_config->ycbcr420 != clrspace_yuv || | |
9288 | pipe_config->ycbcr420 != blend_mode_420) | |
9289 | DRM_DEBUG_KMS("Bad 4:2:0 mode (%08x)\n", tmp); | |
9290 | } else if (clrspace_yuv) { | |
9291 | DRM_DEBUG_KMS("YCbCr 4:2:0 Unsupported\n"); | |
9292 | } | |
9293 | } | |
9294 | ||
1729050e ID |
9295 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
9296 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
d8fc70b7 | 9297 | power_domain_mask |= BIT_ULL(power_domain); |
6315b5d3 | 9298 | if (INTEL_GEN(dev_priv) >= 9) |
bd2e244f | 9299 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 9300 | else |
1c132b44 | 9301 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 9302 | } |
88adfff1 | 9303 | |
772c2a51 | 9304 | if (IS_HASWELL(dev_priv)) |
e59150dc JB |
9305 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
9306 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 9307 | |
4d1de975 JN |
9308 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && |
9309 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { | |
ebb69c95 CT |
9310 | pipe_config->pixel_multiplier = |
9311 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
9312 | } else { | |
9313 | pipe_config->pixel_multiplier = 1; | |
9314 | } | |
6c49f241 | 9315 | |
1729050e ID |
9316 | out: |
9317 | for_each_power_domain(power_domain, power_domain_mask) | |
9318 | intel_display_power_put(dev_priv, power_domain); | |
9319 | ||
cf30429e | 9320 | return active; |
0e8ffe1b DV |
9321 | } |
9322 | ||
cd5dcbf1 | 9323 | static u32 intel_cursor_base(const struct intel_plane_state *plane_state) |
1cecc830 VS |
9324 | { |
9325 | struct drm_i915_private *dev_priv = | |
9326 | to_i915(plane_state->base.plane->dev); | |
9327 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
9328 | const struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
9329 | u32 base; | |
9330 | ||
9331 | if (INTEL_INFO(dev_priv)->cursor_needs_physical) | |
9332 | base = obj->phys_handle->busaddr; | |
9333 | else | |
9334 | base = intel_plane_ggtt_offset(plane_state); | |
9335 | ||
1e7b4fd8 VS |
9336 | base += plane_state->main.offset; |
9337 | ||
1cecc830 VS |
9338 | /* ILK+ do this automagically */ |
9339 | if (HAS_GMCH_DISPLAY(dev_priv) && | |
a82256bc | 9340 | plane_state->base.rotation & DRM_MODE_ROTATE_180) |
1cecc830 VS |
9341 | base += (plane_state->base.crtc_h * |
9342 | plane_state->base.crtc_w - 1) * fb->format->cpp[0]; | |
9343 | ||
9344 | return base; | |
9345 | } | |
9346 | ||
ed270223 VS |
9347 | static u32 intel_cursor_position(const struct intel_plane_state *plane_state) |
9348 | { | |
9349 | int x = plane_state->base.crtc_x; | |
9350 | int y = plane_state->base.crtc_y; | |
9351 | u32 pos = 0; | |
9352 | ||
9353 | if (x < 0) { | |
9354 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
9355 | x = -x; | |
9356 | } | |
9357 | pos |= x << CURSOR_X_SHIFT; | |
9358 | ||
9359 | if (y < 0) { | |
9360 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
9361 | y = -y; | |
9362 | } | |
9363 | pos |= y << CURSOR_Y_SHIFT; | |
9364 | ||
9365 | return pos; | |
9366 | } | |
9367 | ||
3637ecf0 VS |
9368 | static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state) |
9369 | { | |
9370 | const struct drm_mode_config *config = | |
9371 | &plane_state->base.plane->dev->mode_config; | |
9372 | int width = plane_state->base.crtc_w; | |
9373 | int height = plane_state->base.crtc_h; | |
9374 | ||
9375 | return width > 0 && width <= config->cursor_width && | |
9376 | height > 0 && height <= config->cursor_height; | |
9377 | } | |
9378 | ||
659056f2 VS |
9379 | static int intel_check_cursor(struct intel_crtc_state *crtc_state, |
9380 | struct intel_plane_state *plane_state) | |
9381 | { | |
9382 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
1e7b4fd8 VS |
9383 | int src_x, src_y; |
9384 | u32 offset; | |
659056f2 VS |
9385 | int ret; |
9386 | ||
9387 | ret = drm_plane_helper_check_state(&plane_state->base, | |
9388 | &plane_state->clip, | |
9389 | DRM_PLANE_HELPER_NO_SCALING, | |
9390 | DRM_PLANE_HELPER_NO_SCALING, | |
9391 | true, true); | |
9392 | if (ret) | |
9393 | return ret; | |
9394 | ||
9395 | if (!fb) | |
9396 | return 0; | |
9397 | ||
9398 | if (fb->modifier != DRM_FORMAT_MOD_LINEAR) { | |
9399 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); | |
9400 | return -EINVAL; | |
9401 | } | |
9402 | ||
1e7b4fd8 VS |
9403 | src_x = plane_state->base.src_x >> 16; |
9404 | src_y = plane_state->base.src_y >> 16; | |
9405 | ||
9406 | intel_add_fb_offsets(&src_x, &src_y, plane_state, 0); | |
9407 | offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0); | |
9408 | ||
9409 | if (src_x != 0 || src_y != 0) { | |
9410 | DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n"); | |
9411 | return -EINVAL; | |
9412 | } | |
9413 | ||
9414 | plane_state->main.offset = offset; | |
9415 | ||
659056f2 VS |
9416 | return 0; |
9417 | } | |
9418 | ||
292889e1 VS |
9419 | static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state, |
9420 | const struct intel_plane_state *plane_state) | |
9421 | { | |
1e1bb871 | 9422 | const struct drm_framebuffer *fb = plane_state->base.fb; |
292889e1 | 9423 | |
292889e1 VS |
9424 | return CURSOR_ENABLE | |
9425 | CURSOR_GAMMA_ENABLE | | |
9426 | CURSOR_FORMAT_ARGB | | |
1e1bb871 | 9427 | CURSOR_STRIDE(fb->pitches[0]); |
292889e1 VS |
9428 | } |
9429 | ||
659056f2 VS |
9430 | static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state) |
9431 | { | |
659056f2 | 9432 | int width = plane_state->base.crtc_w; |
659056f2 VS |
9433 | |
9434 | /* | |
9435 | * 845g/865g are only limited by the width of their cursors, | |
9436 | * the height is arbitrary up to the precision of the register. | |
9437 | */ | |
3637ecf0 | 9438 | return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64); |
659056f2 VS |
9439 | } |
9440 | ||
9441 | static int i845_check_cursor(struct intel_plane *plane, | |
9442 | struct intel_crtc_state *crtc_state, | |
9443 | struct intel_plane_state *plane_state) | |
9444 | { | |
9445 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
659056f2 VS |
9446 | int ret; |
9447 | ||
9448 | ret = intel_check_cursor(crtc_state, plane_state); | |
9449 | if (ret) | |
9450 | return ret; | |
9451 | ||
9452 | /* if we want to turn off the cursor ignore width and height */ | |
1e1bb871 | 9453 | if (!fb) |
659056f2 VS |
9454 | return 0; |
9455 | ||
9456 | /* Check for which cursor types we support */ | |
9457 | if (!i845_cursor_size_ok(plane_state)) { | |
9458 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", | |
9459 | plane_state->base.crtc_w, | |
9460 | plane_state->base.crtc_h); | |
9461 | return -EINVAL; | |
9462 | } | |
9463 | ||
1e1bb871 | 9464 | switch (fb->pitches[0]) { |
292889e1 VS |
9465 | case 256: |
9466 | case 512: | |
9467 | case 1024: | |
9468 | case 2048: | |
9469 | break; | |
1e1bb871 VS |
9470 | default: |
9471 | DRM_DEBUG_KMS("Invalid cursor stride (%u)\n", | |
9472 | fb->pitches[0]); | |
9473 | return -EINVAL; | |
292889e1 VS |
9474 | } |
9475 | ||
659056f2 VS |
9476 | plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state); |
9477 | ||
9478 | return 0; | |
292889e1 VS |
9479 | } |
9480 | ||
b2d03b0d VS |
9481 | static void i845_update_cursor(struct intel_plane *plane, |
9482 | const struct intel_crtc_state *crtc_state, | |
55a08b3f | 9483 | const struct intel_plane_state *plane_state) |
560b85bb | 9484 | { |
cd5dcbf1 | 9485 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
b2d03b0d VS |
9486 | u32 cntl = 0, base = 0, pos = 0, size = 0; |
9487 | unsigned long irqflags; | |
560b85bb | 9488 | |
936e71e3 | 9489 | if (plane_state && plane_state->base.visible) { |
55a08b3f ML |
9490 | unsigned int width = plane_state->base.crtc_w; |
9491 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 | 9492 | |
a0864d59 | 9493 | cntl = plane_state->ctl; |
dc41c154 | 9494 | size = (height << 12) | width; |
560b85bb | 9495 | |
b2d03b0d VS |
9496 | base = intel_cursor_base(plane_state); |
9497 | pos = intel_cursor_position(plane_state); | |
4b0e333e | 9498 | } |
560b85bb | 9499 | |
b2d03b0d | 9500 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
4726e0b0 | 9501 | |
e11ffddb VS |
9502 | /* On these chipsets we can only modify the base/size/stride |
9503 | * whilst the cursor is disabled. | |
9504 | */ | |
9505 | if (plane->cursor.base != base || | |
9506 | plane->cursor.size != size || | |
9507 | plane->cursor.cntl != cntl) { | |
dd584fc0 | 9508 | I915_WRITE_FW(CURCNTR(PIPE_A), 0); |
dd584fc0 | 9509 | I915_WRITE_FW(CURBASE(PIPE_A), base); |
dd584fc0 | 9510 | I915_WRITE_FW(CURSIZE, size); |
b2d03b0d | 9511 | I915_WRITE_FW(CURPOS(PIPE_A), pos); |
dd584fc0 | 9512 | I915_WRITE_FW(CURCNTR(PIPE_A), cntl); |
75343a44 | 9513 | |
e11ffddb VS |
9514 | plane->cursor.base = base; |
9515 | plane->cursor.size = size; | |
9516 | plane->cursor.cntl = cntl; | |
9517 | } else { | |
9518 | I915_WRITE_FW(CURPOS(PIPE_A), pos); | |
560b85bb | 9519 | } |
e11ffddb | 9520 | |
75343a44 | 9521 | POSTING_READ_FW(CURCNTR(PIPE_A)); |
b2d03b0d VS |
9522 | |
9523 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
9524 | } | |
9525 | ||
9526 | static void i845_disable_cursor(struct intel_plane *plane, | |
9527 | struct intel_crtc *crtc) | |
9528 | { | |
9529 | i845_update_cursor(plane, NULL, NULL); | |
560b85bb CW |
9530 | } |
9531 | ||
292889e1 VS |
9532 | static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state, |
9533 | const struct intel_plane_state *plane_state) | |
9534 | { | |
9535 | struct drm_i915_private *dev_priv = | |
9536 | to_i915(plane_state->base.plane->dev); | |
9537 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
292889e1 VS |
9538 | u32 cntl; |
9539 | ||
9540 | cntl = MCURSOR_GAMMA_ENABLE; | |
9541 | ||
9542 | if (HAS_DDI(dev_priv)) | |
9543 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
9544 | ||
d509e28b | 9545 | cntl |= MCURSOR_PIPE_SELECT(crtc->pipe); |
292889e1 VS |
9546 | |
9547 | switch (plane_state->base.crtc_w) { | |
9548 | case 64: | |
9549 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
9550 | break; | |
9551 | case 128: | |
9552 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
9553 | break; | |
9554 | case 256: | |
9555 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
9556 | break; | |
9557 | default: | |
9558 | MISSING_CASE(plane_state->base.crtc_w); | |
9559 | return 0; | |
9560 | } | |
9561 | ||
c2c446ad | 9562 | if (plane_state->base.rotation & DRM_MODE_ROTATE_180) |
292889e1 VS |
9563 | cntl |= CURSOR_ROTATE_180; |
9564 | ||
9565 | return cntl; | |
9566 | } | |
9567 | ||
659056f2 | 9568 | static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state) |
65a21cd6 | 9569 | { |
024faac7 VS |
9570 | struct drm_i915_private *dev_priv = |
9571 | to_i915(plane_state->base.plane->dev); | |
659056f2 VS |
9572 | int width = plane_state->base.crtc_w; |
9573 | int height = plane_state->base.crtc_h; | |
4b0e333e | 9574 | |
3637ecf0 | 9575 | if (!intel_cursor_size_ok(plane_state)) |
659056f2 | 9576 | return false; |
4398ad45 | 9577 | |
024faac7 VS |
9578 | /* Cursor width is limited to a few power-of-two sizes */ |
9579 | switch (width) { | |
659056f2 VS |
9580 | case 256: |
9581 | case 128: | |
659056f2 VS |
9582 | case 64: |
9583 | break; | |
9584 | default: | |
9585 | return false; | |
65a21cd6 | 9586 | } |
4b0e333e | 9587 | |
024faac7 VS |
9588 | /* |
9589 | * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor | |
9590 | * height from 8 lines up to the cursor width, when the | |
9591 | * cursor is not rotated. Everything else requires square | |
9592 | * cursors. | |
9593 | */ | |
9594 | if (HAS_CUR_FBC(dev_priv) && | |
a82256bc | 9595 | plane_state->base.rotation & DRM_MODE_ROTATE_0) { |
024faac7 VS |
9596 | if (height < 8 || height > width) |
9597 | return false; | |
9598 | } else { | |
9599 | if (height != width) | |
9600 | return false; | |
9601 | } | |
99d1f387 | 9602 | |
659056f2 | 9603 | return true; |
65a21cd6 JB |
9604 | } |
9605 | ||
659056f2 VS |
9606 | static int i9xx_check_cursor(struct intel_plane *plane, |
9607 | struct intel_crtc_state *crtc_state, | |
9608 | struct intel_plane_state *plane_state) | |
cda4b7d3 | 9609 | { |
659056f2 VS |
9610 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
9611 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
659056f2 | 9612 | enum pipe pipe = plane->pipe; |
659056f2 | 9613 | int ret; |
cda4b7d3 | 9614 | |
659056f2 VS |
9615 | ret = intel_check_cursor(crtc_state, plane_state); |
9616 | if (ret) | |
9617 | return ret; | |
cda4b7d3 | 9618 | |
659056f2 | 9619 | /* if we want to turn off the cursor ignore width and height */ |
1e1bb871 | 9620 | if (!fb) |
659056f2 | 9621 | return 0; |
55a08b3f | 9622 | |
659056f2 VS |
9623 | /* Check for which cursor types we support */ |
9624 | if (!i9xx_cursor_size_ok(plane_state)) { | |
9625 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", | |
9626 | plane_state->base.crtc_w, | |
9627 | plane_state->base.crtc_h); | |
9628 | return -EINVAL; | |
cda4b7d3 | 9629 | } |
cda4b7d3 | 9630 | |
1e1bb871 VS |
9631 | if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) { |
9632 | DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n", | |
9633 | fb->pitches[0], plane_state->base.crtc_w); | |
9634 | return -EINVAL; | |
659056f2 | 9635 | } |
dd584fc0 | 9636 | |
659056f2 VS |
9637 | /* |
9638 | * There's something wrong with the cursor on CHV pipe C. | |
9639 | * If it straddles the left edge of the screen then | |
9640 | * moving it away from the edge or disabling it often | |
9641 | * results in a pipe underrun, and often that can lead to | |
9642 | * dead pipe (constant underrun reported, and it scans | |
9643 | * out just a solid color). To recover from that, the | |
9644 | * display power well must be turned off and on again. | |
9645 | * Refuse the put the cursor into that compromised position. | |
9646 | */ | |
9647 | if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C && | |
9648 | plane_state->base.visible && plane_state->base.crtc_x < 0) { | |
9649 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); | |
9650 | return -EINVAL; | |
9651 | } | |
5efb3e28 | 9652 | |
659056f2 | 9653 | plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state); |
dd584fc0 | 9654 | |
659056f2 | 9655 | return 0; |
cda4b7d3 CW |
9656 | } |
9657 | ||
b2d03b0d VS |
9658 | static void i9xx_update_cursor(struct intel_plane *plane, |
9659 | const struct intel_crtc_state *crtc_state, | |
55a08b3f | 9660 | const struct intel_plane_state *plane_state) |
dc41c154 | 9661 | { |
cd5dcbf1 VS |
9662 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
9663 | enum pipe pipe = plane->pipe; | |
024faac7 | 9664 | u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0; |
b2d03b0d | 9665 | unsigned long irqflags; |
dc41c154 | 9666 | |
b2d03b0d | 9667 | if (plane_state && plane_state->base.visible) { |
a0864d59 | 9668 | cntl = plane_state->ctl; |
dc41c154 | 9669 | |
024faac7 VS |
9670 | if (plane_state->base.crtc_h != plane_state->base.crtc_w) |
9671 | fbc_ctl = CUR_FBC_CTL_EN | (plane_state->base.crtc_h - 1); | |
dc41c154 | 9672 | |
b2d03b0d VS |
9673 | base = intel_cursor_base(plane_state); |
9674 | pos = intel_cursor_position(plane_state); | |
9675 | } | |
9676 | ||
9677 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
9678 | ||
e11ffddb VS |
9679 | /* |
9680 | * On some platforms writing CURCNTR first will also | |
9681 | * cause CURPOS to be armed by the CURBASE write. | |
9682 | * Without the CURCNTR write the CURPOS write would | |
8753d2bc VS |
9683 | * arm itself. Thus we always start the full update |
9684 | * with a CURCNTR write. | |
9685 | * | |
9686 | * On other platforms CURPOS always requires the | |
9687 | * CURBASE write to arm the update. Additonally | |
9688 | * a write to any of the cursor register will cancel | |
9689 | * an already armed cursor update. Thus leaving out | |
9690 | * the CURBASE write after CURPOS could lead to a | |
9691 | * cursor that doesn't appear to move, or even change | |
9692 | * shape. Thus we always write CURBASE. | |
e11ffddb VS |
9693 | * |
9694 | * CURCNTR and CUR_FBC_CTL are always | |
9695 | * armed by the CURBASE write only. | |
9696 | */ | |
9697 | if (plane->cursor.base != base || | |
9698 | plane->cursor.size != fbc_ctl || | |
9699 | plane->cursor.cntl != cntl) { | |
dd584fc0 | 9700 | I915_WRITE_FW(CURCNTR(pipe), cntl); |
e11ffddb VS |
9701 | if (HAS_CUR_FBC(dev_priv)) |
9702 | I915_WRITE_FW(CUR_FBC_CTL(pipe), fbc_ctl); | |
b2d03b0d | 9703 | I915_WRITE_FW(CURPOS(pipe), pos); |
75343a44 VS |
9704 | I915_WRITE_FW(CURBASE(pipe), base); |
9705 | ||
e11ffddb VS |
9706 | plane->cursor.base = base; |
9707 | plane->cursor.size = fbc_ctl; | |
9708 | plane->cursor.cntl = cntl; | |
dc41c154 | 9709 | } else { |
e11ffddb | 9710 | I915_WRITE_FW(CURPOS(pipe), pos); |
8753d2bc | 9711 | I915_WRITE_FW(CURBASE(pipe), base); |
dc41c154 VS |
9712 | } |
9713 | ||
dd584fc0 | 9714 | POSTING_READ_FW(CURBASE(pipe)); |
99d1f387 | 9715 | |
b2d03b0d | 9716 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
65a21cd6 JB |
9717 | } |
9718 | ||
b2d03b0d VS |
9719 | static void i9xx_disable_cursor(struct intel_plane *plane, |
9720 | struct intel_crtc *crtc) | |
cda4b7d3 | 9721 | { |
b2d03b0d | 9722 | i9xx_update_cursor(plane, NULL, NULL); |
dc41c154 VS |
9723 | } |
9724 | ||
dc41c154 | 9725 | |
79e53945 JB |
9726 | /* VESA 640x480x72Hz mode to set on the pipe */ |
9727 | static struct drm_display_mode load_detect_mode = { | |
9728 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
9729 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
9730 | }; | |
9731 | ||
a8bb6818 | 9732 | struct drm_framebuffer * |
24dbf51a CW |
9733 | intel_framebuffer_create(struct drm_i915_gem_object *obj, |
9734 | struct drm_mode_fb_cmd2 *mode_cmd) | |
d2dff872 CW |
9735 | { |
9736 | struct intel_framebuffer *intel_fb; | |
9737 | int ret; | |
9738 | ||
9739 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 9740 | if (!intel_fb) |
d2dff872 | 9741 | return ERR_PTR(-ENOMEM); |
d2dff872 | 9742 | |
24dbf51a | 9743 | ret = intel_framebuffer_init(intel_fb, obj, mode_cmd); |
dd4916c5 DV |
9744 | if (ret) |
9745 | goto err; | |
d2dff872 CW |
9746 | |
9747 | return &intel_fb->base; | |
dcb1394e | 9748 | |
dd4916c5 | 9749 | err: |
dd4916c5 | 9750 | kfree(intel_fb); |
dd4916c5 | 9751 | return ERR_PTR(ret); |
d2dff872 CW |
9752 | } |
9753 | ||
9754 | static u32 | |
9755 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
9756 | { | |
9757 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
9758 | return ALIGN(pitch, 64); | |
9759 | } | |
9760 | ||
9761 | static u32 | |
9762 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
9763 | { | |
9764 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 9765 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
9766 | } |
9767 | ||
9768 | static struct drm_framebuffer * | |
9769 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
9770 | struct drm_display_mode *mode, | |
9771 | int depth, int bpp) | |
9772 | { | |
dcb1394e | 9773 | struct drm_framebuffer *fb; |
d2dff872 | 9774 | struct drm_i915_gem_object *obj; |
0fed39bd | 9775 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 | 9776 | |
12d79d78 | 9777 | obj = i915_gem_object_create(to_i915(dev), |
d2dff872 | 9778 | intel_framebuffer_size_for_mode(mode, bpp)); |
fe3db79b CW |
9779 | if (IS_ERR(obj)) |
9780 | return ERR_CAST(obj); | |
d2dff872 CW |
9781 | |
9782 | mode_cmd.width = mode->hdisplay; | |
9783 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
9784 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
9785 | bpp); | |
5ca0c34a | 9786 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 9787 | |
24dbf51a | 9788 | fb = intel_framebuffer_create(obj, &mode_cmd); |
dcb1394e | 9789 | if (IS_ERR(fb)) |
f0cd5182 | 9790 | i915_gem_object_put(obj); |
dcb1394e LW |
9791 | |
9792 | return fb; | |
d2dff872 CW |
9793 | } |
9794 | ||
9795 | static struct drm_framebuffer * | |
9796 | mode_fits_in_fbdev(struct drm_device *dev, | |
9797 | struct drm_display_mode *mode) | |
9798 | { | |
0695726e | 9799 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
fac5e23e | 9800 | struct drm_i915_private *dev_priv = to_i915(dev); |
d2dff872 CW |
9801 | struct drm_i915_gem_object *obj; |
9802 | struct drm_framebuffer *fb; | |
9803 | ||
4c0e5528 | 9804 | if (!dev_priv->fbdev) |
d2dff872 CW |
9805 | return NULL; |
9806 | ||
4c0e5528 | 9807 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
9808 | return NULL; |
9809 | ||
4c0e5528 DV |
9810 | obj = dev_priv->fbdev->fb->obj; |
9811 | BUG_ON(!obj); | |
9812 | ||
8bcd4553 | 9813 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 | 9814 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
272725c7 | 9815 | fb->format->cpp[0] * 8)) |
d2dff872 CW |
9816 | return NULL; |
9817 | ||
01f2c773 | 9818 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
9819 | return NULL; |
9820 | ||
edde3617 | 9821 | drm_framebuffer_reference(fb); |
d2dff872 | 9822 | return fb; |
4520f53a DV |
9823 | #else |
9824 | return NULL; | |
9825 | #endif | |
d2dff872 CW |
9826 | } |
9827 | ||
d3a40d1b ACO |
9828 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
9829 | struct drm_crtc *crtc, | |
9830 | struct drm_display_mode *mode, | |
9831 | struct drm_framebuffer *fb, | |
9832 | int x, int y) | |
9833 | { | |
9834 | struct drm_plane_state *plane_state; | |
9835 | int hdisplay, vdisplay; | |
9836 | int ret; | |
9837 | ||
9838 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
9839 | if (IS_ERR(plane_state)) | |
9840 | return PTR_ERR(plane_state); | |
9841 | ||
9842 | if (mode) | |
196cd5d3 | 9843 | drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay); |
d3a40d1b ACO |
9844 | else |
9845 | hdisplay = vdisplay = 0; | |
9846 | ||
9847 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
9848 | if (ret) | |
9849 | return ret; | |
9850 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
9851 | plane_state->crtc_x = 0; | |
9852 | plane_state->crtc_y = 0; | |
9853 | plane_state->crtc_w = hdisplay; | |
9854 | plane_state->crtc_h = vdisplay; | |
9855 | plane_state->src_x = x << 16; | |
9856 | plane_state->src_y = y << 16; | |
9857 | plane_state->src_w = hdisplay << 16; | |
9858 | plane_state->src_h = vdisplay << 16; | |
9859 | ||
9860 | return 0; | |
9861 | } | |
9862 | ||
6c5ed5ae ML |
9863 | int intel_get_load_detect_pipe(struct drm_connector *connector, |
9864 | struct drm_display_mode *mode, | |
9865 | struct intel_load_detect_pipe *old, | |
9866 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
9867 | { |
9868 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
9869 | struct intel_encoder *intel_encoder = |
9870 | intel_attached_encoder(connector); | |
79e53945 | 9871 | struct drm_crtc *possible_crtc; |
4ef69c7a | 9872 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
9873 | struct drm_crtc *crtc = NULL; |
9874 | struct drm_device *dev = encoder->dev; | |
0f0f74bc | 9875 | struct drm_i915_private *dev_priv = to_i915(dev); |
94352cf9 | 9876 | struct drm_framebuffer *fb; |
51fd371b | 9877 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 9878 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 9879 | struct drm_connector_state *connector_state; |
4be07317 | 9880 | struct intel_crtc_state *crtc_state; |
51fd371b | 9881 | int ret, i = -1; |
79e53945 | 9882 | |
d2dff872 | 9883 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9884 | connector->base.id, connector->name, |
8e329a03 | 9885 | encoder->base.id, encoder->name); |
d2dff872 | 9886 | |
edde3617 ML |
9887 | old->restore_state = NULL; |
9888 | ||
6c5ed5ae | 9889 | WARN_ON(!drm_modeset_is_locked(&config->connection_mutex)); |
6e9f798d | 9890 | |
79e53945 JB |
9891 | /* |
9892 | * Algorithm gets a little messy: | |
7a5e4805 | 9893 | * |
79e53945 JB |
9894 | * - if the connector already has an assigned crtc, use it (but make |
9895 | * sure it's on first) | |
7a5e4805 | 9896 | * |
79e53945 JB |
9897 | * - try to find the first unused crtc that can drive this connector, |
9898 | * and use that if we find one | |
79e53945 JB |
9899 | */ |
9900 | ||
9901 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
9902 | if (connector->state->crtc) { |
9903 | crtc = connector->state->crtc; | |
8261b191 | 9904 | |
51fd371b | 9905 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 9906 | if (ret) |
ad3c558f | 9907 | goto fail; |
8261b191 CW |
9908 | |
9909 | /* Make sure the crtc and connector are running */ | |
edde3617 | 9910 | goto found; |
79e53945 JB |
9911 | } |
9912 | ||
9913 | /* Find an unused one (if possible) */ | |
70e1e0ec | 9914 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
9915 | i++; |
9916 | if (!(encoder->possible_crtcs & (1 << i))) | |
9917 | continue; | |
edde3617 ML |
9918 | |
9919 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
9920 | if (ret) | |
9921 | goto fail; | |
9922 | ||
9923 | if (possible_crtc->state->enable) { | |
9924 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 9925 | continue; |
edde3617 | 9926 | } |
a459249c VS |
9927 | |
9928 | crtc = possible_crtc; | |
9929 | break; | |
79e53945 JB |
9930 | } |
9931 | ||
9932 | /* | |
9933 | * If we didn't find an unused CRTC, don't use any. | |
9934 | */ | |
9935 | if (!crtc) { | |
7173188d | 9936 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
f4bf77b4 | 9937 | ret = -ENODEV; |
ad3c558f | 9938 | goto fail; |
79e53945 JB |
9939 | } |
9940 | ||
edde3617 ML |
9941 | found: |
9942 | intel_crtc = to_intel_crtc(crtc); | |
9943 | ||
4d02e2de DV |
9944 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
9945 | if (ret) | |
ad3c558f | 9946 | goto fail; |
79e53945 | 9947 | |
83a57153 | 9948 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
9949 | restore_state = drm_atomic_state_alloc(dev); |
9950 | if (!state || !restore_state) { | |
9951 | ret = -ENOMEM; | |
9952 | goto fail; | |
9953 | } | |
83a57153 ACO |
9954 | |
9955 | state->acquire_ctx = ctx; | |
edde3617 | 9956 | restore_state->acquire_ctx = ctx; |
83a57153 | 9957 | |
944b0c76 ACO |
9958 | connector_state = drm_atomic_get_connector_state(state, connector); |
9959 | if (IS_ERR(connector_state)) { | |
9960 | ret = PTR_ERR(connector_state); | |
9961 | goto fail; | |
9962 | } | |
9963 | ||
edde3617 ML |
9964 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
9965 | if (ret) | |
9966 | goto fail; | |
944b0c76 | 9967 | |
4be07317 ACO |
9968 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
9969 | if (IS_ERR(crtc_state)) { | |
9970 | ret = PTR_ERR(crtc_state); | |
9971 | goto fail; | |
9972 | } | |
9973 | ||
49d6fa21 | 9974 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 9975 | |
6492711d CW |
9976 | if (!mode) |
9977 | mode = &load_detect_mode; | |
79e53945 | 9978 | |
d2dff872 CW |
9979 | /* We need a framebuffer large enough to accommodate all accesses |
9980 | * that the plane may generate whilst we perform load detection. | |
9981 | * We can not rely on the fbcon either being present (we get called | |
9982 | * during its initialisation to detect all boot displays, or it may | |
9983 | * not even exist) or that it is large enough to satisfy the | |
9984 | * requested mode. | |
9985 | */ | |
94352cf9 DV |
9986 | fb = mode_fits_in_fbdev(dev, mode); |
9987 | if (fb == NULL) { | |
d2dff872 | 9988 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 | 9989 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
d2dff872 CW |
9990 | } else |
9991 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 9992 | if (IS_ERR(fb)) { |
d2dff872 | 9993 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
f4bf77b4 | 9994 | ret = PTR_ERR(fb); |
412b61d8 | 9995 | goto fail; |
79e53945 | 9996 | } |
79e53945 | 9997 | |
d3a40d1b ACO |
9998 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
9999 | if (ret) | |
10000 | goto fail; | |
10001 | ||
edde3617 ML |
10002 | drm_framebuffer_unreference(fb); |
10003 | ||
10004 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
10005 | if (ret) | |
10006 | goto fail; | |
10007 | ||
10008 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
10009 | if (!ret) | |
10010 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
10011 | if (!ret) | |
10012 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
10013 | if (ret) { | |
10014 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
10015 | goto fail; | |
10016 | } | |
8c7b5ccb | 10017 | |
3ba86073 ML |
10018 | ret = drm_atomic_commit(state); |
10019 | if (ret) { | |
6492711d | 10020 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
412b61d8 | 10021 | goto fail; |
79e53945 | 10022 | } |
edde3617 ML |
10023 | |
10024 | old->restore_state = restore_state; | |
7abbd11f | 10025 | drm_atomic_state_put(state); |
7173188d | 10026 | |
79e53945 | 10027 | /* let the connector get through one full cycle before testing */ |
0f0f74bc | 10028 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
7173188d | 10029 | return true; |
412b61d8 | 10030 | |
ad3c558f | 10031 | fail: |
7fb71c8f CW |
10032 | if (state) { |
10033 | drm_atomic_state_put(state); | |
10034 | state = NULL; | |
10035 | } | |
10036 | if (restore_state) { | |
10037 | drm_atomic_state_put(restore_state); | |
10038 | restore_state = NULL; | |
10039 | } | |
83a57153 | 10040 | |
6c5ed5ae ML |
10041 | if (ret == -EDEADLK) |
10042 | return ret; | |
51fd371b | 10043 | |
412b61d8 | 10044 | return false; |
79e53945 JB |
10045 | } |
10046 | ||
d2434ab7 | 10047 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10048 | struct intel_load_detect_pipe *old, |
10049 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10050 | { |
d2434ab7 DV |
10051 | struct intel_encoder *intel_encoder = |
10052 | intel_attached_encoder(connector); | |
4ef69c7a | 10053 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 10054 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 10055 | int ret; |
79e53945 | 10056 | |
d2dff872 | 10057 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10058 | connector->base.id, connector->name, |
8e329a03 | 10059 | encoder->base.id, encoder->name); |
d2dff872 | 10060 | |
edde3617 | 10061 | if (!state) |
0622a53c | 10062 | return; |
79e53945 | 10063 | |
581e49fe | 10064 | ret = drm_atomic_helper_commit_duplicated_state(state, ctx); |
0853695c | 10065 | if (ret) |
edde3617 | 10066 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); |
0853695c | 10067 | drm_atomic_state_put(state); |
79e53945 JB |
10068 | } |
10069 | ||
da4a1efa | 10070 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10071 | const struct intel_crtc_state *pipe_config) |
da4a1efa | 10072 | { |
fac5e23e | 10073 | struct drm_i915_private *dev_priv = to_i915(dev); |
da4a1efa VS |
10074 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
10075 | ||
10076 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10077 | return dev_priv->vbt.lvds_ssc_freq; |
6e266956 | 10078 | else if (HAS_PCH_SPLIT(dev_priv)) |
da4a1efa | 10079 | return 120000; |
5db94019 | 10080 | else if (!IS_GEN2(dev_priv)) |
da4a1efa VS |
10081 | return 96000; |
10082 | else | |
10083 | return 48000; | |
10084 | } | |
10085 | ||
79e53945 | 10086 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10087 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10088 | struct intel_crtc_state *pipe_config) |
79e53945 | 10089 | { |
f1f644dc | 10090 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 10091 | struct drm_i915_private *dev_priv = to_i915(dev); |
f1f644dc | 10092 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10093 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 | 10094 | u32 fp; |
9e2c8475 | 10095 | struct dpll clock; |
dccbea3b | 10096 | int port_clock; |
da4a1efa | 10097 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10098 | |
10099 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10100 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10101 | else |
293623f7 | 10102 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10103 | |
10104 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
9b1e14f4 | 10105 | if (IS_PINEVIEW(dev_priv)) { |
f2b115e6 AJ |
10106 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
10107 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10108 | } else { |
10109 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10110 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10111 | } | |
10112 | ||
5db94019 | 10113 | if (!IS_GEN2(dev_priv)) { |
9b1e14f4 | 10114 | if (IS_PINEVIEW(dev_priv)) |
f2b115e6 AJ |
10115 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
10116 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10117 | else |
10118 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10119 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10120 | ||
10121 | switch (dpll & DPLL_MODE_MASK) { | |
10122 | case DPLLB_MODE_DAC_SERIAL: | |
10123 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10124 | 5 : 10; | |
10125 | break; | |
10126 | case DPLLB_MODE_LVDS: | |
10127 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10128 | 7 : 14; | |
10129 | break; | |
10130 | default: | |
28c97730 | 10131 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10132 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10133 | return; |
79e53945 JB |
10134 | } |
10135 | ||
9b1e14f4 | 10136 | if (IS_PINEVIEW(dev_priv)) |
dccbea3b | 10137 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 10138 | else |
dccbea3b | 10139 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 10140 | } else { |
50a0bc90 | 10141 | u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10142 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10143 | |
10144 | if (is_lvds) { | |
10145 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10146 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10147 | |
10148 | if (lvds & LVDS_CLKB_POWER_UP) | |
10149 | clock.p2 = 7; | |
10150 | else | |
10151 | clock.p2 = 14; | |
79e53945 JB |
10152 | } else { |
10153 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10154 | clock.p1 = 2; | |
10155 | else { | |
10156 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10157 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10158 | } | |
10159 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10160 | clock.p2 = 4; | |
10161 | else | |
10162 | clock.p2 = 2; | |
79e53945 | 10163 | } |
da4a1efa | 10164 | |
dccbea3b | 10165 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
10166 | } |
10167 | ||
18442d08 VS |
10168 | /* |
10169 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10170 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10171 | * encoder's get_config() function. |
10172 | */ | |
dccbea3b | 10173 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
10174 | } |
10175 | ||
6878da05 VS |
10176 | int intel_dotclock_calculate(int link_freq, |
10177 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10178 | { |
f1f644dc JB |
10179 | /* |
10180 | * The calculation for the data clock is: | |
1041a02f | 10181 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10182 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10183 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10184 | * |
10185 | * and the link clock is simpler: | |
1041a02f | 10186 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10187 | */ |
10188 | ||
6878da05 VS |
10189 | if (!m_n->link_n) |
10190 | return 0; | |
f1f644dc | 10191 | |
6878da05 VS |
10192 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10193 | } | |
f1f644dc | 10194 | |
18442d08 | 10195 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10196 | struct intel_crtc_state *pipe_config) |
6878da05 | 10197 | { |
e3b247da | 10198 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
79e53945 | 10199 | |
18442d08 VS |
10200 | /* read out port_clock from the DPLL */ |
10201 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10202 | |
f1f644dc | 10203 | /* |
e3b247da VS |
10204 | * In case there is an active pipe without active ports, |
10205 | * we may need some idea for the dotclock anyway. | |
10206 | * Calculate one based on the FDI configuration. | |
79e53945 | 10207 | */ |
2d112de7 | 10208 | pipe_config->base.adjusted_mode.crtc_clock = |
21a727b3 | 10209 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
18442d08 | 10210 | &pipe_config->fdi_m_n); |
79e53945 JB |
10211 | } |
10212 | ||
10213 | /** Returns the currently programmed mode of the given pipe. */ | |
10214 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10215 | struct drm_crtc *crtc) | |
10216 | { | |
fac5e23e | 10217 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 10218 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10219 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10220 | struct drm_display_mode *mode; |
3f36b937 | 10221 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
10222 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10223 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10224 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10225 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10226 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10227 | |
10228 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10229 | if (!mode) | |
10230 | return NULL; | |
10231 | ||
3f36b937 TU |
10232 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
10233 | if (!pipe_config) { | |
10234 | kfree(mode); | |
10235 | return NULL; | |
10236 | } | |
10237 | ||
f1f644dc JB |
10238 | /* |
10239 | * Construct a pipe_config sufficient for getting the clock info | |
10240 | * back out of crtc_clock_get. | |
10241 | * | |
10242 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10243 | * to use a real value here instead. | |
10244 | */ | |
3f36b937 TU |
10245 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
10246 | pipe_config->pixel_multiplier = 1; | |
10247 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
10248 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10249 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
10250 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
10251 | ||
10252 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
10253 | mode->hdisplay = (htot & 0xffff) + 1; |
10254 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10255 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10256 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10257 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10258 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10259 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10260 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10261 | ||
10262 | drm_mode_set_name(mode); | |
79e53945 | 10263 | |
3f36b937 TU |
10264 | kfree(pipe_config); |
10265 | ||
79e53945 JB |
10266 | return mode; |
10267 | } | |
10268 | ||
10269 | static void intel_crtc_destroy(struct drm_crtc *crtc) | |
10270 | { | |
10271 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10272 | ||
10273 | drm_crtc_cleanup(crtc); | |
10274 | kfree(intel_crtc); | |
10275 | } | |
10276 | ||
5a21b665 DV |
10277 | /** |
10278 | * intel_wm_need_update - Check whether watermarks need updating | |
10279 | * @plane: drm plane | |
10280 | * @state: new plane state | |
10281 | * | |
10282 | * Check current plane state versus the new one to determine whether | |
10283 | * watermarks need to be recalculated. | |
10284 | * | |
10285 | * Returns true or false. | |
10286 | */ | |
10287 | static bool intel_wm_need_update(struct drm_plane *plane, | |
10288 | struct drm_plane_state *state) | |
10289 | { | |
10290 | struct intel_plane_state *new = to_intel_plane_state(state); | |
10291 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
10292 | ||
10293 | /* Update watermarks on tiling or size changes. */ | |
936e71e3 | 10294 | if (new->base.visible != cur->base.visible) |
5a21b665 DV |
10295 | return true; |
10296 | ||
10297 | if (!cur->base.fb || !new->base.fb) | |
10298 | return false; | |
10299 | ||
bae781b2 | 10300 | if (cur->base.fb->modifier != new->base.fb->modifier || |
5a21b665 | 10301 | cur->base.rotation != new->base.rotation || |
936e71e3 VS |
10302 | drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) || |
10303 | drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) || | |
10304 | drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) || | |
10305 | drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst)) | |
5a21b665 DV |
10306 | return true; |
10307 | ||
10308 | return false; | |
10309 | } | |
10310 | ||
10311 | static bool needs_scaling(struct intel_plane_state *state) | |
10312 | { | |
936e71e3 VS |
10313 | int src_w = drm_rect_width(&state->base.src) >> 16; |
10314 | int src_h = drm_rect_height(&state->base.src) >> 16; | |
10315 | int dst_w = drm_rect_width(&state->base.dst); | |
10316 | int dst_h = drm_rect_height(&state->base.dst); | |
5a21b665 DV |
10317 | |
10318 | return (src_w != dst_w || src_h != dst_h); | |
10319 | } | |
d21fbe87 | 10320 | |
da20eabd ML |
10321 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
10322 | struct drm_plane_state *plane_state) | |
10323 | { | |
ab1d3a0e | 10324 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
10325 | struct drm_crtc *crtc = crtc_state->crtc; |
10326 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e9728bd8 | 10327 | struct intel_plane *plane = to_intel_plane(plane_state->plane); |
da20eabd | 10328 | struct drm_device *dev = crtc->dev; |
ed4a6a7c | 10329 | struct drm_i915_private *dev_priv = to_i915(dev); |
da20eabd | 10330 | struct intel_plane_state *old_plane_state = |
e9728bd8 | 10331 | to_intel_plane_state(plane->base.state); |
da20eabd ML |
10332 | bool mode_changed = needs_modeset(crtc_state); |
10333 | bool was_crtc_enabled = crtc->state->active; | |
10334 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
10335 | bool turn_off, turn_on, visible, was_visible; |
10336 | struct drm_framebuffer *fb = plane_state->fb; | |
78108b7c | 10337 | int ret; |
da20eabd | 10338 | |
e9728bd8 | 10339 | if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) { |
da20eabd ML |
10340 | ret = skl_update_scaler_plane( |
10341 | to_intel_crtc_state(crtc_state), | |
10342 | to_intel_plane_state(plane_state)); | |
10343 | if (ret) | |
10344 | return ret; | |
10345 | } | |
10346 | ||
936e71e3 | 10347 | was_visible = old_plane_state->base.visible; |
1d4258db | 10348 | visible = plane_state->visible; |
da20eabd ML |
10349 | |
10350 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
10351 | was_visible = false; | |
10352 | ||
35c08f43 ML |
10353 | /* |
10354 | * Visibility is calculated as if the crtc was on, but | |
10355 | * after scaler setup everything depends on it being off | |
10356 | * when the crtc isn't active. | |
f818ffea VS |
10357 | * |
10358 | * FIXME this is wrong for watermarks. Watermarks should also | |
10359 | * be computed as if the pipe would be active. Perhaps move | |
10360 | * per-plane wm computation to the .check_plane() hook, and | |
10361 | * only combine the results from all planes in the current place? | |
35c08f43 | 10362 | */ |
e9728bd8 | 10363 | if (!is_crtc_enabled) { |
1d4258db | 10364 | plane_state->visible = visible = false; |
e9728bd8 VS |
10365 | to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id); |
10366 | } | |
da20eabd ML |
10367 | |
10368 | if (!was_visible && !visible) | |
10369 | return 0; | |
10370 | ||
e8861675 ML |
10371 | if (fb != old_plane_state->base.fb) |
10372 | pipe_config->fb_changed = true; | |
10373 | ||
da20eabd ML |
10374 | turn_off = was_visible && (!visible || mode_changed); |
10375 | turn_on = visible && (!was_visible || mode_changed); | |
10376 | ||
72660ce0 | 10377 | DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n", |
e9728bd8 VS |
10378 | intel_crtc->base.base.id, intel_crtc->base.name, |
10379 | plane->base.base.id, plane->base.name, | |
72660ce0 | 10380 | fb ? fb->base.id : -1); |
da20eabd | 10381 | |
72660ce0 | 10382 | DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n", |
e9728bd8 | 10383 | plane->base.base.id, plane->base.name, |
72660ce0 | 10384 | was_visible, visible, |
da20eabd ML |
10385 | turn_off, turn_on, mode_changed); |
10386 | ||
caed361d | 10387 | if (turn_on) { |
04548cba | 10388 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
b4ede6df | 10389 | pipe_config->update_wm_pre = true; |
caed361d VS |
10390 | |
10391 | /* must disable cxsr around plane enable/disable */ | |
e9728bd8 | 10392 | if (plane->id != PLANE_CURSOR) |
caed361d VS |
10393 | pipe_config->disable_cxsr = true; |
10394 | } else if (turn_off) { | |
04548cba | 10395 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
b4ede6df | 10396 | pipe_config->update_wm_post = true; |
92826fcd | 10397 | |
852eb00d | 10398 | /* must disable cxsr around plane enable/disable */ |
e9728bd8 | 10399 | if (plane->id != PLANE_CURSOR) |
ab1d3a0e | 10400 | pipe_config->disable_cxsr = true; |
e9728bd8 | 10401 | } else if (intel_wm_need_update(&plane->base, plane_state)) { |
04548cba | 10402 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) { |
b4ede6df VS |
10403 | /* FIXME bollocks */ |
10404 | pipe_config->update_wm_pre = true; | |
10405 | pipe_config->update_wm_post = true; | |
10406 | } | |
852eb00d | 10407 | } |
da20eabd | 10408 | |
8be6ca85 | 10409 | if (visible || was_visible) |
e9728bd8 | 10410 | pipe_config->fb_bits |= plane->frontbuffer_bit; |
a9ff8714 | 10411 | |
31ae71fc ML |
10412 | /* |
10413 | * WaCxSRDisabledForSpriteScaling:ivb | |
10414 | * | |
10415 | * cstate->update_wm was already set above, so this flag will | |
10416 | * take effect when we commit and program watermarks. | |
10417 | */ | |
e9728bd8 | 10418 | if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) && |
31ae71fc ML |
10419 | needs_scaling(to_intel_plane_state(plane_state)) && |
10420 | !needs_scaling(old_plane_state)) | |
10421 | pipe_config->disable_lp_wm = true; | |
d21fbe87 | 10422 | |
da20eabd ML |
10423 | return 0; |
10424 | } | |
10425 | ||
6d3a1ce7 ML |
10426 | static bool encoders_cloneable(const struct intel_encoder *a, |
10427 | const struct intel_encoder *b) | |
10428 | { | |
10429 | /* masks could be asymmetric, so check both ways */ | |
10430 | return a == b || (a->cloneable & (1 << b->type) && | |
10431 | b->cloneable & (1 << a->type)); | |
10432 | } | |
10433 | ||
10434 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
10435 | struct intel_crtc *crtc, | |
10436 | struct intel_encoder *encoder) | |
10437 | { | |
10438 | struct intel_encoder *source_encoder; | |
10439 | struct drm_connector *connector; | |
10440 | struct drm_connector_state *connector_state; | |
10441 | int i; | |
10442 | ||
aa5e9b47 | 10443 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
6d3a1ce7 ML |
10444 | if (connector_state->crtc != &crtc->base) |
10445 | continue; | |
10446 | ||
10447 | source_encoder = | |
10448 | to_intel_encoder(connector_state->best_encoder); | |
10449 | if (!encoders_cloneable(encoder, source_encoder)) | |
10450 | return false; | |
10451 | } | |
10452 | ||
10453 | return true; | |
10454 | } | |
10455 | ||
6d3a1ce7 ML |
10456 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, |
10457 | struct drm_crtc_state *crtc_state) | |
10458 | { | |
cf5a15be | 10459 | struct drm_device *dev = crtc->dev; |
fac5e23e | 10460 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d3a1ce7 | 10461 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
10462 | struct intel_crtc_state *pipe_config = |
10463 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 10464 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 10465 | int ret; |
6d3a1ce7 ML |
10466 | bool mode_changed = needs_modeset(crtc_state); |
10467 | ||
852eb00d | 10468 | if (mode_changed && !crtc_state->active) |
caed361d | 10469 | pipe_config->update_wm_post = true; |
eddfcbcd | 10470 | |
ad421372 ML |
10471 | if (mode_changed && crtc_state->enable && |
10472 | dev_priv->display.crtc_compute_clock && | |
8106ddbd | 10473 | !WARN_ON(pipe_config->shared_dpll)) { |
ad421372 ML |
10474 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
10475 | pipe_config); | |
10476 | if (ret) | |
10477 | return ret; | |
10478 | } | |
10479 | ||
82cf435b LL |
10480 | if (crtc_state->color_mgmt_changed) { |
10481 | ret = intel_color_check(crtc, crtc_state); | |
10482 | if (ret) | |
10483 | return ret; | |
e7852a4b LL |
10484 | |
10485 | /* | |
10486 | * Changing color management on Intel hardware is | |
10487 | * handled as part of planes update. | |
10488 | */ | |
10489 | crtc_state->planes_changed = true; | |
82cf435b LL |
10490 | } |
10491 | ||
e435d6e5 | 10492 | ret = 0; |
86c8bbbe | 10493 | if (dev_priv->display.compute_pipe_wm) { |
e3bddded | 10494 | ret = dev_priv->display.compute_pipe_wm(pipe_config); |
ed4a6a7c MR |
10495 | if (ret) { |
10496 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
10497 | return ret; | |
10498 | } | |
10499 | } | |
10500 | ||
10501 | if (dev_priv->display.compute_intermediate_wm && | |
10502 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
10503 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
10504 | return 0; | |
10505 | ||
10506 | /* | |
10507 | * Calculate 'intermediate' watermarks that satisfy both the | |
10508 | * old state and the new state. We can program these | |
10509 | * immediately. | |
10510 | */ | |
6315b5d3 | 10511 | ret = dev_priv->display.compute_intermediate_wm(dev, |
ed4a6a7c MR |
10512 | intel_crtc, |
10513 | pipe_config); | |
10514 | if (ret) { | |
10515 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 10516 | return ret; |
ed4a6a7c | 10517 | } |
e3d5457c VS |
10518 | } else if (dev_priv->display.compute_intermediate_wm) { |
10519 | if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9) | |
10520 | pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; | |
86c8bbbe MR |
10521 | } |
10522 | ||
6315b5d3 | 10523 | if (INTEL_GEN(dev_priv) >= 9) { |
e435d6e5 ML |
10524 | if (mode_changed) |
10525 | ret = skl_update_scaler_crtc(pipe_config); | |
10526 | ||
73b0ca8e MK |
10527 | if (!ret) |
10528 | ret = skl_check_pipe_max_pixel_rate(intel_crtc, | |
10529 | pipe_config); | |
e435d6e5 | 10530 | if (!ret) |
6ebc6923 | 10531 | ret = intel_atomic_setup_scalers(dev_priv, intel_crtc, |
e435d6e5 ML |
10532 | pipe_config); |
10533 | } | |
10534 | ||
10535 | return ret; | |
6d3a1ce7 ML |
10536 | } |
10537 | ||
65b38e0d | 10538 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
5a21b665 DV |
10539 | .atomic_begin = intel_begin_crtc_commit, |
10540 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 10541 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
10542 | }; |
10543 | ||
d29b2f9d ACO |
10544 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
10545 | { | |
10546 | struct intel_connector *connector; | |
f9e905ca | 10547 | struct drm_connector_list_iter conn_iter; |
d29b2f9d | 10548 | |
f9e905ca DV |
10549 | drm_connector_list_iter_begin(dev, &conn_iter); |
10550 | for_each_intel_connector_iter(connector, &conn_iter) { | |
8863dc7f DV |
10551 | if (connector->base.state->crtc) |
10552 | drm_connector_unreference(&connector->base); | |
10553 | ||
d29b2f9d ACO |
10554 | if (connector->base.encoder) { |
10555 | connector->base.state->best_encoder = | |
10556 | connector->base.encoder; | |
10557 | connector->base.state->crtc = | |
10558 | connector->base.encoder->crtc; | |
8863dc7f DV |
10559 | |
10560 | drm_connector_reference(&connector->base); | |
d29b2f9d ACO |
10561 | } else { |
10562 | connector->base.state->best_encoder = NULL; | |
10563 | connector->base.state->crtc = NULL; | |
10564 | } | |
10565 | } | |
f9e905ca | 10566 | drm_connector_list_iter_end(&conn_iter); |
d29b2f9d ACO |
10567 | } |
10568 | ||
050f7aeb | 10569 | static void |
eba905b2 | 10570 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 10571 | struct intel_crtc_state *pipe_config) |
050f7aeb | 10572 | { |
6a2a5c5d | 10573 | const struct drm_display_info *info = &connector->base.display_info; |
050f7aeb DV |
10574 | int bpp = pipe_config->pipe_bpp; |
10575 | ||
10576 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
6a2a5c5d VS |
10577 | connector->base.base.id, |
10578 | connector->base.name); | |
050f7aeb DV |
10579 | |
10580 | /* Don't use an invalid EDID bpc value */ | |
6a2a5c5d | 10581 | if (info->bpc != 0 && info->bpc * 3 < bpp) { |
050f7aeb | 10582 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", |
6a2a5c5d VS |
10583 | bpp, info->bpc * 3); |
10584 | pipe_config->pipe_bpp = info->bpc * 3; | |
050f7aeb DV |
10585 | } |
10586 | ||
196f954e | 10587 | /* Clamp bpp to 8 on screens without EDID 1.4 */ |
6a2a5c5d | 10588 | if (info->bpc == 0 && bpp > 24) { |
196f954e MK |
10589 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", |
10590 | bpp); | |
10591 | pipe_config->pipe_bpp = 24; | |
050f7aeb DV |
10592 | } |
10593 | } | |
10594 | ||
4e53c2e0 | 10595 | static int |
050f7aeb | 10596 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 10597 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 10598 | { |
9beb5fea | 10599 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1486017f | 10600 | struct drm_atomic_state *state; |
da3ced29 ACO |
10601 | struct drm_connector *connector; |
10602 | struct drm_connector_state *connector_state; | |
1486017f | 10603 | int bpp, i; |
4e53c2e0 | 10604 | |
9beb5fea TU |
10605 | if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
10606 | IS_CHERRYVIEW(dev_priv))) | |
4e53c2e0 | 10607 | bpp = 10*3; |
9beb5fea | 10608 | else if (INTEL_GEN(dev_priv) >= 5) |
d328c9d7 DV |
10609 | bpp = 12*3; |
10610 | else | |
10611 | bpp = 8*3; | |
10612 | ||
4e53c2e0 | 10613 | |
4e53c2e0 DV |
10614 | pipe_config->pipe_bpp = bpp; |
10615 | ||
1486017f ACO |
10616 | state = pipe_config->base.state; |
10617 | ||
4e53c2e0 | 10618 | /* Clamp display bpp to EDID value */ |
aa5e9b47 | 10619 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
da3ced29 | 10620 | if (connector_state->crtc != &crtc->base) |
4e53c2e0 DV |
10621 | continue; |
10622 | ||
da3ced29 ACO |
10623 | connected_sink_compute_bpp(to_intel_connector(connector), |
10624 | pipe_config); | |
4e53c2e0 DV |
10625 | } |
10626 | ||
10627 | return bpp; | |
10628 | } | |
10629 | ||
644db711 DV |
10630 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
10631 | { | |
10632 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
10633 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 10634 | mode->crtc_clock, |
644db711 DV |
10635 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
10636 | mode->crtc_hsync_end, mode->crtc_htotal, | |
10637 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
10638 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
10639 | } | |
10640 | ||
f6982332 TU |
10641 | static inline void |
10642 | intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id, | |
a4309657 | 10643 | unsigned int lane_count, struct intel_link_m_n *m_n) |
f6982332 | 10644 | { |
a4309657 TU |
10645 | DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
10646 | id, lane_count, | |
f6982332 TU |
10647 | m_n->gmch_m, m_n->gmch_n, |
10648 | m_n->link_m, m_n->link_n, m_n->tu); | |
10649 | } | |
10650 | ||
c0b03411 | 10651 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 10652 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
10653 | const char *context) |
10654 | { | |
6a60cd87 | 10655 | struct drm_device *dev = crtc->base.dev; |
4f8036a2 | 10656 | struct drm_i915_private *dev_priv = to_i915(dev); |
6a60cd87 CK |
10657 | struct drm_plane *plane; |
10658 | struct intel_plane *intel_plane; | |
10659 | struct intel_plane_state *state; | |
10660 | struct drm_framebuffer *fb; | |
10661 | ||
66766e4f TU |
10662 | DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n", |
10663 | crtc->base.base.id, crtc->base.name, context); | |
c0b03411 | 10664 | |
2c89429e TU |
10665 | DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", |
10666 | transcoder_name(pipe_config->cpu_transcoder), | |
c0b03411 | 10667 | pipe_config->pipe_bpp, pipe_config->dither); |
a4309657 TU |
10668 | |
10669 | if (pipe_config->has_pch_encoder) | |
10670 | intel_dump_m_n_config(pipe_config, "fdi", | |
10671 | pipe_config->fdi_lanes, | |
10672 | &pipe_config->fdi_m_n); | |
f6982332 | 10673 | |
b22ca995 SS |
10674 | if (pipe_config->ycbcr420) |
10675 | DRM_DEBUG_KMS("YCbCr 4:2:0 output enabled\n"); | |
10676 | ||
f6982332 | 10677 | if (intel_crtc_has_dp_encoder(pipe_config)) { |
a4309657 TU |
10678 | intel_dump_m_n_config(pipe_config, "dp m_n", |
10679 | pipe_config->lane_count, &pipe_config->dp_m_n); | |
d806e682 TU |
10680 | if (pipe_config->has_drrs) |
10681 | intel_dump_m_n_config(pipe_config, "dp m2_n2", | |
10682 | pipe_config->lane_count, | |
10683 | &pipe_config->dp_m2_n2); | |
f6982332 | 10684 | } |
b95af8be | 10685 | |
55072d19 | 10686 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
2c89429e | 10687 | pipe_config->has_audio, pipe_config->has_infoframe); |
55072d19 | 10688 | |
c0b03411 | 10689 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 10690 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 10691 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
10692 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
10693 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
a7d1b3f4 | 10694 | DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n", |
2c89429e | 10695 | pipe_config->port_clock, |
a7d1b3f4 VS |
10696 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
10697 | pipe_config->pixel_rate); | |
dd2f616d TU |
10698 | |
10699 | if (INTEL_GEN(dev_priv) >= 9) | |
10700 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", | |
10701 | crtc->num_scalers, | |
10702 | pipe_config->scaler_state.scaler_users, | |
10703 | pipe_config->scaler_state.scaler_id); | |
a74f8375 TU |
10704 | |
10705 | if (HAS_GMCH_DISPLAY(dev_priv)) | |
10706 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", | |
10707 | pipe_config->gmch_pfit.control, | |
10708 | pipe_config->gmch_pfit.pgm_ratios, | |
10709 | pipe_config->gmch_pfit.lvds_border_bits); | |
10710 | else | |
10711 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", | |
10712 | pipe_config->pch_pfit.pos, | |
10713 | pipe_config->pch_pfit.size, | |
08c4d7fc | 10714 | enableddisabled(pipe_config->pch_pfit.enabled)); |
a74f8375 | 10715 | |
2c89429e TU |
10716 | DRM_DEBUG_KMS("ips: %i, double wide: %i\n", |
10717 | pipe_config->ips_enabled, pipe_config->double_wide); | |
6a60cd87 | 10718 | |
f50b79f0 | 10719 | intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state); |
415ff0f6 | 10720 | |
6a60cd87 CK |
10721 | DRM_DEBUG_KMS("planes on this crtc\n"); |
10722 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
b3c11ac2 | 10723 | struct drm_format_name_buf format_name; |
6a60cd87 CK |
10724 | intel_plane = to_intel_plane(plane); |
10725 | if (intel_plane->pipe != crtc->pipe) | |
10726 | continue; | |
10727 | ||
10728 | state = to_intel_plane_state(plane->state); | |
10729 | fb = state->base.fb; | |
10730 | if (!fb) { | |
1d577e02 VS |
10731 | DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n", |
10732 | plane->base.id, plane->name, state->scaler_id); | |
6a60cd87 CK |
10733 | continue; |
10734 | } | |
10735 | ||
dd2f616d TU |
10736 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n", |
10737 | plane->base.id, plane->name, | |
b3c11ac2 | 10738 | fb->base.id, fb->width, fb->height, |
438b74a5 | 10739 | drm_get_format_name(fb->format->format, &format_name)); |
dd2f616d TU |
10740 | if (INTEL_GEN(dev_priv) >= 9) |
10741 | DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n", | |
10742 | state->scaler_id, | |
10743 | state->base.src.x1 >> 16, | |
10744 | state->base.src.y1 >> 16, | |
10745 | drm_rect_width(&state->base.src) >> 16, | |
10746 | drm_rect_height(&state->base.src) >> 16, | |
10747 | state->base.dst.x1, state->base.dst.y1, | |
10748 | drm_rect_width(&state->base.dst), | |
10749 | drm_rect_height(&state->base.dst)); | |
6a60cd87 | 10750 | } |
c0b03411 DV |
10751 | } |
10752 | ||
5448a00d | 10753 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 10754 | { |
5448a00d | 10755 | struct drm_device *dev = state->dev; |
da3ced29 | 10756 | struct drm_connector *connector; |
2fd96b41 | 10757 | struct drm_connector_list_iter conn_iter; |
00f0b378 | 10758 | unsigned int used_ports = 0; |
477321e0 | 10759 | unsigned int used_mst_ports = 0; |
00f0b378 VS |
10760 | |
10761 | /* | |
10762 | * Walk the connector list instead of the encoder | |
10763 | * list to detect the problem on ddi platforms | |
10764 | * where there's just one encoder per digital port. | |
10765 | */ | |
2fd96b41 GP |
10766 | drm_connector_list_iter_begin(dev, &conn_iter); |
10767 | drm_for_each_connector_iter(connector, &conn_iter) { | |
0bff4858 VS |
10768 | struct drm_connector_state *connector_state; |
10769 | struct intel_encoder *encoder; | |
10770 | ||
10771 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
10772 | if (!connector_state) | |
10773 | connector_state = connector->state; | |
10774 | ||
5448a00d | 10775 | if (!connector_state->best_encoder) |
00f0b378 VS |
10776 | continue; |
10777 | ||
5448a00d ACO |
10778 | encoder = to_intel_encoder(connector_state->best_encoder); |
10779 | ||
10780 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
10781 | |
10782 | switch (encoder->type) { | |
10783 | unsigned int port_mask; | |
10784 | case INTEL_OUTPUT_UNKNOWN: | |
4f8036a2 | 10785 | if (WARN_ON(!HAS_DDI(to_i915(dev)))) |
00f0b378 | 10786 | break; |
cca0502b | 10787 | case INTEL_OUTPUT_DP: |
00f0b378 VS |
10788 | case INTEL_OUTPUT_HDMI: |
10789 | case INTEL_OUTPUT_EDP: | |
10790 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
10791 | ||
10792 | /* the same port mustn't appear more than once */ | |
10793 | if (used_ports & port_mask) | |
10794 | return false; | |
10795 | ||
10796 | used_ports |= port_mask; | |
477321e0 VS |
10797 | break; |
10798 | case INTEL_OUTPUT_DP_MST: | |
10799 | used_mst_ports |= | |
10800 | 1 << enc_to_mst(&encoder->base)->primary->port; | |
10801 | break; | |
00f0b378 VS |
10802 | default: |
10803 | break; | |
10804 | } | |
10805 | } | |
2fd96b41 | 10806 | drm_connector_list_iter_end(&conn_iter); |
00f0b378 | 10807 | |
477321e0 VS |
10808 | /* can't mix MST and SST/HDMI on the same port */ |
10809 | if (used_ports & used_mst_ports) | |
10810 | return false; | |
10811 | ||
00f0b378 VS |
10812 | return true; |
10813 | } | |
10814 | ||
83a57153 ACO |
10815 | static void |
10816 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
10817 | { | |
ff32c54e VS |
10818 | struct drm_i915_private *dev_priv = |
10819 | to_i915(crtc_state->base.crtc->dev); | |
663a3640 | 10820 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 | 10821 | struct intel_dpll_hw_state dpll_hw_state; |
8106ddbd | 10822 | struct intel_shared_dpll *shared_dpll; |
ff32c54e | 10823 | struct intel_crtc_wm_state wm_state; |
c4e2d043 | 10824 | bool force_thru; |
83a57153 | 10825 | |
7546a384 ACO |
10826 | /* FIXME: before the switch to atomic started, a new pipe_config was |
10827 | * kzalloc'd. Code that depends on any field being zero should be | |
10828 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
10829 | * only fields that are know to not cause problems are preserved. */ | |
10830 | ||
663a3640 | 10831 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
10832 | shared_dpll = crtc_state->shared_dpll; |
10833 | dpll_hw_state = crtc_state->dpll_hw_state; | |
c4e2d043 | 10834 | force_thru = crtc_state->pch_pfit.force_thru; |
04548cba VS |
10835 | if (IS_G4X(dev_priv) || |
10836 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
ff32c54e | 10837 | wm_state = crtc_state->wm; |
4978cc93 | 10838 | |
d2fa80a5 CW |
10839 | /* Keep base drm_crtc_state intact, only clear our extended struct */ |
10840 | BUILD_BUG_ON(offsetof(struct intel_crtc_state, base)); | |
10841 | memset(&crtc_state->base + 1, 0, | |
10842 | sizeof(*crtc_state) - sizeof(crtc_state->base)); | |
4978cc93 | 10843 | |
663a3640 | 10844 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
10845 | crtc_state->shared_dpll = shared_dpll; |
10846 | crtc_state->dpll_hw_state = dpll_hw_state; | |
c4e2d043 | 10847 | crtc_state->pch_pfit.force_thru = force_thru; |
04548cba VS |
10848 | if (IS_G4X(dev_priv) || |
10849 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
ff32c54e | 10850 | crtc_state->wm = wm_state; |
83a57153 ACO |
10851 | } |
10852 | ||
548ee15b | 10853 | static int |
b8cecdf5 | 10854 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 10855 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 10856 | { |
b359283a | 10857 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 10858 | struct intel_encoder *encoder; |
da3ced29 | 10859 | struct drm_connector *connector; |
0b901879 | 10860 | struct drm_connector_state *connector_state; |
d328c9d7 | 10861 | int base_bpp, ret = -EINVAL; |
0b901879 | 10862 | int i; |
e29c22c0 | 10863 | bool retry = true; |
ee7b9f93 | 10864 | |
83a57153 | 10865 | clear_intel_crtc_state(pipe_config); |
7758a113 | 10866 | |
e143a21c DV |
10867 | pipe_config->cpu_transcoder = |
10868 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 10869 | |
2960bc9c ID |
10870 | /* |
10871 | * Sanitize sync polarity flags based on requested ones. If neither | |
10872 | * positive or negative polarity is requested, treat this as meaning | |
10873 | * negative polarity. | |
10874 | */ | |
2d112de7 | 10875 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 10876 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 10877 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 10878 | |
2d112de7 | 10879 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 10880 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 10881 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 10882 | |
d328c9d7 DV |
10883 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
10884 | pipe_config); | |
10885 | if (base_bpp < 0) | |
4e53c2e0 DV |
10886 | goto fail; |
10887 | ||
e41a56be VS |
10888 | /* |
10889 | * Determine the real pipe dimensions. Note that stereo modes can | |
10890 | * increase the actual pipe size due to the frame doubling and | |
10891 | * insertion of additional space for blanks between the frame. This | |
10892 | * is stored in the crtc timings. We use the requested mode to do this | |
10893 | * computation to clearly distinguish it from the adjusted mode, which | |
10894 | * can be changed by the connectors in the below retry loop. | |
10895 | */ | |
196cd5d3 | 10896 | drm_mode_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
10897 | &pipe_config->pipe_src_w, |
10898 | &pipe_config->pipe_src_h); | |
e41a56be | 10899 | |
aa5e9b47 | 10900 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
253c84c8 VS |
10901 | if (connector_state->crtc != crtc) |
10902 | continue; | |
10903 | ||
10904 | encoder = to_intel_encoder(connector_state->best_encoder); | |
10905 | ||
e25148d0 VS |
10906 | if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) { |
10907 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
10908 | goto fail; | |
10909 | } | |
10910 | ||
253c84c8 VS |
10911 | /* |
10912 | * Determine output_types before calling the .compute_config() | |
10913 | * hooks so that the hooks can use this information safely. | |
10914 | */ | |
10915 | pipe_config->output_types |= 1 << encoder->type; | |
10916 | } | |
10917 | ||
e29c22c0 | 10918 | encoder_retry: |
ef1b460d | 10919 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 10920 | pipe_config->port_clock = 0; |
ef1b460d | 10921 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 10922 | |
135c81b8 | 10923 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
10924 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
10925 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 10926 | |
7758a113 DV |
10927 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
10928 | * adjust it according to limitations or connector properties, and also | |
10929 | * a chance to reject the mode entirely. | |
47f1c6c9 | 10930 | */ |
aa5e9b47 | 10931 | for_each_new_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 10932 | if (connector_state->crtc != crtc) |
7758a113 | 10933 | continue; |
7ae89233 | 10934 | |
0b901879 ACO |
10935 | encoder = to_intel_encoder(connector_state->best_encoder); |
10936 | ||
0a478c27 | 10937 | if (!(encoder->compute_config(encoder, pipe_config, connector_state))) { |
efea6e8e | 10938 | DRM_DEBUG_KMS("Encoder config failure\n"); |
7758a113 DV |
10939 | goto fail; |
10940 | } | |
ee7b9f93 | 10941 | } |
47f1c6c9 | 10942 | |
ff9a6750 DV |
10943 | /* Set default port clock if not overwritten by the encoder. Needs to be |
10944 | * done afterwards in case the encoder adjusts the mode. */ | |
10945 | if (!pipe_config->port_clock) | |
2d112de7 | 10946 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 10947 | * pipe_config->pixel_multiplier; |
ff9a6750 | 10948 | |
a43f6e0f | 10949 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 10950 | if (ret < 0) { |
7758a113 DV |
10951 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
10952 | goto fail; | |
ee7b9f93 | 10953 | } |
e29c22c0 DV |
10954 | |
10955 | if (ret == RETRY) { | |
10956 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
10957 | ret = -EINVAL; | |
10958 | goto fail; | |
10959 | } | |
10960 | ||
10961 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
10962 | retry = false; | |
10963 | goto encoder_retry; | |
10964 | } | |
10965 | ||
e8fa4270 | 10966 | /* Dithering seems to not pass-through bits correctly when it should, so |
611032bf MN |
10967 | * only enable it on 6bpc panels and when its not a compliance |
10968 | * test requesting 6bpc video pattern. | |
10969 | */ | |
10970 | pipe_config->dither = (pipe_config->pipe_bpp == 6*3) && | |
10971 | !pipe_config->dither_force_disable; | |
62f0ace5 | 10972 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 10973 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 10974 | |
7758a113 | 10975 | fail: |
548ee15b | 10976 | return ret; |
ee7b9f93 | 10977 | } |
47f1c6c9 | 10978 | |
ea9d758d | 10979 | static void |
4740b0f2 | 10980 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 10981 | { |
0a9ab303 | 10982 | struct drm_crtc *crtc; |
aa5e9b47 | 10983 | struct drm_crtc_state *new_crtc_state; |
8a75d157 | 10984 | int i; |
ea9d758d | 10985 | |
7668851f | 10986 | /* Double check state. */ |
aa5e9b47 ML |
10987 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
10988 | to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state); | |
fc467a22 | 10989 | |
61067a5e ML |
10990 | /* |
10991 | * Update legacy state to satisfy fbc code. This can | |
10992 | * be removed when fbc uses the atomic state. | |
10993 | */ | |
10994 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
10995 | struct drm_plane_state *plane_state = crtc->primary->state; | |
10996 | ||
10997 | crtc->primary->fb = plane_state->fb; | |
10998 | crtc->x = plane_state->src_x >> 16; | |
10999 | crtc->y = plane_state->src_y >> 16; | |
11000 | } | |
ea9d758d | 11001 | } |
ea9d758d DV |
11002 | } |
11003 | ||
3bd26263 | 11004 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 11005 | { |
3bd26263 | 11006 | int diff; |
f1f644dc JB |
11007 | |
11008 | if (clock1 == clock2) | |
11009 | return true; | |
11010 | ||
11011 | if (!clock1 || !clock2) | |
11012 | return false; | |
11013 | ||
11014 | diff = abs(clock1 - clock2); | |
11015 | ||
11016 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
11017 | return true; | |
11018 | ||
11019 | return false; | |
11020 | } | |
11021 | ||
cfb23ed6 ML |
11022 | static bool |
11023 | intel_compare_m_n(unsigned int m, unsigned int n, | |
11024 | unsigned int m2, unsigned int n2, | |
11025 | bool exact) | |
11026 | { | |
11027 | if (m == m2 && n == n2) | |
11028 | return true; | |
11029 | ||
11030 | if (exact || !m || !n || !m2 || !n2) | |
11031 | return false; | |
11032 | ||
11033 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
11034 | ||
31d10b57 ML |
11035 | if (n > n2) { |
11036 | while (n > n2) { | |
cfb23ed6 ML |
11037 | m2 <<= 1; |
11038 | n2 <<= 1; | |
11039 | } | |
31d10b57 ML |
11040 | } else if (n < n2) { |
11041 | while (n < n2) { | |
cfb23ed6 ML |
11042 | m <<= 1; |
11043 | n <<= 1; | |
11044 | } | |
11045 | } | |
11046 | ||
31d10b57 ML |
11047 | if (n != n2) |
11048 | return false; | |
11049 | ||
11050 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
11051 | } |
11052 | ||
11053 | static bool | |
11054 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
11055 | struct intel_link_m_n *m2_n2, | |
11056 | bool adjust) | |
11057 | { | |
11058 | if (m_n->tu == m2_n2->tu && | |
11059 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
11060 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
11061 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
11062 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
11063 | if (adjust) | |
11064 | *m2_n2 = *m_n; | |
11065 | ||
11066 | return true; | |
11067 | } | |
11068 | ||
11069 | return false; | |
11070 | } | |
11071 | ||
4e8048f8 TU |
11072 | static void __printf(3, 4) |
11073 | pipe_config_err(bool adjust, const char *name, const char *format, ...) | |
11074 | { | |
11075 | char *level; | |
11076 | unsigned int category; | |
11077 | struct va_format vaf; | |
11078 | va_list args; | |
11079 | ||
11080 | if (adjust) { | |
11081 | level = KERN_DEBUG; | |
11082 | category = DRM_UT_KMS; | |
11083 | } else { | |
11084 | level = KERN_ERR; | |
11085 | category = DRM_UT_NONE; | |
11086 | } | |
11087 | ||
11088 | va_start(args, format); | |
11089 | vaf.fmt = format; | |
11090 | vaf.va = &args; | |
11091 | ||
11092 | drm_printk(level, category, "mismatch in %s %pV", name, &vaf); | |
11093 | ||
11094 | va_end(args); | |
11095 | } | |
11096 | ||
0e8ffe1b | 11097 | static bool |
6315b5d3 | 11098 | intel_pipe_config_compare(struct drm_i915_private *dev_priv, |
5cec258b | 11099 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
11100 | struct intel_crtc_state *pipe_config, |
11101 | bool adjust) | |
0e8ffe1b | 11102 | { |
cfb23ed6 ML |
11103 | bool ret = true; |
11104 | ||
66e985c0 DV |
11105 | #define PIPE_CONF_CHECK_X(name) \ |
11106 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 11107 | pipe_config_err(adjust, __stringify(name), \ |
66e985c0 DV |
11108 | "(expected 0x%08x, found 0x%08x)\n", \ |
11109 | current_config->name, \ | |
11110 | pipe_config->name); \ | |
cfb23ed6 | 11111 | ret = false; \ |
66e985c0 DV |
11112 | } |
11113 | ||
08a24034 DV |
11114 | #define PIPE_CONF_CHECK_I(name) \ |
11115 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 11116 | pipe_config_err(adjust, __stringify(name), \ |
08a24034 DV |
11117 | "(expected %i, found %i)\n", \ |
11118 | current_config->name, \ | |
11119 | pipe_config->name); \ | |
cfb23ed6 ML |
11120 | ret = false; \ |
11121 | } | |
11122 | ||
8106ddbd ACO |
11123 | #define PIPE_CONF_CHECK_P(name) \ |
11124 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 11125 | pipe_config_err(adjust, __stringify(name), \ |
8106ddbd ACO |
11126 | "(expected %p, found %p)\n", \ |
11127 | current_config->name, \ | |
11128 | pipe_config->name); \ | |
11129 | ret = false; \ | |
11130 | } | |
11131 | ||
cfb23ed6 ML |
11132 | #define PIPE_CONF_CHECK_M_N(name) \ |
11133 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
11134 | &pipe_config->name,\ | |
11135 | adjust)) { \ | |
4e8048f8 | 11136 | pipe_config_err(adjust, __stringify(name), \ |
cfb23ed6 ML |
11137 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
11138 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
11139 | current_config->name.tu, \ | |
11140 | current_config->name.gmch_m, \ | |
11141 | current_config->name.gmch_n, \ | |
11142 | current_config->name.link_m, \ | |
11143 | current_config->name.link_n, \ | |
11144 | pipe_config->name.tu, \ | |
11145 | pipe_config->name.gmch_m, \ | |
11146 | pipe_config->name.gmch_n, \ | |
11147 | pipe_config->name.link_m, \ | |
11148 | pipe_config->name.link_n); \ | |
11149 | ret = false; \ | |
11150 | } | |
11151 | ||
55c561a7 DV |
11152 | /* This is required for BDW+ where there is only one set of registers for |
11153 | * switching between high and low RR. | |
11154 | * This macro can be used whenever a comparison has to be made between one | |
11155 | * hw state and multiple sw state variables. | |
11156 | */ | |
cfb23ed6 ML |
11157 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ |
11158 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
11159 | &pipe_config->name, adjust) && \ | |
11160 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
11161 | &pipe_config->name, adjust)) { \ | |
4e8048f8 | 11162 | pipe_config_err(adjust, __stringify(name), \ |
cfb23ed6 ML |
11163 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
11164 | "or tu %i gmch %i/%i link %i/%i, " \ | |
11165 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
11166 | current_config->name.tu, \ | |
11167 | current_config->name.gmch_m, \ | |
11168 | current_config->name.gmch_n, \ | |
11169 | current_config->name.link_m, \ | |
11170 | current_config->name.link_n, \ | |
11171 | current_config->alt_name.tu, \ | |
11172 | current_config->alt_name.gmch_m, \ | |
11173 | current_config->alt_name.gmch_n, \ | |
11174 | current_config->alt_name.link_m, \ | |
11175 | current_config->alt_name.link_n, \ | |
11176 | pipe_config->name.tu, \ | |
11177 | pipe_config->name.gmch_m, \ | |
11178 | pipe_config->name.gmch_n, \ | |
11179 | pipe_config->name.link_m, \ | |
11180 | pipe_config->name.link_n); \ | |
11181 | ret = false; \ | |
88adfff1 DV |
11182 | } |
11183 | ||
1bd1bd80 DV |
11184 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
11185 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
4e8048f8 TU |
11186 | pipe_config_err(adjust, __stringify(name), \ |
11187 | "(%x) (expected %i, found %i)\n", \ | |
11188 | (mask), \ | |
1bd1bd80 DV |
11189 | current_config->name & (mask), \ |
11190 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 11191 | ret = false; \ |
1bd1bd80 DV |
11192 | } |
11193 | ||
5e550656 VS |
11194 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
11195 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
4e8048f8 | 11196 | pipe_config_err(adjust, __stringify(name), \ |
5e550656 VS |
11197 | "(expected %i, found %i)\n", \ |
11198 | current_config->name, \ | |
11199 | pipe_config->name); \ | |
cfb23ed6 | 11200 | ret = false; \ |
5e550656 VS |
11201 | } |
11202 | ||
bb760063 DV |
11203 | #define PIPE_CONF_QUIRK(quirk) \ |
11204 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
11205 | ||
eccb140b DV |
11206 | PIPE_CONF_CHECK_I(cpu_transcoder); |
11207 | ||
08a24034 DV |
11208 | PIPE_CONF_CHECK_I(has_pch_encoder); |
11209 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 11210 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 11211 | |
90a6b7b0 | 11212 | PIPE_CONF_CHECK_I(lane_count); |
95a7a2ae | 11213 | PIPE_CONF_CHECK_X(lane_lat_optim_mask); |
b95af8be | 11214 | |
6315b5d3 | 11215 | if (INTEL_GEN(dev_priv) < 8) { |
cfb23ed6 ML |
11216 | PIPE_CONF_CHECK_M_N(dp_m_n); |
11217 | ||
cfb23ed6 ML |
11218 | if (current_config->has_drrs) |
11219 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
11220 | } else | |
11221 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 11222 | |
253c84c8 | 11223 | PIPE_CONF_CHECK_X(output_types); |
a65347ba | 11224 | |
2d112de7 ACO |
11225 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
11226 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
11227 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
11228 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
11229 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
11230 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 11231 | |
2d112de7 ACO |
11232 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
11233 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
11234 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
11235 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
11236 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
11237 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 11238 | |
c93f54cf | 11239 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 11240 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
772c2a51 | 11241 | if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || |
920a14b2 | 11242 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
b5a9fa09 | 11243 | PIPE_CONF_CHECK_I(limited_color_range); |
15953637 SS |
11244 | |
11245 | PIPE_CONF_CHECK_I(hdmi_scrambling); | |
11246 | PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio); | |
e43823ec | 11247 | PIPE_CONF_CHECK_I(has_infoframe); |
60436fd4 | 11248 | PIPE_CONF_CHECK_I(ycbcr420); |
6c49f241 | 11249 | |
9ed109a7 DV |
11250 | PIPE_CONF_CHECK_I(has_audio); |
11251 | ||
2d112de7 | 11252 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
11253 | DRM_MODE_FLAG_INTERLACE); |
11254 | ||
bb760063 | 11255 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 11256 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11257 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 11258 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11259 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 11260 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11261 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 11262 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
11263 | DRM_MODE_FLAG_NVSYNC); |
11264 | } | |
045ac3b5 | 11265 | |
333b8ca8 | 11266 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a | 11267 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
6315b5d3 | 11268 | if (INTEL_GEN(dev_priv) < 4) |
7f7d8dd6 | 11269 | PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); |
333b8ca8 | 11270 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 11271 | |
bfd16b2a ML |
11272 | if (!adjust) { |
11273 | PIPE_CONF_CHECK_I(pipe_src_w); | |
11274 | PIPE_CONF_CHECK_I(pipe_src_h); | |
11275 | ||
11276 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
11277 | if (current_config->pch_pfit.enabled) { | |
11278 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
11279 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
11280 | } | |
2fa2fe9a | 11281 | |
7aefe2b5 | 11282 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
a7d1b3f4 | 11283 | PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate); |
7aefe2b5 | 11284 | } |
a1b2278e | 11285 | |
e59150dc | 11286 | /* BDW+ don't expose a synchronous way to read the state */ |
772c2a51 | 11287 | if (IS_HASWELL(dev_priv)) |
e59150dc | 11288 | PIPE_CONF_CHECK_I(ips_enabled); |
42db64ef | 11289 | |
282740f7 VS |
11290 | PIPE_CONF_CHECK_I(double_wide); |
11291 | ||
8106ddbd | 11292 | PIPE_CONF_CHECK_P(shared_dpll); |
66e985c0 | 11293 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 11294 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
11295 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
11296 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 11297 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 11298 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
11299 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
11300 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
11301 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 11302 | |
47eacbab VS |
11303 | PIPE_CONF_CHECK_X(dsi_pll.ctrl); |
11304 | PIPE_CONF_CHECK_X(dsi_pll.div); | |
11305 | ||
9beb5fea | 11306 | if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) |
42571aef VS |
11307 | PIPE_CONF_CHECK_I(pipe_bpp); |
11308 | ||
2d112de7 | 11309 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 11310 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 11311 | |
66e985c0 | 11312 | #undef PIPE_CONF_CHECK_X |
08a24034 | 11313 | #undef PIPE_CONF_CHECK_I |
8106ddbd | 11314 | #undef PIPE_CONF_CHECK_P |
1bd1bd80 | 11315 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 11316 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 11317 | #undef PIPE_CONF_QUIRK |
88adfff1 | 11318 | |
cfb23ed6 | 11319 | return ret; |
0e8ffe1b DV |
11320 | } |
11321 | ||
e3b247da VS |
11322 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
11323 | const struct intel_crtc_state *pipe_config) | |
11324 | { | |
11325 | if (pipe_config->has_pch_encoder) { | |
21a727b3 | 11326 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
e3b247da VS |
11327 | &pipe_config->fdi_m_n); |
11328 | int dotclock = pipe_config->base.adjusted_mode.crtc_clock; | |
11329 | ||
11330 | /* | |
11331 | * FDI already provided one idea for the dotclock. | |
11332 | * Yell if the encoder disagrees. | |
11333 | */ | |
11334 | WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
11335 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
11336 | fdi_dotclock, dotclock); | |
11337 | } | |
11338 | } | |
11339 | ||
c0ead703 ML |
11340 | static void verify_wm_state(struct drm_crtc *crtc, |
11341 | struct drm_crtc_state *new_state) | |
08db6652 | 11342 | { |
6315b5d3 | 11343 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
08db6652 | 11344 | struct skl_ddb_allocation hw_ddb, *sw_ddb; |
3de8a14c | 11345 | struct skl_pipe_wm hw_wm, *sw_wm; |
11346 | struct skl_plane_wm *hw_plane_wm, *sw_plane_wm; | |
11347 | struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; | |
e7c84544 ML |
11348 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11349 | const enum pipe pipe = intel_crtc->pipe; | |
3de8a14c | 11350 | int plane, level, max_level = ilk_wm_max_level(dev_priv); |
08db6652 | 11351 | |
6315b5d3 | 11352 | if (INTEL_GEN(dev_priv) < 9 || !new_state->active) |
08db6652 DL |
11353 | return; |
11354 | ||
3de8a14c | 11355 | skl_pipe_wm_get_hw_state(crtc, &hw_wm); |
03af79e0 | 11356 | sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal; |
3de8a14c | 11357 | |
08db6652 DL |
11358 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); |
11359 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
11360 | ||
e7c84544 | 11361 | /* planes */ |
8b364b41 | 11362 | for_each_universal_plane(dev_priv, pipe, plane) { |
3de8a14c | 11363 | hw_plane_wm = &hw_wm.planes[plane]; |
11364 | sw_plane_wm = &sw_wm->planes[plane]; | |
08db6652 | 11365 | |
3de8a14c | 11366 | /* Watermarks */ |
11367 | for (level = 0; level <= max_level; level++) { | |
11368 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
11369 | &sw_plane_wm->wm[level])) | |
11370 | continue; | |
11371 | ||
11372 | DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11373 | pipe_name(pipe), plane + 1, level, | |
11374 | sw_plane_wm->wm[level].plane_en, | |
11375 | sw_plane_wm->wm[level].plane_res_b, | |
11376 | sw_plane_wm->wm[level].plane_res_l, | |
11377 | hw_plane_wm->wm[level].plane_en, | |
11378 | hw_plane_wm->wm[level].plane_res_b, | |
11379 | hw_plane_wm->wm[level].plane_res_l); | |
11380 | } | |
08db6652 | 11381 | |
3de8a14c | 11382 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, |
11383 | &sw_plane_wm->trans_wm)) { | |
11384 | DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11385 | pipe_name(pipe), plane + 1, | |
11386 | sw_plane_wm->trans_wm.plane_en, | |
11387 | sw_plane_wm->trans_wm.plane_res_b, | |
11388 | sw_plane_wm->trans_wm.plane_res_l, | |
11389 | hw_plane_wm->trans_wm.plane_en, | |
11390 | hw_plane_wm->trans_wm.plane_res_b, | |
11391 | hw_plane_wm->trans_wm.plane_res_l); | |
11392 | } | |
11393 | ||
11394 | /* DDB */ | |
11395 | hw_ddb_entry = &hw_ddb.plane[pipe][plane]; | |
11396 | sw_ddb_entry = &sw_ddb->plane[pipe][plane]; | |
11397 | ||
11398 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { | |
faccd994 | 11399 | DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n", |
3de8a14c | 11400 | pipe_name(pipe), plane + 1, |
11401 | sw_ddb_entry->start, sw_ddb_entry->end, | |
11402 | hw_ddb_entry->start, hw_ddb_entry->end); | |
11403 | } | |
e7c84544 | 11404 | } |
08db6652 | 11405 | |
27082493 L |
11406 | /* |
11407 | * cursor | |
11408 | * If the cursor plane isn't active, we may not have updated it's ddb | |
11409 | * allocation. In that case since the ddb allocation will be updated | |
11410 | * once the plane becomes visible, we can skip this check | |
11411 | */ | |
cd5dcbf1 | 11412 | if (1) { |
3de8a14c | 11413 | hw_plane_wm = &hw_wm.planes[PLANE_CURSOR]; |
11414 | sw_plane_wm = &sw_wm->planes[PLANE_CURSOR]; | |
11415 | ||
11416 | /* Watermarks */ | |
11417 | for (level = 0; level <= max_level; level++) { | |
11418 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
11419 | &sw_plane_wm->wm[level])) | |
11420 | continue; | |
11421 | ||
11422 | DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11423 | pipe_name(pipe), level, | |
11424 | sw_plane_wm->wm[level].plane_en, | |
11425 | sw_plane_wm->wm[level].plane_res_b, | |
11426 | sw_plane_wm->wm[level].plane_res_l, | |
11427 | hw_plane_wm->wm[level].plane_en, | |
11428 | hw_plane_wm->wm[level].plane_res_b, | |
11429 | hw_plane_wm->wm[level].plane_res_l); | |
11430 | } | |
11431 | ||
11432 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, | |
11433 | &sw_plane_wm->trans_wm)) { | |
11434 | DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11435 | pipe_name(pipe), | |
11436 | sw_plane_wm->trans_wm.plane_en, | |
11437 | sw_plane_wm->trans_wm.plane_res_b, | |
11438 | sw_plane_wm->trans_wm.plane_res_l, | |
11439 | hw_plane_wm->trans_wm.plane_en, | |
11440 | hw_plane_wm->trans_wm.plane_res_b, | |
11441 | hw_plane_wm->trans_wm.plane_res_l); | |
11442 | } | |
11443 | ||
11444 | /* DDB */ | |
11445 | hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; | |
11446 | sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
27082493 | 11447 | |
3de8a14c | 11448 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { |
faccd994 | 11449 | DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n", |
27082493 | 11450 | pipe_name(pipe), |
3de8a14c | 11451 | sw_ddb_entry->start, sw_ddb_entry->end, |
11452 | hw_ddb_entry->start, hw_ddb_entry->end); | |
27082493 | 11453 | } |
08db6652 DL |
11454 | } |
11455 | } | |
11456 | ||
91d1b4bd | 11457 | static void |
677100ce ML |
11458 | verify_connector_state(struct drm_device *dev, |
11459 | struct drm_atomic_state *state, | |
11460 | struct drm_crtc *crtc) | |
8af6cf88 | 11461 | { |
35dd3c64 | 11462 | struct drm_connector *connector; |
aa5e9b47 | 11463 | struct drm_connector_state *new_conn_state; |
677100ce | 11464 | int i; |
8af6cf88 | 11465 | |
aa5e9b47 | 11466 | for_each_new_connector_in_state(state, connector, new_conn_state, i) { |
35dd3c64 | 11467 | struct drm_encoder *encoder = connector->encoder; |
749d98b8 | 11468 | struct drm_crtc_state *crtc_state = NULL; |
ad3c558f | 11469 | |
aa5e9b47 | 11470 | if (new_conn_state->crtc != crtc) |
e7c84544 ML |
11471 | continue; |
11472 | ||
749d98b8 ML |
11473 | if (crtc) |
11474 | crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc); | |
11475 | ||
11476 | intel_connector_verify_state(crtc_state, new_conn_state); | |
8af6cf88 | 11477 | |
aa5e9b47 | 11478 | I915_STATE_WARN(new_conn_state->best_encoder != encoder, |
35dd3c64 | 11479 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 11480 | } |
91d1b4bd DV |
11481 | } |
11482 | ||
11483 | static void | |
86b04268 | 11484 | verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state) |
91d1b4bd DV |
11485 | { |
11486 | struct intel_encoder *encoder; | |
86b04268 DV |
11487 | struct drm_connector *connector; |
11488 | struct drm_connector_state *old_conn_state, *new_conn_state; | |
11489 | int i; | |
8af6cf88 | 11490 | |
b2784e15 | 11491 | for_each_intel_encoder(dev, encoder) { |
86b04268 | 11492 | bool enabled = false, found = false; |
4d20cd86 | 11493 | enum pipe pipe; |
8af6cf88 DV |
11494 | |
11495 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
11496 | encoder->base.base.id, | |
8e329a03 | 11497 | encoder->base.name); |
8af6cf88 | 11498 | |
86b04268 DV |
11499 | for_each_oldnew_connector_in_state(state, connector, old_conn_state, |
11500 | new_conn_state, i) { | |
11501 | if (old_conn_state->best_encoder == &encoder->base) | |
11502 | found = true; | |
11503 | ||
11504 | if (new_conn_state->best_encoder != &encoder->base) | |
8af6cf88 | 11505 | continue; |
86b04268 | 11506 | found = enabled = true; |
ad3c558f | 11507 | |
86b04268 | 11508 | I915_STATE_WARN(new_conn_state->crtc != |
ad3c558f ML |
11509 | encoder->base.crtc, |
11510 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 11511 | } |
86b04268 DV |
11512 | |
11513 | if (!found) | |
11514 | continue; | |
0e32b39c | 11515 | |
e2c719b7 | 11516 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
11517 | "encoder's enabled state mismatch " |
11518 | "(expected %i, found %i)\n", | |
11519 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
11520 | |
11521 | if (!encoder->base.crtc) { | |
4d20cd86 | 11522 | bool active; |
7c60d198 | 11523 | |
4d20cd86 ML |
11524 | active = encoder->get_hw_state(encoder, &pipe); |
11525 | I915_STATE_WARN(active, | |
11526 | "encoder detached but still enabled on pipe %c.\n", | |
11527 | pipe_name(pipe)); | |
7c60d198 | 11528 | } |
8af6cf88 | 11529 | } |
91d1b4bd DV |
11530 | } |
11531 | ||
11532 | static void | |
c0ead703 ML |
11533 | verify_crtc_state(struct drm_crtc *crtc, |
11534 | struct drm_crtc_state *old_crtc_state, | |
11535 | struct drm_crtc_state *new_crtc_state) | |
91d1b4bd | 11536 | { |
e7c84544 | 11537 | struct drm_device *dev = crtc->dev; |
fac5e23e | 11538 | struct drm_i915_private *dev_priv = to_i915(dev); |
91d1b4bd | 11539 | struct intel_encoder *encoder; |
e7c84544 ML |
11540 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11541 | struct intel_crtc_state *pipe_config, *sw_config; | |
11542 | struct drm_atomic_state *old_state; | |
11543 | bool active; | |
045ac3b5 | 11544 | |
e7c84544 | 11545 | old_state = old_crtc_state->state; |
ec2dc6a0 | 11546 | __drm_atomic_helper_crtc_destroy_state(old_crtc_state); |
e7c84544 ML |
11547 | pipe_config = to_intel_crtc_state(old_crtc_state); |
11548 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
11549 | pipe_config->base.crtc = crtc; | |
11550 | pipe_config->base.state = old_state; | |
8af6cf88 | 11551 | |
78108b7c | 11552 | DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); |
8af6cf88 | 11553 | |
e7c84544 | 11554 | active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config); |
d62cf62a | 11555 | |
e56134bc VS |
11556 | /* we keep both pipes enabled on 830 */ |
11557 | if (IS_I830(dev_priv)) | |
e7c84544 | 11558 | active = new_crtc_state->active; |
6c49f241 | 11559 | |
e7c84544 ML |
11560 | I915_STATE_WARN(new_crtc_state->active != active, |
11561 | "crtc active state doesn't match with hw state " | |
11562 | "(expected %i, found %i)\n", new_crtc_state->active, active); | |
0e8ffe1b | 11563 | |
e7c84544 ML |
11564 | I915_STATE_WARN(intel_crtc->active != new_crtc_state->active, |
11565 | "transitional active state does not match atomic hw state " | |
11566 | "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active); | |
4d20cd86 | 11567 | |
e7c84544 ML |
11568 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
11569 | enum pipe pipe; | |
4d20cd86 | 11570 | |
e7c84544 ML |
11571 | active = encoder->get_hw_state(encoder, &pipe); |
11572 | I915_STATE_WARN(active != new_crtc_state->active, | |
11573 | "[ENCODER:%i] active %i with crtc active %i\n", | |
11574 | encoder->base.base.id, active, new_crtc_state->active); | |
4d20cd86 | 11575 | |
e7c84544 ML |
11576 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, |
11577 | "Encoder connected to wrong pipe %c\n", | |
11578 | pipe_name(pipe)); | |
4d20cd86 | 11579 | |
253c84c8 VS |
11580 | if (active) { |
11581 | pipe_config->output_types |= 1 << encoder->type; | |
e7c84544 | 11582 | encoder->get_config(encoder, pipe_config); |
253c84c8 | 11583 | } |
e7c84544 | 11584 | } |
53d9f4e9 | 11585 | |
a7d1b3f4 VS |
11586 | intel_crtc_compute_pixel_rate(pipe_config); |
11587 | ||
e7c84544 ML |
11588 | if (!new_crtc_state->active) |
11589 | return; | |
cfb23ed6 | 11590 | |
e7c84544 | 11591 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
e3b247da | 11592 | |
749d98b8 | 11593 | sw_config = to_intel_crtc_state(new_crtc_state); |
6315b5d3 | 11594 | if (!intel_pipe_config_compare(dev_priv, sw_config, |
e7c84544 ML |
11595 | pipe_config, false)) { |
11596 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); | |
11597 | intel_dump_pipe_config(intel_crtc, pipe_config, | |
11598 | "[hw state]"); | |
11599 | intel_dump_pipe_config(intel_crtc, sw_config, | |
11600 | "[sw state]"); | |
8af6cf88 DV |
11601 | } |
11602 | } | |
11603 | ||
91d1b4bd | 11604 | static void |
c0ead703 ML |
11605 | verify_single_dpll_state(struct drm_i915_private *dev_priv, |
11606 | struct intel_shared_dpll *pll, | |
11607 | struct drm_crtc *crtc, | |
11608 | struct drm_crtc_state *new_state) | |
91d1b4bd | 11609 | { |
91d1b4bd | 11610 | struct intel_dpll_hw_state dpll_hw_state; |
e7c84544 ML |
11611 | unsigned crtc_mask; |
11612 | bool active; | |
5358901f | 11613 | |
e7c84544 | 11614 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
5358901f | 11615 | |
e7c84544 | 11616 | DRM_DEBUG_KMS("%s\n", pll->name); |
5358901f | 11617 | |
e7c84544 | 11618 | active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state); |
5358901f | 11619 | |
e7c84544 ML |
11620 | if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) { |
11621 | I915_STATE_WARN(!pll->on && pll->active_mask, | |
11622 | "pll in active use but not on in sw tracking\n"); | |
11623 | I915_STATE_WARN(pll->on && !pll->active_mask, | |
11624 | "pll is on but not used by any active crtc\n"); | |
11625 | I915_STATE_WARN(pll->on != active, | |
11626 | "pll on state mismatch (expected %i, found %i)\n", | |
11627 | pll->on, active); | |
11628 | } | |
5358901f | 11629 | |
e7c84544 | 11630 | if (!crtc) { |
2c42e535 | 11631 | I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask, |
e7c84544 | 11632 | "more active pll users than references: %x vs %x\n", |
2c42e535 | 11633 | pll->active_mask, pll->state.crtc_mask); |
5358901f | 11634 | |
e7c84544 ML |
11635 | return; |
11636 | } | |
11637 | ||
11638 | crtc_mask = 1 << drm_crtc_index(crtc); | |
11639 | ||
11640 | if (new_state->active) | |
11641 | I915_STATE_WARN(!(pll->active_mask & crtc_mask), | |
11642 | "pll active mismatch (expected pipe %c in active mask 0x%02x)\n", | |
11643 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
11644 | else | |
11645 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
11646 | "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n", | |
11647 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
2dd66ebd | 11648 | |
2c42e535 | 11649 | I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask), |
e7c84544 | 11650 | "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", |
2c42e535 | 11651 | crtc_mask, pll->state.crtc_mask); |
66e985c0 | 11652 | |
2c42e535 | 11653 | I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state, |
e7c84544 ML |
11654 | &dpll_hw_state, |
11655 | sizeof(dpll_hw_state)), | |
11656 | "pll hw state mismatch\n"); | |
11657 | } | |
11658 | ||
11659 | static void | |
c0ead703 ML |
11660 | verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc, |
11661 | struct drm_crtc_state *old_crtc_state, | |
11662 | struct drm_crtc_state *new_crtc_state) | |
e7c84544 | 11663 | { |
fac5e23e | 11664 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
11665 | struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state); |
11666 | struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state); | |
11667 | ||
11668 | if (new_state->shared_dpll) | |
c0ead703 | 11669 | verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state); |
e7c84544 ML |
11670 | |
11671 | if (old_state->shared_dpll && | |
11672 | old_state->shared_dpll != new_state->shared_dpll) { | |
11673 | unsigned crtc_mask = 1 << drm_crtc_index(crtc); | |
11674 | struct intel_shared_dpll *pll = old_state->shared_dpll; | |
11675 | ||
11676 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
11677 | "pll active mismatch (didn't expect pipe %c in active mask)\n", | |
11678 | pipe_name(drm_crtc_index(crtc))); | |
2c42e535 | 11679 | I915_STATE_WARN(pll->state.crtc_mask & crtc_mask, |
e7c84544 ML |
11680 | "pll enabled crtcs mismatch (found %x in enabled mask)\n", |
11681 | pipe_name(drm_crtc_index(crtc))); | |
5358901f | 11682 | } |
8af6cf88 DV |
11683 | } |
11684 | ||
e7c84544 | 11685 | static void |
c0ead703 | 11686 | intel_modeset_verify_crtc(struct drm_crtc *crtc, |
677100ce ML |
11687 | struct drm_atomic_state *state, |
11688 | struct drm_crtc_state *old_state, | |
11689 | struct drm_crtc_state *new_state) | |
e7c84544 | 11690 | { |
5a21b665 DV |
11691 | if (!needs_modeset(new_state) && |
11692 | !to_intel_crtc_state(new_state)->update_pipe) | |
11693 | return; | |
11694 | ||
c0ead703 | 11695 | verify_wm_state(crtc, new_state); |
677100ce | 11696 | verify_connector_state(crtc->dev, state, crtc); |
c0ead703 ML |
11697 | verify_crtc_state(crtc, old_state, new_state); |
11698 | verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state); | |
e7c84544 ML |
11699 | } |
11700 | ||
11701 | static void | |
c0ead703 | 11702 | verify_disabled_dpll_state(struct drm_device *dev) |
e7c84544 | 11703 | { |
fac5e23e | 11704 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
11705 | int i; |
11706 | ||
11707 | for (i = 0; i < dev_priv->num_shared_dpll; i++) | |
c0ead703 | 11708 | verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL); |
e7c84544 ML |
11709 | } |
11710 | ||
11711 | static void | |
677100ce ML |
11712 | intel_modeset_verify_disabled(struct drm_device *dev, |
11713 | struct drm_atomic_state *state) | |
e7c84544 | 11714 | { |
86b04268 | 11715 | verify_encoder_state(dev, state); |
677100ce | 11716 | verify_connector_state(dev, state, NULL); |
c0ead703 | 11717 | verify_disabled_dpll_state(dev); |
e7c84544 ML |
11718 | } |
11719 | ||
80715b2f VS |
11720 | static void update_scanline_offset(struct intel_crtc *crtc) |
11721 | { | |
4f8036a2 | 11722 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
80715b2f VS |
11723 | |
11724 | /* | |
11725 | * The scanline counter increments at the leading edge of hsync. | |
11726 | * | |
11727 | * On most platforms it starts counting from vtotal-1 on the | |
11728 | * first active line. That means the scanline counter value is | |
11729 | * always one less than what we would expect. Ie. just after | |
11730 | * start of vblank, which also occurs at start of hsync (on the | |
11731 | * last active line), the scanline counter will read vblank_start-1. | |
11732 | * | |
11733 | * On gen2 the scanline counter starts counting from 1 instead | |
11734 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
11735 | * to keep the value positive), instead of adding one. | |
11736 | * | |
11737 | * On HSW+ the behaviour of the scanline counter depends on the output | |
11738 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
11739 | * there's an extra 1 line difference. So we need to add two instead of | |
11740 | * one to the value. | |
ec1b4ee2 VS |
11741 | * |
11742 | * On VLV/CHV DSI the scanline counter would appear to increment | |
11743 | * approx. 1/3 of a scanline before start of vblank. Unfortunately | |
11744 | * that means we can't tell whether we're in vblank or not while | |
11745 | * we're on that particular line. We must still set scanline_offset | |
11746 | * to 1 so that the vblank timestamps come out correct when we query | |
11747 | * the scanline counter from within the vblank interrupt handler. | |
11748 | * However if queried just before the start of vblank we'll get an | |
11749 | * answer that's slightly in the future. | |
80715b2f | 11750 | */ |
4f8036a2 | 11751 | if (IS_GEN2(dev_priv)) { |
124abe07 | 11752 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
11753 | int vtotal; |
11754 | ||
124abe07 VS |
11755 | vtotal = adjusted_mode->crtc_vtotal; |
11756 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
11757 | vtotal /= 2; |
11758 | ||
11759 | crtc->scanline_offset = vtotal - 1; | |
4f8036a2 | 11760 | } else if (HAS_DDI(dev_priv) && |
2d84d2b3 | 11761 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
11762 | crtc->scanline_offset = 2; |
11763 | } else | |
11764 | crtc->scanline_offset = 1; | |
11765 | } | |
11766 | ||
ad421372 | 11767 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 11768 | { |
225da59b | 11769 | struct drm_device *dev = state->dev; |
ed6739ef | 11770 | struct drm_i915_private *dev_priv = to_i915(dev); |
0a9ab303 | 11771 | struct drm_crtc *crtc; |
aa5e9b47 | 11772 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
0a9ab303 | 11773 | int i; |
ed6739ef ACO |
11774 | |
11775 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 11776 | return; |
ed6739ef | 11777 | |
aa5e9b47 | 11778 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
fb1a38a9 | 11779 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8106ddbd | 11780 | struct intel_shared_dpll *old_dpll = |
aa5e9b47 | 11781 | to_intel_crtc_state(old_crtc_state)->shared_dpll; |
0a9ab303 | 11782 | |
aa5e9b47 | 11783 | if (!needs_modeset(new_crtc_state)) |
225da59b ACO |
11784 | continue; |
11785 | ||
aa5e9b47 | 11786 | to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL; |
fb1a38a9 | 11787 | |
8106ddbd | 11788 | if (!old_dpll) |
fb1a38a9 | 11789 | continue; |
0a9ab303 | 11790 | |
a1c414ee | 11791 | intel_release_shared_dpll(old_dpll, intel_crtc, state); |
ad421372 | 11792 | } |
ed6739ef ACO |
11793 | } |
11794 | ||
99d736a2 ML |
11795 | /* |
11796 | * This implements the workaround described in the "notes" section of the mode | |
11797 | * set sequence documentation. When going from no pipes or single pipe to | |
11798 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
11799 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
11800 | */ | |
11801 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
11802 | { | |
11803 | struct drm_crtc_state *crtc_state; | |
11804 | struct intel_crtc *intel_crtc; | |
11805 | struct drm_crtc *crtc; | |
11806 | struct intel_crtc_state *first_crtc_state = NULL; | |
11807 | struct intel_crtc_state *other_crtc_state = NULL; | |
11808 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
11809 | int i; | |
11810 | ||
11811 | /* look at all crtc's that are going to be enabled in during modeset */ | |
aa5e9b47 | 11812 | for_each_new_crtc_in_state(state, crtc, crtc_state, i) { |
99d736a2 ML |
11813 | intel_crtc = to_intel_crtc(crtc); |
11814 | ||
11815 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
11816 | continue; | |
11817 | ||
11818 | if (first_crtc_state) { | |
11819 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
11820 | break; | |
11821 | } else { | |
11822 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
11823 | first_pipe = intel_crtc->pipe; | |
11824 | } | |
11825 | } | |
11826 | ||
11827 | /* No workaround needed? */ | |
11828 | if (!first_crtc_state) | |
11829 | return 0; | |
11830 | ||
11831 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
11832 | for_each_intel_crtc(state->dev, intel_crtc) { | |
11833 | struct intel_crtc_state *pipe_config; | |
11834 | ||
11835 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
11836 | if (IS_ERR(pipe_config)) | |
11837 | return PTR_ERR(pipe_config); | |
11838 | ||
11839 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
11840 | ||
11841 | if (!pipe_config->base.active || | |
11842 | needs_modeset(&pipe_config->base)) | |
11843 | continue; | |
11844 | ||
11845 | /* 2 or more enabled crtcs means no need for w/a */ | |
11846 | if (enabled_pipe != INVALID_PIPE) | |
11847 | return 0; | |
11848 | ||
11849 | enabled_pipe = intel_crtc->pipe; | |
11850 | } | |
11851 | ||
11852 | if (enabled_pipe != INVALID_PIPE) | |
11853 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
11854 | else if (other_crtc_state) | |
11855 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
11856 | ||
11857 | return 0; | |
11858 | } | |
11859 | ||
8d96561a VS |
11860 | static int intel_lock_all_pipes(struct drm_atomic_state *state) |
11861 | { | |
11862 | struct drm_crtc *crtc; | |
11863 | ||
11864 | /* Add all pipes to the state */ | |
11865 | for_each_crtc(state->dev, crtc) { | |
11866 | struct drm_crtc_state *crtc_state; | |
11867 | ||
11868 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
11869 | if (IS_ERR(crtc_state)) | |
11870 | return PTR_ERR(crtc_state); | |
11871 | } | |
11872 | ||
11873 | return 0; | |
11874 | } | |
11875 | ||
27c329ed ML |
11876 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
11877 | { | |
11878 | struct drm_crtc *crtc; | |
27c329ed | 11879 | |
8d96561a VS |
11880 | /* |
11881 | * Add all pipes to the state, and force | |
11882 | * a modeset on all the active ones. | |
11883 | */ | |
27c329ed | 11884 | for_each_crtc(state->dev, crtc) { |
9780aad5 VS |
11885 | struct drm_crtc_state *crtc_state; |
11886 | int ret; | |
11887 | ||
27c329ed ML |
11888 | crtc_state = drm_atomic_get_crtc_state(state, crtc); |
11889 | if (IS_ERR(crtc_state)) | |
11890 | return PTR_ERR(crtc_state); | |
11891 | ||
11892 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
11893 | continue; | |
11894 | ||
11895 | crtc_state->mode_changed = true; | |
11896 | ||
11897 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
11898 | if (ret) | |
9780aad5 | 11899 | return ret; |
27c329ed ML |
11900 | |
11901 | ret = drm_atomic_add_affected_planes(state, crtc); | |
11902 | if (ret) | |
9780aad5 | 11903 | return ret; |
27c329ed ML |
11904 | } |
11905 | ||
9780aad5 | 11906 | return 0; |
27c329ed ML |
11907 | } |
11908 | ||
c347a676 | 11909 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 11910 | { |
565602d7 | 11911 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 11912 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
565602d7 | 11913 | struct drm_crtc *crtc; |
aa5e9b47 | 11914 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
565602d7 | 11915 | int ret = 0, i; |
054518dd | 11916 | |
b359283a ML |
11917 | if (!check_digital_port_conflicts(state)) { |
11918 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
11919 | return -EINVAL; | |
11920 | } | |
11921 | ||
565602d7 ML |
11922 | intel_state->modeset = true; |
11923 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
bb0f4aab VS |
11924 | intel_state->cdclk.logical = dev_priv->cdclk.logical; |
11925 | intel_state->cdclk.actual = dev_priv->cdclk.actual; | |
565602d7 | 11926 | |
aa5e9b47 ML |
11927 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
11928 | if (new_crtc_state->active) | |
565602d7 ML |
11929 | intel_state->active_crtcs |= 1 << i; |
11930 | else | |
11931 | intel_state->active_crtcs &= ~(1 << i); | |
8b4a7d05 | 11932 | |
aa5e9b47 | 11933 | if (old_crtc_state->active != new_crtc_state->active) |
8b4a7d05 | 11934 | intel_state->active_pipe_changes |= drm_crtc_mask(crtc); |
565602d7 ML |
11935 | } |
11936 | ||
054518dd ACO |
11937 | /* |
11938 | * See if the config requires any additional preparation, e.g. | |
11939 | * to adjust global state with pipes off. We need to do this | |
11940 | * here so we can get the modeset_pipe updated config for the new | |
11941 | * mode set on this crtc. For other crtcs we need to use the | |
11942 | * adjusted_mode bits in the crtc directly. | |
11943 | */ | |
27c329ed | 11944 | if (dev_priv->display.modeset_calc_cdclk) { |
27c329ed | 11945 | ret = dev_priv->display.modeset_calc_cdclk(state); |
c89e39f3 CT |
11946 | if (ret < 0) |
11947 | return ret; | |
27c329ed | 11948 | |
8d96561a | 11949 | /* |
bb0f4aab | 11950 | * Writes to dev_priv->cdclk.logical must protected by |
8d96561a VS |
11951 | * holding all the crtc locks, even if we don't end up |
11952 | * touching the hardware | |
11953 | */ | |
bb0f4aab VS |
11954 | if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical, |
11955 | &intel_state->cdclk.logical)) { | |
8d96561a VS |
11956 | ret = intel_lock_all_pipes(state); |
11957 | if (ret < 0) | |
11958 | return ret; | |
11959 | } | |
11960 | ||
11961 | /* All pipes must be switched off while we change the cdclk. */ | |
bb0f4aab VS |
11962 | if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual, |
11963 | &intel_state->cdclk.actual)) { | |
27c329ed | 11964 | ret = intel_modeset_all_pipes(state); |
8d96561a VS |
11965 | if (ret < 0) |
11966 | return ret; | |
11967 | } | |
e8788cbc | 11968 | |
bb0f4aab VS |
11969 | DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n", |
11970 | intel_state->cdclk.logical.cdclk, | |
11971 | intel_state->cdclk.actual.cdclk); | |
e0ca7a6b | 11972 | } else { |
bb0f4aab | 11973 | to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical; |
e0ca7a6b | 11974 | } |
054518dd | 11975 | |
ad421372 | 11976 | intel_modeset_clear_plls(state); |
054518dd | 11977 | |
565602d7 | 11978 | if (IS_HASWELL(dev_priv)) |
ad421372 | 11979 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 11980 | |
ad421372 | 11981 | return 0; |
c347a676 ACO |
11982 | } |
11983 | ||
aa363136 MR |
11984 | /* |
11985 | * Handle calculation of various watermark data at the end of the atomic check | |
11986 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
11987 | * handlers to ensure that all derived state has been updated. | |
11988 | */ | |
55994c2c | 11989 | static int calc_watermark_data(struct drm_atomic_state *state) |
aa363136 MR |
11990 | { |
11991 | struct drm_device *dev = state->dev; | |
98d39494 | 11992 | struct drm_i915_private *dev_priv = to_i915(dev); |
98d39494 MR |
11993 | |
11994 | /* Is there platform-specific watermark information to calculate? */ | |
11995 | if (dev_priv->display.compute_global_watermarks) | |
55994c2c MR |
11996 | return dev_priv->display.compute_global_watermarks(state); |
11997 | ||
11998 | return 0; | |
aa363136 MR |
11999 | } |
12000 | ||
74c090b1 ML |
12001 | /** |
12002 | * intel_atomic_check - validate state object | |
12003 | * @dev: drm device | |
12004 | * @state: state to validate | |
12005 | */ | |
12006 | static int intel_atomic_check(struct drm_device *dev, | |
12007 | struct drm_atomic_state *state) | |
c347a676 | 12008 | { |
dd8b3bdb | 12009 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 12010 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 | 12011 | struct drm_crtc *crtc; |
aa5e9b47 | 12012 | struct drm_crtc_state *old_crtc_state, *crtc_state; |
c347a676 | 12013 | int ret, i; |
61333b60 | 12014 | bool any_ms = false; |
c347a676 | 12015 | |
74c090b1 | 12016 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
12017 | if (ret) |
12018 | return ret; | |
12019 | ||
aa5e9b47 | 12020 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) { |
cfb23ed6 ML |
12021 | struct intel_crtc_state *pipe_config = |
12022 | to_intel_crtc_state(crtc_state); | |
1ed51de9 DV |
12023 | |
12024 | /* Catch I915_MODE_FLAG_INHERITED */ | |
aa5e9b47 | 12025 | if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags) |
1ed51de9 | 12026 | crtc_state->mode_changed = true; |
cfb23ed6 | 12027 | |
af4a879e | 12028 | if (!needs_modeset(crtc_state)) |
c347a676 ACO |
12029 | continue; |
12030 | ||
af4a879e DV |
12031 | if (!crtc_state->enable) { |
12032 | any_ms = true; | |
cfb23ed6 | 12033 | continue; |
af4a879e | 12034 | } |
cfb23ed6 | 12035 | |
26495481 DV |
12036 | /* FIXME: For only active_changed we shouldn't need to do any |
12037 | * state recomputation at all. */ | |
12038 | ||
1ed51de9 DV |
12039 | ret = drm_atomic_add_affected_connectors(state, crtc); |
12040 | if (ret) | |
12041 | return ret; | |
b359283a | 12042 | |
cfb23ed6 | 12043 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
25aa1c39 ML |
12044 | if (ret) { |
12045 | intel_dump_pipe_config(to_intel_crtc(crtc), | |
12046 | pipe_config, "[failed]"); | |
c347a676 | 12047 | return ret; |
25aa1c39 | 12048 | } |
c347a676 | 12049 | |
73831236 | 12050 | if (i915.fastboot && |
6315b5d3 | 12051 | intel_pipe_config_compare(dev_priv, |
aa5e9b47 | 12052 | to_intel_crtc_state(old_crtc_state), |
1ed51de9 | 12053 | pipe_config, true)) { |
26495481 | 12054 | crtc_state->mode_changed = false; |
aa5e9b47 | 12055 | pipe_config->update_pipe = true; |
26495481 DV |
12056 | } |
12057 | ||
af4a879e | 12058 | if (needs_modeset(crtc_state)) |
26495481 | 12059 | any_ms = true; |
cfb23ed6 | 12060 | |
af4a879e DV |
12061 | ret = drm_atomic_add_affected_planes(state, crtc); |
12062 | if (ret) | |
12063 | return ret; | |
61333b60 | 12064 | |
26495481 DV |
12065 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
12066 | needs_modeset(crtc_state) ? | |
12067 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
12068 | } |
12069 | ||
61333b60 ML |
12070 | if (any_ms) { |
12071 | ret = intel_modeset_checks(state); | |
12072 | ||
12073 | if (ret) | |
12074 | return ret; | |
e0ca7a6b | 12075 | } else { |
bb0f4aab | 12076 | intel_state->cdclk.logical = dev_priv->cdclk.logical; |
e0ca7a6b | 12077 | } |
76305b1a | 12078 | |
dd8b3bdb | 12079 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
12080 | if (ret) |
12081 | return ret; | |
12082 | ||
f51be2e0 | 12083 | intel_fbc_choose_crtc(dev_priv, state); |
55994c2c | 12084 | return calc_watermark_data(state); |
054518dd ACO |
12085 | } |
12086 | ||
5008e874 | 12087 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
d07f0e59 | 12088 | struct drm_atomic_state *state) |
5008e874 | 12089 | { |
fd70075f | 12090 | return drm_atomic_helper_prepare_planes(dev, state); |
5008e874 ML |
12091 | } |
12092 | ||
a2991414 ML |
12093 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) |
12094 | { | |
12095 | struct drm_device *dev = crtc->base.dev; | |
12096 | ||
12097 | if (!dev->max_vblank_count) | |
ca814b25 | 12098 | return drm_crtc_accurate_vblank_count(&crtc->base); |
a2991414 ML |
12099 | |
12100 | return dev->driver->get_vblank_counter(dev, crtc->pipe); | |
12101 | } | |
12102 | ||
5a21b665 DV |
12103 | static void intel_atomic_wait_for_vblanks(struct drm_device *dev, |
12104 | struct drm_i915_private *dev_priv, | |
12105 | unsigned crtc_mask) | |
e8861675 | 12106 | { |
5a21b665 DV |
12107 | unsigned last_vblank_count[I915_MAX_PIPES]; |
12108 | enum pipe pipe; | |
12109 | int ret; | |
e8861675 | 12110 | |
5a21b665 DV |
12111 | if (!crtc_mask) |
12112 | return; | |
e8861675 | 12113 | |
5a21b665 | 12114 | for_each_pipe(dev_priv, pipe) { |
98187836 VS |
12115 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, |
12116 | pipe); | |
e8861675 | 12117 | |
5a21b665 | 12118 | if (!((1 << pipe) & crtc_mask)) |
e8861675 ML |
12119 | continue; |
12120 | ||
e2af48c6 | 12121 | ret = drm_crtc_vblank_get(&crtc->base); |
5a21b665 DV |
12122 | if (WARN_ON(ret != 0)) { |
12123 | crtc_mask &= ~(1 << pipe); | |
12124 | continue; | |
e8861675 ML |
12125 | } |
12126 | ||
e2af48c6 | 12127 | last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base); |
e8861675 ML |
12128 | } |
12129 | ||
5a21b665 | 12130 | for_each_pipe(dev_priv, pipe) { |
98187836 VS |
12131 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, |
12132 | pipe); | |
5a21b665 | 12133 | long lret; |
e8861675 | 12134 | |
5a21b665 DV |
12135 | if (!((1 << pipe) & crtc_mask)) |
12136 | continue; | |
d55dbd06 | 12137 | |
5a21b665 DV |
12138 | lret = wait_event_timeout(dev->vblank[pipe].queue, |
12139 | last_vblank_count[pipe] != | |
e2af48c6 | 12140 | drm_crtc_vblank_count(&crtc->base), |
5a21b665 | 12141 | msecs_to_jiffies(50)); |
d55dbd06 | 12142 | |
5a21b665 | 12143 | WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe)); |
d55dbd06 | 12144 | |
e2af48c6 | 12145 | drm_crtc_vblank_put(&crtc->base); |
d55dbd06 ML |
12146 | } |
12147 | } | |
12148 | ||
5a21b665 | 12149 | static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) |
a6747b73 | 12150 | { |
5a21b665 DV |
12151 | /* fb updated, need to unpin old fb */ |
12152 | if (crtc_state->fb_changed) | |
12153 | return true; | |
a6747b73 | 12154 | |
5a21b665 DV |
12155 | /* wm changes, need vblank before final wm's */ |
12156 | if (crtc_state->update_wm_post) | |
12157 | return true; | |
a6747b73 | 12158 | |
5eeb798b | 12159 | if (crtc_state->wm.need_postvbl_update) |
5a21b665 | 12160 | return true; |
a6747b73 | 12161 | |
5a21b665 | 12162 | return false; |
e8861675 ML |
12163 | } |
12164 | ||
896e5bb0 L |
12165 | static void intel_update_crtc(struct drm_crtc *crtc, |
12166 | struct drm_atomic_state *state, | |
12167 | struct drm_crtc_state *old_crtc_state, | |
aa5e9b47 | 12168 | struct drm_crtc_state *new_crtc_state, |
896e5bb0 L |
12169 | unsigned int *crtc_vblank_mask) |
12170 | { | |
12171 | struct drm_device *dev = crtc->dev; | |
12172 | struct drm_i915_private *dev_priv = to_i915(dev); | |
12173 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
aa5e9b47 ML |
12174 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state); |
12175 | bool modeset = needs_modeset(new_crtc_state); | |
896e5bb0 L |
12176 | |
12177 | if (modeset) { | |
12178 | update_scanline_offset(intel_crtc); | |
12179 | dev_priv->display.crtc_enable(pipe_config, state); | |
12180 | } else { | |
aa5e9b47 ML |
12181 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state), |
12182 | pipe_config); | |
896e5bb0 L |
12183 | } |
12184 | ||
12185 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12186 | intel_fbc_enable( | |
12187 | intel_crtc, pipe_config, | |
12188 | to_intel_plane_state(crtc->primary->state)); | |
12189 | } | |
12190 | ||
12191 | drm_atomic_helper_commit_planes_on_crtc(old_crtc_state); | |
12192 | ||
12193 | if (needs_vblank_wait(pipe_config)) | |
12194 | *crtc_vblank_mask |= drm_crtc_mask(crtc); | |
12195 | } | |
12196 | ||
12197 | static void intel_update_crtcs(struct drm_atomic_state *state, | |
12198 | unsigned int *crtc_vblank_mask) | |
12199 | { | |
12200 | struct drm_crtc *crtc; | |
aa5e9b47 | 12201 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
896e5bb0 L |
12202 | int i; |
12203 | ||
aa5e9b47 ML |
12204 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
12205 | if (!new_crtc_state->active) | |
896e5bb0 L |
12206 | continue; |
12207 | ||
12208 | intel_update_crtc(crtc, state, old_crtc_state, | |
aa5e9b47 | 12209 | new_crtc_state, crtc_vblank_mask); |
896e5bb0 L |
12210 | } |
12211 | } | |
12212 | ||
27082493 L |
12213 | static void skl_update_crtcs(struct drm_atomic_state *state, |
12214 | unsigned int *crtc_vblank_mask) | |
12215 | { | |
0f0f74bc | 12216 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
27082493 L |
12217 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
12218 | struct drm_crtc *crtc; | |
ce0ba283 | 12219 | struct intel_crtc *intel_crtc; |
aa5e9b47 | 12220 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
ce0ba283 | 12221 | struct intel_crtc_state *cstate; |
27082493 L |
12222 | unsigned int updated = 0; |
12223 | bool progress; | |
12224 | enum pipe pipe; | |
5eff503b ML |
12225 | int i; |
12226 | ||
12227 | const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {}; | |
12228 | ||
aa5e9b47 | 12229 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) |
5eff503b | 12230 | /* ignore allocations for crtc's that have been turned off. */ |
aa5e9b47 | 12231 | if (new_crtc_state->active) |
5eff503b | 12232 | entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb; |
27082493 L |
12233 | |
12234 | /* | |
12235 | * Whenever the number of active pipes changes, we need to make sure we | |
12236 | * update the pipes in the right order so that their ddb allocations | |
12237 | * never overlap with eachother inbetween CRTC updates. Otherwise we'll | |
12238 | * cause pipe underruns and other bad stuff. | |
12239 | */ | |
12240 | do { | |
27082493 L |
12241 | progress = false; |
12242 | ||
aa5e9b47 | 12243 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
27082493 L |
12244 | bool vbl_wait = false; |
12245 | unsigned int cmask = drm_crtc_mask(crtc); | |
ce0ba283 L |
12246 | |
12247 | intel_crtc = to_intel_crtc(crtc); | |
12248 | cstate = to_intel_crtc_state(crtc->state); | |
12249 | pipe = intel_crtc->pipe; | |
27082493 | 12250 | |
5eff503b | 12251 | if (updated & cmask || !cstate->base.active) |
27082493 | 12252 | continue; |
5eff503b ML |
12253 | |
12254 | if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i)) | |
27082493 L |
12255 | continue; |
12256 | ||
12257 | updated |= cmask; | |
5eff503b | 12258 | entries[i] = &cstate->wm.skl.ddb; |
27082493 L |
12259 | |
12260 | /* | |
12261 | * If this is an already active pipe, it's DDB changed, | |
12262 | * and this isn't the last pipe that needs updating | |
12263 | * then we need to wait for a vblank to pass for the | |
12264 | * new ddb allocation to take effect. | |
12265 | */ | |
ce0ba283 | 12266 | if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb, |
512b5527 | 12267 | &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) && |
aa5e9b47 | 12268 | !new_crtc_state->active_changed && |
27082493 L |
12269 | intel_state->wm_results.dirty_pipes != updated) |
12270 | vbl_wait = true; | |
12271 | ||
12272 | intel_update_crtc(crtc, state, old_crtc_state, | |
aa5e9b47 | 12273 | new_crtc_state, crtc_vblank_mask); |
27082493 L |
12274 | |
12275 | if (vbl_wait) | |
0f0f74bc | 12276 | intel_wait_for_vblank(dev_priv, pipe); |
27082493 L |
12277 | |
12278 | progress = true; | |
12279 | } | |
12280 | } while (progress); | |
12281 | } | |
12282 | ||
ba318c61 CW |
12283 | static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) |
12284 | { | |
12285 | struct intel_atomic_state *state, *next; | |
12286 | struct llist_node *freed; | |
12287 | ||
12288 | freed = llist_del_all(&dev_priv->atomic_helper.free_list); | |
12289 | llist_for_each_entry_safe(state, next, freed, freed) | |
12290 | drm_atomic_state_put(&state->base); | |
12291 | } | |
12292 | ||
12293 | static void intel_atomic_helper_free_state_worker(struct work_struct *work) | |
12294 | { | |
12295 | struct drm_i915_private *dev_priv = | |
12296 | container_of(work, typeof(*dev_priv), atomic_helper.free_work); | |
12297 | ||
12298 | intel_atomic_helper_free_state(dev_priv); | |
12299 | } | |
12300 | ||
94f05024 | 12301 | static void intel_atomic_commit_tail(struct drm_atomic_state *state) |
a6778b3c | 12302 | { |
94f05024 | 12303 | struct drm_device *dev = state->dev; |
565602d7 | 12304 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 12305 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa5e9b47 | 12306 | struct drm_crtc_state *old_crtc_state, *new_crtc_state; |
7580d774 | 12307 | struct drm_crtc *crtc; |
5a21b665 | 12308 | struct intel_crtc_state *intel_cstate; |
5a21b665 | 12309 | bool hw_check = intel_state->modeset; |
d8fc70b7 | 12310 | u64 put_domains[I915_MAX_PIPES] = {}; |
5a21b665 | 12311 | unsigned crtc_vblank_mask = 0; |
e95433c7 | 12312 | int i; |
a6778b3c | 12313 | |
42b062b0 DV |
12314 | i915_sw_fence_wait(&intel_state->commit_ready); |
12315 | ||
ea0000f0 DV |
12316 | drm_atomic_helper_wait_for_dependencies(state); |
12317 | ||
c3b32658 | 12318 | if (intel_state->modeset) |
5a21b665 | 12319 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); |
565602d7 | 12320 | |
aa5e9b47 | 12321 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
a539205a ML |
12322 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
12323 | ||
aa5e9b47 ML |
12324 | if (needs_modeset(new_crtc_state) || |
12325 | to_intel_crtc_state(new_crtc_state)->update_pipe) { | |
5a21b665 DV |
12326 | hw_check = true; |
12327 | ||
12328 | put_domains[to_intel_crtc(crtc)->pipe] = | |
12329 | modeset_get_crtc_power_domains(crtc, | |
aa5e9b47 | 12330 | to_intel_crtc_state(new_crtc_state)); |
5a21b665 DV |
12331 | } |
12332 | ||
aa5e9b47 | 12333 | if (!needs_modeset(new_crtc_state)) |
61333b60 ML |
12334 | continue; |
12335 | ||
aa5e9b47 ML |
12336 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state), |
12337 | to_intel_crtc_state(new_crtc_state)); | |
460da916 | 12338 | |
29ceb0e6 VS |
12339 | if (old_crtc_state->active) { |
12340 | intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); | |
4a806558 | 12341 | dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state); |
eddfcbcd | 12342 | intel_crtc->active = false; |
58f9c0bc | 12343 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 12344 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
12345 | |
12346 | /* | |
12347 | * Underruns don't always raise | |
12348 | * interrupts, so check manually. | |
12349 | */ | |
12350 | intel_check_cpu_fifo_underruns(dev_priv); | |
12351 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 | 12352 | |
e62929b3 ML |
12353 | if (!crtc->state->active) { |
12354 | /* | |
12355 | * Make sure we don't call initial_watermarks | |
12356 | * for ILK-style watermark updates. | |
ff32c54e VS |
12357 | * |
12358 | * No clue what this is supposed to achieve. | |
e62929b3 | 12359 | */ |
ff32c54e | 12360 | if (INTEL_GEN(dev_priv) >= 9) |
e62929b3 ML |
12361 | dev_priv->display.initial_watermarks(intel_state, |
12362 | to_intel_crtc_state(crtc->state)); | |
e62929b3 | 12363 | } |
a539205a | 12364 | } |
b8cecdf5 | 12365 | } |
7758a113 | 12366 | |
ea9d758d DV |
12367 | /* Only after disabling all output pipelines that will be changed can we |
12368 | * update the the output configuration. */ | |
4740b0f2 | 12369 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 12370 | |
565602d7 | 12371 | if (intel_state->modeset) { |
4740b0f2 | 12372 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
33c8df89 | 12373 | |
b0587e4d | 12374 | intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual); |
f6d1973d | 12375 | |
656d1b89 L |
12376 | /* |
12377 | * SKL workaround: bspec recommends we disable the SAGV when we | |
12378 | * have more then one pipe enabled | |
12379 | */ | |
56feca91 | 12380 | if (!intel_can_enable_sagv(state)) |
16dcdc4e | 12381 | intel_disable_sagv(dev_priv); |
656d1b89 | 12382 | |
677100ce | 12383 | intel_modeset_verify_disabled(dev, state); |
4740b0f2 | 12384 | } |
47fab737 | 12385 | |
896e5bb0 | 12386 | /* Complete the events for pipes that have now been disabled */ |
aa5e9b47 ML |
12387 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
12388 | bool modeset = needs_modeset(new_crtc_state); | |
80715b2f | 12389 | |
1f7528c4 | 12390 | /* Complete events for now disable pipes here. */ |
aa5e9b47 | 12391 | if (modeset && !new_crtc_state->active && new_crtc_state->event) { |
1f7528c4 | 12392 | spin_lock_irq(&dev->event_lock); |
aa5e9b47 | 12393 | drm_crtc_send_vblank_event(crtc, new_crtc_state->event); |
1f7528c4 DV |
12394 | spin_unlock_irq(&dev->event_lock); |
12395 | ||
aa5e9b47 | 12396 | new_crtc_state->event = NULL; |
1f7528c4 | 12397 | } |
177246a8 MR |
12398 | } |
12399 | ||
896e5bb0 L |
12400 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
12401 | dev_priv->display.update_crtcs(state, &crtc_vblank_mask); | |
12402 | ||
94f05024 DV |
12403 | /* FIXME: We should call drm_atomic_helper_commit_hw_done() here |
12404 | * already, but still need the state for the delayed optimization. To | |
12405 | * fix this: | |
12406 | * - wrap the optimization/post_plane_update stuff into a per-crtc work. | |
12407 | * - schedule that vblank worker _before_ calling hw_done | |
12408 | * - at the start of commit_tail, cancel it _synchrously | |
12409 | * - switch over to the vblank wait helper in the core after that since | |
12410 | * we don't need out special handling any more. | |
12411 | */ | |
5a21b665 DV |
12412 | if (!state->legacy_cursor_update) |
12413 | intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); | |
12414 | ||
12415 | /* | |
12416 | * Now that the vblank has passed, we can go ahead and program the | |
12417 | * optimal watermarks on platforms that need two-step watermark | |
12418 | * programming. | |
12419 | * | |
12420 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
12421 | */ | |
aa5e9b47 ML |
12422 | for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { |
12423 | intel_cstate = to_intel_crtc_state(new_crtc_state); | |
5a21b665 DV |
12424 | |
12425 | if (dev_priv->display.optimize_watermarks) | |
ccf010fb ML |
12426 | dev_priv->display.optimize_watermarks(intel_state, |
12427 | intel_cstate); | |
5a21b665 DV |
12428 | } |
12429 | ||
aa5e9b47 | 12430 | for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { |
5a21b665 DV |
12431 | intel_post_plane_update(to_intel_crtc_state(old_crtc_state)); |
12432 | ||
12433 | if (put_domains[i]) | |
12434 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
12435 | ||
aa5e9b47 | 12436 | intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state); |
5a21b665 DV |
12437 | } |
12438 | ||
56feca91 | 12439 | if (intel_state->modeset && intel_can_enable_sagv(state)) |
16dcdc4e | 12440 | intel_enable_sagv(dev_priv); |
656d1b89 | 12441 | |
94f05024 DV |
12442 | drm_atomic_helper_commit_hw_done(state); |
12443 | ||
d5553c09 CW |
12444 | if (intel_state->modeset) { |
12445 | /* As one of the primary mmio accessors, KMS has a high | |
12446 | * likelihood of triggering bugs in unclaimed access. After we | |
12447 | * finish modesetting, see if an error has been flagged, and if | |
12448 | * so enable debugging for the next modeset - and hope we catch | |
12449 | * the culprit. | |
12450 | */ | |
12451 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
5a21b665 | 12452 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); |
d5553c09 | 12453 | } |
5a21b665 | 12454 | |
5a21b665 | 12455 | drm_atomic_helper_cleanup_planes(dev, state); |
5a21b665 | 12456 | |
ea0000f0 DV |
12457 | drm_atomic_helper_commit_cleanup_done(state); |
12458 | ||
0853695c | 12459 | drm_atomic_state_put(state); |
f30da187 | 12460 | |
ba318c61 | 12461 | intel_atomic_helper_free_state(dev_priv); |
94f05024 DV |
12462 | } |
12463 | ||
12464 | static void intel_atomic_commit_work(struct work_struct *work) | |
12465 | { | |
c004a90b CW |
12466 | struct drm_atomic_state *state = |
12467 | container_of(work, struct drm_atomic_state, commit_work); | |
12468 | ||
94f05024 DV |
12469 | intel_atomic_commit_tail(state); |
12470 | } | |
12471 | ||
c004a90b CW |
12472 | static int __i915_sw_fence_call |
12473 | intel_atomic_commit_ready(struct i915_sw_fence *fence, | |
12474 | enum i915_sw_fence_notify notify) | |
12475 | { | |
12476 | struct intel_atomic_state *state = | |
12477 | container_of(fence, struct intel_atomic_state, commit_ready); | |
12478 | ||
12479 | switch (notify) { | |
12480 | case FENCE_COMPLETE: | |
42b062b0 | 12481 | /* we do blocking waits in the worker, nothing to do here */ |
c004a90b | 12482 | break; |
c004a90b | 12483 | case FENCE_FREE: |
eb955eee CW |
12484 | { |
12485 | struct intel_atomic_helper *helper = | |
12486 | &to_i915(state->base.dev)->atomic_helper; | |
12487 | ||
12488 | if (llist_add(&state->freed, &helper->free_list)) | |
12489 | schedule_work(&helper->free_work); | |
12490 | break; | |
12491 | } | |
c004a90b CW |
12492 | } |
12493 | ||
12494 | return NOTIFY_DONE; | |
12495 | } | |
12496 | ||
6c9c1b38 DV |
12497 | static void intel_atomic_track_fbs(struct drm_atomic_state *state) |
12498 | { | |
aa5e9b47 | 12499 | struct drm_plane_state *old_plane_state, *new_plane_state; |
6c9c1b38 | 12500 | struct drm_plane *plane; |
6c9c1b38 DV |
12501 | int i; |
12502 | ||
aa5e9b47 | 12503 | for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i) |
faf5bf0a | 12504 | i915_gem_track_fb(intel_fb_obj(old_plane_state->fb), |
aa5e9b47 | 12505 | intel_fb_obj(new_plane_state->fb), |
faf5bf0a | 12506 | to_intel_plane(plane)->frontbuffer_bit); |
6c9c1b38 DV |
12507 | } |
12508 | ||
94f05024 DV |
12509 | /** |
12510 | * intel_atomic_commit - commit validated state object | |
12511 | * @dev: DRM device | |
12512 | * @state: the top-level driver state object | |
12513 | * @nonblock: nonblocking commit | |
12514 | * | |
12515 | * This function commits a top-level state object that has been validated | |
12516 | * with drm_atomic_helper_check(). | |
12517 | * | |
94f05024 DV |
12518 | * RETURNS |
12519 | * Zero for success or -errno. | |
12520 | */ | |
12521 | static int intel_atomic_commit(struct drm_device *dev, | |
12522 | struct drm_atomic_state *state, | |
12523 | bool nonblock) | |
12524 | { | |
12525 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
fac5e23e | 12526 | struct drm_i915_private *dev_priv = to_i915(dev); |
94f05024 DV |
12527 | int ret = 0; |
12528 | ||
94f05024 DV |
12529 | ret = drm_atomic_helper_setup_commit(state, nonblock); |
12530 | if (ret) | |
12531 | return ret; | |
12532 | ||
c004a90b CW |
12533 | drm_atomic_state_get(state); |
12534 | i915_sw_fence_init(&intel_state->commit_ready, | |
12535 | intel_atomic_commit_ready); | |
94f05024 | 12536 | |
d07f0e59 | 12537 | ret = intel_atomic_prepare_commit(dev, state); |
94f05024 DV |
12538 | if (ret) { |
12539 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
c004a90b | 12540 | i915_sw_fence_commit(&intel_state->commit_ready); |
94f05024 DV |
12541 | return ret; |
12542 | } | |
12543 | ||
440df938 VS |
12544 | /* |
12545 | * The intel_legacy_cursor_update() fast path takes care | |
12546 | * of avoiding the vblank waits for simple cursor | |
12547 | * movement and flips. For cursor on/off and size changes, | |
12548 | * we want to perform the vblank waits so that watermark | |
12549 | * updates happen during the correct frames. Gen9+ have | |
12550 | * double buffered watermarks and so shouldn't need this. | |
12551 | * | |
12552 | * Do this after drm_atomic_helper_setup_commit() and | |
12553 | * intel_atomic_prepare_commit() because we still want | |
12554 | * to skip the flip and fb cleanup waits. Although that | |
12555 | * does risk yanking the mapping from under the display | |
12556 | * engine. | |
12557 | * | |
12558 | * FIXME doing watermarks and fb cleanup from a vblank worker | |
12559 | * (assuming we had any) would solve these problems. | |
12560 | */ | |
12561 | if (INTEL_GEN(dev_priv) < 9) | |
12562 | state->legacy_cursor_update = false; | |
12563 | ||
0806f4ee ML |
12564 | ret = drm_atomic_helper_swap_state(state, true); |
12565 | if (ret) { | |
12566 | i915_sw_fence_commit(&intel_state->commit_ready); | |
12567 | ||
0806f4ee | 12568 | drm_atomic_helper_cleanup_planes(dev, state); |
0806f4ee ML |
12569 | return ret; |
12570 | } | |
94f05024 | 12571 | dev_priv->wm.distrust_bios_wm = false; |
3c0fb588 | 12572 | intel_shared_dpll_swap_state(state); |
6c9c1b38 | 12573 | intel_atomic_track_fbs(state); |
94f05024 | 12574 | |
c3b32658 ML |
12575 | if (intel_state->modeset) { |
12576 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
12577 | sizeof(intel_state->min_pixclk)); | |
12578 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
bb0f4aab VS |
12579 | dev_priv->cdclk.logical = intel_state->cdclk.logical; |
12580 | dev_priv->cdclk.actual = intel_state->cdclk.actual; | |
c3b32658 ML |
12581 | } |
12582 | ||
0853695c | 12583 | drm_atomic_state_get(state); |
42b062b0 | 12584 | INIT_WORK(&state->commit_work, intel_atomic_commit_work); |
c004a90b CW |
12585 | |
12586 | i915_sw_fence_commit(&intel_state->commit_ready); | |
42b062b0 DV |
12587 | if (nonblock) |
12588 | queue_work(system_unbound_wq, &state->commit_work); | |
12589 | else | |
94f05024 | 12590 | intel_atomic_commit_tail(state); |
42b062b0 | 12591 | |
75714940 | 12592 | |
74c090b1 | 12593 | return 0; |
7f27126e JB |
12594 | } |
12595 | ||
f6e5b160 | 12596 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
3fab2f09 | 12597 | .gamma_set = drm_atomic_helper_legacy_gamma_set, |
74c090b1 | 12598 | .set_config = drm_atomic_helper_set_config, |
f6e5b160 | 12599 | .destroy = intel_crtc_destroy, |
4c01ded5 | 12600 | .page_flip = drm_atomic_helper_page_flip, |
1356837e MR |
12601 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
12602 | .atomic_destroy_state = intel_crtc_destroy_state, | |
8c6b709d | 12603 | .set_crc_source = intel_crtc_set_crc_source, |
f6e5b160 CW |
12604 | }; |
12605 | ||
6beb8c23 MR |
12606 | /** |
12607 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
12608 | * @plane: drm plane to prepare for | |
12609 | * @fb: framebuffer to prepare for presentation | |
12610 | * | |
12611 | * Prepares a framebuffer for usage on a display plane. Generally this | |
12612 | * involves pinning the underlying object and updating the frontbuffer tracking | |
12613 | * bits. Some older platforms need special physical address handling for | |
12614 | * cursor planes. | |
12615 | * | |
f935675f ML |
12616 | * Must be called with struct_mutex held. |
12617 | * | |
6beb8c23 MR |
12618 | * Returns 0 on success, negative error code on failure. |
12619 | */ | |
12620 | int | |
12621 | intel_prepare_plane_fb(struct drm_plane *plane, | |
1832040d | 12622 | struct drm_plane_state *new_state) |
465c120c | 12623 | { |
c004a90b CW |
12624 | struct intel_atomic_state *intel_state = |
12625 | to_intel_atomic_state(new_state->state); | |
b7f05d4a | 12626 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
844f9111 | 12627 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 12628 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 12629 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
c004a90b | 12630 | int ret; |
465c120c | 12631 | |
5008e874 ML |
12632 | if (old_obj) { |
12633 | struct drm_crtc_state *crtc_state = | |
c004a90b CW |
12634 | drm_atomic_get_existing_crtc_state(new_state->state, |
12635 | plane->state->crtc); | |
5008e874 ML |
12636 | |
12637 | /* Big Hammer, we also need to ensure that any pending | |
12638 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
12639 | * current scanout is retired before unpinning the old | |
12640 | * framebuffer. Note that we rely on userspace rendering | |
12641 | * into the buffer attached to the pipe they are waiting | |
12642 | * on. If not, userspace generates a GPU hang with IPEHR | |
12643 | * point to the MI_WAIT_FOR_EVENT. | |
12644 | * | |
12645 | * This should only fail upon a hung GPU, in which case we | |
12646 | * can safely continue. | |
12647 | */ | |
c004a90b CW |
12648 | if (needs_modeset(crtc_state)) { |
12649 | ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, | |
12650 | old_obj->resv, NULL, | |
12651 | false, 0, | |
12652 | GFP_KERNEL); | |
12653 | if (ret < 0) | |
12654 | return ret; | |
f4457ae7 | 12655 | } |
5008e874 ML |
12656 | } |
12657 | ||
c004a90b CW |
12658 | if (new_state->fence) { /* explicit fencing */ |
12659 | ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready, | |
12660 | new_state->fence, | |
12661 | I915_FENCE_TIMEOUT, | |
12662 | GFP_KERNEL); | |
12663 | if (ret < 0) | |
12664 | return ret; | |
12665 | } | |
12666 | ||
c37efb99 CW |
12667 | if (!obj) |
12668 | return 0; | |
12669 | ||
4d3088c7 | 12670 | ret = i915_gem_object_pin_pages(obj); |
fd70075f CW |
12671 | if (ret) |
12672 | return ret; | |
12673 | ||
4d3088c7 CW |
12674 | ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex); |
12675 | if (ret) { | |
12676 | i915_gem_object_unpin_pages(obj); | |
12677 | return ret; | |
12678 | } | |
12679 | ||
fd70075f CW |
12680 | if (plane->type == DRM_PLANE_TYPE_CURSOR && |
12681 | INTEL_INFO(dev_priv)->cursor_needs_physical) { | |
12682 | const int align = intel_cursor_alignment(dev_priv); | |
12683 | ||
12684 | ret = i915_gem_object_attach_phys(obj, align); | |
12685 | } else { | |
12686 | struct i915_vma *vma; | |
12687 | ||
12688 | vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation); | |
12689 | if (!IS_ERR(vma)) | |
12690 | to_intel_plane_state(new_state)->vma = vma; | |
12691 | else | |
12692 | ret = PTR_ERR(vma); | |
12693 | } | |
12694 | ||
12695 | i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); | |
12696 | ||
12697 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
4d3088c7 | 12698 | i915_gem_object_unpin_pages(obj); |
fd70075f CW |
12699 | if (ret) |
12700 | return ret; | |
12701 | ||
c004a90b CW |
12702 | if (!new_state->fence) { /* implicit fencing */ |
12703 | ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, | |
12704 | obj->resv, NULL, | |
12705 | false, I915_FENCE_TIMEOUT, | |
12706 | GFP_KERNEL); | |
12707 | if (ret < 0) | |
12708 | return ret; | |
12709 | } | |
5a21b665 | 12710 | |
d07f0e59 | 12711 | return 0; |
6beb8c23 MR |
12712 | } |
12713 | ||
38f3ce3a MR |
12714 | /** |
12715 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
12716 | * @plane: drm plane to clean up for | |
12717 | * @fb: old framebuffer that was on plane | |
12718 | * | |
12719 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
12720 | * |
12721 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
12722 | */ |
12723 | void | |
12724 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
1832040d | 12725 | struct drm_plane_state *old_state) |
38f3ce3a | 12726 | { |
be1e3415 | 12727 | struct i915_vma *vma; |
38f3ce3a | 12728 | |
be1e3415 CW |
12729 | /* Should only be called after a successful intel_prepare_plane_fb()! */ |
12730 | vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma); | |
fd70075f CW |
12731 | if (vma) { |
12732 | mutex_lock(&plane->dev->struct_mutex); | |
be1e3415 | 12733 | intel_unpin_fb_vma(vma); |
fd70075f CW |
12734 | mutex_unlock(&plane->dev->struct_mutex); |
12735 | } | |
465c120c MR |
12736 | } |
12737 | ||
6156a456 CK |
12738 | int |
12739 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
12740 | { | |
5b7280f0 | 12741 | struct drm_i915_private *dev_priv; |
6156a456 | 12742 | int max_scale; |
5b7280f0 | 12743 | int crtc_clock, max_dotclk; |
6156a456 | 12744 | |
bf8a0af0 | 12745 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
12746 | return DRM_PLANE_HELPER_NO_SCALING; |
12747 | ||
5b7280f0 ACO |
12748 | dev_priv = to_i915(intel_crtc->base.dev); |
12749 | ||
6156a456 | 12750 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; |
5b7280f0 ACO |
12751 | max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk; |
12752 | ||
12753 | if (IS_GEMINILAKE(dev_priv)) | |
12754 | max_dotclk *= 2; | |
6156a456 | 12755 | |
5b7280f0 | 12756 | if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock)) |
6156a456 CK |
12757 | return DRM_PLANE_HELPER_NO_SCALING; |
12758 | ||
12759 | /* | |
12760 | * skl max scale is lower of: | |
12761 | * close to 3 but not 3, -1 is for that purpose | |
12762 | * or | |
12763 | * cdclk/crtc_clock | |
12764 | */ | |
5b7280f0 ACO |
12765 | max_scale = min((1 << 16) * 3 - 1, |
12766 | (1 << 8) * ((max_dotclk << 8) / crtc_clock)); | |
6156a456 CK |
12767 | |
12768 | return max_scale; | |
12769 | } | |
12770 | ||
465c120c | 12771 | static int |
282dbf9b | 12772 | intel_check_primary_plane(struct intel_plane *plane, |
061e4b8d | 12773 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
12774 | struct intel_plane_state *state) |
12775 | { | |
282dbf9b | 12776 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
2b875c22 | 12777 | struct drm_crtc *crtc = state->base.crtc; |
6156a456 | 12778 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
12779 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
12780 | bool can_position = false; | |
b63a16f6 | 12781 | int ret; |
465c120c | 12782 | |
b63a16f6 | 12783 | if (INTEL_GEN(dev_priv) >= 9) { |
693bdc28 VS |
12784 | /* use scaler when colorkey is not required */ |
12785 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
12786 | min_scale = 1; | |
12787 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
12788 | } | |
d8106366 | 12789 | can_position = true; |
6156a456 | 12790 | } |
d8106366 | 12791 | |
cc926387 DV |
12792 | ret = drm_plane_helper_check_state(&state->base, |
12793 | &state->clip, | |
12794 | min_scale, max_scale, | |
12795 | can_position, true); | |
b63a16f6 VS |
12796 | if (ret) |
12797 | return ret; | |
12798 | ||
cc926387 | 12799 | if (!state->base.fb) |
b63a16f6 VS |
12800 | return 0; |
12801 | ||
12802 | if (INTEL_GEN(dev_priv) >= 9) { | |
12803 | ret = skl_check_plane_surface(state); | |
12804 | if (ret) | |
12805 | return ret; | |
a0864d59 VS |
12806 | |
12807 | state->ctl = skl_plane_ctl(crtc_state, state); | |
12808 | } else { | |
5b7fcc44 VS |
12809 | ret = i9xx_check_plane_surface(state); |
12810 | if (ret) | |
12811 | return ret; | |
12812 | ||
a0864d59 | 12813 | state->ctl = i9xx_plane_ctl(crtc_state, state); |
b63a16f6 VS |
12814 | } |
12815 | ||
12816 | return 0; | |
14af293f GP |
12817 | } |
12818 | ||
5a21b665 DV |
12819 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
12820 | struct drm_crtc_state *old_crtc_state) | |
12821 | { | |
12822 | struct drm_device *dev = crtc->dev; | |
62e0fb88 | 12823 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 12824 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b707aa50 L |
12825 | struct intel_crtc_state *intel_cstate = |
12826 | to_intel_crtc_state(crtc->state); | |
ccf010fb | 12827 | struct intel_crtc_state *old_intel_cstate = |
5a21b665 | 12828 | to_intel_crtc_state(old_crtc_state); |
ccf010fb ML |
12829 | struct intel_atomic_state *old_intel_state = |
12830 | to_intel_atomic_state(old_crtc_state->state); | |
5a21b665 DV |
12831 | bool modeset = needs_modeset(crtc->state); |
12832 | ||
567f0792 ML |
12833 | if (!modeset && |
12834 | (intel_cstate->base.color_mgmt_changed || | |
12835 | intel_cstate->update_pipe)) { | |
12836 | intel_color_set_csc(crtc->state); | |
12837 | intel_color_load_luts(crtc->state); | |
12838 | } | |
12839 | ||
5a21b665 DV |
12840 | /* Perform vblank evasion around commit operation */ |
12841 | intel_pipe_update_start(intel_crtc); | |
12842 | ||
12843 | if (modeset) | |
e62929b3 | 12844 | goto out; |
5a21b665 | 12845 | |
ccf010fb ML |
12846 | if (intel_cstate->update_pipe) |
12847 | intel_update_pipe_config(intel_crtc, old_intel_cstate); | |
12848 | else if (INTEL_GEN(dev_priv) >= 9) | |
5a21b665 | 12849 | skl_detach_scalers(intel_crtc); |
62e0fb88 | 12850 | |
e62929b3 | 12851 | out: |
ccf010fb ML |
12852 | if (dev_priv->display.atomic_update_watermarks) |
12853 | dev_priv->display.atomic_update_watermarks(old_intel_state, | |
12854 | intel_cstate); | |
5a21b665 DV |
12855 | } |
12856 | ||
12857 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, | |
12858 | struct drm_crtc_state *old_crtc_state) | |
12859 | { | |
12860 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12861 | ||
8b5d27b9 | 12862 | intel_pipe_update_end(intel_crtc); |
5a21b665 DV |
12863 | } |
12864 | ||
cf4c7c12 | 12865 | /** |
4a3b8769 MR |
12866 | * intel_plane_destroy - destroy a plane |
12867 | * @plane: plane to destroy | |
cf4c7c12 | 12868 | * |
4a3b8769 MR |
12869 | * Common destruction function for all types of planes (primary, cursor, |
12870 | * sprite). | |
cf4c7c12 | 12871 | */ |
4a3b8769 | 12872 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c | 12873 | { |
465c120c | 12874 | drm_plane_cleanup(plane); |
69ae561f | 12875 | kfree(to_intel_plane(plane)); |
465c120c MR |
12876 | } |
12877 | ||
714244e2 BW |
12878 | static bool i8xx_mod_supported(uint32_t format, uint64_t modifier) |
12879 | { | |
12880 | switch (format) { | |
12881 | case DRM_FORMAT_C8: | |
12882 | case DRM_FORMAT_RGB565: | |
12883 | case DRM_FORMAT_XRGB1555: | |
12884 | case DRM_FORMAT_XRGB8888: | |
12885 | return modifier == DRM_FORMAT_MOD_LINEAR || | |
12886 | modifier == I915_FORMAT_MOD_X_TILED; | |
12887 | default: | |
12888 | return false; | |
12889 | } | |
12890 | } | |
12891 | ||
12892 | static bool i965_mod_supported(uint32_t format, uint64_t modifier) | |
12893 | { | |
12894 | switch (format) { | |
12895 | case DRM_FORMAT_C8: | |
12896 | case DRM_FORMAT_RGB565: | |
12897 | case DRM_FORMAT_XRGB8888: | |
12898 | case DRM_FORMAT_XBGR8888: | |
12899 | case DRM_FORMAT_XRGB2101010: | |
12900 | case DRM_FORMAT_XBGR2101010: | |
12901 | return modifier == DRM_FORMAT_MOD_LINEAR || | |
12902 | modifier == I915_FORMAT_MOD_X_TILED; | |
12903 | default: | |
12904 | return false; | |
12905 | } | |
12906 | } | |
12907 | ||
12908 | static bool skl_mod_supported(uint32_t format, uint64_t modifier) | |
12909 | { | |
12910 | switch (format) { | |
12911 | case DRM_FORMAT_XRGB8888: | |
12912 | case DRM_FORMAT_XBGR8888: | |
12913 | case DRM_FORMAT_ARGB8888: | |
12914 | case DRM_FORMAT_ABGR8888: | |
12915 | if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS || | |
12916 | modifier == I915_FORMAT_MOD_Y_TILED_CCS) | |
12917 | return true; | |
12918 | /* fall through */ | |
12919 | case DRM_FORMAT_RGB565: | |
12920 | case DRM_FORMAT_XRGB2101010: | |
12921 | case DRM_FORMAT_XBGR2101010: | |
12922 | case DRM_FORMAT_YUYV: | |
12923 | case DRM_FORMAT_YVYU: | |
12924 | case DRM_FORMAT_UYVY: | |
12925 | case DRM_FORMAT_VYUY: | |
12926 | if (modifier == I915_FORMAT_MOD_Yf_TILED) | |
12927 | return true; | |
12928 | /* fall through */ | |
12929 | case DRM_FORMAT_C8: | |
12930 | if (modifier == DRM_FORMAT_MOD_LINEAR || | |
12931 | modifier == I915_FORMAT_MOD_X_TILED || | |
12932 | modifier == I915_FORMAT_MOD_Y_TILED) | |
12933 | return true; | |
12934 | /* fall through */ | |
12935 | default: | |
12936 | return false; | |
12937 | } | |
12938 | } | |
12939 | ||
12940 | static bool intel_primary_plane_format_mod_supported(struct drm_plane *plane, | |
12941 | uint32_t format, | |
12942 | uint64_t modifier) | |
12943 | { | |
12944 | struct drm_i915_private *dev_priv = to_i915(plane->dev); | |
12945 | ||
12946 | if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID)) | |
12947 | return false; | |
12948 | ||
12949 | if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL && | |
12950 | modifier != DRM_FORMAT_MOD_LINEAR) | |
12951 | return false; | |
12952 | ||
12953 | if (INTEL_GEN(dev_priv) >= 9) | |
12954 | return skl_mod_supported(format, modifier); | |
12955 | else if (INTEL_GEN(dev_priv) >= 4) | |
12956 | return i965_mod_supported(format, modifier); | |
12957 | else | |
12958 | return i8xx_mod_supported(format, modifier); | |
12959 | ||
12960 | unreachable(); | |
12961 | } | |
12962 | ||
12963 | static bool intel_cursor_plane_format_mod_supported(struct drm_plane *plane, | |
12964 | uint32_t format, | |
12965 | uint64_t modifier) | |
12966 | { | |
12967 | if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID)) | |
12968 | return false; | |
12969 | ||
12970 | return modifier == DRM_FORMAT_MOD_LINEAR && format == DRM_FORMAT_ARGB8888; | |
12971 | } | |
12972 | ||
12973 | static struct drm_plane_funcs intel_plane_funcs = { | |
70a101f8 MR |
12974 | .update_plane = drm_atomic_helper_update_plane, |
12975 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 12976 | .destroy = intel_plane_destroy, |
a98b3431 MR |
12977 | .atomic_get_property = intel_plane_atomic_get_property, |
12978 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
12979 | .atomic_duplicate_state = intel_plane_duplicate_state, |
12980 | .atomic_destroy_state = intel_plane_destroy_state, | |
714244e2 | 12981 | .format_mod_supported = intel_primary_plane_format_mod_supported, |
465c120c MR |
12982 | }; |
12983 | ||
f79f2692 ML |
12984 | static int |
12985 | intel_legacy_cursor_update(struct drm_plane *plane, | |
12986 | struct drm_crtc *crtc, | |
12987 | struct drm_framebuffer *fb, | |
12988 | int crtc_x, int crtc_y, | |
12989 | unsigned int crtc_w, unsigned int crtc_h, | |
12990 | uint32_t src_x, uint32_t src_y, | |
34a2ab5e DV |
12991 | uint32_t src_w, uint32_t src_h, |
12992 | struct drm_modeset_acquire_ctx *ctx) | |
f79f2692 ML |
12993 | { |
12994 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
12995 | int ret; | |
12996 | struct drm_plane_state *old_plane_state, *new_plane_state; | |
12997 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
12998 | struct drm_framebuffer *old_fb; | |
12999 | struct drm_crtc_state *crtc_state = crtc->state; | |
fd70075f | 13000 | struct i915_vma *old_vma, *vma; |
f79f2692 ML |
13001 | |
13002 | /* | |
13003 | * When crtc is inactive or there is a modeset pending, | |
13004 | * wait for it to complete in the slowpath | |
13005 | */ | |
13006 | if (!crtc_state->active || needs_modeset(crtc_state) || | |
13007 | to_intel_crtc_state(crtc_state)->update_pipe) | |
13008 | goto slow; | |
13009 | ||
13010 | old_plane_state = plane->state; | |
13011 | ||
13012 | /* | |
13013 | * If any parameters change that may affect watermarks, | |
13014 | * take the slowpath. Only changing fb or position should be | |
13015 | * in the fastpath. | |
13016 | */ | |
13017 | if (old_plane_state->crtc != crtc || | |
13018 | old_plane_state->src_w != src_w || | |
13019 | old_plane_state->src_h != src_h || | |
13020 | old_plane_state->crtc_w != crtc_w || | |
13021 | old_plane_state->crtc_h != crtc_h || | |
a5509abd | 13022 | !old_plane_state->fb != !fb) |
f79f2692 ML |
13023 | goto slow; |
13024 | ||
13025 | new_plane_state = intel_plane_duplicate_state(plane); | |
13026 | if (!new_plane_state) | |
13027 | return -ENOMEM; | |
13028 | ||
13029 | drm_atomic_set_fb_for_plane(new_plane_state, fb); | |
13030 | ||
13031 | new_plane_state->src_x = src_x; | |
13032 | new_plane_state->src_y = src_y; | |
13033 | new_plane_state->src_w = src_w; | |
13034 | new_plane_state->src_h = src_h; | |
13035 | new_plane_state->crtc_x = crtc_x; | |
13036 | new_plane_state->crtc_y = crtc_y; | |
13037 | new_plane_state->crtc_w = crtc_w; | |
13038 | new_plane_state->crtc_h = crtc_h; | |
13039 | ||
13040 | ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state), | |
13041 | to_intel_plane_state(new_plane_state)); | |
13042 | if (ret) | |
13043 | goto out_free; | |
13044 | ||
f79f2692 ML |
13045 | ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex); |
13046 | if (ret) | |
13047 | goto out_free; | |
13048 | ||
13049 | if (INTEL_INFO(dev_priv)->cursor_needs_physical) { | |
fabac484 | 13050 | int align = intel_cursor_alignment(dev_priv); |
f79f2692 ML |
13051 | |
13052 | ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align); | |
13053 | if (ret) { | |
13054 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13055 | goto out_unlock; | |
13056 | } | |
13057 | } else { | |
f79f2692 ML |
13058 | vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation); |
13059 | if (IS_ERR(vma)) { | |
13060 | DRM_DEBUG_KMS("failed to pin object\n"); | |
13061 | ||
13062 | ret = PTR_ERR(vma); | |
13063 | goto out_unlock; | |
13064 | } | |
be1e3415 CW |
13065 | |
13066 | to_intel_plane_state(new_plane_state)->vma = vma; | |
f79f2692 ML |
13067 | } |
13068 | ||
13069 | old_fb = old_plane_state->fb; | |
be1e3415 | 13070 | old_vma = to_intel_plane_state(old_plane_state)->vma; |
f79f2692 ML |
13071 | |
13072 | i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb), | |
13073 | intel_plane->frontbuffer_bit); | |
13074 | ||
13075 | /* Swap plane state */ | |
13076 | new_plane_state->fence = old_plane_state->fence; | |
13077 | *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state); | |
13078 | new_plane_state->fence = NULL; | |
13079 | new_plane_state->fb = old_fb; | |
fd70075f | 13080 | to_intel_plane_state(new_plane_state)->vma = NULL; |
f79f2692 | 13081 | |
72259536 VS |
13082 | if (plane->state->visible) { |
13083 | trace_intel_update_plane(plane, to_intel_crtc(crtc)); | |
282dbf9b | 13084 | intel_plane->update_plane(intel_plane, |
a5509abd VS |
13085 | to_intel_crtc_state(crtc->state), |
13086 | to_intel_plane_state(plane->state)); | |
72259536 VS |
13087 | } else { |
13088 | trace_intel_disable_plane(plane, to_intel_crtc(crtc)); | |
282dbf9b | 13089 | intel_plane->disable_plane(intel_plane, to_intel_crtc(crtc)); |
72259536 | 13090 | } |
f79f2692 | 13091 | |
fd70075f CW |
13092 | if (old_vma) |
13093 | intel_unpin_fb_vma(old_vma); | |
f79f2692 ML |
13094 | |
13095 | out_unlock: | |
13096 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
13097 | out_free: | |
13098 | intel_plane_destroy_state(plane, new_plane_state); | |
13099 | return ret; | |
13100 | ||
f79f2692 ML |
13101 | slow: |
13102 | return drm_atomic_helper_update_plane(plane, crtc, fb, | |
13103 | crtc_x, crtc_y, crtc_w, crtc_h, | |
34a2ab5e | 13104 | src_x, src_y, src_w, src_h, ctx); |
f79f2692 ML |
13105 | } |
13106 | ||
13107 | static const struct drm_plane_funcs intel_cursor_plane_funcs = { | |
13108 | .update_plane = intel_legacy_cursor_update, | |
13109 | .disable_plane = drm_atomic_helper_disable_plane, | |
13110 | .destroy = intel_plane_destroy, | |
f79f2692 ML |
13111 | .atomic_get_property = intel_plane_atomic_get_property, |
13112 | .atomic_set_property = intel_plane_atomic_set_property, | |
13113 | .atomic_duplicate_state = intel_plane_duplicate_state, | |
13114 | .atomic_destroy_state = intel_plane_destroy_state, | |
714244e2 | 13115 | .format_mod_supported = intel_cursor_plane_format_mod_supported, |
f79f2692 ML |
13116 | }; |
13117 | ||
b079bd17 | 13118 | static struct intel_plane * |
580503c7 | 13119 | intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) |
465c120c | 13120 | { |
fca0ce2a VS |
13121 | struct intel_plane *primary = NULL; |
13122 | struct intel_plane_state *state = NULL; | |
465c120c | 13123 | const uint32_t *intel_primary_formats; |
93ca7e00 | 13124 | unsigned int supported_rotations; |
45e3743a | 13125 | unsigned int num_formats; |
714244e2 | 13126 | const uint64_t *modifiers; |
fca0ce2a | 13127 | int ret; |
465c120c MR |
13128 | |
13129 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
b079bd17 VS |
13130 | if (!primary) { |
13131 | ret = -ENOMEM; | |
fca0ce2a | 13132 | goto fail; |
b079bd17 | 13133 | } |
465c120c | 13134 | |
8e7d688b | 13135 | state = intel_create_plane_state(&primary->base); |
b079bd17 VS |
13136 | if (!state) { |
13137 | ret = -ENOMEM; | |
fca0ce2a | 13138 | goto fail; |
b079bd17 VS |
13139 | } |
13140 | ||
8e7d688b | 13141 | primary->base.state = &state->base; |
ea2c67bb | 13142 | |
465c120c MR |
13143 | primary->can_scale = false; |
13144 | primary->max_downscale = 1; | |
580503c7 | 13145 | if (INTEL_GEN(dev_priv) >= 9) { |
6156a456 | 13146 | primary->can_scale = true; |
af99ceda | 13147 | state->scaler_id = -1; |
6156a456 | 13148 | } |
465c120c | 13149 | primary->pipe = pipe; |
e3c566df VS |
13150 | /* |
13151 | * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS | |
13152 | * port is hooked to pipe B. Hence we want plane A feeding pipe B. | |
13153 | */ | |
13154 | if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4) | |
13155 | primary->plane = (enum plane) !pipe; | |
13156 | else | |
13157 | primary->plane = (enum plane) pipe; | |
b14e5848 | 13158 | primary->id = PLANE_PRIMARY; |
a9ff8714 | 13159 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 13160 | primary->check_plane = intel_check_primary_plane; |
465c120c | 13161 | |
714244e2 | 13162 | if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { |
6c0fd451 DL |
13163 | intel_primary_formats = skl_primary_formats; |
13164 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
714244e2 BW |
13165 | modifiers = skl_format_modifiers_ccs; |
13166 | ||
13167 | primary->update_plane = skylake_update_primary_plane; | |
13168 | primary->disable_plane = skylake_disable_primary_plane; | |
13169 | } else if (INTEL_GEN(dev_priv) >= 9) { | |
13170 | intel_primary_formats = skl_primary_formats; | |
13171 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
13172 | if (pipe < PIPE_C) | |
13173 | modifiers = skl_format_modifiers_ccs; | |
13174 | else | |
13175 | modifiers = skl_format_modifiers_noccs; | |
a8d201af ML |
13176 | |
13177 | primary->update_plane = skylake_update_primary_plane; | |
13178 | primary->disable_plane = skylake_disable_primary_plane; | |
580503c7 | 13179 | } else if (INTEL_GEN(dev_priv) >= 4) { |
568db4f2 DL |
13180 | intel_primary_formats = i965_primary_formats; |
13181 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
714244e2 | 13182 | modifiers = i9xx_format_modifiers; |
a8d201af ML |
13183 | |
13184 | primary->update_plane = i9xx_update_primary_plane; | |
13185 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
13186 | } else { |
13187 | intel_primary_formats = i8xx_primary_formats; | |
13188 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
714244e2 | 13189 | modifiers = i9xx_format_modifiers; |
a8d201af ML |
13190 | |
13191 | primary->update_plane = i9xx_update_primary_plane; | |
13192 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
13193 | } |
13194 | ||
580503c7 VS |
13195 | if (INTEL_GEN(dev_priv) >= 9) |
13196 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, | |
13197 | 0, &intel_plane_funcs, | |
38573dc1 | 13198 | intel_primary_formats, num_formats, |
714244e2 | 13199 | modifiers, |
38573dc1 VS |
13200 | DRM_PLANE_TYPE_PRIMARY, |
13201 | "plane 1%c", pipe_name(pipe)); | |
9beb5fea | 13202 | else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
580503c7 VS |
13203 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, |
13204 | 0, &intel_plane_funcs, | |
38573dc1 | 13205 | intel_primary_formats, num_formats, |
714244e2 | 13206 | modifiers, |
38573dc1 VS |
13207 | DRM_PLANE_TYPE_PRIMARY, |
13208 | "primary %c", pipe_name(pipe)); | |
13209 | else | |
580503c7 VS |
13210 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, |
13211 | 0, &intel_plane_funcs, | |
38573dc1 | 13212 | intel_primary_formats, num_formats, |
714244e2 | 13213 | modifiers, |
38573dc1 VS |
13214 | DRM_PLANE_TYPE_PRIMARY, |
13215 | "plane %c", plane_name(primary->plane)); | |
fca0ce2a VS |
13216 | if (ret) |
13217 | goto fail; | |
48404c1e | 13218 | |
5481e27f | 13219 | if (INTEL_GEN(dev_priv) >= 9) { |
93ca7e00 | 13220 | supported_rotations = |
c2c446ad RF |
13221 | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 | |
13222 | DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270; | |
4ea7be2b VS |
13223 | } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { |
13224 | supported_rotations = | |
c2c446ad RF |
13225 | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 | |
13226 | DRM_MODE_REFLECT_X; | |
5481e27f | 13227 | } else if (INTEL_GEN(dev_priv) >= 4) { |
93ca7e00 | 13228 | supported_rotations = |
c2c446ad | 13229 | DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180; |
93ca7e00 | 13230 | } else { |
c2c446ad | 13231 | supported_rotations = DRM_MODE_ROTATE_0; |
93ca7e00 VS |
13232 | } |
13233 | ||
5481e27f | 13234 | if (INTEL_GEN(dev_priv) >= 4) |
93ca7e00 | 13235 | drm_plane_create_rotation_property(&primary->base, |
c2c446ad | 13236 | DRM_MODE_ROTATE_0, |
93ca7e00 | 13237 | supported_rotations); |
48404c1e | 13238 | |
ea2c67bb MR |
13239 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
13240 | ||
b079bd17 | 13241 | return primary; |
fca0ce2a VS |
13242 | |
13243 | fail: | |
13244 | kfree(state); | |
13245 | kfree(primary); | |
13246 | ||
b079bd17 | 13247 | return ERR_PTR(ret); |
465c120c MR |
13248 | } |
13249 | ||
b079bd17 | 13250 | static struct intel_plane * |
b2d03b0d VS |
13251 | intel_cursor_plane_create(struct drm_i915_private *dev_priv, |
13252 | enum pipe pipe) | |
3d7d6510 | 13253 | { |
fca0ce2a VS |
13254 | struct intel_plane *cursor = NULL; |
13255 | struct intel_plane_state *state = NULL; | |
13256 | int ret; | |
3d7d6510 MR |
13257 | |
13258 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
b079bd17 VS |
13259 | if (!cursor) { |
13260 | ret = -ENOMEM; | |
fca0ce2a | 13261 | goto fail; |
b079bd17 | 13262 | } |
3d7d6510 | 13263 | |
8e7d688b | 13264 | state = intel_create_plane_state(&cursor->base); |
b079bd17 VS |
13265 | if (!state) { |
13266 | ret = -ENOMEM; | |
fca0ce2a | 13267 | goto fail; |
b079bd17 VS |
13268 | } |
13269 | ||
8e7d688b | 13270 | cursor->base.state = &state->base; |
ea2c67bb | 13271 | |
3d7d6510 MR |
13272 | cursor->can_scale = false; |
13273 | cursor->max_downscale = 1; | |
13274 | cursor->pipe = pipe; | |
13275 | cursor->plane = pipe; | |
b14e5848 | 13276 | cursor->id = PLANE_CURSOR; |
a9ff8714 | 13277 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
b2d03b0d VS |
13278 | |
13279 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { | |
13280 | cursor->update_plane = i845_update_cursor; | |
13281 | cursor->disable_plane = i845_disable_cursor; | |
659056f2 | 13282 | cursor->check_plane = i845_check_cursor; |
b2d03b0d VS |
13283 | } else { |
13284 | cursor->update_plane = i9xx_update_cursor; | |
13285 | cursor->disable_plane = i9xx_disable_cursor; | |
659056f2 | 13286 | cursor->check_plane = i9xx_check_cursor; |
b2d03b0d | 13287 | } |
3d7d6510 | 13288 | |
cd5dcbf1 VS |
13289 | cursor->cursor.base = ~0; |
13290 | cursor->cursor.cntl = ~0; | |
024faac7 VS |
13291 | |
13292 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv)) | |
13293 | cursor->cursor.size = ~0; | |
3d7d6510 | 13294 | |
580503c7 | 13295 | ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, |
f79f2692 | 13296 | 0, &intel_cursor_plane_funcs, |
fca0ce2a VS |
13297 | intel_cursor_formats, |
13298 | ARRAY_SIZE(intel_cursor_formats), | |
714244e2 BW |
13299 | cursor_format_modifiers, |
13300 | DRM_PLANE_TYPE_CURSOR, | |
38573dc1 | 13301 | "cursor %c", pipe_name(pipe)); |
fca0ce2a VS |
13302 | if (ret) |
13303 | goto fail; | |
4398ad45 | 13304 | |
5481e27f | 13305 | if (INTEL_GEN(dev_priv) >= 4) |
93ca7e00 | 13306 | drm_plane_create_rotation_property(&cursor->base, |
c2c446ad RF |
13307 | DRM_MODE_ROTATE_0, |
13308 | DRM_MODE_ROTATE_0 | | |
13309 | DRM_MODE_ROTATE_180); | |
4398ad45 | 13310 | |
580503c7 | 13311 | if (INTEL_GEN(dev_priv) >= 9) |
af99ceda CK |
13312 | state->scaler_id = -1; |
13313 | ||
ea2c67bb MR |
13314 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
13315 | ||
b079bd17 | 13316 | return cursor; |
fca0ce2a VS |
13317 | |
13318 | fail: | |
13319 | kfree(state); | |
13320 | kfree(cursor); | |
13321 | ||
b079bd17 | 13322 | return ERR_PTR(ret); |
3d7d6510 MR |
13323 | } |
13324 | ||
1c74eeaf NM |
13325 | static void intel_crtc_init_scalers(struct intel_crtc *crtc, |
13326 | struct intel_crtc_state *crtc_state) | |
549e2bfb | 13327 | { |
65edccce VS |
13328 | struct intel_crtc_scaler_state *scaler_state = |
13329 | &crtc_state->scaler_state; | |
1c74eeaf | 13330 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
549e2bfb | 13331 | int i; |
549e2bfb | 13332 | |
1c74eeaf NM |
13333 | crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe]; |
13334 | if (!crtc->num_scalers) | |
13335 | return; | |
13336 | ||
65edccce VS |
13337 | for (i = 0; i < crtc->num_scalers; i++) { |
13338 | struct intel_scaler *scaler = &scaler_state->scalers[i]; | |
13339 | ||
13340 | scaler->in_use = 0; | |
13341 | scaler->mode = PS_SCALER_MODE_DYN; | |
549e2bfb CK |
13342 | } |
13343 | ||
13344 | scaler_state->scaler_id = -1; | |
13345 | } | |
13346 | ||
5ab0d85b | 13347 | static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) |
79e53945 JB |
13348 | { |
13349 | struct intel_crtc *intel_crtc; | |
f5de6e07 | 13350 | struct intel_crtc_state *crtc_state = NULL; |
b079bd17 VS |
13351 | struct intel_plane *primary = NULL; |
13352 | struct intel_plane *cursor = NULL; | |
a81d6fa0 | 13353 | int sprite, ret; |
79e53945 | 13354 | |
955382f3 | 13355 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
b079bd17 VS |
13356 | if (!intel_crtc) |
13357 | return -ENOMEM; | |
79e53945 | 13358 | |
f5de6e07 | 13359 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
b079bd17 VS |
13360 | if (!crtc_state) { |
13361 | ret = -ENOMEM; | |
f5de6e07 | 13362 | goto fail; |
b079bd17 | 13363 | } |
550acefd ACO |
13364 | intel_crtc->config = crtc_state; |
13365 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 13366 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 13367 | |
580503c7 | 13368 | primary = intel_primary_plane_create(dev_priv, pipe); |
b079bd17 VS |
13369 | if (IS_ERR(primary)) { |
13370 | ret = PTR_ERR(primary); | |
3d7d6510 | 13371 | goto fail; |
b079bd17 | 13372 | } |
d97d7b48 | 13373 | intel_crtc->plane_ids_mask |= BIT(primary->id); |
3d7d6510 | 13374 | |
a81d6fa0 | 13375 | for_each_sprite(dev_priv, pipe, sprite) { |
b079bd17 VS |
13376 | struct intel_plane *plane; |
13377 | ||
580503c7 | 13378 | plane = intel_sprite_plane_create(dev_priv, pipe, sprite); |
d2b2cbce | 13379 | if (IS_ERR(plane)) { |
b079bd17 VS |
13380 | ret = PTR_ERR(plane); |
13381 | goto fail; | |
13382 | } | |
d97d7b48 | 13383 | intel_crtc->plane_ids_mask |= BIT(plane->id); |
a81d6fa0 VS |
13384 | } |
13385 | ||
580503c7 | 13386 | cursor = intel_cursor_plane_create(dev_priv, pipe); |
d2b2cbce | 13387 | if (IS_ERR(cursor)) { |
b079bd17 | 13388 | ret = PTR_ERR(cursor); |
3d7d6510 | 13389 | goto fail; |
b079bd17 | 13390 | } |
d97d7b48 | 13391 | intel_crtc->plane_ids_mask |= BIT(cursor->id); |
3d7d6510 | 13392 | |
5ab0d85b | 13393 | ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base, |
b079bd17 VS |
13394 | &primary->base, &cursor->base, |
13395 | &intel_crtc_funcs, | |
4d5d72b7 | 13396 | "pipe %c", pipe_name(pipe)); |
3d7d6510 MR |
13397 | if (ret) |
13398 | goto fail; | |
79e53945 | 13399 | |
80824003 | 13400 | intel_crtc->pipe = pipe; |
e3c566df | 13401 | intel_crtc->plane = primary->plane; |
80824003 | 13402 | |
1c74eeaf NM |
13403 | /* initialize shared scalers */ |
13404 | intel_crtc_init_scalers(intel_crtc, crtc_state); | |
13405 | ||
22fd0fab JB |
13406 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
13407 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
e2af48c6 VS |
13408 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc; |
13409 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc; | |
22fd0fab | 13410 | |
79e53945 | 13411 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 | 13412 | |
8563b1e8 LL |
13413 | intel_color_init(&intel_crtc->base); |
13414 | ||
87b6b101 | 13415 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
b079bd17 VS |
13416 | |
13417 | return 0; | |
3d7d6510 MR |
13418 | |
13419 | fail: | |
b079bd17 VS |
13420 | /* |
13421 | * drm_mode_config_cleanup() will free up any | |
13422 | * crtcs/planes already initialized. | |
13423 | */ | |
f5de6e07 | 13424 | kfree(crtc_state); |
3d7d6510 | 13425 | kfree(intel_crtc); |
b079bd17 VS |
13426 | |
13427 | return ret; | |
79e53945 JB |
13428 | } |
13429 | ||
752aa88a JB |
13430 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
13431 | { | |
6e9f798d | 13432 | struct drm_device *dev = connector->base.dev; |
752aa88a | 13433 | |
51fd371b | 13434 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 13435 | |
51ec53da | 13436 | if (!connector->base.state->crtc) |
752aa88a JB |
13437 | return INVALID_PIPE; |
13438 | ||
51ec53da | 13439 | return to_intel_crtc(connector->base.state->crtc)->pipe; |
752aa88a JB |
13440 | } |
13441 | ||
08d7b3d1 | 13442 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 13443 | struct drm_file *file) |
08d7b3d1 | 13444 | { |
08d7b3d1 | 13445 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 13446 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 13447 | struct intel_crtc *crtc; |
08d7b3d1 | 13448 | |
7707e653 | 13449 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
71240ed2 | 13450 | if (!drmmode_crtc) |
3f2c2057 | 13451 | return -ENOENT; |
08d7b3d1 | 13452 | |
7707e653 | 13453 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 13454 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 13455 | |
c05422d5 | 13456 | return 0; |
08d7b3d1 CW |
13457 | } |
13458 | ||
66a9278e | 13459 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 13460 | { |
66a9278e DV |
13461 | struct drm_device *dev = encoder->base.dev; |
13462 | struct intel_encoder *source_encoder; | |
79e53945 | 13463 | int index_mask = 0; |
79e53945 JB |
13464 | int entry = 0; |
13465 | ||
b2784e15 | 13466 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 13467 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
13468 | index_mask |= (1 << entry); |
13469 | ||
79e53945 JB |
13470 | entry++; |
13471 | } | |
4ef69c7a | 13472 | |
79e53945 JB |
13473 | return index_mask; |
13474 | } | |
13475 | ||
646d5772 | 13476 | static bool has_edp_a(struct drm_i915_private *dev_priv) |
4d302442 | 13477 | { |
646d5772 | 13478 | if (!IS_MOBILE(dev_priv)) |
4d302442 CW |
13479 | return false; |
13480 | ||
13481 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
13482 | return false; | |
13483 | ||
5db94019 | 13484 | if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
13485 | return false; |
13486 | ||
13487 | return true; | |
13488 | } | |
13489 | ||
6315b5d3 | 13490 | static bool intel_crt_present(struct drm_i915_private *dev_priv) |
84b4e042 | 13491 | { |
6315b5d3 | 13492 | if (INTEL_GEN(dev_priv) >= 9) |
884497ed DL |
13493 | return false; |
13494 | ||
50a0bc90 | 13495 | if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) |
84b4e042 JB |
13496 | return false; |
13497 | ||
920a14b2 | 13498 | if (IS_CHERRYVIEW(dev_priv)) |
84b4e042 JB |
13499 | return false; |
13500 | ||
4f8036a2 TU |
13501 | if (HAS_PCH_LPT_H(dev_priv) && |
13502 | I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) | |
65e472e4 VS |
13503 | return false; |
13504 | ||
70ac54d0 | 13505 | /* DDI E can't be used if DDI A requires 4 lanes */ |
4f8036a2 | 13506 | if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) |
70ac54d0 VS |
13507 | return false; |
13508 | ||
e4abb733 | 13509 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
13510 | return false; |
13511 | ||
13512 | return true; | |
13513 | } | |
13514 | ||
8090ba8c ID |
13515 | void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv) |
13516 | { | |
13517 | int pps_num; | |
13518 | int pps_idx; | |
13519 | ||
13520 | if (HAS_DDI(dev_priv)) | |
13521 | return; | |
13522 | /* | |
13523 | * This w/a is needed at least on CPT/PPT, but to be sure apply it | |
13524 | * everywhere where registers can be write protected. | |
13525 | */ | |
13526 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
13527 | pps_num = 2; | |
13528 | else | |
13529 | pps_num = 1; | |
13530 | ||
13531 | for (pps_idx = 0; pps_idx < pps_num; pps_idx++) { | |
13532 | u32 val = I915_READ(PP_CONTROL(pps_idx)); | |
13533 | ||
13534 | val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS; | |
13535 | I915_WRITE(PP_CONTROL(pps_idx), val); | |
13536 | } | |
13537 | } | |
13538 | ||
44cb734c ID |
13539 | static void intel_pps_init(struct drm_i915_private *dev_priv) |
13540 | { | |
cc3f90f0 | 13541 | if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv)) |
44cb734c ID |
13542 | dev_priv->pps_mmio_base = PCH_PPS_BASE; |
13543 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
13544 | dev_priv->pps_mmio_base = VLV_PPS_BASE; | |
13545 | else | |
13546 | dev_priv->pps_mmio_base = PPS_BASE; | |
8090ba8c ID |
13547 | |
13548 | intel_pps_unlock_regs_wa(dev_priv); | |
44cb734c ID |
13549 | } |
13550 | ||
c39055b0 | 13551 | static void intel_setup_outputs(struct drm_i915_private *dev_priv) |
79e53945 | 13552 | { |
4ef69c7a | 13553 | struct intel_encoder *encoder; |
cb0953d7 | 13554 | bool dpd_is_edp = false; |
79e53945 | 13555 | |
44cb734c ID |
13556 | intel_pps_init(dev_priv); |
13557 | ||
97a824e1 ID |
13558 | /* |
13559 | * intel_edp_init_connector() depends on this completing first, to | |
13560 | * prevent the registeration of both eDP and LVDS and the incorrect | |
13561 | * sharing of the PPS. | |
13562 | */ | |
c39055b0 | 13563 | intel_lvds_init(dev_priv); |
79e53945 | 13564 | |
6315b5d3 | 13565 | if (intel_crt_present(dev_priv)) |
c39055b0 | 13566 | intel_crt_init(dev_priv); |
cb0953d7 | 13567 | |
cc3f90f0 | 13568 | if (IS_GEN9_LP(dev_priv)) { |
c776eb2e VK |
13569 | /* |
13570 | * FIXME: Broxton doesn't support port detection via the | |
13571 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
13572 | * detect the ports. | |
13573 | */ | |
c39055b0 ACO |
13574 | intel_ddi_init(dev_priv, PORT_A); |
13575 | intel_ddi_init(dev_priv, PORT_B); | |
13576 | intel_ddi_init(dev_priv, PORT_C); | |
c6c794a2 | 13577 | |
c39055b0 | 13578 | intel_dsi_init(dev_priv); |
4f8036a2 | 13579 | } else if (HAS_DDI(dev_priv)) { |
0e72a5b5 ED |
13580 | int found; |
13581 | ||
de31facd JB |
13582 | /* |
13583 | * Haswell uses DDI functions to detect digital outputs. | |
13584 | * On SKL pre-D0 the strap isn't connected, so we assume | |
13585 | * it's there. | |
13586 | */ | |
77179400 | 13587 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 13588 | /* WaIgnoreDDIAStrap: skl */ |
b976dc53 | 13589 | if (found || IS_GEN9_BC(dev_priv)) |
c39055b0 | 13590 | intel_ddi_init(dev_priv, PORT_A); |
0e72a5b5 ED |
13591 | |
13592 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
13593 | * register */ | |
13594 | found = I915_READ(SFUSE_STRAP); | |
13595 | ||
13596 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
c39055b0 | 13597 | intel_ddi_init(dev_priv, PORT_B); |
0e72a5b5 | 13598 | if (found & SFUSE_STRAP_DDIC_DETECTED) |
c39055b0 | 13599 | intel_ddi_init(dev_priv, PORT_C); |
0e72a5b5 | 13600 | if (found & SFUSE_STRAP_DDID_DETECTED) |
c39055b0 | 13601 | intel_ddi_init(dev_priv, PORT_D); |
2800e4c2 RV |
13602 | /* |
13603 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
13604 | */ | |
b976dc53 | 13605 | if (IS_GEN9_BC(dev_priv) && |
2800e4c2 RV |
13606 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
13607 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
13608 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
c39055b0 | 13609 | intel_ddi_init(dev_priv, PORT_E); |
2800e4c2 | 13610 | |
6e266956 | 13611 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
cb0953d7 | 13612 | int found; |
dd11bc10 | 13613 | dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D); |
270b3042 | 13614 | |
646d5772 | 13615 | if (has_edp_a(dev_priv)) |
c39055b0 | 13616 | intel_dp_init(dev_priv, DP_A, PORT_A); |
cb0953d7 | 13617 | |
dc0fa718 | 13618 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 13619 | /* PCH SDVOB multiplex with HDMIB */ |
c39055b0 | 13620 | found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); |
30ad48b7 | 13621 | if (!found) |
c39055b0 | 13622 | intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); |
5eb08b69 | 13623 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
c39055b0 | 13624 | intel_dp_init(dev_priv, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
13625 | } |
13626 | ||
dc0fa718 | 13627 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
c39055b0 | 13628 | intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); |
30ad48b7 | 13629 | |
dc0fa718 | 13630 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
c39055b0 | 13631 | intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D); |
30ad48b7 | 13632 | |
5eb08b69 | 13633 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
c39055b0 | 13634 | intel_dp_init(dev_priv, PCH_DP_C, PORT_C); |
5eb08b69 | 13635 | |
270b3042 | 13636 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
c39055b0 | 13637 | intel_dp_init(dev_priv, PCH_DP_D, PORT_D); |
920a14b2 | 13638 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
22f35042 | 13639 | bool has_edp, has_port; |
457c52d8 | 13640 | |
e17ac6db VS |
13641 | /* |
13642 | * The DP_DETECTED bit is the latched state of the DDC | |
13643 | * SDA pin at boot. However since eDP doesn't require DDC | |
13644 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
13645 | * eDP ports may have been muxed to an alternate function. | |
13646 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
13647 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
13648 | * detect eDP ports. | |
22f35042 VS |
13649 | * |
13650 | * Sadly the straps seem to be missing sometimes even for HDMI | |
13651 | * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap | |
13652 | * and VBT for the presence of the port. Additionally we can't | |
13653 | * trust the port type the VBT declares as we've seen at least | |
13654 | * HDMI ports that the VBT claim are DP or eDP. | |
e17ac6db | 13655 | */ |
dd11bc10 | 13656 | has_edp = intel_dp_is_edp(dev_priv, PORT_B); |
22f35042 VS |
13657 | has_port = intel_bios_is_port_present(dev_priv, PORT_B); |
13658 | if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port) | |
c39055b0 | 13659 | has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B); |
22f35042 | 13660 | if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) |
c39055b0 | 13661 | intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); |
585a94b8 | 13662 | |
dd11bc10 | 13663 | has_edp = intel_dp_is_edp(dev_priv, PORT_C); |
22f35042 VS |
13664 | has_port = intel_bios_is_port_present(dev_priv, PORT_C); |
13665 | if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port) | |
c39055b0 | 13666 | has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C); |
22f35042 | 13667 | if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) |
c39055b0 | 13668 | intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); |
19c03924 | 13669 | |
920a14b2 | 13670 | if (IS_CHERRYVIEW(dev_priv)) { |
22f35042 VS |
13671 | /* |
13672 | * eDP not supported on port D, | |
13673 | * so no need to worry about it | |
13674 | */ | |
13675 | has_port = intel_bios_is_port_present(dev_priv, PORT_D); | |
13676 | if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port) | |
c39055b0 | 13677 | intel_dp_init(dev_priv, CHV_DP_D, PORT_D); |
22f35042 | 13678 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port) |
c39055b0 | 13679 | intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D); |
9418c1f1 VS |
13680 | } |
13681 | ||
c39055b0 | 13682 | intel_dsi_init(dev_priv); |
5db94019 | 13683 | } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) { |
27185ae1 | 13684 | bool found = false; |
7d57382e | 13685 | |
e2debe91 | 13686 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 13687 | DRM_DEBUG_KMS("probing SDVOB\n"); |
c39055b0 | 13688 | found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); |
9beb5fea | 13689 | if (!found && IS_G4X(dev_priv)) { |
b01f2c3a | 13690 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
c39055b0 | 13691 | intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); |
b01f2c3a | 13692 | } |
27185ae1 | 13693 | |
9beb5fea | 13694 | if (!found && IS_G4X(dev_priv)) |
c39055b0 | 13695 | intel_dp_init(dev_priv, DP_B, PORT_B); |
725e30ad | 13696 | } |
13520b05 KH |
13697 | |
13698 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 13699 | |
e2debe91 | 13700 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 13701 | DRM_DEBUG_KMS("probing SDVOC\n"); |
c39055b0 | 13702 | found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); |
b01f2c3a | 13703 | } |
27185ae1 | 13704 | |
e2debe91 | 13705 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 13706 | |
9beb5fea | 13707 | if (IS_G4X(dev_priv)) { |
b01f2c3a | 13708 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
c39055b0 | 13709 | intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); |
b01f2c3a | 13710 | } |
9beb5fea | 13711 | if (IS_G4X(dev_priv)) |
c39055b0 | 13712 | intel_dp_init(dev_priv, DP_C, PORT_C); |
725e30ad | 13713 | } |
27185ae1 | 13714 | |
9beb5fea | 13715 | if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED)) |
c39055b0 | 13716 | intel_dp_init(dev_priv, DP_D, PORT_D); |
5db94019 | 13717 | } else if (IS_GEN2(dev_priv)) |
c39055b0 | 13718 | intel_dvo_init(dev_priv); |
79e53945 | 13719 | |
56b857a5 | 13720 | if (SUPPORTS_TV(dev_priv)) |
c39055b0 | 13721 | intel_tv_init(dev_priv); |
79e53945 | 13722 | |
c39055b0 | 13723 | intel_psr_init(dev_priv); |
7c8f8a70 | 13724 | |
c39055b0 | 13725 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
4ef69c7a CW |
13726 | encoder->base.possible_crtcs = encoder->crtc_mask; |
13727 | encoder->base.possible_clones = | |
66a9278e | 13728 | intel_encoder_clones(encoder); |
79e53945 | 13729 | } |
47356eb6 | 13730 | |
c39055b0 | 13731 | intel_init_pch_refclk(dev_priv); |
270b3042 | 13732 | |
c39055b0 | 13733 | drm_helper_move_panel_connectors_to_head(&dev_priv->drm); |
79e53945 JB |
13734 | } |
13735 | ||
13736 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
13737 | { | |
13738 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 | 13739 | |
ef2d633e | 13740 | drm_framebuffer_cleanup(fb); |
70001cd2 | 13741 | |
dd689287 CW |
13742 | i915_gem_object_lock(intel_fb->obj); |
13743 | WARN_ON(!intel_fb->obj->framebuffer_references--); | |
13744 | i915_gem_object_unlock(intel_fb->obj); | |
13745 | ||
f8c417cd | 13746 | i915_gem_object_put(intel_fb->obj); |
70001cd2 | 13747 | |
79e53945 JB |
13748 | kfree(intel_fb); |
13749 | } | |
13750 | ||
13751 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 13752 | struct drm_file *file, |
79e53945 JB |
13753 | unsigned int *handle) |
13754 | { | |
13755 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 13756 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 13757 | |
cc917ab4 CW |
13758 | if (obj->userptr.mm) { |
13759 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
13760 | return -EINVAL; | |
13761 | } | |
13762 | ||
05394f39 | 13763 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
13764 | } |
13765 | ||
86c98588 RV |
13766 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
13767 | struct drm_file *file, | |
13768 | unsigned flags, unsigned color, | |
13769 | struct drm_clip_rect *clips, | |
13770 | unsigned num_clips) | |
13771 | { | |
5a97bcc6 | 13772 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
86c98588 | 13773 | |
5a97bcc6 | 13774 | i915_gem_object_flush_if_display(obj); |
d59b21ec | 13775 | intel_fb_obj_flush(obj, ORIGIN_DIRTYFB); |
86c98588 RV |
13776 | |
13777 | return 0; | |
13778 | } | |
13779 | ||
79e53945 JB |
13780 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
13781 | .destroy = intel_user_framebuffer_destroy, | |
13782 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 13783 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
13784 | }; |
13785 | ||
b321803d | 13786 | static |
920a14b2 TU |
13787 | u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv, |
13788 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 13789 | { |
24dbf51a | 13790 | u32 gen = INTEL_GEN(dev_priv); |
b321803d DL |
13791 | |
13792 | if (gen >= 9) { | |
ac484963 VS |
13793 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
13794 | ||
b321803d DL |
13795 | /* "The stride in bytes must not exceed the of the size of 8K |
13796 | * pixels and 32K bytes." | |
13797 | */ | |
ac484963 | 13798 | return min(8192 * cpp, 32768); |
6401c37d | 13799 | } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) { |
b321803d DL |
13800 | return 32*1024; |
13801 | } else if (gen >= 4) { | |
13802 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
13803 | return 16*1024; | |
13804 | else | |
13805 | return 32*1024; | |
13806 | } else if (gen >= 3) { | |
13807 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
13808 | return 8*1024; | |
13809 | else | |
13810 | return 16*1024; | |
13811 | } else { | |
13812 | /* XXX DSPC is limited to 4k tiled */ | |
13813 | return 8*1024; | |
13814 | } | |
13815 | } | |
13816 | ||
24dbf51a CW |
13817 | static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, |
13818 | struct drm_i915_gem_object *obj, | |
13819 | struct drm_mode_fb_cmd2 *mode_cmd) | |
79e53945 | 13820 | { |
24dbf51a | 13821 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
2e2adb05 | 13822 | struct drm_framebuffer *fb = &intel_fb->base; |
b3c11ac2 | 13823 | struct drm_format_name_buf format_name; |
2e2adb05 | 13824 | u32 pitch_limit; |
dd689287 | 13825 | unsigned int tiling, stride; |
24dbf51a | 13826 | int ret = -EINVAL; |
2e2adb05 | 13827 | int i; |
79e53945 | 13828 | |
dd689287 CW |
13829 | i915_gem_object_lock(obj); |
13830 | obj->framebuffer_references++; | |
13831 | tiling = i915_gem_object_get_tiling(obj); | |
13832 | stride = i915_gem_object_get_stride(obj); | |
13833 | i915_gem_object_unlock(obj); | |
dd4916c5 | 13834 | |
2a80eada | 13835 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
c2ff7370 VS |
13836 | /* |
13837 | * If there's a fence, enforce that | |
13838 | * the fb modifier and tiling mode match. | |
13839 | */ | |
13840 | if (tiling != I915_TILING_NONE && | |
13841 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
144cc143 | 13842 | DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n"); |
24dbf51a | 13843 | goto err; |
2a80eada DV |
13844 | } |
13845 | } else { | |
c2ff7370 | 13846 | if (tiling == I915_TILING_X) { |
2a80eada | 13847 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; |
c2ff7370 | 13848 | } else if (tiling == I915_TILING_Y) { |
144cc143 | 13849 | DRM_DEBUG_KMS("No Y tiling for legacy addfb\n"); |
24dbf51a | 13850 | goto err; |
2a80eada DV |
13851 | } |
13852 | } | |
13853 | ||
9a8f0a12 TU |
13854 | /* Passed in modifier sanity checking. */ |
13855 | switch (mode_cmd->modifier[0]) { | |
2e2adb05 VS |
13856 | case I915_FORMAT_MOD_Y_TILED_CCS: |
13857 | case I915_FORMAT_MOD_Yf_TILED_CCS: | |
13858 | switch (mode_cmd->pixel_format) { | |
13859 | case DRM_FORMAT_XBGR8888: | |
13860 | case DRM_FORMAT_ABGR8888: | |
13861 | case DRM_FORMAT_XRGB8888: | |
13862 | case DRM_FORMAT_ARGB8888: | |
13863 | break; | |
13864 | default: | |
13865 | DRM_DEBUG_KMS("RC supported only with RGB8888 formats\n"); | |
13866 | goto err; | |
13867 | } | |
13868 | /* fall through */ | |
9a8f0a12 TU |
13869 | case I915_FORMAT_MOD_Y_TILED: |
13870 | case I915_FORMAT_MOD_Yf_TILED: | |
6315b5d3 | 13871 | if (INTEL_GEN(dev_priv) < 9) { |
144cc143 VS |
13872 | DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n", |
13873 | mode_cmd->modifier[0]); | |
24dbf51a | 13874 | goto err; |
9a8f0a12 | 13875 | } |
2f075565 | 13876 | case DRM_FORMAT_MOD_LINEAR: |
9a8f0a12 TU |
13877 | case I915_FORMAT_MOD_X_TILED: |
13878 | break; | |
13879 | default: | |
144cc143 VS |
13880 | DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n", |
13881 | mode_cmd->modifier[0]); | |
24dbf51a | 13882 | goto err; |
c16ed4be | 13883 | } |
57cd6508 | 13884 | |
c2ff7370 VS |
13885 | /* |
13886 | * gen2/3 display engine uses the fence if present, | |
13887 | * so the tiling mode must match the fb modifier exactly. | |
13888 | */ | |
13889 | if (INTEL_INFO(dev_priv)->gen < 4 && | |
13890 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
144cc143 | 13891 | DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n"); |
9aceb5c1 | 13892 | goto err; |
c2ff7370 VS |
13893 | } |
13894 | ||
920a14b2 | 13895 | pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0], |
b321803d | 13896 | mode_cmd->pixel_format); |
a35cdaa0 | 13897 | if (mode_cmd->pitches[0] > pitch_limit) { |
144cc143 | 13898 | DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n", |
2f075565 | 13899 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ? |
144cc143 VS |
13900 | "tiled" : "linear", |
13901 | mode_cmd->pitches[0], pitch_limit); | |
24dbf51a | 13902 | goto err; |
c16ed4be | 13903 | } |
5d7bd705 | 13904 | |
c2ff7370 VS |
13905 | /* |
13906 | * If there's a fence, enforce that | |
13907 | * the fb pitch and fence stride match. | |
13908 | */ | |
144cc143 VS |
13909 | if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) { |
13910 | DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n", | |
13911 | mode_cmd->pitches[0], stride); | |
24dbf51a | 13912 | goto err; |
c16ed4be | 13913 | } |
5d7bd705 | 13914 | |
57779d06 | 13915 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 13916 | switch (mode_cmd->pixel_format) { |
57779d06 | 13917 | case DRM_FORMAT_C8: |
04b3924d VS |
13918 | case DRM_FORMAT_RGB565: |
13919 | case DRM_FORMAT_XRGB8888: | |
13920 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
13921 | break; |
13922 | case DRM_FORMAT_XRGB1555: | |
6315b5d3 | 13923 | if (INTEL_GEN(dev_priv) > 3) { |
144cc143 VS |
13924 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
13925 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 13926 | goto err; |
c16ed4be | 13927 | } |
57779d06 | 13928 | break; |
57779d06 | 13929 | case DRM_FORMAT_ABGR8888: |
920a14b2 | 13930 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
6315b5d3 | 13931 | INTEL_GEN(dev_priv) < 9) { |
144cc143 VS |
13932 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
13933 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 13934 | goto err; |
6c0fd451 DL |
13935 | } |
13936 | break; | |
13937 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 13938 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 13939 | case DRM_FORMAT_XBGR2101010: |
6315b5d3 | 13940 | if (INTEL_GEN(dev_priv) < 4) { |
144cc143 VS |
13941 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
13942 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 13943 | goto err; |
c16ed4be | 13944 | } |
b5626747 | 13945 | break; |
7531208b | 13946 | case DRM_FORMAT_ABGR2101010: |
920a14b2 | 13947 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
144cc143 VS |
13948 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
13949 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 13950 | goto err; |
7531208b DL |
13951 | } |
13952 | break; | |
04b3924d VS |
13953 | case DRM_FORMAT_YUYV: |
13954 | case DRM_FORMAT_UYVY: | |
13955 | case DRM_FORMAT_YVYU: | |
13956 | case DRM_FORMAT_VYUY: | |
ab33081a | 13957 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) { |
144cc143 VS |
13958 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
13959 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 13960 | goto err; |
c16ed4be | 13961 | } |
57cd6508 CW |
13962 | break; |
13963 | default: | |
144cc143 VS |
13964 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
13965 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 13966 | goto err; |
57cd6508 CW |
13967 | } |
13968 | ||
90f9a336 VS |
13969 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
13970 | if (mode_cmd->offsets[0] != 0) | |
24dbf51a | 13971 | goto err; |
90f9a336 | 13972 | |
2e2adb05 | 13973 | drm_helper_mode_fill_fb_struct(&dev_priv->drm, fb, mode_cmd); |
d88c4afd | 13974 | |
2e2adb05 VS |
13975 | for (i = 0; i < fb->format->num_planes; i++) { |
13976 | u32 stride_alignment; | |
13977 | ||
13978 | if (mode_cmd->handles[i] != mode_cmd->handles[0]) { | |
13979 | DRM_DEBUG_KMS("bad plane %d handle\n", i); | |
13980 | return -EINVAL; | |
13981 | } | |
13982 | ||
13983 | stride_alignment = intel_fb_stride_alignment(fb, i); | |
13984 | ||
13985 | /* | |
13986 | * Display WA #0531: skl,bxt,kbl,glk | |
13987 | * | |
13988 | * Render decompression and plane width > 3840 | |
13989 | * combined with horizontal panning requires the | |
13990 | * plane stride to be a multiple of 4. We'll just | |
13991 | * require the entire fb to accommodate that to avoid | |
13992 | * potential runtime errors at plane configuration time. | |
13993 | */ | |
13994 | if (IS_GEN9(dev_priv) && i == 0 && fb->width > 3840 && | |
13995 | (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || | |
13996 | fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) | |
13997 | stride_alignment *= 4; | |
13998 | ||
13999 | if (fb->pitches[i] & (stride_alignment - 1)) { | |
14000 | DRM_DEBUG_KMS("plane %d pitch (%d) must be at least %u byte aligned\n", | |
14001 | i, fb->pitches[i], stride_alignment); | |
14002 | goto err; | |
14003 | } | |
d88c4afd VS |
14004 | } |
14005 | ||
c7d73f6a DV |
14006 | intel_fb->obj = obj; |
14007 | ||
2e2adb05 | 14008 | ret = intel_fill_fb_info(dev_priv, fb); |
6687c906 | 14009 | if (ret) |
9aceb5c1 | 14010 | goto err; |
2d7a215f | 14011 | |
2e2adb05 | 14012 | ret = drm_framebuffer_init(&dev_priv->drm, fb, &intel_fb_funcs); |
79e53945 JB |
14013 | if (ret) { |
14014 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
24dbf51a | 14015 | goto err; |
79e53945 JB |
14016 | } |
14017 | ||
79e53945 | 14018 | return 0; |
24dbf51a CW |
14019 | |
14020 | err: | |
dd689287 CW |
14021 | i915_gem_object_lock(obj); |
14022 | obj->framebuffer_references--; | |
14023 | i915_gem_object_unlock(obj); | |
24dbf51a | 14024 | return ret; |
79e53945 JB |
14025 | } |
14026 | ||
79e53945 JB |
14027 | static struct drm_framebuffer * |
14028 | intel_user_framebuffer_create(struct drm_device *dev, | |
14029 | struct drm_file *filp, | |
1eb83451 | 14030 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 14031 | { |
dcb1394e | 14032 | struct drm_framebuffer *fb; |
05394f39 | 14033 | struct drm_i915_gem_object *obj; |
76dc3769 | 14034 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 14035 | |
03ac0642 CW |
14036 | obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]); |
14037 | if (!obj) | |
cce13ff7 | 14038 | return ERR_PTR(-ENOENT); |
79e53945 | 14039 | |
24dbf51a | 14040 | fb = intel_framebuffer_create(obj, &mode_cmd); |
dcb1394e | 14041 | if (IS_ERR(fb)) |
f0cd5182 | 14042 | i915_gem_object_put(obj); |
dcb1394e LW |
14043 | |
14044 | return fb; | |
79e53945 JB |
14045 | } |
14046 | ||
778e23a9 CW |
14047 | static void intel_atomic_state_free(struct drm_atomic_state *state) |
14048 | { | |
14049 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
14050 | ||
14051 | drm_atomic_state_default_release(state); | |
14052 | ||
14053 | i915_sw_fence_fini(&intel_state->commit_ready); | |
14054 | ||
14055 | kfree(state); | |
14056 | } | |
14057 | ||
79e53945 | 14058 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14059 | .fb_create = intel_user_framebuffer_create, |
bbfb6ce8 | 14060 | .get_format_info = intel_get_format_info, |
0632fef6 | 14061 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14062 | .atomic_check = intel_atomic_check, |
14063 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
14064 | .atomic_state_alloc = intel_atomic_state_alloc, |
14065 | .atomic_state_clear = intel_atomic_state_clear, | |
778e23a9 | 14066 | .atomic_state_free = intel_atomic_state_free, |
79e53945 JB |
14067 | }; |
14068 | ||
88212941 ID |
14069 | /** |
14070 | * intel_init_display_hooks - initialize the display modesetting hooks | |
14071 | * @dev_priv: device private | |
14072 | */ | |
14073 | void intel_init_display_hooks(struct drm_i915_private *dev_priv) | |
e70236a8 | 14074 | { |
7ff89ca2 VS |
14075 | intel_init_cdclk_hooks(dev_priv); |
14076 | ||
88212941 | 14077 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
bc8d7dff | 14078 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14079 | dev_priv->display.get_initial_plane_config = |
14080 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14081 | dev_priv->display.crtc_compute_clock = |
14082 | haswell_crtc_compute_clock; | |
14083 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14084 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 14085 | } else if (HAS_DDI(dev_priv)) { |
0e8ffe1b | 14086 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14087 | dev_priv->display.get_initial_plane_config = |
14088 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14089 | dev_priv->display.crtc_compute_clock = |
14090 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14091 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14092 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 14093 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
0e8ffe1b | 14094 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14095 | dev_priv->display.get_initial_plane_config = |
14096 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14097 | dev_priv->display.crtc_compute_clock = |
14098 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14099 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14100 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
65b3d6a9 | 14101 | } else if (IS_CHERRYVIEW(dev_priv)) { |
89b667f8 | 14102 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14103 | dev_priv->display.get_initial_plane_config = |
14104 | i9xx_get_initial_plane_config; | |
65b3d6a9 ACO |
14105 | dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; |
14106 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
14107 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
14108 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
14109 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14110 | dev_priv->display.get_initial_plane_config = | |
14111 | i9xx_get_initial_plane_config; | |
14112 | dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; | |
89b667f8 JB |
14113 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14114 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
19ec6693 ACO |
14115 | } else if (IS_G4X(dev_priv)) { |
14116 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14117 | dev_priv->display.get_initial_plane_config = | |
14118 | i9xx_get_initial_plane_config; | |
14119 | dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; | |
14120 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14121 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
70e8aa21 ACO |
14122 | } else if (IS_PINEVIEW(dev_priv)) { |
14123 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14124 | dev_priv->display.get_initial_plane_config = | |
14125 | i9xx_get_initial_plane_config; | |
14126 | dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; | |
14127 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14128 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 | 14129 | } else if (!IS_GEN2(dev_priv)) { |
0e8ffe1b | 14130 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14131 | dev_priv->display.get_initial_plane_config = |
14132 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14133 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14134 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14135 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 ACO |
14136 | } else { |
14137 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14138 | dev_priv->display.get_initial_plane_config = | |
14139 | i9xx_get_initial_plane_config; | |
14140 | dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; | |
14141 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14142 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 14143 | } |
e70236a8 | 14144 | |
88212941 | 14145 | if (IS_GEN5(dev_priv)) { |
3bb11b53 | 14146 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
88212941 | 14147 | } else if (IS_GEN6(dev_priv)) { |
3bb11b53 | 14148 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
88212941 | 14149 | } else if (IS_IVYBRIDGE(dev_priv)) { |
3bb11b53 SJ |
14150 | /* FIXME: detect B0+ stepping and use auto training */ |
14151 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
88212941 | 14152 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3bb11b53 | 14153 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
445e780b VS |
14154 | } |
14155 | ||
27082493 L |
14156 | if (dev_priv->info.gen >= 9) |
14157 | dev_priv->display.update_crtcs = skl_update_crtcs; | |
14158 | else | |
14159 | dev_priv->display.update_crtcs = intel_update_crtcs; | |
e70236a8 JB |
14160 | } |
14161 | ||
435793df KP |
14162 | /* |
14163 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
14164 | */ | |
14165 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
14166 | { | |
fac5e23e | 14167 | struct drm_i915_private *dev_priv = to_i915(dev); |
435793df | 14168 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
bc0daf48 | 14169 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
14170 | } |
14171 | ||
4dca20ef | 14172 | /* |
5a15ab5b CE |
14173 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
14174 | * brightness value | |
4dca20ef CE |
14175 | */ |
14176 | static void quirk_invert_brightness(struct drm_device *dev) | |
14177 | { | |
fac5e23e | 14178 | struct drm_i915_private *dev_priv = to_i915(dev); |
4dca20ef | 14179 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
bc0daf48 | 14180 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
14181 | } |
14182 | ||
9c72cc6f SD |
14183 | /* Some VBT's incorrectly indicate no backlight is present */ |
14184 | static void quirk_backlight_present(struct drm_device *dev) | |
14185 | { | |
fac5e23e | 14186 | struct drm_i915_private *dev_priv = to_i915(dev); |
9c72cc6f SD |
14187 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; |
14188 | DRM_INFO("applying backlight present quirk\n"); | |
14189 | } | |
14190 | ||
c99a259b MN |
14191 | /* Toshiba Satellite P50-C-18C requires T12 delay to be min 800ms |
14192 | * which is 300 ms greater than eDP spec T12 min. | |
14193 | */ | |
14194 | static void quirk_increase_t12_delay(struct drm_device *dev) | |
14195 | { | |
14196 | struct drm_i915_private *dev_priv = to_i915(dev); | |
14197 | ||
14198 | dev_priv->quirks |= QUIRK_INCREASE_T12_DELAY; | |
14199 | DRM_INFO("Applying T12 delay quirk\n"); | |
14200 | } | |
14201 | ||
b690e96c JB |
14202 | struct intel_quirk { |
14203 | int device; | |
14204 | int subsystem_vendor; | |
14205 | int subsystem_device; | |
14206 | void (*hook)(struct drm_device *dev); | |
14207 | }; | |
14208 | ||
5f85f176 EE |
14209 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
14210 | struct intel_dmi_quirk { | |
14211 | void (*hook)(struct drm_device *dev); | |
14212 | const struct dmi_system_id (*dmi_id_list)[]; | |
14213 | }; | |
14214 | ||
14215 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
14216 | { | |
14217 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
14218 | return 1; | |
14219 | } | |
14220 | ||
14221 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
14222 | { | |
14223 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
14224 | { | |
14225 | .callback = intel_dmi_reverse_brightness, | |
14226 | .ident = "NCR Corporation", | |
14227 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
14228 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
14229 | }, | |
14230 | }, | |
14231 | { } /* terminating entry */ | |
14232 | }, | |
14233 | .hook = quirk_invert_brightness, | |
14234 | }, | |
14235 | }; | |
14236 | ||
c43b5634 | 14237 | static struct intel_quirk intel_quirks[] = { |
435793df KP |
14238 | /* Lenovo U160 cannot use SSC on LVDS */ |
14239 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
14240 | |
14241 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
14242 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 14243 | |
be505f64 AH |
14244 | /* Acer Aspire 5734Z must invert backlight brightness */ |
14245 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
14246 | ||
14247 | /* Acer/eMachines G725 */ | |
14248 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
14249 | ||
14250 | /* Acer/eMachines e725 */ | |
14251 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
14252 | ||
14253 | /* Acer/Packard Bell NCL20 */ | |
14254 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
14255 | ||
14256 | /* Acer Aspire 4736Z */ | |
14257 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
14258 | |
14259 | /* Acer Aspire 5336 */ | |
14260 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
14261 | |
14262 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
14263 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 14264 | |
dfb3d47b SD |
14265 | /* Acer C720 Chromebook (Core i3 4005U) */ |
14266 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
14267 | ||
b2a9601c | 14268 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
14269 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
14270 | ||
1b9448b0 JN |
14271 | /* Apple Macbook 4,1 */ |
14272 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
14273 | ||
d4967d8c SD |
14274 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
14275 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
14276 | |
14277 | /* HP Chromebook 14 (Celeron 2955U) */ | |
14278 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
14279 | |
14280 | /* Dell Chromebook 11 */ | |
14281 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
14282 | |
14283 | /* Dell Chromebook 11 (2015 version) */ | |
14284 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
c99a259b MN |
14285 | |
14286 | /* Toshiba Satellite P50-C-18C */ | |
14287 | { 0x191B, 0x1179, 0xF840, quirk_increase_t12_delay }, | |
b690e96c JB |
14288 | }; |
14289 | ||
14290 | static void intel_init_quirks(struct drm_device *dev) | |
14291 | { | |
14292 | struct pci_dev *d = dev->pdev; | |
14293 | int i; | |
14294 | ||
14295 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
14296 | struct intel_quirk *q = &intel_quirks[i]; | |
14297 | ||
14298 | if (d->device == q->device && | |
14299 | (d->subsystem_vendor == q->subsystem_vendor || | |
14300 | q->subsystem_vendor == PCI_ANY_ID) && | |
14301 | (d->subsystem_device == q->subsystem_device || | |
14302 | q->subsystem_device == PCI_ANY_ID)) | |
14303 | q->hook(dev); | |
14304 | } | |
5f85f176 EE |
14305 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
14306 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
14307 | intel_dmi_quirks[i].hook(dev); | |
14308 | } | |
b690e96c JB |
14309 | } |
14310 | ||
9cce37f4 | 14311 | /* Disable the VGA plane that we never use */ |
29b74b7f | 14312 | static void i915_disable_vga(struct drm_i915_private *dev_priv) |
9cce37f4 | 14313 | { |
52a05c30 | 14314 | struct pci_dev *pdev = dev_priv->drm.pdev; |
9cce37f4 | 14315 | u8 sr1; |
920a14b2 | 14316 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); |
9cce37f4 | 14317 | |
2b37c616 | 14318 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
52a05c30 | 14319 | vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 14320 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
14321 | sr1 = inb(VGA_SR_DATA); |
14322 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
52a05c30 | 14323 | vga_put(pdev, VGA_RSRC_LEGACY_IO); |
9cce37f4 JB |
14324 | udelay(300); |
14325 | ||
01f5a626 | 14326 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
14327 | POSTING_READ(vga_reg); |
14328 | } | |
14329 | ||
f817586c DV |
14330 | void intel_modeset_init_hw(struct drm_device *dev) |
14331 | { | |
fac5e23e | 14332 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a617b77 | 14333 | |
4c75b940 | 14334 | intel_update_cdclk(dev_priv); |
bb0f4aab | 14335 | dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw; |
1a617b77 | 14336 | |
46f16e63 | 14337 | intel_init_clock_gating(dev_priv); |
f817586c DV |
14338 | } |
14339 | ||
d93c0372 MR |
14340 | /* |
14341 | * Calculate what we think the watermarks should be for the state we've read | |
14342 | * out of the hardware and then immediately program those watermarks so that | |
14343 | * we ensure the hardware settings match our internal state. | |
14344 | * | |
14345 | * We can calculate what we think WM's should be by creating a duplicate of the | |
14346 | * current state (which was constructed during hardware readout) and running it | |
14347 | * through the atomic check code to calculate new watermark values in the | |
14348 | * state object. | |
14349 | */ | |
14350 | static void sanitize_watermarks(struct drm_device *dev) | |
14351 | { | |
14352 | struct drm_i915_private *dev_priv = to_i915(dev); | |
14353 | struct drm_atomic_state *state; | |
ccf010fb | 14354 | struct intel_atomic_state *intel_state; |
d93c0372 MR |
14355 | struct drm_crtc *crtc; |
14356 | struct drm_crtc_state *cstate; | |
14357 | struct drm_modeset_acquire_ctx ctx; | |
14358 | int ret; | |
14359 | int i; | |
14360 | ||
14361 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 14362 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
14363 | return; |
14364 | ||
14365 | /* | |
14366 | * We need to hold connection_mutex before calling duplicate_state so | |
14367 | * that the connector loop is protected. | |
14368 | */ | |
14369 | drm_modeset_acquire_init(&ctx, 0); | |
14370 | retry: | |
0cd1262d | 14371 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
14372 | if (ret == -EDEADLK) { |
14373 | drm_modeset_backoff(&ctx); | |
14374 | goto retry; | |
14375 | } else if (WARN_ON(ret)) { | |
0cd1262d | 14376 | goto fail; |
d93c0372 MR |
14377 | } |
14378 | ||
14379 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
14380 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 14381 | goto fail; |
d93c0372 | 14382 | |
ccf010fb ML |
14383 | intel_state = to_intel_atomic_state(state); |
14384 | ||
ed4a6a7c MR |
14385 | /* |
14386 | * Hardware readout is the only time we don't want to calculate | |
14387 | * intermediate watermarks (since we don't trust the current | |
14388 | * watermarks). | |
14389 | */ | |
602ae835 VS |
14390 | if (!HAS_GMCH_DISPLAY(dev_priv)) |
14391 | intel_state->skip_intermediate_wm = true; | |
ed4a6a7c | 14392 | |
d93c0372 MR |
14393 | ret = intel_atomic_check(dev, state); |
14394 | if (ret) { | |
14395 | /* | |
14396 | * If we fail here, it means that the hardware appears to be | |
14397 | * programmed in a way that shouldn't be possible, given our | |
14398 | * understanding of watermark requirements. This might mean a | |
14399 | * mistake in the hardware readout code or a mistake in the | |
14400 | * watermark calculations for a given platform. Raise a WARN | |
14401 | * so that this is noticeable. | |
14402 | * | |
14403 | * If this actually happens, we'll have to just leave the | |
14404 | * BIOS-programmed watermarks untouched and hope for the best. | |
14405 | */ | |
14406 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
b9a1b717 | 14407 | goto put_state; |
d93c0372 MR |
14408 | } |
14409 | ||
14410 | /* Write calculated watermark values back */ | |
aa5e9b47 | 14411 | for_each_new_crtc_in_state(state, crtc, cstate, i) { |
d93c0372 MR |
14412 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); |
14413 | ||
ed4a6a7c | 14414 | cs->wm.need_postvbl_update = true; |
ccf010fb | 14415 | dev_priv->display.optimize_watermarks(intel_state, cs); |
d93c0372 MR |
14416 | } |
14417 | ||
b9a1b717 | 14418 | put_state: |
0853695c | 14419 | drm_atomic_state_put(state); |
0cd1262d | 14420 | fail: |
d93c0372 MR |
14421 | drm_modeset_drop_locks(&ctx); |
14422 | drm_modeset_acquire_fini(&ctx); | |
14423 | } | |
14424 | ||
b079bd17 | 14425 | int intel_modeset_init(struct drm_device *dev) |
79e53945 | 14426 | { |
72e96d64 JL |
14427 | struct drm_i915_private *dev_priv = to_i915(dev); |
14428 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
8cc87b75 | 14429 | enum pipe pipe; |
46f297fb | 14430 | struct intel_crtc *crtc; |
79e53945 JB |
14431 | |
14432 | drm_mode_config_init(dev); | |
14433 | ||
14434 | dev->mode_config.min_width = 0; | |
14435 | dev->mode_config.min_height = 0; | |
14436 | ||
019d96cb DA |
14437 | dev->mode_config.preferred_depth = 24; |
14438 | dev->mode_config.prefer_shadow = 1; | |
14439 | ||
25bab385 TU |
14440 | dev->mode_config.allow_fb_modifiers = true; |
14441 | ||
e6ecefaa | 14442 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 14443 | |
400c19d9 | 14444 | init_llist_head(&dev_priv->atomic_helper.free_list); |
eb955eee | 14445 | INIT_WORK(&dev_priv->atomic_helper.free_work, |
ba318c61 | 14446 | intel_atomic_helper_free_state_worker); |
eb955eee | 14447 | |
b690e96c JB |
14448 | intel_init_quirks(dev); |
14449 | ||
62d75df7 | 14450 | intel_init_pm(dev_priv); |
1fa61106 | 14451 | |
b7f05d4a | 14452 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
b079bd17 | 14453 | return 0; |
e3c74757 | 14454 | |
69f92f67 LW |
14455 | /* |
14456 | * There may be no VBT; and if the BIOS enabled SSC we can | |
14457 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
14458 | * BIOS isn't using it, don't assume it will work even if the VBT | |
14459 | * indicates as much. | |
14460 | */ | |
6e266956 | 14461 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { |
69f92f67 LW |
14462 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & |
14463 | DREF_SSC1_ENABLE); | |
14464 | ||
14465 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
14466 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
14467 | bios_lvds_use_ssc ? "en" : "dis", | |
14468 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
14469 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
14470 | } | |
14471 | } | |
14472 | ||
5db94019 | 14473 | if (IS_GEN2(dev_priv)) { |
a6c45cf0 CW |
14474 | dev->mode_config.max_width = 2048; |
14475 | dev->mode_config.max_height = 2048; | |
5db94019 | 14476 | } else if (IS_GEN3(dev_priv)) { |
5e4d6fa7 KP |
14477 | dev->mode_config.max_width = 4096; |
14478 | dev->mode_config.max_height = 4096; | |
79e53945 | 14479 | } else { |
a6c45cf0 CW |
14480 | dev->mode_config.max_width = 8192; |
14481 | dev->mode_config.max_height = 8192; | |
79e53945 | 14482 | } |
068be561 | 14483 | |
2a307c2e JN |
14484 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { |
14485 | dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512; | |
dc41c154 | 14486 | dev->mode_config.cursor_height = 1023; |
5db94019 | 14487 | } else if (IS_GEN2(dev_priv)) { |
068be561 DL |
14488 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
14489 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
14490 | } else { | |
14491 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
14492 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
14493 | } | |
14494 | ||
72e96d64 | 14495 | dev->mode_config.fb_base = ggtt->mappable_base; |
79e53945 | 14496 | |
28c97730 | 14497 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
b7f05d4a TU |
14498 | INTEL_INFO(dev_priv)->num_pipes, |
14499 | INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 14500 | |
055e393f | 14501 | for_each_pipe(dev_priv, pipe) { |
b079bd17 VS |
14502 | int ret; |
14503 | ||
5ab0d85b | 14504 | ret = intel_crtc_init(dev_priv, pipe); |
b079bd17 VS |
14505 | if (ret) { |
14506 | drm_mode_config_cleanup(dev); | |
14507 | return ret; | |
14508 | } | |
79e53945 JB |
14509 | } |
14510 | ||
e72f9fbf | 14511 | intel_shared_dpll_init(dev); |
ee7b9f93 | 14512 | |
5be6e334 VS |
14513 | intel_update_czclk(dev_priv); |
14514 | intel_modeset_init_hw(dev); | |
14515 | ||
b2045352 | 14516 | if (dev_priv->max_cdclk_freq == 0) |
4c75b940 | 14517 | intel_update_max_cdclk(dev_priv); |
b2045352 | 14518 | |
9cce37f4 | 14519 | /* Just disable it once at startup */ |
29b74b7f | 14520 | i915_disable_vga(dev_priv); |
c39055b0 | 14521 | intel_setup_outputs(dev_priv); |
11be49eb | 14522 | |
6e9f798d | 14523 | drm_modeset_lock_all(dev); |
aecd36b8 | 14524 | intel_modeset_setup_hw_state(dev, dev->mode_config.acquire_ctx); |
6e9f798d | 14525 | drm_modeset_unlock_all(dev); |
46f297fb | 14526 | |
d3fcc808 | 14527 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
14528 | struct intel_initial_plane_config plane_config = {}; |
14529 | ||
46f297fb JB |
14530 | if (!crtc->active) |
14531 | continue; | |
14532 | ||
46f297fb | 14533 | /* |
46f297fb JB |
14534 | * Note that reserving the BIOS fb up front prevents us |
14535 | * from stuffing other stolen allocations like the ring | |
14536 | * on top. This prevents some ugliness at boot time, and | |
14537 | * can even allow for smooth boot transitions if the BIOS | |
14538 | * fb is large enough for the active pipe configuration. | |
14539 | */ | |
eeebeac5 ML |
14540 | dev_priv->display.get_initial_plane_config(crtc, |
14541 | &plane_config); | |
14542 | ||
14543 | /* | |
14544 | * If the fb is shared between multiple heads, we'll | |
14545 | * just get the first one. | |
14546 | */ | |
14547 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 14548 | } |
d93c0372 MR |
14549 | |
14550 | /* | |
14551 | * Make sure hardware watermarks really match the state we read out. | |
14552 | * Note that we need to do this after reconstructing the BIOS fb's | |
14553 | * since the watermark calculation done here will use pstate->fb. | |
14554 | */ | |
602ae835 VS |
14555 | if (!HAS_GMCH_DISPLAY(dev_priv)) |
14556 | sanitize_watermarks(dev); | |
b079bd17 VS |
14557 | |
14558 | return 0; | |
2c7111db CW |
14559 | } |
14560 | ||
2ee0da16 VS |
14561 | void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) |
14562 | { | |
14563 | /* 640x480@60Hz, ~25175 kHz */ | |
14564 | struct dpll clock = { | |
14565 | .m1 = 18, | |
14566 | .m2 = 7, | |
14567 | .p1 = 13, | |
14568 | .p2 = 4, | |
14569 | .n = 2, | |
14570 | }; | |
14571 | u32 dpll, fp; | |
14572 | int i; | |
14573 | ||
14574 | WARN_ON(i9xx_calc_dpll_params(48000, &clock) != 25154); | |
14575 | ||
14576 | DRM_DEBUG_KMS("enabling pipe %c due to force quirk (vco=%d dot=%d)\n", | |
14577 | pipe_name(pipe), clock.vco, clock.dot); | |
14578 | ||
14579 | fp = i9xx_dpll_compute_fp(&clock); | |
14580 | dpll = (I915_READ(DPLL(pipe)) & DPLL_DVO_2X_MODE) | | |
14581 | DPLL_VGA_MODE_DIS | | |
14582 | ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) | | |
14583 | PLL_P2_DIVIDE_BY_4 | | |
14584 | PLL_REF_INPUT_DREFCLK | | |
14585 | DPLL_VCO_ENABLE; | |
14586 | ||
14587 | I915_WRITE(FP0(pipe), fp); | |
14588 | I915_WRITE(FP1(pipe), fp); | |
14589 | ||
14590 | I915_WRITE(HTOTAL(pipe), (640 - 1) | ((800 - 1) << 16)); | |
14591 | I915_WRITE(HBLANK(pipe), (640 - 1) | ((800 - 1) << 16)); | |
14592 | I915_WRITE(HSYNC(pipe), (656 - 1) | ((752 - 1) << 16)); | |
14593 | I915_WRITE(VTOTAL(pipe), (480 - 1) | ((525 - 1) << 16)); | |
14594 | I915_WRITE(VBLANK(pipe), (480 - 1) | ((525 - 1) << 16)); | |
14595 | I915_WRITE(VSYNC(pipe), (490 - 1) | ((492 - 1) << 16)); | |
14596 | I915_WRITE(PIPESRC(pipe), ((640 - 1) << 16) | (480 - 1)); | |
14597 | ||
14598 | /* | |
14599 | * Apparently we need to have VGA mode enabled prior to changing | |
14600 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
14601 | * dividers, even though the register value does change. | |
14602 | */ | |
14603 | I915_WRITE(DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); | |
14604 | I915_WRITE(DPLL(pipe), dpll); | |
14605 | ||
14606 | /* Wait for the clocks to stabilize. */ | |
14607 | POSTING_READ(DPLL(pipe)); | |
14608 | udelay(150); | |
14609 | ||
14610 | /* The pixel multiplier can only be updated once the | |
14611 | * DPLL is enabled and the clocks are stable. | |
14612 | * | |
14613 | * So write it again. | |
14614 | */ | |
14615 | I915_WRITE(DPLL(pipe), dpll); | |
14616 | ||
14617 | /* We do this three times for luck */ | |
14618 | for (i = 0; i < 3 ; i++) { | |
14619 | I915_WRITE(DPLL(pipe), dpll); | |
14620 | POSTING_READ(DPLL(pipe)); | |
14621 | udelay(150); /* wait for warmup */ | |
14622 | } | |
14623 | ||
14624 | I915_WRITE(PIPECONF(pipe), PIPECONF_ENABLE | PIPECONF_PROGRESSIVE); | |
14625 | POSTING_READ(PIPECONF(pipe)); | |
14626 | } | |
14627 | ||
14628 | void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe) | |
14629 | { | |
14630 | DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n", | |
14631 | pipe_name(pipe)); | |
14632 | ||
14633 | assert_plane_disabled(dev_priv, PLANE_A); | |
14634 | assert_plane_disabled(dev_priv, PLANE_B); | |
14635 | ||
14636 | I915_WRITE(PIPECONF(pipe), 0); | |
14637 | POSTING_READ(PIPECONF(pipe)); | |
14638 | ||
14639 | if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100)) | |
14640 | DRM_ERROR("pipe %c off wait timed out\n", pipe_name(pipe)); | |
14641 | ||
14642 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); | |
14643 | POSTING_READ(DPLL(pipe)); | |
14644 | } | |
14645 | ||
fa555837 DV |
14646 | static bool |
14647 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
14648 | { | |
b7f05d4a | 14649 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
649636ef | 14650 | u32 val; |
fa555837 | 14651 | |
b7f05d4a | 14652 | if (INTEL_INFO(dev_priv)->num_pipes == 1) |
fa555837 DV |
14653 | return true; |
14654 | ||
649636ef | 14655 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
14656 | |
14657 | if ((val & DISPLAY_PLANE_ENABLE) && | |
14658 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
14659 | return false; | |
14660 | ||
14661 | return true; | |
14662 | } | |
14663 | ||
02e93c35 VS |
14664 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
14665 | { | |
14666 | struct drm_device *dev = crtc->base.dev; | |
14667 | struct intel_encoder *encoder; | |
14668 | ||
14669 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
14670 | return true; | |
14671 | ||
14672 | return false; | |
14673 | } | |
14674 | ||
496b0fc3 ML |
14675 | static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) |
14676 | { | |
14677 | struct drm_device *dev = encoder->base.dev; | |
14678 | struct intel_connector *connector; | |
14679 | ||
14680 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
14681 | return connector; | |
14682 | ||
14683 | return NULL; | |
14684 | } | |
14685 | ||
a168f5b3 VS |
14686 | static bool has_pch_trancoder(struct drm_i915_private *dev_priv, |
14687 | enum transcoder pch_transcoder) | |
14688 | { | |
14689 | return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || | |
14690 | (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A); | |
14691 | } | |
14692 | ||
aecd36b8 VS |
14693 | static void intel_sanitize_crtc(struct intel_crtc *crtc, |
14694 | struct drm_modeset_acquire_ctx *ctx) | |
24929352 DV |
14695 | { |
14696 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 14697 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 | 14698 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
24929352 | 14699 | |
24929352 | 14700 | /* Clear any frame start delays used for debugging left by the BIOS */ |
4d1de975 JN |
14701 | if (!transcoder_is_dsi(cpu_transcoder)) { |
14702 | i915_reg_t reg = PIPECONF(cpu_transcoder); | |
14703 | ||
14704 | I915_WRITE(reg, | |
14705 | I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | |
14706 | } | |
24929352 | 14707 | |
d3eaf884 | 14708 | /* restore vblank interrupts to correct state */ |
9625604c | 14709 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 14710 | if (crtc->active) { |
f9cd7b88 VS |
14711 | struct intel_plane *plane; |
14712 | ||
9625604c | 14713 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
14714 | |
14715 | /* Disable everything but the primary plane */ | |
14716 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
14717 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
14718 | continue; | |
14719 | ||
72259536 | 14720 | trace_intel_disable_plane(&plane->base, crtc); |
282dbf9b | 14721 | plane->disable_plane(plane, crtc); |
f9cd7b88 | 14722 | } |
9625604c | 14723 | } |
d3eaf884 | 14724 | |
24929352 | 14725 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
14726 | * disable the crtc (and hence change the state) if it is wrong. Note |
14727 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
6315b5d3 | 14728 | if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) { |
24929352 DV |
14729 | bool plane; |
14730 | ||
78108b7c VS |
14731 | DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n", |
14732 | crtc->base.base.id, crtc->base.name); | |
24929352 DV |
14733 | |
14734 | /* Pipe has the wrong plane attached and the plane is active. | |
14735 | * Temporarily change the plane mapping and disable everything | |
14736 | * ... */ | |
14737 | plane = crtc->plane; | |
1d4258db | 14738 | crtc->base.primary->state->visible = true; |
24929352 | 14739 | crtc->plane = !plane; |
da1d0e26 | 14740 | intel_crtc_disable_noatomic(&crtc->base, ctx); |
24929352 | 14741 | crtc->plane = plane; |
24929352 | 14742 | } |
24929352 DV |
14743 | |
14744 | /* Adjust the state of the output pipe according to whether we | |
14745 | * have active connectors/encoders. */ | |
842e0307 | 14746 | if (crtc->active && !intel_crtc_has_encoders(crtc)) |
da1d0e26 | 14747 | intel_crtc_disable_noatomic(&crtc->base, ctx); |
24929352 | 14748 | |
49cff963 | 14749 | if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) { |
4cc31489 DV |
14750 | /* |
14751 | * We start out with underrun reporting disabled to avoid races. | |
14752 | * For correct bookkeeping mark this on active crtcs. | |
14753 | * | |
c5ab3bc0 DV |
14754 | * Also on gmch platforms we dont have any hardware bits to |
14755 | * disable the underrun reporting. Which means we need to start | |
14756 | * out with underrun reporting disabled also on inactive pipes, | |
14757 | * since otherwise we'll complain about the garbage we read when | |
14758 | * e.g. coming up after runtime pm. | |
14759 | * | |
4cc31489 DV |
14760 | * No protection against concurrent access is required - at |
14761 | * worst a fifo underrun happens which also sets this to false. | |
14762 | */ | |
14763 | crtc->cpu_fifo_underrun_disabled = true; | |
a168f5b3 VS |
14764 | /* |
14765 | * We track the PCH trancoder underrun reporting state | |
14766 | * within the crtc. With crtc for pipe A housing the underrun | |
14767 | * reporting state for PCH transcoder A, crtc for pipe B housing | |
14768 | * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, | |
14769 | * and marking underrun reporting as disabled for the non-existing | |
14770 | * PCH transcoders B and C would prevent enabling the south | |
14771 | * error interrupt (see cpt_can_enable_serr_int()). | |
14772 | */ | |
14773 | if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe)) | |
14774 | crtc->pch_fifo_underrun_disabled = true; | |
4cc31489 | 14775 | } |
24929352 DV |
14776 | } |
14777 | ||
14778 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
14779 | { | |
14780 | struct intel_connector *connector; | |
24929352 DV |
14781 | |
14782 | /* We need to check both for a crtc link (meaning that the | |
14783 | * encoder is active and trying to read from a pipe) and the | |
14784 | * pipe itself being active. */ | |
14785 | bool has_active_crtc = encoder->base.crtc && | |
14786 | to_intel_crtc(encoder->base.crtc)->active; | |
14787 | ||
496b0fc3 ML |
14788 | connector = intel_encoder_find_connector(encoder); |
14789 | if (connector && !has_active_crtc) { | |
24929352 DV |
14790 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
14791 | encoder->base.base.id, | |
8e329a03 | 14792 | encoder->base.name); |
24929352 DV |
14793 | |
14794 | /* Connector is active, but has no active pipe. This is | |
14795 | * fallout from our resume register restoring. Disable | |
14796 | * the encoder manually again. */ | |
14797 | if (encoder->base.crtc) { | |
fd6bbda9 ML |
14798 | struct drm_crtc_state *crtc_state = encoder->base.crtc->state; |
14799 | ||
24929352 DV |
14800 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", |
14801 | encoder->base.base.id, | |
8e329a03 | 14802 | encoder->base.name); |
fd6bbda9 | 14803 | encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); |
a62d1497 | 14804 | if (encoder->post_disable) |
fd6bbda9 | 14805 | encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); |
24929352 | 14806 | } |
7f1950fb | 14807 | encoder->base.crtc = NULL; |
24929352 DV |
14808 | |
14809 | /* Inconsistent output/port/pipe state happens presumably due to | |
14810 | * a bug in one of the get_hw_state functions. Or someplace else | |
14811 | * in our code, like the register restore mess on resume. Clamp | |
14812 | * things to off as a safer default. */ | |
fd6bbda9 ML |
14813 | |
14814 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
14815 | connector->base.encoder = NULL; | |
24929352 DV |
14816 | } |
14817 | /* Enabled encoders without active connectors will be fixed in | |
14818 | * the crtc fixup. */ | |
14819 | } | |
14820 | ||
29b74b7f | 14821 | void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv) |
0fde901f | 14822 | { |
920a14b2 | 14823 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); |
0fde901f | 14824 | |
04098753 ID |
14825 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
14826 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
29b74b7f | 14827 | i915_disable_vga(dev_priv); |
04098753 ID |
14828 | } |
14829 | } | |
14830 | ||
29b74b7f | 14831 | void i915_redisable_vga(struct drm_i915_private *dev_priv) |
04098753 | 14832 | { |
8dc8a27c PZ |
14833 | /* This function can be called both from intel_modeset_setup_hw_state or |
14834 | * at a very early point in our resume sequence, where the power well | |
14835 | * structures are not yet restored. Since this function is at a very | |
14836 | * paranoid "someone might have enabled VGA while we were not looking" | |
14837 | * level, just check if the power well is enabled instead of trying to | |
14838 | * follow the "don't touch the power well if we don't need it" policy | |
14839 | * the rest of the driver uses. */ | |
6392f847 | 14840 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
14841 | return; |
14842 | ||
29b74b7f | 14843 | i915_redisable_vga_power_on(dev_priv); |
6392f847 ID |
14844 | |
14845 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
0fde901f KM |
14846 | } |
14847 | ||
f9cd7b88 | 14848 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 14849 | { |
f9cd7b88 | 14850 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 14851 | |
f9cd7b88 | 14852 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
14853 | } |
14854 | ||
f9cd7b88 VS |
14855 | /* FIXME read out full plane state for all planes */ |
14856 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 14857 | { |
e9728bd8 VS |
14858 | struct intel_plane *primary = to_intel_plane(crtc->base.primary); |
14859 | bool visible; | |
d032ffa0 | 14860 | |
e9728bd8 | 14861 | visible = crtc->active && primary_get_hw_state(primary); |
b26d3ea3 | 14862 | |
e9728bd8 VS |
14863 | intel_set_plane_visible(to_intel_crtc_state(crtc->base.state), |
14864 | to_intel_plane_state(primary->base.state), | |
14865 | visible); | |
98ec7739 VS |
14866 | } |
14867 | ||
30e984df | 14868 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 | 14869 | { |
fac5e23e | 14870 | struct drm_i915_private *dev_priv = to_i915(dev); |
24929352 | 14871 | enum pipe pipe; |
24929352 DV |
14872 | struct intel_crtc *crtc; |
14873 | struct intel_encoder *encoder; | |
14874 | struct intel_connector *connector; | |
f9e905ca | 14875 | struct drm_connector_list_iter conn_iter; |
5358901f | 14876 | int i; |
24929352 | 14877 | |
565602d7 ML |
14878 | dev_priv->active_crtcs = 0; |
14879 | ||
d3fcc808 | 14880 | for_each_intel_crtc(dev, crtc) { |
a8cd6da0 VS |
14881 | struct intel_crtc_state *crtc_state = |
14882 | to_intel_crtc_state(crtc->base.state); | |
3b117c8f | 14883 | |
ec2dc6a0 | 14884 | __drm_atomic_helper_crtc_destroy_state(&crtc_state->base); |
565602d7 ML |
14885 | memset(crtc_state, 0, sizeof(*crtc_state)); |
14886 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 14887 | |
565602d7 ML |
14888 | crtc_state->base.active = crtc_state->base.enable = |
14889 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
14890 | ||
14891 | crtc->base.enabled = crtc_state->base.enable; | |
14892 | crtc->active = crtc_state->base.active; | |
14893 | ||
aca1ebf4 | 14894 | if (crtc_state->base.active) |
565602d7 ML |
14895 | dev_priv->active_crtcs |= 1 << crtc->pipe; |
14896 | ||
f9cd7b88 | 14897 | readout_plane_state(crtc); |
24929352 | 14898 | |
78108b7c VS |
14899 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n", |
14900 | crtc->base.base.id, crtc->base.name, | |
a8cd6da0 | 14901 | enableddisabled(crtc_state->base.active)); |
24929352 DV |
14902 | } |
14903 | ||
5358901f DV |
14904 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
14905 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
14906 | ||
2edd6443 | 14907 | pll->on = pll->funcs.get_hw_state(dev_priv, pll, |
2c42e535 ACO |
14908 | &pll->state.hw_state); |
14909 | pll->state.crtc_mask = 0; | |
d3fcc808 | 14910 | for_each_intel_crtc(dev, crtc) { |
a8cd6da0 VS |
14911 | struct intel_crtc_state *crtc_state = |
14912 | to_intel_crtc_state(crtc->base.state); | |
14913 | ||
14914 | if (crtc_state->base.active && | |
14915 | crtc_state->shared_dpll == pll) | |
2c42e535 | 14916 | pll->state.crtc_mask |= 1 << crtc->pipe; |
5358901f | 14917 | } |
2c42e535 | 14918 | pll->active_mask = pll->state.crtc_mask; |
5358901f | 14919 | |
1e6f2ddc | 14920 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
2c42e535 | 14921 | pll->name, pll->state.crtc_mask, pll->on); |
5358901f DV |
14922 | } |
14923 | ||
b2784e15 | 14924 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
14925 | pipe = 0; |
14926 | ||
14927 | if (encoder->get_hw_state(encoder, &pipe)) { | |
a8cd6da0 VS |
14928 | struct intel_crtc_state *crtc_state; |
14929 | ||
98187836 | 14930 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
a8cd6da0 | 14931 | crtc_state = to_intel_crtc_state(crtc->base.state); |
e2af48c6 | 14932 | |
045ac3b5 | 14933 | encoder->base.crtc = &crtc->base; |
a8cd6da0 VS |
14934 | crtc_state->output_types |= 1 << encoder->type; |
14935 | encoder->get_config(encoder, crtc_state); | |
24929352 DV |
14936 | } else { |
14937 | encoder->base.crtc = NULL; | |
14938 | } | |
14939 | ||
6f2bcceb | 14940 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
08c4d7fc TU |
14941 | encoder->base.base.id, encoder->base.name, |
14942 | enableddisabled(encoder->base.crtc), | |
6f2bcceb | 14943 | pipe_name(pipe)); |
24929352 DV |
14944 | } |
14945 | ||
f9e905ca DV |
14946 | drm_connector_list_iter_begin(dev, &conn_iter); |
14947 | for_each_intel_connector_iter(connector, &conn_iter) { | |
24929352 DV |
14948 | if (connector->get_hw_state(connector)) { |
14949 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
14950 | |
14951 | encoder = connector->encoder; | |
14952 | connector->base.encoder = &encoder->base; | |
14953 | ||
14954 | if (encoder->base.crtc && | |
14955 | encoder->base.crtc->state->active) { | |
14956 | /* | |
14957 | * This has to be done during hardware readout | |
14958 | * because anything calling .crtc_disable may | |
14959 | * rely on the connector_mask being accurate. | |
14960 | */ | |
14961 | encoder->base.crtc->state->connector_mask |= | |
14962 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
14963 | encoder->base.crtc->state->encoder_mask |= |
14964 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
14965 | } |
14966 | ||
24929352 DV |
14967 | } else { |
14968 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
14969 | connector->base.encoder = NULL; | |
14970 | } | |
14971 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
08c4d7fc TU |
14972 | connector->base.base.id, connector->base.name, |
14973 | enableddisabled(connector->base.encoder)); | |
24929352 | 14974 | } |
f9e905ca | 14975 | drm_connector_list_iter_end(&conn_iter); |
7f4c6284 VS |
14976 | |
14977 | for_each_intel_crtc(dev, crtc) { | |
a8cd6da0 VS |
14978 | struct intel_crtc_state *crtc_state = |
14979 | to_intel_crtc_state(crtc->base.state); | |
aca1ebf4 VS |
14980 | int pixclk = 0; |
14981 | ||
7f4c6284 | 14982 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); |
a8cd6da0 VS |
14983 | if (crtc_state->base.active) { |
14984 | intel_mode_from_pipe_config(&crtc->base.mode, crtc_state); | |
14985 | intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state); | |
7f4c6284 VS |
14986 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); |
14987 | ||
14988 | /* | |
14989 | * The initial mode needs to be set in order to keep | |
14990 | * the atomic core happy. It wants a valid mode if the | |
14991 | * crtc's enabled, so we do the above call. | |
14992 | * | |
7800fb69 DV |
14993 | * But we don't set all the derived state fully, hence |
14994 | * set a flag to indicate that a full recalculation is | |
14995 | * needed on the next commit. | |
7f4c6284 | 14996 | */ |
a8cd6da0 | 14997 | crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED; |
9eca6832 | 14998 | |
a7d1b3f4 VS |
14999 | intel_crtc_compute_pixel_rate(crtc_state); |
15000 | ||
15001 | if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) || | |
15002 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
15003 | pixclk = crtc_state->pixel_rate; | |
aca1ebf4 VS |
15004 | else |
15005 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
15006 | ||
15007 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
a8cd6da0 | 15008 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
aca1ebf4 VS |
15009 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); |
15010 | ||
5caa0fea DV |
15011 | drm_calc_timestamping_constants(&crtc->base, |
15012 | &crtc_state->base.adjusted_mode); | |
9eca6832 | 15013 | update_scanline_offset(crtc); |
7f4c6284 | 15014 | } |
e3b247da | 15015 | |
aca1ebf4 VS |
15016 | dev_priv->min_pixclk[crtc->pipe] = pixclk; |
15017 | ||
a8cd6da0 | 15018 | intel_pipe_config_sanity_check(dev_priv, crtc_state); |
7f4c6284 | 15019 | } |
30e984df DV |
15020 | } |
15021 | ||
62b69566 ACO |
15022 | static void |
15023 | get_encoder_power_domains(struct drm_i915_private *dev_priv) | |
15024 | { | |
15025 | struct intel_encoder *encoder; | |
15026 | ||
15027 | for_each_intel_encoder(&dev_priv->drm, encoder) { | |
15028 | u64 get_domains; | |
15029 | enum intel_display_power_domain domain; | |
15030 | ||
15031 | if (!encoder->get_power_domains) | |
15032 | continue; | |
15033 | ||
15034 | get_domains = encoder->get_power_domains(encoder); | |
15035 | for_each_power_domain(domain, get_domains) | |
15036 | intel_display_power_get(dev_priv, domain); | |
15037 | } | |
15038 | } | |
15039 | ||
043e9bda ML |
15040 | /* Scan out the current hw modeset state, |
15041 | * and sanitizes it to the current state | |
15042 | */ | |
15043 | static void | |
aecd36b8 VS |
15044 | intel_modeset_setup_hw_state(struct drm_device *dev, |
15045 | struct drm_modeset_acquire_ctx *ctx) | |
30e984df | 15046 | { |
fac5e23e | 15047 | struct drm_i915_private *dev_priv = to_i915(dev); |
30e984df | 15048 | enum pipe pipe; |
30e984df DV |
15049 | struct intel_crtc *crtc; |
15050 | struct intel_encoder *encoder; | |
35c95375 | 15051 | int i; |
30e984df DV |
15052 | |
15053 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
15054 | |
15055 | /* HW state is read out, now we need to sanitize this mess. */ | |
62b69566 ACO |
15056 | get_encoder_power_domains(dev_priv); |
15057 | ||
b2784e15 | 15058 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15059 | intel_sanitize_encoder(encoder); |
15060 | } | |
15061 | ||
055e393f | 15062 | for_each_pipe(dev_priv, pipe) { |
98187836 | 15063 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
e2af48c6 | 15064 | |
aecd36b8 | 15065 | intel_sanitize_crtc(crtc, ctx); |
6e3c9717 ACO |
15066 | intel_dump_pipe_config(crtc, crtc->config, |
15067 | "[setup_hw_state]"); | |
24929352 | 15068 | } |
9a935856 | 15069 | |
d29b2f9d ACO |
15070 | intel_modeset_update_connector_atomic_state(dev); |
15071 | ||
35c95375 DV |
15072 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15073 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15074 | ||
2dd66ebd | 15075 | if (!pll->on || pll->active_mask) |
35c95375 DV |
15076 | continue; |
15077 | ||
15078 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15079 | ||
2edd6443 | 15080 | pll->funcs.disable(dev_priv, pll); |
35c95375 DV |
15081 | pll->on = false; |
15082 | } | |
15083 | ||
04548cba VS |
15084 | if (IS_G4X(dev_priv)) { |
15085 | g4x_wm_get_hw_state(dev); | |
15086 | g4x_wm_sanitize(dev_priv); | |
15087 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
6eb1a681 | 15088 | vlv_wm_get_hw_state(dev); |
602ae835 VS |
15089 | vlv_wm_sanitize(dev_priv); |
15090 | } else if (IS_GEN9(dev_priv)) { | |
3078999f | 15091 | skl_wm_get_hw_state(dev); |
602ae835 | 15092 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
243e6a44 | 15093 | ilk_wm_get_hw_state(dev); |
602ae835 | 15094 | } |
292b990e ML |
15095 | |
15096 | for_each_intel_crtc(dev, crtc) { | |
d8fc70b7 | 15097 | u64 put_domains; |
292b990e | 15098 | |
74bff5f9 | 15099 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
292b990e ML |
15100 | if (WARN_ON(put_domains)) |
15101 | modeset_put_power_domains(dev_priv, put_domains); | |
15102 | } | |
15103 | intel_display_set_init_power(dev_priv, false); | |
010cf73d | 15104 | |
8d8c386c ID |
15105 | intel_power_domains_verify_state(dev_priv); |
15106 | ||
010cf73d | 15107 | intel_fbc_init_pipe_state(dev_priv); |
043e9bda | 15108 | } |
7d0bc1ea | 15109 | |
043e9bda ML |
15110 | void intel_display_resume(struct drm_device *dev) |
15111 | { | |
e2c8b870 ML |
15112 | struct drm_i915_private *dev_priv = to_i915(dev); |
15113 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
15114 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 15115 | int ret; |
f30da187 | 15116 | |
e2c8b870 | 15117 | dev_priv->modeset_restore_state = NULL; |
73974893 ML |
15118 | if (state) |
15119 | state->acquire_ctx = &ctx; | |
043e9bda | 15120 | |
e2c8b870 | 15121 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 15122 | |
73974893 ML |
15123 | while (1) { |
15124 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
15125 | if (ret != -EDEADLK) | |
15126 | break; | |
043e9bda | 15127 | |
e2c8b870 | 15128 | drm_modeset_backoff(&ctx); |
e2c8b870 | 15129 | } |
043e9bda | 15130 | |
73974893 | 15131 | if (!ret) |
581e49fe | 15132 | ret = __intel_display_resume(dev, state, &ctx); |
73974893 | 15133 | |
e2c8b870 ML |
15134 | drm_modeset_drop_locks(&ctx); |
15135 | drm_modeset_acquire_fini(&ctx); | |
043e9bda | 15136 | |
0853695c | 15137 | if (ret) |
e2c8b870 | 15138 | DRM_ERROR("Restoring old state failed with %i\n", ret); |
3c5e37f1 CW |
15139 | if (state) |
15140 | drm_atomic_state_put(state); | |
2c7111db CW |
15141 | } |
15142 | ||
15143 | void intel_modeset_gem_init(struct drm_device *dev) | |
15144 | { | |
dc97997a | 15145 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 15146 | |
dc97997a | 15147 | intel_init_gt_powersave(dev_priv); |
ae48434c | 15148 | |
1ee8da6d | 15149 | intel_setup_overlay(dev_priv); |
1ebaa0b9 CW |
15150 | } |
15151 | ||
15152 | int intel_connector_register(struct drm_connector *connector) | |
15153 | { | |
15154 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
15155 | int ret; | |
15156 | ||
15157 | ret = intel_backlight_device_register(intel_connector); | |
15158 | if (ret) | |
15159 | goto err; | |
15160 | ||
15161 | return 0; | |
0962c3c9 | 15162 | |
1ebaa0b9 CW |
15163 | err: |
15164 | return ret; | |
79e53945 JB |
15165 | } |
15166 | ||
c191eca1 | 15167 | void intel_connector_unregister(struct drm_connector *connector) |
4932e2c3 | 15168 | { |
e63d87c0 | 15169 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4932e2c3 | 15170 | |
e63d87c0 | 15171 | intel_backlight_device_unregister(intel_connector); |
4932e2c3 | 15172 | intel_panel_destroy_backlight(connector); |
4932e2c3 ID |
15173 | } |
15174 | ||
79e53945 JB |
15175 | void intel_modeset_cleanup(struct drm_device *dev) |
15176 | { | |
fac5e23e | 15177 | struct drm_i915_private *dev_priv = to_i915(dev); |
652c393a | 15178 | |
eb955eee CW |
15179 | flush_work(&dev_priv->atomic_helper.free_work); |
15180 | WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list)); | |
15181 | ||
dc97997a | 15182 | intel_disable_gt_powersave(dev_priv); |
2eb5252e | 15183 | |
fd0c0642 DV |
15184 | /* |
15185 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 15186 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
15187 | * experience fancy races otherwise. |
15188 | */ | |
2aeb7d3a | 15189 | intel_irq_uninstall(dev_priv); |
eb21b92b | 15190 | |
fd0c0642 DV |
15191 | /* |
15192 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
15193 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
15194 | */ | |
f87ea761 | 15195 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 15196 | |
4f256d82 DV |
15197 | /* poll work can call into fbdev, hence clean that up afterwards */ |
15198 | intel_fbdev_fini(dev_priv); | |
15199 | ||
723bfd70 JB |
15200 | intel_unregister_dsm_handler(); |
15201 | ||
c937ab3e | 15202 | intel_fbc_global_disable(dev_priv); |
69341a5e | 15203 | |
1630fe75 CW |
15204 | /* flush any delayed tasks or pending work */ |
15205 | flush_scheduled_work(); | |
15206 | ||
79e53945 | 15207 | drm_mode_config_cleanup(dev); |
4d7bb011 | 15208 | |
1ee8da6d | 15209 | intel_cleanup_overlay(dev_priv); |
ae48434c | 15210 | |
dc97997a | 15211 | intel_cleanup_gt_powersave(dev_priv); |
f5949141 | 15212 | |
40196446 | 15213 | intel_teardown_gmbus(dev_priv); |
79e53945 JB |
15214 | } |
15215 | ||
df0e9248 CW |
15216 | void intel_connector_attach_encoder(struct intel_connector *connector, |
15217 | struct intel_encoder *encoder) | |
15218 | { | |
15219 | connector->encoder = encoder; | |
15220 | drm_mode_connector_attach_encoder(&connector->base, | |
15221 | &encoder->base); | |
79e53945 | 15222 | } |
28d52043 DA |
15223 | |
15224 | /* | |
15225 | * set vga decode state - true == enable VGA decode | |
15226 | */ | |
6315b5d3 | 15227 | int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state) |
28d52043 | 15228 | { |
6315b5d3 | 15229 | unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
15230 | u16 gmch_ctrl; |
15231 | ||
75fa041d CW |
15232 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
15233 | DRM_ERROR("failed to read control word\n"); | |
15234 | return -EIO; | |
15235 | } | |
15236 | ||
c0cc8a55 CW |
15237 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
15238 | return 0; | |
15239 | ||
28d52043 DA |
15240 | if (state) |
15241 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
15242 | else | |
15243 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
15244 | |
15245 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
15246 | DRM_ERROR("failed to write control word\n"); | |
15247 | return -EIO; | |
15248 | } | |
15249 | ||
28d52043 DA |
15250 | return 0; |
15251 | } | |
c4a1d9e4 | 15252 | |
98a2f411 CW |
15253 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
15254 | ||
c4a1d9e4 | 15255 | struct intel_display_error_state { |
ff57f1b0 PZ |
15256 | |
15257 | u32 power_well_driver; | |
15258 | ||
63b66e5b CW |
15259 | int num_transcoders; |
15260 | ||
c4a1d9e4 CW |
15261 | struct intel_cursor_error_state { |
15262 | u32 control; | |
15263 | u32 position; | |
15264 | u32 base; | |
15265 | u32 size; | |
52331309 | 15266 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15267 | |
15268 | struct intel_pipe_error_state { | |
ddf9c536 | 15269 | bool power_domain_on; |
c4a1d9e4 | 15270 | u32 source; |
f301b1e1 | 15271 | u32 stat; |
52331309 | 15272 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15273 | |
15274 | struct intel_plane_error_state { | |
15275 | u32 control; | |
15276 | u32 stride; | |
15277 | u32 size; | |
15278 | u32 pos; | |
15279 | u32 addr; | |
15280 | u32 surface; | |
15281 | u32 tile_offset; | |
52331309 | 15282 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
15283 | |
15284 | struct intel_transcoder_error_state { | |
ddf9c536 | 15285 | bool power_domain_on; |
63b66e5b CW |
15286 | enum transcoder cpu_transcoder; |
15287 | ||
15288 | u32 conf; | |
15289 | ||
15290 | u32 htotal; | |
15291 | u32 hblank; | |
15292 | u32 hsync; | |
15293 | u32 vtotal; | |
15294 | u32 vblank; | |
15295 | u32 vsync; | |
15296 | } transcoder[4]; | |
c4a1d9e4 CW |
15297 | }; |
15298 | ||
15299 | struct intel_display_error_state * | |
c033666a | 15300 | intel_display_capture_error_state(struct drm_i915_private *dev_priv) |
c4a1d9e4 | 15301 | { |
c4a1d9e4 | 15302 | struct intel_display_error_state *error; |
63b66e5b CW |
15303 | int transcoders[] = { |
15304 | TRANSCODER_A, | |
15305 | TRANSCODER_B, | |
15306 | TRANSCODER_C, | |
15307 | TRANSCODER_EDP, | |
15308 | }; | |
c4a1d9e4 CW |
15309 | int i; |
15310 | ||
c033666a | 15311 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
63b66e5b CW |
15312 | return NULL; |
15313 | ||
9d1cb914 | 15314 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
15315 | if (error == NULL) |
15316 | return NULL; | |
15317 | ||
c033666a | 15318 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ff57f1b0 PZ |
15319 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
15320 | ||
055e393f | 15321 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 15322 | error->pipe[i].power_domain_on = |
f458ebbc DV |
15323 | __intel_display_power_is_enabled(dev_priv, |
15324 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 15325 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
15326 | continue; |
15327 | ||
5efb3e28 VS |
15328 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
15329 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
15330 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
15331 | |
15332 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
15333 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
c033666a | 15334 | if (INTEL_GEN(dev_priv) <= 3) { |
51889b35 | 15335 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
15336 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
15337 | } | |
c033666a | 15338 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
ca291363 | 15339 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
c033666a | 15340 | if (INTEL_GEN(dev_priv) >= 4) { |
c4a1d9e4 CW |
15341 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
15342 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
15343 | } | |
15344 | ||
c4a1d9e4 | 15345 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 15346 | |
c033666a | 15347 | if (HAS_GMCH_DISPLAY(dev_priv)) |
f301b1e1 | 15348 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
15349 | } |
15350 | ||
4d1de975 | 15351 | /* Note: this does not include DSI transcoders. */ |
c033666a | 15352 | error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes; |
2d1fe073 | 15353 | if (HAS_DDI(dev_priv)) |
63b66e5b CW |
15354 | error->num_transcoders++; /* Account for eDP. */ |
15355 | ||
15356 | for (i = 0; i < error->num_transcoders; i++) { | |
15357 | enum transcoder cpu_transcoder = transcoders[i]; | |
15358 | ||
ddf9c536 | 15359 | error->transcoder[i].power_domain_on = |
f458ebbc | 15360 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 15361 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 15362 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
15363 | continue; |
15364 | ||
63b66e5b CW |
15365 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
15366 | ||
15367 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
15368 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
15369 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
15370 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
15371 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
15372 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
15373 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
15374 | } |
15375 | ||
15376 | return error; | |
15377 | } | |
15378 | ||
edc3d884 MK |
15379 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
15380 | ||
c4a1d9e4 | 15381 | void |
edc3d884 | 15382 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
15383 | struct intel_display_error_state *error) |
15384 | { | |
5a4c6f1b | 15385 | struct drm_i915_private *dev_priv = m->i915; |
c4a1d9e4 CW |
15386 | int i; |
15387 | ||
63b66e5b CW |
15388 | if (!error) |
15389 | return; | |
15390 | ||
b7f05d4a | 15391 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes); |
8652744b | 15392 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
edc3d884 | 15393 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 15394 | error->power_well_driver); |
055e393f | 15395 | for_each_pipe(dev_priv, i) { |
edc3d884 | 15396 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 15397 | err_printf(m, " Power: %s\n", |
87ad3212 | 15398 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 15399 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 15400 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
15401 | |
15402 | err_printf(m, "Plane [%d]:\n", i); | |
15403 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
15404 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
5f56d5f9 | 15405 | if (INTEL_GEN(dev_priv) <= 3) { |
edc3d884 MK |
15406 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
15407 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 15408 | } |
772c2a51 | 15409 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
edc3d884 | 15410 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
5f56d5f9 | 15411 | if (INTEL_GEN(dev_priv) >= 4) { |
edc3d884 MK |
15412 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
15413 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
15414 | } |
15415 | ||
edc3d884 MK |
15416 | err_printf(m, "Cursor [%d]:\n", i); |
15417 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
15418 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
15419 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 15420 | } |
63b66e5b CW |
15421 | |
15422 | for (i = 0; i < error->num_transcoders; i++) { | |
da205630 | 15423 | err_printf(m, "CPU transcoder: %s\n", |
63b66e5b | 15424 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 15425 | err_printf(m, " Power: %s\n", |
87ad3212 | 15426 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
15427 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
15428 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
15429 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
15430 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
15431 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
15432 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
15433 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
15434 | } | |
c4a1d9e4 | 15435 | } |
98a2f411 CW |
15436 | |
15437 | #endif |