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drm/i915: Apply the g4x TLB miss w/a to SR watermarks as well
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB
1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB
28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
5d723d7a 37#include "intel_frontbuffer.h"
760285e7 38#include <drm/i915_drm.h>
79e53945 39#include "i915_drv.h"
57822dc6 40#include "i915_gem_clflush.h"
db18b6a6 41#include "intel_dsi.h"
e5510fac 42#include "i915_trace.h"
319c1d42 43#include <drm/drm_atomic.h>
c196e1d6 44#include <drm/drm_atomic_helper.h>
760285e7
DH
45#include <drm/drm_dp_helper.h>
46#include <drm/drm_crtc_helper.h>
465c120c
MR
47#include <drm/drm_plane_helper.h>
48#include <drm/drm_rect.h>
c0f372b3 49#include <linux/dma_remapping.h>
fd8e058a 50#include <linux/reservation.h>
79e53945 51
5a21b665
DV
52static bool is_mmio_work(struct intel_flip_work *work)
53{
54 return work->mmio_work.func;
55}
56
465c120c 57/* Primary plane formats for gen <= 3 */
568db4f2 58static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL
59 DRM_FORMAT_C8,
60 DRM_FORMAT_RGB565,
465c120c 61 DRM_FORMAT_XRGB1555,
67fe7dc5 62 DRM_FORMAT_XRGB8888,
465c120c
MR
63};
64
65/* Primary plane formats for gen >= 4 */
568db4f2 66static const uint32_t i965_primary_formats[] = {
6c0fd451
DL
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_XRGB2101010,
72 DRM_FORMAT_XBGR2101010,
73};
74
75static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL
76 DRM_FORMAT_C8,
77 DRM_FORMAT_RGB565,
78 DRM_FORMAT_XRGB8888,
465c120c 79 DRM_FORMAT_XBGR8888,
67fe7dc5 80 DRM_FORMAT_ARGB8888,
465c120c
MR
81 DRM_FORMAT_ABGR8888,
82 DRM_FORMAT_XRGB2101010,
465c120c 83 DRM_FORMAT_XBGR2101010,
ea916ea0
KM
84 DRM_FORMAT_YUYV,
85 DRM_FORMAT_YVYU,
86 DRM_FORMAT_UYVY,
87 DRM_FORMAT_VYUY,
465c120c
MR
88};
89
3d7d6510
MR
90/* Cursor formats */
91static const uint32_t intel_cursor_formats[] = {
92 DRM_FORMAT_ARGB8888,
93};
94
f1f644dc 95static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 96 struct intel_crtc_state *pipe_config);
18442d08 97static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 98 struct intel_crtc_state *pipe_config);
f1f644dc 99
24dbf51a
CW
100static int intel_framebuffer_init(struct intel_framebuffer *ifb,
101 struct drm_i915_gem_object *obj,
102 struct drm_mode_fb_cmd2 *mode_cmd);
5b18e57c
DV
103static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
104static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
bc58be60 105static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
29407aab 106static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK
107 struct intel_link_m_n *m_n,
108 struct intel_link_m_n *m2_n2);
29407aab 109static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97 110static void haswell_set_pipeconf(struct drm_crtc *crtc);
391bf048 111static void haswell_set_pipemisc(struct drm_crtc *crtc);
d288f65f 112static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 113 const struct intel_crtc_state *pipe_config);
d288f65f 114static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 115 const struct intel_crtc_state *pipe_config);
5a21b665
DV
116static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
117static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
1c74eeaf
NM
118static void intel_crtc_init_scalers(struct intel_crtc *crtc,
119 struct intel_crtc_state *crtc_state);
bfd16b2a
ML
120static void skylake_pfit_enable(struct intel_crtc *crtc);
121static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
122static void ironlake_pfit_enable(struct intel_crtc *crtc);
043e9bda 123static void intel_modeset_setup_hw_state(struct drm_device *dev);
2622a081 124static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
e7457a9a 125
d4906093 126struct intel_limit {
4c5def93
ACO
127 struct {
128 int min, max;
129 } dot, vco, n, m, m1, m2, p, p1;
130
131 struct {
132 int dot_limit;
133 int p2_slow, p2_fast;
134 } p2;
d4906093 135};
79e53945 136
bfa7df01 137/* returns HPLL frequency in kHz */
49cd97a3 138int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
bfa7df01
VS
139{
140 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
141
142 /* Obtain SKU information */
143 mutex_lock(&dev_priv->sb_lock);
144 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
145 CCK_FUSE_HPLL_FREQ_MASK;
146 mutex_unlock(&dev_priv->sb_lock);
147
148 return vco_freq[hpll_freq] * 1000;
149}
150
c30fec65
VS
151int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
152 const char *name, u32 reg, int ref_freq)
bfa7df01
VS
153{
154 u32 val;
155 int divider;
156
bfa7df01
VS
157 mutex_lock(&dev_priv->sb_lock);
158 val = vlv_cck_read(dev_priv, reg);
159 mutex_unlock(&dev_priv->sb_lock);
160
161 divider = val & CCK_FREQUENCY_VALUES;
162
163 WARN((val & CCK_FREQUENCY_STATUS) !=
164 (divider << CCK_FREQUENCY_STATUS_SHIFT),
165 "%s change in progress\n", name);
166
c30fec65
VS
167 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
168}
169
7ff89ca2
VS
170int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
171 const char *name, u32 reg)
c30fec65
VS
172{
173 if (dev_priv->hpll_freq == 0)
49cd97a3 174 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
c30fec65
VS
175
176 return vlv_get_cck_clock(dev_priv, name, reg,
177 dev_priv->hpll_freq);
bfa7df01
VS
178}
179
bfa7df01
VS
180static void intel_update_czclk(struct drm_i915_private *dev_priv)
181{
666a4537 182 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
bfa7df01
VS
183 return;
184
185 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
186 CCK_CZ_CLOCK_CONTROL);
187
188 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
189}
190
021357ac 191static inline u32 /* units of 100MHz */
21a727b3
VS
192intel_fdi_link_freq(struct drm_i915_private *dev_priv,
193 const struct intel_crtc_state *pipe_config)
021357ac 194{
21a727b3
VS
195 if (HAS_DDI(dev_priv))
196 return pipe_config->port_clock; /* SPLL */
197 else if (IS_GEN5(dev_priv))
198 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
e3b247da 199 else
21a727b3 200 return 270000;
021357ac
CW
201}
202
1b6f4958 203static const struct intel_limit intel_limits_i8xx_dac = {
0206e353 204 .dot = { .min = 25000, .max = 350000 },
9c333719 205 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 206 .n = { .min = 2, .max = 16 },
0206e353
AJ
207 .m = { .min = 96, .max = 140 },
208 .m1 = { .min = 18, .max = 26 },
209 .m2 = { .min = 6, .max = 16 },
210 .p = { .min = 4, .max = 128 },
211 .p1 = { .min = 2, .max = 33 },
273e27ca
EA
212 .p2 = { .dot_limit = 165000,
213 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP
214};
215
1b6f4958 216static const struct intel_limit intel_limits_i8xx_dvo = {
5d536e28 217 .dot = { .min = 25000, .max = 350000 },
9c333719 218 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 219 .n = { .min = 2, .max = 16 },
5d536e28
DV
220 .m = { .min = 96, .max = 140 },
221 .m1 = { .min = 18, .max = 26 },
222 .m2 = { .min = 6, .max = 16 },
223 .p = { .min = 4, .max = 128 },
224 .p1 = { .min = 2, .max = 33 },
225 .p2 = { .dot_limit = 165000,
226 .p2_slow = 4, .p2_fast = 4 },
227};
228
1b6f4958 229static const struct intel_limit intel_limits_i8xx_lvds = {
0206e353 230 .dot = { .min = 25000, .max = 350000 },
9c333719 231 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 232 .n = { .min = 2, .max = 16 },
0206e353
AJ
233 .m = { .min = 96, .max = 140 },
234 .m1 = { .min = 18, .max = 26 },
235 .m2 = { .min = 6, .max = 16 },
236 .p = { .min = 4, .max = 128 },
237 .p1 = { .min = 1, .max = 6 },
273e27ca
EA
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 14, .p2_fast = 7 },
e4b36699 240};
273e27ca 241
1b6f4958 242static const struct intel_limit intel_limits_i9xx_sdvo = {
0206e353
AJ
243 .dot = { .min = 20000, .max = 400000 },
244 .vco = { .min = 1400000, .max = 2800000 },
245 .n = { .min = 1, .max = 6 },
246 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ
247 .m1 = { .min = 8, .max = 18 },
248 .m2 = { .min = 3, .max = 7 },
0206e353
AJ
249 .p = { .min = 5, .max = 80 },
250 .p1 = { .min = 1, .max = 8 },
273e27ca
EA
251 .p2 = { .dot_limit = 200000,
252 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP
253};
254
1b6f4958 255static const struct intel_limit intel_limits_i9xx_lvds = {
0206e353
AJ
256 .dot = { .min = 20000, .max = 400000 },
257 .vco = { .min = 1400000, .max = 2800000 },
258 .n = { .min = 1, .max = 6 },
259 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ
260 .m1 = { .min = 8, .max = 18 },
261 .m2 = { .min = 3, .max = 7 },
0206e353
AJ
262 .p = { .min = 7, .max = 98 },
263 .p1 = { .min = 1, .max = 8 },
273e27ca
EA
264 .p2 = { .dot_limit = 112000,
265 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP
266};
267
273e27ca 268
1b6f4958 269static const struct intel_limit intel_limits_g4x_sdvo = {
273e27ca
EA
270 .dot = { .min = 25000, .max = 270000 },
271 .vco = { .min = 1750000, .max = 3500000},
272 .n = { .min = 1, .max = 4 },
273 .m = { .min = 104, .max = 138 },
274 .m1 = { .min = 17, .max = 23 },
275 .m2 = { .min = 5, .max = 11 },
276 .p = { .min = 10, .max = 30 },
277 .p1 = { .min = 1, .max = 3},
278 .p2 = { .dot_limit = 270000,
279 .p2_slow = 10,
280 .p2_fast = 10
044c7c41 281 },
e4b36699
KP
282};
283
1b6f4958 284static const struct intel_limit intel_limits_g4x_hdmi = {
273e27ca
EA
285 .dot = { .min = 22000, .max = 400000 },
286 .vco = { .min = 1750000, .max = 3500000},
287 .n = { .min = 1, .max = 4 },
288 .m = { .min = 104, .max = 138 },
289 .m1 = { .min = 16, .max = 23 },
290 .m2 = { .min = 5, .max = 11 },
291 .p = { .min = 5, .max = 80 },
292 .p1 = { .min = 1, .max = 8},
293 .p2 = { .dot_limit = 165000,
294 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP
295};
296
1b6f4958 297static const struct intel_limit intel_limits_g4x_single_channel_lvds = {
273e27ca
EA
298 .dot = { .min = 20000, .max = 115000 },
299 .vco = { .min = 1750000, .max = 3500000 },
300 .n = { .min = 1, .max = 3 },
301 .m = { .min = 104, .max = 138 },
302 .m1 = { .min = 17, .max = 23 },
303 .m2 = { .min = 5, .max = 11 },
304 .p = { .min = 28, .max = 112 },
305 .p1 = { .min = 2, .max = 8 },
306 .p2 = { .dot_limit = 0,
307 .p2_slow = 14, .p2_fast = 14
044c7c41 308 },
e4b36699
KP
309};
310
1b6f4958 311static const struct intel_limit intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA
312 .dot = { .min = 80000, .max = 224000 },
313 .vco = { .min = 1750000, .max = 3500000 },
314 .n = { .min = 1, .max = 3 },
315 .m = { .min = 104, .max = 138 },
316 .m1 = { .min = 17, .max = 23 },
317 .m2 = { .min = 5, .max = 11 },
318 .p = { .min = 14, .max = 42 },
319 .p1 = { .min = 2, .max = 6 },
320 .p2 = { .dot_limit = 0,
321 .p2_slow = 7, .p2_fast = 7
044c7c41 322 },
e4b36699
KP
323};
324
1b6f4958 325static const struct intel_limit intel_limits_pineview_sdvo = {
0206e353
AJ
326 .dot = { .min = 20000, .max = 400000},
327 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 328 /* Pineview's Ncounter is a ring counter */
0206e353
AJ
329 .n = { .min = 3, .max = 6 },
330 .m = { .min = 2, .max = 256 },
273e27ca 331 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ
332 .m1 = { .min = 0, .max = 0 },
333 .m2 = { .min = 0, .max = 254 },
334 .p = { .min = 5, .max = 80 },
335 .p1 = { .min = 1, .max = 8 },
273e27ca
EA
336 .p2 = { .dot_limit = 200000,
337 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP
338};
339
1b6f4958 340static const struct intel_limit intel_limits_pineview_lvds = {
0206e353
AJ
341 .dot = { .min = 20000, .max = 400000 },
342 .vco = { .min = 1700000, .max = 3500000 },
343 .n = { .min = 3, .max = 6 },
344 .m = { .min = 2, .max = 256 },
345 .m1 = { .min = 0, .max = 0 },
346 .m2 = { .min = 0, .max = 254 },
347 .p = { .min = 7, .max = 112 },
348 .p1 = { .min = 1, .max = 8 },
273e27ca
EA
349 .p2 = { .dot_limit = 112000,
350 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP
351};
352
273e27ca
EA
353/* Ironlake / Sandybridge
354 *
355 * We calculate clock using (register_value + 2) for N/M1/M2, so here
356 * the range value for them is (actual_value - 2).
357 */
1b6f4958 358static const struct intel_limit intel_limits_ironlake_dac = {
273e27ca
EA
359 .dot = { .min = 25000, .max = 350000 },
360 .vco = { .min = 1760000, .max = 3510000 },
361 .n = { .min = 1, .max = 5 },
362 .m = { .min = 79, .max = 127 },
363 .m1 = { .min = 12, .max = 22 },
364 .m2 = { .min = 5, .max = 9 },
365 .p = { .min = 5, .max = 80 },
366 .p1 = { .min = 1, .max = 8 },
367 .p2 = { .dot_limit = 225000,
368 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP
369};
370
1b6f4958 371static const struct intel_limit intel_limits_ironlake_single_lvds = {
273e27ca
EA
372 .dot = { .min = 25000, .max = 350000 },
373 .vco = { .min = 1760000, .max = 3510000 },
374 .n = { .min = 1, .max = 3 },
375 .m = { .min = 79, .max = 118 },
376 .m1 = { .min = 12, .max = 22 },
377 .m2 = { .min = 5, .max = 9 },
378 .p = { .min = 28, .max = 112 },
379 .p1 = { .min = 2, .max = 8 },
380 .p2 = { .dot_limit = 225000,
381 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW
382};
383
1b6f4958 384static const struct intel_limit intel_limits_ironlake_dual_lvds = {
273e27ca
EA
385 .dot = { .min = 25000, .max = 350000 },
386 .vco = { .min = 1760000, .max = 3510000 },
387 .n = { .min = 1, .max = 3 },
388 .m = { .min = 79, .max = 127 },
389 .m1 = { .min = 12, .max = 22 },
390 .m2 = { .min = 5, .max = 9 },
391 .p = { .min = 14, .max = 56 },
392 .p1 = { .min = 2, .max = 8 },
393 .p2 = { .dot_limit = 225000,
394 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW
395};
396
273e27ca 397/* LVDS 100mhz refclk limits. */
1b6f4958 398static const struct intel_limit intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA
399 .dot = { .min = 25000, .max = 350000 },
400 .vco = { .min = 1760000, .max = 3510000 },
401 .n = { .min = 1, .max = 2 },
402 .m = { .min = 79, .max = 126 },
403 .m1 = { .min = 12, .max = 22 },
404 .m2 = { .min = 5, .max = 9 },
405 .p = { .min = 28, .max = 112 },
0206e353 406 .p1 = { .min = 2, .max = 8 },
273e27ca
EA
407 .p2 = { .dot_limit = 225000,
408 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW
409};
410
1b6f4958 411static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA
412 .dot = { .min = 25000, .max = 350000 },
413 .vco = { .min = 1760000, .max = 3510000 },
414 .n = { .min = 1, .max = 3 },
415 .m = { .min = 79, .max = 126 },
416 .m1 = { .min = 12, .max = 22 },
417 .m2 = { .min = 5, .max = 9 },
418 .p = { .min = 14, .max = 42 },
0206e353 419 .p1 = { .min = 2, .max = 6 },
273e27ca
EA
420 .p2 = { .dot_limit = 225000,
421 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY
422};
423
1b6f4958 424static const struct intel_limit intel_limits_vlv = {
f01b7962
VS
425 /*
426 * These are the data rate limits (measured in fast clocks)
427 * since those are the strictest limits we have. The fast
428 * clock and actual rate limits are more relaxed, so checking
429 * them would make no difference.
430 */
431 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 432 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 433 .n = { .min = 1, .max = 7 },
a0c4da24
JB
434 .m1 = { .min = 2, .max = 3 },
435 .m2 = { .min = 11, .max = 156 },
b99ab663 436 .p1 = { .min = 2, .max = 3 },
5fdc9c49 437 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB
438};
439
1b6f4958 440static const struct intel_limit intel_limits_chv = {
ef9348c8
CML
441 /*
442 * These are the data rate limits (measured in fast clocks)
443 * since those are the strictest limits we have. The fast
444 * clock and actual rate limits are more relaxed, so checking
445 * them would make no difference.
446 */
447 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 448 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML
449 .n = { .min = 1, .max = 1 },
450 .m1 = { .min = 2, .max = 2 },
451 .m2 = { .min = 24 << 22, .max = 175 << 22 },
452 .p1 = { .min = 2, .max = 4 },
453 .p2 = { .p2_slow = 1, .p2_fast = 14 },
454};
455
1b6f4958 456static const struct intel_limit intel_limits_bxt = {
5ab7b0b7
ID
457 /* FIXME: find real dot limits */
458 .dot = { .min = 0, .max = INT_MAX },
e6292556 459 .vco = { .min = 4800000, .max = 6700000 },
5ab7b0b7
ID
460 .n = { .min = 1, .max = 1 },
461 .m1 = { .min = 2, .max = 2 },
462 /* FIXME: find real m2 limits */
463 .m2 = { .min = 2 << 22, .max = 255 << 22 },
464 .p1 = { .min = 2, .max = 4 },
465 .p2 = { .p2_slow = 1, .p2_fast = 20 },
466};
467
cdba954e
ACO
468static bool
469needs_modeset(struct drm_crtc_state *state)
470{
fc596660 471 return drm_atomic_crtc_needs_modeset(state);
cdba954e
ACO
472}
473
dccbea3b
ID
474/*
475 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
476 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
477 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
478 * The helpers' return value is the rate of the clock that is fed to the
479 * display engine's pipe which can be the above fast dot clock rate or a
480 * divided-down version of it.
481 */
f2b115e6 482/* m1 is reserved as 0 in Pineview, n is a ring counter */
9e2c8475 483static int pnv_calc_dpll_params(int refclk, struct dpll *clock)
79e53945 484{
2177832f
SL
485 clock->m = clock->m2 + 2;
486 clock->p = clock->p1 * clock->p2;
ed5ca77e 487 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 488 return 0;
fb03ac01
VS
489 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
490 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID
491
492 return clock->dot;
2177832f
SL
493}
494
7429e9d4
DV
495static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
496{
497 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
498}
499
9e2c8475 500static int i9xx_calc_dpll_params(int refclk, struct dpll *clock)
2177832f 501{
7429e9d4 502 clock->m = i9xx_dpll_compute_m(clock);
79e53945 503 clock->p = clock->p1 * clock->p2;
ed5ca77e 504 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
dccbea3b 505 return 0;
fb03ac01
VS
506 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
507 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID
508
509 return clock->dot;
79e53945
JB
510}
511
9e2c8475 512static int vlv_calc_dpll_params(int refclk, struct dpll *clock)
589eca67
ID
513{
514 clock->m = clock->m1 * clock->m2;
515 clock->p = clock->p1 * clock->p2;
516 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 517 return 0;
589eca67
ID
518 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
519 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID
520
521 return clock->dot / 5;
589eca67
ID
522}
523
9e2c8475 524int chv_calc_dpll_params(int refclk, struct dpll *clock)
ef9348c8
CML
525{
526 clock->m = clock->m1 * clock->m2;
527 clock->p = clock->p1 * clock->p2;
528 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 529 return 0;
ef9348c8
CML
530 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
531 clock->n << 22);
532 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID
533
534 return clock->dot / 5;
ef9348c8
CML
535}
536
7c04d1d9 537#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB
538/**
539 * Returns whether the given set of divisors are valid for a given refclk with
540 * the given connectors.
541 */
542
e2d214ae 543static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv,
1b6f4958 544 const struct intel_limit *limit,
9e2c8475 545 const struct dpll *clock)
79e53945 546{
f01b7962
VS
547 if (clock->n < limit->n.min || limit->n.max < clock->n)
548 INTELPllInvalid("n out of range\n");
79e53945 549 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 550 INTELPllInvalid("p1 out of range\n");
79e53945 551 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 552 INTELPllInvalid("m2 out of range\n");
79e53945 553 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 554 INTELPllInvalid("m1 out of range\n");
f01b7962 555
e2d214ae 556 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) &&
cc3f90f0 557 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv))
f01b7962
VS
558 if (clock->m1 <= clock->m2)
559 INTELPllInvalid("m1 <= m2\n");
560
e2d214ae 561 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
cc3f90f0 562 !IS_GEN9_LP(dev_priv)) {
f01b7962
VS
563 if (clock->p < limit->p.min || limit->p.max < clock->p)
564 INTELPllInvalid("p out of range\n");
565 if (clock->m < limit->m.min || limit->m.max < clock->m)
566 INTELPllInvalid("m out of range\n");
567 }
568
79e53945 569 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 570 INTELPllInvalid("vco out of range\n");
79e53945
JB
571 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
572 * connector, etc., rather than just a single range.
573 */
574 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 575 INTELPllInvalid("dot out of range\n");
79e53945
JB
576
577 return true;
578}
579
3b1429d9 580static int
1b6f4958 581i9xx_select_p2_div(const struct intel_limit *limit,
3b1429d9
VS
582 const struct intel_crtc_state *crtc_state,
583 int target)
79e53945 584{
3b1429d9 585 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 586
2d84d2b3 587 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 588 /*
a210b028
DV
589 * For LVDS just rely on its current settings for dual-channel.
590 * We haven't figured out how to reliably set up different
591 * single/dual channel state, if we even can.
79e53945 592 */
1974cad0 593 if (intel_is_dual_link_lvds(dev))
3b1429d9 594 return limit->p2.p2_fast;
79e53945 595 else
3b1429d9 596 return limit->p2.p2_slow;
79e53945
JB
597 } else {
598 if (target < limit->p2.dot_limit)
3b1429d9 599 return limit->p2.p2_slow;
79e53945 600 else
3b1429d9 601 return limit->p2.p2_fast;
79e53945 602 }
3b1429d9
VS
603}
604
70e8aa21
ACO
605/*
606 * Returns a set of divisors for the desired target clock with the given
607 * refclk, or FALSE. The returned values represent the clock equation:
608 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
609 *
610 * Target and reference clocks are specified in kHz.
611 *
612 * If match_clock is provided, then best_clock P divider must match the P
613 * divider from @match_clock used for LVDS downclocking.
614 */
3b1429d9 615static bool
1b6f4958 616i9xx_find_best_dpll(const struct intel_limit *limit,
3b1429d9 617 struct intel_crtc_state *crtc_state,
9e2c8475
ACO
618 int target, int refclk, struct dpll *match_clock,
619 struct dpll *best_clock)
3b1429d9
VS
620{
621 struct drm_device *dev = crtc_state->base.crtc->dev;
9e2c8475 622 struct dpll clock;
3b1429d9 623 int err = target;
79e53945 624
0206e353 625 memset(best_clock, 0, sizeof(*best_clock));
79e53945 626
3b1429d9
VS
627 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
628
42158660
ZY
629 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
630 clock.m1++) {
631 for (clock.m2 = limit->m2.min;
632 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 633 if (clock.m2 >= clock.m1)
42158660
ZY
634 break;
635 for (clock.n = limit->n.min;
636 clock.n <= limit->n.max; clock.n++) {
637 for (clock.p1 = limit->p1.min;
638 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB
639 int this_err;
640
dccbea3b 641 i9xx_calc_dpll_params(refclk, &clock);
e2d214ae
TU
642 if (!intel_PLL_is_valid(to_i915(dev),
643 limit,
ac58c3f0
DV
644 &clock))
645 continue;
646 if (match_clock &&
647 clock.p != match_clock->p)
648 continue;
649
650 this_err = abs(clock.dot - target);
651 if (this_err < err) {
652 *best_clock = clock;
653 err = this_err;
654 }
655 }
656 }
657 }
658 }
659
660 return (err != target);
661}
662
70e8aa21
ACO
663/*
664 * Returns a set of divisors for the desired target clock with the given
665 * refclk, or FALSE. The returned values represent the clock equation:
666 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
667 *
668 * Target and reference clocks are specified in kHz.
669 *
670 * If match_clock is provided, then best_clock P divider must match the P
671 * divider from @match_clock used for LVDS downclocking.
672 */
ac58c3f0 673static bool
1b6f4958 674pnv_find_best_dpll(const struct intel_limit *limit,
a93e255f 675 struct intel_crtc_state *crtc_state,
9e2c8475
ACO
676 int target, int refclk, struct dpll *match_clock,
677 struct dpll *best_clock)
79e53945 678{
3b1429d9 679 struct drm_device *dev = crtc_state->base.crtc->dev;
9e2c8475 680 struct dpll clock;
79e53945
JB
681 int err = target;
682
0206e353 683 memset(best_clock, 0, sizeof(*best_clock));
79e53945 684
3b1429d9
VS
685 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
686
42158660
ZY
687 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
688 clock.m1++) {
689 for (clock.m2 = limit->m2.min;
690 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY
691 for (clock.n = limit->n.min;
692 clock.n <= limit->n.max; clock.n++) {
693 for (clock.p1 = limit->p1.min;
694 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB
695 int this_err;
696
dccbea3b 697 pnv_calc_dpll_params(refclk, &clock);
e2d214ae
TU
698 if (!intel_PLL_is_valid(to_i915(dev),
699 limit,
1b894b59 700 &clock))
79e53945 701 continue;
cec2f356
SP
702 if (match_clock &&
703 clock.p != match_clock->p)
704 continue;
79e53945
JB
705
706 this_err = abs(clock.dot - target);
707 if (this_err < err) {
708 *best_clock = clock;
709 err = this_err;
710 }
711 }
712 }
713 }
714 }
715
716 return (err != target);
717}
718
997c030c
ACO
719/*
720 * Returns a set of divisors for the desired target clock with the given
721 * refclk, or FALSE. The returned values represent the clock equation:
722 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
70e8aa21
ACO
723 *
724 * Target and reference clocks are specified in kHz.
725 *
726 * If match_clock is provided, then best_clock P divider must match the P
727 * divider from @match_clock used for LVDS downclocking.
997c030c 728 */
d4906093 729static bool
1b6f4958 730g4x_find_best_dpll(const struct intel_limit *limit,
a93e255f 731 struct intel_crtc_state *crtc_state,
9e2c8475
ACO
732 int target, int refclk, struct dpll *match_clock,
733 struct dpll *best_clock)
d4906093 734{
3b1429d9 735 struct drm_device *dev = crtc_state->base.crtc->dev;
9e2c8475 736 struct dpll clock;
d4906093 737 int max_n;
3b1429d9 738 bool found = false;
6ba770dc
AJ
739 /* approximately equals target * 0.00585 */
740 int err_most = (target >> 8) + (target >> 9);
d4906093
ML
741
742 memset(best_clock, 0, sizeof(*best_clock));
3b1429d9
VS
743
744 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
745
d4906093 746 max_n = limit->n.max;
f77f13e2 747 /* based on hardware requirement, prefer smaller n to precision */
d4906093 748 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 749 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML
750 for (clock.m1 = limit->m1.max;
751 clock.m1 >= limit->m1.min; clock.m1--) {
752 for (clock.m2 = limit->m2.max;
753 clock.m2 >= limit->m2.min; clock.m2--) {
754 for (clock.p1 = limit->p1.max;
755 clock.p1 >= limit->p1.min; clock.p1--) {
756 int this_err;
757
dccbea3b 758 i9xx_calc_dpll_params(refclk, &clock);
e2d214ae
TU
759 if (!intel_PLL_is_valid(to_i915(dev),
760 limit,
1b894b59 761 &clock))
d4906093 762 continue;
1b894b59
CW
763
764 this_err = abs(clock.dot - target);
d4906093
ML
765 if (this_err < err_most) {
766 *best_clock = clock;
767 err_most = this_err;
768 max_n = clock.n;
769 found = true;
770 }
771 }
772 }
773 }
774 }
2c07245f
ZW
775 return found;
776}
777
d5dd62bd
ID
778/*
779 * Check if the calculated PLL configuration is more optimal compared to the
780 * best configuration and error found so far. Return the calculated error.
781 */
782static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
9e2c8475
ACO
783 const struct dpll *calculated_clock,
784 const struct dpll *best_clock,
d5dd62bd
ID
785 unsigned int best_error_ppm,
786 unsigned int *error_ppm)
787{
9ca3ba01
ID
788 /*
789 * For CHV ignore the error and consider only the P value.
790 * Prefer a bigger P value based on HW requirements.
791 */
920a14b2 792 if (IS_CHERRYVIEW(to_i915(dev))) {
9ca3ba01
ID
793 *error_ppm = 0;
794
795 return calculated_clock->p > best_clock->p;
796 }
797
24be4e46
ID
798 if (WARN_ON_ONCE(!target_freq))
799 return false;
800
d5dd62bd
ID
801 *error_ppm = div_u64(1000000ULL *
802 abs(target_freq - calculated_clock->dot),
803 target_freq);
804 /*
805 * Prefer a better P value over a better (smaller) error if the error
806 * is small. Ensure this preference for future configurations too by
807 * setting the error to 0.
808 */
809 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
810 *error_ppm = 0;
811
812 return true;
813 }
814
815 return *error_ppm + 10 < best_error_ppm;
816}
817
65b3d6a9
ACO
818/*
819 * Returns a set of divisors for the desired target clock with the given
820 * refclk, or FALSE. The returned values represent the clock equation:
821 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
822 */
a0c4da24 823static bool
1b6f4958 824vlv_find_best_dpll(const struct intel_limit *limit,
a93e255f 825 struct intel_crtc_state *crtc_state,
9e2c8475
ACO
826 int target, int refclk, struct dpll *match_clock,
827 struct dpll *best_clock)
a0c4da24 828{
a93e255f 829 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 830 struct drm_device *dev = crtc->base.dev;
9e2c8475 831 struct dpll clock;
69e4f900 832 unsigned int bestppm = 1000000;
27e639bf
VS
833 /* min update 19.2 MHz */
834 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 835 bool found = false;
a0c4da24 836
6b4bf1c4
VS
837 target *= 5; /* fast clock */
838
839 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB
840
841 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 842 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 843 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 844 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 845 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 846 clock.p = clock.p1 * clock.p2;
a0c4da24 847 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 848 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 849 unsigned int ppm;
69e4f900 850
6b4bf1c4
VS
851 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
852 refclk * clock.m1);
853
dccbea3b 854 vlv_calc_dpll_params(refclk, &clock);
43b0ac53 855
e2d214ae
TU
856 if (!intel_PLL_is_valid(to_i915(dev),
857 limit,
f01b7962 858 &clock))
43b0ac53
VS
859 continue;
860
d5dd62bd
ID
861 if (!vlv_PLL_is_optimal(dev, target,
862 &clock,
863 best_clock,
864 bestppm, &ppm))
865 continue;
6b4bf1c4 866
d5dd62bd
ID
867 *best_clock = clock;
868 bestppm = ppm;
869 found = true;
a0c4da24
JB
870 }
871 }
872 }
873 }
a0c4da24 874
49e497ef 875 return found;
a0c4da24 876}
a4fc5ed6 877
65b3d6a9
ACO
878/*
879 * Returns a set of divisors for the desired target clock with the given
880 * refclk, or FALSE. The returned values represent the clock equation:
881 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
882 */
ef9348c8 883static bool
1b6f4958 884chv_find_best_dpll(const struct intel_limit *limit,
a93e255f 885 struct intel_crtc_state *crtc_state,
9e2c8475
ACO
886 int target, int refclk, struct dpll *match_clock,
887 struct dpll *best_clock)
ef9348c8 888{
a93e255f 889 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 890 struct drm_device *dev = crtc->base.dev;
9ca3ba01 891 unsigned int best_error_ppm;
9e2c8475 892 struct dpll clock;
ef9348c8
CML
893 uint64_t m2;
894 int found = false;
895
896 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 897 best_error_ppm = 1000000;
ef9348c8
CML
898
899 /*
900 * Based on hardware doc, the n always set to 1, and m1 always
901 * set to 2. If requires to support 200Mhz refclk, we need to
902 * revisit this because n may not 1 anymore.
903 */
904 clock.n = 1, clock.m1 = 2;
905 target *= 5; /* fast clock */
906
907 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
908 for (clock.p2 = limit->p2.p2_fast;
909 clock.p2 >= limit->p2.p2_slow;
910 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 911 unsigned int error_ppm;
ef9348c8
CML
912
913 clock.p = clock.p1 * clock.p2;
914
915 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
916 clock.n) << 22, refclk * clock.m1);
917
918 if (m2 > INT_MAX/clock.m1)
919 continue;
920
921 clock.m2 = m2;
922
dccbea3b 923 chv_calc_dpll_params(refclk, &clock);
ef9348c8 924
e2d214ae 925 if (!intel_PLL_is_valid(to_i915(dev), limit, &clock))
ef9348c8
CML
926 continue;
927
9ca3ba01
ID
928 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
929 best_error_ppm, &error_ppm))
930 continue;
931
932 *best_clock = clock;
933 best_error_ppm = error_ppm;
934 found = true;
ef9348c8
CML
935 }
936 }
937
938 return found;
939}
940
5ab7b0b7 941bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
9e2c8475 942 struct dpll *best_clock)
5ab7b0b7 943{
65b3d6a9 944 int refclk = 100000;
1b6f4958 945 const struct intel_limit *limit = &intel_limits_bxt;
5ab7b0b7 946
65b3d6a9 947 return chv_find_best_dpll(limit, crtc_state,
5ab7b0b7
ID
948 target_clock, refclk, NULL, best_clock);
949}
950
525b9311 951bool intel_crtc_active(struct intel_crtc *crtc)
20ddf665 952{
20ddf665
VS
953 /* Be paranoid as we can arrive here with only partial
954 * state retrieved from the hardware during setup.
955 *
241bfc38 956 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS
957 * as Haswell has gained clock readout/fastboot support.
958 *
66e514c1 959 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 960 * properly reconstruct framebuffers.
c3d1f436
MR
961 *
962 * FIXME: The intel_crtc->active here should be switched to
963 * crtc->state->active once we have proper CRTC states wired up
964 * for atomic.
20ddf665 965 */
525b9311
VS
966 return crtc->active && crtc->base.primary->state->fb &&
967 crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS
968}
969
a5c961d1
PZ
970enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
971 enum pipe pipe)
972{
98187836 973 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
a5c961d1 974
e2af48c6 975 return crtc->config->cpu_transcoder;
a5c961d1
PZ
976}
977
6315b5d3 978static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe)
fbf49ea2 979{
f0f59a00 980 i915_reg_t reg = PIPEDSL(pipe);
fbf49ea2
VS
981 u32 line1, line2;
982 u32 line_mask;
983
5db94019 984 if (IS_GEN2(dev_priv))
fbf49ea2
VS
985 line_mask = DSL_LINEMASK_GEN2;
986 else
987 line_mask = DSL_LINEMASK_GEN3;
988
989 line1 = I915_READ(reg) & line_mask;
6adfb1ef 990 msleep(5);
fbf49ea2
VS
991 line2 = I915_READ(reg) & line_mask;
992
993 return line1 == line2;
994}
995
ab7ad7f6
KP
996/*
997 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 998 * @crtc: crtc whose pipe to wait for
9d0498a2
JB
999 *
1000 * After disabling a pipe, we can't wait for vblank in the usual way,
1001 * spinning on the vblank interrupt status bit, since we won't actually
1002 * see an interrupt when the pipe is disabled.
1003 *
ab7ad7f6
KP
1004 * On Gen4 and above:
1005 * wait for the pipe register state bit to turn off
1006 *
1007 * Otherwise:
1008 * wait for the display line value to settle (it usually
1009 * ends up stopping at the start of the next frame).
58e10eb9 1010 *
9d0498a2 1011 */
575f7ab7 1012static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1013{
6315b5d3 1014 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6e3c9717 1015 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1016 enum pipe pipe = crtc->pipe;
ab7ad7f6 1017
6315b5d3 1018 if (INTEL_GEN(dev_priv) >= 4) {
f0f59a00 1019 i915_reg_t reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP
1020
1021 /* Wait for the Pipe State to go off */
b8511f53
CW
1022 if (intel_wait_for_register(dev_priv,
1023 reg, I965_PIPECONF_ACTIVE, 0,
1024 100))
284637d9 1025 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1026 } else {
ab7ad7f6 1027 /* Wait for the display line to settle */
6315b5d3 1028 if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100))
284637d9 1029 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1030 }
79e53945
JB
1031}
1032
b24e7179 1033/* Only for pre-ILK configs */
55607e8a
DV
1034void assert_pll(struct drm_i915_private *dev_priv,
1035 enum pipe pipe, bool state)
b24e7179 1036{
b24e7179
JB
1037 u32 val;
1038 bool cur_state;
1039
649636ef 1040 val = I915_READ(DPLL(pipe));
b24e7179 1041 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1042 I915_STATE_WARN(cur_state != state,
b24e7179 1043 "PLL state assertion failure (expected %s, current %s)\n",
87ad3212 1044 onoff(state), onoff(cur_state));
b24e7179 1045}
b24e7179 1046
23538ef1 1047/* XXX: the dsi pll is shared between MIPI DSI ports */
8563b1e8 1048void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
23538ef1
JN
1049{
1050 u32 val;
1051 bool cur_state;
1052
a580516d 1053 mutex_lock(&dev_priv->sb_lock);
23538ef1 1054 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1055 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN
1056
1057 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1058 I915_STATE_WARN(cur_state != state,
23538ef1 1059 "DSI PLL state assertion failure (expected %s, current %s)\n",
87ad3212 1060 onoff(state), onoff(cur_state));
23538ef1 1061}
23538ef1 1062
040484af
JB
1063static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1064 enum pipe pipe, bool state)
1065{
040484af 1066 bool cur_state;
ad80a810
PZ
1067 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1068 pipe);
040484af 1069
2d1fe073 1070 if (HAS_DDI(dev_priv)) {
affa9354 1071 /* DDI does not have a specific FDI_TX register */
649636ef 1072 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
ad80a810 1073 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7 1074 } else {
649636ef 1075 u32 val = I915_READ(FDI_TX_CTL(pipe));
bf507ef7
ED
1076 cur_state = !!(val & FDI_TX_ENABLE);
1077 }
e2c719b7 1078 I915_STATE_WARN(cur_state != state,
040484af 1079 "FDI TX state assertion failure (expected %s, current %s)\n",
87ad3212 1080 onoff(state), onoff(cur_state));
040484af
JB
1081}
1082#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1083#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1084
1085static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1086 enum pipe pipe, bool state)
1087{
040484af
JB
1088 u32 val;
1089 bool cur_state;
1090
649636ef 1091 val = I915_READ(FDI_RX_CTL(pipe));
d63fa0dc 1092 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1093 I915_STATE_WARN(cur_state != state,
040484af 1094 "FDI RX state assertion failure (expected %s, current %s)\n",
87ad3212 1095 onoff(state), onoff(cur_state));
040484af
JB
1096}
1097#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1098#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1099
1100static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1101 enum pipe pipe)
1102{
040484af
JB
1103 u32 val;
1104
1105 /* ILK FDI PLL is always enabled */
7e22dbbb 1106 if (IS_GEN5(dev_priv))
040484af
JB
1107 return;
1108
bf507ef7 1109 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
2d1fe073 1110 if (HAS_DDI(dev_priv))
bf507ef7
ED
1111 return;
1112
649636ef 1113 val = I915_READ(FDI_TX_CTL(pipe));
e2c719b7 1114 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB
1115}
1116
55607e8a
DV
1117void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1118 enum pipe pipe, bool state)
040484af 1119{
040484af 1120 u32 val;
55607e8a 1121 bool cur_state;
040484af 1122
649636ef 1123 val = I915_READ(FDI_RX_CTL(pipe));
55607e8a 1124 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1125 I915_STATE_WARN(cur_state != state,
55607e8a 1126 "FDI RX PLL assertion failure (expected %s, current %s)\n",
87ad3212 1127 onoff(state), onoff(cur_state));
040484af
JB
1128}
1129
4f8036a2 1130void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe)
ea0760cf 1131{
f0f59a00 1132 i915_reg_t pp_reg;
ea0760cf
JB
1133 u32 val;
1134 enum pipe panel_pipe = PIPE_A;
0de3b485 1135 bool locked = true;
ea0760cf 1136
4f8036a2 1137 if (WARN_ON(HAS_DDI(dev_priv)))
bedd4dba
JN
1138 return;
1139
4f8036a2 1140 if (HAS_PCH_SPLIT(dev_priv)) {
bedd4dba
JN
1141 u32 port_sel;
1142
44cb734c
ID
1143 pp_reg = PP_CONTROL(0);
1144 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK;
bedd4dba
JN
1145
1146 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1147 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1148 panel_pipe = PIPE_B;
1149 /* XXX: else fix for eDP */
4f8036a2 1150 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
bedd4dba 1151 /* presumably write lock depends on pipe, not port select */
44cb734c 1152 pp_reg = PP_CONTROL(pipe);
bedd4dba 1153 panel_pipe = pipe;
ea0760cf 1154 } else {
44cb734c 1155 pp_reg = PP_CONTROL(0);
bedd4dba
JN
1156 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1157 panel_pipe = PIPE_B;
ea0760cf
JB
1158 }
1159
1160 val = I915_READ(pp_reg);
1161 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1162 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB
1163 locked = false;
1164
e2c719b7 1165 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1166 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1167 pipe_name(pipe));
ea0760cf
JB
1168}
1169
93ce0ba6
JN
1170static void assert_cursor(struct drm_i915_private *dev_priv,
1171 enum pipe pipe, bool state)
1172{
93ce0ba6
JN
1173 bool cur_state;
1174
2a307c2e 1175 if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
0b87c24e 1176 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
d9d82081 1177 else
5efb3e28 1178 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1179
e2c719b7 1180 I915_STATE_WARN(cur_state != state,
93ce0ba6 1181 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
87ad3212 1182 pipe_name(pipe), onoff(state), onoff(cur_state));
93ce0ba6
JN
1183}
1184#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1185#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1186
b840d907
JB
1187void assert_pipe(struct drm_i915_private *dev_priv,
1188 enum pipe pipe, bool state)
b24e7179 1189{
63d7bbe9 1190 bool cur_state;
702e7a56
PZ
1191 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1192 pipe);
4feed0eb 1193 enum intel_display_power_domain power_domain;
b24e7179 1194
b6b5d049
VS
1195 /* if we need the pipe quirk it must be always on */
1196 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1197 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV
1198 state = true;
1199
4feed0eb
ID
1200 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1201 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
649636ef 1202 u32 val = I915_READ(PIPECONF(cpu_transcoder));
69310161 1203 cur_state = !!(val & PIPECONF_ENABLE);
4feed0eb
ID
1204
1205 intel_display_power_put(dev_priv, power_domain);
1206 } else {
1207 cur_state = false;
69310161
PZ
1208 }
1209
e2c719b7 1210 I915_STATE_WARN(cur_state != state,
63d7bbe9 1211 "pipe %c assertion failure (expected %s, current %s)\n",
87ad3212 1212 pipe_name(pipe), onoff(state), onoff(cur_state));
b24e7179
JB
1213}
1214
931872fc
CW
1215static void assert_plane(struct drm_i915_private *dev_priv,
1216 enum plane plane, bool state)
b24e7179 1217{
b24e7179 1218 u32 val;
931872fc 1219 bool cur_state;
b24e7179 1220
649636ef 1221 val = I915_READ(DSPCNTR(plane));
931872fc 1222 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1223 I915_STATE_WARN(cur_state != state,
931872fc 1224 "plane %c assertion failure (expected %s, current %s)\n",
87ad3212 1225 plane_name(plane), onoff(state), onoff(cur_state));
b24e7179
JB
1226}
1227
931872fc
CW
1228#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1229#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1230
b24e7179
JB
1231static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1232 enum pipe pipe)
1233{
649636ef 1234 int i;
b24e7179 1235
653e1026 1236 /* Primary planes are fixed to pipes on gen4+ */
6315b5d3 1237 if (INTEL_GEN(dev_priv) >= 4) {
649636ef 1238 u32 val = I915_READ(DSPCNTR(pipe));
e2c719b7 1239 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ
1240 "plane %c assertion failure, should be disabled but not\n",
1241 plane_name(pipe));
19ec1358 1242 return;
28c05794 1243 }
19ec1358 1244
b24e7179 1245 /* Need to check both planes against the pipe */
055e393f 1246 for_each_pipe(dev_priv, i) {
649636ef
VS
1247 u32 val = I915_READ(DSPCNTR(i));
1248 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
b24e7179 1249 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1250 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB
1251 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1252 plane_name(i), pipe_name(pipe));
b24e7179
JB
1253 }
1254}
1255
19332d7a
JB
1256static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1257 enum pipe pipe)
1258{
649636ef 1259 int sprite;
19332d7a 1260
6315b5d3 1261 if (INTEL_GEN(dev_priv) >= 9) {
3bdcfc0c 1262 for_each_sprite(dev_priv, pipe, sprite) {
649636ef 1263 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1264 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL
1265 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1266 sprite, pipe_name(pipe));
1267 }
920a14b2 1268 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3bdcfc0c 1269 for_each_sprite(dev_priv, pipe, sprite) {
83c04a62 1270 u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite));
e2c719b7 1271 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1272 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1273 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef 1274 }
6315b5d3 1275 } else if (INTEL_GEN(dev_priv) >= 7) {
649636ef 1276 u32 val = I915_READ(SPRCTL(pipe));
e2c719b7 1277 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1278 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1279 plane_name(pipe), pipe_name(pipe));
6315b5d3 1280 } else if (INTEL_GEN(dev_priv) >= 5) {
649636ef 1281 u32 val = I915_READ(DVSCNTR(pipe));
e2c719b7 1282 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1283 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1284 plane_name(pipe), pipe_name(pipe));
19332d7a
JB
1285 }
1286}
1287
08c71e5e
VS
1288static void assert_vblank_disabled(struct drm_crtc *crtc)
1289{
e2c719b7 1290 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS
1291 drm_crtc_vblank_put(crtc);
1292}
1293
7abd4b35
ACO
1294void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1295 enum pipe pipe)
92f2584a 1296{
92f2584a
JB
1297 u32 val;
1298 bool enabled;
1299
649636ef 1300 val = I915_READ(PCH_TRANSCONF(pipe));
92f2584a 1301 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1302 I915_STATE_WARN(enabled,
9db4a9c7
JB
1303 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1304 pipe_name(pipe));
92f2584a
JB
1305}
1306
4e634389
KP
1307static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1308 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP
1309{
1310 if ((val & DP_PORT_EN) == 0)
1311 return false;
1312
2d1fe073 1313 if (HAS_PCH_CPT(dev_priv)) {
f0f59a00 1314 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
f0575e92
KP
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316 return false;
2d1fe073 1317 } else if (IS_CHERRYVIEW(dev_priv)) {
44f37d1f
CML
1318 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1319 return false;
f0575e92
KP
1320 } else {
1321 if ((val & DP_PIPE_MASK) != (pipe << 30))
1322 return false;
1323 }
1324 return true;
1325}
1326
1519b995
KP
1327static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1328 enum pipe pipe, u32 val)
1329{
dc0fa718 1330 if ((val & SDVO_ENABLE) == 0)
1519b995
KP
1331 return false;
1332
2d1fe073 1333 if (HAS_PCH_CPT(dev_priv)) {
dc0fa718 1334 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1335 return false;
2d1fe073 1336 } else if (IS_CHERRYVIEW(dev_priv)) {
44f37d1f
CML
1337 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1338 return false;
1519b995 1339 } else {
dc0fa718 1340 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP
1341 return false;
1342 }
1343 return true;
1344}
1345
1346static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1347 enum pipe pipe, u32 val)
1348{
1349 if ((val & LVDS_PORT_EN) == 0)
1350 return false;
1351
2d1fe073 1352 if (HAS_PCH_CPT(dev_priv)) {
1519b995
KP
1353 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1354 return false;
1355 } else {
1356 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1357 return false;
1358 }
1359 return true;
1360}
1361
1362static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1363 enum pipe pipe, u32 val)
1364{
1365 if ((val & ADPA_DAC_ENABLE) == 0)
1366 return false;
2d1fe073 1367 if (HAS_PCH_CPT(dev_priv)) {
1519b995
KP
1368 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1369 return false;
1370 } else {
1371 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1372 return false;
1373 }
1374 return true;
1375}
1376
291906f1 1377static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0f59a00
VS
1378 enum pipe pipe, i915_reg_t reg,
1379 u32 port_sel)
291906f1 1380{
47a05eca 1381 u32 val = I915_READ(reg);
e2c719b7 1382 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1383 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
f0f59a00 1384 i915_mmio_reg_offset(reg), pipe_name(pipe));
de9a35ab 1385
2d1fe073 1386 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0
75c5da27 1387 && (val & DP_PIPEB_SELECT),
de9a35ab 1388 "IBX PCH dp port still using transcoder B\n");
291906f1
JB
1389}
1390
1391static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
f0f59a00 1392 enum pipe pipe, i915_reg_t reg)
291906f1 1393{
47a05eca 1394 u32 val = I915_READ(reg);
e2c719b7 1395 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1396 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
f0f59a00 1397 i915_mmio_reg_offset(reg), pipe_name(pipe));
de9a35ab 1398
2d1fe073 1399 I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0
75c5da27 1400 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1401 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB
1402}
1403
1404static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1405 enum pipe pipe)
1406{
291906f1 1407 u32 val;
291906f1 1408
f0575e92
KP
1409 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1410 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1411 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1 1412
649636ef 1413 val = I915_READ(PCH_ADPA);
e2c719b7 1414 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1415 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1416 pipe_name(pipe));
291906f1 1417
649636ef 1418 val = I915_READ(PCH_LVDS);
e2c719b7 1419 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1420 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1421 pipe_name(pipe));
291906f1 1422
e2debe91
PZ
1423 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1424 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1425 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB
1426}
1427
cd2d34d9
VS
1428static void _vlv_enable_pll(struct intel_crtc *crtc,
1429 const struct intel_crtc_state *pipe_config)
1430{
1431 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1432 enum pipe pipe = crtc->pipe;
1433
1434 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1435 POSTING_READ(DPLL(pipe));
1436 udelay(150);
1437
2c30b43b
CW
1438 if (intel_wait_for_register(dev_priv,
1439 DPLL(pipe),
1440 DPLL_LOCK_VLV,
1441 DPLL_LOCK_VLV,
1442 1))
cd2d34d9
VS
1443 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1444}
1445
d288f65f 1446static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1447 const struct intel_crtc_state *pipe_config)
87442f73 1448{
cd2d34d9 1449 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8bd3f301 1450 enum pipe pipe = crtc->pipe;
87442f73 1451
8bd3f301 1452 assert_pipe_disabled(dev_priv, pipe);
87442f73 1453
87442f73 1454 /* PLL is protected by panel, make sure we can write it */
7d1a83cb 1455 assert_panel_unlocked(dev_priv, pipe);
87442f73 1456
cd2d34d9
VS
1457 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1458 _vlv_enable_pll(crtc, pipe_config);
426115cf 1459
8bd3f301
VS
1460 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1461 POSTING_READ(DPLL_MD(pipe));
87442f73
DV
1462}
1463
cd2d34d9
VS
1464
1465static void _chv_enable_pll(struct intel_crtc *crtc,
1466 const struct intel_crtc_state *pipe_config)
9d556c99 1467{
cd2d34d9 1468 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
8bd3f301 1469 enum pipe pipe = crtc->pipe;
9d556c99 1470 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML
1471 u32 tmp;
1472
a580516d 1473 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML
1474
1475 /* Enable back the 10bit clock to display controller */
1476 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1477 tmp |= DPIO_DCLKP_EN;
1478 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1479
54433e91
VS
1480 mutex_unlock(&dev_priv->sb_lock);
1481
9d556c99
CML
1482 /*
1483 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1484 */
1485 udelay(1);
1486
1487 /* Enable PLL */
d288f65f 1488 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML
1489
1490 /* Check PLL is locked */
6b18826a
CW
1491 if (intel_wait_for_register(dev_priv,
1492 DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV,
1493 1))
9d556c99 1494 DRM_ERROR("PLL %d failed to lock\n", pipe);
cd2d34d9
VS
1495}
1496
1497static void chv_enable_pll(struct intel_crtc *crtc,
1498 const struct intel_crtc_state *pipe_config)
1499{
1500 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1501 enum pipe pipe = crtc->pipe;
1502
1503 assert_pipe_disabled(dev_priv, pipe);
1504
1505 /* PLL is protected by panel, make sure we can write it */
1506 assert_panel_unlocked(dev_priv, pipe);
1507
1508 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)
1509 _chv_enable_pll(crtc, pipe_config);
9d556c99 1510
c231775c
VS
1511 if (pipe != PIPE_A) {
1512 /*
1513 * WaPixelRepeatModeFixForC0:chv
1514 *
1515 * DPLLCMD is AWOL. Use chicken bits to propagate
1516 * the value from DPLLBMD to either pipe B or C.
1517 */
1518 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1519 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1520 I915_WRITE(CBR4_VLV, 0);
1521 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1522
1523 /*
1524 * DPLLB VGA mode also seems to cause problems.
1525 * We should always have it disabled.
1526 */
1527 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1528 } else {
1529 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1530 POSTING_READ(DPLL_MD(pipe));
1531 }
9d556c99
CML
1532}
1533
6315b5d3 1534static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv)
1c4e0274
VS
1535{
1536 struct intel_crtc *crtc;
1537 int count = 0;
1538
6315b5d3 1539 for_each_intel_crtc(&dev_priv->drm, crtc) {
3538b9df 1540 count += crtc->base.state->active &&
2d84d2b3
VS
1541 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO);
1542 }
1c4e0274
VS
1543
1544 return count;
1545}
1546
66e3d5c0 1547static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1548{
6315b5d3 1549 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
f0f59a00 1550 i915_reg_t reg = DPLL(crtc->pipe);
6e3c9717 1551 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1552
66e3d5c0 1553 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1554
63d7bbe9 1555 /* PLL is protected by panel, make sure we can write it */
50a0bc90 1556 if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
66e3d5c0 1557 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1558
1c4e0274 1559 /* Enable DVO 2x clock on both PLLs if necessary */
6315b5d3 1560 if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) {
1c4e0274
VS
1561 /*
1562 * It appears to be important that we don't enable this
1563 * for the current pipe before otherwise configuring the
1564 * PLL. No idea how this should be handled if multiple
1565 * DVO outputs are enabled simultaneosly.
1566 */
1567 dpll |= DPLL_DVO_2X_MODE;
1568 I915_WRITE(DPLL(!crtc->pipe),
1569 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1570 }
66e3d5c0 1571
c2b63374
VS
1572 /*
1573 * Apparently we need to have VGA mode enabled prior to changing
1574 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1575 * dividers, even though the register value does change.
1576 */
1577 I915_WRITE(reg, 0);
1578
8e7a65aa
VS
1579 I915_WRITE(reg, dpll);
1580
66e3d5c0
DV
1581 /* Wait for the clocks to stabilize. */
1582 POSTING_READ(reg);
1583 udelay(150);
1584
6315b5d3 1585 if (INTEL_GEN(dev_priv) >= 4) {
66e3d5c0 1586 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1587 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV
1588 } else {
1589 /* The pixel multiplier can only be updated once the
1590 * DPLL is enabled and the clocks are stable.
1591 *
1592 * So write it again.
1593 */
1594 I915_WRITE(reg, dpll);
1595 }
63d7bbe9
JB
1596
1597 /* We do this three times for luck */
66e3d5c0 1598 I915_WRITE(reg, dpll);
63d7bbe9
JB
1599 POSTING_READ(reg);
1600 udelay(150); /* wait for warmup */
66e3d5c0 1601 I915_WRITE(reg, dpll);
63d7bbe9
JB
1602 POSTING_READ(reg);
1603 udelay(150); /* wait for warmup */
66e3d5c0 1604 I915_WRITE(reg, dpll);
63d7bbe9
JB
1605 POSTING_READ(reg);
1606 udelay(150); /* wait for warmup */
1607}
1608
1609/**
50b44a44 1610 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB
1611 * @dev_priv: i915 private structure
1612 * @pipe: pipe PLL to disable
1613 *
1614 * Disable the PLL for @pipe, making sure the pipe is off first.
1615 *
1616 * Note! This is for pre-ILK only.
1617 */
1c4e0274 1618static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1619{
6315b5d3 1620 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1c4e0274
VS
1621 enum pipe pipe = crtc->pipe;
1622
1623 /* Disable DVO 2x clock on both PLLs if necessary */
50a0bc90 1624 if (IS_I830(dev_priv) &&
2d84d2b3 1625 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) &&
6315b5d3 1626 !intel_num_dvo_pipes(dev_priv)) {
1c4e0274
VS
1627 I915_WRITE(DPLL(PIPE_B),
1628 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1629 I915_WRITE(DPLL(PIPE_A),
1630 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1631 }
1632
b6b5d049
VS
1633 /* Don't disable pipe or pipe PLLs if needed */
1634 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1635 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB
1636 return;
1637
1638 /* Make sure the pipe isn't still relying on us */
1639 assert_pipe_disabled(dev_priv, pipe);
1640
b8afb911 1641 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
50b44a44 1642 POSTING_READ(DPLL(pipe));
63d7bbe9
JB
1643}
1644
f6071166
JB
1645static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1646{
b8afb911 1647 u32 val;
f6071166
JB
1648
1649 /* Make sure the pipe isn't still relying on us */
1650 assert_pipe_disabled(dev_priv, pipe);
1651
03ed5cbf
VS
1652 val = DPLL_INTEGRATED_REF_CLK_VLV |
1653 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1654 if (pipe != PIPE_A)
1655 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1656
f6071166
JB
1657 I915_WRITE(DPLL(pipe), val);
1658 POSTING_READ(DPLL(pipe));
076ed3b2
CML
1659}
1660
1661static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1662{
d752048d 1663 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML
1664 u32 val;
1665
a11b0703
VS
1666 /* Make sure the pipe isn't still relying on us */
1667 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1668
60bfe44f
VS
1669 val = DPLL_SSC_REF_CLK_CHV |
1670 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
a11b0703
VS
1671 if (pipe != PIPE_A)
1672 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
03ed5cbf 1673
a11b0703
VS
1674 I915_WRITE(DPLL(pipe), val);
1675 POSTING_READ(DPLL(pipe));
d752048d 1676
a580516d 1677 mutex_lock(&dev_priv->sb_lock);
d752048d
VS
1678
1679 /* Disable 10bit clock to display controller */
1680 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1681 val &= ~DPIO_DCLKP_EN;
1682 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1683
a580516d 1684 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB
1685}
1686
e4607fcf 1687void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS
1688 struct intel_digital_port *dport,
1689 unsigned int expected_mask)
89b667f8
JB
1690{
1691 u32 port_mask;
f0f59a00 1692 i915_reg_t dpll_reg;
89b667f8 1693
e4607fcf
CML
1694 switch (dport->port) {
1695 case PORT_B:
89b667f8 1696 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1697 dpll_reg = DPLL(0);
e4607fcf
CML
1698 break;
1699 case PORT_C:
89b667f8 1700 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1701 dpll_reg = DPLL(0);
9b6de0a1 1702 expected_mask <<= 4;
00fc31b7
CML
1703 break;
1704 case PORT_D:
1705 port_mask = DPLL_PORTD_READY_MASK;
1706 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML
1707 break;
1708 default:
1709 BUG();
1710 }
89b667f8 1711
370004d3
CW
1712 if (intel_wait_for_register(dev_priv,
1713 dpll_reg, port_mask, expected_mask,
1714 1000))
9b6de0a1
VS
1715 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1716 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB
1717}
1718
b8a4f404
PZ
1719static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1720 enum pipe pipe)
040484af 1721{
98187836
VS
1722 struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv,
1723 pipe);
f0f59a00
VS
1724 i915_reg_t reg;
1725 uint32_t val, pipeconf_val;
040484af 1726
040484af 1727 /* Make sure PCH DPLL is enabled */
8106ddbd 1728 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
040484af
JB
1729
1730 /* FDI must be feeding us bits for PCH ports */
1731 assert_fdi_tx_enabled(dev_priv, pipe);
1732 assert_fdi_rx_enabled(dev_priv, pipe);
1733
6e266956 1734 if (HAS_PCH_CPT(dev_priv)) {
23670b32
DV
1735 /* Workaround: Set the timing override bit before enabling the
1736 * pch transcoder. */
1737 reg = TRANS_CHICKEN2(pipe);
1738 val = I915_READ(reg);
1739 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1740 I915_WRITE(reg, val);
59c859d6 1741 }
23670b32 1742
ab9412ba 1743 reg = PCH_TRANSCONF(pipe);
040484af 1744 val = I915_READ(reg);
5f7f726d 1745 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c 1746
2d1fe073 1747 if (HAS_PCH_IBX(dev_priv)) {
e9bcff5c 1748 /*
c5de7c6f
VS
1749 * Make the BPC in transcoder be consistent with
1750 * that in pipeconf reg. For HDMI we must use 8bpc
1751 * here for both 8bpc and 12bpc.
e9bcff5c 1752 */
dfd07d72 1753 val &= ~PIPECONF_BPC_MASK;
2d84d2b3 1754 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI))
c5de7c6f
VS
1755 val |= PIPECONF_8BPC;
1756 else
1757 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1758 }
5f7f726d
PZ
1759
1760 val &= ~TRANS_INTERLACE_MASK;
1761 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2d1fe073 1762 if (HAS_PCH_IBX(dev_priv) &&
2d84d2b3 1763 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ
1764 val |= TRANS_LEGACY_INTERLACED_ILK;
1765 else
1766 val |= TRANS_INTERLACED;
5f7f726d
PZ
1767 else
1768 val |= TRANS_PROGRESSIVE;
1769
040484af 1770 I915_WRITE(reg, val | TRANS_ENABLE);
650fbd84
CW
1771 if (intel_wait_for_register(dev_priv,
1772 reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE,
1773 100))
4bb6f1f3 1774 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB
1775}
1776
8fb033d7 1777static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1778 enum transcoder cpu_transcoder)
040484af 1779{
8fb033d7 1780 u32 val, pipeconf_val;
8fb033d7 1781
8fb033d7 1782 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1783 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1784 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1785
223a6fdf 1786 /* Workaround: set timing override bit. */
36c0d0cf 1787 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
23670b32 1788 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
36c0d0cf 1789 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
223a6fdf 1790
25f3ef11 1791 val = TRANS_ENABLE;
937bb610 1792 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1793
9a76b1c6
PZ
1794 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1795 PIPECONF_INTERLACED_ILK)
a35f2679 1796 val |= TRANS_INTERLACED;
8fb033d7
PZ
1797 else
1798 val |= TRANS_PROGRESSIVE;
1799
ab9412ba 1800 I915_WRITE(LPT_TRANSCONF, val);
d9f96244
CW
1801 if (intel_wait_for_register(dev_priv,
1802 LPT_TRANSCONF,
1803 TRANS_STATE_ENABLE,
1804 TRANS_STATE_ENABLE,
1805 100))
937bb610 1806 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ
1807}
1808
b8a4f404
PZ
1809static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1810 enum pipe pipe)
040484af 1811{
f0f59a00
VS
1812 i915_reg_t reg;
1813 uint32_t val;
040484af
JB
1814
1815 /* FDI relies on the transcoder */
1816 assert_fdi_tx_disabled(dev_priv, pipe);
1817 assert_fdi_rx_disabled(dev_priv, pipe);
1818
291906f1
JB
1819 /* Ports must be off as well */
1820 assert_pch_ports_disabled(dev_priv, pipe);
1821
ab9412ba 1822 reg = PCH_TRANSCONF(pipe);
040484af
JB
1823 val = I915_READ(reg);
1824 val &= ~TRANS_ENABLE;
1825 I915_WRITE(reg, val);
1826 /* wait for PCH transcoder off, transcoder state */
a7d04662
CW
1827 if (intel_wait_for_register(dev_priv,
1828 reg, TRANS_STATE_ENABLE, 0,
1829 50))
4bb6f1f3 1830 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32 1831
6e266956 1832 if (HAS_PCH_CPT(dev_priv)) {
23670b32
DV
1833 /* Workaround: Clear the timing override chicken bit again. */
1834 reg = TRANS_CHICKEN2(pipe);
1835 val = I915_READ(reg);
1836 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1837 I915_WRITE(reg, val);
1838 }
040484af
JB
1839}
1840
b7076546 1841void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1842{
8fb033d7
PZ
1843 u32 val;
1844
ab9412ba 1845 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1846 val &= ~TRANS_ENABLE;
ab9412ba 1847 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1848 /* wait for PCH transcoder off, transcoder state */
dfdb4749
CW
1849 if (intel_wait_for_register(dev_priv,
1850 LPT_TRANSCONF, TRANS_STATE_ENABLE, 0,
1851 50))
8a52fd9f 1852 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ
1853
1854 /* Workaround: clear timing override bit. */
36c0d0cf 1855 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
23670b32 1856 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
36c0d0cf 1857 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
040484af
JB
1858}
1859
65f2130c
VS
1860enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc)
1861{
1862 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1863
1864 WARN_ON(!crtc->config->has_pch_encoder);
1865
1866 if (HAS_PCH_LPT(dev_priv))
1867 return TRANSCODER_A;
1868 else
1869 return (enum transcoder) crtc->pipe;
1870}
1871
b24e7179 1872/**
309cfea8 1873 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 1874 * @crtc: crtc responsible for the pipe
b24e7179 1875 *
0372264a 1876 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 1877 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 1878 */
e1fdc473 1879static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 1880{
0372264a 1881 struct drm_device *dev = crtc->base.dev;
fac5e23e 1882 struct drm_i915_private *dev_priv = to_i915(dev);
0372264a 1883 enum pipe pipe = crtc->pipe;
1a70a728 1884 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
f0f59a00 1885 i915_reg_t reg;
b24e7179
JB
1886 u32 val;
1887
9e2ee2dd
VS
1888 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1889
58c6eaa2 1890 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1891 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV
1892 assert_sprites_disabled(dev_priv, pipe);
1893
b24e7179
JB
1894 /*
1895 * A pipe without a PLL won't actually be able to drive bits from
1896 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1897 * need the check.
1898 */
09fa8bb9 1899 if (HAS_GMCH_DISPLAY(dev_priv)) {
d7edc4e5 1900 if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI))
23538ef1
JN
1901 assert_dsi_pll_enabled(dev_priv);
1902 else
1903 assert_pll_enabled(dev_priv, pipe);
09fa8bb9 1904 } else {
6e3c9717 1905 if (crtc->config->has_pch_encoder) {
040484af 1906 /* if driving the PCH, we need FDI enabled */
65f2130c
VS
1907 assert_fdi_rx_pll_enabled(dev_priv,
1908 (enum pipe) intel_crtc_pch_transcoder(crtc));
1a240d4d
DV
1909 assert_fdi_tx_pll_enabled(dev_priv,
1910 (enum pipe) cpu_transcoder);
040484af
JB
1911 }
1912 /* FIXME: assert CPU port conditions for SNB+ */
1913 }
b24e7179 1914
702e7a56 1915 reg = PIPECONF(cpu_transcoder);
b24e7179 1916 val = I915_READ(reg);
7ad25d48 1917 if (val & PIPECONF_ENABLE) {
b6b5d049
VS
1918 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1919 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 1920 return;
7ad25d48 1921 }
00d70b15
CW
1922
1923 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 1924 POSTING_READ(reg);
b7792d8b
VS
1925
1926 /*
1927 * Until the pipe starts DSL will read as 0, which would cause
1928 * an apparent vblank timestamp jump, which messes up also the
1929 * frame count when it's derived from the timestamps. So let's
1930 * wait for the pipe to start properly before we call
1931 * drm_crtc_vblank_on()
1932 */
1933 if (dev->max_vblank_count == 0 &&
1934 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
1935 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
b24e7179
JB
1936}
1937
1938/**
309cfea8 1939 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 1940 * @crtc: crtc whose pipes is to be disabled
b24e7179 1941 *
575f7ab7
VS
1942 * Disable the pipe of @crtc, making sure that various hardware
1943 * specific requirements are met, if applicable, e.g. plane
1944 * disabled, panel fitter off, etc.
b24e7179
JB
1945 *
1946 * Will wait until the pipe has shut down before returning.
1947 */
575f7ab7 1948static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 1949{
fac5e23e 1950 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6e3c9717 1951 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1952 enum pipe pipe = crtc->pipe;
f0f59a00 1953 i915_reg_t reg;
b24e7179
JB
1954 u32 val;
1955
9e2ee2dd
VS
1956 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
1957
b24e7179
JB
1958 /*
1959 * Make sure planes won't keep trying to pump pixels to us,
1960 * or we might hang the display.
1961 */
1962 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1963 assert_cursor_disabled(dev_priv, pipe);
19332d7a 1964 assert_sprites_disabled(dev_priv, pipe);
b24e7179 1965
702e7a56 1966 reg = PIPECONF(cpu_transcoder);
b24e7179 1967 val = I915_READ(reg);
00d70b15
CW
1968 if ((val & PIPECONF_ENABLE) == 0)
1969 return;
1970
67adc644
VS
1971 /*
1972 * Double wide has implications for planes
1973 * so best keep it disabled when not needed.
1974 */
6e3c9717 1975 if (crtc->config->double_wide)
67adc644
VS
1976 val &= ~PIPECONF_DOUBLE_WIDE;
1977
1978 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS
1979 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
1980 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS
1981 val &= ~PIPECONF_ENABLE;
1982
1983 I915_WRITE(reg, val);
1984 if ((val & PIPECONF_ENABLE) == 0)
1985 intel_wait_for_pipe_off(crtc);
b24e7179
JB
1986}
1987
832be82f
VS
1988static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
1989{
1990 return IS_GEN2(dev_priv) ? 2048 : 4096;
1991}
1992
d88c4afd
VS
1993static unsigned int
1994intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
7b49f948 1995{
d88c4afd
VS
1996 struct drm_i915_private *dev_priv = to_i915(fb->dev);
1997 unsigned int cpp = fb->format->cpp[plane];
1998
1999 switch (fb->modifier) {
2f075565 2000 case DRM_FORMAT_MOD_LINEAR:
7b49f948
VS
2001 return cpp;
2002 case I915_FORMAT_MOD_X_TILED:
2003 if (IS_GEN2(dev_priv))
2004 return 128;
2005 else
2006 return 512;
2007 case I915_FORMAT_MOD_Y_TILED:
2008 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2009 return 128;
2010 else
2011 return 512;
2012 case I915_FORMAT_MOD_Yf_TILED:
2013 switch (cpp) {
2014 case 1:
2015 return 64;
2016 case 2:
2017 case 4:
2018 return 128;
2019 case 8:
2020 case 16:
2021 return 256;
2022 default:
2023 MISSING_CASE(cpp);
2024 return cpp;
2025 }
2026 break;
2027 default:
d88c4afd 2028 MISSING_CASE(fb->modifier);
7b49f948
VS
2029 return cpp;
2030 }
2031}
2032
d88c4afd
VS
2033static unsigned int
2034intel_tile_height(const struct drm_framebuffer *fb, int plane)
a57ce0b2 2035{
2f075565 2036 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
832be82f
VS
2037 return 1;
2038 else
d88c4afd
VS
2039 return intel_tile_size(to_i915(fb->dev)) /
2040 intel_tile_width_bytes(fb, plane);
6761dd31
TU
2041}
2042
8d0deca8 2043/* Return the tile dimensions in pixel units */
d88c4afd 2044static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
8d0deca8 2045 unsigned int *tile_width,
d88c4afd 2046 unsigned int *tile_height)
8d0deca8 2047{
d88c4afd
VS
2048 unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
2049 unsigned int cpp = fb->format->cpp[plane];
8d0deca8
VS
2050
2051 *tile_width = tile_width_bytes / cpp;
d88c4afd 2052 *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
8d0deca8
VS
2053}
2054
6761dd31 2055unsigned int
d88c4afd
VS
2056intel_fb_align_height(const struct drm_framebuffer *fb,
2057 int plane, unsigned int height)
6761dd31 2058{
d88c4afd 2059 unsigned int tile_height = intel_tile_height(fb, plane);
832be82f
VS
2060
2061 return ALIGN(height, tile_height);
a57ce0b2
JB
2062}
2063
1663b9d6
VS
2064unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2065{
2066 unsigned int size = 0;
2067 int i;
2068
2069 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2070 size += rot_info->plane[i].width * rot_info->plane[i].height;
2071
2072 return size;
2073}
2074
75c82a53 2075static void
3465c580
VS
2076intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2077 const struct drm_framebuffer *fb,
2078 unsigned int rotation)
f64b98cd 2079{
7b92c047 2080 view->type = I915_GGTT_VIEW_NORMAL;
bd2ef25d 2081 if (drm_rotation_90_or_270(rotation)) {
7b92c047 2082 view->type = I915_GGTT_VIEW_ROTATED;
8bab1193 2083 view->rotated = to_intel_framebuffer(fb)->rot_info;
2d7a215f
VS
2084 }
2085}
50470bb0 2086
603525d7 2087static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
4e9a86b6
VS
2088{
2089 if (INTEL_INFO(dev_priv)->gen >= 9)
2090 return 256 * 1024;
c0f86832 2091 else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
666a4537 2092 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4e9a86b6
VS
2093 return 128 * 1024;
2094 else if (INTEL_INFO(dev_priv)->gen >= 4)
2095 return 4 * 1024;
2096 else
44c5905e 2097 return 0;
4e9a86b6
VS
2098}
2099
d88c4afd
VS
2100static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
2101 int plane)
603525d7 2102{
d88c4afd
VS
2103 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2104
b90c1ee1
VS
2105 /* AUX_DIST needs only 4K alignment */
2106 if (fb->format->format == DRM_FORMAT_NV12 && plane == 1)
2107 return 4096;
2108
d88c4afd 2109 switch (fb->modifier) {
2f075565 2110 case DRM_FORMAT_MOD_LINEAR:
603525d7
VS
2111 return intel_linear_alignment(dev_priv);
2112 case I915_FORMAT_MOD_X_TILED:
d88c4afd 2113 if (INTEL_GEN(dev_priv) >= 9)
603525d7
VS
2114 return 256 * 1024;
2115 return 0;
2116 case I915_FORMAT_MOD_Y_TILED:
2117 case I915_FORMAT_MOD_Yf_TILED:
2118 return 1 * 1024 * 1024;
2119 default:
d88c4afd 2120 MISSING_CASE(fb->modifier);
603525d7
VS
2121 return 0;
2122 }
2123}
2124
058d88c4
CW
2125struct i915_vma *
2126intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
6b95a207 2127{
850c4cdc 2128 struct drm_device *dev = fb->dev;
fac5e23e 2129 struct drm_i915_private *dev_priv = to_i915(dev);
850c4cdc 2130 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2131 struct i915_ggtt_view view;
058d88c4 2132 struct i915_vma *vma;
6b95a207 2133 u32 alignment;
6b95a207 2134
ebcdd39e
MR
2135 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2136
d88c4afd 2137 alignment = intel_surf_alignment(fb, 0);
6b95a207 2138
3465c580 2139 intel_fill_fb_ggtt_view(&view, fb, rotation);
f64b98cd 2140
693db184
CW
2141 /* Note that the w/a also requires 64 PTE of padding following the
2142 * bo. We currently fill all unused PTE with the shadow page and so
2143 * we should always have valid PTE following the scanout preventing
2144 * the VT-d warning.
2145 */
48f112fe 2146 if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024)
693db184
CW
2147 alignment = 256 * 1024;
2148
d6dd6843
PZ
2149 /*
2150 * Global gtt pte registers are special registers which actually forward
2151 * writes to a chunk of system memory. Which means that there is no risk
2152 * that the register values disappear as soon as we call
2153 * intel_runtime_pm_put(), so it is correct to wrap only the
2154 * pin/unpin/fence and not more.
2155 */
2156 intel_runtime_pm_get(dev_priv);
2157
058d88c4 2158 vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view);
49ef5294
CW
2159 if (IS_ERR(vma))
2160 goto err;
6b95a207 2161
05a20d09 2162 if (i915_vma_is_map_and_fenceable(vma)) {
49ef5294
CW
2163 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2164 * fence, whereas 965+ only requires a fence if using
2165 * framebuffer compression. For simplicity, we always, when
2166 * possible, install a fence as the cost is not that onerous.
2167 *
2168 * If we fail to fence the tiled scanout, then either the
2169 * modeset will reject the change (which is highly unlikely as
2170 * the affected systems, all but one, do not have unmappable
2171 * space) or we will not be able to enable full powersaving
2172 * techniques (also likely not to apply due to various limits
2173 * FBC and the like impose on the size of the buffer, which
2174 * presumably we violated anyway with this unmappable buffer).
2175 * Anyway, it is presumably better to stumble onwards with
2176 * something and try to run the system in a "less than optimal"
2177 * mode that matches the user configuration.
2178 */
2179 if (i915_vma_get_fence(vma) == 0)
2180 i915_vma_pin_fence(vma);
9807216f 2181 }
6b95a207 2182
be1e3415 2183 i915_vma_get(vma);
49ef5294 2184err:
d6dd6843 2185 intel_runtime_pm_put(dev_priv);
058d88c4 2186 return vma;
6b95a207
KH
2187}
2188
be1e3415 2189void intel_unpin_fb_vma(struct i915_vma *vma)
1690e1eb 2190{
be1e3415 2191 lockdep_assert_held(&vma->vm->i915->drm.struct_mutex);
f64b98cd 2192
49ef5294 2193 i915_vma_unpin_fence(vma);
058d88c4 2194 i915_gem_object_unpin_from_display_plane(vma);
be1e3415 2195 i915_vma_put(vma);
1690e1eb
CW
2196}
2197
ef78ec94
VS
2198static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
2199 unsigned int rotation)
2200{
bd2ef25d 2201 if (drm_rotation_90_or_270(rotation))
ef78ec94
VS
2202 return to_intel_framebuffer(fb)->rotated[plane].pitch;
2203 else
2204 return fb->pitches[plane];
2205}
2206
6687c906
VS
2207/*
2208 * Convert the x/y offsets into a linear offset.
2209 * Only valid with 0/180 degree rotation, which is fine since linear
2210 * offset is only used with linear buffers on pre-hsw and tiled buffers
2211 * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
2212 */
2213u32 intel_fb_xy_to_linear(int x, int y,
2949056c
VS
2214 const struct intel_plane_state *state,
2215 int plane)
6687c906 2216{
2949056c 2217 const struct drm_framebuffer *fb = state->base.fb;
353c8598 2218 unsigned int cpp = fb->format->cpp[plane];
6687c906
VS
2219 unsigned int pitch = fb->pitches[plane];
2220
2221 return y * pitch + x * cpp;
2222}
2223
2224/*
2225 * Add the x/y offsets derived from fb->offsets[] to the user
2226 * specified plane src x/y offsets. The resulting x/y offsets
2227 * specify the start of scanout from the beginning of the gtt mapping.
2228 */
2229void intel_add_fb_offsets(int *x, int *y,
2949056c
VS
2230 const struct intel_plane_state *state,
2231 int plane)
6687c906
VS
2232
2233{
2949056c
VS
2234 const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
2235 unsigned int rotation = state->base.rotation;
6687c906 2236
bd2ef25d 2237 if (drm_rotation_90_or_270(rotation)) {
6687c906
VS
2238 *x += intel_fb->rotated[plane].x;
2239 *y += intel_fb->rotated[plane].y;
2240 } else {
2241 *x += intel_fb->normal[plane].x;
2242 *y += intel_fb->normal[plane].y;
2243 }
2244}
2245
29cf9491 2246/*
29cf9491
VS
2247 * Input tile dimensions and pitch must already be
2248 * rotated to match x and y, and in pixel units.
2249 */
66a2d927
VS
2250static u32 _intel_adjust_tile_offset(int *x, int *y,
2251 unsigned int tile_width,
2252 unsigned int tile_height,
2253 unsigned int tile_size,
2254 unsigned int pitch_tiles,
2255 u32 old_offset,
2256 u32 new_offset)
29cf9491 2257{
b9b24038 2258 unsigned int pitch_pixels = pitch_tiles * tile_width;
29cf9491
VS
2259 unsigned int tiles;
2260
2261 WARN_ON(old_offset & (tile_size - 1));
2262 WARN_ON(new_offset & (tile_size - 1));
2263 WARN_ON(new_offset > old_offset);
2264
2265 tiles = (old_offset - new_offset) / tile_size;
2266
2267 *y += tiles / pitch_tiles * tile_height;
2268 *x += tiles % pitch_tiles * tile_width;
2269
b9b24038
VS
2270 /* minimize x in case it got needlessly big */
2271 *y += *x / pitch_pixels * tile_height;
2272 *x %= pitch_pixels;
2273
29cf9491
VS
2274 return new_offset;
2275}
2276
66a2d927
VS
2277/*
2278 * Adjust the tile offset by moving the difference into
2279 * the x/y offsets.
2280 */
2281static u32 intel_adjust_tile_offset(int *x, int *y,
2282 const struct intel_plane_state *state, int plane,
2283 u32 old_offset, u32 new_offset)
2284{
2285 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2286 const struct drm_framebuffer *fb = state->base.fb;
353c8598 2287 unsigned int cpp = fb->format->cpp[plane];
66a2d927
VS
2288 unsigned int rotation = state->base.rotation;
2289 unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
2290
2291 WARN_ON(new_offset > old_offset);
2292
2f075565 2293 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
66a2d927
VS
2294 unsigned int tile_size, tile_width, tile_height;
2295 unsigned int pitch_tiles;
2296
2297 tile_size = intel_tile_size(dev_priv);
d88c4afd 2298 intel_tile_dims(fb, plane, &tile_width, &tile_height);
66a2d927 2299
bd2ef25d 2300 if (drm_rotation_90_or_270(rotation)) {
66a2d927
VS
2301 pitch_tiles = pitch / tile_height;
2302 swap(tile_width, tile_height);
2303 } else {
2304 pitch_tiles = pitch / (tile_width * cpp);
2305 }
2306
2307 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2308 tile_size, pitch_tiles,
2309 old_offset, new_offset);
2310 } else {
2311 old_offset += *y * pitch + *x * cpp;
2312
2313 *y = (old_offset - new_offset) / pitch;
2314 *x = ((old_offset - new_offset) - *y * pitch) / cpp;
2315 }
2316
2317 return new_offset;
2318}
2319
8d0deca8
VS
2320/*
2321 * Computes the linear offset to the base tile and adjusts
2322 * x, y. bytes per pixel is assumed to be a power-of-two.
2323 *
2324 * In the 90/270 rotated case, x and y are assumed
2325 * to be already rotated to match the rotated GTT view, and
2326 * pitch is the tile_height aligned framebuffer height.
6687c906
VS
2327 *
2328 * This function is used when computing the derived information
2329 * under intel_framebuffer, so using any of that information
2330 * here is not allowed. Anything under drm_framebuffer can be
2331 * used. This is why the user has to pass in the pitch since it
2332 * is specified in the rotated orientation.
8d0deca8 2333 */
6687c906
VS
2334static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
2335 int *x, int *y,
2336 const struct drm_framebuffer *fb, int plane,
2337 unsigned int pitch,
2338 unsigned int rotation,
2339 u32 alignment)
c2c75131 2340{
bae781b2 2341 uint64_t fb_modifier = fb->modifier;
353c8598 2342 unsigned int cpp = fb->format->cpp[plane];
6687c906 2343 u32 offset, offset_aligned;
29cf9491 2344
29cf9491
VS
2345 if (alignment)
2346 alignment--;
2347
2f075565 2348 if (fb_modifier != DRM_FORMAT_MOD_LINEAR) {
8d0deca8
VS
2349 unsigned int tile_size, tile_width, tile_height;
2350 unsigned int tile_rows, tiles, pitch_tiles;
c2c75131 2351
d843310d 2352 tile_size = intel_tile_size(dev_priv);
d88c4afd 2353 intel_tile_dims(fb, plane, &tile_width, &tile_height);
8d0deca8 2354
bd2ef25d 2355 if (drm_rotation_90_or_270(rotation)) {
8d0deca8
VS
2356 pitch_tiles = pitch / tile_height;
2357 swap(tile_width, tile_height);
2358 } else {
2359 pitch_tiles = pitch / (tile_width * cpp);
2360 }
d843310d
VS
2361
2362 tile_rows = *y / tile_height;
2363 *y %= tile_height;
c2c75131 2364
8d0deca8
VS
2365 tiles = *x / tile_width;
2366 *x %= tile_width;
bc752862 2367
29cf9491
VS
2368 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2369 offset_aligned = offset & ~alignment;
bc752862 2370
66a2d927
VS
2371 _intel_adjust_tile_offset(x, y, tile_width, tile_height,
2372 tile_size, pitch_tiles,
2373 offset, offset_aligned);
29cf9491 2374 } else {
bc752862 2375 offset = *y * pitch + *x * cpp;
29cf9491
VS
2376 offset_aligned = offset & ~alignment;
2377
4e9a86b6
VS
2378 *y = (offset & alignment) / pitch;
2379 *x = ((offset & alignment) - *y * pitch) / cpp;
bc752862 2380 }
29cf9491
VS
2381
2382 return offset_aligned;
c2c75131
DV
2383}
2384
6687c906 2385u32 intel_compute_tile_offset(int *x, int *y,
2949056c
VS
2386 const struct intel_plane_state *state,
2387 int plane)
6687c906 2388{
2949056c
VS
2389 const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev);
2390 const struct drm_framebuffer *fb = state->base.fb;
2391 unsigned int rotation = state->base.rotation;
ef78ec94 2392 int pitch = intel_fb_pitch(fb, plane, rotation);
b90c1ee1 2393 u32 alignment = intel_surf_alignment(fb, plane);
6687c906
VS
2394
2395 return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
2396 rotation, alignment);
2397}
2398
2399/* Convert the fb->offset[] linear offset into x/y offsets */
2400static void intel_fb_offset_to_xy(int *x, int *y,
2401 const struct drm_framebuffer *fb, int plane)
2402{
353c8598 2403 unsigned int cpp = fb->format->cpp[plane];
6687c906
VS
2404 unsigned int pitch = fb->pitches[plane];
2405 u32 linear_offset = fb->offsets[plane];
2406
2407 *y = linear_offset / pitch;
2408 *x = linear_offset % pitch / cpp;
2409}
2410
72618ebf
VS
2411static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier)
2412{
2413 switch (fb_modifier) {
2414 case I915_FORMAT_MOD_X_TILED:
2415 return I915_TILING_X;
2416 case I915_FORMAT_MOD_Y_TILED:
2417 return I915_TILING_Y;
2418 default:
2419 return I915_TILING_NONE;
2420 }
2421}
2422
6687c906
VS
2423static int
2424intel_fill_fb_info(struct drm_i915_private *dev_priv,
2425 struct drm_framebuffer *fb)
2426{
2427 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
2428 struct intel_rotation_info *rot_info = &intel_fb->rot_info;
2429 u32 gtt_offset_rotated = 0;
2430 unsigned int max_size = 0;
bcb0b461 2431 int i, num_planes = fb->format->num_planes;
6687c906
VS
2432 unsigned int tile_size = intel_tile_size(dev_priv);
2433
2434 for (i = 0; i < num_planes; i++) {
2435 unsigned int width, height;
2436 unsigned int cpp, size;
2437 u32 offset;
2438 int x, y;
2439
353c8598 2440 cpp = fb->format->cpp[i];
145fcb11
VS
2441 width = drm_framebuffer_plane_width(fb->width, fb, i);
2442 height = drm_framebuffer_plane_height(fb->height, fb, i);
6687c906
VS
2443
2444 intel_fb_offset_to_xy(&x, &y, fb, i);
2445
60d5f2a4
VS
2446 /*
2447 * The fence (if used) is aligned to the start of the object
2448 * so having the framebuffer wrap around across the edge of the
2449 * fenced region doesn't really work. We have no API to configure
2450 * the fence start offset within the object (nor could we probably
2451 * on gen2/3). So it's just easier if we just require that the
2452 * fb layout agrees with the fence layout. We already check that the
2453 * fb stride matches the fence stride elsewhere.
2454 */
2455 if (i915_gem_object_is_tiled(intel_fb->obj) &&
2456 (x + width) * cpp > fb->pitches[i]) {
144cc143
VS
2457 DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n",
2458 i, fb->offsets[i]);
60d5f2a4
VS
2459 return -EINVAL;
2460 }
2461
6687c906
VS
2462 /*
2463 * First pixel of the framebuffer from
2464 * the start of the normal gtt mapping.
2465 */
2466 intel_fb->normal[i].x = x;
2467 intel_fb->normal[i].y = y;
2468
2469 offset = _intel_compute_tile_offset(dev_priv, &x, &y,
3ca46c0a 2470 fb, i, fb->pitches[i],
cc926387 2471 DRM_ROTATE_0, tile_size);
6687c906
VS
2472 offset /= tile_size;
2473
2f075565 2474 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
6687c906
VS
2475 unsigned int tile_width, tile_height;
2476 unsigned int pitch_tiles;
2477 struct drm_rect r;
2478
d88c4afd 2479 intel_tile_dims(fb, i, &tile_width, &tile_height);
6687c906
VS
2480
2481 rot_info->plane[i].offset = offset;
2482 rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp);
2483 rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
2484 rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
2485
2486 intel_fb->rotated[i].pitch =
2487 rot_info->plane[i].height * tile_height;
2488
2489 /* how many tiles does this plane need */
2490 size = rot_info->plane[i].stride * rot_info->plane[i].height;
2491 /*
2492 * If the plane isn't horizontally tile aligned,
2493 * we need one more tile.
2494 */
2495 if (x != 0)
2496 size++;
2497
2498 /* rotate the x/y offsets to match the GTT view */
2499 r.x1 = x;
2500 r.y1 = y;
2501 r.x2 = x + width;
2502 r.y2 = y + height;
2503 drm_rect_rotate(&r,
2504 rot_info->plane[i].width * tile_width,
2505 rot_info->plane[i].height * tile_height,
cc926387 2506 DRM_ROTATE_270);
6687c906
VS
2507 x = r.x1;
2508 y = r.y1;
2509
2510 /* rotate the tile dimensions to match the GTT view */
2511 pitch_tiles = intel_fb->rotated[i].pitch / tile_height;
2512 swap(tile_width, tile_height);
2513
2514 /*
2515 * We only keep the x/y offsets, so push all of the
2516 * gtt offset into the x/y offsets.
2517 */
46a1bd28
ACO
2518 _intel_adjust_tile_offset(&x, &y,
2519 tile_width, tile_height,
2520 tile_size, pitch_tiles,
66a2d927 2521 gtt_offset_rotated * tile_size, 0);
6687c906
VS
2522
2523 gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
2524
2525 /*
2526 * First pixel of the framebuffer from
2527 * the start of the rotated gtt mapping.
2528 */
2529 intel_fb->rotated[i].x = x;
2530 intel_fb->rotated[i].y = y;
2531 } else {
2532 size = DIV_ROUND_UP((y + height) * fb->pitches[i] +
2533 x * cpp, tile_size);
2534 }
2535
2536 /* how many tiles in total needed in the bo */
2537 max_size = max(max_size, offset + size);
2538 }
2539
144cc143
VS
2540 if (max_size * tile_size > intel_fb->obj->base.size) {
2541 DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n",
2542 max_size * tile_size, intel_fb->obj->base.size);
6687c906
VS
2543 return -EINVAL;
2544 }
2545
2546 return 0;
2547}
2548
b35d63fa 2549static int i9xx_format_to_fourcc(int format)
46f297fb
JB
2550{
2551 switch (format) {
2552 case DISPPLANE_8BPP:
2553 return DRM_FORMAT_C8;
2554 case DISPPLANE_BGRX555:
2555 return DRM_FORMAT_XRGB1555;
2556 case DISPPLANE_BGRX565:
2557 return DRM_FORMAT_RGB565;
2558 default:
2559 case DISPPLANE_BGRX888:
2560 return DRM_FORMAT_XRGB8888;
2561 case DISPPLANE_RGBX888:
2562 return DRM_FORMAT_XBGR8888;
2563 case DISPPLANE_BGRX101010:
2564 return DRM_FORMAT_XRGB2101010;
2565 case DISPPLANE_RGBX101010:
2566 return DRM_FORMAT_XBGR2101010;
2567 }
2568}
2569
bc8d7dff
DL
2570static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2571{
2572 switch (format) {
2573 case PLANE_CTL_FORMAT_RGB_565:
2574 return DRM_FORMAT_RGB565;
2575 default:
2576 case PLANE_CTL_FORMAT_XRGB_8888:
2577 if (rgb_order) {
2578 if (alpha)
2579 return DRM_FORMAT_ABGR8888;
2580 else
2581 return DRM_FORMAT_XBGR8888;
2582 } else {
2583 if (alpha)
2584 return DRM_FORMAT_ARGB8888;
2585 else
2586 return DRM_FORMAT_XRGB8888;
2587 }
2588 case PLANE_CTL_FORMAT_XRGB_2101010:
2589 if (rgb_order)
2590 return DRM_FORMAT_XBGR2101010;
2591 else
2592 return DRM_FORMAT_XRGB2101010;
2593 }
2594}
2595
5724dbd1 2596static bool
f6936e29
DV
2597intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2598 struct intel_initial_plane_config *plane_config)
46f297fb
JB
2599{
2600 struct drm_device *dev = crtc->base.dev;
3badb49f 2601 struct drm_i915_private *dev_priv = to_i915(dev);
72e96d64 2602 struct i915_ggtt *ggtt = &dev_priv->ggtt;
46f297fb
JB
2603 struct drm_i915_gem_object *obj = NULL;
2604 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2605 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV
2606 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2607 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2608 PAGE_SIZE);
2609
2610 size_aligned -= base_aligned;
46f297fb 2611
ff2652ea
CW
2612 if (plane_config->size == 0)
2613 return false;
2614
3badb49f
PZ
2615 /* If the FB is too big, just don't use it since fbdev is not very
2616 * important and we should probably use that space with FBC or other
2617 * features. */
72e96d64 2618 if (size_aligned * 2 > ggtt->stolen_usable_size)
3badb49f
PZ
2619 return false;
2620
12c83d99 2621 mutex_lock(&dev->struct_mutex);
187685cb 2622 obj = i915_gem_object_create_stolen_for_preallocated(dev_priv,
f37b5c2b
DV
2623 base_aligned,
2624 base_aligned,
2625 size_aligned);
24dbf51a
CW
2626 mutex_unlock(&dev->struct_mutex);
2627 if (!obj)
484b41dd 2628 return false;
46f297fb 2629
3e510a8e
CW
2630 if (plane_config->tiling == I915_TILING_X)
2631 obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X;
46f297fb 2632
438b74a5 2633 mode_cmd.pixel_format = fb->format->format;
6bf129df
DL
2634 mode_cmd.width = fb->width;
2635 mode_cmd.height = fb->height;
2636 mode_cmd.pitches[0] = fb->pitches[0];
bae781b2 2637 mode_cmd.modifier[0] = fb->modifier;
18c5247e 2638 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb 2639
24dbf51a 2640 if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) {
46f297fb
JB
2641 DRM_DEBUG_KMS("intel fb init failed\n");
2642 goto out_unref_obj;
2643 }
12c83d99 2644
484b41dd 2645
f6936e29 2646 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2647 return true;
46f297fb
JB
2648
2649out_unref_obj:
f8c417cd 2650 i915_gem_object_put(obj);
484b41dd
JB
2651 return false;
2652}
2653
5a21b665
DV
2654/* Update plane->state->fb to match plane->fb after driver-internal updates */
2655static void
2656update_state_fb(struct drm_plane *plane)
2657{
2658 if (plane->fb == plane->state->fb)
2659 return;
2660
2661 if (plane->state->fb)
2662 drm_framebuffer_unreference(plane->state->fb);
2663 plane->state->fb = plane->fb;
2664 if (plane->state->fb)
2665 drm_framebuffer_reference(plane->state->fb);
2666}
2667
e9728bd8
VS
2668static void
2669intel_set_plane_visible(struct intel_crtc_state *crtc_state,
2670 struct intel_plane_state *plane_state,
2671 bool visible)
2672{
2673 struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
2674
2675 plane_state->base.visible = visible;
2676
2677 /* FIXME pre-g4x don't work like this */
2678 if (visible) {
2679 crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base));
2680 crtc_state->active_planes |= BIT(plane->id);
2681 } else {
2682 crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base));
2683 crtc_state->active_planes &= ~BIT(plane->id);
2684 }
2685
2686 DRM_DEBUG_KMS("%s active planes 0x%x\n",
2687 crtc_state->base.crtc->name,
2688 crtc_state->active_planes);
2689}
2690
5724dbd1 2691static void
f6936e29
DV
2692intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2693 struct intel_initial_plane_config *plane_config)
484b41dd
JB
2694{
2695 struct drm_device *dev = intel_crtc->base.dev;
fac5e23e 2696 struct drm_i915_private *dev_priv = to_i915(dev);
484b41dd 2697 struct drm_crtc *c;
2ff8fde1 2698 struct drm_i915_gem_object *obj;
88595ac9 2699 struct drm_plane *primary = intel_crtc->base.primary;
be5651f2 2700 struct drm_plane_state *plane_state = primary->state;
200757f5
MR
2701 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2702 struct intel_plane *intel_plane = to_intel_plane(primary);
0a8d8a86
MR
2703 struct intel_plane_state *intel_state =
2704 to_intel_plane_state(plane_state);
88595ac9 2705 struct drm_framebuffer *fb;
484b41dd 2706
2d14030b 2707 if (!plane_config->fb)
484b41dd
JB
2708 return;
2709
f6936e29 2710 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV
2711 fb = &plane_config->fb->base;
2712 goto valid_fb;
f55548b5 2713 }
484b41dd 2714
2d14030b 2715 kfree(plane_config->fb);
484b41dd
JB
2716
2717 /*
2718 * Failed to alloc the obj, check to see if we should share
2719 * an fb with another CRTC instead
2720 */
70e1e0ec 2721 for_each_crtc(dev, c) {
be1e3415 2722 struct intel_plane_state *state;
484b41dd
JB
2723
2724 if (c == &intel_crtc->base)
2725 continue;
2726
be1e3415 2727 if (!to_intel_crtc(c)->active)
2ff8fde1
MR
2728 continue;
2729
be1e3415
CW
2730 state = to_intel_plane_state(c->primary->state);
2731 if (!state->vma)
484b41dd
JB
2732 continue;
2733
be1e3415
CW
2734 if (intel_plane_ggtt_offset(state) == plane_config->base) {
2735 fb = c->primary->fb;
88595ac9
DV
2736 drm_framebuffer_reference(fb);
2737 goto valid_fb;
484b41dd
JB
2738 }
2739 }
88595ac9 2740
200757f5
MR
2741 /*
2742 * We've failed to reconstruct the BIOS FB. Current display state
2743 * indicates that the primary plane is visible, but has a NULL FB,
2744 * which will lead to problems later if we don't fix it up. The
2745 * simplest solution is to just disable the primary plane now and
2746 * pretend the BIOS never had it enabled.
2747 */
e9728bd8
VS
2748 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2749 to_intel_plane_state(plane_state),
2750 false);
2622a081 2751 intel_pre_disable_primary_noatomic(&intel_crtc->base);
72259536 2752 trace_intel_disable_plane(primary, intel_crtc);
200757f5
MR
2753 intel_plane->disable_plane(primary, &intel_crtc->base);
2754
88595ac9
DV
2755 return;
2756
2757valid_fb:
be1e3415
CW
2758 mutex_lock(&dev->struct_mutex);
2759 intel_state->vma =
2760 intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
2761 mutex_unlock(&dev->struct_mutex);
2762 if (IS_ERR(intel_state->vma)) {
2763 DRM_ERROR("failed to pin boot fb on pipe %d: %li\n",
2764 intel_crtc->pipe, PTR_ERR(intel_state->vma));
2765
2766 intel_state->vma = NULL;
2767 drm_framebuffer_unreference(fb);
2768 return;
2769 }
2770
f44e2659
VS
2771 plane_state->src_x = 0;
2772 plane_state->src_y = 0;
be5651f2
ML
2773 plane_state->src_w = fb->width << 16;
2774 plane_state->src_h = fb->height << 16;
2775
f44e2659
VS
2776 plane_state->crtc_x = 0;
2777 plane_state->crtc_y = 0;
be5651f2
ML
2778 plane_state->crtc_w = fb->width;
2779 plane_state->crtc_h = fb->height;
2780
1638d30c
RC
2781 intel_state->base.src = drm_plane_state_src(plane_state);
2782 intel_state->base.dst = drm_plane_state_dest(plane_state);
0a8d8a86 2783
88595ac9 2784 obj = intel_fb_obj(fb);
3e510a8e 2785 if (i915_gem_object_is_tiled(obj))
88595ac9
DV
2786 dev_priv->preserve_bios_swizzle = true;
2787
be5651f2
ML
2788 drm_framebuffer_reference(fb);
2789 primary->fb = primary->state->fb = fb;
36750f28 2790 primary->crtc = primary->state->crtc = &intel_crtc->base;
e9728bd8
VS
2791
2792 intel_set_plane_visible(to_intel_crtc_state(crtc_state),
2793 to_intel_plane_state(plane_state),
2794 true);
2795
faf5bf0a
CW
2796 atomic_or(to_intel_plane(primary)->frontbuffer_bit,
2797 &obj->frontbuffer_bits);
46f297fb
JB
2798}
2799
b63a16f6
VS
2800static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
2801 unsigned int rotation)
2802{
353c8598 2803 int cpp = fb->format->cpp[plane];
b63a16f6 2804
bae781b2 2805 switch (fb->modifier) {
2f075565 2806 case DRM_FORMAT_MOD_LINEAR:
b63a16f6
VS
2807 case I915_FORMAT_MOD_X_TILED:
2808 switch (cpp) {
2809 case 8:
2810 return 4096;
2811 case 4:
2812 case 2:
2813 case 1:
2814 return 8192;
2815 default:
2816 MISSING_CASE(cpp);
2817 break;
2818 }
2819 break;
2820 case I915_FORMAT_MOD_Y_TILED:
2821 case I915_FORMAT_MOD_Yf_TILED:
2822 switch (cpp) {
2823 case 8:
2824 return 2048;
2825 case 4:
2826 return 4096;
2827 case 2:
2828 case 1:
2829 return 8192;
2830 default:
2831 MISSING_CASE(cpp);
2832 break;
2833 }
2834 break;
2835 default:
bae781b2 2836 MISSING_CASE(fb->modifier);
b63a16f6
VS
2837 }
2838
2839 return 2048;
2840}
2841
2842static int skl_check_main_surface(struct intel_plane_state *plane_state)
2843{
b63a16f6
VS
2844 const struct drm_framebuffer *fb = plane_state->base.fb;
2845 unsigned int rotation = plane_state->base.rotation;
cc926387
DV
2846 int x = plane_state->base.src.x1 >> 16;
2847 int y = plane_state->base.src.y1 >> 16;
2848 int w = drm_rect_width(&plane_state->base.src) >> 16;
2849 int h = drm_rect_height(&plane_state->base.src) >> 16;
b63a16f6
VS
2850 int max_width = skl_max_plane_width(fb, 0, rotation);
2851 int max_height = 4096;
8d970654 2852 u32 alignment, offset, aux_offset = plane_state->aux.offset;
b63a16f6
VS
2853
2854 if (w > max_width || h > max_height) {
2855 DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
2856 w, h, max_width, max_height);
2857 return -EINVAL;
2858 }
2859
2860 intel_add_fb_offsets(&x, &y, plane_state, 0);
2861 offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
d88c4afd 2862 alignment = intel_surf_alignment(fb, 0);
b63a16f6 2863
8d970654
VS
2864 /*
2865 * AUX surface offset is specified as the distance from the
2866 * main surface offset, and it must be non-negative. Make
2867 * sure that is what we will get.
2868 */
2869 if (offset > aux_offset)
2870 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2871 offset, aux_offset & ~(alignment - 1));
2872
b63a16f6
VS
2873 /*
2874 * When using an X-tiled surface, the plane blows up
2875 * if the x offset + width exceed the stride.
2876 *
2877 * TODO: linear and Y-tiled seem fine, Yf untested,
2878 */
bae781b2 2879 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
353c8598 2880 int cpp = fb->format->cpp[0];
b63a16f6
VS
2881
2882 while ((x + w) * cpp > fb->pitches[0]) {
2883 if (offset == 0) {
2884 DRM_DEBUG_KMS("Unable to find suitable display surface offset\n");
2885 return -EINVAL;
2886 }
2887
2888 offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
2889 offset, offset - alignment);
2890 }
2891 }
2892
2893 plane_state->main.offset = offset;
2894 plane_state->main.x = x;
2895 plane_state->main.y = y;
2896
2897 return 0;
2898}
2899
8d970654
VS
2900static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
2901{
2902 const struct drm_framebuffer *fb = plane_state->base.fb;
2903 unsigned int rotation = plane_state->base.rotation;
2904 int max_width = skl_max_plane_width(fb, 1, rotation);
2905 int max_height = 4096;
cc926387
DV
2906 int x = plane_state->base.src.x1 >> 17;
2907 int y = plane_state->base.src.y1 >> 17;
2908 int w = drm_rect_width(&plane_state->base.src) >> 17;
2909 int h = drm_rect_height(&plane_state->base.src) >> 17;
8d970654
VS
2910 u32 offset;
2911
2912 intel_add_fb_offsets(&x, &y, plane_state, 1);
2913 offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
2914
2915 /* FIXME not quite sure how/if these apply to the chroma plane */
2916 if (w > max_width || h > max_height) {
2917 DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n",
2918 w, h, max_width, max_height);
2919 return -EINVAL;
2920 }
2921
2922 plane_state->aux.offset = offset;
2923 plane_state->aux.x = x;
2924 plane_state->aux.y = y;
2925
2926 return 0;
2927}
2928
b63a16f6
VS
2929int skl_check_plane_surface(struct intel_plane_state *plane_state)
2930{
2931 const struct drm_framebuffer *fb = plane_state->base.fb;
2932 unsigned int rotation = plane_state->base.rotation;
2933 int ret;
2934
a5e4c7d0
VS
2935 if (!plane_state->base.visible)
2936 return 0;
2937
b63a16f6 2938 /* Rotate src coordinates to match rotated GTT view */
bd2ef25d 2939 if (drm_rotation_90_or_270(rotation))
cc926387 2940 drm_rect_rotate(&plane_state->base.src,
da064b47
VS
2941 fb->width << 16, fb->height << 16,
2942 DRM_ROTATE_270);
b63a16f6 2943
8d970654
VS
2944 /*
2945 * Handle the AUX surface first since
2946 * the main surface setup depends on it.
2947 */
438b74a5 2948 if (fb->format->format == DRM_FORMAT_NV12) {
8d970654
VS
2949 ret = skl_check_nv12_aux_surface(plane_state);
2950 if (ret)
2951 return ret;
2952 } else {
2953 plane_state->aux.offset = ~0xfff;
2954 plane_state->aux.x = 0;
2955 plane_state->aux.y = 0;
2956 }
2957
b63a16f6
VS
2958 ret = skl_check_main_surface(plane_state);
2959 if (ret)
2960 return ret;
2961
2962 return 0;
2963}
2964
7145f60a
VS
2965static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
2966 const struct intel_plane_state *plane_state)
81255565 2967{
7145f60a
VS
2968 struct drm_i915_private *dev_priv =
2969 to_i915(plane_state->base.plane->dev);
2970 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
2971 const struct drm_framebuffer *fb = plane_state->base.fb;
8d0deca8 2972 unsigned int rotation = plane_state->base.rotation;
7145f60a 2973 u32 dspcntr;
c9ba6fad 2974
7145f60a 2975 dspcntr = DISPLAY_PLANE_ENABLE | DISPPLANE_GAMMA_ENABLE;
f45651ba 2976
6a4407a6
VS
2977 if (IS_G4X(dev_priv) || IS_GEN5(dev_priv) ||
2978 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
7145f60a 2979 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
f45651ba 2980
6a4407a6
VS
2981 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
2982 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2983
6315b5d3 2984 if (INTEL_GEN(dev_priv) < 4) {
7145f60a 2985 if (crtc->pipe == PIPE_B)
f45651ba 2986 dspcntr |= DISPPLANE_SEL_PIPE_B;
f45651ba 2987 }
81255565 2988
438b74a5 2989 switch (fb->format->format) {
57779d06 2990 case DRM_FORMAT_C8:
81255565
JB
2991 dspcntr |= DISPPLANE_8BPP;
2992 break;
57779d06 2993 case DRM_FORMAT_XRGB1555:
57779d06 2994 dspcntr |= DISPPLANE_BGRX555;
81255565 2995 break;
57779d06
VS
2996 case DRM_FORMAT_RGB565:
2997 dspcntr |= DISPPLANE_BGRX565;
2998 break;
2999 case DRM_FORMAT_XRGB8888:
57779d06
VS
3000 dspcntr |= DISPPLANE_BGRX888;
3001 break;
3002 case DRM_FORMAT_XBGR8888:
57779d06
VS
3003 dspcntr |= DISPPLANE_RGBX888;
3004 break;
3005 case DRM_FORMAT_XRGB2101010:
57779d06
VS
3006 dspcntr |= DISPPLANE_BGRX101010;
3007 break;
3008 case DRM_FORMAT_XBGR2101010:
57779d06 3009 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB
3010 break;
3011 default:
7145f60a
VS
3012 MISSING_CASE(fb->format->format);
3013 return 0;
81255565 3014 }
57779d06 3015
72618ebf 3016 if (INTEL_GEN(dev_priv) >= 4 &&
bae781b2 3017 fb->modifier == I915_FORMAT_MOD_X_TILED)
f45651ba 3018 dspcntr |= DISPPLANE_TILED;
81255565 3019
df0cd455
VS
3020 if (rotation & DRM_ROTATE_180)
3021 dspcntr |= DISPPLANE_ROTATE_180;
3022
4ea7be2b
VS
3023 if (rotation & DRM_REFLECT_X)
3024 dspcntr |= DISPPLANE_MIRROR;
3025
7145f60a
VS
3026 return dspcntr;
3027}
3028
f9407ae1 3029int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
5b7fcc44
VS
3030{
3031 struct drm_i915_private *dev_priv =
3032 to_i915(plane_state->base.plane->dev);
3033 int src_x = plane_state->base.src.x1 >> 16;
3034 int src_y = plane_state->base.src.y1 >> 16;
3035 u32 offset;
3036
3037 intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
3038
3039 if (INTEL_GEN(dev_priv) >= 4)
3040 offset = intel_compute_tile_offset(&src_x, &src_y,
3041 plane_state, 0);
3042 else
3043 offset = 0;
3044
3045 /* HSW/BDW do this automagically in hardware */
3046 if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
3047 unsigned int rotation = plane_state->base.rotation;
3048 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3049 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3050
3051 if (rotation & DRM_ROTATE_180) {
3052 src_x += src_w - 1;
3053 src_y += src_h - 1;
3054 } else if (rotation & DRM_REFLECT_X) {
3055 src_x += src_w - 1;
3056 }
3057 }
3058
3059 plane_state->main.offset = offset;
3060 plane_state->main.x = src_x;
3061 plane_state->main.y = src_y;
3062
3063 return 0;
3064}
3065
7145f60a
VS
3066static void i9xx_update_primary_plane(struct drm_plane *primary,
3067 const struct intel_crtc_state *crtc_state,
3068 const struct intel_plane_state *plane_state)
3069{
3070 struct drm_i915_private *dev_priv = to_i915(primary->dev);
3071 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3072 struct drm_framebuffer *fb = plane_state->base.fb;
3073 int plane = intel_crtc->plane;
3074 u32 linear_offset;
a0864d59 3075 u32 dspcntr = plane_state->ctl;
7145f60a 3076 i915_reg_t reg = DSPCNTR(plane);
5b7fcc44
VS
3077 int x = plane_state->main.x;
3078 int y = plane_state->main.y;
7145f60a
VS
3079 unsigned long irqflags;
3080
2949056c 3081 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
6687c906 3082
5b7fcc44
VS
3083 if (INTEL_GEN(dev_priv) >= 4)
3084 intel_crtc->dspaddr_offset = plane_state->main.offset;
3085 else
6687c906
VS
3086 intel_crtc->dspaddr_offset = linear_offset;
3087
2db3366b
PZ
3088 intel_crtc->adjusted_x = x;
3089 intel_crtc->adjusted_y = y;
3090
dd584fc0
VS
3091 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3092
78587de2
VS
3093 if (INTEL_GEN(dev_priv) < 4) {
3094 /* pipesrc and dspsize control the size that is scaled from,
3095 * which should always be the user's requested size.
3096 */
dd584fc0
VS
3097 I915_WRITE_FW(DSPSIZE(plane),
3098 ((crtc_state->pipe_src_h - 1) << 16) |
3099 (crtc_state->pipe_src_w - 1));
3100 I915_WRITE_FW(DSPPOS(plane), 0);
78587de2 3101 } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) {
dd584fc0
VS
3102 I915_WRITE_FW(PRIMSIZE(plane),
3103 ((crtc_state->pipe_src_h - 1) << 16) |
3104 (crtc_state->pipe_src_w - 1));
3105 I915_WRITE_FW(PRIMPOS(plane), 0);
3106 I915_WRITE_FW(PRIMCNSTALPHA(plane), 0);
78587de2
VS
3107 }
3108
dd584fc0 3109 I915_WRITE_FW(reg, dspcntr);
48404c1e 3110
dd584fc0 3111 I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
3ba35e53
VS
3112 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3113 I915_WRITE_FW(DSPSURF(plane),
3114 intel_plane_ggtt_offset(plane_state) +
3115 intel_crtc->dspaddr_offset);
3116 I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
3117 } else if (INTEL_GEN(dev_priv) >= 4) {
dd584fc0
VS
3118 I915_WRITE_FW(DSPSURF(plane),
3119 intel_plane_ggtt_offset(plane_state) +
3120 intel_crtc->dspaddr_offset);
3121 I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
3122 I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
bfb81049 3123 } else {
dd584fc0
VS
3124 I915_WRITE_FW(DSPADDR(plane),
3125 intel_plane_ggtt_offset(plane_state) +
3126 intel_crtc->dspaddr_offset);
bfb81049 3127 }
dd584fc0
VS
3128 POSTING_READ_FW(reg);
3129
3130 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
17638cd6
JB
3131}
3132
a8d201af
ML
3133static void i9xx_disable_primary_plane(struct drm_plane *primary,
3134 struct drm_crtc *crtc)
17638cd6
JB
3135{
3136 struct drm_device *dev = crtc->dev;
fac5e23e 3137 struct drm_i915_private *dev_priv = to_i915(dev);
17638cd6 3138 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
17638cd6 3139 int plane = intel_crtc->plane;
dd584fc0
VS
3140 unsigned long irqflags;
3141
3142 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
f45651ba 3143
dd584fc0 3144 I915_WRITE_FW(DSPCNTR(plane), 0);
a8d201af 3145 if (INTEL_INFO(dev_priv)->gen >= 4)
dd584fc0 3146 I915_WRITE_FW(DSPSURF(plane), 0);
a8d201af 3147 else
dd584fc0
VS
3148 I915_WRITE_FW(DSPADDR(plane), 0);
3149 POSTING_READ_FW(DSPCNTR(plane));
3150
3151 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
a8d201af 3152}
c9ba6fad 3153
d88c4afd
VS
3154static u32
3155intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
b321803d 3156{
2f075565 3157 if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
b321803d 3158 return 64;
d88c4afd
VS
3159 else
3160 return intel_tile_width_bytes(fb, plane);
b321803d
DL
3161}
3162
e435d6e5
ML
3163static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
3164{
3165 struct drm_device *dev = intel_crtc->base.dev;
fac5e23e 3166 struct drm_i915_private *dev_priv = to_i915(dev);
e435d6e5
ML
3167
3168 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3169 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3170 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
e435d6e5
ML
3171}
3172
a1b2278e
CK
3173/*
3174 * This function detaches (aka. unbinds) unused scalers in hardware
3175 */
0583236e 3176static void skl_detach_scalers(struct intel_crtc *intel_crtc)
a1b2278e 3177{
a1b2278e
CK
3178 struct intel_crtc_scaler_state *scaler_state;
3179 int i;
3180
a1b2278e
CK
3181 scaler_state = &intel_crtc->config->scaler_state;
3182
3183 /* loop through and disable scalers that aren't in use */
3184 for (i = 0; i < intel_crtc->num_scalers; i++) {
e435d6e5
ML
3185 if (!scaler_state->scalers[i].in_use)
3186 skl_detach_scaler(intel_crtc, i);
a1b2278e
CK
3187 }
3188}
3189
d2196774
VS
3190u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
3191 unsigned int rotation)
3192{
1b500535
VS
3193 u32 stride;
3194
3195 if (plane >= fb->format->num_planes)
3196 return 0;
3197
3198 stride = intel_fb_pitch(fb, plane, rotation);
d2196774
VS
3199
3200 /*
3201 * The stride is either expressed as a multiple of 64 bytes chunks for
3202 * linear buffers or in number of tiles for tiled buffers.
3203 */
d88c4afd
VS
3204 if (drm_rotation_90_or_270(rotation))
3205 stride /= intel_tile_height(fb, plane);
3206 else
3207 stride /= intel_fb_stride_alignment(fb, plane);
d2196774
VS
3208
3209 return stride;
3210}
3211
2e881264 3212static u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 3213{
6156a456 3214 switch (pixel_format) {
d161cf7a 3215 case DRM_FORMAT_C8:
c34ce3d1 3216 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 3217 case DRM_FORMAT_RGB565:
c34ce3d1 3218 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 3219 case DRM_FORMAT_XBGR8888:
c34ce3d1 3220 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 3221 case DRM_FORMAT_XRGB8888:
c34ce3d1 3222 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK
3223 /*
3224 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3225 * to be already pre-multiplied. We need to add a knob (or a different
3226 * DRM_FORMAT) for user-space to configure that.
3227 */
f75fb42a 3228 case DRM_FORMAT_ABGR8888:
c34ce3d1 3229 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 3230 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 3231 case DRM_FORMAT_ARGB8888:
c34ce3d1 3232 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 3233 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 3234 case DRM_FORMAT_XRGB2101010:
c34ce3d1 3235 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 3236 case DRM_FORMAT_XBGR2101010:
c34ce3d1 3237 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 3238 case DRM_FORMAT_YUYV:
c34ce3d1 3239 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 3240 case DRM_FORMAT_YVYU:
c34ce3d1 3241 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 3242 case DRM_FORMAT_UYVY:
c34ce3d1 3243 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 3244 case DRM_FORMAT_VYUY:
c34ce3d1 3245 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 3246 default:
4249eeef 3247 MISSING_CASE(pixel_format);
70d21f0e 3248 }
8cfcba41 3249
c34ce3d1 3250 return 0;
6156a456 3251}
70d21f0e 3252
2e881264 3253static u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
6156a456 3254{
6156a456 3255 switch (fb_modifier) {
2f075565 3256 case DRM_FORMAT_MOD_LINEAR:
70d21f0e 3257 break;
30af77c4 3258 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 3259 return PLANE_CTL_TILED_X;
b321803d 3260 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 3261 return PLANE_CTL_TILED_Y;
b321803d 3262 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 3263 return PLANE_CTL_TILED_YF;
70d21f0e 3264 default:
6156a456 3265 MISSING_CASE(fb_modifier);
70d21f0e 3266 }
8cfcba41 3267
c34ce3d1 3268 return 0;
6156a456 3269}
70d21f0e 3270
2e881264 3271static u32 skl_plane_ctl_rotation(unsigned int rotation)
6156a456 3272{
3b7a5119 3273 switch (rotation) {
31ad61e4 3274 case DRM_ROTATE_0:
6156a456 3275 break;
1e8df167
SJ
3276 /*
3277 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3278 * while i915 HW rotation is clockwise, thats why this swapping.
3279 */
31ad61e4 3280 case DRM_ROTATE_90:
1e8df167 3281 return PLANE_CTL_ROTATE_270;
31ad61e4 3282 case DRM_ROTATE_180:
c34ce3d1 3283 return PLANE_CTL_ROTATE_180;
31ad61e4 3284 case DRM_ROTATE_270:
1e8df167 3285 return PLANE_CTL_ROTATE_90;
6156a456
CK
3286 default:
3287 MISSING_CASE(rotation);
3288 }
3289
c34ce3d1 3290 return 0;
6156a456
CK
3291}
3292
2e881264
VS
3293u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
3294 const struct intel_plane_state *plane_state)
46f788ba
VS
3295{
3296 struct drm_i915_private *dev_priv =
3297 to_i915(plane_state->base.plane->dev);
3298 const struct drm_framebuffer *fb = plane_state->base.fb;
3299 unsigned int rotation = plane_state->base.rotation;
2e881264 3300 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
46f788ba
VS
3301 u32 plane_ctl;
3302
3303 plane_ctl = PLANE_CTL_ENABLE;
3304
3305 if (!IS_GEMINILAKE(dev_priv)) {
3306 plane_ctl |=
3307 PLANE_CTL_PIPE_GAMMA_ENABLE |
3308 PLANE_CTL_PIPE_CSC_ENABLE |
3309 PLANE_CTL_PLANE_GAMMA_DISABLE;
3310 }
3311
3312 plane_ctl |= skl_plane_ctl_format(fb->format->format);
3313 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
3314 plane_ctl |= skl_plane_ctl_rotation(rotation);
3315
2e881264
VS
3316 if (key->flags & I915_SET_COLORKEY_DESTINATION)
3317 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
3318 else if (key->flags & I915_SET_COLORKEY_SOURCE)
3319 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
3320
46f788ba
VS
3321 return plane_ctl;
3322}
3323
a8d201af
ML
3324static void skylake_update_primary_plane(struct drm_plane *plane,
3325 const struct intel_crtc_state *crtc_state,
3326 const struct intel_plane_state *plane_state)
6156a456 3327{
a8d201af 3328 struct drm_device *dev = plane->dev;
fac5e23e 3329 struct drm_i915_private *dev_priv = to_i915(dev);
a8d201af
ML
3330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3331 struct drm_framebuffer *fb = plane_state->base.fb;
8e816bb4
VS
3332 enum plane_id plane_id = to_intel_plane(plane)->id;
3333 enum pipe pipe = to_intel_plane(plane)->pipe;
a0864d59 3334 u32 plane_ctl = plane_state->ctl;
a8d201af 3335 unsigned int rotation = plane_state->base.rotation;
d2196774 3336 u32 stride = skl_plane_stride(fb, 0, rotation);
b63a16f6 3337 u32 surf_addr = plane_state->main.offset;
a8d201af 3338 int scaler_id = plane_state->scaler_id;
b63a16f6
VS
3339 int src_x = plane_state->main.x;
3340 int src_y = plane_state->main.y;
936e71e3
VS
3341 int src_w = drm_rect_width(&plane_state->base.src) >> 16;
3342 int src_h = drm_rect_height(&plane_state->base.src) >> 16;
3343 int dst_x = plane_state->base.dst.x1;
3344 int dst_y = plane_state->base.dst.y1;
3345 int dst_w = drm_rect_width(&plane_state->base.dst);
3346 int dst_h = drm_rect_height(&plane_state->base.dst);
dd584fc0 3347 unsigned long irqflags;
70d21f0e 3348
6687c906
VS
3349 /* Sizes are 0 based */
3350 src_w--;
3351 src_h--;
3352 dst_w--;
3353 dst_h--;
3354
4c0b8a8b
PZ
3355 intel_crtc->dspaddr_offset = surf_addr;
3356
6687c906
VS
3357 intel_crtc->adjusted_x = src_x;
3358 intel_crtc->adjusted_y = src_y;
2db3366b 3359
dd584fc0
VS
3360 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
3361
78587de2 3362 if (IS_GEMINILAKE(dev_priv)) {
dd584fc0
VS
3363 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
3364 PLANE_COLOR_PIPE_GAMMA_ENABLE |
3365 PLANE_COLOR_PIPE_CSC_ENABLE |
3366 PLANE_COLOR_PLANE_GAMMA_DISABLE);
78587de2
VS
3367 }
3368
dd584fc0
VS
3369 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
3370 I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x);
3371 I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
3372 I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
6156a456
CK
3373
3374 if (scaler_id >= 0) {
3375 uint32_t ps_ctrl = 0;
3376
3377 WARN_ON(!dst_w || !dst_h);
8e816bb4 3378 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) |
6156a456 3379 crtc_state->scaler_state.scalers[scaler_id].mode;
dd584fc0
VS
3380 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3381 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3382 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3383 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3384 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
6156a456 3385 } else {
dd584fc0 3386 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x);
6156a456
CK
3387 }
3388
dd584fc0
VS
3389 I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
3390 intel_plane_ggtt_offset(plane_state) + surf_addr);
70d21f0e 3391
dd584fc0
VS
3392 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3393
3394 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
70d21f0e
DL
3395}
3396
a8d201af
ML
3397static void skylake_disable_primary_plane(struct drm_plane *primary,
3398 struct drm_crtc *crtc)
17638cd6
JB
3399{
3400 struct drm_device *dev = crtc->dev;
fac5e23e 3401 struct drm_i915_private *dev_priv = to_i915(dev);
8e816bb4
VS
3402 enum plane_id plane_id = to_intel_plane(primary)->id;
3403 enum pipe pipe = to_intel_plane(primary)->pipe;
dd584fc0
VS
3404 unsigned long irqflags;
3405
3406 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
62e0fb88 3407
dd584fc0
VS
3408 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
3409 I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
3410 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
3411
3412 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
a8d201af 3413}
29b9bde6 3414
5a21b665
DV
3415static void intel_complete_page_flips(struct drm_i915_private *dev_priv)
3416{
3417 struct intel_crtc *crtc;
3418
91c8a326 3419 for_each_intel_crtc(&dev_priv->drm, crtc)
5a21b665
DV
3420 intel_finish_page_flip_cs(dev_priv, crtc->pipe);
3421}
3422
7514747d
VS
3423static void intel_update_primary_planes(struct drm_device *dev)
3424{
7514747d 3425 struct drm_crtc *crtc;
96a02917 3426
70e1e0ec 3427 for_each_crtc(dev, crtc) {
11c22da6 3428 struct intel_plane *plane = to_intel_plane(crtc->primary);
73974893
ML
3429 struct intel_plane_state *plane_state =
3430 to_intel_plane_state(plane->base.state);
11c22da6 3431
72259536
VS
3432 if (plane_state->base.visible) {
3433 trace_intel_update_plane(&plane->base,
3434 to_intel_crtc(crtc));
3435
a8d201af
ML
3436 plane->update_plane(&plane->base,
3437 to_intel_crtc_state(crtc->state),
3438 plane_state);
72259536 3439 }
73974893
ML
3440 }
3441}
3442
3443static int
3444__intel_display_resume(struct drm_device *dev,
581e49fe
ML
3445 struct drm_atomic_state *state,
3446 struct drm_modeset_acquire_ctx *ctx)
73974893
ML
3447{
3448 struct drm_crtc_state *crtc_state;
3449 struct drm_crtc *crtc;
3450 int i, ret;
11c22da6 3451
73974893 3452 intel_modeset_setup_hw_state(dev);
29b74b7f 3453 i915_redisable_vga(to_i915(dev));
73974893
ML
3454
3455 if (!state)
3456 return 0;
3457
aa5e9b47
ML
3458 /*
3459 * We've duplicated the state, pointers to the old state are invalid.
3460 *
3461 * Don't attempt to use the old state until we commit the duplicated state.
3462 */
3463 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
73974893
ML
3464 /*
3465 * Force recalculation even if we restore
3466 * current state. With fast modeset this may not result
3467 * in a modeset when the state is compatible.
3468 */
3469 crtc_state->mode_changed = true;
96a02917 3470 }
73974893
ML
3471
3472 /* ignore any reset values/BIOS leftovers in the WM registers */
602ae835
VS
3473 if (!HAS_GMCH_DISPLAY(to_i915(dev)))
3474 to_intel_atomic_state(state)->skip_intermediate_wm = true;
73974893 3475
581e49fe 3476 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
73974893
ML
3477
3478 WARN_ON(ret == -EDEADLK);
3479 return ret;
96a02917
VS
3480}
3481
4ac2ba2f
VS
3482static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv)
3483{
ae98104b
VS
3484 return intel_has_gpu_reset(dev_priv) &&
3485 INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv);
4ac2ba2f
VS
3486}
3487
c033666a 3488void intel_prepare_reset(struct drm_i915_private *dev_priv)
7514747d 3489{
73974893
ML
3490 struct drm_device *dev = &dev_priv->drm;
3491 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3492 struct drm_atomic_state *state;
3493 int ret;
3494
73974893
ML
3495 /*
3496 * Need mode_config.mutex so that we don't
3497 * trample ongoing ->detect() and whatnot.
3498 */
3499 mutex_lock(&dev->mode_config.mutex);
3500 drm_modeset_acquire_init(ctx, 0);
3501 while (1) {
3502 ret = drm_modeset_lock_all_ctx(dev, ctx);
3503 if (ret != -EDEADLK)
3504 break;
3505
3506 drm_modeset_backoff(ctx);
3507 }
3508
3509 /* reset doesn't touch the display, but flips might get nuked anyway, */
522a63de 3510 if (!i915.force_reset_modeset_test &&
4ac2ba2f 3511 !gpu_reset_clobbers_display(dev_priv))
7514747d
VS
3512 return;
3513
f98ce92f
VS
3514 /*
3515 * Disabling the crtcs gracefully seems nicer. Also the
3516 * g33 docs say we should at least disable all the planes.
3517 */
73974893
ML
3518 state = drm_atomic_helper_duplicate_state(dev, ctx);
3519 if (IS_ERR(state)) {
3520 ret = PTR_ERR(state);
73974893 3521 DRM_ERROR("Duplicating state failed with %i\n", ret);
1e5a15d6 3522 return;
73974893
ML
3523 }
3524
3525 ret = drm_atomic_helper_disable_all(dev, ctx);
3526 if (ret) {
3527 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
1e5a15d6
ACO
3528 drm_atomic_state_put(state);
3529 return;
73974893
ML
3530 }
3531
3532 dev_priv->modeset_restore_state = state;
3533 state->acquire_ctx = ctx;
7514747d
VS
3534}
3535
c033666a 3536void intel_finish_reset(struct drm_i915_private *dev_priv)
7514747d 3537{
73974893
ML
3538 struct drm_device *dev = &dev_priv->drm;
3539 struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx;
3540 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
3541 int ret;
3542
5a21b665
DV
3543 /*
3544 * Flips in the rings will be nuked by the reset,
3545 * so complete all pending flips so that user space
3546 * will get its events and not get stuck.
3547 */
3548 intel_complete_page_flips(dev_priv);
3549
73974893
ML
3550 dev_priv->modeset_restore_state = NULL;
3551
7514747d 3552 /* reset doesn't touch the display */
4ac2ba2f 3553 if (!gpu_reset_clobbers_display(dev_priv)) {
522a63de
ML
3554 if (!state) {
3555 /*
3556 * Flips in the rings have been nuked by the reset,
3557 * so update the base address of all primary
3558 * planes to the the last fb to make sure we're
3559 * showing the correct fb after a reset.
3560 *
3561 * FIXME: Atomic will make this obsolete since we won't schedule
3562 * CS-based flips (which might get lost in gpu resets) any more.
3563 */
3564 intel_update_primary_planes(dev);
3565 } else {
581e49fe 3566 ret = __intel_display_resume(dev, state, ctx);
522a63de
ML
3567 if (ret)
3568 DRM_ERROR("Restoring old state failed with %i\n", ret);
3569 }
73974893
ML
3570 } else {
3571 /*
3572 * The display has been reset as well,
3573 * so need a full re-initialization.
3574 */
3575 intel_runtime_pm_disable_interrupts(dev_priv);
3576 intel_runtime_pm_enable_interrupts(dev_priv);
7514747d 3577
51f59205 3578 intel_pps_unlock_regs_wa(dev_priv);
73974893 3579 intel_modeset_init_hw(dev);
7514747d 3580
73974893
ML
3581 spin_lock_irq(&dev_priv->irq_lock);
3582 if (dev_priv->display.hpd_irq_setup)
3583 dev_priv->display.hpd_irq_setup(dev_priv);
3584 spin_unlock_irq(&dev_priv->irq_lock);
7514747d 3585
581e49fe 3586 ret = __intel_display_resume(dev, state, ctx);
73974893
ML
3587 if (ret)
3588 DRM_ERROR("Restoring old state failed with %i\n", ret);
7514747d 3589
73974893
ML
3590 intel_hpd_init(dev_priv);
3591 }
7514747d 3592
0853695c
CW
3593 if (state)
3594 drm_atomic_state_put(state);
73974893
ML
3595 drm_modeset_drop_locks(ctx);
3596 drm_modeset_acquire_fini(ctx);
3597 mutex_unlock(&dev->mode_config.mutex);
7514747d
VS
3598}
3599
8af29b0c
CW
3600static bool abort_flip_on_reset(struct intel_crtc *crtc)
3601{
3602 struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error;
3603
8c185eca 3604 if (i915_reset_backoff(error))
8af29b0c
CW
3605 return true;
3606
3607 if (crtc->reset_count != i915_reset_count(error))
3608 return true;
3609
3610 return false;
3611}
3612
7d5e3799
CW
3613static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3614{
5a21b665
DV
3615 struct drm_device *dev = crtc->dev;
3616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5a21b665
DV
3617 bool pending;
3618
8af29b0c 3619 if (abort_flip_on_reset(intel_crtc))
5a21b665
DV
3620 return false;
3621
3622 spin_lock_irq(&dev->event_lock);
3623 pending = to_intel_crtc(crtc)->flip_work != NULL;
3624 spin_unlock_irq(&dev->event_lock);
3625
3626 return pending;
7d5e3799
CW
3627}
3628
bfd16b2a
ML
3629static void intel_update_pipe_config(struct intel_crtc *crtc,
3630 struct intel_crtc_state *old_crtc_state)
e30e8f75 3631{
6315b5d3 3632 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
bfd16b2a
ML
3633 struct intel_crtc_state *pipe_config =
3634 to_intel_crtc_state(crtc->base.state);
e30e8f75 3635
bfd16b2a
ML
3636 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3637 crtc->base.mode = crtc->base.state->mode;
3638
e30e8f75
GP
3639 /*
3640 * Update pipe size and adjust fitter if needed: the reason for this is
3641 * that in compute_mode_changes we check the native mode (not the pfit
3642 * mode) to see if we can flip rather than do a full mode set. In the
3643 * fastboot case, we'll flip, but if we don't update the pipesrc and
3644 * pfit state, we'll end up with a big fb scanned out into the wrong
3645 * sized surface.
e30e8f75
GP
3646 */
3647
e30e8f75 3648 I915_WRITE(PIPESRC(crtc->pipe),
bfd16b2a
ML
3649 ((pipe_config->pipe_src_w - 1) << 16) |
3650 (pipe_config->pipe_src_h - 1));
3651
3652 /* on skylake this is done by detaching scalers */
6315b5d3 3653 if (INTEL_GEN(dev_priv) >= 9) {
bfd16b2a
ML
3654 skl_detach_scalers(crtc);
3655
3656 if (pipe_config->pch_pfit.enabled)
3657 skylake_pfit_enable(crtc);
6e266956 3658 } else if (HAS_PCH_SPLIT(dev_priv)) {
bfd16b2a
ML
3659 if (pipe_config->pch_pfit.enabled)
3660 ironlake_pfit_enable(crtc);
3661 else if (old_crtc_state->pch_pfit.enabled)
3662 ironlake_pfit_disable(crtc, true);
e30e8f75 3663 }
e30e8f75
GP
3664}
3665
4cbe4b2b 3666static void intel_fdi_normal_train(struct intel_crtc *crtc)
5e84e1a4 3667{
4cbe4b2b 3668 struct drm_device *dev = crtc->base.dev;
fac5e23e 3669 struct drm_i915_private *dev_priv = to_i915(dev);
4cbe4b2b 3670 int pipe = crtc->pipe;
f0f59a00
VS
3671 i915_reg_t reg;
3672 u32 temp;
5e84e1a4
ZW
3673
3674 /* enable normal train */
3675 reg = FDI_TX_CTL(pipe);
3676 temp = I915_READ(reg);
fd6b8f43 3677 if (IS_IVYBRIDGE(dev_priv)) {
357555c0
JB
3678 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3679 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP
3680 } else {
3681 temp &= ~FDI_LINK_TRAIN_NONE;
3682 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3683 }
5e84e1a4
ZW
3684 I915_WRITE(reg, temp);
3685
3686 reg = FDI_RX_CTL(pipe);
3687 temp = I915_READ(reg);
6e266956 3688 if (HAS_PCH_CPT(dev_priv)) {
5e84e1a4
ZW
3689 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3690 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3691 } else {
3692 temp &= ~FDI_LINK_TRAIN_NONE;
3693 temp |= FDI_LINK_TRAIN_NONE;
3694 }
3695 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3696
3697 /* wait one idle pattern time */
3698 POSTING_READ(reg);
3699 udelay(1000);
357555c0
JB
3700
3701 /* IVB wants error correction enabled */
fd6b8f43 3702 if (IS_IVYBRIDGE(dev_priv))
357555c0
JB
3703 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3704 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW
3705}
3706
8db9d77b 3707/* The FDI link training functions for ILK/Ibexpeak. */
dc4a1094
ACO
3708static void ironlake_fdi_link_train(struct intel_crtc *crtc,
3709 const struct intel_crtc_state *crtc_state)
8db9d77b 3710{
4cbe4b2b 3711 struct drm_device *dev = crtc->base.dev;
fac5e23e 3712 struct drm_i915_private *dev_priv = to_i915(dev);
4cbe4b2b 3713 int pipe = crtc->pipe;
f0f59a00
VS
3714 i915_reg_t reg;
3715 u32 temp, tries;
8db9d77b 3716
1c8562f6 3717 /* FDI needs bits from pipe first */
0fc932b8 3718 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3719
e1a44743
AJ
3720 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3721 for train result */
5eddb70b
CW
3722 reg = FDI_RX_IMR(pipe);
3723 temp = I915_READ(reg);
e1a44743
AJ
3724 temp &= ~FDI_RX_SYMBOL_LOCK;
3725 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW
3726 I915_WRITE(reg, temp);
3727 I915_READ(reg);
e1a44743
AJ
3728 udelay(150);
3729
8db9d77b 3730 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW
3731 reg = FDI_TX_CTL(pipe);
3732 temp = I915_READ(reg);
627eb5a3 3733 temp &= ~FDI_DP_PORT_WIDTH_MASK;
dc4a1094 3734 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
8db9d77b
ZW
3735 temp &= ~FDI_LINK_TRAIN_NONE;
3736 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3737 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3738
5eddb70b
CW
3739 reg = FDI_RX_CTL(pipe);
3740 temp = I915_READ(reg);
8db9d77b
ZW
3741 temp &= ~FDI_LINK_TRAIN_NONE;
3742 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW
3743 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3744
3745 POSTING_READ(reg);
8db9d77b
ZW
3746 udelay(150);
3747
5b2adf89 3748 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV
3749 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3750 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3751 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3752
5eddb70b 3753 reg = FDI_RX_IIR(pipe);
e1a44743 3754 for (tries = 0; tries < 5; tries++) {
5eddb70b 3755 temp = I915_READ(reg);
8db9d77b
ZW
3756 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3757
3758 if ((temp & FDI_RX_BIT_LOCK)) {
3759 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3760 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW
3761 break;
3762 }
8db9d77b 3763 }
e1a44743 3764 if (tries == 5)
5eddb70b 3765 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW
3766
3767 /* Train 2 */
5eddb70b
CW
3768 reg = FDI_TX_CTL(pipe);
3769 temp = I915_READ(reg);
8db9d77b
ZW
3770 temp &= ~FDI_LINK_TRAIN_NONE;
3771 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3772 I915_WRITE(reg, temp);
8db9d77b 3773
5eddb70b
CW
3774 reg = FDI_RX_CTL(pipe);
3775 temp = I915_READ(reg);
8db9d77b
ZW
3776 temp &= ~FDI_LINK_TRAIN_NONE;
3777 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3778 I915_WRITE(reg, temp);
8db9d77b 3779
5eddb70b
CW
3780 POSTING_READ(reg);
3781 udelay(150);
8db9d77b 3782
5eddb70b 3783 reg = FDI_RX_IIR(pipe);
e1a44743 3784 for (tries = 0; tries < 5; tries++) {
5eddb70b 3785 temp = I915_READ(reg);
8db9d77b
ZW
3786 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3787
3788 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3789 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW
3790 DRM_DEBUG_KMS("FDI train 2 done.\n");
3791 break;
3792 }
8db9d77b 3793 }
e1a44743 3794 if (tries == 5)
5eddb70b 3795 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW
3796
3797 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3798
8db9d77b
ZW
3799}
3800
0206e353 3801static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW
3802 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3803 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3804 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3805 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3806};
3807
3808/* The FDI link training functions for SNB/Cougarpoint. */
dc4a1094
ACO
3809static void gen6_fdi_link_train(struct intel_crtc *crtc,
3810 const struct intel_crtc_state *crtc_state)
8db9d77b 3811{
4cbe4b2b 3812 struct drm_device *dev = crtc->base.dev;
fac5e23e 3813 struct drm_i915_private *dev_priv = to_i915(dev);
4cbe4b2b 3814 int pipe = crtc->pipe;
f0f59a00
VS
3815 i915_reg_t reg;
3816 u32 temp, i, retry;
8db9d77b 3817
e1a44743
AJ
3818 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3819 for train result */
5eddb70b
CW
3820 reg = FDI_RX_IMR(pipe);
3821 temp = I915_READ(reg);
e1a44743
AJ
3822 temp &= ~FDI_RX_SYMBOL_LOCK;
3823 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW
3824 I915_WRITE(reg, temp);
3825
3826 POSTING_READ(reg);
e1a44743
AJ
3827 udelay(150);
3828
8db9d77b 3829 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW
3830 reg = FDI_TX_CTL(pipe);
3831 temp = I915_READ(reg);
627eb5a3 3832 temp &= ~FDI_DP_PORT_WIDTH_MASK;
dc4a1094 3833 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
8db9d77b
ZW
3834 temp &= ~FDI_LINK_TRAIN_NONE;
3835 temp |= FDI_LINK_TRAIN_PATTERN_1;
3836 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3837 /* SNB-B */
3838 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3839 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3840
d74cf324
DV
3841 I915_WRITE(FDI_RX_MISC(pipe),
3842 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3843
5eddb70b
CW
3844 reg = FDI_RX_CTL(pipe);
3845 temp = I915_READ(reg);
6e266956 3846 if (HAS_PCH_CPT(dev_priv)) {
8db9d77b
ZW
3847 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3848 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3849 } else {
3850 temp &= ~FDI_LINK_TRAIN_NONE;
3851 temp |= FDI_LINK_TRAIN_PATTERN_1;
3852 }
5eddb70b
CW
3853 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3854
3855 POSTING_READ(reg);
8db9d77b
ZW
3856 udelay(150);
3857
0206e353 3858 for (i = 0; i < 4; i++) {
5eddb70b
CW
3859 reg = FDI_TX_CTL(pipe);
3860 temp = I915_READ(reg);
8db9d77b
ZW
3861 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3862 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW
3863 I915_WRITE(reg, temp);
3864
3865 POSTING_READ(reg);
8db9d77b
ZW
3866 udelay(500);
3867
fa37d39e
SP
3868 for (retry = 0; retry < 5; retry++) {
3869 reg = FDI_RX_IIR(pipe);
3870 temp = I915_READ(reg);
3871 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3872 if (temp & FDI_RX_BIT_LOCK) {
3873 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3874 DRM_DEBUG_KMS("FDI train 1 done.\n");
3875 break;
3876 }
3877 udelay(50);
8db9d77b 3878 }
fa37d39e
SP
3879 if (retry < 5)
3880 break;
8db9d77b
ZW
3881 }
3882 if (i == 4)
5eddb70b 3883 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW
3884
3885 /* Train 2 */
5eddb70b
CW
3886 reg = FDI_TX_CTL(pipe);
3887 temp = I915_READ(reg);
8db9d77b
ZW
3888 temp &= ~FDI_LINK_TRAIN_NONE;
3889 temp |= FDI_LINK_TRAIN_PATTERN_2;
5db94019 3890 if (IS_GEN6(dev_priv)) {
8db9d77b
ZW
3891 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3892 /* SNB-B */
3893 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3894 }
5eddb70b 3895 I915_WRITE(reg, temp);
8db9d77b 3896
5eddb70b
CW
3897 reg = FDI_RX_CTL(pipe);
3898 temp = I915_READ(reg);
6e266956 3899 if (HAS_PCH_CPT(dev_priv)) {
8db9d77b
ZW
3900 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3901 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3902 } else {
3903 temp &= ~FDI_LINK_TRAIN_NONE;
3904 temp |= FDI_LINK_TRAIN_PATTERN_2;
3905 }
5eddb70b
CW
3906 I915_WRITE(reg, temp);
3907
3908 POSTING_READ(reg);
8db9d77b
ZW
3909 udelay(150);
3910
0206e353 3911 for (i = 0; i < 4; i++) {
5eddb70b
CW
3912 reg = FDI_TX_CTL(pipe);
3913 temp = I915_READ(reg);
8db9d77b
ZW
3914 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3915 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW
3916 I915_WRITE(reg, temp);
3917
3918 POSTING_READ(reg);
8db9d77b
ZW
3919 udelay(500);
3920
fa37d39e
SP
3921 for (retry = 0; retry < 5; retry++) {
3922 reg = FDI_RX_IIR(pipe);
3923 temp = I915_READ(reg);
3924 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3925 if (temp & FDI_RX_SYMBOL_LOCK) {
3926 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3927 DRM_DEBUG_KMS("FDI train 2 done.\n");
3928 break;
3929 }
3930 udelay(50);
8db9d77b 3931 }
fa37d39e
SP
3932 if (retry < 5)
3933 break;
8db9d77b
ZW
3934 }
3935 if (i == 4)
5eddb70b 3936 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW
3937
3938 DRM_DEBUG_KMS("FDI train done.\n");
3939}
3940
357555c0 3941/* Manual link training for Ivy Bridge A0 parts */
dc4a1094
ACO
3942static void ivb_manual_fdi_link_train(struct intel_crtc *crtc,
3943 const struct intel_crtc_state *crtc_state)
357555c0 3944{
4cbe4b2b 3945 struct drm_device *dev = crtc->base.dev;
fac5e23e 3946 struct drm_i915_private *dev_priv = to_i915(dev);
4cbe4b2b 3947 int pipe = crtc->pipe;
f0f59a00
VS
3948 i915_reg_t reg;
3949 u32 temp, i, j;
357555c0
JB
3950
3951 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3952 for train result */
3953 reg = FDI_RX_IMR(pipe);
3954 temp = I915_READ(reg);
3955 temp &= ~FDI_RX_SYMBOL_LOCK;
3956 temp &= ~FDI_RX_BIT_LOCK;
3957 I915_WRITE(reg, temp);
3958
3959 POSTING_READ(reg);
3960 udelay(150);
3961
01a415fd
DV
3962 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3963 I915_READ(FDI_RX_IIR(pipe)));
3964
139ccd3f
JB
3965 /* Try each vswing and preemphasis setting twice before moving on */
3966 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3967 /* disable first in case we need to retry */
3968 reg = FDI_TX_CTL(pipe);
3969 temp = I915_READ(reg);
3970 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3971 temp &= ~FDI_TX_ENABLE;
3972 I915_WRITE(reg, temp);
357555c0 3973
139ccd3f
JB
3974 reg = FDI_RX_CTL(pipe);
3975 temp = I915_READ(reg);
3976 temp &= ~FDI_LINK_TRAIN_AUTO;
3977 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3978 temp &= ~FDI_RX_ENABLE;
3979 I915_WRITE(reg, temp);
357555c0 3980
139ccd3f 3981 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB
3982 reg = FDI_TX_CTL(pipe);
3983 temp = I915_READ(reg);
139ccd3f 3984 temp &= ~FDI_DP_PORT_WIDTH_MASK;
dc4a1094 3985 temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes);
139ccd3f 3986 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3987 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB
3988 temp |= snb_b_fdi_train_param[j/2];
3989 temp |= FDI_COMPOSITE_SYNC;
3990 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3991
139ccd3f
JB
3992 I915_WRITE(FDI_RX_MISC(pipe),
3993 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3994
139ccd3f 3995 reg = FDI_RX_CTL(pipe);
357555c0 3996 temp = I915_READ(reg);
139ccd3f
JB
3997 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3998 temp |= FDI_COMPOSITE_SYNC;
3999 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 4000
139ccd3f
JB
4001 POSTING_READ(reg);
4002 udelay(1); /* should be 0.5us */
357555c0 4003
139ccd3f
JB
4004 for (i = 0; i < 4; i++) {
4005 reg = FDI_RX_IIR(pipe);
4006 temp = I915_READ(reg);
4007 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 4008
139ccd3f
JB
4009 if (temp & FDI_RX_BIT_LOCK ||
4010 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
4011 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
4012 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
4013 i);
4014 break;
4015 }
4016 udelay(1); /* should be 0.5us */
4017 }
4018 if (i == 4) {
4019 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
4020 continue;
4021 }
357555c0 4022
139ccd3f 4023 /* Train 2 */
357555c0
JB
4024 reg = FDI_TX_CTL(pipe);
4025 temp = I915_READ(reg);
139ccd3f
JB
4026 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
4027 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
4028 I915_WRITE(reg, temp);
4029
4030 reg = FDI_RX_CTL(pipe);
4031 temp = I915_READ(reg);
4032 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4033 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB
4034 I915_WRITE(reg, temp);
4035
4036 POSTING_READ(reg);
139ccd3f 4037 udelay(2); /* should be 1.5us */
357555c0 4038
139ccd3f
JB
4039 for (i = 0; i < 4; i++) {
4040 reg = FDI_RX_IIR(pipe);
4041 temp = I915_READ(reg);
4042 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 4043
139ccd3f
JB
4044 if (temp & FDI_RX_SYMBOL_LOCK ||
4045 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
4046 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
4047 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
4048 i);
4049 goto train_done;
4050 }
4051 udelay(2); /* should be 1.5us */
357555c0 4052 }
139ccd3f
JB
4053 if (i == 4)
4054 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 4055 }
357555c0 4056
139ccd3f 4057train_done:
357555c0
JB
4058 DRM_DEBUG_KMS("FDI train done.\n");
4059}
4060
88cefb6c 4061static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 4062{
88cefb6c 4063 struct drm_device *dev = intel_crtc->base.dev;
fac5e23e 4064 struct drm_i915_private *dev_priv = to_i915(dev);
2c07245f 4065 int pipe = intel_crtc->pipe;
f0f59a00
VS
4066 i915_reg_t reg;
4067 u32 temp;
c64e311e 4068
c98e9dcf 4069 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW
4070 reg = FDI_RX_CTL(pipe);
4071 temp = I915_READ(reg);
627eb5a3 4072 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 4073 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 4074 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW
4075 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4076
4077 POSTING_READ(reg);
c98e9dcf
JB
4078 udelay(200);
4079
4080 /* Switch from Rawclk to PCDclk */
5eddb70b
CW
4081 temp = I915_READ(reg);
4082 I915_WRITE(reg, temp | FDI_PCDCLK);
4083
4084 POSTING_READ(reg);
c98e9dcf
JB
4085 udelay(200);
4086
20749730
PZ
4087 /* Enable CPU FDI TX PLL, always on for Ironlake */
4088 reg = FDI_TX_CTL(pipe);
4089 temp = I915_READ(reg);
4090 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
4091 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 4092
20749730
PZ
4093 POSTING_READ(reg);
4094 udelay(100);
6be4a607 4095 }
0e23b99d
JB
4096}
4097
88cefb6c
DV
4098static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
4099{
4100 struct drm_device *dev = intel_crtc->base.dev;
fac5e23e 4101 struct drm_i915_private *dev_priv = to_i915(dev);
88cefb6c 4102 int pipe = intel_crtc->pipe;
f0f59a00
VS
4103 i915_reg_t reg;
4104 u32 temp;
88cefb6c
DV
4105
4106 /* Switch from PCDclk to Rawclk */
4107 reg = FDI_RX_CTL(pipe);
4108 temp = I915_READ(reg);
4109 I915_WRITE(reg, temp & ~FDI_PCDCLK);
4110
4111 /* Disable CPU FDI TX PLL */
4112 reg = FDI_TX_CTL(pipe);
4113 temp = I915_READ(reg);
4114 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
4115
4116 POSTING_READ(reg);
4117 udelay(100);
4118
4119 reg = FDI_RX_CTL(pipe);
4120 temp = I915_READ(reg);
4121 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
4122
4123 /* Wait for the clocks to turn off. */
4124 POSTING_READ(reg);
4125 udelay(100);
4126}
4127
0fc932b8
JB
4128static void ironlake_fdi_disable(struct drm_crtc *crtc)
4129{
4130 struct drm_device *dev = crtc->dev;
fac5e23e 4131 struct drm_i915_private *dev_priv = to_i915(dev);
0fc932b8
JB
4132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4133 int pipe = intel_crtc->pipe;
f0f59a00
VS
4134 i915_reg_t reg;
4135 u32 temp;
0fc932b8
JB
4136
4137 /* disable CPU FDI tx and PCH FDI rx */
4138 reg = FDI_TX_CTL(pipe);
4139 temp = I915_READ(reg);
4140 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
4141 POSTING_READ(reg);
4142
4143 reg = FDI_RX_CTL(pipe);
4144 temp = I915_READ(reg);
4145 temp &= ~(0x7 << 16);
dfd07d72 4146 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB
4147 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
4148
4149 POSTING_READ(reg);
4150 udelay(100);
4151
4152 /* Ironlake workaround, disable clock pointer after downing FDI */
6e266956 4153 if (HAS_PCH_IBX(dev_priv))
6f06ce18 4154 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB
4155
4156 /* still set train pattern 1 */
4157 reg = FDI_TX_CTL(pipe);
4158 temp = I915_READ(reg);
4159 temp &= ~FDI_LINK_TRAIN_NONE;
4160 temp |= FDI_LINK_TRAIN_PATTERN_1;
4161 I915_WRITE(reg, temp);
4162
4163 reg = FDI_RX_CTL(pipe);
4164 temp = I915_READ(reg);
6e266956 4165 if (HAS_PCH_CPT(dev_priv)) {
0fc932b8
JB
4166 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
4167 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
4168 } else {
4169 temp &= ~FDI_LINK_TRAIN_NONE;
4170 temp |= FDI_LINK_TRAIN_PATTERN_1;
4171 }
4172 /* BPC in FDI rx is consistent with that in PIPECONF */
4173 temp &= ~(0x07 << 16);
dfd07d72 4174 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB
4175 I915_WRITE(reg, temp);
4176
4177 POSTING_READ(reg);
4178 udelay(100);
4179}
4180
49d73912 4181bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
5dce5b93
CW
4182{
4183 struct intel_crtc *crtc;
4184
4185 /* Note that we don't need to be called with mode_config.lock here
4186 * as our list of CRTC objects is static for the lifetime of the
4187 * device and so cannot disappear as we iterate. Similarly, we can
4188 * happily treat the predicates as racy, atomic checks as userspace
4189 * cannot claim and pin a new fb without at least acquring the
4190 * struct_mutex and so serialising with us.
4191 */
49d73912 4192 for_each_intel_crtc(&dev_priv->drm, crtc) {
5dce5b93
CW
4193 if (atomic_read(&crtc->unpin_work_count) == 0)
4194 continue;
4195
5a21b665 4196 if (crtc->flip_work)
0f0f74bc 4197 intel_wait_for_vblank(dev_priv, crtc->pipe);
5dce5b93
CW
4198
4199 return true;
4200 }
4201
4202 return false;
4203}
4204
5a21b665 4205static void page_flip_completed(struct intel_crtc *intel_crtc)
d6bbafa1
CW
4206{
4207 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
5a21b665
DV
4208 struct intel_flip_work *work = intel_crtc->flip_work;
4209
4210 intel_crtc->flip_work = NULL;
d6bbafa1
CW
4211
4212 if (work->event)
560ce1dc 4213 drm_crtc_send_vblank_event(&intel_crtc->base, work->event);
d6bbafa1
CW
4214
4215 drm_crtc_vblank_put(&intel_crtc->base);
4216
5a21b665 4217 wake_up_all(&dev_priv->pending_flip_queue);
5a21b665
DV
4218 trace_i915_flip_complete(intel_crtc->plane,
4219 work->pending_flip_obj);
05c41f92
AR
4220
4221 queue_work(dev_priv->wq, &work->unpin_work);
d6bbafa1
CW
4222}
4223
5008e874 4224static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 4225{
0f91128d 4226 struct drm_device *dev = crtc->dev;
fac5e23e 4227 struct drm_i915_private *dev_priv = to_i915(dev);
5008e874 4228 long ret;
e6c3a2a6 4229
2c10d571 4230 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
5008e874
ML
4231
4232 ret = wait_event_interruptible_timeout(
4233 dev_priv->pending_flip_queue,
4234 !intel_crtc_has_pending_flip(crtc),
4235 60*HZ);
4236
4237 if (ret < 0)
4238 return ret;
4239
5a21b665
DV
4240 if (ret == 0) {
4241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4242 struct intel_flip_work *work;
4243
4244 spin_lock_irq(&dev->event_lock);
4245 work = intel_crtc->flip_work;
4246 if (work && !is_mmio_work(work)) {
4247 WARN_ONCE(1, "Removing stuck page flip\n");
4248 page_flip_completed(intel_crtc);
4249 }
4250 spin_unlock_irq(&dev->event_lock);
4251 }
5bb61643 4252
5008e874 4253 return 0;
e6c3a2a6
CW
4254}
4255
b7076546 4256void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
060f02d8
VS
4257{
4258 u32 temp;
4259
4260 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
4261
4262 mutex_lock(&dev_priv->sb_lock);
4263
4264 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4265 temp |= SBI_SSCCTL_DISABLE;
4266 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4267
4268 mutex_unlock(&dev_priv->sb_lock);
4269}
4270
e615efe4 4271/* Program iCLKIP clock to the desired frequency */
0dcdc382 4272static void lpt_program_iclkip(struct intel_crtc *crtc)
e615efe4 4273{
0dcdc382
ACO
4274 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4275 int clock = crtc->config->base.adjusted_mode.crtc_clock;
e615efe4
ED
4276 u32 divsel, phaseinc, auxdiv, phasedir = 0;
4277 u32 temp;
4278
060f02d8 4279 lpt_disable_iclkip(dev_priv);
e615efe4 4280
64b46a06
VS
4281 /* The iCLK virtual clock root frequency is in MHz,
4282 * but the adjusted_mode->crtc_clock in in KHz. To get the
4283 * divisors, it is necessary to divide one by another, so we
4284 * convert the virtual clock precision to KHz here for higher
4285 * precision.
4286 */
4287 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
e615efe4
ED
4288 u32 iclk_virtual_root_freq = 172800 * 1000;
4289 u32 iclk_pi_range = 64;
64b46a06 4290 u32 desired_divisor;
e615efe4 4291
64b46a06
VS
4292 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4293 clock << auxdiv);
4294 divsel = (desired_divisor / iclk_pi_range) - 2;
4295 phaseinc = desired_divisor % iclk_pi_range;
e615efe4 4296
64b46a06
VS
4297 /*
4298 * Near 20MHz is a corner case which is
4299 * out of range for the 7-bit divisor
4300 */
4301 if (divsel <= 0x7f)
4302 break;
e615efe4
ED
4303 }
4304
4305 /* This should not happen with any sane values */
4306 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4307 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4308 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4309 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4310
4311 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 4312 clock,
e615efe4
ED
4313 auxdiv,
4314 divsel,
4315 phasedir,
4316 phaseinc);
4317
060f02d8
VS
4318 mutex_lock(&dev_priv->sb_lock);
4319
e615efe4 4320 /* Program SSCDIVINTPHASE6 */
988d6ee8 4321 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED
4322 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4323 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4324 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4325 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4326 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4327 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 4328 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED
4329
4330 /* Program SSCAUXDIV */
988d6ee8 4331 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED
4332 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4333 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 4334 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED
4335
4336 /* Enable modulator and associated divider */
988d6ee8 4337 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 4338 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 4339 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4 4340
060f02d8
VS
4341 mutex_unlock(&dev_priv->sb_lock);
4342
e615efe4
ED
4343 /* Wait for initialization time */
4344 udelay(24);
4345
4346 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4347}
4348
8802e5b6
VS
4349int lpt_get_iclkip(struct drm_i915_private *dev_priv)
4350{
4351 u32 divsel, phaseinc, auxdiv;
4352 u32 iclk_virtual_root_freq = 172800 * 1000;
4353 u32 iclk_pi_range = 64;
4354 u32 desired_divisor;
4355 u32 temp;
4356
4357 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
4358 return 0;
4359
4360 mutex_lock(&dev_priv->sb_lock);
4361
4362 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4363 if (temp & SBI_SSCCTL_DISABLE) {
4364 mutex_unlock(&dev_priv->sb_lock);
4365 return 0;
4366 }
4367
4368 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4369 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
4370 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
4371 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
4372 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
4373
4374 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4375 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
4376 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
4377
4378 mutex_unlock(&dev_priv->sb_lock);
4379
4380 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
4381
4382 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
4383 desired_divisor << auxdiv);
4384}
4385
275f01b2
DV
4386static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4387 enum pipe pch_transcoder)
4388{
4389 struct drm_device *dev = crtc->base.dev;
fac5e23e 4390 struct drm_i915_private *dev_priv = to_i915(dev);
6e3c9717 4391 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV
4392
4393 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4394 I915_READ(HTOTAL(cpu_transcoder)));
4395 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4396 I915_READ(HBLANK(cpu_transcoder)));
4397 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4398 I915_READ(HSYNC(cpu_transcoder)));
4399
4400 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4401 I915_READ(VTOTAL(cpu_transcoder)));
4402 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4403 I915_READ(VBLANK(cpu_transcoder)));
4404 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4405 I915_READ(VSYNC(cpu_transcoder)));
4406 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4407 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4408}
4409
003632d9 4410static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78 4411{
fac5e23e 4412 struct drm_i915_private *dev_priv = to_i915(dev);
1fbc0d78
DV
4413 uint32_t temp;
4414
4415 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4416 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV
4417 return;
4418
4419 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4420 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4421
003632d9
ACO
4422 temp &= ~FDI_BC_BIFURCATION_SELECT;
4423 if (enable)
4424 temp |= FDI_BC_BIFURCATION_SELECT;
4425
4426 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV
4427 I915_WRITE(SOUTH_CHICKEN1, temp);
4428 POSTING_READ(SOUTH_CHICKEN1);
4429}
4430
4431static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4432{
4433 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV
4434
4435 switch (intel_crtc->pipe) {
4436 case PIPE_A:
4437 break;
4438 case PIPE_B:
6e3c9717 4439 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4440 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4441 else
003632d9 4442 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV
4443
4444 break;
4445 case PIPE_C:
003632d9 4446 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV
4447
4448 break;
4449 default:
4450 BUG();
4451 }
4452}
4453
c48b5305
VS
4454/* Return which DP Port should be selected for Transcoder DP control */
4455static enum port
4cbe4b2b 4456intel_trans_dp_port_sel(struct intel_crtc *crtc)
c48b5305 4457{
4cbe4b2b 4458 struct drm_device *dev = crtc->base.dev;
c48b5305
VS
4459 struct intel_encoder *encoder;
4460
4cbe4b2b 4461 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
cca0502b 4462 if (encoder->type == INTEL_OUTPUT_DP ||
c48b5305
VS
4463 encoder->type == INTEL_OUTPUT_EDP)
4464 return enc_to_dig_port(&encoder->base)->port;
4465 }
4466
4467 return -1;
4468}
4469
f67a559d
JB
4470/*
4471 * Enable PCH resources required for PCH ports:
4472 * - PCH PLLs
4473 * - FDI training & RX/TX
4474 * - update transcoder timings
4475 * - DP transcoding bits
4476 * - transcoder
4477 */
2ce42273 4478static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state)
0e23b99d 4479{
2ce42273 4480 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
4cbe4b2b 4481 struct drm_device *dev = crtc->base.dev;
fac5e23e 4482 struct drm_i915_private *dev_priv = to_i915(dev);
4cbe4b2b 4483 int pipe = crtc->pipe;
f0f59a00 4484 u32 temp;
2c07245f 4485
ab9412ba 4486 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4487
fd6b8f43 4488 if (IS_IVYBRIDGE(dev_priv))
4cbe4b2b 4489 ivybridge_update_fdi_bc_bifurcation(crtc);
1fbc0d78 4490
cd986abb
DV
4491 /* Write the TU size bits before fdi link training, so that error
4492 * detection works. */
4493 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4494 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4495
c98e9dcf 4496 /* For PCH output, training FDI link */
dc4a1094 4497 dev_priv->display.fdi_link_train(crtc, crtc_state);
2c07245f 4498
3ad8a208
DV
4499 /* We need to program the right clock selection before writing the pixel
4500 * mutliplier into the DPLL. */
6e266956 4501 if (HAS_PCH_CPT(dev_priv)) {
ee7b9f93 4502 u32 sel;
4b645f14 4503
c98e9dcf 4504 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV
4505 temp |= TRANS_DPLL_ENABLE(pipe);
4506 sel = TRANS_DPLLB_SEL(pipe);
2ce42273 4507 if (crtc_state->shared_dpll ==
8106ddbd 4508 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
ee7b9f93
JB
4509 temp |= sel;
4510 else
4511 temp &= ~sel;
c98e9dcf 4512 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4513 }
5eddb70b 4514
3ad8a208
DV
4515 /* XXX: pch pll's can be enabled any time before we enable the PCH
4516 * transcoder, and we actually should do this to not upset any PCH
4517 * transcoder that already use the clock when we share it.
4518 *
4519 * Note that enable_shared_dpll tries to do the right thing, but
4520 * get_shared_dpll unconditionally resets the pll - we need that to have
4521 * the right LVDS enable sequence. */
4cbe4b2b 4522 intel_enable_shared_dpll(crtc);
3ad8a208 4523
d9b6cb56
JB
4524 /* set transcoder timing, panel must allow it */
4525 assert_panel_unlocked(dev_priv, pipe);
4cbe4b2b 4526 ironlake_pch_transcoder_set_timings(crtc, pipe);
8db9d77b 4527
303b81e0 4528 intel_fdi_normal_train(crtc);
5e84e1a4 4529
c98e9dcf 4530 /* For PCH DP, enable TRANS_DP_CTL */
6e266956 4531 if (HAS_PCH_CPT(dev_priv) &&
2ce42273 4532 intel_crtc_has_dp_encoder(crtc_state)) {
9c4edaee 4533 const struct drm_display_mode *adjusted_mode =
2ce42273 4534 &crtc_state->base.adjusted_mode;
dfd07d72 4535 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
f0f59a00 4536 i915_reg_t reg = TRANS_DP_CTL(pipe);
5eddb70b
CW
4537 temp = I915_READ(reg);
4538 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA
4539 TRANS_DP_SYNC_MASK |
4540 TRANS_DP_BPC_MASK);
e3ef4479 4541 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4542 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf 4543
9c4edaee 4544 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4545 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
9c4edaee 4546 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4547 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB
4548
4549 switch (intel_trans_dp_port_sel(crtc)) {
c48b5305 4550 case PORT_B:
5eddb70b 4551 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 4552 break;
c48b5305 4553 case PORT_C:
5eddb70b 4554 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf 4555 break;
c48b5305 4556 case PORT_D:
5eddb70b 4557 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB
4558 break;
4559 default:
e95d41e1 4560 BUG();
32f9d658 4561 }
2c07245f 4562
5eddb70b 4563 I915_WRITE(reg, temp);
6be4a607 4564 }
b52eb4dc 4565
b8a4f404 4566 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB
4567}
4568
2ce42273 4569static void lpt_pch_enable(const struct intel_crtc_state *crtc_state)
1507e5bd 4570{
2ce42273 4571 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
0dcdc382 4572 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2ce42273 4573 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1507e5bd 4574
ab9412ba 4575 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4576
8c52b5e8 4577 lpt_program_iclkip(crtc);
1507e5bd 4578
0540e488 4579 /* Set transcoder timing. */
0dcdc382 4580 ironlake_pch_transcoder_set_timings(crtc, PIPE_A);
1507e5bd 4581
937bb610 4582 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB
4583}
4584
a1520318 4585static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57 4586{
fac5e23e 4587 struct drm_i915_private *dev_priv = to_i915(dev);
f0f59a00 4588 i915_reg_t dslreg = PIPEDSL(pipe);
d4270e57
JB
4589 u32 temp;
4590
4591 temp = I915_READ(dslreg);
4592 udelay(500);
4593 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4594 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4595 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB
4596 }
4597}
4598
86adf9d7
ML
4599static int
4600skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4601 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4602 int src_w, int src_h, int dst_w, int dst_h)
a1b2278e 4603{
86adf9d7
ML
4604 struct intel_crtc_scaler_state *scaler_state =
4605 &crtc_state->scaler_state;
4606 struct intel_crtc *intel_crtc =
4607 to_intel_crtc(crtc_state->base.crtc);
a1b2278e 4608 int need_scaling;
6156a456 4609
bd2ef25d 4610 need_scaling = drm_rotation_90_or_270(rotation) ?
6156a456
CK
4611 (src_h != dst_w || src_w != dst_h):
4612 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK
4613
4614 /*
4615 * if plane is being disabled or scaler is no more required or force detach
4616 * - free scaler binded to this plane/crtc
4617 * - in order to do this, update crtc->scaler_usage
4618 *
4619 * Here scaler state in crtc_state is set free so that
4620 * scaler can be assigned to other user. Actual register
4621 * update to free the scaler is done in plane/panel-fit programming.
4622 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4623 */
86adf9d7 4624 if (force_detach || !need_scaling) {
a1b2278e 4625 if (*scaler_id >= 0) {
86adf9d7 4626 scaler_state->scaler_users &= ~(1 << scaler_user);
a1b2278e
CK
4627 scaler_state->scalers[*scaler_id].in_use = 0;
4628
86adf9d7
ML
4629 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4630 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4631 intel_crtc->pipe, scaler_user, *scaler_id,
a1b2278e
CK
4632 scaler_state->scaler_users);
4633 *scaler_id = -1;
4634 }
4635 return 0;
4636 }
4637
4638 /* range checks */
4639 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4640 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4641
4642 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4643 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
86adf9d7 4644 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
a1b2278e 4645 "size is out of scaler range\n",
86adf9d7 4646 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
a1b2278e
CK
4647 return -EINVAL;
4648 }
4649
86adf9d7
ML
4650 /* mark this plane as a scaler user in crtc_state */
4651 scaler_state->scaler_users |= (1 << scaler_user);
4652 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4653 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4654 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4655 scaler_state->scaler_users);
4656
4657 return 0;
4658}
4659
4660/**
4661 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4662 *
4663 * @state: crtc's scaler state
86adf9d7
ML
4664 *
4665 * Return
4666 * 0 - scaler_usage updated successfully
4667 * error - requested scaling cannot be supported or other error condition
4668 */
e435d6e5 4669int skl_update_scaler_crtc(struct intel_crtc_state *state)
86adf9d7 4670{
7c5f93b0 4671 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
86adf9d7 4672
e435d6e5 4673 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
31ad61e4 4674 &state->scaler_state.scaler_id, DRM_ROTATE_0,
86adf9d7 4675 state->pipe_src_w, state->pipe_src_h,
aad941d5 4676 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
86adf9d7
ML
4677}
4678
4679/**
4680 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4681 *
4682 * @state: crtc's scaler state
86adf9d7
ML
4683 * @plane_state: atomic plane state to update
4684 *
4685 * Return
4686 * 0 - scaler_usage updated successfully
4687 * error - requested scaling cannot be supported or other error condition
4688 */
da20eabd
ML
4689static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4690 struct intel_plane_state *plane_state)
86adf9d7
ML
4691{
4692
da20eabd
ML
4693 struct intel_plane *intel_plane =
4694 to_intel_plane(plane_state->base.plane);
86adf9d7
ML
4695 struct drm_framebuffer *fb = plane_state->base.fb;
4696 int ret;
4697
936e71e3 4698 bool force_detach = !fb || !plane_state->base.visible;
86adf9d7 4699
86adf9d7
ML
4700 ret = skl_update_scaler(crtc_state, force_detach,
4701 drm_plane_index(&intel_plane->base),
4702 &plane_state->scaler_id,
4703 plane_state->base.rotation,
936e71e3
VS
4704 drm_rect_width(&plane_state->base.src) >> 16,
4705 drm_rect_height(&plane_state->base.src) >> 16,
4706 drm_rect_width(&plane_state->base.dst),
4707 drm_rect_height(&plane_state->base.dst));
86adf9d7
ML
4708
4709 if (ret || plane_state->scaler_id < 0)
4710 return ret;
4711
a1b2278e 4712 /* check colorkey */
818ed961 4713 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
72660ce0
VS
4714 DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed",
4715 intel_plane->base.base.id,
4716 intel_plane->base.name);
a1b2278e
CK
4717 return -EINVAL;
4718 }
4719
4720 /* Check src format */
438b74a5 4721 switch (fb->format->format) {
86adf9d7
ML
4722 case DRM_FORMAT_RGB565:
4723 case DRM_FORMAT_XBGR8888:
4724 case DRM_FORMAT_XRGB8888:
4725 case DRM_FORMAT_ABGR8888:
4726 case DRM_FORMAT_ARGB8888:
4727 case DRM_FORMAT_XRGB2101010:
4728 case DRM_FORMAT_XBGR2101010:
4729 case DRM_FORMAT_YUYV:
4730 case DRM_FORMAT_YVYU:
4731 case DRM_FORMAT_UYVY:
4732 case DRM_FORMAT_VYUY:
4733 break;
4734 default:
72660ce0
VS
4735 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
4736 intel_plane->base.base.id, intel_plane->base.name,
438b74a5 4737 fb->base.id, fb->format->format);
86adf9d7 4738 return -EINVAL;
a1b2278e
CK
4739 }
4740
a1b2278e
CK
4741 return 0;
4742}
4743
e435d6e5
ML
4744static void skylake_scaler_disable(struct intel_crtc *crtc)
4745{
4746 int i;
4747
4748 for (i = 0; i < crtc->num_scalers; i++)
4749 skl_detach_scaler(crtc, i);
4750}
4751
4752static void skylake_pfit_enable(struct intel_crtc *crtc)
bd2e244f
JB
4753{
4754 struct drm_device *dev = crtc->base.dev;
fac5e23e 4755 struct drm_i915_private *dev_priv = to_i915(dev);
bd2e244f 4756 int pipe = crtc->pipe;
a1b2278e
CK
4757 struct intel_crtc_scaler_state *scaler_state =
4758 &crtc->config->scaler_state;
4759
6e3c9717 4760 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK
4761 int id;
4762
c3f8ad57 4763 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0))
a1b2278e 4764 return;
a1b2278e
CK
4765
4766 id = scaler_state->scaler_id;
4767 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4768 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4769 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4770 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
bd2e244f
JB
4771 }
4772}
4773
b074cec8
JB
4774static void ironlake_pfit_enable(struct intel_crtc *crtc)
4775{
4776 struct drm_device *dev = crtc->base.dev;
fac5e23e 4777 struct drm_i915_private *dev_priv = to_i915(dev);
b074cec8
JB
4778 int pipe = crtc->pipe;
4779
6e3c9717 4780 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB
4781 /* Force use of hard-coded filter coefficients
4782 * as some pre-programmed values are broken,
4783 * e.g. x201.
4784 */
fd6b8f43 4785 if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
b074cec8
JB
4786 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4787 PF_PIPE_SEL_IVB(pipe));
4788 else
4789 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO
4790 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4791 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB
4792 }
4793}
4794
20bc8673 4795void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4796{
cea165c3 4797 struct drm_device *dev = crtc->base.dev;
fac5e23e 4798 struct drm_i915_private *dev_priv = to_i915(dev);
d77e4531 4799
6e3c9717 4800 if (!crtc->config->ips_enabled)
d77e4531
PZ
4801 return;
4802
307e4498
ML
4803 /*
4804 * We can only enable IPS after we enable a plane and wait for a vblank
4805 * This function is called from post_plane_update, which is run after
4806 * a vblank wait.
4807 */
cea165c3 4808
d77e4531 4809 assert_plane_enabled(dev_priv, crtc->plane);
8652744b 4810 if (IS_BROADWELL(dev_priv)) {
2a114cc1
BW
4811 mutex_lock(&dev_priv->rps.hw_lock);
4812 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4813 mutex_unlock(&dev_priv->rps.hw_lock);
4814 /* Quoting Art Runyan: "its not safe to expect any particular
4815 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB
4816 * mailbox." Moreover, the mailbox may return a bogus state,
4817 * so we need to just enable it and continue on.
2a114cc1
BW
4818 */
4819 } else {
4820 I915_WRITE(IPS_CTL, IPS_ENABLE);
4821 /* The bit only becomes 1 in the next vblank, so this wait here
4822 * is essentially intel_wait_for_vblank. If we don't have this
4823 * and don't wait for vblanks until the end of crtc_enable, then
4824 * the HW state readout code will complain that the expected
4825 * IPS_CTL value is not the one we read. */
2ec9ba3c
CW
4826 if (intel_wait_for_register(dev_priv,
4827 IPS_CTL, IPS_ENABLE, IPS_ENABLE,
4828 50))
2a114cc1
BW
4829 DRM_ERROR("Timed out waiting for IPS enable\n");
4830 }
d77e4531
PZ
4831}
4832
20bc8673 4833void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ
4834{
4835 struct drm_device *dev = crtc->base.dev;
fac5e23e 4836 struct drm_i915_private *dev_priv = to_i915(dev);
d77e4531 4837
6e3c9717 4838 if (!crtc->config->ips_enabled)
d77e4531
PZ
4839 return;
4840
4841 assert_plane_enabled(dev_priv, crtc->plane);
8652744b 4842 if (IS_BROADWELL(dev_priv)) {
2a114cc1
BW
4843 mutex_lock(&dev_priv->rps.hw_lock);
4844 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4845 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130 4846 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
b85c1ecf
CW
4847 if (intel_wait_for_register(dev_priv,
4848 IPS_CTL, IPS_ENABLE, 0,
4849 42))
23d0b130 4850 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4851 } else {
2a114cc1 4852 I915_WRITE(IPS_CTL, 0);
e59150dc
JB
4853 POSTING_READ(IPS_CTL);
4854 }
d77e4531
PZ
4855
4856 /* We need to wait for a vblank before we can disable the plane. */
0f0f74bc 4857 intel_wait_for_vblank(dev_priv, crtc->pipe);
d77e4531
PZ
4858}
4859
7cac945f 4860static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4861{
7cac945f 4862 if (intel_crtc->overlay) {
d3eedb1a 4863 struct drm_device *dev = intel_crtc->base.dev;
d3eedb1a
VS
4864
4865 mutex_lock(&dev->struct_mutex);
d3eedb1a 4866 (void) intel_overlay_switch_off(intel_crtc->overlay);
d3eedb1a
VS
4867 mutex_unlock(&dev->struct_mutex);
4868 }
4869
4870 /* Let userspace switch the overlay on again. In most cases userspace
4871 * has to recompute where to put it anyway.
4872 */
4873}
4874
87d4300a
ML
4875/**
4876 * intel_post_enable_primary - Perform operations after enabling primary plane
4877 * @crtc: the CRTC whose primary plane was just enabled
4878 *
4879 * Performs potentially sleeping operations that must be done after the primary
4880 * plane is enabled, such as updating FBC and IPS. Note that this may be
4881 * called due to an explicit primary plane update, or due to an implicit
4882 * re-enable that is caused when a sprite plane is updated to no longer
4883 * completely hide the primary plane.
4884 */
4885static void
4886intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS
4887{
4888 struct drm_device *dev = crtc->dev;
fac5e23e 4889 struct drm_i915_private *dev_priv = to_i915(dev);
a5c4d7bc
VS
4890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4891 int pipe = intel_crtc->pipe;
a5c4d7bc 4892
87d4300a
ML
4893 /*
4894 * FIXME IPS should be fine as long as one plane is
4895 * enabled, but in practice it seems to have problems
4896 * when going from primary only to sprite only and vice
4897 * versa.
4898 */
a5c4d7bc
VS
4899 hsw_enable_ips(intel_crtc);
4900
f99d7069 4901 /*
87d4300a
ML
4902 * Gen2 reports pipe underruns whenever all planes are disabled.
4903 * So don't enable underrun reporting before at least some planes
4904 * are enabled.
4905 * FIXME: Need to fix the logic to work when we turn off all planes
4906 * but leave the pipe running.
f99d7069 4907 */
5db94019 4908 if (IS_GEN2(dev_priv))
87d4300a
ML
4909 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4910
aca7b684
VS
4911 /* Underruns don't always raise interrupts, so check manually. */
4912 intel_check_cpu_fifo_underruns(dev_priv);
4913 intel_check_pch_fifo_underruns(dev_priv);
a5c4d7bc
VS
4914}
4915
2622a081 4916/* FIXME move all this to pre_plane_update() with proper state tracking */
87d4300a
ML
4917static void
4918intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS
4919{
4920 struct drm_device *dev = crtc->dev;
fac5e23e 4921 struct drm_i915_private *dev_priv = to_i915(dev);
a5c4d7bc
VS
4922 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4923 int pipe = intel_crtc->pipe;
a5c4d7bc 4924
87d4300a
ML
4925 /*
4926 * Gen2 reports pipe underruns whenever all planes are disabled.
4927 * So diasble underrun reporting before all the planes get disabled.
4928 * FIXME: Need to fix the logic to work when we turn off all planes
4929 * but leave the pipe running.
4930 */
5db94019 4931 if (IS_GEN2(dev_priv))
87d4300a 4932 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4933
2622a081
VS
4934 /*
4935 * FIXME IPS should be fine as long as one plane is
4936 * enabled, but in practice it seems to have problems
4937 * when going from primary only to sprite only and vice
4938 * versa.
4939 */
4940 hsw_disable_ips(intel_crtc);
4941}
4942
4943/* FIXME get rid of this and use pre_plane_update */
4944static void
4945intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4946{
4947 struct drm_device *dev = crtc->dev;
fac5e23e 4948 struct drm_i915_private *dev_priv = to_i915(dev);
2622a081
VS
4949 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4950 int pipe = intel_crtc->pipe;
4951
4952 intel_pre_disable_primary(crtc);
4953
87d4300a
ML
4954 /*
4955 * Vblank time updates from the shadow to live plane control register
4956 * are blocked if the memory self-refresh mode is active at that
4957 * moment. So to make sure the plane gets truly disabled, disable
4958 * first the self-refresh mode. The self-refresh enable bit in turn
4959 * will be checked/applied by the HW only at the next frame start
4960 * event which is after the vblank start event, so we need to have a
4961 * wait-for-vblank between disabling the plane and the pipe.
4962 */
11a85d6a
VS
4963 if (HAS_GMCH_DISPLAY(dev_priv) &&
4964 intel_set_memory_cxsr(dev_priv, false))
0f0f74bc 4965 intel_wait_for_vblank(dev_priv, pipe);
87d4300a
ML
4966}
4967
5a21b665
DV
4968static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4969{
4970 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4971 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4972 struct intel_crtc_state *pipe_config =
4973 to_intel_crtc_state(crtc->base.state);
5a21b665
DV
4974 struct drm_plane *primary = crtc->base.primary;
4975 struct drm_plane_state *old_pri_state =
4976 drm_atomic_get_existing_plane_state(old_state, primary);
4977
5748b6a1 4978 intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits);
5a21b665 4979
5a21b665 4980 if (pipe_config->update_wm_post && pipe_config->base.active)
432081bc 4981 intel_update_watermarks(crtc);
5a21b665
DV
4982
4983 if (old_pri_state) {
4984 struct intel_plane_state *primary_state =
4985 to_intel_plane_state(primary->state);
4986 struct intel_plane_state *old_primary_state =
4987 to_intel_plane_state(old_pri_state);
4988
4989 intel_fbc_post_update(crtc);
4990
936e71e3 4991 if (primary_state->base.visible &&
5a21b665 4992 (needs_modeset(&pipe_config->base) ||
936e71e3 4993 !old_primary_state->base.visible))
5a21b665
DV
4994 intel_post_enable_primary(&crtc->base);
4995 }
4996}
4997
aa5e9b47
ML
4998static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
4999 struct intel_crtc_state *pipe_config)
ac21b225 5000{
5c74cd73 5001 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
ac21b225 5002 struct drm_device *dev = crtc->base.dev;
fac5e23e 5003 struct drm_i915_private *dev_priv = to_i915(dev);
5c74cd73
ML
5004 struct drm_atomic_state *old_state = old_crtc_state->base.state;
5005 struct drm_plane *primary = crtc->base.primary;
5006 struct drm_plane_state *old_pri_state =
5007 drm_atomic_get_existing_plane_state(old_state, primary);
5008 bool modeset = needs_modeset(&pipe_config->base);
ccf010fb
ML
5009 struct intel_atomic_state *old_intel_state =
5010 to_intel_atomic_state(old_state);
ac21b225 5011
5c74cd73
ML
5012 if (old_pri_state) {
5013 struct intel_plane_state *primary_state =
5014 to_intel_plane_state(primary->state);
5015 struct intel_plane_state *old_primary_state =
5016 to_intel_plane_state(old_pri_state);
5017
faf68d92 5018 intel_fbc_pre_update(crtc, pipe_config, primary_state);
31ae71fc 5019
936e71e3
VS
5020 if (old_primary_state->base.visible &&
5021 (modeset || !primary_state->base.visible))
5c74cd73
ML
5022 intel_pre_disable_primary(&crtc->base);
5023 }
852eb00d 5024
5eeb798b
VS
5025 /*
5026 * Vblank time updates from the shadow to live plane control register
5027 * are blocked if the memory self-refresh mode is active at that
5028 * moment. So to make sure the plane gets truly disabled, disable
5029 * first the self-refresh mode. The self-refresh enable bit in turn
5030 * will be checked/applied by the HW only at the next frame start
5031 * event which is after the vblank start event, so we need to have a
5032 * wait-for-vblank between disabling the plane and the pipe.
5033 */
5034 if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active &&
5035 pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
5036 intel_wait_for_vblank(dev_priv, crtc->pipe);
92826fcd 5037
ed4a6a7c
MR
5038 /*
5039 * IVB workaround: must disable low power watermarks for at least
5040 * one frame before enabling scaling. LP watermarks can be re-enabled
5041 * when scaling is disabled.
5042 *
5043 * WaCxSRDisabledForSpriteScaling:ivb
5044 */
ddd2b792 5045 if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev))
0f0f74bc 5046 intel_wait_for_vblank(dev_priv, crtc->pipe);
ed4a6a7c
MR
5047
5048 /*
5049 * If we're doing a modeset, we're done. No need to do any pre-vblank
5050 * watermark programming here.
5051 */
5052 if (needs_modeset(&pipe_config->base))
5053 return;
5054
5055 /*
5056 * For platforms that support atomic watermarks, program the
5057 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
5058 * will be the intermediate values that are safe for both pre- and
5059 * post- vblank; when vblank happens, the 'active' values will be set
5060 * to the final 'target' values and we'll do this again to get the
5061 * optimal watermarks. For gen9+ platforms, the values we program here
5062 * will be the final target values which will get automatically latched
5063 * at vblank time; no further programming will be necessary.
5064 *
5065 * If a platform hasn't been transitioned to atomic watermarks yet,
5066 * we'll continue to update watermarks the old way, if flags tell
5067 * us to.
5068 */
5069 if (dev_priv->display.initial_watermarks != NULL)
ccf010fb
ML
5070 dev_priv->display.initial_watermarks(old_intel_state,
5071 pipe_config);
caed361d 5072 else if (pipe_config->update_wm_pre)
432081bc 5073 intel_update_watermarks(crtc);
ac21b225
ML
5074}
5075
d032ffa0 5076static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
87d4300a
ML
5077{
5078 struct drm_device *dev = crtc->dev;
5079 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d032ffa0 5080 struct drm_plane *p;
87d4300a
ML
5081 int pipe = intel_crtc->pipe;
5082
7cac945f 5083 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8 5084
d032ffa0
ML
5085 drm_for_each_plane_mask(p, dev, plane_mask)
5086 to_intel_plane(p)->disable_plane(p, crtc);
f98551ae 5087
f99d7069
DV
5088 /*
5089 * FIXME: Once we grow proper nuclear flip support out of this we need
5090 * to compute the mask of flip planes precisely. For the time being
5091 * consider this a flip to a NULL plane.
5092 */
5748b6a1 5093 intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS
5094}
5095
fb1c98b1 5096static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc,
fd6bbda9 5097 struct intel_crtc_state *crtc_state,
fb1c98b1
ML
5098 struct drm_atomic_state *old_state)
5099{
aa5e9b47 5100 struct drm_connector_state *conn_state;
fb1c98b1
ML
5101 struct drm_connector *conn;
5102 int i;
5103
aa5e9b47 5104 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
fb1c98b1
ML
5105 struct intel_encoder *encoder =
5106 to_intel_encoder(conn_state->best_encoder);
5107
5108 if (conn_state->crtc != crtc)
5109 continue;
5110
5111 if (encoder->pre_pll_enable)
fd6bbda9 5112 encoder->pre_pll_enable(encoder, crtc_state, conn_state);
fb1c98b1
ML
5113 }
5114}
5115
5116static void intel_encoders_pre_enable(struct drm_crtc *crtc,
fd6bbda9 5117 struct intel_crtc_state *crtc_state,
fb1c98b1
ML
5118 struct drm_atomic_state *old_state)
5119{
aa5e9b47 5120 struct drm_connector_state *conn_state;
fb1c98b1
ML
5121 struct drm_connector *conn;
5122 int i;
5123
aa5e9b47 5124 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
fb1c98b1
ML
5125 struct intel_encoder *encoder =
5126 to_intel_encoder(conn_state->best_encoder);
5127
5128 if (conn_state->crtc != crtc)
5129 continue;
5130
5131 if (encoder->pre_enable)
fd6bbda9 5132 encoder->pre_enable(encoder, crtc_state, conn_state);
fb1c98b1
ML
5133 }
5134}
5135
5136static void intel_encoders_enable(struct drm_crtc *crtc,
fd6bbda9 5137 struct intel_crtc_state *crtc_state,
fb1c98b1
ML
5138 struct drm_atomic_state *old_state)
5139{
aa5e9b47 5140 struct drm_connector_state *conn_state;
fb1c98b1
ML
5141 struct drm_connector *conn;
5142 int i;
5143
aa5e9b47 5144 for_each_new_connector_in_state(old_state, conn, conn_state, i) {
fb1c98b1
ML
5145 struct intel_encoder *encoder =
5146 to_intel_encoder(conn_state->best_encoder);
5147
5148 if (conn_state->crtc != crtc)
5149 continue;
5150
fd6bbda9 5151 encoder->enable(encoder, crtc_state, conn_state);
fb1c98b1
ML
5152 intel_opregion_notify_encoder(encoder, true);
5153 }
5154}
5155
5156static void intel_encoders_disable(struct drm_crtc *crtc,
fd6bbda9 5157 struct intel_crtc_state *old_crtc_state,
fb1c98b1
ML
5158 struct drm_atomic_state *old_state)
5159{
5160 struct drm_connector_state *old_conn_state;
5161 struct drm_connector *conn;
5162 int i;
5163
aa5e9b47 5164 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
fb1c98b1
ML
5165 struct intel_encoder *encoder =
5166 to_intel_encoder(old_conn_state->best_encoder);
5167
5168 if (old_conn_state->crtc != crtc)
5169 continue;
5170
5171 intel_opregion_notify_encoder(encoder, false);
fd6bbda9 5172 encoder->disable(encoder, old_crtc_state, old_conn_state);
fb1c98b1
ML
5173 }
5174}
5175
5176static void intel_encoders_post_disable(struct drm_crtc *crtc,
fd6bbda9 5177 struct intel_crtc_state *old_crtc_state,
fb1c98b1
ML
5178 struct drm_atomic_state *old_state)
5179{
5180 struct drm_connector_state *old_conn_state;
5181 struct drm_connector *conn;
5182 int i;
5183
aa5e9b47 5184 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
fb1c98b1
ML
5185 struct intel_encoder *encoder =
5186 to_intel_encoder(old_conn_state->best_encoder);
5187
5188 if (old_conn_state->crtc != crtc)
5189 continue;
5190
5191 if (encoder->post_disable)
fd6bbda9 5192 encoder->post_disable(encoder, old_crtc_state, old_conn_state);
fb1c98b1
ML
5193 }
5194}
5195
5196static void intel_encoders_post_pll_disable(struct drm_crtc *crtc,
fd6bbda9 5197 struct intel_crtc_state *old_crtc_state,
fb1c98b1
ML
5198 struct drm_atomic_state *old_state)
5199{
5200 struct drm_connector_state *old_conn_state;
5201 struct drm_connector *conn;
5202 int i;
5203
aa5e9b47 5204 for_each_old_connector_in_state(old_state, conn, old_conn_state, i) {
fb1c98b1
ML
5205 struct intel_encoder *encoder =
5206 to_intel_encoder(old_conn_state->best_encoder);
5207
5208 if (old_conn_state->crtc != crtc)
5209 continue;
5210
5211 if (encoder->post_pll_disable)
fd6bbda9 5212 encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state);
fb1c98b1
ML
5213 }
5214}
5215
4a806558
ML
5216static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
5217 struct drm_atomic_state *old_state)
f67a559d 5218{
4a806558 5219 struct drm_crtc *crtc = pipe_config->base.crtc;
f67a559d 5220 struct drm_device *dev = crtc->dev;
fac5e23e 5221 struct drm_i915_private *dev_priv = to_i915(dev);
f67a559d
JB
5222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5223 int pipe = intel_crtc->pipe;
ccf010fb
ML
5224 struct intel_atomic_state *old_intel_state =
5225 to_intel_atomic_state(old_state);
f67a559d 5226
53d9f4e9 5227 if (WARN_ON(intel_crtc->active))
f67a559d
JB
5228 return;
5229
b2c0593a
VS
5230 /*
5231 * Sometimes spurious CPU pipe underruns happen during FDI
5232 * training, at least with VGA+HDMI cloning. Suppress them.
5233 *
5234 * On ILK we get an occasional spurious CPU pipe underruns
5235 * between eDP port A enable and vdd enable. Also PCH port
5236 * enable seems to result in the occasional CPU pipe underrun.
5237 *
5238 * Spurious PCH underruns also occur during PCH enabling.
5239 */
5240 if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv))
5241 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
81b088ca
VS
5242 if (intel_crtc->config->has_pch_encoder)
5243 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5244
6e3c9717 5245 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV
5246 intel_prepare_shared_dpll(intel_crtc);
5247
37a5650b 5248 if (intel_crtc_has_dp_encoder(intel_crtc->config))
fe3cd48d 5249 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV
5250
5251 intel_set_pipe_timings(intel_crtc);
bc58be60 5252 intel_set_pipe_src_size(intel_crtc);
29407aab 5253
6e3c9717 5254 if (intel_crtc->config->has_pch_encoder) {
29407aab 5255 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 5256 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV
5257 }
5258
5259 ironlake_set_pipeconf(crtc);
5260
f67a559d 5261 intel_crtc->active = true;
8664281b 5262
fd6bbda9 5263 intel_encoders_pre_enable(crtc, pipe_config, old_state);
f67a559d 5264
6e3c9717 5265 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV
5266 /* Note: FDI PLL enabling _must_ be done before we enable the
5267 * cpu pipes, hence this is separate from all the other fdi/pch
5268 * enabling. */
88cefb6c 5269 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV
5270 } else {
5271 assert_fdi_tx_disabled(dev_priv, pipe);
5272 assert_fdi_rx_disabled(dev_priv, pipe);
5273 }
f67a559d 5274
b074cec8 5275 ironlake_pfit_enable(intel_crtc);
f67a559d 5276
9c54c0dd
JB
5277 /*
5278 * On ILK+ LUT must be loaded before the pipe is running but with
5279 * clocks enabled
5280 */
b95c5321 5281 intel_color_load_luts(&pipe_config->base);
9c54c0dd 5282
1d5bf5d9 5283 if (dev_priv->display.initial_watermarks != NULL)
ccf010fb 5284 dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config);
e1fdc473 5285 intel_enable_pipe(intel_crtc);
f67a559d 5286
6e3c9717 5287 if (intel_crtc->config->has_pch_encoder)
2ce42273 5288 ironlake_pch_enable(pipe_config);
c98e9dcf 5289
f9b61ff6
DV
5290 assert_vblank_disabled(crtc);
5291 drm_crtc_vblank_on(crtc);
5292
fd6bbda9 5293 intel_encoders_enable(crtc, pipe_config, old_state);
61b77ddd 5294
6e266956 5295 if (HAS_PCH_CPT(dev_priv))
a1520318 5296 cpt_verify_modeset(dev, intel_crtc->pipe);
37ca8d4c
VS
5297
5298 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
5299 if (intel_crtc->config->has_pch_encoder)
0f0f74bc 5300 intel_wait_for_vblank(dev_priv, pipe);
b2c0593a 5301 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
37ca8d4c 5302 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
6be4a607
JB
5303}
5304
42db64ef
PZ
5305/* IPS only exists on ULT machines and is tied to pipe A. */
5306static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5307{
50a0bc90 5308 return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A;
42db64ef
PZ
5309}
5310
4a806558
ML
5311static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
5312 struct drm_atomic_state *old_state)
4f771f10 5313{
4a806558 5314 struct drm_crtc *crtc = pipe_config->base.crtc;
6315b5d3 5315 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
4f771f10 5316 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
99d736a2 5317 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4d1de975 5318 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ccf010fb
ML
5319 struct intel_atomic_state *old_intel_state =
5320 to_intel_atomic_state(old_state);
4f771f10 5321
53d9f4e9 5322 if (WARN_ON(intel_crtc->active))
4f771f10
PZ
5323 return;
5324
81b088ca
VS
5325 if (intel_crtc->config->has_pch_encoder)
5326 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5327 false);
5328
fd6bbda9 5329 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
95a7a2ae 5330
8106ddbd 5331 if (intel_crtc->config->shared_dpll)
df8ad70c
DV
5332 intel_enable_shared_dpll(intel_crtc);
5333
37a5650b 5334 if (intel_crtc_has_dp_encoder(intel_crtc->config))
fe3cd48d 5335 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97 5336
d7edc4e5 5337 if (!transcoder_is_dsi(cpu_transcoder))
4d1de975
JN
5338 intel_set_pipe_timings(intel_crtc);
5339
bc58be60 5340 intel_set_pipe_src_size(intel_crtc);
229fca97 5341
4d1de975
JN
5342 if (cpu_transcoder != TRANSCODER_EDP &&
5343 !transcoder_is_dsi(cpu_transcoder)) {
5344 I915_WRITE(PIPE_MULT(cpu_transcoder),
6e3c9717 5345 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT
5346 }
5347
6e3c9717 5348 if (intel_crtc->config->has_pch_encoder) {
229fca97 5349 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 5350 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV
5351 }
5352
d7edc4e5 5353 if (!transcoder_is_dsi(cpu_transcoder))
4d1de975
JN
5354 haswell_set_pipeconf(crtc);
5355
391bf048 5356 haswell_set_pipemisc(crtc);
229fca97 5357
b95c5321 5358 intel_color_set_csc(&pipe_config->base);
229fca97 5359
4f771f10 5360 intel_crtc->active = true;
8664281b 5361
6b698516
DV
5362 if (intel_crtc->config->has_pch_encoder)
5363 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5364 else
5365 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5366
fd6bbda9 5367 intel_encoders_pre_enable(crtc, pipe_config, old_state);
4f771f10 5368
d2d65408 5369 if (intel_crtc->config->has_pch_encoder)
dc4a1094 5370 dev_priv->display.fdi_link_train(intel_crtc, pipe_config);
4fe9467d 5371
d7edc4e5 5372 if (!transcoder_is_dsi(cpu_transcoder))
3dc38eea 5373 intel_ddi_enable_pipe_clock(pipe_config);
4f771f10 5374
6315b5d3 5375 if (INTEL_GEN(dev_priv) >= 9)
e435d6e5 5376 skylake_pfit_enable(intel_crtc);
ff6d9f55 5377 else
1c132b44 5378 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ
5379
5380 /*
5381 * On ILK+ LUT must be loaded before the pipe is running but with
5382 * clocks enabled
5383 */
b95c5321 5384 intel_color_load_luts(&pipe_config->base);
4f771f10 5385
3dc38eea 5386 intel_ddi_set_pipe_settings(pipe_config);
d7edc4e5 5387 if (!transcoder_is_dsi(cpu_transcoder))
3dc38eea 5388 intel_ddi_enable_transcoder_func(pipe_config);
4f771f10 5389
1d5bf5d9 5390 if (dev_priv->display.initial_watermarks != NULL)
3125d39f 5391 dev_priv->display.initial_watermarks(old_intel_state, pipe_config);
4d1de975
JN
5392
5393 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
d7edc4e5 5394 if (!transcoder_is_dsi(cpu_transcoder))
4d1de975 5395 intel_enable_pipe(intel_crtc);
42db64ef 5396
6e3c9717 5397 if (intel_crtc->config->has_pch_encoder)
2ce42273 5398 lpt_pch_enable(pipe_config);
4f771f10 5399
0037071d 5400 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
3dc38eea 5401 intel_ddi_set_vc_payload_alloc(pipe_config, true);
0e32b39c 5402
f9b61ff6
DV
5403 assert_vblank_disabled(crtc);
5404 drm_crtc_vblank_on(crtc);
5405
fd6bbda9 5406 intel_encoders_enable(crtc, pipe_config, old_state);
4f771f10 5407
6b698516 5408 if (intel_crtc->config->has_pch_encoder) {
0f0f74bc
VS
5409 intel_wait_for_vblank(dev_priv, pipe);
5410 intel_wait_for_vblank(dev_priv, pipe);
6b698516 5411 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
d2d65408
VS
5412 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5413 true);
6b698516 5414 }
d2d65408 5415
e4916946
PZ
5416 /* If we change the relative order between pipe/planes enabling, we need
5417 * to change the workaround. */
99d736a2 5418 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
772c2a51 5419 if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
0f0f74bc
VS
5420 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
5421 intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
99d736a2 5422 }
4f771f10
PZ
5423}
5424
bfd16b2a 5425static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
3f8dce3a
DV
5426{
5427 struct drm_device *dev = crtc->base.dev;
fac5e23e 5428 struct drm_i915_private *dev_priv = to_i915(dev);
3f8dce3a
DV
5429 int pipe = crtc->pipe;
5430
5431 /* To avoid upsetting the power well on haswell only disable the pfit if
5432 * it's in use. The hw state code will make sure we get this right. */
bfd16b2a 5433 if (force || crtc->config->pch_pfit.enabled) {
3f8dce3a
DV
5434 I915_WRITE(PF_CTL(pipe), 0);
5435 I915_WRITE(PF_WIN_POS(pipe), 0);
5436 I915_WRITE(PF_WIN_SZ(pipe), 0);
5437 }
5438}
5439
4a806558
ML
5440static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
5441 struct drm_atomic_state *old_state)
6be4a607 5442{
4a806558 5443 struct drm_crtc *crtc = old_crtc_state->base.crtc;
6be4a607 5444 struct drm_device *dev = crtc->dev;
fac5e23e 5445 struct drm_i915_private *dev_priv = to_i915(dev);
6be4a607
JB
5446 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5447 int pipe = intel_crtc->pipe;
b52eb4dc 5448
b2c0593a
VS
5449 /*
5450 * Sometimes spurious CPU pipe underruns happen when the
5451 * pipe is already disabled, but FDI RX/TX is still enabled.
5452 * Happens at least with VGA+HDMI cloning. Suppress them.
5453 */
5454 if (intel_crtc->config->has_pch_encoder) {
5455 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
37ca8d4c 5456 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
b2c0593a 5457 }
37ca8d4c 5458
fd6bbda9 5459 intel_encoders_disable(crtc, old_crtc_state, old_state);
ea9d758d 5460
f9b61ff6
DV
5461 drm_crtc_vblank_off(crtc);
5462 assert_vblank_disabled(crtc);
5463
575f7ab7 5464 intel_disable_pipe(intel_crtc);
32f9d658 5465
bfd16b2a 5466 ironlake_pfit_disable(intel_crtc, false);
2c07245f 5467
b2c0593a 5468 if (intel_crtc->config->has_pch_encoder)
5a74f70a
VS
5469 ironlake_fdi_disable(crtc);
5470
fd6bbda9 5471 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
2c07245f 5472
6e3c9717 5473 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5474 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5475
6e266956 5476 if (HAS_PCH_CPT(dev_priv)) {
f0f59a00
VS
5477 i915_reg_t reg;
5478 u32 temp;
5479
d925c59a
DV
5480 /* disable TRANS_DP_CTL */
5481 reg = TRANS_DP_CTL(pipe);
5482 temp = I915_READ(reg);
5483 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5484 TRANS_DP_PORT_SEL_MASK);
5485 temp |= TRANS_DP_PORT_SEL_NONE;
5486 I915_WRITE(reg, temp);
5487
5488 /* disable DPLL_SEL */
5489 temp = I915_READ(PCH_DPLL_SEL);
11887397 5490 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5491 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5492 }
e3421a18 5493
d925c59a
DV
5494 ironlake_fdi_pll_disable(intel_crtc);
5495 }
81b088ca 5496
b2c0593a 5497 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
81b088ca 5498 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
6be4a607 5499}
1b3c7a47 5500
4a806558
ML
5501static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
5502 struct drm_atomic_state *old_state)
ee7b9f93 5503{
4a806558 5504 struct drm_crtc *crtc = old_crtc_state->base.crtc;
6315b5d3 5505 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
ee7b9f93 5506 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 5507 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5508
d2d65408
VS
5509 if (intel_crtc->config->has_pch_encoder)
5510 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5511 false);
5512
fd6bbda9 5513 intel_encoders_disable(crtc, old_crtc_state, old_state);
4f771f10 5514
f9b61ff6
DV
5515 drm_crtc_vblank_off(crtc);
5516 assert_vblank_disabled(crtc);
5517
4d1de975 5518 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
d7edc4e5 5519 if (!transcoder_is_dsi(cpu_transcoder))
4d1de975 5520 intel_disable_pipe(intel_crtc);
4f771f10 5521
0037071d 5522 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST))
3dc38eea 5523 intel_ddi_set_vc_payload_alloc(intel_crtc->config, false);
a4bf214f 5524
d7edc4e5 5525 if (!transcoder_is_dsi(cpu_transcoder))
7d4aefd0 5526 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5527
6315b5d3 5528 if (INTEL_GEN(dev_priv) >= 9)
e435d6e5 5529 skylake_scaler_disable(intel_crtc);
ff6d9f55 5530 else
bfd16b2a 5531 ironlake_pfit_disable(intel_crtc, false);
4f771f10 5532
d7edc4e5 5533 if (!transcoder_is_dsi(cpu_transcoder))
3dc38eea 5534 intel_ddi_disable_pipe_clock(intel_crtc->config);
4f771f10 5535
fd6bbda9 5536 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
81b088ca 5537
b7076546 5538 if (old_crtc_state->has_pch_encoder)
81b088ca
VS
5539 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5540 true);
4f771f10
PZ
5541}
5542
2dd24552
JB
5543static void i9xx_pfit_enable(struct intel_crtc *crtc)
5544{
5545 struct drm_device *dev = crtc->base.dev;
fac5e23e 5546 struct drm_i915_private *dev_priv = to_i915(dev);
6e3c9717 5547 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5548
681a8504 5549 if (!pipe_config->gmch_pfit.control)
2dd24552
JB
5550 return;
5551
2dd24552 5552 /*
c0b03411
DV
5553 * The panel fitter should only be adjusted whilst the pipe is disabled,
5554 * according to register description and PRM.
2dd24552 5555 */
c0b03411
DV
5556 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5557 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5558
b074cec8
JB
5559 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5560 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV
5561
5562 /* Border color in case we don't scale up to the full screen. Black by
5563 * default, change to something else for debugging. */
5564 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB
5565}
5566
79f255a0 5567enum intel_display_power_domain intel_port_to_power_domain(enum port port)
d05410f9
DA
5568{
5569 switch (port) {
5570 case PORT_A:
6331a704 5571 return POWER_DOMAIN_PORT_DDI_A_LANES;
d05410f9 5572 case PORT_B:
6331a704 5573 return POWER_DOMAIN_PORT_DDI_B_LANES;
d05410f9 5574 case PORT_C:
6331a704 5575 return POWER_DOMAIN_PORT_DDI_C_LANES;
d05410f9 5576 case PORT_D:
6331a704 5577 return POWER_DOMAIN_PORT_DDI_D_LANES;
d8e19f99 5578 case PORT_E:
6331a704 5579 return POWER_DOMAIN_PORT_DDI_E_LANES;
d05410f9 5580 default:
b9fec167 5581 MISSING_CASE(port);
d05410f9
DA
5582 return POWER_DOMAIN_PORT_OTHER;
5583 }
5584}
5585
d8fc70b7
ACO
5586static u64 get_crtc_power_domains(struct drm_crtc *crtc,
5587 struct intel_crtc_state *crtc_state)
77d22dca 5588{
319be8ae 5589 struct drm_device *dev = crtc->dev;
37255d8d 5590 struct drm_i915_private *dev_priv = to_i915(dev);
74bff5f9 5591 struct drm_encoder *encoder;
319be8ae
ID
5592 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5593 enum pipe pipe = intel_crtc->pipe;
d8fc70b7 5594 u64 mask;
74bff5f9 5595 enum transcoder transcoder = crtc_state->cpu_transcoder;
77d22dca 5596
74bff5f9 5597 if (!crtc_state->base.active)
292b990e
ML
5598 return 0;
5599
77d22dca
ID
5600 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5601 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
74bff5f9
ML
5602 if (crtc_state->pch_pfit.enabled ||
5603 crtc_state->pch_pfit.force_thru)
d8fc70b7 5604 mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
77d22dca 5605
74bff5f9
ML
5606 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5607 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5608
79f255a0 5609 mask |= BIT_ULL(intel_encoder->power_domain);
74bff5f9 5610 }
319be8ae 5611
37255d8d
ML
5612 if (HAS_DDI(dev_priv) && crtc_state->has_audio)
5613 mask |= BIT(POWER_DOMAIN_AUDIO);
5614
15e7ec29 5615 if (crtc_state->shared_dpll)
d8fc70b7 5616 mask |= BIT_ULL(POWER_DOMAIN_PLLS);
15e7ec29 5617
77d22dca
ID
5618 return mask;
5619}
5620
d2d15016 5621static u64
74bff5f9
ML
5622modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5623 struct intel_crtc_state *crtc_state)
77d22dca 5624{
fac5e23e 5625 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
292b990e
ML
5626 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5627 enum intel_display_power_domain domain;
d8fc70b7 5628 u64 domains, new_domains, old_domains;
77d22dca 5629
292b990e 5630 old_domains = intel_crtc->enabled_power_domains;
74bff5f9
ML
5631 intel_crtc->enabled_power_domains = new_domains =
5632 get_crtc_power_domains(crtc, crtc_state);
77d22dca 5633
5a21b665 5634 domains = new_domains & ~old_domains;
292b990e
ML
5635
5636 for_each_power_domain(domain, domains)
5637 intel_display_power_get(dev_priv, domain);
5638
5a21b665 5639 return old_domains & ~new_domains;
292b990e
ML
5640}
5641
5642static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
d8fc70b7 5643 u64 domains)
292b990e
ML
5644{
5645 enum intel_display_power_domain domain;
5646
5647 for_each_power_domain(domain, domains)
5648 intel_display_power_put(dev_priv, domain);
5649}
77d22dca 5650
7ff89ca2
VS
5651static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
5652 struct drm_atomic_state *old_state)
adafdc6f 5653{
ff32c54e
VS
5654 struct intel_atomic_state *old_intel_state =
5655 to_intel_atomic_state(old_state);
7ff89ca2
VS
5656 struct drm_crtc *crtc = pipe_config->base.crtc;
5657 struct drm_device *dev = crtc->dev;
5658 struct drm_i915_private *dev_priv = to_i915(dev);
5659 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5660 int pipe = intel_crtc->pipe;
adafdc6f 5661
7ff89ca2
VS
5662 if (WARN_ON(intel_crtc->active))
5663 return;
adafdc6f 5664
7ff89ca2
VS
5665 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5666 intel_dp_set_m_n(intel_crtc, M1_N1);
b2045352 5667
7ff89ca2
VS
5668 intel_set_pipe_timings(intel_crtc);
5669 intel_set_pipe_src_size(intel_crtc);
b2045352 5670
7ff89ca2
VS
5671 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
5672 struct drm_i915_private *dev_priv = to_i915(dev);
560a7ae4 5673
7ff89ca2
VS
5674 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5675 I915_WRITE(CHV_CANVAS(pipe), 0);
560a7ae4
DL
5676 }
5677
7ff89ca2 5678 i9xx_set_pipeconf(intel_crtc);
560a7ae4 5679
7ff89ca2 5680 intel_crtc->active = true;
92891e45 5681
7ff89ca2 5682 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5f199dfa 5683
7ff89ca2 5684 intel_encoders_pre_pll_enable(crtc, pipe_config, old_state);
5f199dfa 5685
7ff89ca2
VS
5686 if (IS_CHERRYVIEW(dev_priv)) {
5687 chv_prepare_pll(intel_crtc, intel_crtc->config);
5688 chv_enable_pll(intel_crtc, intel_crtc->config);
5689 } else {
5690 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5691 vlv_enable_pll(intel_crtc, intel_crtc->config);
5f199dfa
VS
5692 }
5693
7ff89ca2 5694 intel_encoders_pre_enable(crtc, pipe_config, old_state);
5f199dfa 5695
7ff89ca2 5696 i9xx_pfit_enable(intel_crtc);
89b3c3c7 5697
7ff89ca2 5698 intel_color_load_luts(&pipe_config->base);
89b3c3c7 5699
ff32c54e
VS
5700 dev_priv->display.initial_watermarks(old_intel_state,
5701 pipe_config);
7ff89ca2
VS
5702 intel_enable_pipe(intel_crtc);
5703
5704 assert_vblank_disabled(crtc);
5705 drm_crtc_vblank_on(crtc);
89b3c3c7 5706
7ff89ca2 5707 intel_encoders_enable(crtc, pipe_config, old_state);
89b3c3c7
ACO
5708}
5709
7ff89ca2 5710static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
2b73001e 5711{
7ff89ca2
VS
5712 struct drm_device *dev = crtc->base.dev;
5713 struct drm_i915_private *dev_priv = to_i915(dev);
83d7c81f 5714
7ff89ca2
VS
5715 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5716 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
2b73001e
VS
5717}
5718
7ff89ca2
VS
5719static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
5720 struct drm_atomic_state *old_state)
2b73001e 5721{
7ff89ca2
VS
5722 struct drm_crtc *crtc = pipe_config->base.crtc;
5723 struct drm_device *dev = crtc->dev;
5724 struct drm_i915_private *dev_priv = to_i915(dev);
5725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5726 enum pipe pipe = intel_crtc->pipe;
2b73001e 5727
7ff89ca2
VS
5728 if (WARN_ON(intel_crtc->active))
5729 return;
2b73001e 5730
7ff89ca2 5731 i9xx_set_pll_dividers(intel_crtc);
2b73001e 5732
7ff89ca2
VS
5733 if (intel_crtc_has_dp_encoder(intel_crtc->config))
5734 intel_dp_set_m_n(intel_crtc, M1_N1);
83d7c81f 5735
7ff89ca2
VS
5736 intel_set_pipe_timings(intel_crtc);
5737 intel_set_pipe_src_size(intel_crtc);
2b73001e 5738
7ff89ca2 5739 i9xx_set_pipeconf(intel_crtc);
f8437dd1 5740
7ff89ca2 5741 intel_crtc->active = true;
5f199dfa 5742
7ff89ca2
VS
5743 if (!IS_GEN2(dev_priv))
5744 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5f199dfa 5745
7ff89ca2 5746 intel_encoders_pre_enable(crtc, pipe_config, old_state);
f8437dd1 5747
7ff89ca2 5748 i9xx_enable_pll(intel_crtc);
f8437dd1 5749
7ff89ca2 5750 i9xx_pfit_enable(intel_crtc);
f8437dd1 5751
7ff89ca2 5752 intel_color_load_luts(&pipe_config->base);
f8437dd1 5753
7ff89ca2
VS
5754 intel_update_watermarks(intel_crtc);
5755 intel_enable_pipe(intel_crtc);
f8437dd1 5756
7ff89ca2
VS
5757 assert_vblank_disabled(crtc);
5758 drm_crtc_vblank_on(crtc);
f8437dd1 5759
7ff89ca2
VS
5760 intel_encoders_enable(crtc, pipe_config, old_state);
5761}
f8437dd1 5762
7ff89ca2
VS
5763static void i9xx_pfit_disable(struct intel_crtc *crtc)
5764{
5765 struct drm_device *dev = crtc->base.dev;
5766 struct drm_i915_private *dev_priv = to_i915(dev);
f8437dd1 5767
7ff89ca2 5768 if (!crtc->config->gmch_pfit.control)
f8437dd1 5769 return;
f8437dd1 5770
7ff89ca2
VS
5771 assert_pipe_disabled(dev_priv, crtc->pipe);
5772
5773 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5774 I915_READ(PFIT_CONTROL));
5775 I915_WRITE(PFIT_CONTROL, 0);
f8437dd1
VK
5776}
5777
7ff89ca2
VS
5778static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
5779 struct drm_atomic_state *old_state)
f8437dd1 5780{
7ff89ca2
VS
5781 struct drm_crtc *crtc = old_crtc_state->base.crtc;
5782 struct drm_device *dev = crtc->dev;
5783 struct drm_i915_private *dev_priv = to_i915(dev);
5784 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5785 int pipe = intel_crtc->pipe;
d66a2194 5786
d66a2194 5787 /*
7ff89ca2
VS
5788 * On gen2 planes are double buffered but the pipe isn't, so we must
5789 * wait for planes to fully turn off before disabling the pipe.
d66a2194 5790 */
7ff89ca2
VS
5791 if (IS_GEN2(dev_priv))
5792 intel_wait_for_vblank(dev_priv, pipe);
d66a2194 5793
7ff89ca2 5794 intel_encoders_disable(crtc, old_crtc_state, old_state);
d66a2194 5795
7ff89ca2
VS
5796 drm_crtc_vblank_off(crtc);
5797 assert_vblank_disabled(crtc);
d66a2194 5798
7ff89ca2 5799 intel_disable_pipe(intel_crtc);
d66a2194 5800
7ff89ca2 5801 i9xx_pfit_disable(intel_crtc);
89b3c3c7 5802
7ff89ca2 5803 intel_encoders_post_disable(crtc, old_crtc_state, old_state);
d66a2194 5804
7ff89ca2
VS
5805 if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) {
5806 if (IS_CHERRYVIEW(dev_priv))
5807 chv_disable_pll(dev_priv, pipe);
5808 else if (IS_VALLEYVIEW(dev_priv))
5809 vlv_disable_pll(dev_priv, pipe);
5810 else
5811 i9xx_disable_pll(intel_crtc);
5812 }
c2e001ef 5813
7ff89ca2 5814 intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state);
89b3c3c7 5815
7ff89ca2
VS
5816 if (!IS_GEN2(dev_priv))
5817 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
ff32c54e
VS
5818
5819 if (!dev_priv->display.initial_watermarks)
5820 intel_update_watermarks(intel_crtc);
f8437dd1
VK
5821}
5822
7ff89ca2 5823static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
f8437dd1 5824{
7ff89ca2
VS
5825 struct intel_encoder *encoder;
5826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5827 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
5828 enum intel_display_power_domain domain;
d2d15016 5829 u64 domains;
7ff89ca2
VS
5830 struct drm_atomic_state *state;
5831 struct intel_crtc_state *crtc_state;
5832 int ret;
f8437dd1 5833
7ff89ca2
VS
5834 if (!intel_crtc->active)
5835 return;
a8ca4934 5836
7ff89ca2
VS
5837 if (crtc->primary->state->visible) {
5838 WARN_ON(intel_crtc->flip_work);
5d96d8af 5839
7ff89ca2 5840 intel_pre_disable_primary_noatomic(crtc);
709e05c3 5841
7ff89ca2
VS
5842 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
5843 crtc->primary->state->visible = false;
5844 }
5d96d8af 5845
7ff89ca2
VS
5846 state = drm_atomic_state_alloc(crtc->dev);
5847 if (!state) {
5848 DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory",
5849 crtc->base.id, crtc->name);
1c3f7700 5850 return;
7ff89ca2 5851 }
9f7eb31a 5852
7ff89ca2 5853 state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
ea61791e 5854
7ff89ca2
VS
5855 /* Everything's already locked, -EDEADLK can't happen. */
5856 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5857 ret = drm_atomic_add_affected_connectors(state, crtc);
9f7eb31a 5858
7ff89ca2 5859 WARN_ON(IS_ERR(crtc_state) || ret);
5d96d8af 5860
7ff89ca2 5861 dev_priv->display.crtc_disable(crtc_state, state);
4a806558 5862
0853695c 5863 drm_atomic_state_put(state);
842e0307 5864
78108b7c
VS
5865 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
5866 crtc->base.id, crtc->name);
842e0307
ML
5867
5868 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
5869 crtc->state->active = false;
37d9078b 5870 intel_crtc->active = false;
842e0307
ML
5871 crtc->enabled = false;
5872 crtc->state->connector_mask = 0;
5873 crtc->state->encoder_mask = 0;
5874
5875 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
5876 encoder->base.crtc = NULL;
5877
58f9c0bc 5878 intel_fbc_disable(intel_crtc);
432081bc 5879 intel_update_watermarks(intel_crtc);
1f7457b1 5880 intel_disable_shared_dpll(intel_crtc);
b17d48e2
ML
5881
5882 domains = intel_crtc->enabled_power_domains;
5883 for_each_power_domain(domain, domains)
5884 intel_display_power_put(dev_priv, domain);
5885 intel_crtc->enabled_power_domains = 0;
565602d7
ML
5886
5887 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
5888 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
b17d48e2
ML
5889}
5890
6b72d486
ML
5891/*
5892 * turn all crtc's off, but do not adjust state
5893 * This has to be paired with a call to intel_modeset_setup_hw_state.
5894 */
70e0bd74 5895int intel_display_suspend(struct drm_device *dev)
ee7b9f93 5896{
e2c8b870 5897 struct drm_i915_private *dev_priv = to_i915(dev);
70e0bd74 5898 struct drm_atomic_state *state;
e2c8b870 5899 int ret;
70e0bd74 5900
e2c8b870
ML
5901 state = drm_atomic_helper_suspend(dev);
5902 ret = PTR_ERR_OR_ZERO(state);
70e0bd74
ML
5903 if (ret)
5904 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
e2c8b870
ML
5905 else
5906 dev_priv->modeset_restore_state = state;
70e0bd74 5907 return ret;
ee7b9f93
JB
5908}
5909
ea5b213a 5910void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 5911{
4ef69c7a 5912 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 5913
ea5b213a
CW
5914 drm_encoder_cleanup(encoder);
5915 kfree(intel_encoder);
7e7d76c3
JB
5916}
5917
0a91ca29
DV
5918/* Cross check the actual hw state with our own modeset state tracking (and it's
5919 * internal consistency). */
5a21b665 5920static void intel_connector_verify_state(struct intel_connector *connector)
79e53945 5921{
5a21b665 5922 struct drm_crtc *crtc = connector->base.state->crtc;
35dd3c64
ML
5923
5924 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5925 connector->base.base.id,
5926 connector->base.name);
5927
0a91ca29 5928 if (connector->get_hw_state(connector)) {
e85376cb 5929 struct intel_encoder *encoder = connector->encoder;
5a21b665 5930 struct drm_connector_state *conn_state = connector->base.state;
0a91ca29 5931
35dd3c64
ML
5932 I915_STATE_WARN(!crtc,
5933 "connector enabled without attached crtc\n");
0a91ca29 5934
35dd3c64
ML
5935 if (!crtc)
5936 return;
5937
5938 I915_STATE_WARN(!crtc->state->active,
5939 "connector is active, but attached crtc isn't\n");
5940
e85376cb 5941 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
35dd3c64
ML
5942 return;
5943
e85376cb 5944 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
35dd3c64
ML
5945 "atomic encoder doesn't match attached encoder\n");
5946
e85376cb 5947 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
35dd3c64
ML
5948 "attached encoder crtc differs from connector crtc\n");
5949 } else {
4d688a2a
ML
5950 I915_STATE_WARN(crtc && crtc->state->active,
5951 "attached crtc is active, but connector isn't\n");
5a21b665 5952 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
35dd3c64 5953 "best encoder set without crtc!\n");
0a91ca29 5954 }
79e53945
JB
5955}
5956
08d9bc92
ACO
5957int intel_connector_init(struct intel_connector *connector)
5958{
5350a031 5959 drm_atomic_helper_connector_reset(&connector->base);
08d9bc92 5960
5350a031 5961 if (!connector->base.state)
08d9bc92
ACO
5962 return -ENOMEM;
5963
08d9bc92
ACO
5964 return 0;
5965}
5966
5967struct intel_connector *intel_connector_alloc(void)
5968{
5969 struct intel_connector *connector;
5970
5971 connector = kzalloc(sizeof *connector, GFP_KERNEL);
5972 if (!connector)
5973 return NULL;
5974
5975 if (intel_connector_init(connector) < 0) {
5976 kfree(connector);
5977 return NULL;
5978 }
5979
5980 return connector;
5981}
5982
f0947c37
DV
5983/* Simple connector->get_hw_state implementation for encoders that support only
5984 * one connector and no cloning and hence the encoder state determines the state
5985 * of the connector. */
5986bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 5987{
24929352 5988 enum pipe pipe = 0;
f0947c37 5989 struct intel_encoder *encoder = connector->encoder;
ea5b213a 5990
f0947c37 5991 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW
5992}
5993
6d293983 5994static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 5995{
6d293983
ACO
5996 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
5997 return crtc_state->fdi_lanes;
d272ddfa
VS
5998
5999 return 0;
6000}
6001
6d293983 6002static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6003 struct intel_crtc_state *pipe_config)
1857e1da 6004{
8652744b 6005 struct drm_i915_private *dev_priv = to_i915(dev);
6d293983
ACO
6006 struct drm_atomic_state *state = pipe_config->base.state;
6007 struct intel_crtc *other_crtc;
6008 struct intel_crtc_state *other_crtc_state;
6009
1857e1da
DV
6010 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6011 pipe_name(pipe), pipe_config->fdi_lanes);
6012 if (pipe_config->fdi_lanes > 4) {
6013 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6014 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6015 return -EINVAL;
1857e1da
DV
6016 }
6017
8652744b 6018 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
1857e1da
DV
6019 if (pipe_config->fdi_lanes > 2) {
6020 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6021 pipe_config->fdi_lanes);
6d293983 6022 return -EINVAL;
1857e1da 6023 } else {
6d293983 6024 return 0;
1857e1da
DV
6025 }
6026 }
6027
b7f05d4a 6028 if (INTEL_INFO(dev_priv)->num_pipes == 2)
6d293983 6029 return 0;
1857e1da
DV
6030
6031 /* Ivybridge 3 pipe is really complicated */
6032 switch (pipe) {
6033 case PIPE_A:
6d293983 6034 return 0;
1857e1da 6035 case PIPE_B:
6d293983
ACO
6036 if (pipe_config->fdi_lanes <= 2)
6037 return 0;
6038
b91eb5cc 6039 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C);
6d293983
ACO
6040 other_crtc_state =
6041 intel_atomic_get_crtc_state(state, other_crtc);
6042 if (IS_ERR(other_crtc_state))
6043 return PTR_ERR(other_crtc_state);
6044
6045 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV
6046 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6047 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6048 return -EINVAL;
1857e1da 6049 }
6d293983 6050 return 0;
1857e1da 6051 case PIPE_C:
251cc67c
VS
6052 if (pipe_config->fdi_lanes > 2) {
6053 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6054 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6055 return -EINVAL;
251cc67c 6056 }
6d293983 6057
b91eb5cc 6058 other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B);
6d293983
ACO
6059 other_crtc_state =
6060 intel_atomic_get_crtc_state(state, other_crtc);
6061 if (IS_ERR(other_crtc_state))
6062 return PTR_ERR(other_crtc_state);
6063
6064 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6065 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6066 return -EINVAL;
1857e1da 6067 }
6d293983 6068 return 0;
1857e1da
DV
6069 default:
6070 BUG();
6071 }
6072}
6073
e29c22c0
DV
6074#define RETRY 1
6075static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6076 struct intel_crtc_state *pipe_config)
877d48d5 6077{
1857e1da 6078 struct drm_device *dev = intel_crtc->base.dev;
7c5f93b0 6079 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO
6080 int lane, link_bw, fdi_dotclock, ret;
6081 bool needs_recompute = false;
877d48d5 6082
e29c22c0 6083retry:
877d48d5
DV
6084 /* FDI is a binary signal running at ~2.7GHz, encoding
6085 * each output octet as 10 bits. The actual frequency
6086 * is stored as a divider into a 100MHz clock, and the
6087 * mode pixel clock is stored in units of 1KHz.
6088 * Hence the bw of each lane in terms of the mode signal
6089 * is:
6090 */
21a727b3 6091 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
877d48d5 6092
241bfc38 6093 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6094
2bd89a07 6095 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV
6096 pipe_config->pipe_bpp);
6097
6098 pipe_config->fdi_lanes = lane;
6099
2bd89a07 6100 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6101 link_bw, &pipe_config->fdi_m_n);
1857e1da 6102
e3b247da 6103 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6d293983 6104 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0 6105 pipe_config->pipe_bpp -= 2*3;
7ff89ca2
VS
6106 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6107 pipe_config->pipe_bpp);
6108 needs_recompute = true;
6109 pipe_config->bw_constrained = true;
257a7ffc 6110
7ff89ca2 6111 goto retry;
257a7ffc 6112 }
79e53945 6113
7ff89ca2
VS
6114 if (needs_recompute)
6115 return RETRY;
e70236a8 6116
7ff89ca2 6117 return ret;
e70236a8
JB
6118}
6119
7ff89ca2
VS
6120static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6121 struct intel_crtc_state *pipe_config)
e70236a8 6122{
7ff89ca2
VS
6123 if (pipe_config->pipe_bpp > 24)
6124 return false;
e70236a8 6125
7ff89ca2
VS
6126 /* HSW can handle pixel rate up to cdclk? */
6127 if (IS_HASWELL(dev_priv))
6128 return true;
1b1d2716 6129
65cd2b3f 6130 /*
7ff89ca2
VS
6131 * We compare against max which means we must take
6132 * the increased cdclk requirement into account when
6133 * calculating the new cdclk.
6134 *
6135 * Should measure whether using a lower cdclk w/o IPS
e70236a8 6136 */
7ff89ca2
VS
6137 return pipe_config->pixel_rate <=
6138 dev_priv->max_cdclk_freq * 95 / 100;
e70236a8 6139}
79e53945 6140
7ff89ca2
VS
6141static void hsw_compute_ips_config(struct intel_crtc *crtc,
6142 struct intel_crtc_state *pipe_config)
6143{
6144 struct drm_device *dev = crtc->base.dev;
6145 struct drm_i915_private *dev_priv = to_i915(dev);
34edce2f 6146
7ff89ca2
VS
6147 pipe_config->ips_enabled = i915.enable_ips &&
6148 hsw_crtc_supports_ips(crtc) &&
6149 pipe_config_supports_ips(dev_priv, pipe_config);
34edce2f
VS
6150}
6151
7ff89ca2 6152static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
34edce2f 6153{
7ff89ca2 6154 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
34edce2f 6155
7ff89ca2
VS
6156 /* GDG double wide on either pipe, otherwise pipe A only */
6157 return INTEL_INFO(dev_priv)->gen < 4 &&
6158 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
34edce2f
VS
6159}
6160
ceb99320
VS
6161static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
6162{
6163 uint32_t pixel_rate;
6164
6165 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
6166
6167 /*
6168 * We only use IF-ID interlacing. If we ever use
6169 * PF-ID we'll need to adjust the pixel_rate here.
6170 */
6171
6172 if (pipe_config->pch_pfit.enabled) {
6173 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
6174 uint32_t pfit_size = pipe_config->pch_pfit.size;
6175
6176 pipe_w = pipe_config->pipe_src_w;
6177 pipe_h = pipe_config->pipe_src_h;
6178
6179 pfit_w = (pfit_size >> 16) & 0xFFFF;
6180 pfit_h = pfit_size & 0xFFFF;
6181 if (pipe_w < pfit_w)
6182 pipe_w = pfit_w;
6183 if (pipe_h < pfit_h)
6184 pipe_h = pfit_h;
6185
6186 if (WARN_ON(!pfit_w || !pfit_h))
6187 return pixel_rate;
6188
6189 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
6190 pfit_w * pfit_h);
6191 }
6192
6193 return pixel_rate;
6194}
6195
7ff89ca2 6196static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
34edce2f 6197{
7ff89ca2 6198 struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
34edce2f 6199
7ff89ca2
VS
6200 if (HAS_GMCH_DISPLAY(dev_priv))
6201 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
6202 crtc_state->pixel_rate =
6203 crtc_state->base.adjusted_mode.crtc_clock;
6204 else
6205 crtc_state->pixel_rate =
6206 ilk_pipe_pixel_rate(crtc_state);
6207}
34edce2f 6208
7ff89ca2
VS
6209static int intel_crtc_compute_config(struct intel_crtc *crtc,
6210 struct intel_crtc_state *pipe_config)
6211{
6212 struct drm_device *dev = crtc->base.dev;
6213 struct drm_i915_private *dev_priv = to_i915(dev);
6214 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6215 int clock_limit = dev_priv->max_dotclk_freq;
34edce2f 6216
7ff89ca2
VS
6217 if (INTEL_GEN(dev_priv) < 4) {
6218 clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
34edce2f 6219
7ff89ca2
VS
6220 /*
6221 * Enable double wide mode when the dot clock
6222 * is > 90% of the (display) core speed.
6223 */
6224 if (intel_crtc_supports_double_wide(crtc) &&
6225 adjusted_mode->crtc_clock > clock_limit) {
6226 clock_limit = dev_priv->max_dotclk_freq;
6227 pipe_config->double_wide = true;
6228 }
34edce2f
VS
6229 }
6230
7ff89ca2
VS
6231 if (adjusted_mode->crtc_clock > clock_limit) {
6232 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6233 adjusted_mode->crtc_clock, clock_limit,
6234 yesno(pipe_config->double_wide));
6235 return -EINVAL;
6236 }
34edce2f 6237
7ff89ca2
VS
6238 /*
6239 * Pipe horizontal size must be even in:
6240 * - DVO ganged mode
6241 * - LVDS dual channel mode
6242 * - Double wide pipe
6243 */
6244 if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6245 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6246 pipe_config->pipe_src_w &= ~1;
34edce2f 6247
7ff89ca2
VS
6248 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6249 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6250 */
6251 if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) &&
6252 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6253 return -EINVAL;
34edce2f 6254
7ff89ca2 6255 intel_crtc_compute_pixel_rate(pipe_config);
34edce2f 6256
7ff89ca2
VS
6257 if (HAS_IPS(dev_priv))
6258 hsw_compute_ips_config(crtc, pipe_config);
34edce2f 6259
7ff89ca2
VS
6260 if (pipe_config->has_pch_encoder)
6261 return ironlake_fdi_compute_config(crtc, pipe_config);
34edce2f 6262
7ff89ca2 6263 return 0;
34edce2f
VS
6264}
6265
2c07245f 6266static void
a65851af 6267intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 6268{
a65851af
VS
6269 while (*num > DATA_LINK_M_N_MASK ||
6270 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW
6271 *num >>= 1;
6272 *den >>= 1;
6273 }
6274}
6275
a65851af
VS
6276static void compute_m_n(unsigned int m, unsigned int n,
6277 uint32_t *ret_m, uint32_t *ret_n)
6278{
9a86cda0
JN
6279 /*
6280 * Reduce M/N as much as possible without loss in precision. Several DP
6281 * dongles in particular seem to be fussy about too large *link* M/N
6282 * values. The passed in values are more likely to have the least
6283 * significant bits zero than M after rounding below, so do this first.
6284 */
6285 while ((m & 1) == 0 && (n & 1) == 0) {
6286 m >>= 1;
6287 n >>= 1;
6288 }
6289
a65851af
VS
6290 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6291 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6292 intel_reduce_m_n_ratio(ret_m, ret_n);
6293}
6294
e69d0bc1
DV
6295void
6296intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6297 int pixel_clock, int link_clock,
6298 struct intel_link_m_n *m_n)
2c07245f 6299{
e69d0bc1 6300 m_n->tu = 64;
a65851af
VS
6301
6302 compute_m_n(bits_per_pixel * pixel_clock,
6303 link_clock * nlanes * 8,
6304 &m_n->gmch_m, &m_n->gmch_n);
6305
6306 compute_m_n(pixel_clock, link_clock,
6307 &m_n->link_m, &m_n->link_n);
2c07245f
ZW
6308}
6309
a7615030
CW
6310static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6311{
d330a953
JN
6312 if (i915.panel_use_ssc >= 0)
6313 return i915.panel_use_ssc != 0;
41aa3448 6314 return dev_priv->vbt.lvds_use_ssc
435793df 6315 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW
6316}
6317
7429e9d4 6318static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 6319{
7df00d7a 6320 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 6321}
f47709a9 6322
7429e9d4
DV
6323static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6324{
6325 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB
6326}
6327
f47709a9 6328static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 6329 struct intel_crtc_state *crtc_state,
9e2c8475 6330 struct dpll *reduced_clock)
a7516a05 6331{
9b1e14f4 6332 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
a7516a05
JB
6333 u32 fp, fp2 = 0;
6334
9b1e14f4 6335 if (IS_PINEVIEW(dev_priv)) {
190f68c5 6336 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6337 if (reduced_clock)
7429e9d4 6338 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 6339 } else {
190f68c5 6340 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6341 if (reduced_clock)
7429e9d4 6342 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB
6343 }
6344
190f68c5 6345 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 6346
f47709a9 6347 crtc->lowfreq_avail = false;
2d84d2b3 6348 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 6349 reduced_clock) {
190f68c5 6350 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 6351 crtc->lowfreq_avail = true;
a7516a05 6352 } else {
190f68c5 6353 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB
6354 }
6355}
6356
5e69f97f
CML
6357static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6358 pipe)
89b667f8
JB
6359{
6360 u32 reg_val;
6361
6362 /*
6363 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6364 * and set it to a reasonable value instead.
6365 */
ab3c759a 6366 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB
6367 reg_val &= 0xffffff00;
6368 reg_val |= 0x00000030;
ab3c759a 6369 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6370
ab3c759a 6371 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
ed58570f
ID
6372 reg_val &= 0x00ffffff;
6373 reg_val |= 0x8c000000;
ab3c759a 6374 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 6375
ab3c759a 6376 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 6377 reg_val &= 0xffffff00;
ab3c759a 6378 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6379
ab3c759a 6380 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB
6381 reg_val &= 0x00ffffff;
6382 reg_val |= 0xb0000000;
ab3c759a 6383 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB
6384}
6385
b551842d
DV
6386static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6387 struct intel_link_m_n *m_n)
6388{
6389 struct drm_device *dev = crtc->base.dev;
fac5e23e 6390 struct drm_i915_private *dev_priv = to_i915(dev);
b551842d
DV
6391 int pipe = crtc->pipe;
6392
e3b95f1e
DV
6393 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6394 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6395 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6396 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV
6397}
6398
6399static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK
6400 struct intel_link_m_n *m_n,
6401 struct intel_link_m_n *m2_n2)
b551842d 6402{
6315b5d3 6403 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
b551842d 6404 int pipe = crtc->pipe;
6e3c9717 6405 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d 6406
6315b5d3 6407 if (INTEL_GEN(dev_priv) >= 5) {
b551842d
DV
6408 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6409 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6410 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6411 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK
6412 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6413 * for gen < 8) and if DRRS is supported (to make sure the
6414 * registers are not unnecessarily accessed).
6415 */
920a14b2
TU
6416 if (m2_n2 && (IS_CHERRYVIEW(dev_priv) ||
6417 INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) {
f769cd24
VK
6418 I915_WRITE(PIPE_DATA_M2(transcoder),
6419 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6420 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6421 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6422 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6423 }
b551842d 6424 } else {
e3b95f1e
DV
6425 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6426 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6427 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6428 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV
6429 }
6430}
6431
fe3cd48d 6432void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 6433{
fe3cd48d
R
6434 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6435
6436 if (m_n == M1_N1) {
6437 dp_m_n = &crtc->config->dp_m_n;
6438 dp_m2_n2 = &crtc->config->dp_m2_n2;
6439 } else if (m_n == M2_N2) {
6440
6441 /*
6442 * M2_N2 registers are not supported. Hence m2_n2 divider value
6443 * needs to be programmed into M1_N1.
6444 */
6445 dp_m_n = &crtc->config->dp_m2_n2;
6446 } else {
6447 DRM_ERROR("Unsupported divider value\n");
6448 return;
6449 }
6450
6e3c9717
ACO
6451 if (crtc->config->has_pch_encoder)
6452 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 6453 else
fe3cd48d 6454 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV
6455}
6456
251ac862
DV
6457static void vlv_compute_dpll(struct intel_crtc *crtc,
6458 struct intel_crtc_state *pipe_config)
bdd4b6a6 6459{
03ed5cbf 6460 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
cd2d34d9 6461 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
03ed5cbf
VS
6462 if (crtc->pipe != PIPE_A)
6463 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
bdd4b6a6 6464
cd2d34d9 6465 /* DPLL not used with DSI, but still need the rest set up */
d7edc4e5 6466 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
cd2d34d9
VS
6467 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE |
6468 DPLL_EXT_BUFFER_ENABLE_VLV;
6469
03ed5cbf
VS
6470 pipe_config->dpll_hw_state.dpll_md =
6471 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6472}
bdd4b6a6 6473
03ed5cbf
VS
6474static void chv_compute_dpll(struct intel_crtc *crtc,
6475 struct intel_crtc_state *pipe_config)
6476{
6477 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
cd2d34d9 6478 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
03ed5cbf
VS
6479 if (crtc->pipe != PIPE_A)
6480 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6481
cd2d34d9 6482 /* DPLL not used with DSI, but still need the rest set up */
d7edc4e5 6483 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI))
cd2d34d9
VS
6484 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE;
6485
03ed5cbf
VS
6486 pipe_config->dpll_hw_state.dpll_md =
6487 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
bdd4b6a6
DV
6488}
6489
d288f65f 6490static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6491 const struct intel_crtc_state *pipe_config)
a0c4da24 6492{
f47709a9 6493 struct drm_device *dev = crtc->base.dev;
fac5e23e 6494 struct drm_i915_private *dev_priv = to_i915(dev);
cd2d34d9 6495 enum pipe pipe = crtc->pipe;
bdd4b6a6 6496 u32 mdiv;
a0c4da24 6497 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 6498 u32 coreclk, reg_val;
a0c4da24 6499
cd2d34d9
VS
6500 /* Enable Refclk */
6501 I915_WRITE(DPLL(pipe),
6502 pipe_config->dpll_hw_state.dpll &
6503 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV));
6504
6505 /* No need to actually set up the DPLL with DSI */
6506 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6507 return;
6508
a580516d 6509 mutex_lock(&dev_priv->sb_lock);
09153000 6510
d288f65f
VS
6511 bestn = pipe_config->dpll.n;
6512 bestm1 = pipe_config->dpll.m1;
6513 bestm2 = pipe_config->dpll.m2;
6514 bestp1 = pipe_config->dpll.p1;
6515 bestp2 = pipe_config->dpll.p2;
a0c4da24 6516
89b667f8
JB
6517 /* See eDP HDMI DPIO driver vbios notes doc */
6518
6519 /* PLL B needs special handling */
bdd4b6a6 6520 if (pipe == PIPE_B)
5e69f97f 6521 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB
6522
6523 /* Set up Tx target for periodic Rcomp update */
ab3c759a 6524 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB
6525
6526 /* Disable target IRef on PLL */
ab3c759a 6527 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 6528 reg_val &= 0x00ffffff;
ab3c759a 6529 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB
6530
6531 /* Disable fast lock */
ab3c759a 6532 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB
6533
6534 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB
6535 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6536 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6537 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 6538 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB
6539
6540 /*
6541 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6542 * but we don't support that).
6543 * Note: don't use the DAC post divider as it seems unstable.
6544 */
6545 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 6546 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6547
a0c4da24 6548 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 6549 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6550
89b667f8 6551 /* Set HBR and RBR LPF coefficients */
d288f65f 6552 if (pipe_config->port_clock == 162000 ||
2d84d2b3
VS
6553 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) ||
6554 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI))
ab3c759a 6555 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 6556 0x009f0003);
89b667f8 6557 else
ab3c759a 6558 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB
6559 0x00d0000f);
6560
37a5650b 6561 if (intel_crtc_has_dp_encoder(pipe_config)) {
89b667f8 6562 /* Use SSC source */
bdd4b6a6 6563 if (pipe == PIPE_A)
ab3c759a 6564 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB
6565 0x0df40000);
6566 else
ab3c759a 6567 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB
6568 0x0df70000);
6569 } else { /* HDMI or VGA */
6570 /* Use bend source */
bdd4b6a6 6571 if (pipe == PIPE_A)
ab3c759a 6572 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB
6573 0x0df70000);
6574 else
ab3c759a 6575 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB
6576 0x0df40000);
6577 }
a0c4da24 6578
ab3c759a 6579 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 6580 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
2210ce7f 6581 if (intel_crtc_has_dp_encoder(crtc->config))
89b667f8 6582 coreclk |= 0x01000000;
ab3c759a 6583 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 6584
ab3c759a 6585 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 6586 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB
6587}
6588
d288f65f 6589static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6590 const struct intel_crtc_state *pipe_config)
9d556c99
CML
6591{
6592 struct drm_device *dev = crtc->base.dev;
fac5e23e 6593 struct drm_i915_private *dev_priv = to_i915(dev);
cd2d34d9 6594 enum pipe pipe = crtc->pipe;
9d556c99 6595 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 6596 u32 loopfilter, tribuf_calcntr;
9d556c99 6597 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 6598 u32 dpio_val;
9cbe40c1 6599 int vco;
9d556c99 6600
cd2d34d9
VS
6601 /* Enable Refclk and SSC */
6602 I915_WRITE(DPLL(pipe),
6603 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6604
6605 /* No need to actually set up the DPLL with DSI */
6606 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
6607 return;
6608
d288f65f
VS
6609 bestn = pipe_config->dpll.n;
6610 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6611 bestm1 = pipe_config->dpll.m1;
6612 bestm2 = pipe_config->dpll.m2 >> 22;
6613 bestp1 = pipe_config->dpll.p1;
6614 bestp2 = pipe_config->dpll.p2;
9cbe40c1 6615 vco = pipe_config->dpll.vco;
a945ce7e 6616 dpio_val = 0;
9cbe40c1 6617 loopfilter = 0;
9d556c99 6618
a580516d 6619 mutex_lock(&dev_priv->sb_lock);
9d556c99 6620
9d556c99
CML
6621 /* p1 and p2 divider */
6622 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6623 5 << DPIO_CHV_S1_DIV_SHIFT |
6624 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6625 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6626 1 << DPIO_CHV_K_DIV_SHIFT);
6627
6628 /* Feedback post-divider - m2 */
6629 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6630
6631 /* Feedback refclk divider - n and m1 */
6632 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6633 DPIO_CHV_M1_DIV_BY_2 |
6634 1 << DPIO_CHV_N_DIV_SHIFT);
6635
6636 /* M2 fraction division */
25a25dfc 6637 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML
6638
6639 /* M2 fraction division enable */
a945ce7e
VP
6640 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6641 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6642 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6643 if (bestm2_frac)
6644 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6645 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 6646
de3a0fde
VP
6647 /* Program digital lock detect threshold */
6648 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6649 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6650 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6651 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6652 if (!bestm2_frac)
6653 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6654 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6655
9d556c99 6656 /* Loop filter */
9cbe40c1
VP
6657 if (vco == 5400000) {
6658 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6659 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6660 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6661 tribuf_calcntr = 0x9;
6662 } else if (vco <= 6200000) {
6663 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6664 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6665 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6666 tribuf_calcntr = 0x9;
6667 } else if (vco <= 6480000) {
6668 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6669 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6670 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6671 tribuf_calcntr = 0x8;
6672 } else {
6673 /* Not supported. Apply the same limits as in the max case */
6674 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6675 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6676 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6677 tribuf_calcntr = 0;
6678 }
9d556c99
CML
6679 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6680
968040b2 6681 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP
6682 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6683 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6684 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6685
9d556c99
CML
6686 /* AFC Recal */
6687 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6688 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6689 DPIO_AFC_RECAL);
6690
a580516d 6691 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML
6692}
6693
d288f65f
VS
6694/**
6695 * vlv_force_pll_on - forcibly enable just the PLL
6696 * @dev_priv: i915 private structure
6697 * @pipe: pipe PLL to enable
6698 * @dpll: PLL configuration
6699 *
6700 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6701 * in cases where we need the PLL enabled even when @pipe is not going to
6702 * be enabled.
6703 */
30ad9814 6704int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe,
3f36b937 6705 const struct dpll *dpll)
d288f65f 6706{
b91eb5cc 6707 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
3f36b937
TU
6708 struct intel_crtc_state *pipe_config;
6709
6710 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
6711 if (!pipe_config)
6712 return -ENOMEM;
6713
6714 pipe_config->base.crtc = &crtc->base;
6715 pipe_config->pixel_multiplier = 1;
6716 pipe_config->dpll = *dpll;
d288f65f 6717
30ad9814 6718 if (IS_CHERRYVIEW(dev_priv)) {
3f36b937
TU
6719 chv_compute_dpll(crtc, pipe_config);
6720 chv_prepare_pll(crtc, pipe_config);
6721 chv_enable_pll(crtc, pipe_config);
d288f65f 6722 } else {
3f36b937
TU
6723 vlv_compute_dpll(crtc, pipe_config);
6724 vlv_prepare_pll(crtc, pipe_config);
6725 vlv_enable_pll(crtc, pipe_config);
d288f65f 6726 }
3f36b937
TU
6727
6728 kfree(pipe_config);
6729
6730 return 0;
d288f65f
VS
6731}
6732
6733/**
6734 * vlv_force_pll_off - forcibly disable just the PLL
6735 * @dev_priv: i915 private structure
6736 * @pipe: pipe PLL to disable
6737 *
6738 * Disable the PLL for @pipe. To be used in cases where we need
6739 * the PLL enabled even when @pipe is not going to be enabled.
6740 */
30ad9814 6741void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe)
d288f65f 6742{
30ad9814
VS
6743 if (IS_CHERRYVIEW(dev_priv))
6744 chv_disable_pll(dev_priv, pipe);
d288f65f 6745 else
30ad9814 6746 vlv_disable_pll(dev_priv, pipe);
d288f65f
VS
6747}
6748
251ac862
DV
6749static void i9xx_compute_dpll(struct intel_crtc *crtc,
6750 struct intel_crtc_state *crtc_state,
9e2c8475 6751 struct dpll *reduced_clock)
eb1cbe48 6752{
9b1e14f4 6753 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
eb1cbe48 6754 u32 dpll;
190f68c5 6755 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 6756
190f68c5 6757 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 6758
eb1cbe48
DV
6759 dpll = DPLL_VGA_MODE_DIS;
6760
2d84d2b3 6761 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV
6762 dpll |= DPLLB_MODE_LVDS;
6763 else
6764 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 6765
73f67aa8
JN
6766 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
6767 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
190f68c5 6768 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 6769 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 6770 }
198a037f 6771
3d6e9ee0
VS
6772 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
6773 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
4a33e48d 6774 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 6775
37a5650b 6776 if (intel_crtc_has_dp_encoder(crtc_state))
4a33e48d 6777 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV
6778
6779 /* compute bitmask from p1 value */
9b1e14f4 6780 if (IS_PINEVIEW(dev_priv))
eb1cbe48
DV
6781 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6782 else {
6783 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9beb5fea 6784 if (IS_G4X(dev_priv) && reduced_clock)
eb1cbe48
DV
6785 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6786 }
6787 switch (clock->p2) {
6788 case 5:
6789 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6790 break;
6791 case 7:
6792 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6793 break;
6794 case 10:
6795 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6796 break;
6797 case 14:
6798 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6799 break;
6800 }
9b1e14f4 6801 if (INTEL_GEN(dev_priv) >= 4)
eb1cbe48
DV
6802 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6803
190f68c5 6804 if (crtc_state->sdvo_tv_clock)
eb1cbe48 6805 dpll |= PLL_REF_INPUT_TVCLKINBC;
2d84d2b3 6806 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ceb41007 6807 intel_panel_use_ssc(dev_priv))
eb1cbe48
DV
6808 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6809 else
6810 dpll |= PLL_REF_INPUT_DREFCLK;
6811
6812 dpll |= DPLL_VCO_ENABLE;
190f68c5 6813 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 6814
9b1e14f4 6815 if (INTEL_GEN(dev_priv) >= 4) {
190f68c5 6816 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 6817 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 6818 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV
6819 }
6820}
6821
251ac862
DV
6822static void i8xx_compute_dpll(struct intel_crtc *crtc,
6823 struct intel_crtc_state *crtc_state,
9e2c8475 6824 struct dpll *reduced_clock)
eb1cbe48 6825{
f47709a9 6826 struct drm_device *dev = crtc->base.dev;
fac5e23e 6827 struct drm_i915_private *dev_priv = to_i915(dev);
eb1cbe48 6828 u32 dpll;
190f68c5 6829 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 6830
190f68c5 6831 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 6832
eb1cbe48
DV
6833 dpll = DPLL_VGA_MODE_DIS;
6834
2d84d2b3 6835 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV
6836 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6837 } else {
6838 if (clock->p1 == 2)
6839 dpll |= PLL_P1_DIVIDE_BY_TWO;
6840 else
6841 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6842 if (clock->p2 == 4)
6843 dpll |= PLL_P2_DIVIDE_BY_4;
6844 }
6845
50a0bc90
TU
6846 if (!IS_I830(dev_priv) &&
6847 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV
6848 dpll |= DPLL_DVO_2X_MODE;
6849
2d84d2b3 6850 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ceb41007 6851 intel_panel_use_ssc(dev_priv))
eb1cbe48
DV
6852 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6853 else
6854 dpll |= PLL_REF_INPUT_DREFCLK;
6855
6856 dpll |= DPLL_VCO_ENABLE;
190f68c5 6857 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV
6858}
6859
8a654f3b 6860static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c 6861{
6315b5d3 6862 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
b0e77b9c 6863 enum pipe pipe = intel_crtc->pipe;
6e3c9717 6864 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7c5f93b0 6865 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS
6866 uint32_t crtc_vtotal, crtc_vblank_end;
6867 int vsyncshift = 0;
4d8a62ea
DV
6868
6869 /* We need to be careful not to changed the adjusted mode, for otherwise
6870 * the hw state checker will get angry at the mismatch. */
6871 crtc_vtotal = adjusted_mode->crtc_vtotal;
6872 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 6873
609aeaca 6874 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 6875 /* the chip adds 2 halflines automatically */
4d8a62ea
DV
6876 crtc_vtotal -= 1;
6877 crtc_vblank_end -= 1;
609aeaca 6878
2d84d2b3 6879 if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
609aeaca
VS
6880 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6881 else
6882 vsyncshift = adjusted_mode->crtc_hsync_start -
6883 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS
6884 if (vsyncshift < 0)
6885 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ
6886 }
6887
6315b5d3 6888 if (INTEL_GEN(dev_priv) > 3)
fe2b8f9d 6889 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 6890
fe2b8f9d 6891 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ
6892 (adjusted_mode->crtc_hdisplay - 1) |
6893 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 6894 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ
6895 (adjusted_mode->crtc_hblank_start - 1) |
6896 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 6897 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ
6898 (adjusted_mode->crtc_hsync_start - 1) |
6899 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6900
fe2b8f9d 6901 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 6902 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 6903 ((crtc_vtotal - 1) << 16));
fe2b8f9d 6904 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 6905 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 6906 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 6907 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ
6908 (adjusted_mode->crtc_vsync_start - 1) |
6909 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6910
b5e508d4
PZ
6911 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6912 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6913 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6914 * bits. */
772c2a51 6915 if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
b5e508d4
PZ
6916 (pipe == PIPE_B || pipe == PIPE_C))
6917 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6918
bc58be60
JN
6919}
6920
6921static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
6922{
6923 struct drm_device *dev = intel_crtc->base.dev;
fac5e23e 6924 struct drm_i915_private *dev_priv = to_i915(dev);
bc58be60
JN
6925 enum pipe pipe = intel_crtc->pipe;
6926
b0e77b9c
PZ
6927 /* pipesrc controls the size that is scaled from, which should
6928 * always be the user's requested size.
6929 */
6930 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO
6931 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6932 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ
6933}
6934
1bd1bd80 6935static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 6936 struct intel_crtc_state *pipe_config)
1bd1bd80
DV
6937{
6938 struct drm_device *dev = crtc->base.dev;
fac5e23e 6939 struct drm_i915_private *dev_priv = to_i915(dev);
1bd1bd80
DV
6940 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6941 uint32_t tmp;
6942
6943 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO
6944 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6945 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 6946 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO
6947 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6948 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 6949 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO
6950 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6951 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV
6952
6953 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO
6954 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6955 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 6956 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO
6957 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6958 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 6959 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO
6960 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6961 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV
6962
6963 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO
6964 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6965 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6966 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80 6967 }
bc58be60
JN
6968}
6969
6970static void intel_get_pipe_src_size(struct intel_crtc *crtc,
6971 struct intel_crtc_state *pipe_config)
6972{
6973 struct drm_device *dev = crtc->base.dev;
fac5e23e 6974 struct drm_i915_private *dev_priv = to_i915(dev);
bc58be60 6975 u32 tmp;
1bd1bd80
DV
6976
6977 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS
6978 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6979 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6980
2d112de7
ACO
6981 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6982 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV
6983}
6984
f6a83288 6985void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 6986 struct intel_crtc_state *pipe_config)
babea61d 6987{
2d112de7
ACO
6988 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6989 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6990 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6991 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 6992
2d112de7
ACO
6993 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6994 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6995 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6996 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 6997
2d112de7 6998 mode->flags = pipe_config->base.adjusted_mode.flags;
cd13f5ab 6999 mode->type = DRM_MODE_TYPE_DRIVER;
babea61d 7000
2d112de7 7001 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
cd13f5ab
ML
7002
7003 mode->hsync = drm_mode_hsync(mode);
7004 mode->vrefresh = drm_mode_vrefresh(mode);
7005 drm_mode_set_name(mode);
babea61d
JB
7006}
7007
84b046f3
DV
7008static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7009{
6315b5d3 7010 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
84b046f3
DV
7011 uint32_t pipeconf;
7012
9f11a9e4 7013 pipeconf = 0;
84b046f3 7014
b6b5d049
VS
7015 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7016 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7017 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7018
6e3c9717 7019 if (intel_crtc->config->double_wide)
cf532bb2 7020 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7021
ff9ce46e 7022 /* only g4x and later have fancy bpc/dither controls */
9beb5fea
TU
7023 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7024 IS_CHERRYVIEW(dev_priv)) {
ff9ce46e 7025 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7026 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7027 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7028 PIPECONF_DITHER_TYPE_SP;
84b046f3 7029
6e3c9717 7030 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV
7031 case 18:
7032 pipeconf |= PIPECONF_6BPC;
7033 break;
7034 case 24:
7035 pipeconf |= PIPECONF_8BPC;
7036 break;
7037 case 30:
7038 pipeconf |= PIPECONF_10BPC;
7039 break;
7040 default:
7041 /* Case prevented by intel_choose_pipe_bpp_dither. */
7042 BUG();
84b046f3
DV
7043 }
7044 }
7045
56b857a5 7046 if (HAS_PIPE_CXSR(dev_priv)) {
84b046f3
DV
7047 if (intel_crtc->lowfreq_avail) {
7048 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7049 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7050 } else {
7051 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV
7052 }
7053 }
7054
6e3c9717 7055 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6315b5d3 7056 if (INTEL_GEN(dev_priv) < 4 ||
2d84d2b3 7057 intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO))
efc2cfff
VS
7058 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7059 else
7060 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7061 } else
84b046f3
DV
7062 pipeconf |= PIPECONF_PROGRESSIVE;
7063
920a14b2 7064 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
666a4537 7065 intel_crtc->config->limited_color_range)
9f11a9e4 7066 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7067
84b046f3
DV
7068 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7069 POSTING_READ(PIPECONF(intel_crtc->pipe));
7070}
7071
81c97f52
ACO
7072static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7073 struct intel_crtc_state *crtc_state)
7074{
7075 struct drm_device *dev = crtc->base.dev;
fac5e23e 7076 struct drm_i915_private *dev_priv = to_i915(dev);
1b6f4958 7077 const struct intel_limit *limit;
81c97f52
ACO
7078 int refclk = 48000;
7079
7080 memset(&crtc_state->dpll_hw_state, 0,
7081 sizeof(crtc_state->dpll_hw_state));
7082
2d84d2b3 7083 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
81c97f52
ACO
7084 if (intel_panel_use_ssc(dev_priv)) {
7085 refclk = dev_priv->vbt.lvds_ssc_freq;
7086 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7087 }
7088
7089 limit = &intel_limits_i8xx_lvds;
2d84d2b3 7090 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) {
81c97f52
ACO
7091 limit = &intel_limits_i8xx_dvo;
7092 } else {
7093 limit = &intel_limits_i8xx_dac;
7094 }
7095
7096 if (!crtc_state->clock_set &&
7097 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7098 refclk, NULL, &crtc_state->dpll)) {
7099 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7100 return -EINVAL;
7101 }
7102
7103 i8xx_compute_dpll(crtc, crtc_state, NULL);
7104
7105 return 0;
7106}
7107
19ec6693
ACO
7108static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7109 struct intel_crtc_state *crtc_state)
7110{
7111 struct drm_device *dev = crtc->base.dev;
fac5e23e 7112 struct drm_i915_private *dev_priv = to_i915(dev);
1b6f4958 7113 const struct intel_limit *limit;
19ec6693
ACO
7114 int refclk = 96000;
7115
7116 memset(&crtc_state->dpll_hw_state, 0,
7117 sizeof(crtc_state->dpll_hw_state));
7118
2d84d2b3 7119 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
19ec6693
ACO
7120 if (intel_panel_use_ssc(dev_priv)) {
7121 refclk = dev_priv->vbt.lvds_ssc_freq;
7122 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7123 }
7124
7125 if (intel_is_dual_link_lvds(dev))
7126 limit = &intel_limits_g4x_dual_channel_lvds;
7127 else
7128 limit = &intel_limits_g4x_single_channel_lvds;
2d84d2b3
VS
7129 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7130 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
19ec6693 7131 limit = &intel_limits_g4x_hdmi;
2d84d2b3 7132 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) {
19ec6693
ACO
7133 limit = &intel_limits_g4x_sdvo;
7134 } else {
7135 /* The option is for other outputs */
7136 limit = &intel_limits_i9xx_sdvo;
7137 }
7138
7139 if (!crtc_state->clock_set &&
7140 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7141 refclk, NULL, &crtc_state->dpll)) {
7142 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7143 return -EINVAL;
7144 }
7145
7146 i9xx_compute_dpll(crtc, crtc_state, NULL);
7147
7148 return 0;
7149}
7150
70e8aa21
ACO
7151static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7152 struct intel_crtc_state *crtc_state)
7153{
7154 struct drm_device *dev = crtc->base.dev;
fac5e23e 7155 struct drm_i915_private *dev_priv = to_i915(dev);
1b6f4958 7156 const struct intel_limit *limit;
70e8aa21
ACO
7157 int refclk = 96000;
7158
7159 memset(&crtc_state->dpll_hw_state, 0,
7160 sizeof(crtc_state->dpll_hw_state));
7161
2d84d2b3 7162 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
70e8aa21
ACO
7163 if (intel_panel_use_ssc(dev_priv)) {
7164 refclk = dev_priv->vbt.lvds_ssc_freq;
7165 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7166 }
7167
7168 limit = &intel_limits_pineview_lvds;
7169 } else {
7170 limit = &intel_limits_pineview_sdvo;
7171 }
7172
7173 if (!crtc_state->clock_set &&
7174 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7175 refclk, NULL, &crtc_state->dpll)) {
7176 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7177 return -EINVAL;
7178 }
7179
7180 i9xx_compute_dpll(crtc, crtc_state, NULL);
7181
7182 return 0;
7183}
7184
190f68c5
ACO
7185static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7186 struct intel_crtc_state *crtc_state)
79e53945 7187{
c7653199 7188 struct drm_device *dev = crtc->base.dev;
fac5e23e 7189 struct drm_i915_private *dev_priv = to_i915(dev);
1b6f4958 7190 const struct intel_limit *limit;
81c97f52 7191 int refclk = 96000;
79e53945 7192
dd3cd74a
ACO
7193 memset(&crtc_state->dpll_hw_state, 0,
7194 sizeof(crtc_state->dpll_hw_state));
7195
2d84d2b3 7196 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
70e8aa21
ACO
7197 if (intel_panel_use_ssc(dev_priv)) {
7198 refclk = dev_priv->vbt.lvds_ssc_freq;
7199 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7200 }
43565a06 7201
70e8aa21
ACO
7202 limit = &intel_limits_i9xx_lvds;
7203 } else {
7204 limit = &intel_limits_i9xx_sdvo;
81c97f52 7205 }
79e53945 7206
70e8aa21
ACO
7207 if (!crtc_state->clock_set &&
7208 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7209 refclk, NULL, &crtc_state->dpll)) {
7210 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7211 return -EINVAL;
f47709a9 7212 }
7026d4ac 7213
81c97f52 7214 i9xx_compute_dpll(crtc, crtc_state, NULL);
79e53945 7215
c8f7a0db 7216 return 0;
f564048e
EA
7217}
7218
65b3d6a9
ACO
7219static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7220 struct intel_crtc_state *crtc_state)
7221{
7222 int refclk = 100000;
1b6f4958 7223 const struct intel_limit *limit = &intel_limits_chv;
65b3d6a9
ACO
7224
7225 memset(&crtc_state->dpll_hw_state, 0,
7226 sizeof(crtc_state->dpll_hw_state));
7227
65b3d6a9
ACO
7228 if (!crtc_state->clock_set &&
7229 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7230 refclk, NULL, &crtc_state->dpll)) {
7231 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7232 return -EINVAL;
7233 }
7234
7235 chv_compute_dpll(crtc, crtc_state);
7236
7237 return 0;
7238}
7239
7240static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7241 struct intel_crtc_state *crtc_state)
7242{
7243 int refclk = 100000;
1b6f4958 7244 const struct intel_limit *limit = &intel_limits_vlv;
65b3d6a9
ACO
7245
7246 memset(&crtc_state->dpll_hw_state, 0,
7247 sizeof(crtc_state->dpll_hw_state));
7248
65b3d6a9
ACO
7249 if (!crtc_state->clock_set &&
7250 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7251 refclk, NULL, &crtc_state->dpll)) {
7252 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7253 return -EINVAL;
7254 }
7255
7256 vlv_compute_dpll(crtc, crtc_state);
7257
7258 return 0;
7259}
7260
2fa2fe9a 7261static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7262 struct intel_crtc_state *pipe_config)
2fa2fe9a 7263{
6315b5d3 7264 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2fa2fe9a
DV
7265 uint32_t tmp;
7266
50a0bc90
TU
7267 if (INTEL_GEN(dev_priv) <= 3 &&
7268 (IS_I830(dev_priv) || !IS_MOBILE(dev_priv)))
dc9e7dec
VS
7269 return;
7270
2fa2fe9a 7271 tmp = I915_READ(PFIT_CONTROL);
06922821
DV
7272 if (!(tmp & PFIT_ENABLE))
7273 return;
2fa2fe9a 7274
06922821 7275 /* Check whether the pfit is attached to our pipe. */
6315b5d3 7276 if (INTEL_GEN(dev_priv) < 4) {
2fa2fe9a
DV
7277 if (crtc->pipe != PIPE_B)
7278 return;
2fa2fe9a
DV
7279 } else {
7280 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7281 return;
7282 }
7283
06922821 7284 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a 7285 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
2fa2fe9a
DV
7286}
7287
acbec814 7288static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7289 struct intel_crtc_state *pipe_config)
acbec814
JB
7290{
7291 struct drm_device *dev = crtc->base.dev;
fac5e23e 7292 struct drm_i915_private *dev_priv = to_i915(dev);
acbec814 7293 int pipe = pipe_config->cpu_transcoder;
9e2c8475 7294 struct dpll clock;
acbec814 7295 u32 mdiv;
662c6ecb 7296 int refclk = 100000;
acbec814 7297
b521973b
VS
7298 /* In case of DSI, DPLL will not be used */
7299 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
f573de5a
SK
7300 return;
7301
a580516d 7302 mutex_lock(&dev_priv->sb_lock);
ab3c759a 7303 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 7304 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB
7305
7306 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7307 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7308 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7309 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7310 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7311
dccbea3b 7312 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
acbec814
JB
7313}
7314
5724dbd1
DL
7315static void
7316i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7317 struct intel_initial_plane_config *plane_config)
1ad292b5
JB
7318{
7319 struct drm_device *dev = crtc->base.dev;
fac5e23e 7320 struct drm_i915_private *dev_priv = to_i915(dev);
1ad292b5
JB
7321 u32 val, base, offset;
7322 int pipe = crtc->pipe, plane = crtc->plane;
7323 int fourcc, pixel_format;
6761dd31 7324 unsigned int aligned_height;
b113d5ee 7325 struct drm_framebuffer *fb;
1b842c89 7326 struct intel_framebuffer *intel_fb;
1ad292b5 7327
42a7b088
DL
7328 val = I915_READ(DSPCNTR(plane));
7329 if (!(val & DISPLAY_PLANE_ENABLE))
7330 return;
7331
d9806c9f 7332 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7333 if (!intel_fb) {
1ad292b5
JB
7334 DRM_DEBUG_KMS("failed to alloc fb\n");
7335 return;
7336 }
7337
1b842c89
DL
7338 fb = &intel_fb->base;
7339
d2e9f5fc
VS
7340 fb->dev = dev;
7341
6315b5d3 7342 if (INTEL_GEN(dev_priv) >= 4) {
18c5247e 7343 if (val & DISPPLANE_TILED) {
49af449b 7344 plane_config->tiling = I915_TILING_X;
bae781b2 7345 fb->modifier = I915_FORMAT_MOD_X_TILED;
18c5247e
DV
7346 }
7347 }
1ad292b5
JB
7348
7349 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7350 fourcc = i9xx_format_to_fourcc(pixel_format);
2f3f4763 7351 fb->format = drm_format_info(fourcc);
1ad292b5 7352
6315b5d3 7353 if (INTEL_GEN(dev_priv) >= 4) {
49af449b 7354 if (plane_config->tiling)
1ad292b5
JB
7355 offset = I915_READ(DSPTILEOFF(plane));
7356 else
7357 offset = I915_READ(DSPLINOFF(plane));
7358 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7359 } else {
7360 base = I915_READ(DSPADDR(plane));
7361 }
7362 plane_config->base = base;
7363
7364 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL
7365 fb->width = ((val >> 16) & 0xfff) + 1;
7366 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB
7367
7368 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 7369 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 7370
d88c4afd 7371 aligned_height = intel_fb_align_height(fb, 0, fb->height);
1ad292b5 7372
f37b5c2b 7373 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 7374
2844a921
DL
7375 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7376 pipe_name(pipe), plane, fb->width, fb->height,
272725c7 7377 fb->format->cpp[0] * 8, base, fb->pitches[0],
2844a921 7378 plane_config->size);
1ad292b5 7379
2d14030b 7380 plane_config->fb = intel_fb;
1ad292b5
JB
7381}
7382
70b23a98 7383static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7384 struct intel_crtc_state *pipe_config)
70b23a98
VS
7385{
7386 struct drm_device *dev = crtc->base.dev;
fac5e23e 7387 struct drm_i915_private *dev_priv = to_i915(dev);
70b23a98
VS
7388 int pipe = pipe_config->cpu_transcoder;
7389 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9e2c8475 7390 struct dpll clock;
0d7b6b11 7391 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
70b23a98
VS
7392 int refclk = 100000;
7393
b521973b
VS
7394 /* In case of DSI, DPLL will not be used */
7395 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
7396 return;
7397
a580516d 7398 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS
7399 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7400 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7401 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7402 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
0d7b6b11 7403 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
a580516d 7404 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS
7405
7406 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
0d7b6b11
ID
7407 clock.m2 = (pll_dw0 & 0xff) << 22;
7408 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
7409 clock.m2 |= pll_dw2 & 0x3fffff;
70b23a98
VS
7410 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7411 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7412 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7413
dccbea3b 7414 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
70b23a98
VS
7415}
7416
0e8ffe1b 7417static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 7418 struct intel_crtc_state *pipe_config)
0e8ffe1b 7419{
6315b5d3 7420 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1729050e 7421 enum intel_display_power_domain power_domain;
0e8ffe1b 7422 uint32_t tmp;
1729050e 7423 bool ret;
0e8ffe1b 7424
1729050e
ID
7425 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
7426 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
b5482bd0
ID
7427 return false;
7428
e143a21c 7429 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8106ddbd 7430 pipe_config->shared_dpll = NULL;
eccb140b 7431
1729050e
ID
7432 ret = false;
7433
0e8ffe1b
DV
7434 tmp = I915_READ(PIPECONF(crtc->pipe));
7435 if (!(tmp & PIPECONF_ENABLE))
1729050e 7436 goto out;
0e8ffe1b 7437
9beb5fea
TU
7438 if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
7439 IS_CHERRYVIEW(dev_priv)) {
42571aef
VS
7440 switch (tmp & PIPECONF_BPC_MASK) {
7441 case PIPECONF_6BPC:
7442 pipe_config->pipe_bpp = 18;
7443 break;
7444 case PIPECONF_8BPC:
7445 pipe_config->pipe_bpp = 24;
7446 break;
7447 case PIPECONF_10BPC:
7448 pipe_config->pipe_bpp = 30;
7449 break;
7450 default:
7451 break;
7452 }
7453 }
7454
920a14b2 7455 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
666a4537 7456 (tmp & PIPECONF_COLOR_RANGE_SELECT))
b5a9fa09
DV
7457 pipe_config->limited_color_range = true;
7458
6315b5d3 7459 if (INTEL_GEN(dev_priv) < 4)
282740f7
VS
7460 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7461
1bd1bd80 7462 intel_get_pipe_timings(crtc, pipe_config);
bc58be60 7463 intel_get_pipe_src_size(crtc, pipe_config);
1bd1bd80 7464
2fa2fe9a
DV
7465 i9xx_get_pfit_config(crtc, pipe_config);
7466
6315b5d3 7467 if (INTEL_GEN(dev_priv) >= 4) {
c231775c 7468 /* No way to read it out on pipes B and C */
920a14b2 7469 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
c231775c
VS
7470 tmp = dev_priv->chv_dpll_md[crtc->pipe];
7471 else
7472 tmp = I915_READ(DPLL_MD(crtc->pipe));
6c49f241
DV
7473 pipe_config->pixel_multiplier =
7474 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7475 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 7476 pipe_config->dpll_hw_state.dpll_md = tmp;
50a0bc90 7477 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
73f67aa8 7478 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
6c49f241
DV
7479 tmp = I915_READ(DPLL(crtc->pipe));
7480 pipe_config->pixel_multiplier =
7481 ((tmp & SDVO_MULTIPLIER_MASK)
7482 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7483 } else {
7484 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7485 * port and will be fixed up in the encoder->get_config
7486 * function. */
7487 pipe_config->pixel_multiplier = 1;
7488 }
8bcc2795 7489 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
920a14b2 7490 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
1c4e0274
VS
7491 /*
7492 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7493 * on 830. Filter it out here so that we don't
7494 * report errors due to that.
7495 */
50a0bc90 7496 if (IS_I830(dev_priv))
1c4e0274
VS
7497 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7498
8bcc2795
DV
7499 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7500 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS
7501 } else {
7502 /* Mask out read-only status bits. */
7503 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7504 DPLL_PORTC_READY_MASK |
7505 DPLL_PORTB_READY_MASK);
8bcc2795 7506 }
6c49f241 7507
920a14b2 7508 if (IS_CHERRYVIEW(dev_priv))
70b23a98 7509 chv_crtc_clock_get(crtc, pipe_config);
11a914c2 7510 else if (IS_VALLEYVIEW(dev_priv))
acbec814
JB
7511 vlv_crtc_clock_get(crtc, pipe_config);
7512 else
7513 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 7514
0f64614d
VS
7515 /*
7516 * Normally the dotclock is filled in by the encoder .get_config()
7517 * but in case the pipe is enabled w/o any ports we need a sane
7518 * default.
7519 */
7520 pipe_config->base.adjusted_mode.crtc_clock =
7521 pipe_config->port_clock / pipe_config->pixel_multiplier;
7522
1729050e
ID
7523 ret = true;
7524
7525out:
7526 intel_display_power_put(dev_priv, power_domain);
7527
7528 return ret;
0e8ffe1b
DV
7529}
7530
c39055b0 7531static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv)
13d83a67 7532{
13d83a67 7533 struct intel_encoder *encoder;
1c1a24d2 7534 int i;
74cfd7ac 7535 u32 val, final;
13d83a67 7536 bool has_lvds = false;
199e5d79 7537 bool has_cpu_edp = false;
199e5d79 7538 bool has_panel = false;
99eb6a01
KP
7539 bool has_ck505 = false;
7540 bool can_ssc = false;
1c1a24d2 7541 bool using_ssc_source = false;
13d83a67
JB
7542
7543 /* We need to take the global config into account */
c39055b0 7544 for_each_intel_encoder(&dev_priv->drm, encoder) {
199e5d79
KP
7545 switch (encoder->type) {
7546 case INTEL_OUTPUT_LVDS:
7547 has_panel = true;
7548 has_lvds = true;
7549 break;
7550 case INTEL_OUTPUT_EDP:
7551 has_panel = true;
2de6905f 7552 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP
7553 has_cpu_edp = true;
7554 break;
6847d71b
PZ
7555 default:
7556 break;
13d83a67
JB
7557 }
7558 }
7559
6e266956 7560 if (HAS_PCH_IBX(dev_priv)) {
41aa3448 7561 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP
7562 can_ssc = has_ck505;
7563 } else {
7564 has_ck505 = false;
7565 can_ssc = true;
7566 }
7567
1c1a24d2
L
7568 /* Check if any DPLLs are using the SSC source */
7569 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
7570 u32 temp = I915_READ(PCH_DPLL(i));
7571
7572 if (!(temp & DPLL_VCO_ENABLE))
7573 continue;
7574
7575 if ((temp & PLL_REF_INPUT_MASK) ==
7576 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7577 using_ssc_source = true;
7578 break;
7579 }
7580 }
7581
7582 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n",
7583 has_panel, has_lvds, has_ck505, using_ssc_source);
13d83a67
JB
7584
7585 /* Ironlake: try to setup display ref clock before DPLL
7586 * enabling. This is only under driver's control after
7587 * PCH B stepping, previous chipset stepping should be
7588 * ignoring this setting.
7589 */
74cfd7ac
CW
7590 val = I915_READ(PCH_DREF_CONTROL);
7591
7592 /* As we must carefully and slowly disable/enable each source in turn,
7593 * compute the final state we want first and check if we need to
7594 * make any changes at all.
7595 */
7596 final = val;
7597 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7598 if (has_ck505)
7599 final |= DREF_NONSPREAD_CK505_ENABLE;
7600 else
7601 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7602
8c07eb68 7603 final &= ~DREF_SSC_SOURCE_MASK;
74cfd7ac 7604 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8c07eb68 7605 final &= ~DREF_SSC1_ENABLE;
74cfd7ac
CW
7606
7607 if (has_panel) {
7608 final |= DREF_SSC_SOURCE_ENABLE;
7609
7610 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7611 final |= DREF_SSC1_ENABLE;
7612
7613 if (has_cpu_edp) {
7614 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7615 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7616 else
7617 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7618 } else
7619 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
1c1a24d2
L
7620 } else if (using_ssc_source) {
7621 final |= DREF_SSC_SOURCE_ENABLE;
7622 final |= DREF_SSC1_ENABLE;
74cfd7ac
CW
7623 }
7624
7625 if (final == val)
7626 return;
7627
13d83a67 7628 /* Always enable nonspread source */
74cfd7ac 7629 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 7630
99eb6a01 7631 if (has_ck505)
74cfd7ac 7632 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 7633 else
74cfd7ac 7634 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 7635
199e5d79 7636 if (has_panel) {
74cfd7ac
CW
7637 val &= ~DREF_SSC_SOURCE_MASK;
7638 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 7639
199e5d79 7640 /* SSC must be turned on before enabling the CPU output */
99eb6a01 7641 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7642 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 7643 val |= DREF_SSC1_ENABLE;
e77166b5 7644 } else
74cfd7ac 7645 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP
7646
7647 /* Get SSC going before enabling the outputs */
74cfd7ac 7648 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP
7649 POSTING_READ(PCH_DREF_CONTROL);
7650 udelay(200);
7651
74cfd7ac 7652 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB
7653
7654 /* Enable CPU source on CPU attached eDP */
199e5d79 7655 if (has_cpu_edp) {
99eb6a01 7656 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7657 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 7658 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 7659 } else
74cfd7ac 7660 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 7661 } else
74cfd7ac 7662 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7663
74cfd7ac 7664 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP
7665 POSTING_READ(PCH_DREF_CONTROL);
7666 udelay(200);
7667 } else {
1c1a24d2 7668 DRM_DEBUG_KMS("Disabling CPU source output\n");
199e5d79 7669
74cfd7ac 7670 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP
7671
7672 /* Turn off CPU output */
74cfd7ac 7673 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7674
74cfd7ac 7675 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP
7676 POSTING_READ(PCH_DREF_CONTROL);
7677 udelay(200);
7678
1c1a24d2
L
7679 if (!using_ssc_source) {
7680 DRM_DEBUG_KMS("Disabling SSC source\n");
199e5d79 7681
1c1a24d2
L
7682 /* Turn off the SSC source */
7683 val &= ~DREF_SSC_SOURCE_MASK;
7684 val |= DREF_SSC_SOURCE_DISABLE;
f165d283 7685
1c1a24d2
L
7686 /* Turn off SSC1 */
7687 val &= ~DREF_SSC1_ENABLE;
7688
7689 I915_WRITE(PCH_DREF_CONTROL, val);
7690 POSTING_READ(PCH_DREF_CONTROL);
7691 udelay(200);
7692 }
13d83a67 7693 }
74cfd7ac
CW
7694
7695 BUG_ON(val != final);
13d83a67
JB
7696}
7697
f31f2d55 7698static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 7699{
f31f2d55 7700 uint32_t tmp;
dde86e2d 7701
0ff066a9
PZ
7702 tmp = I915_READ(SOUTH_CHICKEN2);
7703 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7704 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7705
cf3598c2
ID
7706 if (wait_for_us(I915_READ(SOUTH_CHICKEN2) &
7707 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
0ff066a9 7708 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 7709
0ff066a9
PZ
7710 tmp = I915_READ(SOUTH_CHICKEN2);
7711 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7712 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7713
cf3598c2
ID
7714 if (wait_for_us((I915_READ(SOUTH_CHICKEN2) &
7715 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
0ff066a9 7716 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ
7717}
7718
7719/* WaMPhyProgramming:hsw */
7720static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7721{
7722 uint32_t tmp;
dde86e2d
PZ
7723
7724 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7725 tmp &= ~(0xFF << 24);
7726 tmp |= (0x12 << 24);
7727 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7728
dde86e2d
PZ
7729 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7730 tmp |= (1 << 11);
7731 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7732
7733 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7734 tmp |= (1 << 11);
7735 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7736
dde86e2d
PZ
7737 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7738 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7739 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7740
7741 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7742 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7743 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7744
0ff066a9
PZ
7745 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7746 tmp &= ~(7 << 13);
7747 tmp |= (5 << 13);
7748 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 7749
0ff066a9
PZ
7750 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7751 tmp &= ~(7 << 13);
7752 tmp |= (5 << 13);
7753 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ
7754
7755 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7756 tmp &= ~0xFF;
7757 tmp |= 0x1C;
7758 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7759
7760 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7761 tmp &= ~0xFF;
7762 tmp |= 0x1C;
7763 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7764
7765 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7766 tmp &= ~(0xFF << 16);
7767 tmp |= (0x1C << 16);
7768 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7769
7770 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7771 tmp &= ~(0xFF << 16);
7772 tmp |= (0x1C << 16);
7773 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7774
0ff066a9
PZ
7775 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7776 tmp |= (1 << 27);
7777 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 7778
0ff066a9
PZ
7779 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7780 tmp |= (1 << 27);
7781 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 7782
0ff066a9
PZ
7783 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7784 tmp &= ~(0xF << 28);
7785 tmp |= (4 << 28);
7786 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 7787
0ff066a9
PZ
7788 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7789 tmp &= ~(0xF << 28);
7790 tmp |= (4 << 28);
7791 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ
7792}
7793
2fa86a1f
PZ
7794/* Implements 3 different sequences from BSpec chapter "Display iCLK
7795 * Programming" based on the parameters passed:
7796 * - Sequence to enable CLKOUT_DP
7797 * - Sequence to enable CLKOUT_DP without spread
7798 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7799 */
c39055b0
ACO
7800static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv,
7801 bool with_spread, bool with_fdi)
f31f2d55 7802{
2fa86a1f
PZ
7803 uint32_t reg, tmp;
7804
7805 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7806 with_spread = true;
4f8036a2
TU
7807 if (WARN(HAS_PCH_LPT_LP(dev_priv) &&
7808 with_fdi, "LP PCH doesn't have FDI\n"))
2fa86a1f 7809 with_fdi = false;
f31f2d55 7810
a580516d 7811 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ
7812
7813 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7814 tmp &= ~SBI_SSCCTL_DISABLE;
7815 tmp |= SBI_SSCCTL_PATHALT;
7816 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7817
7818 udelay(24);
7819
2fa86a1f
PZ
7820 if (with_spread) {
7821 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7822 tmp &= ~SBI_SSCCTL_PATHALT;
7823 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 7824
2fa86a1f
PZ
7825 if (with_fdi) {
7826 lpt_reset_fdi_mphy(dev_priv);
7827 lpt_program_fdi_mphy(dev_priv);
7828 }
7829 }
dde86e2d 7830
4f8036a2 7831 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
2fa86a1f
PZ
7832 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7833 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7834 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 7835
a580516d 7836 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ
7837}
7838
47701c3b 7839/* Sequence to disable CLKOUT_DP */
c39055b0 7840static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv)
47701c3b 7841{
47701c3b
PZ
7842 uint32_t reg, tmp;
7843
a580516d 7844 mutex_lock(&dev_priv->sb_lock);
47701c3b 7845
4f8036a2 7846 reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0;
47701c3b
PZ
7847 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7848 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7849 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7850
7851 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7852 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7853 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7854 tmp |= SBI_SSCCTL_PATHALT;
7855 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7856 udelay(32);
7857 }
7858 tmp |= SBI_SSCCTL_DISABLE;
7859 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7860 }
7861
a580516d 7862 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ
7863}
7864
f7be2c21
VS
7865#define BEND_IDX(steps) ((50 + (steps)) / 5)
7866
7867static const uint16_t sscdivintphase[] = {
7868 [BEND_IDX( 50)] = 0x3B23,
7869 [BEND_IDX( 45)] = 0x3B23,
7870 [BEND_IDX( 40)] = 0x3C23,
7871 [BEND_IDX( 35)] = 0x3C23,
7872 [BEND_IDX( 30)] = 0x3D23,
7873 [BEND_IDX( 25)] = 0x3D23,
7874 [BEND_IDX( 20)] = 0x3E23,
7875 [BEND_IDX( 15)] = 0x3E23,
7876 [BEND_IDX( 10)] = 0x3F23,
7877 [BEND_IDX( 5)] = 0x3F23,
7878 [BEND_IDX( 0)] = 0x0025,
7879 [BEND_IDX( -5)] = 0x0025,
7880 [BEND_IDX(-10)] = 0x0125,
7881 [BEND_IDX(-15)] = 0x0125,
7882 [BEND_IDX(-20)] = 0x0225,
7883 [BEND_IDX(-25)] = 0x0225,
7884 [BEND_IDX(-30)] = 0x0325,
7885 [BEND_IDX(-35)] = 0x0325,
7886 [BEND_IDX(-40)] = 0x0425,
7887 [BEND_IDX(-45)] = 0x0425,
7888 [BEND_IDX(-50)] = 0x0525,
7889};
7890
7891/*
7892 * Bend CLKOUT_DP
7893 * steps -50 to 50 inclusive, in steps of 5
7894 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
7895 * change in clock period = -(steps / 10) * 5.787 ps
7896 */
7897static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
7898{
7899 uint32_t tmp;
7900 int idx = BEND_IDX(steps);
7901
7902 if (WARN_ON(steps % 5 != 0))
7903 return;
7904
7905 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
7906 return;
7907
7908 mutex_lock(&dev_priv->sb_lock);
7909
7910 if (steps % 10 != 0)
7911 tmp = 0xAAAAAAAB;
7912 else
7913 tmp = 0x00000000;
7914 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
7915
7916 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
7917 tmp &= 0xffff0000;
7918 tmp |= sscdivintphase[idx];
7919 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
7920
7921 mutex_unlock(&dev_priv->sb_lock);
7922}
7923
7924#undef BEND_IDX
7925
c39055b0 7926static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv)
bf8fa3d3 7927{
bf8fa3d3
PZ
7928 struct intel_encoder *encoder;
7929 bool has_vga = false;
7930
c39055b0 7931 for_each_intel_encoder(&dev_priv->drm, encoder) {
bf8fa3d3
PZ
7932 switch (encoder->type) {
7933 case INTEL_OUTPUT_ANALOG:
7934 has_vga = true;
7935 break;
6847d71b
PZ
7936 default:
7937 break;
bf8fa3d3
PZ
7938 }
7939 }
7940
f7be2c21 7941 if (has_vga) {
c39055b0
ACO
7942 lpt_bend_clkout_dp(dev_priv, 0);
7943 lpt_enable_clkout_dp(dev_priv, true, true);
f7be2c21 7944 } else {
c39055b0 7945 lpt_disable_clkout_dp(dev_priv);
f7be2c21 7946 }
bf8fa3d3
PZ
7947}
7948
dde86e2d
PZ
7949/*
7950 * Initialize reference clocks when the driver loads
7951 */
c39055b0 7952void intel_init_pch_refclk(struct drm_i915_private *dev_priv)
dde86e2d 7953{
6e266956 7954 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
c39055b0 7955 ironlake_init_pch_refclk(dev_priv);
6e266956 7956 else if (HAS_PCH_LPT(dev_priv))
c39055b0 7957 lpt_init_pch_refclk(dev_priv);
dde86e2d
PZ
7958}
7959
6ff93609 7960static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 7961{
fac5e23e 7962 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
79e53945
JB
7963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7964 int pipe = intel_crtc->pipe;
c8203565
PZ
7965 uint32_t val;
7966
78114071 7967 val = 0;
c8203565 7968
6e3c9717 7969 switch (intel_crtc->config->pipe_bpp) {
c8203565 7970 case 18:
dfd07d72 7971 val |= PIPECONF_6BPC;
c8203565
PZ
7972 break;
7973 case 24:
dfd07d72 7974 val |= PIPECONF_8BPC;
c8203565
PZ
7975 break;
7976 case 30:
dfd07d72 7977 val |= PIPECONF_10BPC;
c8203565
PZ
7978 break;
7979 case 36:
dfd07d72 7980 val |= PIPECONF_12BPC;
c8203565
PZ
7981 break;
7982 default:
cc769b62
PZ
7983 /* Case prevented by intel_choose_pipe_bpp_dither. */
7984 BUG();
c8203565
PZ
7985 }
7986
6e3c9717 7987 if (intel_crtc->config->dither)
c8203565
PZ
7988 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7989
6e3c9717 7990 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ
7991 val |= PIPECONF_INTERLACED_ILK;
7992 else
7993 val |= PIPECONF_PROGRESSIVE;
7994
6e3c9717 7995 if (intel_crtc->config->limited_color_range)
3685a8f3 7996 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 7997
c8203565
PZ
7998 I915_WRITE(PIPECONF(pipe), val);
7999 POSTING_READ(PIPECONF(pipe));
8000}
8001
6ff93609 8002static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8003{
fac5e23e 8004 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
ee2b0b38 8005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 8006 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
391bf048 8007 u32 val = 0;
ee2b0b38 8008
391bf048 8009 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
ee2b0b38
PZ
8010 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8011
6e3c9717 8012 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ
8013 val |= PIPECONF_INTERLACED_ILK;
8014 else
8015 val |= PIPECONF_PROGRESSIVE;
8016
702e7a56
PZ
8017 I915_WRITE(PIPECONF(cpu_transcoder), val);
8018 POSTING_READ(PIPECONF(cpu_transcoder));
391bf048
JN
8019}
8020
391bf048
JN
8021static void haswell_set_pipemisc(struct drm_crtc *crtc)
8022{
fac5e23e 8023 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
391bf048 8024 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8025
391bf048
JN
8026 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8027 u32 val = 0;
756f85cf 8028
6e3c9717 8029 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ
8030 case 18:
8031 val |= PIPEMISC_DITHER_6_BPC;
8032 break;
8033 case 24:
8034 val |= PIPEMISC_DITHER_8_BPC;
8035 break;
8036 case 30:
8037 val |= PIPEMISC_DITHER_10_BPC;
8038 break;
8039 case 36:
8040 val |= PIPEMISC_DITHER_12_BPC;
8041 break;
8042 default:
8043 /* Case prevented by pipe_config_set_bpp. */
8044 BUG();
8045 }
8046
6e3c9717 8047 if (intel_crtc->config->dither)
756f85cf
PZ
8048 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8049
391bf048 8050 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
756f85cf 8051 }
ee2b0b38
PZ
8052}
8053
d4b1931c
PZ
8054int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8055{
8056 /*
8057 * Account for spread spectrum to avoid
8058 * oversubscribing the link. Max center spread
8059 * is 2.5%; use 5% for safety's sake.
8060 */
8061 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8062 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ
8063}
8064
7429e9d4 8065static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8066{
7429e9d4 8067 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ
8068}
8069
b75ca6f6
ACO
8070static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8071 struct intel_crtc_state *crtc_state,
9e2c8475 8072 struct dpll *reduced_clock)
79e53945 8073{
de13a2e3 8074 struct drm_crtc *crtc = &intel_crtc->base;
79e53945 8075 struct drm_device *dev = crtc->dev;
fac5e23e 8076 struct drm_i915_private *dev_priv = to_i915(dev);
b75ca6f6 8077 u32 dpll, fp, fp2;
3d6e9ee0 8078 int factor;
79e53945 8079
c1858123 8080 /* Enable autotuning of the PLL clock (if permissible) */
8febb297 8081 factor = 21;
3d6e9ee0 8082 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8febb297 8083 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8084 dev_priv->vbt.lvds_ssc_freq == 100000) ||
6e266956 8085 (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev)))
8febb297 8086 factor = 25;
190f68c5 8087 } else if (crtc_state->sdvo_tv_clock)
8febb297 8088 factor = 20;
c1858123 8089
b75ca6f6
ACO
8090 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8091
190f68c5 8092 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
b75ca6f6
ACO
8093 fp |= FP_CB_TUNE;
8094
8095 if (reduced_clock) {
8096 fp2 = i9xx_dpll_compute_fp(reduced_clock);
2c07245f 8097
b75ca6f6
ACO
8098 if (reduced_clock->m < factor * reduced_clock->n)
8099 fp2 |= FP_CB_TUNE;
8100 } else {
8101 fp2 = fp;
8102 }
9a7c7890 8103
5eddb70b 8104 dpll = 0;
2c07245f 8105
3d6e9ee0 8106 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS))
a07d6787
EA
8107 dpll |= DPLLB_MODE_LVDS;
8108 else
8109 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8110
190f68c5 8111 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8112 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f 8113
3d6e9ee0
VS
8114 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) ||
8115 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
4a33e48d 8116 dpll |= DPLL_SDVO_HIGH_SPEED;
3d6e9ee0 8117
37a5650b 8118 if (intel_crtc_has_dp_encoder(crtc_state))
4a33e48d 8119 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8120
7d7f8633
VS
8121 /*
8122 * The high speed IO clock is only really required for
8123 * SDVO/HDMI/DP, but we also enable it for CRT to make it
8124 * possible to share the DPLL between CRT and HDMI. Enabling
8125 * the clock needlessly does no real harm, except use up a
8126 * bit of power potentially.
8127 *
8128 * We'll limit this to IVB with 3 pipes, since it has only two
8129 * DPLLs and so DPLL sharing is the only way to get three pipes
8130 * driving PCH ports at the same time. On SNB we could do this,
8131 * and potentially avoid enabling the second DPLL, but it's not
8132 * clear if it''s a win or loss power wise. No point in doing
8133 * this on ILK at all since it has a fixed DPLL<->pipe mapping.
8134 */
8135 if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
8136 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
8137 dpll |= DPLL_SDVO_HIGH_SPEED;
8138
a07d6787 8139 /* compute bitmask from p1 value */
190f68c5 8140 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8141 /* also FPA1 */
190f68c5 8142 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8143
190f68c5 8144 switch (crtc_state->dpll.p2) {
a07d6787
EA
8145 case 5:
8146 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8147 break;
8148 case 7:
8149 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8150 break;
8151 case 10:
8152 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8153 break;
8154 case 14:
8155 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8156 break;
79e53945
JB
8157 }
8158
3d6e9ee0
VS
8159 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8160 intel_panel_use_ssc(dev_priv))
43565a06 8161 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB
8162 else
8163 dpll |= PLL_REF_INPUT_DREFCLK;
8164
b75ca6f6
ACO
8165 dpll |= DPLL_VCO_ENABLE;
8166
8167 crtc_state->dpll_hw_state.dpll = dpll;
8168 crtc_state->dpll_hw_state.fp0 = fp;
8169 crtc_state->dpll_hw_state.fp1 = fp2;
de13a2e3
PZ
8170}
8171
190f68c5
ACO
8172static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8173 struct intel_crtc_state *crtc_state)
de13a2e3 8174{
997c030c 8175 struct drm_device *dev = crtc->base.dev;
fac5e23e 8176 struct drm_i915_private *dev_priv = to_i915(dev);
9e2c8475 8177 struct dpll reduced_clock;
7ed9f894 8178 bool has_reduced_clock = false;
e2b78267 8179 struct intel_shared_dpll *pll;
1b6f4958 8180 const struct intel_limit *limit;
997c030c 8181 int refclk = 120000;
de13a2e3 8182
dd3cd74a
ACO
8183 memset(&crtc_state->dpll_hw_state, 0,
8184 sizeof(crtc_state->dpll_hw_state));
8185
ded220e2
ACO
8186 crtc->lowfreq_avail = false;
8187
8188 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8189 if (!crtc_state->has_pch_encoder)
8190 return 0;
79e53945 8191
2d84d2b3 8192 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) {
997c030c
ACO
8193 if (intel_panel_use_ssc(dev_priv)) {
8194 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8195 dev_priv->vbt.lvds_ssc_freq);
8196 refclk = dev_priv->vbt.lvds_ssc_freq;
8197 }
8198
8199 if (intel_is_dual_link_lvds(dev)) {
8200 if (refclk == 100000)
8201 limit = &intel_limits_ironlake_dual_lvds_100m;
8202 else
8203 limit = &intel_limits_ironlake_dual_lvds;
8204 } else {
8205 if (refclk == 100000)
8206 limit = &intel_limits_ironlake_single_lvds_100m;
8207 else
8208 limit = &intel_limits_ironlake_single_lvds;
8209 }
8210 } else {
8211 limit = &intel_limits_ironlake_dac;
8212 }
8213
364ee29d 8214 if (!crtc_state->clock_set &&
997c030c
ACO
8215 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8216 refclk, NULL, &crtc_state->dpll)) {
364ee29d
ACO
8217 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8218 return -EINVAL;
f47709a9 8219 }
79e53945 8220
b75ca6f6
ACO
8221 ironlake_compute_dpll(crtc, crtc_state,
8222 has_reduced_clock ? &reduced_clock : NULL);
66e985c0 8223
ded220e2
ACO
8224 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8225 if (pll == NULL) {
8226 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8227 pipe_name(crtc->pipe));
8228 return -EINVAL;
3fb37703 8229 }
79e53945 8230
2d84d2b3 8231 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ded220e2 8232 has_reduced_clock)
c7653199 8233 crtc->lowfreq_avail = true;
e2b78267 8234
c8f7a0db 8235 return 0;
79e53945
JB
8236}
8237
eb14cb74
VS
8238static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8239 struct intel_link_m_n *m_n)
8240{
8241 struct drm_device *dev = crtc->base.dev;
fac5e23e 8242 struct drm_i915_private *dev_priv = to_i915(dev);
eb14cb74
VS
8243 enum pipe pipe = crtc->pipe;
8244
8245 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8246 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8247 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8248 & ~TU_SIZE_MASK;
8249 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8250 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8251 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8252}
8253
8254static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8255 enum transcoder transcoder,
b95af8be
VK
8256 struct intel_link_m_n *m_n,
8257 struct intel_link_m_n *m2_n2)
72419203 8258{
6315b5d3 8259 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
eb14cb74 8260 enum pipe pipe = crtc->pipe;
72419203 8261
6315b5d3 8262 if (INTEL_GEN(dev_priv) >= 5) {
eb14cb74
VS
8263 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8264 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8265 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8266 & ~TU_SIZE_MASK;
8267 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8268 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8269 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK
8270 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8271 * gen < 8) and if DRRS is supported (to make sure the
8272 * registers are not unnecessarily read).
8273 */
6315b5d3 8274 if (m2_n2 && INTEL_GEN(dev_priv) < 8 &&
6e3c9717 8275 crtc->config->has_drrs) {
b95af8be
VK
8276 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8277 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8278 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8279 & ~TU_SIZE_MASK;
8280 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8281 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8282 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8283 }
eb14cb74
VS
8284 } else {
8285 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8286 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8287 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8288 & ~TU_SIZE_MASK;
8289 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8290 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8291 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8292 }
8293}
8294
8295void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8296 struct intel_crtc_state *pipe_config)
eb14cb74 8297{
681a8504 8298 if (pipe_config->has_pch_encoder)
eb14cb74
VS
8299 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8300 else
8301 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK
8302 &pipe_config->dp_m_n,
8303 &pipe_config->dp_m2_n2);
eb14cb74 8304}
72419203 8305
eb14cb74 8306static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8307 struct intel_crtc_state *pipe_config)
eb14cb74
VS
8308{
8309 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8310 &pipe_config->fdi_m_n, NULL);
72419203
DV
8311}
8312
bd2e244f 8313static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8314 struct intel_crtc_state *pipe_config)
bd2e244f
JB
8315{
8316 struct drm_device *dev = crtc->base.dev;
fac5e23e 8317 struct drm_i915_private *dev_priv = to_i915(dev);
a1b2278e
CK
8318 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8319 uint32_t ps_ctrl = 0;
8320 int id = -1;
8321 int i;
bd2e244f 8322
a1b2278e
CK
8323 /* find scaler attached to this pipe */
8324 for (i = 0; i < crtc->num_scalers; i++) {
8325 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8326 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8327 id = i;
8328 pipe_config->pch_pfit.enabled = true;
8329 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8330 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8331 break;
8332 }
8333 }
bd2e244f 8334
a1b2278e
CK
8335 scaler_state->scaler_id = id;
8336 if (id >= 0) {
8337 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8338 } else {
8339 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB
8340 }
8341}
8342
5724dbd1
DL
8343static void
8344skylake_get_initial_plane_config(struct intel_crtc *crtc,
8345 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL
8346{
8347 struct drm_device *dev = crtc->base.dev;
fac5e23e 8348 struct drm_i915_private *dev_priv = to_i915(dev);
40f46283 8349 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL
8350 int pipe = crtc->pipe;
8351 int fourcc, pixel_format;
6761dd31 8352 unsigned int aligned_height;
bc8d7dff 8353 struct drm_framebuffer *fb;
1b842c89 8354 struct intel_framebuffer *intel_fb;
bc8d7dff 8355
d9806c9f 8356 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8357 if (!intel_fb) {
bc8d7dff
DL
8358 DRM_DEBUG_KMS("failed to alloc fb\n");
8359 return;
8360 }
8361
1b842c89
DL
8362 fb = &intel_fb->base;
8363
d2e9f5fc
VS
8364 fb->dev = dev;
8365
bc8d7dff 8366 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL
8367 if (!(val & PLANE_CTL_ENABLE))
8368 goto error;
8369
bc8d7dff
DL
8370 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8371 fourcc = skl_format_to_fourcc(pixel_format,
8372 val & PLANE_CTL_ORDER_RGBX,
8373 val & PLANE_CTL_ALPHA_MASK);
2f3f4763 8374 fb->format = drm_format_info(fourcc);
bc8d7dff 8375
40f46283
DL
8376 tiling = val & PLANE_CTL_TILED_MASK;
8377 switch (tiling) {
8378 case PLANE_CTL_TILED_LINEAR:
2f075565 8379 fb->modifier = DRM_FORMAT_MOD_LINEAR;
40f46283
DL
8380 break;
8381 case PLANE_CTL_TILED_X:
8382 plane_config->tiling = I915_TILING_X;
bae781b2 8383 fb->modifier = I915_FORMAT_MOD_X_TILED;
40f46283
DL
8384 break;
8385 case PLANE_CTL_TILED_Y:
bae781b2 8386 fb->modifier = I915_FORMAT_MOD_Y_TILED;
40f46283
DL
8387 break;
8388 case PLANE_CTL_TILED_YF:
bae781b2 8389 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
40f46283
DL
8390 break;
8391 default:
8392 MISSING_CASE(tiling);
8393 goto error;
8394 }
8395
bc8d7dff
DL
8396 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8397 plane_config->base = base;
8398
8399 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8400
8401 val = I915_READ(PLANE_SIZE(pipe, 0));
8402 fb->height = ((val >> 16) & 0xfff) + 1;
8403 fb->width = ((val >> 0) & 0x1fff) + 1;
8404
8405 val = I915_READ(PLANE_STRIDE(pipe, 0));
d88c4afd 8406 stride_mult = intel_fb_stride_alignment(fb, 0);
bc8d7dff
DL
8407 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8408
d88c4afd 8409 aligned_height = intel_fb_align_height(fb, 0, fb->height);
bc8d7dff 8410
f37b5c2b 8411 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL
8412
8413 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8414 pipe_name(pipe), fb->width, fb->height,
272725c7 8415 fb->format->cpp[0] * 8, base, fb->pitches[0],
bc8d7dff
DL
8416 plane_config->size);
8417
2d14030b 8418 plane_config->fb = intel_fb;
bc8d7dff
DL
8419 return;
8420
8421error:
d1a3a036 8422 kfree(intel_fb);
bc8d7dff
DL
8423}
8424
2fa2fe9a 8425static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8426 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV
8427{
8428 struct drm_device *dev = crtc->base.dev;
fac5e23e 8429 struct drm_i915_private *dev_priv = to_i915(dev);
2fa2fe9a
DV
8430 uint32_t tmp;
8431
8432 tmp = I915_READ(PF_CTL(crtc->pipe));
8433
8434 if (tmp & PF_ENABLE) {
fd4daa9c 8435 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV
8436 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8437 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV
8438
8439 /* We currently do not free assignements of panel fitters on
8440 * ivb/hsw (since we don't use the higher upscaling modes which
8441 * differentiates them) so just WARN about this case for now. */
5db94019 8442 if (IS_GEN7(dev_priv)) {
cb8b2a30
DV
8443 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8444 PF_PIPE_SEL_IVB(crtc->pipe));
8445 }
2fa2fe9a 8446 }
79e53945
JB
8447}
8448
5724dbd1
DL
8449static void
8450ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8451 struct intel_initial_plane_config *plane_config)
4c6baa59
JB
8452{
8453 struct drm_device *dev = crtc->base.dev;
fac5e23e 8454 struct drm_i915_private *dev_priv = to_i915(dev);
4c6baa59 8455 u32 val, base, offset;
aeee5a49 8456 int pipe = crtc->pipe;
4c6baa59 8457 int fourcc, pixel_format;
6761dd31 8458 unsigned int aligned_height;
b113d5ee 8459 struct drm_framebuffer *fb;
1b842c89 8460 struct intel_framebuffer *intel_fb;
4c6baa59 8461
42a7b088
DL
8462 val = I915_READ(DSPCNTR(pipe));
8463 if (!(val & DISPLAY_PLANE_ENABLE))
8464 return;
8465
d9806c9f 8466 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8467 if (!intel_fb) {
4c6baa59
JB
8468 DRM_DEBUG_KMS("failed to alloc fb\n");
8469 return;
8470 }
8471
1b842c89
DL
8472 fb = &intel_fb->base;
8473
d2e9f5fc
VS
8474 fb->dev = dev;
8475
6315b5d3 8476 if (INTEL_GEN(dev_priv) >= 4) {
18c5247e 8477 if (val & DISPPLANE_TILED) {
49af449b 8478 plane_config->tiling = I915_TILING_X;
bae781b2 8479 fb->modifier = I915_FORMAT_MOD_X_TILED;
18c5247e
DV
8480 }
8481 }
4c6baa59
JB
8482
8483 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 8484 fourcc = i9xx_format_to_fourcc(pixel_format);
2f3f4763 8485 fb->format = drm_format_info(fourcc);
4c6baa59 8486
aeee5a49 8487 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8652744b 8488 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
aeee5a49 8489 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 8490 } else {
49af449b 8491 if (plane_config->tiling)
aeee5a49 8492 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 8493 else
aeee5a49 8494 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB
8495 }
8496 plane_config->base = base;
8497
8498 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL
8499 fb->width = ((val >> 16) & 0xfff) + 1;
8500 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB
8501
8502 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8503 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 8504
d88c4afd 8505 aligned_height = intel_fb_align_height(fb, 0, fb->height);
4c6baa59 8506
f37b5c2b 8507 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 8508
2844a921
DL
8509 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8510 pipe_name(pipe), fb->width, fb->height,
272725c7 8511 fb->format->cpp[0] * 8, base, fb->pitches[0],
2844a921 8512 plane_config->size);
b113d5ee 8513
2d14030b 8514 plane_config->fb = intel_fb;
4c6baa59
JB
8515}
8516
0e8ffe1b 8517static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8518 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV
8519{
8520 struct drm_device *dev = crtc->base.dev;
fac5e23e 8521 struct drm_i915_private *dev_priv = to_i915(dev);
1729050e 8522 enum intel_display_power_domain power_domain;
0e8ffe1b 8523 uint32_t tmp;
1729050e 8524 bool ret;
0e8ffe1b 8525
1729050e
ID
8526 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8527 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
930e8c9e
PZ
8528 return false;
8529
e143a21c 8530 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8106ddbd 8531 pipe_config->shared_dpll = NULL;
eccb140b 8532
1729050e 8533 ret = false;
0e8ffe1b
DV
8534 tmp = I915_READ(PIPECONF(crtc->pipe));
8535 if (!(tmp & PIPECONF_ENABLE))
1729050e 8536 goto out;
0e8ffe1b 8537
42571aef
VS
8538 switch (tmp & PIPECONF_BPC_MASK) {
8539 case PIPECONF_6BPC:
8540 pipe_config->pipe_bpp = 18;
8541 break;
8542 case PIPECONF_8BPC:
8543 pipe_config->pipe_bpp = 24;
8544 break;
8545 case PIPECONF_10BPC:
8546 pipe_config->pipe_bpp = 30;
8547 break;
8548 case PIPECONF_12BPC:
8549 pipe_config->pipe_bpp = 36;
8550 break;
8551 default:
8552 break;
8553 }
8554
b5a9fa09
DV
8555 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8556 pipe_config->limited_color_range = true;
8557
ab9412ba 8558 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0 8559 struct intel_shared_dpll *pll;
8106ddbd 8560 enum intel_dpll_id pll_id;
66e985c0 8561
88adfff1
DV
8562 pipe_config->has_pch_encoder = true;
8563
627eb5a3
DV
8564 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8565 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8566 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV
8567
8568 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 8569
2d1fe073 8570 if (HAS_PCH_IBX(dev_priv)) {
d9a7bc67
ID
8571 /*
8572 * The pipe->pch transcoder and pch transcoder->pll
8573 * mapping is fixed.
8574 */
8106ddbd 8575 pll_id = (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV
8576 } else {
8577 tmp = I915_READ(PCH_DPLL_SEL);
8578 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8106ddbd 8579 pll_id = DPLL_ID_PCH_PLL_B;
c0d43d62 8580 else
8106ddbd 8581 pll_id= DPLL_ID_PCH_PLL_A;
c0d43d62 8582 }
66e985c0 8583
8106ddbd
ACO
8584 pipe_config->shared_dpll =
8585 intel_get_shared_dpll_by_id(dev_priv, pll_id);
8586 pll = pipe_config->shared_dpll;
66e985c0 8587
2edd6443
ACO
8588 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
8589 &pipe_config->dpll_hw_state));
c93f54cf
DV
8590
8591 tmp = pipe_config->dpll_hw_state.dpll;
8592 pipe_config->pixel_multiplier =
8593 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8594 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS
8595
8596 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV
8597 } else {
8598 pipe_config->pixel_multiplier = 1;
627eb5a3
DV
8599 }
8600
1bd1bd80 8601 intel_get_pipe_timings(crtc, pipe_config);
bc58be60 8602 intel_get_pipe_src_size(crtc, pipe_config);
1bd1bd80 8603
2fa2fe9a
DV
8604 ironlake_get_pfit_config(crtc, pipe_config);
8605
1729050e
ID
8606 ret = true;
8607
8608out:
8609 intel_display_power_put(dev_priv, power_domain);
8610
8611 return ret;
0e8ffe1b
DV
8612}
8613
be256dc7
PZ
8614static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8615{
91c8a326 8616 struct drm_device *dev = &dev_priv->drm;
be256dc7 8617 struct intel_crtc *crtc;
be256dc7 8618
d3fcc808 8619 for_each_intel_crtc(dev, crtc)
e2c719b7 8620 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ
8621 pipe_name(crtc->pipe));
8622
e2c719b7
RC
8623 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8624 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
01403de3
VS
8625 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8626 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
44cb734c 8627 I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n");
e2c719b7 8628 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 8629 "CPU PWM1 enabled\n");
772c2a51 8630 if (IS_HASWELL(dev_priv))
e2c719b7 8631 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 8632 "CPU PWM2 enabled\n");
e2c719b7 8633 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 8634 "PCH PWM1 enabled\n");
e2c719b7 8635 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 8636 "Utility pin enabled\n");
e2c719b7 8637 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 8638
9926ada1
PZ
8639 /*
8640 * In theory we can still leave IRQs enabled, as long as only the HPD
8641 * interrupts remain enabled. We used to check for that, but since it's
8642 * gen-specific and since we only disable LCPLL after we fully disable
8643 * the interrupts, the check below should be enough.
8644 */
e2c719b7 8645 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ
8646}
8647
9ccd5aeb
PZ
8648static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8649{
772c2a51 8650 if (IS_HASWELL(dev_priv))
9ccd5aeb
PZ
8651 return I915_READ(D_COMP_HSW);
8652 else
8653 return I915_READ(D_COMP_BDW);
8654}
8655
3c4c9b81
PZ
8656static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8657{
772c2a51 8658 if (IS_HASWELL(dev_priv)) {
3c4c9b81
PZ
8659 mutex_lock(&dev_priv->rps.hw_lock);
8660 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8661 val))
79cf219a 8662 DRM_DEBUG_KMS("Failed to write to D_COMP\n");
3c4c9b81
PZ
8663 mutex_unlock(&dev_priv->rps.hw_lock);
8664 } else {
9ccd5aeb
PZ
8665 I915_WRITE(D_COMP_BDW, val);
8666 POSTING_READ(D_COMP_BDW);
3c4c9b81 8667 }
be256dc7
PZ
8668}
8669
8670/*
8671 * This function implements pieces of two sequences from BSpec:
8672 * - Sequence for display software to disable LCPLL
8673 * - Sequence for display software to allow package C8+
8674 * The steps implemented here are just the steps that actually touch the LCPLL
8675 * register. Callers should take care of disabling all the display engine
8676 * functions, doing the mode unset, fixing interrupts, etc.
8677 */
6ff58d53
PZ
8678static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8679 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ
8680{
8681 uint32_t val;
8682
8683 assert_can_disable_lcpll(dev_priv);
8684
8685 val = I915_READ(LCPLL_CTL);
8686
8687 if (switch_to_fclk) {
8688 val |= LCPLL_CD_SOURCE_FCLK;
8689 I915_WRITE(LCPLL_CTL, val);
8690
f53dd63f
ID
8691 if (wait_for_us(I915_READ(LCPLL_CTL) &
8692 LCPLL_CD_SOURCE_FCLK_DONE, 1))
be256dc7
PZ
8693 DRM_ERROR("Switching to FCLK failed\n");
8694
8695 val = I915_READ(LCPLL_CTL);
8696 }
8697
8698 val |= LCPLL_PLL_DISABLE;
8699 I915_WRITE(LCPLL_CTL, val);
8700 POSTING_READ(LCPLL_CTL);
8701
24d8441d 8702 if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1))
be256dc7
PZ
8703 DRM_ERROR("LCPLL still locked\n");
8704
9ccd5aeb 8705 val = hsw_read_dcomp(dev_priv);
be256dc7 8706 val |= D_COMP_COMP_DISABLE;
3c4c9b81 8707 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ
8708 ndelay(100);
8709
9ccd5aeb
PZ
8710 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8711 1))
be256dc7
PZ
8712 DRM_ERROR("D_COMP RCOMP still in progress\n");
8713
8714 if (allow_power_down) {
8715 val = I915_READ(LCPLL_CTL);
8716 val |= LCPLL_POWER_DOWN_ALLOW;
8717 I915_WRITE(LCPLL_CTL, val);
8718 POSTING_READ(LCPLL_CTL);
8719 }
8720}
8721
8722/*
8723 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8724 * source.
8725 */
6ff58d53 8726static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ
8727{
8728 uint32_t val;
8729
8730 val = I915_READ(LCPLL_CTL);
8731
8732 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8733 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8734 return;
8735
a8a8bd54
PZ
8736 /*
8737 * Make sure we're not on PC8 state before disabling PC8, otherwise
8738 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 8739 */
59bad947 8740 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 8741
be256dc7
PZ
8742 if (val & LCPLL_POWER_DOWN_ALLOW) {
8743 val &= ~LCPLL_POWER_DOWN_ALLOW;
8744 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 8745 POSTING_READ(LCPLL_CTL);
be256dc7
PZ
8746 }
8747
9ccd5aeb 8748 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ
8749 val |= D_COMP_COMP_FORCE;
8750 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 8751 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ
8752
8753 val = I915_READ(LCPLL_CTL);
8754 val &= ~LCPLL_PLL_DISABLE;
8755 I915_WRITE(LCPLL_CTL, val);
8756
93220c08
CW
8757 if (intel_wait_for_register(dev_priv,
8758 LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK,
8759 5))
be256dc7
PZ
8760 DRM_ERROR("LCPLL not locked yet\n");
8761
8762 if (val & LCPLL_CD_SOURCE_FCLK) {
8763 val = I915_READ(LCPLL_CTL);
8764 val &= ~LCPLL_CD_SOURCE_FCLK;
8765 I915_WRITE(LCPLL_CTL, val);
8766
f53dd63f
ID
8767 if (wait_for_us((I915_READ(LCPLL_CTL) &
8768 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
be256dc7
PZ
8769 DRM_ERROR("Switching back to LCPLL failed\n");
8770 }
215733fa 8771
59bad947 8772 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4c75b940 8773 intel_update_cdclk(dev_priv);
be256dc7
PZ
8774}
8775
765dab67
PZ
8776/*
8777 * Package states C8 and deeper are really deep PC states that can only be
8778 * reached when all the devices on the system allow it, so even if the graphics
8779 * device allows PC8+, it doesn't mean the system will actually get to these
8780 * states. Our driver only allows PC8+ when going into runtime PM.
8781 *
8782 * The requirements for PC8+ are that all the outputs are disabled, the power
8783 * well is disabled and most interrupts are disabled, and these are also
8784 * requirements for runtime PM. When these conditions are met, we manually do
8785 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8786 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8787 * hang the machine.
8788 *
8789 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8790 * the state of some registers, so when we come back from PC8+ we need to
8791 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8792 * need to take care of the registers kept by RC6. Notice that this happens even
8793 * if we don't put the device in PCI D3 state (which is what currently happens
8794 * because of the runtime PM support).
8795 *
8796 * For more, read "Display Sequences for Package C8" on the hardware
8797 * documentation.
8798 */
a14cb6fc 8799void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 8800{
c67a470b
PZ
8801 uint32_t val;
8802
c67a470b
PZ
8803 DRM_DEBUG_KMS("Enabling package C8+\n");
8804
4f8036a2 8805 if (HAS_PCH_LPT_LP(dev_priv)) {
c67a470b
PZ
8806 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8807 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8808 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8809 }
8810
c39055b0 8811 lpt_disable_clkout_dp(dev_priv);
c67a470b
PZ
8812 hsw_disable_lcpll(dev_priv, true, true);
8813}
8814
a14cb6fc 8815void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b 8816{
c67a470b
PZ
8817 uint32_t val;
8818
c67a470b
PZ
8819 DRM_DEBUG_KMS("Disabling package C8+\n");
8820
8821 hsw_restore_lcpll(dev_priv);
c39055b0 8822 lpt_init_pch_refclk(dev_priv);
c67a470b 8823
4f8036a2 8824 if (HAS_PCH_LPT_LP(dev_priv)) {
c67a470b
PZ
8825 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8826 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8827 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8828 }
c67a470b
PZ
8829}
8830
190f68c5
ACO
8831static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8832 struct intel_crtc_state *crtc_state)
09b4ddf9 8833{
d7edc4e5 8834 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) {
44a126ba
PZ
8835 struct intel_encoder *encoder =
8836 intel_ddi_get_crtc_new_encoder(crtc_state);
8837
8838 if (!intel_get_shared_dpll(crtc, crtc_state, encoder)) {
8839 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8840 pipe_name(crtc->pipe));
af3997b5 8841 return -EINVAL;
44a126ba 8842 }
af3997b5 8843 }
716c2e55 8844
c7653199 8845 crtc->lowfreq_avail = false;
644cef34 8846
c8f7a0db 8847 return 0;
79e53945
JB
8848}
8849
3760b59c
S
8850static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
8851 enum port port,
8852 struct intel_crtc_state *pipe_config)
8853{
8106ddbd
ACO
8854 enum intel_dpll_id id;
8855
3760b59c
S
8856 switch (port) {
8857 case PORT_A:
08250c4b 8858 id = DPLL_ID_SKL_DPLL0;
3760b59c
S
8859 break;
8860 case PORT_B:
08250c4b 8861 id = DPLL_ID_SKL_DPLL1;
3760b59c
S
8862 break;
8863 case PORT_C:
08250c4b 8864 id = DPLL_ID_SKL_DPLL2;
3760b59c
S
8865 break;
8866 default:
8867 DRM_ERROR("Incorrect port type\n");
8106ddbd 8868 return;
3760b59c 8869 }
8106ddbd
ACO
8870
8871 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
3760b59c
S
8872}
8873
96b7dfb7
S
8874static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8875 enum port port,
5cec258b 8876 struct intel_crtc_state *pipe_config)
96b7dfb7 8877{
8106ddbd 8878 enum intel_dpll_id id;
a3c988ea 8879 u32 temp;
96b7dfb7
S
8880
8881 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
c856052a 8882 id = temp >> (port * 3 + 1);
96b7dfb7 8883
c856052a 8884 if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3))
8106ddbd 8885 return;
8106ddbd
ACO
8886
8887 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
96b7dfb7
S
8888}
8889
7d2c8175
DL
8890static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8891 enum port port,
5cec258b 8892 struct intel_crtc_state *pipe_config)
7d2c8175 8893{
8106ddbd 8894 enum intel_dpll_id id;
c856052a 8895 uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8106ddbd 8896
c856052a 8897 switch (ddi_pll_sel) {
7d2c8175 8898 case PORT_CLK_SEL_WRPLL1:
8106ddbd 8899 id = DPLL_ID_WRPLL1;
7d2c8175
DL
8900 break;
8901 case PORT_CLK_SEL_WRPLL2:
8106ddbd 8902 id = DPLL_ID_WRPLL2;
7d2c8175 8903 break;
00490c22 8904 case PORT_CLK_SEL_SPLL:
8106ddbd 8905 id = DPLL_ID_SPLL;
79bd23da 8906 break;
9d16da65
ACO
8907 case PORT_CLK_SEL_LCPLL_810:
8908 id = DPLL_ID_LCPLL_810;
8909 break;
8910 case PORT_CLK_SEL_LCPLL_1350:
8911 id = DPLL_ID_LCPLL_1350;
8912 break;
8913 case PORT_CLK_SEL_LCPLL_2700:
8914 id = DPLL_ID_LCPLL_2700;
8915 break;
8106ddbd 8916 default:
c856052a 8917 MISSING_CASE(ddi_pll_sel);
8106ddbd
ACO
8918 /* fall through */
8919 case PORT_CLK_SEL_NONE:
8106ddbd 8920 return;
7d2c8175 8921 }
8106ddbd
ACO
8922
8923 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
7d2c8175
DL
8924}
8925
cf30429e
JN
8926static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
8927 struct intel_crtc_state *pipe_config,
d8fc70b7 8928 u64 *power_domain_mask)
cf30429e
JN
8929{
8930 struct drm_device *dev = crtc->base.dev;
fac5e23e 8931 struct drm_i915_private *dev_priv = to_i915(dev);
cf30429e
JN
8932 enum intel_display_power_domain power_domain;
8933 u32 tmp;
8934
d9a7bc67
ID
8935 /*
8936 * The pipe->transcoder mapping is fixed with the exception of the eDP
8937 * transcoder handled below.
8938 */
cf30429e
JN
8939 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8940
8941 /*
8942 * XXX: Do intel_display_power_get_if_enabled before reading this (for
8943 * consistency and less surprising code; it's in always on power).
8944 */
8945 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8946 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8947 enum pipe trans_edp_pipe;
8948 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8949 default:
8950 WARN(1, "unknown pipe linked to edp transcoder\n");
8951 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8952 case TRANS_DDI_EDP_INPUT_A_ON:
8953 trans_edp_pipe = PIPE_A;
8954 break;
8955 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8956 trans_edp_pipe = PIPE_B;
8957 break;
8958 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8959 trans_edp_pipe = PIPE_C;
8960 break;
8961 }
8962
8963 if (trans_edp_pipe == crtc->pipe)
8964 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8965 }
8966
8967 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
8968 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8969 return false;
d8fc70b7 8970 *power_domain_mask |= BIT_ULL(power_domain);
cf30429e
JN
8971
8972 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8973
8974 return tmp & PIPECONF_ENABLE;
8975}
8976
4d1de975
JN
8977static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
8978 struct intel_crtc_state *pipe_config,
d8fc70b7 8979 u64 *power_domain_mask)
4d1de975
JN
8980{
8981 struct drm_device *dev = crtc->base.dev;
fac5e23e 8982 struct drm_i915_private *dev_priv = to_i915(dev);
4d1de975
JN
8983 enum intel_display_power_domain power_domain;
8984 enum port port;
8985 enum transcoder cpu_transcoder;
8986 u32 tmp;
8987
4d1de975
JN
8988 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
8989 if (port == PORT_A)
8990 cpu_transcoder = TRANSCODER_DSI_A;
8991 else
8992 cpu_transcoder = TRANSCODER_DSI_C;
8993
8994 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
8995 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8996 continue;
d8fc70b7 8997 *power_domain_mask |= BIT_ULL(power_domain);
4d1de975 8998
db18b6a6
ID
8999 /*
9000 * The PLL needs to be enabled with a valid divider
9001 * configuration, otherwise accessing DSI registers will hang
9002 * the machine. See BSpec North Display Engine
9003 * registers/MIPI[BXT]. We can break out here early, since we
9004 * need the same DSI PLL to be enabled for both DSI ports.
9005 */
9006 if (!intel_dsi_pll_is_enabled(dev_priv))
9007 break;
9008
4d1de975
JN
9009 /* XXX: this works for video mode only */
9010 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9011 if (!(tmp & DPI_ENABLE))
9012 continue;
9013
9014 tmp = I915_READ(MIPI_CTRL(port));
9015 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9016 continue;
9017
9018 pipe_config->cpu_transcoder = cpu_transcoder;
4d1de975
JN
9019 break;
9020 }
9021
d7edc4e5 9022 return transcoder_is_dsi(pipe_config->cpu_transcoder);
4d1de975
JN
9023}
9024
26804afd 9025static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9026 struct intel_crtc_state *pipe_config)
26804afd 9027{
6315b5d3 9028 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
d452c5b6 9029 struct intel_shared_dpll *pll;
26804afd
DV
9030 enum port port;
9031 uint32_t tmp;
9032
9033 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9034
9035 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9036
b976dc53 9037 if (IS_GEN9_BC(dev_priv))
96b7dfb7 9038 skylake_get_ddi_pll(dev_priv, port, pipe_config);
cc3f90f0 9039 else if (IS_GEN9_LP(dev_priv))
3760b59c 9040 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S
9041 else
9042 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9043
8106ddbd
ACO
9044 pll = pipe_config->shared_dpll;
9045 if (pll) {
2edd6443
ACO
9046 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9047 &pipe_config->dpll_hw_state));
d452c5b6
DV
9048 }
9049
26804afd
DV
9050 /*
9051 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9052 * DDI E. So just check whether this pipe is wired to DDI E and whether
9053 * the PCH transcoder is on.
9054 */
6315b5d3 9055 if (INTEL_GEN(dev_priv) < 9 &&
ca370455 9056 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV
9057 pipe_config->has_pch_encoder = true;
9058
9059 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9060 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9061 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9062
9063 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9064 }
9065}
9066
0e8ffe1b 9067static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9068 struct intel_crtc_state *pipe_config)
0e8ffe1b 9069{
6315b5d3 9070 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1729050e 9071 enum intel_display_power_domain power_domain;
d8fc70b7 9072 u64 power_domain_mask;
cf30429e 9073 bool active;
0e8ffe1b 9074
1729050e
ID
9075 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9076 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
b5482bd0 9077 return false;
d8fc70b7 9078 power_domain_mask = BIT_ULL(power_domain);
1729050e 9079
8106ddbd 9080 pipe_config->shared_dpll = NULL;
c0d43d62 9081
cf30429e 9082 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
eccb140b 9083
cc3f90f0 9084 if (IS_GEN9_LP(dev_priv) &&
d7edc4e5
VS
9085 bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) {
9086 WARN_ON(active);
9087 active = true;
4d1de975
JN
9088 }
9089
cf30429e 9090 if (!active)
1729050e 9091 goto out;
0e8ffe1b 9092
d7edc4e5 9093 if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
4d1de975
JN
9094 haswell_get_ddi_port_state(crtc, pipe_config);
9095 intel_get_pipe_timings(crtc, pipe_config);
9096 }
627eb5a3 9097
bc58be60 9098 intel_get_pipe_src_size(crtc, pipe_config);
1bd1bd80 9099
05dc698c
LL
9100 pipe_config->gamma_mode =
9101 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9102
6315b5d3 9103 if (INTEL_GEN(dev_priv) >= 9) {
1c74eeaf 9104 intel_crtc_init_scalers(crtc, pipe_config);
a1b2278e 9105
af99ceda
CK
9106 pipe_config->scaler_state.scaler_id = -1;
9107 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9108 }
9109
1729050e
ID
9110 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9111 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
d8fc70b7 9112 power_domain_mask |= BIT_ULL(power_domain);
6315b5d3 9113 if (INTEL_GEN(dev_priv) >= 9)
bd2e244f 9114 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9115 else
1c132b44 9116 ironlake_get_pfit_config(crtc, pipe_config);
bd2e244f 9117 }
88adfff1 9118
772c2a51 9119 if (IS_HASWELL(dev_priv))
e59150dc
JB
9120 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9121 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9122
4d1de975
JN
9123 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
9124 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
ebb69c95
CT
9125 pipe_config->pixel_multiplier =
9126 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9127 } else {
9128 pipe_config->pixel_multiplier = 1;
9129 }
6c49f241 9130
1729050e
ID
9131out:
9132 for_each_power_domain(power_domain, power_domain_mask)
9133 intel_display_power_put(dev_priv, power_domain);
9134
cf30429e 9135 return active;
0e8ffe1b
DV
9136}
9137
292889e1
VS
9138static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
9139 const struct intel_plane_state *plane_state)
9140{
9141 unsigned int width = plane_state->base.crtc_w;
9142 unsigned int stride = roundup_pow_of_two(width) * 4;
9143
9144 switch (stride) {
9145 default:
9146 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9147 width, stride);
9148 stride = 256;
9149 /* fallthrough */
9150 case 256:
9151 case 512:
9152 case 1024:
9153 case 2048:
9154 break;
9155 }
9156
9157 return CURSOR_ENABLE |
9158 CURSOR_GAMMA_ENABLE |
9159 CURSOR_FORMAT_ARGB |
9160 CURSOR_STRIDE(stride);
9161}
9162
55a08b3f
ML
9163static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
9164 const struct intel_plane_state *plane_state)
560b85bb
CW
9165{
9166 struct drm_device *dev = crtc->dev;
fac5e23e 9167 struct drm_i915_private *dev_priv = to_i915(dev);
560b85bb 9168 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9169 uint32_t cntl = 0, size = 0;
560b85bb 9170
936e71e3 9171 if (plane_state && plane_state->base.visible) {
55a08b3f
ML
9172 unsigned int width = plane_state->base.crtc_w;
9173 unsigned int height = plane_state->base.crtc_h;
dc41c154 9174
a0864d59 9175 cntl = plane_state->ctl;
dc41c154 9176 size = (height << 12) | width;
4b0e333e 9177 }
560b85bb 9178
dc41c154
VS
9179 if (intel_crtc->cursor_cntl != 0 &&
9180 (intel_crtc->cursor_base != base ||
9181 intel_crtc->cursor_size != size ||
9182 intel_crtc->cursor_cntl != cntl)) {
9183 /* On these chipsets we can only modify the base/size/stride
9184 * whilst the cursor is disabled.
9185 */
dd584fc0
VS
9186 I915_WRITE_FW(CURCNTR(PIPE_A), 0);
9187 POSTING_READ_FW(CURCNTR(PIPE_A));
dc41c154 9188 intel_crtc->cursor_cntl = 0;
4b0e333e 9189 }
560b85bb 9190
99d1f387 9191 if (intel_crtc->cursor_base != base) {
dd584fc0 9192 I915_WRITE_FW(CURBASE(PIPE_A), base);
99d1f387
VS
9193 intel_crtc->cursor_base = base;
9194 }
4726e0b0 9195
dc41c154 9196 if (intel_crtc->cursor_size != size) {
dd584fc0 9197 I915_WRITE_FW(CURSIZE, size);
dc41c154 9198 intel_crtc->cursor_size = size;
4b0e333e 9199 }
560b85bb 9200
4b0e333e 9201 if (intel_crtc->cursor_cntl != cntl) {
dd584fc0
VS
9202 I915_WRITE_FW(CURCNTR(PIPE_A), cntl);
9203 POSTING_READ_FW(CURCNTR(PIPE_A));
4b0e333e 9204 intel_crtc->cursor_cntl = cntl;
560b85bb 9205 }
560b85bb
CW
9206}
9207
292889e1
VS
9208static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
9209 const struct intel_plane_state *plane_state)
9210{
9211 struct drm_i915_private *dev_priv =
9212 to_i915(plane_state->base.plane->dev);
9213 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
9214 enum pipe pipe = crtc->pipe;
9215 u32 cntl;
9216
9217 cntl = MCURSOR_GAMMA_ENABLE;
9218
9219 if (HAS_DDI(dev_priv))
9220 cntl |= CURSOR_PIPE_CSC_ENABLE;
9221
9222 cntl |= pipe << 28; /* Connect to correct pipe */
9223
9224 switch (plane_state->base.crtc_w) {
9225 case 64:
9226 cntl |= CURSOR_MODE_64_ARGB_AX;
9227 break;
9228 case 128:
9229 cntl |= CURSOR_MODE_128_ARGB_AX;
9230 break;
9231 case 256:
9232 cntl |= CURSOR_MODE_256_ARGB_AX;
9233 break;
9234 default:
9235 MISSING_CASE(plane_state->base.crtc_w);
9236 return 0;
9237 }
9238
9239 if (plane_state->base.rotation & DRM_ROTATE_180)
9240 cntl |= CURSOR_ROTATE_180;
9241
9242 return cntl;
9243}
9244
55a08b3f
ML
9245static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
9246 const struct intel_plane_state *plane_state)
65a21cd6
JB
9247{
9248 struct drm_device *dev = crtc->dev;
fac5e23e 9249 struct drm_i915_private *dev_priv = to_i915(dev);
65a21cd6
JB
9250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9251 int pipe = intel_crtc->pipe;
663f3122 9252 uint32_t cntl = 0;
4b0e333e 9253
292889e1 9254 if (plane_state && plane_state->base.visible)
a0864d59 9255 cntl = plane_state->ctl;
4398ad45 9256
4b0e333e 9257 if (intel_crtc->cursor_cntl != cntl) {
dd584fc0
VS
9258 I915_WRITE_FW(CURCNTR(pipe), cntl);
9259 POSTING_READ_FW(CURCNTR(pipe));
4b0e333e 9260 intel_crtc->cursor_cntl = cntl;
65a21cd6 9261 }
4b0e333e 9262
65a21cd6 9263 /* and commit changes on next vblank */
dd584fc0
VS
9264 I915_WRITE_FW(CURBASE(pipe), base);
9265 POSTING_READ_FW(CURBASE(pipe));
99d1f387
VS
9266
9267 intel_crtc->cursor_base = base;
65a21cd6
JB
9268}
9269
cda4b7d3 9270/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f 9271static void intel_crtc_update_cursor(struct drm_crtc *crtc,
55a08b3f 9272 const struct intel_plane_state *plane_state)
cda4b7d3
CW
9273{
9274 struct drm_device *dev = crtc->dev;
fac5e23e 9275 struct drm_i915_private *dev_priv = to_i915(dev);
cda4b7d3
CW
9276 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9277 int pipe = intel_crtc->pipe;
55a08b3f 9278 u32 base = intel_crtc->cursor_addr;
dd584fc0 9279 unsigned long irqflags;
55a08b3f 9280 u32 pos = 0;
cda4b7d3 9281
55a08b3f
ML
9282 if (plane_state) {
9283 int x = plane_state->base.crtc_x;
9284 int y = plane_state->base.crtc_y;
cda4b7d3 9285
55a08b3f
ML
9286 if (x < 0) {
9287 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9288 x = -x;
9289 }
9290 pos |= x << CURSOR_X_SHIFT;
cda4b7d3 9291
55a08b3f
ML
9292 if (y < 0) {
9293 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9294 y = -y;
9295 }
9296 pos |= y << CURSOR_Y_SHIFT;
9297
9298 /* ILK+ do this automagically */
49cff963 9299 if (HAS_GMCH_DISPLAY(dev_priv) &&
f22aa143 9300 plane_state->base.rotation & DRM_ROTATE_180) {
55a08b3f
ML
9301 base += (plane_state->base.crtc_h *
9302 plane_state->base.crtc_w - 1) * 4;
9303 }
cda4b7d3 9304 }
cda4b7d3 9305
dd584fc0
VS
9306 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
9307
9308 I915_WRITE_FW(CURPOS(pipe), pos);
5efb3e28 9309
2a307c2e 9310 if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
a0864d59 9311 i845_update_cursor(crtc, base, plane_state);
5efb3e28 9312 else
a0864d59 9313 i9xx_update_cursor(crtc, base, plane_state);
dd584fc0
VS
9314
9315 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
cda4b7d3
CW
9316}
9317
50a0bc90 9318static bool cursor_size_ok(struct drm_i915_private *dev_priv,
dc41c154
VS
9319 uint32_t width, uint32_t height)
9320{
9321 if (width == 0 || height == 0)
9322 return false;
9323
9324 /*
9325 * 845g/865g are special in that they are only limited by
9326 * the width of their cursors, the height is arbitrary up to
9327 * the precision of the register. Everything else requires
9328 * square cursors, limited to a few power-of-two sizes.
9329 */
2a307c2e 9330 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
dc41c154
VS
9331 if ((width & 63) != 0)
9332 return false;
9333
2a307c2e 9334 if (width > (IS_I845G(dev_priv) ? 64 : 512))
dc41c154
VS
9335 return false;
9336
9337 if (height > 1023)
9338 return false;
9339 } else {
9340 switch (width | height) {
9341 case 256:
9342 case 128:
50a0bc90 9343 if (IS_GEN2(dev_priv))
dc41c154
VS
9344 return false;
9345 case 64:
9346 break;
9347 default:
9348 return false;
9349 }
9350 }
9351
9352 return true;
9353}
9354
79e53945
JB
9355/* VESA 640x480x72Hz mode to set on the pipe */
9356static struct drm_display_mode load_detect_mode = {
9357 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9358 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9359};
9360
a8bb6818 9361struct drm_framebuffer *
24dbf51a
CW
9362intel_framebuffer_create(struct drm_i915_gem_object *obj,
9363 struct drm_mode_fb_cmd2 *mode_cmd)
d2dff872
CW
9364{
9365 struct intel_framebuffer *intel_fb;
9366 int ret;
9367
9368 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
dcb1394e 9369 if (!intel_fb)
d2dff872 9370 return ERR_PTR(-ENOMEM);
d2dff872 9371
24dbf51a 9372 ret = intel_framebuffer_init(intel_fb, obj, mode_cmd);
dd4916c5
DV
9373 if (ret)
9374 goto err;
d2dff872
CW
9375
9376 return &intel_fb->base;
dcb1394e 9377
dd4916c5 9378err:
dd4916c5 9379 kfree(intel_fb);
dd4916c5 9380 return ERR_PTR(ret);
d2dff872
CW
9381}
9382
9383static u32
9384intel_framebuffer_pitch_for_width(int width, int bpp)
9385{
9386 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9387 return ALIGN(pitch, 64);
9388}
9389
9390static u32
9391intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9392{
9393 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 9394 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW
9395}
9396
9397static struct drm_framebuffer *
9398intel_framebuffer_create_for_mode(struct drm_device *dev,
9399 struct drm_display_mode *mode,
9400 int depth, int bpp)
9401{
dcb1394e 9402 struct drm_framebuffer *fb;
d2dff872 9403 struct drm_i915_gem_object *obj;
0fed39bd 9404 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872 9405
12d79d78 9406 obj = i915_gem_object_create(to_i915(dev),
d2dff872 9407 intel_framebuffer_size_for_mode(mode, bpp));
fe3db79b
CW
9408 if (IS_ERR(obj))
9409 return ERR_CAST(obj);
d2dff872
CW
9410
9411 mode_cmd.width = mode->hdisplay;
9412 mode_cmd.height = mode->vdisplay;
308e5bcb
JB
9413 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9414 bpp);
5ca0c34a 9415 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872 9416
24dbf51a 9417 fb = intel_framebuffer_create(obj, &mode_cmd);
dcb1394e 9418 if (IS_ERR(fb))
f0cd5182 9419 i915_gem_object_put(obj);
dcb1394e
LW
9420
9421 return fb;
d2dff872
CW
9422}
9423
9424static struct drm_framebuffer *
9425mode_fits_in_fbdev(struct drm_device *dev,
9426 struct drm_display_mode *mode)
9427{
0695726e 9428#ifdef CONFIG_DRM_FBDEV_EMULATION
fac5e23e 9429 struct drm_i915_private *dev_priv = to_i915(dev);
d2dff872
CW
9430 struct drm_i915_gem_object *obj;
9431 struct drm_framebuffer *fb;
9432
4c0e5528 9433 if (!dev_priv->fbdev)
d2dff872
CW
9434 return NULL;
9435
4c0e5528 9436 if (!dev_priv->fbdev->fb)
d2dff872
CW
9437 return NULL;
9438
4c0e5528
DV
9439 obj = dev_priv->fbdev->fb->obj;
9440 BUG_ON(!obj);
9441
8bcd4553 9442 fb = &dev_priv->fbdev->fb->base;
01f2c773 9443 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
272725c7 9444 fb->format->cpp[0] * 8))
d2dff872
CW
9445 return NULL;
9446
01f2c773 9447 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW
9448 return NULL;
9449
edde3617 9450 drm_framebuffer_reference(fb);
d2dff872 9451 return fb;
4520f53a
DV
9452#else
9453 return NULL;
9454#endif
d2dff872
CW
9455}
9456
d3a40d1b
ACO
9457static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9458 struct drm_crtc *crtc,
9459 struct drm_display_mode *mode,
9460 struct drm_framebuffer *fb,
9461 int x, int y)
9462{
9463 struct drm_plane_state *plane_state;
9464 int hdisplay, vdisplay;
9465 int ret;
9466
9467 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9468 if (IS_ERR(plane_state))
9469 return PTR_ERR(plane_state);
9470
9471 if (mode)
196cd5d3 9472 drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay);
d3a40d1b
ACO
9473 else
9474 hdisplay = vdisplay = 0;
9475
9476 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9477 if (ret)
9478 return ret;
9479 drm_atomic_set_fb_for_plane(plane_state, fb);
9480 plane_state->crtc_x = 0;
9481 plane_state->crtc_y = 0;
9482 plane_state->crtc_w = hdisplay;
9483 plane_state->crtc_h = vdisplay;
9484 plane_state->src_x = x << 16;
9485 plane_state->src_y = y << 16;
9486 plane_state->src_w = hdisplay << 16;
9487 plane_state->src_h = vdisplay << 16;
9488
9489 return 0;
9490}
9491
6c5ed5ae
ML
9492int intel_get_load_detect_pipe(struct drm_connector *connector,
9493 struct drm_display_mode *mode,
9494 struct intel_load_detect_pipe *old,
9495 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB
9496{
9497 struct intel_crtc *intel_crtc;
d2434ab7
DV
9498 struct intel_encoder *intel_encoder =
9499 intel_attached_encoder(connector);
79e53945 9500 struct drm_crtc *possible_crtc;
4ef69c7a 9501 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB
9502 struct drm_crtc *crtc = NULL;
9503 struct drm_device *dev = encoder->dev;
0f0f74bc 9504 struct drm_i915_private *dev_priv = to_i915(dev);
94352cf9 9505 struct drm_framebuffer *fb;
51fd371b 9506 struct drm_mode_config *config = &dev->mode_config;
edde3617 9507 struct drm_atomic_state *state = NULL, *restore_state = NULL;
944b0c76 9508 struct drm_connector_state *connector_state;
4be07317 9509 struct intel_crtc_state *crtc_state;
51fd371b 9510 int ret, i = -1;
79e53945 9511
d2dff872 9512 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9513 connector->base.id, connector->name,
8e329a03 9514 encoder->base.id, encoder->name);
d2dff872 9515
edde3617
ML
9516 old->restore_state = NULL;
9517
6c5ed5ae 9518 WARN_ON(!drm_modeset_is_locked(&config->connection_mutex));
6e9f798d 9519
79e53945
JB
9520 /*
9521 * Algorithm gets a little messy:
7a5e4805 9522 *
79e53945
JB
9523 * - if the connector already has an assigned crtc, use it (but make
9524 * sure it's on first)
7a5e4805 9525 *
79e53945
JB
9526 * - try to find the first unused crtc that can drive this connector,
9527 * and use that if we find one
79e53945
JB
9528 */
9529
9530 /* See if we already have a CRTC for this connector */
edde3617
ML
9531 if (connector->state->crtc) {
9532 crtc = connector->state->crtc;
8261b191 9533
51fd371b 9534 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de 9535 if (ret)
ad3c558f 9536 goto fail;
8261b191
CW
9537
9538 /* Make sure the crtc and connector are running */
edde3617 9539 goto found;
79e53945
JB
9540 }
9541
9542 /* Find an unused one (if possible) */
70e1e0ec 9543 for_each_crtc(dev, possible_crtc) {
79e53945
JB
9544 i++;
9545 if (!(encoder->possible_crtcs & (1 << i)))
9546 continue;
edde3617
ML
9547
9548 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
9549 if (ret)
9550 goto fail;
9551
9552 if (possible_crtc->state->enable) {
9553 drm_modeset_unlock(&possible_crtc->mutex);
a459249c 9554 continue;
edde3617 9555 }
a459249c
VS
9556
9557 crtc = possible_crtc;
9558 break;
79e53945
JB
9559 }
9560
9561 /*
9562 * If we didn't find an unused CRTC, don't use any.
9563 */
9564 if (!crtc) {
7173188d 9565 DRM_DEBUG_KMS("no pipe available for load-detect\n");
f4bf77b4 9566 ret = -ENODEV;
ad3c558f 9567 goto fail;
79e53945
JB
9568 }
9569
edde3617
ML
9570found:
9571 intel_crtc = to_intel_crtc(crtc);
9572
4d02e2de
DV
9573 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9574 if (ret)
ad3c558f 9575 goto fail;
79e53945 9576
83a57153 9577 state = drm_atomic_state_alloc(dev);
edde3617
ML
9578 restore_state = drm_atomic_state_alloc(dev);
9579 if (!state || !restore_state) {
9580 ret = -ENOMEM;
9581 goto fail;
9582 }
83a57153
ACO
9583
9584 state->acquire_ctx = ctx;
edde3617 9585 restore_state->acquire_ctx = ctx;
83a57153 9586
944b0c76
ACO
9587 connector_state = drm_atomic_get_connector_state(state, connector);
9588 if (IS_ERR(connector_state)) {
9589 ret = PTR_ERR(connector_state);
9590 goto fail;
9591 }
9592
edde3617
ML
9593 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
9594 if (ret)
9595 goto fail;
944b0c76 9596
4be07317
ACO
9597 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9598 if (IS_ERR(crtc_state)) {
9599 ret = PTR_ERR(crtc_state);
9600 goto fail;
9601 }
9602
49d6fa21 9603 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 9604
6492711d
CW
9605 if (!mode)
9606 mode = &load_detect_mode;
79e53945 9607
d2dff872
CW
9608 /* We need a framebuffer large enough to accommodate all accesses
9609 * that the plane may generate whilst we perform load detection.
9610 * We can not rely on the fbcon either being present (we get called
9611 * during its initialisation to detect all boot displays, or it may
9612 * not even exist) or that it is large enough to satisfy the
9613 * requested mode.
9614 */
94352cf9
DV
9615 fb = mode_fits_in_fbdev(dev, mode);
9616 if (fb == NULL) {
d2dff872 9617 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9 9618 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
d2dff872
CW
9619 } else
9620 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 9621 if (IS_ERR(fb)) {
d2dff872 9622 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
f4bf77b4 9623 ret = PTR_ERR(fb);
412b61d8 9624 goto fail;
79e53945 9625 }
79e53945 9626
d3a40d1b
ACO
9627 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9628 if (ret)
9629 goto fail;
9630
edde3617
ML
9631 drm_framebuffer_unreference(fb);
9632
9633 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
9634 if (ret)
9635 goto fail;
9636
9637 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
9638 if (!ret)
9639 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
9640 if (!ret)
9641 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
9642 if (ret) {
9643 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
9644 goto fail;
9645 }
8c7b5ccb 9646
3ba86073
ML
9647 ret = drm_atomic_commit(state);
9648 if (ret) {
6492711d 9649 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
412b61d8 9650 goto fail;
79e53945 9651 }
edde3617
ML
9652
9653 old->restore_state = restore_state;
7abbd11f 9654 drm_atomic_state_put(state);
7173188d 9655
79e53945 9656 /* let the connector get through one full cycle before testing */
0f0f74bc 9657 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
7173188d 9658 return true;
412b61d8 9659
ad3c558f 9660fail:
7fb71c8f
CW
9661 if (state) {
9662 drm_atomic_state_put(state);
9663 state = NULL;
9664 }
9665 if (restore_state) {
9666 drm_atomic_state_put(restore_state);
9667 restore_state = NULL;
9668 }
83a57153 9669
6c5ed5ae
ML
9670 if (ret == -EDEADLK)
9671 return ret;
51fd371b 9672
412b61d8 9673 return false;
79e53945
JB
9674}
9675
d2434ab7 9676void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO
9677 struct intel_load_detect_pipe *old,
9678 struct drm_modeset_acquire_ctx *ctx)
79e53945 9679{
d2434ab7
DV
9680 struct intel_encoder *intel_encoder =
9681 intel_attached_encoder(connector);
4ef69c7a 9682 struct drm_encoder *encoder = &intel_encoder->base;
edde3617 9683 struct drm_atomic_state *state = old->restore_state;
d3a40d1b 9684 int ret;
79e53945 9685
d2dff872 9686 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9687 connector->base.id, connector->name,
8e329a03 9688 encoder->base.id, encoder->name);
d2dff872 9689
edde3617 9690 if (!state)
0622a53c 9691 return;
79e53945 9692
581e49fe 9693 ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
0853695c 9694 if (ret)
edde3617 9695 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
0853695c 9696 drm_atomic_state_put(state);
79e53945
JB
9697}
9698
da4a1efa 9699static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 9700 const struct intel_crtc_state *pipe_config)
da4a1efa 9701{
fac5e23e 9702 struct drm_i915_private *dev_priv = to_i915(dev);
da4a1efa
VS
9703 u32 dpll = pipe_config->dpll_hw_state.dpll;
9704
9705 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 9706 return dev_priv->vbt.lvds_ssc_freq;
6e266956 9707 else if (HAS_PCH_SPLIT(dev_priv))
da4a1efa 9708 return 120000;
5db94019 9709 else if (!IS_GEN2(dev_priv))
da4a1efa
VS
9710 return 96000;
9711 else
9712 return 48000;
9713}
9714
79e53945 9715/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 9716static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 9717 struct intel_crtc_state *pipe_config)
79e53945 9718{
f1f644dc 9719 struct drm_device *dev = crtc->base.dev;
fac5e23e 9720 struct drm_i915_private *dev_priv = to_i915(dev);
f1f644dc 9721 int pipe = pipe_config->cpu_transcoder;
293623f7 9722 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945 9723 u32 fp;
9e2c8475 9724 struct dpll clock;
dccbea3b 9725 int port_clock;
da4a1efa 9726 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB
9727
9728 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 9729 fp = pipe_config->dpll_hw_state.fp0;
79e53945 9730 else
293623f7 9731 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB
9732
9733 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9b1e14f4 9734 if (IS_PINEVIEW(dev_priv)) {
f2b115e6
AJ
9735 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9736 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL
9737 } else {
9738 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9739 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9740 }
9741
5db94019 9742 if (!IS_GEN2(dev_priv)) {
9b1e14f4 9743 if (IS_PINEVIEW(dev_priv))
f2b115e6
AJ
9744 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9745 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL
9746 else
9747 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB
9748 DPLL_FPA01_P1_POST_DIV_SHIFT);
9749
9750 switch (dpll & DPLL_MODE_MASK) {
9751 case DPLLB_MODE_DAC_SERIAL:
9752 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9753 5 : 10;
9754 break;
9755 case DPLLB_MODE_LVDS:
9756 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9757 7 : 14;
9758 break;
9759 default:
28c97730 9760 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 9761 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 9762 return;
79e53945
JB
9763 }
9764
9b1e14f4 9765 if (IS_PINEVIEW(dev_priv))
dccbea3b 9766 port_clock = pnv_calc_dpll_params(refclk, &clock);
ac58c3f0 9767 else
dccbea3b 9768 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945 9769 } else {
50a0bc90 9770 u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS);
b1c560d1 9771 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB
9772
9773 if (is_lvds) {
9774 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9775 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS
9776
9777 if (lvds & LVDS_CLKB_POWER_UP)
9778 clock.p2 = 7;
9779 else
9780 clock.p2 = 14;
79e53945
JB
9781 } else {
9782 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9783 clock.p1 = 2;
9784 else {
9785 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9786 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9787 }
9788 if (dpll & PLL_P2_DIVIDE_BY_4)
9789 clock.p2 = 4;
9790 else
9791 clock.p2 = 2;
79e53945 9792 }
da4a1efa 9793
dccbea3b 9794 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945
JB
9795 }
9796
18442d08
VS
9797 /*
9798 * This value includes pixel_multiplier. We will use
241bfc38 9799 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS
9800 * encoder's get_config() function.
9801 */
dccbea3b 9802 pipe_config->port_clock = port_clock;
f1f644dc
JB
9803}
9804
6878da05
VS
9805int intel_dotclock_calculate(int link_freq,
9806 const struct intel_link_m_n *m_n)
f1f644dc 9807{
f1f644dc
JB
9808 /*
9809 * The calculation for the data clock is:
1041a02f 9810 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 9811 * But we want to avoid losing precison if possible, so:
1041a02f 9812 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB
9813 *
9814 * and the link clock is simpler:
1041a02f 9815 * link_clock = (m * link_clock) / n
f1f644dc
JB
9816 */
9817
6878da05
VS
9818 if (!m_n->link_n)
9819 return 0;
f1f644dc 9820
6878da05
VS
9821 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9822}
f1f644dc 9823
18442d08 9824static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 9825 struct intel_crtc_state *pipe_config)
6878da05 9826{
e3b247da 9827 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
79e53945 9828
18442d08
VS
9829 /* read out port_clock from the DPLL */
9830 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 9831
f1f644dc 9832 /*
e3b247da
VS
9833 * In case there is an active pipe without active ports,
9834 * we may need some idea for the dotclock anyway.
9835 * Calculate one based on the FDI configuration.
79e53945 9836 */
2d112de7 9837 pipe_config->base.adjusted_mode.crtc_clock =
21a727b3 9838 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
18442d08 9839 &pipe_config->fdi_m_n);
79e53945
JB
9840}
9841
9842/** Returns the currently programmed mode of the given pipe. */
9843struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9844 struct drm_crtc *crtc)
9845{
fac5e23e 9846 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 9847 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 9848 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 9849 struct drm_display_mode *mode;
3f36b937 9850 struct intel_crtc_state *pipe_config;
fe2b8f9d
PZ
9851 int htot = I915_READ(HTOTAL(cpu_transcoder));
9852 int hsync = I915_READ(HSYNC(cpu_transcoder));
9853 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9854 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 9855 enum pipe pipe = intel_crtc->pipe;
79e53945
JB
9856
9857 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9858 if (!mode)
9859 return NULL;
9860
3f36b937
TU
9861 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9862 if (!pipe_config) {
9863 kfree(mode);
9864 return NULL;
9865 }
9866
f1f644dc
JB
9867 /*
9868 * Construct a pipe_config sufficient for getting the clock info
9869 * back out of crtc_clock_get.
9870 *
9871 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9872 * to use a real value here instead.
9873 */
3f36b937
TU
9874 pipe_config->cpu_transcoder = (enum transcoder) pipe;
9875 pipe_config->pixel_multiplier = 1;
9876 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9877 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9878 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9879 i9xx_crtc_clock_get(intel_crtc, pipe_config);
9880
9881 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
79e53945
JB
9882 mode->hdisplay = (htot & 0xffff) + 1;
9883 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9884 mode->hsync_start = (hsync & 0xffff) + 1;
9885 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9886 mode->vdisplay = (vtot & 0xffff) + 1;
9887 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9888 mode->vsync_start = (vsync & 0xffff) + 1;
9889 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9890
9891 drm_mode_set_name(mode);
79e53945 9892
3f36b937
TU
9893 kfree(pipe_config);
9894
79e53945
JB
9895 return mode;
9896}
9897
9898static void intel_crtc_destroy(struct drm_crtc *crtc)
9899{
9900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a 9901 struct drm_device *dev = crtc->dev;
51cbaf01 9902 struct intel_flip_work *work;
67e77c5a 9903
5e2d7afc 9904 spin_lock_irq(&dev->event_lock);
5a21b665
DV
9905 work = intel_crtc->flip_work;
9906 intel_crtc->flip_work = NULL;
9907 spin_unlock_irq(&dev->event_lock);
67e77c5a 9908
5a21b665 9909 if (work) {
51cbaf01
ML
9910 cancel_work_sync(&work->mmio_work);
9911 cancel_work_sync(&work->unpin_work);
5a21b665 9912 kfree(work);
67e77c5a 9913 }
79e53945
JB
9914
9915 drm_crtc_cleanup(crtc);
67e77c5a 9916
79e53945
JB
9917 kfree(intel_crtc);
9918}
9919
6b95a207
KH
9920static void intel_unpin_work_fn(struct work_struct *__work)
9921{
51cbaf01
ML
9922 struct intel_flip_work *work =
9923 container_of(__work, struct intel_flip_work, unpin_work);
5a21b665
DV
9924 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
9925 struct drm_device *dev = crtc->base.dev;
9926 struct drm_plane *primary = crtc->base.primary;
03f476e1 9927
5a21b665
DV
9928 if (is_mmio_work(work))
9929 flush_work(&work->mmio_work);
03f476e1 9930
5a21b665 9931 mutex_lock(&dev->struct_mutex);
be1e3415 9932 intel_unpin_fb_vma(work->old_vma);
f8c417cd 9933 i915_gem_object_put(work->pending_flip_obj);
5a21b665 9934 mutex_unlock(&dev->struct_mutex);
143f73b3 9935
e8a261ea
CW
9936 i915_gem_request_put(work->flip_queued_req);
9937
5748b6a1
CW
9938 intel_frontbuffer_flip_complete(to_i915(dev),
9939 to_intel_plane(primary)->frontbuffer_bit);
5a21b665
DV
9940 intel_fbc_post_update(crtc);
9941 drm_framebuffer_unreference(work->old_fb);
143f73b3 9942
5a21b665
DV
9943 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
9944 atomic_dec(&crtc->unpin_work_count);
a6747b73 9945
5a21b665
DV
9946 kfree(work);
9947}
d9e86c0e 9948
5a21b665
DV
9949/* Is 'a' after or equal to 'b'? */
9950static bool g4x_flip_count_after_eq(u32 a, u32 b)
9951{
9952 return !((a - b) & 0x80000000);
9953}
143f73b3 9954
5a21b665
DV
9955static bool __pageflip_finished_cs(struct intel_crtc *crtc,
9956 struct intel_flip_work *work)
9957{
9958 struct drm_device *dev = crtc->base.dev;
fac5e23e 9959 struct drm_i915_private *dev_priv = to_i915(dev);
143f73b3 9960
8af29b0c 9961 if (abort_flip_on_reset(crtc))
5a21b665 9962 return true;
143f73b3 9963
5a21b665
DV
9964 /*
9965 * The relevant registers doen't exist on pre-ctg.
9966 * As the flip done interrupt doesn't trigger for mmio
9967 * flips on gmch platforms, a flip count check isn't
9968 * really needed there. But since ctg has the registers,
9969 * include it in the check anyway.
9970 */
9beb5fea 9971 if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv))
5a21b665 9972 return true;
b4a98e57 9973
5a21b665
DV
9974 /*
9975 * BDW signals flip done immediately if the plane
9976 * is disabled, even if the plane enable is already
9977 * armed to occur at the next vblank :(
9978 */
f99d7069 9979
5a21b665
DV
9980 /*
9981 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9982 * used the same base address. In that case the mmio flip might
9983 * have completed, but the CS hasn't even executed the flip yet.
9984 *
9985 * A flip count check isn't enough as the CS might have updated
9986 * the base address just after start of vblank, but before we
9987 * managed to process the interrupt. This means we'd complete the
9988 * CS flip too soon.
9989 *
9990 * Combining both checks should get us a good enough result. It may
9991 * still happen that the CS flip has been executed, but has not
9992 * yet actually completed. But in case the base address is the same
9993 * anyway, we don't really care.
9994 */
9995 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9996 crtc->flip_work->gtt_offset &&
9997 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
9998 crtc->flip_work->flip_count);
9999}
b4a98e57 10000
5a21b665
DV
10001static bool
10002__pageflip_finished_mmio(struct intel_crtc *crtc,
10003 struct intel_flip_work *work)
10004{
10005 /*
10006 * MMIO work completes when vblank is different from
10007 * flip_queued_vblank.
10008 *
10009 * Reset counter value doesn't matter, this is handled by
10010 * i915_wait_request finishing early, so no need to handle
10011 * reset here.
10012 */
10013 return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank;
6b95a207
KH
10014}
10015
51cbaf01
ML
10016
10017static bool pageflip_finished(struct intel_crtc *crtc,
10018 struct intel_flip_work *work)
10019{
10020 if (!atomic_read(&work->pending))
10021 return false;
10022
10023 smp_rmb();
10024
5a21b665
DV
10025 if (is_mmio_work(work))
10026 return __pageflip_finished_mmio(crtc, work);
10027 else
10028 return __pageflip_finished_cs(crtc, work);
10029}
10030
10031void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe)
10032{
91c8a326 10033 struct drm_device *dev = &dev_priv->drm;
98187836 10034 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
5a21b665
DV
10035 struct intel_flip_work *work;
10036 unsigned long flags;
10037
10038 /* Ignore early vblank irqs */
10039 if (!crtc)
10040 return;
10041
51cbaf01 10042 /*
5a21b665
DV
10043 * This is called both by irq handlers and the reset code (to complete
10044 * lost pageflips) so needs the full irqsave spinlocks.
51cbaf01 10045 */
5a21b665 10046 spin_lock_irqsave(&dev->event_lock, flags);
e2af48c6 10047 work = crtc->flip_work;
5a21b665
DV
10048
10049 if (work != NULL &&
10050 !is_mmio_work(work) &&
e2af48c6
VS
10051 pageflip_finished(crtc, work))
10052 page_flip_completed(crtc);
5a21b665
DV
10053
10054 spin_unlock_irqrestore(&dev->event_lock, flags);
75f7f3ec
VS
10055}
10056
51cbaf01 10057void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe)
6b95a207 10058{
91c8a326 10059 struct drm_device *dev = &dev_priv->drm;
98187836 10060 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
51cbaf01 10061 struct intel_flip_work *work;
6b95a207
KH
10062 unsigned long flags;
10063
5251f04e
ML
10064 /* Ignore early vblank irqs */
10065 if (!crtc)
10066 return;
f326038a
DV
10067
10068 /*
10069 * This is called both by irq handlers and the reset code (to complete
10070 * lost pageflips) so needs the full irqsave spinlocks.
e7d841ca 10071 */
6b95a207 10072 spin_lock_irqsave(&dev->event_lock, flags);
e2af48c6 10073 work = crtc->flip_work;
5251f04e 10074
5a21b665
DV
10075 if (work != NULL &&
10076 is_mmio_work(work) &&
e2af48c6
VS
10077 pageflip_finished(crtc, work))
10078 page_flip_completed(crtc);
5251f04e 10079
6b95a207
KH
10080 spin_unlock_irqrestore(&dev->event_lock, flags);
10081}
10082
5a21b665
DV
10083static inline void intel_mark_page_flip_active(struct intel_crtc *crtc,
10084 struct intel_flip_work *work)
84c33a64 10085{
5a21b665 10086 work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc);
84c33a64 10087
5a21b665
DV
10088 /* Ensure that the work item is consistent when activating it ... */
10089 smp_mb__before_atomic();
10090 atomic_set(&work->pending, 1);
10091}
a6747b73 10092
5a21b665
DV
10093static int intel_gen2_queue_flip(struct drm_device *dev,
10094 struct drm_crtc *crtc,
10095 struct drm_framebuffer *fb,
10096 struct drm_i915_gem_object *obj,
10097 struct drm_i915_gem_request *req,
10098 uint32_t flags)
10099{
5a21b665 10100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
73dec95e 10101 u32 flip_mask, *cs;
143f73b3 10102
73dec95e
TU
10103 cs = intel_ring_begin(req, 6);
10104 if (IS_ERR(cs))
10105 return PTR_ERR(cs);
143f73b3 10106
5a21b665
DV
10107 /* Can't queue multiple flips, so wait for the previous
10108 * one to finish before executing the next.
10109 */
10110 if (intel_crtc->plane)
10111 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10112 else
10113 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
73dec95e
TU
10114 *cs++ = MI_WAIT_FOR_EVENT | flip_mask;
10115 *cs++ = MI_NOOP;
10116 *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10117 *cs++ = fb->pitches[0];
10118 *cs++ = intel_crtc->flip_work->gtt_offset;
10119 *cs++ = 0; /* aux display base address, unused */
143f73b3 10120
5a21b665
DV
10121 return 0;
10122}
84c33a64 10123
5a21b665
DV
10124static int intel_gen3_queue_flip(struct drm_device *dev,
10125 struct drm_crtc *crtc,
10126 struct drm_framebuffer *fb,
10127 struct drm_i915_gem_object *obj,
10128 struct drm_i915_gem_request *req,
10129 uint32_t flags)
10130{
5a21b665 10131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
73dec95e 10132 u32 flip_mask, *cs;
d55dbd06 10133
73dec95e
TU
10134 cs = intel_ring_begin(req, 6);
10135 if (IS_ERR(cs))
10136 return PTR_ERR(cs);
d55dbd06 10137
5a21b665
DV
10138 if (intel_crtc->plane)
10139 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10140 else
10141 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
73dec95e
TU
10142 *cs++ = MI_WAIT_FOR_EVENT | flip_mask;
10143 *cs++ = MI_NOOP;
10144 *cs++ = MI_DISPLAY_FLIP_I915 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10145 *cs++ = fb->pitches[0];
10146 *cs++ = intel_crtc->flip_work->gtt_offset;
10147 *cs++ = MI_NOOP;
fd8e058a 10148
5a21b665
DV
10149 return 0;
10150}
84c33a64 10151
5a21b665
DV
10152static int intel_gen4_queue_flip(struct drm_device *dev,
10153 struct drm_crtc *crtc,
10154 struct drm_framebuffer *fb,
10155 struct drm_i915_gem_object *obj,
10156 struct drm_i915_gem_request *req,
10157 uint32_t flags)
10158{
fac5e23e 10159 struct drm_i915_private *dev_priv = to_i915(dev);
5a21b665 10160 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
73dec95e 10161 u32 pf, pipesrc, *cs;
143f73b3 10162
73dec95e
TU
10163 cs = intel_ring_begin(req, 4);
10164 if (IS_ERR(cs))
10165 return PTR_ERR(cs);
143f73b3 10166
5a21b665
DV
10167 /* i965+ uses the linear or tiled offsets from the
10168 * Display Registers (which do not change across a page-flip)
10169 * so we need only reprogram the base address.
10170 */
73dec95e
TU
10171 *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10172 *cs++ = fb->pitches[0];
10173 *cs++ = intel_crtc->flip_work->gtt_offset |
10174 intel_fb_modifier_to_tiling(fb->modifier);
5a21b665
DV
10175
10176 /* XXX Enabling the panel-fitter across page-flip is so far
10177 * untested on non-native modes, so ignore it for now.
10178 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10179 */
10180 pf = 0;
10181 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
73dec95e 10182 *cs++ = pf | pipesrc;
143f73b3 10183
5a21b665 10184 return 0;
8c9f3aaf
JB
10185}
10186
5a21b665
DV
10187static int intel_gen6_queue_flip(struct drm_device *dev,
10188 struct drm_crtc *crtc,
10189 struct drm_framebuffer *fb,
10190 struct drm_i915_gem_object *obj,
10191 struct drm_i915_gem_request *req,
10192 uint32_t flags)
da20eabd 10193{
fac5e23e 10194 struct drm_i915_private *dev_priv = to_i915(dev);
5a21b665 10195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
73dec95e 10196 u32 pf, pipesrc, *cs;
d21fbe87 10197
73dec95e
TU
10198 cs = intel_ring_begin(req, 4);
10199 if (IS_ERR(cs))
10200 return PTR_ERR(cs);
92826fcd 10201
73dec95e
TU
10202 *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane);
10203 *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier);
10204 *cs++ = intel_crtc->flip_work->gtt_offset;
92826fcd 10205
5a21b665
DV
10206 /* Contrary to the suggestions in the documentation,
10207 * "Enable Panel Fitter" does not seem to be required when page
10208 * flipping with a non-native mode, and worse causes a normal
10209 * modeset to fail.
10210 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10211 */
10212 pf = 0;
10213 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
73dec95e 10214 *cs++ = pf | pipesrc;
7809e5ae 10215
5a21b665 10216 return 0;
7809e5ae
MR
10217}
10218
5a21b665
DV
10219static int intel_gen7_queue_flip(struct drm_device *dev,
10220 struct drm_crtc *crtc,
10221 struct drm_framebuffer *fb,
10222 struct drm_i915_gem_object *obj,
10223 struct drm_i915_gem_request *req,
10224 uint32_t flags)
d21fbe87 10225{
5db94019 10226 struct drm_i915_private *dev_priv = to_i915(dev);
5a21b665 10227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
73dec95e 10228 u32 *cs, plane_bit = 0;
5a21b665 10229 int len, ret;
d21fbe87 10230
5a21b665
DV
10231 switch (intel_crtc->plane) {
10232 case PLANE_A:
10233 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10234 break;
10235 case PLANE_B:
10236 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10237 break;
10238 case PLANE_C:
10239 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10240 break;
10241 default:
10242 WARN_ONCE(1, "unknown plane in flip command\n");
10243 return -ENODEV;
10244 }
10245
10246 len = 4;
b5321f30 10247 if (req->engine->id == RCS) {
5a21b665
DV
10248 len += 6;
10249 /*
10250 * On Gen 8, SRM is now taking an extra dword to accommodate
10251 * 48bits addresses, and we need a NOOP for the batch size to
10252 * stay even.
10253 */
5db94019 10254 if (IS_GEN8(dev_priv))
5a21b665
DV
10255 len += 2;
10256 }
10257
10258 /*
10259 * BSpec MI_DISPLAY_FLIP for IVB:
10260 * "The full packet must be contained within the same cache line."
10261 *
10262 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10263 * cacheline, if we ever start emitting more commands before
10264 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10265 * then do the cacheline alignment, and finally emit the
10266 * MI_DISPLAY_FLIP.
10267 */
10268 ret = intel_ring_cacheline_align(req);
10269 if (ret)
10270 return ret;
10271
73dec95e
TU
10272 cs = intel_ring_begin(req, len);
10273 if (IS_ERR(cs))
10274 return PTR_ERR(cs);
5a21b665
DV
10275
10276 /* Unmask the flip-done completion message. Note that the bspec says that
10277 * we should do this for both the BCS and RCS, and that we must not unmask
10278 * more than one flip event at any time (or ensure that one flip message
10279 * can be sent by waiting for flip-done prior to queueing new flips).
10280 * Experimentation says that BCS works despite DERRMR masking all
10281 * flip-done completion events and that unmasking all planes at once
10282 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10283 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10284 */
b5321f30 10285 if (req->engine->id == RCS) {
73dec95e
TU
10286 *cs++ = MI_LOAD_REGISTER_IMM(1);
10287 *cs++ = i915_mmio_reg_offset(DERRMR);
10288 *cs++ = ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10289 DERRMR_PIPEB_PRI_FLIP_DONE |
10290 DERRMR_PIPEC_PRI_FLIP_DONE);
5db94019 10291 if (IS_GEN8(dev_priv))
73dec95e
TU
10292 *cs++ = MI_STORE_REGISTER_MEM_GEN8 |
10293 MI_SRM_LRM_GLOBAL_GTT;
5a21b665 10294 else
73dec95e
TU
10295 *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
10296 *cs++ = i915_mmio_reg_offset(DERRMR);
10297 *cs++ = i915_ggtt_offset(req->engine->scratch) + 256;
5db94019 10298 if (IS_GEN8(dev_priv)) {
73dec95e
TU
10299 *cs++ = 0;
10300 *cs++ = MI_NOOP;
5a21b665
DV
10301 }
10302 }
10303
73dec95e
TU
10304 *cs++ = MI_DISPLAY_FLIP_I915 | plane_bit;
10305 *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier);
10306 *cs++ = intel_crtc->flip_work->gtt_offset;
10307 *cs++ = MI_NOOP;
5a21b665
DV
10308
10309 return 0;
10310}
10311
10312static bool use_mmio_flip(struct intel_engine_cs *engine,
10313 struct drm_i915_gem_object *obj)
10314{
10315 /*
10316 * This is not being used for older platforms, because
10317 * non-availability of flip done interrupt forces us to use
10318 * CS flips. Older platforms derive flip done using some clever
10319 * tricks involving the flip_pending status bits and vblank irqs.
10320 * So using MMIO flips there would disrupt this mechanism.
10321 */
10322
10323 if (engine == NULL)
10324 return true;
10325
10326 if (INTEL_GEN(engine->i915) < 5)
10327 return false;
10328
10329 if (i915.use_mmio_flip < 0)
10330 return false;
10331 else if (i915.use_mmio_flip > 0)
10332 return true;
10333 else if (i915.enable_execlists)
10334 return true;
c37efb99 10335
d07f0e59 10336 return engine != i915_gem_object_last_write_engine(obj);
5a21b665
DV
10337}
10338
10339static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
10340 unsigned int rotation,
10341 struct intel_flip_work *work)
10342{
10343 struct drm_device *dev = intel_crtc->base.dev;
fac5e23e 10344 struct drm_i915_private *dev_priv = to_i915(dev);
5a21b665
DV
10345 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10346 const enum pipe pipe = intel_crtc->pipe;
d2196774 10347 u32 ctl, stride = skl_plane_stride(fb, 0, rotation);
5a21b665
DV
10348
10349 ctl = I915_READ(PLANE_CTL(pipe, 0));
10350 ctl &= ~PLANE_CTL_TILED_MASK;
bae781b2 10351 switch (fb->modifier) {
2f075565 10352 case DRM_FORMAT_MOD_LINEAR:
5a21b665
DV
10353 break;
10354 case I915_FORMAT_MOD_X_TILED:
10355 ctl |= PLANE_CTL_TILED_X;
10356 break;
10357 case I915_FORMAT_MOD_Y_TILED:
10358 ctl |= PLANE_CTL_TILED_Y;
10359 break;
10360 case I915_FORMAT_MOD_Yf_TILED:
10361 ctl |= PLANE_CTL_TILED_YF;
10362 break;
10363 default:
bae781b2 10364 MISSING_CASE(fb->modifier);
5a21b665
DV
10365 }
10366
5a21b665
DV
10367 /*
10368 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10369 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10370 */
10371 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10372 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10373
10374 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
10375 POSTING_READ(PLANE_SURF(pipe, 0));
10376}
10377
10378static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
10379 struct intel_flip_work *work)
10380{
10381 struct drm_device *dev = intel_crtc->base.dev;
fac5e23e 10382 struct drm_i915_private *dev_priv = to_i915(dev);
72618ebf 10383 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
5a21b665
DV
10384 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
10385 u32 dspcntr;
10386
10387 dspcntr = I915_READ(reg);
10388
bae781b2 10389 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
5a21b665
DV
10390 dspcntr |= DISPPLANE_TILED;
10391 else
10392 dspcntr &= ~DISPPLANE_TILED;
10393
10394 I915_WRITE(reg, dspcntr);
10395
10396 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
10397 POSTING_READ(DSPSURF(intel_crtc->plane));
10398}
10399
10400static void intel_mmio_flip_work_func(struct work_struct *w)
10401{
10402 struct intel_flip_work *work =
10403 container_of(w, struct intel_flip_work, mmio_work);
10404 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10405 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10406 struct intel_framebuffer *intel_fb =
10407 to_intel_framebuffer(crtc->base.primary->fb);
10408 struct drm_i915_gem_object *obj = intel_fb->obj;
10409
d07f0e59 10410 WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0);
5a21b665
DV
10411
10412 intel_pipe_update_start(crtc);
10413
10414 if (INTEL_GEN(dev_priv) >= 9)
10415 skl_do_mmio_flip(crtc, work->rotation, work);
10416 else
10417 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10418 ilk_do_mmio_flip(crtc, work);
10419
10420 intel_pipe_update_end(crtc, work);
10421}
10422
10423static int intel_default_queue_flip(struct drm_device *dev,
10424 struct drm_crtc *crtc,
10425 struct drm_framebuffer *fb,
10426 struct drm_i915_gem_object *obj,
10427 struct drm_i915_gem_request *req,
10428 uint32_t flags)
10429{
10430 return -ENODEV;
10431}
10432
10433static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv,
10434 struct intel_crtc *intel_crtc,
10435 struct intel_flip_work *work)
10436{
10437 u32 addr, vblank;
10438
10439 if (!atomic_read(&work->pending))
10440 return false;
10441
10442 smp_rmb();
10443
10444 vblank = intel_crtc_get_vblank_counter(intel_crtc);
10445 if (work->flip_ready_vblank == 0) {
10446 if (work->flip_queued_req &&
f69a02c9 10447 !i915_gem_request_completed(work->flip_queued_req))
5a21b665
DV
10448 return false;
10449
10450 work->flip_ready_vblank = vblank;
10451 }
10452
10453 if (vblank - work->flip_ready_vblank < 3)
10454 return false;
10455
10456 /* Potential stall - if we see that the flip has happened,
10457 * assume a missed interrupt. */
10458 if (INTEL_GEN(dev_priv) >= 4)
10459 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10460 else
10461 addr = I915_READ(DSPADDR(intel_crtc->plane));
10462
10463 /* There is a potential issue here with a false positive after a flip
10464 * to the same address. We could address this by checking for a
10465 * non-incrementing frame counter.
10466 */
10467 return addr == work->gtt_offset;
10468}
10469
10470void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe)
10471{
91c8a326 10472 struct drm_device *dev = &dev_priv->drm;
98187836 10473 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
5a21b665
DV
10474 struct intel_flip_work *work;
10475
10476 WARN_ON(!in_interrupt());
10477
10478 if (crtc == NULL)
10479 return;
10480
10481 spin_lock(&dev->event_lock);
e2af48c6 10482 work = crtc->flip_work;
5a21b665
DV
10483
10484 if (work != NULL && !is_mmio_work(work) &&
e2af48c6 10485 __pageflip_stall_check_cs(dev_priv, crtc, work)) {
5a21b665
DV
10486 WARN_ONCE(1,
10487 "Kicking stuck page flip: queued at %d, now %d\n",
e2af48c6
VS
10488 work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc));
10489 page_flip_completed(crtc);
5a21b665
DV
10490 work = NULL;
10491 }
10492
10493 if (work != NULL && !is_mmio_work(work) &&
e2af48c6 10494 intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1)
5a21b665
DV
10495 intel_queue_rps_boost_for_request(work->flip_queued_req);
10496 spin_unlock(&dev->event_lock);
10497}
10498
4c01ded5 10499__maybe_unused
5a21b665
DV
10500static int intel_crtc_page_flip(struct drm_crtc *crtc,
10501 struct drm_framebuffer *fb,
10502 struct drm_pending_vblank_event *event,
10503 uint32_t page_flip_flags)
10504{
10505 struct drm_device *dev = crtc->dev;
fac5e23e 10506 struct drm_i915_private *dev_priv = to_i915(dev);
5a21b665
DV
10507 struct drm_framebuffer *old_fb = crtc->primary->fb;
10508 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10509 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10510 struct drm_plane *primary = crtc->primary;
10511 enum pipe pipe = intel_crtc->pipe;
10512 struct intel_flip_work *work;
10513 struct intel_engine_cs *engine;
10514 bool mmio_flip;
8e637178 10515 struct drm_i915_gem_request *request;
058d88c4 10516 struct i915_vma *vma;
5a21b665
DV
10517 int ret;
10518
10519 /*
10520 * drm_mode_page_flip_ioctl() should already catch this, but double
10521 * check to be safe. In the future we may enable pageflipping from
10522 * a disabled primary plane.
10523 */
10524 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10525 return -EBUSY;
10526
10527 /* Can't change pixel format via MI display flips. */
dbd4d576 10528 if (fb->format != crtc->primary->fb->format)
5a21b665
DV
10529 return -EINVAL;
10530
10531 /*
10532 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10533 * Note that pitch changes could also affect these register.
10534 */
6315b5d3 10535 if (INTEL_GEN(dev_priv) > 3 &&
5a21b665
DV
10536 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10537 fb->pitches[0] != crtc->primary->fb->pitches[0]))
10538 return -EINVAL;
10539
10540 if (i915_terminally_wedged(&dev_priv->gpu_error))
10541 goto out_hang;
10542
10543 work = kzalloc(sizeof(*work), GFP_KERNEL);
10544 if (work == NULL)
10545 return -ENOMEM;
10546
10547 work->event = event;
10548 work->crtc = crtc;
10549 work->old_fb = old_fb;
10550 INIT_WORK(&work->unpin_work, intel_unpin_work_fn);
10551
10552 ret = drm_crtc_vblank_get(crtc);
10553 if (ret)
10554 goto free_work;
10555
10556 /* We borrow the event spin lock for protecting flip_work */
10557 spin_lock_irq(&dev->event_lock);
10558 if (intel_crtc->flip_work) {
10559 /* Before declaring the flip queue wedged, check if
10560 * the hardware completed the operation behind our backs.
10561 */
10562 if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) {
10563 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10564 page_flip_completed(intel_crtc);
10565 } else {
10566 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10567 spin_unlock_irq(&dev->event_lock);
10568
10569 drm_crtc_vblank_put(crtc);
10570 kfree(work);
10571 return -EBUSY;
10572 }
10573 }
10574 intel_crtc->flip_work = work;
10575 spin_unlock_irq(&dev->event_lock);
10576
10577 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10578 flush_workqueue(dev_priv->wq);
10579
10580 /* Reference the objects for the scheduled work. */
10581 drm_framebuffer_reference(work->old_fb);
5a21b665
DV
10582
10583 crtc->primary->fb = fb;
10584 update_state_fb(crtc->primary);
faf68d92 10585
25dc556a 10586 work->pending_flip_obj = i915_gem_object_get(obj);
5a21b665
DV
10587
10588 ret = i915_mutex_lock_interruptible(dev);
10589 if (ret)
10590 goto cleanup;
10591
8af29b0c 10592 intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error);
8c185eca 10593 if (i915_reset_backoff_or_wedged(&dev_priv->gpu_error)) {
5a21b665 10594 ret = -EIO;
ddbb271a 10595 goto unlock;
5a21b665
DV
10596 }
10597
10598 atomic_inc(&intel_crtc->unpin_work_count);
10599
9beb5fea 10600 if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
5a21b665
DV
10601 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
10602
920a14b2 10603 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3b3f1650 10604 engine = dev_priv->engine[BCS];
bae781b2 10605 if (fb->modifier != old_fb->modifier)
5a21b665
DV
10606 /* vlv: DISPLAY_FLIP fails to change tiling */
10607 engine = NULL;
fd6b8f43 10608 } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
3b3f1650 10609 engine = dev_priv->engine[BCS];
6315b5d3 10610 } else if (INTEL_GEN(dev_priv) >= 7) {
d07f0e59 10611 engine = i915_gem_object_last_write_engine(obj);
5a21b665 10612 if (engine == NULL || engine->id != RCS)
3b3f1650 10613 engine = dev_priv->engine[BCS];
5a21b665 10614 } else {
3b3f1650 10615 engine = dev_priv->engine[RCS];
5a21b665
DV
10616 }
10617
10618 mmio_flip = use_mmio_flip(engine, obj);
10619
058d88c4
CW
10620 vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
10621 if (IS_ERR(vma)) {
10622 ret = PTR_ERR(vma);
5a21b665 10623 goto cleanup_pending;
058d88c4 10624 }
5a21b665 10625
be1e3415
CW
10626 work->old_vma = to_intel_plane_state(primary->state)->vma;
10627 to_intel_plane_state(primary->state)->vma = vma;
10628
10629 work->gtt_offset = i915_ggtt_offset(vma) + intel_crtc->dspaddr_offset;
5a21b665
DV
10630 work->rotation = crtc->primary->state->rotation;
10631
1f061316
PZ
10632 /*
10633 * There's the potential that the next frame will not be compatible with
10634 * FBC, so we want to call pre_update() before the actual page flip.
10635 * The problem is that pre_update() caches some information about the fb
10636 * object, so we want to do this only after the object is pinned. Let's
10637 * be on the safe side and do this immediately before scheduling the
10638 * flip.
10639 */
10640 intel_fbc_pre_update(intel_crtc, intel_crtc->config,
10641 to_intel_plane_state(primary->state));
10642
5a21b665
DV
10643 if (mmio_flip) {
10644 INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func);
6277c8d0 10645 queue_work(system_unbound_wq, &work->mmio_work);
5a21b665 10646 } else {
e8a9c58f
CW
10647 request = i915_gem_request_alloc(engine,
10648 dev_priv->kernel_context);
8e637178
CW
10649 if (IS_ERR(request)) {
10650 ret = PTR_ERR(request);
10651 goto cleanup_unpin;
10652 }
10653
a2bc4695 10654 ret = i915_gem_request_await_object(request, obj, false);
8e637178
CW
10655 if (ret)
10656 goto cleanup_request;
10657
5a21b665
DV
10658 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
10659 page_flip_flags);
10660 if (ret)
8e637178 10661 goto cleanup_request;
5a21b665
DV
10662
10663 intel_mark_page_flip_active(intel_crtc, work);
10664
8e637178 10665 work->flip_queued_req = i915_gem_request_get(request);
e642c85b 10666 i915_add_request(request);
5a21b665
DV
10667 }
10668
92117f0b 10669 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
5a21b665
DV
10670 i915_gem_track_fb(intel_fb_obj(old_fb), obj,
10671 to_intel_plane(primary)->frontbuffer_bit);
10672 mutex_unlock(&dev->struct_mutex);
10673
5748b6a1 10674 intel_frontbuffer_flip_prepare(to_i915(dev),
5a21b665
DV
10675 to_intel_plane(primary)->frontbuffer_bit);
10676
10677 trace_i915_flip_request(intel_crtc->plane, obj);
10678
10679 return 0;
10680
8e637178 10681cleanup_request:
e642c85b 10682 i915_add_request(request);
5a21b665 10683cleanup_unpin:
be1e3415
CW
10684 to_intel_plane_state(primary->state)->vma = work->old_vma;
10685 intel_unpin_fb_vma(vma);
5a21b665 10686cleanup_pending:
5a21b665 10687 atomic_dec(&intel_crtc->unpin_work_count);
ddbb271a 10688unlock:
5a21b665
DV
10689 mutex_unlock(&dev->struct_mutex);
10690cleanup:
10691 crtc->primary->fb = old_fb;
10692 update_state_fb(crtc->primary);
10693
f0cd5182 10694 i915_gem_object_put(obj);
5a21b665
DV
10695 drm_framebuffer_unreference(work->old_fb);
10696
10697 spin_lock_irq(&dev->event_lock);
10698 intel_crtc->flip_work = NULL;
10699 spin_unlock_irq(&dev->event_lock);
10700
10701 drm_crtc_vblank_put(crtc);
10702free_work:
10703 kfree(work);
10704
10705 if (ret == -EIO) {
10706 struct drm_atomic_state *state;
10707 struct drm_plane_state *plane_state;
10708
10709out_hang:
10710 state = drm_atomic_state_alloc(dev);
10711 if (!state)
10712 return -ENOMEM;
b260ac3e 10713 state->acquire_ctx = dev->mode_config.acquire_ctx;
5a21b665
DV
10714
10715retry:
10716 plane_state = drm_atomic_get_plane_state(state, primary);
10717 ret = PTR_ERR_OR_ZERO(plane_state);
10718 if (!ret) {
10719 drm_atomic_set_fb_for_plane(plane_state, fb);
10720
10721 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
10722 if (!ret)
10723 ret = drm_atomic_commit(state);
10724 }
10725
10726 if (ret == -EDEADLK) {
10727 drm_modeset_backoff(state->acquire_ctx);
10728 drm_atomic_state_clear(state);
10729 goto retry;
10730 }
10731
0853695c 10732 drm_atomic_state_put(state);
5a21b665
DV
10733
10734 if (ret == 0 && event) {
10735 spin_lock_irq(&dev->event_lock);
10736 drm_crtc_send_vblank_event(crtc, event);
10737 spin_unlock_irq(&dev->event_lock);
10738 }
10739 }
10740 return ret;
10741}
10742
10743
10744/**
10745 * intel_wm_need_update - Check whether watermarks need updating
10746 * @plane: drm plane
10747 * @state: new plane state
10748 *
10749 * Check current plane state versus the new one to determine whether
10750 * watermarks need to be recalculated.
10751 *
10752 * Returns true or false.
10753 */
10754static bool intel_wm_need_update(struct drm_plane *plane,
10755 struct drm_plane_state *state)
10756{
10757 struct intel_plane_state *new = to_intel_plane_state(state);
10758 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
10759
10760 /* Update watermarks on tiling or size changes. */
936e71e3 10761 if (new->base.visible != cur->base.visible)
5a21b665
DV
10762 return true;
10763
10764 if (!cur->base.fb || !new->base.fb)
10765 return false;
10766
bae781b2 10767 if (cur->base.fb->modifier != new->base.fb->modifier ||
5a21b665 10768 cur->base.rotation != new->base.rotation ||
936e71e3
VS
10769 drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) ||
10770 drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) ||
10771 drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) ||
10772 drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst))
5a21b665
DV
10773 return true;
10774
10775 return false;
10776}
10777
10778static bool needs_scaling(struct intel_plane_state *state)
10779{
936e71e3
VS
10780 int src_w = drm_rect_width(&state->base.src) >> 16;
10781 int src_h = drm_rect_height(&state->base.src) >> 16;
10782 int dst_w = drm_rect_width(&state->base.dst);
10783 int dst_h = drm_rect_height(&state->base.dst);
5a21b665
DV
10784
10785 return (src_w != dst_w || src_h != dst_h);
10786}
d21fbe87 10787
da20eabd
ML
10788int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
10789 struct drm_plane_state *plane_state)
10790{
ab1d3a0e 10791 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
da20eabd
ML
10792 struct drm_crtc *crtc = crtc_state->crtc;
10793 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e9728bd8 10794 struct intel_plane *plane = to_intel_plane(plane_state->plane);
da20eabd 10795 struct drm_device *dev = crtc->dev;
ed4a6a7c 10796 struct drm_i915_private *dev_priv = to_i915(dev);
da20eabd 10797 struct intel_plane_state *old_plane_state =
e9728bd8 10798 to_intel_plane_state(plane->base.state);
da20eabd
ML
10799 bool mode_changed = needs_modeset(crtc_state);
10800 bool was_crtc_enabled = crtc->state->active;
10801 bool is_crtc_enabled = crtc_state->active;
da20eabd
ML
10802 bool turn_off, turn_on, visible, was_visible;
10803 struct drm_framebuffer *fb = plane_state->fb;
78108b7c 10804 int ret;
da20eabd 10805
e9728bd8 10806 if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
da20eabd
ML
10807 ret = skl_update_scaler_plane(
10808 to_intel_crtc_state(crtc_state),
10809 to_intel_plane_state(plane_state));
10810 if (ret)
10811 return ret;
10812 }
10813
936e71e3 10814 was_visible = old_plane_state->base.visible;
1d4258db 10815 visible = plane_state->visible;
da20eabd
ML
10816
10817 if (!was_crtc_enabled && WARN_ON(was_visible))
10818 was_visible = false;
10819
35c08f43
ML
10820 /*
10821 * Visibility is calculated as if the crtc was on, but
10822 * after scaler setup everything depends on it being off
10823 * when the crtc isn't active.
f818ffea
VS
10824 *
10825 * FIXME this is wrong for watermarks. Watermarks should also
10826 * be computed as if the pipe would be active. Perhaps move
10827 * per-plane wm computation to the .check_plane() hook, and
10828 * only combine the results from all planes in the current place?
35c08f43 10829 */
e9728bd8 10830 if (!is_crtc_enabled) {
1d4258db 10831 plane_state->visible = visible = false;
e9728bd8
VS
10832 to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id);
10833 }
da20eabd
ML
10834
10835 if (!was_visible && !visible)
10836 return 0;
10837
e8861675
ML
10838 if (fb != old_plane_state->base.fb)
10839 pipe_config->fb_changed = true;
10840
da20eabd
ML
10841 turn_off = was_visible && (!visible || mode_changed);
10842 turn_on = visible && (!was_visible || mode_changed);
10843
72660ce0 10844 DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n",
e9728bd8
VS
10845 intel_crtc->base.base.id, intel_crtc->base.name,
10846 plane->base.base.id, plane->base.name,
72660ce0 10847 fb ? fb->base.id : -1);
da20eabd 10848
72660ce0 10849 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
e9728bd8 10850 plane->base.base.id, plane->base.name,
72660ce0 10851 was_visible, visible,
da20eabd
ML
10852 turn_off, turn_on, mode_changed);
10853
caed361d 10854 if (turn_on) {
b4ede6df
VS
10855 if (INTEL_GEN(dev_priv) < 5)
10856 pipe_config->update_wm_pre = true;
caed361d
VS
10857
10858 /* must disable cxsr around plane enable/disable */
e9728bd8 10859 if (plane->id != PLANE_CURSOR)
caed361d
VS
10860 pipe_config->disable_cxsr = true;
10861 } else if (turn_off) {
b4ede6df
VS
10862 if (INTEL_GEN(dev_priv) < 5)
10863 pipe_config->update_wm_post = true;
92826fcd 10864
852eb00d 10865 /* must disable cxsr around plane enable/disable */
e9728bd8 10866 if (plane->id != PLANE_CURSOR)
ab1d3a0e 10867 pipe_config->disable_cxsr = true;
e9728bd8 10868 } else if (intel_wm_need_update(&plane->base, plane_state)) {
b4ede6df
VS
10869 if (INTEL_GEN(dev_priv) < 5) {
10870 /* FIXME bollocks */
10871 pipe_config->update_wm_pre = true;
10872 pipe_config->update_wm_post = true;
10873 }
852eb00d 10874 }
da20eabd 10875
8be6ca85 10876 if (visible || was_visible)
e9728bd8 10877 pipe_config->fb_bits |= plane->frontbuffer_bit;
a9ff8714 10878
31ae71fc
ML
10879 /*
10880 * WaCxSRDisabledForSpriteScaling:ivb
10881 *
10882 * cstate->update_wm was already set above, so this flag will
10883 * take effect when we commit and program watermarks.
10884 */
e9728bd8 10885 if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) &&
31ae71fc
ML
10886 needs_scaling(to_intel_plane_state(plane_state)) &&
10887 !needs_scaling(old_plane_state))
10888 pipe_config->disable_lp_wm = true;
d21fbe87 10889
da20eabd
ML
10890 return 0;
10891}
10892
6d3a1ce7
ML
10893static bool encoders_cloneable(const struct intel_encoder *a,
10894 const struct intel_encoder *b)
10895{
10896 /* masks could be asymmetric, so check both ways */
10897 return a == b || (a->cloneable & (1 << b->type) &&
10898 b->cloneable & (1 << a->type));
10899}
10900
10901static bool check_single_encoder_cloning(struct drm_atomic_state *state,
10902 struct intel_crtc *crtc,
10903 struct intel_encoder *encoder)
10904{
10905 struct intel_encoder *source_encoder;
10906 struct drm_connector *connector;
10907 struct drm_connector_state *connector_state;
10908 int i;
10909
aa5e9b47 10910 for_each_new_connector_in_state(state, connector, connector_state, i) {
6d3a1ce7
ML
10911 if (connector_state->crtc != &crtc->base)
10912 continue;
10913
10914 source_encoder =
10915 to_intel_encoder(connector_state->best_encoder);
10916 if (!encoders_cloneable(encoder, source_encoder))
10917 return false;
10918 }
10919
10920 return true;
10921}
10922
6d3a1ce7
ML
10923static int intel_crtc_atomic_check(struct drm_crtc *crtc,
10924 struct drm_crtc_state *crtc_state)
10925{
cf5a15be 10926 struct drm_device *dev = crtc->dev;
fac5e23e 10927 struct drm_i915_private *dev_priv = to_i915(dev);
6d3a1ce7 10928 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cf5a15be
ML
10929 struct intel_crtc_state *pipe_config =
10930 to_intel_crtc_state(crtc_state);
6d3a1ce7 10931 struct drm_atomic_state *state = crtc_state->state;
4d20cd86 10932 int ret;
6d3a1ce7
ML
10933 bool mode_changed = needs_modeset(crtc_state);
10934
852eb00d 10935 if (mode_changed && !crtc_state->active)
caed361d 10936 pipe_config->update_wm_post = true;
eddfcbcd 10937
ad421372
ML
10938 if (mode_changed && crtc_state->enable &&
10939 dev_priv->display.crtc_compute_clock &&
8106ddbd 10940 !WARN_ON(pipe_config->shared_dpll)) {
ad421372
ML
10941 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
10942 pipe_config);
10943 if (ret)
10944 return ret;
10945 }
10946
82cf435b
LL
10947 if (crtc_state->color_mgmt_changed) {
10948 ret = intel_color_check(crtc, crtc_state);
10949 if (ret)
10950 return ret;
e7852a4b
LL
10951
10952 /*
10953 * Changing color management on Intel hardware is
10954 * handled as part of planes update.
10955 */
10956 crtc_state->planes_changed = true;
82cf435b
LL
10957 }
10958
e435d6e5 10959 ret = 0;
86c8bbbe 10960 if (dev_priv->display.compute_pipe_wm) {
e3bddded 10961 ret = dev_priv->display.compute_pipe_wm(pipe_config);
ed4a6a7c
MR
10962 if (ret) {
10963 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
10964 return ret;
10965 }
10966 }
10967
10968 if (dev_priv->display.compute_intermediate_wm &&
10969 !to_intel_atomic_state(state)->skip_intermediate_wm) {
10970 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
10971 return 0;
10972
10973 /*
10974 * Calculate 'intermediate' watermarks that satisfy both the
10975 * old state and the new state. We can program these
10976 * immediately.
10977 */
6315b5d3 10978 ret = dev_priv->display.compute_intermediate_wm(dev,
ed4a6a7c
MR
10979 intel_crtc,
10980 pipe_config);
10981 if (ret) {
10982 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
86c8bbbe 10983 return ret;
ed4a6a7c 10984 }
e3d5457c
VS
10985 } else if (dev_priv->display.compute_intermediate_wm) {
10986 if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9)
10987 pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal;
86c8bbbe
MR
10988 }
10989
6315b5d3 10990 if (INTEL_GEN(dev_priv) >= 9) {
e435d6e5
ML
10991 if (mode_changed)
10992 ret = skl_update_scaler_crtc(pipe_config);
10993
10994 if (!ret)
6ebc6923 10995 ret = intel_atomic_setup_scalers(dev_priv, intel_crtc,
e435d6e5
ML
10996 pipe_config);
10997 }
10998
10999 return ret;
6d3a1ce7
ML
11000}
11001
65b38e0d 11002static const struct drm_crtc_helper_funcs intel_helper_funcs = {
5a21b665
DV
11003 .atomic_begin = intel_begin_crtc_commit,
11004 .atomic_flush = intel_finish_crtc_commit,
6d3a1ce7 11005 .atomic_check = intel_crtc_atomic_check,
f6e5b160
CW
11006};
11007
d29b2f9d
ACO
11008static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11009{
11010 struct intel_connector *connector;
f9e905ca 11011 struct drm_connector_list_iter conn_iter;
d29b2f9d 11012
f9e905ca
DV
11013 drm_connector_list_iter_begin(dev, &conn_iter);
11014 for_each_intel_connector_iter(connector, &conn_iter) {
8863dc7f
DV
11015 if (connector->base.state->crtc)
11016 drm_connector_unreference(&connector->base);
11017
d29b2f9d
ACO
11018 if (connector->base.encoder) {
11019 connector->base.state->best_encoder =
11020 connector->base.encoder;
11021 connector->base.state->crtc =
11022 connector->base.encoder->crtc;
8863dc7f
DV
11023
11024 drm_connector_reference(&connector->base);
d29b2f9d
ACO
11025 } else {
11026 connector->base.state->best_encoder = NULL;
11027 connector->base.state->crtc = NULL;
11028 }
11029 }
f9e905ca 11030 drm_connector_list_iter_end(&conn_iter);
d29b2f9d
ACO
11031}
11032
050f7aeb 11033static void
eba905b2 11034connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11035 struct intel_crtc_state *pipe_config)
050f7aeb 11036{
6a2a5c5d 11037 const struct drm_display_info *info = &connector->base.display_info;
050f7aeb
DV
11038 int bpp = pipe_config->pipe_bpp;
11039
11040 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
6a2a5c5d
VS
11041 connector->base.base.id,
11042 connector->base.name);
050f7aeb
DV
11043
11044 /* Don't use an invalid EDID bpc value */
6a2a5c5d 11045 if (info->bpc != 0 && info->bpc * 3 < bpp) {
050f7aeb 11046 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
6a2a5c5d
VS
11047 bpp, info->bpc * 3);
11048 pipe_config->pipe_bpp = info->bpc * 3;
050f7aeb
DV
11049 }
11050
196f954e 11051 /* Clamp bpp to 8 on screens without EDID 1.4 */
6a2a5c5d 11052 if (info->bpc == 0 && bpp > 24) {
196f954e
MK
11053 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11054 bpp);
11055 pipe_config->pipe_bpp = 24;
050f7aeb
DV
11056 }
11057}
11058
4e53c2e0 11059static int
050f7aeb 11060compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11061 struct intel_crtc_state *pipe_config)
4e53c2e0 11062{
9beb5fea 11063 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1486017f 11064 struct drm_atomic_state *state;
da3ced29
ACO
11065 struct drm_connector *connector;
11066 struct drm_connector_state *connector_state;
1486017f 11067 int bpp, i;
4e53c2e0 11068
9beb5fea
TU
11069 if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
11070 IS_CHERRYVIEW(dev_priv)))
4e53c2e0 11071 bpp = 10*3;
9beb5fea 11072 else if (INTEL_GEN(dev_priv) >= 5)
d328c9d7
DV
11073 bpp = 12*3;
11074 else
11075 bpp = 8*3;
11076
4e53c2e0 11077
4e53c2e0
DV
11078 pipe_config->pipe_bpp = bpp;
11079
1486017f
ACO
11080 state = pipe_config->base.state;
11081
4e53c2e0 11082 /* Clamp display bpp to EDID value */
aa5e9b47 11083 for_each_new_connector_in_state(state, connector, connector_state, i) {
da3ced29 11084 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV
11085 continue;
11086
da3ced29
ACO
11087 connected_sink_compute_bpp(to_intel_connector(connector),
11088 pipe_config);
4e53c2e0
DV
11089 }
11090
11091 return bpp;
11092}
11093
644db711
DV
11094static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11095{
11096 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11097 "type: 0x%x flags: 0x%x\n",
1342830c 11098 mode->crtc_clock,
644db711
DV
11099 mode->crtc_hdisplay, mode->crtc_hsync_start,
11100 mode->crtc_hsync_end, mode->crtc_htotal,
11101 mode->crtc_vdisplay, mode->crtc_vsync_start,
11102 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11103}
11104
f6982332
TU
11105static inline void
11106intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id,
a4309657 11107 unsigned int lane_count, struct intel_link_m_n *m_n)
f6982332 11108{
a4309657
TU
11109 DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11110 id, lane_count,
f6982332
TU
11111 m_n->gmch_m, m_n->gmch_n,
11112 m_n->link_m, m_n->link_n, m_n->tu);
11113}
11114
c0b03411 11115static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11116 struct intel_crtc_state *pipe_config,
c0b03411
DV
11117 const char *context)
11118{
6a60cd87 11119 struct drm_device *dev = crtc->base.dev;
4f8036a2 11120 struct drm_i915_private *dev_priv = to_i915(dev);
6a60cd87
CK
11121 struct drm_plane *plane;
11122 struct intel_plane *intel_plane;
11123 struct intel_plane_state *state;
11124 struct drm_framebuffer *fb;
11125
66766e4f
TU
11126 DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n",
11127 crtc->base.base.id, crtc->base.name, context);
c0b03411 11128
2c89429e
TU
11129 DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n",
11130 transcoder_name(pipe_config->cpu_transcoder),
c0b03411 11131 pipe_config->pipe_bpp, pipe_config->dither);
a4309657
TU
11132
11133 if (pipe_config->has_pch_encoder)
11134 intel_dump_m_n_config(pipe_config, "fdi",
11135 pipe_config->fdi_lanes,
11136 &pipe_config->fdi_m_n);
f6982332
TU
11137
11138 if (intel_crtc_has_dp_encoder(pipe_config)) {
a4309657
TU
11139 intel_dump_m_n_config(pipe_config, "dp m_n",
11140 pipe_config->lane_count, &pipe_config->dp_m_n);
d806e682
TU
11141 if (pipe_config->has_drrs)
11142 intel_dump_m_n_config(pipe_config, "dp m2_n2",
11143 pipe_config->lane_count,
11144 &pipe_config->dp_m2_n2);
f6982332 11145 }
b95af8be 11146
55072d19 11147 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
2c89429e 11148 pipe_config->has_audio, pipe_config->has_infoframe);
55072d19 11149
c0b03411 11150 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11151 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11152 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO
11153 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11154 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
a7d1b3f4 11155 DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n",
2c89429e 11156 pipe_config->port_clock,
a7d1b3f4
VS
11157 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
11158 pipe_config->pixel_rate);
dd2f616d
TU
11159
11160 if (INTEL_GEN(dev_priv) >= 9)
11161 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11162 crtc->num_scalers,
11163 pipe_config->scaler_state.scaler_users,
11164 pipe_config->scaler_state.scaler_id);
a74f8375
TU
11165
11166 if (HAS_GMCH_DISPLAY(dev_priv))
11167 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11168 pipe_config->gmch_pfit.control,
11169 pipe_config->gmch_pfit.pgm_ratios,
11170 pipe_config->gmch_pfit.lvds_border_bits);
11171 else
11172 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11173 pipe_config->pch_pfit.pos,
11174 pipe_config->pch_pfit.size,
08c4d7fc 11175 enableddisabled(pipe_config->pch_pfit.enabled));
a74f8375 11176
2c89429e
TU
11177 DRM_DEBUG_KMS("ips: %i, double wide: %i\n",
11178 pipe_config->ips_enabled, pipe_config->double_wide);
6a60cd87 11179
f50b79f0 11180 intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state);
415ff0f6 11181
6a60cd87
CK
11182 DRM_DEBUG_KMS("planes on this crtc\n");
11183 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
b3c11ac2 11184 struct drm_format_name_buf format_name;
6a60cd87
CK
11185 intel_plane = to_intel_plane(plane);
11186 if (intel_plane->pipe != crtc->pipe)
11187 continue;
11188
11189 state = to_intel_plane_state(plane->state);
11190 fb = state->base.fb;
11191 if (!fb) {
1d577e02
VS
11192 DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n",
11193 plane->base.id, plane->name, state->scaler_id);
6a60cd87
CK
11194 continue;
11195 }
11196
dd2f616d
TU
11197 DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n",
11198 plane->base.id, plane->name,
b3c11ac2 11199 fb->base.id, fb->width, fb->height,
438b74a5 11200 drm_get_format_name(fb->format->format, &format_name));
dd2f616d
TU
11201 if (INTEL_GEN(dev_priv) >= 9)
11202 DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n",
11203 state->scaler_id,
11204 state->base.src.x1 >> 16,
11205 state->base.src.y1 >> 16,
11206 drm_rect_width(&state->base.src) >> 16,
11207 drm_rect_height(&state->base.src) >> 16,
11208 state->base.dst.x1, state->base.dst.y1,
11209 drm_rect_width(&state->base.dst),
11210 drm_rect_height(&state->base.dst));
6a60cd87 11211 }
c0b03411
DV
11212}
11213
5448a00d 11214static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 11215{
5448a00d 11216 struct drm_device *dev = state->dev;
da3ced29 11217 struct drm_connector *connector;
00f0b378 11218 unsigned int used_ports = 0;
477321e0 11219 unsigned int used_mst_ports = 0;
00f0b378
VS
11220
11221 /*
11222 * Walk the connector list instead of the encoder
11223 * list to detect the problem on ddi platforms
11224 * where there's just one encoder per digital port.
11225 */
0bff4858
VS
11226 drm_for_each_connector(connector, dev) {
11227 struct drm_connector_state *connector_state;
11228 struct intel_encoder *encoder;
11229
11230 connector_state = drm_atomic_get_existing_connector_state(state, connector);
11231 if (!connector_state)
11232 connector_state = connector->state;
11233
5448a00d 11234 if (!connector_state->best_encoder)
00f0b378
VS
11235 continue;
11236
5448a00d
ACO
11237 encoder = to_intel_encoder(connector_state->best_encoder);
11238
11239 WARN_ON(!connector_state->crtc);
00f0b378
VS
11240
11241 switch (encoder->type) {
11242 unsigned int port_mask;
11243 case INTEL_OUTPUT_UNKNOWN:
4f8036a2 11244 if (WARN_ON(!HAS_DDI(to_i915(dev))))
00f0b378 11245 break;
cca0502b 11246 case INTEL_OUTPUT_DP:
00f0b378
VS
11247 case INTEL_OUTPUT_HDMI:
11248 case INTEL_OUTPUT_EDP:
11249 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11250
11251 /* the same port mustn't appear more than once */
11252 if (used_ports & port_mask)
11253 return false;
11254
11255 used_ports |= port_mask;
477321e0
VS
11256 break;
11257 case INTEL_OUTPUT_DP_MST:
11258 used_mst_ports |=
11259 1 << enc_to_mst(&encoder->base)->primary->port;
11260 break;
00f0b378
VS
11261 default:
11262 break;
11263 }
11264 }
11265
477321e0
VS
11266 /* can't mix MST and SST/HDMI on the same port */
11267 if (used_ports & used_mst_ports)
11268 return false;
11269
00f0b378
VS
11270 return true;
11271}
11272
83a57153
ACO
11273static void
11274clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11275{
ff32c54e
VS
11276 struct drm_i915_private *dev_priv =
11277 to_i915(crtc_state->base.crtc->dev);
663a3640 11278 struct intel_crtc_scaler_state scaler_state;
4978cc93 11279 struct intel_dpll_hw_state dpll_hw_state;
8106ddbd 11280 struct intel_shared_dpll *shared_dpll;
ff32c54e 11281 struct intel_crtc_wm_state wm_state;
c4e2d043 11282 bool force_thru;
83a57153 11283
7546a384
ACO
11284 /* FIXME: before the switch to atomic started, a new pipe_config was
11285 * kzalloc'd. Code that depends on any field being zero should be
11286 * fixed, so that the crtc_state can be safely duplicated. For now,
11287 * only fields that are know to not cause problems are preserved. */
11288
663a3640 11289 scaler_state = crtc_state->scaler_state;
4978cc93
ACO
11290 shared_dpll = crtc_state->shared_dpll;
11291 dpll_hw_state = crtc_state->dpll_hw_state;
c4e2d043 11292 force_thru = crtc_state->pch_pfit.force_thru;
ff32c54e
VS
11293 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11294 wm_state = crtc_state->wm;
4978cc93 11295
d2fa80a5
CW
11296 /* Keep base drm_crtc_state intact, only clear our extended struct */
11297 BUILD_BUG_ON(offsetof(struct intel_crtc_state, base));
11298 memset(&crtc_state->base + 1, 0,
11299 sizeof(*crtc_state) - sizeof(crtc_state->base));
4978cc93 11300
663a3640 11301 crtc_state->scaler_state = scaler_state;
4978cc93
ACO
11302 crtc_state->shared_dpll = shared_dpll;
11303 crtc_state->dpll_hw_state = dpll_hw_state;
c4e2d043 11304 crtc_state->pch_pfit.force_thru = force_thru;
ff32c54e
VS
11305 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
11306 crtc_state->wm = wm_state;
83a57153
ACO
11307}
11308
548ee15b 11309static int
b8cecdf5 11310intel_modeset_pipe_config(struct drm_crtc *crtc,
b359283a 11311 struct intel_crtc_state *pipe_config)
ee7b9f93 11312{
b359283a 11313 struct drm_atomic_state *state = pipe_config->base.state;
7758a113 11314 struct intel_encoder *encoder;
da3ced29 11315 struct drm_connector *connector;
0b901879 11316 struct drm_connector_state *connector_state;
d328c9d7 11317 int base_bpp, ret = -EINVAL;
0b901879 11318 int i;
e29c22c0 11319 bool retry = true;
ee7b9f93 11320
83a57153 11321 clear_intel_crtc_state(pipe_config);
7758a113 11322
e143a21c
DV
11323 pipe_config->cpu_transcoder =
11324 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 11325
2960bc9c
ID
11326 /*
11327 * Sanitize sync polarity flags based on requested ones. If neither
11328 * positive or negative polarity is requested, treat this as meaning
11329 * negative polarity.
11330 */
2d112de7 11331 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 11332 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 11333 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 11334
2d112de7 11335 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 11336 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 11337 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 11338
d328c9d7
DV
11339 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11340 pipe_config);
11341 if (base_bpp < 0)
4e53c2e0
DV
11342 goto fail;
11343
e41a56be
VS
11344 /*
11345 * Determine the real pipe dimensions. Note that stereo modes can
11346 * increase the actual pipe size due to the frame doubling and
11347 * insertion of additional space for blanks between the frame. This
11348 * is stored in the crtc timings. We use the requested mode to do this
11349 * computation to clearly distinguish it from the adjusted mode, which
11350 * can be changed by the connectors in the below retry loop.
11351 */
196cd5d3 11352 drm_mode_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP
11353 &pipe_config->pipe_src_w,
11354 &pipe_config->pipe_src_h);
e41a56be 11355
aa5e9b47 11356 for_each_new_connector_in_state(state, connector, connector_state, i) {
253c84c8
VS
11357 if (connector_state->crtc != crtc)
11358 continue;
11359
11360 encoder = to_intel_encoder(connector_state->best_encoder);
11361
e25148d0
VS
11362 if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) {
11363 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11364 goto fail;
11365 }
11366
253c84c8
VS
11367 /*
11368 * Determine output_types before calling the .compute_config()
11369 * hooks so that the hooks can use this information safely.
11370 */
11371 pipe_config->output_types |= 1 << encoder->type;
11372 }
11373
e29c22c0 11374encoder_retry:
ef1b460d 11375 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 11376 pipe_config->port_clock = 0;
ef1b460d 11377 pipe_config->pixel_multiplier = 1;
ff9a6750 11378
135c81b8 11379 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO
11380 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11381 CRTC_STEREO_DOUBLE);
135c81b8 11382
7758a113
DV
11383 /* Pass our mode to the connectors and the CRTC to give them a chance to
11384 * adjust it according to limitations or connector properties, and also
11385 * a chance to reject the mode entirely.
47f1c6c9 11386 */
aa5e9b47 11387 for_each_new_connector_in_state(state, connector, connector_state, i) {
0b901879 11388 if (connector_state->crtc != crtc)
7758a113 11389 continue;
7ae89233 11390
0b901879
ACO
11391 encoder = to_intel_encoder(connector_state->best_encoder);
11392
0a478c27 11393 if (!(encoder->compute_config(encoder, pipe_config, connector_state))) {
efea6e8e 11394 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV
11395 goto fail;
11396 }
ee7b9f93 11397 }
47f1c6c9 11398
ff9a6750
DV
11399 /* Set default port clock if not overwritten by the encoder. Needs to be
11400 * done afterwards in case the encoder adjusts the mode. */
11401 if (!pipe_config->port_clock)
2d112de7 11402 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 11403 * pipe_config->pixel_multiplier;
ff9a6750 11404
a43f6e0f 11405 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 11406 if (ret < 0) {
7758a113
DV
11407 DRM_DEBUG_KMS("CRTC fixup failed\n");
11408 goto fail;
ee7b9f93 11409 }
e29c22c0
DV
11410
11411 if (ret == RETRY) {
11412 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11413 ret = -EINVAL;
11414 goto fail;
11415 }
11416
11417 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11418 retry = false;
11419 goto encoder_retry;
11420 }
11421
e8fa4270 11422 /* Dithering seems to not pass-through bits correctly when it should, so
611032bf
MN
11423 * only enable it on 6bpc panels and when its not a compliance
11424 * test requesting 6bpc video pattern.
11425 */
11426 pipe_config->dither = (pipe_config->pipe_bpp == 6*3) &&
11427 !pipe_config->dither_force_disable;
62f0ace5 11428 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 11429 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 11430
7758a113 11431fail:
548ee15b 11432 return ret;
ee7b9f93 11433}
47f1c6c9 11434
ea9d758d 11435static void
4740b0f2 11436intel_modeset_update_crtc_state(struct drm_atomic_state *state)
ea9d758d 11437{
0a9ab303 11438 struct drm_crtc *crtc;
aa5e9b47 11439 struct drm_crtc_state *new_crtc_state;
8a75d157 11440 int i;
ea9d758d 11441
7668851f 11442 /* Double check state. */
aa5e9b47
ML
11443 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
11444 to_intel_crtc(crtc)->config = to_intel_crtc_state(new_crtc_state);
fc467a22
ML
11445
11446 /* Update hwmode for vblank functions */
aa5e9b47
ML
11447 if (new_crtc_state->active)
11448 crtc->hwmode = new_crtc_state->adjusted_mode;
fc467a22
ML
11449 else
11450 crtc->hwmode.crtc_clock = 0;
61067a5e
ML
11451
11452 /*
11453 * Update legacy state to satisfy fbc code. This can
11454 * be removed when fbc uses the atomic state.
11455 */
11456 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
11457 struct drm_plane_state *plane_state = crtc->primary->state;
11458
11459 crtc->primary->fb = plane_state->fb;
11460 crtc->x = plane_state->src_x >> 16;
11461 crtc->y = plane_state->src_y >> 16;
11462 }
ea9d758d 11463 }
ea9d758d
DV
11464}
11465
3bd26263 11466static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 11467{
3bd26263 11468 int diff;
f1f644dc
JB
11469
11470 if (clock1 == clock2)
11471 return true;
11472
11473 if (!clock1 || !clock2)
11474 return false;
11475
11476 diff = abs(clock1 - clock2);
11477
11478 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11479 return true;
11480
11481 return false;
11482}
11483
cfb23ed6
ML
11484static bool
11485intel_compare_m_n(unsigned int m, unsigned int n,
11486 unsigned int m2, unsigned int n2,
11487 bool exact)
11488{
11489 if (m == m2 && n == n2)
11490 return true;
11491
11492 if (exact || !m || !n || !m2 || !n2)
11493 return false;
11494
11495 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
11496
31d10b57
ML
11497 if (n > n2) {
11498 while (n > n2) {
cfb23ed6
ML
11499 m2 <<= 1;
11500 n2 <<= 1;
11501 }
31d10b57
ML
11502 } else if (n < n2) {
11503 while (n < n2) {
cfb23ed6
ML
11504 m <<= 1;
11505 n <<= 1;
11506 }
11507 }
11508
31d10b57
ML
11509 if (n != n2)
11510 return false;
11511
11512 return intel_fuzzy_clock_check(m, m2);
cfb23ed6
ML
11513}
11514
11515static bool
11516intel_compare_link_m_n(const struct intel_link_m_n *m_n,
11517 struct intel_link_m_n *m2_n2,
11518 bool adjust)
11519{
11520 if (m_n->tu == m2_n2->tu &&
11521 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
11522 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
11523 intel_compare_m_n(m_n->link_m, m_n->link_n,
11524 m2_n2->link_m, m2_n2->link_n, !adjust)) {
11525 if (adjust)
11526 *m2_n2 = *m_n;
11527
11528 return true;
11529 }
11530
11531 return false;
11532}
11533
4e8048f8
TU
11534static void __printf(3, 4)
11535pipe_config_err(bool adjust, const char *name, const char *format, ...)
11536{
11537 char *level;
11538 unsigned int category;
11539 struct va_format vaf;
11540 va_list args;
11541
11542 if (adjust) {
11543 level = KERN_DEBUG;
11544 category = DRM_UT_KMS;
11545 } else {
11546 level = KERN_ERR;
11547 category = DRM_UT_NONE;
11548 }
11549
11550 va_start(args, format);
11551 vaf.fmt = format;
11552 vaf.va = &args;
11553
11554 drm_printk(level, category, "mismatch in %s %pV", name, &vaf);
11555
11556 va_end(args);
11557}
11558
0e8ffe1b 11559static bool
6315b5d3 11560intel_pipe_config_compare(struct drm_i915_private *dev_priv,
5cec258b 11561 struct intel_crtc_state *current_config,
cfb23ed6
ML
11562 struct intel_crtc_state *pipe_config,
11563 bool adjust)
0e8ffe1b 11564{
cfb23ed6
ML
11565 bool ret = true;
11566
66e985c0
DV
11567#define PIPE_CONF_CHECK_X(name) \
11568 if (current_config->name != pipe_config->name) { \
4e8048f8 11569 pipe_config_err(adjust, __stringify(name), \
66e985c0
DV
11570 "(expected 0x%08x, found 0x%08x)\n", \
11571 current_config->name, \
11572 pipe_config->name); \
cfb23ed6 11573 ret = false; \
66e985c0
DV
11574 }
11575
08a24034
DV
11576#define PIPE_CONF_CHECK_I(name) \
11577 if (current_config->name != pipe_config->name) { \
4e8048f8 11578 pipe_config_err(adjust, __stringify(name), \
08a24034
DV
11579 "(expected %i, found %i)\n", \
11580 current_config->name, \
11581 pipe_config->name); \
cfb23ed6
ML
11582 ret = false; \
11583 }
11584
8106ddbd
ACO
11585#define PIPE_CONF_CHECK_P(name) \
11586 if (current_config->name != pipe_config->name) { \
4e8048f8 11587 pipe_config_err(adjust, __stringify(name), \
8106ddbd
ACO
11588 "(expected %p, found %p)\n", \
11589 current_config->name, \
11590 pipe_config->name); \
11591 ret = false; \
11592 }
11593
cfb23ed6
ML
11594#define PIPE_CONF_CHECK_M_N(name) \
11595 if (!intel_compare_link_m_n(&current_config->name, \
11596 &pipe_config->name,\
11597 adjust)) { \
4e8048f8 11598 pipe_config_err(adjust, __stringify(name), \
cfb23ed6
ML
11599 "(expected tu %i gmch %i/%i link %i/%i, " \
11600 "found tu %i, gmch %i/%i link %i/%i)\n", \
11601 current_config->name.tu, \
11602 current_config->name.gmch_m, \
11603 current_config->name.gmch_n, \
11604 current_config->name.link_m, \
11605 current_config->name.link_n, \
11606 pipe_config->name.tu, \
11607 pipe_config->name.gmch_m, \
11608 pipe_config->name.gmch_n, \
11609 pipe_config->name.link_m, \
11610 pipe_config->name.link_n); \
11611 ret = false; \
11612 }
11613
55c561a7
DV
11614/* This is required for BDW+ where there is only one set of registers for
11615 * switching between high and low RR.
11616 * This macro can be used whenever a comparison has to be made between one
11617 * hw state and multiple sw state variables.
11618 */
cfb23ed6
ML
11619#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
11620 if (!intel_compare_link_m_n(&current_config->name, \
11621 &pipe_config->name, adjust) && \
11622 !intel_compare_link_m_n(&current_config->alt_name, \
11623 &pipe_config->name, adjust)) { \
4e8048f8 11624 pipe_config_err(adjust, __stringify(name), \
cfb23ed6
ML
11625 "(expected tu %i gmch %i/%i link %i/%i, " \
11626 "or tu %i gmch %i/%i link %i/%i, " \
11627 "found tu %i, gmch %i/%i link %i/%i)\n", \
11628 current_config->name.tu, \
11629 current_config->name.gmch_m, \
11630 current_config->name.gmch_n, \
11631 current_config->name.link_m, \
11632 current_config->name.link_n, \
11633 current_config->alt_name.tu, \
11634 current_config->alt_name.gmch_m, \
11635 current_config->alt_name.gmch_n, \
11636 current_config->alt_name.link_m, \
11637 current_config->alt_name.link_n, \
11638 pipe_config->name.tu, \
11639 pipe_config->name.gmch_m, \
11640 pipe_config->name.gmch_n, \
11641 pipe_config->name.link_m, \
11642 pipe_config->name.link_n); \
11643 ret = false; \
88adfff1
DV
11644 }
11645
1bd1bd80
DV
11646#define PIPE_CONF_CHECK_FLAGS(name, mask) \
11647 if ((current_config->name ^ pipe_config->name) & (mask)) { \
4e8048f8
TU
11648 pipe_config_err(adjust, __stringify(name), \
11649 "(%x) (expected %i, found %i)\n", \
11650 (mask), \
1bd1bd80
DV
11651 current_config->name & (mask), \
11652 pipe_config->name & (mask)); \
cfb23ed6 11653 ret = false; \
1bd1bd80
DV
11654 }
11655
5e550656
VS
11656#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11657 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
4e8048f8 11658 pipe_config_err(adjust, __stringify(name), \
5e550656
VS
11659 "(expected %i, found %i)\n", \
11660 current_config->name, \
11661 pipe_config->name); \
cfb23ed6 11662 ret = false; \
5e550656
VS
11663 }
11664
bb760063
DV
11665#define PIPE_CONF_QUIRK(quirk) \
11666 ((current_config->quirks | pipe_config->quirks) & (quirk))
11667
eccb140b
DV
11668 PIPE_CONF_CHECK_I(cpu_transcoder);
11669
08a24034
DV
11670 PIPE_CONF_CHECK_I(has_pch_encoder);
11671 PIPE_CONF_CHECK_I(fdi_lanes);
cfb23ed6 11672 PIPE_CONF_CHECK_M_N(fdi_m_n);
08a24034 11673
90a6b7b0 11674 PIPE_CONF_CHECK_I(lane_count);
95a7a2ae 11675 PIPE_CONF_CHECK_X(lane_lat_optim_mask);
b95af8be 11676
6315b5d3 11677 if (INTEL_GEN(dev_priv) < 8) {
cfb23ed6
ML
11678 PIPE_CONF_CHECK_M_N(dp_m_n);
11679
cfb23ed6
ML
11680 if (current_config->has_drrs)
11681 PIPE_CONF_CHECK_M_N(dp_m2_n2);
11682 } else
11683 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
eb14cb74 11684
253c84c8 11685 PIPE_CONF_CHECK_X(output_types);
a65347ba 11686
2d112de7
ACO
11687 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11688 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11689 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11690 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11691 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11692 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 11693
2d112de7
ACO
11694 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11695 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11696 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11697 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11698 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11699 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 11700
c93f54cf 11701 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 11702 PIPE_CONF_CHECK_I(has_hdmi_sink);
772c2a51 11703 if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
920a14b2 11704 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
b5a9fa09 11705 PIPE_CONF_CHECK_I(limited_color_range);
15953637
SS
11706
11707 PIPE_CONF_CHECK_I(hdmi_scrambling);
11708 PIPE_CONF_CHECK_I(hdmi_high_tmds_clock_ratio);
e43823ec 11709 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 11710
9ed109a7
DV
11711 PIPE_CONF_CHECK_I(has_audio);
11712
2d112de7 11713 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV
11714 DRM_MODE_FLAG_INTERLACE);
11715
bb760063 11716 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 11717 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11718 DRM_MODE_FLAG_PHSYNC);
2d112de7 11719 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11720 DRM_MODE_FLAG_NHSYNC);
2d112de7 11721 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11722 DRM_MODE_FLAG_PVSYNC);
2d112de7 11723 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV
11724 DRM_MODE_FLAG_NVSYNC);
11725 }
045ac3b5 11726
333b8ca8 11727 PIPE_CONF_CHECK_X(gmch_pfit.control);
e2ff2d4a 11728 /* pfit ratios are autocomputed by the hw on gen4+ */
6315b5d3 11729 if (INTEL_GEN(dev_priv) < 4)
7f7d8dd6 11730 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
333b8ca8 11731 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
9953599b 11732
bfd16b2a
ML
11733 if (!adjust) {
11734 PIPE_CONF_CHECK_I(pipe_src_w);
11735 PIPE_CONF_CHECK_I(pipe_src_h);
11736
11737 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11738 if (current_config->pch_pfit.enabled) {
11739 PIPE_CONF_CHECK_X(pch_pfit.pos);
11740 PIPE_CONF_CHECK_X(pch_pfit.size);
11741 }
2fa2fe9a 11742
7aefe2b5 11743 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
a7d1b3f4 11744 PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate);
7aefe2b5 11745 }
a1b2278e 11746
e59150dc 11747 /* BDW+ don't expose a synchronous way to read the state */
772c2a51 11748 if (IS_HASWELL(dev_priv))
e59150dc 11749 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 11750
282740f7
VS
11751 PIPE_CONF_CHECK_I(double_wide);
11752
8106ddbd 11753 PIPE_CONF_CHECK_P(shared_dpll);
66e985c0 11754 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 11755 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV
11756 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11757 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 11758 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
00490c22 11759 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
3f4cd19f
DL
11760 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11761 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11762 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 11763
47eacbab
VS
11764 PIPE_CONF_CHECK_X(dsi_pll.ctrl);
11765 PIPE_CONF_CHECK_X(dsi_pll.div);
11766
9beb5fea 11767 if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5)
42571aef
VS
11768 PIPE_CONF_CHECK_I(pipe_bpp);
11769
2d112de7 11770 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 11771 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 11772
66e985c0 11773#undef PIPE_CONF_CHECK_X
08a24034 11774#undef PIPE_CONF_CHECK_I
8106ddbd 11775#undef PIPE_CONF_CHECK_P
1bd1bd80 11776#undef PIPE_CONF_CHECK_FLAGS
5e550656 11777#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 11778#undef PIPE_CONF_QUIRK
88adfff1 11779
cfb23ed6 11780 return ret;
0e8ffe1b
DV
11781}
11782
e3b247da
VS
11783static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
11784 const struct intel_crtc_state *pipe_config)
11785{
11786 if (pipe_config->has_pch_encoder) {
21a727b3 11787 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
e3b247da
VS
11788 &pipe_config->fdi_m_n);
11789 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
11790
11791 /*
11792 * FDI already provided one idea for the dotclock.
11793 * Yell if the encoder disagrees.
11794 */
11795 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
11796 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11797 fdi_dotclock, dotclock);
11798 }
11799}
11800
c0ead703
ML
11801static void verify_wm_state(struct drm_crtc *crtc,
11802 struct drm_crtc_state *new_state)
08db6652 11803{
6315b5d3 11804 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
08db6652 11805 struct skl_ddb_allocation hw_ddb, *sw_ddb;
3de8a14c 11806 struct skl_pipe_wm hw_wm, *sw_wm;
11807 struct skl_plane_wm *hw_plane_wm, *sw_plane_wm;
11808 struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
e7c84544
ML
11809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11810 const enum pipe pipe = intel_crtc->pipe;
3de8a14c 11811 int plane, level, max_level = ilk_wm_max_level(dev_priv);
08db6652 11812
6315b5d3 11813 if (INTEL_GEN(dev_priv) < 9 || !new_state->active)
08db6652
DL
11814 return;
11815
3de8a14c 11816 skl_pipe_wm_get_hw_state(crtc, &hw_wm);
03af79e0 11817 sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal;
3de8a14c 11818
08db6652
DL
11819 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11820 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11821
e7c84544 11822 /* planes */
8b364b41 11823 for_each_universal_plane(dev_priv, pipe, plane) {
3de8a14c 11824 hw_plane_wm = &hw_wm.planes[plane];
11825 sw_plane_wm = &sw_wm->planes[plane];
08db6652 11826
3de8a14c 11827 /* Watermarks */
11828 for (level = 0; level <= max_level; level++) {
11829 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11830 &sw_plane_wm->wm[level]))
11831 continue;
11832
11833 DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11834 pipe_name(pipe), plane + 1, level,
11835 sw_plane_wm->wm[level].plane_en,
11836 sw_plane_wm->wm[level].plane_res_b,
11837 sw_plane_wm->wm[level].plane_res_l,
11838 hw_plane_wm->wm[level].plane_en,
11839 hw_plane_wm->wm[level].plane_res_b,
11840 hw_plane_wm->wm[level].plane_res_l);
11841 }
08db6652 11842
3de8a14c 11843 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11844 &sw_plane_wm->trans_wm)) {
11845 DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11846 pipe_name(pipe), plane + 1,
11847 sw_plane_wm->trans_wm.plane_en,
11848 sw_plane_wm->trans_wm.plane_res_b,
11849 sw_plane_wm->trans_wm.plane_res_l,
11850 hw_plane_wm->trans_wm.plane_en,
11851 hw_plane_wm->trans_wm.plane_res_b,
11852 hw_plane_wm->trans_wm.plane_res_l);
11853 }
11854
11855 /* DDB */
11856 hw_ddb_entry = &hw_ddb.plane[pipe][plane];
11857 sw_ddb_entry = &sw_ddb->plane[pipe][plane];
11858
11859 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
faccd994 11860 DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n",
3de8a14c 11861 pipe_name(pipe), plane + 1,
11862 sw_ddb_entry->start, sw_ddb_entry->end,
11863 hw_ddb_entry->start, hw_ddb_entry->end);
11864 }
e7c84544 11865 }
08db6652 11866
27082493
L
11867 /*
11868 * cursor
11869 * If the cursor plane isn't active, we may not have updated it's ddb
11870 * allocation. In that case since the ddb allocation will be updated
11871 * once the plane becomes visible, we can skip this check
11872 */
11873 if (intel_crtc->cursor_addr) {
3de8a14c 11874 hw_plane_wm = &hw_wm.planes[PLANE_CURSOR];
11875 sw_plane_wm = &sw_wm->planes[PLANE_CURSOR];
11876
11877 /* Watermarks */
11878 for (level = 0; level <= max_level; level++) {
11879 if (skl_wm_level_equals(&hw_plane_wm->wm[level],
11880 &sw_plane_wm->wm[level]))
11881 continue;
11882
11883 DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11884 pipe_name(pipe), level,
11885 sw_plane_wm->wm[level].plane_en,
11886 sw_plane_wm->wm[level].plane_res_b,
11887 sw_plane_wm->wm[level].plane_res_l,
11888 hw_plane_wm->wm[level].plane_en,
11889 hw_plane_wm->wm[level].plane_res_b,
11890 hw_plane_wm->wm[level].plane_res_l);
11891 }
11892
11893 if (!skl_wm_level_equals(&hw_plane_wm->trans_wm,
11894 &sw_plane_wm->trans_wm)) {
11895 DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
11896 pipe_name(pipe),
11897 sw_plane_wm->trans_wm.plane_en,
11898 sw_plane_wm->trans_wm.plane_res_b,
11899 sw_plane_wm->trans_wm.plane_res_l,
11900 hw_plane_wm->trans_wm.plane_en,
11901 hw_plane_wm->trans_wm.plane_res_b,
11902 hw_plane_wm->trans_wm.plane_res_l);
11903 }
11904
11905 /* DDB */
11906 hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
11907 sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
27082493 11908
3de8a14c 11909 if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) {
faccd994 11910 DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n",
27082493 11911 pipe_name(pipe),
3de8a14c 11912 sw_ddb_entry->start, sw_ddb_entry->end,
11913 hw_ddb_entry->start, hw_ddb_entry->end);
27082493 11914 }
08db6652
DL
11915 }
11916}
11917
91d1b4bd 11918static void
677100ce
ML
11919verify_connector_state(struct drm_device *dev,
11920 struct drm_atomic_state *state,
11921 struct drm_crtc *crtc)
8af6cf88 11922{
35dd3c64 11923 struct drm_connector *connector;
aa5e9b47 11924 struct drm_connector_state *new_conn_state;
677100ce 11925 int i;
8af6cf88 11926
aa5e9b47 11927 for_each_new_connector_in_state(state, connector, new_conn_state, i) {
35dd3c64 11928 struct drm_encoder *encoder = connector->encoder;
ad3c558f 11929
aa5e9b47 11930 if (new_conn_state->crtc != crtc)
e7c84544
ML
11931 continue;
11932
5a21b665 11933 intel_connector_verify_state(to_intel_connector(connector));
8af6cf88 11934
aa5e9b47 11935 I915_STATE_WARN(new_conn_state->best_encoder != encoder,
35dd3c64 11936 "connector's atomic encoder doesn't match legacy encoder\n");
8af6cf88 11937 }
91d1b4bd
DV
11938}
11939
11940static void
86b04268 11941verify_encoder_state(struct drm_device *dev, struct drm_atomic_state *state)
91d1b4bd
DV
11942{
11943 struct intel_encoder *encoder;
86b04268
DV
11944 struct drm_connector *connector;
11945 struct drm_connector_state *old_conn_state, *new_conn_state;
11946 int i;
8af6cf88 11947
b2784e15 11948 for_each_intel_encoder(dev, encoder) {
86b04268 11949 bool enabled = false, found = false;
4d20cd86 11950 enum pipe pipe;
8af6cf88
DV
11951
11952 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11953 encoder->base.base.id,
8e329a03 11954 encoder->base.name);
8af6cf88 11955
86b04268
DV
11956 for_each_oldnew_connector_in_state(state, connector, old_conn_state,
11957 new_conn_state, i) {
11958 if (old_conn_state->best_encoder == &encoder->base)
11959 found = true;
11960
11961 if (new_conn_state->best_encoder != &encoder->base)
8af6cf88 11962 continue;
86b04268 11963 found = enabled = true;
ad3c558f 11964
86b04268 11965 I915_STATE_WARN(new_conn_state->crtc !=
ad3c558f
ML
11966 encoder->base.crtc,
11967 "connector's crtc doesn't match encoder crtc\n");
8af6cf88 11968 }
86b04268
DV
11969
11970 if (!found)
11971 continue;
0e32b39c 11972
e2c719b7 11973 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV
11974 "encoder's enabled state mismatch "
11975 "(expected %i, found %i)\n",
11976 !!encoder->base.crtc, enabled);
7c60d198
ML
11977
11978 if (!encoder->base.crtc) {
4d20cd86 11979 bool active;
7c60d198 11980
4d20cd86
ML
11981 active = encoder->get_hw_state(encoder, &pipe);
11982 I915_STATE_WARN(active,
11983 "encoder detached but still enabled on pipe %c.\n",
11984 pipe_name(pipe));
7c60d198 11985 }
8af6cf88 11986 }
91d1b4bd
DV
11987}
11988
11989static void
c0ead703
ML
11990verify_crtc_state(struct drm_crtc *crtc,
11991 struct drm_crtc_state *old_crtc_state,
11992 struct drm_crtc_state *new_crtc_state)
91d1b4bd 11993{
e7c84544 11994 struct drm_device *dev = crtc->dev;
fac5e23e 11995 struct drm_i915_private *dev_priv = to_i915(dev);
91d1b4bd 11996 struct intel_encoder *encoder;
e7c84544
ML
11997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11998 struct intel_crtc_state *pipe_config, *sw_config;
11999 struct drm_atomic_state *old_state;
12000 bool active;
045ac3b5 12001
e7c84544 12002 old_state = old_crtc_state->state;
ec2dc6a0 12003 __drm_atomic_helper_crtc_destroy_state(old_crtc_state);
e7c84544
ML
12004 pipe_config = to_intel_crtc_state(old_crtc_state);
12005 memset(pipe_config, 0, sizeof(*pipe_config));
12006 pipe_config->base.crtc = crtc;
12007 pipe_config->base.state = old_state;
8af6cf88 12008
78108b7c 12009 DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name);
8af6cf88 12010
e7c84544 12011 active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config);
d62cf62a 12012
e7c84544
ML
12013 /* hw state is inconsistent with the pipe quirk */
12014 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12015 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12016 active = new_crtc_state->active;
6c49f241 12017
e7c84544
ML
12018 I915_STATE_WARN(new_crtc_state->active != active,
12019 "crtc active state doesn't match with hw state "
12020 "(expected %i, found %i)\n", new_crtc_state->active, active);
0e8ffe1b 12021
e7c84544
ML
12022 I915_STATE_WARN(intel_crtc->active != new_crtc_state->active,
12023 "transitional active state does not match atomic hw state "
12024 "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active);
4d20cd86 12025
e7c84544
ML
12026 for_each_encoder_on_crtc(dev, crtc, encoder) {
12027 enum pipe pipe;
4d20cd86 12028
e7c84544
ML
12029 active = encoder->get_hw_state(encoder, &pipe);
12030 I915_STATE_WARN(active != new_crtc_state->active,
12031 "[ENCODER:%i] active %i with crtc active %i\n",
12032 encoder->base.base.id, active, new_crtc_state->active);
4d20cd86 12033
e7c84544
ML
12034 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12035 "Encoder connected to wrong pipe %c\n",
12036 pipe_name(pipe));
4d20cd86 12037
253c84c8
VS
12038 if (active) {
12039 pipe_config->output_types |= 1 << encoder->type;
e7c84544 12040 encoder->get_config(encoder, pipe_config);
253c84c8 12041 }
e7c84544 12042 }
53d9f4e9 12043
a7d1b3f4
VS
12044 intel_crtc_compute_pixel_rate(pipe_config);
12045
e7c84544
ML
12046 if (!new_crtc_state->active)
12047 return;
cfb23ed6 12048
e7c84544 12049 intel_pipe_config_sanity_check(dev_priv, pipe_config);
e3b247da 12050
e7c84544 12051 sw_config = to_intel_crtc_state(crtc->state);
6315b5d3 12052 if (!intel_pipe_config_compare(dev_priv, sw_config,
e7c84544
ML
12053 pipe_config, false)) {
12054 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12055 intel_dump_pipe_config(intel_crtc, pipe_config,
12056 "[hw state]");
12057 intel_dump_pipe_config(intel_crtc, sw_config,
12058 "[sw state]");
8af6cf88
DV
12059 }
12060}
12061
91d1b4bd 12062static void
c0ead703
ML
12063verify_single_dpll_state(struct drm_i915_private *dev_priv,
12064 struct intel_shared_dpll *pll,
12065 struct drm_crtc *crtc,
12066 struct drm_crtc_state *new_state)
91d1b4bd 12067{
91d1b4bd 12068 struct intel_dpll_hw_state dpll_hw_state;
e7c84544
ML
12069 unsigned crtc_mask;
12070 bool active;
5358901f 12071
e7c84544 12072 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
5358901f 12073
e7c84544 12074 DRM_DEBUG_KMS("%s\n", pll->name);
5358901f 12075
e7c84544 12076 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
5358901f 12077
e7c84544
ML
12078 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12079 I915_STATE_WARN(!pll->on && pll->active_mask,
12080 "pll in active use but not on in sw tracking\n");
12081 I915_STATE_WARN(pll->on && !pll->active_mask,
12082 "pll is on but not used by any active crtc\n");
12083 I915_STATE_WARN(pll->on != active,
12084 "pll on state mismatch (expected %i, found %i)\n",
12085 pll->on, active);
12086 }
5358901f 12087
e7c84544 12088 if (!crtc) {
2c42e535 12089 I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask,
e7c84544 12090 "more active pll users than references: %x vs %x\n",
2c42e535 12091 pll->active_mask, pll->state.crtc_mask);
5358901f 12092
e7c84544
ML
12093 return;
12094 }
12095
12096 crtc_mask = 1 << drm_crtc_index(crtc);
12097
12098 if (new_state->active)
12099 I915_STATE_WARN(!(pll->active_mask & crtc_mask),
12100 "pll active mismatch (expected pipe %c in active mask 0x%02x)\n",
12101 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
12102 else
12103 I915_STATE_WARN(pll->active_mask & crtc_mask,
12104 "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n",
12105 pipe_name(drm_crtc_index(crtc)), pll->active_mask);
2dd66ebd 12106
2c42e535 12107 I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask),
e7c84544 12108 "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n",
2c42e535 12109 crtc_mask, pll->state.crtc_mask);
66e985c0 12110
2c42e535 12111 I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state,
e7c84544
ML
12112 &dpll_hw_state,
12113 sizeof(dpll_hw_state)),
12114 "pll hw state mismatch\n");
12115}
12116
12117static void
c0ead703
ML
12118verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc,
12119 struct drm_crtc_state *old_crtc_state,
12120 struct drm_crtc_state *new_crtc_state)
e7c84544 12121{
fac5e23e 12122 struct drm_i915_private *dev_priv = to_i915(dev);
e7c84544
ML
12123 struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state);
12124 struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state);
12125
12126 if (new_state->shared_dpll)
c0ead703 12127 verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state);
e7c84544
ML
12128
12129 if (old_state->shared_dpll &&
12130 old_state->shared_dpll != new_state->shared_dpll) {
12131 unsigned crtc_mask = 1 << drm_crtc_index(crtc);
12132 struct intel_shared_dpll *pll = old_state->shared_dpll;
12133
12134 I915_STATE_WARN(pll->active_mask & crtc_mask,
12135 "pll active mismatch (didn't expect pipe %c in active mask)\n",
12136 pipe_name(drm_crtc_index(crtc)));
2c42e535 12137 I915_STATE_WARN(pll->state.crtc_mask & crtc_mask,
e7c84544
ML
12138 "pll enabled crtcs mismatch (found %x in enabled mask)\n",
12139 pipe_name(drm_crtc_index(crtc)));
5358901f 12140 }
8af6cf88
DV
12141}
12142
e7c84544 12143static void
c0ead703 12144intel_modeset_verify_crtc(struct drm_crtc *crtc,
677100ce
ML
12145 struct drm_atomic_state *state,
12146 struct drm_crtc_state *old_state,
12147 struct drm_crtc_state *new_state)
e7c84544 12148{
5a21b665
DV
12149 if (!needs_modeset(new_state) &&
12150 !to_intel_crtc_state(new_state)->update_pipe)
12151 return;
12152
c0ead703 12153 verify_wm_state(crtc, new_state);
677100ce 12154 verify_connector_state(crtc->dev, state, crtc);
c0ead703
ML
12155 verify_crtc_state(crtc, old_state, new_state);
12156 verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state);
e7c84544
ML
12157}
12158
12159static void
c0ead703 12160verify_disabled_dpll_state(struct drm_device *dev)
e7c84544 12161{
fac5e23e 12162 struct drm_i915_private *dev_priv = to_i915(dev);
e7c84544
ML
12163 int i;
12164
12165 for (i = 0; i < dev_priv->num_shared_dpll; i++)
c0ead703 12166 verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL);
e7c84544
ML
12167}
12168
12169static void
677100ce
ML
12170intel_modeset_verify_disabled(struct drm_device *dev,
12171 struct drm_atomic_state *state)
e7c84544 12172{
86b04268 12173 verify_encoder_state(dev, state);
677100ce 12174 verify_connector_state(dev, state, NULL);
c0ead703 12175 verify_disabled_dpll_state(dev);
e7c84544
ML
12176}
12177
80715b2f
VS
12178static void update_scanline_offset(struct intel_crtc *crtc)
12179{
4f8036a2 12180 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
80715b2f
VS
12181
12182 /*
12183 * The scanline counter increments at the leading edge of hsync.
12184 *
12185 * On most platforms it starts counting from vtotal-1 on the
12186 * first active line. That means the scanline counter value is
12187 * always one less than what we would expect. Ie. just after
12188 * start of vblank, which also occurs at start of hsync (on the
12189 * last active line), the scanline counter will read vblank_start-1.
12190 *
12191 * On gen2 the scanline counter starts counting from 1 instead
12192 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12193 * to keep the value positive), instead of adding one.
12194 *
12195 * On HSW+ the behaviour of the scanline counter depends on the output
12196 * type. For DP ports it behaves like most other platforms, but on HDMI
12197 * there's an extra 1 line difference. So we need to add two instead of
12198 * one to the value.
12199 */
4f8036a2 12200 if (IS_GEN2(dev_priv)) {
124abe07 12201 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
80715b2f
VS
12202 int vtotal;
12203
124abe07
VS
12204 vtotal = adjusted_mode->crtc_vtotal;
12205 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
80715b2f
VS
12206 vtotal /= 2;
12207
12208 crtc->scanline_offset = vtotal - 1;
4f8036a2 12209 } else if (HAS_DDI(dev_priv) &&
2d84d2b3 12210 intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) {
80715b2f
VS
12211 crtc->scanline_offset = 2;
12212 } else
12213 crtc->scanline_offset = 1;
12214}
12215
ad421372 12216static void intel_modeset_clear_plls(struct drm_atomic_state *state)
ed6739ef 12217{
225da59b 12218 struct drm_device *dev = state->dev;
ed6739ef 12219 struct drm_i915_private *dev_priv = to_i915(dev);
0a9ab303 12220 struct drm_crtc *crtc;
aa5e9b47 12221 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
0a9ab303 12222 int i;
ed6739ef
ACO
12223
12224 if (!dev_priv->display.crtc_compute_clock)
ad421372 12225 return;
ed6739ef 12226
aa5e9b47 12227 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
fb1a38a9 12228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8106ddbd 12229 struct intel_shared_dpll *old_dpll =
aa5e9b47 12230 to_intel_crtc_state(old_crtc_state)->shared_dpll;
0a9ab303 12231
aa5e9b47 12232 if (!needs_modeset(new_crtc_state))
225da59b
ACO
12233 continue;
12234
aa5e9b47 12235 to_intel_crtc_state(new_crtc_state)->shared_dpll = NULL;
fb1a38a9 12236
8106ddbd 12237 if (!old_dpll)
fb1a38a9 12238 continue;
0a9ab303 12239
a1c414ee 12240 intel_release_shared_dpll(old_dpll, intel_crtc, state);
ad421372 12241 }
ed6739ef
ACO
12242}
12243
99d736a2
ML
12244/*
12245 * This implements the workaround described in the "notes" section of the mode
12246 * set sequence documentation. When going from no pipes or single pipe to
12247 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12248 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12249 */
12250static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
12251{
12252 struct drm_crtc_state *crtc_state;
12253 struct intel_crtc *intel_crtc;
12254 struct drm_crtc *crtc;
12255 struct intel_crtc_state *first_crtc_state = NULL;
12256 struct intel_crtc_state *other_crtc_state = NULL;
12257 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
12258 int i;
12259
12260 /* look at all crtc's that are going to be enabled in during modeset */
aa5e9b47 12261 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
99d736a2
ML
12262 intel_crtc = to_intel_crtc(crtc);
12263
12264 if (!crtc_state->active || !needs_modeset(crtc_state))
12265 continue;
12266
12267 if (first_crtc_state) {
12268 other_crtc_state = to_intel_crtc_state(crtc_state);
12269 break;
12270 } else {
12271 first_crtc_state = to_intel_crtc_state(crtc_state);
12272 first_pipe = intel_crtc->pipe;
12273 }
12274 }
12275
12276 /* No workaround needed? */
12277 if (!first_crtc_state)
12278 return 0;
12279
12280 /* w/a possibly needed, check how many crtc's are already enabled. */
12281 for_each_intel_crtc(state->dev, intel_crtc) {
12282 struct intel_crtc_state *pipe_config;
12283
12284 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12285 if (IS_ERR(pipe_config))
12286 return PTR_ERR(pipe_config);
12287
12288 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
12289
12290 if (!pipe_config->base.active ||
12291 needs_modeset(&pipe_config->base))
12292 continue;
12293
12294 /* 2 or more enabled crtcs means no need for w/a */
12295 if (enabled_pipe != INVALID_PIPE)
12296 return 0;
12297
12298 enabled_pipe = intel_crtc->pipe;
12299 }
12300
12301 if (enabled_pipe != INVALID_PIPE)
12302 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
12303 else if (other_crtc_state)
12304 other_crtc_state->hsw_workaround_pipe = first_pipe;
12305
12306 return 0;
12307}
12308
8d96561a
VS
12309static int intel_lock_all_pipes(struct drm_atomic_state *state)
12310{
12311 struct drm_crtc *crtc;
12312
12313 /* Add all pipes to the state */
12314 for_each_crtc(state->dev, crtc) {
12315 struct drm_crtc_state *crtc_state;
12316
12317 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12318 if (IS_ERR(crtc_state))
12319 return PTR_ERR(crtc_state);
12320 }
12321
12322 return 0;
12323}
12324
27c329ed
ML
12325static int intel_modeset_all_pipes(struct drm_atomic_state *state)
12326{
12327 struct drm_crtc *crtc;
27c329ed 12328
8d96561a
VS
12329 /*
12330 * Add all pipes to the state, and force
12331 * a modeset on all the active ones.
12332 */
27c329ed 12333 for_each_crtc(state->dev, crtc) {
9780aad5
VS
12334 struct drm_crtc_state *crtc_state;
12335 int ret;
12336
27c329ed
ML
12337 crtc_state = drm_atomic_get_crtc_state(state, crtc);
12338 if (IS_ERR(crtc_state))
12339 return PTR_ERR(crtc_state);
12340
12341 if (!crtc_state->active || needs_modeset(crtc_state))
12342 continue;
12343
12344 crtc_state->mode_changed = true;
12345
12346 ret = drm_atomic_add_affected_connectors(state, crtc);
12347 if (ret)
9780aad5 12348 return ret;
27c329ed
ML
12349
12350 ret = drm_atomic_add_affected_planes(state, crtc);
12351 if (ret)
9780aad5 12352 return ret;
27c329ed
ML
12353 }
12354
9780aad5 12355 return 0;
27c329ed
ML
12356}
12357
c347a676 12358static int intel_modeset_checks(struct drm_atomic_state *state)
054518dd 12359{
565602d7 12360 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
fac5e23e 12361 struct drm_i915_private *dev_priv = to_i915(state->dev);
565602d7 12362 struct drm_crtc *crtc;
aa5e9b47 12363 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
565602d7 12364 int ret = 0, i;
054518dd 12365
b359283a
ML
12366 if (!check_digital_port_conflicts(state)) {
12367 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
12368 return -EINVAL;
12369 }
12370
565602d7
ML
12371 intel_state->modeset = true;
12372 intel_state->active_crtcs = dev_priv->active_crtcs;
bb0f4aab
VS
12373 intel_state->cdclk.logical = dev_priv->cdclk.logical;
12374 intel_state->cdclk.actual = dev_priv->cdclk.actual;
565602d7 12375
aa5e9b47
ML
12376 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12377 if (new_crtc_state->active)
565602d7
ML
12378 intel_state->active_crtcs |= 1 << i;
12379 else
12380 intel_state->active_crtcs &= ~(1 << i);
8b4a7d05 12381
aa5e9b47 12382 if (old_crtc_state->active != new_crtc_state->active)
8b4a7d05 12383 intel_state->active_pipe_changes |= drm_crtc_mask(crtc);
565602d7
ML
12384 }
12385
054518dd
ACO
12386 /*
12387 * See if the config requires any additional preparation, e.g.
12388 * to adjust global state with pipes off. We need to do this
12389 * here so we can get the modeset_pipe updated config for the new
12390 * mode set on this crtc. For other crtcs we need to use the
12391 * adjusted_mode bits in the crtc directly.
12392 */
27c329ed 12393 if (dev_priv->display.modeset_calc_cdclk) {
27c329ed 12394 ret = dev_priv->display.modeset_calc_cdclk(state);
c89e39f3
CT
12395 if (ret < 0)
12396 return ret;
27c329ed 12397
8d96561a 12398 /*
bb0f4aab 12399 * Writes to dev_priv->cdclk.logical must protected by
8d96561a
VS
12400 * holding all the crtc locks, even if we don't end up
12401 * touching the hardware
12402 */
bb0f4aab
VS
12403 if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical,
12404 &intel_state->cdclk.logical)) {
8d96561a
VS
12405 ret = intel_lock_all_pipes(state);
12406 if (ret < 0)
12407 return ret;
12408 }
12409
12410 /* All pipes must be switched off while we change the cdclk. */
bb0f4aab
VS
12411 if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual,
12412 &intel_state->cdclk.actual)) {
27c329ed 12413 ret = intel_modeset_all_pipes(state);
8d96561a
VS
12414 if (ret < 0)
12415 return ret;
12416 }
e8788cbc 12417
bb0f4aab
VS
12418 DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n",
12419 intel_state->cdclk.logical.cdclk,
12420 intel_state->cdclk.actual.cdclk);
e0ca7a6b 12421 } else {
bb0f4aab 12422 to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical;
e0ca7a6b 12423 }
054518dd 12424
ad421372 12425 intel_modeset_clear_plls(state);
054518dd 12426
565602d7 12427 if (IS_HASWELL(dev_priv))
ad421372 12428 return haswell_mode_set_planes_workaround(state);
99d736a2 12429
ad421372 12430 return 0;
c347a676
ACO
12431}
12432
aa363136
MR
12433/*
12434 * Handle calculation of various watermark data at the end of the atomic check
12435 * phase. The code here should be run after the per-crtc and per-plane 'check'
12436 * handlers to ensure that all derived state has been updated.
12437 */
55994c2c 12438static int calc_watermark_data(struct drm_atomic_state *state)
aa363136
MR
12439{
12440 struct drm_device *dev = state->dev;
98d39494 12441 struct drm_i915_private *dev_priv = to_i915(dev);
98d39494
MR
12442
12443 /* Is there platform-specific watermark information to calculate? */
12444 if (dev_priv->display.compute_global_watermarks)
55994c2c
MR
12445 return dev_priv->display.compute_global_watermarks(state);
12446
12447 return 0;
aa363136
MR
12448}
12449
74c090b1
ML
12450/**
12451 * intel_atomic_check - validate state object
12452 * @dev: drm device
12453 * @state: state to validate
12454 */
12455static int intel_atomic_check(struct drm_device *dev,
12456 struct drm_atomic_state *state)
c347a676 12457{
dd8b3bdb 12458 struct drm_i915_private *dev_priv = to_i915(dev);
aa363136 12459 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
c347a676 12460 struct drm_crtc *crtc;
aa5e9b47 12461 struct drm_crtc_state *old_crtc_state, *crtc_state;
c347a676 12462 int ret, i;
61333b60 12463 bool any_ms = false;
c347a676 12464
74c090b1 12465 ret = drm_atomic_helper_check_modeset(dev, state);
054518dd
ACO
12466 if (ret)
12467 return ret;
12468
aa5e9b47 12469 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, crtc_state, i) {
cfb23ed6
ML
12470 struct intel_crtc_state *pipe_config =
12471 to_intel_crtc_state(crtc_state);
1ed51de9
DV
12472
12473 /* Catch I915_MODE_FLAG_INHERITED */
aa5e9b47 12474 if (crtc_state->mode.private_flags != old_crtc_state->mode.private_flags)
1ed51de9 12475 crtc_state->mode_changed = true;
cfb23ed6 12476
af4a879e 12477 if (!needs_modeset(crtc_state))
c347a676
ACO
12478 continue;
12479
af4a879e
DV
12480 if (!crtc_state->enable) {
12481 any_ms = true;
cfb23ed6 12482 continue;
af4a879e 12483 }
cfb23ed6 12484
26495481
DV
12485 /* FIXME: For only active_changed we shouldn't need to do any
12486 * state recomputation at all. */
12487
1ed51de9
DV
12488 ret = drm_atomic_add_affected_connectors(state, crtc);
12489 if (ret)
12490 return ret;
b359283a 12491
cfb23ed6 12492 ret = intel_modeset_pipe_config(crtc, pipe_config);
25aa1c39
ML
12493 if (ret) {
12494 intel_dump_pipe_config(to_intel_crtc(crtc),
12495 pipe_config, "[failed]");
c347a676 12496 return ret;
25aa1c39 12497 }
c347a676 12498
73831236 12499 if (i915.fastboot &&
6315b5d3 12500 intel_pipe_config_compare(dev_priv,
aa5e9b47 12501 to_intel_crtc_state(old_crtc_state),
1ed51de9 12502 pipe_config, true)) {
26495481 12503 crtc_state->mode_changed = false;
aa5e9b47 12504 pipe_config->update_pipe = true;
26495481
DV
12505 }
12506
af4a879e 12507 if (needs_modeset(crtc_state))
26495481 12508 any_ms = true;
cfb23ed6 12509
af4a879e
DV
12510 ret = drm_atomic_add_affected_planes(state, crtc);
12511 if (ret)
12512 return ret;
61333b60 12513
26495481
DV
12514 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12515 needs_modeset(crtc_state) ?
12516 "[modeset]" : "[fastset]");
c347a676
ACO
12517 }
12518
61333b60
ML
12519 if (any_ms) {
12520 ret = intel_modeset_checks(state);
12521
12522 if (ret)
12523 return ret;
e0ca7a6b 12524 } else {
bb0f4aab 12525 intel_state->cdclk.logical = dev_priv->cdclk.logical;
e0ca7a6b 12526 }
76305b1a 12527
dd8b3bdb 12528 ret = drm_atomic_helper_check_planes(dev, state);
aa363136
MR
12529 if (ret)
12530 return ret;
12531
f51be2e0 12532 intel_fbc_choose_crtc(dev_priv, state);
55994c2c 12533 return calc_watermark_data(state);
054518dd
ACO
12534}
12535
5008e874 12536static int intel_atomic_prepare_commit(struct drm_device *dev,
d07f0e59 12537 struct drm_atomic_state *state)
5008e874 12538{
fac5e23e 12539 struct drm_i915_private *dev_priv = to_i915(dev);
5008e874
ML
12540 struct drm_crtc_state *crtc_state;
12541 struct drm_crtc *crtc;
12542 int i, ret;
12543
aa5e9b47 12544 for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
5a21b665 12545 if (state->legacy_cursor_update)
a6747b73
ML
12546 continue;
12547
5a21b665
DV
12548 ret = intel_crtc_wait_for_pending_flips(crtc);
12549 if (ret)
12550 return ret;
5008e874 12551
5a21b665
DV
12552 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
12553 flush_workqueue(dev_priv->wq);
d55dbd06
ML
12554 }
12555
f935675f
ML
12556 ret = mutex_lock_interruptible(&dev->struct_mutex);
12557 if (ret)
12558 return ret;
12559
5008e874 12560 ret = drm_atomic_helper_prepare_planes(dev, state);
f7e5838b 12561 mutex_unlock(&dev->struct_mutex);
7580d774 12562
5008e874
ML
12563 return ret;
12564}
12565
a2991414
ML
12566u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc)
12567{
12568 struct drm_device *dev = crtc->base.dev;
12569
12570 if (!dev->max_vblank_count)
12571 return drm_accurate_vblank_count(&crtc->base);
12572
12573 return dev->driver->get_vblank_counter(dev, crtc->pipe);
12574}
12575
5a21b665
DV
12576static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
12577 struct drm_i915_private *dev_priv,
12578 unsigned crtc_mask)
e8861675 12579{
5a21b665
DV
12580 unsigned last_vblank_count[I915_MAX_PIPES];
12581 enum pipe pipe;
12582 int ret;
e8861675 12583
5a21b665
DV
12584 if (!crtc_mask)
12585 return;
e8861675 12586
5a21b665 12587 for_each_pipe(dev_priv, pipe) {
98187836
VS
12588 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12589 pipe);
e8861675 12590
5a21b665 12591 if (!((1 << pipe) & crtc_mask))
e8861675
ML
12592 continue;
12593
e2af48c6 12594 ret = drm_crtc_vblank_get(&crtc->base);
5a21b665
DV
12595 if (WARN_ON(ret != 0)) {
12596 crtc_mask &= ~(1 << pipe);
12597 continue;
e8861675
ML
12598 }
12599
e2af48c6 12600 last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base);
e8861675
ML
12601 }
12602
5a21b665 12603 for_each_pipe(dev_priv, pipe) {
98187836
VS
12604 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
12605 pipe);
5a21b665 12606 long lret;
e8861675 12607
5a21b665
DV
12608 if (!((1 << pipe) & crtc_mask))
12609 continue;
d55dbd06 12610
5a21b665
DV
12611 lret = wait_event_timeout(dev->vblank[pipe].queue,
12612 last_vblank_count[pipe] !=
e2af48c6 12613 drm_crtc_vblank_count(&crtc->base),
5a21b665 12614 msecs_to_jiffies(50));
d55dbd06 12615
5a21b665 12616 WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe));
d55dbd06 12617
e2af48c6 12618 drm_crtc_vblank_put(&crtc->base);
d55dbd06
ML
12619 }
12620}
12621
5a21b665 12622static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
a6747b73 12623{
5a21b665
DV
12624 /* fb updated, need to unpin old fb */
12625 if (crtc_state->fb_changed)
12626 return true;
a6747b73 12627
5a21b665
DV
12628 /* wm changes, need vblank before final wm's */
12629 if (crtc_state->update_wm_post)
12630 return true;
a6747b73 12631
5eeb798b 12632 if (crtc_state->wm.need_postvbl_update)
5a21b665 12633 return true;
a6747b73 12634
5a21b665 12635 return false;
e8861675
ML
12636}
12637
896e5bb0
L
12638static void intel_update_crtc(struct drm_crtc *crtc,
12639 struct drm_atomic_state *state,
12640 struct drm_crtc_state *old_crtc_state,
aa5e9b47 12641 struct drm_crtc_state *new_crtc_state,
896e5bb0
L
12642 unsigned int *crtc_vblank_mask)
12643{
12644 struct drm_device *dev = crtc->dev;
12645 struct drm_i915_private *dev_priv = to_i915(dev);
12646 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
aa5e9b47
ML
12647 struct intel_crtc_state *pipe_config = to_intel_crtc_state(new_crtc_state);
12648 bool modeset = needs_modeset(new_crtc_state);
896e5bb0
L
12649
12650 if (modeset) {
12651 update_scanline_offset(intel_crtc);
12652 dev_priv->display.crtc_enable(pipe_config, state);
12653 } else {
aa5e9b47
ML
12654 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12655 pipe_config);
896e5bb0
L
12656 }
12657
12658 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12659 intel_fbc_enable(
12660 intel_crtc, pipe_config,
12661 to_intel_plane_state(crtc->primary->state));
12662 }
12663
12664 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
12665
12666 if (needs_vblank_wait(pipe_config))
12667 *crtc_vblank_mask |= drm_crtc_mask(crtc);
12668}
12669
12670static void intel_update_crtcs(struct drm_atomic_state *state,
12671 unsigned int *crtc_vblank_mask)
12672{
12673 struct drm_crtc *crtc;
aa5e9b47 12674 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
896e5bb0
L
12675 int i;
12676
aa5e9b47
ML
12677 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
12678 if (!new_crtc_state->active)
896e5bb0
L
12679 continue;
12680
12681 intel_update_crtc(crtc, state, old_crtc_state,
aa5e9b47 12682 new_crtc_state, crtc_vblank_mask);
896e5bb0
L
12683 }
12684}
12685
27082493
L
12686static void skl_update_crtcs(struct drm_atomic_state *state,
12687 unsigned int *crtc_vblank_mask)
12688{
0f0f74bc 12689 struct drm_i915_private *dev_priv = to_i915(state->dev);
27082493
L
12690 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
12691 struct drm_crtc *crtc;
ce0ba283 12692 struct intel_crtc *intel_crtc;
aa5e9b47 12693 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
ce0ba283 12694 struct intel_crtc_state *cstate;
27082493
L
12695 unsigned int updated = 0;
12696 bool progress;
12697 enum pipe pipe;
5eff503b
ML
12698 int i;
12699
12700 const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {};
12701
aa5e9b47 12702 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
5eff503b 12703 /* ignore allocations for crtc's that have been turned off. */
aa5e9b47 12704 if (new_crtc_state->active)
5eff503b 12705 entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb;
27082493
L
12706
12707 /*
12708 * Whenever the number of active pipes changes, we need to make sure we
12709 * update the pipes in the right order so that their ddb allocations
12710 * never overlap with eachother inbetween CRTC updates. Otherwise we'll
12711 * cause pipe underruns and other bad stuff.
12712 */
12713 do {
27082493
L
12714 progress = false;
12715
aa5e9b47 12716 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
27082493
L
12717 bool vbl_wait = false;
12718 unsigned int cmask = drm_crtc_mask(crtc);
ce0ba283
L
12719
12720 intel_crtc = to_intel_crtc(crtc);
12721 cstate = to_intel_crtc_state(crtc->state);
12722 pipe = intel_crtc->pipe;
27082493 12723
5eff503b 12724 if (updated & cmask || !cstate->base.active)
27082493 12725 continue;
5eff503b
ML
12726
12727 if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i))
27082493
L
12728 continue;
12729
12730 updated |= cmask;
5eff503b 12731 entries[i] = &cstate->wm.skl.ddb;
27082493
L
12732
12733 /*
12734 * If this is an already active pipe, it's DDB changed,
12735 * and this isn't the last pipe that needs updating
12736 * then we need to wait for a vblank to pass for the
12737 * new ddb allocation to take effect.
12738 */
ce0ba283 12739 if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb,
512b5527 12740 &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) &&
aa5e9b47 12741 !new_crtc_state->active_changed &&
27082493
L
12742 intel_state->wm_results.dirty_pipes != updated)
12743 vbl_wait = true;
12744
12745 intel_update_crtc(crtc, state, old_crtc_state,
aa5e9b47 12746 new_crtc_state, crtc_vblank_mask);
27082493
L
12747
12748 if (vbl_wait)
0f0f74bc 12749 intel_wait_for_vblank(dev_priv, pipe);
27082493
L
12750
12751 progress = true;
12752 }
12753 } while (progress);
12754}
12755
ba318c61
CW
12756static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
12757{
12758 struct intel_atomic_state *state, *next;
12759 struct llist_node *freed;
12760
12761 freed = llist_del_all(&dev_priv->atomic_helper.free_list);
12762 llist_for_each_entry_safe(state, next, freed, freed)
12763 drm_atomic_state_put(&state->base);
12764}
12765
12766static void intel_atomic_helper_free_state_worker(struct work_struct *work)
12767{
12768 struct drm_i915_private *dev_priv =
12769 container_of(work, typeof(*dev_priv), atomic_helper.free_work);
12770
12771 intel_atomic_helper_free_state(dev_priv);
12772}
12773
94f05024 12774static void intel_atomic_commit_tail(struct drm_atomic_state *state)
a6778b3c 12775{
94f05024 12776 struct drm_device *dev = state->dev;
565602d7 12777 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
fac5e23e 12778 struct drm_i915_private *dev_priv = to_i915(dev);
aa5e9b47 12779 struct drm_crtc_state *old_crtc_state, *new_crtc_state;
7580d774 12780 struct drm_crtc *crtc;
5a21b665 12781 struct intel_crtc_state *intel_cstate;
5a21b665 12782 bool hw_check = intel_state->modeset;
d8fc70b7 12783 u64 put_domains[I915_MAX_PIPES] = {};
5a21b665 12784 unsigned crtc_vblank_mask = 0;
e95433c7 12785 int i;
a6778b3c 12786
ea0000f0
DV
12787 drm_atomic_helper_wait_for_dependencies(state);
12788
c3b32658 12789 if (intel_state->modeset)
5a21b665 12790 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
565602d7 12791
aa5e9b47 12792 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
a539205a
ML
12793 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12794
aa5e9b47
ML
12795 if (needs_modeset(new_crtc_state) ||
12796 to_intel_crtc_state(new_crtc_state)->update_pipe) {
5a21b665
DV
12797 hw_check = true;
12798
12799 put_domains[to_intel_crtc(crtc)->pipe] =
12800 modeset_get_crtc_power_domains(crtc,
aa5e9b47 12801 to_intel_crtc_state(new_crtc_state));
5a21b665
DV
12802 }
12803
aa5e9b47 12804 if (!needs_modeset(new_crtc_state))
61333b60
ML
12805 continue;
12806
aa5e9b47
ML
12807 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state),
12808 to_intel_crtc_state(new_crtc_state));
460da916 12809
29ceb0e6
VS
12810 if (old_crtc_state->active) {
12811 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
4a806558 12812 dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
eddfcbcd 12813 intel_crtc->active = false;
58f9c0bc 12814 intel_fbc_disable(intel_crtc);
eddfcbcd 12815 intel_disable_shared_dpll(intel_crtc);
9bbc8258
VS
12816
12817 /*
12818 * Underruns don't always raise
12819 * interrupts, so check manually.
12820 */
12821 intel_check_cpu_fifo_underruns(dev_priv);
12822 intel_check_pch_fifo_underruns(dev_priv);
b9001114 12823
e62929b3
ML
12824 if (!crtc->state->active) {
12825 /*
12826 * Make sure we don't call initial_watermarks
12827 * for ILK-style watermark updates.
ff32c54e
VS
12828 *
12829 * No clue what this is supposed to achieve.
e62929b3 12830 */
ff32c54e 12831 if (INTEL_GEN(dev_priv) >= 9)
e62929b3
ML
12832 dev_priv->display.initial_watermarks(intel_state,
12833 to_intel_crtc_state(crtc->state));
e62929b3 12834 }
a539205a 12835 }
b8cecdf5 12836 }
7758a113 12837
ea9d758d
DV
12838 /* Only after disabling all output pipelines that will be changed can we
12839 * update the the output configuration. */
4740b0f2 12840 intel_modeset_update_crtc_state(state);
f6e5b160 12841
565602d7 12842 if (intel_state->modeset) {
4740b0f2 12843 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
33c8df89 12844
b0587e4d 12845 intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual);
f6d1973d 12846
656d1b89
L
12847 /*
12848 * SKL workaround: bspec recommends we disable the SAGV when we
12849 * have more then one pipe enabled
12850 */
56feca91 12851 if (!intel_can_enable_sagv(state))
16dcdc4e 12852 intel_disable_sagv(dev_priv);
656d1b89 12853
677100ce 12854 intel_modeset_verify_disabled(dev, state);
4740b0f2 12855 }
47fab737 12856
896e5bb0 12857 /* Complete the events for pipes that have now been disabled */
aa5e9b47
ML
12858 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12859 bool modeset = needs_modeset(new_crtc_state);
80715b2f 12860
1f7528c4 12861 /* Complete events for now disable pipes here. */
aa5e9b47 12862 if (modeset && !new_crtc_state->active && new_crtc_state->event) {
1f7528c4 12863 spin_lock_irq(&dev->event_lock);
aa5e9b47 12864 drm_crtc_send_vblank_event(crtc, new_crtc_state->event);
1f7528c4
DV
12865 spin_unlock_irq(&dev->event_lock);
12866
aa5e9b47 12867 new_crtc_state->event = NULL;
1f7528c4 12868 }
177246a8
MR
12869 }
12870
896e5bb0
L
12871 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12872 dev_priv->display.update_crtcs(state, &crtc_vblank_mask);
12873
94f05024
DV
12874 /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
12875 * already, but still need the state for the delayed optimization. To
12876 * fix this:
12877 * - wrap the optimization/post_plane_update stuff into a per-crtc work.
12878 * - schedule that vblank worker _before_ calling hw_done
12879 * - at the start of commit_tail, cancel it _synchrously
12880 * - switch over to the vblank wait helper in the core after that since
12881 * we don't need out special handling any more.
12882 */
5a21b665
DV
12883 if (!state->legacy_cursor_update)
12884 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
12885
12886 /*
12887 * Now that the vblank has passed, we can go ahead and program the
12888 * optimal watermarks on platforms that need two-step watermark
12889 * programming.
12890 *
12891 * TODO: Move this (and other cleanup) to an async worker eventually.
12892 */
aa5e9b47
ML
12893 for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
12894 intel_cstate = to_intel_crtc_state(new_crtc_state);
5a21b665
DV
12895
12896 if (dev_priv->display.optimize_watermarks)
ccf010fb
ML
12897 dev_priv->display.optimize_watermarks(intel_state,
12898 intel_cstate);
5a21b665
DV
12899 }
12900
aa5e9b47 12901 for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
5a21b665
DV
12902 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
12903
12904 if (put_domains[i])
12905 modeset_put_power_domains(dev_priv, put_domains[i]);
12906
aa5e9b47 12907 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
5a21b665
DV
12908 }
12909
56feca91 12910 if (intel_state->modeset && intel_can_enable_sagv(state))
16dcdc4e 12911 intel_enable_sagv(dev_priv);
656d1b89 12912
94f05024
DV
12913 drm_atomic_helper_commit_hw_done(state);
12914
5a21b665
DV
12915 if (intel_state->modeset)
12916 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
12917
12918 mutex_lock(&dev->struct_mutex);
12919 drm_atomic_helper_cleanup_planes(dev, state);
12920 mutex_unlock(&dev->struct_mutex);
12921
ea0000f0
DV
12922 drm_atomic_helper_commit_cleanup_done(state);
12923
0853695c 12924 drm_atomic_state_put(state);
f30da187 12925
75714940
MK
12926 /* As one of the primary mmio accessors, KMS has a high likelihood
12927 * of triggering bugs in unclaimed access. After we finish
12928 * modesetting, see if an error has been flagged, and if so
12929 * enable debugging for the next modeset - and hope we catch
12930 * the culprit.
12931 *
12932 * XXX note that we assume display power is on at this point.
12933 * This might hold true now but we need to add pm helper to check
12934 * unclaimed only when the hardware is on, as atomic commits
12935 * can happen also when the device is completely off.
12936 */
12937 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
ba318c61
CW
12938
12939 intel_atomic_helper_free_state(dev_priv);
94f05024
DV
12940}
12941
12942static void intel_atomic_commit_work(struct work_struct *work)
12943{
c004a90b
CW
12944 struct drm_atomic_state *state =
12945 container_of(work, struct drm_atomic_state, commit_work);
12946
94f05024
DV
12947 intel_atomic_commit_tail(state);
12948}
12949
c004a90b
CW
12950static int __i915_sw_fence_call
12951intel_atomic_commit_ready(struct i915_sw_fence *fence,
12952 enum i915_sw_fence_notify notify)
12953{
12954 struct intel_atomic_state *state =
12955 container_of(fence, struct intel_atomic_state, commit_ready);
12956
12957 switch (notify) {
12958 case FENCE_COMPLETE:
12959 if (state->base.commit_work.func)
12960 queue_work(system_unbound_wq, &state->base.commit_work);
12961 break;
12962
12963 case FENCE_FREE:
eb955eee
CW
12964 {
12965 struct intel_atomic_helper *helper =
12966 &to_i915(state->base.dev)->atomic_helper;
12967
12968 if (llist_add(&state->freed, &helper->free_list))
12969 schedule_work(&helper->free_work);
12970 break;
12971 }
c004a90b
CW
12972 }
12973
12974 return NOTIFY_DONE;
12975}
12976
6c9c1b38
DV
12977static void intel_atomic_track_fbs(struct drm_atomic_state *state)
12978{
aa5e9b47 12979 struct drm_plane_state *old_plane_state, *new_plane_state;
6c9c1b38 12980 struct drm_plane *plane;
6c9c1b38
DV
12981 int i;
12982
aa5e9b47 12983 for_each_oldnew_plane_in_state(state, plane, old_plane_state, new_plane_state, i)
faf5bf0a 12984 i915_gem_track_fb(intel_fb_obj(old_plane_state->fb),
aa5e9b47 12985 intel_fb_obj(new_plane_state->fb),
faf5bf0a 12986 to_intel_plane(plane)->frontbuffer_bit);
6c9c1b38
DV
12987}
12988
94f05024
DV
12989/**
12990 * intel_atomic_commit - commit validated state object
12991 * @dev: DRM device
12992 * @state: the top-level driver state object
12993 * @nonblock: nonblocking commit
12994 *
12995 * This function commits a top-level state object that has been validated
12996 * with drm_atomic_helper_check().
12997 *
94f05024
DV
12998 * RETURNS
12999 * Zero for success or -errno.
13000 */
13001static int intel_atomic_commit(struct drm_device *dev,
13002 struct drm_atomic_state *state,
13003 bool nonblock)
13004{
13005 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
fac5e23e 13006 struct drm_i915_private *dev_priv = to_i915(dev);
94f05024
DV
13007 int ret = 0;
13008
94f05024
DV
13009 ret = drm_atomic_helper_setup_commit(state, nonblock);
13010 if (ret)
13011 return ret;
13012
c004a90b
CW
13013 drm_atomic_state_get(state);
13014 i915_sw_fence_init(&intel_state->commit_ready,
13015 intel_atomic_commit_ready);
94f05024 13016
d07f0e59 13017 ret = intel_atomic_prepare_commit(dev, state);
94f05024
DV
13018 if (ret) {
13019 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
c004a90b 13020 i915_sw_fence_commit(&intel_state->commit_ready);
94f05024
DV
13021 return ret;
13022 }
13023
89520304
VS
13024 /*
13025 * The intel_legacy_cursor_update() fast path takes care
13026 * of avoiding the vblank waits for simple cursor
13027 * movement and flips. For cursor on/off and size changes,
13028 * we want to perform the vblank waits so that watermark
13029 * updates happen during the correct frames. Gen9+ have
13030 * double buffered watermarks and so shouldn't need this.
13031 *
13032 * Do this after drm_atomic_helper_setup_commit() and
13033 * intel_atomic_prepare_commit() because we still want
13034 * to skip the flip and fb cleanup waits. Although that
13035 * does risk yanking the mapping from under the display
13036 * engine.
13037 *
13038 * FIXME doing watermarks and fb cleanup from a vblank worker
13039 * (assuming we had any) would solve these problems.
13040 */
13041 if (INTEL_GEN(dev_priv) < 9)
13042 state->legacy_cursor_update = false;
13043
94f05024
DV
13044 drm_atomic_helper_swap_state(state, true);
13045 dev_priv->wm.distrust_bios_wm = false;
3c0fb588 13046 intel_shared_dpll_swap_state(state);
6c9c1b38 13047 intel_atomic_track_fbs(state);
94f05024 13048
c3b32658
ML
13049 if (intel_state->modeset) {
13050 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13051 sizeof(intel_state->min_pixclk));
13052 dev_priv->active_crtcs = intel_state->active_crtcs;
bb0f4aab
VS
13053 dev_priv->cdclk.logical = intel_state->cdclk.logical;
13054 dev_priv->cdclk.actual = intel_state->cdclk.actual;
c3b32658
ML
13055 }
13056
0853695c 13057 drm_atomic_state_get(state);
c004a90b
CW
13058 INIT_WORK(&state->commit_work,
13059 nonblock ? intel_atomic_commit_work : NULL);
13060
13061 i915_sw_fence_commit(&intel_state->commit_ready);
13062 if (!nonblock) {
13063 i915_sw_fence_wait(&intel_state->commit_ready);
94f05024 13064 intel_atomic_commit_tail(state);
c004a90b 13065 }
75714940 13066
74c090b1 13067 return 0;
7f27126e
JB
13068}
13069
c0c36b94
CW
13070void intel_crtc_restore_mode(struct drm_crtc *crtc)
13071{
83a57153
ACO
13072 struct drm_device *dev = crtc->dev;
13073 struct drm_atomic_state *state;
e694eb02 13074 struct drm_crtc_state *crtc_state;
2bfb4627 13075 int ret;
83a57153
ACO
13076
13077 state = drm_atomic_state_alloc(dev);
13078 if (!state) {
78108b7c
VS
13079 DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory",
13080 crtc->base.id, crtc->name);
83a57153
ACO
13081 return;
13082 }
13083
b260ac3e 13084 state->acquire_ctx = crtc->dev->mode_config.acquire_ctx;
83a57153 13085
e694eb02
ML
13086retry:
13087 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13088 ret = PTR_ERR_OR_ZERO(crtc_state);
13089 if (!ret) {
13090 if (!crtc_state->active)
13091 goto out;
83a57153 13092
e694eb02 13093 crtc_state->mode_changed = true;
74c090b1 13094 ret = drm_atomic_commit(state);
83a57153
ACO
13095 }
13096
e694eb02
ML
13097 if (ret == -EDEADLK) {
13098 drm_atomic_state_clear(state);
13099 drm_modeset_backoff(state->acquire_ctx);
13100 goto retry;
4ed9fb37 13101 }
4be07317 13102
e694eb02 13103out:
0853695c 13104 drm_atomic_state_put(state);
c0c36b94
CW
13105}
13106
f6e5b160 13107static const struct drm_crtc_funcs intel_crtc_funcs = {
3fab2f09 13108 .gamma_set = drm_atomic_helper_legacy_gamma_set,
74c090b1 13109 .set_config = drm_atomic_helper_set_config,
82cf435b 13110 .set_property = drm_atomic_helper_crtc_set_property,
f6e5b160 13111 .destroy = intel_crtc_destroy,
4c01ded5 13112 .page_flip = drm_atomic_helper_page_flip,
1356837e
MR
13113 .atomic_duplicate_state = intel_crtc_duplicate_state,
13114 .atomic_destroy_state = intel_crtc_destroy_state,
8c6b709d 13115 .set_crc_source = intel_crtc_set_crc_source,
f6e5b160
CW
13116};
13117
6beb8c23
MR
13118/**
13119 * intel_prepare_plane_fb - Prepare fb for usage on plane
13120 * @plane: drm plane to prepare for
13121 * @fb: framebuffer to prepare for presentation
13122 *
13123 * Prepares a framebuffer for usage on a display plane. Generally this
13124 * involves pinning the underlying object and updating the frontbuffer tracking
13125 * bits. Some older platforms need special physical address handling for
13126 * cursor planes.
13127 *
f935675f
ML
13128 * Must be called with struct_mutex held.
13129 *
6beb8c23
MR
13130 * Returns 0 on success, negative error code on failure.
13131 */
13132int
13133intel_prepare_plane_fb(struct drm_plane *plane,
1832040d 13134 struct drm_plane_state *new_state)
465c120c 13135{
c004a90b
CW
13136 struct intel_atomic_state *intel_state =
13137 to_intel_atomic_state(new_state->state);
b7f05d4a 13138 struct drm_i915_private *dev_priv = to_i915(plane->dev);
844f9111 13139 struct drm_framebuffer *fb = new_state->fb;
6beb8c23 13140 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
1ee49399 13141 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
c004a90b 13142 int ret;
465c120c 13143
57822dc6
CW
13144 if (obj) {
13145 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13146 INTEL_INFO(dev_priv)->cursor_needs_physical) {
13147 const int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
13148
13149 ret = i915_gem_object_attach_phys(obj, align);
13150 if (ret) {
13151 DRM_DEBUG_KMS("failed to attach phys object\n");
13152 return ret;
13153 }
13154 } else {
13155 struct i915_vma *vma;
13156
13157 vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13158 if (IS_ERR(vma)) {
13159 DRM_DEBUG_KMS("failed to pin object\n");
13160 return PTR_ERR(vma);
13161 }
13162
13163 to_intel_plane_state(new_state)->vma = vma;
13164 }
13165 }
13166
1ee49399 13167 if (!obj && !old_obj)
465c120c
MR
13168 return 0;
13169
5008e874
ML
13170 if (old_obj) {
13171 struct drm_crtc_state *crtc_state =
c004a90b
CW
13172 drm_atomic_get_existing_crtc_state(new_state->state,
13173 plane->state->crtc);
5008e874
ML
13174
13175 /* Big Hammer, we also need to ensure that any pending
13176 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13177 * current scanout is retired before unpinning the old
13178 * framebuffer. Note that we rely on userspace rendering
13179 * into the buffer attached to the pipe they are waiting
13180 * on. If not, userspace generates a GPU hang with IPEHR
13181 * point to the MI_WAIT_FOR_EVENT.
13182 *
13183 * This should only fail upon a hung GPU, in which case we
13184 * can safely continue.
13185 */
c004a90b
CW
13186 if (needs_modeset(crtc_state)) {
13187 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13188 old_obj->resv, NULL,
13189 false, 0,
13190 GFP_KERNEL);
13191 if (ret < 0)
13192 return ret;
f4457ae7 13193 }
5008e874
ML
13194 }
13195
c004a90b
CW
13196 if (new_state->fence) { /* explicit fencing */
13197 ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready,
13198 new_state->fence,
13199 I915_FENCE_TIMEOUT,
13200 GFP_KERNEL);
13201 if (ret < 0)
13202 return ret;
13203 }
13204
c37efb99
CW
13205 if (!obj)
13206 return 0;
13207
c004a90b
CW
13208 if (!new_state->fence) { /* implicit fencing */
13209 ret = i915_sw_fence_await_reservation(&intel_state->commit_ready,
13210 obj->resv, NULL,
13211 false, I915_FENCE_TIMEOUT,
13212 GFP_KERNEL);
13213 if (ret < 0)
13214 return ret;
6b5e90f5
CW
13215
13216 i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY);
c004a90b 13217 }
5a21b665 13218
d07f0e59 13219 return 0;
6beb8c23
MR
13220}
13221
38f3ce3a
MR
13222/**
13223 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13224 * @plane: drm plane to clean up for
13225 * @fb: old framebuffer that was on plane
13226 *
13227 * Cleans up a framebuffer that has just been removed from a plane.
f935675f
ML
13228 *
13229 * Must be called with struct_mutex held.
38f3ce3a
MR
13230 */
13231void
13232intel_cleanup_plane_fb(struct drm_plane *plane,
1832040d 13233 struct drm_plane_state *old_state)
38f3ce3a 13234{
be1e3415 13235 struct i915_vma *vma;
38f3ce3a 13236
be1e3415
CW
13237 /* Should only be called after a successful intel_prepare_plane_fb()! */
13238 vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma);
13239 if (vma)
13240 intel_unpin_fb_vma(vma);
465c120c
MR
13241}
13242
6156a456
CK
13243int
13244skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13245{
5b7280f0 13246 struct drm_i915_private *dev_priv;
6156a456 13247 int max_scale;
5b7280f0 13248 int crtc_clock, max_dotclk;
6156a456 13249
bf8a0af0 13250 if (!intel_crtc || !crtc_state->base.enable)
6156a456
CK
13251 return DRM_PLANE_HELPER_NO_SCALING;
13252
5b7280f0
ACO
13253 dev_priv = to_i915(intel_crtc->base.dev);
13254
6156a456 13255 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
5b7280f0
ACO
13256 max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
13257
13258 if (IS_GEMINILAKE(dev_priv))
13259 max_dotclk *= 2;
6156a456 13260
5b7280f0 13261 if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock))
6156a456
CK
13262 return DRM_PLANE_HELPER_NO_SCALING;
13263
13264 /*
13265 * skl max scale is lower of:
13266 * close to 3 but not 3, -1 is for that purpose
13267 * or
13268 * cdclk/crtc_clock
13269 */
5b7280f0
ACO
13270 max_scale = min((1 << 16) * 3 - 1,
13271 (1 << 8) * ((max_dotclk << 8) / crtc_clock));
6156a456
CK
13272
13273 return max_scale;
13274}
13275
465c120c 13276static int
3c692a41 13277intel_check_primary_plane(struct drm_plane *plane,
061e4b8d 13278 struct intel_crtc_state *crtc_state,
3c692a41
GP
13279 struct intel_plane_state *state)
13280{
b63a16f6 13281 struct drm_i915_private *dev_priv = to_i915(plane->dev);
2b875c22 13282 struct drm_crtc *crtc = state->base.crtc;
6156a456 13283 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
061e4b8d
ML
13284 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13285 bool can_position = false;
b63a16f6 13286 int ret;
465c120c 13287
b63a16f6 13288 if (INTEL_GEN(dev_priv) >= 9) {
693bdc28
VS
13289 /* use scaler when colorkey is not required */
13290 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13291 min_scale = 1;
13292 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13293 }
d8106366 13294 can_position = true;
6156a456 13295 }
d8106366 13296
cc926387
DV
13297 ret = drm_plane_helper_check_state(&state->base,
13298 &state->clip,
13299 min_scale, max_scale,
13300 can_position, true);
b63a16f6
VS
13301 if (ret)
13302 return ret;
13303
cc926387 13304 if (!state->base.fb)
b63a16f6
VS
13305 return 0;
13306
13307 if (INTEL_GEN(dev_priv) >= 9) {
13308 ret = skl_check_plane_surface(state);
13309 if (ret)
13310 return ret;
a0864d59
VS
13311
13312 state->ctl = skl_plane_ctl(crtc_state, state);
13313 } else {
5b7fcc44
VS
13314 ret = i9xx_check_plane_surface(state);
13315 if (ret)
13316 return ret;
13317
a0864d59 13318 state->ctl = i9xx_plane_ctl(crtc_state, state);
b63a16f6
VS
13319 }
13320
13321 return 0;
14af293f
GP
13322}
13323
5a21b665
DV
13324static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13325 struct drm_crtc_state *old_crtc_state)
13326{
13327 struct drm_device *dev = crtc->dev;
62e0fb88 13328 struct drm_i915_private *dev_priv = to_i915(dev);
5a21b665 13329 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b707aa50
L
13330 struct intel_crtc_state *intel_cstate =
13331 to_intel_crtc_state(crtc->state);
ccf010fb 13332 struct intel_crtc_state *old_intel_cstate =
5a21b665 13333 to_intel_crtc_state(old_crtc_state);
ccf010fb
ML
13334 struct intel_atomic_state *old_intel_state =
13335 to_intel_atomic_state(old_crtc_state->state);
5a21b665
DV
13336 bool modeset = needs_modeset(crtc->state);
13337
567f0792
ML
13338 if (!modeset &&
13339 (intel_cstate->base.color_mgmt_changed ||
13340 intel_cstate->update_pipe)) {
13341 intel_color_set_csc(crtc->state);
13342 intel_color_load_luts(crtc->state);
13343 }
13344
5a21b665
DV
13345 /* Perform vblank evasion around commit operation */
13346 intel_pipe_update_start(intel_crtc);
13347
13348 if (modeset)
e62929b3 13349 goto out;
5a21b665 13350
ccf010fb
ML
13351 if (intel_cstate->update_pipe)
13352 intel_update_pipe_config(intel_crtc, old_intel_cstate);
13353 else if (INTEL_GEN(dev_priv) >= 9)
5a21b665 13354 skl_detach_scalers(intel_crtc);
62e0fb88 13355
e62929b3 13356out:
ccf010fb
ML
13357 if (dev_priv->display.atomic_update_watermarks)
13358 dev_priv->display.atomic_update_watermarks(old_intel_state,
13359 intel_cstate);
5a21b665
DV
13360}
13361
13362static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13363 struct drm_crtc_state *old_crtc_state)
13364{
13365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13366
13367 intel_pipe_update_end(intel_crtc, NULL);
13368}
13369
cf4c7c12 13370/**
4a3b8769
MR
13371 * intel_plane_destroy - destroy a plane
13372 * @plane: plane to destroy
cf4c7c12 13373 *
4a3b8769
MR
13374 * Common destruction function for all types of planes (primary, cursor,
13375 * sprite).
cf4c7c12 13376 */
4a3b8769 13377void intel_plane_destroy(struct drm_plane *plane)
465c120c 13378{
465c120c 13379 drm_plane_cleanup(plane);
69ae561f 13380 kfree(to_intel_plane(plane));
465c120c
MR
13381}
13382
65a3fea0 13383const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR
13384 .update_plane = drm_atomic_helper_update_plane,
13385 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13386 .destroy = intel_plane_destroy,
c196e1d6 13387 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR
13388 .atomic_get_property = intel_plane_atomic_get_property,
13389 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR
13390 .atomic_duplicate_state = intel_plane_duplicate_state,
13391 .atomic_destroy_state = intel_plane_destroy_state,
465c120c
MR
13392};
13393
f79f2692
ML
13394static int
13395intel_legacy_cursor_update(struct drm_plane *plane,
13396 struct drm_crtc *crtc,
13397 struct drm_framebuffer *fb,
13398 int crtc_x, int crtc_y,
13399 unsigned int crtc_w, unsigned int crtc_h,
13400 uint32_t src_x, uint32_t src_y,
34a2ab5e
DV
13401 uint32_t src_w, uint32_t src_h,
13402 struct drm_modeset_acquire_ctx *ctx)
f79f2692
ML
13403{
13404 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
13405 int ret;
13406 struct drm_plane_state *old_plane_state, *new_plane_state;
13407 struct intel_plane *intel_plane = to_intel_plane(plane);
13408 struct drm_framebuffer *old_fb;
13409 struct drm_crtc_state *crtc_state = crtc->state;
be1e3415 13410 struct i915_vma *old_vma;
f79f2692
ML
13411
13412 /*
13413 * When crtc is inactive or there is a modeset pending,
13414 * wait for it to complete in the slowpath
13415 */
13416 if (!crtc_state->active || needs_modeset(crtc_state) ||
13417 to_intel_crtc_state(crtc_state)->update_pipe)
13418 goto slow;
13419
13420 old_plane_state = plane->state;
13421
13422 /*
13423 * If any parameters change that may affect watermarks,
13424 * take the slowpath. Only changing fb or position should be
13425 * in the fastpath.
13426 */
13427 if (old_plane_state->crtc != crtc ||
13428 old_plane_state->src_w != src_w ||
13429 old_plane_state->src_h != src_h ||
13430 old_plane_state->crtc_w != crtc_w ||
13431 old_plane_state->crtc_h != crtc_h ||
a5509abd 13432 !old_plane_state->fb != !fb)
f79f2692
ML
13433 goto slow;
13434
13435 new_plane_state = intel_plane_duplicate_state(plane);
13436 if (!new_plane_state)
13437 return -ENOMEM;
13438
13439 drm_atomic_set_fb_for_plane(new_plane_state, fb);
13440
13441 new_plane_state->src_x = src_x;
13442 new_plane_state->src_y = src_y;
13443 new_plane_state->src_w = src_w;
13444 new_plane_state->src_h = src_h;
13445 new_plane_state->crtc_x = crtc_x;
13446 new_plane_state->crtc_y = crtc_y;
13447 new_plane_state->crtc_w = crtc_w;
13448 new_plane_state->crtc_h = crtc_h;
13449
13450 ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state),
13451 to_intel_plane_state(new_plane_state));
13452 if (ret)
13453 goto out_free;
13454
f79f2692
ML
13455 ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
13456 if (ret)
13457 goto out_free;
13458
13459 if (INTEL_INFO(dev_priv)->cursor_needs_physical) {
13460 int align = IS_I830(dev_priv) ? 16 * 1024 : 256;
13461
13462 ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align);
13463 if (ret) {
13464 DRM_DEBUG_KMS("failed to attach phys object\n");
13465 goto out_unlock;
13466 }
13467 } else {
13468 struct i915_vma *vma;
13469
13470 vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation);
13471 if (IS_ERR(vma)) {
13472 DRM_DEBUG_KMS("failed to pin object\n");
13473
13474 ret = PTR_ERR(vma);
13475 goto out_unlock;
13476 }
be1e3415
CW
13477
13478 to_intel_plane_state(new_plane_state)->vma = vma;
f79f2692
ML
13479 }
13480
13481 old_fb = old_plane_state->fb;
be1e3415 13482 old_vma = to_intel_plane_state(old_plane_state)->vma;
f79f2692
ML
13483
13484 i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb),
13485 intel_plane->frontbuffer_bit);
13486
13487 /* Swap plane state */
13488 new_plane_state->fence = old_plane_state->fence;
13489 *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state);
13490 new_plane_state->fence = NULL;
13491 new_plane_state->fb = old_fb;
be1e3415 13492 to_intel_plane_state(new_plane_state)->vma = old_vma;
f79f2692 13493
72259536
VS
13494 if (plane->state->visible) {
13495 trace_intel_update_plane(plane, to_intel_crtc(crtc));
a5509abd
VS
13496 intel_plane->update_plane(plane,
13497 to_intel_crtc_state(crtc->state),
13498 to_intel_plane_state(plane->state));
72259536
VS
13499 } else {
13500 trace_intel_disable_plane(plane, to_intel_crtc(crtc));
a5509abd 13501 intel_plane->disable_plane(plane, crtc);
72259536 13502 }
f79f2692
ML
13503
13504 intel_cleanup_plane_fb(plane, new_plane_state);
13505
13506out_unlock:
13507 mutex_unlock(&dev_priv->drm.struct_mutex);
13508out_free:
13509 intel_plane_destroy_state(plane, new_plane_state);
13510 return ret;
13511
f79f2692
ML
13512slow:
13513 return drm_atomic_helper_update_plane(plane, crtc, fb,
13514 crtc_x, crtc_y, crtc_w, crtc_h,
34a2ab5e 13515 src_x, src_y, src_w, src_h, ctx);
f79f2692
ML
13516}
13517
13518static const struct drm_plane_funcs intel_cursor_plane_funcs = {
13519 .update_plane = intel_legacy_cursor_update,
13520 .disable_plane = drm_atomic_helper_disable_plane,
13521 .destroy = intel_plane_destroy,
13522 .set_property = drm_atomic_helper_plane_set_property,
13523 .atomic_get_property = intel_plane_atomic_get_property,
13524 .atomic_set_property = intel_plane_atomic_set_property,
13525 .atomic_duplicate_state = intel_plane_duplicate_state,
13526 .atomic_destroy_state = intel_plane_destroy_state,
13527};
13528
b079bd17 13529static struct intel_plane *
580503c7 13530intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
465c120c 13531{
fca0ce2a
VS
13532 struct intel_plane *primary = NULL;
13533 struct intel_plane_state *state = NULL;
465c120c 13534 const uint32_t *intel_primary_formats;
93ca7e00 13535 unsigned int supported_rotations;
45e3743a 13536 unsigned int num_formats;
fca0ce2a 13537 int ret;
465c120c
MR
13538
13539 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
b079bd17
VS
13540 if (!primary) {
13541 ret = -ENOMEM;
fca0ce2a 13542 goto fail;
b079bd17 13543 }
465c120c 13544
8e7d688b 13545 state = intel_create_plane_state(&primary->base);
b079bd17
VS
13546 if (!state) {
13547 ret = -ENOMEM;
fca0ce2a 13548 goto fail;
b079bd17
VS
13549 }
13550
8e7d688b 13551 primary->base.state = &state->base;
ea2c67bb 13552
465c120c
MR
13553 primary->can_scale = false;
13554 primary->max_downscale = 1;
580503c7 13555 if (INTEL_GEN(dev_priv) >= 9) {
6156a456 13556 primary->can_scale = true;
af99ceda 13557 state->scaler_id = -1;
6156a456 13558 }
465c120c 13559 primary->pipe = pipe;
e3c566df
VS
13560 /*
13561 * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
13562 * port is hooked to pipe B. Hence we want plane A feeding pipe B.
13563 */
13564 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4)
13565 primary->plane = (enum plane) !pipe;
13566 else
13567 primary->plane = (enum plane) pipe;
b14e5848 13568 primary->id = PLANE_PRIMARY;
a9ff8714 13569 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
c59cb179 13570 primary->check_plane = intel_check_primary_plane;
465c120c 13571
580503c7 13572 if (INTEL_GEN(dev_priv) >= 9) {
6c0fd451
DL
13573 intel_primary_formats = skl_primary_formats;
13574 num_formats = ARRAY_SIZE(skl_primary_formats);
a8d201af
ML
13575
13576 primary->update_plane = skylake_update_primary_plane;
13577 primary->disable_plane = skylake_disable_primary_plane;
580503c7 13578 } else if (INTEL_GEN(dev_priv) >= 4) {
568db4f2
DL
13579 intel_primary_formats = i965_primary_formats;
13580 num_formats = ARRAY_SIZE(i965_primary_formats);
a8d201af
ML
13581
13582 primary->update_plane = i9xx_update_primary_plane;
13583 primary->disable_plane = i9xx_disable_primary_plane;
6c0fd451
DL
13584 } else {
13585 intel_primary_formats = i8xx_primary_formats;
13586 num_formats = ARRAY_SIZE(i8xx_primary_formats);
a8d201af
ML
13587
13588 primary->update_plane = i9xx_update_primary_plane;
13589 primary->disable_plane = i9xx_disable_primary_plane;
465c120c
MR
13590 }
13591
580503c7
VS
13592 if (INTEL_GEN(dev_priv) >= 9)
13593 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13594 0, &intel_plane_funcs,
38573dc1
VS
13595 intel_primary_formats, num_formats,
13596 DRM_PLANE_TYPE_PRIMARY,
13597 "plane 1%c", pipe_name(pipe));
9beb5fea 13598 else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv))
580503c7
VS
13599 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13600 0, &intel_plane_funcs,
38573dc1
VS
13601 intel_primary_formats, num_formats,
13602 DRM_PLANE_TYPE_PRIMARY,
13603 "primary %c", pipe_name(pipe));
13604 else
580503c7
VS
13605 ret = drm_universal_plane_init(&dev_priv->drm, &primary->base,
13606 0, &intel_plane_funcs,
38573dc1
VS
13607 intel_primary_formats, num_formats,
13608 DRM_PLANE_TYPE_PRIMARY,
13609 "plane %c", plane_name(primary->plane));
fca0ce2a
VS
13610 if (ret)
13611 goto fail;
48404c1e 13612
5481e27f 13613 if (INTEL_GEN(dev_priv) >= 9) {
93ca7e00
VS
13614 supported_rotations =
13615 DRM_ROTATE_0 | DRM_ROTATE_90 |
13616 DRM_ROTATE_180 | DRM_ROTATE_270;
4ea7be2b
VS
13617 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
13618 supported_rotations =
13619 DRM_ROTATE_0 | DRM_ROTATE_180 |
13620 DRM_REFLECT_X;
5481e27f 13621 } else if (INTEL_GEN(dev_priv) >= 4) {
93ca7e00
VS
13622 supported_rotations =
13623 DRM_ROTATE_0 | DRM_ROTATE_180;
13624 } else {
13625 supported_rotations = DRM_ROTATE_0;
13626 }
13627
5481e27f 13628 if (INTEL_GEN(dev_priv) >= 4)
93ca7e00
VS
13629 drm_plane_create_rotation_property(&primary->base,
13630 DRM_ROTATE_0,
13631 supported_rotations);
48404c1e 13632
ea2c67bb
MR
13633 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13634
b079bd17 13635 return primary;
fca0ce2a
VS
13636
13637fail:
13638 kfree(state);
13639 kfree(primary);
13640
b079bd17 13641 return ERR_PTR(ret);
465c120c
MR
13642}
13643
3d7d6510 13644static int
852e787c 13645intel_check_cursor_plane(struct drm_plane *plane,
061e4b8d 13646 struct intel_crtc_state *crtc_state,
852e787c 13647 struct intel_plane_state *state)
3d7d6510 13648{
a0864d59 13649 struct drm_i915_private *dev_priv = to_i915(plane->dev);
2b875c22 13650 struct drm_framebuffer *fb = state->base.fb;
757f9a3e 13651 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
b29ec92c 13652 enum pipe pipe = to_intel_plane(plane)->pipe;
757f9a3e
GP
13653 unsigned stride;
13654 int ret;
3d7d6510 13655
f8856a44
VS
13656 ret = drm_plane_helper_check_state(&state->base,
13657 &state->clip,
13658 DRM_PLANE_HELPER_NO_SCALING,
13659 DRM_PLANE_HELPER_NO_SCALING,
13660 true, true);
757f9a3e
GP
13661 if (ret)
13662 return ret;
13663
757f9a3e
GP
13664 /* if we want to turn off the cursor ignore width and height */
13665 if (!obj)
da20eabd 13666 return 0;
757f9a3e 13667
757f9a3e 13668 /* Check for which cursor types we support */
a0864d59 13669 if (!cursor_size_ok(dev_priv, state->base.crtc_w,
50a0bc90 13670 state->base.crtc_h)) {
ea2c67bb
MR
13671 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13672 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP
13673 return -EINVAL;
13674 }
13675
ea2c67bb
MR
13676 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13677 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP
13678 DRM_DEBUG_KMS("buffer is too small\n");
13679 return -ENOMEM;
13680 }
13681
2f075565 13682 if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
757f9a3e 13683 DRM_DEBUG_KMS("cursor cannot be tiled\n");
da20eabd 13684 return -EINVAL;
32b7eeec
MR
13685 }
13686
b29ec92c
VS
13687 /*
13688 * There's something wrong with the cursor on CHV pipe C.
13689 * If it straddles the left edge of the screen then
13690 * moving it away from the edge or disabling it often
13691 * results in a pipe underrun, and often that can lead to
13692 * dead pipe (constant underrun reported, and it scans
13693 * out just a solid color). To recover from that, the
13694 * display power well must be turned off and on again.
13695 * Refuse the put the cursor into that compromised position.
13696 */
a0864d59 13697 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
936e71e3 13698 state->base.visible && state->base.crtc_x < 0) {
b29ec92c
VS
13699 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
13700 return -EINVAL;
13701 }
13702
a0864d59
VS
13703 if (IS_I845G(dev_priv) || IS_I865G(dev_priv))
13704 state->ctl = i845_cursor_ctl(crtc_state, state);
13705 else
13706 state->ctl = i9xx_cursor_ctl(crtc_state, state);
13707
da20eabd 13708 return 0;
852e787c 13709}
3d7d6510 13710
a8ad0d8e
ML
13711static void
13712intel_disable_cursor_plane(struct drm_plane *plane,
7fabf5ef 13713 struct drm_crtc *crtc)
a8ad0d8e 13714{
f2858021
ML
13715 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13716
13717 intel_crtc->cursor_addr = 0;
a0864d59 13718 intel_crtc_update_cursor(crtc, NULL);
a8ad0d8e
ML
13719}
13720
f4a2cf29 13721static void
55a08b3f
ML
13722intel_update_cursor_plane(struct drm_plane *plane,
13723 const struct intel_crtc_state *crtc_state,
13724 const struct intel_plane_state *state)
852e787c 13725{
55a08b3f
ML
13726 struct drm_crtc *crtc = crtc_state->base.crtc;
13727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b7f05d4a 13728 struct drm_i915_private *dev_priv = to_i915(plane->dev);
2b875c22 13729 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13730 uint32_t addr;
852e787c 13731
f4a2cf29 13732 if (!obj)
a912f12f 13733 addr = 0;
b7f05d4a 13734 else if (!INTEL_INFO(dev_priv)->cursor_needs_physical)
be1e3415 13735 addr = intel_plane_ggtt_offset(state);
f4a2cf29 13736 else
a912f12f 13737 addr = obj->phys_handle->busaddr;
852e787c 13738
a912f12f 13739 intel_crtc->cursor_addr = addr;
a0864d59 13740 intel_crtc_update_cursor(crtc, state);
852e787c
GP
13741}
13742
b079bd17 13743static struct intel_plane *
580503c7 13744intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
3d7d6510 13745{
fca0ce2a
VS
13746 struct intel_plane *cursor = NULL;
13747 struct intel_plane_state *state = NULL;
13748 int ret;
3d7d6510
MR
13749
13750 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
b079bd17
VS
13751 if (!cursor) {
13752 ret = -ENOMEM;
fca0ce2a 13753 goto fail;
b079bd17 13754 }
3d7d6510 13755
8e7d688b 13756 state = intel_create_plane_state(&cursor->base);
b079bd17
VS
13757 if (!state) {
13758 ret = -ENOMEM;
fca0ce2a 13759 goto fail;
b079bd17
VS
13760 }
13761
8e7d688b 13762 cursor->base.state = &state->base;
ea2c67bb 13763
3d7d6510
MR
13764 cursor->can_scale = false;
13765 cursor->max_downscale = 1;
13766 cursor->pipe = pipe;
13767 cursor->plane = pipe;
b14e5848 13768 cursor->id = PLANE_CURSOR;
a9ff8714 13769 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
c59cb179 13770 cursor->check_plane = intel_check_cursor_plane;
55a08b3f 13771 cursor->update_plane = intel_update_cursor_plane;
a8ad0d8e 13772 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510 13773
580503c7 13774 ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
f79f2692 13775 0, &intel_cursor_plane_funcs,
fca0ce2a
VS
13776 intel_cursor_formats,
13777 ARRAY_SIZE(intel_cursor_formats),
38573dc1
VS
13778 DRM_PLANE_TYPE_CURSOR,
13779 "cursor %c", pipe_name(pipe));
fca0ce2a
VS
13780 if (ret)
13781 goto fail;
4398ad45 13782
5481e27f 13783 if (INTEL_GEN(dev_priv) >= 4)
93ca7e00
VS
13784 drm_plane_create_rotation_property(&cursor->base,
13785 DRM_ROTATE_0,
13786 DRM_ROTATE_0 |
13787 DRM_ROTATE_180);
4398ad45 13788
580503c7 13789 if (INTEL_GEN(dev_priv) >= 9)
af99ceda
CK
13790 state->scaler_id = -1;
13791
ea2c67bb
MR
13792 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13793
b079bd17 13794 return cursor;
fca0ce2a
VS
13795
13796fail:
13797 kfree(state);
13798 kfree(cursor);
13799
b079bd17 13800 return ERR_PTR(ret);
3d7d6510
MR
13801}
13802
1c74eeaf
NM
13803static void intel_crtc_init_scalers(struct intel_crtc *crtc,
13804 struct intel_crtc_state *crtc_state)
549e2bfb 13805{
65edccce
VS
13806 struct intel_crtc_scaler_state *scaler_state =
13807 &crtc_state->scaler_state;
1c74eeaf 13808 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
549e2bfb 13809 int i;
549e2bfb 13810
1c74eeaf
NM
13811 crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe];
13812 if (!crtc->num_scalers)
13813 return;
13814
65edccce
VS
13815 for (i = 0; i < crtc->num_scalers; i++) {
13816 struct intel_scaler *scaler = &scaler_state->scalers[i];
13817
13818 scaler->in_use = 0;
13819 scaler->mode = PS_SCALER_MODE_DYN;
549e2bfb
CK
13820 }
13821
13822 scaler_state->scaler_id = -1;
13823}
13824
5ab0d85b 13825static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe)
79e53945
JB
13826{
13827 struct intel_crtc *intel_crtc;
f5de6e07 13828 struct intel_crtc_state *crtc_state = NULL;
b079bd17
VS
13829 struct intel_plane *primary = NULL;
13830 struct intel_plane *cursor = NULL;
a81d6fa0 13831 int sprite, ret;
79e53945 13832
955382f3 13833 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
b079bd17
VS
13834 if (!intel_crtc)
13835 return -ENOMEM;
79e53945 13836
f5de6e07 13837 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
b079bd17
VS
13838 if (!crtc_state) {
13839 ret = -ENOMEM;
f5de6e07 13840 goto fail;
b079bd17 13841 }
550acefd
ACO
13842 intel_crtc->config = crtc_state;
13843 intel_crtc->base.state = &crtc_state->base;
07878248 13844 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 13845
580503c7 13846 primary = intel_primary_plane_create(dev_priv, pipe);
b079bd17
VS
13847 if (IS_ERR(primary)) {
13848 ret = PTR_ERR(primary);
3d7d6510 13849 goto fail;
b079bd17 13850 }
d97d7b48 13851 intel_crtc->plane_ids_mask |= BIT(primary->id);
3d7d6510 13852
a81d6fa0 13853 for_each_sprite(dev_priv, pipe, sprite) {
b079bd17
VS
13854 struct intel_plane *plane;
13855
580503c7 13856 plane = intel_sprite_plane_create(dev_priv, pipe, sprite);
d2b2cbce 13857 if (IS_ERR(plane)) {
b079bd17
VS
13858 ret = PTR_ERR(plane);
13859 goto fail;
13860 }
d97d7b48 13861 intel_crtc->plane_ids_mask |= BIT(plane->id);
a81d6fa0
VS
13862 }
13863
580503c7 13864 cursor = intel_cursor_plane_create(dev_priv, pipe);
d2b2cbce 13865 if (IS_ERR(cursor)) {
b079bd17 13866 ret = PTR_ERR(cursor);
3d7d6510 13867 goto fail;
b079bd17 13868 }
d97d7b48 13869 intel_crtc->plane_ids_mask |= BIT(cursor->id);
3d7d6510 13870
5ab0d85b 13871 ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base,
b079bd17
VS
13872 &primary->base, &cursor->base,
13873 &intel_crtc_funcs,
4d5d72b7 13874 "pipe %c", pipe_name(pipe));
3d7d6510
MR
13875 if (ret)
13876 goto fail;
79e53945 13877
80824003 13878 intel_crtc->pipe = pipe;
e3c566df 13879 intel_crtc->plane = primary->plane;
80824003 13880
4b0e333e
CW
13881 intel_crtc->cursor_base = ~0;
13882 intel_crtc->cursor_cntl = ~0;
dc41c154 13883 intel_crtc->cursor_size = ~0;
8d7849db 13884
1c74eeaf
NM
13885 /* initialize shared scalers */
13886 intel_crtc_init_scalers(intel_crtc, crtc_state);
13887
22fd0fab
JB
13888 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13889 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
e2af48c6
VS
13890 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc;
13891 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc;
22fd0fab 13892
79e53945 13893 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101 13894
8563b1e8
LL
13895 intel_color_init(&intel_crtc->base);
13896
87b6b101 13897 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
b079bd17
VS
13898
13899 return 0;
3d7d6510
MR
13900
13901fail:
b079bd17
VS
13902 /*
13903 * drm_mode_config_cleanup() will free up any
13904 * crtcs/planes already initialized.
13905 */
f5de6e07 13906 kfree(crtc_state);
3d7d6510 13907 kfree(intel_crtc);
b079bd17
VS
13908
13909 return ret;
79e53945
JB
13910}
13911
752aa88a
JB
13912enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13913{
6e9f798d 13914 struct drm_device *dev = connector->base.dev;
752aa88a 13915
51fd371b 13916 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 13917
51ec53da 13918 if (!connector->base.state->crtc)
752aa88a
JB
13919 return INVALID_PIPE;
13920
51ec53da 13921 return to_intel_crtc(connector->base.state->crtc)->pipe;
752aa88a
JB
13922}
13923
08d7b3d1 13924int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 13925 struct drm_file *file)
08d7b3d1 13926{
08d7b3d1 13927 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 13928 struct drm_crtc *drmmode_crtc;
c05422d5 13929 struct intel_crtc *crtc;
08d7b3d1 13930
7707e653 13931 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
71240ed2 13932 if (!drmmode_crtc)
3f2c2057 13933 return -ENOENT;
08d7b3d1 13934
7707e653 13935 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 13936 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 13937
c05422d5 13938 return 0;
08d7b3d1
CW
13939}
13940
66a9278e 13941static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 13942{
66a9278e
DV
13943 struct drm_device *dev = encoder->base.dev;
13944 struct intel_encoder *source_encoder;
79e53945 13945 int index_mask = 0;
79e53945
JB
13946 int entry = 0;
13947
b2784e15 13948 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 13949 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV
13950 index_mask |= (1 << entry);
13951
79e53945
JB
13952 entry++;
13953 }
4ef69c7a 13954
79e53945
JB
13955 return index_mask;
13956}
13957
646d5772 13958static bool has_edp_a(struct drm_i915_private *dev_priv)
4d302442 13959{
646d5772 13960 if (!IS_MOBILE(dev_priv))
4d302442
CW
13961 return false;
13962
13963 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13964 return false;
13965
5db94019 13966 if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW
13967 return false;
13968
13969 return true;
13970}
13971
6315b5d3 13972static bool intel_crt_present(struct drm_i915_private *dev_priv)
84b4e042 13973{
6315b5d3 13974 if (INTEL_GEN(dev_priv) >= 9)
884497ed
DL
13975 return false;
13976
50a0bc90 13977 if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
84b4e042
JB
13978 return false;
13979
920a14b2 13980 if (IS_CHERRYVIEW(dev_priv))
84b4e042
JB
13981 return false;
13982
4f8036a2
TU
13983 if (HAS_PCH_LPT_H(dev_priv) &&
13984 I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
65e472e4
VS
13985 return false;
13986
70ac54d0 13987 /* DDI E can't be used if DDI A requires 4 lanes */
4f8036a2 13988 if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
70ac54d0
VS
13989 return false;
13990
e4abb733 13991 if (!dev_priv->vbt.int_crt_support)
84b4e042
JB
13992 return false;
13993
13994 return true;
13995}
13996
8090ba8c
ID
13997void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv)
13998{
13999 int pps_num;
14000 int pps_idx;
14001
14002 if (HAS_DDI(dev_priv))
14003 return;
14004 /*
14005 * This w/a is needed at least on CPT/PPT, but to be sure apply it
14006 * everywhere where registers can be write protected.
14007 */
14008 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14009 pps_num = 2;
14010 else
14011 pps_num = 1;
14012
14013 for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
14014 u32 val = I915_READ(PP_CONTROL(pps_idx));
14015
14016 val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS;
14017 I915_WRITE(PP_CONTROL(pps_idx), val);
14018 }
14019}
14020
44cb734c
ID
14021static void intel_pps_init(struct drm_i915_private *dev_priv)
14022{
cc3f90f0 14023 if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv))
44cb734c
ID
14024 dev_priv->pps_mmio_base = PCH_PPS_BASE;
14025 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14026 dev_priv->pps_mmio_base = VLV_PPS_BASE;
14027 else
14028 dev_priv->pps_mmio_base = PPS_BASE;
8090ba8c
ID
14029
14030 intel_pps_unlock_regs_wa(dev_priv);
44cb734c
ID
14031}
14032
c39055b0 14033static void intel_setup_outputs(struct drm_i915_private *dev_priv)
79e53945 14034{
4ef69c7a 14035 struct intel_encoder *encoder;
cb0953d7 14036 bool dpd_is_edp = false;
79e53945 14037
44cb734c
ID
14038 intel_pps_init(dev_priv);
14039
97a824e1
ID
14040 /*
14041 * intel_edp_init_connector() depends on this completing first, to
14042 * prevent the registeration of both eDP and LVDS and the incorrect
14043 * sharing of the PPS.
14044 */
c39055b0 14045 intel_lvds_init(dev_priv);
79e53945 14046
6315b5d3 14047 if (intel_crt_present(dev_priv))
c39055b0 14048 intel_crt_init(dev_priv);
cb0953d7 14049
cc3f90f0 14050 if (IS_GEN9_LP(dev_priv)) {
c776eb2e
VK
14051 /*
14052 * FIXME: Broxton doesn't support port detection via the
14053 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14054 * detect the ports.
14055 */
c39055b0
ACO
14056 intel_ddi_init(dev_priv, PORT_A);
14057 intel_ddi_init(dev_priv, PORT_B);
14058 intel_ddi_init(dev_priv, PORT_C);
c6c794a2 14059
c39055b0 14060 intel_dsi_init(dev_priv);
4f8036a2 14061 } else if (HAS_DDI(dev_priv)) {
0e72a5b5
ED
14062 int found;
14063
de31facd
JB
14064 /*
14065 * Haswell uses DDI functions to detect digital outputs.
14066 * On SKL pre-D0 the strap isn't connected, so we assume
14067 * it's there.
14068 */
77179400 14069 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
de31facd 14070 /* WaIgnoreDDIAStrap: skl */
b976dc53 14071 if (found || IS_GEN9_BC(dev_priv))
c39055b0 14072 intel_ddi_init(dev_priv, PORT_A);
0e72a5b5
ED
14073
14074 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14075 * register */
14076 found = I915_READ(SFUSE_STRAP);
14077
14078 if (found & SFUSE_STRAP_DDIB_DETECTED)
c39055b0 14079 intel_ddi_init(dev_priv, PORT_B);
0e72a5b5 14080 if (found & SFUSE_STRAP_DDIC_DETECTED)
c39055b0 14081 intel_ddi_init(dev_priv, PORT_C);
0e72a5b5 14082 if (found & SFUSE_STRAP_DDID_DETECTED)
c39055b0 14083 intel_ddi_init(dev_priv, PORT_D);
2800e4c2
RV
14084 /*
14085 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14086 */
b976dc53 14087 if (IS_GEN9_BC(dev_priv) &&
2800e4c2
RV
14088 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14089 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14090 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
c39055b0 14091 intel_ddi_init(dev_priv, PORT_E);
2800e4c2 14092
6e266956 14093 } else if (HAS_PCH_SPLIT(dev_priv)) {
cb0953d7 14094 int found;
dd11bc10 14095 dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D);
270b3042 14096
646d5772 14097 if (has_edp_a(dev_priv))
c39055b0 14098 intel_dp_init(dev_priv, DP_A, PORT_A);
cb0953d7 14099
dc0fa718 14100 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 14101 /* PCH SDVOB multiplex with HDMIB */
c39055b0 14102 found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
30ad48b7 14103 if (!found)
c39055b0 14104 intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
5eb08b69 14105 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
c39055b0 14106 intel_dp_init(dev_priv, PCH_DP_B, PORT_B);
30ad48b7
ZW
14107 }
14108
dc0fa718 14109 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
c39055b0 14110 intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
30ad48b7 14111
dc0fa718 14112 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
c39055b0 14113 intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
30ad48b7 14114
5eb08b69 14115 if (I915_READ(PCH_DP_C) & DP_DETECTED)
c39055b0 14116 intel_dp_init(dev_priv, PCH_DP_C, PORT_C);
5eb08b69 14117
270b3042 14118 if (I915_READ(PCH_DP_D) & DP_DETECTED)
c39055b0 14119 intel_dp_init(dev_priv, PCH_DP_D, PORT_D);
920a14b2 14120 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
22f35042 14121 bool has_edp, has_port;
457c52d8 14122
e17ac6db
VS
14123 /*
14124 * The DP_DETECTED bit is the latched state of the DDC
14125 * SDA pin at boot. However since eDP doesn't require DDC
14126 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14127 * eDP ports may have been muxed to an alternate function.
14128 * Thus we can't rely on the DP_DETECTED bit alone to detect
14129 * eDP ports. Consult the VBT as well as DP_DETECTED to
14130 * detect eDP ports.
22f35042
VS
14131 *
14132 * Sadly the straps seem to be missing sometimes even for HDMI
14133 * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
14134 * and VBT for the presence of the port. Additionally we can't
14135 * trust the port type the VBT declares as we've seen at least
14136 * HDMI ports that the VBT claim are DP or eDP.
e17ac6db 14137 */
dd11bc10 14138 has_edp = intel_dp_is_edp(dev_priv, PORT_B);
22f35042
VS
14139 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
14140 if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port)
c39055b0 14141 has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B);
22f35042 14142 if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
c39055b0 14143 intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
585a94b8 14144
dd11bc10 14145 has_edp = intel_dp_is_edp(dev_priv, PORT_C);
22f35042
VS
14146 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
14147 if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port)
c39055b0 14148 has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C);
22f35042 14149 if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
c39055b0 14150 intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
19c03924 14151
920a14b2 14152 if (IS_CHERRYVIEW(dev_priv)) {
22f35042
VS
14153 /*
14154 * eDP not supported on port D,
14155 * so no need to worry about it
14156 */
14157 has_port = intel_bios_is_port_present(dev_priv, PORT_D);
14158 if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port)
c39055b0 14159 intel_dp_init(dev_priv, CHV_DP_D, PORT_D);
22f35042 14160 if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port)
c39055b0 14161 intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
9418c1f1
VS
14162 }
14163
c39055b0 14164 intel_dsi_init(dev_priv);
5db94019 14165 } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) {
27185ae1 14166 bool found = false;
7d57382e 14167
e2debe91 14168 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14169 DRM_DEBUG_KMS("probing SDVOB\n");
c39055b0 14170 found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
9beb5fea 14171 if (!found && IS_G4X(dev_priv)) {
b01f2c3a 14172 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
c39055b0 14173 intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
b01f2c3a 14174 }
27185ae1 14175
9beb5fea 14176 if (!found && IS_G4X(dev_priv))
c39055b0 14177 intel_dp_init(dev_priv, DP_B, PORT_B);
725e30ad 14178 }
13520b05
KH
14179
14180 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14181
e2debe91 14182 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14183 DRM_DEBUG_KMS("probing SDVOC\n");
c39055b0 14184 found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
b01f2c3a 14185 }
27185ae1 14186
e2debe91 14187 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14188
9beb5fea 14189 if (IS_G4X(dev_priv)) {
b01f2c3a 14190 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
c39055b0 14191 intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
b01f2c3a 14192 }
9beb5fea 14193 if (IS_G4X(dev_priv))
c39055b0 14194 intel_dp_init(dev_priv, DP_C, PORT_C);
725e30ad 14195 }
27185ae1 14196
9beb5fea 14197 if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED))
c39055b0 14198 intel_dp_init(dev_priv, DP_D, PORT_D);
5db94019 14199 } else if (IS_GEN2(dev_priv))
c39055b0 14200 intel_dvo_init(dev_priv);
79e53945 14201
56b857a5 14202 if (SUPPORTS_TV(dev_priv))
c39055b0 14203 intel_tv_init(dev_priv);
79e53945 14204
c39055b0 14205 intel_psr_init(dev_priv);
7c8f8a70 14206
c39055b0 14207 for_each_intel_encoder(&dev_priv->drm, encoder) {
4ef69c7a
CW
14208 encoder->base.possible_crtcs = encoder->crtc_mask;
14209 encoder->base.possible_clones =
66a9278e 14210 intel_encoder_clones(encoder);
79e53945 14211 }
47356eb6 14212
c39055b0 14213 intel_init_pch_refclk(dev_priv);
270b3042 14214
c39055b0 14215 drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
79e53945
JB
14216}
14217
14218static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14219{
14220 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14221
ef2d633e 14222 drm_framebuffer_cleanup(fb);
70001cd2 14223
dd689287
CW
14224 i915_gem_object_lock(intel_fb->obj);
14225 WARN_ON(!intel_fb->obj->framebuffer_references--);
14226 i915_gem_object_unlock(intel_fb->obj);
14227
f8c417cd 14228 i915_gem_object_put(intel_fb->obj);
70001cd2 14229
79e53945
JB
14230 kfree(intel_fb);
14231}
14232
14233static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14234 struct drm_file *file,
79e53945
JB
14235 unsigned int *handle)
14236{
14237 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14238 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14239
cc917ab4
CW
14240 if (obj->userptr.mm) {
14241 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14242 return -EINVAL;
14243 }
14244
05394f39 14245 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB
14246}
14247
86c98588
RV
14248static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14249 struct drm_file *file,
14250 unsigned flags, unsigned color,
14251 struct drm_clip_rect *clips,
14252 unsigned num_clips)
14253{
5a97bcc6 14254 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
86c98588 14255
5a97bcc6 14256 i915_gem_object_flush_if_display(obj);
d59b21ec 14257 intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
86c98588
RV
14258
14259 return 0;
14260}
14261
79e53945
JB
14262static const struct drm_framebuffer_funcs intel_fb_funcs = {
14263 .destroy = intel_user_framebuffer_destroy,
14264 .create_handle = intel_user_framebuffer_create_handle,
86c98588 14265 .dirty = intel_user_framebuffer_dirty,
79e53945
JB
14266};
14267
b321803d 14268static
920a14b2
TU
14269u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
14270 uint64_t fb_modifier, uint32_t pixel_format)
b321803d 14271{
24dbf51a 14272 u32 gen = INTEL_GEN(dev_priv);
b321803d
DL
14273
14274 if (gen >= 9) {
ac484963
VS
14275 int cpp = drm_format_plane_cpp(pixel_format, 0);
14276
b321803d
DL
14277 /* "The stride in bytes must not exceed the of the size of 8K
14278 * pixels and 32K bytes."
14279 */
ac484963 14280 return min(8192 * cpp, 32768);
6401c37d 14281 } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
b321803d
DL
14282 return 32*1024;
14283 } else if (gen >= 4) {
14284 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14285 return 16*1024;
14286 else
14287 return 32*1024;
14288 } else if (gen >= 3) {
14289 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14290 return 8*1024;
14291 else
14292 return 16*1024;
14293 } else {
14294 /* XXX DSPC is limited to 4k tiled */
14295 return 8*1024;
14296 }
14297}
14298
24dbf51a
CW
14299static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
14300 struct drm_i915_gem_object *obj,
14301 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14302{
24dbf51a 14303 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
b3c11ac2 14304 struct drm_format_name_buf format_name;
dd689287
CW
14305 u32 pitch_limit, stride_alignment;
14306 unsigned int tiling, stride;
24dbf51a 14307 int ret = -EINVAL;
79e53945 14308
dd689287
CW
14309 i915_gem_object_lock(obj);
14310 obj->framebuffer_references++;
14311 tiling = i915_gem_object_get_tiling(obj);
14312 stride = i915_gem_object_get_stride(obj);
14313 i915_gem_object_unlock(obj);
dd4916c5 14314
2a80eada 14315 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
c2ff7370
VS
14316 /*
14317 * If there's a fence, enforce that
14318 * the fb modifier and tiling mode match.
14319 */
14320 if (tiling != I915_TILING_NONE &&
14321 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
144cc143 14322 DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n");
24dbf51a 14323 goto err;
2a80eada
DV
14324 }
14325 } else {
c2ff7370 14326 if (tiling == I915_TILING_X) {
2a80eada 14327 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
c2ff7370 14328 } else if (tiling == I915_TILING_Y) {
144cc143 14329 DRM_DEBUG_KMS("No Y tiling for legacy addfb\n");
24dbf51a 14330 goto err;
2a80eada
DV
14331 }
14332 }
14333
9a8f0a12
TU
14334 /* Passed in modifier sanity checking. */
14335 switch (mode_cmd->modifier[0]) {
14336 case I915_FORMAT_MOD_Y_TILED:
14337 case I915_FORMAT_MOD_Yf_TILED:
6315b5d3 14338 if (INTEL_GEN(dev_priv) < 9) {
144cc143
VS
14339 DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n",
14340 mode_cmd->modifier[0]);
24dbf51a 14341 goto err;
9a8f0a12 14342 }
2f075565 14343 case DRM_FORMAT_MOD_LINEAR:
9a8f0a12
TU
14344 case I915_FORMAT_MOD_X_TILED:
14345 break;
14346 default:
144cc143
VS
14347 DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n",
14348 mode_cmd->modifier[0]);
24dbf51a 14349 goto err;
c16ed4be 14350 }
57cd6508 14351
c2ff7370
VS
14352 /*
14353 * gen2/3 display engine uses the fence if present,
14354 * so the tiling mode must match the fb modifier exactly.
14355 */
14356 if (INTEL_INFO(dev_priv)->gen < 4 &&
14357 tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) {
144cc143 14358 DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n");
9aceb5c1 14359 goto err;
c2ff7370
VS
14360 }
14361
920a14b2 14362 pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
b321803d 14363 mode_cmd->pixel_format);
a35cdaa0 14364 if (mode_cmd->pitches[0] > pitch_limit) {
144cc143 14365 DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
2f075565 14366 mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
144cc143
VS
14367 "tiled" : "linear",
14368 mode_cmd->pitches[0], pitch_limit);
24dbf51a 14369 goto err;
c16ed4be 14370 }
5d7bd705 14371
c2ff7370
VS
14372 /*
14373 * If there's a fence, enforce that
14374 * the fb pitch and fence stride match.
14375 */
144cc143
VS
14376 if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) {
14377 DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n",
14378 mode_cmd->pitches[0], stride);
24dbf51a 14379 goto err;
c16ed4be 14380 }
5d7bd705 14381
57779d06 14382 /* Reject formats not supported by any plane early. */
308e5bcb 14383 switch (mode_cmd->pixel_format) {
57779d06 14384 case DRM_FORMAT_C8:
04b3924d
VS
14385 case DRM_FORMAT_RGB565:
14386 case DRM_FORMAT_XRGB8888:
14387 case DRM_FORMAT_ARGB8888:
57779d06
VS
14388 break;
14389 case DRM_FORMAT_XRGB1555:
6315b5d3 14390 if (INTEL_GEN(dev_priv) > 3) {
144cc143
VS
14391 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14392 drm_get_format_name(mode_cmd->pixel_format, &format_name));
9aceb5c1 14393 goto err;
c16ed4be 14394 }
57779d06 14395 break;
57779d06 14396 case DRM_FORMAT_ABGR8888:
920a14b2 14397 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
6315b5d3 14398 INTEL_GEN(dev_priv) < 9) {
144cc143
VS
14399 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14400 drm_get_format_name(mode_cmd->pixel_format, &format_name));
9aceb5c1 14401 goto err;
6c0fd451
DL
14402 }
14403 break;
14404 case DRM_FORMAT_XBGR8888:
04b3924d 14405 case DRM_FORMAT_XRGB2101010:
57779d06 14406 case DRM_FORMAT_XBGR2101010:
6315b5d3 14407 if (INTEL_GEN(dev_priv) < 4) {
144cc143
VS
14408 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14409 drm_get_format_name(mode_cmd->pixel_format, &format_name));
9aceb5c1 14410 goto err;
c16ed4be 14411 }
b5626747 14412 break;
7531208b 14413 case DRM_FORMAT_ABGR2101010:
920a14b2 14414 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
144cc143
VS
14415 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14416 drm_get_format_name(mode_cmd->pixel_format, &format_name));
9aceb5c1 14417 goto err;
7531208b
DL
14418 }
14419 break;
04b3924d
VS
14420 case DRM_FORMAT_YUYV:
14421 case DRM_FORMAT_UYVY:
14422 case DRM_FORMAT_YVYU:
14423 case DRM_FORMAT_VYUY:
6315b5d3 14424 if (INTEL_GEN(dev_priv) < 5) {
144cc143
VS
14425 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14426 drm_get_format_name(mode_cmd->pixel_format, &format_name));
9aceb5c1 14427 goto err;
c16ed4be 14428 }
57cd6508
CW
14429 break;
14430 default:
144cc143
VS
14431 DRM_DEBUG_KMS("unsupported pixel format: %s\n",
14432 drm_get_format_name(mode_cmd->pixel_format, &format_name));
9aceb5c1 14433 goto err;
57cd6508
CW
14434 }
14435
90f9a336
VS
14436 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14437 if (mode_cmd->offsets[0] != 0)
24dbf51a 14438 goto err;
90f9a336 14439
24dbf51a
CW
14440 drm_helper_mode_fill_fb_struct(&dev_priv->drm,
14441 &intel_fb->base, mode_cmd);
d88c4afd
VS
14442
14443 stride_alignment = intel_fb_stride_alignment(&intel_fb->base, 0);
14444 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
144cc143
VS
14445 DRM_DEBUG_KMS("pitch (%d) must be at least %u byte aligned\n",
14446 mode_cmd->pitches[0], stride_alignment);
d88c4afd
VS
14447 goto err;
14448 }
14449
c7d73f6a
DV
14450 intel_fb->obj = obj;
14451
6687c906
VS
14452 ret = intel_fill_fb_info(dev_priv, &intel_fb->base);
14453 if (ret)
9aceb5c1 14454 goto err;
2d7a215f 14455
24dbf51a
CW
14456 ret = drm_framebuffer_init(obj->base.dev,
14457 &intel_fb->base,
14458 &intel_fb_funcs);
79e53945
JB
14459 if (ret) {
14460 DRM_ERROR("framebuffer init failed %d\n", ret);
24dbf51a 14461 goto err;
79e53945
JB
14462 }
14463
79e53945 14464 return 0;
24dbf51a
CW
14465
14466err:
dd689287
CW
14467 i915_gem_object_lock(obj);
14468 obj->framebuffer_references--;
14469 i915_gem_object_unlock(obj);
24dbf51a 14470 return ret;
79e53945
JB
14471}
14472
79e53945
JB
14473static struct drm_framebuffer *
14474intel_user_framebuffer_create(struct drm_device *dev,
14475 struct drm_file *filp,
1eb83451 14476 const struct drm_mode_fb_cmd2 *user_mode_cmd)
79e53945 14477{
dcb1394e 14478 struct drm_framebuffer *fb;
05394f39 14479 struct drm_i915_gem_object *obj;
76dc3769 14480 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
79e53945 14481
03ac0642
CW
14482 obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]);
14483 if (!obj)
cce13ff7 14484 return ERR_PTR(-ENOENT);
79e53945 14485
24dbf51a 14486 fb = intel_framebuffer_create(obj, &mode_cmd);
dcb1394e 14487 if (IS_ERR(fb))
f0cd5182 14488 i915_gem_object_put(obj);
dcb1394e
LW
14489
14490 return fb;
79e53945
JB
14491}
14492
778e23a9
CW
14493static void intel_atomic_state_free(struct drm_atomic_state *state)
14494{
14495 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
14496
14497 drm_atomic_state_default_release(state);
14498
14499 i915_sw_fence_fini(&intel_state->commit_ready);
14500
14501 kfree(state);
14502}
14503
79e53945 14504static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14505 .fb_create = intel_user_framebuffer_create,
0632fef6 14506 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR
14507 .atomic_check = intel_atomic_check,
14508 .atomic_commit = intel_atomic_commit,
de419ab6
ML
14509 .atomic_state_alloc = intel_atomic_state_alloc,
14510 .atomic_state_clear = intel_atomic_state_clear,
778e23a9 14511 .atomic_state_free = intel_atomic_state_free,
79e53945
JB
14512};
14513
88212941
ID
14514/**
14515 * intel_init_display_hooks - initialize the display modesetting hooks
14516 * @dev_priv: device private
14517 */
14518void intel_init_display_hooks(struct drm_i915_private *dev_priv)
e70236a8 14519{
7ff89ca2
VS
14520 intel_init_cdclk_hooks(dev_priv);
14521
88212941 14522 if (INTEL_INFO(dev_priv)->gen >= 9) {
bc8d7dff 14523 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL
14524 dev_priv->display.get_initial_plane_config =
14525 skylake_get_initial_plane_config;
bc8d7dff
DL
14526 dev_priv->display.crtc_compute_clock =
14527 haswell_crtc_compute_clock;
14528 dev_priv->display.crtc_enable = haswell_crtc_enable;
14529 dev_priv->display.crtc_disable = haswell_crtc_disable;
88212941 14530 } else if (HAS_DDI(dev_priv)) {
0e8ffe1b 14531 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL
14532 dev_priv->display.get_initial_plane_config =
14533 ironlake_get_initial_plane_config;
797d0259
ACO
14534 dev_priv->display.crtc_compute_clock =
14535 haswell_crtc_compute_clock;
4f771f10
PZ
14536 dev_priv->display.crtc_enable = haswell_crtc_enable;
14537 dev_priv->display.crtc_disable = haswell_crtc_disable;
88212941 14538 } else if (HAS_PCH_SPLIT(dev_priv)) {
0e8ffe1b 14539 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL
14540 dev_priv->display.get_initial_plane_config =
14541 ironlake_get_initial_plane_config;
3fb37703
ACO
14542 dev_priv->display.crtc_compute_clock =
14543 ironlake_crtc_compute_clock;
76e5a89c
DV
14544 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14545 dev_priv->display.crtc_disable = ironlake_crtc_disable;
65b3d6a9 14546 } else if (IS_CHERRYVIEW(dev_priv)) {
89b667f8 14547 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL
14548 dev_priv->display.get_initial_plane_config =
14549 i9xx_get_initial_plane_config;
65b3d6a9
ACO
14550 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14551 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14552 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14553 } else if (IS_VALLEYVIEW(dev_priv)) {
14554 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14555 dev_priv->display.get_initial_plane_config =
14556 i9xx_get_initial_plane_config;
14557 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
89b667f8
JB
14558 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14559 dev_priv->display.crtc_disable = i9xx_crtc_disable;
19ec6693
ACO
14560 } else if (IS_G4X(dev_priv)) {
14561 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14562 dev_priv->display.get_initial_plane_config =
14563 i9xx_get_initial_plane_config;
14564 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14565 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14566 dev_priv->display.crtc_disable = i9xx_crtc_disable;
70e8aa21
ACO
14567 } else if (IS_PINEVIEW(dev_priv)) {
14568 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14569 dev_priv->display.get_initial_plane_config =
14570 i9xx_get_initial_plane_config;
14571 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14572 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14573 dev_priv->display.crtc_disable = i9xx_crtc_disable;
81c97f52 14574 } else if (!IS_GEN2(dev_priv)) {
0e8ffe1b 14575 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL
14576 dev_priv->display.get_initial_plane_config =
14577 i9xx_get_initial_plane_config;
d6dfee7a 14578 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV
14579 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14580 dev_priv->display.crtc_disable = i9xx_crtc_disable;
81c97f52
ACO
14581 } else {
14582 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14583 dev_priv->display.get_initial_plane_config =
14584 i9xx_get_initial_plane_config;
14585 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14586 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14587 dev_priv->display.crtc_disable = i9xx_crtc_disable;
f564048e 14588 }
e70236a8 14589
88212941 14590 if (IS_GEN5(dev_priv)) {
3bb11b53 14591 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
88212941 14592 } else if (IS_GEN6(dev_priv)) {
3bb11b53 14593 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
88212941 14594 } else if (IS_IVYBRIDGE(dev_priv)) {
3bb11b53
SJ
14595 /* FIXME: detect B0+ stepping and use auto training */
14596 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
88212941 14597 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3bb11b53 14598 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
445e780b
VS
14599 }
14600
27082493
L
14601 if (dev_priv->info.gen >= 9)
14602 dev_priv->display.update_crtcs = skl_update_crtcs;
14603 else
14604 dev_priv->display.update_crtcs = intel_update_crtcs;
14605
5a21b665
DV
14606 switch (INTEL_INFO(dev_priv)->gen) {
14607 case 2:
14608 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14609 break;
14610
14611 case 3:
14612 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14613 break;
14614
14615 case 4:
14616 case 5:
14617 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14618 break;
14619
14620 case 6:
14621 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14622 break;
14623 case 7:
14624 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14625 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14626 break;
14627 case 9:
14628 /* Drop through - unsupported since execlist only. */
14629 default:
14630 /* Default just returns -ENODEV to indicate unsupported */
14631 dev_priv->display.queue_flip = intel_default_queue_flip;
14632 }
e70236a8
JB
14633}
14634
b690e96c
JB
14635/*
14636 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14637 * resume, or other times. This quirk makes sure that's the case for
14638 * affected systems.
14639 */
0206e353 14640static void quirk_pipea_force(struct drm_device *dev)
b690e96c 14641{
fac5e23e 14642 struct drm_i915_private *dev_priv = to_i915(dev);
b690e96c
JB
14643
14644 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14645 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB
14646}
14647
b6b5d049
VS
14648static void quirk_pipeb_force(struct drm_device *dev)
14649{
fac5e23e 14650 struct drm_i915_private *dev_priv = to_i915(dev);
b6b5d049
VS
14651
14652 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14653 DRM_INFO("applying pipe b force quirk\n");
14654}
14655
435793df
KP
14656/*
14657 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14658 */
14659static void quirk_ssc_force_disable(struct drm_device *dev)
14660{
fac5e23e 14661 struct drm_i915_private *dev_priv = to_i915(dev);
435793df 14662 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14663 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP
14664}
14665
4dca20ef 14666/*
5a15ab5b
CE
14667 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14668 * brightness value
4dca20ef
CE
14669 */
14670static void quirk_invert_brightness(struct drm_device *dev)
14671{
fac5e23e 14672 struct drm_i915_private *dev_priv = to_i915(dev);
4dca20ef 14673 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14674 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP
14675}
14676
9c72cc6f
SD
14677/* Some VBT's incorrectly indicate no backlight is present */
14678static void quirk_backlight_present(struct drm_device *dev)
14679{
fac5e23e 14680 struct drm_i915_private *dev_priv = to_i915(dev);
9c72cc6f
SD
14681 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14682 DRM_INFO("applying backlight present quirk\n");
14683}
14684
b690e96c
JB
14685struct intel_quirk {
14686 int device;
14687 int subsystem_vendor;
14688 int subsystem_device;
14689 void (*hook)(struct drm_device *dev);
14690};
14691
5f85f176
EE
14692/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14693struct intel_dmi_quirk {
14694 void (*hook)(struct drm_device *dev);
14695 const struct dmi_system_id (*dmi_id_list)[];
14696};
14697
14698static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14699{
14700 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14701 return 1;
14702}
14703
14704static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14705 {
14706 .dmi_id_list = &(const struct dmi_system_id[]) {
14707 {
14708 .callback = intel_dmi_reverse_brightness,
14709 .ident = "NCR Corporation",
14710 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14711 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14712 },
14713 },
14714 { } /* terminating entry */
14715 },
14716 .hook = quirk_invert_brightness,
14717 },
14718};
14719
c43b5634 14720static struct intel_quirk intel_quirks[] = {
b690e96c
JB
14721 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14722 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14723
b690e96c
JB
14724 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14725 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14726
5f080c0f
VS
14727 /* 830 needs to leave pipe A & dpll A up */
14728 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14729
b6b5d049
VS
14730 /* 830 needs to leave pipe B & dpll B up */
14731 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14732
435793df
KP
14733 /* Lenovo U160 cannot use SSC on LVDS */
14734 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS
14735
14736 /* Sony Vaio Y cannot use SSC on LVDS */
14737 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14738
be505f64
AH
14739 /* Acer Aspire 5734Z must invert backlight brightness */
14740 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14741
14742 /* Acer/eMachines G725 */
14743 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14744
14745 /* Acer/eMachines e725 */
14746 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14747
14748 /* Acer/Packard Bell NCL20 */
14749 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14750
14751 /* Acer Aspire 4736Z */
14752 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN
14753
14754 /* Acer Aspire 5336 */
14755 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD
14756
14757 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14758 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14759
dfb3d47b
SD
14760 /* Acer C720 Chromebook (Core i3 4005U) */
14761 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14762
b2a9601c 14763 /* Apple Macbook 2,1 (Core 2 T7400) */
14764 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14765
1b9448b0
JN
14766 /* Apple Macbook 4,1 */
14767 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
14768
d4967d8c
SD
14769 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14770 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD
14771
14772 /* HP Chromebook 14 (Celeron 2955U) */
14773 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN
14774
14775 /* Dell Chromebook 11 */
14776 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
9be64eee
JN
14777
14778 /* Dell Chromebook 11 (2015 version) */
14779 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB
14780};
14781
14782static void intel_init_quirks(struct drm_device *dev)
14783{
14784 struct pci_dev *d = dev->pdev;
14785 int i;
14786
14787 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14788 struct intel_quirk *q = &intel_quirks[i];
14789
14790 if (d->device == q->device &&
14791 (d->subsystem_vendor == q->subsystem_vendor ||
14792 q->subsystem_vendor == PCI_ANY_ID) &&
14793 (d->subsystem_device == q->subsystem_device ||
14794 q->subsystem_device == PCI_ANY_ID))
14795 q->hook(dev);
14796 }
5f85f176
EE
14797 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14798 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14799 intel_dmi_quirks[i].hook(dev);
14800 }
b690e96c
JB
14801}
14802
9cce37f4 14803/* Disable the VGA plane that we never use */
29b74b7f 14804static void i915_disable_vga(struct drm_i915_private *dev_priv)
9cce37f4 14805{
52a05c30 14806 struct pci_dev *pdev = dev_priv->drm.pdev;
9cce37f4 14807 u8 sr1;
920a14b2 14808 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
9cce37f4 14809
2b37c616 14810 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
52a05c30 14811 vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14812 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB
14813 sr1 = inb(VGA_SR_DATA);
14814 outb(sr1 | 1<<5, VGA_SR_DATA);
52a05c30 14815 vga_put(pdev, VGA_RSRC_LEGACY_IO);
9cce37f4
JB
14816 udelay(300);
14817
01f5a626 14818 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB
14819 POSTING_READ(vga_reg);
14820}
14821
f817586c
DV
14822void intel_modeset_init_hw(struct drm_device *dev)
14823{
fac5e23e 14824 struct drm_i915_private *dev_priv = to_i915(dev);
1a617b77 14825
4c75b940 14826 intel_update_cdclk(dev_priv);
bb0f4aab 14827 dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw;
1a617b77 14828
46f16e63 14829 intel_init_clock_gating(dev_priv);
f817586c
DV
14830}
14831
d93c0372
MR
14832/*
14833 * Calculate what we think the watermarks should be for the state we've read
14834 * out of the hardware and then immediately program those watermarks so that
14835 * we ensure the hardware settings match our internal state.
14836 *
14837 * We can calculate what we think WM's should be by creating a duplicate of the
14838 * current state (which was constructed during hardware readout) and running it
14839 * through the atomic check code to calculate new watermark values in the
14840 * state object.
14841 */
14842static void sanitize_watermarks(struct drm_device *dev)
14843{
14844 struct drm_i915_private *dev_priv = to_i915(dev);
14845 struct drm_atomic_state *state;
ccf010fb 14846 struct intel_atomic_state *intel_state;
d93c0372
MR
14847 struct drm_crtc *crtc;
14848 struct drm_crtc_state *cstate;
14849 struct drm_modeset_acquire_ctx ctx;
14850 int ret;
14851 int i;
14852
14853 /* Only supported on platforms that use atomic watermark design */
ed4a6a7c 14854 if (!dev_priv->display.optimize_watermarks)
d93c0372
MR
14855 return;
14856
14857 /*
14858 * We need to hold connection_mutex before calling duplicate_state so
14859 * that the connector loop is protected.
14860 */
14861 drm_modeset_acquire_init(&ctx, 0);
14862retry:
0cd1262d 14863 ret = drm_modeset_lock_all_ctx(dev, &ctx);
d93c0372
MR
14864 if (ret == -EDEADLK) {
14865 drm_modeset_backoff(&ctx);
14866 goto retry;
14867 } else if (WARN_ON(ret)) {
0cd1262d 14868 goto fail;
d93c0372
MR
14869 }
14870
14871 state = drm_atomic_helper_duplicate_state(dev, &ctx);
14872 if (WARN_ON(IS_ERR(state)))
0cd1262d 14873 goto fail;
d93c0372 14874
ccf010fb
ML
14875 intel_state = to_intel_atomic_state(state);
14876
ed4a6a7c
MR
14877 /*
14878 * Hardware readout is the only time we don't want to calculate
14879 * intermediate watermarks (since we don't trust the current
14880 * watermarks).
14881 */
602ae835
VS
14882 if (!HAS_GMCH_DISPLAY(dev_priv))
14883 intel_state->skip_intermediate_wm = true;
ed4a6a7c 14884
d93c0372
MR
14885 ret = intel_atomic_check(dev, state);
14886 if (ret) {
14887 /*
14888 * If we fail here, it means that the hardware appears to be
14889 * programmed in a way that shouldn't be possible, given our
14890 * understanding of watermark requirements. This might mean a
14891 * mistake in the hardware readout code or a mistake in the
14892 * watermark calculations for a given platform. Raise a WARN
14893 * so that this is noticeable.
14894 *
14895 * If this actually happens, we'll have to just leave the
14896 * BIOS-programmed watermarks untouched and hope for the best.
14897 */
14898 WARN(true, "Could not determine valid watermarks for inherited state\n");
b9a1b717 14899 goto put_state;
d93c0372
MR
14900 }
14901
14902 /* Write calculated watermark values back */
aa5e9b47 14903 for_each_new_crtc_in_state(state, crtc, cstate, i) {
d93c0372
MR
14904 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
14905
ed4a6a7c 14906 cs->wm.need_postvbl_update = true;
ccf010fb 14907 dev_priv->display.optimize_watermarks(intel_state, cs);
d93c0372
MR
14908 }
14909
b9a1b717 14910put_state:
0853695c 14911 drm_atomic_state_put(state);
0cd1262d 14912fail:
d93c0372
MR
14913 drm_modeset_drop_locks(&ctx);
14914 drm_modeset_acquire_fini(&ctx);
14915}
14916
b079bd17 14917int intel_modeset_init(struct drm_device *dev)
79e53945 14918{
72e96d64
JL
14919 struct drm_i915_private *dev_priv = to_i915(dev);
14920 struct i915_ggtt *ggtt = &dev_priv->ggtt;
8cc87b75 14921 enum pipe pipe;
46f297fb 14922 struct intel_crtc *crtc;
79e53945
JB
14923
14924 drm_mode_config_init(dev);
14925
14926 dev->mode_config.min_width = 0;
14927 dev->mode_config.min_height = 0;
14928
019d96cb
DA
14929 dev->mode_config.preferred_depth = 24;
14930 dev->mode_config.prefer_shadow = 1;
14931
25bab385
TU
14932 dev->mode_config.allow_fb_modifiers = true;
14933
e6ecefaa 14934 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14935
400c19d9 14936 init_llist_head(&dev_priv->atomic_helper.free_list);
eb955eee 14937 INIT_WORK(&dev_priv->atomic_helper.free_work,
ba318c61 14938 intel_atomic_helper_free_state_worker);
eb955eee 14939
b690e96c
JB
14940 intel_init_quirks(dev);
14941
62d75df7 14942 intel_init_pm(dev_priv);
1fa61106 14943
b7f05d4a 14944 if (INTEL_INFO(dev_priv)->num_pipes == 0)
b079bd17 14945 return 0;
e3c74757 14946
69f92f67
LW
14947 /*
14948 * There may be no VBT; and if the BIOS enabled SSC we can
14949 * just keep using it to avoid unnecessary flicker. Whereas if the
14950 * BIOS isn't using it, don't assume it will work even if the VBT
14951 * indicates as much.
14952 */
6e266956 14953 if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
69f92f67
LW
14954 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14955 DREF_SSC1_ENABLE);
14956
14957 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
14958 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14959 bios_lvds_use_ssc ? "en" : "dis",
14960 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
14961 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
14962 }
14963 }
14964
5db94019 14965 if (IS_GEN2(dev_priv)) {
a6c45cf0
CW
14966 dev->mode_config.max_width = 2048;
14967 dev->mode_config.max_height = 2048;
5db94019 14968 } else if (IS_GEN3(dev_priv)) {
5e4d6fa7
KP
14969 dev->mode_config.max_width = 4096;
14970 dev->mode_config.max_height = 4096;
79e53945 14971 } else {
a6c45cf0
CW
14972 dev->mode_config.max_width = 8192;
14973 dev->mode_config.max_height = 8192;
79e53945 14974 }
068be561 14975
2a307c2e
JN
14976 if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
14977 dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512;
dc41c154 14978 dev->mode_config.cursor_height = 1023;
5db94019 14979 } else if (IS_GEN2(dev_priv)) {
068be561
DL
14980 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14981 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14982 } else {
14983 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14984 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14985 }
14986
72e96d64 14987 dev->mode_config.fb_base = ggtt->mappable_base;
79e53945 14988
28c97730 14989 DRM_DEBUG_KMS("%d display pipe%s available.\n",
b7f05d4a
TU
14990 INTEL_INFO(dev_priv)->num_pipes,
14991 INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : "");
79e53945 14992
055e393f 14993 for_each_pipe(dev_priv, pipe) {
b079bd17
VS
14994 int ret;
14995
5ab0d85b 14996 ret = intel_crtc_init(dev_priv, pipe);
b079bd17
VS
14997 if (ret) {
14998 drm_mode_config_cleanup(dev);
14999 return ret;
15000 }
79e53945
JB
15001 }
15002
e72f9fbf 15003 intel_shared_dpll_init(dev);
ee7b9f93 15004
5be6e334
VS
15005 intel_update_czclk(dev_priv);
15006 intel_modeset_init_hw(dev);
15007
b2045352 15008 if (dev_priv->max_cdclk_freq == 0)
4c75b940 15009 intel_update_max_cdclk(dev_priv);
b2045352 15010
9cce37f4 15011 /* Just disable it once at startup */
29b74b7f 15012 i915_disable_vga(dev_priv);
c39055b0 15013 intel_setup_outputs(dev_priv);
11be49eb 15014
6e9f798d 15015 drm_modeset_lock_all(dev);
043e9bda 15016 intel_modeset_setup_hw_state(dev);
6e9f798d 15017 drm_modeset_unlock_all(dev);
46f297fb 15018
d3fcc808 15019 for_each_intel_crtc(dev, crtc) {
eeebeac5
ML
15020 struct intel_initial_plane_config plane_config = {};
15021
46f297fb
JB
15022 if (!crtc->active)
15023 continue;
15024
46f297fb 15025 /*
46f297fb
JB
15026 * Note that reserving the BIOS fb up front prevents us
15027 * from stuffing other stolen allocations like the ring
15028 * on top. This prevents some ugliness at boot time, and
15029 * can even allow for smooth boot transitions if the BIOS
15030 * fb is large enough for the active pipe configuration.
15031 */
eeebeac5
ML
15032 dev_priv->display.get_initial_plane_config(crtc,
15033 &plane_config);
15034
15035 /*
15036 * If the fb is shared between multiple heads, we'll
15037 * just get the first one.
15038 */
15039 intel_find_initial_plane_obj(crtc, &plane_config);
46f297fb 15040 }
d93c0372
MR
15041
15042 /*
15043 * Make sure hardware watermarks really match the state we read out.
15044 * Note that we need to do this after reconstructing the BIOS fb's
15045 * since the watermark calculation done here will use pstate->fb.
15046 */
602ae835
VS
15047 if (!HAS_GMCH_DISPLAY(dev_priv))
15048 sanitize_watermarks(dev);
b079bd17
VS
15049
15050 return 0;
2c7111db
CW
15051}
15052
7fad798e
DV
15053static void intel_enable_pipe_a(struct drm_device *dev)
15054{
15055 struct intel_connector *connector;
f9e905ca 15056 struct drm_connector_list_iter conn_iter;
7fad798e
DV
15057 struct drm_connector *crt = NULL;
15058 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 15059 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
6c5ed5ae 15060 int ret;
7fad798e
DV
15061
15062 /* We can't just switch on the pipe A, we need to set things up with a
15063 * proper mode and output configuration. As a gross hack, enable pipe A
15064 * by enabling the load detect pipe once. */
f9e905ca
DV
15065 drm_connector_list_iter_begin(dev, &conn_iter);
15066 for_each_intel_connector_iter(connector, &conn_iter) {
7fad798e
DV
15067 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15068 crt = &connector->base;
15069 break;
15070 }
15071 }
f9e905ca 15072 drm_connector_list_iter_end(&conn_iter);
7fad798e
DV
15073
15074 if (!crt)
15075 return;
15076
6c5ed5ae
ML
15077 ret = intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx);
15078 WARN(ret < 0, "All modeset mutexes are locked, but intel_get_load_detect_pipe failed\n");
15079
15080 if (ret > 0)
49172fee 15081 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV
15082}
15083
fa555837
DV
15084static bool
15085intel_check_plane_mapping(struct intel_crtc *crtc)
15086{
b7f05d4a 15087 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
649636ef 15088 u32 val;
fa555837 15089
b7f05d4a 15090 if (INTEL_INFO(dev_priv)->num_pipes == 1)
fa555837
DV
15091 return true;
15092
649636ef 15093 val = I915_READ(DSPCNTR(!crtc->plane));
fa555837
DV
15094
15095 if ((val & DISPLAY_PLANE_ENABLE) &&
15096 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15097 return false;
15098
15099 return true;
15100}
15101
02e93c35
VS
15102static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15103{
15104 struct drm_device *dev = crtc->base.dev;
15105 struct intel_encoder *encoder;
15106
15107 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15108 return true;
15109
15110 return false;
15111}
15112
496b0fc3
ML
15113static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
15114{
15115 struct drm_device *dev = encoder->base.dev;
15116 struct intel_connector *connector;
15117
15118 for_each_connector_on_encoder(dev, &encoder->base, connector)
15119 return connector;
15120
15121 return NULL;
15122}
15123
a168f5b3
VS
15124static bool has_pch_trancoder(struct drm_i915_private *dev_priv,
15125 enum transcoder pch_transcoder)
15126{
15127 return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) ||
15128 (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A);
15129}
15130
24929352
DV
15131static void intel_sanitize_crtc(struct intel_crtc *crtc)
15132{
15133 struct drm_device *dev = crtc->base.dev;
fac5e23e 15134 struct drm_i915_private *dev_priv = to_i915(dev);
4d1de975 15135 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
24929352 15136
24929352 15137 /* Clear any frame start delays used for debugging left by the BIOS */
4d1de975
JN
15138 if (!transcoder_is_dsi(cpu_transcoder)) {
15139 i915_reg_t reg = PIPECONF(cpu_transcoder);
15140
15141 I915_WRITE(reg,
15142 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15143 }
24929352 15144
d3eaf884 15145 /* restore vblank interrupts to correct state */
9625604c 15146 drm_crtc_vblank_reset(&crtc->base);
d297e103 15147 if (crtc->active) {
f9cd7b88
VS
15148 struct intel_plane *plane;
15149
9625604c 15150 drm_crtc_vblank_on(&crtc->base);
f9cd7b88
VS
15151
15152 /* Disable everything but the primary plane */
15153 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15154 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15155 continue;
15156
72259536 15157 trace_intel_disable_plane(&plane->base, crtc);
f9cd7b88
VS
15158 plane->disable_plane(&plane->base, &crtc->base);
15159 }
9625604c 15160 }
d3eaf884 15161
24929352 15162 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV
15163 * disable the crtc (and hence change the state) if it is wrong. Note
15164 * that gen4+ has a fixed plane -> pipe mapping. */
6315b5d3 15165 if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV
15166 bool plane;
15167
78108b7c
VS
15168 DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n",
15169 crtc->base.base.id, crtc->base.name);
24929352
DV
15170
15171 /* Pipe has the wrong plane attached and the plane is active.
15172 * Temporarily change the plane mapping and disable everything
15173 * ... */
15174 plane = crtc->plane;
1d4258db 15175 crtc->base.primary->state->visible = true;
24929352 15176 crtc->plane = !plane;
b17d48e2 15177 intel_crtc_disable_noatomic(&crtc->base);
24929352 15178 crtc->plane = plane;
24929352 15179 }
24929352 15180
7fad798e
DV
15181 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15182 crtc->pipe == PIPE_A && !crtc->active) {
15183 /* BIOS forgot to enable pipe A, this mostly happens after
15184 * resume. Force-enable the pipe to fix this, the update_dpms
15185 * call below we restore the pipe to the right state, but leave
15186 * the required bits on. */
15187 intel_enable_pipe_a(dev);
15188 }
15189
24929352
DV
15190 /* Adjust the state of the output pipe according to whether we
15191 * have active connectors/encoders. */
842e0307 15192 if (crtc->active && !intel_crtc_has_encoders(crtc))
b17d48e2 15193 intel_crtc_disable_noatomic(&crtc->base);
24929352 15194
49cff963 15195 if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) {
4cc31489
DV
15196 /*
15197 * We start out with underrun reporting disabled to avoid races.
15198 * For correct bookkeeping mark this on active crtcs.
15199 *
c5ab3bc0
DV
15200 * Also on gmch platforms we dont have any hardware bits to
15201 * disable the underrun reporting. Which means we need to start
15202 * out with underrun reporting disabled also on inactive pipes,
15203 * since otherwise we'll complain about the garbage we read when
15204 * e.g. coming up after runtime pm.
15205 *
4cc31489
DV
15206 * No protection against concurrent access is required - at
15207 * worst a fifo underrun happens which also sets this to false.
15208 */
15209 crtc->cpu_fifo_underrun_disabled = true;
a168f5b3
VS
15210 /*
15211 * We track the PCH trancoder underrun reporting state
15212 * within the crtc. With crtc for pipe A housing the underrun
15213 * reporting state for PCH transcoder A, crtc for pipe B housing
15214 * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A,
15215 * and marking underrun reporting as disabled for the non-existing
15216 * PCH transcoders B and C would prevent enabling the south
15217 * error interrupt (see cpt_can_enable_serr_int()).
15218 */
15219 if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe))
15220 crtc->pch_fifo_underrun_disabled = true;
4cc31489 15221 }
24929352
DV
15222}
15223
15224static void intel_sanitize_encoder(struct intel_encoder *encoder)
15225{
15226 struct intel_connector *connector;
24929352
DV
15227
15228 /* We need to check both for a crtc link (meaning that the
15229 * encoder is active and trying to read from a pipe) and the
15230 * pipe itself being active. */
15231 bool has_active_crtc = encoder->base.crtc &&
15232 to_intel_crtc(encoder->base.crtc)->active;
15233
496b0fc3
ML
15234 connector = intel_encoder_find_connector(encoder);
15235 if (connector && !has_active_crtc) {
24929352
DV
15236 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15237 encoder->base.base.id,
8e329a03 15238 encoder->base.name);
24929352
DV
15239
15240 /* Connector is active, but has no active pipe. This is
15241 * fallout from our resume register restoring. Disable
15242 * the encoder manually again. */
15243 if (encoder->base.crtc) {
fd6bbda9
ML
15244 struct drm_crtc_state *crtc_state = encoder->base.crtc->state;
15245
24929352
DV
15246 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15247 encoder->base.base.id,
8e329a03 15248 encoder->base.name);
fd6bbda9 15249 encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
a62d1497 15250 if (encoder->post_disable)
fd6bbda9 15251 encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state);
24929352 15252 }
7f1950fb 15253 encoder->base.crtc = NULL;
24929352
DV
15254
15255 /* Inconsistent output/port/pipe state happens presumably due to
15256 * a bug in one of the get_hw_state functions. Or someplace else
15257 * in our code, like the register restore mess on resume. Clamp
15258 * things to off as a safer default. */
fd6bbda9
ML
15259
15260 connector->base.dpms = DRM_MODE_DPMS_OFF;
15261 connector->base.encoder = NULL;
24929352
DV
15262 }
15263 /* Enabled encoders without active connectors will be fixed in
15264 * the crtc fixup. */
15265}
15266
29b74b7f 15267void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv)
0fde901f 15268{
920a14b2 15269 i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv);
0fde901f 15270
04098753
ID
15271 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15272 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
29b74b7f 15273 i915_disable_vga(dev_priv);
04098753
ID
15274 }
15275}
15276
29b74b7f 15277void i915_redisable_vga(struct drm_i915_private *dev_priv)
04098753 15278{
8dc8a27c
PZ
15279 /* This function can be called both from intel_modeset_setup_hw_state or
15280 * at a very early point in our resume sequence, where the power well
15281 * structures are not yet restored. Since this function is at a very
15282 * paranoid "someone might have enabled VGA while we were not looking"
15283 * level, just check if the power well is enabled instead of trying to
15284 * follow the "don't touch the power well if we don't need it" policy
15285 * the rest of the driver uses. */
6392f847 15286 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ
15287 return;
15288
29b74b7f 15289 i915_redisable_vga_power_on(dev_priv);
6392f847
ID
15290
15291 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
0fde901f
KM
15292}
15293
f9cd7b88 15294static bool primary_get_hw_state(struct intel_plane *plane)
98ec7739 15295{
f9cd7b88 15296 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
98ec7739 15297
f9cd7b88 15298 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
d032ffa0
ML
15299}
15300
f9cd7b88
VS
15301/* FIXME read out full plane state for all planes */
15302static void readout_plane_state(struct intel_crtc *crtc)
d032ffa0 15303{
e9728bd8
VS
15304 struct intel_plane *primary = to_intel_plane(crtc->base.primary);
15305 bool visible;
d032ffa0 15306
e9728bd8 15307 visible = crtc->active && primary_get_hw_state(primary);
b26d3ea3 15308
e9728bd8
VS
15309 intel_set_plane_visible(to_intel_crtc_state(crtc->base.state),
15310 to_intel_plane_state(primary->base.state),
15311 visible);
98ec7739
VS
15312}
15313
30e984df 15314static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352 15315{
fac5e23e 15316 struct drm_i915_private *dev_priv = to_i915(dev);
24929352 15317 enum pipe pipe;
24929352
DV
15318 struct intel_crtc *crtc;
15319 struct intel_encoder *encoder;
15320 struct intel_connector *connector;
f9e905ca 15321 struct drm_connector_list_iter conn_iter;
5358901f 15322 int i;
24929352 15323
565602d7
ML
15324 dev_priv->active_crtcs = 0;
15325
d3fcc808 15326 for_each_intel_crtc(dev, crtc) {
a8cd6da0
VS
15327 struct intel_crtc_state *crtc_state =
15328 to_intel_crtc_state(crtc->base.state);
3b117c8f 15329
ec2dc6a0 15330 __drm_atomic_helper_crtc_destroy_state(&crtc_state->base);
565602d7
ML
15331 memset(crtc_state, 0, sizeof(*crtc_state));
15332 crtc_state->base.crtc = &crtc->base;
24929352 15333
565602d7
ML
15334 crtc_state->base.active = crtc_state->base.enable =
15335 dev_priv->display.get_pipe_config(crtc, crtc_state);
15336
15337 crtc->base.enabled = crtc_state->base.enable;
15338 crtc->active = crtc_state->base.active;
15339
aca1ebf4 15340 if (crtc_state->base.active)
565602d7
ML
15341 dev_priv->active_crtcs |= 1 << crtc->pipe;
15342
f9cd7b88 15343 readout_plane_state(crtc);
24929352 15344
78108b7c
VS
15345 DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n",
15346 crtc->base.base.id, crtc->base.name,
a8cd6da0 15347 enableddisabled(crtc_state->base.active));
24929352
DV
15348 }
15349
5358901f
DV
15350 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15351 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15352
2edd6443 15353 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
2c42e535
ACO
15354 &pll->state.hw_state);
15355 pll->state.crtc_mask = 0;
d3fcc808 15356 for_each_intel_crtc(dev, crtc) {
a8cd6da0
VS
15357 struct intel_crtc_state *crtc_state =
15358 to_intel_crtc_state(crtc->base.state);
15359
15360 if (crtc_state->base.active &&
15361 crtc_state->shared_dpll == pll)
2c42e535 15362 pll->state.crtc_mask |= 1 << crtc->pipe;
5358901f 15363 }
2c42e535 15364 pll->active_mask = pll->state.crtc_mask;
5358901f 15365
1e6f2ddc 15366 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
2c42e535 15367 pll->name, pll->state.crtc_mask, pll->on);
5358901f
DV
15368 }
15369
b2784e15 15370 for_each_intel_encoder(dev, encoder) {
24929352
DV
15371 pipe = 0;
15372
15373 if (encoder->get_hw_state(encoder, &pipe)) {
a8cd6da0
VS
15374 struct intel_crtc_state *crtc_state;
15375
98187836 15376 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
a8cd6da0 15377 crtc_state = to_intel_crtc_state(crtc->base.state);
e2af48c6 15378
045ac3b5 15379 encoder->base.crtc = &crtc->base;
a8cd6da0
VS
15380 crtc_state->output_types |= 1 << encoder->type;
15381 encoder->get_config(encoder, crtc_state);
24929352
DV
15382 } else {
15383 encoder->base.crtc = NULL;
15384 }
15385
6f2bcceb 15386 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
08c4d7fc
TU
15387 encoder->base.base.id, encoder->base.name,
15388 enableddisabled(encoder->base.crtc),
6f2bcceb 15389 pipe_name(pipe));
24929352
DV
15390 }
15391
f9e905ca
DV
15392 drm_connector_list_iter_begin(dev, &conn_iter);
15393 for_each_intel_connector_iter(connector, &conn_iter) {
24929352
DV
15394 if (connector->get_hw_state(connector)) {
15395 connector->base.dpms = DRM_MODE_DPMS_ON;
2aa974c9
ML
15396
15397 encoder = connector->encoder;
15398 connector->base.encoder = &encoder->base;
15399
15400 if (encoder->base.crtc &&
15401 encoder->base.crtc->state->active) {
15402 /*
15403 * This has to be done during hardware readout
15404 * because anything calling .crtc_disable may
15405 * rely on the connector_mask being accurate.
15406 */
15407 encoder->base.crtc->state->connector_mask |=
15408 1 << drm_connector_index(&connector->base);
e87a52b3
ML
15409 encoder->base.crtc->state->encoder_mask |=
15410 1 << drm_encoder_index(&encoder->base);
2aa974c9
ML
15411 }
15412
24929352
DV
15413 } else {
15414 connector->base.dpms = DRM_MODE_DPMS_OFF;
15415 connector->base.encoder = NULL;
15416 }
15417 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
08c4d7fc
TU
15418 connector->base.base.id, connector->base.name,
15419 enableddisabled(connector->base.encoder));
24929352 15420 }
f9e905ca 15421 drm_connector_list_iter_end(&conn_iter);
7f4c6284
VS
15422
15423 for_each_intel_crtc(dev, crtc) {
a8cd6da0
VS
15424 struct intel_crtc_state *crtc_state =
15425 to_intel_crtc_state(crtc->base.state);
aca1ebf4
VS
15426 int pixclk = 0;
15427
a8cd6da0 15428 crtc->base.hwmode = crtc_state->base.adjusted_mode;
7f4c6284
VS
15429
15430 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
a8cd6da0
VS
15431 if (crtc_state->base.active) {
15432 intel_mode_from_pipe_config(&crtc->base.mode, crtc_state);
15433 intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state);
7f4c6284
VS
15434 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15435
15436 /*
15437 * The initial mode needs to be set in order to keep
15438 * the atomic core happy. It wants a valid mode if the
15439 * crtc's enabled, so we do the above call.
15440 *
7800fb69
DV
15441 * But we don't set all the derived state fully, hence
15442 * set a flag to indicate that a full recalculation is
15443 * needed on the next commit.
7f4c6284 15444 */
a8cd6da0 15445 crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED;
9eca6832 15446
a7d1b3f4
VS
15447 intel_crtc_compute_pixel_rate(crtc_state);
15448
15449 if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) ||
15450 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
15451 pixclk = crtc_state->pixel_rate;
aca1ebf4
VS
15452 else
15453 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15454
15455 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
a8cd6da0 15456 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
aca1ebf4
VS
15457 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15458
9eca6832
VS
15459 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15460 update_scanline_offset(crtc);
7f4c6284 15461 }
e3b247da 15462
aca1ebf4
VS
15463 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15464
a8cd6da0 15465 intel_pipe_config_sanity_check(dev_priv, crtc_state);
7f4c6284 15466 }
30e984df
DV
15467}
15468
62b69566
ACO
15469static void
15470get_encoder_power_domains(struct drm_i915_private *dev_priv)
15471{
15472 struct intel_encoder *encoder;
15473
15474 for_each_intel_encoder(&dev_priv->drm, encoder) {
15475 u64 get_domains;
15476 enum intel_display_power_domain domain;
15477
15478 if (!encoder->get_power_domains)
15479 continue;
15480
15481 get_domains = encoder->get_power_domains(encoder);
15482 for_each_power_domain(domain, get_domains)
15483 intel_display_power_get(dev_priv, domain);
15484 }
15485}
15486
043e9bda
ML
15487/* Scan out the current hw modeset state,
15488 * and sanitizes it to the current state
15489 */
15490static void
15491intel_modeset_setup_hw_state(struct drm_device *dev)
30e984df 15492{
fac5e23e 15493 struct drm_i915_private *dev_priv = to_i915(dev);
30e984df 15494 enum pipe pipe;
30e984df
DV
15495 struct intel_crtc *crtc;
15496 struct intel_encoder *encoder;
35c95375 15497 int i;
30e984df
DV
15498
15499 intel_modeset_readout_hw_state(dev);
24929352
DV
15500
15501 /* HW state is read out, now we need to sanitize this mess. */
62b69566
ACO
15502 get_encoder_power_domains(dev_priv);
15503
b2784e15 15504 for_each_intel_encoder(dev, encoder) {
24929352
DV
15505 intel_sanitize_encoder(encoder);
15506 }
15507
055e393f 15508 for_each_pipe(dev_priv, pipe) {
98187836 15509 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
e2af48c6 15510
24929352 15511 intel_sanitize_crtc(crtc);
6e3c9717
ACO
15512 intel_dump_pipe_config(crtc, crtc->config,
15513 "[setup_hw_state]");
24929352 15514 }
9a935856 15515
d29b2f9d
ACO
15516 intel_modeset_update_connector_atomic_state(dev);
15517
35c95375
DV
15518 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15519 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15520
2dd66ebd 15521 if (!pll->on || pll->active_mask)
35c95375
DV
15522 continue;
15523
15524 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15525
2edd6443 15526 pll->funcs.disable(dev_priv, pll);
35c95375
DV
15527 pll->on = false;
15528 }
15529
602ae835 15530 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
6eb1a681 15531 vlv_wm_get_hw_state(dev);
602ae835
VS
15532 vlv_wm_sanitize(dev_priv);
15533 } else if (IS_GEN9(dev_priv)) {
3078999f 15534 skl_wm_get_hw_state(dev);
602ae835 15535 } else if (HAS_PCH_SPLIT(dev_priv)) {
243e6a44 15536 ilk_wm_get_hw_state(dev);
602ae835 15537 }
292b990e
ML
15538
15539 for_each_intel_crtc(dev, crtc) {
d8fc70b7 15540 u64 put_domains;
292b990e 15541
74bff5f9 15542 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
292b990e
ML
15543 if (WARN_ON(put_domains))
15544 modeset_put_power_domains(dev_priv, put_domains);
15545 }
15546 intel_display_set_init_power(dev_priv, false);
010cf73d 15547
8d8c386c
ID
15548 intel_power_domains_verify_state(dev_priv);
15549
010cf73d 15550 intel_fbc_init_pipe_state(dev_priv);
043e9bda 15551}
7d0bc1ea 15552
043e9bda
ML
15553void intel_display_resume(struct drm_device *dev)
15554{
e2c8b870
ML
15555 struct drm_i915_private *dev_priv = to_i915(dev);
15556 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15557 struct drm_modeset_acquire_ctx ctx;
043e9bda 15558 int ret;
f30da187 15559
e2c8b870 15560 dev_priv->modeset_restore_state = NULL;
73974893
ML
15561 if (state)
15562 state->acquire_ctx = &ctx;
043e9bda 15563
e2c8b870 15564 drm_modeset_acquire_init(&ctx, 0);
043e9bda 15565
73974893
ML
15566 while (1) {
15567 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15568 if (ret != -EDEADLK)
15569 break;
043e9bda 15570
e2c8b870 15571 drm_modeset_backoff(&ctx);
e2c8b870 15572 }
043e9bda 15573
73974893 15574 if (!ret)
581e49fe 15575 ret = __intel_display_resume(dev, state, &ctx);
73974893 15576
e2c8b870
ML
15577 drm_modeset_drop_locks(&ctx);
15578 drm_modeset_acquire_fini(&ctx);
043e9bda 15579
0853695c 15580 if (ret)
e2c8b870 15581 DRM_ERROR("Restoring old state failed with %i\n", ret);
3c5e37f1
CW
15582 if (state)
15583 drm_atomic_state_put(state);
2c7111db
CW
15584}
15585
15586void intel_modeset_gem_init(struct drm_device *dev)
15587{
dc97997a 15588 struct drm_i915_private *dev_priv = to_i915(dev);
484b41dd 15589
dc97997a 15590 intel_init_gt_powersave(dev_priv);
ae48434c 15591
1ee8da6d 15592 intel_setup_overlay(dev_priv);
1ebaa0b9
CW
15593}
15594
15595int intel_connector_register(struct drm_connector *connector)
15596{
15597 struct intel_connector *intel_connector = to_intel_connector(connector);
15598 int ret;
15599
15600 ret = intel_backlight_device_register(intel_connector);
15601 if (ret)
15602 goto err;
15603
15604 return 0;
0962c3c9 15605
1ebaa0b9
CW
15606err:
15607 return ret;
79e53945
JB
15608}
15609
c191eca1 15610void intel_connector_unregister(struct drm_connector *connector)
4932e2c3 15611{
e63d87c0 15612 struct intel_connector *intel_connector = to_intel_connector(connector);
4932e2c3 15613
e63d87c0 15614 intel_backlight_device_unregister(intel_connector);
4932e2c3 15615 intel_panel_destroy_backlight(connector);
4932e2c3
ID
15616}
15617
79e53945
JB
15618void intel_modeset_cleanup(struct drm_device *dev)
15619{
fac5e23e 15620 struct drm_i915_private *dev_priv = to_i915(dev);
652c393a 15621
eb955eee
CW
15622 flush_work(&dev_priv->atomic_helper.free_work);
15623 WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list));
15624
dc97997a 15625 intel_disable_gt_powersave(dev_priv);
2eb5252e 15626
fd0c0642
DV
15627 /*
15628 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15629 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV
15630 * experience fancy races otherwise.
15631 */
2aeb7d3a 15632 intel_irq_uninstall(dev_priv);
eb21b92b 15633
fd0c0642
DV
15634 /*
15635 * Due to the hpd irq storm handling the hotplug work can re-arm the
15636 * poll handlers. Hence disable polling after hpd handling is shut down.
15637 */
f87ea761 15638 drm_kms_helper_poll_fini(dev);
fd0c0642 15639
723bfd70
JB
15640 intel_unregister_dsm_handler();
15641
c937ab3e 15642 intel_fbc_global_disable(dev_priv);
69341a5e 15643
1630fe75
CW
15644 /* flush any delayed tasks or pending work */
15645 flush_scheduled_work();
15646
79e53945 15647 drm_mode_config_cleanup(dev);
4d7bb011 15648
1ee8da6d 15649 intel_cleanup_overlay(dev_priv);
ae48434c 15650
dc97997a 15651 intel_cleanup_gt_powersave(dev_priv);
f5949141 15652
40196446 15653 intel_teardown_gmbus(dev_priv);
79e53945
JB
15654}
15655
df0e9248
CW
15656void intel_connector_attach_encoder(struct intel_connector *connector,
15657 struct intel_encoder *encoder)
15658{
15659 connector->encoder = encoder;
15660 drm_mode_connector_attach_encoder(&connector->base,
15661 &encoder->base);
79e53945 15662}
28d52043
DA
15663
15664/*
15665 * set vga decode state - true == enable VGA decode
15666 */
6315b5d3 15667int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state)
28d52043 15668{
6315b5d3 15669 unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA
15670 u16 gmch_ctrl;
15671
75fa041d
CW
15672 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15673 DRM_ERROR("failed to read control word\n");
15674 return -EIO;
15675 }
15676
c0cc8a55
CW
15677 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15678 return 0;
15679
28d52043
DA
15680 if (state)
15681 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15682 else
15683 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW
15684
15685 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15686 DRM_ERROR("failed to write control word\n");
15687 return -EIO;
15688 }
15689
28d52043
DA
15690 return 0;
15691}
c4a1d9e4 15692
98a2f411
CW
15693#if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
15694
c4a1d9e4 15695struct intel_display_error_state {
ff57f1b0
PZ
15696
15697 u32 power_well_driver;
15698
63b66e5b
CW
15699 int num_transcoders;
15700
c4a1d9e4
CW
15701 struct intel_cursor_error_state {
15702 u32 control;
15703 u32 position;
15704 u32 base;
15705 u32 size;
52331309 15706 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW
15707
15708 struct intel_pipe_error_state {
ddf9c536 15709 bool power_domain_on;
c4a1d9e4 15710 u32 source;
f301b1e1 15711 u32 stat;
52331309 15712 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW
15713
15714 struct intel_plane_error_state {
15715 u32 control;
15716 u32 stride;
15717 u32 size;
15718 u32 pos;
15719 u32 addr;
15720 u32 surface;
15721 u32 tile_offset;
52331309 15722 } plane[I915_MAX_PIPES];
63b66e5b
CW
15723
15724 struct intel_transcoder_error_state {
ddf9c536 15725 bool power_domain_on;
63b66e5b
CW
15726 enum transcoder cpu_transcoder;
15727
15728 u32 conf;
15729
15730 u32 htotal;
15731 u32 hblank;
15732 u32 hsync;
15733 u32 vtotal;
15734 u32 vblank;
15735 u32 vsync;
15736 } transcoder[4];
c4a1d9e4
CW
15737};
15738
15739struct intel_display_error_state *
c033666a 15740intel_display_capture_error_state(struct drm_i915_private *dev_priv)
c4a1d9e4 15741{
c4a1d9e4 15742 struct intel_display_error_state *error;
63b66e5b
CW
15743 int transcoders[] = {
15744 TRANSCODER_A,
15745 TRANSCODER_B,
15746 TRANSCODER_C,
15747 TRANSCODER_EDP,
15748 };
c4a1d9e4
CW
15749 int i;
15750
c033666a 15751 if (INTEL_INFO(dev_priv)->num_pipes == 0)
63b66e5b
CW
15752 return NULL;
15753
9d1cb914 15754 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW
15755 if (error == NULL)
15756 return NULL;
15757
c033666a 15758 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ff57f1b0
PZ
15759 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15760
055e393f 15761 for_each_pipe(dev_priv, i) {
ddf9c536 15762 error->pipe[i].power_domain_on =
f458ebbc
DV
15763 __intel_display_power_is_enabled(dev_priv,
15764 POWER_DOMAIN_PIPE(i));
ddf9c536 15765 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ
15766 continue;
15767
5efb3e28
VS
15768 error->cursor[i].control = I915_READ(CURCNTR(i));
15769 error->cursor[i].position = I915_READ(CURPOS(i));
15770 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW
15771
15772 error->plane[i].control = I915_READ(DSPCNTR(i));
15773 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
c033666a 15774 if (INTEL_GEN(dev_priv) <= 3) {
51889b35 15775 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ
15776 error->plane[i].pos = I915_READ(DSPPOS(i));
15777 }
c033666a 15778 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
ca291363 15779 error->plane[i].addr = I915_READ(DSPADDR(i));
c033666a 15780 if (INTEL_GEN(dev_priv) >= 4) {
c4a1d9e4
CW
15781 error->plane[i].surface = I915_READ(DSPSURF(i));
15782 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15783 }
15784
c4a1d9e4 15785 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15786
c033666a 15787 if (HAS_GMCH_DISPLAY(dev_priv))
f301b1e1 15788 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW
15789 }
15790
4d1de975 15791 /* Note: this does not include DSI transcoders. */
c033666a 15792 error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes;
2d1fe073 15793 if (HAS_DDI(dev_priv))
63b66e5b
CW
15794 error->num_transcoders++; /* Account for eDP. */
15795
15796 for (i = 0; i < error->num_transcoders; i++) {
15797 enum transcoder cpu_transcoder = transcoders[i];
15798
ddf9c536 15799 error->transcoder[i].power_domain_on =
f458ebbc 15800 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15801 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15802 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ
15803 continue;
15804
63b66e5b
CW
15805 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15806
15807 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15808 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15809 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15810 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15811 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15812 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15813 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW
15814 }
15815
15816 return error;
15817}
15818
edc3d884
MK
15819#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15820
c4a1d9e4 15821void
edc3d884 15822intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW
15823 struct intel_display_error_state *error)
15824{
5a4c6f1b 15825 struct drm_i915_private *dev_priv = m->i915;
c4a1d9e4
CW
15826 int i;
15827
63b66e5b
CW
15828 if (!error)
15829 return;
15830
b7f05d4a 15831 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes);
8652744b 15832 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
edc3d884 15833 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15834 error->power_well_driver);
055e393f 15835 for_each_pipe(dev_priv, i) {
edc3d884 15836 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536 15837 err_printf(m, " Power: %s\n",
87ad3212 15838 onoff(error->pipe[i].power_domain_on));
edc3d884 15839 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15840 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK
15841
15842 err_printf(m, "Plane [%d]:\n", i);
15843 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15844 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
5f56d5f9 15845 if (INTEL_GEN(dev_priv) <= 3) {
edc3d884
MK
15846 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15847 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15848 }
772c2a51 15849 if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv))
edc3d884 15850 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
5f56d5f9 15851 if (INTEL_GEN(dev_priv) >= 4) {
edc3d884
MK
15852 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15853 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW
15854 }
15855
edc3d884
MK
15856 err_printf(m, "Cursor [%d]:\n", i);
15857 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15858 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15859 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15860 }
63b66e5b
CW
15861
15862 for (i = 0; i < error->num_transcoders; i++) {
da205630 15863 err_printf(m, "CPU transcoder: %s\n",
63b66e5b 15864 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536 15865 err_printf(m, " Power: %s\n",
87ad3212 15866 onoff(error->transcoder[i].power_domain_on));
63b66e5b
CW
15867 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15868 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15869 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15870 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15871 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15872 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15873 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15874 }
c4a1d9e4 15875}
98a2f411
CW
15876
15877#endif