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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
319c1d42 | 40 | #include <drm/drm_atomic.h> |
c196e1d6 | 41 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
42 | #include <drm/drm_dp_helper.h> |
43 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
44 | #include <drm/drm_plane_helper.h> |
45 | #include <drm/drm_rect.h> | |
c0f372b3 | 46 | #include <linux/dma_remapping.h> |
fd8e058a AG |
47 | #include <linux/reservation.h> |
48 | #include <linux/dma-buf.h> | |
79e53945 | 49 | |
465c120c | 50 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 51 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
52 | DRM_FORMAT_C8, |
53 | DRM_FORMAT_RGB565, | |
465c120c | 54 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 55 | DRM_FORMAT_XRGB8888, |
465c120c MR |
56 | }; |
57 | ||
58 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 59 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
60 | DRM_FORMAT_C8, |
61 | DRM_FORMAT_RGB565, | |
62 | DRM_FORMAT_XRGB8888, | |
63 | DRM_FORMAT_XBGR8888, | |
64 | DRM_FORMAT_XRGB2101010, | |
65 | DRM_FORMAT_XBGR2101010, | |
66 | }; | |
67 | ||
68 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
69 | DRM_FORMAT_C8, |
70 | DRM_FORMAT_RGB565, | |
71 | DRM_FORMAT_XRGB8888, | |
465c120c | 72 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 73 | DRM_FORMAT_ARGB8888, |
465c120c MR |
74 | DRM_FORMAT_ABGR8888, |
75 | DRM_FORMAT_XRGB2101010, | |
465c120c | 76 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
77 | DRM_FORMAT_YUYV, |
78 | DRM_FORMAT_YVYU, | |
79 | DRM_FORMAT_UYVY, | |
80 | DRM_FORMAT_VYUY, | |
465c120c MR |
81 | }; |
82 | ||
3d7d6510 MR |
83 | /* Cursor formats */ |
84 | static const uint32_t intel_cursor_formats[] = { | |
85 | DRM_FORMAT_ARGB8888, | |
86 | }; | |
87 | ||
6b383a7f | 88 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 89 | |
f1f644dc | 90 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 91 | struct intel_crtc_state *pipe_config); |
18442d08 | 92 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 93 | struct intel_crtc_state *pipe_config); |
f1f644dc | 94 | |
eb1bfe80 JB |
95 | static int intel_framebuffer_init(struct drm_device *dev, |
96 | struct intel_framebuffer *ifb, | |
97 | struct drm_mode_fb_cmd2 *mode_cmd, | |
98 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
99 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
100 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 101 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
102 | struct intel_link_m_n *m_n, |
103 | struct intel_link_m_n *m2_n2); | |
29407aab | 104 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
105 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
106 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f | 107 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 108 | const struct intel_crtc_state *pipe_config); |
d288f65f | 109 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 110 | const struct intel_crtc_state *pipe_config); |
613d2b27 ML |
111 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
112 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
549e2bfb CK |
113 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
114 | struct intel_crtc_state *crtc_state); | |
5ab7b0b7 ID |
115 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
116 | int num_connectors); | |
bfd16b2a ML |
117 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
118 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
119 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 120 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
e7457a9a | 121 | |
79e53945 | 122 | typedef struct { |
0206e353 | 123 | int min, max; |
79e53945 JB |
124 | } intel_range_t; |
125 | ||
126 | typedef struct { | |
0206e353 AJ |
127 | int dot_limit; |
128 | int p2_slow, p2_fast; | |
79e53945 JB |
129 | } intel_p2_t; |
130 | ||
d4906093 ML |
131 | typedef struct intel_limit intel_limit_t; |
132 | struct intel_limit { | |
0206e353 AJ |
133 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
134 | intel_p2_t p2; | |
d4906093 | 135 | }; |
79e53945 | 136 | |
bfa7df01 VS |
137 | /* returns HPLL frequency in kHz */ |
138 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) | |
139 | { | |
140 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
141 | ||
142 | /* Obtain SKU information */ | |
143 | mutex_lock(&dev_priv->sb_lock); | |
144 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
145 | CCK_FUSE_HPLL_FREQ_MASK; | |
146 | mutex_unlock(&dev_priv->sb_lock); | |
147 | ||
148 | return vco_freq[hpll_freq] * 1000; | |
149 | } | |
150 | ||
151 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
152 | const char *name, u32 reg) | |
153 | { | |
154 | u32 val; | |
155 | int divider; | |
156 | ||
157 | if (dev_priv->hpll_freq == 0) | |
158 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
159 | ||
160 | mutex_lock(&dev_priv->sb_lock); | |
161 | val = vlv_cck_read(dev_priv, reg); | |
162 | mutex_unlock(&dev_priv->sb_lock); | |
163 | ||
164 | divider = val & CCK_FREQUENCY_VALUES; | |
165 | ||
166 | WARN((val & CCK_FREQUENCY_STATUS) != | |
167 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
168 | "%s change in progress\n", name); | |
169 | ||
170 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); | |
171 | } | |
172 | ||
d2acd215 DV |
173 | int |
174 | intel_pch_rawclk(struct drm_device *dev) | |
175 | { | |
176 | struct drm_i915_private *dev_priv = dev->dev_private; | |
177 | ||
178 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
179 | ||
180 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
181 | } | |
182 | ||
79e50a4f JN |
183 | /* hrawclock is 1/4 the FSB frequency */ |
184 | int intel_hrawclk(struct drm_device *dev) | |
185 | { | |
186 | struct drm_i915_private *dev_priv = dev->dev_private; | |
187 | uint32_t clkcfg; | |
188 | ||
189 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ | |
666a4537 | 190 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
79e50a4f JN |
191 | return 200; |
192 | ||
193 | clkcfg = I915_READ(CLKCFG); | |
194 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
195 | case CLKCFG_FSB_400: | |
196 | return 100; | |
197 | case CLKCFG_FSB_533: | |
198 | return 133; | |
199 | case CLKCFG_FSB_667: | |
200 | return 166; | |
201 | case CLKCFG_FSB_800: | |
202 | return 200; | |
203 | case CLKCFG_FSB_1067: | |
204 | return 266; | |
205 | case CLKCFG_FSB_1333: | |
206 | return 333; | |
207 | /* these two are just a guess; one of them might be right */ | |
208 | case CLKCFG_FSB_1600: | |
209 | case CLKCFG_FSB_1600_ALT: | |
210 | return 400; | |
211 | default: | |
212 | return 133; | |
213 | } | |
214 | } | |
215 | ||
bfa7df01 VS |
216 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
217 | { | |
666a4537 | 218 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
219 | return; |
220 | ||
221 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
222 | CCK_CZ_CLOCK_CONTROL); | |
223 | ||
224 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
225 | } | |
226 | ||
021357ac CW |
227 | static inline u32 /* units of 100MHz */ |
228 | intel_fdi_link_freq(struct drm_device *dev) | |
229 | { | |
8b99e68c CW |
230 | if (IS_GEN5(dev)) { |
231 | struct drm_i915_private *dev_priv = dev->dev_private; | |
232 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
233 | } else | |
234 | return 27; | |
021357ac CW |
235 | } |
236 | ||
5d536e28 | 237 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 238 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 239 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 240 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
241 | .m = { .min = 96, .max = 140 }, |
242 | .m1 = { .min = 18, .max = 26 }, | |
243 | .m2 = { .min = 6, .max = 16 }, | |
244 | .p = { .min = 4, .max = 128 }, | |
245 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
246 | .p2 = { .dot_limit = 165000, |
247 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
248 | }; |
249 | ||
5d536e28 DV |
250 | static const intel_limit_t intel_limits_i8xx_dvo = { |
251 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 252 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 253 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
254 | .m = { .min = 96, .max = 140 }, |
255 | .m1 = { .min = 18, .max = 26 }, | |
256 | .m2 = { .min = 6, .max = 16 }, | |
257 | .p = { .min = 4, .max = 128 }, | |
258 | .p1 = { .min = 2, .max = 33 }, | |
259 | .p2 = { .dot_limit = 165000, | |
260 | .p2_slow = 4, .p2_fast = 4 }, | |
261 | }; | |
262 | ||
e4b36699 | 263 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 264 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 265 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 266 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
267 | .m = { .min = 96, .max = 140 }, |
268 | .m1 = { .min = 18, .max = 26 }, | |
269 | .m2 = { .min = 6, .max = 16 }, | |
270 | .p = { .min = 4, .max = 128 }, | |
271 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
272 | .p2 = { .dot_limit = 165000, |
273 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 274 | }; |
273e27ca | 275 | |
e4b36699 | 276 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
277 | .dot = { .min = 20000, .max = 400000 }, |
278 | .vco = { .min = 1400000, .max = 2800000 }, | |
279 | .n = { .min = 1, .max = 6 }, | |
280 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
281 | .m1 = { .min = 8, .max = 18 }, |
282 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
283 | .p = { .min = 5, .max = 80 }, |
284 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
285 | .p2 = { .dot_limit = 200000, |
286 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
287 | }; |
288 | ||
289 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
290 | .dot = { .min = 20000, .max = 400000 }, |
291 | .vco = { .min = 1400000, .max = 2800000 }, | |
292 | .n = { .min = 1, .max = 6 }, | |
293 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
294 | .m1 = { .min = 8, .max = 18 }, |
295 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
296 | .p = { .min = 7, .max = 98 }, |
297 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
298 | .p2 = { .dot_limit = 112000, |
299 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
300 | }; |
301 | ||
273e27ca | 302 | |
e4b36699 | 303 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
304 | .dot = { .min = 25000, .max = 270000 }, |
305 | .vco = { .min = 1750000, .max = 3500000}, | |
306 | .n = { .min = 1, .max = 4 }, | |
307 | .m = { .min = 104, .max = 138 }, | |
308 | .m1 = { .min = 17, .max = 23 }, | |
309 | .m2 = { .min = 5, .max = 11 }, | |
310 | .p = { .min = 10, .max = 30 }, | |
311 | .p1 = { .min = 1, .max = 3}, | |
312 | .p2 = { .dot_limit = 270000, | |
313 | .p2_slow = 10, | |
314 | .p2_fast = 10 | |
044c7c41 | 315 | }, |
e4b36699 KP |
316 | }; |
317 | ||
318 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
319 | .dot = { .min = 22000, .max = 400000 }, |
320 | .vco = { .min = 1750000, .max = 3500000}, | |
321 | .n = { .min = 1, .max = 4 }, | |
322 | .m = { .min = 104, .max = 138 }, | |
323 | .m1 = { .min = 16, .max = 23 }, | |
324 | .m2 = { .min = 5, .max = 11 }, | |
325 | .p = { .min = 5, .max = 80 }, | |
326 | .p1 = { .min = 1, .max = 8}, | |
327 | .p2 = { .dot_limit = 165000, | |
328 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
329 | }; |
330 | ||
331 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
332 | .dot = { .min = 20000, .max = 115000 }, |
333 | .vco = { .min = 1750000, .max = 3500000 }, | |
334 | .n = { .min = 1, .max = 3 }, | |
335 | .m = { .min = 104, .max = 138 }, | |
336 | .m1 = { .min = 17, .max = 23 }, | |
337 | .m2 = { .min = 5, .max = 11 }, | |
338 | .p = { .min = 28, .max = 112 }, | |
339 | .p1 = { .min = 2, .max = 8 }, | |
340 | .p2 = { .dot_limit = 0, | |
341 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 342 | }, |
e4b36699 KP |
343 | }; |
344 | ||
345 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
346 | .dot = { .min = 80000, .max = 224000 }, |
347 | .vco = { .min = 1750000, .max = 3500000 }, | |
348 | .n = { .min = 1, .max = 3 }, | |
349 | .m = { .min = 104, .max = 138 }, | |
350 | .m1 = { .min = 17, .max = 23 }, | |
351 | .m2 = { .min = 5, .max = 11 }, | |
352 | .p = { .min = 14, .max = 42 }, | |
353 | .p1 = { .min = 2, .max = 6 }, | |
354 | .p2 = { .dot_limit = 0, | |
355 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 356 | }, |
e4b36699 KP |
357 | }; |
358 | ||
f2b115e6 | 359 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
360 | .dot = { .min = 20000, .max = 400000}, |
361 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 362 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
363 | .n = { .min = 3, .max = 6 }, |
364 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 365 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
366 | .m1 = { .min = 0, .max = 0 }, |
367 | .m2 = { .min = 0, .max = 254 }, | |
368 | .p = { .min = 5, .max = 80 }, | |
369 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
370 | .p2 = { .dot_limit = 200000, |
371 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
372 | }; |
373 | ||
f2b115e6 | 374 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
375 | .dot = { .min = 20000, .max = 400000 }, |
376 | .vco = { .min = 1700000, .max = 3500000 }, | |
377 | .n = { .min = 3, .max = 6 }, | |
378 | .m = { .min = 2, .max = 256 }, | |
379 | .m1 = { .min = 0, .max = 0 }, | |
380 | .m2 = { .min = 0, .max = 254 }, | |
381 | .p = { .min = 7, .max = 112 }, | |
382 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
383 | .p2 = { .dot_limit = 112000, |
384 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
385 | }; |
386 | ||
273e27ca EA |
387 | /* Ironlake / Sandybridge |
388 | * | |
389 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
390 | * the range value for them is (actual_value - 2). | |
391 | */ | |
b91ad0ec | 392 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
393 | .dot = { .min = 25000, .max = 350000 }, |
394 | .vco = { .min = 1760000, .max = 3510000 }, | |
395 | .n = { .min = 1, .max = 5 }, | |
396 | .m = { .min = 79, .max = 127 }, | |
397 | .m1 = { .min = 12, .max = 22 }, | |
398 | .m2 = { .min = 5, .max = 9 }, | |
399 | .p = { .min = 5, .max = 80 }, | |
400 | .p1 = { .min = 1, .max = 8 }, | |
401 | .p2 = { .dot_limit = 225000, | |
402 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
403 | }; |
404 | ||
b91ad0ec | 405 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
406 | .dot = { .min = 25000, .max = 350000 }, |
407 | .vco = { .min = 1760000, .max = 3510000 }, | |
408 | .n = { .min = 1, .max = 3 }, | |
409 | .m = { .min = 79, .max = 118 }, | |
410 | .m1 = { .min = 12, .max = 22 }, | |
411 | .m2 = { .min = 5, .max = 9 }, | |
412 | .p = { .min = 28, .max = 112 }, | |
413 | .p1 = { .min = 2, .max = 8 }, | |
414 | .p2 = { .dot_limit = 225000, | |
415 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
416 | }; |
417 | ||
418 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
419 | .dot = { .min = 25000, .max = 350000 }, |
420 | .vco = { .min = 1760000, .max = 3510000 }, | |
421 | .n = { .min = 1, .max = 3 }, | |
422 | .m = { .min = 79, .max = 127 }, | |
423 | .m1 = { .min = 12, .max = 22 }, | |
424 | .m2 = { .min = 5, .max = 9 }, | |
425 | .p = { .min = 14, .max = 56 }, | |
426 | .p1 = { .min = 2, .max = 8 }, | |
427 | .p2 = { .dot_limit = 225000, | |
428 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
429 | }; |
430 | ||
273e27ca | 431 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 432 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
433 | .dot = { .min = 25000, .max = 350000 }, |
434 | .vco = { .min = 1760000, .max = 3510000 }, | |
435 | .n = { .min = 1, .max = 2 }, | |
436 | .m = { .min = 79, .max = 126 }, | |
437 | .m1 = { .min = 12, .max = 22 }, | |
438 | .m2 = { .min = 5, .max = 9 }, | |
439 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 440 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
441 | .p2 = { .dot_limit = 225000, |
442 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
443 | }; |
444 | ||
445 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
446 | .dot = { .min = 25000, .max = 350000 }, |
447 | .vco = { .min = 1760000, .max = 3510000 }, | |
448 | .n = { .min = 1, .max = 3 }, | |
449 | .m = { .min = 79, .max = 126 }, | |
450 | .m1 = { .min = 12, .max = 22 }, | |
451 | .m2 = { .min = 5, .max = 9 }, | |
452 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 453 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
454 | .p2 = { .dot_limit = 225000, |
455 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
456 | }; |
457 | ||
dc730512 | 458 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
459 | /* |
460 | * These are the data rate limits (measured in fast clocks) | |
461 | * since those are the strictest limits we have. The fast | |
462 | * clock and actual rate limits are more relaxed, so checking | |
463 | * them would make no difference. | |
464 | */ | |
465 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 466 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 467 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
468 | .m1 = { .min = 2, .max = 3 }, |
469 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 470 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 471 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
472 | }; |
473 | ||
ef9348c8 CML |
474 | static const intel_limit_t intel_limits_chv = { |
475 | /* | |
476 | * These are the data rate limits (measured in fast clocks) | |
477 | * since those are the strictest limits we have. The fast | |
478 | * clock and actual rate limits are more relaxed, so checking | |
479 | * them would make no difference. | |
480 | */ | |
481 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 482 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
483 | .n = { .min = 1, .max = 1 }, |
484 | .m1 = { .min = 2, .max = 2 }, | |
485 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
486 | .p1 = { .min = 2, .max = 4 }, | |
487 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
488 | }; | |
489 | ||
5ab7b0b7 ID |
490 | static const intel_limit_t intel_limits_bxt = { |
491 | /* FIXME: find real dot limits */ | |
492 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 493 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
494 | .n = { .min = 1, .max = 1 }, |
495 | .m1 = { .min = 2, .max = 2 }, | |
496 | /* FIXME: find real m2 limits */ | |
497 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
498 | .p1 = { .min = 2, .max = 4 }, | |
499 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
500 | }; | |
501 | ||
cdba954e ACO |
502 | static bool |
503 | needs_modeset(struct drm_crtc_state *state) | |
504 | { | |
fc596660 | 505 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
506 | } |
507 | ||
e0638cdf PZ |
508 | /** |
509 | * Returns whether any output on the specified pipe is of the specified type | |
510 | */ | |
4093561b | 511 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 512 | { |
409ee761 | 513 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
514 | struct intel_encoder *encoder; |
515 | ||
409ee761 | 516 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
517 | if (encoder->type == type) |
518 | return true; | |
519 | ||
520 | return false; | |
521 | } | |
522 | ||
d0737e1d ACO |
523 | /** |
524 | * Returns whether any output on the specified pipe will have the specified | |
525 | * type after a staged modeset is complete, i.e., the same as | |
526 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
527 | * encoder->crtc. | |
528 | */ | |
a93e255f ACO |
529 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
530 | int type) | |
d0737e1d | 531 | { |
a93e255f | 532 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 533 | struct drm_connector *connector; |
a93e255f | 534 | struct drm_connector_state *connector_state; |
d0737e1d | 535 | struct intel_encoder *encoder; |
a93e255f ACO |
536 | int i, num_connectors = 0; |
537 | ||
da3ced29 | 538 | for_each_connector_in_state(state, connector, connector_state, i) { |
a93e255f ACO |
539 | if (connector_state->crtc != crtc_state->base.crtc) |
540 | continue; | |
541 | ||
542 | num_connectors++; | |
d0737e1d | 543 | |
a93e255f ACO |
544 | encoder = to_intel_encoder(connector_state->best_encoder); |
545 | if (encoder->type == type) | |
d0737e1d | 546 | return true; |
a93e255f ACO |
547 | } |
548 | ||
549 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
550 | |
551 | return false; | |
552 | } | |
553 | ||
a93e255f ACO |
554 | static const intel_limit_t * |
555 | intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) | |
2c07245f | 556 | { |
a93e255f | 557 | struct drm_device *dev = crtc_state->base.crtc->dev; |
2c07245f | 558 | const intel_limit_t *limit; |
b91ad0ec | 559 | |
a93e255f | 560 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 561 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 562 | if (refclk == 100000) |
b91ad0ec ZW |
563 | limit = &intel_limits_ironlake_dual_lvds_100m; |
564 | else | |
565 | limit = &intel_limits_ironlake_dual_lvds; | |
566 | } else { | |
1b894b59 | 567 | if (refclk == 100000) |
b91ad0ec ZW |
568 | limit = &intel_limits_ironlake_single_lvds_100m; |
569 | else | |
570 | limit = &intel_limits_ironlake_single_lvds; | |
571 | } | |
c6bb3538 | 572 | } else |
b91ad0ec | 573 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
574 | |
575 | return limit; | |
576 | } | |
577 | ||
a93e255f ACO |
578 | static const intel_limit_t * |
579 | intel_g4x_limit(struct intel_crtc_state *crtc_state) | |
044c7c41 | 580 | { |
a93e255f | 581 | struct drm_device *dev = crtc_state->base.crtc->dev; |
044c7c41 ML |
582 | const intel_limit_t *limit; |
583 | ||
a93e255f | 584 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 585 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 586 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 587 | else |
e4b36699 | 588 | limit = &intel_limits_g4x_single_channel_lvds; |
a93e255f ACO |
589 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || |
590 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 591 | limit = &intel_limits_g4x_hdmi; |
a93e255f | 592 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 593 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 594 | } else /* The option is for other outputs */ |
e4b36699 | 595 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
596 | |
597 | return limit; | |
598 | } | |
599 | ||
a93e255f ACO |
600 | static const intel_limit_t * |
601 | intel_limit(struct intel_crtc_state *crtc_state, int refclk) | |
79e53945 | 602 | { |
a93e255f | 603 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 JB |
604 | const intel_limit_t *limit; |
605 | ||
5ab7b0b7 ID |
606 | if (IS_BROXTON(dev)) |
607 | limit = &intel_limits_bxt; | |
608 | else if (HAS_PCH_SPLIT(dev)) | |
a93e255f | 609 | limit = intel_ironlake_limit(crtc_state, refclk); |
2c07245f | 610 | else if (IS_G4X(dev)) { |
a93e255f | 611 | limit = intel_g4x_limit(crtc_state); |
f2b115e6 | 612 | } else if (IS_PINEVIEW(dev)) { |
a93e255f | 613 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 614 | limit = &intel_limits_pineview_lvds; |
2177832f | 615 | else |
f2b115e6 | 616 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
617 | } else if (IS_CHERRYVIEW(dev)) { |
618 | limit = &intel_limits_chv; | |
a0c4da24 | 619 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 620 | limit = &intel_limits_vlv; |
a6c45cf0 | 621 | } else if (!IS_GEN2(dev)) { |
a93e255f | 622 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
623 | limit = &intel_limits_i9xx_lvds; |
624 | else | |
625 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 626 | } else { |
a93e255f | 627 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
e4b36699 | 628 | limit = &intel_limits_i8xx_lvds; |
a93e255f | 629 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
e4b36699 | 630 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
631 | else |
632 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
633 | } |
634 | return limit; | |
635 | } | |
636 | ||
dccbea3b ID |
637 | /* |
638 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
639 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
640 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
641 | * The helpers' return value is the rate of the clock that is fed to the | |
642 | * display engine's pipe which can be the above fast dot clock rate or a | |
643 | * divided-down version of it. | |
644 | */ | |
f2b115e6 | 645 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
dccbea3b | 646 | static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock) |
79e53945 | 647 | { |
2177832f SL |
648 | clock->m = clock->m2 + 2; |
649 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 650 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 651 | return 0; |
fb03ac01 VS |
652 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
653 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
654 | |
655 | return clock->dot; | |
2177832f SL |
656 | } |
657 | ||
7429e9d4 DV |
658 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
659 | { | |
660 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
661 | } | |
662 | ||
dccbea3b | 663 | static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock) |
2177832f | 664 | { |
7429e9d4 | 665 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 666 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 667 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 668 | return 0; |
fb03ac01 VS |
669 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
670 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
671 | |
672 | return clock->dot; | |
79e53945 JB |
673 | } |
674 | ||
dccbea3b | 675 | static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock) |
589eca67 ID |
676 | { |
677 | clock->m = clock->m1 * clock->m2; | |
678 | clock->p = clock->p1 * clock->p2; | |
679 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 680 | return 0; |
589eca67 ID |
681 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
682 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
683 | |
684 | return clock->dot / 5; | |
589eca67 ID |
685 | } |
686 | ||
dccbea3b | 687 | int chv_calc_dpll_params(int refclk, intel_clock_t *clock) |
ef9348c8 CML |
688 | { |
689 | clock->m = clock->m1 * clock->m2; | |
690 | clock->p = clock->p1 * clock->p2; | |
691 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 692 | return 0; |
ef9348c8 CML |
693 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
694 | clock->n << 22); | |
695 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
696 | |
697 | return clock->dot / 5; | |
ef9348c8 CML |
698 | } |
699 | ||
7c04d1d9 | 700 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
701 | /** |
702 | * Returns whether the given set of divisors are valid for a given refclk with | |
703 | * the given connectors. | |
704 | */ | |
705 | ||
1b894b59 CW |
706 | static bool intel_PLL_is_valid(struct drm_device *dev, |
707 | const intel_limit_t *limit, | |
708 | const intel_clock_t *clock) | |
79e53945 | 709 | { |
f01b7962 VS |
710 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
711 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 712 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 713 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 714 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 715 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 716 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 717 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 718 | |
666a4537 WB |
719 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && |
720 | !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) | |
f01b7962 VS |
721 | if (clock->m1 <= clock->m2) |
722 | INTELPllInvalid("m1 <= m2\n"); | |
723 | ||
666a4537 | 724 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
725 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
726 | INTELPllInvalid("p out of range\n"); | |
727 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
728 | INTELPllInvalid("m out of range\n"); | |
729 | } | |
730 | ||
79e53945 | 731 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 732 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
733 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
734 | * connector, etc., rather than just a single range. | |
735 | */ | |
736 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 737 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
738 | |
739 | return true; | |
740 | } | |
741 | ||
3b1429d9 VS |
742 | static int |
743 | i9xx_select_p2_div(const intel_limit_t *limit, | |
744 | const struct intel_crtc_state *crtc_state, | |
745 | int target) | |
79e53945 | 746 | { |
3b1429d9 | 747 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 748 | |
a93e255f | 749 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 750 | /* |
a210b028 DV |
751 | * For LVDS just rely on its current settings for dual-channel. |
752 | * We haven't figured out how to reliably set up different | |
753 | * single/dual channel state, if we even can. | |
79e53945 | 754 | */ |
1974cad0 | 755 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 756 | return limit->p2.p2_fast; |
79e53945 | 757 | else |
3b1429d9 | 758 | return limit->p2.p2_slow; |
79e53945 JB |
759 | } else { |
760 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 761 | return limit->p2.p2_slow; |
79e53945 | 762 | else |
3b1429d9 | 763 | return limit->p2.p2_fast; |
79e53945 | 764 | } |
3b1429d9 VS |
765 | } |
766 | ||
767 | static bool | |
768 | i9xx_find_best_dpll(const intel_limit_t *limit, | |
769 | struct intel_crtc_state *crtc_state, | |
770 | int target, int refclk, intel_clock_t *match_clock, | |
771 | intel_clock_t *best_clock) | |
772 | { | |
773 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
774 | intel_clock_t clock; | |
775 | int err = target; | |
79e53945 | 776 | |
0206e353 | 777 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 778 | |
3b1429d9 VS |
779 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
780 | ||
42158660 ZY |
781 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
782 | clock.m1++) { | |
783 | for (clock.m2 = limit->m2.min; | |
784 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 785 | if (clock.m2 >= clock.m1) |
42158660 ZY |
786 | break; |
787 | for (clock.n = limit->n.min; | |
788 | clock.n <= limit->n.max; clock.n++) { | |
789 | for (clock.p1 = limit->p1.min; | |
790 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
791 | int this_err; |
792 | ||
dccbea3b | 793 | i9xx_calc_dpll_params(refclk, &clock); |
ac58c3f0 DV |
794 | if (!intel_PLL_is_valid(dev, limit, |
795 | &clock)) | |
796 | continue; | |
797 | if (match_clock && | |
798 | clock.p != match_clock->p) | |
799 | continue; | |
800 | ||
801 | this_err = abs(clock.dot - target); | |
802 | if (this_err < err) { | |
803 | *best_clock = clock; | |
804 | err = this_err; | |
805 | } | |
806 | } | |
807 | } | |
808 | } | |
809 | } | |
810 | ||
811 | return (err != target); | |
812 | } | |
813 | ||
814 | static bool | |
a93e255f ACO |
815 | pnv_find_best_dpll(const intel_limit_t *limit, |
816 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
817 | int target, int refclk, intel_clock_t *match_clock, |
818 | intel_clock_t *best_clock) | |
79e53945 | 819 | { |
3b1429d9 | 820 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 821 | intel_clock_t clock; |
79e53945 JB |
822 | int err = target; |
823 | ||
0206e353 | 824 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 825 | |
3b1429d9 VS |
826 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
827 | ||
42158660 ZY |
828 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
829 | clock.m1++) { | |
830 | for (clock.m2 = limit->m2.min; | |
831 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
832 | for (clock.n = limit->n.min; |
833 | clock.n <= limit->n.max; clock.n++) { | |
834 | for (clock.p1 = limit->p1.min; | |
835 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
836 | int this_err; |
837 | ||
dccbea3b | 838 | pnv_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
839 | if (!intel_PLL_is_valid(dev, limit, |
840 | &clock)) | |
79e53945 | 841 | continue; |
cec2f356 SP |
842 | if (match_clock && |
843 | clock.p != match_clock->p) | |
844 | continue; | |
79e53945 JB |
845 | |
846 | this_err = abs(clock.dot - target); | |
847 | if (this_err < err) { | |
848 | *best_clock = clock; | |
849 | err = this_err; | |
850 | } | |
851 | } | |
852 | } | |
853 | } | |
854 | } | |
855 | ||
856 | return (err != target); | |
857 | } | |
858 | ||
d4906093 | 859 | static bool |
a93e255f ACO |
860 | g4x_find_best_dpll(const intel_limit_t *limit, |
861 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
862 | int target, int refclk, intel_clock_t *match_clock, |
863 | intel_clock_t *best_clock) | |
d4906093 | 864 | { |
3b1429d9 | 865 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d4906093 ML |
866 | intel_clock_t clock; |
867 | int max_n; | |
3b1429d9 | 868 | bool found = false; |
6ba770dc AJ |
869 | /* approximately equals target * 0.00585 */ |
870 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
871 | |
872 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
873 | |
874 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
875 | ||
d4906093 | 876 | max_n = limit->n.max; |
f77f13e2 | 877 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 878 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 879 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
880 | for (clock.m1 = limit->m1.max; |
881 | clock.m1 >= limit->m1.min; clock.m1--) { | |
882 | for (clock.m2 = limit->m2.max; | |
883 | clock.m2 >= limit->m2.min; clock.m2--) { | |
884 | for (clock.p1 = limit->p1.max; | |
885 | clock.p1 >= limit->p1.min; clock.p1--) { | |
886 | int this_err; | |
887 | ||
dccbea3b | 888 | i9xx_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
889 | if (!intel_PLL_is_valid(dev, limit, |
890 | &clock)) | |
d4906093 | 891 | continue; |
1b894b59 CW |
892 | |
893 | this_err = abs(clock.dot - target); | |
d4906093 ML |
894 | if (this_err < err_most) { |
895 | *best_clock = clock; | |
896 | err_most = this_err; | |
897 | max_n = clock.n; | |
898 | found = true; | |
899 | } | |
900 | } | |
901 | } | |
902 | } | |
903 | } | |
2c07245f ZW |
904 | return found; |
905 | } | |
906 | ||
d5dd62bd ID |
907 | /* |
908 | * Check if the calculated PLL configuration is more optimal compared to the | |
909 | * best configuration and error found so far. Return the calculated error. | |
910 | */ | |
911 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
912 | const intel_clock_t *calculated_clock, | |
913 | const intel_clock_t *best_clock, | |
914 | unsigned int best_error_ppm, | |
915 | unsigned int *error_ppm) | |
916 | { | |
9ca3ba01 ID |
917 | /* |
918 | * For CHV ignore the error and consider only the P value. | |
919 | * Prefer a bigger P value based on HW requirements. | |
920 | */ | |
921 | if (IS_CHERRYVIEW(dev)) { | |
922 | *error_ppm = 0; | |
923 | ||
924 | return calculated_clock->p > best_clock->p; | |
925 | } | |
926 | ||
24be4e46 ID |
927 | if (WARN_ON_ONCE(!target_freq)) |
928 | return false; | |
929 | ||
d5dd62bd ID |
930 | *error_ppm = div_u64(1000000ULL * |
931 | abs(target_freq - calculated_clock->dot), | |
932 | target_freq); | |
933 | /* | |
934 | * Prefer a better P value over a better (smaller) error if the error | |
935 | * is small. Ensure this preference for future configurations too by | |
936 | * setting the error to 0. | |
937 | */ | |
938 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
939 | *error_ppm = 0; | |
940 | ||
941 | return true; | |
942 | } | |
943 | ||
944 | return *error_ppm + 10 < best_error_ppm; | |
945 | } | |
946 | ||
a0c4da24 | 947 | static bool |
a93e255f ACO |
948 | vlv_find_best_dpll(const intel_limit_t *limit, |
949 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
950 | int target, int refclk, intel_clock_t *match_clock, |
951 | intel_clock_t *best_clock) | |
a0c4da24 | 952 | { |
a93e255f | 953 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 954 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 955 | intel_clock_t clock; |
69e4f900 | 956 | unsigned int bestppm = 1000000; |
27e639bf VS |
957 | /* min update 19.2 MHz */ |
958 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 959 | bool found = false; |
a0c4da24 | 960 | |
6b4bf1c4 VS |
961 | target *= 5; /* fast clock */ |
962 | ||
963 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
964 | |
965 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 966 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 967 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 968 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 969 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 970 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 971 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 972 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 973 | unsigned int ppm; |
69e4f900 | 974 | |
6b4bf1c4 VS |
975 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
976 | refclk * clock.m1); | |
977 | ||
dccbea3b | 978 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 979 | |
f01b7962 VS |
980 | if (!intel_PLL_is_valid(dev, limit, |
981 | &clock)) | |
43b0ac53 VS |
982 | continue; |
983 | ||
d5dd62bd ID |
984 | if (!vlv_PLL_is_optimal(dev, target, |
985 | &clock, | |
986 | best_clock, | |
987 | bestppm, &ppm)) | |
988 | continue; | |
6b4bf1c4 | 989 | |
d5dd62bd ID |
990 | *best_clock = clock; |
991 | bestppm = ppm; | |
992 | found = true; | |
a0c4da24 JB |
993 | } |
994 | } | |
995 | } | |
996 | } | |
a0c4da24 | 997 | |
49e497ef | 998 | return found; |
a0c4da24 | 999 | } |
a4fc5ed6 | 1000 | |
ef9348c8 | 1001 | static bool |
a93e255f ACO |
1002 | chv_find_best_dpll(const intel_limit_t *limit, |
1003 | struct intel_crtc_state *crtc_state, | |
ef9348c8 CML |
1004 | int target, int refclk, intel_clock_t *match_clock, |
1005 | intel_clock_t *best_clock) | |
1006 | { | |
a93e255f | 1007 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 1008 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 1009 | unsigned int best_error_ppm; |
ef9348c8 CML |
1010 | intel_clock_t clock; |
1011 | uint64_t m2; | |
1012 | int found = false; | |
1013 | ||
1014 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 1015 | best_error_ppm = 1000000; |
ef9348c8 CML |
1016 | |
1017 | /* | |
1018 | * Based on hardware doc, the n always set to 1, and m1 always | |
1019 | * set to 2. If requires to support 200Mhz refclk, we need to | |
1020 | * revisit this because n may not 1 anymore. | |
1021 | */ | |
1022 | clock.n = 1, clock.m1 = 2; | |
1023 | target *= 5; /* fast clock */ | |
1024 | ||
1025 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
1026 | for (clock.p2 = limit->p2.p2_fast; | |
1027 | clock.p2 >= limit->p2.p2_slow; | |
1028 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 1029 | unsigned int error_ppm; |
ef9348c8 CML |
1030 | |
1031 | clock.p = clock.p1 * clock.p2; | |
1032 | ||
1033 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
1034 | clock.n) << 22, refclk * clock.m1); | |
1035 | ||
1036 | if (m2 > INT_MAX/clock.m1) | |
1037 | continue; | |
1038 | ||
1039 | clock.m2 = m2; | |
1040 | ||
dccbea3b | 1041 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 CML |
1042 | |
1043 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
1044 | continue; | |
1045 | ||
9ca3ba01 ID |
1046 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
1047 | best_error_ppm, &error_ppm)) | |
1048 | continue; | |
1049 | ||
1050 | *best_clock = clock; | |
1051 | best_error_ppm = error_ppm; | |
1052 | found = true; | |
ef9348c8 CML |
1053 | } |
1054 | } | |
1055 | ||
1056 | return found; | |
1057 | } | |
1058 | ||
5ab7b0b7 ID |
1059 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
1060 | intel_clock_t *best_clock) | |
1061 | { | |
1062 | int refclk = i9xx_get_refclk(crtc_state, 0); | |
1063 | ||
1064 | return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state, | |
1065 | target_clock, refclk, NULL, best_clock); | |
1066 | } | |
1067 | ||
20ddf665 VS |
1068 | bool intel_crtc_active(struct drm_crtc *crtc) |
1069 | { | |
1070 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1071 | ||
1072 | /* Be paranoid as we can arrive here with only partial | |
1073 | * state retrieved from the hardware during setup. | |
1074 | * | |
241bfc38 | 1075 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1076 | * as Haswell has gained clock readout/fastboot support. |
1077 | * | |
66e514c1 | 1078 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1079 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1080 | * |
1081 | * FIXME: The intel_crtc->active here should be switched to | |
1082 | * crtc->state->active once we have proper CRTC states wired up | |
1083 | * for atomic. | |
20ddf665 | 1084 | */ |
c3d1f436 | 1085 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1086 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1087 | } |
1088 | ||
a5c961d1 PZ |
1089 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1090 | enum pipe pipe) | |
1091 | { | |
1092 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1093 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1094 | ||
6e3c9717 | 1095 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1096 | } |
1097 | ||
fbf49ea2 VS |
1098 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1099 | { | |
1100 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1101 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1102 | u32 line1, line2; |
1103 | u32 line_mask; | |
1104 | ||
1105 | if (IS_GEN2(dev)) | |
1106 | line_mask = DSL_LINEMASK_GEN2; | |
1107 | else | |
1108 | line_mask = DSL_LINEMASK_GEN3; | |
1109 | ||
1110 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1111 | msleep(5); |
fbf49ea2 VS |
1112 | line2 = I915_READ(reg) & line_mask; |
1113 | ||
1114 | return line1 == line2; | |
1115 | } | |
1116 | ||
ab7ad7f6 KP |
1117 | /* |
1118 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1119 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1120 | * |
1121 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1122 | * spinning on the vblank interrupt status bit, since we won't actually | |
1123 | * see an interrupt when the pipe is disabled. | |
1124 | * | |
ab7ad7f6 KP |
1125 | * On Gen4 and above: |
1126 | * wait for the pipe register state bit to turn off | |
1127 | * | |
1128 | * Otherwise: | |
1129 | * wait for the display line value to settle (it usually | |
1130 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1131 | * |
9d0498a2 | 1132 | */ |
575f7ab7 | 1133 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1134 | { |
575f7ab7 | 1135 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1136 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1137 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1138 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1139 | |
1140 | if (INTEL_INFO(dev)->gen >= 4) { | |
f0f59a00 | 1141 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1142 | |
1143 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1144 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1145 | 100)) | |
284637d9 | 1146 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1147 | } else { |
ab7ad7f6 | 1148 | /* Wait for the display line to settle */ |
fbf49ea2 | 1149 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1150 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1151 | } |
79e53945 JB |
1152 | } |
1153 | ||
b24e7179 JB |
1154 | static const char *state_string(bool enabled) |
1155 | { | |
1156 | return enabled ? "on" : "off"; | |
1157 | } | |
1158 | ||
1159 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1160 | void assert_pll(struct drm_i915_private *dev_priv, |
1161 | enum pipe pipe, bool state) | |
b24e7179 | 1162 | { |
b24e7179 JB |
1163 | u32 val; |
1164 | bool cur_state; | |
1165 | ||
649636ef | 1166 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1167 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1168 | I915_STATE_WARN(cur_state != state, |
b24e7179 JB |
1169 | "PLL state assertion failure (expected %s, current %s)\n", |
1170 | state_string(state), state_string(cur_state)); | |
1171 | } | |
b24e7179 | 1172 | |
23538ef1 JN |
1173 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1174 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1175 | { | |
1176 | u32 val; | |
1177 | bool cur_state; | |
1178 | ||
a580516d | 1179 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1180 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1181 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1182 | |
1183 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1184 | I915_STATE_WARN(cur_state != state, |
23538ef1 JN |
1185 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
1186 | state_string(state), state_string(cur_state)); | |
1187 | } | |
1188 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1189 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1190 | ||
55607e8a | 1191 | struct intel_shared_dpll * |
e2b78267 DV |
1192 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1193 | { | |
1194 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1195 | ||
6e3c9717 | 1196 | if (crtc->config->shared_dpll < 0) |
e2b78267 DV |
1197 | return NULL; |
1198 | ||
6e3c9717 | 1199 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
e2b78267 DV |
1200 | } |
1201 | ||
040484af | 1202 | /* For ILK+ */ |
55607e8a DV |
1203 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1204 | struct intel_shared_dpll *pll, | |
1205 | bool state) | |
040484af | 1206 | { |
040484af | 1207 | bool cur_state; |
5358901f | 1208 | struct intel_dpll_hw_state hw_state; |
040484af | 1209 | |
92b27b08 | 1210 | if (WARN (!pll, |
46edb027 | 1211 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1212 | return; |
ee7b9f93 | 1213 | |
5358901f | 1214 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
e2c719b7 | 1215 | I915_STATE_WARN(cur_state != state, |
5358901f DV |
1216 | "%s assertion failure (expected %s, current %s)\n", |
1217 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1218 | } |
040484af JB |
1219 | |
1220 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1221 | enum pipe pipe, bool state) | |
1222 | { | |
040484af | 1223 | bool cur_state; |
ad80a810 PZ |
1224 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1225 | pipe); | |
040484af | 1226 | |
affa9354 PZ |
1227 | if (HAS_DDI(dev_priv->dev)) { |
1228 | /* DDI does not have a specific FDI_TX register */ | |
649636ef | 1229 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1230 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1231 | } else { |
649636ef | 1232 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1233 | cur_state = !!(val & FDI_TX_ENABLE); |
1234 | } | |
e2c719b7 | 1235 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1236 | "FDI TX state assertion failure (expected %s, current %s)\n", |
1237 | state_string(state), state_string(cur_state)); | |
1238 | } | |
1239 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1240 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1241 | ||
1242 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1243 | enum pipe pipe, bool state) | |
1244 | { | |
040484af JB |
1245 | u32 val; |
1246 | bool cur_state; | |
1247 | ||
649636ef | 1248 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1249 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1250 | I915_STATE_WARN(cur_state != state, |
040484af JB |
1251 | "FDI RX state assertion failure (expected %s, current %s)\n", |
1252 | state_string(state), state_string(cur_state)); | |
1253 | } | |
1254 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1255 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1256 | ||
1257 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1258 | enum pipe pipe) | |
1259 | { | |
040484af JB |
1260 | u32 val; |
1261 | ||
1262 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1263 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1264 | return; |
1265 | ||
bf507ef7 | 1266 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1267 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1268 | return; |
1269 | ||
649636ef | 1270 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1271 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1272 | } |
1273 | ||
55607e8a DV |
1274 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1275 | enum pipe pipe, bool state) | |
040484af | 1276 | { |
040484af | 1277 | u32 val; |
55607e8a | 1278 | bool cur_state; |
040484af | 1279 | |
649636ef | 1280 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1281 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1282 | I915_STATE_WARN(cur_state != state, |
55607e8a DV |
1283 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
1284 | state_string(state), state_string(cur_state)); | |
040484af JB |
1285 | } |
1286 | ||
b680c37a DV |
1287 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1288 | enum pipe pipe) | |
ea0760cf | 1289 | { |
bedd4dba | 1290 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 | 1291 | i915_reg_t pp_reg; |
ea0760cf JB |
1292 | u32 val; |
1293 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1294 | bool locked = true; |
ea0760cf | 1295 | |
bedd4dba JN |
1296 | if (WARN_ON(HAS_DDI(dev))) |
1297 | return; | |
1298 | ||
1299 | if (HAS_PCH_SPLIT(dev)) { | |
1300 | u32 port_sel; | |
1301 | ||
ea0760cf | 1302 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1303 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1304 | ||
1305 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1306 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1307 | panel_pipe = PIPE_B; | |
1308 | /* XXX: else fix for eDP */ | |
666a4537 | 1309 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
bedd4dba JN |
1310 | /* presumably write lock depends on pipe, not port select */ |
1311 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1312 | panel_pipe = pipe; | |
ea0760cf JB |
1313 | } else { |
1314 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1315 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1316 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1317 | } |
1318 | ||
1319 | val = I915_READ(pp_reg); | |
1320 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1321 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1322 | locked = false; |
1323 | ||
e2c719b7 | 1324 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1325 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1326 | pipe_name(pipe)); |
ea0760cf JB |
1327 | } |
1328 | ||
93ce0ba6 JN |
1329 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1330 | enum pipe pipe, bool state) | |
1331 | { | |
1332 | struct drm_device *dev = dev_priv->dev; | |
1333 | bool cur_state; | |
1334 | ||
d9d82081 | 1335 | if (IS_845G(dev) || IS_I865G(dev)) |
0b87c24e | 1336 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1337 | else |
5efb3e28 | 1338 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1339 | |
e2c719b7 | 1340 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 JN |
1341 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
1342 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1343 | } | |
1344 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1345 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1346 | ||
b840d907 JB |
1347 | void assert_pipe(struct drm_i915_private *dev_priv, |
1348 | enum pipe pipe, bool state) | |
b24e7179 | 1349 | { |
63d7bbe9 | 1350 | bool cur_state; |
702e7a56 PZ |
1351 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1352 | pipe); | |
b24e7179 | 1353 | |
b6b5d049 VS |
1354 | /* if we need the pipe quirk it must be always on */ |
1355 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1356 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1357 | state = true; |
1358 | ||
f458ebbc | 1359 | if (!intel_display_power_is_enabled(dev_priv, |
b97186f0 | 1360 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1361 | cur_state = false; |
1362 | } else { | |
649636ef | 1363 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 PZ |
1364 | cur_state = !!(val & PIPECONF_ENABLE); |
1365 | } | |
1366 | ||
e2c719b7 | 1367 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1368 | "pipe %c assertion failure (expected %s, current %s)\n", |
9db4a9c7 | 1369 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1370 | } |
1371 | ||
931872fc CW |
1372 | static void assert_plane(struct drm_i915_private *dev_priv, |
1373 | enum plane plane, bool state) | |
b24e7179 | 1374 | { |
b24e7179 | 1375 | u32 val; |
931872fc | 1376 | bool cur_state; |
b24e7179 | 1377 | |
649636ef | 1378 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1379 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1380 | I915_STATE_WARN(cur_state != state, |
931872fc CW |
1381 | "plane %c assertion failure (expected %s, current %s)\n", |
1382 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1383 | } |
1384 | ||
931872fc CW |
1385 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1386 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1387 | ||
b24e7179 JB |
1388 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1389 | enum pipe pipe) | |
1390 | { | |
653e1026 | 1391 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1392 | int i; |
b24e7179 | 1393 | |
653e1026 VS |
1394 | /* Primary planes are fixed to pipes on gen4+ */ |
1395 | if (INTEL_INFO(dev)->gen >= 4) { | |
649636ef | 1396 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1397 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1398 | "plane %c assertion failure, should be disabled but not\n", |
1399 | plane_name(pipe)); | |
19ec1358 | 1400 | return; |
28c05794 | 1401 | } |
19ec1358 | 1402 | |
b24e7179 | 1403 | /* Need to check both planes against the pipe */ |
055e393f | 1404 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1405 | u32 val = I915_READ(DSPCNTR(i)); |
1406 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1407 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1408 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1409 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1410 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1411 | } |
1412 | } | |
1413 | ||
19332d7a JB |
1414 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1415 | enum pipe pipe) | |
1416 | { | |
20674eef | 1417 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1418 | int sprite; |
19332d7a | 1419 | |
7feb8b88 | 1420 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1421 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1422 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1423 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1424 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1425 | sprite, pipe_name(pipe)); | |
1426 | } | |
666a4537 | 1427 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
3bdcfc0c | 1428 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1429 | u32 val = I915_READ(SPCNTR(pipe, sprite)); |
e2c719b7 | 1430 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1431 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1432 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1433 | } |
1434 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
649636ef | 1435 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1436 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1437 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1438 | plane_name(pipe), pipe_name(pipe)); |
1439 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
649636ef | 1440 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1441 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1442 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1443 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1444 | } |
1445 | } | |
1446 | ||
08c71e5e VS |
1447 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1448 | { | |
e2c719b7 | 1449 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1450 | drm_crtc_vblank_put(crtc); |
1451 | } | |
1452 | ||
89eff4be | 1453 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1454 | { |
1455 | u32 val; | |
1456 | bool enabled; | |
1457 | ||
e2c719b7 | 1458 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1459 | |
92f2584a JB |
1460 | val = I915_READ(PCH_DREF_CONTROL); |
1461 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1462 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
e2c719b7 | 1463 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
92f2584a JB |
1464 | } |
1465 | ||
ab9412ba DV |
1466 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1467 | enum pipe pipe) | |
92f2584a | 1468 | { |
92f2584a JB |
1469 | u32 val; |
1470 | bool enabled; | |
1471 | ||
649636ef | 1472 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1473 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1474 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1475 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1476 | pipe_name(pipe)); | |
92f2584a JB |
1477 | } |
1478 | ||
4e634389 KP |
1479 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1480 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1481 | { |
1482 | if ((val & DP_PORT_EN) == 0) | |
1483 | return false; | |
1484 | ||
1485 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
f0f59a00 | 1486 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1487 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1488 | return false; | |
44f37d1f CML |
1489 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1490 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1491 | return false; | |
f0575e92 KP |
1492 | } else { |
1493 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1494 | return false; | |
1495 | } | |
1496 | return true; | |
1497 | } | |
1498 | ||
1519b995 KP |
1499 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1500 | enum pipe pipe, u32 val) | |
1501 | { | |
dc0fa718 | 1502 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1503 | return false; |
1504 | ||
1505 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1506 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1507 | return false; |
44f37d1f CML |
1508 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1509 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1510 | return false; | |
1519b995 | 1511 | } else { |
dc0fa718 | 1512 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1513 | return false; |
1514 | } | |
1515 | return true; | |
1516 | } | |
1517 | ||
1518 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1519 | enum pipe pipe, u32 val) | |
1520 | { | |
1521 | if ((val & LVDS_PORT_EN) == 0) | |
1522 | return false; | |
1523 | ||
1524 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1525 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1526 | return false; | |
1527 | } else { | |
1528 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1529 | return false; | |
1530 | } | |
1531 | return true; | |
1532 | } | |
1533 | ||
1534 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1535 | enum pipe pipe, u32 val) | |
1536 | { | |
1537 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1538 | return false; | |
1539 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1540 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1541 | return false; | |
1542 | } else { | |
1543 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1544 | return false; | |
1545 | } | |
1546 | return true; | |
1547 | } | |
1548 | ||
291906f1 | 1549 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1550 | enum pipe pipe, i915_reg_t reg, |
1551 | u32 port_sel) | |
291906f1 | 1552 | { |
47a05eca | 1553 | u32 val = I915_READ(reg); |
e2c719b7 | 1554 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1555 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1556 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1557 | |
e2c719b7 | 1558 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1559 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1560 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1561 | } |
1562 | ||
1563 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1564 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1565 | { |
47a05eca | 1566 | u32 val = I915_READ(reg); |
e2c719b7 | 1567 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1568 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1569 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1570 | |
e2c719b7 | 1571 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1572 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1573 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1574 | } |
1575 | ||
1576 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1577 | enum pipe pipe) | |
1578 | { | |
291906f1 | 1579 | u32 val; |
291906f1 | 1580 | |
f0575e92 KP |
1581 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1582 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1583 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1584 | |
649636ef | 1585 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1586 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1587 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1588 | pipe_name(pipe)); |
291906f1 | 1589 | |
649636ef | 1590 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1591 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1592 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1593 | pipe_name(pipe)); |
291906f1 | 1594 | |
e2debe91 PZ |
1595 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1596 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1597 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1598 | } |
1599 | ||
d288f65f | 1600 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1601 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1602 | { |
426115cf DV |
1603 | struct drm_device *dev = crtc->base.dev; |
1604 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1605 | i915_reg_t reg = DPLL(crtc->pipe); |
d288f65f | 1606 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1607 | |
426115cf | 1608 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 | 1609 | |
87442f73 | 1610 | /* PLL is protected by panel, make sure we can write it */ |
6a9e7363 | 1611 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1612 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1613 | |
426115cf DV |
1614 | I915_WRITE(reg, dpll); |
1615 | POSTING_READ(reg); | |
1616 | udelay(150); | |
1617 | ||
1618 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1619 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1620 | ||
d288f65f | 1621 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1622 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1623 | |
1624 | /* We do this three times for luck */ | |
426115cf | 1625 | I915_WRITE(reg, dpll); |
87442f73 DV |
1626 | POSTING_READ(reg); |
1627 | udelay(150); /* wait for warmup */ | |
426115cf | 1628 | I915_WRITE(reg, dpll); |
87442f73 DV |
1629 | POSTING_READ(reg); |
1630 | udelay(150); /* wait for warmup */ | |
426115cf | 1631 | I915_WRITE(reg, dpll); |
87442f73 DV |
1632 | POSTING_READ(reg); |
1633 | udelay(150); /* wait for warmup */ | |
1634 | } | |
1635 | ||
d288f65f | 1636 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1637 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1638 | { |
1639 | struct drm_device *dev = crtc->base.dev; | |
1640 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1641 | int pipe = crtc->pipe; | |
1642 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1643 | u32 tmp; |
1644 | ||
1645 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1646 | ||
a580516d | 1647 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1648 | |
1649 | /* Enable back the 10bit clock to display controller */ | |
1650 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1651 | tmp |= DPIO_DCLKP_EN; | |
1652 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1653 | ||
54433e91 VS |
1654 | mutex_unlock(&dev_priv->sb_lock); |
1655 | ||
9d556c99 CML |
1656 | /* |
1657 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1658 | */ | |
1659 | udelay(1); | |
1660 | ||
1661 | /* Enable PLL */ | |
d288f65f | 1662 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1663 | |
1664 | /* Check PLL is locked */ | |
a11b0703 | 1665 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1666 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1667 | ||
a11b0703 | 1668 | /* not sure when this should be written */ |
d288f65f | 1669 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 | 1670 | POSTING_READ(DPLL_MD(pipe)); |
9d556c99 CML |
1671 | } |
1672 | ||
1c4e0274 VS |
1673 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1674 | { | |
1675 | struct intel_crtc *crtc; | |
1676 | int count = 0; | |
1677 | ||
1678 | for_each_intel_crtc(dev, crtc) | |
3538b9df | 1679 | count += crtc->base.state->active && |
409ee761 | 1680 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1681 | |
1682 | return count; | |
1683 | } | |
1684 | ||
66e3d5c0 | 1685 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1686 | { |
66e3d5c0 DV |
1687 | struct drm_device *dev = crtc->base.dev; |
1688 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1689 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1690 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1691 | |
66e3d5c0 | 1692 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1693 | |
63d7bbe9 | 1694 | /* No really, not for ILK+ */ |
3d13ef2e | 1695 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1696 | |
1697 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1698 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1699 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1700 | |
1c4e0274 VS |
1701 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1702 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1703 | /* | |
1704 | * It appears to be important that we don't enable this | |
1705 | * for the current pipe before otherwise configuring the | |
1706 | * PLL. No idea how this should be handled if multiple | |
1707 | * DVO outputs are enabled simultaneosly. | |
1708 | */ | |
1709 | dpll |= DPLL_DVO_2X_MODE; | |
1710 | I915_WRITE(DPLL(!crtc->pipe), | |
1711 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1712 | } | |
66e3d5c0 | 1713 | |
c2b63374 VS |
1714 | /* |
1715 | * Apparently we need to have VGA mode enabled prior to changing | |
1716 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1717 | * dividers, even though the register value does change. | |
1718 | */ | |
1719 | I915_WRITE(reg, 0); | |
1720 | ||
8e7a65aa VS |
1721 | I915_WRITE(reg, dpll); |
1722 | ||
66e3d5c0 DV |
1723 | /* Wait for the clocks to stabilize. */ |
1724 | POSTING_READ(reg); | |
1725 | udelay(150); | |
1726 | ||
1727 | if (INTEL_INFO(dev)->gen >= 4) { | |
1728 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1729 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1730 | } else { |
1731 | /* The pixel multiplier can only be updated once the | |
1732 | * DPLL is enabled and the clocks are stable. | |
1733 | * | |
1734 | * So write it again. | |
1735 | */ | |
1736 | I915_WRITE(reg, dpll); | |
1737 | } | |
63d7bbe9 JB |
1738 | |
1739 | /* We do this three times for luck */ | |
66e3d5c0 | 1740 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1741 | POSTING_READ(reg); |
1742 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1743 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1744 | POSTING_READ(reg); |
1745 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1746 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1747 | POSTING_READ(reg); |
1748 | udelay(150); /* wait for warmup */ | |
1749 | } | |
1750 | ||
1751 | /** | |
50b44a44 | 1752 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1753 | * @dev_priv: i915 private structure |
1754 | * @pipe: pipe PLL to disable | |
1755 | * | |
1756 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1757 | * | |
1758 | * Note! This is for pre-ILK only. | |
1759 | */ | |
1c4e0274 | 1760 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1761 | { |
1c4e0274 VS |
1762 | struct drm_device *dev = crtc->base.dev; |
1763 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1764 | enum pipe pipe = crtc->pipe; | |
1765 | ||
1766 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1767 | if (IS_I830(dev) && | |
409ee761 | 1768 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
3538b9df | 1769 | !intel_num_dvo_pipes(dev)) { |
1c4e0274 VS |
1770 | I915_WRITE(DPLL(PIPE_B), |
1771 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1772 | I915_WRITE(DPLL(PIPE_A), | |
1773 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1774 | } | |
1775 | ||
b6b5d049 VS |
1776 | /* Don't disable pipe or pipe PLLs if needed */ |
1777 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1778 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1779 | return; |
1780 | ||
1781 | /* Make sure the pipe isn't still relying on us */ | |
1782 | assert_pipe_disabled(dev_priv, pipe); | |
1783 | ||
b8afb911 | 1784 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1785 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1786 | } |
1787 | ||
f6071166 JB |
1788 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1789 | { | |
b8afb911 | 1790 | u32 val; |
f6071166 JB |
1791 | |
1792 | /* Make sure the pipe isn't still relying on us */ | |
1793 | assert_pipe_disabled(dev_priv, pipe); | |
1794 | ||
e5cbfbfb ID |
1795 | /* |
1796 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1797 | * The latter is needed for VGA hotplug / manual detection. | |
1798 | */ | |
b8afb911 | 1799 | val = DPLL_VGA_MODE_DIS; |
f6071166 | 1800 | if (pipe == PIPE_B) |
60bfe44f | 1801 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV; |
f6071166 JB |
1802 | I915_WRITE(DPLL(pipe), val); |
1803 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1804 | |
1805 | } | |
1806 | ||
1807 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1808 | { | |
d752048d | 1809 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1810 | u32 val; |
1811 | ||
a11b0703 VS |
1812 | /* Make sure the pipe isn't still relying on us */ |
1813 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1814 | |
a11b0703 | 1815 | /* Set PLL en = 0 */ |
60bfe44f VS |
1816 | val = DPLL_SSC_REF_CLK_CHV | |
1817 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1818 | if (pipe != PIPE_A) |
1819 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1820 | I915_WRITE(DPLL(pipe), val); | |
1821 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1822 | |
a580516d | 1823 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1824 | |
1825 | /* Disable 10bit clock to display controller */ | |
1826 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1827 | val &= ~DPIO_DCLKP_EN; | |
1828 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1829 | ||
a580516d | 1830 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1831 | } |
1832 | ||
e4607fcf | 1833 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1834 | struct intel_digital_port *dport, |
1835 | unsigned int expected_mask) | |
89b667f8 JB |
1836 | { |
1837 | u32 port_mask; | |
f0f59a00 | 1838 | i915_reg_t dpll_reg; |
89b667f8 | 1839 | |
e4607fcf CML |
1840 | switch (dport->port) { |
1841 | case PORT_B: | |
89b667f8 | 1842 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1843 | dpll_reg = DPLL(0); |
e4607fcf CML |
1844 | break; |
1845 | case PORT_C: | |
89b667f8 | 1846 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1847 | dpll_reg = DPLL(0); |
9b6de0a1 | 1848 | expected_mask <<= 4; |
00fc31b7 CML |
1849 | break; |
1850 | case PORT_D: | |
1851 | port_mask = DPLL_PORTD_READY_MASK; | |
1852 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1853 | break; |
1854 | default: | |
1855 | BUG(); | |
1856 | } | |
89b667f8 | 1857 | |
9b6de0a1 VS |
1858 | if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) |
1859 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", | |
1860 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1861 | } |
1862 | ||
b14b1055 DV |
1863 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1864 | { | |
1865 | struct drm_device *dev = crtc->base.dev; | |
1866 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1867 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1868 | ||
be19f0ff CW |
1869 | if (WARN_ON(pll == NULL)) |
1870 | return; | |
1871 | ||
3e369b76 | 1872 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1873 | if (pll->active == 0) { |
1874 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1875 | WARN_ON(pll->on); | |
1876 | assert_shared_dpll_disabled(dev_priv, pll); | |
1877 | ||
1878 | pll->mode_set(dev_priv, pll); | |
1879 | } | |
1880 | } | |
1881 | ||
92f2584a | 1882 | /** |
85b3894f | 1883 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1884 | * @dev_priv: i915 private structure |
1885 | * @pipe: pipe PLL to enable | |
1886 | * | |
1887 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1888 | * drives the transcoder clock. | |
1889 | */ | |
85b3894f | 1890 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1891 | { |
3d13ef2e DL |
1892 | struct drm_device *dev = crtc->base.dev; |
1893 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1894 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1895 | |
87a875bb | 1896 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1897 | return; |
1898 | ||
3e369b76 | 1899 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1900 | return; |
ee7b9f93 | 1901 | |
74dd6928 | 1902 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1903 | pll->name, pll->active, pll->on, |
e2b78267 | 1904 | crtc->base.base.id); |
92f2584a | 1905 | |
cdbd2316 DV |
1906 | if (pll->active++) { |
1907 | WARN_ON(!pll->on); | |
e9d6944e | 1908 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1909 | return; |
1910 | } | |
f4a091c7 | 1911 | WARN_ON(pll->on); |
ee7b9f93 | 1912 | |
bd2bb1b9 PZ |
1913 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1914 | ||
46edb027 | 1915 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1916 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1917 | pll->on = true; |
92f2584a JB |
1918 | } |
1919 | ||
f6daaec2 | 1920 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1921 | { |
3d13ef2e DL |
1922 | struct drm_device *dev = crtc->base.dev; |
1923 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1924 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1925 | |
92f2584a | 1926 | /* PCH only available on ILK+ */ |
80aa9312 JB |
1927 | if (INTEL_INFO(dev)->gen < 5) |
1928 | return; | |
1929 | ||
eddfcbcd ML |
1930 | if (pll == NULL) |
1931 | return; | |
92f2584a | 1932 | |
eddfcbcd | 1933 | if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base))))) |
48da64a8 | 1934 | return; |
7a419866 | 1935 | |
46edb027 DV |
1936 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1937 | pll->name, pll->active, pll->on, | |
e2b78267 | 1938 | crtc->base.base.id); |
7a419866 | 1939 | |
48da64a8 | 1940 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1941 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1942 | return; |
1943 | } | |
1944 | ||
e9d6944e | 1945 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1946 | WARN_ON(!pll->on); |
cdbd2316 | 1947 | if (--pll->active) |
7a419866 | 1948 | return; |
ee7b9f93 | 1949 | |
46edb027 | 1950 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1951 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1952 | pll->on = false; |
bd2bb1b9 PZ |
1953 | |
1954 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1955 | } |
1956 | ||
b8a4f404 PZ |
1957 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1958 | enum pipe pipe) | |
040484af | 1959 | { |
23670b32 | 1960 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1961 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1962 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
f0f59a00 VS |
1963 | i915_reg_t reg; |
1964 | uint32_t val, pipeconf_val; | |
040484af JB |
1965 | |
1966 | /* PCH only available on ILK+ */ | |
55522f37 | 1967 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1968 | |
1969 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1970 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1971 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1972 | |
1973 | /* FDI must be feeding us bits for PCH ports */ | |
1974 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1975 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1976 | ||
23670b32 DV |
1977 | if (HAS_PCH_CPT(dev)) { |
1978 | /* Workaround: Set the timing override bit before enabling the | |
1979 | * pch transcoder. */ | |
1980 | reg = TRANS_CHICKEN2(pipe); | |
1981 | val = I915_READ(reg); | |
1982 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1983 | I915_WRITE(reg, val); | |
59c859d6 | 1984 | } |
23670b32 | 1985 | |
ab9412ba | 1986 | reg = PCH_TRANSCONF(pipe); |
040484af | 1987 | val = I915_READ(reg); |
5f7f726d | 1988 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1989 | |
1990 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1991 | /* | |
c5de7c6f VS |
1992 | * Make the BPC in transcoder be consistent with |
1993 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1994 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1995 | */ |
dfd07d72 | 1996 | val &= ~PIPECONF_BPC_MASK; |
c5de7c6f VS |
1997 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) |
1998 | val |= PIPECONF_8BPC; | |
1999 | else | |
2000 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 2001 | } |
5f7f726d PZ |
2002 | |
2003 | val &= ~TRANS_INTERLACE_MASK; | |
2004 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 2005 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 2006 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
2007 | val |= TRANS_LEGACY_INTERLACED_ILK; |
2008 | else | |
2009 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
2010 | else |
2011 | val |= TRANS_PROGRESSIVE; | |
2012 | ||
040484af JB |
2013 | I915_WRITE(reg, val | TRANS_ENABLE); |
2014 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 2015 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
2016 | } |
2017 | ||
8fb033d7 | 2018 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 2019 | enum transcoder cpu_transcoder) |
040484af | 2020 | { |
8fb033d7 | 2021 | u32 val, pipeconf_val; |
8fb033d7 PZ |
2022 | |
2023 | /* PCH only available on ILK+ */ | |
55522f37 | 2024 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 2025 | |
8fb033d7 | 2026 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 2027 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 2028 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 2029 | |
223a6fdf | 2030 | /* Workaround: set timing override bit. */ |
36c0d0cf | 2031 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 2032 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 2033 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 2034 | |
25f3ef11 | 2035 | val = TRANS_ENABLE; |
937bb610 | 2036 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 2037 | |
9a76b1c6 PZ |
2038 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
2039 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 2040 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
2041 | else |
2042 | val |= TRANS_PROGRESSIVE; | |
2043 | ||
ab9412ba DV |
2044 | I915_WRITE(LPT_TRANSCONF, val); |
2045 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 2046 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
2047 | } |
2048 | ||
b8a4f404 PZ |
2049 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
2050 | enum pipe pipe) | |
040484af | 2051 | { |
23670b32 | 2052 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 VS |
2053 | i915_reg_t reg; |
2054 | uint32_t val; | |
040484af JB |
2055 | |
2056 | /* FDI relies on the transcoder */ | |
2057 | assert_fdi_tx_disabled(dev_priv, pipe); | |
2058 | assert_fdi_rx_disabled(dev_priv, pipe); | |
2059 | ||
291906f1 JB |
2060 | /* Ports must be off as well */ |
2061 | assert_pch_ports_disabled(dev_priv, pipe); | |
2062 | ||
ab9412ba | 2063 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
2064 | val = I915_READ(reg); |
2065 | val &= ~TRANS_ENABLE; | |
2066 | I915_WRITE(reg, val); | |
2067 | /* wait for PCH transcoder off, transcoder state */ | |
2068 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 2069 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 2070 | |
c465613b | 2071 | if (HAS_PCH_CPT(dev)) { |
23670b32 DV |
2072 | /* Workaround: Clear the timing override chicken bit again. */ |
2073 | reg = TRANS_CHICKEN2(pipe); | |
2074 | val = I915_READ(reg); | |
2075 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2076 | I915_WRITE(reg, val); | |
2077 | } | |
040484af JB |
2078 | } |
2079 | ||
ab4d966c | 2080 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 2081 | { |
8fb033d7 PZ |
2082 | u32 val; |
2083 | ||
ab9412ba | 2084 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 2085 | val &= ~TRANS_ENABLE; |
ab9412ba | 2086 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 2087 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 2088 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 2089 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
2090 | |
2091 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 2092 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 2093 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 2094 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
2095 | } |
2096 | ||
b24e7179 | 2097 | /** |
309cfea8 | 2098 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2099 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2100 | * |
0372264a | 2101 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2102 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2103 | */ |
e1fdc473 | 2104 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2105 | { |
0372264a PZ |
2106 | struct drm_device *dev = crtc->base.dev; |
2107 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2108 | enum pipe pipe = crtc->pipe; | |
1a70a728 | 2109 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
1a240d4d | 2110 | enum pipe pch_transcoder; |
f0f59a00 | 2111 | i915_reg_t reg; |
b24e7179 JB |
2112 | u32 val; |
2113 | ||
9e2ee2dd VS |
2114 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
2115 | ||
58c6eaa2 | 2116 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2117 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2118 | assert_sprites_disabled(dev_priv, pipe); |
2119 | ||
681e5811 | 2120 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2121 | pch_transcoder = TRANSCODER_A; |
2122 | else | |
2123 | pch_transcoder = pipe; | |
2124 | ||
b24e7179 JB |
2125 | /* |
2126 | * A pipe without a PLL won't actually be able to drive bits from | |
2127 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2128 | * need the check. | |
2129 | */ | |
50360403 | 2130 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) |
a65347ba | 2131 | if (crtc->config->has_dsi_encoder) |
23538ef1 JN |
2132 | assert_dsi_pll_enabled(dev_priv); |
2133 | else | |
2134 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2135 | else { |
6e3c9717 | 2136 | if (crtc->config->has_pch_encoder) { |
040484af | 2137 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2138 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2139 | assert_fdi_tx_pll_enabled(dev_priv, |
2140 | (enum pipe) cpu_transcoder); | |
040484af JB |
2141 | } |
2142 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2143 | } | |
b24e7179 | 2144 | |
702e7a56 | 2145 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2146 | val = I915_READ(reg); |
7ad25d48 | 2147 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2148 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2149 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2150 | return; |
7ad25d48 | 2151 | } |
00d70b15 CW |
2152 | |
2153 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2154 | POSTING_READ(reg); |
b24e7179 JB |
2155 | } |
2156 | ||
2157 | /** | |
309cfea8 | 2158 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2159 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2160 | * |
575f7ab7 VS |
2161 | * Disable the pipe of @crtc, making sure that various hardware |
2162 | * specific requirements are met, if applicable, e.g. plane | |
2163 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2164 | * |
2165 | * Will wait until the pipe has shut down before returning. | |
2166 | */ | |
575f7ab7 | 2167 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2168 | { |
575f7ab7 | 2169 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2170 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2171 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 2172 | i915_reg_t reg; |
b24e7179 JB |
2173 | u32 val; |
2174 | ||
9e2ee2dd VS |
2175 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2176 | ||
b24e7179 JB |
2177 | /* |
2178 | * Make sure planes won't keep trying to pump pixels to us, | |
2179 | * or we might hang the display. | |
2180 | */ | |
2181 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2182 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2183 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2184 | |
702e7a56 | 2185 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2186 | val = I915_READ(reg); |
00d70b15 CW |
2187 | if ((val & PIPECONF_ENABLE) == 0) |
2188 | return; | |
2189 | ||
67adc644 VS |
2190 | /* |
2191 | * Double wide has implications for planes | |
2192 | * so best keep it disabled when not needed. | |
2193 | */ | |
6e3c9717 | 2194 | if (crtc->config->double_wide) |
67adc644 VS |
2195 | val &= ~PIPECONF_DOUBLE_WIDE; |
2196 | ||
2197 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2198 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2199 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2200 | val &= ~PIPECONF_ENABLE; |
2201 | ||
2202 | I915_WRITE(reg, val); | |
2203 | if ((val & PIPECONF_ENABLE) == 0) | |
2204 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2205 | } |
2206 | ||
693db184 CW |
2207 | static bool need_vtd_wa(struct drm_device *dev) |
2208 | { | |
2209 | #ifdef CONFIG_INTEL_IOMMU | |
2210 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2211 | return true; | |
2212 | #endif | |
2213 | return false; | |
2214 | } | |
2215 | ||
50470bb0 | 2216 | unsigned int |
6761dd31 | 2217 | intel_tile_height(struct drm_device *dev, uint32_t pixel_format, |
fe47ea0c | 2218 | uint64_t fb_format_modifier, unsigned int plane) |
a57ce0b2 | 2219 | { |
6761dd31 TU |
2220 | unsigned int tile_height; |
2221 | uint32_t pixel_bytes; | |
a57ce0b2 | 2222 | |
b5d0e9bf DL |
2223 | switch (fb_format_modifier) { |
2224 | case DRM_FORMAT_MOD_NONE: | |
2225 | tile_height = 1; | |
2226 | break; | |
2227 | case I915_FORMAT_MOD_X_TILED: | |
2228 | tile_height = IS_GEN2(dev) ? 16 : 8; | |
2229 | break; | |
2230 | case I915_FORMAT_MOD_Y_TILED: | |
2231 | tile_height = 32; | |
2232 | break; | |
2233 | case I915_FORMAT_MOD_Yf_TILED: | |
fe47ea0c | 2234 | pixel_bytes = drm_format_plane_cpp(pixel_format, plane); |
6761dd31 | 2235 | switch (pixel_bytes) { |
b5d0e9bf | 2236 | default: |
6761dd31 | 2237 | case 1: |
b5d0e9bf DL |
2238 | tile_height = 64; |
2239 | break; | |
6761dd31 TU |
2240 | case 2: |
2241 | case 4: | |
b5d0e9bf DL |
2242 | tile_height = 32; |
2243 | break; | |
6761dd31 | 2244 | case 8: |
b5d0e9bf DL |
2245 | tile_height = 16; |
2246 | break; | |
6761dd31 | 2247 | case 16: |
b5d0e9bf DL |
2248 | WARN_ONCE(1, |
2249 | "128-bit pixels are not supported for display!"); | |
2250 | tile_height = 16; | |
2251 | break; | |
2252 | } | |
2253 | break; | |
2254 | default: | |
2255 | MISSING_CASE(fb_format_modifier); | |
2256 | tile_height = 1; | |
2257 | break; | |
2258 | } | |
091df6cb | 2259 | |
6761dd31 TU |
2260 | return tile_height; |
2261 | } | |
2262 | ||
2263 | unsigned int | |
2264 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
2265 | uint32_t pixel_format, uint64_t fb_format_modifier) | |
2266 | { | |
2267 | return ALIGN(height, intel_tile_height(dev, pixel_format, | |
fe47ea0c | 2268 | fb_format_modifier, 0)); |
a57ce0b2 JB |
2269 | } |
2270 | ||
75c82a53 | 2271 | static void |
f64b98cd TU |
2272 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, |
2273 | const struct drm_plane_state *plane_state) | |
2274 | { | |
a6d09186 | 2275 | struct intel_rotation_info *info = &view->params.rotation_info; |
84fe03f7 | 2276 | unsigned int tile_height, tile_pitch; |
50470bb0 | 2277 | |
f64b98cd TU |
2278 | *view = i915_ggtt_view_normal; |
2279 | ||
50470bb0 | 2280 | if (!plane_state) |
75c82a53 | 2281 | return; |
50470bb0 | 2282 | |
121920fa | 2283 | if (!intel_rotation_90_or_270(plane_state->rotation)) |
75c82a53 | 2284 | return; |
50470bb0 | 2285 | |
9abc4648 | 2286 | *view = i915_ggtt_view_rotated; |
50470bb0 TU |
2287 | |
2288 | info->height = fb->height; | |
2289 | info->pixel_format = fb->pixel_format; | |
2290 | info->pitch = fb->pitches[0]; | |
89e3e142 | 2291 | info->uv_offset = fb->offsets[1]; |
50470bb0 TU |
2292 | info->fb_modifier = fb->modifier[0]; |
2293 | ||
84fe03f7 | 2294 | tile_height = intel_tile_height(fb->dev, fb->pixel_format, |
fe47ea0c | 2295 | fb->modifier[0], 0); |
84fe03f7 TU |
2296 | tile_pitch = PAGE_SIZE / tile_height; |
2297 | info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch); | |
2298 | info->height_pages = DIV_ROUND_UP(fb->height, tile_height); | |
2299 | info->size = info->width_pages * info->height_pages * PAGE_SIZE; | |
2300 | ||
89e3e142 TU |
2301 | if (info->pixel_format == DRM_FORMAT_NV12) { |
2302 | tile_height = intel_tile_height(fb->dev, fb->pixel_format, | |
2303 | fb->modifier[0], 1); | |
2304 | tile_pitch = PAGE_SIZE / tile_height; | |
2305 | info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch); | |
2306 | info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, | |
2307 | tile_height); | |
2308 | info->size_uv = info->width_pages_uv * info->height_pages_uv * | |
2309 | PAGE_SIZE; | |
2310 | } | |
f64b98cd TU |
2311 | } |
2312 | ||
4e9a86b6 VS |
2313 | static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv) |
2314 | { | |
2315 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2316 | return 256 * 1024; | |
985b8bb4 | 2317 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
666a4537 | 2318 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2319 | return 128 * 1024; |
2320 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2321 | return 4 * 1024; | |
2322 | else | |
44c5905e | 2323 | return 0; |
4e9a86b6 VS |
2324 | } |
2325 | ||
127bd2ac | 2326 | int |
850c4cdc TU |
2327 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2328 | struct drm_framebuffer *fb, | |
7580d774 | 2329 | const struct drm_plane_state *plane_state) |
6b95a207 | 2330 | { |
850c4cdc | 2331 | struct drm_device *dev = fb->dev; |
ce453d81 | 2332 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2333 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2334 | struct i915_ggtt_view view; |
6b95a207 KH |
2335 | u32 alignment; |
2336 | int ret; | |
2337 | ||
ebcdd39e MR |
2338 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2339 | ||
7b911adc TU |
2340 | switch (fb->modifier[0]) { |
2341 | case DRM_FORMAT_MOD_NONE: | |
4e9a86b6 | 2342 | alignment = intel_linear_alignment(dev_priv); |
6b95a207 | 2343 | break; |
7b911adc | 2344 | case I915_FORMAT_MOD_X_TILED: |
1fada4cc DL |
2345 | if (INTEL_INFO(dev)->gen >= 9) |
2346 | alignment = 256 * 1024; | |
2347 | else { | |
2348 | /* pin() will align the object as required by fence */ | |
2349 | alignment = 0; | |
2350 | } | |
6b95a207 | 2351 | break; |
7b911adc | 2352 | case I915_FORMAT_MOD_Y_TILED: |
1327b9a1 DL |
2353 | case I915_FORMAT_MOD_Yf_TILED: |
2354 | if (WARN_ONCE(INTEL_INFO(dev)->gen < 9, | |
2355 | "Y tiling bo slipped through, driver bug!\n")) | |
2356 | return -EINVAL; | |
2357 | alignment = 1 * 1024 * 1024; | |
2358 | break; | |
6b95a207 | 2359 | default: |
7b911adc TU |
2360 | MISSING_CASE(fb->modifier[0]); |
2361 | return -EINVAL; | |
6b95a207 KH |
2362 | } |
2363 | ||
75c82a53 | 2364 | intel_fill_fb_ggtt_view(&view, fb, plane_state); |
f64b98cd | 2365 | |
693db184 CW |
2366 | /* Note that the w/a also requires 64 PTE of padding following the |
2367 | * bo. We currently fill all unused PTE with the shadow page and so | |
2368 | * we should always have valid PTE following the scanout preventing | |
2369 | * the VT-d warning. | |
2370 | */ | |
2371 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2372 | alignment = 256 * 1024; | |
2373 | ||
d6dd6843 PZ |
2374 | /* |
2375 | * Global gtt pte registers are special registers which actually forward | |
2376 | * writes to a chunk of system memory. Which means that there is no risk | |
2377 | * that the register values disappear as soon as we call | |
2378 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2379 | * pin/unpin/fence and not more. | |
2380 | */ | |
2381 | intel_runtime_pm_get(dev_priv); | |
2382 | ||
7580d774 ML |
2383 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, |
2384 | &view); | |
48b956c5 | 2385 | if (ret) |
b26a6b35 | 2386 | goto err_pm; |
6b95a207 KH |
2387 | |
2388 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2389 | * fence, whereas 965+ only requires a fence if using | |
2390 | * framebuffer compression. For simplicity, we always install | |
2391 | * a fence as the cost is not that onerous. | |
2392 | */ | |
9807216f VK |
2393 | if (view.type == I915_GGTT_VIEW_NORMAL) { |
2394 | ret = i915_gem_object_get_fence(obj); | |
2395 | if (ret == -EDEADLK) { | |
2396 | /* | |
2397 | * -EDEADLK means there are no free fences | |
2398 | * no pending flips. | |
2399 | * | |
2400 | * This is propagated to atomic, but it uses | |
2401 | * -EDEADLK to force a locking recovery, so | |
2402 | * change the returned error to -EBUSY. | |
2403 | */ | |
2404 | ret = -EBUSY; | |
2405 | goto err_unpin; | |
2406 | } else if (ret) | |
2407 | goto err_unpin; | |
1690e1eb | 2408 | |
9807216f VK |
2409 | i915_gem_object_pin_fence(obj); |
2410 | } | |
6b95a207 | 2411 | |
d6dd6843 | 2412 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2413 | return 0; |
48b956c5 CW |
2414 | |
2415 | err_unpin: | |
f64b98cd | 2416 | i915_gem_object_unpin_from_display_plane(obj, &view); |
b26a6b35 | 2417 | err_pm: |
d6dd6843 | 2418 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2419 | return ret; |
6b95a207 KH |
2420 | } |
2421 | ||
82bc3b2d TU |
2422 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, |
2423 | const struct drm_plane_state *plane_state) | |
1690e1eb | 2424 | { |
82bc3b2d | 2425 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2426 | struct i915_ggtt_view view; |
82bc3b2d | 2427 | |
ebcdd39e MR |
2428 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2429 | ||
75c82a53 | 2430 | intel_fill_fb_ggtt_view(&view, fb, plane_state); |
f64b98cd | 2431 | |
9807216f VK |
2432 | if (view.type == I915_GGTT_VIEW_NORMAL) |
2433 | i915_gem_object_unpin_fence(obj); | |
2434 | ||
f64b98cd | 2435 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2436 | } |
2437 | ||
c2c75131 DV |
2438 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2439 | * is assumed to be a power-of-two. */ | |
4e9a86b6 VS |
2440 | unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv, |
2441 | int *x, int *y, | |
bc752862 CW |
2442 | unsigned int tiling_mode, |
2443 | unsigned int cpp, | |
2444 | unsigned int pitch) | |
c2c75131 | 2445 | { |
bc752862 CW |
2446 | if (tiling_mode != I915_TILING_NONE) { |
2447 | unsigned int tile_rows, tiles; | |
c2c75131 | 2448 | |
bc752862 CW |
2449 | tile_rows = *y / 8; |
2450 | *y %= 8; | |
c2c75131 | 2451 | |
bc752862 CW |
2452 | tiles = *x / (512/cpp); |
2453 | *x %= 512/cpp; | |
2454 | ||
2455 | return tile_rows * pitch * 8 + tiles * 4096; | |
2456 | } else { | |
4e9a86b6 | 2457 | unsigned int alignment = intel_linear_alignment(dev_priv) - 1; |
bc752862 CW |
2458 | unsigned int offset; |
2459 | ||
2460 | offset = *y * pitch + *x * cpp; | |
4e9a86b6 VS |
2461 | *y = (offset & alignment) / pitch; |
2462 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
2463 | return offset & ~alignment; | |
bc752862 | 2464 | } |
c2c75131 DV |
2465 | } |
2466 | ||
b35d63fa | 2467 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2468 | { |
2469 | switch (format) { | |
2470 | case DISPPLANE_8BPP: | |
2471 | return DRM_FORMAT_C8; | |
2472 | case DISPPLANE_BGRX555: | |
2473 | return DRM_FORMAT_XRGB1555; | |
2474 | case DISPPLANE_BGRX565: | |
2475 | return DRM_FORMAT_RGB565; | |
2476 | default: | |
2477 | case DISPPLANE_BGRX888: | |
2478 | return DRM_FORMAT_XRGB8888; | |
2479 | case DISPPLANE_RGBX888: | |
2480 | return DRM_FORMAT_XBGR8888; | |
2481 | case DISPPLANE_BGRX101010: | |
2482 | return DRM_FORMAT_XRGB2101010; | |
2483 | case DISPPLANE_RGBX101010: | |
2484 | return DRM_FORMAT_XBGR2101010; | |
2485 | } | |
2486 | } | |
2487 | ||
bc8d7dff DL |
2488 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2489 | { | |
2490 | switch (format) { | |
2491 | case PLANE_CTL_FORMAT_RGB_565: | |
2492 | return DRM_FORMAT_RGB565; | |
2493 | default: | |
2494 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2495 | if (rgb_order) { | |
2496 | if (alpha) | |
2497 | return DRM_FORMAT_ABGR8888; | |
2498 | else | |
2499 | return DRM_FORMAT_XBGR8888; | |
2500 | } else { | |
2501 | if (alpha) | |
2502 | return DRM_FORMAT_ARGB8888; | |
2503 | else | |
2504 | return DRM_FORMAT_XRGB8888; | |
2505 | } | |
2506 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2507 | if (rgb_order) | |
2508 | return DRM_FORMAT_XBGR2101010; | |
2509 | else | |
2510 | return DRM_FORMAT_XRGB2101010; | |
2511 | } | |
2512 | } | |
2513 | ||
5724dbd1 | 2514 | static bool |
f6936e29 DV |
2515 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2516 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2517 | { |
2518 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2519 | struct drm_i915_private *dev_priv = to_i915(dev); |
46f297fb JB |
2520 | struct drm_i915_gem_object *obj = NULL; |
2521 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2522 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2523 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2524 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2525 | PAGE_SIZE); | |
2526 | ||
2527 | size_aligned -= base_aligned; | |
46f297fb | 2528 | |
ff2652ea CW |
2529 | if (plane_config->size == 0) |
2530 | return false; | |
2531 | ||
3badb49f PZ |
2532 | /* If the FB is too big, just don't use it since fbdev is not very |
2533 | * important and we should probably use that space with FBC or other | |
2534 | * features. */ | |
2535 | if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size) | |
2536 | return false; | |
2537 | ||
f37b5c2b DV |
2538 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2539 | base_aligned, | |
2540 | base_aligned, | |
2541 | size_aligned); | |
46f297fb | 2542 | if (!obj) |
484b41dd | 2543 | return false; |
46f297fb | 2544 | |
49af449b DL |
2545 | obj->tiling_mode = plane_config->tiling; |
2546 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2547 | obj->stride = fb->pitches[0]; |
46f297fb | 2548 | |
6bf129df DL |
2549 | mode_cmd.pixel_format = fb->pixel_format; |
2550 | mode_cmd.width = fb->width; | |
2551 | mode_cmd.height = fb->height; | |
2552 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2553 | mode_cmd.modifier[0] = fb->modifier[0]; |
2554 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb JB |
2555 | |
2556 | mutex_lock(&dev->struct_mutex); | |
6bf129df | 2557 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2558 | &mode_cmd, obj)) { |
46f297fb JB |
2559 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2560 | goto out_unref_obj; | |
2561 | } | |
46f297fb | 2562 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2563 | |
f6936e29 | 2564 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2565 | return true; |
46f297fb JB |
2566 | |
2567 | out_unref_obj: | |
2568 | drm_gem_object_unreference(&obj->base); | |
2569 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2570 | return false; |
2571 | } | |
2572 | ||
afd65eb4 MR |
2573 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2574 | static void | |
2575 | update_state_fb(struct drm_plane *plane) | |
2576 | { | |
2577 | if (plane->fb == plane->state->fb) | |
2578 | return; | |
2579 | ||
2580 | if (plane->state->fb) | |
2581 | drm_framebuffer_unreference(plane->state->fb); | |
2582 | plane->state->fb = plane->fb; | |
2583 | if (plane->state->fb) | |
2584 | drm_framebuffer_reference(plane->state->fb); | |
2585 | } | |
2586 | ||
5724dbd1 | 2587 | static void |
f6936e29 DV |
2588 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2589 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2590 | { |
2591 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2592 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2593 | struct drm_crtc *c; |
2594 | struct intel_crtc *i; | |
2ff8fde1 | 2595 | struct drm_i915_gem_object *obj; |
88595ac9 | 2596 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2597 | struct drm_plane_state *plane_state = primary->state; |
88595ac9 | 2598 | struct drm_framebuffer *fb; |
484b41dd | 2599 | |
2d14030b | 2600 | if (!plane_config->fb) |
484b41dd JB |
2601 | return; |
2602 | ||
f6936e29 | 2603 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2604 | fb = &plane_config->fb->base; |
2605 | goto valid_fb; | |
f55548b5 | 2606 | } |
484b41dd | 2607 | |
2d14030b | 2608 | kfree(plane_config->fb); |
484b41dd JB |
2609 | |
2610 | /* | |
2611 | * Failed to alloc the obj, check to see if we should share | |
2612 | * an fb with another CRTC instead | |
2613 | */ | |
70e1e0ec | 2614 | for_each_crtc(dev, c) { |
484b41dd JB |
2615 | i = to_intel_crtc(c); |
2616 | ||
2617 | if (c == &intel_crtc->base) | |
2618 | continue; | |
2619 | ||
2ff8fde1 MR |
2620 | if (!i->active) |
2621 | continue; | |
2622 | ||
88595ac9 DV |
2623 | fb = c->primary->fb; |
2624 | if (!fb) | |
484b41dd JB |
2625 | continue; |
2626 | ||
88595ac9 | 2627 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2628 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2629 | drm_framebuffer_reference(fb); |
2630 | goto valid_fb; | |
484b41dd JB |
2631 | } |
2632 | } | |
88595ac9 DV |
2633 | |
2634 | return; | |
2635 | ||
2636 | valid_fb: | |
f44e2659 VS |
2637 | plane_state->src_x = 0; |
2638 | plane_state->src_y = 0; | |
be5651f2 ML |
2639 | plane_state->src_w = fb->width << 16; |
2640 | plane_state->src_h = fb->height << 16; | |
2641 | ||
f44e2659 VS |
2642 | plane_state->crtc_x = 0; |
2643 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2644 | plane_state->crtc_w = fb->width; |
2645 | plane_state->crtc_h = fb->height; | |
2646 | ||
88595ac9 DV |
2647 | obj = intel_fb_obj(fb); |
2648 | if (obj->tiling_mode != I915_TILING_NONE) | |
2649 | dev_priv->preserve_bios_swizzle = true; | |
2650 | ||
be5651f2 ML |
2651 | drm_framebuffer_reference(fb); |
2652 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2653 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2654 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
a9ff8714 | 2655 | obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit; |
46f297fb JB |
2656 | } |
2657 | ||
29b9bde6 DV |
2658 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2659 | struct drm_framebuffer *fb, | |
2660 | int x, int y) | |
81255565 JB |
2661 | { |
2662 | struct drm_device *dev = crtc->dev; | |
2663 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2664 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
2665 | struct drm_plane *primary = crtc->primary; |
2666 | bool visible = to_intel_plane_state(primary->state)->visible; | |
c9ba6fad | 2667 | struct drm_i915_gem_object *obj; |
81255565 | 2668 | int plane = intel_crtc->plane; |
e506a0c6 | 2669 | unsigned long linear_offset; |
81255565 | 2670 | u32 dspcntr; |
f0f59a00 | 2671 | i915_reg_t reg = DSPCNTR(plane); |
48404c1e | 2672 | int pixel_size; |
f45651ba | 2673 | |
b70709a6 | 2674 | if (!visible || !fb) { |
fdd508a6 VS |
2675 | I915_WRITE(reg, 0); |
2676 | if (INTEL_INFO(dev)->gen >= 4) | |
2677 | I915_WRITE(DSPSURF(plane), 0); | |
2678 | else | |
2679 | I915_WRITE(DSPADDR(plane), 0); | |
2680 | POSTING_READ(reg); | |
2681 | return; | |
2682 | } | |
2683 | ||
c9ba6fad VS |
2684 | obj = intel_fb_obj(fb); |
2685 | if (WARN_ON(obj == NULL)) | |
2686 | return; | |
2687 | ||
2688 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2689 | ||
f45651ba VS |
2690 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2691 | ||
fdd508a6 | 2692 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2693 | |
2694 | if (INTEL_INFO(dev)->gen < 4) { | |
2695 | if (intel_crtc->pipe == PIPE_B) | |
2696 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2697 | ||
2698 | /* pipesrc and dspsize control the size that is scaled from, | |
2699 | * which should always be the user's requested size. | |
2700 | */ | |
2701 | I915_WRITE(DSPSIZE(plane), | |
6e3c9717 ACO |
2702 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2703 | (intel_crtc->config->pipe_src_w - 1)); | |
f45651ba | 2704 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2705 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2706 | I915_WRITE(PRIMSIZE(plane), | |
6e3c9717 ACO |
2707 | ((intel_crtc->config->pipe_src_h - 1) << 16) | |
2708 | (intel_crtc->config->pipe_src_w - 1)); | |
c14b0485 VS |
2709 | I915_WRITE(PRIMPOS(plane), 0); |
2710 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2711 | } |
81255565 | 2712 | |
57779d06 VS |
2713 | switch (fb->pixel_format) { |
2714 | case DRM_FORMAT_C8: | |
81255565 JB |
2715 | dspcntr |= DISPPLANE_8BPP; |
2716 | break; | |
57779d06 | 2717 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2718 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2719 | break; |
57779d06 VS |
2720 | case DRM_FORMAT_RGB565: |
2721 | dspcntr |= DISPPLANE_BGRX565; | |
2722 | break; | |
2723 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2724 | dspcntr |= DISPPLANE_BGRX888; |
2725 | break; | |
2726 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2727 | dspcntr |= DISPPLANE_RGBX888; |
2728 | break; | |
2729 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2730 | dspcntr |= DISPPLANE_BGRX101010; |
2731 | break; | |
2732 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2733 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
2734 | break; |
2735 | default: | |
baba133a | 2736 | BUG(); |
81255565 | 2737 | } |
57779d06 | 2738 | |
f45651ba VS |
2739 | if (INTEL_INFO(dev)->gen >= 4 && |
2740 | obj->tiling_mode != I915_TILING_NONE) | |
2741 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2742 | |
de1aa629 VS |
2743 | if (IS_G4X(dev)) |
2744 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2745 | ||
b9897127 | 2746 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
81255565 | 2747 | |
c2c75131 DV |
2748 | if (INTEL_INFO(dev)->gen >= 4) { |
2749 | intel_crtc->dspaddr_offset = | |
4e9a86b6 VS |
2750 | intel_gen4_compute_page_offset(dev_priv, |
2751 | &x, &y, obj->tiling_mode, | |
b9897127 | 2752 | pixel_size, |
bc752862 | 2753 | fb->pitches[0]); |
c2c75131 DV |
2754 | linear_offset -= intel_crtc->dspaddr_offset; |
2755 | } else { | |
e506a0c6 | 2756 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2757 | } |
e506a0c6 | 2758 | |
8e7d688b | 2759 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2760 | dspcntr |= DISPPLANE_ROTATE_180; |
2761 | ||
6e3c9717 ACO |
2762 | x += (intel_crtc->config->pipe_src_w - 1); |
2763 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2764 | |
2765 | /* Finding the last pixel of the last line of the display | |
2766 | data and adding to linear_offset*/ | |
2767 | linear_offset += | |
6e3c9717 ACO |
2768 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2769 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2770 | } |
2771 | ||
2db3366b PZ |
2772 | intel_crtc->adjusted_x = x; |
2773 | intel_crtc->adjusted_y = y; | |
2774 | ||
48404c1e SJ |
2775 | I915_WRITE(reg, dspcntr); |
2776 | ||
01f2c773 | 2777 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2778 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2779 | I915_WRITE(DSPSURF(plane), |
2780 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2781 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2782 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2783 | } else |
f343c5f6 | 2784 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2785 | POSTING_READ(reg); |
17638cd6 JB |
2786 | } |
2787 | ||
29b9bde6 DV |
2788 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2789 | struct drm_framebuffer *fb, | |
2790 | int x, int y) | |
17638cd6 JB |
2791 | { |
2792 | struct drm_device *dev = crtc->dev; | |
2793 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2794 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
2795 | struct drm_plane *primary = crtc->primary; |
2796 | bool visible = to_intel_plane_state(primary->state)->visible; | |
c9ba6fad | 2797 | struct drm_i915_gem_object *obj; |
17638cd6 | 2798 | int plane = intel_crtc->plane; |
e506a0c6 | 2799 | unsigned long linear_offset; |
17638cd6 | 2800 | u32 dspcntr; |
f0f59a00 | 2801 | i915_reg_t reg = DSPCNTR(plane); |
48404c1e | 2802 | int pixel_size; |
f45651ba | 2803 | |
b70709a6 | 2804 | if (!visible || !fb) { |
fdd508a6 VS |
2805 | I915_WRITE(reg, 0); |
2806 | I915_WRITE(DSPSURF(plane), 0); | |
2807 | POSTING_READ(reg); | |
2808 | return; | |
2809 | } | |
2810 | ||
c9ba6fad VS |
2811 | obj = intel_fb_obj(fb); |
2812 | if (WARN_ON(obj == NULL)) | |
2813 | return; | |
2814 | ||
2815 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2816 | ||
f45651ba VS |
2817 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2818 | ||
fdd508a6 | 2819 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2820 | |
2821 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2822 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2823 | |
57779d06 VS |
2824 | switch (fb->pixel_format) { |
2825 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2826 | dspcntr |= DISPPLANE_8BPP; |
2827 | break; | |
57779d06 VS |
2828 | case DRM_FORMAT_RGB565: |
2829 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2830 | break; |
57779d06 | 2831 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
2832 | dspcntr |= DISPPLANE_BGRX888; |
2833 | break; | |
2834 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2835 | dspcntr |= DISPPLANE_RGBX888; |
2836 | break; | |
2837 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2838 | dspcntr |= DISPPLANE_BGRX101010; |
2839 | break; | |
2840 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2841 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
2842 | break; |
2843 | default: | |
baba133a | 2844 | BUG(); |
17638cd6 JB |
2845 | } |
2846 | ||
2847 | if (obj->tiling_mode != I915_TILING_NONE) | |
2848 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2849 | |
f45651ba | 2850 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2851 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2852 | |
b9897127 | 2853 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
c2c75131 | 2854 | intel_crtc->dspaddr_offset = |
4e9a86b6 VS |
2855 | intel_gen4_compute_page_offset(dev_priv, |
2856 | &x, &y, obj->tiling_mode, | |
b9897127 | 2857 | pixel_size, |
bc752862 | 2858 | fb->pitches[0]); |
c2c75131 | 2859 | linear_offset -= intel_crtc->dspaddr_offset; |
8e7d688b | 2860 | if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2861 | dspcntr |= DISPPLANE_ROTATE_180; |
2862 | ||
2863 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
6e3c9717 ACO |
2864 | x += (intel_crtc->config->pipe_src_w - 1); |
2865 | y += (intel_crtc->config->pipe_src_h - 1); | |
48404c1e SJ |
2866 | |
2867 | /* Finding the last pixel of the last line of the display | |
2868 | data and adding to linear_offset*/ | |
2869 | linear_offset += | |
6e3c9717 ACO |
2870 | (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] + |
2871 | (intel_crtc->config->pipe_src_w - 1) * pixel_size; | |
48404c1e SJ |
2872 | } |
2873 | } | |
2874 | ||
2db3366b PZ |
2875 | intel_crtc->adjusted_x = x; |
2876 | intel_crtc->adjusted_y = y; | |
2877 | ||
48404c1e | 2878 | I915_WRITE(reg, dspcntr); |
17638cd6 | 2879 | |
01f2c773 | 2880 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2881 | I915_WRITE(DSPSURF(plane), |
2882 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2883 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2884 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2885 | } else { | |
2886 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2887 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2888 | } | |
17638cd6 | 2889 | POSTING_READ(reg); |
17638cd6 JB |
2890 | } |
2891 | ||
b321803d DL |
2892 | u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier, |
2893 | uint32_t pixel_format) | |
2894 | { | |
2895 | u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8; | |
2896 | ||
2897 | /* | |
2898 | * The stride is either expressed as a multiple of 64 bytes | |
2899 | * chunks for linear buffers or in number of tiles for tiled | |
2900 | * buffers. | |
2901 | */ | |
2902 | switch (fb_modifier) { | |
2903 | case DRM_FORMAT_MOD_NONE: | |
2904 | return 64; | |
2905 | case I915_FORMAT_MOD_X_TILED: | |
2906 | if (INTEL_INFO(dev)->gen == 2) | |
2907 | return 128; | |
2908 | return 512; | |
2909 | case I915_FORMAT_MOD_Y_TILED: | |
2910 | /* No need to check for old gens and Y tiling since this is | |
2911 | * about the display engine and those will be blocked before | |
2912 | * we get here. | |
2913 | */ | |
2914 | return 128; | |
2915 | case I915_FORMAT_MOD_Yf_TILED: | |
2916 | if (bits_per_pixel == 8) | |
2917 | return 64; | |
2918 | else | |
2919 | return 128; | |
2920 | default: | |
2921 | MISSING_CASE(fb_modifier); | |
2922 | return 64; | |
2923 | } | |
2924 | } | |
2925 | ||
44eb0cb9 MK |
2926 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, |
2927 | struct drm_i915_gem_object *obj, | |
2928 | unsigned int plane) | |
121920fa | 2929 | { |
ce7f1728 | 2930 | struct i915_ggtt_view view; |
dedf278c | 2931 | struct i915_vma *vma; |
44eb0cb9 | 2932 | u64 offset; |
121920fa | 2933 | |
ce7f1728 DV |
2934 | intel_fill_fb_ggtt_view(&view, intel_plane->base.fb, |
2935 | intel_plane->base.state); | |
121920fa | 2936 | |
ce7f1728 | 2937 | vma = i915_gem_obj_to_ggtt_view(obj, &view); |
dedf278c | 2938 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", |
ce7f1728 | 2939 | view.type)) |
dedf278c TU |
2940 | return -1; |
2941 | ||
44eb0cb9 | 2942 | offset = vma->node.start; |
dedf278c TU |
2943 | |
2944 | if (plane == 1) { | |
a6d09186 | 2945 | offset += vma->ggtt_view.params.rotation_info.uv_start_page * |
dedf278c TU |
2946 | PAGE_SIZE; |
2947 | } | |
2948 | ||
44eb0cb9 MK |
2949 | WARN_ON(upper_32_bits(offset)); |
2950 | ||
2951 | return lower_32_bits(offset); | |
121920fa TU |
2952 | } |
2953 | ||
e435d6e5 ML |
2954 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
2955 | { | |
2956 | struct drm_device *dev = intel_crtc->base.dev; | |
2957 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2958 | ||
2959 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
2960 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
2961 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
2962 | } |
2963 | ||
a1b2278e CK |
2964 | /* |
2965 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2966 | */ | |
0583236e | 2967 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 2968 | { |
a1b2278e CK |
2969 | struct intel_crtc_scaler_state *scaler_state; |
2970 | int i; | |
2971 | ||
a1b2278e CK |
2972 | scaler_state = &intel_crtc->config->scaler_state; |
2973 | ||
2974 | /* loop through and disable scalers that aren't in use */ | |
2975 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
2976 | if (!scaler_state->scalers[i].in_use) |
2977 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
2978 | } |
2979 | } | |
2980 | ||
6156a456 | 2981 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 2982 | { |
6156a456 | 2983 | switch (pixel_format) { |
d161cf7a | 2984 | case DRM_FORMAT_C8: |
c34ce3d1 | 2985 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 2986 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 2987 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 2988 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 2989 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 2990 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 2991 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
2992 | /* |
2993 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
2994 | * to be already pre-multiplied. We need to add a knob (or a different | |
2995 | * DRM_FORMAT) for user-space to configure that. | |
2996 | */ | |
f75fb42a | 2997 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 2998 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 2999 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 3000 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 3001 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 3002 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 3003 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 3004 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 3005 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 3006 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 3007 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 3008 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 3009 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 3010 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 3011 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 3012 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 3013 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 3014 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 3015 | default: |
4249eeef | 3016 | MISSING_CASE(pixel_format); |
70d21f0e | 3017 | } |
8cfcba41 | 3018 | |
c34ce3d1 | 3019 | return 0; |
6156a456 | 3020 | } |
70d21f0e | 3021 | |
6156a456 CK |
3022 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
3023 | { | |
6156a456 | 3024 | switch (fb_modifier) { |
30af77c4 | 3025 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 3026 | break; |
30af77c4 | 3027 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 3028 | return PLANE_CTL_TILED_X; |
b321803d | 3029 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3030 | return PLANE_CTL_TILED_Y; |
b321803d | 3031 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3032 | return PLANE_CTL_TILED_YF; |
70d21f0e | 3033 | default: |
6156a456 | 3034 | MISSING_CASE(fb_modifier); |
70d21f0e | 3035 | } |
8cfcba41 | 3036 | |
c34ce3d1 | 3037 | return 0; |
6156a456 | 3038 | } |
70d21f0e | 3039 | |
6156a456 CK |
3040 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
3041 | { | |
3b7a5119 | 3042 | switch (rotation) { |
6156a456 CK |
3043 | case BIT(DRM_ROTATE_0): |
3044 | break; | |
1e8df167 SJ |
3045 | /* |
3046 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
3047 | * while i915 HW rotation is clockwise, thats why this swapping. | |
3048 | */ | |
3b7a5119 | 3049 | case BIT(DRM_ROTATE_90): |
1e8df167 | 3050 | return PLANE_CTL_ROTATE_270; |
3b7a5119 | 3051 | case BIT(DRM_ROTATE_180): |
c34ce3d1 | 3052 | return PLANE_CTL_ROTATE_180; |
3b7a5119 | 3053 | case BIT(DRM_ROTATE_270): |
1e8df167 | 3054 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3055 | default: |
3056 | MISSING_CASE(rotation); | |
3057 | } | |
3058 | ||
c34ce3d1 | 3059 | return 0; |
6156a456 CK |
3060 | } |
3061 | ||
3062 | static void skylake_update_primary_plane(struct drm_crtc *crtc, | |
3063 | struct drm_framebuffer *fb, | |
3064 | int x, int y) | |
3065 | { | |
3066 | struct drm_device *dev = crtc->dev; | |
3067 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3068 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b70709a6 ML |
3069 | struct drm_plane *plane = crtc->primary; |
3070 | bool visible = to_intel_plane_state(plane->state)->visible; | |
6156a456 CK |
3071 | struct drm_i915_gem_object *obj; |
3072 | int pipe = intel_crtc->pipe; | |
3073 | u32 plane_ctl, stride_div, stride; | |
3074 | u32 tile_height, plane_offset, plane_size; | |
3075 | unsigned int rotation; | |
3076 | int x_offset, y_offset; | |
44eb0cb9 | 3077 | u32 surf_addr; |
6156a456 CK |
3078 | struct intel_crtc_state *crtc_state = intel_crtc->config; |
3079 | struct intel_plane_state *plane_state; | |
3080 | int src_x = 0, src_y = 0, src_w = 0, src_h = 0; | |
3081 | int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0; | |
3082 | int scaler_id = -1; | |
3083 | ||
6156a456 CK |
3084 | plane_state = to_intel_plane_state(plane->state); |
3085 | ||
b70709a6 | 3086 | if (!visible || !fb) { |
6156a456 CK |
3087 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3088 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3089 | POSTING_READ(PLANE_CTL(pipe, 0)); | |
3090 | return; | |
3b7a5119 | 3091 | } |
70d21f0e | 3092 | |
6156a456 CK |
3093 | plane_ctl = PLANE_CTL_ENABLE | |
3094 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3095 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3096 | ||
3097 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3098 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3099 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
3100 | ||
3101 | rotation = plane->state->rotation; | |
3102 | plane_ctl |= skl_plane_ctl_rotation(rotation); | |
3103 | ||
b321803d DL |
3104 | obj = intel_fb_obj(fb); |
3105 | stride_div = intel_fb_stride_alignment(dev, fb->modifier[0], | |
3106 | fb->pixel_format); | |
dedf278c | 3107 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); |
3b7a5119 | 3108 | |
a42e5a23 PZ |
3109 | WARN_ON(drm_rect_width(&plane_state->src) == 0); |
3110 | ||
3111 | scaler_id = plane_state->scaler_id; | |
3112 | src_x = plane_state->src.x1 >> 16; | |
3113 | src_y = plane_state->src.y1 >> 16; | |
3114 | src_w = drm_rect_width(&plane_state->src) >> 16; | |
3115 | src_h = drm_rect_height(&plane_state->src) >> 16; | |
3116 | dst_x = plane_state->dst.x1; | |
3117 | dst_y = plane_state->dst.y1; | |
3118 | dst_w = drm_rect_width(&plane_state->dst); | |
3119 | dst_h = drm_rect_height(&plane_state->dst); | |
3120 | ||
3121 | WARN_ON(x != src_x || y != src_y); | |
6156a456 | 3122 | |
3b7a5119 SJ |
3123 | if (intel_rotation_90_or_270(rotation)) { |
3124 | /* stride = Surface height in tiles */ | |
2614f17d | 3125 | tile_height = intel_tile_height(dev, fb->pixel_format, |
fe47ea0c | 3126 | fb->modifier[0], 0); |
3b7a5119 | 3127 | stride = DIV_ROUND_UP(fb->height, tile_height); |
6156a456 | 3128 | x_offset = stride * tile_height - y - src_h; |
3b7a5119 | 3129 | y_offset = x; |
6156a456 | 3130 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3131 | } else { |
3132 | stride = fb->pitches[0] / stride_div; | |
3133 | x_offset = x; | |
3134 | y_offset = y; | |
6156a456 | 3135 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3136 | } |
3137 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3138 | |
2db3366b PZ |
3139 | intel_crtc->adjusted_x = x_offset; |
3140 | intel_crtc->adjusted_y = y_offset; | |
3141 | ||
70d21f0e | 3142 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3143 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3144 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3145 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3146 | |
3147 | if (scaler_id >= 0) { | |
3148 | uint32_t ps_ctrl = 0; | |
3149 | ||
3150 | WARN_ON(!dst_w || !dst_h); | |
3151 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3152 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3153 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3154 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3155 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3156 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3157 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3158 | } else { | |
3159 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3160 | } | |
3161 | ||
121920fa | 3162 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3163 | |
3164 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3165 | } | |
3166 | ||
17638cd6 JB |
3167 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3168 | static int | |
3169 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3170 | int x, int y, enum mode_set_atomic state) | |
3171 | { | |
3172 | struct drm_device *dev = crtc->dev; | |
3173 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 3174 | |
0e631adc PZ |
3175 | if (dev_priv->fbc.deactivate) |
3176 | dev_priv->fbc.deactivate(dev_priv); | |
81255565 | 3177 | |
29b9bde6 DV |
3178 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3179 | ||
3180 | return 0; | |
81255565 JB |
3181 | } |
3182 | ||
7514747d | 3183 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 3184 | { |
96a02917 VS |
3185 | struct drm_crtc *crtc; |
3186 | ||
70e1e0ec | 3187 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3188 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3189 | enum plane plane = intel_crtc->plane; | |
3190 | ||
3191 | intel_prepare_page_flip(dev, plane); | |
3192 | intel_finish_page_flip_plane(dev, plane); | |
3193 | } | |
7514747d VS |
3194 | } |
3195 | ||
3196 | static void intel_update_primary_planes(struct drm_device *dev) | |
3197 | { | |
7514747d | 3198 | struct drm_crtc *crtc; |
96a02917 | 3199 | |
70e1e0ec | 3200 | for_each_crtc(dev, crtc) { |
11c22da6 ML |
3201 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
3202 | struct intel_plane_state *plane_state; | |
96a02917 | 3203 | |
11c22da6 | 3204 | drm_modeset_lock_crtc(crtc, &plane->base); |
11c22da6 ML |
3205 | plane_state = to_intel_plane_state(plane->base.state); |
3206 | ||
f029ee82 | 3207 | if (crtc->state->active && plane_state->base.fb) |
11c22da6 ML |
3208 | plane->commit_plane(&plane->base, plane_state); |
3209 | ||
3210 | drm_modeset_unlock_crtc(crtc); | |
96a02917 VS |
3211 | } |
3212 | } | |
3213 | ||
7514747d VS |
3214 | void intel_prepare_reset(struct drm_device *dev) |
3215 | { | |
3216 | /* no reset support for gen2 */ | |
3217 | if (IS_GEN2(dev)) | |
3218 | return; | |
3219 | ||
3220 | /* reset doesn't touch the display */ | |
3221 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3222 | return; | |
3223 | ||
3224 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3225 | /* |
3226 | * Disabling the crtcs gracefully seems nicer. Also the | |
3227 | * g33 docs say we should at least disable all the planes. | |
3228 | */ | |
6b72d486 | 3229 | intel_display_suspend(dev); |
7514747d VS |
3230 | } |
3231 | ||
3232 | void intel_finish_reset(struct drm_device *dev) | |
3233 | { | |
3234 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3235 | ||
3236 | /* | |
3237 | * Flips in the rings will be nuked by the reset, | |
3238 | * so complete all pending flips so that user space | |
3239 | * will get its events and not get stuck. | |
3240 | */ | |
3241 | intel_complete_page_flips(dev); | |
3242 | ||
3243 | /* no reset support for gen2 */ | |
3244 | if (IS_GEN2(dev)) | |
3245 | return; | |
3246 | ||
3247 | /* reset doesn't touch the display */ | |
3248 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3249 | /* | |
3250 | * Flips in the rings have been nuked by the reset, | |
3251 | * so update the base address of all primary | |
3252 | * planes to the the last fb to make sure we're | |
3253 | * showing the correct fb after a reset. | |
11c22da6 ML |
3254 | * |
3255 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3256 | * CS-based flips (which might get lost in gpu resets) any more. | |
7514747d VS |
3257 | */ |
3258 | intel_update_primary_planes(dev); | |
3259 | return; | |
3260 | } | |
3261 | ||
3262 | /* | |
3263 | * The display has been reset as well, | |
3264 | * so need a full re-initialization. | |
3265 | */ | |
3266 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3267 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3268 | ||
3269 | intel_modeset_init_hw(dev); | |
3270 | ||
3271 | spin_lock_irq(&dev_priv->irq_lock); | |
3272 | if (dev_priv->display.hpd_irq_setup) | |
3273 | dev_priv->display.hpd_irq_setup(dev); | |
3274 | spin_unlock_irq(&dev_priv->irq_lock); | |
3275 | ||
043e9bda | 3276 | intel_display_resume(dev); |
7514747d VS |
3277 | |
3278 | intel_hpd_init(dev_priv); | |
3279 | ||
3280 | drm_modeset_unlock_all(dev); | |
3281 | } | |
3282 | ||
7d5e3799 CW |
3283 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3284 | { | |
3285 | struct drm_device *dev = crtc->dev; | |
3286 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3287 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3288 | bool pending; |
3289 | ||
3290 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3291 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3292 | return false; | |
3293 | ||
5e2d7afc | 3294 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3295 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3296 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3297 | |
3298 | return pending; | |
3299 | } | |
3300 | ||
bfd16b2a ML |
3301 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3302 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 GP |
3303 | { |
3304 | struct drm_device *dev = crtc->base.dev; | |
3305 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bfd16b2a ML |
3306 | struct intel_crtc_state *pipe_config = |
3307 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3308 | |
bfd16b2a ML |
3309 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3310 | crtc->base.mode = crtc->base.state->mode; | |
3311 | ||
3312 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3313 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3314 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 | 3315 | |
44522d85 ML |
3316 | if (HAS_DDI(dev)) |
3317 | intel_set_pipe_csc(&crtc->base); | |
3318 | ||
e30e8f75 GP |
3319 | /* |
3320 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3321 | * that in compute_mode_changes we check the native mode (not the pfit | |
3322 | * mode) to see if we can flip rather than do a full mode set. In the | |
3323 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3324 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3325 | * sized surface. | |
e30e8f75 GP |
3326 | */ |
3327 | ||
e30e8f75 | 3328 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3329 | ((pipe_config->pipe_src_w - 1) << 16) | |
3330 | (pipe_config->pipe_src_h - 1)); | |
3331 | ||
3332 | /* on skylake this is done by detaching scalers */ | |
3333 | if (INTEL_INFO(dev)->gen >= 9) { | |
3334 | skl_detach_scalers(crtc); | |
3335 | ||
3336 | if (pipe_config->pch_pfit.enabled) | |
3337 | skylake_pfit_enable(crtc); | |
3338 | } else if (HAS_PCH_SPLIT(dev)) { | |
3339 | if (pipe_config->pch_pfit.enabled) | |
3340 | ironlake_pfit_enable(crtc); | |
3341 | else if (old_crtc_state->pch_pfit.enabled) | |
3342 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3343 | } |
e30e8f75 GP |
3344 | } |
3345 | ||
5e84e1a4 ZW |
3346 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3347 | { | |
3348 | struct drm_device *dev = crtc->dev; | |
3349 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3350 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3351 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3352 | i915_reg_t reg; |
3353 | u32 temp; | |
5e84e1a4 ZW |
3354 | |
3355 | /* enable normal train */ | |
3356 | reg = FDI_TX_CTL(pipe); | |
3357 | temp = I915_READ(reg); | |
61e499bf | 3358 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3359 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3360 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3361 | } else { |
3362 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3363 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3364 | } |
5e84e1a4 ZW |
3365 | I915_WRITE(reg, temp); |
3366 | ||
3367 | reg = FDI_RX_CTL(pipe); | |
3368 | temp = I915_READ(reg); | |
3369 | if (HAS_PCH_CPT(dev)) { | |
3370 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3371 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3372 | } else { | |
3373 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3374 | temp |= FDI_LINK_TRAIN_NONE; | |
3375 | } | |
3376 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3377 | ||
3378 | /* wait one idle pattern time */ | |
3379 | POSTING_READ(reg); | |
3380 | udelay(1000); | |
357555c0 JB |
3381 | |
3382 | /* IVB wants error correction enabled */ | |
3383 | if (IS_IVYBRIDGE(dev)) | |
3384 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3385 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3386 | } |
3387 | ||
8db9d77b ZW |
3388 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3389 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3390 | { | |
3391 | struct drm_device *dev = crtc->dev; | |
3392 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3393 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3394 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3395 | i915_reg_t reg; |
3396 | u32 temp, tries; | |
8db9d77b | 3397 | |
1c8562f6 | 3398 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3399 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3400 | |
e1a44743 AJ |
3401 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3402 | for train result */ | |
5eddb70b CW |
3403 | reg = FDI_RX_IMR(pipe); |
3404 | temp = I915_READ(reg); | |
e1a44743 AJ |
3405 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3406 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3407 | I915_WRITE(reg, temp); |
3408 | I915_READ(reg); | |
e1a44743 AJ |
3409 | udelay(150); |
3410 | ||
8db9d77b | 3411 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3412 | reg = FDI_TX_CTL(pipe); |
3413 | temp = I915_READ(reg); | |
627eb5a3 | 3414 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3415 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3416 | temp &= ~FDI_LINK_TRAIN_NONE; |
3417 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3418 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3419 | |
5eddb70b CW |
3420 | reg = FDI_RX_CTL(pipe); |
3421 | temp = I915_READ(reg); | |
8db9d77b ZW |
3422 | temp &= ~FDI_LINK_TRAIN_NONE; |
3423 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3424 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3425 | ||
3426 | POSTING_READ(reg); | |
8db9d77b ZW |
3427 | udelay(150); |
3428 | ||
5b2adf89 | 3429 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3430 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3431 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3432 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3433 | |
5eddb70b | 3434 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3435 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3436 | temp = I915_READ(reg); |
8db9d77b ZW |
3437 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3438 | ||
3439 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3440 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3441 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3442 | break; |
3443 | } | |
8db9d77b | 3444 | } |
e1a44743 | 3445 | if (tries == 5) |
5eddb70b | 3446 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3447 | |
3448 | /* Train 2 */ | |
5eddb70b CW |
3449 | reg = FDI_TX_CTL(pipe); |
3450 | temp = I915_READ(reg); | |
8db9d77b ZW |
3451 | temp &= ~FDI_LINK_TRAIN_NONE; |
3452 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3453 | I915_WRITE(reg, temp); |
8db9d77b | 3454 | |
5eddb70b CW |
3455 | reg = FDI_RX_CTL(pipe); |
3456 | temp = I915_READ(reg); | |
8db9d77b ZW |
3457 | temp &= ~FDI_LINK_TRAIN_NONE; |
3458 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3459 | I915_WRITE(reg, temp); |
8db9d77b | 3460 | |
5eddb70b CW |
3461 | POSTING_READ(reg); |
3462 | udelay(150); | |
8db9d77b | 3463 | |
5eddb70b | 3464 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3465 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3466 | temp = I915_READ(reg); |
8db9d77b ZW |
3467 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3468 | ||
3469 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3470 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3471 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3472 | break; | |
3473 | } | |
8db9d77b | 3474 | } |
e1a44743 | 3475 | if (tries == 5) |
5eddb70b | 3476 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3477 | |
3478 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3479 | |
8db9d77b ZW |
3480 | } |
3481 | ||
0206e353 | 3482 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3483 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3484 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3485 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3486 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3487 | }; | |
3488 | ||
3489 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3490 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3491 | { | |
3492 | struct drm_device *dev = crtc->dev; | |
3493 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3494 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3495 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3496 | i915_reg_t reg; |
3497 | u32 temp, i, retry; | |
8db9d77b | 3498 | |
e1a44743 AJ |
3499 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3500 | for train result */ | |
5eddb70b CW |
3501 | reg = FDI_RX_IMR(pipe); |
3502 | temp = I915_READ(reg); | |
e1a44743 AJ |
3503 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3504 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3505 | I915_WRITE(reg, temp); |
3506 | ||
3507 | POSTING_READ(reg); | |
e1a44743 AJ |
3508 | udelay(150); |
3509 | ||
8db9d77b | 3510 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3511 | reg = FDI_TX_CTL(pipe); |
3512 | temp = I915_READ(reg); | |
627eb5a3 | 3513 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3514 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3515 | temp &= ~FDI_LINK_TRAIN_NONE; |
3516 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3517 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3518 | /* SNB-B */ | |
3519 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3520 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3521 | |
d74cf324 DV |
3522 | I915_WRITE(FDI_RX_MISC(pipe), |
3523 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3524 | ||
5eddb70b CW |
3525 | reg = FDI_RX_CTL(pipe); |
3526 | temp = I915_READ(reg); | |
8db9d77b ZW |
3527 | if (HAS_PCH_CPT(dev)) { |
3528 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3529 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3530 | } else { | |
3531 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3532 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3533 | } | |
5eddb70b CW |
3534 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3535 | ||
3536 | POSTING_READ(reg); | |
8db9d77b ZW |
3537 | udelay(150); |
3538 | ||
0206e353 | 3539 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3540 | reg = FDI_TX_CTL(pipe); |
3541 | temp = I915_READ(reg); | |
8db9d77b ZW |
3542 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3543 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3544 | I915_WRITE(reg, temp); |
3545 | ||
3546 | POSTING_READ(reg); | |
8db9d77b ZW |
3547 | udelay(500); |
3548 | ||
fa37d39e SP |
3549 | for (retry = 0; retry < 5; retry++) { |
3550 | reg = FDI_RX_IIR(pipe); | |
3551 | temp = I915_READ(reg); | |
3552 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3553 | if (temp & FDI_RX_BIT_LOCK) { | |
3554 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3555 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3556 | break; | |
3557 | } | |
3558 | udelay(50); | |
8db9d77b | 3559 | } |
fa37d39e SP |
3560 | if (retry < 5) |
3561 | break; | |
8db9d77b ZW |
3562 | } |
3563 | if (i == 4) | |
5eddb70b | 3564 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3565 | |
3566 | /* Train 2 */ | |
5eddb70b CW |
3567 | reg = FDI_TX_CTL(pipe); |
3568 | temp = I915_READ(reg); | |
8db9d77b ZW |
3569 | temp &= ~FDI_LINK_TRAIN_NONE; |
3570 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3571 | if (IS_GEN6(dev)) { | |
3572 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3573 | /* SNB-B */ | |
3574 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3575 | } | |
5eddb70b | 3576 | I915_WRITE(reg, temp); |
8db9d77b | 3577 | |
5eddb70b CW |
3578 | reg = FDI_RX_CTL(pipe); |
3579 | temp = I915_READ(reg); | |
8db9d77b ZW |
3580 | if (HAS_PCH_CPT(dev)) { |
3581 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3582 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3583 | } else { | |
3584 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3585 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3586 | } | |
5eddb70b CW |
3587 | I915_WRITE(reg, temp); |
3588 | ||
3589 | POSTING_READ(reg); | |
8db9d77b ZW |
3590 | udelay(150); |
3591 | ||
0206e353 | 3592 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3593 | reg = FDI_TX_CTL(pipe); |
3594 | temp = I915_READ(reg); | |
8db9d77b ZW |
3595 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3596 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3597 | I915_WRITE(reg, temp); |
3598 | ||
3599 | POSTING_READ(reg); | |
8db9d77b ZW |
3600 | udelay(500); |
3601 | ||
fa37d39e SP |
3602 | for (retry = 0; retry < 5; retry++) { |
3603 | reg = FDI_RX_IIR(pipe); | |
3604 | temp = I915_READ(reg); | |
3605 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3606 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3607 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3608 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3609 | break; | |
3610 | } | |
3611 | udelay(50); | |
8db9d77b | 3612 | } |
fa37d39e SP |
3613 | if (retry < 5) |
3614 | break; | |
8db9d77b ZW |
3615 | } |
3616 | if (i == 4) | |
5eddb70b | 3617 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3618 | |
3619 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3620 | } | |
3621 | ||
357555c0 JB |
3622 | /* Manual link training for Ivy Bridge A0 parts */ |
3623 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3624 | { | |
3625 | struct drm_device *dev = crtc->dev; | |
3626 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3627 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3628 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3629 | i915_reg_t reg; |
3630 | u32 temp, i, j; | |
357555c0 JB |
3631 | |
3632 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3633 | for train result */ | |
3634 | reg = FDI_RX_IMR(pipe); | |
3635 | temp = I915_READ(reg); | |
3636 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3637 | temp &= ~FDI_RX_BIT_LOCK; | |
3638 | I915_WRITE(reg, temp); | |
3639 | ||
3640 | POSTING_READ(reg); | |
3641 | udelay(150); | |
3642 | ||
01a415fd DV |
3643 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3644 | I915_READ(FDI_RX_IIR(pipe))); | |
3645 | ||
139ccd3f JB |
3646 | /* Try each vswing and preemphasis setting twice before moving on */ |
3647 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3648 | /* disable first in case we need to retry */ | |
3649 | reg = FDI_TX_CTL(pipe); | |
3650 | temp = I915_READ(reg); | |
3651 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3652 | temp &= ~FDI_TX_ENABLE; | |
3653 | I915_WRITE(reg, temp); | |
357555c0 | 3654 | |
139ccd3f JB |
3655 | reg = FDI_RX_CTL(pipe); |
3656 | temp = I915_READ(reg); | |
3657 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3658 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3659 | temp &= ~FDI_RX_ENABLE; | |
3660 | I915_WRITE(reg, temp); | |
357555c0 | 3661 | |
139ccd3f | 3662 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3663 | reg = FDI_TX_CTL(pipe); |
3664 | temp = I915_READ(reg); | |
139ccd3f | 3665 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3666 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3667 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3668 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3669 | temp |= snb_b_fdi_train_param[j/2]; |
3670 | temp |= FDI_COMPOSITE_SYNC; | |
3671 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3672 | |
139ccd3f JB |
3673 | I915_WRITE(FDI_RX_MISC(pipe), |
3674 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3675 | |
139ccd3f | 3676 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3677 | temp = I915_READ(reg); |
139ccd3f JB |
3678 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3679 | temp |= FDI_COMPOSITE_SYNC; | |
3680 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3681 | |
139ccd3f JB |
3682 | POSTING_READ(reg); |
3683 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3684 | |
139ccd3f JB |
3685 | for (i = 0; i < 4; i++) { |
3686 | reg = FDI_RX_IIR(pipe); | |
3687 | temp = I915_READ(reg); | |
3688 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3689 | |
139ccd3f JB |
3690 | if (temp & FDI_RX_BIT_LOCK || |
3691 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3692 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3693 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3694 | i); | |
3695 | break; | |
3696 | } | |
3697 | udelay(1); /* should be 0.5us */ | |
3698 | } | |
3699 | if (i == 4) { | |
3700 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3701 | continue; | |
3702 | } | |
357555c0 | 3703 | |
139ccd3f | 3704 | /* Train 2 */ |
357555c0 JB |
3705 | reg = FDI_TX_CTL(pipe); |
3706 | temp = I915_READ(reg); | |
139ccd3f JB |
3707 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3708 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3709 | I915_WRITE(reg, temp); | |
3710 | ||
3711 | reg = FDI_RX_CTL(pipe); | |
3712 | temp = I915_READ(reg); | |
3713 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3714 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3715 | I915_WRITE(reg, temp); |
3716 | ||
3717 | POSTING_READ(reg); | |
139ccd3f | 3718 | udelay(2); /* should be 1.5us */ |
357555c0 | 3719 | |
139ccd3f JB |
3720 | for (i = 0; i < 4; i++) { |
3721 | reg = FDI_RX_IIR(pipe); | |
3722 | temp = I915_READ(reg); | |
3723 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3724 | |
139ccd3f JB |
3725 | if (temp & FDI_RX_SYMBOL_LOCK || |
3726 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3727 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3728 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3729 | i); | |
3730 | goto train_done; | |
3731 | } | |
3732 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3733 | } |
139ccd3f JB |
3734 | if (i == 4) |
3735 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3736 | } |
357555c0 | 3737 | |
139ccd3f | 3738 | train_done: |
357555c0 JB |
3739 | DRM_DEBUG_KMS("FDI train done.\n"); |
3740 | } | |
3741 | ||
88cefb6c | 3742 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3743 | { |
88cefb6c | 3744 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3745 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3746 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
3747 | i915_reg_t reg; |
3748 | u32 temp; | |
c64e311e | 3749 | |
c98e9dcf | 3750 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3751 | reg = FDI_RX_CTL(pipe); |
3752 | temp = I915_READ(reg); | |
627eb5a3 | 3753 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3754 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3755 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3756 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3757 | ||
3758 | POSTING_READ(reg); | |
c98e9dcf JB |
3759 | udelay(200); |
3760 | ||
3761 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3762 | temp = I915_READ(reg); |
3763 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3764 | ||
3765 | POSTING_READ(reg); | |
c98e9dcf JB |
3766 | udelay(200); |
3767 | ||
20749730 PZ |
3768 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3769 | reg = FDI_TX_CTL(pipe); | |
3770 | temp = I915_READ(reg); | |
3771 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3772 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3773 | |
20749730 PZ |
3774 | POSTING_READ(reg); |
3775 | udelay(100); | |
6be4a607 | 3776 | } |
0e23b99d JB |
3777 | } |
3778 | ||
88cefb6c DV |
3779 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3780 | { | |
3781 | struct drm_device *dev = intel_crtc->base.dev; | |
3782 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3783 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3784 | i915_reg_t reg; |
3785 | u32 temp; | |
88cefb6c DV |
3786 | |
3787 | /* Switch from PCDclk to Rawclk */ | |
3788 | reg = FDI_RX_CTL(pipe); | |
3789 | temp = I915_READ(reg); | |
3790 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3791 | ||
3792 | /* Disable CPU FDI TX PLL */ | |
3793 | reg = FDI_TX_CTL(pipe); | |
3794 | temp = I915_READ(reg); | |
3795 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3796 | ||
3797 | POSTING_READ(reg); | |
3798 | udelay(100); | |
3799 | ||
3800 | reg = FDI_RX_CTL(pipe); | |
3801 | temp = I915_READ(reg); | |
3802 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3803 | ||
3804 | /* Wait for the clocks to turn off. */ | |
3805 | POSTING_READ(reg); | |
3806 | udelay(100); | |
3807 | } | |
3808 | ||
0fc932b8 JB |
3809 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3810 | { | |
3811 | struct drm_device *dev = crtc->dev; | |
3812 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3813 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3814 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3815 | i915_reg_t reg; |
3816 | u32 temp; | |
0fc932b8 JB |
3817 | |
3818 | /* disable CPU FDI tx and PCH FDI rx */ | |
3819 | reg = FDI_TX_CTL(pipe); | |
3820 | temp = I915_READ(reg); | |
3821 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3822 | POSTING_READ(reg); | |
3823 | ||
3824 | reg = FDI_RX_CTL(pipe); | |
3825 | temp = I915_READ(reg); | |
3826 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3827 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3828 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3829 | ||
3830 | POSTING_READ(reg); | |
3831 | udelay(100); | |
3832 | ||
3833 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3834 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3835 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3836 | |
3837 | /* still set train pattern 1 */ | |
3838 | reg = FDI_TX_CTL(pipe); | |
3839 | temp = I915_READ(reg); | |
3840 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3841 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3842 | I915_WRITE(reg, temp); | |
3843 | ||
3844 | reg = FDI_RX_CTL(pipe); | |
3845 | temp = I915_READ(reg); | |
3846 | if (HAS_PCH_CPT(dev)) { | |
3847 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3848 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3849 | } else { | |
3850 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3851 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3852 | } | |
3853 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3854 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3855 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3856 | I915_WRITE(reg, temp); |
3857 | ||
3858 | POSTING_READ(reg); | |
3859 | udelay(100); | |
3860 | } | |
3861 | ||
5dce5b93 CW |
3862 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3863 | { | |
3864 | struct intel_crtc *crtc; | |
3865 | ||
3866 | /* Note that we don't need to be called with mode_config.lock here | |
3867 | * as our list of CRTC objects is static for the lifetime of the | |
3868 | * device and so cannot disappear as we iterate. Similarly, we can | |
3869 | * happily treat the predicates as racy, atomic checks as userspace | |
3870 | * cannot claim and pin a new fb without at least acquring the | |
3871 | * struct_mutex and so serialising with us. | |
3872 | */ | |
d3fcc808 | 3873 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3874 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3875 | continue; | |
3876 | ||
3877 | if (crtc->unpin_work) | |
3878 | intel_wait_for_vblank(dev, crtc->pipe); | |
3879 | ||
3880 | return true; | |
3881 | } | |
3882 | ||
3883 | return false; | |
3884 | } | |
3885 | ||
d6bbafa1 CW |
3886 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3887 | { | |
3888 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3889 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3890 | ||
3891 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3892 | smp_rmb(); | |
3893 | intel_crtc->unpin_work = NULL; | |
3894 | ||
3895 | if (work->event) | |
3896 | drm_send_vblank_event(intel_crtc->base.dev, | |
3897 | intel_crtc->pipe, | |
3898 | work->event); | |
3899 | ||
3900 | drm_crtc_vblank_put(&intel_crtc->base); | |
3901 | ||
3902 | wake_up_all(&dev_priv->pending_flip_queue); | |
3903 | queue_work(dev_priv->wq, &work->work); | |
3904 | ||
3905 | trace_i915_flip_complete(intel_crtc->plane, | |
3906 | work->pending_flip_obj); | |
3907 | } | |
3908 | ||
5008e874 | 3909 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3910 | { |
0f91128d | 3911 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3912 | struct drm_i915_private *dev_priv = dev->dev_private; |
5008e874 | 3913 | long ret; |
e6c3a2a6 | 3914 | |
2c10d571 | 3915 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
3916 | |
3917 | ret = wait_event_interruptible_timeout( | |
3918 | dev_priv->pending_flip_queue, | |
3919 | !intel_crtc_has_pending_flip(crtc), | |
3920 | 60*HZ); | |
3921 | ||
3922 | if (ret < 0) | |
3923 | return ret; | |
3924 | ||
3925 | if (ret == 0) { | |
9c787942 | 3926 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2c10d571 | 3927 | |
5e2d7afc | 3928 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3929 | if (intel_crtc->unpin_work) { |
3930 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3931 | page_flip_completed(intel_crtc); | |
3932 | } | |
5e2d7afc | 3933 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3934 | } |
5bb61643 | 3935 | |
5008e874 | 3936 | return 0; |
e6c3a2a6 CW |
3937 | } |
3938 | ||
060f02d8 VS |
3939 | static void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
3940 | { | |
3941 | u32 temp; | |
3942 | ||
3943 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3944 | ||
3945 | mutex_lock(&dev_priv->sb_lock); | |
3946 | ||
3947 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
3948 | temp |= SBI_SSCCTL_DISABLE; | |
3949 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
3950 | ||
3951 | mutex_unlock(&dev_priv->sb_lock); | |
3952 | } | |
3953 | ||
e615efe4 ED |
3954 | /* Program iCLKIP clock to the desired frequency */ |
3955 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3956 | { | |
3957 | struct drm_device *dev = crtc->dev; | |
3958 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3959 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3960 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3961 | u32 temp; | |
3962 | ||
060f02d8 | 3963 | lpt_disable_iclkip(dev_priv); |
e615efe4 ED |
3964 | |
3965 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3966 | if (clock == 20000) { |
e615efe4 ED |
3967 | auxdiv = 1; |
3968 | divsel = 0x41; | |
3969 | phaseinc = 0x20; | |
3970 | } else { | |
3971 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3972 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3973 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3974 | * convert the virtual clock precision to KHz here for higher |
3975 | * precision. | |
3976 | */ | |
3977 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3978 | u32 iclk_pi_range = 64; | |
3979 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3980 | ||
a2572f5c | 3981 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, clock); |
e615efe4 ED |
3982 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3983 | pi_value = desired_divisor % iclk_pi_range; | |
3984 | ||
3985 | auxdiv = 0; | |
3986 | divsel = msb_divisor_value - 2; | |
3987 | phaseinc = pi_value; | |
3988 | } | |
3989 | ||
3990 | /* This should not happen with any sane values */ | |
3991 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3992 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3993 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3994 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3995 | ||
3996 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3997 | clock, |
e615efe4 ED |
3998 | auxdiv, |
3999 | divsel, | |
4000 | phasedir, | |
4001 | phaseinc); | |
4002 | ||
060f02d8 VS |
4003 | mutex_lock(&dev_priv->sb_lock); |
4004 | ||
e615efe4 | 4005 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 4006 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4007 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4008 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4009 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4010 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4011 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4012 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4013 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4014 | |
4015 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4016 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4017 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4018 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4019 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4020 | |
4021 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4022 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4023 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4024 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 4025 | |
060f02d8 VS |
4026 | mutex_unlock(&dev_priv->sb_lock); |
4027 | ||
e615efe4 ED |
4028 | /* Wait for initialization time */ |
4029 | udelay(24); | |
4030 | ||
4031 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
4032 | } | |
4033 | ||
275f01b2 DV |
4034 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4035 | enum pipe pch_transcoder) | |
4036 | { | |
4037 | struct drm_device *dev = crtc->base.dev; | |
4038 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4039 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4040 | |
4041 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4042 | I915_READ(HTOTAL(cpu_transcoder))); | |
4043 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4044 | I915_READ(HBLANK(cpu_transcoder))); | |
4045 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4046 | I915_READ(HSYNC(cpu_transcoder))); | |
4047 | ||
4048 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4049 | I915_READ(VTOTAL(cpu_transcoder))); | |
4050 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4051 | I915_READ(VBLANK(cpu_transcoder))); | |
4052 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4053 | I915_READ(VSYNC(cpu_transcoder))); | |
4054 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4055 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4056 | } | |
4057 | ||
003632d9 | 4058 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
4059 | { |
4060 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4061 | uint32_t temp; | |
4062 | ||
4063 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4064 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4065 | return; |
4066 | ||
4067 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4068 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4069 | ||
003632d9 ACO |
4070 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4071 | if (enable) | |
4072 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4073 | ||
4074 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4075 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4076 | POSTING_READ(SOUTH_CHICKEN1); | |
4077 | } | |
4078 | ||
4079 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4080 | { | |
4081 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4082 | |
4083 | switch (intel_crtc->pipe) { | |
4084 | case PIPE_A: | |
4085 | break; | |
4086 | case PIPE_B: | |
6e3c9717 | 4087 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4088 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4089 | else |
003632d9 | 4090 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4091 | |
4092 | break; | |
4093 | case PIPE_C: | |
003632d9 | 4094 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4095 | |
4096 | break; | |
4097 | default: | |
4098 | BUG(); | |
4099 | } | |
4100 | } | |
4101 | ||
c48b5305 VS |
4102 | /* Return which DP Port should be selected for Transcoder DP control */ |
4103 | static enum port | |
4104 | intel_trans_dp_port_sel(struct drm_crtc *crtc) | |
4105 | { | |
4106 | struct drm_device *dev = crtc->dev; | |
4107 | struct intel_encoder *encoder; | |
4108 | ||
4109 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
4110 | if (encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
4111 | encoder->type == INTEL_OUTPUT_EDP) | |
4112 | return enc_to_dig_port(&encoder->base)->port; | |
4113 | } | |
4114 | ||
4115 | return -1; | |
4116 | } | |
4117 | ||
f67a559d JB |
4118 | /* |
4119 | * Enable PCH resources required for PCH ports: | |
4120 | * - PCH PLLs | |
4121 | * - FDI training & RX/TX | |
4122 | * - update transcoder timings | |
4123 | * - DP transcoding bits | |
4124 | * - transcoder | |
4125 | */ | |
4126 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4127 | { |
4128 | struct drm_device *dev = crtc->dev; | |
4129 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4130 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4131 | int pipe = intel_crtc->pipe; | |
f0f59a00 | 4132 | u32 temp; |
2c07245f | 4133 | |
ab9412ba | 4134 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4135 | |
1fbc0d78 DV |
4136 | if (IS_IVYBRIDGE(dev)) |
4137 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4138 | ||
cd986abb DV |
4139 | /* Write the TU size bits before fdi link training, so that error |
4140 | * detection works. */ | |
4141 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4142 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4143 | ||
3860b2ec VS |
4144 | /* |
4145 | * Sometimes spurious CPU pipe underruns happen during FDI | |
4146 | * training, at least with VGA+HDMI cloning. Suppress them. | |
4147 | */ | |
4148 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4149 | ||
c98e9dcf | 4150 | /* For PCH output, training FDI link */ |
674cf967 | 4151 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4152 | |
3ad8a208 DV |
4153 | /* We need to program the right clock selection before writing the pixel |
4154 | * mutliplier into the DPLL. */ | |
303b81e0 | 4155 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4156 | u32 sel; |
4b645f14 | 4157 | |
c98e9dcf | 4158 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4159 | temp |= TRANS_DPLL_ENABLE(pipe); |
4160 | sel = TRANS_DPLLB_SEL(pipe); | |
6e3c9717 | 4161 | if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
4162 | temp |= sel; |
4163 | else | |
4164 | temp &= ~sel; | |
c98e9dcf | 4165 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4166 | } |
5eddb70b | 4167 | |
3ad8a208 DV |
4168 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4169 | * transcoder, and we actually should do this to not upset any PCH | |
4170 | * transcoder that already use the clock when we share it. | |
4171 | * | |
4172 | * Note that enable_shared_dpll tries to do the right thing, but | |
4173 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4174 | * the right LVDS enable sequence. */ | |
85b3894f | 4175 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4176 | |
d9b6cb56 JB |
4177 | /* set transcoder timing, panel must allow it */ |
4178 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4179 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4180 | |
303b81e0 | 4181 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4182 | |
3860b2ec VS |
4183 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4184 | ||
c98e9dcf | 4185 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4186 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
9c4edaee VS |
4187 | const struct drm_display_mode *adjusted_mode = |
4188 | &intel_crtc->config->base.adjusted_mode; | |
dfd07d72 | 4189 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4190 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4191 | temp = I915_READ(reg); |
4192 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4193 | TRANS_DP_SYNC_MASK | |
4194 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4195 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4196 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4197 | |
9c4edaee | 4198 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4199 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4200 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4201 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4202 | |
4203 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4204 | case PORT_B: |
5eddb70b | 4205 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4206 | break; |
c48b5305 | 4207 | case PORT_C: |
5eddb70b | 4208 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4209 | break; |
c48b5305 | 4210 | case PORT_D: |
5eddb70b | 4211 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4212 | break; |
4213 | default: | |
e95d41e1 | 4214 | BUG(); |
32f9d658 | 4215 | } |
2c07245f | 4216 | |
5eddb70b | 4217 | I915_WRITE(reg, temp); |
6be4a607 | 4218 | } |
b52eb4dc | 4219 | |
b8a4f404 | 4220 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4221 | } |
4222 | ||
1507e5bd PZ |
4223 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4224 | { | |
4225 | struct drm_device *dev = crtc->dev; | |
4226 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4227 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4228 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4229 | |
ab9412ba | 4230 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4231 | |
8c52b5e8 | 4232 | lpt_program_iclkip(crtc); |
1507e5bd | 4233 | |
0540e488 | 4234 | /* Set transcoder timing. */ |
275f01b2 | 4235 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4236 | |
937bb610 | 4237 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4238 | } |
4239 | ||
190f68c5 ACO |
4240 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
4241 | struct intel_crtc_state *crtc_state) | |
ee7b9f93 | 4242 | { |
e2b78267 | 4243 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 4244 | struct intel_shared_dpll *pll; |
de419ab6 | 4245 | struct intel_shared_dpll_config *shared_dpll; |
e2b78267 | 4246 | enum intel_dpll_id i; |
00490c22 | 4247 | int max = dev_priv->num_shared_dpll; |
ee7b9f93 | 4248 | |
de419ab6 ML |
4249 | shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state); |
4250 | ||
98b6bd99 DV |
4251 | if (HAS_PCH_IBX(dev_priv->dev)) { |
4252 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 4253 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 4254 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 4255 | |
46edb027 DV |
4256 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
4257 | crtc->base.base.id, pll->name); | |
98b6bd99 | 4258 | |
de419ab6 | 4259 | WARN_ON(shared_dpll[i].crtc_mask); |
f2a69f44 | 4260 | |
98b6bd99 DV |
4261 | goto found; |
4262 | } | |
4263 | ||
bcddf610 S |
4264 | if (IS_BROXTON(dev_priv->dev)) { |
4265 | /* PLL is attached to port in bxt */ | |
4266 | struct intel_encoder *encoder; | |
4267 | struct intel_digital_port *intel_dig_port; | |
4268 | ||
4269 | encoder = intel_ddi_get_crtc_new_encoder(crtc_state); | |
4270 | if (WARN_ON(!encoder)) | |
4271 | return NULL; | |
4272 | ||
4273 | intel_dig_port = enc_to_dig_port(&encoder->base); | |
4274 | /* 1:1 mapping between ports and PLLs */ | |
4275 | i = (enum intel_dpll_id)intel_dig_port->port; | |
4276 | pll = &dev_priv->shared_dplls[i]; | |
4277 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", | |
4278 | crtc->base.base.id, pll->name); | |
de419ab6 | 4279 | WARN_ON(shared_dpll[i].crtc_mask); |
bcddf610 S |
4280 | |
4281 | goto found; | |
00490c22 ML |
4282 | } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv)) |
4283 | /* Do not consider SPLL */ | |
4284 | max = 2; | |
bcddf610 | 4285 | |
00490c22 | 4286 | for (i = 0; i < max; i++) { |
e72f9fbf | 4287 | pll = &dev_priv->shared_dplls[i]; |
ee7b9f93 JB |
4288 | |
4289 | /* Only want to check enabled timings first */ | |
de419ab6 | 4290 | if (shared_dpll[i].crtc_mask == 0) |
ee7b9f93 JB |
4291 | continue; |
4292 | ||
190f68c5 | 4293 | if (memcmp(&crtc_state->dpll_hw_state, |
de419ab6 ML |
4294 | &shared_dpll[i].hw_state, |
4295 | sizeof(crtc_state->dpll_hw_state)) == 0) { | |
8bd31e67 | 4296 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", |
1e6f2ddc | 4297 | crtc->base.base.id, pll->name, |
de419ab6 | 4298 | shared_dpll[i].crtc_mask, |
8bd31e67 | 4299 | pll->active); |
ee7b9f93 JB |
4300 | goto found; |
4301 | } | |
4302 | } | |
4303 | ||
4304 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
4305 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4306 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4307 | if (shared_dpll[i].crtc_mask == 0) { |
46edb027 DV |
4308 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
4309 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
4310 | goto found; |
4311 | } | |
4312 | } | |
4313 | ||
4314 | return NULL; | |
4315 | ||
4316 | found: | |
de419ab6 ML |
4317 | if (shared_dpll[i].crtc_mask == 0) |
4318 | shared_dpll[i].hw_state = | |
4319 | crtc_state->dpll_hw_state; | |
f2a69f44 | 4320 | |
190f68c5 | 4321 | crtc_state->shared_dpll = i; |
46edb027 DV |
4322 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
4323 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 4324 | |
de419ab6 | 4325 | shared_dpll[i].crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 4326 | |
ee7b9f93 JB |
4327 | return pll; |
4328 | } | |
4329 | ||
de419ab6 | 4330 | static void intel_shared_dpll_commit(struct drm_atomic_state *state) |
8bd31e67 | 4331 | { |
de419ab6 ML |
4332 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
4333 | struct intel_shared_dpll_config *shared_dpll; | |
8bd31e67 ACO |
4334 | struct intel_shared_dpll *pll; |
4335 | enum intel_dpll_id i; | |
4336 | ||
de419ab6 ML |
4337 | if (!to_intel_atomic_state(state)->dpll_set) |
4338 | return; | |
8bd31e67 | 4339 | |
de419ab6 | 4340 | shared_dpll = to_intel_atomic_state(state)->shared_dpll; |
8bd31e67 ACO |
4341 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4342 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4343 | pll->config = shared_dpll[i]; |
8bd31e67 ACO |
4344 | } |
4345 | } | |
4346 | ||
a1520318 | 4347 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4348 | { |
4349 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 4350 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4351 | u32 temp; |
4352 | ||
4353 | temp = I915_READ(dslreg); | |
4354 | udelay(500); | |
4355 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4356 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4357 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4358 | } |
4359 | } | |
4360 | ||
86adf9d7 ML |
4361 | static int |
4362 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4363 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4364 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4365 | { |
86adf9d7 ML |
4366 | struct intel_crtc_scaler_state *scaler_state = |
4367 | &crtc_state->scaler_state; | |
4368 | struct intel_crtc *intel_crtc = | |
4369 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4370 | int need_scaling; |
6156a456 CK |
4371 | |
4372 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4373 | (src_h != dst_w || src_w != dst_h): | |
4374 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4375 | |
4376 | /* | |
4377 | * if plane is being disabled or scaler is no more required or force detach | |
4378 | * - free scaler binded to this plane/crtc | |
4379 | * - in order to do this, update crtc->scaler_usage | |
4380 | * | |
4381 | * Here scaler state in crtc_state is set free so that | |
4382 | * scaler can be assigned to other user. Actual register | |
4383 | * update to free the scaler is done in plane/panel-fit programming. | |
4384 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4385 | */ | |
86adf9d7 | 4386 | if (force_detach || !need_scaling) { |
a1b2278e | 4387 | if (*scaler_id >= 0) { |
86adf9d7 | 4388 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4389 | scaler_state->scalers[*scaler_id].in_use = 0; |
4390 | ||
86adf9d7 ML |
4391 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4392 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4393 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4394 | scaler_state->scaler_users); |
4395 | *scaler_id = -1; | |
4396 | } | |
4397 | return 0; | |
4398 | } | |
4399 | ||
4400 | /* range checks */ | |
4401 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4402 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4403 | ||
4404 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4405 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4406 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4407 | "size is out of scaler range\n", |
86adf9d7 | 4408 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4409 | return -EINVAL; |
4410 | } | |
4411 | ||
86adf9d7 ML |
4412 | /* mark this plane as a scaler user in crtc_state */ |
4413 | scaler_state->scaler_users |= (1 << scaler_user); | |
4414 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4415 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4416 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4417 | scaler_state->scaler_users); | |
4418 | ||
4419 | return 0; | |
4420 | } | |
4421 | ||
4422 | /** | |
4423 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4424 | * | |
4425 | * @state: crtc's scaler state | |
86adf9d7 ML |
4426 | * |
4427 | * Return | |
4428 | * 0 - scaler_usage updated successfully | |
4429 | * error - requested scaling cannot be supported or other error condition | |
4430 | */ | |
e435d6e5 | 4431 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 ML |
4432 | { |
4433 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); | |
7c5f93b0 | 4434 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 ML |
4435 | |
4436 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n", | |
4437 | intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX); | |
4438 | ||
e435d6e5 | 4439 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
86adf9d7 ML |
4440 | &state->scaler_state.scaler_id, DRM_ROTATE_0, |
4441 | state->pipe_src_w, state->pipe_src_h, | |
aad941d5 | 4442 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4443 | } |
4444 | ||
4445 | /** | |
4446 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4447 | * | |
4448 | * @state: crtc's scaler state | |
86adf9d7 ML |
4449 | * @plane_state: atomic plane state to update |
4450 | * | |
4451 | * Return | |
4452 | * 0 - scaler_usage updated successfully | |
4453 | * error - requested scaling cannot be supported or other error condition | |
4454 | */ | |
da20eabd ML |
4455 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4456 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4457 | { |
4458 | ||
4459 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
da20eabd ML |
4460 | struct intel_plane *intel_plane = |
4461 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4462 | struct drm_framebuffer *fb = plane_state->base.fb; |
4463 | int ret; | |
4464 | ||
4465 | bool force_detach = !fb || !plane_state->visible; | |
4466 | ||
4467 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n", | |
4468 | intel_plane->base.base.id, intel_crtc->pipe, | |
4469 | drm_plane_index(&intel_plane->base)); | |
4470 | ||
4471 | ret = skl_update_scaler(crtc_state, force_detach, | |
4472 | drm_plane_index(&intel_plane->base), | |
4473 | &plane_state->scaler_id, | |
4474 | plane_state->base.rotation, | |
4475 | drm_rect_width(&plane_state->src) >> 16, | |
4476 | drm_rect_height(&plane_state->src) >> 16, | |
4477 | drm_rect_width(&plane_state->dst), | |
4478 | drm_rect_height(&plane_state->dst)); | |
4479 | ||
4480 | if (ret || plane_state->scaler_id < 0) | |
4481 | return ret; | |
4482 | ||
a1b2278e | 4483 | /* check colorkey */ |
818ed961 | 4484 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
86adf9d7 | 4485 | DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed", |
818ed961 | 4486 | intel_plane->base.base.id); |
a1b2278e CK |
4487 | return -EINVAL; |
4488 | } | |
4489 | ||
4490 | /* Check src format */ | |
86adf9d7 ML |
4491 | switch (fb->pixel_format) { |
4492 | case DRM_FORMAT_RGB565: | |
4493 | case DRM_FORMAT_XBGR8888: | |
4494 | case DRM_FORMAT_XRGB8888: | |
4495 | case DRM_FORMAT_ABGR8888: | |
4496 | case DRM_FORMAT_ARGB8888: | |
4497 | case DRM_FORMAT_XRGB2101010: | |
4498 | case DRM_FORMAT_XBGR2101010: | |
4499 | case DRM_FORMAT_YUYV: | |
4500 | case DRM_FORMAT_YVYU: | |
4501 | case DRM_FORMAT_UYVY: | |
4502 | case DRM_FORMAT_VYUY: | |
4503 | break; | |
4504 | default: | |
4505 | DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n", | |
4506 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); | |
4507 | return -EINVAL; | |
a1b2278e CK |
4508 | } |
4509 | ||
a1b2278e CK |
4510 | return 0; |
4511 | } | |
4512 | ||
e435d6e5 ML |
4513 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4514 | { | |
4515 | int i; | |
4516 | ||
4517 | for (i = 0; i < crtc->num_scalers; i++) | |
4518 | skl_detach_scaler(crtc, i); | |
4519 | } | |
4520 | ||
4521 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4522 | { |
4523 | struct drm_device *dev = crtc->base.dev; | |
4524 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4525 | int pipe = crtc->pipe; | |
a1b2278e CK |
4526 | struct intel_crtc_scaler_state *scaler_state = |
4527 | &crtc->config->scaler_state; | |
4528 | ||
4529 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4530 | ||
6e3c9717 | 4531 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4532 | int id; |
4533 | ||
4534 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4535 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4536 | return; | |
4537 | } | |
4538 | ||
4539 | id = scaler_state->scaler_id; | |
4540 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4541 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4542 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4543 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4544 | ||
4545 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4546 | } |
4547 | } | |
4548 | ||
b074cec8 JB |
4549 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4550 | { | |
4551 | struct drm_device *dev = crtc->base.dev; | |
4552 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4553 | int pipe = crtc->pipe; | |
4554 | ||
6e3c9717 | 4555 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4556 | /* Force use of hard-coded filter coefficients |
4557 | * as some pre-programmed values are broken, | |
4558 | * e.g. x201. | |
4559 | */ | |
4560 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4561 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4562 | PF_PIPE_SEL_IVB(pipe)); | |
4563 | else | |
4564 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4565 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4566 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4567 | } |
4568 | } | |
4569 | ||
20bc8673 | 4570 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4571 | { |
cea165c3 VS |
4572 | struct drm_device *dev = crtc->base.dev; |
4573 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4574 | |
6e3c9717 | 4575 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4576 | return; |
4577 | ||
cea165c3 VS |
4578 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4579 | intel_wait_for_vblank(dev, crtc->pipe); | |
4580 | ||
d77e4531 | 4581 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4582 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4583 | mutex_lock(&dev_priv->rps.hw_lock); |
4584 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4585 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4586 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4587 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4588 | * mailbox." Moreover, the mailbox may return a bogus state, |
4589 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4590 | */ |
4591 | } else { | |
4592 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4593 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4594 | * is essentially intel_wait_for_vblank. If we don't have this | |
4595 | * and don't wait for vblanks until the end of crtc_enable, then | |
4596 | * the HW state readout code will complain that the expected | |
4597 | * IPS_CTL value is not the one we read. */ | |
4598 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4599 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4600 | } | |
d77e4531 PZ |
4601 | } |
4602 | ||
20bc8673 | 4603 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4604 | { |
4605 | struct drm_device *dev = crtc->base.dev; | |
4606 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4607 | ||
6e3c9717 | 4608 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4609 | return; |
4610 | ||
4611 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4612 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4613 | mutex_lock(&dev_priv->rps.hw_lock); |
4614 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4615 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4616 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4617 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4618 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4619 | } else { |
2a114cc1 | 4620 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4621 | POSTING_READ(IPS_CTL); |
4622 | } | |
d77e4531 PZ |
4623 | |
4624 | /* We need to wait for a vblank before we can disable the plane. */ | |
4625 | intel_wait_for_vblank(dev, crtc->pipe); | |
4626 | } | |
4627 | ||
4628 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4629 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4630 | { | |
4631 | struct drm_device *dev = crtc->dev; | |
4632 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4633 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4634 | enum pipe pipe = intel_crtc->pipe; | |
d77e4531 PZ |
4635 | int i; |
4636 | bool reenable_ips = false; | |
4637 | ||
4638 | /* The clocks have to be on to load the palette. */ | |
53d9f4e9 | 4639 | if (!crtc->state->active) |
d77e4531 PZ |
4640 | return; |
4641 | ||
50360403 | 4642 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) { |
a65347ba | 4643 | if (intel_crtc->config->has_dsi_encoder) |
d77e4531 PZ |
4644 | assert_dsi_pll_enabled(dev_priv); |
4645 | else | |
4646 | assert_pll_enabled(dev_priv, pipe); | |
4647 | } | |
4648 | ||
d77e4531 PZ |
4649 | /* Workaround : Do not read or write the pipe palette/gamma data while |
4650 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4651 | */ | |
6e3c9717 | 4652 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
d77e4531 PZ |
4653 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4654 | GAMMA_MODE_MODE_SPLIT)) { | |
4655 | hsw_disable_ips(intel_crtc); | |
4656 | reenable_ips = true; | |
4657 | } | |
4658 | ||
4659 | for (i = 0; i < 256; i++) { | |
f0f59a00 | 4660 | i915_reg_t palreg; |
f65a9c5b VS |
4661 | |
4662 | if (HAS_GMCH_DISPLAY(dev)) | |
4663 | palreg = PALETTE(pipe, i); | |
4664 | else | |
4665 | palreg = LGC_PALETTE(pipe, i); | |
4666 | ||
4667 | I915_WRITE(palreg, | |
d77e4531 PZ |
4668 | (intel_crtc->lut_r[i] << 16) | |
4669 | (intel_crtc->lut_g[i] << 8) | | |
4670 | intel_crtc->lut_b[i]); | |
4671 | } | |
4672 | ||
4673 | if (reenable_ips) | |
4674 | hsw_enable_ips(intel_crtc); | |
4675 | } | |
4676 | ||
7cac945f | 4677 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4678 | { |
7cac945f | 4679 | if (intel_crtc->overlay) { |
d3eedb1a VS |
4680 | struct drm_device *dev = intel_crtc->base.dev; |
4681 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4682 | ||
4683 | mutex_lock(&dev->struct_mutex); | |
4684 | dev_priv->mm.interruptible = false; | |
4685 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4686 | dev_priv->mm.interruptible = true; | |
4687 | mutex_unlock(&dev->struct_mutex); | |
4688 | } | |
4689 | ||
4690 | /* Let userspace switch the overlay on again. In most cases userspace | |
4691 | * has to recompute where to put it anyway. | |
4692 | */ | |
4693 | } | |
4694 | ||
87d4300a ML |
4695 | /** |
4696 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4697 | * @crtc: the CRTC whose primary plane was just enabled | |
4698 | * | |
4699 | * Performs potentially sleeping operations that must be done after the primary | |
4700 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4701 | * called due to an explicit primary plane update, or due to an implicit | |
4702 | * re-enable that is caused when a sprite plane is updated to no longer | |
4703 | * completely hide the primary plane. | |
4704 | */ | |
4705 | static void | |
4706 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4707 | { |
4708 | struct drm_device *dev = crtc->dev; | |
87d4300a | 4709 | struct drm_i915_private *dev_priv = dev->dev_private; |
a5c4d7bc VS |
4710 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4711 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4712 | |
87d4300a ML |
4713 | /* |
4714 | * FIXME IPS should be fine as long as one plane is | |
4715 | * enabled, but in practice it seems to have problems | |
4716 | * when going from primary only to sprite only and vice | |
4717 | * versa. | |
4718 | */ | |
a5c4d7bc VS |
4719 | hsw_enable_ips(intel_crtc); |
4720 | ||
f99d7069 | 4721 | /* |
87d4300a ML |
4722 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4723 | * So don't enable underrun reporting before at least some planes | |
4724 | * are enabled. | |
4725 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4726 | * but leave the pipe running. | |
f99d7069 | 4727 | */ |
87d4300a ML |
4728 | if (IS_GEN2(dev)) |
4729 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4730 | ||
aca7b684 VS |
4731 | /* Underruns don't always raise interrupts, so check manually. */ |
4732 | intel_check_cpu_fifo_underruns(dev_priv); | |
4733 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4734 | } |
4735 | ||
87d4300a ML |
4736 | /** |
4737 | * intel_pre_disable_primary - Perform operations before disabling primary plane | |
4738 | * @crtc: the CRTC whose primary plane is to be disabled | |
4739 | * | |
4740 | * Performs potentially sleeping operations that must be done before the | |
4741 | * primary plane is disabled, such as updating FBC and IPS. Note that this may | |
4742 | * be called due to an explicit primary plane update, or due to an implicit | |
4743 | * disable that is caused when a sprite plane completely hides the primary | |
4744 | * plane. | |
4745 | */ | |
4746 | static void | |
4747 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4748 | { |
4749 | struct drm_device *dev = crtc->dev; | |
4750 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4751 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4752 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4753 | |
87d4300a ML |
4754 | /* |
4755 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4756 | * So diasble underrun reporting before all the planes get disabled. | |
4757 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4758 | * but leave the pipe running. | |
4759 | */ | |
4760 | if (IS_GEN2(dev)) | |
4761 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4762 | |
87d4300a ML |
4763 | /* |
4764 | * Vblank time updates from the shadow to live plane control register | |
4765 | * are blocked if the memory self-refresh mode is active at that | |
4766 | * moment. So to make sure the plane gets truly disabled, disable | |
4767 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4768 | * will be checked/applied by the HW only at the next frame start | |
4769 | * event which is after the vblank start event, so we need to have a | |
4770 | * wait-for-vblank between disabling the plane and the pipe. | |
4771 | */ | |
262cd2e1 | 4772 | if (HAS_GMCH_DISPLAY(dev)) { |
87d4300a | 4773 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 VS |
4774 | dev_priv->wm.vlv.cxsr = false; |
4775 | intel_wait_for_vblank(dev, pipe); | |
4776 | } | |
87d4300a | 4777 | |
87d4300a ML |
4778 | /* |
4779 | * FIXME IPS should be fine as long as one plane is | |
4780 | * enabled, but in practice it seems to have problems | |
4781 | * when going from primary only to sprite only and vice | |
4782 | * versa. | |
4783 | */ | |
a5c4d7bc | 4784 | hsw_disable_ips(intel_crtc); |
87d4300a ML |
4785 | } |
4786 | ||
ac21b225 ML |
4787 | static void intel_post_plane_update(struct intel_crtc *crtc) |
4788 | { | |
4789 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; | |
92826fcd ML |
4790 | struct intel_crtc_state *pipe_config = |
4791 | to_intel_crtc_state(crtc->base.state); | |
ac21b225 | 4792 | struct drm_device *dev = crtc->base.dev; |
ac21b225 ML |
4793 | |
4794 | if (atomic->wait_vblank) | |
4795 | intel_wait_for_vblank(dev, crtc->pipe); | |
4796 | ||
4797 | intel_frontbuffer_flip(dev, atomic->fb_bits); | |
4798 | ||
ab1d3a0e | 4799 | crtc->wm.cxsr_allowed = true; |
852eb00d | 4800 | |
b9001114 | 4801 | if (pipe_config->wm_changed && pipe_config->base.active) |
f015c551 VS |
4802 | intel_update_watermarks(&crtc->base); |
4803 | ||
c80ac854 | 4804 | if (atomic->update_fbc) |
754d1133 | 4805 | intel_fbc_update(crtc); |
ac21b225 ML |
4806 | |
4807 | if (atomic->post_enable_primary) | |
4808 | intel_post_enable_primary(&crtc->base); | |
4809 | ||
ac21b225 ML |
4810 | memset(atomic, 0, sizeof(*atomic)); |
4811 | } | |
4812 | ||
4813 | static void intel_pre_plane_update(struct intel_crtc *crtc) | |
4814 | { | |
4815 | struct drm_device *dev = crtc->base.dev; | |
eddfcbcd | 4816 | struct drm_i915_private *dev_priv = dev->dev_private; |
ac21b225 | 4817 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; |
ab1d3a0e ML |
4818 | struct intel_crtc_state *pipe_config = |
4819 | to_intel_crtc_state(crtc->base.state); | |
ac21b225 | 4820 | |
c80ac854 | 4821 | if (atomic->disable_fbc) |
d029bcad | 4822 | intel_fbc_deactivate(crtc); |
ac21b225 | 4823 | |
066cf55b RV |
4824 | if (crtc->atomic.disable_ips) |
4825 | hsw_disable_ips(crtc); | |
4826 | ||
ac21b225 ML |
4827 | if (atomic->pre_disable_primary) |
4828 | intel_pre_disable_primary(&crtc->base); | |
852eb00d | 4829 | |
ab1d3a0e | 4830 | if (pipe_config->disable_cxsr) { |
852eb00d VS |
4831 | crtc->wm.cxsr_allowed = false; |
4832 | intel_set_memory_cxsr(dev_priv, false); | |
4833 | } | |
92826fcd ML |
4834 | |
4835 | if (!needs_modeset(&pipe_config->base) && pipe_config->wm_changed) | |
4836 | intel_update_watermarks(&crtc->base); | |
ac21b225 ML |
4837 | } |
4838 | ||
d032ffa0 | 4839 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
4840 | { |
4841 | struct drm_device *dev = crtc->dev; | |
4842 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 4843 | struct drm_plane *p; |
87d4300a ML |
4844 | int pipe = intel_crtc->pipe; |
4845 | ||
7cac945f | 4846 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 4847 | |
d032ffa0 ML |
4848 | drm_for_each_plane_mask(p, dev, plane_mask) |
4849 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 4850 | |
f99d7069 DV |
4851 | /* |
4852 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4853 | * to compute the mask of flip planes precisely. For the time being | |
4854 | * consider this a flip to a NULL plane. | |
4855 | */ | |
4856 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4857 | } |
4858 | ||
f67a559d JB |
4859 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4860 | { | |
4861 | struct drm_device *dev = crtc->dev; | |
4862 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4863 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4864 | struct intel_encoder *encoder; |
f67a559d | 4865 | int pipe = intel_crtc->pipe; |
f67a559d | 4866 | |
53d9f4e9 | 4867 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
4868 | return; |
4869 | ||
81b088ca VS |
4870 | if (intel_crtc->config->has_pch_encoder) |
4871 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
4872 | ||
6e3c9717 | 4873 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4874 | intel_prepare_shared_dpll(intel_crtc); |
4875 | ||
6e3c9717 | 4876 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4877 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4878 | |
4879 | intel_set_pipe_timings(intel_crtc); | |
4880 | ||
6e3c9717 | 4881 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4882 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4883 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4884 | } |
4885 | ||
4886 | ironlake_set_pipeconf(crtc); | |
4887 | ||
f67a559d | 4888 | intel_crtc->active = true; |
8664281b | 4889 | |
a72e4c9f | 4890 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
8664281b | 4891 | |
f6736a1a | 4892 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4893 | if (encoder->pre_enable) |
4894 | encoder->pre_enable(encoder); | |
f67a559d | 4895 | |
6e3c9717 | 4896 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4897 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4898 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4899 | * enabling. */ | |
88cefb6c | 4900 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4901 | } else { |
4902 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4903 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4904 | } | |
f67a559d | 4905 | |
b074cec8 | 4906 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4907 | |
9c54c0dd JB |
4908 | /* |
4909 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4910 | * clocks enabled | |
4911 | */ | |
4912 | intel_crtc_load_lut(crtc); | |
4913 | ||
f37fcc2a | 4914 | intel_update_watermarks(crtc); |
e1fdc473 | 4915 | intel_enable_pipe(intel_crtc); |
f67a559d | 4916 | |
6e3c9717 | 4917 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4918 | ironlake_pch_enable(crtc); |
c98e9dcf | 4919 | |
f9b61ff6 DV |
4920 | assert_vblank_disabled(crtc); |
4921 | drm_crtc_vblank_on(crtc); | |
4922 | ||
fa5c73b1 DV |
4923 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4924 | encoder->enable(encoder); | |
61b77ddd DV |
4925 | |
4926 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4927 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
4928 | |
4929 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
4930 | if (intel_crtc->config->has_pch_encoder) | |
4931 | intel_wait_for_vblank(dev, pipe); | |
4932 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
d029bcad PZ |
4933 | |
4934 | intel_fbc_enable(intel_crtc); | |
6be4a607 JB |
4935 | } |
4936 | ||
42db64ef PZ |
4937 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4938 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4939 | { | |
f5adf94e | 4940 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4941 | } |
4942 | ||
4f771f10 PZ |
4943 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4944 | { | |
4945 | struct drm_device *dev = crtc->dev; | |
4946 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4947 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4948 | struct intel_encoder *encoder; | |
99d736a2 ML |
4949 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4950 | struct intel_crtc_state *pipe_config = | |
4951 | to_intel_crtc_state(crtc->state); | |
4f771f10 | 4952 | |
53d9f4e9 | 4953 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
4954 | return; |
4955 | ||
81b088ca VS |
4956 | if (intel_crtc->config->has_pch_encoder) |
4957 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
4958 | false); | |
4959 | ||
df8ad70c DV |
4960 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4961 | intel_enable_shared_dpll(intel_crtc); | |
4962 | ||
6e3c9717 | 4963 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4964 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 DV |
4965 | |
4966 | intel_set_pipe_timings(intel_crtc); | |
4967 | ||
6e3c9717 ACO |
4968 | if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
4969 | I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), | |
4970 | intel_crtc->config->pixel_multiplier - 1); | |
ebb69c95 CT |
4971 | } |
4972 | ||
6e3c9717 | 4973 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 4974 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4975 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
4976 | } |
4977 | ||
4978 | haswell_set_pipeconf(crtc); | |
4979 | ||
4980 | intel_set_pipe_csc(crtc); | |
4981 | ||
4f771f10 | 4982 | intel_crtc->active = true; |
8664281b | 4983 | |
6b698516 DV |
4984 | if (intel_crtc->config->has_pch_encoder) |
4985 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4986 | else | |
4987 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4988 | ||
7d4aefd0 | 4989 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 PZ |
4990 | if (encoder->pre_enable) |
4991 | encoder->pre_enable(encoder); | |
7d4aefd0 | 4992 | } |
4f771f10 | 4993 | |
d2d65408 | 4994 | if (intel_crtc->config->has_pch_encoder) |
4fe9467d | 4995 | dev_priv->display.fdi_link_train(crtc); |
4fe9467d | 4996 | |
a65347ba | 4997 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 4998 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4999 | |
1c132b44 | 5000 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5001 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 5002 | else |
1c132b44 | 5003 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
5004 | |
5005 | /* | |
5006 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5007 | * clocks enabled | |
5008 | */ | |
5009 | intel_crtc_load_lut(crtc); | |
5010 | ||
1f544388 | 5011 | intel_ddi_set_pipe_settings(crtc); |
a65347ba | 5012 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5013 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 5014 | |
f37fcc2a | 5015 | intel_update_watermarks(crtc); |
e1fdc473 | 5016 | intel_enable_pipe(intel_crtc); |
42db64ef | 5017 | |
6e3c9717 | 5018 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 5019 | lpt_pch_enable(crtc); |
4f771f10 | 5020 | |
a65347ba | 5021 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
5022 | intel_ddi_set_vc_payload_alloc(crtc, true); |
5023 | ||
f9b61ff6 DV |
5024 | assert_vblank_disabled(crtc); |
5025 | drm_crtc_vblank_on(crtc); | |
5026 | ||
8807e55b | 5027 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 5028 | encoder->enable(encoder); |
8807e55b JN |
5029 | intel_opregion_notify_encoder(encoder, true); |
5030 | } | |
4f771f10 | 5031 | |
6b698516 DV |
5032 | if (intel_crtc->config->has_pch_encoder) { |
5033 | intel_wait_for_vblank(dev, pipe); | |
5034 | intel_wait_for_vblank(dev, pipe); | |
5035 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
d2d65408 VS |
5036 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5037 | true); | |
6b698516 | 5038 | } |
d2d65408 | 5039 | |
e4916946 PZ |
5040 | /* If we change the relative order between pipe/planes enabling, we need |
5041 | * to change the workaround. */ | |
99d736a2 ML |
5042 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
5043 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { | |
5044 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5045 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5046 | } | |
d029bcad PZ |
5047 | |
5048 | intel_fbc_enable(intel_crtc); | |
4f771f10 PZ |
5049 | } |
5050 | ||
bfd16b2a | 5051 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
5052 | { |
5053 | struct drm_device *dev = crtc->base.dev; | |
5054 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5055 | int pipe = crtc->pipe; | |
5056 | ||
5057 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5058 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5059 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5060 | I915_WRITE(PF_CTL(pipe), 0); |
5061 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5062 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5063 | } | |
5064 | } | |
5065 | ||
6be4a607 JB |
5066 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
5067 | { | |
5068 | struct drm_device *dev = crtc->dev; | |
5069 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5070 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5071 | struct intel_encoder *encoder; |
6be4a607 | 5072 | int pipe = intel_crtc->pipe; |
b52eb4dc | 5073 | |
37ca8d4c VS |
5074 | if (intel_crtc->config->has_pch_encoder) |
5075 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
5076 | ||
ea9d758d DV |
5077 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5078 | encoder->disable(encoder); | |
5079 | ||
f9b61ff6 DV |
5080 | drm_crtc_vblank_off(crtc); |
5081 | assert_vblank_disabled(crtc); | |
5082 | ||
3860b2ec VS |
5083 | /* |
5084 | * Sometimes spurious CPU pipe underruns happen when the | |
5085 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
5086 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
5087 | */ | |
5088 | if (intel_crtc->config->has_pch_encoder) | |
5089 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5090 | ||
575f7ab7 | 5091 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5092 | |
bfd16b2a | 5093 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5094 | |
3860b2ec | 5095 | if (intel_crtc->config->has_pch_encoder) { |
5a74f70a | 5096 | ironlake_fdi_disable(crtc); |
3860b2ec VS |
5097 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5098 | } | |
5a74f70a | 5099 | |
bf49ec8c DV |
5100 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5101 | if (encoder->post_disable) | |
5102 | encoder->post_disable(encoder); | |
2c07245f | 5103 | |
6e3c9717 | 5104 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5105 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5106 | |
d925c59a | 5107 | if (HAS_PCH_CPT(dev)) { |
f0f59a00 VS |
5108 | i915_reg_t reg; |
5109 | u32 temp; | |
5110 | ||
d925c59a DV |
5111 | /* disable TRANS_DP_CTL */ |
5112 | reg = TRANS_DP_CTL(pipe); | |
5113 | temp = I915_READ(reg); | |
5114 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5115 | TRANS_DP_PORT_SEL_MASK); | |
5116 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5117 | I915_WRITE(reg, temp); | |
5118 | ||
5119 | /* disable DPLL_SEL */ | |
5120 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5121 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5122 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5123 | } |
e3421a18 | 5124 | |
d925c59a DV |
5125 | ironlake_fdi_pll_disable(intel_crtc); |
5126 | } | |
81b088ca VS |
5127 | |
5128 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
d029bcad PZ |
5129 | |
5130 | intel_fbc_disable_crtc(intel_crtc); | |
6be4a607 | 5131 | } |
1b3c7a47 | 5132 | |
4f771f10 | 5133 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5134 | { |
4f771f10 PZ |
5135 | struct drm_device *dev = crtc->dev; |
5136 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 5137 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5138 | struct intel_encoder *encoder; |
6e3c9717 | 5139 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5140 | |
d2d65408 VS |
5141 | if (intel_crtc->config->has_pch_encoder) |
5142 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5143 | false); | |
5144 | ||
8807e55b JN |
5145 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5146 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5147 | encoder->disable(encoder); |
8807e55b | 5148 | } |
4f771f10 | 5149 | |
f9b61ff6 DV |
5150 | drm_crtc_vblank_off(crtc); |
5151 | assert_vblank_disabled(crtc); | |
5152 | ||
575f7ab7 | 5153 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5154 | |
6e3c9717 | 5155 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5156 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5157 | ||
a65347ba | 5158 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5159 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5160 | |
1c132b44 | 5161 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5162 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5163 | else |
bfd16b2a | 5164 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5165 | |
a65347ba | 5166 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5167 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5168 | |
97b040aa ID |
5169 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5170 | if (encoder->post_disable) | |
5171 | encoder->post_disable(encoder); | |
81b088ca | 5172 | |
92966a37 VS |
5173 | if (intel_crtc->config->has_pch_encoder) { |
5174 | lpt_disable_pch_transcoder(dev_priv); | |
503a74e9 | 5175 | lpt_disable_iclkip(dev_priv); |
92966a37 VS |
5176 | intel_ddi_fdi_disable(crtc); |
5177 | ||
81b088ca VS |
5178 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5179 | true); | |
92966a37 | 5180 | } |
d029bcad PZ |
5181 | |
5182 | intel_fbc_disable_crtc(intel_crtc); | |
4f771f10 PZ |
5183 | } |
5184 | ||
2dd24552 JB |
5185 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5186 | { | |
5187 | struct drm_device *dev = crtc->base.dev; | |
5188 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 5189 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5190 | |
681a8504 | 5191 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5192 | return; |
5193 | ||
2dd24552 | 5194 | /* |
c0b03411 DV |
5195 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5196 | * according to register description and PRM. | |
2dd24552 | 5197 | */ |
c0b03411 DV |
5198 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5199 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5200 | |
b074cec8 JB |
5201 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5202 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5203 | |
5204 | /* Border color in case we don't scale up to the full screen. Black by | |
5205 | * default, change to something else for debugging. */ | |
5206 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5207 | } |
5208 | ||
d05410f9 DA |
5209 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5210 | { | |
5211 | switch (port) { | |
5212 | case PORT_A: | |
6331a704 | 5213 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5214 | case PORT_B: |
6331a704 | 5215 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5216 | case PORT_C: |
6331a704 | 5217 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5218 | case PORT_D: |
6331a704 | 5219 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5220 | case PORT_E: |
6331a704 | 5221 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5222 | default: |
b9fec167 | 5223 | MISSING_CASE(port); |
d05410f9 DA |
5224 | return POWER_DOMAIN_PORT_OTHER; |
5225 | } | |
5226 | } | |
5227 | ||
25f78f58 VS |
5228 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
5229 | { | |
5230 | switch (port) { | |
5231 | case PORT_A: | |
5232 | return POWER_DOMAIN_AUX_A; | |
5233 | case PORT_B: | |
5234 | return POWER_DOMAIN_AUX_B; | |
5235 | case PORT_C: | |
5236 | return POWER_DOMAIN_AUX_C; | |
5237 | case PORT_D: | |
5238 | return POWER_DOMAIN_AUX_D; | |
5239 | case PORT_E: | |
5240 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5241 | return POWER_DOMAIN_AUX_D; | |
5242 | default: | |
b9fec167 | 5243 | MISSING_CASE(port); |
25f78f58 VS |
5244 | return POWER_DOMAIN_AUX_A; |
5245 | } | |
5246 | } | |
5247 | ||
319be8ae ID |
5248 | enum intel_display_power_domain |
5249 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5250 | { | |
5251 | struct drm_device *dev = intel_encoder->base.dev; | |
5252 | struct intel_digital_port *intel_dig_port; | |
5253 | ||
5254 | switch (intel_encoder->type) { | |
5255 | case INTEL_OUTPUT_UNKNOWN: | |
5256 | /* Only DDI platforms should ever use this output type */ | |
5257 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5258 | case INTEL_OUTPUT_DISPLAYPORT: | |
5259 | case INTEL_OUTPUT_HDMI: | |
5260 | case INTEL_OUTPUT_EDP: | |
5261 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5262 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5263 | case INTEL_OUTPUT_DP_MST: |
5264 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5265 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5266 | case INTEL_OUTPUT_ANALOG: |
5267 | return POWER_DOMAIN_PORT_CRT; | |
5268 | case INTEL_OUTPUT_DSI: | |
5269 | return POWER_DOMAIN_PORT_DSI; | |
5270 | default: | |
5271 | return POWER_DOMAIN_PORT_OTHER; | |
5272 | } | |
5273 | } | |
5274 | ||
25f78f58 VS |
5275 | enum intel_display_power_domain |
5276 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) | |
5277 | { | |
5278 | struct drm_device *dev = intel_encoder->base.dev; | |
5279 | struct intel_digital_port *intel_dig_port; | |
5280 | ||
5281 | switch (intel_encoder->type) { | |
5282 | case INTEL_OUTPUT_UNKNOWN: | |
651174a4 ID |
5283 | case INTEL_OUTPUT_HDMI: |
5284 | /* | |
5285 | * Only DDI platforms should ever use these output types. | |
5286 | * We can get here after the HDMI detect code has already set | |
5287 | * the type of the shared encoder. Since we can't be sure | |
5288 | * what's the status of the given connectors, play safe and | |
5289 | * run the DP detection too. | |
5290 | */ | |
25f78f58 VS |
5291 | WARN_ON_ONCE(!HAS_DDI(dev)); |
5292 | case INTEL_OUTPUT_DISPLAYPORT: | |
5293 | case INTEL_OUTPUT_EDP: | |
5294 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
5295 | return port_to_aux_power_domain(intel_dig_port->port); | |
5296 | case INTEL_OUTPUT_DP_MST: | |
5297 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5298 | return port_to_aux_power_domain(intel_dig_port->port); | |
5299 | default: | |
b9fec167 | 5300 | MISSING_CASE(intel_encoder->type); |
25f78f58 VS |
5301 | return POWER_DOMAIN_AUX_A; |
5302 | } | |
5303 | } | |
5304 | ||
319be8ae | 5305 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) |
77d22dca | 5306 | { |
319be8ae ID |
5307 | struct drm_device *dev = crtc->dev; |
5308 | struct intel_encoder *intel_encoder; | |
5309 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5310 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca | 5311 | unsigned long mask; |
1a70a728 | 5312 | enum transcoder transcoder = intel_crtc->config->cpu_transcoder; |
77d22dca | 5313 | |
292b990e ML |
5314 | if (!crtc->state->active) |
5315 | return 0; | |
5316 | ||
77d22dca ID |
5317 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5318 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
6e3c9717 ACO |
5319 | if (intel_crtc->config->pch_pfit.enabled || |
5320 | intel_crtc->config->pch_pfit.force_thru) | |
77d22dca ID |
5321 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5322 | ||
319be8ae ID |
5323 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
5324 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
5325 | ||
77d22dca ID |
5326 | return mask; |
5327 | } | |
5328 | ||
292b990e | 5329 | static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc) |
77d22dca | 5330 | { |
292b990e ML |
5331 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5332 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5333 | enum intel_display_power_domain domain; | |
5334 | unsigned long domains, new_domains, old_domains; | |
77d22dca | 5335 | |
292b990e ML |
5336 | old_domains = intel_crtc->enabled_power_domains; |
5337 | intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc); | |
77d22dca | 5338 | |
292b990e ML |
5339 | domains = new_domains & ~old_domains; |
5340 | ||
5341 | for_each_power_domain(domain, domains) | |
5342 | intel_display_power_get(dev_priv, domain); | |
5343 | ||
5344 | return old_domains & ~new_domains; | |
5345 | } | |
5346 | ||
5347 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5348 | unsigned long domains) | |
5349 | { | |
5350 | enum intel_display_power_domain domain; | |
5351 | ||
5352 | for_each_power_domain(domain, domains) | |
5353 | intel_display_power_put(dev_priv, domain); | |
5354 | } | |
77d22dca | 5355 | |
292b990e ML |
5356 | static void modeset_update_crtc_power_domains(struct drm_atomic_state *state) |
5357 | { | |
5358 | struct drm_device *dev = state->dev; | |
5359 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5360 | unsigned long put_domains[I915_MAX_PIPES] = {}; | |
5361 | struct drm_crtc_state *crtc_state; | |
5362 | struct drm_crtc *crtc; | |
5363 | int i; | |
77d22dca | 5364 | |
292b990e ML |
5365 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
5366 | if (needs_modeset(crtc->state)) | |
5367 | put_domains[to_intel_crtc(crtc)->pipe] = | |
5368 | modeset_get_crtc_power_domains(crtc); | |
77d22dca ID |
5369 | } |
5370 | ||
27c329ed ML |
5371 | if (dev_priv->display.modeset_commit_cdclk) { |
5372 | unsigned int cdclk = to_intel_atomic_state(state)->cdclk; | |
5373 | ||
5374 | if (cdclk != dev_priv->cdclk_freq && | |
5375 | !WARN_ON(!state->allow_modeset)) | |
5376 | dev_priv->display.modeset_commit_cdclk(state); | |
5377 | } | |
50f6e502 | 5378 | |
292b990e ML |
5379 | for (i = 0; i < I915_MAX_PIPES; i++) |
5380 | if (put_domains[i]) | |
5381 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
77d22dca ID |
5382 | } |
5383 | ||
adafdc6f MK |
5384 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5385 | { | |
5386 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5387 | ||
5388 | if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5389 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
5390 | return max_cdclk_freq; | |
5391 | else if (IS_CHERRYVIEW(dev_priv)) | |
5392 | return max_cdclk_freq*95/100; | |
5393 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5394 | return 2*max_cdclk_freq*90/100; | |
5395 | else | |
5396 | return max_cdclk_freq*90/100; | |
5397 | } | |
5398 | ||
560a7ae4 DL |
5399 | static void intel_update_max_cdclk(struct drm_device *dev) |
5400 | { | |
5401 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5402 | ||
ef11bdb3 | 5403 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
560a7ae4 DL |
5404 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
5405 | ||
5406 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) | |
5407 | dev_priv->max_cdclk_freq = 675000; | |
5408 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) | |
5409 | dev_priv->max_cdclk_freq = 540000; | |
5410 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) | |
5411 | dev_priv->max_cdclk_freq = 450000; | |
5412 | else | |
5413 | dev_priv->max_cdclk_freq = 337500; | |
5414 | } else if (IS_BROADWELL(dev)) { | |
5415 | /* | |
5416 | * FIXME with extra cooling we can allow | |
5417 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5418 | * How can we know if extra cooling is | |
5419 | * available? PCI ID, VTB, something else? | |
5420 | */ | |
5421 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5422 | dev_priv->max_cdclk_freq = 450000; | |
5423 | else if (IS_BDW_ULX(dev)) | |
5424 | dev_priv->max_cdclk_freq = 450000; | |
5425 | else if (IS_BDW_ULT(dev)) | |
5426 | dev_priv->max_cdclk_freq = 540000; | |
5427 | else | |
5428 | dev_priv->max_cdclk_freq = 675000; | |
0904deaf MK |
5429 | } else if (IS_CHERRYVIEW(dev)) { |
5430 | dev_priv->max_cdclk_freq = 320000; | |
560a7ae4 DL |
5431 | } else if (IS_VALLEYVIEW(dev)) { |
5432 | dev_priv->max_cdclk_freq = 400000; | |
5433 | } else { | |
5434 | /* otherwise assume cdclk is fixed */ | |
5435 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5436 | } | |
5437 | ||
adafdc6f MK |
5438 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5439 | ||
560a7ae4 DL |
5440 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5441 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5442 | |
5443 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5444 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5445 | } |
5446 | ||
5447 | static void intel_update_cdclk(struct drm_device *dev) | |
5448 | { | |
5449 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5450 | ||
5451 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
5452 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5453 | dev_priv->cdclk_freq); | |
5454 | ||
5455 | /* | |
5456 | * Program the gmbus_freq based on the cdclk frequency. | |
5457 | * BSpec erroneously claims we should aim for 4MHz, but | |
5458 | * in fact 1MHz is the correct frequency. | |
5459 | */ | |
666a4537 | 5460 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
560a7ae4 DL |
5461 | /* |
5462 | * Program the gmbus_freq based on the cdclk frequency. | |
5463 | * BSpec erroneously claims we should aim for 4MHz, but | |
5464 | * in fact 1MHz is the correct frequency. | |
5465 | */ | |
5466 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); | |
5467 | } | |
5468 | ||
5469 | if (dev_priv->max_cdclk_freq == 0) | |
5470 | intel_update_max_cdclk(dev); | |
5471 | } | |
5472 | ||
70d0c574 | 5473 | static void broxton_set_cdclk(struct drm_device *dev, int frequency) |
f8437dd1 VK |
5474 | { |
5475 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5476 | uint32_t divider; | |
5477 | uint32_t ratio; | |
5478 | uint32_t current_freq; | |
5479 | int ret; | |
5480 | ||
5481 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ | |
5482 | switch (frequency) { | |
5483 | case 144000: | |
5484 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
5485 | ratio = BXT_DE_PLL_RATIO(60); | |
5486 | break; | |
5487 | case 288000: | |
5488 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
5489 | ratio = BXT_DE_PLL_RATIO(60); | |
5490 | break; | |
5491 | case 384000: | |
5492 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
5493 | ratio = BXT_DE_PLL_RATIO(60); | |
5494 | break; | |
5495 | case 576000: | |
5496 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5497 | ratio = BXT_DE_PLL_RATIO(60); | |
5498 | break; | |
5499 | case 624000: | |
5500 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5501 | ratio = BXT_DE_PLL_RATIO(65); | |
5502 | break; | |
5503 | case 19200: | |
5504 | /* | |
5505 | * Bypass frequency with DE PLL disabled. Init ratio, divider | |
5506 | * to suppress GCC warning. | |
5507 | */ | |
5508 | ratio = 0; | |
5509 | divider = 0; | |
5510 | break; | |
5511 | default: | |
5512 | DRM_ERROR("unsupported CDCLK freq %d", frequency); | |
5513 | ||
5514 | return; | |
5515 | } | |
5516 | ||
5517 | mutex_lock(&dev_priv->rps.hw_lock); | |
5518 | /* Inform power controller of upcoming frequency change */ | |
5519 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5520 | 0x80000000); | |
5521 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5522 | ||
5523 | if (ret) { | |
5524 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
5525 | ret, frequency); | |
5526 | return; | |
5527 | } | |
5528 | ||
5529 | current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; | |
5530 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ | |
5531 | current_freq = current_freq * 500 + 1000; | |
5532 | ||
5533 | /* | |
5534 | * DE PLL has to be disabled when | |
5535 | * - setting to 19.2MHz (bypass, PLL isn't used) | |
5536 | * - before setting to 624MHz (PLL needs toggling) | |
5537 | * - before setting to any frequency from 624MHz (PLL needs toggling) | |
5538 | */ | |
5539 | if (frequency == 19200 || frequency == 624000 || | |
5540 | current_freq == 624000) { | |
5541 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); | |
5542 | /* Timeout 200us */ | |
5543 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), | |
5544 | 1)) | |
5545 | DRM_ERROR("timout waiting for DE PLL unlock\n"); | |
5546 | } | |
5547 | ||
5548 | if (frequency != 19200) { | |
5549 | uint32_t val; | |
5550 | ||
5551 | val = I915_READ(BXT_DE_PLL_CTL); | |
5552 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5553 | val |= ratio; | |
5554 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
5555 | ||
5556 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5557 | /* Timeout 200us */ | |
5558 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) | |
5559 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
5560 | ||
5561 | val = I915_READ(CDCLK_CTL); | |
5562 | val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
5563 | val |= divider; | |
5564 | /* | |
5565 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5566 | * enable otherwise. | |
5567 | */ | |
5568 | val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5569 | if (frequency >= 500000) | |
5570 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5571 | ||
5572 | val &= ~CDCLK_FREQ_DECIMAL_MASK; | |
5573 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
5574 | val |= (frequency - 1000) / 500; | |
5575 | I915_WRITE(CDCLK_CTL, val); | |
5576 | } | |
5577 | ||
5578 | mutex_lock(&dev_priv->rps.hw_lock); | |
5579 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5580 | DIV_ROUND_UP(frequency, 25000)); | |
5581 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5582 | ||
5583 | if (ret) { | |
5584 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
5585 | ret, frequency); | |
5586 | return; | |
5587 | } | |
5588 | ||
a47871bd | 5589 | intel_update_cdclk(dev); |
f8437dd1 VK |
5590 | } |
5591 | ||
5592 | void broxton_init_cdclk(struct drm_device *dev) | |
5593 | { | |
5594 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5595 | uint32_t val; | |
5596 | ||
5597 | /* | |
5598 | * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT | |
5599 | * or else the reset will hang because there is no PCH to respond. | |
5600 | * Move the handshake programming to initialization sequence. | |
5601 | * Previously was left up to BIOS. | |
5602 | */ | |
5603 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5604 | val &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
5605 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val); | |
5606 | ||
5607 | /* Enable PG1 for cdclk */ | |
5608 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5609 | ||
5610 | /* check if cd clock is enabled */ | |
5611 | if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { | |
5612 | DRM_DEBUG_KMS("Display already initialized\n"); | |
5613 | return; | |
5614 | } | |
5615 | ||
5616 | /* | |
5617 | * FIXME: | |
5618 | * - The initial CDCLK needs to be read from VBT. | |
5619 | * Need to make this change after VBT has changes for BXT. | |
5620 | * - check if setting the max (or any) cdclk freq is really necessary | |
5621 | * here, it belongs to modeset time | |
5622 | */ | |
5623 | broxton_set_cdclk(dev, 624000); | |
5624 | ||
5625 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
22e02c0b VS |
5626 | POSTING_READ(DBUF_CTL); |
5627 | ||
f8437dd1 VK |
5628 | udelay(10); |
5629 | ||
5630 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5631 | DRM_ERROR("DBuf power enable timeout!\n"); | |
5632 | } | |
5633 | ||
5634 | void broxton_uninit_cdclk(struct drm_device *dev) | |
5635 | { | |
5636 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5637 | ||
5638 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
22e02c0b VS |
5639 | POSTING_READ(DBUF_CTL); |
5640 | ||
f8437dd1 VK |
5641 | udelay(10); |
5642 | ||
5643 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5644 | DRM_ERROR("DBuf power disable timeout!\n"); | |
5645 | ||
5646 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ | |
5647 | broxton_set_cdclk(dev, 19200); | |
5648 | ||
5649 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5650 | } | |
5651 | ||
5d96d8af DL |
5652 | static const struct skl_cdclk_entry { |
5653 | unsigned int freq; | |
5654 | unsigned int vco; | |
5655 | } skl_cdclk_frequencies[] = { | |
5656 | { .freq = 308570, .vco = 8640 }, | |
5657 | { .freq = 337500, .vco = 8100 }, | |
5658 | { .freq = 432000, .vco = 8640 }, | |
5659 | { .freq = 450000, .vco = 8100 }, | |
5660 | { .freq = 540000, .vco = 8100 }, | |
5661 | { .freq = 617140, .vco = 8640 }, | |
5662 | { .freq = 675000, .vco = 8100 }, | |
5663 | }; | |
5664 | ||
5665 | static unsigned int skl_cdclk_decimal(unsigned int freq) | |
5666 | { | |
5667 | return (freq - 1000) / 500; | |
5668 | } | |
5669 | ||
5670 | static unsigned int skl_cdclk_get_vco(unsigned int freq) | |
5671 | { | |
5672 | unsigned int i; | |
5673 | ||
5674 | for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) { | |
5675 | const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i]; | |
5676 | ||
5677 | if (e->freq == freq) | |
5678 | return e->vco; | |
5679 | } | |
5680 | ||
5681 | return 8100; | |
5682 | } | |
5683 | ||
5684 | static void | |
5685 | skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco) | |
5686 | { | |
5687 | unsigned int min_freq; | |
5688 | u32 val; | |
5689 | ||
5690 | /* select the minimum CDCLK before enabling DPLL 0 */ | |
5691 | val = I915_READ(CDCLK_CTL); | |
5692 | val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK; | |
5693 | val |= CDCLK_FREQ_337_308; | |
5694 | ||
5695 | if (required_vco == 8640) | |
5696 | min_freq = 308570; | |
5697 | else | |
5698 | min_freq = 337500; | |
5699 | ||
5700 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq); | |
5701 | ||
5702 | I915_WRITE(CDCLK_CTL, val); | |
5703 | POSTING_READ(CDCLK_CTL); | |
5704 | ||
5705 | /* | |
5706 | * We always enable DPLL0 with the lowest link rate possible, but still | |
5707 | * taking into account the VCO required to operate the eDP panel at the | |
5708 | * desired frequency. The usual DP link rates operate with a VCO of | |
5709 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
5710 | * The modeset code is responsible for the selection of the exact link | |
5711 | * rate later on, with the constraint of choosing a frequency that | |
5712 | * works with required_vco. | |
5713 | */ | |
5714 | val = I915_READ(DPLL_CTRL1); | |
5715 | ||
5716 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5717 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
5718 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
5719 | if (required_vco == 8640) | |
5720 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, | |
5721 | SKL_DPLL0); | |
5722 | else | |
5723 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
5724 | SKL_DPLL0); | |
5725 | ||
5726 | I915_WRITE(DPLL_CTRL1, val); | |
5727 | POSTING_READ(DPLL_CTRL1); | |
5728 | ||
5729 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
5730 | ||
5731 | if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) | |
5732 | DRM_ERROR("DPLL0 not locked\n"); | |
5733 | } | |
5734 | ||
5735 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) | |
5736 | { | |
5737 | int ret; | |
5738 | u32 val; | |
5739 | ||
5740 | /* inform PCU we want to change CDCLK */ | |
5741 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
5742 | mutex_lock(&dev_priv->rps.hw_lock); | |
5743 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
5744 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5745 | ||
5746 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
5747 | } | |
5748 | ||
5749 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
5750 | { | |
5751 | unsigned int i; | |
5752 | ||
5753 | for (i = 0; i < 15; i++) { | |
5754 | if (skl_cdclk_pcu_ready(dev_priv)) | |
5755 | return true; | |
5756 | udelay(10); | |
5757 | } | |
5758 | ||
5759 | return false; | |
5760 | } | |
5761 | ||
5762 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq) | |
5763 | { | |
560a7ae4 | 5764 | struct drm_device *dev = dev_priv->dev; |
5d96d8af DL |
5765 | u32 freq_select, pcu_ack; |
5766 | ||
5767 | DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq); | |
5768 | ||
5769 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
5770 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
5771 | return; | |
5772 | } | |
5773 | ||
5774 | /* set CDCLK_CTL */ | |
5775 | switch(freq) { | |
5776 | case 450000: | |
5777 | case 432000: | |
5778 | freq_select = CDCLK_FREQ_450_432; | |
5779 | pcu_ack = 1; | |
5780 | break; | |
5781 | case 540000: | |
5782 | freq_select = CDCLK_FREQ_540; | |
5783 | pcu_ack = 2; | |
5784 | break; | |
5785 | case 308570: | |
5786 | case 337500: | |
5787 | default: | |
5788 | freq_select = CDCLK_FREQ_337_308; | |
5789 | pcu_ack = 0; | |
5790 | break; | |
5791 | case 617140: | |
5792 | case 675000: | |
5793 | freq_select = CDCLK_FREQ_675_617; | |
5794 | pcu_ack = 3; | |
5795 | break; | |
5796 | } | |
5797 | ||
5798 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq)); | |
5799 | POSTING_READ(CDCLK_CTL); | |
5800 | ||
5801 | /* inform PCU of the change */ | |
5802 | mutex_lock(&dev_priv->rps.hw_lock); | |
5803 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
5804 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 DL |
5805 | |
5806 | intel_update_cdclk(dev); | |
5d96d8af DL |
5807 | } |
5808 | ||
5809 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
5810 | { | |
5811 | /* disable DBUF power */ | |
5812 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
5813 | POSTING_READ(DBUF_CTL); | |
5814 | ||
5815 | udelay(10); | |
5816 | ||
5817 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5818 | DRM_ERROR("DBuf power disable timeout\n"); | |
5819 | ||
ab96c1ee ID |
5820 | /* disable DPLL0 */ |
5821 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
5822 | if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) | |
5823 | DRM_ERROR("Couldn't disable DPLL0\n"); | |
5d96d8af DL |
5824 | } |
5825 | ||
5826 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
5827 | { | |
5d96d8af DL |
5828 | unsigned int required_vco; |
5829 | ||
39d9b85a GW |
5830 | /* DPLL0 not enabled (happens on early BIOS versions) */ |
5831 | if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) { | |
5832 | /* enable DPLL0 */ | |
5833 | required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); | |
5834 | skl_dpll0_enable(dev_priv, required_vco); | |
5d96d8af DL |
5835 | } |
5836 | ||
5d96d8af DL |
5837 | /* set CDCLK to the frequency the BIOS chose */ |
5838 | skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); | |
5839 | ||
5840 | /* enable DBUF power */ | |
5841 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
5842 | POSTING_READ(DBUF_CTL); | |
5843 | ||
5844 | udelay(10); | |
5845 | ||
5846 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5847 | DRM_ERROR("DBuf power enable timeout\n"); | |
5848 | } | |
5849 | ||
c73666f3 SK |
5850 | int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
5851 | { | |
5852 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
5853 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
5854 | int freq = dev_priv->skl_boot_cdclk; | |
5855 | ||
f1b391a5 SK |
5856 | /* |
5857 | * check if the pre-os intialized the display | |
5858 | * There is SWF18 scratchpad register defined which is set by the | |
5859 | * pre-os which can be used by the OS drivers to check the status | |
5860 | */ | |
5861 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
5862 | goto sanitize; | |
5863 | ||
c73666f3 SK |
5864 | /* Is PLL enabled and locked ? */ |
5865 | if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK))) | |
5866 | goto sanitize; | |
5867 | ||
5868 | /* DPLL okay; verify the cdclock | |
5869 | * | |
5870 | * Noticed in some instances that the freq selection is correct but | |
5871 | * decimal part is programmed wrong from BIOS where pre-os does not | |
5872 | * enable display. Verify the same as well. | |
5873 | */ | |
5874 | if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq))) | |
5875 | /* All well; nothing to sanitize */ | |
5876 | return false; | |
5877 | sanitize: | |
5878 | /* | |
5879 | * As of now initialize with max cdclk till | |
5880 | * we get dynamic cdclk support | |
5881 | * */ | |
5882 | dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq; | |
5883 | skl_init_cdclk(dev_priv); | |
5884 | ||
5885 | /* we did have to sanitize */ | |
5886 | return true; | |
5887 | } | |
5888 | ||
30a970c6 JB |
5889 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5890 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5891 | { | |
5892 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5893 | u32 val, cmd; | |
5894 | ||
164dfd28 VK |
5895 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5896 | != dev_priv->cdclk_freq); | |
d60c4473 | 5897 | |
dfcab17e | 5898 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5899 | cmd = 2; |
dfcab17e | 5900 | else if (cdclk == 266667) |
30a970c6 JB |
5901 | cmd = 1; |
5902 | else | |
5903 | cmd = 0; | |
5904 | ||
5905 | mutex_lock(&dev_priv->rps.hw_lock); | |
5906 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5907 | val &= ~DSPFREQGUAR_MASK; | |
5908 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5909 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5910 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5911 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5912 | 50)) { | |
5913 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5914 | } | |
5915 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5916 | ||
54433e91 VS |
5917 | mutex_lock(&dev_priv->sb_lock); |
5918 | ||
dfcab17e | 5919 | if (cdclk == 400000) { |
6bcda4f0 | 5920 | u32 divider; |
30a970c6 | 5921 | |
6bcda4f0 | 5922 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 5923 | |
30a970c6 JB |
5924 | /* adjust cdclk divider */ |
5925 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
87d5d259 | 5926 | val &= ~CCK_FREQUENCY_VALUES; |
30a970c6 JB |
5927 | val |= divider; |
5928 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5929 | |
5930 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
87d5d259 | 5931 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
a877e801 VS |
5932 | 50)) |
5933 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5934 | } |
5935 | ||
30a970c6 JB |
5936 | /* adjust self-refresh exit latency value */ |
5937 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5938 | val &= ~0x7f; | |
5939 | ||
5940 | /* | |
5941 | * For high bandwidth configs, we set a higher latency in the bunit | |
5942 | * so that the core display fetch happens in time to avoid underruns. | |
5943 | */ | |
dfcab17e | 5944 | if (cdclk == 400000) |
30a970c6 JB |
5945 | val |= 4500 / 250; /* 4.5 usec */ |
5946 | else | |
5947 | val |= 3000 / 250; /* 3.0 usec */ | |
5948 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 5949 | |
a580516d | 5950 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5951 | |
b6283055 | 5952 | intel_update_cdclk(dev); |
30a970c6 JB |
5953 | } |
5954 | ||
383c5a6a VS |
5955 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5956 | { | |
5957 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5958 | u32 val, cmd; | |
5959 | ||
164dfd28 VK |
5960 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5961 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5962 | |
5963 | switch (cdclk) { | |
383c5a6a VS |
5964 | case 333333: |
5965 | case 320000: | |
383c5a6a | 5966 | case 266667: |
383c5a6a | 5967 | case 200000: |
383c5a6a VS |
5968 | break; |
5969 | default: | |
5f77eeb0 | 5970 | MISSING_CASE(cdclk); |
383c5a6a VS |
5971 | return; |
5972 | } | |
5973 | ||
9d0d3fda VS |
5974 | /* |
5975 | * Specs are full of misinformation, but testing on actual | |
5976 | * hardware has shown that we just need to write the desired | |
5977 | * CCK divider into the Punit register. | |
5978 | */ | |
5979 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5980 | ||
383c5a6a VS |
5981 | mutex_lock(&dev_priv->rps.hw_lock); |
5982 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5983 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5984 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5985 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5986 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5987 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5988 | 50)) { | |
5989 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5990 | } | |
5991 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5992 | ||
b6283055 | 5993 | intel_update_cdclk(dev); |
383c5a6a VS |
5994 | } |
5995 | ||
30a970c6 JB |
5996 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5997 | int max_pixclk) | |
5998 | { | |
6bcda4f0 | 5999 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 6000 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 6001 | |
30a970c6 JB |
6002 | /* |
6003 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
6004 | * 200MHz | |
6005 | * 267MHz | |
29dc7ef3 | 6006 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
6007 | * 400MHz (VLV only) |
6008 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
6009 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
6010 | * |
6011 | * We seem to get an unstable or solid color picture at 200MHz. | |
6012 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
6013 | * are off. | |
30a970c6 | 6014 | */ |
6cca3195 VS |
6015 | if (!IS_CHERRYVIEW(dev_priv) && |
6016 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 6017 | return 400000; |
6cca3195 | 6018 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 6019 | return freq_320; |
e37c67a1 | 6020 | else if (max_pixclk > 0) |
dfcab17e | 6021 | return 266667; |
e37c67a1 VS |
6022 | else |
6023 | return 200000; | |
30a970c6 JB |
6024 | } |
6025 | ||
f8437dd1 VK |
6026 | static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, |
6027 | int max_pixclk) | |
6028 | { | |
6029 | /* | |
6030 | * FIXME: | |
6031 | * - remove the guardband, it's not needed on BXT | |
6032 | * - set 19.2MHz bypass frequency if there are no active pipes | |
6033 | */ | |
6034 | if (max_pixclk > 576000*9/10) | |
6035 | return 624000; | |
6036 | else if (max_pixclk > 384000*9/10) | |
6037 | return 576000; | |
6038 | else if (max_pixclk > 288000*9/10) | |
6039 | return 384000; | |
6040 | else if (max_pixclk > 144000*9/10) | |
6041 | return 288000; | |
6042 | else | |
6043 | return 144000; | |
6044 | } | |
6045 | ||
a821fc46 ACO |
6046 | /* Compute the max pixel clock for new configuration. Uses atomic state if |
6047 | * that's non-NULL, look at current state otherwise. */ | |
6048 | static int intel_mode_max_pixclk(struct drm_device *dev, | |
6049 | struct drm_atomic_state *state) | |
30a970c6 | 6050 | { |
30a970c6 | 6051 | struct intel_crtc *intel_crtc; |
304603f4 | 6052 | struct intel_crtc_state *crtc_state; |
30a970c6 JB |
6053 | int max_pixclk = 0; |
6054 | ||
d3fcc808 | 6055 | for_each_intel_crtc(dev, intel_crtc) { |
27c329ed | 6056 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
304603f4 ACO |
6057 | if (IS_ERR(crtc_state)) |
6058 | return PTR_ERR(crtc_state); | |
6059 | ||
6060 | if (!crtc_state->base.enable) | |
6061 | continue; | |
6062 | ||
6063 | max_pixclk = max(max_pixclk, | |
6064 | crtc_state->base.adjusted_mode.crtc_clock); | |
30a970c6 JB |
6065 | } |
6066 | ||
6067 | return max_pixclk; | |
6068 | } | |
6069 | ||
27c329ed | 6070 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 6071 | { |
27c329ed ML |
6072 | struct drm_device *dev = state->dev; |
6073 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6074 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
30a970c6 | 6075 | |
304603f4 ACO |
6076 | if (max_pixclk < 0) |
6077 | return max_pixclk; | |
30a970c6 | 6078 | |
27c329ed ML |
6079 | to_intel_atomic_state(state)->cdclk = |
6080 | valleyview_calc_cdclk(dev_priv, max_pixclk); | |
0a9ab303 | 6081 | |
27c329ed ML |
6082 | return 0; |
6083 | } | |
304603f4 | 6084 | |
27c329ed ML |
6085 | static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state) |
6086 | { | |
6087 | struct drm_device *dev = state->dev; | |
6088 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6089 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
85a96e7a | 6090 | |
27c329ed ML |
6091 | if (max_pixclk < 0) |
6092 | return max_pixclk; | |
85a96e7a | 6093 | |
27c329ed ML |
6094 | to_intel_atomic_state(state)->cdclk = |
6095 | broxton_calc_cdclk(dev_priv, max_pixclk); | |
85a96e7a | 6096 | |
27c329ed | 6097 | return 0; |
30a970c6 JB |
6098 | } |
6099 | ||
1e69cd74 VS |
6100 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
6101 | { | |
6102 | unsigned int credits, default_credits; | |
6103 | ||
6104 | if (IS_CHERRYVIEW(dev_priv)) | |
6105 | default_credits = PFI_CREDIT(12); | |
6106 | else | |
6107 | default_credits = PFI_CREDIT(8); | |
6108 | ||
bfa7df01 | 6109 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
1e69cd74 VS |
6110 | /* CHV suggested value is 31 or 63 */ |
6111 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 6112 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
6113 | else |
6114 | credits = PFI_CREDIT(15); | |
6115 | } else { | |
6116 | credits = default_credits; | |
6117 | } | |
6118 | ||
6119 | /* | |
6120 | * WA - write default credits before re-programming | |
6121 | * FIXME: should we also set the resend bit here? | |
6122 | */ | |
6123 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6124 | default_credits); | |
6125 | ||
6126 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6127 | credits | PFI_CREDIT_RESEND); | |
6128 | ||
6129 | /* | |
6130 | * FIXME is this guaranteed to clear | |
6131 | * immediately or should we poll for it? | |
6132 | */ | |
6133 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6134 | } | |
6135 | ||
27c329ed | 6136 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 6137 | { |
a821fc46 | 6138 | struct drm_device *dev = old_state->dev; |
27c329ed | 6139 | unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk; |
30a970c6 | 6140 | struct drm_i915_private *dev_priv = dev->dev_private; |
30a970c6 | 6141 | |
27c329ed ML |
6142 | /* |
6143 | * FIXME: We can end up here with all power domains off, yet | |
6144 | * with a CDCLK frequency other than the minimum. To account | |
6145 | * for this take the PIPE-A power domain, which covers the HW | |
6146 | * blocks needed for the following programming. This can be | |
6147 | * removed once it's guaranteed that we get here either with | |
6148 | * the minimum CDCLK set, or the required power domains | |
6149 | * enabled. | |
6150 | */ | |
6151 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6152 | |
27c329ed ML |
6153 | if (IS_CHERRYVIEW(dev)) |
6154 | cherryview_set_cdclk(dev, req_cdclk); | |
6155 | else | |
6156 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6157 | |
27c329ed | 6158 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6159 | |
27c329ed | 6160 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6161 | } |
6162 | ||
89b667f8 JB |
6163 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
6164 | { | |
6165 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6166 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
6167 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6168 | struct intel_encoder *encoder; | |
6169 | int pipe = intel_crtc->pipe; | |
89b667f8 | 6170 | |
53d9f4e9 | 6171 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6172 | return; |
6173 | ||
6e3c9717 | 6174 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6175 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6176 | |
6177 | intel_set_pipe_timings(intel_crtc); | |
6178 | ||
c14b0485 VS |
6179 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
6180 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6181 | ||
6182 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6183 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6184 | } | |
6185 | ||
5b18e57c DV |
6186 | i9xx_set_pipeconf(intel_crtc); |
6187 | ||
89b667f8 | 6188 | intel_crtc->active = true; |
89b667f8 | 6189 | |
a72e4c9f | 6190 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6191 | |
89b667f8 JB |
6192 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6193 | if (encoder->pre_pll_enable) | |
6194 | encoder->pre_pll_enable(encoder); | |
6195 | ||
a65347ba | 6196 | if (!intel_crtc->config->has_dsi_encoder) { |
c0b4c660 VS |
6197 | if (IS_CHERRYVIEW(dev)) { |
6198 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6199 | chv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 VS |
6200 | } else { |
6201 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6202 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 | 6203 | } |
9d556c99 | 6204 | } |
89b667f8 JB |
6205 | |
6206 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6207 | if (encoder->pre_enable) | |
6208 | encoder->pre_enable(encoder); | |
6209 | ||
2dd24552 JB |
6210 | i9xx_pfit_enable(intel_crtc); |
6211 | ||
63cbb074 VS |
6212 | intel_crtc_load_lut(crtc); |
6213 | ||
e1fdc473 | 6214 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6215 | |
4b3a9526 VS |
6216 | assert_vblank_disabled(crtc); |
6217 | drm_crtc_vblank_on(crtc); | |
6218 | ||
f9b61ff6 DV |
6219 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6220 | encoder->enable(encoder); | |
89b667f8 JB |
6221 | } |
6222 | ||
f13c2ef3 DV |
6223 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6224 | { | |
6225 | struct drm_device *dev = crtc->base.dev; | |
6226 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6227 | ||
6e3c9717 ACO |
6228 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6229 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6230 | } |
6231 | ||
0b8765c6 | 6232 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
6233 | { |
6234 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6235 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6236 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6237 | struct intel_encoder *encoder; |
79e53945 | 6238 | int pipe = intel_crtc->pipe; |
79e53945 | 6239 | |
53d9f4e9 | 6240 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6241 | return; |
6242 | ||
f13c2ef3 DV |
6243 | i9xx_set_pll_dividers(intel_crtc); |
6244 | ||
6e3c9717 | 6245 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6246 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6247 | |
6248 | intel_set_pipe_timings(intel_crtc); | |
6249 | ||
5b18e57c DV |
6250 | i9xx_set_pipeconf(intel_crtc); |
6251 | ||
f7abfe8b | 6252 | intel_crtc->active = true; |
6b383a7f | 6253 | |
4a3436e8 | 6254 | if (!IS_GEN2(dev)) |
a72e4c9f | 6255 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6256 | |
9d6d9f19 MK |
6257 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6258 | if (encoder->pre_enable) | |
6259 | encoder->pre_enable(encoder); | |
6260 | ||
f6736a1a DV |
6261 | i9xx_enable_pll(intel_crtc); |
6262 | ||
2dd24552 JB |
6263 | i9xx_pfit_enable(intel_crtc); |
6264 | ||
63cbb074 VS |
6265 | intel_crtc_load_lut(crtc); |
6266 | ||
f37fcc2a | 6267 | intel_update_watermarks(crtc); |
e1fdc473 | 6268 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6269 | |
4b3a9526 VS |
6270 | assert_vblank_disabled(crtc); |
6271 | drm_crtc_vblank_on(crtc); | |
6272 | ||
f9b61ff6 DV |
6273 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6274 | encoder->enable(encoder); | |
d029bcad PZ |
6275 | |
6276 | intel_fbc_enable(intel_crtc); | |
0b8765c6 | 6277 | } |
79e53945 | 6278 | |
87476d63 DV |
6279 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6280 | { | |
6281 | struct drm_device *dev = crtc->base.dev; | |
6282 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 6283 | |
6e3c9717 | 6284 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6285 | return; |
87476d63 | 6286 | |
328d8e82 | 6287 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6288 | |
328d8e82 DV |
6289 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6290 | I915_READ(PFIT_CONTROL)); | |
6291 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6292 | } |
6293 | ||
0b8765c6 JB |
6294 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6295 | { | |
6296 | struct drm_device *dev = crtc->dev; | |
6297 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6298 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 6299 | struct intel_encoder *encoder; |
0b8765c6 | 6300 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6301 | |
6304cd91 VS |
6302 | /* |
6303 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6304 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
6305 | * We also need to wait on all gmch platforms because of the |
6306 | * self-refresh mode constraint explained above. | |
6304cd91 | 6307 | */ |
564ed191 | 6308 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 6309 | |
4b3a9526 VS |
6310 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6311 | encoder->disable(encoder); | |
6312 | ||
f9b61ff6 DV |
6313 | drm_crtc_vblank_off(crtc); |
6314 | assert_vblank_disabled(crtc); | |
6315 | ||
575f7ab7 | 6316 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6317 | |
87476d63 | 6318 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6319 | |
89b667f8 JB |
6320 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6321 | if (encoder->post_disable) | |
6322 | encoder->post_disable(encoder); | |
6323 | ||
a65347ba | 6324 | if (!intel_crtc->config->has_dsi_encoder) { |
076ed3b2 CML |
6325 | if (IS_CHERRYVIEW(dev)) |
6326 | chv_disable_pll(dev_priv, pipe); | |
6327 | else if (IS_VALLEYVIEW(dev)) | |
6328 | vlv_disable_pll(dev_priv, pipe); | |
6329 | else | |
1c4e0274 | 6330 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6331 | } |
0b8765c6 | 6332 | |
d6db995f VS |
6333 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6334 | if (encoder->post_pll_disable) | |
6335 | encoder->post_pll_disable(encoder); | |
6336 | ||
4a3436e8 | 6337 | if (!IS_GEN2(dev)) |
a72e4c9f | 6338 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
d029bcad PZ |
6339 | |
6340 | intel_fbc_disable_crtc(intel_crtc); | |
0b8765c6 JB |
6341 | } |
6342 | ||
b17d48e2 ML |
6343 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6344 | { | |
6345 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6346 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6347 | enum intel_display_power_domain domain; | |
6348 | unsigned long domains; | |
6349 | ||
6350 | if (!intel_crtc->active) | |
6351 | return; | |
6352 | ||
a539205a | 6353 | if (to_intel_plane_state(crtc->primary->state)->visible) { |
fc32b1fd ML |
6354 | WARN_ON(intel_crtc->unpin_work); |
6355 | ||
a539205a ML |
6356 | intel_pre_disable_primary(crtc); |
6357 | } | |
6358 | ||
d032ffa0 | 6359 | intel_crtc_disable_planes(crtc, crtc->state->plane_mask); |
b17d48e2 | 6360 | dev_priv->display.crtc_disable(crtc); |
37d9078b MR |
6361 | intel_crtc->active = false; |
6362 | intel_update_watermarks(crtc); | |
1f7457b1 | 6363 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6364 | |
6365 | domains = intel_crtc->enabled_power_domains; | |
6366 | for_each_power_domain(domain, domains) | |
6367 | intel_display_power_put(dev_priv, domain); | |
6368 | intel_crtc->enabled_power_domains = 0; | |
6369 | } | |
6370 | ||
6b72d486 ML |
6371 | /* |
6372 | * turn all crtc's off, but do not adjust state | |
6373 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6374 | */ | |
70e0bd74 | 6375 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6376 | { |
70e0bd74 ML |
6377 | struct drm_mode_config *config = &dev->mode_config; |
6378 | struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx; | |
6379 | struct drm_atomic_state *state; | |
6b72d486 | 6380 | struct drm_crtc *crtc; |
70e0bd74 ML |
6381 | unsigned crtc_mask = 0; |
6382 | int ret = 0; | |
6383 | ||
6384 | if (WARN_ON(!ctx)) | |
6385 | return 0; | |
6386 | ||
6387 | lockdep_assert_held(&ctx->ww_ctx); | |
6388 | state = drm_atomic_state_alloc(dev); | |
6389 | if (WARN_ON(!state)) | |
6390 | return -ENOMEM; | |
6391 | ||
6392 | state->acquire_ctx = ctx; | |
6393 | state->allow_modeset = true; | |
6394 | ||
6395 | for_each_crtc(dev, crtc) { | |
6396 | struct drm_crtc_state *crtc_state = | |
6397 | drm_atomic_get_crtc_state(state, crtc); | |
6b72d486 | 6398 | |
70e0bd74 ML |
6399 | ret = PTR_ERR_OR_ZERO(crtc_state); |
6400 | if (ret) | |
6401 | goto free; | |
6402 | ||
6403 | if (!crtc_state->active) | |
6404 | continue; | |
6405 | ||
6406 | crtc_state->active = false; | |
6407 | crtc_mask |= 1 << drm_crtc_index(crtc); | |
6408 | } | |
6409 | ||
6410 | if (crtc_mask) { | |
74c090b1 | 6411 | ret = drm_atomic_commit(state); |
70e0bd74 ML |
6412 | |
6413 | if (!ret) { | |
6414 | for_each_crtc(dev, crtc) | |
6415 | if (crtc_mask & (1 << drm_crtc_index(crtc))) | |
6416 | crtc->state->active = true; | |
6417 | ||
6418 | return ret; | |
6419 | } | |
6420 | } | |
6421 | ||
6422 | free: | |
6423 | if (ret) | |
6424 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
6425 | drm_atomic_state_free(state); | |
6426 | return ret; | |
ee7b9f93 JB |
6427 | } |
6428 | ||
ea5b213a | 6429 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6430 | { |
4ef69c7a | 6431 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6432 | |
ea5b213a CW |
6433 | drm_encoder_cleanup(encoder); |
6434 | kfree(intel_encoder); | |
7e7d76c3 JB |
6435 | } |
6436 | ||
0a91ca29 DV |
6437 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6438 | * internal consistency). */ | |
b980514c | 6439 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 6440 | { |
35dd3c64 ML |
6441 | struct drm_crtc *crtc = connector->base.state->crtc; |
6442 | ||
6443 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6444 | connector->base.base.id, | |
6445 | connector->base.name); | |
6446 | ||
0a91ca29 | 6447 | if (connector->get_hw_state(connector)) { |
e85376cb | 6448 | struct intel_encoder *encoder = connector->encoder; |
35dd3c64 | 6449 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 6450 | |
35dd3c64 ML |
6451 | I915_STATE_WARN(!crtc, |
6452 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6453 | |
35dd3c64 ML |
6454 | if (!crtc) |
6455 | return; | |
6456 | ||
6457 | I915_STATE_WARN(!crtc->state->active, | |
6458 | "connector is active, but attached crtc isn't\n"); | |
6459 | ||
e85376cb | 6460 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6461 | return; |
6462 | ||
e85376cb | 6463 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6464 | "atomic encoder doesn't match attached encoder\n"); |
6465 | ||
e85376cb | 6466 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6467 | "attached encoder crtc differs from connector crtc\n"); |
6468 | } else { | |
4d688a2a ML |
6469 | I915_STATE_WARN(crtc && crtc->state->active, |
6470 | "attached crtc is active, but connector isn't\n"); | |
35dd3c64 ML |
6471 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
6472 | "best encoder set without crtc!\n"); | |
0a91ca29 | 6473 | } |
79e53945 JB |
6474 | } |
6475 | ||
08d9bc92 ACO |
6476 | int intel_connector_init(struct intel_connector *connector) |
6477 | { | |
6478 | struct drm_connector_state *connector_state; | |
6479 | ||
6480 | connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL); | |
6481 | if (!connector_state) | |
6482 | return -ENOMEM; | |
6483 | ||
6484 | connector->base.state = connector_state; | |
6485 | return 0; | |
6486 | } | |
6487 | ||
6488 | struct intel_connector *intel_connector_alloc(void) | |
6489 | { | |
6490 | struct intel_connector *connector; | |
6491 | ||
6492 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6493 | if (!connector) | |
6494 | return NULL; | |
6495 | ||
6496 | if (intel_connector_init(connector) < 0) { | |
6497 | kfree(connector); | |
6498 | return NULL; | |
6499 | } | |
6500 | ||
6501 | return connector; | |
6502 | } | |
6503 | ||
f0947c37 DV |
6504 | /* Simple connector->get_hw_state implementation for encoders that support only |
6505 | * one connector and no cloning and hence the encoder state determines the state | |
6506 | * of the connector. */ | |
6507 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6508 | { |
24929352 | 6509 | enum pipe pipe = 0; |
f0947c37 | 6510 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6511 | |
f0947c37 | 6512 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6513 | } |
6514 | ||
6d293983 | 6515 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6516 | { |
6d293983 ACO |
6517 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6518 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6519 | |
6520 | return 0; | |
6521 | } | |
6522 | ||
6d293983 | 6523 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6524 | struct intel_crtc_state *pipe_config) |
1857e1da | 6525 | { |
6d293983 ACO |
6526 | struct drm_atomic_state *state = pipe_config->base.state; |
6527 | struct intel_crtc *other_crtc; | |
6528 | struct intel_crtc_state *other_crtc_state; | |
6529 | ||
1857e1da DV |
6530 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6531 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6532 | if (pipe_config->fdi_lanes > 4) { | |
6533 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6534 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6535 | return -EINVAL; |
1857e1da DV |
6536 | } |
6537 | ||
bafb6553 | 6538 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6539 | if (pipe_config->fdi_lanes > 2) { |
6540 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6541 | pipe_config->fdi_lanes); | |
6d293983 | 6542 | return -EINVAL; |
1857e1da | 6543 | } else { |
6d293983 | 6544 | return 0; |
1857e1da DV |
6545 | } |
6546 | } | |
6547 | ||
6548 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6549 | return 0; |
1857e1da DV |
6550 | |
6551 | /* Ivybridge 3 pipe is really complicated */ | |
6552 | switch (pipe) { | |
6553 | case PIPE_A: | |
6d293983 | 6554 | return 0; |
1857e1da | 6555 | case PIPE_B: |
6d293983 ACO |
6556 | if (pipe_config->fdi_lanes <= 2) |
6557 | return 0; | |
6558 | ||
6559 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6560 | other_crtc_state = | |
6561 | intel_atomic_get_crtc_state(state, other_crtc); | |
6562 | if (IS_ERR(other_crtc_state)) | |
6563 | return PTR_ERR(other_crtc_state); | |
6564 | ||
6565 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6566 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6567 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6568 | return -EINVAL; |
1857e1da | 6569 | } |
6d293983 | 6570 | return 0; |
1857e1da | 6571 | case PIPE_C: |
251cc67c VS |
6572 | if (pipe_config->fdi_lanes > 2) { |
6573 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6574 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6575 | return -EINVAL; |
251cc67c | 6576 | } |
6d293983 ACO |
6577 | |
6578 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6579 | other_crtc_state = | |
6580 | intel_atomic_get_crtc_state(state, other_crtc); | |
6581 | if (IS_ERR(other_crtc_state)) | |
6582 | return PTR_ERR(other_crtc_state); | |
6583 | ||
6584 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6585 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6586 | return -EINVAL; |
1857e1da | 6587 | } |
6d293983 | 6588 | return 0; |
1857e1da DV |
6589 | default: |
6590 | BUG(); | |
6591 | } | |
6592 | } | |
6593 | ||
e29c22c0 DV |
6594 | #define RETRY 1 |
6595 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6596 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6597 | { |
1857e1da | 6598 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6599 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6600 | int lane, link_bw, fdi_dotclock, ret; |
6601 | bool needs_recompute = false; | |
877d48d5 | 6602 | |
e29c22c0 | 6603 | retry: |
877d48d5 DV |
6604 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6605 | * each output octet as 10 bits. The actual frequency | |
6606 | * is stored as a divider into a 100MHz clock, and the | |
6607 | * mode pixel clock is stored in units of 1KHz. | |
6608 | * Hence the bw of each lane in terms of the mode signal | |
6609 | * is: | |
6610 | */ | |
6611 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
6612 | ||
241bfc38 | 6613 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6614 | |
2bd89a07 | 6615 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6616 | pipe_config->pipe_bpp); |
6617 | ||
6618 | pipe_config->fdi_lanes = lane; | |
6619 | ||
2bd89a07 | 6620 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6621 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6622 | |
6d293983 ACO |
6623 | ret = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
6624 | intel_crtc->pipe, pipe_config); | |
6625 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { | |
e29c22c0 DV |
6626 | pipe_config->pipe_bpp -= 2*3; |
6627 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6628 | pipe_config->pipe_bpp); | |
6629 | needs_recompute = true; | |
6630 | pipe_config->bw_constrained = true; | |
6631 | ||
6632 | goto retry; | |
6633 | } | |
6634 | ||
6635 | if (needs_recompute) | |
6636 | return RETRY; | |
6637 | ||
6d293983 | 6638 | return ret; |
877d48d5 DV |
6639 | } |
6640 | ||
8cfb3407 VS |
6641 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6642 | struct intel_crtc_state *pipe_config) | |
6643 | { | |
6644 | if (pipe_config->pipe_bpp > 24) | |
6645 | return false; | |
6646 | ||
6647 | /* HSW can handle pixel rate up to cdclk? */ | |
6648 | if (IS_HASWELL(dev_priv->dev)) | |
6649 | return true; | |
6650 | ||
6651 | /* | |
b432e5cf VS |
6652 | * We compare against max which means we must take |
6653 | * the increased cdclk requirement into account when | |
6654 | * calculating the new cdclk. | |
6655 | * | |
6656 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
6657 | */ |
6658 | return ilk_pipe_pixel_rate(pipe_config) <= | |
6659 | dev_priv->max_cdclk_freq * 95 / 100; | |
6660 | } | |
6661 | ||
42db64ef | 6662 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6663 | struct intel_crtc_state *pipe_config) |
42db64ef | 6664 | { |
8cfb3407 VS |
6665 | struct drm_device *dev = crtc->base.dev; |
6666 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6667 | ||
d330a953 | 6668 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
6669 | hsw_crtc_supports_ips(crtc) && |
6670 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
6671 | } |
6672 | ||
39acb4aa VS |
6673 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
6674 | { | |
6675 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
6676 | ||
6677 | /* GDG double wide on either pipe, otherwise pipe A only */ | |
6678 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6679 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
6680 | } | |
6681 | ||
a43f6e0f | 6682 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6683 | struct intel_crtc_state *pipe_config) |
79e53945 | 6684 | { |
a43f6e0f | 6685 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 6686 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c5f93b0 | 6687 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
89749350 | 6688 | |
ad3a4479 | 6689 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 6690 | if (INTEL_INFO(dev)->gen < 4) { |
39acb4aa | 6691 | int clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
cf532bb2 VS |
6692 | |
6693 | /* | |
39acb4aa | 6694 | * Enable double wide mode when the dot clock |
cf532bb2 | 6695 | * is > 90% of the (display) core speed. |
cf532bb2 | 6696 | */ |
39acb4aa VS |
6697 | if (intel_crtc_supports_double_wide(crtc) && |
6698 | adjusted_mode->crtc_clock > clock_limit) { | |
ad3a4479 | 6699 | clock_limit *= 2; |
cf532bb2 | 6700 | pipe_config->double_wide = true; |
ad3a4479 VS |
6701 | } |
6702 | ||
39acb4aa VS |
6703 | if (adjusted_mode->crtc_clock > clock_limit) { |
6704 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6705 | adjusted_mode->crtc_clock, clock_limit, | |
6706 | yesno(pipe_config->double_wide)); | |
e29c22c0 | 6707 | return -EINVAL; |
39acb4aa | 6708 | } |
2c07245f | 6709 | } |
89749350 | 6710 | |
1d1d0e27 VS |
6711 | /* |
6712 | * Pipe horizontal size must be even in: | |
6713 | * - DVO ganged mode | |
6714 | * - LVDS dual channel mode | |
6715 | * - Double wide pipe | |
6716 | */ | |
a93e255f | 6717 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6718 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6719 | pipe_config->pipe_src_w &= ~1; | |
6720 | ||
8693a824 DL |
6721 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6722 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6723 | */ |
6724 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
aad941d5 | 6725 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
e29c22c0 | 6726 | return -EINVAL; |
44f46b42 | 6727 | |
f5adf94e | 6728 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6729 | hsw_compute_ips_config(crtc, pipe_config); |
6730 | ||
877d48d5 | 6731 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6732 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6733 | |
cf5a15be | 6734 | return 0; |
79e53945 JB |
6735 | } |
6736 | ||
1652d19e VS |
6737 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6738 | { | |
6739 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6740 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
6741 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6742 | uint32_t linkrate; | |
6743 | ||
414355a7 | 6744 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) |
1652d19e | 6745 | return 24000; /* 24MHz is the cd freq with NSSC ref */ |
1652d19e VS |
6746 | |
6747 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
6748 | return 540000; | |
6749 | ||
6750 | linkrate = (I915_READ(DPLL_CTRL1) & | |
71cd8423 | 6751 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; |
1652d19e | 6752 | |
71cd8423 DL |
6753 | if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || |
6754 | linkrate == DPLL_CTRL1_LINK_RATE_1080) { | |
1652d19e VS |
6755 | /* vco 8640 */ |
6756 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6757 | case CDCLK_FREQ_450_432: | |
6758 | return 432000; | |
6759 | case CDCLK_FREQ_337_308: | |
6760 | return 308570; | |
6761 | case CDCLK_FREQ_675_617: | |
6762 | return 617140; | |
6763 | default: | |
6764 | WARN(1, "Unknown cd freq selection\n"); | |
6765 | } | |
6766 | } else { | |
6767 | /* vco 8100 */ | |
6768 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6769 | case CDCLK_FREQ_450_432: | |
6770 | return 450000; | |
6771 | case CDCLK_FREQ_337_308: | |
6772 | return 337500; | |
6773 | case CDCLK_FREQ_675_617: | |
6774 | return 675000; | |
6775 | default: | |
6776 | WARN(1, "Unknown cd freq selection\n"); | |
6777 | } | |
6778 | } | |
6779 | ||
6780 | /* error case, do as if DPLL0 isn't enabled */ | |
6781 | return 24000; | |
6782 | } | |
6783 | ||
acd3f3d3 BP |
6784 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
6785 | { | |
6786 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6787 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6788 | uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; | |
6789 | uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE); | |
6790 | int cdclk; | |
6791 | ||
6792 | if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE)) | |
6793 | return 19200; | |
6794 | ||
6795 | cdclk = 19200 * pll_ratio / 2; | |
6796 | ||
6797 | switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) { | |
6798 | case BXT_CDCLK_CD2X_DIV_SEL_1: | |
6799 | return cdclk; /* 576MHz or 624MHz */ | |
6800 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: | |
6801 | return cdclk * 2 / 3; /* 384MHz */ | |
6802 | case BXT_CDCLK_CD2X_DIV_SEL_2: | |
6803 | return cdclk / 2; /* 288MHz */ | |
6804 | case BXT_CDCLK_CD2X_DIV_SEL_4: | |
6805 | return cdclk / 4; /* 144MHz */ | |
6806 | } | |
6807 | ||
6808 | /* error case, do as if DE PLL isn't enabled */ | |
6809 | return 19200; | |
6810 | } | |
6811 | ||
1652d19e VS |
6812 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
6813 | { | |
6814 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6815 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6816 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6817 | ||
6818 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6819 | return 800000; | |
6820 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6821 | return 450000; | |
6822 | else if (freq == LCPLL_CLK_FREQ_450) | |
6823 | return 450000; | |
6824 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6825 | return 540000; | |
6826 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6827 | return 337500; | |
6828 | else | |
6829 | return 675000; | |
6830 | } | |
6831 | ||
6832 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6833 | { | |
6834 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6835 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6836 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6837 | ||
6838 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6839 | return 800000; | |
6840 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6841 | return 450000; | |
6842 | else if (freq == LCPLL_CLK_FREQ_450) | |
6843 | return 450000; | |
6844 | else if (IS_HSW_ULT(dev)) | |
6845 | return 337500; | |
6846 | else | |
6847 | return 540000; | |
79e53945 JB |
6848 | } |
6849 | ||
25eb05fc JB |
6850 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6851 | { | |
bfa7df01 VS |
6852 | return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", |
6853 | CCK_DISPLAY_CLOCK_CONTROL); | |
25eb05fc JB |
6854 | } |
6855 | ||
b37a6434 VS |
6856 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6857 | { | |
6858 | return 450000; | |
6859 | } | |
6860 | ||
e70236a8 JB |
6861 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6862 | { | |
6863 | return 400000; | |
6864 | } | |
79e53945 | 6865 | |
e70236a8 | 6866 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6867 | { |
e907f170 | 6868 | return 333333; |
e70236a8 | 6869 | } |
79e53945 | 6870 | |
e70236a8 JB |
6871 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6872 | { | |
6873 | return 200000; | |
6874 | } | |
79e53945 | 6875 | |
257a7ffc DV |
6876 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6877 | { | |
6878 | u16 gcfgc = 0; | |
6879 | ||
6880 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6881 | ||
6882 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6883 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6884 | return 266667; |
257a7ffc | 6885 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6886 | return 333333; |
257a7ffc | 6887 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6888 | return 444444; |
257a7ffc DV |
6889 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6890 | return 200000; | |
6891 | default: | |
6892 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6893 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6894 | return 133333; |
257a7ffc | 6895 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6896 | return 166667; |
257a7ffc DV |
6897 | } |
6898 | } | |
6899 | ||
e70236a8 JB |
6900 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6901 | { | |
6902 | u16 gcfgc = 0; | |
79e53945 | 6903 | |
e70236a8 JB |
6904 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6905 | ||
6906 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6907 | return 133333; |
e70236a8 JB |
6908 | else { |
6909 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6910 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6911 | return 333333; |
e70236a8 JB |
6912 | default: |
6913 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6914 | return 190000; | |
79e53945 | 6915 | } |
e70236a8 JB |
6916 | } |
6917 | } | |
6918 | ||
6919 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6920 | { | |
e907f170 | 6921 | return 266667; |
e70236a8 JB |
6922 | } |
6923 | ||
1b1d2716 | 6924 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 JB |
6925 | { |
6926 | u16 hpllcc = 0; | |
1b1d2716 | 6927 | |
65cd2b3f VS |
6928 | /* |
6929 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
6930 | * encoding is different :( | |
6931 | * FIXME is this the right way to detect 852GM/852GMV? | |
6932 | */ | |
6933 | if (dev->pdev->revision == 0x1) | |
6934 | return 133333; | |
6935 | ||
1b1d2716 VS |
6936 | pci_bus_read_config_word(dev->pdev->bus, |
6937 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
6938 | ||
e70236a8 JB |
6939 | /* Assume that the hardware is in the high speed state. This |
6940 | * should be the default. | |
6941 | */ | |
6942 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6943 | case GC_CLOCK_133_200: | |
1b1d2716 | 6944 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
6945 | case GC_CLOCK_100_200: |
6946 | return 200000; | |
6947 | case GC_CLOCK_166_250: | |
6948 | return 250000; | |
6949 | case GC_CLOCK_100_133: | |
e907f170 | 6950 | return 133333; |
1b1d2716 VS |
6951 | case GC_CLOCK_133_266: |
6952 | case GC_CLOCK_133_266_2: | |
6953 | case GC_CLOCK_166_266: | |
6954 | return 266667; | |
e70236a8 | 6955 | } |
79e53945 | 6956 | |
e70236a8 JB |
6957 | /* Shouldn't happen */ |
6958 | return 0; | |
6959 | } | |
79e53945 | 6960 | |
e70236a8 JB |
6961 | static int i830_get_display_clock_speed(struct drm_device *dev) |
6962 | { | |
e907f170 | 6963 | return 133333; |
79e53945 JB |
6964 | } |
6965 | ||
34edce2f VS |
6966 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
6967 | { | |
6968 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6969 | static const unsigned int blb_vco[8] = { | |
6970 | [0] = 3200000, | |
6971 | [1] = 4000000, | |
6972 | [2] = 5333333, | |
6973 | [3] = 4800000, | |
6974 | [4] = 6400000, | |
6975 | }; | |
6976 | static const unsigned int pnv_vco[8] = { | |
6977 | [0] = 3200000, | |
6978 | [1] = 4000000, | |
6979 | [2] = 5333333, | |
6980 | [3] = 4800000, | |
6981 | [4] = 2666667, | |
6982 | }; | |
6983 | static const unsigned int cl_vco[8] = { | |
6984 | [0] = 3200000, | |
6985 | [1] = 4000000, | |
6986 | [2] = 5333333, | |
6987 | [3] = 6400000, | |
6988 | [4] = 3333333, | |
6989 | [5] = 3566667, | |
6990 | [6] = 4266667, | |
6991 | }; | |
6992 | static const unsigned int elk_vco[8] = { | |
6993 | [0] = 3200000, | |
6994 | [1] = 4000000, | |
6995 | [2] = 5333333, | |
6996 | [3] = 4800000, | |
6997 | }; | |
6998 | static const unsigned int ctg_vco[8] = { | |
6999 | [0] = 3200000, | |
7000 | [1] = 4000000, | |
7001 | [2] = 5333333, | |
7002 | [3] = 6400000, | |
7003 | [4] = 2666667, | |
7004 | [5] = 4266667, | |
7005 | }; | |
7006 | const unsigned int *vco_table; | |
7007 | unsigned int vco; | |
7008 | uint8_t tmp = 0; | |
7009 | ||
7010 | /* FIXME other chipsets? */ | |
7011 | if (IS_GM45(dev)) | |
7012 | vco_table = ctg_vco; | |
7013 | else if (IS_G4X(dev)) | |
7014 | vco_table = elk_vco; | |
7015 | else if (IS_CRESTLINE(dev)) | |
7016 | vco_table = cl_vco; | |
7017 | else if (IS_PINEVIEW(dev)) | |
7018 | vco_table = pnv_vco; | |
7019 | else if (IS_G33(dev)) | |
7020 | vco_table = blb_vco; | |
7021 | else | |
7022 | return 0; | |
7023 | ||
7024 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
7025 | ||
7026 | vco = vco_table[tmp & 0x7]; | |
7027 | if (vco == 0) | |
7028 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
7029 | else | |
7030 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
7031 | ||
7032 | return vco; | |
7033 | } | |
7034 | ||
7035 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
7036 | { | |
7037 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7038 | uint16_t tmp = 0; | |
7039 | ||
7040 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7041 | ||
7042 | cdclk_sel = (tmp >> 12) & 0x1; | |
7043 | ||
7044 | switch (vco) { | |
7045 | case 2666667: | |
7046 | case 4000000: | |
7047 | case 5333333: | |
7048 | return cdclk_sel ? 333333 : 222222; | |
7049 | case 3200000: | |
7050 | return cdclk_sel ? 320000 : 228571; | |
7051 | default: | |
7052 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
7053 | return 222222; | |
7054 | } | |
7055 | } | |
7056 | ||
7057 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
7058 | { | |
7059 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
7060 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
7061 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
7062 | const uint8_t *div_table; | |
7063 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7064 | uint16_t tmp = 0; | |
7065 | ||
7066 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7067 | ||
7068 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
7069 | ||
7070 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7071 | goto fail; | |
7072 | ||
7073 | switch (vco) { | |
7074 | case 3200000: | |
7075 | div_table = div_3200; | |
7076 | break; | |
7077 | case 4000000: | |
7078 | div_table = div_4000; | |
7079 | break; | |
7080 | case 5333333: | |
7081 | div_table = div_5333; | |
7082 | break; | |
7083 | default: | |
7084 | goto fail; | |
7085 | } | |
7086 | ||
7087 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7088 | ||
caf4e252 | 7089 | fail: |
34edce2f VS |
7090 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
7091 | return 200000; | |
7092 | } | |
7093 | ||
7094 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
7095 | { | |
7096 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
7097 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
7098 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
7099 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
7100 | const uint8_t *div_table; | |
7101 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7102 | uint16_t tmp = 0; | |
7103 | ||
7104 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7105 | ||
7106 | cdclk_sel = (tmp >> 4) & 0x7; | |
7107 | ||
7108 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7109 | goto fail; | |
7110 | ||
7111 | switch (vco) { | |
7112 | case 3200000: | |
7113 | div_table = div_3200; | |
7114 | break; | |
7115 | case 4000000: | |
7116 | div_table = div_4000; | |
7117 | break; | |
7118 | case 4800000: | |
7119 | div_table = div_4800; | |
7120 | break; | |
7121 | case 5333333: | |
7122 | div_table = div_5333; | |
7123 | break; | |
7124 | default: | |
7125 | goto fail; | |
7126 | } | |
7127 | ||
7128 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7129 | ||
caf4e252 | 7130 | fail: |
34edce2f VS |
7131 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
7132 | return 190476; | |
7133 | } | |
7134 | ||
2c07245f | 7135 | static void |
a65851af | 7136 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 7137 | { |
a65851af VS |
7138 | while (*num > DATA_LINK_M_N_MASK || |
7139 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
7140 | *num >>= 1; |
7141 | *den >>= 1; | |
7142 | } | |
7143 | } | |
7144 | ||
a65851af VS |
7145 | static void compute_m_n(unsigned int m, unsigned int n, |
7146 | uint32_t *ret_m, uint32_t *ret_n) | |
7147 | { | |
7148 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7149 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7150 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7151 | } | |
7152 | ||
e69d0bc1 DV |
7153 | void |
7154 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7155 | int pixel_clock, int link_clock, | |
7156 | struct intel_link_m_n *m_n) | |
2c07245f | 7157 | { |
e69d0bc1 | 7158 | m_n->tu = 64; |
a65851af VS |
7159 | |
7160 | compute_m_n(bits_per_pixel * pixel_clock, | |
7161 | link_clock * nlanes * 8, | |
7162 | &m_n->gmch_m, &m_n->gmch_n); | |
7163 | ||
7164 | compute_m_n(pixel_clock, link_clock, | |
7165 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7166 | } |
7167 | ||
a7615030 CW |
7168 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7169 | { | |
d330a953 JN |
7170 | if (i915.panel_use_ssc >= 0) |
7171 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7172 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7173 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7174 | } |
7175 | ||
a93e255f ACO |
7176 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
7177 | int num_connectors) | |
c65d77d8 | 7178 | { |
a93e255f | 7179 | struct drm_device *dev = crtc_state->base.crtc->dev; |
c65d77d8 JB |
7180 | struct drm_i915_private *dev_priv = dev->dev_private; |
7181 | int refclk; | |
7182 | ||
a93e255f ACO |
7183 | WARN_ON(!crtc_state->base.state); |
7184 | ||
666a4537 | 7185 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) { |
9a0ea498 | 7186 | refclk = 100000; |
a93e255f | 7187 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 7188 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
7189 | refclk = dev_priv->vbt.lvds_ssc_freq; |
7190 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
7191 | } else if (!IS_GEN2(dev)) { |
7192 | refclk = 96000; | |
7193 | } else { | |
7194 | refclk = 48000; | |
7195 | } | |
7196 | ||
7197 | return refclk; | |
7198 | } | |
7199 | ||
7429e9d4 | 7200 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7201 | { |
7df00d7a | 7202 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7203 | } |
f47709a9 | 7204 | |
7429e9d4 DV |
7205 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7206 | { | |
7207 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7208 | } |
7209 | ||
f47709a9 | 7210 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7211 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
7212 | intel_clock_t *reduced_clock) |
7213 | { | |
f47709a9 | 7214 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
7215 | u32 fp, fp2 = 0; |
7216 | ||
7217 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 7218 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7219 | if (reduced_clock) |
7429e9d4 | 7220 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7221 | } else { |
190f68c5 | 7222 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7223 | if (reduced_clock) |
7429e9d4 | 7224 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7225 | } |
7226 | ||
190f68c5 | 7227 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7228 | |
f47709a9 | 7229 | crtc->lowfreq_avail = false; |
a93e255f | 7230 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7231 | reduced_clock) { |
190f68c5 | 7232 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7233 | crtc->lowfreq_avail = true; |
a7516a05 | 7234 | } else { |
190f68c5 | 7235 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7236 | } |
7237 | } | |
7238 | ||
5e69f97f CML |
7239 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7240 | pipe) | |
89b667f8 JB |
7241 | { |
7242 | u32 reg_val; | |
7243 | ||
7244 | /* | |
7245 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7246 | * and set it to a reasonable value instead. | |
7247 | */ | |
ab3c759a | 7248 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7249 | reg_val &= 0xffffff00; |
7250 | reg_val |= 0x00000030; | |
ab3c759a | 7251 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7252 | |
ab3c759a | 7253 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7254 | reg_val &= 0x8cffffff; |
7255 | reg_val = 0x8c000000; | |
ab3c759a | 7256 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7257 | |
ab3c759a | 7258 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7259 | reg_val &= 0xffffff00; |
ab3c759a | 7260 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7261 | |
ab3c759a | 7262 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7263 | reg_val &= 0x00ffffff; |
7264 | reg_val |= 0xb0000000; | |
ab3c759a | 7265 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7266 | } |
7267 | ||
b551842d DV |
7268 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7269 | struct intel_link_m_n *m_n) | |
7270 | { | |
7271 | struct drm_device *dev = crtc->base.dev; | |
7272 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7273 | int pipe = crtc->pipe; | |
7274 | ||
e3b95f1e DV |
7275 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7276 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7277 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7278 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7279 | } |
7280 | ||
7281 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7282 | struct intel_link_m_n *m_n, |
7283 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7284 | { |
7285 | struct drm_device *dev = crtc->base.dev; | |
7286 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7287 | int pipe = crtc->pipe; | |
6e3c9717 | 7288 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7289 | |
7290 | if (INTEL_INFO(dev)->gen >= 5) { | |
7291 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7292 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7293 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7294 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7295 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7296 | * for gen < 8) and if DRRS is supported (to make sure the | |
7297 | * registers are not unnecessarily accessed). | |
7298 | */ | |
44395bfe | 7299 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 7300 | crtc->config->has_drrs) { |
f769cd24 VK |
7301 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7302 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7303 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7304 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7305 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7306 | } | |
b551842d | 7307 | } else { |
e3b95f1e DV |
7308 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7309 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7310 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7311 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7312 | } |
7313 | } | |
7314 | ||
fe3cd48d | 7315 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7316 | { |
fe3cd48d R |
7317 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7318 | ||
7319 | if (m_n == M1_N1) { | |
7320 | dp_m_n = &crtc->config->dp_m_n; | |
7321 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7322 | } else if (m_n == M2_N2) { | |
7323 | ||
7324 | /* | |
7325 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7326 | * needs to be programmed into M1_N1. | |
7327 | */ | |
7328 | dp_m_n = &crtc->config->dp_m2_n2; | |
7329 | } else { | |
7330 | DRM_ERROR("Unsupported divider value\n"); | |
7331 | return; | |
7332 | } | |
7333 | ||
6e3c9717 ACO |
7334 | if (crtc->config->has_pch_encoder) |
7335 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7336 | else |
fe3cd48d | 7337 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7338 | } |
7339 | ||
251ac862 DV |
7340 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7341 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 DV |
7342 | { |
7343 | u32 dpll, dpll_md; | |
7344 | ||
7345 | /* | |
7346 | * Enable DPIO clock input. We should never disable the reference | |
7347 | * clock for pipe B, since VGA hotplug / manual detection depends | |
7348 | * on it. | |
7349 | */ | |
60bfe44f VS |
7350 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV | |
7351 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV; | |
bdd4b6a6 DV |
7352 | /* We should never disable this, set it here for state tracking */ |
7353 | if (crtc->pipe == PIPE_B) | |
7354 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7355 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 7356 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 7357 | |
d288f65f | 7358 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 7359 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 7360 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
7361 | } |
7362 | ||
d288f65f | 7363 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7364 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7365 | { |
f47709a9 | 7366 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 7367 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 7368 | int pipe = crtc->pipe; |
bdd4b6a6 | 7369 | u32 mdiv; |
a0c4da24 | 7370 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7371 | u32 coreclk, reg_val; |
a0c4da24 | 7372 | |
a580516d | 7373 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7374 | |
d288f65f VS |
7375 | bestn = pipe_config->dpll.n; |
7376 | bestm1 = pipe_config->dpll.m1; | |
7377 | bestm2 = pipe_config->dpll.m2; | |
7378 | bestp1 = pipe_config->dpll.p1; | |
7379 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7380 | |
89b667f8 JB |
7381 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7382 | ||
7383 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7384 | if (pipe == PIPE_B) |
5e69f97f | 7385 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7386 | |
7387 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7388 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7389 | |
7390 | /* Disable target IRef on PLL */ | |
ab3c759a | 7391 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7392 | reg_val &= 0x00ffffff; |
ab3c759a | 7393 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7394 | |
7395 | /* Disable fast lock */ | |
ab3c759a | 7396 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7397 | |
7398 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7399 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7400 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7401 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7402 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7403 | |
7404 | /* | |
7405 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7406 | * but we don't support that). | |
7407 | * Note: don't use the DAC post divider as it seems unstable. | |
7408 | */ | |
7409 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7410 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7411 | |
a0c4da24 | 7412 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7413 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7414 | |
89b667f8 | 7415 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7416 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
7417 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
7418 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7419 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7420 | 0x009f0003); |
89b667f8 | 7421 | else |
ab3c759a | 7422 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7423 | 0x00d0000f); |
7424 | ||
681a8504 | 7425 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 7426 | /* Use SSC source */ |
bdd4b6a6 | 7427 | if (pipe == PIPE_A) |
ab3c759a | 7428 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7429 | 0x0df40000); |
7430 | else | |
ab3c759a | 7431 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7432 | 0x0df70000); |
7433 | } else { /* HDMI or VGA */ | |
7434 | /* Use bend source */ | |
bdd4b6a6 | 7435 | if (pipe == PIPE_A) |
ab3c759a | 7436 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7437 | 0x0df70000); |
7438 | else | |
ab3c759a | 7439 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7440 | 0x0df40000); |
7441 | } | |
a0c4da24 | 7442 | |
ab3c759a | 7443 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7444 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
7445 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
7446 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 7447 | coreclk |= 0x01000000; |
ab3c759a | 7448 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7449 | |
ab3c759a | 7450 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7451 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7452 | } |
7453 | ||
251ac862 DV |
7454 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7455 | struct intel_crtc_state *pipe_config) | |
1ae0d137 | 7456 | { |
60bfe44f VS |
7457 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | |
7458 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | | |
1ae0d137 VS |
7459 | DPLL_VCO_ENABLE; |
7460 | if (crtc->pipe != PIPE_A) | |
d288f65f | 7461 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 7462 | |
d288f65f VS |
7463 | pipe_config->dpll_hw_state.dpll_md = |
7464 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
7465 | } |
7466 | ||
d288f65f | 7467 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7468 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7469 | { |
7470 | struct drm_device *dev = crtc->base.dev; | |
7471 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7472 | int pipe = crtc->pipe; | |
f0f59a00 | 7473 | i915_reg_t dpll_reg = DPLL(crtc->pipe); |
9d556c99 | 7474 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 7475 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7476 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7477 | u32 dpio_val; |
9cbe40c1 | 7478 | int vco; |
9d556c99 | 7479 | |
d288f65f VS |
7480 | bestn = pipe_config->dpll.n; |
7481 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7482 | bestm1 = pipe_config->dpll.m1; | |
7483 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7484 | bestp1 = pipe_config->dpll.p1; | |
7485 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7486 | vco = pipe_config->dpll.vco; |
a945ce7e | 7487 | dpio_val = 0; |
9cbe40c1 | 7488 | loopfilter = 0; |
9d556c99 CML |
7489 | |
7490 | /* | |
7491 | * Enable Refclk and SSC | |
7492 | */ | |
a11b0703 | 7493 | I915_WRITE(dpll_reg, |
d288f65f | 7494 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 | 7495 | |
a580516d | 7496 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7497 | |
9d556c99 CML |
7498 | /* p1 and p2 divider */ |
7499 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7500 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7501 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7502 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7503 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7504 | ||
7505 | /* Feedback post-divider - m2 */ | |
7506 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7507 | ||
7508 | /* Feedback refclk divider - n and m1 */ | |
7509 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7510 | DPIO_CHV_M1_DIV_BY_2 | | |
7511 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7512 | ||
7513 | /* M2 fraction division */ | |
25a25dfc | 7514 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
7515 | |
7516 | /* M2 fraction division enable */ | |
a945ce7e VP |
7517 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7518 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7519 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7520 | if (bestm2_frac) | |
7521 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7522 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7523 | |
de3a0fde VP |
7524 | /* Program digital lock detect threshold */ |
7525 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7526 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7527 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7528 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7529 | if (!bestm2_frac) | |
7530 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7531 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7532 | ||
9d556c99 | 7533 | /* Loop filter */ |
9cbe40c1 VP |
7534 | if (vco == 5400000) { |
7535 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7536 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7537 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7538 | tribuf_calcntr = 0x9; | |
7539 | } else if (vco <= 6200000) { | |
7540 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7541 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7542 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7543 | tribuf_calcntr = 0x9; | |
7544 | } else if (vco <= 6480000) { | |
7545 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7546 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7547 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7548 | tribuf_calcntr = 0x8; | |
7549 | } else { | |
7550 | /* Not supported. Apply the same limits as in the max case */ | |
7551 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7552 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7553 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7554 | tribuf_calcntr = 0; | |
7555 | } | |
9d556c99 CML |
7556 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7557 | ||
968040b2 | 7558 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7559 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7560 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7561 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7562 | ||
9d556c99 CML |
7563 | /* AFC Recal */ |
7564 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7565 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7566 | DPIO_AFC_RECAL); | |
7567 | ||
a580516d | 7568 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
7569 | } |
7570 | ||
d288f65f VS |
7571 | /** |
7572 | * vlv_force_pll_on - forcibly enable just the PLL | |
7573 | * @dev_priv: i915 private structure | |
7574 | * @pipe: pipe PLL to enable | |
7575 | * @dpll: PLL configuration | |
7576 | * | |
7577 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7578 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7579 | * be enabled. | |
7580 | */ | |
7581 | void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, | |
7582 | const struct dpll *dpll) | |
7583 | { | |
7584 | struct intel_crtc *crtc = | |
7585 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
5cec258b | 7586 | struct intel_crtc_state pipe_config = { |
a93e255f | 7587 | .base.crtc = &crtc->base, |
d288f65f VS |
7588 | .pixel_multiplier = 1, |
7589 | .dpll = *dpll, | |
7590 | }; | |
7591 | ||
7592 | if (IS_CHERRYVIEW(dev)) { | |
251ac862 | 7593 | chv_compute_dpll(crtc, &pipe_config); |
d288f65f VS |
7594 | chv_prepare_pll(crtc, &pipe_config); |
7595 | chv_enable_pll(crtc, &pipe_config); | |
7596 | } else { | |
251ac862 | 7597 | vlv_compute_dpll(crtc, &pipe_config); |
d288f65f VS |
7598 | vlv_prepare_pll(crtc, &pipe_config); |
7599 | vlv_enable_pll(crtc, &pipe_config); | |
7600 | } | |
7601 | } | |
7602 | ||
7603 | /** | |
7604 | * vlv_force_pll_off - forcibly disable just the PLL | |
7605 | * @dev_priv: i915 private structure | |
7606 | * @pipe: pipe PLL to disable | |
7607 | * | |
7608 | * Disable the PLL for @pipe. To be used in cases where we need | |
7609 | * the PLL enabled even when @pipe is not going to be enabled. | |
7610 | */ | |
7611 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7612 | { | |
7613 | if (IS_CHERRYVIEW(dev)) | |
7614 | chv_disable_pll(to_i915(dev), pipe); | |
7615 | else | |
7616 | vlv_disable_pll(to_i915(dev), pipe); | |
7617 | } | |
7618 | ||
251ac862 DV |
7619 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
7620 | struct intel_crtc_state *crtc_state, | |
7621 | intel_clock_t *reduced_clock, | |
7622 | int num_connectors) | |
eb1cbe48 | 7623 | { |
f47709a9 | 7624 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7625 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
7626 | u32 dpll; |
7627 | bool is_sdvo; | |
190f68c5 | 7628 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7629 | |
190f68c5 | 7630 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7631 | |
a93e255f ACO |
7632 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7633 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
7634 | |
7635 | dpll = DPLL_VGA_MODE_DIS; | |
7636 | ||
a93e255f | 7637 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7638 | dpll |= DPLLB_MODE_LVDS; |
7639 | else | |
7640 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7641 | |
ef1b460d | 7642 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7643 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7644 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7645 | } |
198a037f DV |
7646 | |
7647 | if (is_sdvo) | |
4a33e48d | 7648 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7649 | |
190f68c5 | 7650 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7651 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7652 | |
7653 | /* compute bitmask from p1 value */ | |
7654 | if (IS_PINEVIEW(dev)) | |
7655 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7656 | else { | |
7657 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7658 | if (IS_G4X(dev) && reduced_clock) | |
7659 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7660 | } | |
7661 | switch (clock->p2) { | |
7662 | case 5: | |
7663 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7664 | break; | |
7665 | case 7: | |
7666 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7667 | break; | |
7668 | case 10: | |
7669 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7670 | break; | |
7671 | case 14: | |
7672 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7673 | break; | |
7674 | } | |
7675 | if (INTEL_INFO(dev)->gen >= 4) | |
7676 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7677 | ||
190f68c5 | 7678 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7679 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 7680 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7681 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7682 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7683 | else | |
7684 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7685 | ||
7686 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7687 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7688 | |
eb1cbe48 | 7689 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7690 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7691 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7692 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7693 | } |
7694 | } | |
7695 | ||
251ac862 DV |
7696 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
7697 | struct intel_crtc_state *crtc_state, | |
7698 | intel_clock_t *reduced_clock, | |
7699 | int num_connectors) | |
eb1cbe48 | 7700 | { |
f47709a9 | 7701 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7702 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 7703 | u32 dpll; |
190f68c5 | 7704 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7705 | |
190f68c5 | 7706 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7707 | |
eb1cbe48 DV |
7708 | dpll = DPLL_VGA_MODE_DIS; |
7709 | ||
a93e255f | 7710 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7711 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7712 | } else { | |
7713 | if (clock->p1 == 2) | |
7714 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7715 | else | |
7716 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7717 | if (clock->p2 == 4) | |
7718 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7719 | } | |
7720 | ||
a93e255f | 7721 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7722 | dpll |= DPLL_DVO_2X_MODE; |
7723 | ||
a93e255f | 7724 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7725 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7726 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7727 | else | |
7728 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7729 | ||
7730 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7731 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7732 | } |
7733 | ||
8a654f3b | 7734 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7735 | { |
7736 | struct drm_device *dev = intel_crtc->base.dev; | |
7737 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7738 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 7739 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 7740 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7741 | uint32_t crtc_vtotal, crtc_vblank_end; |
7742 | int vsyncshift = 0; | |
4d8a62ea DV |
7743 | |
7744 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7745 | * the hw state checker will get angry at the mismatch. */ | |
7746 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7747 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7748 | |
609aeaca | 7749 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7750 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7751 | crtc_vtotal -= 1; |
7752 | crtc_vblank_end -= 1; | |
609aeaca | 7753 | |
409ee761 | 7754 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7755 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7756 | else | |
7757 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7758 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7759 | if (vsyncshift < 0) |
7760 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7761 | } |
7762 | ||
7763 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7764 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7765 | |
fe2b8f9d | 7766 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7767 | (adjusted_mode->crtc_hdisplay - 1) | |
7768 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7769 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7770 | (adjusted_mode->crtc_hblank_start - 1) | |
7771 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7772 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7773 | (adjusted_mode->crtc_hsync_start - 1) | |
7774 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7775 | ||
fe2b8f9d | 7776 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7777 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7778 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7779 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7780 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7781 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7782 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7783 | (adjusted_mode->crtc_vsync_start - 1) | |
7784 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7785 | ||
b5e508d4 PZ |
7786 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7787 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7788 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7789 | * bits. */ | |
7790 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7791 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7792 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7793 | ||
b0e77b9c PZ |
7794 | /* pipesrc controls the size that is scaled from, which should |
7795 | * always be the user's requested size. | |
7796 | */ | |
7797 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7798 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7799 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7800 | } |
7801 | ||
1bd1bd80 | 7802 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7803 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7804 | { |
7805 | struct drm_device *dev = crtc->base.dev; | |
7806 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7807 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7808 | uint32_t tmp; | |
7809 | ||
7810 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7811 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7812 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7813 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7814 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7815 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7816 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7817 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7818 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7819 | |
7820 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7821 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7822 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7823 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7824 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7825 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7826 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7827 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7828 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7829 | |
7830 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7831 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7832 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7833 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 DV |
7834 | } |
7835 | ||
7836 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7837 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7838 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7839 | ||
2d112de7 ACO |
7840 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7841 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7842 | } |
7843 | ||
f6a83288 | 7844 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7845 | struct intel_crtc_state *pipe_config) |
babea61d | 7846 | { |
2d112de7 ACO |
7847 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7848 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7849 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7850 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7851 | |
2d112de7 ACO |
7852 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7853 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7854 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7855 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7856 | |
2d112de7 | 7857 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7858 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7859 | |
2d112de7 ACO |
7860 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7861 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
7862 | |
7863 | mode->hsync = drm_mode_hsync(mode); | |
7864 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7865 | drm_mode_set_name(mode); | |
babea61d JB |
7866 | } |
7867 | ||
84b046f3 DV |
7868 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7869 | { | |
7870 | struct drm_device *dev = intel_crtc->base.dev; | |
7871 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7872 | uint32_t pipeconf; | |
7873 | ||
9f11a9e4 | 7874 | pipeconf = 0; |
84b046f3 | 7875 | |
b6b5d049 VS |
7876 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7877 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7878 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7879 | |
6e3c9717 | 7880 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7881 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7882 | |
ff9ce46e | 7883 | /* only g4x and later have fancy bpc/dither controls */ |
666a4537 | 7884 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
ff9ce46e | 7885 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7886 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7887 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7888 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7889 | |
6e3c9717 | 7890 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7891 | case 18: |
7892 | pipeconf |= PIPECONF_6BPC; | |
7893 | break; | |
7894 | case 24: | |
7895 | pipeconf |= PIPECONF_8BPC; | |
7896 | break; | |
7897 | case 30: | |
7898 | pipeconf |= PIPECONF_10BPC; | |
7899 | break; | |
7900 | default: | |
7901 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7902 | BUG(); | |
84b046f3 DV |
7903 | } |
7904 | } | |
7905 | ||
7906 | if (HAS_PIPE_CXSR(dev)) { | |
7907 | if (intel_crtc->lowfreq_avail) { | |
7908 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7909 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7910 | } else { | |
7911 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7912 | } |
7913 | } | |
7914 | ||
6e3c9717 | 7915 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7916 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 7917 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7918 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7919 | else | |
7920 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7921 | } else | |
84b046f3 DV |
7922 | pipeconf |= PIPECONF_PROGRESSIVE; |
7923 | ||
666a4537 WB |
7924 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
7925 | intel_crtc->config->limited_color_range) | |
9f11a9e4 | 7926 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7927 | |
84b046f3 DV |
7928 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7929 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7930 | } | |
7931 | ||
190f68c5 ACO |
7932 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7933 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7934 | { |
c7653199 | 7935 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7936 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 7937 | int refclk, num_connectors = 0; |
c329a4ec DV |
7938 | intel_clock_t clock; |
7939 | bool ok; | |
d4906093 | 7940 | const intel_limit_t *limit; |
55bb9992 | 7941 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 7942 | struct drm_connector *connector; |
55bb9992 ACO |
7943 | struct drm_connector_state *connector_state; |
7944 | int i; | |
79e53945 | 7945 | |
dd3cd74a ACO |
7946 | memset(&crtc_state->dpll_hw_state, 0, |
7947 | sizeof(crtc_state->dpll_hw_state)); | |
7948 | ||
a65347ba JN |
7949 | if (crtc_state->has_dsi_encoder) |
7950 | return 0; | |
43565a06 | 7951 | |
a65347ba JN |
7952 | for_each_connector_in_state(state, connector, connector_state, i) { |
7953 | if (connector_state->crtc == &crtc->base) | |
7954 | num_connectors++; | |
79e53945 JB |
7955 | } |
7956 | ||
190f68c5 | 7957 | if (!crtc_state->clock_set) { |
a93e255f | 7958 | refclk = i9xx_get_refclk(crtc_state, num_connectors); |
79e53945 | 7959 | |
e9fd1c02 JN |
7960 | /* |
7961 | * Returns a set of divisors for the desired target clock with | |
7962 | * the given refclk, or FALSE. The returned values represent | |
7963 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
7964 | * 2) / p1 / p2. | |
7965 | */ | |
a93e255f ACO |
7966 | limit = intel_limit(crtc_state, refclk); |
7967 | ok = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 7968 | crtc_state->port_clock, |
e9fd1c02 | 7969 | refclk, NULL, &clock); |
f2335330 | 7970 | if (!ok) { |
e9fd1c02 JN |
7971 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7972 | return -EINVAL; | |
7973 | } | |
79e53945 | 7974 | |
f2335330 | 7975 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
7976 | crtc_state->dpll.n = clock.n; |
7977 | crtc_state->dpll.m1 = clock.m1; | |
7978 | crtc_state->dpll.m2 = clock.m2; | |
7979 | crtc_state->dpll.p1 = clock.p1; | |
7980 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 7981 | } |
7026d4ac | 7982 | |
e9fd1c02 | 7983 | if (IS_GEN2(dev)) { |
c329a4ec | 7984 | i8xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 7985 | num_connectors); |
9d556c99 | 7986 | } else if (IS_CHERRYVIEW(dev)) { |
251ac862 | 7987 | chv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 7988 | } else if (IS_VALLEYVIEW(dev)) { |
251ac862 | 7989 | vlv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 7990 | } else { |
c329a4ec | 7991 | i9xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 7992 | num_connectors); |
e9fd1c02 | 7993 | } |
79e53945 | 7994 | |
c8f7a0db | 7995 | return 0; |
f564048e EA |
7996 | } |
7997 | ||
2fa2fe9a | 7998 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7999 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8000 | { |
8001 | struct drm_device *dev = crtc->base.dev; | |
8002 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8003 | uint32_t tmp; | |
8004 | ||
dc9e7dec VS |
8005 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
8006 | return; | |
8007 | ||
2fa2fe9a | 8008 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
8009 | if (!(tmp & PFIT_ENABLE)) |
8010 | return; | |
2fa2fe9a | 8011 | |
06922821 | 8012 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
8013 | if (INTEL_INFO(dev)->gen < 4) { |
8014 | if (crtc->pipe != PIPE_B) | |
8015 | return; | |
2fa2fe9a DV |
8016 | } else { |
8017 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
8018 | return; | |
8019 | } | |
8020 | ||
06922821 | 8021 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
8022 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
8023 | if (INTEL_INFO(dev)->gen < 5) | |
8024 | pipe_config->gmch_pfit.lvds_border_bits = | |
8025 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
8026 | } | |
8027 | ||
acbec814 | 8028 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8029 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
8030 | { |
8031 | struct drm_device *dev = crtc->base.dev; | |
8032 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8033 | int pipe = pipe_config->cpu_transcoder; | |
8034 | intel_clock_t clock; | |
8035 | u32 mdiv; | |
662c6ecb | 8036 | int refclk = 100000; |
acbec814 | 8037 | |
f573de5a SK |
8038 | /* In case of MIPI DPLL will not even be used */ |
8039 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
8040 | return; | |
8041 | ||
a580516d | 8042 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 8043 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 8044 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
8045 | |
8046 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
8047 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
8048 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
8049 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
8050 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
8051 | ||
dccbea3b | 8052 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
8053 | } |
8054 | ||
5724dbd1 DL |
8055 | static void |
8056 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
8057 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
8058 | { |
8059 | struct drm_device *dev = crtc->base.dev; | |
8060 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8061 | u32 val, base, offset; | |
8062 | int pipe = crtc->pipe, plane = crtc->plane; | |
8063 | int fourcc, pixel_format; | |
6761dd31 | 8064 | unsigned int aligned_height; |
b113d5ee | 8065 | struct drm_framebuffer *fb; |
1b842c89 | 8066 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 8067 | |
42a7b088 DL |
8068 | val = I915_READ(DSPCNTR(plane)); |
8069 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8070 | return; | |
8071 | ||
d9806c9f | 8072 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8073 | if (!intel_fb) { |
1ad292b5 JB |
8074 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8075 | return; | |
8076 | } | |
8077 | ||
1b842c89 DL |
8078 | fb = &intel_fb->base; |
8079 | ||
18c5247e DV |
8080 | if (INTEL_INFO(dev)->gen >= 4) { |
8081 | if (val & DISPPLANE_TILED) { | |
49af449b | 8082 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8083 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8084 | } | |
8085 | } | |
1ad292b5 JB |
8086 | |
8087 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8088 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8089 | fb->pixel_format = fourcc; |
8090 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
8091 | |
8092 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 8093 | if (plane_config->tiling) |
1ad292b5 JB |
8094 | offset = I915_READ(DSPTILEOFF(plane)); |
8095 | else | |
8096 | offset = I915_READ(DSPLINOFF(plane)); | |
8097 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8098 | } else { | |
8099 | base = I915_READ(DSPADDR(plane)); | |
8100 | } | |
8101 | plane_config->base = base; | |
8102 | ||
8103 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8104 | fb->width = ((val >> 16) & 0xfff) + 1; |
8105 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8106 | |
8107 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8108 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8109 | |
b113d5ee | 8110 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8111 | fb->pixel_format, |
8112 | fb->modifier[0]); | |
1ad292b5 | 8113 | |
f37b5c2b | 8114 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8115 | |
2844a921 DL |
8116 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8117 | pipe_name(pipe), plane, fb->width, fb->height, | |
8118 | fb->bits_per_pixel, base, fb->pitches[0], | |
8119 | plane_config->size); | |
1ad292b5 | 8120 | |
2d14030b | 8121 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8122 | } |
8123 | ||
70b23a98 | 8124 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8125 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8126 | { |
8127 | struct drm_device *dev = crtc->base.dev; | |
8128 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8129 | int pipe = pipe_config->cpu_transcoder; | |
8130 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
8131 | intel_clock_t clock; | |
0d7b6b11 | 8132 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8133 | int refclk = 100000; |
8134 | ||
a580516d | 8135 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8136 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8137 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8138 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8139 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8140 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8141 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8142 | |
8143 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8144 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8145 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8146 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8147 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8148 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8149 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8150 | ||
dccbea3b | 8151 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8152 | } |
8153 | ||
0e8ffe1b | 8154 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8155 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8156 | { |
8157 | struct drm_device *dev = crtc->base.dev; | |
8158 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8159 | uint32_t tmp; | |
8160 | ||
f458ebbc DV |
8161 | if (!intel_display_power_is_enabled(dev_priv, |
8162 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
b5482bd0 ID |
8163 | return false; |
8164 | ||
e143a21c | 8165 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 8166 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 8167 | |
0e8ffe1b DV |
8168 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8169 | if (!(tmp & PIPECONF_ENABLE)) | |
8170 | return false; | |
8171 | ||
666a4537 | 8172 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
42571aef VS |
8173 | switch (tmp & PIPECONF_BPC_MASK) { |
8174 | case PIPECONF_6BPC: | |
8175 | pipe_config->pipe_bpp = 18; | |
8176 | break; | |
8177 | case PIPECONF_8BPC: | |
8178 | pipe_config->pipe_bpp = 24; | |
8179 | break; | |
8180 | case PIPECONF_10BPC: | |
8181 | pipe_config->pipe_bpp = 30; | |
8182 | break; | |
8183 | default: | |
8184 | break; | |
8185 | } | |
8186 | } | |
8187 | ||
666a4537 WB |
8188 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
8189 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) | |
b5a9fa09 DV |
8190 | pipe_config->limited_color_range = true; |
8191 | ||
282740f7 VS |
8192 | if (INTEL_INFO(dev)->gen < 4) |
8193 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8194 | ||
1bd1bd80 DV |
8195 | intel_get_pipe_timings(crtc, pipe_config); |
8196 | ||
2fa2fe9a DV |
8197 | i9xx_get_pfit_config(crtc, pipe_config); |
8198 | ||
6c49f241 DV |
8199 | if (INTEL_INFO(dev)->gen >= 4) { |
8200 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
8201 | pipe_config->pixel_multiplier = | |
8202 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8203 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8204 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
8205 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
8206 | tmp = I915_READ(DPLL(crtc->pipe)); | |
8207 | pipe_config->pixel_multiplier = | |
8208 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8209 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8210 | } else { | |
8211 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8212 | * port and will be fixed up in the encoder->get_config | |
8213 | * function. */ | |
8214 | pipe_config->pixel_multiplier = 1; | |
8215 | } | |
8bcc2795 | 8216 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
666a4537 | 8217 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
1c4e0274 VS |
8218 | /* |
8219 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8220 | * on 830. Filter it out here so that we don't | |
8221 | * report errors due to that. | |
8222 | */ | |
8223 | if (IS_I830(dev)) | |
8224 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
8225 | ||
8bcc2795 DV |
8226 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8227 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8228 | } else { |
8229 | /* Mask out read-only status bits. */ | |
8230 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8231 | DPLL_PORTC_READY_MASK | | |
8232 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8233 | } |
6c49f241 | 8234 | |
70b23a98 VS |
8235 | if (IS_CHERRYVIEW(dev)) |
8236 | chv_crtc_clock_get(crtc, pipe_config); | |
8237 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
8238 | vlv_crtc_clock_get(crtc, pipe_config); |
8239 | else | |
8240 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8241 | |
0f64614d VS |
8242 | /* |
8243 | * Normally the dotclock is filled in by the encoder .get_config() | |
8244 | * but in case the pipe is enabled w/o any ports we need a sane | |
8245 | * default. | |
8246 | */ | |
8247 | pipe_config->base.adjusted_mode.crtc_clock = | |
8248 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8249 | ||
0e8ffe1b DV |
8250 | return true; |
8251 | } | |
8252 | ||
dde86e2d | 8253 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
8254 | { |
8255 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 8256 | struct intel_encoder *encoder; |
74cfd7ac | 8257 | u32 val, final; |
13d83a67 | 8258 | bool has_lvds = false; |
199e5d79 | 8259 | bool has_cpu_edp = false; |
199e5d79 | 8260 | bool has_panel = false; |
99eb6a01 KP |
8261 | bool has_ck505 = false; |
8262 | bool can_ssc = false; | |
13d83a67 JB |
8263 | |
8264 | /* We need to take the global config into account */ | |
b2784e15 | 8265 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8266 | switch (encoder->type) { |
8267 | case INTEL_OUTPUT_LVDS: | |
8268 | has_panel = true; | |
8269 | has_lvds = true; | |
8270 | break; | |
8271 | case INTEL_OUTPUT_EDP: | |
8272 | has_panel = true; | |
2de6905f | 8273 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8274 | has_cpu_edp = true; |
8275 | break; | |
6847d71b PZ |
8276 | default: |
8277 | break; | |
13d83a67 JB |
8278 | } |
8279 | } | |
8280 | ||
99eb6a01 | 8281 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 8282 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8283 | can_ssc = has_ck505; |
8284 | } else { | |
8285 | has_ck505 = false; | |
8286 | can_ssc = true; | |
8287 | } | |
8288 | ||
2de6905f ID |
8289 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
8290 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
8291 | |
8292 | /* Ironlake: try to setup display ref clock before DPLL | |
8293 | * enabling. This is only under driver's control after | |
8294 | * PCH B stepping, previous chipset stepping should be | |
8295 | * ignoring this setting. | |
8296 | */ | |
74cfd7ac CW |
8297 | val = I915_READ(PCH_DREF_CONTROL); |
8298 | ||
8299 | /* As we must carefully and slowly disable/enable each source in turn, | |
8300 | * compute the final state we want first and check if we need to | |
8301 | * make any changes at all. | |
8302 | */ | |
8303 | final = val; | |
8304 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8305 | if (has_ck505) | |
8306 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8307 | else | |
8308 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8309 | ||
8310 | final &= ~DREF_SSC_SOURCE_MASK; | |
8311 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
8312 | final &= ~DREF_SSC1_ENABLE; | |
8313 | ||
8314 | if (has_panel) { | |
8315 | final |= DREF_SSC_SOURCE_ENABLE; | |
8316 | ||
8317 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8318 | final |= DREF_SSC1_ENABLE; | |
8319 | ||
8320 | if (has_cpu_edp) { | |
8321 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8322 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8323 | else | |
8324 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8325 | } else | |
8326 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8327 | } else { | |
8328 | final |= DREF_SSC_SOURCE_DISABLE; | |
8329 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8330 | } | |
8331 | ||
8332 | if (final == val) | |
8333 | return; | |
8334 | ||
13d83a67 | 8335 | /* Always enable nonspread source */ |
74cfd7ac | 8336 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8337 | |
99eb6a01 | 8338 | if (has_ck505) |
74cfd7ac | 8339 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 8340 | else |
74cfd7ac | 8341 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 8342 | |
199e5d79 | 8343 | if (has_panel) { |
74cfd7ac CW |
8344 | val &= ~DREF_SSC_SOURCE_MASK; |
8345 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 8346 | |
199e5d79 | 8347 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 8348 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8349 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 8350 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 8351 | } else |
74cfd7ac | 8352 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
8353 | |
8354 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 8355 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8356 | POSTING_READ(PCH_DREF_CONTROL); |
8357 | udelay(200); | |
8358 | ||
74cfd7ac | 8359 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
8360 | |
8361 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 8362 | if (has_cpu_edp) { |
99eb6a01 | 8363 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8364 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 8365 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 8366 | } else |
74cfd7ac | 8367 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 8368 | } else |
74cfd7ac | 8369 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8370 | |
74cfd7ac | 8371 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8372 | POSTING_READ(PCH_DREF_CONTROL); |
8373 | udelay(200); | |
8374 | } else { | |
8375 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
8376 | ||
74cfd7ac | 8377 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
8378 | |
8379 | /* Turn off CPU output */ | |
74cfd7ac | 8380 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8381 | |
74cfd7ac | 8382 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8383 | POSTING_READ(PCH_DREF_CONTROL); |
8384 | udelay(200); | |
8385 | ||
8386 | /* Turn off the SSC source */ | |
74cfd7ac CW |
8387 | val &= ~DREF_SSC_SOURCE_MASK; |
8388 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
8389 | |
8390 | /* Turn off SSC1 */ | |
74cfd7ac | 8391 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 8392 | |
74cfd7ac | 8393 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
8394 | POSTING_READ(PCH_DREF_CONTROL); |
8395 | udelay(200); | |
8396 | } | |
74cfd7ac CW |
8397 | |
8398 | BUG_ON(val != final); | |
13d83a67 JB |
8399 | } |
8400 | ||
f31f2d55 | 8401 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 8402 | { |
f31f2d55 | 8403 | uint32_t tmp; |
dde86e2d | 8404 | |
0ff066a9 PZ |
8405 | tmp = I915_READ(SOUTH_CHICKEN2); |
8406 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8407 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8408 | |
0ff066a9 PZ |
8409 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
8410 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
8411 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 8412 | |
0ff066a9 PZ |
8413 | tmp = I915_READ(SOUTH_CHICKEN2); |
8414 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8415 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8416 | |
0ff066a9 PZ |
8417 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
8418 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
8419 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
8420 | } |
8421 | ||
8422 | /* WaMPhyProgramming:hsw */ | |
8423 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8424 | { | |
8425 | uint32_t tmp; | |
dde86e2d PZ |
8426 | |
8427 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8428 | tmp &= ~(0xFF << 24); | |
8429 | tmp |= (0x12 << 24); | |
8430 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8431 | ||
dde86e2d PZ |
8432 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
8433 | tmp |= (1 << 11); | |
8434 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8435 | ||
8436 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8437 | tmp |= (1 << 11); | |
8438 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8439 | ||
dde86e2d PZ |
8440 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
8441 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8442 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
8443 | ||
8444 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
8445 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8446 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8447 | ||
0ff066a9 PZ |
8448 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
8449 | tmp &= ~(7 << 13); | |
8450 | tmp |= (5 << 13); | |
8451 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 8452 | |
0ff066a9 PZ |
8453 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
8454 | tmp &= ~(7 << 13); | |
8455 | tmp |= (5 << 13); | |
8456 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
8457 | |
8458 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8459 | tmp &= ~0xFF; | |
8460 | tmp |= 0x1C; | |
8461 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8462 | ||
8463 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8464 | tmp &= ~0xFF; | |
8465 | tmp |= 0x1C; | |
8466 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8467 | ||
8468 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8469 | tmp &= ~(0xFF << 16); | |
8470 | tmp |= (0x1C << 16); | |
8471 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8472 | ||
8473 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8474 | tmp &= ~(0xFF << 16); | |
8475 | tmp |= (0x1C << 16); | |
8476 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8477 | ||
0ff066a9 PZ |
8478 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8479 | tmp |= (1 << 27); | |
8480 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8481 | |
0ff066a9 PZ |
8482 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8483 | tmp |= (1 << 27); | |
8484 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8485 | |
0ff066a9 PZ |
8486 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8487 | tmp &= ~(0xF << 28); | |
8488 | tmp |= (4 << 28); | |
8489 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8490 | |
0ff066a9 PZ |
8491 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8492 | tmp &= ~(0xF << 28); | |
8493 | tmp |= (4 << 28); | |
8494 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8495 | } |
8496 | ||
2fa86a1f PZ |
8497 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8498 | * Programming" based on the parameters passed: | |
8499 | * - Sequence to enable CLKOUT_DP | |
8500 | * - Sequence to enable CLKOUT_DP without spread | |
8501 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8502 | */ | |
8503 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8504 | bool with_fdi) | |
f31f2d55 PZ |
8505 | { |
8506 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
8507 | uint32_t reg, tmp; |
8508 | ||
8509 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8510 | with_spread = true; | |
c2699524 | 8511 | if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) |
2fa86a1f | 8512 | with_fdi = false; |
f31f2d55 | 8513 | |
a580516d | 8514 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
8515 | |
8516 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8517 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8518 | tmp |= SBI_SSCCTL_PATHALT; | |
8519 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8520 | ||
8521 | udelay(24); | |
8522 | ||
2fa86a1f PZ |
8523 | if (with_spread) { |
8524 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8525 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8526 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8527 | |
2fa86a1f PZ |
8528 | if (with_fdi) { |
8529 | lpt_reset_fdi_mphy(dev_priv); | |
8530 | lpt_program_fdi_mphy(dev_priv); | |
8531 | } | |
8532 | } | |
dde86e2d | 8533 | |
c2699524 | 8534 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
8535 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8536 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8537 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 8538 | |
a580516d | 8539 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
8540 | } |
8541 | ||
47701c3b PZ |
8542 | /* Sequence to disable CLKOUT_DP */ |
8543 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8544 | { | |
8545 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8546 | uint32_t reg, tmp; | |
8547 | ||
a580516d | 8548 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 8549 | |
c2699524 | 8550 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
8551 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8552 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8553 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8554 | ||
8555 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8556 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8557 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8558 | tmp |= SBI_SSCCTL_PATHALT; | |
8559 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8560 | udelay(32); | |
8561 | } | |
8562 | tmp |= SBI_SSCCTL_DISABLE; | |
8563 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8564 | } | |
8565 | ||
a580516d | 8566 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8567 | } |
8568 | ||
f7be2c21 VS |
8569 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
8570 | ||
8571 | static const uint16_t sscdivintphase[] = { | |
8572 | [BEND_IDX( 50)] = 0x3B23, | |
8573 | [BEND_IDX( 45)] = 0x3B23, | |
8574 | [BEND_IDX( 40)] = 0x3C23, | |
8575 | [BEND_IDX( 35)] = 0x3C23, | |
8576 | [BEND_IDX( 30)] = 0x3D23, | |
8577 | [BEND_IDX( 25)] = 0x3D23, | |
8578 | [BEND_IDX( 20)] = 0x3E23, | |
8579 | [BEND_IDX( 15)] = 0x3E23, | |
8580 | [BEND_IDX( 10)] = 0x3F23, | |
8581 | [BEND_IDX( 5)] = 0x3F23, | |
8582 | [BEND_IDX( 0)] = 0x0025, | |
8583 | [BEND_IDX( -5)] = 0x0025, | |
8584 | [BEND_IDX(-10)] = 0x0125, | |
8585 | [BEND_IDX(-15)] = 0x0125, | |
8586 | [BEND_IDX(-20)] = 0x0225, | |
8587 | [BEND_IDX(-25)] = 0x0225, | |
8588 | [BEND_IDX(-30)] = 0x0325, | |
8589 | [BEND_IDX(-35)] = 0x0325, | |
8590 | [BEND_IDX(-40)] = 0x0425, | |
8591 | [BEND_IDX(-45)] = 0x0425, | |
8592 | [BEND_IDX(-50)] = 0x0525, | |
8593 | }; | |
8594 | ||
8595 | /* | |
8596 | * Bend CLKOUT_DP | |
8597 | * steps -50 to 50 inclusive, in steps of 5 | |
8598 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
8599 | * change in clock period = -(steps / 10) * 5.787 ps | |
8600 | */ | |
8601 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
8602 | { | |
8603 | uint32_t tmp; | |
8604 | int idx = BEND_IDX(steps); | |
8605 | ||
8606 | if (WARN_ON(steps % 5 != 0)) | |
8607 | return; | |
8608 | ||
8609 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
8610 | return; | |
8611 | ||
8612 | mutex_lock(&dev_priv->sb_lock); | |
8613 | ||
8614 | if (steps % 10 != 0) | |
8615 | tmp = 0xAAAAAAAB; | |
8616 | else | |
8617 | tmp = 0x00000000; | |
8618 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
8619 | ||
8620 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
8621 | tmp &= 0xffff0000; | |
8622 | tmp |= sscdivintphase[idx]; | |
8623 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
8624 | ||
8625 | mutex_unlock(&dev_priv->sb_lock); | |
8626 | } | |
8627 | ||
8628 | #undef BEND_IDX | |
8629 | ||
bf8fa3d3 PZ |
8630 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8631 | { | |
bf8fa3d3 PZ |
8632 | struct intel_encoder *encoder; |
8633 | bool has_vga = false; | |
8634 | ||
b2784e15 | 8635 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8636 | switch (encoder->type) { |
8637 | case INTEL_OUTPUT_ANALOG: | |
8638 | has_vga = true; | |
8639 | break; | |
6847d71b PZ |
8640 | default: |
8641 | break; | |
bf8fa3d3 PZ |
8642 | } |
8643 | } | |
8644 | ||
f7be2c21 VS |
8645 | if (has_vga) { |
8646 | lpt_bend_clkout_dp(to_i915(dev), 0); | |
47701c3b | 8647 | lpt_enable_clkout_dp(dev, true, true); |
f7be2c21 | 8648 | } else { |
47701c3b | 8649 | lpt_disable_clkout_dp(dev); |
f7be2c21 | 8650 | } |
bf8fa3d3 PZ |
8651 | } |
8652 | ||
dde86e2d PZ |
8653 | /* |
8654 | * Initialize reference clocks when the driver loads | |
8655 | */ | |
8656 | void intel_init_pch_refclk(struct drm_device *dev) | |
8657 | { | |
8658 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8659 | ironlake_init_pch_refclk(dev); | |
8660 | else if (HAS_PCH_LPT(dev)) | |
8661 | lpt_init_pch_refclk(dev); | |
8662 | } | |
8663 | ||
55bb9992 | 8664 | static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) |
d9d444cb | 8665 | { |
55bb9992 | 8666 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d9d444cb | 8667 | struct drm_i915_private *dev_priv = dev->dev_private; |
55bb9992 | 8668 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8669 | struct drm_connector *connector; |
55bb9992 | 8670 | struct drm_connector_state *connector_state; |
d9d444cb | 8671 | struct intel_encoder *encoder; |
55bb9992 | 8672 | int num_connectors = 0, i; |
d9d444cb JB |
8673 | bool is_lvds = false; |
8674 | ||
da3ced29 | 8675 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8676 | if (connector_state->crtc != crtc_state->base.crtc) |
8677 | continue; | |
8678 | ||
8679 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8680 | ||
d9d444cb JB |
8681 | switch (encoder->type) { |
8682 | case INTEL_OUTPUT_LVDS: | |
8683 | is_lvds = true; | |
8684 | break; | |
6847d71b PZ |
8685 | default: |
8686 | break; | |
d9d444cb JB |
8687 | } |
8688 | num_connectors++; | |
8689 | } | |
8690 | ||
8691 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 8692 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 8693 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 8694 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
8695 | } |
8696 | ||
8697 | return 120000; | |
8698 | } | |
8699 | ||
6ff93609 | 8700 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8701 | { |
c8203565 | 8702 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
8703 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8704 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8705 | uint32_t val; |
8706 | ||
78114071 | 8707 | val = 0; |
c8203565 | 8708 | |
6e3c9717 | 8709 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8710 | case 18: |
dfd07d72 | 8711 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8712 | break; |
8713 | case 24: | |
dfd07d72 | 8714 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8715 | break; |
8716 | case 30: | |
dfd07d72 | 8717 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8718 | break; |
8719 | case 36: | |
dfd07d72 | 8720 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8721 | break; |
8722 | default: | |
cc769b62 PZ |
8723 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8724 | BUG(); | |
c8203565 PZ |
8725 | } |
8726 | ||
6e3c9717 | 8727 | if (intel_crtc->config->dither) |
c8203565 PZ |
8728 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8729 | ||
6e3c9717 | 8730 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8731 | val |= PIPECONF_INTERLACED_ILK; |
8732 | else | |
8733 | val |= PIPECONF_PROGRESSIVE; | |
8734 | ||
6e3c9717 | 8735 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8736 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8737 | |
c8203565 PZ |
8738 | I915_WRITE(PIPECONF(pipe), val); |
8739 | POSTING_READ(PIPECONF(pipe)); | |
8740 | } | |
8741 | ||
86d3efce VS |
8742 | /* |
8743 | * Set up the pipe CSC unit. | |
8744 | * | |
8745 | * Currently only full range RGB to limited range RGB conversion | |
8746 | * is supported, but eventually this should handle various | |
8747 | * RGB<->YCbCr scenarios as well. | |
8748 | */ | |
50f3b016 | 8749 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
8750 | { |
8751 | struct drm_device *dev = crtc->dev; | |
8752 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8753 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8754 | int pipe = intel_crtc->pipe; | |
8755 | uint16_t coeff = 0x7800; /* 1.0 */ | |
8756 | ||
8757 | /* | |
8758 | * TODO: Check what kind of values actually come out of the pipe | |
8759 | * with these coeff/postoff values and adjust to get the best | |
8760 | * accuracy. Perhaps we even need to take the bpc value into | |
8761 | * consideration. | |
8762 | */ | |
8763 | ||
6e3c9717 | 8764 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8765 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
8766 | ||
8767 | /* | |
8768 | * GY/GU and RY/RU should be the other way around according | |
8769 | * to BSpec, but reality doesn't agree. Just set them up in | |
8770 | * a way that results in the correct picture. | |
8771 | */ | |
8772 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
8773 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
8774 | ||
8775 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
8776 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
8777 | ||
8778 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
8779 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
8780 | ||
8781 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
8782 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
8783 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
8784 | ||
8785 | if (INTEL_INFO(dev)->gen > 6) { | |
8786 | uint16_t postoff = 0; | |
8787 | ||
6e3c9717 | 8788 | if (intel_crtc->config->limited_color_range) |
32cf0cb0 | 8789 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
8790 | |
8791 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
8792 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
8793 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
8794 | ||
8795 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
8796 | } else { | |
8797 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
8798 | ||
6e3c9717 | 8799 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8800 | mode |= CSC_BLACK_SCREEN_OFFSET; |
8801 | ||
8802 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
8803 | } | |
8804 | } | |
8805 | ||
6ff93609 | 8806 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8807 | { |
756f85cf PZ |
8808 | struct drm_device *dev = crtc->dev; |
8809 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 8810 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 8811 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 8812 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee2b0b38 PZ |
8813 | uint32_t val; |
8814 | ||
3eff4faa | 8815 | val = 0; |
ee2b0b38 | 8816 | |
6e3c9717 | 8817 | if (IS_HASWELL(dev) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8818 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8819 | ||
6e3c9717 | 8820 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8821 | val |= PIPECONF_INTERLACED_ILK; |
8822 | else | |
8823 | val |= PIPECONF_PROGRESSIVE; | |
8824 | ||
702e7a56 PZ |
8825 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8826 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
8827 | |
8828 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
8829 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 8830 | |
3cdf122c | 8831 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
8832 | val = 0; |
8833 | ||
6e3c9717 | 8834 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8835 | case 18: |
8836 | val |= PIPEMISC_DITHER_6_BPC; | |
8837 | break; | |
8838 | case 24: | |
8839 | val |= PIPEMISC_DITHER_8_BPC; | |
8840 | break; | |
8841 | case 30: | |
8842 | val |= PIPEMISC_DITHER_10_BPC; | |
8843 | break; | |
8844 | case 36: | |
8845 | val |= PIPEMISC_DITHER_12_BPC; | |
8846 | break; | |
8847 | default: | |
8848 | /* Case prevented by pipe_config_set_bpp. */ | |
8849 | BUG(); | |
8850 | } | |
8851 | ||
6e3c9717 | 8852 | if (intel_crtc->config->dither) |
756f85cf PZ |
8853 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8854 | ||
8855 | I915_WRITE(PIPEMISC(pipe), val); | |
8856 | } | |
ee2b0b38 PZ |
8857 | } |
8858 | ||
6591c6e4 | 8859 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
190f68c5 | 8860 | struct intel_crtc_state *crtc_state, |
6591c6e4 PZ |
8861 | intel_clock_t *clock, |
8862 | bool *has_reduced_clock, | |
8863 | intel_clock_t *reduced_clock) | |
8864 | { | |
8865 | struct drm_device *dev = crtc->dev; | |
8866 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6591c6e4 | 8867 | int refclk; |
d4906093 | 8868 | const intel_limit_t *limit; |
c329a4ec | 8869 | bool ret; |
79e53945 | 8870 | |
55bb9992 | 8871 | refclk = ironlake_get_refclk(crtc_state); |
79e53945 | 8872 | |
d4906093 ML |
8873 | /* |
8874 | * Returns a set of divisors for the desired target clock with the given | |
8875 | * refclk, or FALSE. The returned values represent the clock equation: | |
8876 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
8877 | */ | |
a93e255f ACO |
8878 | limit = intel_limit(crtc_state, refclk); |
8879 | ret = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 8880 | crtc_state->port_clock, |
ee9300bb | 8881 | refclk, NULL, clock); |
6591c6e4 PZ |
8882 | if (!ret) |
8883 | return false; | |
cda4b7d3 | 8884 | |
6591c6e4 PZ |
8885 | return true; |
8886 | } | |
8887 | ||
d4b1931c PZ |
8888 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8889 | { | |
8890 | /* | |
8891 | * Account for spread spectrum to avoid | |
8892 | * oversubscribing the link. Max center spread | |
8893 | * is 2.5%; use 5% for safety's sake. | |
8894 | */ | |
8895 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8896 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8897 | } |
8898 | ||
7429e9d4 | 8899 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8900 | { |
7429e9d4 | 8901 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8902 | } |
8903 | ||
de13a2e3 | 8904 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
190f68c5 | 8905 | struct intel_crtc_state *crtc_state, |
7429e9d4 | 8906 | u32 *fp, |
9a7c7890 | 8907 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 8908 | { |
de13a2e3 | 8909 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
8910 | struct drm_device *dev = crtc->dev; |
8911 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 | 8912 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8913 | struct drm_connector *connector; |
55bb9992 ACO |
8914 | struct drm_connector_state *connector_state; |
8915 | struct intel_encoder *encoder; | |
de13a2e3 | 8916 | uint32_t dpll; |
55bb9992 | 8917 | int factor, num_connectors = 0, i; |
09ede541 | 8918 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 8919 | |
da3ced29 | 8920 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8921 | if (connector_state->crtc != crtc_state->base.crtc) |
8922 | continue; | |
8923 | ||
8924 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8925 | ||
8926 | switch (encoder->type) { | |
79e53945 JB |
8927 | case INTEL_OUTPUT_LVDS: |
8928 | is_lvds = true; | |
8929 | break; | |
8930 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 8931 | case INTEL_OUTPUT_HDMI: |
79e53945 | 8932 | is_sdvo = true; |
79e53945 | 8933 | break; |
6847d71b PZ |
8934 | default: |
8935 | break; | |
79e53945 | 8936 | } |
43565a06 | 8937 | |
c751ce4f | 8938 | num_connectors++; |
79e53945 | 8939 | } |
79e53945 | 8940 | |
c1858123 | 8941 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
8942 | factor = 21; |
8943 | if (is_lvds) { | |
8944 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 8945 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 8946 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8947 | factor = 25; |
190f68c5 | 8948 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8949 | factor = 20; |
c1858123 | 8950 | |
190f68c5 | 8951 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
7d0ac5b7 | 8952 | *fp |= FP_CB_TUNE; |
2c07245f | 8953 | |
9a7c7890 DV |
8954 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
8955 | *fp2 |= FP_CB_TUNE; | |
8956 | ||
5eddb70b | 8957 | dpll = 0; |
2c07245f | 8958 | |
a07d6787 EA |
8959 | if (is_lvds) |
8960 | dpll |= DPLLB_MODE_LVDS; | |
8961 | else | |
8962 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8963 | |
190f68c5 | 8964 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8965 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
8966 | |
8967 | if (is_sdvo) | |
4a33e48d | 8968 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 8969 | if (crtc_state->has_dp_encoder) |
4a33e48d | 8970 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8971 | |
a07d6787 | 8972 | /* compute bitmask from p1 value */ |
190f68c5 | 8973 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8974 | /* also FPA1 */ |
190f68c5 | 8975 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8976 | |
190f68c5 | 8977 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8978 | case 5: |
8979 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8980 | break; | |
8981 | case 7: | |
8982 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8983 | break; | |
8984 | case 10: | |
8985 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8986 | break; | |
8987 | case 14: | |
8988 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8989 | break; | |
79e53945 JB |
8990 | } |
8991 | ||
b4c09f3b | 8992 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 8993 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8994 | else |
8995 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8996 | ||
959e16d6 | 8997 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
8998 | } |
8999 | ||
190f68c5 ACO |
9000 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
9001 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 9002 | { |
c7653199 | 9003 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 9004 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 9005 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 9006 | bool ok, has_reduced_clock = false; |
8b47047b | 9007 | bool is_lvds = false; |
e2b78267 | 9008 | struct intel_shared_dpll *pll; |
de13a2e3 | 9009 | |
dd3cd74a ACO |
9010 | memset(&crtc_state->dpll_hw_state, 0, |
9011 | sizeof(crtc_state->dpll_hw_state)); | |
9012 | ||
7905df29 | 9013 | is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS); |
79e53945 | 9014 | |
5dc5298b PZ |
9015 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
9016 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 9017 | |
190f68c5 | 9018 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
de13a2e3 | 9019 | &has_reduced_clock, &reduced_clock); |
190f68c5 | 9020 | if (!ok && !crtc_state->clock_set) { |
de13a2e3 PZ |
9021 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
9022 | return -EINVAL; | |
79e53945 | 9023 | } |
f47709a9 | 9024 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
9025 | if (!crtc_state->clock_set) { |
9026 | crtc_state->dpll.n = clock.n; | |
9027 | crtc_state->dpll.m1 = clock.m1; | |
9028 | crtc_state->dpll.m2 = clock.m2; | |
9029 | crtc_state->dpll.p1 = clock.p1; | |
9030 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 9031 | } |
79e53945 | 9032 | |
5dc5298b | 9033 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
190f68c5 ACO |
9034 | if (crtc_state->has_pch_encoder) { |
9035 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
cbbab5bd | 9036 | if (has_reduced_clock) |
7429e9d4 | 9037 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 9038 | |
190f68c5 | 9039 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
cbbab5bd DV |
9040 | &fp, &reduced_clock, |
9041 | has_reduced_clock ? &fp2 : NULL); | |
9042 | ||
190f68c5 ACO |
9043 | crtc_state->dpll_hw_state.dpll = dpll; |
9044 | crtc_state->dpll_hw_state.fp0 = fp; | |
66e985c0 | 9045 | if (has_reduced_clock) |
190f68c5 | 9046 | crtc_state->dpll_hw_state.fp1 = fp2; |
66e985c0 | 9047 | else |
190f68c5 | 9048 | crtc_state->dpll_hw_state.fp1 = fp; |
66e985c0 | 9049 | |
190f68c5 | 9050 | pll = intel_get_shared_dpll(crtc, crtc_state); |
ee7b9f93 | 9051 | if (pll == NULL) { |
84f44ce7 | 9052 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 9053 | pipe_name(crtc->pipe)); |
4b645f14 JB |
9054 | return -EINVAL; |
9055 | } | |
3fb37703 | 9056 | } |
79e53945 | 9057 | |
ab585dea | 9058 | if (is_lvds && has_reduced_clock) |
c7653199 | 9059 | crtc->lowfreq_avail = true; |
bcd644e0 | 9060 | else |
c7653199 | 9061 | crtc->lowfreq_avail = false; |
e2b78267 | 9062 | |
c8f7a0db | 9063 | return 0; |
79e53945 JB |
9064 | } |
9065 | ||
eb14cb74 VS |
9066 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
9067 | struct intel_link_m_n *m_n) | |
9068 | { | |
9069 | struct drm_device *dev = crtc->base.dev; | |
9070 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9071 | enum pipe pipe = crtc->pipe; | |
9072 | ||
9073 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
9074 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
9075 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9076 | & ~TU_SIZE_MASK; | |
9077 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
9078 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9079 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9080 | } | |
9081 | ||
9082 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
9083 | enum transcoder transcoder, | |
b95af8be VK |
9084 | struct intel_link_m_n *m_n, |
9085 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
9086 | { |
9087 | struct drm_device *dev = crtc->base.dev; | |
9088 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 9089 | enum pipe pipe = crtc->pipe; |
72419203 | 9090 | |
eb14cb74 VS |
9091 | if (INTEL_INFO(dev)->gen >= 5) { |
9092 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
9093 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
9094 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
9095 | & ~TU_SIZE_MASK; | |
9096 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
9097 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
9098 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
9099 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
9100 | * gen < 8) and if DRRS is supported (to make sure the | |
9101 | * registers are not unnecessarily read). | |
9102 | */ | |
9103 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 9104 | crtc->config->has_drrs) { |
b95af8be VK |
9105 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
9106 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
9107 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
9108 | & ~TU_SIZE_MASK; | |
9109 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
9110 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
9111 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9112 | } | |
eb14cb74 VS |
9113 | } else { |
9114 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
9115 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
9116 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9117 | & ~TU_SIZE_MASK; | |
9118 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
9119 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9120 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9121 | } | |
9122 | } | |
9123 | ||
9124 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 9125 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 9126 | { |
681a8504 | 9127 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
9128 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
9129 | else | |
9130 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
9131 | &pipe_config->dp_m_n, |
9132 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 9133 | } |
72419203 | 9134 | |
eb14cb74 | 9135 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 9136 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
9137 | { |
9138 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 9139 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
9140 | } |
9141 | ||
bd2e244f | 9142 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9143 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
9144 | { |
9145 | struct drm_device *dev = crtc->base.dev; | |
9146 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a1b2278e CK |
9147 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
9148 | uint32_t ps_ctrl = 0; | |
9149 | int id = -1; | |
9150 | int i; | |
bd2e244f | 9151 | |
a1b2278e CK |
9152 | /* find scaler attached to this pipe */ |
9153 | for (i = 0; i < crtc->num_scalers; i++) { | |
9154 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9155 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9156 | id = i; | |
9157 | pipe_config->pch_pfit.enabled = true; | |
9158 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9159 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9160 | break; | |
9161 | } | |
9162 | } | |
bd2e244f | 9163 | |
a1b2278e CK |
9164 | scaler_state->scaler_id = id; |
9165 | if (id >= 0) { | |
9166 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9167 | } else { | |
9168 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9169 | } |
9170 | } | |
9171 | ||
5724dbd1 DL |
9172 | static void |
9173 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9174 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9175 | { |
9176 | struct drm_device *dev = crtc->base.dev; | |
9177 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 9178 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9179 | int pipe = crtc->pipe; |
9180 | int fourcc, pixel_format; | |
6761dd31 | 9181 | unsigned int aligned_height; |
bc8d7dff | 9182 | struct drm_framebuffer *fb; |
1b842c89 | 9183 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9184 | |
d9806c9f | 9185 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9186 | if (!intel_fb) { |
bc8d7dff DL |
9187 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9188 | return; | |
9189 | } | |
9190 | ||
1b842c89 DL |
9191 | fb = &intel_fb->base; |
9192 | ||
bc8d7dff | 9193 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9194 | if (!(val & PLANE_CTL_ENABLE)) |
9195 | goto error; | |
9196 | ||
bc8d7dff DL |
9197 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9198 | fourcc = skl_format_to_fourcc(pixel_format, | |
9199 | val & PLANE_CTL_ORDER_RGBX, | |
9200 | val & PLANE_CTL_ALPHA_MASK); | |
9201 | fb->pixel_format = fourcc; | |
9202 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9203 | ||
40f46283 DL |
9204 | tiling = val & PLANE_CTL_TILED_MASK; |
9205 | switch (tiling) { | |
9206 | case PLANE_CTL_TILED_LINEAR: | |
9207 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9208 | break; | |
9209 | case PLANE_CTL_TILED_X: | |
9210 | plane_config->tiling = I915_TILING_X; | |
9211 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9212 | break; | |
9213 | case PLANE_CTL_TILED_Y: | |
9214 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9215 | break; | |
9216 | case PLANE_CTL_TILED_YF: | |
9217 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9218 | break; | |
9219 | default: | |
9220 | MISSING_CASE(tiling); | |
9221 | goto error; | |
9222 | } | |
9223 | ||
bc8d7dff DL |
9224 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9225 | plane_config->base = base; | |
9226 | ||
9227 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9228 | ||
9229 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9230 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9231 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9232 | ||
9233 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
40f46283 DL |
9234 | stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0], |
9235 | fb->pixel_format); | |
bc8d7dff DL |
9236 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9237 | ||
9238 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9239 | fb->pixel_format, |
9240 | fb->modifier[0]); | |
bc8d7dff | 9241 | |
f37b5c2b | 9242 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9243 | |
9244 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9245 | pipe_name(pipe), fb->width, fb->height, | |
9246 | fb->bits_per_pixel, base, fb->pitches[0], | |
9247 | plane_config->size); | |
9248 | ||
2d14030b | 9249 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9250 | return; |
9251 | ||
9252 | error: | |
9253 | kfree(fb); | |
9254 | } | |
9255 | ||
2fa2fe9a | 9256 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9257 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9258 | { |
9259 | struct drm_device *dev = crtc->base.dev; | |
9260 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9261 | uint32_t tmp; | |
9262 | ||
9263 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9264 | ||
9265 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9266 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9267 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9268 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9269 | |
9270 | /* We currently do not free assignements of panel fitters on | |
9271 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9272 | * differentiates them) so just WARN about this case for now. */ | |
9273 | if (IS_GEN7(dev)) { | |
9274 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
9275 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9276 | } | |
2fa2fe9a | 9277 | } |
79e53945 JB |
9278 | } |
9279 | ||
5724dbd1 DL |
9280 | static void |
9281 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9282 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9283 | { |
9284 | struct drm_device *dev = crtc->base.dev; | |
9285 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9286 | u32 val, base, offset; | |
aeee5a49 | 9287 | int pipe = crtc->pipe; |
4c6baa59 | 9288 | int fourcc, pixel_format; |
6761dd31 | 9289 | unsigned int aligned_height; |
b113d5ee | 9290 | struct drm_framebuffer *fb; |
1b842c89 | 9291 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9292 | |
42a7b088 DL |
9293 | val = I915_READ(DSPCNTR(pipe)); |
9294 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9295 | return; | |
9296 | ||
d9806c9f | 9297 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9298 | if (!intel_fb) { |
4c6baa59 JB |
9299 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9300 | return; | |
9301 | } | |
9302 | ||
1b842c89 DL |
9303 | fb = &intel_fb->base; |
9304 | ||
18c5247e DV |
9305 | if (INTEL_INFO(dev)->gen >= 4) { |
9306 | if (val & DISPPLANE_TILED) { | |
49af449b | 9307 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9308 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9309 | } | |
9310 | } | |
4c6baa59 JB |
9311 | |
9312 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9313 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9314 | fb->pixel_format = fourcc; |
9315 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9316 | |
aeee5a49 | 9317 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 9318 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 9319 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9320 | } else { |
49af449b | 9321 | if (plane_config->tiling) |
aeee5a49 | 9322 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9323 | else |
aeee5a49 | 9324 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9325 | } |
9326 | plane_config->base = base; | |
9327 | ||
9328 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9329 | fb->width = ((val >> 16) & 0xfff) + 1; |
9330 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9331 | |
9332 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9333 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9334 | |
b113d5ee | 9335 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9336 | fb->pixel_format, |
9337 | fb->modifier[0]); | |
4c6baa59 | 9338 | |
f37b5c2b | 9339 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9340 | |
2844a921 DL |
9341 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9342 | pipe_name(pipe), fb->width, fb->height, | |
9343 | fb->bits_per_pixel, base, fb->pitches[0], | |
9344 | plane_config->size); | |
b113d5ee | 9345 | |
2d14030b | 9346 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9347 | } |
9348 | ||
0e8ffe1b | 9349 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9350 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9351 | { |
9352 | struct drm_device *dev = crtc->base.dev; | |
9353 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9354 | uint32_t tmp; | |
9355 | ||
f458ebbc DV |
9356 | if (!intel_display_power_is_enabled(dev_priv, |
9357 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
930e8c9e PZ |
9358 | return false; |
9359 | ||
e143a21c | 9360 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 9361 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 9362 | |
0e8ffe1b DV |
9363 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9364 | if (!(tmp & PIPECONF_ENABLE)) | |
9365 | return false; | |
9366 | ||
42571aef VS |
9367 | switch (tmp & PIPECONF_BPC_MASK) { |
9368 | case PIPECONF_6BPC: | |
9369 | pipe_config->pipe_bpp = 18; | |
9370 | break; | |
9371 | case PIPECONF_8BPC: | |
9372 | pipe_config->pipe_bpp = 24; | |
9373 | break; | |
9374 | case PIPECONF_10BPC: | |
9375 | pipe_config->pipe_bpp = 30; | |
9376 | break; | |
9377 | case PIPECONF_12BPC: | |
9378 | pipe_config->pipe_bpp = 36; | |
9379 | break; | |
9380 | default: | |
9381 | break; | |
9382 | } | |
9383 | ||
b5a9fa09 DV |
9384 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9385 | pipe_config->limited_color_range = true; | |
9386 | ||
ab9412ba | 9387 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
9388 | struct intel_shared_dpll *pll; |
9389 | ||
88adfff1 DV |
9390 | pipe_config->has_pch_encoder = true; |
9391 | ||
627eb5a3 DV |
9392 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9393 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9394 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9395 | |
9396 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9397 | |
c0d43d62 | 9398 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
9399 | pipe_config->shared_dpll = |
9400 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
9401 | } else { |
9402 | tmp = I915_READ(PCH_DPLL_SEL); | |
9403 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
9404 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
9405 | else | |
9406 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
9407 | } | |
66e985c0 DV |
9408 | |
9409 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9410 | ||
9411 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9412 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9413 | |
9414 | tmp = pipe_config->dpll_hw_state.dpll; | |
9415 | pipe_config->pixel_multiplier = | |
9416 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9417 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9418 | |
9419 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9420 | } else { |
9421 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9422 | } |
9423 | ||
1bd1bd80 DV |
9424 | intel_get_pipe_timings(crtc, pipe_config); |
9425 | ||
2fa2fe9a DV |
9426 | ironlake_get_pfit_config(crtc, pipe_config); |
9427 | ||
0e8ffe1b DV |
9428 | return true; |
9429 | } | |
9430 | ||
be256dc7 PZ |
9431 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9432 | { | |
9433 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 9434 | struct intel_crtc *crtc; |
be256dc7 | 9435 | |
d3fcc808 | 9436 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9437 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9438 | pipe_name(crtc->pipe)); |
9439 | ||
e2c719b7 RC |
9440 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9441 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
9442 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
9443 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
e2c719b7 RC |
9444 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
9445 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 9446 | "CPU PWM1 enabled\n"); |
c5107b87 | 9447 | if (IS_HASWELL(dev)) |
e2c719b7 | 9448 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 9449 | "CPU PWM2 enabled\n"); |
e2c719b7 | 9450 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 9451 | "PCH PWM1 enabled\n"); |
e2c719b7 | 9452 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 9453 | "Utility pin enabled\n"); |
e2c719b7 | 9454 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 9455 | |
9926ada1 PZ |
9456 | /* |
9457 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9458 | * interrupts remain enabled. We used to check for that, but since it's | |
9459 | * gen-specific and since we only disable LCPLL after we fully disable | |
9460 | * the interrupts, the check below should be enough. | |
9461 | */ | |
e2c719b7 | 9462 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
9463 | } |
9464 | ||
9ccd5aeb PZ |
9465 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
9466 | { | |
9467 | struct drm_device *dev = dev_priv->dev; | |
9468 | ||
9469 | if (IS_HASWELL(dev)) | |
9470 | return I915_READ(D_COMP_HSW); | |
9471 | else | |
9472 | return I915_READ(D_COMP_BDW); | |
9473 | } | |
9474 | ||
3c4c9b81 PZ |
9475 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
9476 | { | |
9477 | struct drm_device *dev = dev_priv->dev; | |
9478 | ||
9479 | if (IS_HASWELL(dev)) { | |
9480 | mutex_lock(&dev_priv->rps.hw_lock); | |
9481 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9482 | val)) | |
f475dadf | 9483 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
9484 | mutex_unlock(&dev_priv->rps.hw_lock); |
9485 | } else { | |
9ccd5aeb PZ |
9486 | I915_WRITE(D_COMP_BDW, val); |
9487 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 9488 | } |
be256dc7 PZ |
9489 | } |
9490 | ||
9491 | /* | |
9492 | * This function implements pieces of two sequences from BSpec: | |
9493 | * - Sequence for display software to disable LCPLL | |
9494 | * - Sequence for display software to allow package C8+ | |
9495 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9496 | * register. Callers should take care of disabling all the display engine | |
9497 | * functions, doing the mode unset, fixing interrupts, etc. | |
9498 | */ | |
6ff58d53 PZ |
9499 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9500 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9501 | { |
9502 | uint32_t val; | |
9503 | ||
9504 | assert_can_disable_lcpll(dev_priv); | |
9505 | ||
9506 | val = I915_READ(LCPLL_CTL); | |
9507 | ||
9508 | if (switch_to_fclk) { | |
9509 | val |= LCPLL_CD_SOURCE_FCLK; | |
9510 | I915_WRITE(LCPLL_CTL, val); | |
9511 | ||
9512 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9513 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9514 | DRM_ERROR("Switching to FCLK failed\n"); | |
9515 | ||
9516 | val = I915_READ(LCPLL_CTL); | |
9517 | } | |
9518 | ||
9519 | val |= LCPLL_PLL_DISABLE; | |
9520 | I915_WRITE(LCPLL_CTL, val); | |
9521 | POSTING_READ(LCPLL_CTL); | |
9522 | ||
9523 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
9524 | DRM_ERROR("LCPLL still locked\n"); | |
9525 | ||
9ccd5aeb | 9526 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9527 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9528 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9529 | ndelay(100); |
9530 | ||
9ccd5aeb PZ |
9531 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9532 | 1)) | |
be256dc7 PZ |
9533 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9534 | ||
9535 | if (allow_power_down) { | |
9536 | val = I915_READ(LCPLL_CTL); | |
9537 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9538 | I915_WRITE(LCPLL_CTL, val); | |
9539 | POSTING_READ(LCPLL_CTL); | |
9540 | } | |
9541 | } | |
9542 | ||
9543 | /* | |
9544 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9545 | * source. | |
9546 | */ | |
6ff58d53 | 9547 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9548 | { |
9549 | uint32_t val; | |
9550 | ||
9551 | val = I915_READ(LCPLL_CTL); | |
9552 | ||
9553 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9554 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9555 | return; | |
9556 | ||
a8a8bd54 PZ |
9557 | /* |
9558 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9559 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9560 | */ |
59bad947 | 9561 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9562 | |
be256dc7 PZ |
9563 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9564 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9565 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9566 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9567 | } |
9568 | ||
9ccd5aeb | 9569 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9570 | val |= D_COMP_COMP_FORCE; |
9571 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9572 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9573 | |
9574 | val = I915_READ(LCPLL_CTL); | |
9575 | val &= ~LCPLL_PLL_DISABLE; | |
9576 | I915_WRITE(LCPLL_CTL, val); | |
9577 | ||
9578 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
9579 | DRM_ERROR("LCPLL not locked yet\n"); | |
9580 | ||
9581 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9582 | val = I915_READ(LCPLL_CTL); | |
9583 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9584 | I915_WRITE(LCPLL_CTL, val); | |
9585 | ||
9586 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9587 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9588 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9589 | } | |
215733fa | 9590 | |
59bad947 | 9591 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b6283055 | 9592 | intel_update_cdclk(dev_priv->dev); |
be256dc7 PZ |
9593 | } |
9594 | ||
765dab67 PZ |
9595 | /* |
9596 | * Package states C8 and deeper are really deep PC states that can only be | |
9597 | * reached when all the devices on the system allow it, so even if the graphics | |
9598 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9599 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9600 | * | |
9601 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9602 | * well is disabled and most interrupts are disabled, and these are also | |
9603 | * requirements for runtime PM. When these conditions are met, we manually do | |
9604 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9605 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9606 | * hang the machine. | |
9607 | * | |
9608 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9609 | * the state of some registers, so when we come back from PC8+ we need to | |
9610 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9611 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9612 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9613 | * because of the runtime PM support). | |
9614 | * | |
9615 | * For more, read "Display Sequences for Package C8" on the hardware | |
9616 | * documentation. | |
9617 | */ | |
a14cb6fc | 9618 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9619 | { |
c67a470b PZ |
9620 | struct drm_device *dev = dev_priv->dev; |
9621 | uint32_t val; | |
9622 | ||
c67a470b PZ |
9623 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9624 | ||
c2699524 | 9625 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9626 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9627 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9628 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9629 | } | |
9630 | ||
9631 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9632 | hsw_disable_lcpll(dev_priv, true, true); |
9633 | } | |
9634 | ||
a14cb6fc | 9635 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
9636 | { |
9637 | struct drm_device *dev = dev_priv->dev; | |
9638 | uint32_t val; | |
9639 | ||
c67a470b PZ |
9640 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9641 | ||
9642 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9643 | lpt_init_pch_refclk(dev); |
9644 | ||
c2699524 | 9645 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9646 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9647 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9648 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9649 | } | |
9650 | ||
9651 | intel_prepare_ddi(dev); | |
c67a470b PZ |
9652 | } |
9653 | ||
27c329ed | 9654 | static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 9655 | { |
a821fc46 | 9656 | struct drm_device *dev = old_state->dev; |
27c329ed | 9657 | unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk; |
f8437dd1 | 9658 | |
27c329ed | 9659 | broxton_set_cdclk(dev, req_cdclk); |
f8437dd1 VK |
9660 | } |
9661 | ||
b432e5cf | 9662 | /* compute the max rate for new configuration */ |
27c329ed | 9663 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 9664 | { |
b432e5cf | 9665 | struct intel_crtc *intel_crtc; |
27c329ed | 9666 | struct intel_crtc_state *crtc_state; |
b432e5cf | 9667 | int max_pixel_rate = 0; |
b432e5cf | 9668 | |
27c329ed ML |
9669 | for_each_intel_crtc(state->dev, intel_crtc) { |
9670 | int pixel_rate; | |
9671 | ||
9672 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); | |
9673 | if (IS_ERR(crtc_state)) | |
9674 | return PTR_ERR(crtc_state); | |
9675 | ||
9676 | if (!crtc_state->base.enable) | |
b432e5cf VS |
9677 | continue; |
9678 | ||
27c329ed | 9679 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf VS |
9680 | |
9681 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
27c329ed | 9682 | if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled) |
b432e5cf VS |
9683 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
9684 | ||
9685 | max_pixel_rate = max(max_pixel_rate, pixel_rate); | |
9686 | } | |
9687 | ||
9688 | return max_pixel_rate; | |
9689 | } | |
9690 | ||
9691 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
9692 | { | |
9693 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9694 | uint32_t val, data; | |
9695 | int ret; | |
9696 | ||
9697 | if (WARN((I915_READ(LCPLL_CTL) & | |
9698 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
9699 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
9700 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
9701 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
9702 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
9703 | return; | |
9704 | ||
9705 | mutex_lock(&dev_priv->rps.hw_lock); | |
9706 | ret = sandybridge_pcode_write(dev_priv, | |
9707 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
9708 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9709 | if (ret) { | |
9710 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
9711 | return; | |
9712 | } | |
9713 | ||
9714 | val = I915_READ(LCPLL_CTL); | |
9715 | val |= LCPLL_CD_SOURCE_FCLK; | |
9716 | I915_WRITE(LCPLL_CTL, val); | |
9717 | ||
9718 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9719 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9720 | DRM_ERROR("Switching to FCLK failed\n"); | |
9721 | ||
9722 | val = I915_READ(LCPLL_CTL); | |
9723 | val &= ~LCPLL_CLK_FREQ_MASK; | |
9724 | ||
9725 | switch (cdclk) { | |
9726 | case 450000: | |
9727 | val |= LCPLL_CLK_FREQ_450; | |
9728 | data = 0; | |
9729 | break; | |
9730 | case 540000: | |
9731 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
9732 | data = 1; | |
9733 | break; | |
9734 | case 337500: | |
9735 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
9736 | data = 2; | |
9737 | break; | |
9738 | case 675000: | |
9739 | val |= LCPLL_CLK_FREQ_675_BDW; | |
9740 | data = 3; | |
9741 | break; | |
9742 | default: | |
9743 | WARN(1, "invalid cdclk frequency\n"); | |
9744 | return; | |
9745 | } | |
9746 | ||
9747 | I915_WRITE(LCPLL_CTL, val); | |
9748 | ||
9749 | val = I915_READ(LCPLL_CTL); | |
9750 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9751 | I915_WRITE(LCPLL_CTL, val); | |
9752 | ||
9753 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9754 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9755 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9756 | ||
9757 | mutex_lock(&dev_priv->rps.hw_lock); | |
9758 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
9759 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9760 | ||
9761 | intel_update_cdclk(dev); | |
9762 | ||
9763 | WARN(cdclk != dev_priv->cdclk_freq, | |
9764 | "cdclk requested %d kHz but got %d kHz\n", | |
9765 | cdclk, dev_priv->cdclk_freq); | |
9766 | } | |
9767 | ||
27c329ed | 9768 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 9769 | { |
27c329ed ML |
9770 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
9771 | int max_pixclk = ilk_max_pixel_rate(state); | |
b432e5cf VS |
9772 | int cdclk; |
9773 | ||
9774 | /* | |
9775 | * FIXME should also account for plane ratio | |
9776 | * once 64bpp pixel formats are supported. | |
9777 | */ | |
27c329ed | 9778 | if (max_pixclk > 540000) |
b432e5cf | 9779 | cdclk = 675000; |
27c329ed | 9780 | else if (max_pixclk > 450000) |
b432e5cf | 9781 | cdclk = 540000; |
27c329ed | 9782 | else if (max_pixclk > 337500) |
b432e5cf VS |
9783 | cdclk = 450000; |
9784 | else | |
9785 | cdclk = 337500; | |
9786 | ||
b432e5cf | 9787 | if (cdclk > dev_priv->max_cdclk_freq) { |
63ba534e ML |
9788 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
9789 | cdclk, dev_priv->max_cdclk_freq); | |
9790 | return -EINVAL; | |
b432e5cf VS |
9791 | } |
9792 | ||
27c329ed | 9793 | to_intel_atomic_state(state)->cdclk = cdclk; |
b432e5cf VS |
9794 | |
9795 | return 0; | |
9796 | } | |
9797 | ||
27c329ed | 9798 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 9799 | { |
27c329ed ML |
9800 | struct drm_device *dev = old_state->dev; |
9801 | unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk; | |
b432e5cf | 9802 | |
27c329ed | 9803 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
9804 | } |
9805 | ||
190f68c5 ACO |
9806 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9807 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9808 | { |
190f68c5 | 9809 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
6441ab5f | 9810 | return -EINVAL; |
716c2e55 | 9811 | |
c7653199 | 9812 | crtc->lowfreq_avail = false; |
644cef34 | 9813 | |
c8f7a0db | 9814 | return 0; |
79e53945 JB |
9815 | } |
9816 | ||
3760b59c S |
9817 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9818 | enum port port, | |
9819 | struct intel_crtc_state *pipe_config) | |
9820 | { | |
9821 | switch (port) { | |
9822 | case PORT_A: | |
9823 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
9824 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9825 | break; | |
9826 | case PORT_B: | |
9827 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
9828 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9829 | break; | |
9830 | case PORT_C: | |
9831 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
9832 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9833 | break; | |
9834 | default: | |
9835 | DRM_ERROR("Incorrect port type\n"); | |
9836 | } | |
9837 | } | |
9838 | ||
96b7dfb7 S |
9839 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9840 | enum port port, | |
5cec258b | 9841 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9842 | { |
3148ade7 | 9843 | u32 temp, dpll_ctl1; |
96b7dfb7 S |
9844 | |
9845 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9846 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9847 | ||
9848 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 DL |
9849 | case SKL_DPLL0: |
9850 | /* | |
9851 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part | |
9852 | * of the shared DPLL framework and thus needs to be read out | |
9853 | * separately | |
9854 | */ | |
9855 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
9856 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; | |
9857 | break; | |
96b7dfb7 S |
9858 | case SKL_DPLL1: |
9859 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9860 | break; | |
9861 | case SKL_DPLL2: | |
9862 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9863 | break; | |
9864 | case SKL_DPLL3: | |
9865 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9866 | break; | |
96b7dfb7 S |
9867 | } |
9868 | } | |
9869 | ||
7d2c8175 DL |
9870 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9871 | enum port port, | |
5cec258b | 9872 | struct intel_crtc_state *pipe_config) |
7d2c8175 DL |
9873 | { |
9874 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
9875 | ||
9876 | switch (pipe_config->ddi_pll_sel) { | |
9877 | case PORT_CLK_SEL_WRPLL1: | |
9878 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
9879 | break; | |
9880 | case PORT_CLK_SEL_WRPLL2: | |
9881 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
9882 | break; | |
00490c22 ML |
9883 | case PORT_CLK_SEL_SPLL: |
9884 | pipe_config->shared_dpll = DPLL_ID_SPLL; | |
79bd23da | 9885 | break; |
7d2c8175 DL |
9886 | } |
9887 | } | |
9888 | ||
26804afd | 9889 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9890 | struct intel_crtc_state *pipe_config) |
26804afd DV |
9891 | { |
9892 | struct drm_device *dev = crtc->base.dev; | |
9893 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 9894 | struct intel_shared_dpll *pll; |
26804afd DV |
9895 | enum port port; |
9896 | uint32_t tmp; | |
9897 | ||
9898 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9899 | ||
9900 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9901 | ||
ef11bdb3 | 9902 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
96b7dfb7 | 9903 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
3760b59c S |
9904 | else if (IS_BROXTON(dev)) |
9905 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
9906 | else |
9907 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9908 | |
d452c5b6 DV |
9909 | if (pipe_config->shared_dpll >= 0) { |
9910 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9911 | ||
9912 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9913 | &pipe_config->dpll_hw_state)); | |
9914 | } | |
9915 | ||
26804afd DV |
9916 | /* |
9917 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9918 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9919 | * the PCH transcoder is on. | |
9920 | */ | |
ca370455 DL |
9921 | if (INTEL_INFO(dev)->gen < 9 && |
9922 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
9923 | pipe_config->has_pch_encoder = true; |
9924 | ||
9925 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9926 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9927 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9928 | ||
9929 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9930 | } | |
9931 | } | |
9932 | ||
0e8ffe1b | 9933 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9934 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9935 | { |
9936 | struct drm_device *dev = crtc->base.dev; | |
9937 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 9938 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
9939 | uint32_t tmp; |
9940 | ||
f458ebbc | 9941 | if (!intel_display_power_is_enabled(dev_priv, |
b5482bd0 ID |
9942 | POWER_DOMAIN_PIPE(crtc->pipe))) |
9943 | return false; | |
9944 | ||
e143a21c | 9945 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
9946 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
9947 | ||
eccb140b DV |
9948 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
9949 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9950 | enum pipe trans_edp_pipe; | |
9951 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9952 | default: | |
9953 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9954 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9955 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9956 | trans_edp_pipe = PIPE_A; | |
9957 | break; | |
9958 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9959 | trans_edp_pipe = PIPE_B; | |
9960 | break; | |
9961 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9962 | trans_edp_pipe = PIPE_C; | |
9963 | break; | |
9964 | } | |
9965 | ||
9966 | if (trans_edp_pipe == crtc->pipe) | |
9967 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
9968 | } | |
9969 | ||
f458ebbc | 9970 | if (!intel_display_power_is_enabled(dev_priv, |
eccb140b | 9971 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
9972 | return false; |
9973 | ||
eccb140b | 9974 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
9975 | if (!(tmp & PIPECONF_ENABLE)) |
9976 | return false; | |
9977 | ||
26804afd | 9978 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 9979 | |
1bd1bd80 DV |
9980 | intel_get_pipe_timings(crtc, pipe_config); |
9981 | ||
a1b2278e CK |
9982 | if (INTEL_INFO(dev)->gen >= 9) { |
9983 | skl_init_scalers(dev, crtc, pipe_config); | |
9984 | } | |
9985 | ||
2fa2fe9a | 9986 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
af99ceda CK |
9987 | |
9988 | if (INTEL_INFO(dev)->gen >= 9) { | |
9989 | pipe_config->scaler_state.scaler_id = -1; | |
9990 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
9991 | } | |
9992 | ||
bd2e244f | 9993 | if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { |
1c132b44 | 9994 | if (INTEL_INFO(dev)->gen >= 9) |
bd2e244f | 9995 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 9996 | else |
1c132b44 | 9997 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 9998 | } |
88adfff1 | 9999 | |
e59150dc JB |
10000 | if (IS_HASWELL(dev)) |
10001 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
10002 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 10003 | |
ebb69c95 CT |
10004 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
10005 | pipe_config->pixel_multiplier = | |
10006 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
10007 | } else { | |
10008 | pipe_config->pixel_multiplier = 1; | |
10009 | } | |
6c49f241 | 10010 | |
0e8ffe1b DV |
10011 | return true; |
10012 | } | |
10013 | ||
560b85bb CW |
10014 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
10015 | { | |
10016 | struct drm_device *dev = crtc->dev; | |
10017 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10018 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 10019 | uint32_t cntl = 0, size = 0; |
560b85bb | 10020 | |
dc41c154 | 10021 | if (base) { |
3dd512fb MR |
10022 | unsigned int width = intel_crtc->base.cursor->state->crtc_w; |
10023 | unsigned int height = intel_crtc->base.cursor->state->crtc_h; | |
dc41c154 VS |
10024 | unsigned int stride = roundup_pow_of_two(width) * 4; |
10025 | ||
10026 | switch (stride) { | |
10027 | default: | |
10028 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
10029 | width, stride); | |
10030 | stride = 256; | |
10031 | /* fallthrough */ | |
10032 | case 256: | |
10033 | case 512: | |
10034 | case 1024: | |
10035 | case 2048: | |
10036 | break; | |
4b0e333e CW |
10037 | } |
10038 | ||
dc41c154 VS |
10039 | cntl |= CURSOR_ENABLE | |
10040 | CURSOR_GAMMA_ENABLE | | |
10041 | CURSOR_FORMAT_ARGB | | |
10042 | CURSOR_STRIDE(stride); | |
10043 | ||
10044 | size = (height << 12) | width; | |
4b0e333e | 10045 | } |
560b85bb | 10046 | |
dc41c154 VS |
10047 | if (intel_crtc->cursor_cntl != 0 && |
10048 | (intel_crtc->cursor_base != base || | |
10049 | intel_crtc->cursor_size != size || | |
10050 | intel_crtc->cursor_cntl != cntl)) { | |
10051 | /* On these chipsets we can only modify the base/size/stride | |
10052 | * whilst the cursor is disabled. | |
10053 | */ | |
0b87c24e VS |
10054 | I915_WRITE(CURCNTR(PIPE_A), 0); |
10055 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 10056 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 10057 | } |
560b85bb | 10058 | |
99d1f387 | 10059 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 10060 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
10061 | intel_crtc->cursor_base = base; |
10062 | } | |
4726e0b0 | 10063 | |
dc41c154 VS |
10064 | if (intel_crtc->cursor_size != size) { |
10065 | I915_WRITE(CURSIZE, size); | |
10066 | intel_crtc->cursor_size = size; | |
4b0e333e | 10067 | } |
560b85bb | 10068 | |
4b0e333e | 10069 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
10070 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
10071 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 10072 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 10073 | } |
560b85bb CW |
10074 | } |
10075 | ||
560b85bb | 10076 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
65a21cd6 JB |
10077 | { |
10078 | struct drm_device *dev = crtc->dev; | |
10079 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10080 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10081 | int pipe = intel_crtc->pipe; | |
4b0e333e CW |
10082 | uint32_t cntl; |
10083 | ||
10084 | cntl = 0; | |
10085 | if (base) { | |
10086 | cntl = MCURSOR_GAMMA_ENABLE; | |
3dd512fb | 10087 | switch (intel_crtc->base.cursor->state->crtc_w) { |
4726e0b0 SK |
10088 | case 64: |
10089 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
10090 | break; | |
10091 | case 128: | |
10092 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
10093 | break; | |
10094 | case 256: | |
10095 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
10096 | break; | |
10097 | default: | |
3dd512fb | 10098 | MISSING_CASE(intel_crtc->base.cursor->state->crtc_w); |
4726e0b0 | 10099 | return; |
65a21cd6 | 10100 | } |
4b0e333e | 10101 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 10102 | |
fc6f93bc | 10103 | if (HAS_DDI(dev)) |
47bf17a7 | 10104 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
4b0e333e | 10105 | } |
65a21cd6 | 10106 | |
8e7d688b | 10107 | if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) |
4398ad45 VS |
10108 | cntl |= CURSOR_ROTATE_180; |
10109 | ||
4b0e333e CW |
10110 | if (intel_crtc->cursor_cntl != cntl) { |
10111 | I915_WRITE(CURCNTR(pipe), cntl); | |
10112 | POSTING_READ(CURCNTR(pipe)); | |
10113 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 10114 | } |
4b0e333e | 10115 | |
65a21cd6 | 10116 | /* and commit changes on next vblank */ |
5efb3e28 VS |
10117 | I915_WRITE(CURBASE(pipe), base); |
10118 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
10119 | |
10120 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
10121 | } |
10122 | ||
cda4b7d3 | 10123 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
10124 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
10125 | bool on) | |
cda4b7d3 CW |
10126 | { |
10127 | struct drm_device *dev = crtc->dev; | |
10128 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10129 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10130 | int pipe = intel_crtc->pipe; | |
9b4101be ML |
10131 | struct drm_plane_state *cursor_state = crtc->cursor->state; |
10132 | int x = cursor_state->crtc_x; | |
10133 | int y = cursor_state->crtc_y; | |
d6e4db15 | 10134 | u32 base = 0, pos = 0; |
cda4b7d3 | 10135 | |
d6e4db15 | 10136 | if (on) |
cda4b7d3 | 10137 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 10138 | |
6e3c9717 | 10139 | if (x >= intel_crtc->config->pipe_src_w) |
d6e4db15 VS |
10140 | base = 0; |
10141 | ||
6e3c9717 | 10142 | if (y >= intel_crtc->config->pipe_src_h) |
cda4b7d3 CW |
10143 | base = 0; |
10144 | ||
10145 | if (x < 0) { | |
9b4101be | 10146 | if (x + cursor_state->crtc_w <= 0) |
cda4b7d3 CW |
10147 | base = 0; |
10148 | ||
10149 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10150 | x = -x; | |
10151 | } | |
10152 | pos |= x << CURSOR_X_SHIFT; | |
10153 | ||
10154 | if (y < 0) { | |
9b4101be | 10155 | if (y + cursor_state->crtc_h <= 0) |
cda4b7d3 CW |
10156 | base = 0; |
10157 | ||
10158 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10159 | y = -y; | |
10160 | } | |
10161 | pos |= y << CURSOR_Y_SHIFT; | |
10162 | ||
4b0e333e | 10163 | if (base == 0 && intel_crtc->cursor_base == 0) |
cda4b7d3 CW |
10164 | return; |
10165 | ||
5efb3e28 VS |
10166 | I915_WRITE(CURPOS(pipe), pos); |
10167 | ||
4398ad45 VS |
10168 | /* ILK+ do this automagically */ |
10169 | if (HAS_GMCH_DISPLAY(dev) && | |
8e7d688b | 10170 | crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) { |
9b4101be ML |
10171 | base += (cursor_state->crtc_h * |
10172 | cursor_state->crtc_w - 1) * 4; | |
4398ad45 VS |
10173 | } |
10174 | ||
8ac54669 | 10175 | if (IS_845G(dev) || IS_I865G(dev)) |
5efb3e28 VS |
10176 | i845_update_cursor(crtc, base); |
10177 | else | |
10178 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
10179 | } |
10180 | ||
dc41c154 VS |
10181 | static bool cursor_size_ok(struct drm_device *dev, |
10182 | uint32_t width, uint32_t height) | |
10183 | { | |
10184 | if (width == 0 || height == 0) | |
10185 | return false; | |
10186 | ||
10187 | /* | |
10188 | * 845g/865g are special in that they are only limited by | |
10189 | * the width of their cursors, the height is arbitrary up to | |
10190 | * the precision of the register. Everything else requires | |
10191 | * square cursors, limited to a few power-of-two sizes. | |
10192 | */ | |
10193 | if (IS_845G(dev) || IS_I865G(dev)) { | |
10194 | if ((width & 63) != 0) | |
10195 | return false; | |
10196 | ||
10197 | if (width > (IS_845G(dev) ? 64 : 512)) | |
10198 | return false; | |
10199 | ||
10200 | if (height > 1023) | |
10201 | return false; | |
10202 | } else { | |
10203 | switch (width | height) { | |
10204 | case 256: | |
10205 | case 128: | |
10206 | if (IS_GEN2(dev)) | |
10207 | return false; | |
10208 | case 64: | |
10209 | break; | |
10210 | default: | |
10211 | return false; | |
10212 | } | |
10213 | } | |
10214 | ||
10215 | return true; | |
10216 | } | |
10217 | ||
79e53945 | 10218 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 10219 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 10220 | { |
7203425a | 10221 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 10222 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 10223 | |
7203425a | 10224 | for (i = start; i < end; i++) { |
79e53945 JB |
10225 | intel_crtc->lut_r[i] = red[i] >> 8; |
10226 | intel_crtc->lut_g[i] = green[i] >> 8; | |
10227 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
10228 | } | |
10229 | ||
10230 | intel_crtc_load_lut(crtc); | |
10231 | } | |
10232 | ||
79e53945 JB |
10233 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10234 | static struct drm_display_mode load_detect_mode = { | |
10235 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10236 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10237 | }; | |
10238 | ||
a8bb6818 DV |
10239 | struct drm_framebuffer * |
10240 | __intel_framebuffer_create(struct drm_device *dev, | |
10241 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10242 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10243 | { |
10244 | struct intel_framebuffer *intel_fb; | |
10245 | int ret; | |
10246 | ||
10247 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 10248 | if (!intel_fb) |
d2dff872 | 10249 | return ERR_PTR(-ENOMEM); |
d2dff872 CW |
10250 | |
10251 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10252 | if (ret) |
10253 | goto err; | |
d2dff872 CW |
10254 | |
10255 | return &intel_fb->base; | |
dcb1394e | 10256 | |
dd4916c5 | 10257 | err: |
dd4916c5 | 10258 | kfree(intel_fb); |
dd4916c5 | 10259 | return ERR_PTR(ret); |
d2dff872 CW |
10260 | } |
10261 | ||
b5ea642a | 10262 | static struct drm_framebuffer * |
a8bb6818 DV |
10263 | intel_framebuffer_create(struct drm_device *dev, |
10264 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10265 | struct drm_i915_gem_object *obj) | |
10266 | { | |
10267 | struct drm_framebuffer *fb; | |
10268 | int ret; | |
10269 | ||
10270 | ret = i915_mutex_lock_interruptible(dev); | |
10271 | if (ret) | |
10272 | return ERR_PTR(ret); | |
10273 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10274 | mutex_unlock(&dev->struct_mutex); | |
10275 | ||
10276 | return fb; | |
10277 | } | |
10278 | ||
d2dff872 CW |
10279 | static u32 |
10280 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10281 | { | |
10282 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10283 | return ALIGN(pitch, 64); | |
10284 | } | |
10285 | ||
10286 | static u32 | |
10287 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10288 | { | |
10289 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 10290 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
10291 | } |
10292 | ||
10293 | static struct drm_framebuffer * | |
10294 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10295 | struct drm_display_mode *mode, | |
10296 | int depth, int bpp) | |
10297 | { | |
dcb1394e | 10298 | struct drm_framebuffer *fb; |
d2dff872 | 10299 | struct drm_i915_gem_object *obj; |
0fed39bd | 10300 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
10301 | |
10302 | obj = i915_gem_alloc_object(dev, | |
10303 | intel_framebuffer_size_for_mode(mode, bpp)); | |
10304 | if (obj == NULL) | |
10305 | return ERR_PTR(-ENOMEM); | |
10306 | ||
10307 | mode_cmd.width = mode->hdisplay; | |
10308 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
10309 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10310 | bpp); | |
5ca0c34a | 10311 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 10312 | |
dcb1394e LW |
10313 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
10314 | if (IS_ERR(fb)) | |
10315 | drm_gem_object_unreference_unlocked(&obj->base); | |
10316 | ||
10317 | return fb; | |
d2dff872 CW |
10318 | } |
10319 | ||
10320 | static struct drm_framebuffer * | |
10321 | mode_fits_in_fbdev(struct drm_device *dev, | |
10322 | struct drm_display_mode *mode) | |
10323 | { | |
0695726e | 10324 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
d2dff872 CW |
10325 | struct drm_i915_private *dev_priv = dev->dev_private; |
10326 | struct drm_i915_gem_object *obj; | |
10327 | struct drm_framebuffer *fb; | |
10328 | ||
4c0e5528 | 10329 | if (!dev_priv->fbdev) |
d2dff872 CW |
10330 | return NULL; |
10331 | ||
4c0e5528 | 10332 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
10333 | return NULL; |
10334 | ||
4c0e5528 DV |
10335 | obj = dev_priv->fbdev->fb->obj; |
10336 | BUG_ON(!obj); | |
10337 | ||
8bcd4553 | 10338 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
10339 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
10340 | fb->bits_per_pixel)) | |
d2dff872 CW |
10341 | return NULL; |
10342 | ||
01f2c773 | 10343 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
10344 | return NULL; |
10345 | ||
10346 | return fb; | |
4520f53a DV |
10347 | #else |
10348 | return NULL; | |
10349 | #endif | |
d2dff872 CW |
10350 | } |
10351 | ||
d3a40d1b ACO |
10352 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
10353 | struct drm_crtc *crtc, | |
10354 | struct drm_display_mode *mode, | |
10355 | struct drm_framebuffer *fb, | |
10356 | int x, int y) | |
10357 | { | |
10358 | struct drm_plane_state *plane_state; | |
10359 | int hdisplay, vdisplay; | |
10360 | int ret; | |
10361 | ||
10362 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
10363 | if (IS_ERR(plane_state)) | |
10364 | return PTR_ERR(plane_state); | |
10365 | ||
10366 | if (mode) | |
10367 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
10368 | else | |
10369 | hdisplay = vdisplay = 0; | |
10370 | ||
10371 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
10372 | if (ret) | |
10373 | return ret; | |
10374 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10375 | plane_state->crtc_x = 0; | |
10376 | plane_state->crtc_y = 0; | |
10377 | plane_state->crtc_w = hdisplay; | |
10378 | plane_state->crtc_h = vdisplay; | |
10379 | plane_state->src_x = x << 16; | |
10380 | plane_state->src_y = y << 16; | |
10381 | plane_state->src_w = hdisplay << 16; | |
10382 | plane_state->src_h = vdisplay << 16; | |
10383 | ||
10384 | return 0; | |
10385 | } | |
10386 | ||
d2434ab7 | 10387 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 10388 | struct drm_display_mode *mode, |
51fd371b RC |
10389 | struct intel_load_detect_pipe *old, |
10390 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
10391 | { |
10392 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
10393 | struct intel_encoder *intel_encoder = |
10394 | intel_attached_encoder(connector); | |
79e53945 | 10395 | struct drm_crtc *possible_crtc; |
4ef69c7a | 10396 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
10397 | struct drm_crtc *crtc = NULL; |
10398 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 10399 | struct drm_framebuffer *fb; |
51fd371b | 10400 | struct drm_mode_config *config = &dev->mode_config; |
83a57153 | 10401 | struct drm_atomic_state *state = NULL; |
944b0c76 | 10402 | struct drm_connector_state *connector_state; |
4be07317 | 10403 | struct intel_crtc_state *crtc_state; |
51fd371b | 10404 | int ret, i = -1; |
79e53945 | 10405 | |
d2dff872 | 10406 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10407 | connector->base.id, connector->name, |
8e329a03 | 10408 | encoder->base.id, encoder->name); |
d2dff872 | 10409 | |
51fd371b RC |
10410 | retry: |
10411 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
10412 | if (ret) | |
ad3c558f | 10413 | goto fail; |
6e9f798d | 10414 | |
79e53945 JB |
10415 | /* |
10416 | * Algorithm gets a little messy: | |
7a5e4805 | 10417 | * |
79e53945 JB |
10418 | * - if the connector already has an assigned crtc, use it (but make |
10419 | * sure it's on first) | |
7a5e4805 | 10420 | * |
79e53945 JB |
10421 | * - try to find the first unused crtc that can drive this connector, |
10422 | * and use that if we find one | |
79e53945 JB |
10423 | */ |
10424 | ||
10425 | /* See if we already have a CRTC for this connector */ | |
10426 | if (encoder->crtc) { | |
10427 | crtc = encoder->crtc; | |
8261b191 | 10428 | |
51fd371b | 10429 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 10430 | if (ret) |
ad3c558f | 10431 | goto fail; |
4d02e2de | 10432 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
51fd371b | 10433 | if (ret) |
ad3c558f | 10434 | goto fail; |
7b24056b | 10435 | |
24218aac | 10436 | old->dpms_mode = connector->dpms; |
8261b191 CW |
10437 | old->load_detect_temp = false; |
10438 | ||
10439 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
10440 | if (connector->dpms != DRM_MODE_DPMS_ON) |
10441 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 10442 | |
7173188d | 10443 | return true; |
79e53945 JB |
10444 | } |
10445 | ||
10446 | /* Find an unused one (if possible) */ | |
70e1e0ec | 10447 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
10448 | i++; |
10449 | if (!(encoder->possible_crtcs & (1 << i))) | |
10450 | continue; | |
83d65738 | 10451 | if (possible_crtc->state->enable) |
a459249c | 10452 | continue; |
a459249c VS |
10453 | |
10454 | crtc = possible_crtc; | |
10455 | break; | |
79e53945 JB |
10456 | } |
10457 | ||
10458 | /* | |
10459 | * If we didn't find an unused CRTC, don't use any. | |
10460 | */ | |
10461 | if (!crtc) { | |
7173188d | 10462 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 10463 | goto fail; |
79e53945 JB |
10464 | } |
10465 | ||
51fd371b RC |
10466 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
10467 | if (ret) | |
ad3c558f | 10468 | goto fail; |
4d02e2de DV |
10469 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
10470 | if (ret) | |
ad3c558f | 10471 | goto fail; |
79e53945 JB |
10472 | |
10473 | intel_crtc = to_intel_crtc(crtc); | |
24218aac | 10474 | old->dpms_mode = connector->dpms; |
8261b191 | 10475 | old->load_detect_temp = true; |
d2dff872 | 10476 | old->release_fb = NULL; |
79e53945 | 10477 | |
83a57153 ACO |
10478 | state = drm_atomic_state_alloc(dev); |
10479 | if (!state) | |
10480 | return false; | |
10481 | ||
10482 | state->acquire_ctx = ctx; | |
10483 | ||
944b0c76 ACO |
10484 | connector_state = drm_atomic_get_connector_state(state, connector); |
10485 | if (IS_ERR(connector_state)) { | |
10486 | ret = PTR_ERR(connector_state); | |
10487 | goto fail; | |
10488 | } | |
10489 | ||
10490 | connector_state->crtc = crtc; | |
10491 | connector_state->best_encoder = &intel_encoder->base; | |
10492 | ||
4be07317 ACO |
10493 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10494 | if (IS_ERR(crtc_state)) { | |
10495 | ret = PTR_ERR(crtc_state); | |
10496 | goto fail; | |
10497 | } | |
10498 | ||
49d6fa21 | 10499 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 10500 | |
6492711d CW |
10501 | if (!mode) |
10502 | mode = &load_detect_mode; | |
79e53945 | 10503 | |
d2dff872 CW |
10504 | /* We need a framebuffer large enough to accommodate all accesses |
10505 | * that the plane may generate whilst we perform load detection. | |
10506 | * We can not rely on the fbcon either being present (we get called | |
10507 | * during its initialisation to detect all boot displays, or it may | |
10508 | * not even exist) or that it is large enough to satisfy the | |
10509 | * requested mode. | |
10510 | */ | |
94352cf9 DV |
10511 | fb = mode_fits_in_fbdev(dev, mode); |
10512 | if (fb == NULL) { | |
d2dff872 | 10513 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
10514 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
10515 | old->release_fb = fb; | |
d2dff872 CW |
10516 | } else |
10517 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10518 | if (IS_ERR(fb)) { |
d2dff872 | 10519 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 10520 | goto fail; |
79e53945 | 10521 | } |
79e53945 | 10522 | |
d3a40d1b ACO |
10523 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10524 | if (ret) | |
10525 | goto fail; | |
10526 | ||
8c7b5ccb ACO |
10527 | drm_mode_copy(&crtc_state->base.mode, mode); |
10528 | ||
74c090b1 | 10529 | if (drm_atomic_commit(state)) { |
6492711d | 10530 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
10531 | if (old->release_fb) |
10532 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 10533 | goto fail; |
79e53945 | 10534 | } |
9128b040 | 10535 | crtc->primary->crtc = crtc; |
7173188d | 10536 | |
79e53945 | 10537 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 10538 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 10539 | return true; |
412b61d8 | 10540 | |
ad3c558f | 10541 | fail: |
e5d958ef ACO |
10542 | drm_atomic_state_free(state); |
10543 | state = NULL; | |
83a57153 | 10544 | |
51fd371b RC |
10545 | if (ret == -EDEADLK) { |
10546 | drm_modeset_backoff(ctx); | |
10547 | goto retry; | |
10548 | } | |
10549 | ||
412b61d8 | 10550 | return false; |
79e53945 JB |
10551 | } |
10552 | ||
d2434ab7 | 10553 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10554 | struct intel_load_detect_pipe *old, |
10555 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10556 | { |
83a57153 | 10557 | struct drm_device *dev = connector->dev; |
d2434ab7 DV |
10558 | struct intel_encoder *intel_encoder = |
10559 | intel_attached_encoder(connector); | |
4ef69c7a | 10560 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 10561 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 10562 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83a57153 | 10563 | struct drm_atomic_state *state; |
944b0c76 | 10564 | struct drm_connector_state *connector_state; |
4be07317 | 10565 | struct intel_crtc_state *crtc_state; |
d3a40d1b | 10566 | int ret; |
79e53945 | 10567 | |
d2dff872 | 10568 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10569 | connector->base.id, connector->name, |
8e329a03 | 10570 | encoder->base.id, encoder->name); |
d2dff872 | 10571 | |
8261b191 | 10572 | if (old->load_detect_temp) { |
83a57153 | 10573 | state = drm_atomic_state_alloc(dev); |
944b0c76 ACO |
10574 | if (!state) |
10575 | goto fail; | |
83a57153 ACO |
10576 | |
10577 | state->acquire_ctx = ctx; | |
10578 | ||
944b0c76 ACO |
10579 | connector_state = drm_atomic_get_connector_state(state, connector); |
10580 | if (IS_ERR(connector_state)) | |
10581 | goto fail; | |
10582 | ||
4be07317 ACO |
10583 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10584 | if (IS_ERR(crtc_state)) | |
10585 | goto fail; | |
10586 | ||
944b0c76 ACO |
10587 | connector_state->best_encoder = NULL; |
10588 | connector_state->crtc = NULL; | |
10589 | ||
49d6fa21 | 10590 | crtc_state->base.enable = crtc_state->base.active = false; |
4be07317 | 10591 | |
d3a40d1b ACO |
10592 | ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL, |
10593 | 0, 0); | |
10594 | if (ret) | |
10595 | goto fail; | |
10596 | ||
74c090b1 | 10597 | ret = drm_atomic_commit(state); |
2bfb4627 ACO |
10598 | if (ret) |
10599 | goto fail; | |
d2dff872 | 10600 | |
36206361 DV |
10601 | if (old->release_fb) { |
10602 | drm_framebuffer_unregister_private(old->release_fb); | |
10603 | drm_framebuffer_unreference(old->release_fb); | |
10604 | } | |
d2dff872 | 10605 | |
0622a53c | 10606 | return; |
79e53945 JB |
10607 | } |
10608 | ||
c751ce4f | 10609 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
10610 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
10611 | connector->funcs->dpms(connector, old->dpms_mode); | |
944b0c76 ACO |
10612 | |
10613 | return; | |
10614 | fail: | |
10615 | DRM_DEBUG_KMS("Couldn't release load detect pipe.\n"); | |
10616 | drm_atomic_state_free(state); | |
79e53945 JB |
10617 | } |
10618 | ||
da4a1efa | 10619 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10620 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
10621 | { |
10622 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10623 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
10624 | ||
10625 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10626 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
10627 | else if (HAS_PCH_SPLIT(dev)) |
10628 | return 120000; | |
10629 | else if (!IS_GEN2(dev)) | |
10630 | return 96000; | |
10631 | else | |
10632 | return 48000; | |
10633 | } | |
10634 | ||
79e53945 | 10635 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10636 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10637 | struct intel_crtc_state *pipe_config) |
79e53945 | 10638 | { |
f1f644dc | 10639 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 10640 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 10641 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10642 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
10643 | u32 fp; |
10644 | intel_clock_t clock; | |
dccbea3b | 10645 | int port_clock; |
da4a1efa | 10646 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10647 | |
10648 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10649 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10650 | else |
293623f7 | 10651 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10652 | |
10653 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10654 | if (IS_PINEVIEW(dev)) { |
10655 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10656 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10657 | } else { |
10658 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10659 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10660 | } | |
10661 | ||
a6c45cf0 | 10662 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10663 | if (IS_PINEVIEW(dev)) |
10664 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10665 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10666 | else |
10667 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10668 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10669 | ||
10670 | switch (dpll & DPLL_MODE_MASK) { | |
10671 | case DPLLB_MODE_DAC_SERIAL: | |
10672 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10673 | 5 : 10; | |
10674 | break; | |
10675 | case DPLLB_MODE_LVDS: | |
10676 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10677 | 7 : 14; | |
10678 | break; | |
10679 | default: | |
28c97730 | 10680 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10681 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10682 | return; |
79e53945 JB |
10683 | } |
10684 | ||
ac58c3f0 | 10685 | if (IS_PINEVIEW(dev)) |
dccbea3b | 10686 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 10687 | else |
dccbea3b | 10688 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 10689 | } else { |
0fb58223 | 10690 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10691 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10692 | |
10693 | if (is_lvds) { | |
10694 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10695 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10696 | |
10697 | if (lvds & LVDS_CLKB_POWER_UP) | |
10698 | clock.p2 = 7; | |
10699 | else | |
10700 | clock.p2 = 14; | |
79e53945 JB |
10701 | } else { |
10702 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10703 | clock.p1 = 2; | |
10704 | else { | |
10705 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10706 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10707 | } | |
10708 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10709 | clock.p2 = 4; | |
10710 | else | |
10711 | clock.p2 = 2; | |
79e53945 | 10712 | } |
da4a1efa | 10713 | |
dccbea3b | 10714 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
10715 | } |
10716 | ||
18442d08 VS |
10717 | /* |
10718 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10719 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10720 | * encoder's get_config() function. |
10721 | */ | |
dccbea3b | 10722 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
10723 | } |
10724 | ||
6878da05 VS |
10725 | int intel_dotclock_calculate(int link_freq, |
10726 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10727 | { |
f1f644dc JB |
10728 | /* |
10729 | * The calculation for the data clock is: | |
1041a02f | 10730 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10731 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10732 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10733 | * |
10734 | * and the link clock is simpler: | |
1041a02f | 10735 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10736 | */ |
10737 | ||
6878da05 VS |
10738 | if (!m_n->link_n) |
10739 | return 0; | |
f1f644dc | 10740 | |
6878da05 VS |
10741 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10742 | } | |
f1f644dc | 10743 | |
18442d08 | 10744 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10745 | struct intel_crtc_state *pipe_config) |
6878da05 VS |
10746 | { |
10747 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 10748 | |
18442d08 VS |
10749 | /* read out port_clock from the DPLL */ |
10750 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10751 | |
f1f644dc | 10752 | /* |
18442d08 | 10753 | * This value does not include pixel_multiplier. |
241bfc38 | 10754 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
10755 | * agree once we know their relationship in the encoder's |
10756 | * get_config() function. | |
79e53945 | 10757 | */ |
2d112de7 | 10758 | pipe_config->base.adjusted_mode.crtc_clock = |
18442d08 VS |
10759 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
10760 | &pipe_config->fdi_m_n); | |
79e53945 JB |
10761 | } |
10762 | ||
10763 | /** Returns the currently programmed mode of the given pipe. */ | |
10764 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10765 | struct drm_crtc *crtc) | |
10766 | { | |
548f245b | 10767 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 10768 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10769 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10770 | struct drm_display_mode *mode; |
5cec258b | 10771 | struct intel_crtc_state pipe_config; |
fe2b8f9d PZ |
10772 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10773 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10774 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10775 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10776 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10777 | |
10778 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10779 | if (!mode) | |
10780 | return NULL; | |
10781 | ||
f1f644dc JB |
10782 | /* |
10783 | * Construct a pipe_config sufficient for getting the clock info | |
10784 | * back out of crtc_clock_get. | |
10785 | * | |
10786 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10787 | * to use a real value here instead. | |
10788 | */ | |
293623f7 | 10789 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 10790 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
10791 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
10792 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10793 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
10794 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
10795 | ||
773ae034 | 10796 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
10797 | mode->hdisplay = (htot & 0xffff) + 1; |
10798 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10799 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10800 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10801 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10802 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10803 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10804 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10805 | ||
10806 | drm_mode_set_name(mode); | |
79e53945 JB |
10807 | |
10808 | return mode; | |
10809 | } | |
10810 | ||
f047e395 CW |
10811 | void intel_mark_busy(struct drm_device *dev) |
10812 | { | |
c67a470b PZ |
10813 | struct drm_i915_private *dev_priv = dev->dev_private; |
10814 | ||
f62a0076 CW |
10815 | if (dev_priv->mm.busy) |
10816 | return; | |
10817 | ||
43694d69 | 10818 | intel_runtime_pm_get(dev_priv); |
c67a470b | 10819 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
10820 | if (INTEL_INFO(dev)->gen >= 6) |
10821 | gen6_rps_busy(dev_priv); | |
f62a0076 | 10822 | dev_priv->mm.busy = true; |
f047e395 CW |
10823 | } |
10824 | ||
10825 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 10826 | { |
c67a470b | 10827 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10828 | |
f62a0076 CW |
10829 | if (!dev_priv->mm.busy) |
10830 | return; | |
10831 | ||
10832 | dev_priv->mm.busy = false; | |
10833 | ||
3d13ef2e | 10834 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 10835 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 | 10836 | |
43694d69 | 10837 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
10838 | } |
10839 | ||
79e53945 JB |
10840 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
10841 | { | |
10842 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
10843 | struct drm_device *dev = crtc->dev; |
10844 | struct intel_unpin_work *work; | |
67e77c5a | 10845 | |
5e2d7afc | 10846 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
10847 | work = intel_crtc->unpin_work; |
10848 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 10849 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
10850 | |
10851 | if (work) { | |
10852 | cancel_work_sync(&work->work); | |
10853 | kfree(work); | |
10854 | } | |
79e53945 JB |
10855 | |
10856 | drm_crtc_cleanup(crtc); | |
67e77c5a | 10857 | |
79e53945 JB |
10858 | kfree(intel_crtc); |
10859 | } | |
10860 | ||
6b95a207 KH |
10861 | static void intel_unpin_work_fn(struct work_struct *__work) |
10862 | { | |
10863 | struct intel_unpin_work *work = | |
10864 | container_of(__work, struct intel_unpin_work, work); | |
a9ff8714 VS |
10865 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
10866 | struct drm_device *dev = crtc->base.dev; | |
10867 | struct drm_plane *primary = crtc->base.primary; | |
6b95a207 | 10868 | |
b4a98e57 | 10869 | mutex_lock(&dev->struct_mutex); |
a9ff8714 | 10870 | intel_unpin_fb_obj(work->old_fb, primary->state); |
05394f39 | 10871 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 10872 | |
f06cc1b9 | 10873 | if (work->flip_queued_req) |
146d84f0 | 10874 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
10875 | mutex_unlock(&dev->struct_mutex); |
10876 | ||
a9ff8714 | 10877 | intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit); |
89ed88ba | 10878 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 10879 | |
a9ff8714 VS |
10880 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
10881 | atomic_dec(&crtc->unpin_work_count); | |
b4a98e57 | 10882 | |
6b95a207 KH |
10883 | kfree(work); |
10884 | } | |
10885 | ||
1afe3e9d | 10886 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 10887 | struct drm_crtc *crtc) |
6b95a207 | 10888 | { |
6b95a207 KH |
10889 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10890 | struct intel_unpin_work *work; | |
6b95a207 KH |
10891 | unsigned long flags; |
10892 | ||
10893 | /* Ignore early vblank irqs */ | |
10894 | if (intel_crtc == NULL) | |
10895 | return; | |
10896 | ||
f326038a DV |
10897 | /* |
10898 | * This is called both by irq handlers and the reset code (to complete | |
10899 | * lost pageflips) so needs the full irqsave spinlocks. | |
10900 | */ | |
6b95a207 KH |
10901 | spin_lock_irqsave(&dev->event_lock, flags); |
10902 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
10903 | |
10904 | /* Ensure we don't miss a work->pending update ... */ | |
10905 | smp_rmb(); | |
10906 | ||
10907 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
10908 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10909 | return; | |
10910 | } | |
10911 | ||
d6bbafa1 | 10912 | page_flip_completed(intel_crtc); |
0af7e4df | 10913 | |
6b95a207 | 10914 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
10915 | } |
10916 | ||
1afe3e9d JB |
10917 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
10918 | { | |
fbee40df | 10919 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10920 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
10921 | ||
49b14a5c | 10922 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10923 | } |
10924 | ||
10925 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
10926 | { | |
fbee40df | 10927 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10928 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
10929 | ||
49b14a5c | 10930 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10931 | } |
10932 | ||
75f7f3ec VS |
10933 | /* Is 'a' after or equal to 'b'? */ |
10934 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
10935 | { | |
10936 | return !((a - b) & 0x80000000); | |
10937 | } | |
10938 | ||
10939 | static bool page_flip_finished(struct intel_crtc *crtc) | |
10940 | { | |
10941 | struct drm_device *dev = crtc->base.dev; | |
10942 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10943 | ||
bdfa7542 VS |
10944 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
10945 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
10946 | return true; | |
10947 | ||
75f7f3ec VS |
10948 | /* |
10949 | * The relevant registers doen't exist on pre-ctg. | |
10950 | * As the flip done interrupt doesn't trigger for mmio | |
10951 | * flips on gmch platforms, a flip count check isn't | |
10952 | * really needed there. But since ctg has the registers, | |
10953 | * include it in the check anyway. | |
10954 | */ | |
10955 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
10956 | return true; | |
10957 | ||
10958 | /* | |
10959 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
10960 | * used the same base address. In that case the mmio flip might | |
10961 | * have completed, but the CS hasn't even executed the flip yet. | |
10962 | * | |
10963 | * A flip count check isn't enough as the CS might have updated | |
10964 | * the base address just after start of vblank, but before we | |
10965 | * managed to process the interrupt. This means we'd complete the | |
10966 | * CS flip too soon. | |
10967 | * | |
10968 | * Combining both checks should get us a good enough result. It may | |
10969 | * still happen that the CS flip has been executed, but has not | |
10970 | * yet actually completed. But in case the base address is the same | |
10971 | * anyway, we don't really care. | |
10972 | */ | |
10973 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
10974 | crtc->unpin_work->gtt_offset && | |
fd8f507c | 10975 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), |
75f7f3ec VS |
10976 | crtc->unpin_work->flip_count); |
10977 | } | |
10978 | ||
6b95a207 KH |
10979 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
10980 | { | |
fbee40df | 10981 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
10982 | struct intel_crtc *intel_crtc = |
10983 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
10984 | unsigned long flags; | |
10985 | ||
f326038a DV |
10986 | |
10987 | /* | |
10988 | * This is called both by irq handlers and the reset code (to complete | |
10989 | * lost pageflips) so needs the full irqsave spinlocks. | |
10990 | * | |
10991 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
10992 | * generate a page-flip completion irq, i.e. every modeset |
10993 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
10994 | */ | |
6b95a207 | 10995 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 10996 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 10997 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
10998 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10999 | } | |
11000 | ||
6042639c | 11001 | static inline void intel_mark_page_flip_active(struct intel_unpin_work *work) |
e7d841ca CW |
11002 | { |
11003 | /* Ensure that the work item is consistent when activating it ... */ | |
11004 | smp_wmb(); | |
6042639c | 11005 | atomic_set(&work->pending, INTEL_FLIP_PENDING); |
e7d841ca CW |
11006 | /* and that it is marked active as soon as the irq could fire. */ |
11007 | smp_wmb(); | |
11008 | } | |
11009 | ||
8c9f3aaf JB |
11010 | static int intel_gen2_queue_flip(struct drm_device *dev, |
11011 | struct drm_crtc *crtc, | |
11012 | struct drm_framebuffer *fb, | |
ed8d1975 | 11013 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11014 | struct drm_i915_gem_request *req, |
ed8d1975 | 11015 | uint32_t flags) |
8c9f3aaf | 11016 | { |
6258fbe2 | 11017 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf | 11018 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
11019 | u32 flip_mask; |
11020 | int ret; | |
11021 | ||
5fb9de1a | 11022 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 11023 | if (ret) |
4fa62c89 | 11024 | return ret; |
8c9f3aaf JB |
11025 | |
11026 | /* Can't queue multiple flips, so wait for the previous | |
11027 | * one to finish before executing the next. | |
11028 | */ | |
11029 | if (intel_crtc->plane) | |
11030 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11031 | else | |
11032 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
11033 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11034 | intel_ring_emit(ring, MI_NOOP); | |
11035 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
11036 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11037 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11038 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 11039 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca | 11040 | |
6042639c | 11041 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11042 | return 0; |
8c9f3aaf JB |
11043 | } |
11044 | ||
11045 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
11046 | struct drm_crtc *crtc, | |
11047 | struct drm_framebuffer *fb, | |
ed8d1975 | 11048 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11049 | struct drm_i915_gem_request *req, |
ed8d1975 | 11050 | uint32_t flags) |
8c9f3aaf | 11051 | { |
6258fbe2 | 11052 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf | 11053 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
11054 | u32 flip_mask; |
11055 | int ret; | |
11056 | ||
5fb9de1a | 11057 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 11058 | if (ret) |
4fa62c89 | 11059 | return ret; |
8c9f3aaf JB |
11060 | |
11061 | if (intel_crtc->plane) | |
11062 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11063 | else | |
11064 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
11065 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11066 | intel_ring_emit(ring, MI_NOOP); | |
11067 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
11068 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11069 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11070 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
11071 | intel_ring_emit(ring, MI_NOOP); |
11072 | ||
6042639c | 11073 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11074 | return 0; |
8c9f3aaf JB |
11075 | } |
11076 | ||
11077 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
11078 | struct drm_crtc *crtc, | |
11079 | struct drm_framebuffer *fb, | |
ed8d1975 | 11080 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11081 | struct drm_i915_gem_request *req, |
ed8d1975 | 11082 | uint32_t flags) |
8c9f3aaf | 11083 | { |
6258fbe2 | 11084 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf JB |
11085 | struct drm_i915_private *dev_priv = dev->dev_private; |
11086 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11087 | uint32_t pf, pipesrc; | |
11088 | int ret; | |
11089 | ||
5fb9de1a | 11090 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11091 | if (ret) |
4fa62c89 | 11092 | return ret; |
8c9f3aaf JB |
11093 | |
11094 | /* i965+ uses the linear or tiled offsets from the | |
11095 | * Display Registers (which do not change across a page-flip) | |
11096 | * so we need only reprogram the base address. | |
11097 | */ | |
6d90c952 DV |
11098 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
11099 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11100 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11101 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 11102 | obj->tiling_mode); |
8c9f3aaf JB |
11103 | |
11104 | /* XXX Enabling the panel-fitter across page-flip is so far | |
11105 | * untested on non-native modes, so ignore it for now. | |
11106 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
11107 | */ | |
11108 | pf = 0; | |
11109 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 11110 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca | 11111 | |
6042639c | 11112 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11113 | return 0; |
8c9f3aaf JB |
11114 | } |
11115 | ||
11116 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
11117 | struct drm_crtc *crtc, | |
11118 | struct drm_framebuffer *fb, | |
ed8d1975 | 11119 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11120 | struct drm_i915_gem_request *req, |
ed8d1975 | 11121 | uint32_t flags) |
8c9f3aaf | 11122 | { |
6258fbe2 | 11123 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf JB |
11124 | struct drm_i915_private *dev_priv = dev->dev_private; |
11125 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11126 | uint32_t pf, pipesrc; | |
11127 | int ret; | |
11128 | ||
5fb9de1a | 11129 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11130 | if (ret) |
4fa62c89 | 11131 | return ret; |
8c9f3aaf | 11132 | |
6d90c952 DV |
11133 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
11134 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11135 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 11136 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 11137 | |
dc257cf1 DV |
11138 | /* Contrary to the suggestions in the documentation, |
11139 | * "Enable Panel Fitter" does not seem to be required when page | |
11140 | * flipping with a non-native mode, and worse causes a normal | |
11141 | * modeset to fail. | |
11142 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
11143 | */ | |
11144 | pf = 0; | |
8c9f3aaf | 11145 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 11146 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca | 11147 | |
6042639c | 11148 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11149 | return 0; |
8c9f3aaf JB |
11150 | } |
11151 | ||
7c9017e5 JB |
11152 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11153 | struct drm_crtc *crtc, | |
11154 | struct drm_framebuffer *fb, | |
ed8d1975 | 11155 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11156 | struct drm_i915_gem_request *req, |
ed8d1975 | 11157 | uint32_t flags) |
7c9017e5 | 11158 | { |
6258fbe2 | 11159 | struct intel_engine_cs *ring = req->ring; |
7c9017e5 | 11160 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 11161 | uint32_t plane_bit = 0; |
ffe74d75 CW |
11162 | int len, ret; |
11163 | ||
eba905b2 | 11164 | switch (intel_crtc->plane) { |
cb05d8de DV |
11165 | case PLANE_A: |
11166 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11167 | break; | |
11168 | case PLANE_B: | |
11169 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11170 | break; | |
11171 | case PLANE_C: | |
11172 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11173 | break; | |
11174 | default: | |
11175 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 11176 | return -ENODEV; |
cb05d8de DV |
11177 | } |
11178 | ||
ffe74d75 | 11179 | len = 4; |
f476828a | 11180 | if (ring->id == RCS) { |
ffe74d75 | 11181 | len += 6; |
f476828a DL |
11182 | /* |
11183 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11184 | * 48bits addresses, and we need a NOOP for the batch size to | |
11185 | * stay even. | |
11186 | */ | |
11187 | if (IS_GEN8(dev)) | |
11188 | len += 2; | |
11189 | } | |
ffe74d75 | 11190 | |
f66fab8e VS |
11191 | /* |
11192 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11193 | * "The full packet must be contained within the same cache line." | |
11194 | * | |
11195 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11196 | * cacheline, if we ever start emitting more commands before | |
11197 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11198 | * then do the cacheline alignment, and finally emit the | |
11199 | * MI_DISPLAY_FLIP. | |
11200 | */ | |
bba09b12 | 11201 | ret = intel_ring_cacheline_align(req); |
f66fab8e | 11202 | if (ret) |
4fa62c89 | 11203 | return ret; |
f66fab8e | 11204 | |
5fb9de1a | 11205 | ret = intel_ring_begin(req, len); |
7c9017e5 | 11206 | if (ret) |
4fa62c89 | 11207 | return ret; |
7c9017e5 | 11208 | |
ffe74d75 CW |
11209 | /* Unmask the flip-done completion message. Note that the bspec says that |
11210 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11211 | * more than one flip event at any time (or ensure that one flip message | |
11212 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11213 | * Experimentation says that BCS works despite DERRMR masking all | |
11214 | * flip-done completion events and that unmasking all planes at once | |
11215 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11216 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11217 | */ | |
11218 | if (ring->id == RCS) { | |
11219 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
f92a9162 | 11220 | intel_ring_emit_reg(ring, DERRMR); |
ffe74d75 CW |
11221 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | |
11222 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
11223 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a | 11224 | if (IS_GEN8(dev)) |
f1afe24f | 11225 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 | |
f476828a DL |
11226 | MI_SRM_LRM_GLOBAL_GTT); |
11227 | else | |
f1afe24f | 11228 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM | |
f476828a | 11229 | MI_SRM_LRM_GLOBAL_GTT); |
f92a9162 | 11230 | intel_ring_emit_reg(ring, DERRMR); |
ffe74d75 | 11231 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
f476828a DL |
11232 | if (IS_GEN8(dev)) { |
11233 | intel_ring_emit(ring, 0); | |
11234 | intel_ring_emit(ring, MI_NOOP); | |
11235 | } | |
ffe74d75 CW |
11236 | } |
11237 | ||
cb05d8de | 11238 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 11239 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 11240 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 11241 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca | 11242 | |
6042639c | 11243 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11244 | return 0; |
7c9017e5 JB |
11245 | } |
11246 | ||
84c33a64 SG |
11247 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
11248 | struct drm_i915_gem_object *obj) | |
11249 | { | |
11250 | /* | |
11251 | * This is not being used for older platforms, because | |
11252 | * non-availability of flip done interrupt forces us to use | |
11253 | * CS flips. Older platforms derive flip done using some clever | |
11254 | * tricks involving the flip_pending status bits and vblank irqs. | |
11255 | * So using MMIO flips there would disrupt this mechanism. | |
11256 | */ | |
11257 | ||
8e09bf83 CW |
11258 | if (ring == NULL) |
11259 | return true; | |
11260 | ||
84c33a64 SG |
11261 | if (INTEL_INFO(ring->dev)->gen < 5) |
11262 | return false; | |
11263 | ||
11264 | if (i915.use_mmio_flip < 0) | |
11265 | return false; | |
11266 | else if (i915.use_mmio_flip > 0) | |
11267 | return true; | |
14bf993e OM |
11268 | else if (i915.enable_execlists) |
11269 | return true; | |
fd8e058a AG |
11270 | else if (obj->base.dma_buf && |
11271 | !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv, | |
11272 | false)) | |
11273 | return true; | |
84c33a64 | 11274 | else |
b4716185 | 11275 | return ring != i915_gem_request_get_ring(obj->last_write_req); |
84c33a64 SG |
11276 | } |
11277 | ||
6042639c | 11278 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, |
86efe24a | 11279 | unsigned int rotation, |
6042639c | 11280 | struct intel_unpin_work *work) |
ff944564 DL |
11281 | { |
11282 | struct drm_device *dev = intel_crtc->base.dev; | |
11283 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11284 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
ff944564 | 11285 | const enum pipe pipe = intel_crtc->pipe; |
86efe24a | 11286 | u32 ctl, stride, tile_height; |
ff944564 DL |
11287 | |
11288 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
11289 | ctl &= ~PLANE_CTL_TILED_MASK; | |
2ebef630 TU |
11290 | switch (fb->modifier[0]) { |
11291 | case DRM_FORMAT_MOD_NONE: | |
11292 | break; | |
11293 | case I915_FORMAT_MOD_X_TILED: | |
ff944564 | 11294 | ctl |= PLANE_CTL_TILED_X; |
2ebef630 TU |
11295 | break; |
11296 | case I915_FORMAT_MOD_Y_TILED: | |
11297 | ctl |= PLANE_CTL_TILED_Y; | |
11298 | break; | |
11299 | case I915_FORMAT_MOD_Yf_TILED: | |
11300 | ctl |= PLANE_CTL_TILED_YF; | |
11301 | break; | |
11302 | default: | |
11303 | MISSING_CASE(fb->modifier[0]); | |
11304 | } | |
ff944564 DL |
11305 | |
11306 | /* | |
11307 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
11308 | * linear buffers or in number of tiles for tiled buffers. | |
11309 | */ | |
86efe24a TU |
11310 | if (intel_rotation_90_or_270(rotation)) { |
11311 | /* stride = Surface height in tiles */ | |
11312 | tile_height = intel_tile_height(dev, fb->pixel_format, | |
11313 | fb->modifier[0], 0); | |
11314 | stride = DIV_ROUND_UP(fb->height, tile_height); | |
11315 | } else { | |
11316 | stride = fb->pitches[0] / | |
11317 | intel_fb_stride_alignment(dev, fb->modifier[0], | |
11318 | fb->pixel_format); | |
11319 | } | |
ff944564 DL |
11320 | |
11321 | /* | |
11322 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
11323 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
11324 | */ | |
11325 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
11326 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
11327 | ||
6042639c | 11328 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); |
ff944564 DL |
11329 | POSTING_READ(PLANE_SURF(pipe, 0)); |
11330 | } | |
11331 | ||
6042639c CW |
11332 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, |
11333 | struct intel_unpin_work *work) | |
84c33a64 SG |
11334 | { |
11335 | struct drm_device *dev = intel_crtc->base.dev; | |
11336 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11337 | struct intel_framebuffer *intel_fb = | |
11338 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
11339 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
f0f59a00 | 11340 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); |
84c33a64 | 11341 | u32 dspcntr; |
84c33a64 | 11342 | |
84c33a64 SG |
11343 | dspcntr = I915_READ(reg); |
11344 | ||
c5d97472 DL |
11345 | if (obj->tiling_mode != I915_TILING_NONE) |
11346 | dspcntr |= DISPPLANE_TILED; | |
11347 | else | |
11348 | dspcntr &= ~DISPPLANE_TILED; | |
11349 | ||
84c33a64 SG |
11350 | I915_WRITE(reg, dspcntr); |
11351 | ||
6042639c | 11352 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); |
84c33a64 | 11353 | POSTING_READ(DSPSURF(intel_crtc->plane)); |
ff944564 DL |
11354 | } |
11355 | ||
11356 | /* | |
11357 | * XXX: This is the temporary way to update the plane registers until we get | |
11358 | * around to using the usual plane update functions for MMIO flips | |
11359 | */ | |
6042639c | 11360 | static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip) |
ff944564 | 11361 | { |
6042639c CW |
11362 | struct intel_crtc *crtc = mmio_flip->crtc; |
11363 | struct intel_unpin_work *work; | |
11364 | ||
11365 | spin_lock_irq(&crtc->base.dev->event_lock); | |
11366 | work = crtc->unpin_work; | |
11367 | spin_unlock_irq(&crtc->base.dev->event_lock); | |
11368 | if (work == NULL) | |
11369 | return; | |
ff944564 | 11370 | |
6042639c | 11371 | intel_mark_page_flip_active(work); |
ff944564 | 11372 | |
6042639c | 11373 | intel_pipe_update_start(crtc); |
ff944564 | 11374 | |
6042639c | 11375 | if (INTEL_INFO(mmio_flip->i915)->gen >= 9) |
86efe24a | 11376 | skl_do_mmio_flip(crtc, mmio_flip->rotation, work); |
ff944564 DL |
11377 | else |
11378 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
6042639c | 11379 | ilk_do_mmio_flip(crtc, work); |
ff944564 | 11380 | |
6042639c | 11381 | intel_pipe_update_end(crtc); |
84c33a64 SG |
11382 | } |
11383 | ||
9362c7c5 | 11384 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 11385 | { |
b2cfe0ab CW |
11386 | struct intel_mmio_flip *mmio_flip = |
11387 | container_of(work, struct intel_mmio_flip, work); | |
fd8e058a AG |
11388 | struct intel_framebuffer *intel_fb = |
11389 | to_intel_framebuffer(mmio_flip->crtc->base.primary->fb); | |
11390 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
84c33a64 | 11391 | |
6042639c | 11392 | if (mmio_flip->req) { |
eed29a5b | 11393 | WARN_ON(__i915_wait_request(mmio_flip->req, |
b2cfe0ab | 11394 | mmio_flip->crtc->reset_counter, |
bcafc4e3 CW |
11395 | false, NULL, |
11396 | &mmio_flip->i915->rps.mmioflips)); | |
6042639c CW |
11397 | i915_gem_request_unreference__unlocked(mmio_flip->req); |
11398 | } | |
84c33a64 | 11399 | |
fd8e058a AG |
11400 | /* For framebuffer backed by dmabuf, wait for fence */ |
11401 | if (obj->base.dma_buf) | |
11402 | WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
11403 | false, false, | |
11404 | MAX_SCHEDULE_TIMEOUT) < 0); | |
11405 | ||
6042639c | 11406 | intel_do_mmio_flip(mmio_flip); |
b2cfe0ab | 11407 | kfree(mmio_flip); |
84c33a64 SG |
11408 | } |
11409 | ||
11410 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
11411 | struct drm_crtc *crtc, | |
86efe24a | 11412 | struct drm_i915_gem_object *obj) |
84c33a64 | 11413 | { |
b2cfe0ab CW |
11414 | struct intel_mmio_flip *mmio_flip; |
11415 | ||
11416 | mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); | |
11417 | if (mmio_flip == NULL) | |
11418 | return -ENOMEM; | |
84c33a64 | 11419 | |
bcafc4e3 | 11420 | mmio_flip->i915 = to_i915(dev); |
eed29a5b | 11421 | mmio_flip->req = i915_gem_request_reference(obj->last_write_req); |
b2cfe0ab | 11422 | mmio_flip->crtc = to_intel_crtc(crtc); |
86efe24a | 11423 | mmio_flip->rotation = crtc->primary->state->rotation; |
536f5b5e | 11424 | |
b2cfe0ab CW |
11425 | INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); |
11426 | schedule_work(&mmio_flip->work); | |
84c33a64 | 11427 | |
84c33a64 SG |
11428 | return 0; |
11429 | } | |
11430 | ||
8c9f3aaf JB |
11431 | static int intel_default_queue_flip(struct drm_device *dev, |
11432 | struct drm_crtc *crtc, | |
11433 | struct drm_framebuffer *fb, | |
ed8d1975 | 11434 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11435 | struct drm_i915_gem_request *req, |
ed8d1975 | 11436 | uint32_t flags) |
8c9f3aaf JB |
11437 | { |
11438 | return -ENODEV; | |
11439 | } | |
11440 | ||
d6bbafa1 CW |
11441 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
11442 | struct drm_crtc *crtc) | |
11443 | { | |
11444 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11445 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11446 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
11447 | u32 addr; | |
11448 | ||
11449 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
11450 | return true; | |
11451 | ||
908565c2 CW |
11452 | if (atomic_read(&work->pending) < INTEL_FLIP_PENDING) |
11453 | return false; | |
11454 | ||
d6bbafa1 CW |
11455 | if (!work->enable_stall_check) |
11456 | return false; | |
11457 | ||
11458 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
11459 | if (work->flip_queued_req && |
11460 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
11461 | return false; |
11462 | ||
1e3feefd | 11463 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
11464 | } |
11465 | ||
1e3feefd | 11466 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
11467 | return false; |
11468 | ||
11469 | /* Potential stall - if we see that the flip has happened, | |
11470 | * assume a missed interrupt. */ | |
11471 | if (INTEL_INFO(dev)->gen >= 4) | |
11472 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
11473 | else | |
11474 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
11475 | ||
11476 | /* There is a potential issue here with a false positive after a flip | |
11477 | * to the same address. We could address this by checking for a | |
11478 | * non-incrementing frame counter. | |
11479 | */ | |
11480 | return addr == work->gtt_offset; | |
11481 | } | |
11482 | ||
11483 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
11484 | { | |
11485 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11486 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
11487 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6ad790c0 | 11488 | struct intel_unpin_work *work; |
f326038a | 11489 | |
6c51d46f | 11490 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
11491 | |
11492 | if (crtc == NULL) | |
11493 | return; | |
11494 | ||
f326038a | 11495 | spin_lock(&dev->event_lock); |
6ad790c0 CW |
11496 | work = intel_crtc->unpin_work; |
11497 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
d6bbafa1 | 11498 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
6ad790c0 | 11499 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
d6bbafa1 | 11500 | page_flip_completed(intel_crtc); |
6ad790c0 | 11501 | work = NULL; |
d6bbafa1 | 11502 | } |
6ad790c0 CW |
11503 | if (work != NULL && |
11504 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
11505 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); | |
f326038a | 11506 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
11507 | } |
11508 | ||
6b95a207 KH |
11509 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
11510 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
11511 | struct drm_pending_vblank_event *event, |
11512 | uint32_t page_flip_flags) | |
6b95a207 KH |
11513 | { |
11514 | struct drm_device *dev = crtc->dev; | |
11515 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 11516 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 11517 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 11518 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 11519 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 11520 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 11521 | struct intel_unpin_work *work; |
a4872ba6 | 11522 | struct intel_engine_cs *ring; |
cf5d8a46 | 11523 | bool mmio_flip; |
91af127f | 11524 | struct drm_i915_gem_request *request = NULL; |
52e68630 | 11525 | int ret; |
6b95a207 | 11526 | |
2ff8fde1 MR |
11527 | /* |
11528 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
11529 | * check to be safe. In the future we may enable pageflipping from | |
11530 | * a disabled primary plane. | |
11531 | */ | |
11532 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
11533 | return -EBUSY; | |
11534 | ||
e6a595d2 | 11535 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 11536 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
11537 | return -EINVAL; |
11538 | ||
11539 | /* | |
11540 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
11541 | * Note that pitch changes could also affect these register. | |
11542 | */ | |
11543 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
11544 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
11545 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
11546 | return -EINVAL; |
11547 | ||
f900db47 CW |
11548 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
11549 | goto out_hang; | |
11550 | ||
b14c5679 | 11551 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
11552 | if (work == NULL) |
11553 | return -ENOMEM; | |
11554 | ||
6b95a207 | 11555 | work->event = event; |
b4a98e57 | 11556 | work->crtc = crtc; |
ab8d6675 | 11557 | work->old_fb = old_fb; |
6b95a207 KH |
11558 | INIT_WORK(&work->work, intel_unpin_work_fn); |
11559 | ||
87b6b101 | 11560 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
11561 | if (ret) |
11562 | goto free_work; | |
11563 | ||
6b95a207 | 11564 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 11565 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 11566 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
11567 | /* Before declaring the flip queue wedged, check if |
11568 | * the hardware completed the operation behind our backs. | |
11569 | */ | |
11570 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
11571 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
11572 | page_flip_completed(intel_crtc); | |
11573 | } else { | |
11574 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 11575 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 11576 | |
d6bbafa1 CW |
11577 | drm_crtc_vblank_put(crtc); |
11578 | kfree(work); | |
11579 | return -EBUSY; | |
11580 | } | |
6b95a207 KH |
11581 | } |
11582 | intel_crtc->unpin_work = work; | |
5e2d7afc | 11583 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 11584 | |
b4a98e57 CW |
11585 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
11586 | flush_workqueue(dev_priv->wq); | |
11587 | ||
75dfca80 | 11588 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 11589 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 11590 | drm_gem_object_reference(&obj->base); |
6b95a207 | 11591 | |
f4510a27 | 11592 | crtc->primary->fb = fb; |
afd65eb4 | 11593 | update_state_fb(crtc->primary); |
1ed1f968 | 11594 | |
e1f99ce6 | 11595 | work->pending_flip_obj = obj; |
e1f99ce6 | 11596 | |
89ed88ba CW |
11597 | ret = i915_mutex_lock_interruptible(dev); |
11598 | if (ret) | |
11599 | goto cleanup; | |
11600 | ||
b4a98e57 | 11601 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 11602 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 11603 | |
75f7f3ec | 11604 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
fd8f507c | 11605 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
75f7f3ec | 11606 | |
666a4537 | 11607 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
4fa62c89 | 11608 | ring = &dev_priv->ring[BCS]; |
ab8d6675 | 11609 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 CW |
11610 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
11611 | ring = NULL; | |
48bf5b2d | 11612 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
2a92d5bc | 11613 | ring = &dev_priv->ring[BCS]; |
4fa62c89 | 11614 | } else if (INTEL_INFO(dev)->gen >= 7) { |
b4716185 | 11615 | ring = i915_gem_request_get_ring(obj->last_write_req); |
4fa62c89 VS |
11616 | if (ring == NULL || ring->id != RCS) |
11617 | ring = &dev_priv->ring[BCS]; | |
11618 | } else { | |
11619 | ring = &dev_priv->ring[RCS]; | |
11620 | } | |
11621 | ||
cf5d8a46 CW |
11622 | mmio_flip = use_mmio_flip(ring, obj); |
11623 | ||
11624 | /* When using CS flips, we want to emit semaphores between rings. | |
11625 | * However, when using mmio flips we will create a task to do the | |
11626 | * synchronisation, so all we want here is to pin the framebuffer | |
11627 | * into the display plane and skip any waits. | |
11628 | */ | |
7580d774 ML |
11629 | if (!mmio_flip) { |
11630 | ret = i915_gem_object_sync(obj, ring, &request); | |
11631 | if (ret) | |
11632 | goto cleanup_pending; | |
11633 | } | |
11634 | ||
82bc3b2d | 11635 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, |
7580d774 | 11636 | crtc->primary->state); |
8c9f3aaf JB |
11637 | if (ret) |
11638 | goto cleanup_pending; | |
6b95a207 | 11639 | |
dedf278c TU |
11640 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), |
11641 | obj, 0); | |
11642 | work->gtt_offset += intel_crtc->dspaddr_offset; | |
4fa62c89 | 11643 | |
cf5d8a46 | 11644 | if (mmio_flip) { |
86efe24a | 11645 | ret = intel_queue_mmio_flip(dev, crtc, obj); |
d6bbafa1 CW |
11646 | if (ret) |
11647 | goto cleanup_unpin; | |
11648 | ||
f06cc1b9 JH |
11649 | i915_gem_request_assign(&work->flip_queued_req, |
11650 | obj->last_write_req); | |
d6bbafa1 | 11651 | } else { |
6258fbe2 JH |
11652 | if (!request) { |
11653 | ret = i915_gem_request_alloc(ring, ring->default_context, &request); | |
11654 | if (ret) | |
11655 | goto cleanup_unpin; | |
11656 | } | |
11657 | ||
11658 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, | |
d6bbafa1 CW |
11659 | page_flip_flags); |
11660 | if (ret) | |
11661 | goto cleanup_unpin; | |
11662 | ||
6258fbe2 | 11663 | i915_gem_request_assign(&work->flip_queued_req, request); |
d6bbafa1 CW |
11664 | } |
11665 | ||
91af127f | 11666 | if (request) |
75289874 | 11667 | i915_add_request_no_flush(request); |
91af127f | 11668 | |
1e3feefd | 11669 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 11670 | work->enable_stall_check = true; |
4fa62c89 | 11671 | |
ab8d6675 | 11672 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a9ff8714 | 11673 | to_intel_plane(primary)->frontbuffer_bit); |
c80ac854 | 11674 | mutex_unlock(&dev->struct_mutex); |
a071fa00 | 11675 | |
d029bcad | 11676 | intel_fbc_deactivate(intel_crtc); |
a9ff8714 VS |
11677 | intel_frontbuffer_flip_prepare(dev, |
11678 | to_intel_plane(primary)->frontbuffer_bit); | |
6b95a207 | 11679 | |
e5510fac JB |
11680 | trace_i915_flip_request(intel_crtc->plane, obj); |
11681 | ||
6b95a207 | 11682 | return 0; |
96b099fd | 11683 | |
4fa62c89 | 11684 | cleanup_unpin: |
82bc3b2d | 11685 | intel_unpin_fb_obj(fb, crtc->primary->state); |
8c9f3aaf | 11686 | cleanup_pending: |
91af127f JH |
11687 | if (request) |
11688 | i915_gem_request_cancel(request); | |
b4a98e57 | 11689 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
11690 | mutex_unlock(&dev->struct_mutex); |
11691 | cleanup: | |
f4510a27 | 11692 | crtc->primary->fb = old_fb; |
afd65eb4 | 11693 | update_state_fb(crtc->primary); |
89ed88ba CW |
11694 | |
11695 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 11696 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 11697 | |
5e2d7afc | 11698 | spin_lock_irq(&dev->event_lock); |
96b099fd | 11699 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 11700 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 11701 | |
87b6b101 | 11702 | drm_crtc_vblank_put(crtc); |
7317c75e | 11703 | free_work: |
96b099fd CW |
11704 | kfree(work); |
11705 | ||
f900db47 | 11706 | if (ret == -EIO) { |
02e0efb5 ML |
11707 | struct drm_atomic_state *state; |
11708 | struct drm_plane_state *plane_state; | |
11709 | ||
f900db47 | 11710 | out_hang: |
02e0efb5 ML |
11711 | state = drm_atomic_state_alloc(dev); |
11712 | if (!state) | |
11713 | return -ENOMEM; | |
11714 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
11715 | ||
11716 | retry: | |
11717 | plane_state = drm_atomic_get_plane_state(state, primary); | |
11718 | ret = PTR_ERR_OR_ZERO(plane_state); | |
11719 | if (!ret) { | |
11720 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11721 | ||
11722 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
11723 | if (!ret) | |
11724 | ret = drm_atomic_commit(state); | |
11725 | } | |
11726 | ||
11727 | if (ret == -EDEADLK) { | |
11728 | drm_modeset_backoff(state->acquire_ctx); | |
11729 | drm_atomic_state_clear(state); | |
11730 | goto retry; | |
11731 | } | |
11732 | ||
11733 | if (ret) | |
11734 | drm_atomic_state_free(state); | |
11735 | ||
f0d3dad3 | 11736 | if (ret == 0 && event) { |
5e2d7afc | 11737 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 11738 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 11739 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 11740 | } |
f900db47 | 11741 | } |
96b099fd | 11742 | return ret; |
6b95a207 KH |
11743 | } |
11744 | ||
da20eabd ML |
11745 | |
11746 | /** | |
11747 | * intel_wm_need_update - Check whether watermarks need updating | |
11748 | * @plane: drm plane | |
11749 | * @state: new plane state | |
11750 | * | |
11751 | * Check current plane state versus the new one to determine whether | |
11752 | * watermarks need to be recalculated. | |
11753 | * | |
11754 | * Returns true or false. | |
11755 | */ | |
11756 | static bool intel_wm_need_update(struct drm_plane *plane, | |
11757 | struct drm_plane_state *state) | |
11758 | { | |
d21fbe87 MR |
11759 | struct intel_plane_state *new = to_intel_plane_state(state); |
11760 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
11761 | ||
11762 | /* Update watermarks on tiling or size changes. */ | |
92826fcd ML |
11763 | if (new->visible != cur->visible) |
11764 | return true; | |
11765 | ||
11766 | if (!cur->base.fb || !new->base.fb) | |
11767 | return false; | |
11768 | ||
11769 | if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] || | |
11770 | cur->base.rotation != new->base.rotation || | |
d21fbe87 MR |
11771 | drm_rect_width(&new->src) != drm_rect_width(&cur->src) || |
11772 | drm_rect_height(&new->src) != drm_rect_height(&cur->src) || | |
11773 | drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) || | |
11774 | drm_rect_height(&new->dst) != drm_rect_height(&cur->dst)) | |
2791a16c | 11775 | return true; |
7809e5ae | 11776 | |
2791a16c | 11777 | return false; |
7809e5ae MR |
11778 | } |
11779 | ||
d21fbe87 MR |
11780 | static bool needs_scaling(struct intel_plane_state *state) |
11781 | { | |
11782 | int src_w = drm_rect_width(&state->src) >> 16; | |
11783 | int src_h = drm_rect_height(&state->src) >> 16; | |
11784 | int dst_w = drm_rect_width(&state->dst); | |
11785 | int dst_h = drm_rect_height(&state->dst); | |
11786 | ||
11787 | return (src_w != dst_w || src_h != dst_h); | |
11788 | } | |
11789 | ||
da20eabd ML |
11790 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
11791 | struct drm_plane_state *plane_state) | |
11792 | { | |
ab1d3a0e | 11793 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
11794 | struct drm_crtc *crtc = crtc_state->crtc; |
11795 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11796 | struct drm_plane *plane = plane_state->plane; | |
11797 | struct drm_device *dev = crtc->dev; | |
11798 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11799 | struct intel_plane_state *old_plane_state = | |
11800 | to_intel_plane_state(plane->state); | |
11801 | int idx = intel_crtc->base.base.id, ret; | |
11802 | int i = drm_plane_index(plane); | |
11803 | bool mode_changed = needs_modeset(crtc_state); | |
11804 | bool was_crtc_enabled = crtc->state->active; | |
11805 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
11806 | bool turn_off, turn_on, visible, was_visible; |
11807 | struct drm_framebuffer *fb = plane_state->fb; | |
11808 | ||
11809 | if (crtc_state && INTEL_INFO(dev)->gen >= 9 && | |
11810 | plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11811 | ret = skl_update_scaler_plane( | |
11812 | to_intel_crtc_state(crtc_state), | |
11813 | to_intel_plane_state(plane_state)); | |
11814 | if (ret) | |
11815 | return ret; | |
11816 | } | |
11817 | ||
da20eabd ML |
11818 | was_visible = old_plane_state->visible; |
11819 | visible = to_intel_plane_state(plane_state)->visible; | |
11820 | ||
11821 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
11822 | was_visible = false; | |
11823 | ||
11824 | if (!is_crtc_enabled && WARN_ON(visible)) | |
11825 | visible = false; | |
11826 | ||
11827 | if (!was_visible && !visible) | |
11828 | return 0; | |
11829 | ||
11830 | turn_off = was_visible && (!visible || mode_changed); | |
11831 | turn_on = visible && (!was_visible || mode_changed); | |
11832 | ||
11833 | DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx, | |
11834 | plane->base.id, fb ? fb->base.id : -1); | |
11835 | ||
11836 | DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n", | |
11837 | plane->base.id, was_visible, visible, | |
11838 | turn_off, turn_on, mode_changed); | |
11839 | ||
92826fcd ML |
11840 | if (turn_on || turn_off) { |
11841 | pipe_config->wm_changed = true; | |
11842 | ||
852eb00d VS |
11843 | /* must disable cxsr around plane enable/disable */ |
11844 | if (plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11845 | if (is_crtc_enabled) | |
11846 | intel_crtc->atomic.wait_vblank = true; | |
ab1d3a0e | 11847 | pipe_config->disable_cxsr = true; |
852eb00d VS |
11848 | } |
11849 | } else if (intel_wm_need_update(plane, plane_state)) { | |
92826fcd | 11850 | pipe_config->wm_changed = true; |
852eb00d | 11851 | } |
da20eabd | 11852 | |
8be6ca85 | 11853 | if (visible || was_visible) |
a9ff8714 VS |
11854 | intel_crtc->atomic.fb_bits |= |
11855 | to_intel_plane(plane)->frontbuffer_bit; | |
11856 | ||
da20eabd ML |
11857 | switch (plane->type) { |
11858 | case DRM_PLANE_TYPE_PRIMARY: | |
da20eabd ML |
11859 | intel_crtc->atomic.pre_disable_primary = turn_off; |
11860 | intel_crtc->atomic.post_enable_primary = turn_on; | |
11861 | ||
066cf55b RV |
11862 | if (turn_off) { |
11863 | /* | |
11864 | * FIXME: Actually if we will still have any other | |
11865 | * plane enabled on the pipe we could let IPS enabled | |
11866 | * still, but for now lets consider that when we make | |
11867 | * primary invisible by setting DSPCNTR to 0 on | |
11868 | * update_primary_plane function IPS needs to be | |
11869 | * disable. | |
11870 | */ | |
11871 | intel_crtc->atomic.disable_ips = true; | |
11872 | ||
da20eabd | 11873 | intel_crtc->atomic.disable_fbc = true; |
066cf55b | 11874 | } |
da20eabd ML |
11875 | |
11876 | /* | |
11877 | * FBC does not work on some platforms for rotated | |
11878 | * planes, so disable it when rotation is not 0 and | |
11879 | * update it when rotation is set back to 0. | |
11880 | * | |
11881 | * FIXME: This is redundant with the fbc update done in | |
11882 | * the primary plane enable function except that that | |
11883 | * one is done too late. We eventually need to unify | |
11884 | * this. | |
11885 | */ | |
11886 | ||
11887 | if (visible && | |
11888 | INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && | |
11889 | dev_priv->fbc.crtc == intel_crtc && | |
11890 | plane_state->rotation != BIT(DRM_ROTATE_0)) | |
11891 | intel_crtc->atomic.disable_fbc = true; | |
11892 | ||
11893 | /* | |
11894 | * BDW signals flip done immediately if the plane | |
11895 | * is disabled, even if the plane enable is already | |
11896 | * armed to occur at the next vblank :( | |
11897 | */ | |
11898 | if (turn_on && IS_BROADWELL(dev)) | |
11899 | intel_crtc->atomic.wait_vblank = true; | |
11900 | ||
11901 | intel_crtc->atomic.update_fbc |= visible || mode_changed; | |
11902 | break; | |
11903 | case DRM_PLANE_TYPE_CURSOR: | |
da20eabd ML |
11904 | break; |
11905 | case DRM_PLANE_TYPE_OVERLAY: | |
d21fbe87 MR |
11906 | /* |
11907 | * WaCxSRDisabledForSpriteScaling:ivb | |
11908 | * | |
11909 | * cstate->update_wm was already set above, so this flag will | |
11910 | * take effect when we commit and program watermarks. | |
11911 | */ | |
11912 | if (IS_IVYBRIDGE(dev) && | |
11913 | needs_scaling(to_intel_plane_state(plane_state)) && | |
11914 | !needs_scaling(old_plane_state)) { | |
11915 | to_intel_crtc_state(crtc_state)->disable_lp_wm = true; | |
11916 | } else if (turn_off && !mode_changed) { | |
da20eabd ML |
11917 | intel_crtc->atomic.wait_vblank = true; |
11918 | intel_crtc->atomic.update_sprite_watermarks |= | |
11919 | 1 << i; | |
11920 | } | |
d21fbe87 MR |
11921 | |
11922 | break; | |
da20eabd ML |
11923 | } |
11924 | return 0; | |
11925 | } | |
11926 | ||
6d3a1ce7 ML |
11927 | static bool encoders_cloneable(const struct intel_encoder *a, |
11928 | const struct intel_encoder *b) | |
11929 | { | |
11930 | /* masks could be asymmetric, so check both ways */ | |
11931 | return a == b || (a->cloneable & (1 << b->type) && | |
11932 | b->cloneable & (1 << a->type)); | |
11933 | } | |
11934 | ||
11935 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
11936 | struct intel_crtc *crtc, | |
11937 | struct intel_encoder *encoder) | |
11938 | { | |
11939 | struct intel_encoder *source_encoder; | |
11940 | struct drm_connector *connector; | |
11941 | struct drm_connector_state *connector_state; | |
11942 | int i; | |
11943 | ||
11944 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11945 | if (connector_state->crtc != &crtc->base) | |
11946 | continue; | |
11947 | ||
11948 | source_encoder = | |
11949 | to_intel_encoder(connector_state->best_encoder); | |
11950 | if (!encoders_cloneable(encoder, source_encoder)) | |
11951 | return false; | |
11952 | } | |
11953 | ||
11954 | return true; | |
11955 | } | |
11956 | ||
11957 | static bool check_encoder_cloning(struct drm_atomic_state *state, | |
11958 | struct intel_crtc *crtc) | |
11959 | { | |
11960 | struct intel_encoder *encoder; | |
11961 | struct drm_connector *connector; | |
11962 | struct drm_connector_state *connector_state; | |
11963 | int i; | |
11964 | ||
11965 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11966 | if (connector_state->crtc != &crtc->base) | |
11967 | continue; | |
11968 | ||
11969 | encoder = to_intel_encoder(connector_state->best_encoder); | |
11970 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
11971 | return false; | |
11972 | } | |
11973 | ||
11974 | return true; | |
11975 | } | |
11976 | ||
11977 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, | |
11978 | struct drm_crtc_state *crtc_state) | |
11979 | { | |
cf5a15be | 11980 | struct drm_device *dev = crtc->dev; |
ad421372 | 11981 | struct drm_i915_private *dev_priv = dev->dev_private; |
6d3a1ce7 | 11982 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
11983 | struct intel_crtc_state *pipe_config = |
11984 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 11985 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 11986 | int ret; |
6d3a1ce7 ML |
11987 | bool mode_changed = needs_modeset(crtc_state); |
11988 | ||
11989 | if (mode_changed && !check_encoder_cloning(state, intel_crtc)) { | |
11990 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
11991 | return -EINVAL; | |
11992 | } | |
11993 | ||
852eb00d | 11994 | if (mode_changed && !crtc_state->active) |
92826fcd | 11995 | pipe_config->wm_changed = true; |
eddfcbcd | 11996 | |
ad421372 ML |
11997 | if (mode_changed && crtc_state->enable && |
11998 | dev_priv->display.crtc_compute_clock && | |
11999 | !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) { | |
12000 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, | |
12001 | pipe_config); | |
12002 | if (ret) | |
12003 | return ret; | |
12004 | } | |
12005 | ||
e435d6e5 | 12006 | ret = 0; |
86c8bbbe MR |
12007 | if (dev_priv->display.compute_pipe_wm) { |
12008 | ret = dev_priv->display.compute_pipe_wm(intel_crtc, state); | |
12009 | if (ret) | |
12010 | return ret; | |
12011 | } | |
12012 | ||
e435d6e5 ML |
12013 | if (INTEL_INFO(dev)->gen >= 9) { |
12014 | if (mode_changed) | |
12015 | ret = skl_update_scaler_crtc(pipe_config); | |
12016 | ||
12017 | if (!ret) | |
12018 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
12019 | pipe_config); | |
12020 | } | |
12021 | ||
12022 | return ret; | |
6d3a1ce7 ML |
12023 | } |
12024 | ||
65b38e0d | 12025 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
12026 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
12027 | .load_lut = intel_crtc_load_lut, | |
ea2c67bb MR |
12028 | .atomic_begin = intel_begin_crtc_commit, |
12029 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 12030 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
12031 | }; |
12032 | ||
d29b2f9d ACO |
12033 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
12034 | { | |
12035 | struct intel_connector *connector; | |
12036 | ||
12037 | for_each_intel_connector(dev, connector) { | |
12038 | if (connector->base.encoder) { | |
12039 | connector->base.state->best_encoder = | |
12040 | connector->base.encoder; | |
12041 | connector->base.state->crtc = | |
12042 | connector->base.encoder->crtc; | |
12043 | } else { | |
12044 | connector->base.state->best_encoder = NULL; | |
12045 | connector->base.state->crtc = NULL; | |
12046 | } | |
12047 | } | |
12048 | } | |
12049 | ||
050f7aeb | 12050 | static void |
eba905b2 | 12051 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 12052 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
12053 | { |
12054 | int bpp = pipe_config->pipe_bpp; | |
12055 | ||
12056 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
12057 | connector->base.base.id, | |
c23cc417 | 12058 | connector->base.name); |
050f7aeb DV |
12059 | |
12060 | /* Don't use an invalid EDID bpc value */ | |
12061 | if (connector->base.display_info.bpc && | |
12062 | connector->base.display_info.bpc * 3 < bpp) { | |
12063 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
12064 | bpp, connector->base.display_info.bpc*3); | |
12065 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
12066 | } | |
12067 | ||
12068 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
12069 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
12070 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
12071 | bpp); | |
12072 | pipe_config->pipe_bpp = 24; | |
12073 | } | |
12074 | } | |
12075 | ||
4e53c2e0 | 12076 | static int |
050f7aeb | 12077 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 12078 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 12079 | { |
050f7aeb | 12080 | struct drm_device *dev = crtc->base.dev; |
1486017f | 12081 | struct drm_atomic_state *state; |
da3ced29 ACO |
12082 | struct drm_connector *connector; |
12083 | struct drm_connector_state *connector_state; | |
1486017f | 12084 | int bpp, i; |
4e53c2e0 | 12085 | |
666a4537 | 12086 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) |
4e53c2e0 | 12087 | bpp = 10*3; |
d328c9d7 DV |
12088 | else if (INTEL_INFO(dev)->gen >= 5) |
12089 | bpp = 12*3; | |
12090 | else | |
12091 | bpp = 8*3; | |
12092 | ||
4e53c2e0 | 12093 | |
4e53c2e0 DV |
12094 | pipe_config->pipe_bpp = bpp; |
12095 | ||
1486017f ACO |
12096 | state = pipe_config->base.state; |
12097 | ||
4e53c2e0 | 12098 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
12099 | for_each_connector_in_state(state, connector, connector_state, i) { |
12100 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
12101 | continue; |
12102 | ||
da3ced29 ACO |
12103 | connected_sink_compute_bpp(to_intel_connector(connector), |
12104 | pipe_config); | |
4e53c2e0 DV |
12105 | } |
12106 | ||
12107 | return bpp; | |
12108 | } | |
12109 | ||
644db711 DV |
12110 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
12111 | { | |
12112 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
12113 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 12114 | mode->crtc_clock, |
644db711 DV |
12115 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
12116 | mode->crtc_hsync_end, mode->crtc_htotal, | |
12117 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
12118 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
12119 | } | |
12120 | ||
c0b03411 | 12121 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 12122 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
12123 | const char *context) |
12124 | { | |
6a60cd87 CK |
12125 | struct drm_device *dev = crtc->base.dev; |
12126 | struct drm_plane *plane; | |
12127 | struct intel_plane *intel_plane; | |
12128 | struct intel_plane_state *state; | |
12129 | struct drm_framebuffer *fb; | |
12130 | ||
12131 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
12132 | context, pipe_config, pipe_name(crtc->pipe)); | |
c0b03411 DV |
12133 | |
12134 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
12135 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
12136 | pipe_config->pipe_bpp, pipe_config->dither); | |
12137 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
12138 | pipe_config->has_pch_encoder, | |
12139 | pipe_config->fdi_lanes, | |
12140 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
12141 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
12142 | pipe_config->fdi_m_n.tu); | |
90a6b7b0 | 12143 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
eb14cb74 | 12144 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12145 | pipe_config->lane_count, |
eb14cb74 VS |
12146 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
12147 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
12148 | pipe_config->dp_m_n.tu); | |
b95af8be | 12149 | |
90a6b7b0 | 12150 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
b95af8be | 12151 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12152 | pipe_config->lane_count, |
b95af8be VK |
12153 | pipe_config->dp_m2_n2.gmch_m, |
12154 | pipe_config->dp_m2_n2.gmch_n, | |
12155 | pipe_config->dp_m2_n2.link_m, | |
12156 | pipe_config->dp_m2_n2.link_n, | |
12157 | pipe_config->dp_m2_n2.tu); | |
12158 | ||
55072d19 DV |
12159 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
12160 | pipe_config->has_audio, | |
12161 | pipe_config->has_infoframe); | |
12162 | ||
c0b03411 | 12163 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 12164 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 12165 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
12166 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
12167 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 12168 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
12169 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
12170 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
12171 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
12172 | crtc->num_scalers, | |
12173 | pipe_config->scaler_state.scaler_users, | |
12174 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
12175 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
12176 | pipe_config->gmch_pfit.control, | |
12177 | pipe_config->gmch_pfit.pgm_ratios, | |
12178 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 12179 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 12180 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
12181 | pipe_config->pch_pfit.size, |
12182 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 12183 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 12184 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 12185 | |
415ff0f6 | 12186 | if (IS_BROXTON(dev)) { |
05712c15 | 12187 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 12188 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 12189 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 TU |
12190 | pipe_config->ddi_pll_sel, |
12191 | pipe_config->dpll_hw_state.ebb0, | |
05712c15 | 12192 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
12193 | pipe_config->dpll_hw_state.pll0, |
12194 | pipe_config->dpll_hw_state.pll1, | |
12195 | pipe_config->dpll_hw_state.pll2, | |
12196 | pipe_config->dpll_hw_state.pll3, | |
12197 | pipe_config->dpll_hw_state.pll6, | |
12198 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 12199 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 12200 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 | 12201 | pipe_config->dpll_hw_state.pcsdw12); |
ef11bdb3 | 12202 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
415ff0f6 TU |
12203 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " |
12204 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
12205 | pipe_config->ddi_pll_sel, | |
12206 | pipe_config->dpll_hw_state.ctrl1, | |
12207 | pipe_config->dpll_hw_state.cfgcr1, | |
12208 | pipe_config->dpll_hw_state.cfgcr2); | |
12209 | } else if (HAS_DDI(dev)) { | |
00490c22 | 12210 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
415ff0f6 | 12211 | pipe_config->ddi_pll_sel, |
00490c22 ML |
12212 | pipe_config->dpll_hw_state.wrpll, |
12213 | pipe_config->dpll_hw_state.spll); | |
415ff0f6 TU |
12214 | } else { |
12215 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12216 | "fp0: 0x%x, fp1: 0x%x\n", | |
12217 | pipe_config->dpll_hw_state.dpll, | |
12218 | pipe_config->dpll_hw_state.dpll_md, | |
12219 | pipe_config->dpll_hw_state.fp0, | |
12220 | pipe_config->dpll_hw_state.fp1); | |
12221 | } | |
12222 | ||
6a60cd87 CK |
12223 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12224 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
12225 | intel_plane = to_intel_plane(plane); | |
12226 | if (intel_plane->pipe != crtc->pipe) | |
12227 | continue; | |
12228 | ||
12229 | state = to_intel_plane_state(plane->state); | |
12230 | fb = state->base.fb; | |
12231 | if (!fb) { | |
12232 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
12233 | "disabled, scaler_id = %d\n", | |
12234 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12235 | plane->base.id, intel_plane->pipe, | |
12236 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
12237 | drm_plane_index(plane), state->scaler_id); | |
12238 | continue; | |
12239 | } | |
12240 | ||
12241 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
12242 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12243 | plane->base.id, intel_plane->pipe, | |
12244 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
12245 | drm_plane_index(plane)); | |
12246 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
12247 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
12248 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
12249 | state->scaler_id, | |
12250 | state->src.x1 >> 16, state->src.y1 >> 16, | |
12251 | drm_rect_width(&state->src) >> 16, | |
12252 | drm_rect_height(&state->src) >> 16, | |
12253 | state->dst.x1, state->dst.y1, | |
12254 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
12255 | } | |
c0b03411 DV |
12256 | } |
12257 | ||
5448a00d | 12258 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12259 | { |
5448a00d ACO |
12260 | struct drm_device *dev = state->dev; |
12261 | struct intel_encoder *encoder; | |
da3ced29 | 12262 | struct drm_connector *connector; |
5448a00d | 12263 | struct drm_connector_state *connector_state; |
00f0b378 | 12264 | unsigned int used_ports = 0; |
5448a00d | 12265 | int i; |
00f0b378 VS |
12266 | |
12267 | /* | |
12268 | * Walk the connector list instead of the encoder | |
12269 | * list to detect the problem on ddi platforms | |
12270 | * where there's just one encoder per digital port. | |
12271 | */ | |
da3ced29 | 12272 | for_each_connector_in_state(state, connector, connector_state, i) { |
5448a00d | 12273 | if (!connector_state->best_encoder) |
00f0b378 VS |
12274 | continue; |
12275 | ||
5448a00d ACO |
12276 | encoder = to_intel_encoder(connector_state->best_encoder); |
12277 | ||
12278 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12279 | |
12280 | switch (encoder->type) { | |
12281 | unsigned int port_mask; | |
12282 | case INTEL_OUTPUT_UNKNOWN: | |
12283 | if (WARN_ON(!HAS_DDI(dev))) | |
12284 | break; | |
12285 | case INTEL_OUTPUT_DISPLAYPORT: | |
12286 | case INTEL_OUTPUT_HDMI: | |
12287 | case INTEL_OUTPUT_EDP: | |
12288 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12289 | ||
12290 | /* the same port mustn't appear more than once */ | |
12291 | if (used_ports & port_mask) | |
12292 | return false; | |
12293 | ||
12294 | used_ports |= port_mask; | |
12295 | default: | |
12296 | break; | |
12297 | } | |
12298 | } | |
12299 | ||
12300 | return true; | |
12301 | } | |
12302 | ||
83a57153 ACO |
12303 | static void |
12304 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12305 | { | |
12306 | struct drm_crtc_state tmp_state; | |
663a3640 | 12307 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 ACO |
12308 | struct intel_dpll_hw_state dpll_hw_state; |
12309 | enum intel_dpll_id shared_dpll; | |
8504c74c | 12310 | uint32_t ddi_pll_sel; |
c4e2d043 | 12311 | bool force_thru; |
83a57153 | 12312 | |
7546a384 ACO |
12313 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12314 | * kzalloc'd. Code that depends on any field being zero should be | |
12315 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12316 | * only fields that are know to not cause problems are preserved. */ | |
12317 | ||
83a57153 | 12318 | tmp_state = crtc_state->base; |
663a3640 | 12319 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12320 | shared_dpll = crtc_state->shared_dpll; |
12321 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 12322 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
c4e2d043 | 12323 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 12324 | |
83a57153 | 12325 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12326 | |
83a57153 | 12327 | crtc_state->base = tmp_state; |
663a3640 | 12328 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12329 | crtc_state->shared_dpll = shared_dpll; |
12330 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 12331 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
c4e2d043 | 12332 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
12333 | } |
12334 | ||
548ee15b | 12335 | static int |
b8cecdf5 | 12336 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12337 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12338 | { |
b359283a | 12339 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12340 | struct intel_encoder *encoder; |
da3ced29 | 12341 | struct drm_connector *connector; |
0b901879 | 12342 | struct drm_connector_state *connector_state; |
d328c9d7 | 12343 | int base_bpp, ret = -EINVAL; |
0b901879 | 12344 | int i; |
e29c22c0 | 12345 | bool retry = true; |
ee7b9f93 | 12346 | |
83a57153 | 12347 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12348 | |
e143a21c DV |
12349 | pipe_config->cpu_transcoder = |
12350 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12351 | |
2960bc9c ID |
12352 | /* |
12353 | * Sanitize sync polarity flags based on requested ones. If neither | |
12354 | * positive or negative polarity is requested, treat this as meaning | |
12355 | * negative polarity. | |
12356 | */ | |
2d112de7 | 12357 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12358 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12359 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 12360 | |
2d112de7 | 12361 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12362 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 12363 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 12364 | |
d328c9d7 DV |
12365 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
12366 | pipe_config); | |
12367 | if (base_bpp < 0) | |
4e53c2e0 DV |
12368 | goto fail; |
12369 | ||
e41a56be VS |
12370 | /* |
12371 | * Determine the real pipe dimensions. Note that stereo modes can | |
12372 | * increase the actual pipe size due to the frame doubling and | |
12373 | * insertion of additional space for blanks between the frame. This | |
12374 | * is stored in the crtc timings. We use the requested mode to do this | |
12375 | * computation to clearly distinguish it from the adjusted mode, which | |
12376 | * can be changed by the connectors in the below retry loop. | |
12377 | */ | |
2d112de7 | 12378 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
12379 | &pipe_config->pipe_src_w, |
12380 | &pipe_config->pipe_src_h); | |
e41a56be | 12381 | |
e29c22c0 | 12382 | encoder_retry: |
ef1b460d | 12383 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 12384 | pipe_config->port_clock = 0; |
ef1b460d | 12385 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 12386 | |
135c81b8 | 12387 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
12388 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
12389 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 12390 | |
7758a113 DV |
12391 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
12392 | * adjust it according to limitations or connector properties, and also | |
12393 | * a chance to reject the mode entirely. | |
47f1c6c9 | 12394 | */ |
da3ced29 | 12395 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 12396 | if (connector_state->crtc != crtc) |
7758a113 | 12397 | continue; |
7ae89233 | 12398 | |
0b901879 ACO |
12399 | encoder = to_intel_encoder(connector_state->best_encoder); |
12400 | ||
efea6e8e DV |
12401 | if (!(encoder->compute_config(encoder, pipe_config))) { |
12402 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
12403 | goto fail; |
12404 | } | |
ee7b9f93 | 12405 | } |
47f1c6c9 | 12406 | |
ff9a6750 DV |
12407 | /* Set default port clock if not overwritten by the encoder. Needs to be |
12408 | * done afterwards in case the encoder adjusts the mode. */ | |
12409 | if (!pipe_config->port_clock) | |
2d112de7 | 12410 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 12411 | * pipe_config->pixel_multiplier; |
ff9a6750 | 12412 | |
a43f6e0f | 12413 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 12414 | if (ret < 0) { |
7758a113 DV |
12415 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
12416 | goto fail; | |
ee7b9f93 | 12417 | } |
e29c22c0 DV |
12418 | |
12419 | if (ret == RETRY) { | |
12420 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
12421 | ret = -EINVAL; | |
12422 | goto fail; | |
12423 | } | |
12424 | ||
12425 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
12426 | retry = false; | |
12427 | goto encoder_retry; | |
12428 | } | |
12429 | ||
e8fa4270 DV |
12430 | /* Dithering seems to not pass-through bits correctly when it should, so |
12431 | * only enable it on 6bpc panels. */ | |
12432 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 12433 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 12434 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 12435 | |
7758a113 | 12436 | fail: |
548ee15b | 12437 | return ret; |
ee7b9f93 | 12438 | } |
47f1c6c9 | 12439 | |
ea9d758d | 12440 | static void |
4740b0f2 | 12441 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 12442 | { |
0a9ab303 ACO |
12443 | struct drm_crtc *crtc; |
12444 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 12445 | int i; |
ea9d758d | 12446 | |
7668851f | 12447 | /* Double check state. */ |
8a75d157 | 12448 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 12449 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
12450 | |
12451 | /* Update hwmode for vblank functions */ | |
12452 | if (crtc->state->active) | |
12453 | crtc->hwmode = crtc->state->adjusted_mode; | |
12454 | else | |
12455 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
12456 | |
12457 | /* | |
12458 | * Update legacy state to satisfy fbc code. This can | |
12459 | * be removed when fbc uses the atomic state. | |
12460 | */ | |
12461 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12462 | struct drm_plane_state *plane_state = crtc->primary->state; | |
12463 | ||
12464 | crtc->primary->fb = plane_state->fb; | |
12465 | crtc->x = plane_state->src_x >> 16; | |
12466 | crtc->y = plane_state->src_y >> 16; | |
12467 | } | |
ea9d758d | 12468 | } |
ea9d758d DV |
12469 | } |
12470 | ||
3bd26263 | 12471 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 12472 | { |
3bd26263 | 12473 | int diff; |
f1f644dc JB |
12474 | |
12475 | if (clock1 == clock2) | |
12476 | return true; | |
12477 | ||
12478 | if (!clock1 || !clock2) | |
12479 | return false; | |
12480 | ||
12481 | diff = abs(clock1 - clock2); | |
12482 | ||
12483 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
12484 | return true; | |
12485 | ||
12486 | return false; | |
12487 | } | |
12488 | ||
25c5b266 DV |
12489 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
12490 | list_for_each_entry((intel_crtc), \ | |
12491 | &(dev)->mode_config.crtc_list, \ | |
12492 | base.head) \ | |
0973f18f | 12493 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 12494 | |
cfb23ed6 ML |
12495 | static bool |
12496 | intel_compare_m_n(unsigned int m, unsigned int n, | |
12497 | unsigned int m2, unsigned int n2, | |
12498 | bool exact) | |
12499 | { | |
12500 | if (m == m2 && n == n2) | |
12501 | return true; | |
12502 | ||
12503 | if (exact || !m || !n || !m2 || !n2) | |
12504 | return false; | |
12505 | ||
12506 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
12507 | ||
12508 | if (m > m2) { | |
12509 | while (m > m2) { | |
12510 | m2 <<= 1; | |
12511 | n2 <<= 1; | |
12512 | } | |
12513 | } else if (m < m2) { | |
12514 | while (m < m2) { | |
12515 | m <<= 1; | |
12516 | n <<= 1; | |
12517 | } | |
12518 | } | |
12519 | ||
12520 | return m == m2 && n == n2; | |
12521 | } | |
12522 | ||
12523 | static bool | |
12524 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
12525 | struct intel_link_m_n *m2_n2, | |
12526 | bool adjust) | |
12527 | { | |
12528 | if (m_n->tu == m2_n2->tu && | |
12529 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
12530 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
12531 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
12532 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
12533 | if (adjust) | |
12534 | *m2_n2 = *m_n; | |
12535 | ||
12536 | return true; | |
12537 | } | |
12538 | ||
12539 | return false; | |
12540 | } | |
12541 | ||
0e8ffe1b | 12542 | static bool |
2fa2fe9a | 12543 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b | 12544 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
12545 | struct intel_crtc_state *pipe_config, |
12546 | bool adjust) | |
0e8ffe1b | 12547 | { |
cfb23ed6 ML |
12548 | bool ret = true; |
12549 | ||
12550 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
12551 | do { \ | |
12552 | if (!adjust) \ | |
12553 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
12554 | else \ | |
12555 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
12556 | } while (0) | |
12557 | ||
66e985c0 DV |
12558 | #define PIPE_CONF_CHECK_X(name) \ |
12559 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12560 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
12561 | "(expected 0x%08x, found 0x%08x)\n", \ |
12562 | current_config->name, \ | |
12563 | pipe_config->name); \ | |
cfb23ed6 | 12564 | ret = false; \ |
66e985c0 DV |
12565 | } |
12566 | ||
08a24034 DV |
12567 | #define PIPE_CONF_CHECK_I(name) \ |
12568 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12569 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
12570 | "(expected %i, found %i)\n", \ |
12571 | current_config->name, \ | |
12572 | pipe_config->name); \ | |
cfb23ed6 ML |
12573 | ret = false; \ |
12574 | } | |
12575 | ||
12576 | #define PIPE_CONF_CHECK_M_N(name) \ | |
12577 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12578 | &pipe_config->name,\ | |
12579 | adjust)) { \ | |
12580 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12581 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12582 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12583 | current_config->name.tu, \ | |
12584 | current_config->name.gmch_m, \ | |
12585 | current_config->name.gmch_n, \ | |
12586 | current_config->name.link_m, \ | |
12587 | current_config->name.link_n, \ | |
12588 | pipe_config->name.tu, \ | |
12589 | pipe_config->name.gmch_m, \ | |
12590 | pipe_config->name.gmch_n, \ | |
12591 | pipe_config->name.link_m, \ | |
12592 | pipe_config->name.link_n); \ | |
12593 | ret = false; \ | |
12594 | } | |
12595 | ||
12596 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ | |
12597 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12598 | &pipe_config->name, adjust) && \ | |
12599 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
12600 | &pipe_config->name, adjust)) { \ | |
12601 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12602 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12603 | "or tu %i gmch %i/%i link %i/%i, " \ | |
12604 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12605 | current_config->name.tu, \ | |
12606 | current_config->name.gmch_m, \ | |
12607 | current_config->name.gmch_n, \ | |
12608 | current_config->name.link_m, \ | |
12609 | current_config->name.link_n, \ | |
12610 | current_config->alt_name.tu, \ | |
12611 | current_config->alt_name.gmch_m, \ | |
12612 | current_config->alt_name.gmch_n, \ | |
12613 | current_config->alt_name.link_m, \ | |
12614 | current_config->alt_name.link_n, \ | |
12615 | pipe_config->name.tu, \ | |
12616 | pipe_config->name.gmch_m, \ | |
12617 | pipe_config->name.gmch_n, \ | |
12618 | pipe_config->name.link_m, \ | |
12619 | pipe_config->name.link_n); \ | |
12620 | ret = false; \ | |
88adfff1 DV |
12621 | } |
12622 | ||
b95af8be VK |
12623 | /* This is required for BDW+ where there is only one set of registers for |
12624 | * switching between high and low RR. | |
12625 | * This macro can be used whenever a comparison has to be made between one | |
12626 | * hw state and multiple sw state variables. | |
12627 | */ | |
12628 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
12629 | if ((current_config->name != pipe_config->name) && \ | |
12630 | (current_config->alt_name != pipe_config->name)) { \ | |
cfb23ed6 | 12631 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
b95af8be VK |
12632 | "(expected %i or %i, found %i)\n", \ |
12633 | current_config->name, \ | |
12634 | current_config->alt_name, \ | |
12635 | pipe_config->name); \ | |
cfb23ed6 | 12636 | ret = false; \ |
b95af8be VK |
12637 | } |
12638 | ||
1bd1bd80 DV |
12639 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
12640 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 12641 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
12642 | "(expected %i, found %i)\n", \ |
12643 | current_config->name & (mask), \ | |
12644 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 12645 | ret = false; \ |
1bd1bd80 DV |
12646 | } |
12647 | ||
5e550656 VS |
12648 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
12649 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 12650 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
12651 | "(expected %i, found %i)\n", \ |
12652 | current_config->name, \ | |
12653 | pipe_config->name); \ | |
cfb23ed6 | 12654 | ret = false; \ |
5e550656 VS |
12655 | } |
12656 | ||
bb760063 DV |
12657 | #define PIPE_CONF_QUIRK(quirk) \ |
12658 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
12659 | ||
eccb140b DV |
12660 | PIPE_CONF_CHECK_I(cpu_transcoder); |
12661 | ||
08a24034 DV |
12662 | PIPE_CONF_CHECK_I(has_pch_encoder); |
12663 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 12664 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 12665 | |
eb14cb74 | 12666 | PIPE_CONF_CHECK_I(has_dp_encoder); |
90a6b7b0 | 12667 | PIPE_CONF_CHECK_I(lane_count); |
b95af8be VK |
12668 | |
12669 | if (INTEL_INFO(dev)->gen < 8) { | |
cfb23ed6 ML |
12670 | PIPE_CONF_CHECK_M_N(dp_m_n); |
12671 | ||
12672 | PIPE_CONF_CHECK_I(has_drrs); | |
12673 | if (current_config->has_drrs) | |
12674 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
12675 | } else | |
12676 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 12677 | |
a65347ba JN |
12678 | PIPE_CONF_CHECK_I(has_dsi_encoder); |
12679 | ||
2d112de7 ACO |
12680 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12681 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
12682 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
12683 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
12684 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
12685 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 12686 | |
2d112de7 ACO |
12687 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
12688 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
12689 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
12690 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
12691 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
12692 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 12693 | |
c93f54cf | 12694 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 12695 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 | 12696 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
666a4537 | 12697 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
b5a9fa09 | 12698 | PIPE_CONF_CHECK_I(limited_color_range); |
e43823ec | 12699 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 12700 | |
9ed109a7 DV |
12701 | PIPE_CONF_CHECK_I(has_audio); |
12702 | ||
2d112de7 | 12703 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
12704 | DRM_MODE_FLAG_INTERLACE); |
12705 | ||
bb760063 | 12706 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 12707 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12708 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 12709 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12710 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 12711 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12712 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 12713 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
12714 | DRM_MODE_FLAG_NVSYNC); |
12715 | } | |
045ac3b5 | 12716 | |
333b8ca8 | 12717 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a DV |
12718 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
12719 | if (INTEL_INFO(dev)->gen < 4) | |
12720 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
333b8ca8 | 12721 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 12722 | |
bfd16b2a ML |
12723 | if (!adjust) { |
12724 | PIPE_CONF_CHECK_I(pipe_src_w); | |
12725 | PIPE_CONF_CHECK_I(pipe_src_h); | |
12726 | ||
12727 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
12728 | if (current_config->pch_pfit.enabled) { | |
12729 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
12730 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
12731 | } | |
2fa2fe9a | 12732 | |
7aefe2b5 ML |
12733 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
12734 | } | |
a1b2278e | 12735 | |
e59150dc JB |
12736 | /* BDW+ don't expose a synchronous way to read the state */ |
12737 | if (IS_HASWELL(dev)) | |
12738 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 12739 | |
282740f7 VS |
12740 | PIPE_CONF_CHECK_I(double_wide); |
12741 | ||
26804afd DV |
12742 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
12743 | ||
c0d43d62 | 12744 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 12745 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 12746 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
12747 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
12748 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 12749 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 12750 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
12751 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
12752 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
12753 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 12754 | |
42571aef VS |
12755 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
12756 | PIPE_CONF_CHECK_I(pipe_bpp); | |
12757 | ||
2d112de7 | 12758 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 12759 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 12760 | |
66e985c0 | 12761 | #undef PIPE_CONF_CHECK_X |
08a24034 | 12762 | #undef PIPE_CONF_CHECK_I |
b95af8be | 12763 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 12764 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 12765 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 12766 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 12767 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 12768 | |
cfb23ed6 | 12769 | return ret; |
0e8ffe1b DV |
12770 | } |
12771 | ||
08db6652 DL |
12772 | static void check_wm_state(struct drm_device *dev) |
12773 | { | |
12774 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12775 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
12776 | struct intel_crtc *intel_crtc; | |
12777 | int plane; | |
12778 | ||
12779 | if (INTEL_INFO(dev)->gen < 9) | |
12780 | return; | |
12781 | ||
12782 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
12783 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
12784 | ||
12785 | for_each_intel_crtc(dev, intel_crtc) { | |
12786 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
12787 | const enum pipe pipe = intel_crtc->pipe; | |
12788 | ||
12789 | if (!intel_crtc->active) | |
12790 | continue; | |
12791 | ||
12792 | /* planes */ | |
dd740780 | 12793 | for_each_plane(dev_priv, pipe, plane) { |
08db6652 DL |
12794 | hw_entry = &hw_ddb.plane[pipe][plane]; |
12795 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
12796 | ||
12797 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12798 | continue; | |
12799 | ||
12800 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
12801 | "(expected (%u,%u), found (%u,%u))\n", | |
12802 | pipe_name(pipe), plane + 1, | |
12803 | sw_entry->start, sw_entry->end, | |
12804 | hw_entry->start, hw_entry->end); | |
12805 | } | |
12806 | ||
12807 | /* cursor */ | |
4969d33e MR |
12808 | hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; |
12809 | sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
08db6652 DL |
12810 | |
12811 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12812 | continue; | |
12813 | ||
12814 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
12815 | "(expected (%u,%u), found (%u,%u))\n", | |
12816 | pipe_name(pipe), | |
12817 | sw_entry->start, sw_entry->end, | |
12818 | hw_entry->start, hw_entry->end); | |
12819 | } | |
12820 | } | |
12821 | ||
91d1b4bd | 12822 | static void |
35dd3c64 ML |
12823 | check_connector_state(struct drm_device *dev, |
12824 | struct drm_atomic_state *old_state) | |
8af6cf88 | 12825 | { |
35dd3c64 ML |
12826 | struct drm_connector_state *old_conn_state; |
12827 | struct drm_connector *connector; | |
12828 | int i; | |
8af6cf88 | 12829 | |
35dd3c64 ML |
12830 | for_each_connector_in_state(old_state, connector, old_conn_state, i) { |
12831 | struct drm_encoder *encoder = connector->encoder; | |
12832 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 12833 | |
8af6cf88 DV |
12834 | /* This also checks the encoder/connector hw state with the |
12835 | * ->get_hw_state callbacks. */ | |
35dd3c64 | 12836 | intel_connector_check_state(to_intel_connector(connector)); |
8af6cf88 | 12837 | |
ad3c558f | 12838 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 12839 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 12840 | } |
91d1b4bd DV |
12841 | } |
12842 | ||
12843 | static void | |
12844 | check_encoder_state(struct drm_device *dev) | |
12845 | { | |
12846 | struct intel_encoder *encoder; | |
12847 | struct intel_connector *connector; | |
8af6cf88 | 12848 | |
b2784e15 | 12849 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 12850 | bool enabled = false; |
4d20cd86 | 12851 | enum pipe pipe; |
8af6cf88 DV |
12852 | |
12853 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
12854 | encoder->base.base.id, | |
8e329a03 | 12855 | encoder->base.name); |
8af6cf88 | 12856 | |
3a3371ff | 12857 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 12858 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
12859 | continue; |
12860 | enabled = true; | |
ad3c558f ML |
12861 | |
12862 | I915_STATE_WARN(connector->base.state->crtc != | |
12863 | encoder->base.crtc, | |
12864 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 12865 | } |
0e32b39c | 12866 | |
e2c719b7 | 12867 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
12868 | "encoder's enabled state mismatch " |
12869 | "(expected %i, found %i)\n", | |
12870 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
12871 | |
12872 | if (!encoder->base.crtc) { | |
4d20cd86 | 12873 | bool active; |
7c60d198 | 12874 | |
4d20cd86 ML |
12875 | active = encoder->get_hw_state(encoder, &pipe); |
12876 | I915_STATE_WARN(active, | |
12877 | "encoder detached but still enabled on pipe %c.\n", | |
12878 | pipe_name(pipe)); | |
7c60d198 | 12879 | } |
8af6cf88 | 12880 | } |
91d1b4bd DV |
12881 | } |
12882 | ||
12883 | static void | |
4d20cd86 | 12884 | check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state) |
91d1b4bd | 12885 | { |
fbee40df | 12886 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd | 12887 | struct intel_encoder *encoder; |
4d20cd86 ML |
12888 | struct drm_crtc_state *old_crtc_state; |
12889 | struct drm_crtc *crtc; | |
12890 | int i; | |
8af6cf88 | 12891 | |
4d20cd86 ML |
12892 | for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) { |
12893 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12894 | struct intel_crtc_state *pipe_config, *sw_config; | |
7b89b8de | 12895 | bool active; |
8af6cf88 | 12896 | |
bfd16b2a ML |
12897 | if (!needs_modeset(crtc->state) && |
12898 | !to_intel_crtc_state(crtc->state)->update_pipe) | |
4d20cd86 | 12899 | continue; |
045ac3b5 | 12900 | |
4d20cd86 ML |
12901 | __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state); |
12902 | pipe_config = to_intel_crtc_state(old_crtc_state); | |
12903 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
12904 | pipe_config->base.crtc = crtc; | |
12905 | pipe_config->base.state = old_state; | |
8af6cf88 | 12906 | |
4d20cd86 ML |
12907 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
12908 | crtc->base.id); | |
8af6cf88 | 12909 | |
4d20cd86 ML |
12910 | active = dev_priv->display.get_pipe_config(intel_crtc, |
12911 | pipe_config); | |
d62cf62a | 12912 | |
b6b5d049 | 12913 | /* hw state is inconsistent with the pipe quirk */ |
4d20cd86 ML |
12914 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
12915 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
12916 | active = crtc->state->active; | |
6c49f241 | 12917 | |
4d20cd86 | 12918 | I915_STATE_WARN(crtc->state->active != active, |
0e8ffe1b | 12919 | "crtc active state doesn't match with hw state " |
4d20cd86 | 12920 | "(expected %i, found %i)\n", crtc->state->active, active); |
0e8ffe1b | 12921 | |
4d20cd86 | 12922 | I915_STATE_WARN(intel_crtc->active != crtc->state->active, |
53d9f4e9 | 12923 | "transitional active state does not match atomic hw state " |
4d20cd86 ML |
12924 | "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active); |
12925 | ||
12926 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
12927 | enum pipe pipe; | |
12928 | ||
12929 | active = encoder->get_hw_state(encoder, &pipe); | |
12930 | I915_STATE_WARN(active != crtc->state->active, | |
12931 | "[ENCODER:%i] active %i with crtc active %i\n", | |
12932 | encoder->base.base.id, active, crtc->state->active); | |
12933 | ||
12934 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, | |
12935 | "Encoder connected to wrong pipe %c\n", | |
12936 | pipe_name(pipe)); | |
12937 | ||
12938 | if (active) | |
12939 | encoder->get_config(encoder, pipe_config); | |
12940 | } | |
53d9f4e9 | 12941 | |
4d20cd86 | 12942 | if (!crtc->state->active) |
cfb23ed6 ML |
12943 | continue; |
12944 | ||
4d20cd86 ML |
12945 | sw_config = to_intel_crtc_state(crtc->state); |
12946 | if (!intel_pipe_config_compare(dev, sw_config, | |
12947 | pipe_config, false)) { | |
e2c719b7 | 12948 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
4d20cd86 | 12949 | intel_dump_pipe_config(intel_crtc, pipe_config, |
c0b03411 | 12950 | "[hw state]"); |
4d20cd86 | 12951 | intel_dump_pipe_config(intel_crtc, sw_config, |
c0b03411 DV |
12952 | "[sw state]"); |
12953 | } | |
8af6cf88 DV |
12954 | } |
12955 | } | |
12956 | ||
91d1b4bd DV |
12957 | static void |
12958 | check_shared_dpll_state(struct drm_device *dev) | |
12959 | { | |
fbee40df | 12960 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
12961 | struct intel_crtc *crtc; |
12962 | struct intel_dpll_hw_state dpll_hw_state; | |
12963 | int i; | |
5358901f DV |
12964 | |
12965 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
12966 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
12967 | int enabled_crtcs = 0, active_crtcs = 0; | |
12968 | bool active; | |
12969 | ||
12970 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
12971 | ||
12972 | DRM_DEBUG_KMS("%s\n", pll->name); | |
12973 | ||
12974 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
12975 | ||
e2c719b7 | 12976 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 12977 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 12978 | pll->active, hweight32(pll->config.crtc_mask)); |
e2c719b7 | 12979 | I915_STATE_WARN(pll->active && !pll->on, |
5358901f | 12980 | "pll in active use but not on in sw tracking\n"); |
e2c719b7 | 12981 | I915_STATE_WARN(pll->on && !pll->active, |
35c95375 | 12982 | "pll in on but not on in use in sw tracking\n"); |
e2c719b7 | 12983 | I915_STATE_WARN(pll->on != active, |
5358901f DV |
12984 | "pll on state mismatch (expected %i, found %i)\n", |
12985 | pll->on, active); | |
12986 | ||
d3fcc808 | 12987 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 12988 | if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
5358901f DV |
12989 | enabled_crtcs++; |
12990 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
12991 | active_crtcs++; | |
12992 | } | |
e2c719b7 | 12993 | I915_STATE_WARN(pll->active != active_crtcs, |
5358901f DV |
12994 | "pll active crtcs mismatch (expected %i, found %i)\n", |
12995 | pll->active, active_crtcs); | |
e2c719b7 | 12996 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 12997 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 12998 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 12999 | |
e2c719b7 | 13000 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
13001 | sizeof(dpll_hw_state)), |
13002 | "pll hw state mismatch\n"); | |
5358901f | 13003 | } |
8af6cf88 DV |
13004 | } |
13005 | ||
ee165b1a ML |
13006 | static void |
13007 | intel_modeset_check_state(struct drm_device *dev, | |
13008 | struct drm_atomic_state *old_state) | |
91d1b4bd | 13009 | { |
08db6652 | 13010 | check_wm_state(dev); |
35dd3c64 | 13011 | check_connector_state(dev, old_state); |
91d1b4bd | 13012 | check_encoder_state(dev); |
4d20cd86 | 13013 | check_crtc_state(dev, old_state); |
91d1b4bd DV |
13014 | check_shared_dpll_state(dev); |
13015 | } | |
13016 | ||
5cec258b | 13017 | void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
18442d08 VS |
13018 | int dotclock) |
13019 | { | |
13020 | /* | |
13021 | * FDI already provided one idea for the dotclock. | |
13022 | * Yell if the encoder disagrees. | |
13023 | */ | |
2d112de7 | 13024 | WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), |
18442d08 | 13025 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
2d112de7 | 13026 | pipe_config->base.adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
13027 | } |
13028 | ||
80715b2f VS |
13029 | static void update_scanline_offset(struct intel_crtc *crtc) |
13030 | { | |
13031 | struct drm_device *dev = crtc->base.dev; | |
13032 | ||
13033 | /* | |
13034 | * The scanline counter increments at the leading edge of hsync. | |
13035 | * | |
13036 | * On most platforms it starts counting from vtotal-1 on the | |
13037 | * first active line. That means the scanline counter value is | |
13038 | * always one less than what we would expect. Ie. just after | |
13039 | * start of vblank, which also occurs at start of hsync (on the | |
13040 | * last active line), the scanline counter will read vblank_start-1. | |
13041 | * | |
13042 | * On gen2 the scanline counter starts counting from 1 instead | |
13043 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
13044 | * to keep the value positive), instead of adding one. | |
13045 | * | |
13046 | * On HSW+ the behaviour of the scanline counter depends on the output | |
13047 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
13048 | * there's an extra 1 line difference. So we need to add two instead of | |
13049 | * one to the value. | |
13050 | */ | |
13051 | if (IS_GEN2(dev)) { | |
124abe07 | 13052 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
13053 | int vtotal; |
13054 | ||
124abe07 VS |
13055 | vtotal = adjusted_mode->crtc_vtotal; |
13056 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
13057 | vtotal /= 2; |
13058 | ||
13059 | crtc->scanline_offset = vtotal - 1; | |
13060 | } else if (HAS_DDI(dev) && | |
409ee761 | 13061 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
13062 | crtc->scanline_offset = 2; |
13063 | } else | |
13064 | crtc->scanline_offset = 1; | |
13065 | } | |
13066 | ||
ad421372 | 13067 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 13068 | { |
225da59b | 13069 | struct drm_device *dev = state->dev; |
ed6739ef | 13070 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 13071 | struct intel_shared_dpll_config *shared_dpll = NULL; |
ed6739ef | 13072 | struct intel_crtc *intel_crtc; |
0a9ab303 ACO |
13073 | struct intel_crtc_state *intel_crtc_state; |
13074 | struct drm_crtc *crtc; | |
13075 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 13076 | int i; |
ed6739ef ACO |
13077 | |
13078 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 13079 | return; |
ed6739ef | 13080 | |
0a9ab303 | 13081 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
ad421372 ML |
13082 | int dpll; |
13083 | ||
0a9ab303 | 13084 | intel_crtc = to_intel_crtc(crtc); |
4978cc93 | 13085 | intel_crtc_state = to_intel_crtc_state(crtc_state); |
ad421372 | 13086 | dpll = intel_crtc_state->shared_dpll; |
0a9ab303 | 13087 | |
ad421372 | 13088 | if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE) |
225da59b ACO |
13089 | continue; |
13090 | ||
ad421372 | 13091 | intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE; |
0a9ab303 | 13092 | |
ad421372 ML |
13093 | if (!shared_dpll) |
13094 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 13095 | |
ad421372 ML |
13096 | shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe); |
13097 | } | |
ed6739ef ACO |
13098 | } |
13099 | ||
99d736a2 ML |
13100 | /* |
13101 | * This implements the workaround described in the "notes" section of the mode | |
13102 | * set sequence documentation. When going from no pipes or single pipe to | |
13103 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
13104 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
13105 | */ | |
13106 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
13107 | { | |
13108 | struct drm_crtc_state *crtc_state; | |
13109 | struct intel_crtc *intel_crtc; | |
13110 | struct drm_crtc *crtc; | |
13111 | struct intel_crtc_state *first_crtc_state = NULL; | |
13112 | struct intel_crtc_state *other_crtc_state = NULL; | |
13113 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
13114 | int i; | |
13115 | ||
13116 | /* look at all crtc's that are going to be enabled in during modeset */ | |
13117 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13118 | intel_crtc = to_intel_crtc(crtc); | |
13119 | ||
13120 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
13121 | continue; | |
13122 | ||
13123 | if (first_crtc_state) { | |
13124 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
13125 | break; | |
13126 | } else { | |
13127 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
13128 | first_pipe = intel_crtc->pipe; | |
13129 | } | |
13130 | } | |
13131 | ||
13132 | /* No workaround needed? */ | |
13133 | if (!first_crtc_state) | |
13134 | return 0; | |
13135 | ||
13136 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
13137 | for_each_intel_crtc(state->dev, intel_crtc) { | |
13138 | struct intel_crtc_state *pipe_config; | |
13139 | ||
13140 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
13141 | if (IS_ERR(pipe_config)) | |
13142 | return PTR_ERR(pipe_config); | |
13143 | ||
13144 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
13145 | ||
13146 | if (!pipe_config->base.active || | |
13147 | needs_modeset(&pipe_config->base)) | |
13148 | continue; | |
13149 | ||
13150 | /* 2 or more enabled crtcs means no need for w/a */ | |
13151 | if (enabled_pipe != INVALID_PIPE) | |
13152 | return 0; | |
13153 | ||
13154 | enabled_pipe = intel_crtc->pipe; | |
13155 | } | |
13156 | ||
13157 | if (enabled_pipe != INVALID_PIPE) | |
13158 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
13159 | else if (other_crtc_state) | |
13160 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
13161 | ||
13162 | return 0; | |
13163 | } | |
13164 | ||
27c329ed ML |
13165 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
13166 | { | |
13167 | struct drm_crtc *crtc; | |
13168 | struct drm_crtc_state *crtc_state; | |
13169 | int ret = 0; | |
13170 | ||
13171 | /* add all active pipes to the state */ | |
13172 | for_each_crtc(state->dev, crtc) { | |
13173 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13174 | if (IS_ERR(crtc_state)) | |
13175 | return PTR_ERR(crtc_state); | |
13176 | ||
13177 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
13178 | continue; | |
13179 | ||
13180 | crtc_state->mode_changed = true; | |
13181 | ||
13182 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
13183 | if (ret) | |
13184 | break; | |
13185 | ||
13186 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13187 | if (ret) | |
13188 | break; | |
13189 | } | |
13190 | ||
13191 | return ret; | |
13192 | } | |
13193 | ||
c347a676 | 13194 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd ACO |
13195 | { |
13196 | struct drm_device *dev = state->dev; | |
27c329ed | 13197 | struct drm_i915_private *dev_priv = dev->dev_private; |
054518dd ACO |
13198 | int ret; |
13199 | ||
b359283a ML |
13200 | if (!check_digital_port_conflicts(state)) { |
13201 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
13202 | return -EINVAL; | |
13203 | } | |
13204 | ||
054518dd ACO |
13205 | /* |
13206 | * See if the config requires any additional preparation, e.g. | |
13207 | * to adjust global state with pipes off. We need to do this | |
13208 | * here so we can get the modeset_pipe updated config for the new | |
13209 | * mode set on this crtc. For other crtcs we need to use the | |
13210 | * adjusted_mode bits in the crtc directly. | |
13211 | */ | |
27c329ed ML |
13212 | if (dev_priv->display.modeset_calc_cdclk) { |
13213 | unsigned int cdclk; | |
b432e5cf | 13214 | |
27c329ed ML |
13215 | ret = dev_priv->display.modeset_calc_cdclk(state); |
13216 | ||
13217 | cdclk = to_intel_atomic_state(state)->cdclk; | |
13218 | if (!ret && cdclk != dev_priv->cdclk_freq) | |
13219 | ret = intel_modeset_all_pipes(state); | |
13220 | ||
13221 | if (ret < 0) | |
054518dd | 13222 | return ret; |
27c329ed ML |
13223 | } else |
13224 | to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq; | |
054518dd | 13225 | |
ad421372 | 13226 | intel_modeset_clear_plls(state); |
054518dd | 13227 | |
99d736a2 | 13228 | if (IS_HASWELL(dev)) |
ad421372 | 13229 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 13230 | |
ad421372 | 13231 | return 0; |
c347a676 ACO |
13232 | } |
13233 | ||
aa363136 MR |
13234 | /* |
13235 | * Handle calculation of various watermark data at the end of the atomic check | |
13236 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
13237 | * handlers to ensure that all derived state has been updated. | |
13238 | */ | |
13239 | static void calc_watermark_data(struct drm_atomic_state *state) | |
13240 | { | |
13241 | struct drm_device *dev = state->dev; | |
13242 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
13243 | struct drm_crtc *crtc; | |
13244 | struct drm_crtc_state *cstate; | |
13245 | struct drm_plane *plane; | |
13246 | struct drm_plane_state *pstate; | |
13247 | ||
13248 | /* | |
13249 | * Calculate watermark configuration details now that derived | |
13250 | * plane/crtc state is all properly updated. | |
13251 | */ | |
13252 | drm_for_each_crtc(crtc, dev) { | |
13253 | cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?: | |
13254 | crtc->state; | |
13255 | ||
13256 | if (cstate->active) | |
13257 | intel_state->wm_config.num_pipes_active++; | |
13258 | } | |
13259 | drm_for_each_legacy_plane(plane, dev) { | |
13260 | pstate = drm_atomic_get_existing_plane_state(state, plane) ?: | |
13261 | plane->state; | |
13262 | ||
13263 | if (!to_intel_plane_state(pstate)->visible) | |
13264 | continue; | |
13265 | ||
13266 | intel_state->wm_config.sprites_enabled = true; | |
13267 | if (pstate->crtc_w != pstate->src_w >> 16 || | |
13268 | pstate->crtc_h != pstate->src_h >> 16) | |
13269 | intel_state->wm_config.sprites_scaled = true; | |
13270 | } | |
13271 | } | |
13272 | ||
74c090b1 ML |
13273 | /** |
13274 | * intel_atomic_check - validate state object | |
13275 | * @dev: drm device | |
13276 | * @state: state to validate | |
13277 | */ | |
13278 | static int intel_atomic_check(struct drm_device *dev, | |
13279 | struct drm_atomic_state *state) | |
c347a676 | 13280 | { |
aa363136 | 13281 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
13282 | struct drm_crtc *crtc; |
13283 | struct drm_crtc_state *crtc_state; | |
13284 | int ret, i; | |
61333b60 | 13285 | bool any_ms = false; |
c347a676 | 13286 | |
74c090b1 | 13287 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
13288 | if (ret) |
13289 | return ret; | |
13290 | ||
c347a676 | 13291 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
13292 | struct intel_crtc_state *pipe_config = |
13293 | to_intel_crtc_state(crtc_state); | |
1ed51de9 | 13294 | |
ba8af3e5 ML |
13295 | memset(&to_intel_crtc(crtc)->atomic, 0, |
13296 | sizeof(struct intel_crtc_atomic_commit)); | |
13297 | ||
1ed51de9 DV |
13298 | /* Catch I915_MODE_FLAG_INHERITED */ |
13299 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
13300 | crtc_state->mode_changed = true; | |
cfb23ed6 | 13301 | |
61333b60 ML |
13302 | if (!crtc_state->enable) { |
13303 | if (needs_modeset(crtc_state)) | |
13304 | any_ms = true; | |
c347a676 | 13305 | continue; |
61333b60 | 13306 | } |
c347a676 | 13307 | |
26495481 | 13308 | if (!needs_modeset(crtc_state)) |
cfb23ed6 ML |
13309 | continue; |
13310 | ||
26495481 DV |
13311 | /* FIXME: For only active_changed we shouldn't need to do any |
13312 | * state recomputation at all. */ | |
13313 | ||
1ed51de9 DV |
13314 | ret = drm_atomic_add_affected_connectors(state, crtc); |
13315 | if (ret) | |
13316 | return ret; | |
b359283a | 13317 | |
cfb23ed6 | 13318 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
c347a676 ACO |
13319 | if (ret) |
13320 | return ret; | |
13321 | ||
73831236 JN |
13322 | if (i915.fastboot && |
13323 | intel_pipe_config_compare(state->dev, | |
cfb23ed6 | 13324 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 13325 | pipe_config, true)) { |
26495481 | 13326 | crtc_state->mode_changed = false; |
bfd16b2a | 13327 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
13328 | } |
13329 | ||
13330 | if (needs_modeset(crtc_state)) { | |
13331 | any_ms = true; | |
cfb23ed6 ML |
13332 | |
13333 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13334 | if (ret) | |
13335 | return ret; | |
13336 | } | |
61333b60 | 13337 | |
26495481 DV |
13338 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
13339 | needs_modeset(crtc_state) ? | |
13340 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
13341 | } |
13342 | ||
61333b60 ML |
13343 | if (any_ms) { |
13344 | ret = intel_modeset_checks(state); | |
13345 | ||
13346 | if (ret) | |
13347 | return ret; | |
27c329ed | 13348 | } else |
aa363136 | 13349 | intel_state->cdclk = to_i915(state->dev)->cdclk_freq; |
76305b1a | 13350 | |
aa363136 MR |
13351 | ret = drm_atomic_helper_check_planes(state->dev, state); |
13352 | if (ret) | |
13353 | return ret; | |
13354 | ||
13355 | calc_watermark_data(state); | |
13356 | ||
13357 | return 0; | |
054518dd ACO |
13358 | } |
13359 | ||
5008e874 ML |
13360 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
13361 | struct drm_atomic_state *state, | |
13362 | bool async) | |
13363 | { | |
7580d774 ML |
13364 | struct drm_i915_private *dev_priv = dev->dev_private; |
13365 | struct drm_plane_state *plane_state; | |
5008e874 | 13366 | struct drm_crtc_state *crtc_state; |
7580d774 | 13367 | struct drm_plane *plane; |
5008e874 ML |
13368 | struct drm_crtc *crtc; |
13369 | int i, ret; | |
13370 | ||
13371 | if (async) { | |
13372 | DRM_DEBUG_KMS("i915 does not yet support async commit\n"); | |
13373 | return -EINVAL; | |
13374 | } | |
13375 | ||
13376 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13377 | ret = intel_crtc_wait_for_pending_flips(crtc); | |
13378 | if (ret) | |
13379 | return ret; | |
7580d774 ML |
13380 | |
13381 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) | |
13382 | flush_workqueue(dev_priv->wq); | |
5008e874 ML |
13383 | } |
13384 | ||
f935675f ML |
13385 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
13386 | if (ret) | |
13387 | return ret; | |
13388 | ||
5008e874 | 13389 | ret = drm_atomic_helper_prepare_planes(dev, state); |
7580d774 ML |
13390 | if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) { |
13391 | u32 reset_counter; | |
13392 | ||
13393 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); | |
13394 | mutex_unlock(&dev->struct_mutex); | |
13395 | ||
13396 | for_each_plane_in_state(state, plane, plane_state, i) { | |
13397 | struct intel_plane_state *intel_plane_state = | |
13398 | to_intel_plane_state(plane_state); | |
13399 | ||
13400 | if (!intel_plane_state->wait_req) | |
13401 | continue; | |
13402 | ||
13403 | ret = __i915_wait_request(intel_plane_state->wait_req, | |
13404 | reset_counter, true, | |
13405 | NULL, NULL); | |
13406 | ||
13407 | /* Swallow -EIO errors to allow updates during hw lockup. */ | |
13408 | if (ret == -EIO) | |
13409 | ret = 0; | |
13410 | ||
13411 | if (ret) | |
13412 | break; | |
13413 | } | |
13414 | ||
13415 | if (!ret) | |
13416 | return 0; | |
13417 | ||
13418 | mutex_lock(&dev->struct_mutex); | |
13419 | drm_atomic_helper_cleanup_planes(dev, state); | |
13420 | } | |
5008e874 | 13421 | |
f935675f | 13422 | mutex_unlock(&dev->struct_mutex); |
5008e874 ML |
13423 | return ret; |
13424 | } | |
13425 | ||
74c090b1 ML |
13426 | /** |
13427 | * intel_atomic_commit - commit validated state object | |
13428 | * @dev: DRM device | |
13429 | * @state: the top-level driver state object | |
13430 | * @async: asynchronous commit | |
13431 | * | |
13432 | * This function commits a top-level state object that has been validated | |
13433 | * with drm_atomic_helper_check(). | |
13434 | * | |
13435 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment | |
13436 | * we can only handle plane-related operations and do not yet support | |
13437 | * asynchronous commit. | |
13438 | * | |
13439 | * RETURNS | |
13440 | * Zero for success or -errno. | |
13441 | */ | |
13442 | static int intel_atomic_commit(struct drm_device *dev, | |
13443 | struct drm_atomic_state *state, | |
13444 | bool async) | |
a6778b3c | 13445 | { |
fbee40df | 13446 | struct drm_i915_private *dev_priv = dev->dev_private; |
0a9ab303 | 13447 | struct drm_crtc_state *crtc_state; |
7580d774 | 13448 | struct drm_crtc *crtc; |
c0c36b94 | 13449 | int ret = 0; |
0a9ab303 | 13450 | int i; |
61333b60 | 13451 | bool any_ms = false; |
a6778b3c | 13452 | |
5008e874 | 13453 | ret = intel_atomic_prepare_commit(dev, state, async); |
7580d774 ML |
13454 | if (ret) { |
13455 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
d4afb8cc | 13456 | return ret; |
7580d774 | 13457 | } |
d4afb8cc | 13458 | |
1c5e19f8 | 13459 | drm_atomic_helper_swap_state(dev, state); |
aa363136 | 13460 | dev_priv->wm.config = to_intel_atomic_state(state)->wm_config; |
1c5e19f8 | 13461 | |
0a9ab303 | 13462 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
a539205a ML |
13463 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13464 | ||
61333b60 ML |
13465 | if (!needs_modeset(crtc->state)) |
13466 | continue; | |
13467 | ||
13468 | any_ms = true; | |
a539205a | 13469 | intel_pre_plane_update(intel_crtc); |
460da916 | 13470 | |
a539205a ML |
13471 | if (crtc_state->active) { |
13472 | intel_crtc_disable_planes(crtc, crtc_state->plane_mask); | |
13473 | dev_priv->display.crtc_disable(crtc); | |
eddfcbcd ML |
13474 | intel_crtc->active = false; |
13475 | intel_disable_shared_dpll(intel_crtc); | |
9bbc8258 VS |
13476 | |
13477 | /* | |
13478 | * Underruns don't always raise | |
13479 | * interrupts, so check manually. | |
13480 | */ | |
13481 | intel_check_cpu_fifo_underruns(dev_priv); | |
13482 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 ML |
13483 | |
13484 | if (!crtc->state->active) | |
13485 | intel_update_watermarks(crtc); | |
a539205a | 13486 | } |
b8cecdf5 | 13487 | } |
7758a113 | 13488 | |
ea9d758d DV |
13489 | /* Only after disabling all output pipelines that will be changed can we |
13490 | * update the the output configuration. */ | |
4740b0f2 | 13491 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 13492 | |
4740b0f2 ML |
13493 | if (any_ms) { |
13494 | intel_shared_dpll_commit(state); | |
13495 | ||
13496 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); | |
61333b60 | 13497 | modeset_update_crtc_power_domains(state); |
4740b0f2 | 13498 | } |
47fab737 | 13499 | |
a6778b3c | 13500 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
0a9ab303 | 13501 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
f6ac4b2a ML |
13502 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13503 | bool modeset = needs_modeset(crtc->state); | |
bfd16b2a ML |
13504 | bool update_pipe = !modeset && |
13505 | to_intel_crtc_state(crtc->state)->update_pipe; | |
13506 | unsigned long put_domains = 0; | |
f6ac4b2a | 13507 | |
9f836f90 PJ |
13508 | if (modeset) |
13509 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); | |
13510 | ||
f6ac4b2a | 13511 | if (modeset && crtc->state->active) { |
a539205a ML |
13512 | update_scanline_offset(to_intel_crtc(crtc)); |
13513 | dev_priv->display.crtc_enable(crtc); | |
13514 | } | |
80715b2f | 13515 | |
bfd16b2a ML |
13516 | if (update_pipe) { |
13517 | put_domains = modeset_get_crtc_power_domains(crtc); | |
13518 | ||
13519 | /* make sure intel_modeset_check_state runs */ | |
13520 | any_ms = true; | |
13521 | } | |
13522 | ||
f6ac4b2a ML |
13523 | if (!modeset) |
13524 | intel_pre_plane_update(intel_crtc); | |
13525 | ||
6173ee28 ML |
13526 | if (crtc->state->active && |
13527 | (crtc->state->planes_changed || update_pipe)) | |
62852622 | 13528 | drm_atomic_helper_commit_planes_on_crtc(crtc_state); |
bfd16b2a ML |
13529 | |
13530 | if (put_domains) | |
13531 | modeset_put_power_domains(dev_priv, put_domains); | |
13532 | ||
f6ac4b2a | 13533 | intel_post_plane_update(intel_crtc); |
9f836f90 PJ |
13534 | |
13535 | if (modeset) | |
13536 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
80715b2f | 13537 | } |
a6778b3c | 13538 | |
a6778b3c | 13539 | /* FIXME: add subpixel order */ |
83a57153 | 13540 | |
74c090b1 | 13541 | drm_atomic_helper_wait_for_vblanks(dev, state); |
f935675f ML |
13542 | |
13543 | mutex_lock(&dev->struct_mutex); | |
d4afb8cc | 13544 | drm_atomic_helper_cleanup_planes(dev, state); |
f935675f | 13545 | mutex_unlock(&dev->struct_mutex); |
2bfb4627 | 13546 | |
74c090b1 | 13547 | if (any_ms) |
ee165b1a ML |
13548 | intel_modeset_check_state(dev, state); |
13549 | ||
13550 | drm_atomic_state_free(state); | |
f30da187 | 13551 | |
74c090b1 | 13552 | return 0; |
7f27126e JB |
13553 | } |
13554 | ||
c0c36b94 CW |
13555 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13556 | { | |
83a57153 ACO |
13557 | struct drm_device *dev = crtc->dev; |
13558 | struct drm_atomic_state *state; | |
e694eb02 | 13559 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 13560 | int ret; |
83a57153 ACO |
13561 | |
13562 | state = drm_atomic_state_alloc(dev); | |
13563 | if (!state) { | |
e694eb02 | 13564 | DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory", |
83a57153 ACO |
13565 | crtc->base.id); |
13566 | return; | |
13567 | } | |
13568 | ||
e694eb02 | 13569 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 13570 | |
e694eb02 ML |
13571 | retry: |
13572 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13573 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
13574 | if (!ret) { | |
13575 | if (!crtc_state->active) | |
13576 | goto out; | |
83a57153 | 13577 | |
e694eb02 | 13578 | crtc_state->mode_changed = true; |
74c090b1 | 13579 | ret = drm_atomic_commit(state); |
83a57153 ACO |
13580 | } |
13581 | ||
e694eb02 ML |
13582 | if (ret == -EDEADLK) { |
13583 | drm_atomic_state_clear(state); | |
13584 | drm_modeset_backoff(state->acquire_ctx); | |
13585 | goto retry; | |
4ed9fb37 | 13586 | } |
4be07317 | 13587 | |
2bfb4627 | 13588 | if (ret) |
e694eb02 | 13589 | out: |
2bfb4627 | 13590 | drm_atomic_state_free(state); |
c0c36b94 CW |
13591 | } |
13592 | ||
25c5b266 DV |
13593 | #undef for_each_intel_crtc_masked |
13594 | ||
f6e5b160 | 13595 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
f6e5b160 | 13596 | .gamma_set = intel_crtc_gamma_set, |
74c090b1 | 13597 | .set_config = drm_atomic_helper_set_config, |
f6e5b160 CW |
13598 | .destroy = intel_crtc_destroy, |
13599 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
13600 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13601 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
13602 | }; |
13603 | ||
5358901f DV |
13604 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
13605 | struct intel_shared_dpll *pll, | |
13606 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 13607 | { |
5358901f | 13608 | uint32_t val; |
ee7b9f93 | 13609 | |
f458ebbc | 13610 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
13611 | return false; |
13612 | ||
5358901f | 13613 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
13614 | hw_state->dpll = val; |
13615 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
13616 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
13617 | |
13618 | return val & DPLL_VCO_ENABLE; | |
13619 | } | |
13620 | ||
15bdd4cf DV |
13621 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
13622 | struct intel_shared_dpll *pll) | |
13623 | { | |
3e369b76 ACO |
13624 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
13625 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
13626 | } |
13627 | ||
e7b903d2 DV |
13628 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
13629 | struct intel_shared_dpll *pll) | |
13630 | { | |
e7b903d2 | 13631 | /* PCH refclock must be enabled first */ |
89eff4be | 13632 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 13633 | |
3e369b76 | 13634 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
13635 | |
13636 | /* Wait for the clocks to stabilize. */ | |
13637 | POSTING_READ(PCH_DPLL(pll->id)); | |
13638 | udelay(150); | |
13639 | ||
13640 | /* The pixel multiplier can only be updated once the | |
13641 | * DPLL is enabled and the clocks are stable. | |
13642 | * | |
13643 | * So write it again. | |
13644 | */ | |
3e369b76 | 13645 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 13646 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
13647 | udelay(200); |
13648 | } | |
13649 | ||
13650 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
13651 | struct intel_shared_dpll *pll) | |
13652 | { | |
13653 | struct drm_device *dev = dev_priv->dev; | |
13654 | struct intel_crtc *crtc; | |
e7b903d2 DV |
13655 | |
13656 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 13657 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
13658 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
13659 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
13660 | } |
13661 | ||
15bdd4cf DV |
13662 | I915_WRITE(PCH_DPLL(pll->id), 0); |
13663 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
13664 | udelay(200); |
13665 | } | |
13666 | ||
46edb027 DV |
13667 | static char *ibx_pch_dpll_names[] = { |
13668 | "PCH DPLL A", | |
13669 | "PCH DPLL B", | |
13670 | }; | |
13671 | ||
7c74ade1 | 13672 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 13673 | { |
e7b903d2 | 13674 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
13675 | int i; |
13676 | ||
7c74ade1 | 13677 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 13678 | |
e72f9fbf | 13679 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
13680 | dev_priv->shared_dplls[i].id = i; |
13681 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 13682 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
13683 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
13684 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
13685 | dev_priv->shared_dplls[i].get_hw_state = |
13686 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
13687 | } |
13688 | } | |
13689 | ||
7c74ade1 DV |
13690 | static void intel_shared_dpll_init(struct drm_device *dev) |
13691 | { | |
e7b903d2 | 13692 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 13693 | |
9cd86933 DV |
13694 | if (HAS_DDI(dev)) |
13695 | intel_ddi_pll_init(dev); | |
13696 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
13697 | ibx_pch_dpll_init(dev); |
13698 | else | |
13699 | dev_priv->num_shared_dpll = 0; | |
13700 | ||
13701 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
13702 | } |
13703 | ||
6beb8c23 MR |
13704 | /** |
13705 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13706 | * @plane: drm plane to prepare for | |
13707 | * @fb: framebuffer to prepare for presentation | |
13708 | * | |
13709 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13710 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13711 | * bits. Some older platforms need special physical address handling for | |
13712 | * cursor planes. | |
13713 | * | |
f935675f ML |
13714 | * Must be called with struct_mutex held. |
13715 | * | |
6beb8c23 MR |
13716 | * Returns 0 on success, negative error code on failure. |
13717 | */ | |
13718 | int | |
13719 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee | 13720 | const struct drm_plane_state *new_state) |
465c120c MR |
13721 | { |
13722 | struct drm_device *dev = plane->dev; | |
844f9111 | 13723 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 13724 | struct intel_plane *intel_plane = to_intel_plane(plane); |
6beb8c23 | 13725 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 13726 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
6beb8c23 | 13727 | int ret = 0; |
465c120c | 13728 | |
1ee49399 | 13729 | if (!obj && !old_obj) |
465c120c MR |
13730 | return 0; |
13731 | ||
5008e874 ML |
13732 | if (old_obj) { |
13733 | struct drm_crtc_state *crtc_state = | |
13734 | drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc); | |
13735 | ||
13736 | /* Big Hammer, we also need to ensure that any pending | |
13737 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
13738 | * current scanout is retired before unpinning the old | |
13739 | * framebuffer. Note that we rely on userspace rendering | |
13740 | * into the buffer attached to the pipe they are waiting | |
13741 | * on. If not, userspace generates a GPU hang with IPEHR | |
13742 | * point to the MI_WAIT_FOR_EVENT. | |
13743 | * | |
13744 | * This should only fail upon a hung GPU, in which case we | |
13745 | * can safely continue. | |
13746 | */ | |
13747 | if (needs_modeset(crtc_state)) | |
13748 | ret = i915_gem_object_wait_rendering(old_obj, true); | |
13749 | ||
13750 | /* Swallow -EIO errors to allow updates during hw lockup. */ | |
13751 | if (ret && ret != -EIO) | |
f935675f | 13752 | return ret; |
5008e874 ML |
13753 | } |
13754 | ||
3c28ff22 AG |
13755 | /* For framebuffer backed by dmabuf, wait for fence */ |
13756 | if (obj && obj->base.dma_buf) { | |
13757 | ret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
13758 | false, true, | |
13759 | MAX_SCHEDULE_TIMEOUT); | |
13760 | if (ret == -ERESTARTSYS) | |
13761 | return ret; | |
13762 | ||
13763 | WARN_ON(ret < 0); | |
13764 | } | |
13765 | ||
1ee49399 ML |
13766 | if (!obj) { |
13767 | ret = 0; | |
13768 | } else if (plane->type == DRM_PLANE_TYPE_CURSOR && | |
6beb8c23 MR |
13769 | INTEL_INFO(dev)->cursor_needs_physical) { |
13770 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
13771 | ret = i915_gem_object_attach_phys(obj, align); | |
13772 | if (ret) | |
13773 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13774 | } else { | |
7580d774 | 13775 | ret = intel_pin_and_fence_fb_obj(plane, fb, new_state); |
6beb8c23 | 13776 | } |
465c120c | 13777 | |
7580d774 ML |
13778 | if (ret == 0) { |
13779 | if (obj) { | |
13780 | struct intel_plane_state *plane_state = | |
13781 | to_intel_plane_state(new_state); | |
13782 | ||
13783 | i915_gem_request_assign(&plane_state->wait_req, | |
13784 | obj->last_write_req); | |
13785 | } | |
13786 | ||
a9ff8714 | 13787 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); |
7580d774 | 13788 | } |
fdd508a6 | 13789 | |
6beb8c23 MR |
13790 | return ret; |
13791 | } | |
13792 | ||
38f3ce3a MR |
13793 | /** |
13794 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13795 | * @plane: drm plane to clean up for | |
13796 | * @fb: old framebuffer that was on plane | |
13797 | * | |
13798 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
13799 | * |
13800 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
13801 | */ |
13802 | void | |
13803 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee | 13804 | const struct drm_plane_state *old_state) |
38f3ce3a MR |
13805 | { |
13806 | struct drm_device *dev = plane->dev; | |
1ee49399 | 13807 | struct intel_plane *intel_plane = to_intel_plane(plane); |
7580d774 | 13808 | struct intel_plane_state *old_intel_state; |
1ee49399 ML |
13809 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
13810 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); | |
38f3ce3a | 13811 | |
7580d774 ML |
13812 | old_intel_state = to_intel_plane_state(old_state); |
13813 | ||
1ee49399 | 13814 | if (!obj && !old_obj) |
38f3ce3a MR |
13815 | return; |
13816 | ||
1ee49399 ML |
13817 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
13818 | !INTEL_INFO(dev)->cursor_needs_physical)) | |
844f9111 | 13819 | intel_unpin_fb_obj(old_state->fb, old_state); |
1ee49399 ML |
13820 | |
13821 | /* prepare_fb aborted? */ | |
13822 | if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) || | |
13823 | (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit))) | |
13824 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); | |
7580d774 ML |
13825 | |
13826 | i915_gem_request_assign(&old_intel_state->wait_req, NULL); | |
13827 | ||
465c120c MR |
13828 | } |
13829 | ||
6156a456 CK |
13830 | int |
13831 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
13832 | { | |
13833 | int max_scale; | |
13834 | struct drm_device *dev; | |
13835 | struct drm_i915_private *dev_priv; | |
13836 | int crtc_clock, cdclk; | |
13837 | ||
13838 | if (!intel_crtc || !crtc_state) | |
13839 | return DRM_PLANE_HELPER_NO_SCALING; | |
13840 | ||
13841 | dev = intel_crtc->base.dev; | |
13842 | dev_priv = dev->dev_private; | |
13843 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; | |
27c329ed | 13844 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 | 13845 | |
54bf1ce6 | 13846 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
6156a456 CK |
13847 | return DRM_PLANE_HELPER_NO_SCALING; |
13848 | ||
13849 | /* | |
13850 | * skl max scale is lower of: | |
13851 | * close to 3 but not 3, -1 is for that purpose | |
13852 | * or | |
13853 | * cdclk/crtc_clock | |
13854 | */ | |
13855 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
13856 | ||
13857 | return max_scale; | |
13858 | } | |
13859 | ||
465c120c | 13860 | static int |
3c692a41 | 13861 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 13862 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
13863 | struct intel_plane_state *state) |
13864 | { | |
2b875c22 MR |
13865 | struct drm_crtc *crtc = state->base.crtc; |
13866 | struct drm_framebuffer *fb = state->base.fb; | |
6156a456 | 13867 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
13868 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
13869 | bool can_position = false; | |
465c120c | 13870 | |
061e4b8d ML |
13871 | /* use scaler when colorkey is not required */ |
13872 | if (INTEL_INFO(plane->dev)->gen >= 9 && | |
818ed961 | 13873 | state->ckey.flags == I915_SET_COLORKEY_NONE) { |
061e4b8d ML |
13874 | min_scale = 1; |
13875 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
d8106366 | 13876 | can_position = true; |
6156a456 | 13877 | } |
d8106366 | 13878 | |
061e4b8d ML |
13879 | return drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
13880 | &state->dst, &state->clip, | |
da20eabd ML |
13881 | min_scale, max_scale, |
13882 | can_position, true, | |
13883 | &state->visible); | |
14af293f GP |
13884 | } |
13885 | ||
13886 | static void | |
13887 | intel_commit_primary_plane(struct drm_plane *plane, | |
13888 | struct intel_plane_state *state) | |
13889 | { | |
2b875c22 MR |
13890 | struct drm_crtc *crtc = state->base.crtc; |
13891 | struct drm_framebuffer *fb = state->base.fb; | |
13892 | struct drm_device *dev = plane->dev; | |
14af293f | 13893 | struct drm_i915_private *dev_priv = dev->dev_private; |
14af293f | 13894 | |
ea2c67bb | 13895 | crtc = crtc ? crtc : plane->crtc; |
ccc759dc | 13896 | |
d4b08630 ML |
13897 | dev_priv->display.update_primary_plane(crtc, fb, |
13898 | state->src.x1 >> 16, | |
13899 | state->src.y1 >> 16); | |
465c120c MR |
13900 | } |
13901 | ||
a8ad0d8e ML |
13902 | static void |
13903 | intel_disable_primary_plane(struct drm_plane *plane, | |
7fabf5ef | 13904 | struct drm_crtc *crtc) |
a8ad0d8e ML |
13905 | { |
13906 | struct drm_device *dev = plane->dev; | |
13907 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13908 | ||
a8ad0d8e ML |
13909 | dev_priv->display.update_primary_plane(crtc, NULL, 0, 0); |
13910 | } | |
13911 | ||
613d2b27 ML |
13912 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
13913 | struct drm_crtc_state *old_crtc_state) | |
3c692a41 | 13914 | { |
32b7eeec | 13915 | struct drm_device *dev = crtc->dev; |
3c692a41 | 13916 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
bfd16b2a ML |
13917 | struct intel_crtc_state *old_intel_state = |
13918 | to_intel_crtc_state(old_crtc_state); | |
13919 | bool modeset = needs_modeset(crtc->state); | |
3c692a41 | 13920 | |
c34c9ee4 | 13921 | /* Perform vblank evasion around commit operation */ |
62852622 | 13922 | intel_pipe_update_start(intel_crtc); |
0583236e | 13923 | |
bfd16b2a ML |
13924 | if (modeset) |
13925 | return; | |
13926 | ||
13927 | if (to_intel_crtc_state(crtc->state)->update_pipe) | |
13928 | intel_update_pipe_config(intel_crtc, old_intel_state); | |
13929 | else if (INTEL_INFO(dev)->gen >= 9) | |
0583236e | 13930 | skl_detach_scalers(intel_crtc); |
32b7eeec MR |
13931 | } |
13932 | ||
613d2b27 ML |
13933 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, |
13934 | struct drm_crtc_state *old_crtc_state) | |
32b7eeec | 13935 | { |
32b7eeec | 13936 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
32b7eeec | 13937 | |
62852622 | 13938 | intel_pipe_update_end(intel_crtc); |
3c692a41 GP |
13939 | } |
13940 | ||
cf4c7c12 | 13941 | /** |
4a3b8769 MR |
13942 | * intel_plane_destroy - destroy a plane |
13943 | * @plane: plane to destroy | |
cf4c7c12 | 13944 | * |
4a3b8769 MR |
13945 | * Common destruction function for all types of planes (primary, cursor, |
13946 | * sprite). | |
cf4c7c12 | 13947 | */ |
4a3b8769 | 13948 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
13949 | { |
13950 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13951 | drm_plane_cleanup(plane); | |
13952 | kfree(intel_plane); | |
13953 | } | |
13954 | ||
65a3fea0 | 13955 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
13956 | .update_plane = drm_atomic_helper_update_plane, |
13957 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 13958 | .destroy = intel_plane_destroy, |
c196e1d6 | 13959 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
13960 | .atomic_get_property = intel_plane_atomic_get_property, |
13961 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
13962 | .atomic_duplicate_state = intel_plane_duplicate_state, |
13963 | .atomic_destroy_state = intel_plane_destroy_state, | |
13964 | ||
465c120c MR |
13965 | }; |
13966 | ||
13967 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
13968 | int pipe) | |
13969 | { | |
13970 | struct intel_plane *primary; | |
8e7d688b | 13971 | struct intel_plane_state *state; |
465c120c | 13972 | const uint32_t *intel_primary_formats; |
45e3743a | 13973 | unsigned int num_formats; |
465c120c MR |
13974 | |
13975 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
13976 | if (primary == NULL) | |
13977 | return NULL; | |
13978 | ||
8e7d688b MR |
13979 | state = intel_create_plane_state(&primary->base); |
13980 | if (!state) { | |
ea2c67bb MR |
13981 | kfree(primary); |
13982 | return NULL; | |
13983 | } | |
8e7d688b | 13984 | primary->base.state = &state->base; |
ea2c67bb | 13985 | |
465c120c MR |
13986 | primary->can_scale = false; |
13987 | primary->max_downscale = 1; | |
6156a456 CK |
13988 | if (INTEL_INFO(dev)->gen >= 9) { |
13989 | primary->can_scale = true; | |
af99ceda | 13990 | state->scaler_id = -1; |
6156a456 | 13991 | } |
465c120c MR |
13992 | primary->pipe = pipe; |
13993 | primary->plane = pipe; | |
a9ff8714 | 13994 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 MR |
13995 | primary->check_plane = intel_check_primary_plane; |
13996 | primary->commit_plane = intel_commit_primary_plane; | |
a8ad0d8e | 13997 | primary->disable_plane = intel_disable_primary_plane; |
465c120c MR |
13998 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
13999 | primary->plane = !pipe; | |
14000 | ||
6c0fd451 DL |
14001 | if (INTEL_INFO(dev)->gen >= 9) { |
14002 | intel_primary_formats = skl_primary_formats; | |
14003 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
14004 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
568db4f2 DL |
14005 | intel_primary_formats = i965_primary_formats; |
14006 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
6c0fd451 DL |
14007 | } else { |
14008 | intel_primary_formats = i8xx_primary_formats; | |
14009 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
465c120c MR |
14010 | } |
14011 | ||
14012 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 14013 | &intel_plane_funcs, |
465c120c MR |
14014 | intel_primary_formats, num_formats, |
14015 | DRM_PLANE_TYPE_PRIMARY); | |
48404c1e | 14016 | |
3b7a5119 SJ |
14017 | if (INTEL_INFO(dev)->gen >= 4) |
14018 | intel_create_rotation_property(dev, primary); | |
48404c1e | 14019 | |
ea2c67bb MR |
14020 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
14021 | ||
465c120c MR |
14022 | return &primary->base; |
14023 | } | |
14024 | ||
3b7a5119 SJ |
14025 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
14026 | { | |
14027 | if (!dev->mode_config.rotation_property) { | |
14028 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
14029 | BIT(DRM_ROTATE_180); | |
14030 | ||
14031 | if (INTEL_INFO(dev)->gen >= 9) | |
14032 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
14033 | ||
14034 | dev->mode_config.rotation_property = | |
14035 | drm_mode_create_rotation_property(dev, flags); | |
14036 | } | |
14037 | if (dev->mode_config.rotation_property) | |
14038 | drm_object_attach_property(&plane->base.base, | |
14039 | dev->mode_config.rotation_property, | |
14040 | plane->base.state->rotation); | |
14041 | } | |
14042 | ||
3d7d6510 | 14043 | static int |
852e787c | 14044 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 14045 | struct intel_crtc_state *crtc_state, |
852e787c | 14046 | struct intel_plane_state *state) |
3d7d6510 | 14047 | { |
061e4b8d | 14048 | struct drm_crtc *crtc = crtc_state->base.crtc; |
2b875c22 | 14049 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 14050 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
757f9a3e GP |
14051 | unsigned stride; |
14052 | int ret; | |
3d7d6510 | 14053 | |
061e4b8d ML |
14054 | ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
14055 | &state->dst, &state->clip, | |
3d7d6510 MR |
14056 | DRM_PLANE_HELPER_NO_SCALING, |
14057 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 14058 | true, true, &state->visible); |
757f9a3e GP |
14059 | if (ret) |
14060 | return ret; | |
14061 | ||
757f9a3e GP |
14062 | /* if we want to turn off the cursor ignore width and height */ |
14063 | if (!obj) | |
da20eabd | 14064 | return 0; |
757f9a3e | 14065 | |
757f9a3e | 14066 | /* Check for which cursor types we support */ |
061e4b8d | 14067 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
ea2c67bb MR |
14068 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
14069 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
14070 | return -EINVAL; |
14071 | } | |
14072 | ||
ea2c67bb MR |
14073 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
14074 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
14075 | DRM_DEBUG_KMS("buffer is too small\n"); |
14076 | return -ENOMEM; | |
14077 | } | |
14078 | ||
3a656b54 | 14079 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 14080 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 14081 | return -EINVAL; |
32b7eeec MR |
14082 | } |
14083 | ||
da20eabd | 14084 | return 0; |
852e787c | 14085 | } |
3d7d6510 | 14086 | |
a8ad0d8e ML |
14087 | static void |
14088 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 14089 | struct drm_crtc *crtc) |
a8ad0d8e | 14090 | { |
a8ad0d8e ML |
14091 | intel_crtc_update_cursor(crtc, false); |
14092 | } | |
14093 | ||
f4a2cf29 | 14094 | static void |
852e787c GP |
14095 | intel_commit_cursor_plane(struct drm_plane *plane, |
14096 | struct intel_plane_state *state) | |
14097 | { | |
2b875c22 | 14098 | struct drm_crtc *crtc = state->base.crtc; |
ea2c67bb MR |
14099 | struct drm_device *dev = plane->dev; |
14100 | struct intel_crtc *intel_crtc; | |
2b875c22 | 14101 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 14102 | uint32_t addr; |
852e787c | 14103 | |
ea2c67bb MR |
14104 | crtc = crtc ? crtc : plane->crtc; |
14105 | intel_crtc = to_intel_crtc(crtc); | |
14106 | ||
a912f12f GP |
14107 | if (intel_crtc->cursor_bo == obj) |
14108 | goto update; | |
4ed91096 | 14109 | |
f4a2cf29 | 14110 | if (!obj) |
a912f12f | 14111 | addr = 0; |
f4a2cf29 | 14112 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 14113 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 14114 | else |
a912f12f | 14115 | addr = obj->phys_handle->busaddr; |
852e787c | 14116 | |
a912f12f GP |
14117 | intel_crtc->cursor_addr = addr; |
14118 | intel_crtc->cursor_bo = obj; | |
852e787c | 14119 | |
302d19ac | 14120 | update: |
62852622 | 14121 | intel_crtc_update_cursor(crtc, state->visible); |
852e787c GP |
14122 | } |
14123 | ||
3d7d6510 MR |
14124 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
14125 | int pipe) | |
14126 | { | |
14127 | struct intel_plane *cursor; | |
8e7d688b | 14128 | struct intel_plane_state *state; |
3d7d6510 MR |
14129 | |
14130 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
14131 | if (cursor == NULL) | |
14132 | return NULL; | |
14133 | ||
8e7d688b MR |
14134 | state = intel_create_plane_state(&cursor->base); |
14135 | if (!state) { | |
ea2c67bb MR |
14136 | kfree(cursor); |
14137 | return NULL; | |
14138 | } | |
8e7d688b | 14139 | cursor->base.state = &state->base; |
ea2c67bb | 14140 | |
3d7d6510 MR |
14141 | cursor->can_scale = false; |
14142 | cursor->max_downscale = 1; | |
14143 | cursor->pipe = pipe; | |
14144 | cursor->plane = pipe; | |
a9ff8714 | 14145 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 MR |
14146 | cursor->check_plane = intel_check_cursor_plane; |
14147 | cursor->commit_plane = intel_commit_cursor_plane; | |
a8ad0d8e | 14148 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 MR |
14149 | |
14150 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 14151 | &intel_plane_funcs, |
3d7d6510 MR |
14152 | intel_cursor_formats, |
14153 | ARRAY_SIZE(intel_cursor_formats), | |
14154 | DRM_PLANE_TYPE_CURSOR); | |
4398ad45 VS |
14155 | |
14156 | if (INTEL_INFO(dev)->gen >= 4) { | |
14157 | if (!dev->mode_config.rotation_property) | |
14158 | dev->mode_config.rotation_property = | |
14159 | drm_mode_create_rotation_property(dev, | |
14160 | BIT(DRM_ROTATE_0) | | |
14161 | BIT(DRM_ROTATE_180)); | |
14162 | if (dev->mode_config.rotation_property) | |
14163 | drm_object_attach_property(&cursor->base.base, | |
14164 | dev->mode_config.rotation_property, | |
8e7d688b | 14165 | state->base.rotation); |
4398ad45 VS |
14166 | } |
14167 | ||
af99ceda CK |
14168 | if (INTEL_INFO(dev)->gen >=9) |
14169 | state->scaler_id = -1; | |
14170 | ||
ea2c67bb MR |
14171 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
14172 | ||
3d7d6510 MR |
14173 | return &cursor->base; |
14174 | } | |
14175 | ||
549e2bfb CK |
14176 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
14177 | struct intel_crtc_state *crtc_state) | |
14178 | { | |
14179 | int i; | |
14180 | struct intel_scaler *intel_scaler; | |
14181 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
14182 | ||
14183 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
14184 | intel_scaler = &scaler_state->scalers[i]; | |
14185 | intel_scaler->in_use = 0; | |
549e2bfb CK |
14186 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
14187 | } | |
14188 | ||
14189 | scaler_state->scaler_id = -1; | |
14190 | } | |
14191 | ||
b358d0a6 | 14192 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 14193 | { |
fbee40df | 14194 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 14195 | struct intel_crtc *intel_crtc; |
f5de6e07 | 14196 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
14197 | struct drm_plane *primary = NULL; |
14198 | struct drm_plane *cursor = NULL; | |
465c120c | 14199 | int i, ret; |
79e53945 | 14200 | |
955382f3 | 14201 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
14202 | if (intel_crtc == NULL) |
14203 | return; | |
14204 | ||
f5de6e07 ACO |
14205 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
14206 | if (!crtc_state) | |
14207 | goto fail; | |
550acefd ACO |
14208 | intel_crtc->config = crtc_state; |
14209 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 14210 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 14211 | |
549e2bfb CK |
14212 | /* initialize shared scalers */ |
14213 | if (INTEL_INFO(dev)->gen >= 9) { | |
14214 | if (pipe == PIPE_C) | |
14215 | intel_crtc->num_scalers = 1; | |
14216 | else | |
14217 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
14218 | ||
14219 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
14220 | } | |
14221 | ||
465c120c | 14222 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
14223 | if (!primary) |
14224 | goto fail; | |
14225 | ||
14226 | cursor = intel_cursor_plane_create(dev, pipe); | |
14227 | if (!cursor) | |
14228 | goto fail; | |
14229 | ||
465c120c | 14230 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
14231 | cursor, &intel_crtc_funcs); |
14232 | if (ret) | |
14233 | goto fail; | |
79e53945 JB |
14234 | |
14235 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
14236 | for (i = 0; i < 256; i++) { |
14237 | intel_crtc->lut_r[i] = i; | |
14238 | intel_crtc->lut_g[i] = i; | |
14239 | intel_crtc->lut_b[i] = i; | |
14240 | } | |
14241 | ||
1f1c2e24 VS |
14242 | /* |
14243 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 14244 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 14245 | */ |
80824003 JB |
14246 | intel_crtc->pipe = pipe; |
14247 | intel_crtc->plane = pipe; | |
3a77c4c4 | 14248 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 14249 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 14250 | intel_crtc->plane = !pipe; |
80824003 JB |
14251 | } |
14252 | ||
4b0e333e CW |
14253 | intel_crtc->cursor_base = ~0; |
14254 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 14255 | intel_crtc->cursor_size = ~0; |
8d7849db | 14256 | |
852eb00d VS |
14257 | intel_crtc->wm.cxsr_allowed = true; |
14258 | ||
22fd0fab JB |
14259 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
14260 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
14261 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
14262 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
14263 | ||
79e53945 | 14264 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
14265 | |
14266 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
14267 | return; |
14268 | ||
14269 | fail: | |
14270 | if (primary) | |
14271 | drm_plane_cleanup(primary); | |
14272 | if (cursor) | |
14273 | drm_plane_cleanup(cursor); | |
f5de6e07 | 14274 | kfree(crtc_state); |
3d7d6510 | 14275 | kfree(intel_crtc); |
79e53945 JB |
14276 | } |
14277 | ||
752aa88a JB |
14278 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
14279 | { | |
14280 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 14281 | struct drm_device *dev = connector->base.dev; |
752aa88a | 14282 | |
51fd371b | 14283 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 14284 | |
d3babd3f | 14285 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
14286 | return INVALID_PIPE; |
14287 | ||
14288 | return to_intel_crtc(encoder->crtc)->pipe; | |
14289 | } | |
14290 | ||
08d7b3d1 | 14291 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 14292 | struct drm_file *file) |
08d7b3d1 | 14293 | { |
08d7b3d1 | 14294 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 14295 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 14296 | struct intel_crtc *crtc; |
08d7b3d1 | 14297 | |
7707e653 | 14298 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 14299 | |
7707e653 | 14300 | if (!drmmode_crtc) { |
08d7b3d1 | 14301 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 14302 | return -ENOENT; |
08d7b3d1 CW |
14303 | } |
14304 | ||
7707e653 | 14305 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 14306 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 14307 | |
c05422d5 | 14308 | return 0; |
08d7b3d1 CW |
14309 | } |
14310 | ||
66a9278e | 14311 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 14312 | { |
66a9278e DV |
14313 | struct drm_device *dev = encoder->base.dev; |
14314 | struct intel_encoder *source_encoder; | |
79e53945 | 14315 | int index_mask = 0; |
79e53945 JB |
14316 | int entry = 0; |
14317 | ||
b2784e15 | 14318 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 14319 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
14320 | index_mask |= (1 << entry); |
14321 | ||
79e53945 JB |
14322 | entry++; |
14323 | } | |
4ef69c7a | 14324 | |
79e53945 JB |
14325 | return index_mask; |
14326 | } | |
14327 | ||
4d302442 CW |
14328 | static bool has_edp_a(struct drm_device *dev) |
14329 | { | |
14330 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14331 | ||
14332 | if (!IS_MOBILE(dev)) | |
14333 | return false; | |
14334 | ||
14335 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
14336 | return false; | |
14337 | ||
e3589908 | 14338 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
14339 | return false; |
14340 | ||
14341 | return true; | |
14342 | } | |
14343 | ||
84b4e042 JB |
14344 | static bool intel_crt_present(struct drm_device *dev) |
14345 | { | |
14346 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14347 | ||
884497ed DL |
14348 | if (INTEL_INFO(dev)->gen >= 9) |
14349 | return false; | |
14350 | ||
cf404ce4 | 14351 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
14352 | return false; |
14353 | ||
14354 | if (IS_CHERRYVIEW(dev)) | |
14355 | return false; | |
14356 | ||
65e472e4 VS |
14357 | if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) |
14358 | return false; | |
14359 | ||
70ac54d0 VS |
14360 | /* DDI E can't be used if DDI A requires 4 lanes */ |
14361 | if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) | |
14362 | return false; | |
14363 | ||
e4abb733 | 14364 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
14365 | return false; |
14366 | ||
14367 | return true; | |
14368 | } | |
14369 | ||
79e53945 JB |
14370 | static void intel_setup_outputs(struct drm_device *dev) |
14371 | { | |
725e30ad | 14372 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 14373 | struct intel_encoder *encoder; |
cb0953d7 | 14374 | bool dpd_is_edp = false; |
79e53945 | 14375 | |
c9093354 | 14376 | intel_lvds_init(dev); |
79e53945 | 14377 | |
84b4e042 | 14378 | if (intel_crt_present(dev)) |
79935fca | 14379 | intel_crt_init(dev); |
cb0953d7 | 14380 | |
c776eb2e VK |
14381 | if (IS_BROXTON(dev)) { |
14382 | /* | |
14383 | * FIXME: Broxton doesn't support port detection via the | |
14384 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14385 | * detect the ports. | |
14386 | */ | |
14387 | intel_ddi_init(dev, PORT_A); | |
14388 | intel_ddi_init(dev, PORT_B); | |
14389 | intel_ddi_init(dev, PORT_C); | |
14390 | } else if (HAS_DDI(dev)) { | |
0e72a5b5 ED |
14391 | int found; |
14392 | ||
de31facd JB |
14393 | /* |
14394 | * Haswell uses DDI functions to detect digital outputs. | |
14395 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14396 | * it's there. | |
14397 | */ | |
77179400 | 14398 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 14399 | /* WaIgnoreDDIAStrap: skl */ |
ef11bdb3 | 14400 | if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
0e72a5b5 ED |
14401 | intel_ddi_init(dev, PORT_A); |
14402 | ||
14403 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14404 | * register */ | |
14405 | found = I915_READ(SFUSE_STRAP); | |
14406 | ||
14407 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
14408 | intel_ddi_init(dev, PORT_B); | |
14409 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
14410 | intel_ddi_init(dev, PORT_C); | |
14411 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
14412 | intel_ddi_init(dev, PORT_D); | |
2800e4c2 RV |
14413 | /* |
14414 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
14415 | */ | |
ef11bdb3 | 14416 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && |
2800e4c2 RV |
14417 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
14418 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
14419 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
14420 | intel_ddi_init(dev, PORT_E); | |
14421 | ||
0e72a5b5 | 14422 | } else if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 14423 | int found; |
5d8a7752 | 14424 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
14425 | |
14426 | if (has_edp_a(dev)) | |
14427 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 14428 | |
dc0fa718 | 14429 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14430 | /* PCH SDVOB multiplex with HDMIB */ |
2a5c0832 | 14431 | found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); |
30ad48b7 | 14432 | if (!found) |
e2debe91 | 14433 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 14434 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 14435 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14436 | } |
14437 | ||
dc0fa718 | 14438 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 14439 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 14440 | |
dc0fa718 | 14441 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 14442 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 14443 | |
5eb08b69 | 14444 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 14445 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 14446 | |
270b3042 | 14447 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 14448 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
666a4537 | 14449 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
e17ac6db VS |
14450 | /* |
14451 | * The DP_DETECTED bit is the latched state of the DDC | |
14452 | * SDA pin at boot. However since eDP doesn't require DDC | |
14453 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14454 | * eDP ports may have been muxed to an alternate function. | |
14455 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14456 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14457 | * detect eDP ports. | |
14458 | */ | |
e66eb81d | 14459 | if (I915_READ(VLV_HDMIB) & SDVO_DETECTED && |
d2182a66 | 14460 | !intel_dp_is_edp(dev, PORT_B)) |
e66eb81d VS |
14461 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
14462 | if (I915_READ(VLV_DP_B) & DP_DETECTED || | |
e17ac6db | 14463 | intel_dp_is_edp(dev, PORT_B)) |
e66eb81d | 14464 | intel_dp_init(dev, VLV_DP_B, PORT_B); |
585a94b8 | 14465 | |
e66eb81d | 14466 | if (I915_READ(VLV_HDMIC) & SDVO_DETECTED && |
d2182a66 | 14467 | !intel_dp_is_edp(dev, PORT_C)) |
e66eb81d VS |
14468 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
14469 | if (I915_READ(VLV_DP_C) & DP_DETECTED || | |
e17ac6db | 14470 | intel_dp_is_edp(dev, PORT_C)) |
e66eb81d | 14471 | intel_dp_init(dev, VLV_DP_C, PORT_C); |
19c03924 | 14472 | |
9418c1f1 | 14473 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 14474 | /* eDP not supported on port D, so don't check VBT */ |
e66eb81d VS |
14475 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED) |
14476 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); | |
14477 | if (I915_READ(CHV_DP_D) & DP_DETECTED) | |
14478 | intel_dp_init(dev, CHV_DP_D, PORT_D); | |
9418c1f1 VS |
14479 | } |
14480 | ||
3cfca973 | 14481 | intel_dsi_init(dev); |
09da55dc | 14482 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
27185ae1 | 14483 | bool found = false; |
7d57382e | 14484 | |
e2debe91 | 14485 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14486 | DRM_DEBUG_KMS("probing SDVOB\n"); |
2a5c0832 | 14487 | found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B); |
3fec3d2f | 14488 | if (!found && IS_G4X(dev)) { |
b01f2c3a | 14489 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
e2debe91 | 14490 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14491 | } |
27185ae1 | 14492 | |
3fec3d2f | 14493 | if (!found && IS_G4X(dev)) |
ab9d7c30 | 14494 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 14495 | } |
13520b05 KH |
14496 | |
14497 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14498 | |
e2debe91 | 14499 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14500 | DRM_DEBUG_KMS("probing SDVOC\n"); |
2a5c0832 | 14501 | found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); |
b01f2c3a | 14502 | } |
27185ae1 | 14503 | |
e2debe91 | 14504 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14505 | |
3fec3d2f | 14506 | if (IS_G4X(dev)) { |
b01f2c3a | 14507 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
e2debe91 | 14508 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14509 | } |
3fec3d2f | 14510 | if (IS_G4X(dev)) |
ab9d7c30 | 14511 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 14512 | } |
27185ae1 | 14513 | |
3fec3d2f | 14514 | if (IS_G4X(dev) && |
e7281eab | 14515 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 14516 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 14517 | } else if (IS_GEN2(dev)) |
79e53945 JB |
14518 | intel_dvo_init(dev); |
14519 | ||
103a196f | 14520 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
14521 | intel_tv_init(dev); |
14522 | ||
0bc12bcb | 14523 | intel_psr_init(dev); |
7c8f8a70 | 14524 | |
b2784e15 | 14525 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
14526 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14527 | encoder->base.possible_clones = | |
66a9278e | 14528 | intel_encoder_clones(encoder); |
79e53945 | 14529 | } |
47356eb6 | 14530 | |
dde86e2d | 14531 | intel_init_pch_refclk(dev); |
270b3042 DV |
14532 | |
14533 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
14534 | } |
14535 | ||
14536 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14537 | { | |
60a5ca01 | 14538 | struct drm_device *dev = fb->dev; |
79e53945 | 14539 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 14540 | |
ef2d633e | 14541 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 14542 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 14543 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
14544 | drm_gem_object_unreference(&intel_fb->obj->base); |
14545 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14546 | kfree(intel_fb); |
14547 | } | |
14548 | ||
14549 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14550 | struct drm_file *file, |
79e53945 JB |
14551 | unsigned int *handle) |
14552 | { | |
14553 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14554 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14555 | |
cc917ab4 CW |
14556 | if (obj->userptr.mm) { |
14557 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
14558 | return -EINVAL; | |
14559 | } | |
14560 | ||
05394f39 | 14561 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14562 | } |
14563 | ||
86c98588 RV |
14564 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
14565 | struct drm_file *file, | |
14566 | unsigned flags, unsigned color, | |
14567 | struct drm_clip_rect *clips, | |
14568 | unsigned num_clips) | |
14569 | { | |
14570 | struct drm_device *dev = fb->dev; | |
14571 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
14572 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
14573 | ||
14574 | mutex_lock(&dev->struct_mutex); | |
74b4ea1e | 14575 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
14576 | mutex_unlock(&dev->struct_mutex); |
14577 | ||
14578 | return 0; | |
14579 | } | |
14580 | ||
79e53945 JB |
14581 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
14582 | .destroy = intel_user_framebuffer_destroy, | |
14583 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 14584 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
14585 | }; |
14586 | ||
b321803d DL |
14587 | static |
14588 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
14589 | uint32_t pixel_format) | |
14590 | { | |
14591 | u32 gen = INTEL_INFO(dev)->gen; | |
14592 | ||
14593 | if (gen >= 9) { | |
14594 | /* "The stride in bytes must not exceed the of the size of 8K | |
14595 | * pixels and 32K bytes." | |
14596 | */ | |
14597 | return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768); | |
666a4537 | 14598 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
b321803d DL |
14599 | return 32*1024; |
14600 | } else if (gen >= 4) { | |
14601 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14602 | return 16*1024; | |
14603 | else | |
14604 | return 32*1024; | |
14605 | } else if (gen >= 3) { | |
14606 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14607 | return 8*1024; | |
14608 | else | |
14609 | return 16*1024; | |
14610 | } else { | |
14611 | /* XXX DSPC is limited to 4k tiled */ | |
14612 | return 8*1024; | |
14613 | } | |
14614 | } | |
14615 | ||
b5ea642a DV |
14616 | static int intel_framebuffer_init(struct drm_device *dev, |
14617 | struct intel_framebuffer *intel_fb, | |
14618 | struct drm_mode_fb_cmd2 *mode_cmd, | |
14619 | struct drm_i915_gem_object *obj) | |
79e53945 | 14620 | { |
6761dd31 | 14621 | unsigned int aligned_height; |
79e53945 | 14622 | int ret; |
b321803d | 14623 | u32 pitch_limit, stride_alignment; |
79e53945 | 14624 | |
dd4916c5 DV |
14625 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
14626 | ||
2a80eada DV |
14627 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
14628 | /* Enforce that fb modifier and tiling mode match, but only for | |
14629 | * X-tiled. This is needed for FBC. */ | |
14630 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
14631 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
14632 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
14633 | return -EINVAL; | |
14634 | } | |
14635 | } else { | |
14636 | if (obj->tiling_mode == I915_TILING_X) | |
14637 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
14638 | else if (obj->tiling_mode == I915_TILING_Y) { | |
14639 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
14640 | return -EINVAL; | |
14641 | } | |
14642 | } | |
14643 | ||
9a8f0a12 TU |
14644 | /* Passed in modifier sanity checking. */ |
14645 | switch (mode_cmd->modifier[0]) { | |
14646 | case I915_FORMAT_MOD_Y_TILED: | |
14647 | case I915_FORMAT_MOD_Yf_TILED: | |
14648 | if (INTEL_INFO(dev)->gen < 9) { | |
14649 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
14650 | mode_cmd->modifier[0]); | |
14651 | return -EINVAL; | |
14652 | } | |
14653 | case DRM_FORMAT_MOD_NONE: | |
14654 | case I915_FORMAT_MOD_X_TILED: | |
14655 | break; | |
14656 | default: | |
c0f40428 JB |
14657 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14658 | mode_cmd->modifier[0]); | |
57cd6508 | 14659 | return -EINVAL; |
c16ed4be | 14660 | } |
57cd6508 | 14661 | |
b321803d DL |
14662 | stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0], |
14663 | mode_cmd->pixel_format); | |
14664 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
14665 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
14666 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 14667 | return -EINVAL; |
c16ed4be | 14668 | } |
57cd6508 | 14669 | |
b321803d DL |
14670 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
14671 | mode_cmd->pixel_format); | |
a35cdaa0 | 14672 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
14673 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
14674 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 14675 | "tiled" : "linear", |
a35cdaa0 | 14676 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 14677 | return -EINVAL; |
c16ed4be | 14678 | } |
5d7bd705 | 14679 | |
2a80eada | 14680 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
14681 | mode_cmd->pitches[0] != obj->stride) { |
14682 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
14683 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 14684 | return -EINVAL; |
c16ed4be | 14685 | } |
5d7bd705 | 14686 | |
57779d06 | 14687 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14688 | switch (mode_cmd->pixel_format) { |
57779d06 | 14689 | case DRM_FORMAT_C8: |
04b3924d VS |
14690 | case DRM_FORMAT_RGB565: |
14691 | case DRM_FORMAT_XRGB8888: | |
14692 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14693 | break; |
14694 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 14695 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
14696 | DRM_DEBUG("unsupported pixel format: %s\n", |
14697 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14698 | return -EINVAL; |
c16ed4be | 14699 | } |
57779d06 | 14700 | break; |
57779d06 | 14701 | case DRM_FORMAT_ABGR8888: |
666a4537 WB |
14702 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
14703 | INTEL_INFO(dev)->gen < 9) { | |
6c0fd451 DL |
14704 | DRM_DEBUG("unsupported pixel format: %s\n", |
14705 | drm_get_format_name(mode_cmd->pixel_format)); | |
14706 | return -EINVAL; | |
14707 | } | |
14708 | break; | |
14709 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 14710 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 14711 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 14712 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
14713 | DRM_DEBUG("unsupported pixel format: %s\n", |
14714 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14715 | return -EINVAL; |
c16ed4be | 14716 | } |
b5626747 | 14717 | break; |
7531208b | 14718 | case DRM_FORMAT_ABGR2101010: |
666a4537 | 14719 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
7531208b DL |
14720 | DRM_DEBUG("unsupported pixel format: %s\n", |
14721 | drm_get_format_name(mode_cmd->pixel_format)); | |
14722 | return -EINVAL; | |
14723 | } | |
14724 | break; | |
04b3924d VS |
14725 | case DRM_FORMAT_YUYV: |
14726 | case DRM_FORMAT_UYVY: | |
14727 | case DRM_FORMAT_YVYU: | |
14728 | case DRM_FORMAT_VYUY: | |
c16ed4be | 14729 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
14730 | DRM_DEBUG("unsupported pixel format: %s\n", |
14731 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14732 | return -EINVAL; |
c16ed4be | 14733 | } |
57cd6508 CW |
14734 | break; |
14735 | default: | |
4ee62c76 VS |
14736 | DRM_DEBUG("unsupported pixel format: %s\n", |
14737 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
14738 | return -EINVAL; |
14739 | } | |
14740 | ||
90f9a336 VS |
14741 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14742 | if (mode_cmd->offsets[0] != 0) | |
14743 | return -EINVAL; | |
14744 | ||
ec2c981e | 14745 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
14746 | mode_cmd->pixel_format, |
14747 | mode_cmd->modifier[0]); | |
53155c0a DV |
14748 | /* FIXME drm helper for size checks (especially planar formats)? */ |
14749 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
14750 | return -EINVAL; | |
14751 | ||
c7d73f6a DV |
14752 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
14753 | intel_fb->obj = obj; | |
80075d49 | 14754 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 14755 | |
79e53945 JB |
14756 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
14757 | if (ret) { | |
14758 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
14759 | return ret; | |
14760 | } | |
14761 | ||
79e53945 JB |
14762 | return 0; |
14763 | } | |
14764 | ||
79e53945 JB |
14765 | static struct drm_framebuffer * |
14766 | intel_user_framebuffer_create(struct drm_device *dev, | |
14767 | struct drm_file *filp, | |
76dc3769 | 14768 | struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 14769 | { |
dcb1394e | 14770 | struct drm_framebuffer *fb; |
05394f39 | 14771 | struct drm_i915_gem_object *obj; |
76dc3769 | 14772 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 14773 | |
308e5bcb | 14774 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
76dc3769 | 14775 | mode_cmd.handles[0])); |
c8725226 | 14776 | if (&obj->base == NULL) |
cce13ff7 | 14777 | return ERR_PTR(-ENOENT); |
79e53945 | 14778 | |
92907cbb | 14779 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
dcb1394e LW |
14780 | if (IS_ERR(fb)) |
14781 | drm_gem_object_unreference_unlocked(&obj->base); | |
14782 | ||
14783 | return fb; | |
79e53945 JB |
14784 | } |
14785 | ||
0695726e | 14786 | #ifndef CONFIG_DRM_FBDEV_EMULATION |
0632fef6 | 14787 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
14788 | { |
14789 | } | |
14790 | #endif | |
14791 | ||
79e53945 | 14792 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14793 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14794 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14795 | .atomic_check = intel_atomic_check, |
14796 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
14797 | .atomic_state_alloc = intel_atomic_state_alloc, |
14798 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
14799 | }; |
14800 | ||
e70236a8 JB |
14801 | /* Set up chip specific display functions */ |
14802 | static void intel_init_display(struct drm_device *dev) | |
14803 | { | |
14804 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14805 | ||
ee9300bb DV |
14806 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
14807 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
14808 | else if (IS_CHERRYVIEW(dev)) |
14809 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
14810 | else if (IS_VALLEYVIEW(dev)) |
14811 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
14812 | else if (IS_PINEVIEW(dev)) | |
14813 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
14814 | else | |
14815 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
14816 | ||
bc8d7dff DL |
14817 | if (INTEL_INFO(dev)->gen >= 9) { |
14818 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; | |
5724dbd1 DL |
14819 | dev_priv->display.get_initial_plane_config = |
14820 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14821 | dev_priv->display.crtc_compute_clock = |
14822 | haswell_crtc_compute_clock; | |
14823 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14824 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
bc8d7dff DL |
14825 | dev_priv->display.update_primary_plane = |
14826 | skylake_update_primary_plane; | |
14827 | } else if (HAS_DDI(dev)) { | |
0e8ffe1b | 14828 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14829 | dev_priv->display.get_initial_plane_config = |
14830 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14831 | dev_priv->display.crtc_compute_clock = |
14832 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14833 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14834 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
bc8d7dff DL |
14835 | dev_priv->display.update_primary_plane = |
14836 | ironlake_update_primary_plane; | |
09b4ddf9 | 14837 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 14838 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14839 | dev_priv->display.get_initial_plane_config = |
14840 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14841 | dev_priv->display.crtc_compute_clock = |
14842 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14843 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14844 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
262ca2b0 MR |
14845 | dev_priv->display.update_primary_plane = |
14846 | ironlake_update_primary_plane; | |
666a4537 | 14847 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
89b667f8 | 14848 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14849 | dev_priv->display.get_initial_plane_config = |
14850 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14851 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
14852 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14853 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
262ca2b0 MR |
14854 | dev_priv->display.update_primary_plane = |
14855 | i9xx_update_primary_plane; | |
f564048e | 14856 | } else { |
0e8ffe1b | 14857 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14858 | dev_priv->display.get_initial_plane_config = |
14859 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14860 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14861 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14862 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
262ca2b0 MR |
14863 | dev_priv->display.update_primary_plane = |
14864 | i9xx_update_primary_plane; | |
f564048e | 14865 | } |
e70236a8 | 14866 | |
e70236a8 | 14867 | /* Returns the core display clock speed */ |
ef11bdb3 | 14868 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
1652d19e VS |
14869 | dev_priv->display.get_display_clock_speed = |
14870 | skylake_get_display_clock_speed; | |
acd3f3d3 BP |
14871 | else if (IS_BROXTON(dev)) |
14872 | dev_priv->display.get_display_clock_speed = | |
14873 | broxton_get_display_clock_speed; | |
1652d19e VS |
14874 | else if (IS_BROADWELL(dev)) |
14875 | dev_priv->display.get_display_clock_speed = | |
14876 | broadwell_get_display_clock_speed; | |
14877 | else if (IS_HASWELL(dev)) | |
14878 | dev_priv->display.get_display_clock_speed = | |
14879 | haswell_get_display_clock_speed; | |
666a4537 | 14880 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
25eb05fc JB |
14881 | dev_priv->display.get_display_clock_speed = |
14882 | valleyview_get_display_clock_speed; | |
b37a6434 VS |
14883 | else if (IS_GEN5(dev)) |
14884 | dev_priv->display.get_display_clock_speed = | |
14885 | ilk_get_display_clock_speed; | |
a7c66cd8 | 14886 | else if (IS_I945G(dev) || IS_BROADWATER(dev) || |
34edce2f | 14887 | IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
e70236a8 JB |
14888 | dev_priv->display.get_display_clock_speed = |
14889 | i945_get_display_clock_speed; | |
34edce2f VS |
14890 | else if (IS_GM45(dev)) |
14891 | dev_priv->display.get_display_clock_speed = | |
14892 | gm45_get_display_clock_speed; | |
14893 | else if (IS_CRESTLINE(dev)) | |
14894 | dev_priv->display.get_display_clock_speed = | |
14895 | i965gm_get_display_clock_speed; | |
14896 | else if (IS_PINEVIEW(dev)) | |
14897 | dev_priv->display.get_display_clock_speed = | |
14898 | pnv_get_display_clock_speed; | |
14899 | else if (IS_G33(dev) || IS_G4X(dev)) | |
14900 | dev_priv->display.get_display_clock_speed = | |
14901 | g33_get_display_clock_speed; | |
e70236a8 JB |
14902 | else if (IS_I915G(dev)) |
14903 | dev_priv->display.get_display_clock_speed = | |
14904 | i915_get_display_clock_speed; | |
257a7ffc | 14905 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
14906 | dev_priv->display.get_display_clock_speed = |
14907 | i9xx_misc_get_display_clock_speed; | |
14908 | else if (IS_I915GM(dev)) | |
14909 | dev_priv->display.get_display_clock_speed = | |
14910 | i915gm_get_display_clock_speed; | |
14911 | else if (IS_I865G(dev)) | |
14912 | dev_priv->display.get_display_clock_speed = | |
14913 | i865_get_display_clock_speed; | |
f0f8a9ce | 14914 | else if (IS_I85X(dev)) |
e70236a8 | 14915 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 14916 | i85x_get_display_clock_speed; |
623e01e5 VS |
14917 | else { /* 830 */ |
14918 | WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n"); | |
e70236a8 JB |
14919 | dev_priv->display.get_display_clock_speed = |
14920 | i830_get_display_clock_speed; | |
623e01e5 | 14921 | } |
e70236a8 | 14922 | |
7c10a2b5 | 14923 | if (IS_GEN5(dev)) { |
3bb11b53 | 14924 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
14925 | } else if (IS_GEN6(dev)) { |
14926 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
14927 | } else if (IS_IVYBRIDGE(dev)) { |
14928 | /* FIXME: detect B0+ stepping and use auto training */ | |
14929 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
059b2fe9 | 14930 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 14931 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
27c329ed ML |
14932 | if (IS_BROADWELL(dev)) { |
14933 | dev_priv->display.modeset_commit_cdclk = | |
14934 | broadwell_modeset_commit_cdclk; | |
14935 | dev_priv->display.modeset_calc_cdclk = | |
14936 | broadwell_modeset_calc_cdclk; | |
14937 | } | |
666a4537 | 14938 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
27c329ed ML |
14939 | dev_priv->display.modeset_commit_cdclk = |
14940 | valleyview_modeset_commit_cdclk; | |
14941 | dev_priv->display.modeset_calc_cdclk = | |
14942 | valleyview_modeset_calc_cdclk; | |
f8437dd1 | 14943 | } else if (IS_BROXTON(dev)) { |
27c329ed ML |
14944 | dev_priv->display.modeset_commit_cdclk = |
14945 | broxton_modeset_commit_cdclk; | |
14946 | dev_priv->display.modeset_calc_cdclk = | |
14947 | broxton_modeset_calc_cdclk; | |
e70236a8 | 14948 | } |
8c9f3aaf | 14949 | |
8c9f3aaf JB |
14950 | switch (INTEL_INFO(dev)->gen) { |
14951 | case 2: | |
14952 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
14953 | break; | |
14954 | ||
14955 | case 3: | |
14956 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
14957 | break; | |
14958 | ||
14959 | case 4: | |
14960 | case 5: | |
14961 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
14962 | break; | |
14963 | ||
14964 | case 6: | |
14965 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
14966 | break; | |
7c9017e5 | 14967 | case 7: |
4e0bbc31 | 14968 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
14969 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
14970 | break; | |
830c81db | 14971 | case 9: |
ba343e02 TU |
14972 | /* Drop through - unsupported since execlist only. */ |
14973 | default: | |
14974 | /* Default just returns -ENODEV to indicate unsupported */ | |
14975 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 14976 | } |
7bd688cd | 14977 | |
e39b999a | 14978 | mutex_init(&dev_priv->pps_mutex); |
e70236a8 JB |
14979 | } |
14980 | ||
b690e96c JB |
14981 | /* |
14982 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
14983 | * resume, or other times. This quirk makes sure that's the case for | |
14984 | * affected systems. | |
14985 | */ | |
0206e353 | 14986 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
14987 | { |
14988 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14989 | ||
14990 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 14991 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
14992 | } |
14993 | ||
b6b5d049 VS |
14994 | static void quirk_pipeb_force(struct drm_device *dev) |
14995 | { | |
14996 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14997 | ||
14998 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
14999 | DRM_INFO("applying pipe b force quirk\n"); | |
15000 | } | |
15001 | ||
435793df KP |
15002 | /* |
15003 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
15004 | */ | |
15005 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
15006 | { | |
15007 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15008 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 15009 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
15010 | } |
15011 | ||
4dca20ef | 15012 | /* |
5a15ab5b CE |
15013 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
15014 | * brightness value | |
4dca20ef CE |
15015 | */ |
15016 | static void quirk_invert_brightness(struct drm_device *dev) | |
15017 | { | |
15018 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15019 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 15020 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
15021 | } |
15022 | ||
9c72cc6f SD |
15023 | /* Some VBT's incorrectly indicate no backlight is present */ |
15024 | static void quirk_backlight_present(struct drm_device *dev) | |
15025 | { | |
15026 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15027 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
15028 | DRM_INFO("applying backlight present quirk\n"); | |
15029 | } | |
15030 | ||
b690e96c JB |
15031 | struct intel_quirk { |
15032 | int device; | |
15033 | int subsystem_vendor; | |
15034 | int subsystem_device; | |
15035 | void (*hook)(struct drm_device *dev); | |
15036 | }; | |
15037 | ||
5f85f176 EE |
15038 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
15039 | struct intel_dmi_quirk { | |
15040 | void (*hook)(struct drm_device *dev); | |
15041 | const struct dmi_system_id (*dmi_id_list)[]; | |
15042 | }; | |
15043 | ||
15044 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
15045 | { | |
15046 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
15047 | return 1; | |
15048 | } | |
15049 | ||
15050 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
15051 | { | |
15052 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
15053 | { | |
15054 | .callback = intel_dmi_reverse_brightness, | |
15055 | .ident = "NCR Corporation", | |
15056 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
15057 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
15058 | }, | |
15059 | }, | |
15060 | { } /* terminating entry */ | |
15061 | }, | |
15062 | .hook = quirk_invert_brightness, | |
15063 | }, | |
15064 | }; | |
15065 | ||
c43b5634 | 15066 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
15067 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
15068 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
15069 | ||
b690e96c JB |
15070 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
15071 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
15072 | ||
5f080c0f VS |
15073 | /* 830 needs to leave pipe A & dpll A up */ |
15074 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
15075 | ||
b6b5d049 VS |
15076 | /* 830 needs to leave pipe B & dpll B up */ |
15077 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
15078 | ||
435793df KP |
15079 | /* Lenovo U160 cannot use SSC on LVDS */ |
15080 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
15081 | |
15082 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
15083 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 15084 | |
be505f64 AH |
15085 | /* Acer Aspire 5734Z must invert backlight brightness */ |
15086 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
15087 | ||
15088 | /* Acer/eMachines G725 */ | |
15089 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
15090 | ||
15091 | /* Acer/eMachines e725 */ | |
15092 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
15093 | ||
15094 | /* Acer/Packard Bell NCL20 */ | |
15095 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
15096 | ||
15097 | /* Acer Aspire 4736Z */ | |
15098 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
15099 | |
15100 | /* Acer Aspire 5336 */ | |
15101 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
15102 | |
15103 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
15104 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 15105 | |
dfb3d47b SD |
15106 | /* Acer C720 Chromebook (Core i3 4005U) */ |
15107 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
15108 | ||
b2a9601c | 15109 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
15110 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
15111 | ||
1b9448b0 JN |
15112 | /* Apple Macbook 4,1 */ |
15113 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
15114 | ||
d4967d8c SD |
15115 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
15116 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
15117 | |
15118 | /* HP Chromebook 14 (Celeron 2955U) */ | |
15119 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
15120 | |
15121 | /* Dell Chromebook 11 */ | |
15122 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
15123 | |
15124 | /* Dell Chromebook 11 (2015 version) */ | |
15125 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
15126 | }; |
15127 | ||
15128 | static void intel_init_quirks(struct drm_device *dev) | |
15129 | { | |
15130 | struct pci_dev *d = dev->pdev; | |
15131 | int i; | |
15132 | ||
15133 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
15134 | struct intel_quirk *q = &intel_quirks[i]; | |
15135 | ||
15136 | if (d->device == q->device && | |
15137 | (d->subsystem_vendor == q->subsystem_vendor || | |
15138 | q->subsystem_vendor == PCI_ANY_ID) && | |
15139 | (d->subsystem_device == q->subsystem_device || | |
15140 | q->subsystem_device == PCI_ANY_ID)) | |
15141 | q->hook(dev); | |
15142 | } | |
5f85f176 EE |
15143 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
15144 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
15145 | intel_dmi_quirks[i].hook(dev); | |
15146 | } | |
b690e96c JB |
15147 | } |
15148 | ||
9cce37f4 JB |
15149 | /* Disable the VGA plane that we never use */ |
15150 | static void i915_disable_vga(struct drm_device *dev) | |
15151 | { | |
15152 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15153 | u8 sr1; | |
f0f59a00 | 15154 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 15155 | |
2b37c616 | 15156 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 15157 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 15158 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
15159 | sr1 = inb(VGA_SR_DATA); |
15160 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
15161 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
15162 | udelay(300); | |
15163 | ||
01f5a626 | 15164 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
15165 | POSTING_READ(vga_reg); |
15166 | } | |
15167 | ||
f817586c DV |
15168 | void intel_modeset_init_hw(struct drm_device *dev) |
15169 | { | |
b6283055 | 15170 | intel_update_cdclk(dev); |
a8f78b58 | 15171 | intel_prepare_ddi(dev); |
f817586c | 15172 | intel_init_clock_gating(dev); |
8090c6b9 | 15173 | intel_enable_gt_powersave(dev); |
f817586c DV |
15174 | } |
15175 | ||
79e53945 JB |
15176 | void intel_modeset_init(struct drm_device *dev) |
15177 | { | |
652c393a | 15178 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 15179 | int sprite, ret; |
8cc87b75 | 15180 | enum pipe pipe; |
46f297fb | 15181 | struct intel_crtc *crtc; |
79e53945 JB |
15182 | |
15183 | drm_mode_config_init(dev); | |
15184 | ||
15185 | dev->mode_config.min_width = 0; | |
15186 | dev->mode_config.min_height = 0; | |
15187 | ||
019d96cb DA |
15188 | dev->mode_config.preferred_depth = 24; |
15189 | dev->mode_config.prefer_shadow = 1; | |
15190 | ||
25bab385 TU |
15191 | dev->mode_config.allow_fb_modifiers = true; |
15192 | ||
e6ecefaa | 15193 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 15194 | |
b690e96c JB |
15195 | intel_init_quirks(dev); |
15196 | ||
1fa61106 ED |
15197 | intel_init_pm(dev); |
15198 | ||
e3c74757 BW |
15199 | if (INTEL_INFO(dev)->num_pipes == 0) |
15200 | return; | |
15201 | ||
69f92f67 LW |
15202 | /* |
15203 | * There may be no VBT; and if the BIOS enabled SSC we can | |
15204 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
15205 | * BIOS isn't using it, don't assume it will work even if the VBT | |
15206 | * indicates as much. | |
15207 | */ | |
15208 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { | |
15209 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
15210 | DREF_SSC1_ENABLE); | |
15211 | ||
15212 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
15213 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
15214 | bios_lvds_use_ssc ? "en" : "dis", | |
15215 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
15216 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
15217 | } | |
15218 | } | |
15219 | ||
e70236a8 | 15220 | intel_init_display(dev); |
7c10a2b5 | 15221 | intel_init_audio(dev); |
e70236a8 | 15222 | |
a6c45cf0 CW |
15223 | if (IS_GEN2(dev)) { |
15224 | dev->mode_config.max_width = 2048; | |
15225 | dev->mode_config.max_height = 2048; | |
15226 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
15227 | dev->mode_config.max_width = 4096; |
15228 | dev->mode_config.max_height = 4096; | |
79e53945 | 15229 | } else { |
a6c45cf0 CW |
15230 | dev->mode_config.max_width = 8192; |
15231 | dev->mode_config.max_height = 8192; | |
79e53945 | 15232 | } |
068be561 | 15233 | |
dc41c154 VS |
15234 | if (IS_845G(dev) || IS_I865G(dev)) { |
15235 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
15236 | dev->mode_config.cursor_height = 1023; | |
15237 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
15238 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
15239 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
15240 | } else { | |
15241 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
15242 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
15243 | } | |
15244 | ||
5d4545ae | 15245 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 15246 | |
28c97730 | 15247 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
15248 | INTEL_INFO(dev)->num_pipes, |
15249 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 15250 | |
055e393f | 15251 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 15252 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 15253 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 15254 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 15255 | if (ret) |
06da8da2 | 15256 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 15257 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 15258 | } |
79e53945 JB |
15259 | } |
15260 | ||
bfa7df01 VS |
15261 | intel_update_czclk(dev_priv); |
15262 | intel_update_cdclk(dev); | |
15263 | ||
e72f9fbf | 15264 | intel_shared_dpll_init(dev); |
ee7b9f93 | 15265 | |
9cce37f4 JB |
15266 | /* Just disable it once at startup */ |
15267 | i915_disable_vga(dev); | |
79e53945 | 15268 | intel_setup_outputs(dev); |
11be49eb | 15269 | |
6e9f798d | 15270 | drm_modeset_lock_all(dev); |
043e9bda | 15271 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 15272 | drm_modeset_unlock_all(dev); |
46f297fb | 15273 | |
d3fcc808 | 15274 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
15275 | struct intel_initial_plane_config plane_config = {}; |
15276 | ||
46f297fb JB |
15277 | if (!crtc->active) |
15278 | continue; | |
15279 | ||
46f297fb | 15280 | /* |
46f297fb JB |
15281 | * Note that reserving the BIOS fb up front prevents us |
15282 | * from stuffing other stolen allocations like the ring | |
15283 | * on top. This prevents some ugliness at boot time, and | |
15284 | * can even allow for smooth boot transitions if the BIOS | |
15285 | * fb is large enough for the active pipe configuration. | |
15286 | */ | |
eeebeac5 ML |
15287 | dev_priv->display.get_initial_plane_config(crtc, |
15288 | &plane_config); | |
15289 | ||
15290 | /* | |
15291 | * If the fb is shared between multiple heads, we'll | |
15292 | * just get the first one. | |
15293 | */ | |
15294 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 15295 | } |
2c7111db CW |
15296 | } |
15297 | ||
7fad798e DV |
15298 | static void intel_enable_pipe_a(struct drm_device *dev) |
15299 | { | |
15300 | struct intel_connector *connector; | |
15301 | struct drm_connector *crt = NULL; | |
15302 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 15303 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
15304 | |
15305 | /* We can't just switch on the pipe A, we need to set things up with a | |
15306 | * proper mode and output configuration. As a gross hack, enable pipe A | |
15307 | * by enabling the load detect pipe once. */ | |
3a3371ff | 15308 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
15309 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
15310 | crt = &connector->base; | |
15311 | break; | |
15312 | } | |
15313 | } | |
15314 | ||
15315 | if (!crt) | |
15316 | return; | |
15317 | ||
208bf9fd | 15318 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 15319 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
15320 | } |
15321 | ||
fa555837 DV |
15322 | static bool |
15323 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15324 | { | |
7eb552ae BW |
15325 | struct drm_device *dev = crtc->base.dev; |
15326 | struct drm_i915_private *dev_priv = dev->dev_private; | |
649636ef | 15327 | u32 val; |
fa555837 | 15328 | |
7eb552ae | 15329 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
15330 | return true; |
15331 | ||
649636ef | 15332 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
15333 | |
15334 | if ((val & DISPLAY_PLANE_ENABLE) && | |
15335 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
15336 | return false; | |
15337 | ||
15338 | return true; | |
15339 | } | |
15340 | ||
02e93c35 VS |
15341 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
15342 | { | |
15343 | struct drm_device *dev = crtc->base.dev; | |
15344 | struct intel_encoder *encoder; | |
15345 | ||
15346 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
15347 | return true; | |
15348 | ||
15349 | return false; | |
15350 | } | |
15351 | ||
24929352 DV |
15352 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15353 | { | |
15354 | struct drm_device *dev = crtc->base.dev; | |
15355 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 15356 | i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder); |
24929352 | 15357 | |
24929352 | 15358 | /* Clear any frame start delays used for debugging left by the BIOS */ |
24929352 DV |
15359 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
15360 | ||
d3eaf884 | 15361 | /* restore vblank interrupts to correct state */ |
9625604c | 15362 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 15363 | if (crtc->active) { |
f9cd7b88 VS |
15364 | struct intel_plane *plane; |
15365 | ||
9625604c | 15366 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
15367 | |
15368 | /* Disable everything but the primary plane */ | |
15369 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
15370 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
15371 | continue; | |
15372 | ||
15373 | plane->disable_plane(&plane->base, &crtc->base); | |
15374 | } | |
9625604c | 15375 | } |
d3eaf884 | 15376 | |
24929352 | 15377 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
15378 | * disable the crtc (and hence change the state) if it is wrong. Note |
15379 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
15380 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
15381 | bool plane; |
15382 | ||
24929352 DV |
15383 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
15384 | crtc->base.base.id); | |
15385 | ||
15386 | /* Pipe has the wrong plane attached and the plane is active. | |
15387 | * Temporarily change the plane mapping and disable everything | |
15388 | * ... */ | |
15389 | plane = crtc->plane; | |
b70709a6 | 15390 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 15391 | crtc->plane = !plane; |
b17d48e2 | 15392 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15393 | crtc->plane = plane; |
24929352 | 15394 | } |
24929352 | 15395 | |
7fad798e DV |
15396 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
15397 | crtc->pipe == PIPE_A && !crtc->active) { | |
15398 | /* BIOS forgot to enable pipe A, this mostly happens after | |
15399 | * resume. Force-enable the pipe to fix this, the update_dpms | |
15400 | * call below we restore the pipe to the right state, but leave | |
15401 | * the required bits on. */ | |
15402 | intel_enable_pipe_a(dev); | |
15403 | } | |
15404 | ||
24929352 DV |
15405 | /* Adjust the state of the output pipe according to whether we |
15406 | * have active connectors/encoders. */ | |
02e93c35 | 15407 | if (!intel_crtc_has_encoders(crtc)) |
b17d48e2 | 15408 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15409 | |
53d9f4e9 | 15410 | if (crtc->active != crtc->base.state->active) { |
02e93c35 | 15411 | struct intel_encoder *encoder; |
24929352 DV |
15412 | |
15413 | /* This can happen either due to bugs in the get_hw_state | |
b17d48e2 ML |
15414 | * functions or because of calls to intel_crtc_disable_noatomic, |
15415 | * or because the pipe is force-enabled due to the | |
24929352 DV |
15416 | * pipe A quirk. */ |
15417 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
15418 | crtc->base.base.id, | |
83d65738 | 15419 | crtc->base.state->enable ? "enabled" : "disabled", |
24929352 DV |
15420 | crtc->active ? "enabled" : "disabled"); |
15421 | ||
4be40c98 | 15422 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0); |
49d6fa21 | 15423 | crtc->base.state->active = crtc->active; |
24929352 DV |
15424 | crtc->base.enabled = crtc->active; |
15425 | ||
15426 | /* Because we only establish the connector -> encoder -> | |
15427 | * crtc links if something is active, this means the | |
15428 | * crtc is now deactivated. Break the links. connector | |
15429 | * -> encoder links are only establish when things are | |
15430 | * actually up, hence no need to break them. */ | |
15431 | WARN_ON(crtc->active); | |
15432 | ||
2d406bb0 | 15433 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
24929352 | 15434 | encoder->base.crtc = NULL; |
24929352 | 15435 | } |
c5ab3bc0 | 15436 | |
a3ed6aad | 15437 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
15438 | /* |
15439 | * We start out with underrun reporting disabled to avoid races. | |
15440 | * For correct bookkeeping mark this on active crtcs. | |
15441 | * | |
c5ab3bc0 DV |
15442 | * Also on gmch platforms we dont have any hardware bits to |
15443 | * disable the underrun reporting. Which means we need to start | |
15444 | * out with underrun reporting disabled also on inactive pipes, | |
15445 | * since otherwise we'll complain about the garbage we read when | |
15446 | * e.g. coming up after runtime pm. | |
15447 | * | |
4cc31489 DV |
15448 | * No protection against concurrent access is required - at |
15449 | * worst a fifo underrun happens which also sets this to false. | |
15450 | */ | |
15451 | crtc->cpu_fifo_underrun_disabled = true; | |
15452 | crtc->pch_fifo_underrun_disabled = true; | |
15453 | } | |
24929352 DV |
15454 | } |
15455 | ||
15456 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15457 | { | |
15458 | struct intel_connector *connector; | |
15459 | struct drm_device *dev = encoder->base.dev; | |
873ffe69 | 15460 | bool active = false; |
24929352 DV |
15461 | |
15462 | /* We need to check both for a crtc link (meaning that the | |
15463 | * encoder is active and trying to read from a pipe) and the | |
15464 | * pipe itself being active. */ | |
15465 | bool has_active_crtc = encoder->base.crtc && | |
15466 | to_intel_crtc(encoder->base.crtc)->active; | |
15467 | ||
873ffe69 ML |
15468 | for_each_intel_connector(dev, connector) { |
15469 | if (connector->base.encoder != &encoder->base) | |
15470 | continue; | |
15471 | ||
15472 | active = true; | |
15473 | break; | |
15474 | } | |
15475 | ||
15476 | if (active && !has_active_crtc) { | |
24929352 DV |
15477 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
15478 | encoder->base.base.id, | |
8e329a03 | 15479 | encoder->base.name); |
24929352 DV |
15480 | |
15481 | /* Connector is active, but has no active pipe. This is | |
15482 | * fallout from our resume register restoring. Disable | |
15483 | * the encoder manually again. */ | |
15484 | if (encoder->base.crtc) { | |
15485 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
15486 | encoder->base.base.id, | |
8e329a03 | 15487 | encoder->base.name); |
24929352 | 15488 | encoder->disable(encoder); |
a62d1497 VS |
15489 | if (encoder->post_disable) |
15490 | encoder->post_disable(encoder); | |
24929352 | 15491 | } |
7f1950fb | 15492 | encoder->base.crtc = NULL; |
24929352 DV |
15493 | |
15494 | /* Inconsistent output/port/pipe state happens presumably due to | |
15495 | * a bug in one of the get_hw_state functions. Or someplace else | |
15496 | * in our code, like the register restore mess on resume. Clamp | |
15497 | * things to off as a safer default. */ | |
3a3371ff | 15498 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15499 | if (connector->encoder != encoder) |
15500 | continue; | |
7f1950fb EE |
15501 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
15502 | connector->base.encoder = NULL; | |
24929352 DV |
15503 | } |
15504 | } | |
15505 | /* Enabled encoders without active connectors will be fixed in | |
15506 | * the crtc fixup. */ | |
15507 | } | |
15508 | ||
04098753 | 15509 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
15510 | { |
15511 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 15512 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 15513 | |
04098753 ID |
15514 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15515 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
15516 | i915_disable_vga(dev); | |
15517 | } | |
15518 | } | |
15519 | ||
15520 | void i915_redisable_vga(struct drm_device *dev) | |
15521 | { | |
15522 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15523 | ||
8dc8a27c PZ |
15524 | /* This function can be called both from intel_modeset_setup_hw_state or |
15525 | * at a very early point in our resume sequence, where the power well | |
15526 | * structures are not yet restored. Since this function is at a very | |
15527 | * paranoid "someone might have enabled VGA while we were not looking" | |
15528 | * level, just check if the power well is enabled instead of trying to | |
15529 | * follow the "don't touch the power well if we don't need it" policy | |
15530 | * the rest of the driver uses. */ | |
f458ebbc | 15531 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15532 | return; |
15533 | ||
04098753 | 15534 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
15535 | } |
15536 | ||
f9cd7b88 | 15537 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 15538 | { |
f9cd7b88 | 15539 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 15540 | |
f9cd7b88 | 15541 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
15542 | } |
15543 | ||
f9cd7b88 VS |
15544 | /* FIXME read out full plane state for all planes */ |
15545 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 15546 | { |
b26d3ea3 | 15547 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 15548 | struct intel_plane_state *plane_state = |
b26d3ea3 | 15549 | to_intel_plane_state(primary->state); |
d032ffa0 | 15550 | |
19b8d387 | 15551 | plane_state->visible = crtc->active && |
b26d3ea3 ML |
15552 | primary_get_hw_state(to_intel_plane(primary)); |
15553 | ||
15554 | if (plane_state->visible) | |
15555 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); | |
98ec7739 VS |
15556 | } |
15557 | ||
30e984df | 15558 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
15559 | { |
15560 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15561 | enum pipe pipe; | |
24929352 DV |
15562 | struct intel_crtc *crtc; |
15563 | struct intel_encoder *encoder; | |
15564 | struct intel_connector *connector; | |
5358901f | 15565 | int i; |
24929352 | 15566 | |
d3fcc808 | 15567 | for_each_intel_crtc(dev, crtc) { |
b06f8b0d | 15568 | __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state); |
6e3c9717 | 15569 | memset(crtc->config, 0, sizeof(*crtc->config)); |
f7217905 | 15570 | crtc->config->base.crtc = &crtc->base; |
3b117c8f | 15571 | |
0e8ffe1b | 15572 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
6e3c9717 | 15573 | crtc->config); |
24929352 | 15574 | |
49d6fa21 | 15575 | crtc->base.state->active = crtc->active; |
24929352 | 15576 | crtc->base.enabled = crtc->active; |
b70709a6 | 15577 | |
f9cd7b88 | 15578 | readout_plane_state(crtc); |
24929352 DV |
15579 | |
15580 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
15581 | crtc->base.base.id, | |
15582 | crtc->active ? "enabled" : "disabled"); | |
15583 | } | |
15584 | ||
5358901f DV |
15585 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15586 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15587 | ||
3e369b76 ACO |
15588 | pll->on = pll->get_hw_state(dev_priv, pll, |
15589 | &pll->config.hw_state); | |
5358901f | 15590 | pll->active = 0; |
3e369b76 | 15591 | pll->config.crtc_mask = 0; |
d3fcc808 | 15592 | for_each_intel_crtc(dev, crtc) { |
1e6f2ddc | 15593 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
5358901f | 15594 | pll->active++; |
3e369b76 | 15595 | pll->config.crtc_mask |= 1 << crtc->pipe; |
1e6f2ddc | 15596 | } |
5358901f | 15597 | } |
5358901f | 15598 | |
1e6f2ddc | 15599 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 15600 | pll->name, pll->config.crtc_mask, pll->on); |
bd2bb1b9 | 15601 | |
3e369b76 | 15602 | if (pll->config.crtc_mask) |
bd2bb1b9 | 15603 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
15604 | } |
15605 | ||
b2784e15 | 15606 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15607 | pipe = 0; |
15608 | ||
15609 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
15610 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15611 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 15612 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
15613 | } else { |
15614 | encoder->base.crtc = NULL; | |
15615 | } | |
15616 | ||
6f2bcceb | 15617 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 15618 | encoder->base.base.id, |
8e329a03 | 15619 | encoder->base.name, |
24929352 | 15620 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 15621 | pipe_name(pipe)); |
24929352 DV |
15622 | } |
15623 | ||
3a3371ff | 15624 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15625 | if (connector->get_hw_state(connector)) { |
15626 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
24929352 DV |
15627 | connector->base.encoder = &connector->encoder->base; |
15628 | } else { | |
15629 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15630 | connector->base.encoder = NULL; | |
15631 | } | |
15632 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
15633 | connector->base.base.id, | |
c23cc417 | 15634 | connector->base.name, |
24929352 DV |
15635 | connector->base.encoder ? "enabled" : "disabled"); |
15636 | } | |
7f4c6284 VS |
15637 | |
15638 | for_each_intel_crtc(dev, crtc) { | |
15639 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
15640 | ||
15641 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
15642 | if (crtc->base.state->active) { | |
15643 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
15644 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
15645 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
15646 | ||
15647 | /* | |
15648 | * The initial mode needs to be set in order to keep | |
15649 | * the atomic core happy. It wants a valid mode if the | |
15650 | * crtc's enabled, so we do the above call. | |
15651 | * | |
15652 | * At this point some state updated by the connectors | |
15653 | * in their ->detect() callback has not run yet, so | |
15654 | * no recalculation can be done yet. | |
15655 | * | |
15656 | * Even if we could do a recalculation and modeset | |
15657 | * right now it would cause a double modeset if | |
15658 | * fbdev or userspace chooses a different initial mode. | |
15659 | * | |
15660 | * If that happens, someone indicated they wanted a | |
15661 | * mode change, which means it's safe to do a full | |
15662 | * recalculation. | |
15663 | */ | |
15664 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
15665 | |
15666 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
15667 | update_scanline_offset(crtc); | |
7f4c6284 VS |
15668 | } |
15669 | } | |
30e984df DV |
15670 | } |
15671 | ||
043e9bda ML |
15672 | /* Scan out the current hw modeset state, |
15673 | * and sanitizes it to the current state | |
15674 | */ | |
15675 | static void | |
15676 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df DV |
15677 | { |
15678 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15679 | enum pipe pipe; | |
30e984df DV |
15680 | struct intel_crtc *crtc; |
15681 | struct intel_encoder *encoder; | |
35c95375 | 15682 | int i; |
30e984df DV |
15683 | |
15684 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
15685 | |
15686 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 15687 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15688 | intel_sanitize_encoder(encoder); |
15689 | } | |
15690 | ||
055e393f | 15691 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
15692 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15693 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
15694 | intel_dump_pipe_config(crtc, crtc->config, |
15695 | "[setup_hw_state]"); | |
24929352 | 15696 | } |
9a935856 | 15697 | |
d29b2f9d ACO |
15698 | intel_modeset_update_connector_atomic_state(dev); |
15699 | ||
35c95375 DV |
15700 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15701 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15702 | ||
15703 | if (!pll->on || pll->active) | |
15704 | continue; | |
15705 | ||
15706 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15707 | ||
15708 | pll->disable(dev_priv, pll); | |
15709 | pll->on = false; | |
15710 | } | |
15711 | ||
666a4537 | 15712 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6eb1a681 VS |
15713 | vlv_wm_get_hw_state(dev); |
15714 | else if (IS_GEN9(dev)) | |
3078999f PB |
15715 | skl_wm_get_hw_state(dev); |
15716 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 | 15717 | ilk_wm_get_hw_state(dev); |
292b990e ML |
15718 | |
15719 | for_each_intel_crtc(dev, crtc) { | |
15720 | unsigned long put_domains; | |
15721 | ||
15722 | put_domains = modeset_get_crtc_power_domains(&crtc->base); | |
15723 | if (WARN_ON(put_domains)) | |
15724 | modeset_put_power_domains(dev_priv, put_domains); | |
15725 | } | |
15726 | intel_display_set_init_power(dev_priv, false); | |
043e9bda | 15727 | } |
7d0bc1ea | 15728 | |
043e9bda ML |
15729 | void intel_display_resume(struct drm_device *dev) |
15730 | { | |
15731 | struct drm_atomic_state *state = drm_atomic_state_alloc(dev); | |
15732 | struct intel_connector *conn; | |
15733 | struct intel_plane *plane; | |
15734 | struct drm_crtc *crtc; | |
15735 | int ret; | |
f30da187 | 15736 | |
043e9bda ML |
15737 | if (!state) |
15738 | return; | |
15739 | ||
15740 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
15741 | ||
15742 | /* preserve complete old state, including dpll */ | |
15743 | intel_atomic_get_shared_dpll_state(state); | |
15744 | ||
15745 | for_each_crtc(dev, crtc) { | |
15746 | struct drm_crtc_state *crtc_state = | |
15747 | drm_atomic_get_crtc_state(state, crtc); | |
15748 | ||
15749 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
15750 | if (ret) | |
15751 | goto err; | |
15752 | ||
15753 | /* force a restore */ | |
15754 | crtc_state->mode_changed = true; | |
45e2b5f6 | 15755 | } |
8af6cf88 | 15756 | |
043e9bda ML |
15757 | for_each_intel_plane(dev, plane) { |
15758 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base)); | |
15759 | if (ret) | |
15760 | goto err; | |
15761 | } | |
15762 | ||
15763 | for_each_intel_connector(dev, conn) { | |
15764 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base)); | |
15765 | if (ret) | |
15766 | goto err; | |
15767 | } | |
15768 | ||
15769 | intel_modeset_setup_hw_state(dev); | |
15770 | ||
15771 | i915_redisable_vga(dev); | |
74c090b1 | 15772 | ret = drm_atomic_commit(state); |
043e9bda ML |
15773 | if (!ret) |
15774 | return; | |
15775 | ||
15776 | err: | |
15777 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
15778 | drm_atomic_state_free(state); | |
2c7111db CW |
15779 | } |
15780 | ||
15781 | void intel_modeset_gem_init(struct drm_device *dev) | |
15782 | { | |
484b41dd | 15783 | struct drm_crtc *c; |
2ff8fde1 | 15784 | struct drm_i915_gem_object *obj; |
e0d6149b | 15785 | int ret; |
484b41dd | 15786 | |
ae48434c ID |
15787 | mutex_lock(&dev->struct_mutex); |
15788 | intel_init_gt_powersave(dev); | |
15789 | mutex_unlock(&dev->struct_mutex); | |
15790 | ||
1833b134 | 15791 | intel_modeset_init_hw(dev); |
02e792fb DV |
15792 | |
15793 | intel_setup_overlay(dev); | |
484b41dd JB |
15794 | |
15795 | /* | |
15796 | * Make sure any fbs we allocated at startup are properly | |
15797 | * pinned & fenced. When we do the allocation it's too early | |
15798 | * for this. | |
15799 | */ | |
70e1e0ec | 15800 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
15801 | obj = intel_fb_obj(c->primary->fb); |
15802 | if (obj == NULL) | |
484b41dd JB |
15803 | continue; |
15804 | ||
e0d6149b TU |
15805 | mutex_lock(&dev->struct_mutex); |
15806 | ret = intel_pin_and_fence_fb_obj(c->primary, | |
15807 | c->primary->fb, | |
7580d774 | 15808 | c->primary->state); |
e0d6149b TU |
15809 | mutex_unlock(&dev->struct_mutex); |
15810 | if (ret) { | |
484b41dd JB |
15811 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
15812 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
15813 | drm_framebuffer_unreference(c->primary->fb); |
15814 | c->primary->fb = NULL; | |
36750f28 | 15815 | c->primary->crtc = c->primary->state->crtc = NULL; |
afd65eb4 | 15816 | update_state_fb(c->primary); |
36750f28 | 15817 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
15818 | } |
15819 | } | |
0962c3c9 VS |
15820 | |
15821 | intel_backlight_register(dev); | |
79e53945 JB |
15822 | } |
15823 | ||
4932e2c3 ID |
15824 | void intel_connector_unregister(struct intel_connector *intel_connector) |
15825 | { | |
15826 | struct drm_connector *connector = &intel_connector->base; | |
15827 | ||
15828 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 15829 | drm_connector_unregister(connector); |
4932e2c3 ID |
15830 | } |
15831 | ||
79e53945 JB |
15832 | void intel_modeset_cleanup(struct drm_device *dev) |
15833 | { | |
652c393a | 15834 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9255d57 | 15835 | struct drm_connector *connector; |
652c393a | 15836 | |
2eb5252e ID |
15837 | intel_disable_gt_powersave(dev); |
15838 | ||
0962c3c9 VS |
15839 | intel_backlight_unregister(dev); |
15840 | ||
fd0c0642 DV |
15841 | /* |
15842 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 15843 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
15844 | * experience fancy races otherwise. |
15845 | */ | |
2aeb7d3a | 15846 | intel_irq_uninstall(dev_priv); |
eb21b92b | 15847 | |
fd0c0642 DV |
15848 | /* |
15849 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
15850 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
15851 | */ | |
f87ea761 | 15852 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 15853 | |
723bfd70 JB |
15854 | intel_unregister_dsm_handler(); |
15855 | ||
7733b49b | 15856 | intel_fbc_disable(dev_priv); |
69341a5e | 15857 | |
1630fe75 CW |
15858 | /* flush any delayed tasks or pending work */ |
15859 | flush_scheduled_work(); | |
15860 | ||
db31af1d JN |
15861 | /* destroy the backlight and sysfs files before encoders/connectors */ |
15862 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
15863 | struct intel_connector *intel_connector; |
15864 | ||
15865 | intel_connector = to_intel_connector(connector); | |
15866 | intel_connector->unregister(intel_connector); | |
db31af1d | 15867 | } |
d9255d57 | 15868 | |
79e53945 | 15869 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
15870 | |
15871 | intel_cleanup_overlay(dev); | |
ae48434c ID |
15872 | |
15873 | mutex_lock(&dev->struct_mutex); | |
15874 | intel_cleanup_gt_powersave(dev); | |
15875 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
15876 | } |
15877 | ||
f1c79df3 ZW |
15878 | /* |
15879 | * Return which encoder is currently attached for connector. | |
15880 | */ | |
df0e9248 | 15881 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 15882 | { |
df0e9248 CW |
15883 | return &intel_attached_encoder(connector)->base; |
15884 | } | |
f1c79df3 | 15885 | |
df0e9248 CW |
15886 | void intel_connector_attach_encoder(struct intel_connector *connector, |
15887 | struct intel_encoder *encoder) | |
15888 | { | |
15889 | connector->encoder = encoder; | |
15890 | drm_mode_connector_attach_encoder(&connector->base, | |
15891 | &encoder->base); | |
79e53945 | 15892 | } |
28d52043 DA |
15893 | |
15894 | /* | |
15895 | * set vga decode state - true == enable VGA decode | |
15896 | */ | |
15897 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
15898 | { | |
15899 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 15900 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
15901 | u16 gmch_ctrl; |
15902 | ||
75fa041d CW |
15903 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
15904 | DRM_ERROR("failed to read control word\n"); | |
15905 | return -EIO; | |
15906 | } | |
15907 | ||
c0cc8a55 CW |
15908 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
15909 | return 0; | |
15910 | ||
28d52043 DA |
15911 | if (state) |
15912 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
15913 | else | |
15914 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
15915 | |
15916 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
15917 | DRM_ERROR("failed to write control word\n"); | |
15918 | return -EIO; | |
15919 | } | |
15920 | ||
28d52043 DA |
15921 | return 0; |
15922 | } | |
c4a1d9e4 | 15923 | |
c4a1d9e4 | 15924 | struct intel_display_error_state { |
ff57f1b0 PZ |
15925 | |
15926 | u32 power_well_driver; | |
15927 | ||
63b66e5b CW |
15928 | int num_transcoders; |
15929 | ||
c4a1d9e4 CW |
15930 | struct intel_cursor_error_state { |
15931 | u32 control; | |
15932 | u32 position; | |
15933 | u32 base; | |
15934 | u32 size; | |
52331309 | 15935 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15936 | |
15937 | struct intel_pipe_error_state { | |
ddf9c536 | 15938 | bool power_domain_on; |
c4a1d9e4 | 15939 | u32 source; |
f301b1e1 | 15940 | u32 stat; |
52331309 | 15941 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15942 | |
15943 | struct intel_plane_error_state { | |
15944 | u32 control; | |
15945 | u32 stride; | |
15946 | u32 size; | |
15947 | u32 pos; | |
15948 | u32 addr; | |
15949 | u32 surface; | |
15950 | u32 tile_offset; | |
52331309 | 15951 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
15952 | |
15953 | struct intel_transcoder_error_state { | |
ddf9c536 | 15954 | bool power_domain_on; |
63b66e5b CW |
15955 | enum transcoder cpu_transcoder; |
15956 | ||
15957 | u32 conf; | |
15958 | ||
15959 | u32 htotal; | |
15960 | u32 hblank; | |
15961 | u32 hsync; | |
15962 | u32 vtotal; | |
15963 | u32 vblank; | |
15964 | u32 vsync; | |
15965 | } transcoder[4]; | |
c4a1d9e4 CW |
15966 | }; |
15967 | ||
15968 | struct intel_display_error_state * | |
15969 | intel_display_capture_error_state(struct drm_device *dev) | |
15970 | { | |
fbee40df | 15971 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 15972 | struct intel_display_error_state *error; |
63b66e5b CW |
15973 | int transcoders[] = { |
15974 | TRANSCODER_A, | |
15975 | TRANSCODER_B, | |
15976 | TRANSCODER_C, | |
15977 | TRANSCODER_EDP, | |
15978 | }; | |
c4a1d9e4 CW |
15979 | int i; |
15980 | ||
63b66e5b CW |
15981 | if (INTEL_INFO(dev)->num_pipes == 0) |
15982 | return NULL; | |
15983 | ||
9d1cb914 | 15984 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
15985 | if (error == NULL) |
15986 | return NULL; | |
15987 | ||
190be112 | 15988 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
15989 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
15990 | ||
055e393f | 15991 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 15992 | error->pipe[i].power_domain_on = |
f458ebbc DV |
15993 | __intel_display_power_is_enabled(dev_priv, |
15994 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 15995 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
15996 | continue; |
15997 | ||
5efb3e28 VS |
15998 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
15999 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
16000 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
16001 | |
16002 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
16003 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 16004 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 16005 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
16006 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
16007 | } | |
ca291363 PZ |
16008 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
16009 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
16010 | if (INTEL_INFO(dev)->gen >= 4) { |
16011 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
16012 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
16013 | } | |
16014 | ||
c4a1d9e4 | 16015 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 16016 | |
3abfce77 | 16017 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 16018 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
16019 | } |
16020 | ||
16021 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
16022 | if (HAS_DDI(dev_priv->dev)) | |
16023 | error->num_transcoders++; /* Account for eDP. */ | |
16024 | ||
16025 | for (i = 0; i < error->num_transcoders; i++) { | |
16026 | enum transcoder cpu_transcoder = transcoders[i]; | |
16027 | ||
ddf9c536 | 16028 | error->transcoder[i].power_domain_on = |
f458ebbc | 16029 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 16030 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 16031 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
16032 | continue; |
16033 | ||
63b66e5b CW |
16034 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
16035 | ||
16036 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
16037 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
16038 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
16039 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
16040 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
16041 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
16042 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
16043 | } |
16044 | ||
16045 | return error; | |
16046 | } | |
16047 | ||
edc3d884 MK |
16048 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
16049 | ||
c4a1d9e4 | 16050 | void |
edc3d884 | 16051 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
16052 | struct drm_device *dev, |
16053 | struct intel_display_error_state *error) | |
16054 | { | |
055e393f | 16055 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
16056 | int i; |
16057 | ||
63b66e5b CW |
16058 | if (!error) |
16059 | return; | |
16060 | ||
edc3d884 | 16061 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 16062 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 16063 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 16064 | error->power_well_driver); |
055e393f | 16065 | for_each_pipe(dev_priv, i) { |
edc3d884 | 16066 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
16067 | err_printf(m, " Power: %s\n", |
16068 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 16069 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 16070 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
16071 | |
16072 | err_printf(m, "Plane [%d]:\n", i); | |
16073 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
16074 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 16075 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
16076 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
16077 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 16078 | } |
4b71a570 | 16079 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 16080 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 16081 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
16082 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
16083 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
16084 | } |
16085 | ||
edc3d884 MK |
16086 | err_printf(m, "Cursor [%d]:\n", i); |
16087 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
16088 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
16089 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 16090 | } |
63b66e5b CW |
16091 | |
16092 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 16093 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 16094 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
16095 | err_printf(m, " Power: %s\n", |
16096 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
16097 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
16098 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
16099 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
16100 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
16101 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
16102 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
16103 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
16104 | } | |
c4a1d9e4 | 16105 | } |
e2fcdaa9 VS |
16106 | |
16107 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) | |
16108 | { | |
16109 | struct intel_crtc *crtc; | |
16110 | ||
16111 | for_each_intel_crtc(dev, crtc) { | |
16112 | struct intel_unpin_work *work; | |
e2fcdaa9 | 16113 | |
5e2d7afc | 16114 | spin_lock_irq(&dev->event_lock); |
e2fcdaa9 VS |
16115 | |
16116 | work = crtc->unpin_work; | |
16117 | ||
16118 | if (work && work->event && | |
16119 | work->event->base.file_priv == file) { | |
16120 | kfree(work->event); | |
16121 | work->event = NULL; | |
16122 | } | |
16123 | ||
5e2d7afc | 16124 | spin_unlock_irq(&dev->event_lock); |
e2fcdaa9 VS |
16125 | } |
16126 | } |