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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
5d723d7a | 37 | #include "intel_frontbuffer.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
79e53945 | 39 | #include "i915_drv.h" |
57822dc6 | 40 | #include "i915_gem_clflush.h" |
db18b6a6 | 41 | #include "intel_dsi.h" |
e5510fac | 42 | #include "i915_trace.h" |
319c1d42 | 43 | #include <drm/drm_atomic.h> |
c196e1d6 | 44 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
45 | #include <drm/drm_dp_helper.h> |
46 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
47 | #include <drm/drm_plane_helper.h> |
48 | #include <drm/drm_rect.h> | |
c0f372b3 | 49 | #include <linux/dma_remapping.h> |
fd8e058a | 50 | #include <linux/reservation.h> |
79e53945 | 51 | |
5a21b665 DV |
52 | static bool is_mmio_work(struct intel_flip_work *work) |
53 | { | |
54 | return work->mmio_work.func; | |
55 | } | |
56 | ||
465c120c | 57 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 58 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
59 | DRM_FORMAT_C8, |
60 | DRM_FORMAT_RGB565, | |
465c120c | 61 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 62 | DRM_FORMAT_XRGB8888, |
465c120c MR |
63 | }; |
64 | ||
65 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 66 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
67 | DRM_FORMAT_C8, |
68 | DRM_FORMAT_RGB565, | |
69 | DRM_FORMAT_XRGB8888, | |
70 | DRM_FORMAT_XBGR8888, | |
71 | DRM_FORMAT_XRGB2101010, | |
72 | DRM_FORMAT_XBGR2101010, | |
73 | }; | |
74 | ||
75 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
76 | DRM_FORMAT_C8, |
77 | DRM_FORMAT_RGB565, | |
78 | DRM_FORMAT_XRGB8888, | |
465c120c | 79 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 80 | DRM_FORMAT_ARGB8888, |
465c120c MR |
81 | DRM_FORMAT_ABGR8888, |
82 | DRM_FORMAT_XRGB2101010, | |
465c120c | 83 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
84 | DRM_FORMAT_YUYV, |
85 | DRM_FORMAT_YVYU, | |
86 | DRM_FORMAT_UYVY, | |
87 | DRM_FORMAT_VYUY, | |
465c120c MR |
88 | }; |
89 | ||
3d7d6510 MR |
90 | /* Cursor formats */ |
91 | static const uint32_t intel_cursor_formats[] = { | |
92 | DRM_FORMAT_ARGB8888, | |
93 | }; | |
94 | ||
f1f644dc | 95 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 96 | struct intel_crtc_state *pipe_config); |
18442d08 | 97 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 98 | struct intel_crtc_state *pipe_config); |
f1f644dc | 99 | |
24dbf51a CW |
100 | static int intel_framebuffer_init(struct intel_framebuffer *ifb, |
101 | struct drm_i915_gem_object *obj, | |
102 | struct drm_mode_fb_cmd2 *mode_cmd); | |
5b18e57c DV |
103 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
104 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
bc58be60 | 105 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc); |
29407aab | 106 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
107 | struct intel_link_m_n *m_n, |
108 | struct intel_link_m_n *m2_n2); | |
29407aab | 109 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 | 110 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
391bf048 | 111 | static void haswell_set_pipemisc(struct drm_crtc *crtc); |
d288f65f | 112 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 113 | const struct intel_crtc_state *pipe_config); |
d288f65f | 114 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 115 | const struct intel_crtc_state *pipe_config); |
5a21b665 DV |
116 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
117 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
1c74eeaf NM |
118 | static void intel_crtc_init_scalers(struct intel_crtc *crtc, |
119 | struct intel_crtc_state *crtc_state); | |
bfd16b2a ML |
120 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
121 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
122 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 123 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
2622a081 | 124 | static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); |
e7457a9a | 125 | |
d4906093 | 126 | struct intel_limit { |
4c5def93 ACO |
127 | struct { |
128 | int min, max; | |
129 | } dot, vco, n, m, m1, m2, p, p1; | |
130 | ||
131 | struct { | |
132 | int dot_limit; | |
133 | int p2_slow, p2_fast; | |
134 | } p2; | |
d4906093 | 135 | }; |
79e53945 | 136 | |
bfa7df01 | 137 | /* returns HPLL frequency in kHz */ |
49cd97a3 | 138 | int vlv_get_hpll_vco(struct drm_i915_private *dev_priv) |
bfa7df01 VS |
139 | { |
140 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
141 | ||
142 | /* Obtain SKU information */ | |
143 | mutex_lock(&dev_priv->sb_lock); | |
144 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
145 | CCK_FUSE_HPLL_FREQ_MASK; | |
146 | mutex_unlock(&dev_priv->sb_lock); | |
147 | ||
148 | return vco_freq[hpll_freq] * 1000; | |
149 | } | |
150 | ||
c30fec65 VS |
151 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
152 | const char *name, u32 reg, int ref_freq) | |
bfa7df01 VS |
153 | { |
154 | u32 val; | |
155 | int divider; | |
156 | ||
bfa7df01 VS |
157 | mutex_lock(&dev_priv->sb_lock); |
158 | val = vlv_cck_read(dev_priv, reg); | |
159 | mutex_unlock(&dev_priv->sb_lock); | |
160 | ||
161 | divider = val & CCK_FREQUENCY_VALUES; | |
162 | ||
163 | WARN((val & CCK_FREQUENCY_STATUS) != | |
164 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
165 | "%s change in progress\n", name); | |
166 | ||
c30fec65 VS |
167 | return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); |
168 | } | |
169 | ||
7ff89ca2 VS |
170 | int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, |
171 | const char *name, u32 reg) | |
c30fec65 VS |
172 | { |
173 | if (dev_priv->hpll_freq == 0) | |
49cd97a3 | 174 | dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); |
c30fec65 VS |
175 | |
176 | return vlv_get_cck_clock(dev_priv, name, reg, | |
177 | dev_priv->hpll_freq); | |
bfa7df01 VS |
178 | } |
179 | ||
bfa7df01 VS |
180 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
181 | { | |
666a4537 | 182 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
183 | return; |
184 | ||
185 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
186 | CCK_CZ_CLOCK_CONTROL); | |
187 | ||
188 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
189 | } | |
190 | ||
021357ac | 191 | static inline u32 /* units of 100MHz */ |
21a727b3 VS |
192 | intel_fdi_link_freq(struct drm_i915_private *dev_priv, |
193 | const struct intel_crtc_state *pipe_config) | |
021357ac | 194 | { |
21a727b3 VS |
195 | if (HAS_DDI(dev_priv)) |
196 | return pipe_config->port_clock; /* SPLL */ | |
197 | else if (IS_GEN5(dev_priv)) | |
198 | return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; | |
e3b247da | 199 | else |
21a727b3 | 200 | return 270000; |
021357ac CW |
201 | } |
202 | ||
1b6f4958 | 203 | static const struct intel_limit intel_limits_i8xx_dac = { |
0206e353 | 204 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 205 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 206 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
207 | .m = { .min = 96, .max = 140 }, |
208 | .m1 = { .min = 18, .max = 26 }, | |
209 | .m2 = { .min = 6, .max = 16 }, | |
210 | .p = { .min = 4, .max = 128 }, | |
211 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
212 | .p2 = { .dot_limit = 165000, |
213 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
214 | }; |
215 | ||
1b6f4958 | 216 | static const struct intel_limit intel_limits_i8xx_dvo = { |
5d536e28 | 217 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 218 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 219 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
220 | .m = { .min = 96, .max = 140 }, |
221 | .m1 = { .min = 18, .max = 26 }, | |
222 | .m2 = { .min = 6, .max = 16 }, | |
223 | .p = { .min = 4, .max = 128 }, | |
224 | .p1 = { .min = 2, .max = 33 }, | |
225 | .p2 = { .dot_limit = 165000, | |
226 | .p2_slow = 4, .p2_fast = 4 }, | |
227 | }; | |
228 | ||
1b6f4958 | 229 | static const struct intel_limit intel_limits_i8xx_lvds = { |
0206e353 | 230 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 231 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 232 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
233 | .m = { .min = 96, .max = 140 }, |
234 | .m1 = { .min = 18, .max = 26 }, | |
235 | .m2 = { .min = 6, .max = 16 }, | |
236 | .p = { .min = 4, .max = 128 }, | |
237 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
238 | .p2 = { .dot_limit = 165000, |
239 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 240 | }; |
273e27ca | 241 | |
1b6f4958 | 242 | static const struct intel_limit intel_limits_i9xx_sdvo = { |
0206e353 AJ |
243 | .dot = { .min = 20000, .max = 400000 }, |
244 | .vco = { .min = 1400000, .max = 2800000 }, | |
245 | .n = { .min = 1, .max = 6 }, | |
246 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
247 | .m1 = { .min = 8, .max = 18 }, |
248 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
249 | .p = { .min = 5, .max = 80 }, |
250 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
251 | .p2 = { .dot_limit = 200000, |
252 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
253 | }; |
254 | ||
1b6f4958 | 255 | static const struct intel_limit intel_limits_i9xx_lvds = { |
0206e353 AJ |
256 | .dot = { .min = 20000, .max = 400000 }, |
257 | .vco = { .min = 1400000, .max = 2800000 }, | |
258 | .n = { .min = 1, .max = 6 }, | |
259 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
260 | .m1 = { .min = 8, .max = 18 }, |
261 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
262 | .p = { .min = 7, .max = 98 }, |
263 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
264 | .p2 = { .dot_limit = 112000, |
265 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
266 | }; |
267 | ||
273e27ca | 268 | |
1b6f4958 | 269 | static const struct intel_limit intel_limits_g4x_sdvo = { |
273e27ca EA |
270 | .dot = { .min = 25000, .max = 270000 }, |
271 | .vco = { .min = 1750000, .max = 3500000}, | |
272 | .n = { .min = 1, .max = 4 }, | |
273 | .m = { .min = 104, .max = 138 }, | |
274 | .m1 = { .min = 17, .max = 23 }, | |
275 | .m2 = { .min = 5, .max = 11 }, | |
276 | .p = { .min = 10, .max = 30 }, | |
277 | .p1 = { .min = 1, .max = 3}, | |
278 | .p2 = { .dot_limit = 270000, | |
279 | .p2_slow = 10, | |
280 | .p2_fast = 10 | |
044c7c41 | 281 | }, |
e4b36699 KP |
282 | }; |
283 | ||
1b6f4958 | 284 | static const struct intel_limit intel_limits_g4x_hdmi = { |
273e27ca EA |
285 | .dot = { .min = 22000, .max = 400000 }, |
286 | .vco = { .min = 1750000, .max = 3500000}, | |
287 | .n = { .min = 1, .max = 4 }, | |
288 | .m = { .min = 104, .max = 138 }, | |
289 | .m1 = { .min = 16, .max = 23 }, | |
290 | .m2 = { .min = 5, .max = 11 }, | |
291 | .p = { .min = 5, .max = 80 }, | |
292 | .p1 = { .min = 1, .max = 8}, | |
293 | .p2 = { .dot_limit = 165000, | |
294 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
295 | }; |
296 | ||
1b6f4958 | 297 | static const struct intel_limit intel_limits_g4x_single_channel_lvds = { |
273e27ca EA |
298 | .dot = { .min = 20000, .max = 115000 }, |
299 | .vco = { .min = 1750000, .max = 3500000 }, | |
300 | .n = { .min = 1, .max = 3 }, | |
301 | .m = { .min = 104, .max = 138 }, | |
302 | .m1 = { .min = 17, .max = 23 }, | |
303 | .m2 = { .min = 5, .max = 11 }, | |
304 | .p = { .min = 28, .max = 112 }, | |
305 | .p1 = { .min = 2, .max = 8 }, | |
306 | .p2 = { .dot_limit = 0, | |
307 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 308 | }, |
e4b36699 KP |
309 | }; |
310 | ||
1b6f4958 | 311 | static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { |
273e27ca EA |
312 | .dot = { .min = 80000, .max = 224000 }, |
313 | .vco = { .min = 1750000, .max = 3500000 }, | |
314 | .n = { .min = 1, .max = 3 }, | |
315 | .m = { .min = 104, .max = 138 }, | |
316 | .m1 = { .min = 17, .max = 23 }, | |
317 | .m2 = { .min = 5, .max = 11 }, | |
318 | .p = { .min = 14, .max = 42 }, | |
319 | .p1 = { .min = 2, .max = 6 }, | |
320 | .p2 = { .dot_limit = 0, | |
321 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 322 | }, |
e4b36699 KP |
323 | }; |
324 | ||
1b6f4958 | 325 | static const struct intel_limit intel_limits_pineview_sdvo = { |
0206e353 AJ |
326 | .dot = { .min = 20000, .max = 400000}, |
327 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 328 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
329 | .n = { .min = 3, .max = 6 }, |
330 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 331 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
332 | .m1 = { .min = 0, .max = 0 }, |
333 | .m2 = { .min = 0, .max = 254 }, | |
334 | .p = { .min = 5, .max = 80 }, | |
335 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
336 | .p2 = { .dot_limit = 200000, |
337 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
338 | }; |
339 | ||
1b6f4958 | 340 | static const struct intel_limit intel_limits_pineview_lvds = { |
0206e353 AJ |
341 | .dot = { .min = 20000, .max = 400000 }, |
342 | .vco = { .min = 1700000, .max = 3500000 }, | |
343 | .n = { .min = 3, .max = 6 }, | |
344 | .m = { .min = 2, .max = 256 }, | |
345 | .m1 = { .min = 0, .max = 0 }, | |
346 | .m2 = { .min = 0, .max = 254 }, | |
347 | .p = { .min = 7, .max = 112 }, | |
348 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
349 | .p2 = { .dot_limit = 112000, |
350 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
351 | }; |
352 | ||
273e27ca EA |
353 | /* Ironlake / Sandybridge |
354 | * | |
355 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
356 | * the range value for them is (actual_value - 2). | |
357 | */ | |
1b6f4958 | 358 | static const struct intel_limit intel_limits_ironlake_dac = { |
273e27ca EA |
359 | .dot = { .min = 25000, .max = 350000 }, |
360 | .vco = { .min = 1760000, .max = 3510000 }, | |
361 | .n = { .min = 1, .max = 5 }, | |
362 | .m = { .min = 79, .max = 127 }, | |
363 | .m1 = { .min = 12, .max = 22 }, | |
364 | .m2 = { .min = 5, .max = 9 }, | |
365 | .p = { .min = 5, .max = 80 }, | |
366 | .p1 = { .min = 1, .max = 8 }, | |
367 | .p2 = { .dot_limit = 225000, | |
368 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
369 | }; |
370 | ||
1b6f4958 | 371 | static const struct intel_limit intel_limits_ironlake_single_lvds = { |
273e27ca EA |
372 | .dot = { .min = 25000, .max = 350000 }, |
373 | .vco = { .min = 1760000, .max = 3510000 }, | |
374 | .n = { .min = 1, .max = 3 }, | |
375 | .m = { .min = 79, .max = 118 }, | |
376 | .m1 = { .min = 12, .max = 22 }, | |
377 | .m2 = { .min = 5, .max = 9 }, | |
378 | .p = { .min = 28, .max = 112 }, | |
379 | .p1 = { .min = 2, .max = 8 }, | |
380 | .p2 = { .dot_limit = 225000, | |
381 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
382 | }; |
383 | ||
1b6f4958 | 384 | static const struct intel_limit intel_limits_ironlake_dual_lvds = { |
273e27ca EA |
385 | .dot = { .min = 25000, .max = 350000 }, |
386 | .vco = { .min = 1760000, .max = 3510000 }, | |
387 | .n = { .min = 1, .max = 3 }, | |
388 | .m = { .min = 79, .max = 127 }, | |
389 | .m1 = { .min = 12, .max = 22 }, | |
390 | .m2 = { .min = 5, .max = 9 }, | |
391 | .p = { .min = 14, .max = 56 }, | |
392 | .p1 = { .min = 2, .max = 8 }, | |
393 | .p2 = { .dot_limit = 225000, | |
394 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
395 | }; |
396 | ||
273e27ca | 397 | /* LVDS 100mhz refclk limits. */ |
1b6f4958 | 398 | static const struct intel_limit intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
399 | .dot = { .min = 25000, .max = 350000 }, |
400 | .vco = { .min = 1760000, .max = 3510000 }, | |
401 | .n = { .min = 1, .max = 2 }, | |
402 | .m = { .min = 79, .max = 126 }, | |
403 | .m1 = { .min = 12, .max = 22 }, | |
404 | .m2 = { .min = 5, .max = 9 }, | |
405 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 406 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
407 | .p2 = { .dot_limit = 225000, |
408 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
409 | }; |
410 | ||
1b6f4958 | 411 | static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = { |
273e27ca EA |
412 | .dot = { .min = 25000, .max = 350000 }, |
413 | .vco = { .min = 1760000, .max = 3510000 }, | |
414 | .n = { .min = 1, .max = 3 }, | |
415 | .m = { .min = 79, .max = 126 }, | |
416 | .m1 = { .min = 12, .max = 22 }, | |
417 | .m2 = { .min = 5, .max = 9 }, | |
418 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 419 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
420 | .p2 = { .dot_limit = 225000, |
421 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
422 | }; |
423 | ||
1b6f4958 | 424 | static const struct intel_limit intel_limits_vlv = { |
f01b7962 VS |
425 | /* |
426 | * These are the data rate limits (measured in fast clocks) | |
427 | * since those are the strictest limits we have. The fast | |
428 | * clock and actual rate limits are more relaxed, so checking | |
429 | * them would make no difference. | |
430 | */ | |
431 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 432 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 433 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
434 | .m1 = { .min = 2, .max = 3 }, |
435 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 436 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 437 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
438 | }; |
439 | ||
1b6f4958 | 440 | static const struct intel_limit intel_limits_chv = { |
ef9348c8 CML |
441 | /* |
442 | * These are the data rate limits (measured in fast clocks) | |
443 | * since those are the strictest limits we have. The fast | |
444 | * clock and actual rate limits are more relaxed, so checking | |
445 | * them would make no difference. | |
446 | */ | |
447 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 448 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
449 | .n = { .min = 1, .max = 1 }, |
450 | .m1 = { .min = 2, .max = 2 }, | |
451 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
452 | .p1 = { .min = 2, .max = 4 }, | |
453 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
454 | }; | |
455 | ||
1b6f4958 | 456 | static const struct intel_limit intel_limits_bxt = { |
5ab7b0b7 ID |
457 | /* FIXME: find real dot limits */ |
458 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 459 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
460 | .n = { .min = 1, .max = 1 }, |
461 | .m1 = { .min = 2, .max = 2 }, | |
462 | /* FIXME: find real m2 limits */ | |
463 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
464 | .p1 = { .min = 2, .max = 4 }, | |
465 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
466 | }; | |
467 | ||
cdba954e ACO |
468 | static bool |
469 | needs_modeset(struct drm_crtc_state *state) | |
470 | { | |
fc596660 | 471 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
472 | } |
473 | ||
dccbea3b ID |
474 | /* |
475 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
476 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
477 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
478 | * The helpers' return value is the rate of the clock that is fed to the | |
479 | * display engine's pipe which can be the above fast dot clock rate or a | |
480 | * divided-down version of it. | |
481 | */ | |
f2b115e6 | 482 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
9e2c8475 | 483 | static int pnv_calc_dpll_params(int refclk, struct dpll *clock) |
79e53945 | 484 | { |
2177832f SL |
485 | clock->m = clock->m2 + 2; |
486 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 487 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 488 | return 0; |
fb03ac01 VS |
489 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
490 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
491 | |
492 | return clock->dot; | |
2177832f SL |
493 | } |
494 | ||
7429e9d4 DV |
495 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
496 | { | |
497 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
498 | } | |
499 | ||
9e2c8475 | 500 | static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) |
2177832f | 501 | { |
7429e9d4 | 502 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 503 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 504 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 505 | return 0; |
fb03ac01 VS |
506 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
507 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
508 | |
509 | return clock->dot; | |
79e53945 JB |
510 | } |
511 | ||
9e2c8475 | 512 | static int vlv_calc_dpll_params(int refclk, struct dpll *clock) |
589eca67 ID |
513 | { |
514 | clock->m = clock->m1 * clock->m2; | |
515 | clock->p = clock->p1 * clock->p2; | |
516 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 517 | return 0; |
589eca67 ID |
518 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
519 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
520 | |
521 | return clock->dot / 5; | |
589eca67 ID |
522 | } |
523 | ||
9e2c8475 | 524 | int chv_calc_dpll_params(int refclk, struct dpll *clock) |
ef9348c8 CML |
525 | { |
526 | clock->m = clock->m1 * clock->m2; | |
527 | clock->p = clock->p1 * clock->p2; | |
528 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 529 | return 0; |
ef9348c8 CML |
530 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
531 | clock->n << 22); | |
532 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
533 | |
534 | return clock->dot / 5; | |
ef9348c8 CML |
535 | } |
536 | ||
7c04d1d9 | 537 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
538 | /** |
539 | * Returns whether the given set of divisors are valid for a given refclk with | |
540 | * the given connectors. | |
541 | */ | |
542 | ||
e2d214ae | 543 | static bool intel_PLL_is_valid(struct drm_i915_private *dev_priv, |
1b6f4958 | 544 | const struct intel_limit *limit, |
9e2c8475 | 545 | const struct dpll *clock) |
79e53945 | 546 | { |
f01b7962 VS |
547 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
548 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 549 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 550 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 551 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 552 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 553 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 554 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 555 | |
e2d214ae | 556 | if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) && |
cc3f90f0 | 557 | !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv)) |
f01b7962 VS |
558 | if (clock->m1 <= clock->m2) |
559 | INTELPllInvalid("m1 <= m2\n"); | |
560 | ||
e2d214ae | 561 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
cc3f90f0 | 562 | !IS_GEN9_LP(dev_priv)) { |
f01b7962 VS |
563 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
564 | INTELPllInvalid("p out of range\n"); | |
565 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
566 | INTELPllInvalid("m out of range\n"); | |
567 | } | |
568 | ||
79e53945 | 569 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 570 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
571 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
572 | * connector, etc., rather than just a single range. | |
573 | */ | |
574 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 575 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
576 | |
577 | return true; | |
578 | } | |
579 | ||
3b1429d9 | 580 | static int |
1b6f4958 | 581 | i9xx_select_p2_div(const struct intel_limit *limit, |
3b1429d9 VS |
582 | const struct intel_crtc_state *crtc_state, |
583 | int target) | |
79e53945 | 584 | { |
3b1429d9 | 585 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 586 | |
2d84d2b3 | 587 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 588 | /* |
a210b028 DV |
589 | * For LVDS just rely on its current settings for dual-channel. |
590 | * We haven't figured out how to reliably set up different | |
591 | * single/dual channel state, if we even can. | |
79e53945 | 592 | */ |
1974cad0 | 593 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 594 | return limit->p2.p2_fast; |
79e53945 | 595 | else |
3b1429d9 | 596 | return limit->p2.p2_slow; |
79e53945 JB |
597 | } else { |
598 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 599 | return limit->p2.p2_slow; |
79e53945 | 600 | else |
3b1429d9 | 601 | return limit->p2.p2_fast; |
79e53945 | 602 | } |
3b1429d9 VS |
603 | } |
604 | ||
70e8aa21 ACO |
605 | /* |
606 | * Returns a set of divisors for the desired target clock with the given | |
607 | * refclk, or FALSE. The returned values represent the clock equation: | |
608 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
609 | * | |
610 | * Target and reference clocks are specified in kHz. | |
611 | * | |
612 | * If match_clock is provided, then best_clock P divider must match the P | |
613 | * divider from @match_clock used for LVDS downclocking. | |
614 | */ | |
3b1429d9 | 615 | static bool |
1b6f4958 | 616 | i9xx_find_best_dpll(const struct intel_limit *limit, |
3b1429d9 | 617 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
618 | int target, int refclk, struct dpll *match_clock, |
619 | struct dpll *best_clock) | |
3b1429d9 VS |
620 | { |
621 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
9e2c8475 | 622 | struct dpll clock; |
3b1429d9 | 623 | int err = target; |
79e53945 | 624 | |
0206e353 | 625 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 626 | |
3b1429d9 VS |
627 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
628 | ||
42158660 ZY |
629 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
630 | clock.m1++) { | |
631 | for (clock.m2 = limit->m2.min; | |
632 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 633 | if (clock.m2 >= clock.m1) |
42158660 ZY |
634 | break; |
635 | for (clock.n = limit->n.min; | |
636 | clock.n <= limit->n.max; clock.n++) { | |
637 | for (clock.p1 = limit->p1.min; | |
638 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
639 | int this_err; |
640 | ||
dccbea3b | 641 | i9xx_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
642 | if (!intel_PLL_is_valid(to_i915(dev), |
643 | limit, | |
ac58c3f0 DV |
644 | &clock)) |
645 | continue; | |
646 | if (match_clock && | |
647 | clock.p != match_clock->p) | |
648 | continue; | |
649 | ||
650 | this_err = abs(clock.dot - target); | |
651 | if (this_err < err) { | |
652 | *best_clock = clock; | |
653 | err = this_err; | |
654 | } | |
655 | } | |
656 | } | |
657 | } | |
658 | } | |
659 | ||
660 | return (err != target); | |
661 | } | |
662 | ||
70e8aa21 ACO |
663 | /* |
664 | * Returns a set of divisors for the desired target clock with the given | |
665 | * refclk, or FALSE. The returned values represent the clock equation: | |
666 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
667 | * | |
668 | * Target and reference clocks are specified in kHz. | |
669 | * | |
670 | * If match_clock is provided, then best_clock P divider must match the P | |
671 | * divider from @match_clock used for LVDS downclocking. | |
672 | */ | |
ac58c3f0 | 673 | static bool |
1b6f4958 | 674 | pnv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 675 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
676 | int target, int refclk, struct dpll *match_clock, |
677 | struct dpll *best_clock) | |
79e53945 | 678 | { |
3b1429d9 | 679 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 680 | struct dpll clock; |
79e53945 JB |
681 | int err = target; |
682 | ||
0206e353 | 683 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 684 | |
3b1429d9 VS |
685 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
686 | ||
42158660 ZY |
687 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
688 | clock.m1++) { | |
689 | for (clock.m2 = limit->m2.min; | |
690 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
691 | for (clock.n = limit->n.min; |
692 | clock.n <= limit->n.max; clock.n++) { | |
693 | for (clock.p1 = limit->p1.min; | |
694 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
695 | int this_err; |
696 | ||
dccbea3b | 697 | pnv_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
698 | if (!intel_PLL_is_valid(to_i915(dev), |
699 | limit, | |
1b894b59 | 700 | &clock)) |
79e53945 | 701 | continue; |
cec2f356 SP |
702 | if (match_clock && |
703 | clock.p != match_clock->p) | |
704 | continue; | |
79e53945 JB |
705 | |
706 | this_err = abs(clock.dot - target); | |
707 | if (this_err < err) { | |
708 | *best_clock = clock; | |
709 | err = this_err; | |
710 | } | |
711 | } | |
712 | } | |
713 | } | |
714 | } | |
715 | ||
716 | return (err != target); | |
717 | } | |
718 | ||
997c030c ACO |
719 | /* |
720 | * Returns a set of divisors for the desired target clock with the given | |
721 | * refclk, or FALSE. The returned values represent the clock equation: | |
722 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
70e8aa21 ACO |
723 | * |
724 | * Target and reference clocks are specified in kHz. | |
725 | * | |
726 | * If match_clock is provided, then best_clock P divider must match the P | |
727 | * divider from @match_clock used for LVDS downclocking. | |
997c030c | 728 | */ |
d4906093 | 729 | static bool |
1b6f4958 | 730 | g4x_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 731 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
732 | int target, int refclk, struct dpll *match_clock, |
733 | struct dpll *best_clock) | |
d4906093 | 734 | { |
3b1429d9 | 735 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 736 | struct dpll clock; |
d4906093 | 737 | int max_n; |
3b1429d9 | 738 | bool found = false; |
6ba770dc AJ |
739 | /* approximately equals target * 0.00585 */ |
740 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
741 | |
742 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
743 | |
744 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
745 | ||
d4906093 | 746 | max_n = limit->n.max; |
f77f13e2 | 747 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 748 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 749 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
750 | for (clock.m1 = limit->m1.max; |
751 | clock.m1 >= limit->m1.min; clock.m1--) { | |
752 | for (clock.m2 = limit->m2.max; | |
753 | clock.m2 >= limit->m2.min; clock.m2--) { | |
754 | for (clock.p1 = limit->p1.max; | |
755 | clock.p1 >= limit->p1.min; clock.p1--) { | |
756 | int this_err; | |
757 | ||
dccbea3b | 758 | i9xx_calc_dpll_params(refclk, &clock); |
e2d214ae TU |
759 | if (!intel_PLL_is_valid(to_i915(dev), |
760 | limit, | |
1b894b59 | 761 | &clock)) |
d4906093 | 762 | continue; |
1b894b59 CW |
763 | |
764 | this_err = abs(clock.dot - target); | |
d4906093 ML |
765 | if (this_err < err_most) { |
766 | *best_clock = clock; | |
767 | err_most = this_err; | |
768 | max_n = clock.n; | |
769 | found = true; | |
770 | } | |
771 | } | |
772 | } | |
773 | } | |
774 | } | |
2c07245f ZW |
775 | return found; |
776 | } | |
777 | ||
d5dd62bd ID |
778 | /* |
779 | * Check if the calculated PLL configuration is more optimal compared to the | |
780 | * best configuration and error found so far. Return the calculated error. | |
781 | */ | |
782 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
9e2c8475 ACO |
783 | const struct dpll *calculated_clock, |
784 | const struct dpll *best_clock, | |
d5dd62bd ID |
785 | unsigned int best_error_ppm, |
786 | unsigned int *error_ppm) | |
787 | { | |
9ca3ba01 ID |
788 | /* |
789 | * For CHV ignore the error and consider only the P value. | |
790 | * Prefer a bigger P value based on HW requirements. | |
791 | */ | |
920a14b2 | 792 | if (IS_CHERRYVIEW(to_i915(dev))) { |
9ca3ba01 ID |
793 | *error_ppm = 0; |
794 | ||
795 | return calculated_clock->p > best_clock->p; | |
796 | } | |
797 | ||
24be4e46 ID |
798 | if (WARN_ON_ONCE(!target_freq)) |
799 | return false; | |
800 | ||
d5dd62bd ID |
801 | *error_ppm = div_u64(1000000ULL * |
802 | abs(target_freq - calculated_clock->dot), | |
803 | target_freq); | |
804 | /* | |
805 | * Prefer a better P value over a better (smaller) error if the error | |
806 | * is small. Ensure this preference for future configurations too by | |
807 | * setting the error to 0. | |
808 | */ | |
809 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
810 | *error_ppm = 0; | |
811 | ||
812 | return true; | |
813 | } | |
814 | ||
815 | return *error_ppm + 10 < best_error_ppm; | |
816 | } | |
817 | ||
65b3d6a9 ACO |
818 | /* |
819 | * Returns a set of divisors for the desired target clock with the given | |
820 | * refclk, or FALSE. The returned values represent the clock equation: | |
821 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
822 | */ | |
a0c4da24 | 823 | static bool |
1b6f4958 | 824 | vlv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 825 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
826 | int target, int refclk, struct dpll *match_clock, |
827 | struct dpll *best_clock) | |
a0c4da24 | 828 | { |
a93e255f | 829 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 830 | struct drm_device *dev = crtc->base.dev; |
9e2c8475 | 831 | struct dpll clock; |
69e4f900 | 832 | unsigned int bestppm = 1000000; |
27e639bf VS |
833 | /* min update 19.2 MHz */ |
834 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 835 | bool found = false; |
a0c4da24 | 836 | |
6b4bf1c4 VS |
837 | target *= 5; /* fast clock */ |
838 | ||
839 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
840 | |
841 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 842 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 843 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 844 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 845 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 846 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 847 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 848 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 849 | unsigned int ppm; |
69e4f900 | 850 | |
6b4bf1c4 VS |
851 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
852 | refclk * clock.m1); | |
853 | ||
dccbea3b | 854 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 855 | |
e2d214ae TU |
856 | if (!intel_PLL_is_valid(to_i915(dev), |
857 | limit, | |
f01b7962 | 858 | &clock)) |
43b0ac53 VS |
859 | continue; |
860 | ||
d5dd62bd ID |
861 | if (!vlv_PLL_is_optimal(dev, target, |
862 | &clock, | |
863 | best_clock, | |
864 | bestppm, &ppm)) | |
865 | continue; | |
6b4bf1c4 | 866 | |
d5dd62bd ID |
867 | *best_clock = clock; |
868 | bestppm = ppm; | |
869 | found = true; | |
a0c4da24 JB |
870 | } |
871 | } | |
872 | } | |
873 | } | |
a0c4da24 | 874 | |
49e497ef | 875 | return found; |
a0c4da24 | 876 | } |
a4fc5ed6 | 877 | |
65b3d6a9 ACO |
878 | /* |
879 | * Returns a set of divisors for the desired target clock with the given | |
880 | * refclk, or FALSE. The returned values represent the clock equation: | |
881 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
882 | */ | |
ef9348c8 | 883 | static bool |
1b6f4958 | 884 | chv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 885 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
886 | int target, int refclk, struct dpll *match_clock, |
887 | struct dpll *best_clock) | |
ef9348c8 | 888 | { |
a93e255f | 889 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 890 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 891 | unsigned int best_error_ppm; |
9e2c8475 | 892 | struct dpll clock; |
ef9348c8 CML |
893 | uint64_t m2; |
894 | int found = false; | |
895 | ||
896 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 897 | best_error_ppm = 1000000; |
ef9348c8 CML |
898 | |
899 | /* | |
900 | * Based on hardware doc, the n always set to 1, and m1 always | |
901 | * set to 2. If requires to support 200Mhz refclk, we need to | |
902 | * revisit this because n may not 1 anymore. | |
903 | */ | |
904 | clock.n = 1, clock.m1 = 2; | |
905 | target *= 5; /* fast clock */ | |
906 | ||
907 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
908 | for (clock.p2 = limit->p2.p2_fast; | |
909 | clock.p2 >= limit->p2.p2_slow; | |
910 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 911 | unsigned int error_ppm; |
ef9348c8 CML |
912 | |
913 | clock.p = clock.p1 * clock.p2; | |
914 | ||
915 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
916 | clock.n) << 22, refclk * clock.m1); | |
917 | ||
918 | if (m2 > INT_MAX/clock.m1) | |
919 | continue; | |
920 | ||
921 | clock.m2 = m2; | |
922 | ||
dccbea3b | 923 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 | 924 | |
e2d214ae | 925 | if (!intel_PLL_is_valid(to_i915(dev), limit, &clock)) |
ef9348c8 CML |
926 | continue; |
927 | ||
9ca3ba01 ID |
928 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
929 | best_error_ppm, &error_ppm)) | |
930 | continue; | |
931 | ||
932 | *best_clock = clock; | |
933 | best_error_ppm = error_ppm; | |
934 | found = true; | |
ef9348c8 CML |
935 | } |
936 | } | |
937 | ||
938 | return found; | |
939 | } | |
940 | ||
5ab7b0b7 | 941 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
9e2c8475 | 942 | struct dpll *best_clock) |
5ab7b0b7 | 943 | { |
65b3d6a9 | 944 | int refclk = 100000; |
1b6f4958 | 945 | const struct intel_limit *limit = &intel_limits_bxt; |
5ab7b0b7 | 946 | |
65b3d6a9 | 947 | return chv_find_best_dpll(limit, crtc_state, |
5ab7b0b7 ID |
948 | target_clock, refclk, NULL, best_clock); |
949 | } | |
950 | ||
525b9311 | 951 | bool intel_crtc_active(struct intel_crtc *crtc) |
20ddf665 | 952 | { |
20ddf665 VS |
953 | /* Be paranoid as we can arrive here with only partial |
954 | * state retrieved from the hardware during setup. | |
955 | * | |
241bfc38 | 956 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
957 | * as Haswell has gained clock readout/fastboot support. |
958 | * | |
66e514c1 | 959 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 960 | * properly reconstruct framebuffers. |
c3d1f436 MR |
961 | * |
962 | * FIXME: The intel_crtc->active here should be switched to | |
963 | * crtc->state->active once we have proper CRTC states wired up | |
964 | * for atomic. | |
20ddf665 | 965 | */ |
525b9311 VS |
966 | return crtc->active && crtc->base.primary->state->fb && |
967 | crtc->config->base.adjusted_mode.crtc_clock; | |
20ddf665 VS |
968 | } |
969 | ||
a5c961d1 PZ |
970 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
971 | enum pipe pipe) | |
972 | { | |
98187836 | 973 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
a5c961d1 | 974 | |
e2af48c6 | 975 | return crtc->config->cpu_transcoder; |
a5c961d1 PZ |
976 | } |
977 | ||
6315b5d3 | 978 | static bool pipe_dsl_stopped(struct drm_i915_private *dev_priv, enum pipe pipe) |
fbf49ea2 | 979 | { |
f0f59a00 | 980 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
981 | u32 line1, line2; |
982 | u32 line_mask; | |
983 | ||
5db94019 | 984 | if (IS_GEN2(dev_priv)) |
fbf49ea2 VS |
985 | line_mask = DSL_LINEMASK_GEN2; |
986 | else | |
987 | line_mask = DSL_LINEMASK_GEN3; | |
988 | ||
989 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 990 | msleep(5); |
fbf49ea2 VS |
991 | line2 = I915_READ(reg) & line_mask; |
992 | ||
993 | return line1 == line2; | |
994 | } | |
995 | ||
ab7ad7f6 KP |
996 | /* |
997 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 998 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
999 | * |
1000 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1001 | * spinning on the vblank interrupt status bit, since we won't actually | |
1002 | * see an interrupt when the pipe is disabled. | |
1003 | * | |
ab7ad7f6 KP |
1004 | * On Gen4 and above: |
1005 | * wait for the pipe register state bit to turn off | |
1006 | * | |
1007 | * Otherwise: | |
1008 | * wait for the display line value to settle (it usually | |
1009 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1010 | * |
9d0498a2 | 1011 | */ |
575f7ab7 | 1012 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1013 | { |
6315b5d3 | 1014 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 1015 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1016 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 | 1017 | |
6315b5d3 | 1018 | if (INTEL_GEN(dev_priv) >= 4) { |
f0f59a00 | 1019 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1020 | |
1021 | /* Wait for the Pipe State to go off */ | |
b8511f53 CW |
1022 | if (intel_wait_for_register(dev_priv, |
1023 | reg, I965_PIPECONF_ACTIVE, 0, | |
1024 | 100)) | |
284637d9 | 1025 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1026 | } else { |
ab7ad7f6 | 1027 | /* Wait for the display line to settle */ |
6315b5d3 | 1028 | if (wait_for(pipe_dsl_stopped(dev_priv, pipe), 100)) |
284637d9 | 1029 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1030 | } |
79e53945 JB |
1031 | } |
1032 | ||
b24e7179 | 1033 | /* Only for pre-ILK configs */ |
55607e8a DV |
1034 | void assert_pll(struct drm_i915_private *dev_priv, |
1035 | enum pipe pipe, bool state) | |
b24e7179 | 1036 | { |
b24e7179 JB |
1037 | u32 val; |
1038 | bool cur_state; | |
1039 | ||
649636ef | 1040 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1041 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1042 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1043 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1044 | onoff(state), onoff(cur_state)); |
b24e7179 | 1045 | } |
b24e7179 | 1046 | |
23538ef1 | 1047 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
8563b1e8 | 1048 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
23538ef1 JN |
1049 | { |
1050 | u32 val; | |
1051 | bool cur_state; | |
1052 | ||
a580516d | 1053 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1054 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1055 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1056 | |
1057 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1058 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1059 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1060 | onoff(state), onoff(cur_state)); |
23538ef1 | 1061 | } |
23538ef1 | 1062 | |
040484af JB |
1063 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1064 | enum pipe pipe, bool state) | |
1065 | { | |
040484af | 1066 | bool cur_state; |
ad80a810 PZ |
1067 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1068 | pipe); | |
040484af | 1069 | |
2d1fe073 | 1070 | if (HAS_DDI(dev_priv)) { |
affa9354 | 1071 | /* DDI does not have a specific FDI_TX register */ |
649636ef | 1072 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1073 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1074 | } else { |
649636ef | 1075 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1076 | cur_state = !!(val & FDI_TX_ENABLE); |
1077 | } | |
e2c719b7 | 1078 | I915_STATE_WARN(cur_state != state, |
040484af | 1079 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1080 | onoff(state), onoff(cur_state)); |
040484af JB |
1081 | } |
1082 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1083 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1084 | ||
1085 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1086 | enum pipe pipe, bool state) | |
1087 | { | |
040484af JB |
1088 | u32 val; |
1089 | bool cur_state; | |
1090 | ||
649636ef | 1091 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1092 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1093 | I915_STATE_WARN(cur_state != state, |
040484af | 1094 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1095 | onoff(state), onoff(cur_state)); |
040484af JB |
1096 | } |
1097 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1098 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1099 | ||
1100 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1101 | enum pipe pipe) | |
1102 | { | |
040484af JB |
1103 | u32 val; |
1104 | ||
1105 | /* ILK FDI PLL is always enabled */ | |
7e22dbbb | 1106 | if (IS_GEN5(dev_priv)) |
040484af JB |
1107 | return; |
1108 | ||
bf507ef7 | 1109 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
2d1fe073 | 1110 | if (HAS_DDI(dev_priv)) |
bf507ef7 ED |
1111 | return; |
1112 | ||
649636ef | 1113 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1114 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1115 | } |
1116 | ||
55607e8a DV |
1117 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1118 | enum pipe pipe, bool state) | |
040484af | 1119 | { |
040484af | 1120 | u32 val; |
55607e8a | 1121 | bool cur_state; |
040484af | 1122 | |
649636ef | 1123 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1124 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1125 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1126 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1127 | onoff(state), onoff(cur_state)); |
040484af JB |
1128 | } |
1129 | ||
4f8036a2 | 1130 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, enum pipe pipe) |
ea0760cf | 1131 | { |
f0f59a00 | 1132 | i915_reg_t pp_reg; |
ea0760cf JB |
1133 | u32 val; |
1134 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1135 | bool locked = true; |
ea0760cf | 1136 | |
4f8036a2 | 1137 | if (WARN_ON(HAS_DDI(dev_priv))) |
bedd4dba JN |
1138 | return; |
1139 | ||
4f8036a2 | 1140 | if (HAS_PCH_SPLIT(dev_priv)) { |
bedd4dba JN |
1141 | u32 port_sel; |
1142 | ||
44cb734c ID |
1143 | pp_reg = PP_CONTROL(0); |
1144 | port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; | |
bedd4dba JN |
1145 | |
1146 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1147 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1148 | panel_pipe = PIPE_B; | |
1149 | /* XXX: else fix for eDP */ | |
4f8036a2 | 1150 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
bedd4dba | 1151 | /* presumably write lock depends on pipe, not port select */ |
44cb734c | 1152 | pp_reg = PP_CONTROL(pipe); |
bedd4dba | 1153 | panel_pipe = pipe; |
ea0760cf | 1154 | } else { |
44cb734c | 1155 | pp_reg = PP_CONTROL(0); |
bedd4dba JN |
1156 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1157 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1158 | } |
1159 | ||
1160 | val = I915_READ(pp_reg); | |
1161 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1162 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1163 | locked = false; |
1164 | ||
e2c719b7 | 1165 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1166 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1167 | pipe_name(pipe)); |
ea0760cf JB |
1168 | } |
1169 | ||
93ce0ba6 JN |
1170 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1171 | enum pipe pipe, bool state) | |
1172 | { | |
93ce0ba6 JN |
1173 | bool cur_state; |
1174 | ||
2a307c2e | 1175 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
0b87c24e | 1176 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1177 | else |
5efb3e28 | 1178 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1179 | |
e2c719b7 | 1180 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1181 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1182 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1183 | } |
1184 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1185 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1186 | ||
b840d907 JB |
1187 | void assert_pipe(struct drm_i915_private *dev_priv, |
1188 | enum pipe pipe, bool state) | |
b24e7179 | 1189 | { |
63d7bbe9 | 1190 | bool cur_state; |
702e7a56 PZ |
1191 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1192 | pipe); | |
4feed0eb | 1193 | enum intel_display_power_domain power_domain; |
b24e7179 | 1194 | |
b6b5d049 VS |
1195 | /* if we need the pipe quirk it must be always on */ |
1196 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1197 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1198 | state = true; |
1199 | ||
4feed0eb ID |
1200 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1201 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
649636ef | 1202 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 | 1203 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb ID |
1204 | |
1205 | intel_display_power_put(dev_priv, power_domain); | |
1206 | } else { | |
1207 | cur_state = false; | |
69310161 PZ |
1208 | } |
1209 | ||
e2c719b7 | 1210 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1211 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1212 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1213 | } |
1214 | ||
931872fc CW |
1215 | static void assert_plane(struct drm_i915_private *dev_priv, |
1216 | enum plane plane, bool state) | |
b24e7179 | 1217 | { |
b24e7179 | 1218 | u32 val; |
931872fc | 1219 | bool cur_state; |
b24e7179 | 1220 | |
649636ef | 1221 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1222 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1223 | I915_STATE_WARN(cur_state != state, |
931872fc | 1224 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1225 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1226 | } |
1227 | ||
931872fc CW |
1228 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1229 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1230 | ||
b24e7179 JB |
1231 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1232 | enum pipe pipe) | |
1233 | { | |
649636ef | 1234 | int i; |
b24e7179 | 1235 | |
653e1026 | 1236 | /* Primary planes are fixed to pipes on gen4+ */ |
6315b5d3 | 1237 | if (INTEL_GEN(dev_priv) >= 4) { |
649636ef | 1238 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1239 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1240 | "plane %c assertion failure, should be disabled but not\n", |
1241 | plane_name(pipe)); | |
19ec1358 | 1242 | return; |
28c05794 | 1243 | } |
19ec1358 | 1244 | |
b24e7179 | 1245 | /* Need to check both planes against the pipe */ |
055e393f | 1246 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1247 | u32 val = I915_READ(DSPCNTR(i)); |
1248 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1249 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1250 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1251 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1252 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1253 | } |
1254 | } | |
1255 | ||
19332d7a JB |
1256 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1257 | enum pipe pipe) | |
1258 | { | |
649636ef | 1259 | int sprite; |
19332d7a | 1260 | |
6315b5d3 | 1261 | if (INTEL_GEN(dev_priv) >= 9) { |
3bdcfc0c | 1262 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1263 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1264 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1265 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1266 | sprite, pipe_name(pipe)); | |
1267 | } | |
920a14b2 | 1268 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
3bdcfc0c | 1269 | for_each_sprite(dev_priv, pipe, sprite) { |
83c04a62 | 1270 | u32 val = I915_READ(SPCNTR(pipe, PLANE_SPRITE0 + sprite)); |
e2c719b7 | 1271 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1272 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1273 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef | 1274 | } |
6315b5d3 | 1275 | } else if (INTEL_GEN(dev_priv) >= 7) { |
649636ef | 1276 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1277 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1278 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1279 | plane_name(pipe), pipe_name(pipe)); |
6315b5d3 | 1280 | } else if (INTEL_GEN(dev_priv) >= 5) { |
649636ef | 1281 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1282 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1283 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1284 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1285 | } |
1286 | } | |
1287 | ||
08c71e5e VS |
1288 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1289 | { | |
e2c719b7 | 1290 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1291 | drm_crtc_vblank_put(crtc); |
1292 | } | |
1293 | ||
7abd4b35 ACO |
1294 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1295 | enum pipe pipe) | |
92f2584a | 1296 | { |
92f2584a JB |
1297 | u32 val; |
1298 | bool enabled; | |
1299 | ||
649636ef | 1300 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1301 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1302 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1303 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1304 | pipe_name(pipe)); | |
92f2584a JB |
1305 | } |
1306 | ||
4e634389 KP |
1307 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1308 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1309 | { |
1310 | if ((val & DP_PORT_EN) == 0) | |
1311 | return false; | |
1312 | ||
2d1fe073 | 1313 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 | 1314 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1315 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1316 | return false; | |
2d1fe073 | 1317 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1318 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
1319 | return false; | |
f0575e92 KP |
1320 | } else { |
1321 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1322 | return false; | |
1323 | } | |
1324 | return true; | |
1325 | } | |
1326 | ||
1519b995 KP |
1327 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1328 | enum pipe pipe, u32 val) | |
1329 | { | |
dc0fa718 | 1330 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1331 | return false; |
1332 | ||
2d1fe073 | 1333 | if (HAS_PCH_CPT(dev_priv)) { |
dc0fa718 | 1334 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1335 | return false; |
2d1fe073 | 1336 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1337 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) |
1338 | return false; | |
1519b995 | 1339 | } else { |
dc0fa718 | 1340 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1341 | return false; |
1342 | } | |
1343 | return true; | |
1344 | } | |
1345 | ||
1346 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1347 | enum pipe pipe, u32 val) | |
1348 | { | |
1349 | if ((val & LVDS_PORT_EN) == 0) | |
1350 | return false; | |
1351 | ||
2d1fe073 | 1352 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1353 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1354 | return false; | |
1355 | } else { | |
1356 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1357 | return false; | |
1358 | } | |
1359 | return true; | |
1360 | } | |
1361 | ||
1362 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1363 | enum pipe pipe, u32 val) | |
1364 | { | |
1365 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1366 | return false; | |
2d1fe073 | 1367 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1368 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1369 | return false; | |
1370 | } else { | |
1371 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1372 | return false; | |
1373 | } | |
1374 | return true; | |
1375 | } | |
1376 | ||
291906f1 | 1377 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1378 | enum pipe pipe, i915_reg_t reg, |
1379 | u32 port_sel) | |
291906f1 | 1380 | { |
47a05eca | 1381 | u32 val = I915_READ(reg); |
e2c719b7 | 1382 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1383 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1384 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1385 | |
2d1fe073 | 1386 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1387 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1388 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1389 | } |
1390 | ||
1391 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1392 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1393 | { |
47a05eca | 1394 | u32 val = I915_READ(reg); |
e2c719b7 | 1395 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1396 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1397 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1398 | |
2d1fe073 | 1399 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1400 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1401 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1402 | } |
1403 | ||
1404 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1405 | enum pipe pipe) | |
1406 | { | |
291906f1 | 1407 | u32 val; |
291906f1 | 1408 | |
f0575e92 KP |
1409 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1410 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1411 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1412 | |
649636ef | 1413 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1414 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1415 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1416 | pipe_name(pipe)); |
291906f1 | 1417 | |
649636ef | 1418 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1419 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1420 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1421 | pipe_name(pipe)); |
291906f1 | 1422 | |
e2debe91 PZ |
1423 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1424 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1425 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1426 | } |
1427 | ||
cd2d34d9 VS |
1428 | static void _vlv_enable_pll(struct intel_crtc *crtc, |
1429 | const struct intel_crtc_state *pipe_config) | |
1430 | { | |
1431 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1432 | enum pipe pipe = crtc->pipe; | |
1433 | ||
1434 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); | |
1435 | POSTING_READ(DPLL(pipe)); | |
1436 | udelay(150); | |
1437 | ||
2c30b43b CW |
1438 | if (intel_wait_for_register(dev_priv, |
1439 | DPLL(pipe), | |
1440 | DPLL_LOCK_VLV, | |
1441 | DPLL_LOCK_VLV, | |
1442 | 1)) | |
cd2d34d9 VS |
1443 | DRM_ERROR("DPLL %d failed to lock\n", pipe); |
1444 | } | |
1445 | ||
d288f65f | 1446 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1447 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1448 | { |
cd2d34d9 | 1449 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1450 | enum pipe pipe = crtc->pipe; |
87442f73 | 1451 | |
8bd3f301 | 1452 | assert_pipe_disabled(dev_priv, pipe); |
87442f73 | 1453 | |
87442f73 | 1454 | /* PLL is protected by panel, make sure we can write it */ |
7d1a83cb | 1455 | assert_panel_unlocked(dev_priv, pipe); |
87442f73 | 1456 | |
cd2d34d9 VS |
1457 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) |
1458 | _vlv_enable_pll(crtc, pipe_config); | |
426115cf | 1459 | |
8bd3f301 VS |
1460 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
1461 | POSTING_READ(DPLL_MD(pipe)); | |
87442f73 DV |
1462 | } |
1463 | ||
cd2d34d9 VS |
1464 | |
1465 | static void _chv_enable_pll(struct intel_crtc *crtc, | |
1466 | const struct intel_crtc_state *pipe_config) | |
9d556c99 | 1467 | { |
cd2d34d9 | 1468 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1469 | enum pipe pipe = crtc->pipe; |
9d556c99 | 1470 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9d556c99 CML |
1471 | u32 tmp; |
1472 | ||
a580516d | 1473 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1474 | |
1475 | /* Enable back the 10bit clock to display controller */ | |
1476 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1477 | tmp |= DPIO_DCLKP_EN; | |
1478 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1479 | ||
54433e91 VS |
1480 | mutex_unlock(&dev_priv->sb_lock); |
1481 | ||
9d556c99 CML |
1482 | /* |
1483 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1484 | */ | |
1485 | udelay(1); | |
1486 | ||
1487 | /* Enable PLL */ | |
d288f65f | 1488 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1489 | |
1490 | /* Check PLL is locked */ | |
6b18826a CW |
1491 | if (intel_wait_for_register(dev_priv, |
1492 | DPLL(pipe), DPLL_LOCK_VLV, DPLL_LOCK_VLV, | |
1493 | 1)) | |
9d556c99 | 1494 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
cd2d34d9 VS |
1495 | } |
1496 | ||
1497 | static void chv_enable_pll(struct intel_crtc *crtc, | |
1498 | const struct intel_crtc_state *pipe_config) | |
1499 | { | |
1500 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1501 | enum pipe pipe = crtc->pipe; | |
1502 | ||
1503 | assert_pipe_disabled(dev_priv, pipe); | |
1504 | ||
1505 | /* PLL is protected by panel, make sure we can write it */ | |
1506 | assert_panel_unlocked(dev_priv, pipe); | |
1507 | ||
1508 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) | |
1509 | _chv_enable_pll(crtc, pipe_config); | |
9d556c99 | 1510 | |
c231775c VS |
1511 | if (pipe != PIPE_A) { |
1512 | /* | |
1513 | * WaPixelRepeatModeFixForC0:chv | |
1514 | * | |
1515 | * DPLLCMD is AWOL. Use chicken bits to propagate | |
1516 | * the value from DPLLBMD to either pipe B or C. | |
1517 | */ | |
1518 | I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C); | |
1519 | I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); | |
1520 | I915_WRITE(CBR4_VLV, 0); | |
1521 | dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; | |
1522 | ||
1523 | /* | |
1524 | * DPLLB VGA mode also seems to cause problems. | |
1525 | * We should always have it disabled. | |
1526 | */ | |
1527 | WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); | |
1528 | } else { | |
1529 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); | |
1530 | POSTING_READ(DPLL_MD(pipe)); | |
1531 | } | |
9d556c99 CML |
1532 | } |
1533 | ||
6315b5d3 | 1534 | static int intel_num_dvo_pipes(struct drm_i915_private *dev_priv) |
1c4e0274 VS |
1535 | { |
1536 | struct intel_crtc *crtc; | |
1537 | int count = 0; | |
1538 | ||
6315b5d3 | 1539 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
3538b9df | 1540 | count += crtc->base.state->active && |
2d84d2b3 VS |
1541 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO); |
1542 | } | |
1c4e0274 VS |
1543 | |
1544 | return count; | |
1545 | } | |
1546 | ||
66e3d5c0 | 1547 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1548 | { |
6315b5d3 | 1549 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
f0f59a00 | 1550 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1551 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1552 | |
66e3d5c0 | 1553 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1554 | |
63d7bbe9 | 1555 | /* PLL is protected by panel, make sure we can write it */ |
50a0bc90 | 1556 | if (IS_MOBILE(dev_priv) && !IS_I830(dev_priv)) |
66e3d5c0 | 1557 | assert_panel_unlocked(dev_priv, crtc->pipe); |
63d7bbe9 | 1558 | |
1c4e0274 | 1559 | /* Enable DVO 2x clock on both PLLs if necessary */ |
6315b5d3 | 1560 | if (IS_I830(dev_priv) && intel_num_dvo_pipes(dev_priv) > 0) { |
1c4e0274 VS |
1561 | /* |
1562 | * It appears to be important that we don't enable this | |
1563 | * for the current pipe before otherwise configuring the | |
1564 | * PLL. No idea how this should be handled if multiple | |
1565 | * DVO outputs are enabled simultaneosly. | |
1566 | */ | |
1567 | dpll |= DPLL_DVO_2X_MODE; | |
1568 | I915_WRITE(DPLL(!crtc->pipe), | |
1569 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1570 | } | |
66e3d5c0 | 1571 | |
c2b63374 VS |
1572 | /* |
1573 | * Apparently we need to have VGA mode enabled prior to changing | |
1574 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1575 | * dividers, even though the register value does change. | |
1576 | */ | |
1577 | I915_WRITE(reg, 0); | |
1578 | ||
8e7a65aa VS |
1579 | I915_WRITE(reg, dpll); |
1580 | ||
66e3d5c0 DV |
1581 | /* Wait for the clocks to stabilize. */ |
1582 | POSTING_READ(reg); | |
1583 | udelay(150); | |
1584 | ||
6315b5d3 | 1585 | if (INTEL_GEN(dev_priv) >= 4) { |
66e3d5c0 | 1586 | I915_WRITE(DPLL_MD(crtc->pipe), |
6e3c9717 | 1587 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1588 | } else { |
1589 | /* The pixel multiplier can only be updated once the | |
1590 | * DPLL is enabled and the clocks are stable. | |
1591 | * | |
1592 | * So write it again. | |
1593 | */ | |
1594 | I915_WRITE(reg, dpll); | |
1595 | } | |
63d7bbe9 JB |
1596 | |
1597 | /* We do this three times for luck */ | |
66e3d5c0 | 1598 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1599 | POSTING_READ(reg); |
1600 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1601 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1602 | POSTING_READ(reg); |
1603 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1604 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1605 | POSTING_READ(reg); |
1606 | udelay(150); /* wait for warmup */ | |
1607 | } | |
1608 | ||
1609 | /** | |
50b44a44 | 1610 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1611 | * @dev_priv: i915 private structure |
1612 | * @pipe: pipe PLL to disable | |
1613 | * | |
1614 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1615 | * | |
1616 | * Note! This is for pre-ILK only. | |
1617 | */ | |
1c4e0274 | 1618 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1619 | { |
6315b5d3 | 1620 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1c4e0274 VS |
1621 | enum pipe pipe = crtc->pipe; |
1622 | ||
1623 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
50a0bc90 | 1624 | if (IS_I830(dev_priv) && |
2d84d2b3 | 1625 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DVO) && |
6315b5d3 | 1626 | !intel_num_dvo_pipes(dev_priv)) { |
1c4e0274 VS |
1627 | I915_WRITE(DPLL(PIPE_B), |
1628 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1629 | I915_WRITE(DPLL(PIPE_A), | |
1630 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1631 | } | |
1632 | ||
b6b5d049 VS |
1633 | /* Don't disable pipe or pipe PLLs if needed */ |
1634 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1635 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1636 | return; |
1637 | ||
1638 | /* Make sure the pipe isn't still relying on us */ | |
1639 | assert_pipe_disabled(dev_priv, pipe); | |
1640 | ||
b8afb911 | 1641 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1642 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1643 | } |
1644 | ||
f6071166 JB |
1645 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1646 | { | |
b8afb911 | 1647 | u32 val; |
f6071166 JB |
1648 | |
1649 | /* Make sure the pipe isn't still relying on us */ | |
1650 | assert_pipe_disabled(dev_priv, pipe); | |
1651 | ||
03ed5cbf VS |
1652 | val = DPLL_INTEGRATED_REF_CLK_VLV | |
1653 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
1654 | if (pipe != PIPE_A) | |
1655 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1656 | ||
f6071166 JB |
1657 | I915_WRITE(DPLL(pipe), val); |
1658 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1659 | } |
1660 | ||
1661 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1662 | { | |
d752048d | 1663 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1664 | u32 val; |
1665 | ||
a11b0703 VS |
1666 | /* Make sure the pipe isn't still relying on us */ |
1667 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1668 | |
60bfe44f VS |
1669 | val = DPLL_SSC_REF_CLK_CHV | |
1670 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1671 | if (pipe != PIPE_A) |
1672 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
03ed5cbf | 1673 | |
a11b0703 VS |
1674 | I915_WRITE(DPLL(pipe), val); |
1675 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1676 | |
a580516d | 1677 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1678 | |
1679 | /* Disable 10bit clock to display controller */ | |
1680 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1681 | val &= ~DPIO_DCLKP_EN; | |
1682 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1683 | ||
a580516d | 1684 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1685 | } |
1686 | ||
e4607fcf | 1687 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1688 | struct intel_digital_port *dport, |
1689 | unsigned int expected_mask) | |
89b667f8 JB |
1690 | { |
1691 | u32 port_mask; | |
f0f59a00 | 1692 | i915_reg_t dpll_reg; |
89b667f8 | 1693 | |
e4607fcf CML |
1694 | switch (dport->port) { |
1695 | case PORT_B: | |
89b667f8 | 1696 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1697 | dpll_reg = DPLL(0); |
e4607fcf CML |
1698 | break; |
1699 | case PORT_C: | |
89b667f8 | 1700 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1701 | dpll_reg = DPLL(0); |
9b6de0a1 | 1702 | expected_mask <<= 4; |
00fc31b7 CML |
1703 | break; |
1704 | case PORT_D: | |
1705 | port_mask = DPLL_PORTD_READY_MASK; | |
1706 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1707 | break; |
1708 | default: | |
1709 | BUG(); | |
1710 | } | |
89b667f8 | 1711 | |
370004d3 CW |
1712 | if (intel_wait_for_register(dev_priv, |
1713 | dpll_reg, port_mask, expected_mask, | |
1714 | 1000)) | |
9b6de0a1 VS |
1715 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", |
1716 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1717 | } |
1718 | ||
b8a4f404 PZ |
1719 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1720 | enum pipe pipe) | |
040484af | 1721 | { |
98187836 VS |
1722 | struct intel_crtc *intel_crtc = intel_get_crtc_for_pipe(dev_priv, |
1723 | pipe); | |
f0f59a00 VS |
1724 | i915_reg_t reg; |
1725 | uint32_t val, pipeconf_val; | |
040484af | 1726 | |
040484af | 1727 | /* Make sure PCH DPLL is enabled */ |
8106ddbd | 1728 | assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll); |
040484af JB |
1729 | |
1730 | /* FDI must be feeding us bits for PCH ports */ | |
1731 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1732 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1733 | ||
6e266956 | 1734 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 DV |
1735 | /* Workaround: Set the timing override bit before enabling the |
1736 | * pch transcoder. */ | |
1737 | reg = TRANS_CHICKEN2(pipe); | |
1738 | val = I915_READ(reg); | |
1739 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1740 | I915_WRITE(reg, val); | |
59c859d6 | 1741 | } |
23670b32 | 1742 | |
ab9412ba | 1743 | reg = PCH_TRANSCONF(pipe); |
040484af | 1744 | val = I915_READ(reg); |
5f7f726d | 1745 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c | 1746 | |
2d1fe073 | 1747 | if (HAS_PCH_IBX(dev_priv)) { |
e9bcff5c | 1748 | /* |
c5de7c6f VS |
1749 | * Make the BPC in transcoder be consistent with |
1750 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1751 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1752 | */ |
dfd07d72 | 1753 | val &= ~PIPECONF_BPC_MASK; |
2d84d2b3 | 1754 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_HDMI)) |
c5de7c6f VS |
1755 | val |= PIPECONF_8BPC; |
1756 | else | |
1757 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1758 | } |
5f7f726d PZ |
1759 | |
1760 | val &= ~TRANS_INTERLACE_MASK; | |
1761 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
2d1fe073 | 1762 | if (HAS_PCH_IBX(dev_priv) && |
2d84d2b3 | 1763 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1764 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1765 | else | |
1766 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1767 | else |
1768 | val |= TRANS_PROGRESSIVE; | |
1769 | ||
040484af | 1770 | I915_WRITE(reg, val | TRANS_ENABLE); |
650fbd84 CW |
1771 | if (intel_wait_for_register(dev_priv, |
1772 | reg, TRANS_STATE_ENABLE, TRANS_STATE_ENABLE, | |
1773 | 100)) | |
4bb6f1f3 | 1774 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1775 | } |
1776 | ||
8fb033d7 | 1777 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1778 | enum transcoder cpu_transcoder) |
040484af | 1779 | { |
8fb033d7 | 1780 | u32 val, pipeconf_val; |
8fb033d7 | 1781 | |
8fb033d7 | 1782 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1783 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1784 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1785 | |
223a6fdf | 1786 | /* Workaround: set timing override bit. */ |
36c0d0cf | 1787 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1788 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1789 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 1790 | |
25f3ef11 | 1791 | val = TRANS_ENABLE; |
937bb610 | 1792 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1793 | |
9a76b1c6 PZ |
1794 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1795 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1796 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1797 | else |
1798 | val |= TRANS_PROGRESSIVE; | |
1799 | ||
ab9412ba | 1800 | I915_WRITE(LPT_TRANSCONF, val); |
d9f96244 CW |
1801 | if (intel_wait_for_register(dev_priv, |
1802 | LPT_TRANSCONF, | |
1803 | TRANS_STATE_ENABLE, | |
1804 | TRANS_STATE_ENABLE, | |
1805 | 100)) | |
937bb610 | 1806 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1807 | } |
1808 | ||
b8a4f404 PZ |
1809 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1810 | enum pipe pipe) | |
040484af | 1811 | { |
f0f59a00 VS |
1812 | i915_reg_t reg; |
1813 | uint32_t val; | |
040484af JB |
1814 | |
1815 | /* FDI relies on the transcoder */ | |
1816 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1817 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1818 | ||
291906f1 JB |
1819 | /* Ports must be off as well */ |
1820 | assert_pch_ports_disabled(dev_priv, pipe); | |
1821 | ||
ab9412ba | 1822 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1823 | val = I915_READ(reg); |
1824 | val &= ~TRANS_ENABLE; | |
1825 | I915_WRITE(reg, val); | |
1826 | /* wait for PCH transcoder off, transcoder state */ | |
a7d04662 CW |
1827 | if (intel_wait_for_register(dev_priv, |
1828 | reg, TRANS_STATE_ENABLE, 0, | |
1829 | 50)) | |
4bb6f1f3 | 1830 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 1831 | |
6e266956 | 1832 | if (HAS_PCH_CPT(dev_priv)) { |
23670b32 DV |
1833 | /* Workaround: Clear the timing override chicken bit again. */ |
1834 | reg = TRANS_CHICKEN2(pipe); | |
1835 | val = I915_READ(reg); | |
1836 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1837 | I915_WRITE(reg, val); | |
1838 | } | |
040484af JB |
1839 | } |
1840 | ||
b7076546 | 1841 | void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1842 | { |
8fb033d7 PZ |
1843 | u32 val; |
1844 | ||
ab9412ba | 1845 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1846 | val &= ~TRANS_ENABLE; |
ab9412ba | 1847 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1848 | /* wait for PCH transcoder off, transcoder state */ |
dfdb4749 CW |
1849 | if (intel_wait_for_register(dev_priv, |
1850 | LPT_TRANSCONF, TRANS_STATE_ENABLE, 0, | |
1851 | 50)) | |
8a52fd9f | 1852 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1853 | |
1854 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 1855 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1856 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1857 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
1858 | } |
1859 | ||
65f2130c VS |
1860 | enum transcoder intel_crtc_pch_transcoder(struct intel_crtc *crtc) |
1861 | { | |
1862 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1863 | ||
1864 | WARN_ON(!crtc->config->has_pch_encoder); | |
1865 | ||
1866 | if (HAS_PCH_LPT(dev_priv)) | |
1867 | return TRANSCODER_A; | |
1868 | else | |
1869 | return (enum transcoder) crtc->pipe; | |
1870 | } | |
1871 | ||
b24e7179 | 1872 | /** |
309cfea8 | 1873 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1874 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1875 | * |
0372264a | 1876 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1877 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1878 | */ |
e1fdc473 | 1879 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1880 | { |
0372264a | 1881 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 1882 | struct drm_i915_private *dev_priv = to_i915(dev); |
0372264a | 1883 | enum pipe pipe = crtc->pipe; |
1a70a728 | 1884 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
f0f59a00 | 1885 | i915_reg_t reg; |
b24e7179 JB |
1886 | u32 val; |
1887 | ||
9e2ee2dd VS |
1888 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
1889 | ||
58c6eaa2 | 1890 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1891 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1892 | assert_sprites_disabled(dev_priv, pipe); |
1893 | ||
b24e7179 JB |
1894 | /* |
1895 | * A pipe without a PLL won't actually be able to drive bits from | |
1896 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1897 | * need the check. | |
1898 | */ | |
09fa8bb9 | 1899 | if (HAS_GMCH_DISPLAY(dev_priv)) { |
d7edc4e5 | 1900 | if (intel_crtc_has_type(crtc->config, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
1901 | assert_dsi_pll_enabled(dev_priv); |
1902 | else | |
1903 | assert_pll_enabled(dev_priv, pipe); | |
09fa8bb9 | 1904 | } else { |
6e3c9717 | 1905 | if (crtc->config->has_pch_encoder) { |
040484af | 1906 | /* if driving the PCH, we need FDI enabled */ |
65f2130c VS |
1907 | assert_fdi_rx_pll_enabled(dev_priv, |
1908 | (enum pipe) intel_crtc_pch_transcoder(crtc)); | |
1a240d4d DV |
1909 | assert_fdi_tx_pll_enabled(dev_priv, |
1910 | (enum pipe) cpu_transcoder); | |
040484af JB |
1911 | } |
1912 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1913 | } | |
b24e7179 | 1914 | |
702e7a56 | 1915 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1916 | val = I915_READ(reg); |
7ad25d48 | 1917 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
1918 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
1919 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 1920 | return; |
7ad25d48 | 1921 | } |
00d70b15 CW |
1922 | |
1923 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 1924 | POSTING_READ(reg); |
b7792d8b VS |
1925 | |
1926 | /* | |
1927 | * Until the pipe starts DSL will read as 0, which would cause | |
1928 | * an apparent vblank timestamp jump, which messes up also the | |
1929 | * frame count when it's derived from the timestamps. So let's | |
1930 | * wait for the pipe to start properly before we call | |
1931 | * drm_crtc_vblank_on() | |
1932 | */ | |
1933 | if (dev->max_vblank_count == 0 && | |
1934 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
1935 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
1936 | } |
1937 | ||
1938 | /** | |
309cfea8 | 1939 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 1940 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 1941 | * |
575f7ab7 VS |
1942 | * Disable the pipe of @crtc, making sure that various hardware |
1943 | * specific requirements are met, if applicable, e.g. plane | |
1944 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
1945 | * |
1946 | * Will wait until the pipe has shut down before returning. | |
1947 | */ | |
575f7ab7 | 1948 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1949 | { |
fac5e23e | 1950 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
6e3c9717 | 1951 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1952 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 1953 | i915_reg_t reg; |
b24e7179 JB |
1954 | u32 val; |
1955 | ||
9e2ee2dd VS |
1956 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
1957 | ||
b24e7179 JB |
1958 | /* |
1959 | * Make sure planes won't keep trying to pump pixels to us, | |
1960 | * or we might hang the display. | |
1961 | */ | |
1962 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 1963 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 1964 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 1965 | |
702e7a56 | 1966 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1967 | val = I915_READ(reg); |
00d70b15 CW |
1968 | if ((val & PIPECONF_ENABLE) == 0) |
1969 | return; | |
1970 | ||
67adc644 VS |
1971 | /* |
1972 | * Double wide has implications for planes | |
1973 | * so best keep it disabled when not needed. | |
1974 | */ | |
6e3c9717 | 1975 | if (crtc->config->double_wide) |
67adc644 VS |
1976 | val &= ~PIPECONF_DOUBLE_WIDE; |
1977 | ||
1978 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
1979 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
1980 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
1981 | val &= ~PIPECONF_ENABLE; |
1982 | ||
1983 | I915_WRITE(reg, val); | |
1984 | if ((val & PIPECONF_ENABLE) == 0) | |
1985 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
1986 | } |
1987 | ||
832be82f VS |
1988 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
1989 | { | |
1990 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
1991 | } | |
1992 | ||
d88c4afd VS |
1993 | static unsigned int |
1994 | intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane) | |
7b49f948 | 1995 | { |
d88c4afd VS |
1996 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
1997 | unsigned int cpp = fb->format->cpp[plane]; | |
1998 | ||
1999 | switch (fb->modifier) { | |
7b49f948 VS |
2000 | case DRM_FORMAT_MOD_NONE: |
2001 | return cpp; | |
2002 | case I915_FORMAT_MOD_X_TILED: | |
2003 | if (IS_GEN2(dev_priv)) | |
2004 | return 128; | |
2005 | else | |
2006 | return 512; | |
2007 | case I915_FORMAT_MOD_Y_TILED: | |
2008 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2009 | return 128; | |
2010 | else | |
2011 | return 512; | |
2012 | case I915_FORMAT_MOD_Yf_TILED: | |
2013 | switch (cpp) { | |
2014 | case 1: | |
2015 | return 64; | |
2016 | case 2: | |
2017 | case 4: | |
2018 | return 128; | |
2019 | case 8: | |
2020 | case 16: | |
2021 | return 256; | |
2022 | default: | |
2023 | MISSING_CASE(cpp); | |
2024 | return cpp; | |
2025 | } | |
2026 | break; | |
2027 | default: | |
d88c4afd | 2028 | MISSING_CASE(fb->modifier); |
7b49f948 VS |
2029 | return cpp; |
2030 | } | |
2031 | } | |
2032 | ||
d88c4afd VS |
2033 | static unsigned int |
2034 | intel_tile_height(const struct drm_framebuffer *fb, int plane) | |
a57ce0b2 | 2035 | { |
d88c4afd | 2036 | if (fb->modifier == DRM_FORMAT_MOD_NONE) |
832be82f VS |
2037 | return 1; |
2038 | else | |
d88c4afd VS |
2039 | return intel_tile_size(to_i915(fb->dev)) / |
2040 | intel_tile_width_bytes(fb, plane); | |
6761dd31 TU |
2041 | } |
2042 | ||
8d0deca8 | 2043 | /* Return the tile dimensions in pixel units */ |
d88c4afd | 2044 | static void intel_tile_dims(const struct drm_framebuffer *fb, int plane, |
8d0deca8 | 2045 | unsigned int *tile_width, |
d88c4afd | 2046 | unsigned int *tile_height) |
8d0deca8 | 2047 | { |
d88c4afd VS |
2048 | unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane); |
2049 | unsigned int cpp = fb->format->cpp[plane]; | |
8d0deca8 VS |
2050 | |
2051 | *tile_width = tile_width_bytes / cpp; | |
d88c4afd | 2052 | *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes; |
8d0deca8 VS |
2053 | } |
2054 | ||
6761dd31 | 2055 | unsigned int |
d88c4afd VS |
2056 | intel_fb_align_height(const struct drm_framebuffer *fb, |
2057 | int plane, unsigned int height) | |
6761dd31 | 2058 | { |
d88c4afd | 2059 | unsigned int tile_height = intel_tile_height(fb, plane); |
832be82f VS |
2060 | |
2061 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2062 | } |
2063 | ||
1663b9d6 VS |
2064 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
2065 | { | |
2066 | unsigned int size = 0; | |
2067 | int i; | |
2068 | ||
2069 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2070 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2071 | ||
2072 | return size; | |
2073 | } | |
2074 | ||
75c82a53 | 2075 | static void |
3465c580 VS |
2076 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
2077 | const struct drm_framebuffer *fb, | |
2078 | unsigned int rotation) | |
f64b98cd | 2079 | { |
7b92c047 | 2080 | view->type = I915_GGTT_VIEW_NORMAL; |
bd2ef25d | 2081 | if (drm_rotation_90_or_270(rotation)) { |
7b92c047 | 2082 | view->type = I915_GGTT_VIEW_ROTATED; |
8bab1193 | 2083 | view->rotated = to_intel_framebuffer(fb)->rot_info; |
2d7a215f VS |
2084 | } |
2085 | } | |
50470bb0 | 2086 | |
603525d7 | 2087 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2088 | { |
2089 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2090 | return 256 * 1024; | |
c0f86832 | 2091 | else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) || |
666a4537 | 2092 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2093 | return 128 * 1024; |
2094 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2095 | return 4 * 1024; | |
2096 | else | |
44c5905e | 2097 | return 0; |
4e9a86b6 VS |
2098 | } |
2099 | ||
d88c4afd VS |
2100 | static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb, |
2101 | int plane) | |
603525d7 | 2102 | { |
d88c4afd VS |
2103 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
2104 | ||
b90c1ee1 VS |
2105 | /* AUX_DIST needs only 4K alignment */ |
2106 | if (fb->format->format == DRM_FORMAT_NV12 && plane == 1) | |
2107 | return 4096; | |
2108 | ||
d88c4afd | 2109 | switch (fb->modifier) { |
603525d7 VS |
2110 | case DRM_FORMAT_MOD_NONE: |
2111 | return intel_linear_alignment(dev_priv); | |
2112 | case I915_FORMAT_MOD_X_TILED: | |
d88c4afd | 2113 | if (INTEL_GEN(dev_priv) >= 9) |
603525d7 VS |
2114 | return 256 * 1024; |
2115 | return 0; | |
2116 | case I915_FORMAT_MOD_Y_TILED: | |
2117 | case I915_FORMAT_MOD_Yf_TILED: | |
2118 | return 1 * 1024 * 1024; | |
2119 | default: | |
d88c4afd | 2120 | MISSING_CASE(fb->modifier); |
603525d7 VS |
2121 | return 0; |
2122 | } | |
2123 | } | |
2124 | ||
058d88c4 CW |
2125 | struct i915_vma * |
2126 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) | |
6b95a207 | 2127 | { |
850c4cdc | 2128 | struct drm_device *dev = fb->dev; |
fac5e23e | 2129 | struct drm_i915_private *dev_priv = to_i915(dev); |
850c4cdc | 2130 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2131 | struct i915_ggtt_view view; |
058d88c4 | 2132 | struct i915_vma *vma; |
6b95a207 | 2133 | u32 alignment; |
6b95a207 | 2134 | |
ebcdd39e MR |
2135 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2136 | ||
d88c4afd | 2137 | alignment = intel_surf_alignment(fb, 0); |
6b95a207 | 2138 | |
3465c580 | 2139 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2140 | |
693db184 CW |
2141 | /* Note that the w/a also requires 64 PTE of padding following the |
2142 | * bo. We currently fill all unused PTE with the shadow page and so | |
2143 | * we should always have valid PTE following the scanout preventing | |
2144 | * the VT-d warning. | |
2145 | */ | |
48f112fe | 2146 | if (intel_scanout_needs_vtd_wa(dev_priv) && alignment < 256 * 1024) |
693db184 CW |
2147 | alignment = 256 * 1024; |
2148 | ||
d6dd6843 PZ |
2149 | /* |
2150 | * Global gtt pte registers are special registers which actually forward | |
2151 | * writes to a chunk of system memory. Which means that there is no risk | |
2152 | * that the register values disappear as soon as we call | |
2153 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2154 | * pin/unpin/fence and not more. | |
2155 | */ | |
2156 | intel_runtime_pm_get(dev_priv); | |
2157 | ||
058d88c4 | 2158 | vma = i915_gem_object_pin_to_display_plane(obj, alignment, &view); |
49ef5294 CW |
2159 | if (IS_ERR(vma)) |
2160 | goto err; | |
6b95a207 | 2161 | |
05a20d09 | 2162 | if (i915_vma_is_map_and_fenceable(vma)) { |
49ef5294 CW |
2163 | /* Install a fence for tiled scan-out. Pre-i965 always needs a |
2164 | * fence, whereas 965+ only requires a fence if using | |
2165 | * framebuffer compression. For simplicity, we always, when | |
2166 | * possible, install a fence as the cost is not that onerous. | |
2167 | * | |
2168 | * If we fail to fence the tiled scanout, then either the | |
2169 | * modeset will reject the change (which is highly unlikely as | |
2170 | * the affected systems, all but one, do not have unmappable | |
2171 | * space) or we will not be able to enable full powersaving | |
2172 | * techniques (also likely not to apply due to various limits | |
2173 | * FBC and the like impose on the size of the buffer, which | |
2174 | * presumably we violated anyway with this unmappable buffer). | |
2175 | * Anyway, it is presumably better to stumble onwards with | |
2176 | * something and try to run the system in a "less than optimal" | |
2177 | * mode that matches the user configuration. | |
2178 | */ | |
2179 | if (i915_vma_get_fence(vma) == 0) | |
2180 | i915_vma_pin_fence(vma); | |
9807216f | 2181 | } |
6b95a207 | 2182 | |
be1e3415 | 2183 | i915_vma_get(vma); |
49ef5294 | 2184 | err: |
d6dd6843 | 2185 | intel_runtime_pm_put(dev_priv); |
058d88c4 | 2186 | return vma; |
6b95a207 KH |
2187 | } |
2188 | ||
be1e3415 | 2189 | void intel_unpin_fb_vma(struct i915_vma *vma) |
1690e1eb | 2190 | { |
be1e3415 | 2191 | lockdep_assert_held(&vma->vm->i915->drm.struct_mutex); |
f64b98cd | 2192 | |
49ef5294 | 2193 | i915_vma_unpin_fence(vma); |
058d88c4 | 2194 | i915_gem_object_unpin_from_display_plane(vma); |
be1e3415 | 2195 | i915_vma_put(vma); |
1690e1eb CW |
2196 | } |
2197 | ||
ef78ec94 VS |
2198 | static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane, |
2199 | unsigned int rotation) | |
2200 | { | |
bd2ef25d | 2201 | if (drm_rotation_90_or_270(rotation)) |
ef78ec94 VS |
2202 | return to_intel_framebuffer(fb)->rotated[plane].pitch; |
2203 | else | |
2204 | return fb->pitches[plane]; | |
2205 | } | |
2206 | ||
6687c906 VS |
2207 | /* |
2208 | * Convert the x/y offsets into a linear offset. | |
2209 | * Only valid with 0/180 degree rotation, which is fine since linear | |
2210 | * offset is only used with linear buffers on pre-hsw and tiled buffers | |
2211 | * with gen2/3, and 90/270 degree rotations isn't supported on any of them. | |
2212 | */ | |
2213 | u32 intel_fb_xy_to_linear(int x, int y, | |
2949056c VS |
2214 | const struct intel_plane_state *state, |
2215 | int plane) | |
6687c906 | 2216 | { |
2949056c | 2217 | const struct drm_framebuffer *fb = state->base.fb; |
353c8598 | 2218 | unsigned int cpp = fb->format->cpp[plane]; |
6687c906 VS |
2219 | unsigned int pitch = fb->pitches[plane]; |
2220 | ||
2221 | return y * pitch + x * cpp; | |
2222 | } | |
2223 | ||
2224 | /* | |
2225 | * Add the x/y offsets derived from fb->offsets[] to the user | |
2226 | * specified plane src x/y offsets. The resulting x/y offsets | |
2227 | * specify the start of scanout from the beginning of the gtt mapping. | |
2228 | */ | |
2229 | void intel_add_fb_offsets(int *x, int *y, | |
2949056c VS |
2230 | const struct intel_plane_state *state, |
2231 | int plane) | |
6687c906 VS |
2232 | |
2233 | { | |
2949056c VS |
2234 | const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb); |
2235 | unsigned int rotation = state->base.rotation; | |
6687c906 | 2236 | |
bd2ef25d | 2237 | if (drm_rotation_90_or_270(rotation)) { |
6687c906 VS |
2238 | *x += intel_fb->rotated[plane].x; |
2239 | *y += intel_fb->rotated[plane].y; | |
2240 | } else { | |
2241 | *x += intel_fb->normal[plane].x; | |
2242 | *y += intel_fb->normal[plane].y; | |
2243 | } | |
2244 | } | |
2245 | ||
29cf9491 | 2246 | /* |
29cf9491 VS |
2247 | * Input tile dimensions and pitch must already be |
2248 | * rotated to match x and y, and in pixel units. | |
2249 | */ | |
66a2d927 VS |
2250 | static u32 _intel_adjust_tile_offset(int *x, int *y, |
2251 | unsigned int tile_width, | |
2252 | unsigned int tile_height, | |
2253 | unsigned int tile_size, | |
2254 | unsigned int pitch_tiles, | |
2255 | u32 old_offset, | |
2256 | u32 new_offset) | |
29cf9491 | 2257 | { |
b9b24038 | 2258 | unsigned int pitch_pixels = pitch_tiles * tile_width; |
29cf9491 VS |
2259 | unsigned int tiles; |
2260 | ||
2261 | WARN_ON(old_offset & (tile_size - 1)); | |
2262 | WARN_ON(new_offset & (tile_size - 1)); | |
2263 | WARN_ON(new_offset > old_offset); | |
2264 | ||
2265 | tiles = (old_offset - new_offset) / tile_size; | |
2266 | ||
2267 | *y += tiles / pitch_tiles * tile_height; | |
2268 | *x += tiles % pitch_tiles * tile_width; | |
2269 | ||
b9b24038 VS |
2270 | /* minimize x in case it got needlessly big */ |
2271 | *y += *x / pitch_pixels * tile_height; | |
2272 | *x %= pitch_pixels; | |
2273 | ||
29cf9491 VS |
2274 | return new_offset; |
2275 | } | |
2276 | ||
66a2d927 VS |
2277 | /* |
2278 | * Adjust the tile offset by moving the difference into | |
2279 | * the x/y offsets. | |
2280 | */ | |
2281 | static u32 intel_adjust_tile_offset(int *x, int *y, | |
2282 | const struct intel_plane_state *state, int plane, | |
2283 | u32 old_offset, u32 new_offset) | |
2284 | { | |
2285 | const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev); | |
2286 | const struct drm_framebuffer *fb = state->base.fb; | |
353c8598 | 2287 | unsigned int cpp = fb->format->cpp[plane]; |
66a2d927 VS |
2288 | unsigned int rotation = state->base.rotation; |
2289 | unsigned int pitch = intel_fb_pitch(fb, plane, rotation); | |
2290 | ||
2291 | WARN_ON(new_offset > old_offset); | |
2292 | ||
bae781b2 | 2293 | if (fb->modifier != DRM_FORMAT_MOD_NONE) { |
66a2d927 VS |
2294 | unsigned int tile_size, tile_width, tile_height; |
2295 | unsigned int pitch_tiles; | |
2296 | ||
2297 | tile_size = intel_tile_size(dev_priv); | |
d88c4afd | 2298 | intel_tile_dims(fb, plane, &tile_width, &tile_height); |
66a2d927 | 2299 | |
bd2ef25d | 2300 | if (drm_rotation_90_or_270(rotation)) { |
66a2d927 VS |
2301 | pitch_tiles = pitch / tile_height; |
2302 | swap(tile_width, tile_height); | |
2303 | } else { | |
2304 | pitch_tiles = pitch / (tile_width * cpp); | |
2305 | } | |
2306 | ||
2307 | _intel_adjust_tile_offset(x, y, tile_width, tile_height, | |
2308 | tile_size, pitch_tiles, | |
2309 | old_offset, new_offset); | |
2310 | } else { | |
2311 | old_offset += *y * pitch + *x * cpp; | |
2312 | ||
2313 | *y = (old_offset - new_offset) / pitch; | |
2314 | *x = ((old_offset - new_offset) - *y * pitch) / cpp; | |
2315 | } | |
2316 | ||
2317 | return new_offset; | |
2318 | } | |
2319 | ||
8d0deca8 VS |
2320 | /* |
2321 | * Computes the linear offset to the base tile and adjusts | |
2322 | * x, y. bytes per pixel is assumed to be a power-of-two. | |
2323 | * | |
2324 | * In the 90/270 rotated case, x and y are assumed | |
2325 | * to be already rotated to match the rotated GTT view, and | |
2326 | * pitch is the tile_height aligned framebuffer height. | |
6687c906 VS |
2327 | * |
2328 | * This function is used when computing the derived information | |
2329 | * under intel_framebuffer, so using any of that information | |
2330 | * here is not allowed. Anything under drm_framebuffer can be | |
2331 | * used. This is why the user has to pass in the pitch since it | |
2332 | * is specified in the rotated orientation. | |
8d0deca8 | 2333 | */ |
6687c906 VS |
2334 | static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv, |
2335 | int *x, int *y, | |
2336 | const struct drm_framebuffer *fb, int plane, | |
2337 | unsigned int pitch, | |
2338 | unsigned int rotation, | |
2339 | u32 alignment) | |
c2c75131 | 2340 | { |
bae781b2 | 2341 | uint64_t fb_modifier = fb->modifier; |
353c8598 | 2342 | unsigned int cpp = fb->format->cpp[plane]; |
6687c906 | 2343 | u32 offset, offset_aligned; |
29cf9491 | 2344 | |
29cf9491 VS |
2345 | if (alignment) |
2346 | alignment--; | |
2347 | ||
b5c65338 | 2348 | if (fb_modifier != DRM_FORMAT_MOD_NONE) { |
8d0deca8 VS |
2349 | unsigned int tile_size, tile_width, tile_height; |
2350 | unsigned int tile_rows, tiles, pitch_tiles; | |
c2c75131 | 2351 | |
d843310d | 2352 | tile_size = intel_tile_size(dev_priv); |
d88c4afd | 2353 | intel_tile_dims(fb, plane, &tile_width, &tile_height); |
8d0deca8 | 2354 | |
bd2ef25d | 2355 | if (drm_rotation_90_or_270(rotation)) { |
8d0deca8 VS |
2356 | pitch_tiles = pitch / tile_height; |
2357 | swap(tile_width, tile_height); | |
2358 | } else { | |
2359 | pitch_tiles = pitch / (tile_width * cpp); | |
2360 | } | |
d843310d VS |
2361 | |
2362 | tile_rows = *y / tile_height; | |
2363 | *y %= tile_height; | |
c2c75131 | 2364 | |
8d0deca8 VS |
2365 | tiles = *x / tile_width; |
2366 | *x %= tile_width; | |
bc752862 | 2367 | |
29cf9491 VS |
2368 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
2369 | offset_aligned = offset & ~alignment; | |
bc752862 | 2370 | |
66a2d927 VS |
2371 | _intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2372 | tile_size, pitch_tiles, | |
2373 | offset, offset_aligned); | |
29cf9491 | 2374 | } else { |
bc752862 | 2375 | offset = *y * pitch + *x * cpp; |
29cf9491 VS |
2376 | offset_aligned = offset & ~alignment; |
2377 | ||
4e9a86b6 VS |
2378 | *y = (offset & alignment) / pitch; |
2379 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
bc752862 | 2380 | } |
29cf9491 VS |
2381 | |
2382 | return offset_aligned; | |
c2c75131 DV |
2383 | } |
2384 | ||
6687c906 | 2385 | u32 intel_compute_tile_offset(int *x, int *y, |
2949056c VS |
2386 | const struct intel_plane_state *state, |
2387 | int plane) | |
6687c906 | 2388 | { |
2949056c VS |
2389 | const struct drm_i915_private *dev_priv = to_i915(state->base.plane->dev); |
2390 | const struct drm_framebuffer *fb = state->base.fb; | |
2391 | unsigned int rotation = state->base.rotation; | |
ef78ec94 | 2392 | int pitch = intel_fb_pitch(fb, plane, rotation); |
b90c1ee1 | 2393 | u32 alignment = intel_surf_alignment(fb, plane); |
6687c906 VS |
2394 | |
2395 | return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch, | |
2396 | rotation, alignment); | |
2397 | } | |
2398 | ||
2399 | /* Convert the fb->offset[] linear offset into x/y offsets */ | |
2400 | static void intel_fb_offset_to_xy(int *x, int *y, | |
2401 | const struct drm_framebuffer *fb, int plane) | |
2402 | { | |
353c8598 | 2403 | unsigned int cpp = fb->format->cpp[plane]; |
6687c906 VS |
2404 | unsigned int pitch = fb->pitches[plane]; |
2405 | u32 linear_offset = fb->offsets[plane]; | |
2406 | ||
2407 | *y = linear_offset / pitch; | |
2408 | *x = linear_offset % pitch / cpp; | |
2409 | } | |
2410 | ||
72618ebf VS |
2411 | static unsigned int intel_fb_modifier_to_tiling(uint64_t fb_modifier) |
2412 | { | |
2413 | switch (fb_modifier) { | |
2414 | case I915_FORMAT_MOD_X_TILED: | |
2415 | return I915_TILING_X; | |
2416 | case I915_FORMAT_MOD_Y_TILED: | |
2417 | return I915_TILING_Y; | |
2418 | default: | |
2419 | return I915_TILING_NONE; | |
2420 | } | |
2421 | } | |
2422 | ||
6687c906 VS |
2423 | static int |
2424 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
2425 | struct drm_framebuffer *fb) | |
2426 | { | |
2427 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
2428 | struct intel_rotation_info *rot_info = &intel_fb->rot_info; | |
2429 | u32 gtt_offset_rotated = 0; | |
2430 | unsigned int max_size = 0; | |
bcb0b461 | 2431 | int i, num_planes = fb->format->num_planes; |
6687c906 VS |
2432 | unsigned int tile_size = intel_tile_size(dev_priv); |
2433 | ||
2434 | for (i = 0; i < num_planes; i++) { | |
2435 | unsigned int width, height; | |
2436 | unsigned int cpp, size; | |
2437 | u32 offset; | |
2438 | int x, y; | |
2439 | ||
353c8598 | 2440 | cpp = fb->format->cpp[i]; |
145fcb11 VS |
2441 | width = drm_framebuffer_plane_width(fb->width, fb, i); |
2442 | height = drm_framebuffer_plane_height(fb->height, fb, i); | |
6687c906 VS |
2443 | |
2444 | intel_fb_offset_to_xy(&x, &y, fb, i); | |
2445 | ||
60d5f2a4 VS |
2446 | /* |
2447 | * The fence (if used) is aligned to the start of the object | |
2448 | * so having the framebuffer wrap around across the edge of the | |
2449 | * fenced region doesn't really work. We have no API to configure | |
2450 | * the fence start offset within the object (nor could we probably | |
2451 | * on gen2/3). So it's just easier if we just require that the | |
2452 | * fb layout agrees with the fence layout. We already check that the | |
2453 | * fb stride matches the fence stride elsewhere. | |
2454 | */ | |
2455 | if (i915_gem_object_is_tiled(intel_fb->obj) && | |
2456 | (x + width) * cpp > fb->pitches[i]) { | |
144cc143 VS |
2457 | DRM_DEBUG_KMS("bad fb plane %d offset: 0x%x\n", |
2458 | i, fb->offsets[i]); | |
60d5f2a4 VS |
2459 | return -EINVAL; |
2460 | } | |
2461 | ||
6687c906 VS |
2462 | /* |
2463 | * First pixel of the framebuffer from | |
2464 | * the start of the normal gtt mapping. | |
2465 | */ | |
2466 | intel_fb->normal[i].x = x; | |
2467 | intel_fb->normal[i].y = y; | |
2468 | ||
2469 | offset = _intel_compute_tile_offset(dev_priv, &x, &y, | |
3ca46c0a | 2470 | fb, i, fb->pitches[i], |
cc926387 | 2471 | DRM_ROTATE_0, tile_size); |
6687c906 VS |
2472 | offset /= tile_size; |
2473 | ||
bae781b2 | 2474 | if (fb->modifier != DRM_FORMAT_MOD_NONE) { |
6687c906 VS |
2475 | unsigned int tile_width, tile_height; |
2476 | unsigned int pitch_tiles; | |
2477 | struct drm_rect r; | |
2478 | ||
d88c4afd | 2479 | intel_tile_dims(fb, i, &tile_width, &tile_height); |
6687c906 VS |
2480 | |
2481 | rot_info->plane[i].offset = offset; | |
2482 | rot_info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i], tile_width * cpp); | |
2483 | rot_info->plane[i].width = DIV_ROUND_UP(x + width, tile_width); | |
2484 | rot_info->plane[i].height = DIV_ROUND_UP(y + height, tile_height); | |
2485 | ||
2486 | intel_fb->rotated[i].pitch = | |
2487 | rot_info->plane[i].height * tile_height; | |
2488 | ||
2489 | /* how many tiles does this plane need */ | |
2490 | size = rot_info->plane[i].stride * rot_info->plane[i].height; | |
2491 | /* | |
2492 | * If the plane isn't horizontally tile aligned, | |
2493 | * we need one more tile. | |
2494 | */ | |
2495 | if (x != 0) | |
2496 | size++; | |
2497 | ||
2498 | /* rotate the x/y offsets to match the GTT view */ | |
2499 | r.x1 = x; | |
2500 | r.y1 = y; | |
2501 | r.x2 = x + width; | |
2502 | r.y2 = y + height; | |
2503 | drm_rect_rotate(&r, | |
2504 | rot_info->plane[i].width * tile_width, | |
2505 | rot_info->plane[i].height * tile_height, | |
cc926387 | 2506 | DRM_ROTATE_270); |
6687c906 VS |
2507 | x = r.x1; |
2508 | y = r.y1; | |
2509 | ||
2510 | /* rotate the tile dimensions to match the GTT view */ | |
2511 | pitch_tiles = intel_fb->rotated[i].pitch / tile_height; | |
2512 | swap(tile_width, tile_height); | |
2513 | ||
2514 | /* | |
2515 | * We only keep the x/y offsets, so push all of the | |
2516 | * gtt offset into the x/y offsets. | |
2517 | */ | |
46a1bd28 ACO |
2518 | _intel_adjust_tile_offset(&x, &y, |
2519 | tile_width, tile_height, | |
2520 | tile_size, pitch_tiles, | |
66a2d927 | 2521 | gtt_offset_rotated * tile_size, 0); |
6687c906 VS |
2522 | |
2523 | gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height; | |
2524 | ||
2525 | /* | |
2526 | * First pixel of the framebuffer from | |
2527 | * the start of the rotated gtt mapping. | |
2528 | */ | |
2529 | intel_fb->rotated[i].x = x; | |
2530 | intel_fb->rotated[i].y = y; | |
2531 | } else { | |
2532 | size = DIV_ROUND_UP((y + height) * fb->pitches[i] + | |
2533 | x * cpp, tile_size); | |
2534 | } | |
2535 | ||
2536 | /* how many tiles in total needed in the bo */ | |
2537 | max_size = max(max_size, offset + size); | |
2538 | } | |
2539 | ||
144cc143 VS |
2540 | if (max_size * tile_size > intel_fb->obj->base.size) { |
2541 | DRM_DEBUG_KMS("fb too big for bo (need %u bytes, have %zu bytes)\n", | |
2542 | max_size * tile_size, intel_fb->obj->base.size); | |
6687c906 VS |
2543 | return -EINVAL; |
2544 | } | |
2545 | ||
2546 | return 0; | |
2547 | } | |
2548 | ||
b35d63fa | 2549 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2550 | { |
2551 | switch (format) { | |
2552 | case DISPPLANE_8BPP: | |
2553 | return DRM_FORMAT_C8; | |
2554 | case DISPPLANE_BGRX555: | |
2555 | return DRM_FORMAT_XRGB1555; | |
2556 | case DISPPLANE_BGRX565: | |
2557 | return DRM_FORMAT_RGB565; | |
2558 | default: | |
2559 | case DISPPLANE_BGRX888: | |
2560 | return DRM_FORMAT_XRGB8888; | |
2561 | case DISPPLANE_RGBX888: | |
2562 | return DRM_FORMAT_XBGR8888; | |
2563 | case DISPPLANE_BGRX101010: | |
2564 | return DRM_FORMAT_XRGB2101010; | |
2565 | case DISPPLANE_RGBX101010: | |
2566 | return DRM_FORMAT_XBGR2101010; | |
2567 | } | |
2568 | } | |
2569 | ||
bc8d7dff DL |
2570 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2571 | { | |
2572 | switch (format) { | |
2573 | case PLANE_CTL_FORMAT_RGB_565: | |
2574 | return DRM_FORMAT_RGB565; | |
2575 | default: | |
2576 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2577 | if (rgb_order) { | |
2578 | if (alpha) | |
2579 | return DRM_FORMAT_ABGR8888; | |
2580 | else | |
2581 | return DRM_FORMAT_XBGR8888; | |
2582 | } else { | |
2583 | if (alpha) | |
2584 | return DRM_FORMAT_ARGB8888; | |
2585 | else | |
2586 | return DRM_FORMAT_XRGB8888; | |
2587 | } | |
2588 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2589 | if (rgb_order) | |
2590 | return DRM_FORMAT_XBGR2101010; | |
2591 | else | |
2592 | return DRM_FORMAT_XRGB2101010; | |
2593 | } | |
2594 | } | |
2595 | ||
5724dbd1 | 2596 | static bool |
f6936e29 DV |
2597 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2598 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2599 | { |
2600 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2601 | struct drm_i915_private *dev_priv = to_i915(dev); |
72e96d64 | 2602 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
46f297fb JB |
2603 | struct drm_i915_gem_object *obj = NULL; |
2604 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2605 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2606 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2607 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2608 | PAGE_SIZE); | |
2609 | ||
2610 | size_aligned -= base_aligned; | |
46f297fb | 2611 | |
ff2652ea CW |
2612 | if (plane_config->size == 0) |
2613 | return false; | |
2614 | ||
3badb49f PZ |
2615 | /* If the FB is too big, just don't use it since fbdev is not very |
2616 | * important and we should probably use that space with FBC or other | |
2617 | * features. */ | |
72e96d64 | 2618 | if (size_aligned * 2 > ggtt->stolen_usable_size) |
3badb49f PZ |
2619 | return false; |
2620 | ||
12c83d99 | 2621 | mutex_lock(&dev->struct_mutex); |
187685cb | 2622 | obj = i915_gem_object_create_stolen_for_preallocated(dev_priv, |
f37b5c2b DV |
2623 | base_aligned, |
2624 | base_aligned, | |
2625 | size_aligned); | |
24dbf51a CW |
2626 | mutex_unlock(&dev->struct_mutex); |
2627 | if (!obj) | |
484b41dd | 2628 | return false; |
46f297fb | 2629 | |
3e510a8e CW |
2630 | if (plane_config->tiling == I915_TILING_X) |
2631 | obj->tiling_and_stride = fb->pitches[0] | I915_TILING_X; | |
46f297fb | 2632 | |
438b74a5 | 2633 | mode_cmd.pixel_format = fb->format->format; |
6bf129df DL |
2634 | mode_cmd.width = fb->width; |
2635 | mode_cmd.height = fb->height; | |
2636 | mode_cmd.pitches[0] = fb->pitches[0]; | |
bae781b2 | 2637 | mode_cmd.modifier[0] = fb->modifier; |
18c5247e | 2638 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; |
46f297fb | 2639 | |
24dbf51a | 2640 | if (intel_framebuffer_init(to_intel_framebuffer(fb), obj, &mode_cmd)) { |
46f297fb JB |
2641 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2642 | goto out_unref_obj; | |
2643 | } | |
12c83d99 | 2644 | |
484b41dd | 2645 | |
f6936e29 | 2646 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2647 | return true; |
46f297fb JB |
2648 | |
2649 | out_unref_obj: | |
f8c417cd | 2650 | i915_gem_object_put(obj); |
484b41dd JB |
2651 | return false; |
2652 | } | |
2653 | ||
5a21b665 DV |
2654 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2655 | static void | |
2656 | update_state_fb(struct drm_plane *plane) | |
2657 | { | |
2658 | if (plane->fb == plane->state->fb) | |
2659 | return; | |
2660 | ||
2661 | if (plane->state->fb) | |
2662 | drm_framebuffer_unreference(plane->state->fb); | |
2663 | plane->state->fb = plane->fb; | |
2664 | if (plane->state->fb) | |
2665 | drm_framebuffer_reference(plane->state->fb); | |
2666 | } | |
2667 | ||
e9728bd8 VS |
2668 | static void |
2669 | intel_set_plane_visible(struct intel_crtc_state *crtc_state, | |
2670 | struct intel_plane_state *plane_state, | |
2671 | bool visible) | |
2672 | { | |
2673 | struct intel_plane *plane = to_intel_plane(plane_state->base.plane); | |
2674 | ||
2675 | plane_state->base.visible = visible; | |
2676 | ||
2677 | /* FIXME pre-g4x don't work like this */ | |
2678 | if (visible) { | |
2679 | crtc_state->base.plane_mask |= BIT(drm_plane_index(&plane->base)); | |
2680 | crtc_state->active_planes |= BIT(plane->id); | |
2681 | } else { | |
2682 | crtc_state->base.plane_mask &= ~BIT(drm_plane_index(&plane->base)); | |
2683 | crtc_state->active_planes &= ~BIT(plane->id); | |
2684 | } | |
2685 | ||
2686 | DRM_DEBUG_KMS("%s active planes 0x%x\n", | |
2687 | crtc_state->base.crtc->name, | |
2688 | crtc_state->active_planes); | |
2689 | } | |
2690 | ||
5724dbd1 | 2691 | static void |
f6936e29 DV |
2692 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2693 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2694 | { |
2695 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 2696 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 2697 | struct drm_crtc *c; |
2ff8fde1 | 2698 | struct drm_i915_gem_object *obj; |
88595ac9 | 2699 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2700 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2701 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2702 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2703 | struct intel_plane_state *intel_state = |
2704 | to_intel_plane_state(plane_state); | |
88595ac9 | 2705 | struct drm_framebuffer *fb; |
484b41dd | 2706 | |
2d14030b | 2707 | if (!plane_config->fb) |
484b41dd JB |
2708 | return; |
2709 | ||
f6936e29 | 2710 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2711 | fb = &plane_config->fb->base; |
2712 | goto valid_fb; | |
f55548b5 | 2713 | } |
484b41dd | 2714 | |
2d14030b | 2715 | kfree(plane_config->fb); |
484b41dd JB |
2716 | |
2717 | /* | |
2718 | * Failed to alloc the obj, check to see if we should share | |
2719 | * an fb with another CRTC instead | |
2720 | */ | |
70e1e0ec | 2721 | for_each_crtc(dev, c) { |
be1e3415 | 2722 | struct intel_plane_state *state; |
484b41dd JB |
2723 | |
2724 | if (c == &intel_crtc->base) | |
2725 | continue; | |
2726 | ||
be1e3415 | 2727 | if (!to_intel_crtc(c)->active) |
2ff8fde1 MR |
2728 | continue; |
2729 | ||
be1e3415 CW |
2730 | state = to_intel_plane_state(c->primary->state); |
2731 | if (!state->vma) | |
484b41dd JB |
2732 | continue; |
2733 | ||
be1e3415 CW |
2734 | if (intel_plane_ggtt_offset(state) == plane_config->base) { |
2735 | fb = c->primary->fb; | |
88595ac9 DV |
2736 | drm_framebuffer_reference(fb); |
2737 | goto valid_fb; | |
484b41dd JB |
2738 | } |
2739 | } | |
88595ac9 | 2740 | |
200757f5 MR |
2741 | /* |
2742 | * We've failed to reconstruct the BIOS FB. Current display state | |
2743 | * indicates that the primary plane is visible, but has a NULL FB, | |
2744 | * which will lead to problems later if we don't fix it up. The | |
2745 | * simplest solution is to just disable the primary plane now and | |
2746 | * pretend the BIOS never had it enabled. | |
2747 | */ | |
e9728bd8 VS |
2748 | intel_set_plane_visible(to_intel_crtc_state(crtc_state), |
2749 | to_intel_plane_state(plane_state), | |
2750 | false); | |
2622a081 | 2751 | intel_pre_disable_primary_noatomic(&intel_crtc->base); |
72259536 | 2752 | trace_intel_disable_plane(primary, intel_crtc); |
200757f5 MR |
2753 | intel_plane->disable_plane(primary, &intel_crtc->base); |
2754 | ||
88595ac9 DV |
2755 | return; |
2756 | ||
2757 | valid_fb: | |
be1e3415 CW |
2758 | mutex_lock(&dev->struct_mutex); |
2759 | intel_state->vma = | |
2760 | intel_pin_and_fence_fb_obj(fb, primary->state->rotation); | |
2761 | mutex_unlock(&dev->struct_mutex); | |
2762 | if (IS_ERR(intel_state->vma)) { | |
2763 | DRM_ERROR("failed to pin boot fb on pipe %d: %li\n", | |
2764 | intel_crtc->pipe, PTR_ERR(intel_state->vma)); | |
2765 | ||
2766 | intel_state->vma = NULL; | |
2767 | drm_framebuffer_unreference(fb); | |
2768 | return; | |
2769 | } | |
2770 | ||
f44e2659 VS |
2771 | plane_state->src_x = 0; |
2772 | plane_state->src_y = 0; | |
be5651f2 ML |
2773 | plane_state->src_w = fb->width << 16; |
2774 | plane_state->src_h = fb->height << 16; | |
2775 | ||
f44e2659 VS |
2776 | plane_state->crtc_x = 0; |
2777 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2778 | plane_state->crtc_w = fb->width; |
2779 | plane_state->crtc_h = fb->height; | |
2780 | ||
1638d30c RC |
2781 | intel_state->base.src = drm_plane_state_src(plane_state); |
2782 | intel_state->base.dst = drm_plane_state_dest(plane_state); | |
0a8d8a86 | 2783 | |
88595ac9 | 2784 | obj = intel_fb_obj(fb); |
3e510a8e | 2785 | if (i915_gem_object_is_tiled(obj)) |
88595ac9 DV |
2786 | dev_priv->preserve_bios_swizzle = true; |
2787 | ||
be5651f2 ML |
2788 | drm_framebuffer_reference(fb); |
2789 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2790 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
e9728bd8 VS |
2791 | |
2792 | intel_set_plane_visible(to_intel_crtc_state(crtc_state), | |
2793 | to_intel_plane_state(plane_state), | |
2794 | true); | |
2795 | ||
faf5bf0a CW |
2796 | atomic_or(to_intel_plane(primary)->frontbuffer_bit, |
2797 | &obj->frontbuffer_bits); | |
46f297fb JB |
2798 | } |
2799 | ||
b63a16f6 VS |
2800 | static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane, |
2801 | unsigned int rotation) | |
2802 | { | |
353c8598 | 2803 | int cpp = fb->format->cpp[plane]; |
b63a16f6 | 2804 | |
bae781b2 | 2805 | switch (fb->modifier) { |
b63a16f6 VS |
2806 | case DRM_FORMAT_MOD_NONE: |
2807 | case I915_FORMAT_MOD_X_TILED: | |
2808 | switch (cpp) { | |
2809 | case 8: | |
2810 | return 4096; | |
2811 | case 4: | |
2812 | case 2: | |
2813 | case 1: | |
2814 | return 8192; | |
2815 | default: | |
2816 | MISSING_CASE(cpp); | |
2817 | break; | |
2818 | } | |
2819 | break; | |
2820 | case I915_FORMAT_MOD_Y_TILED: | |
2821 | case I915_FORMAT_MOD_Yf_TILED: | |
2822 | switch (cpp) { | |
2823 | case 8: | |
2824 | return 2048; | |
2825 | case 4: | |
2826 | return 4096; | |
2827 | case 2: | |
2828 | case 1: | |
2829 | return 8192; | |
2830 | default: | |
2831 | MISSING_CASE(cpp); | |
2832 | break; | |
2833 | } | |
2834 | break; | |
2835 | default: | |
bae781b2 | 2836 | MISSING_CASE(fb->modifier); |
b63a16f6 VS |
2837 | } |
2838 | ||
2839 | return 2048; | |
2840 | } | |
2841 | ||
2842 | static int skl_check_main_surface(struct intel_plane_state *plane_state) | |
2843 | { | |
b63a16f6 VS |
2844 | const struct drm_framebuffer *fb = plane_state->base.fb; |
2845 | unsigned int rotation = plane_state->base.rotation; | |
cc926387 DV |
2846 | int x = plane_state->base.src.x1 >> 16; |
2847 | int y = plane_state->base.src.y1 >> 16; | |
2848 | int w = drm_rect_width(&plane_state->base.src) >> 16; | |
2849 | int h = drm_rect_height(&plane_state->base.src) >> 16; | |
b63a16f6 VS |
2850 | int max_width = skl_max_plane_width(fb, 0, rotation); |
2851 | int max_height = 4096; | |
8d970654 | 2852 | u32 alignment, offset, aux_offset = plane_state->aux.offset; |
b63a16f6 VS |
2853 | |
2854 | if (w > max_width || h > max_height) { | |
2855 | DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n", | |
2856 | w, h, max_width, max_height); | |
2857 | return -EINVAL; | |
2858 | } | |
2859 | ||
2860 | intel_add_fb_offsets(&x, &y, plane_state, 0); | |
2861 | offset = intel_compute_tile_offset(&x, &y, plane_state, 0); | |
d88c4afd | 2862 | alignment = intel_surf_alignment(fb, 0); |
b63a16f6 | 2863 | |
8d970654 VS |
2864 | /* |
2865 | * AUX surface offset is specified as the distance from the | |
2866 | * main surface offset, and it must be non-negative. Make | |
2867 | * sure that is what we will get. | |
2868 | */ | |
2869 | if (offset > aux_offset) | |
2870 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
2871 | offset, aux_offset & ~(alignment - 1)); | |
2872 | ||
b63a16f6 VS |
2873 | /* |
2874 | * When using an X-tiled surface, the plane blows up | |
2875 | * if the x offset + width exceed the stride. | |
2876 | * | |
2877 | * TODO: linear and Y-tiled seem fine, Yf untested, | |
2878 | */ | |
bae781b2 | 2879 | if (fb->modifier == I915_FORMAT_MOD_X_TILED) { |
353c8598 | 2880 | int cpp = fb->format->cpp[0]; |
b63a16f6 VS |
2881 | |
2882 | while ((x + w) * cpp > fb->pitches[0]) { | |
2883 | if (offset == 0) { | |
2884 | DRM_DEBUG_KMS("Unable to find suitable display surface offset\n"); | |
2885 | return -EINVAL; | |
2886 | } | |
2887 | ||
2888 | offset = intel_adjust_tile_offset(&x, &y, plane_state, 0, | |
2889 | offset, offset - alignment); | |
2890 | } | |
2891 | } | |
2892 | ||
2893 | plane_state->main.offset = offset; | |
2894 | plane_state->main.x = x; | |
2895 | plane_state->main.y = y; | |
2896 | ||
2897 | return 0; | |
2898 | } | |
2899 | ||
8d970654 VS |
2900 | static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state) |
2901 | { | |
2902 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2903 | unsigned int rotation = plane_state->base.rotation; | |
2904 | int max_width = skl_max_plane_width(fb, 1, rotation); | |
2905 | int max_height = 4096; | |
cc926387 DV |
2906 | int x = plane_state->base.src.x1 >> 17; |
2907 | int y = plane_state->base.src.y1 >> 17; | |
2908 | int w = drm_rect_width(&plane_state->base.src) >> 17; | |
2909 | int h = drm_rect_height(&plane_state->base.src) >> 17; | |
8d970654 VS |
2910 | u32 offset; |
2911 | ||
2912 | intel_add_fb_offsets(&x, &y, plane_state, 1); | |
2913 | offset = intel_compute_tile_offset(&x, &y, plane_state, 1); | |
2914 | ||
2915 | /* FIXME not quite sure how/if these apply to the chroma plane */ | |
2916 | if (w > max_width || h > max_height) { | |
2917 | DRM_DEBUG_KMS("CbCr source size %dx%d too big (limit %dx%d)\n", | |
2918 | w, h, max_width, max_height); | |
2919 | return -EINVAL; | |
2920 | } | |
2921 | ||
2922 | plane_state->aux.offset = offset; | |
2923 | plane_state->aux.x = x; | |
2924 | plane_state->aux.y = y; | |
2925 | ||
2926 | return 0; | |
2927 | } | |
2928 | ||
b63a16f6 VS |
2929 | int skl_check_plane_surface(struct intel_plane_state *plane_state) |
2930 | { | |
2931 | const struct drm_framebuffer *fb = plane_state->base.fb; | |
2932 | unsigned int rotation = plane_state->base.rotation; | |
2933 | int ret; | |
2934 | ||
a5e4c7d0 VS |
2935 | if (!plane_state->base.visible) |
2936 | return 0; | |
2937 | ||
b63a16f6 | 2938 | /* Rotate src coordinates to match rotated GTT view */ |
bd2ef25d | 2939 | if (drm_rotation_90_or_270(rotation)) |
cc926387 | 2940 | drm_rect_rotate(&plane_state->base.src, |
da064b47 VS |
2941 | fb->width << 16, fb->height << 16, |
2942 | DRM_ROTATE_270); | |
b63a16f6 | 2943 | |
8d970654 VS |
2944 | /* |
2945 | * Handle the AUX surface first since | |
2946 | * the main surface setup depends on it. | |
2947 | */ | |
438b74a5 | 2948 | if (fb->format->format == DRM_FORMAT_NV12) { |
8d970654 VS |
2949 | ret = skl_check_nv12_aux_surface(plane_state); |
2950 | if (ret) | |
2951 | return ret; | |
2952 | } else { | |
2953 | plane_state->aux.offset = ~0xfff; | |
2954 | plane_state->aux.x = 0; | |
2955 | plane_state->aux.y = 0; | |
2956 | } | |
2957 | ||
b63a16f6 VS |
2958 | ret = skl_check_main_surface(plane_state); |
2959 | if (ret) | |
2960 | return ret; | |
2961 | ||
2962 | return 0; | |
2963 | } | |
2964 | ||
a8d201af ML |
2965 | static void i9xx_update_primary_plane(struct drm_plane *primary, |
2966 | const struct intel_crtc_state *crtc_state, | |
2967 | const struct intel_plane_state *plane_state) | |
81255565 | 2968 | { |
6315b5d3 | 2969 | struct drm_i915_private *dev_priv = to_i915(primary->dev); |
a8d201af ML |
2970 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2971 | struct drm_framebuffer *fb = plane_state->base.fb; | |
81255565 | 2972 | int plane = intel_crtc->plane; |
54ea9da8 | 2973 | u32 linear_offset; |
81255565 | 2974 | u32 dspcntr; |
f0f59a00 | 2975 | i915_reg_t reg = DSPCNTR(plane); |
8d0deca8 | 2976 | unsigned int rotation = plane_state->base.rotation; |
936e71e3 VS |
2977 | int x = plane_state->base.src.x1 >> 16; |
2978 | int y = plane_state->base.src.y1 >> 16; | |
c9ba6fad | 2979 | |
f45651ba VS |
2980 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2981 | ||
fdd508a6 | 2982 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba | 2983 | |
6315b5d3 | 2984 | if (INTEL_GEN(dev_priv) < 4) { |
f45651ba VS |
2985 | if (intel_crtc->pipe == PIPE_B) |
2986 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2987 | ||
2988 | /* pipesrc and dspsize control the size that is scaled from, | |
2989 | * which should always be the user's requested size. | |
2990 | */ | |
2991 | I915_WRITE(DSPSIZE(plane), | |
a8d201af ML |
2992 | ((crtc_state->pipe_src_h - 1) << 16) | |
2993 | (crtc_state->pipe_src_w - 1)); | |
f45651ba | 2994 | I915_WRITE(DSPPOS(plane), 0); |
920a14b2 | 2995 | } else if (IS_CHERRYVIEW(dev_priv) && plane == PLANE_B) { |
c14b0485 | 2996 | I915_WRITE(PRIMSIZE(plane), |
a8d201af ML |
2997 | ((crtc_state->pipe_src_h - 1) << 16) | |
2998 | (crtc_state->pipe_src_w - 1)); | |
c14b0485 VS |
2999 | I915_WRITE(PRIMPOS(plane), 0); |
3000 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 3001 | } |
81255565 | 3002 | |
438b74a5 | 3003 | switch (fb->format->format) { |
57779d06 | 3004 | case DRM_FORMAT_C8: |
81255565 JB |
3005 | dspcntr |= DISPPLANE_8BPP; |
3006 | break; | |
57779d06 | 3007 | case DRM_FORMAT_XRGB1555: |
57779d06 | 3008 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 3009 | break; |
57779d06 VS |
3010 | case DRM_FORMAT_RGB565: |
3011 | dspcntr |= DISPPLANE_BGRX565; | |
3012 | break; | |
3013 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
3014 | dspcntr |= DISPPLANE_BGRX888; |
3015 | break; | |
3016 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
3017 | dspcntr |= DISPPLANE_RGBX888; |
3018 | break; | |
3019 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
3020 | dspcntr |= DISPPLANE_BGRX101010; |
3021 | break; | |
3022 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 3023 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
3024 | break; |
3025 | default: | |
baba133a | 3026 | BUG(); |
81255565 | 3027 | } |
57779d06 | 3028 | |
72618ebf | 3029 | if (INTEL_GEN(dev_priv) >= 4 && |
bae781b2 | 3030 | fb->modifier == I915_FORMAT_MOD_X_TILED) |
f45651ba | 3031 | dspcntr |= DISPPLANE_TILED; |
81255565 | 3032 | |
df0cd455 VS |
3033 | if (rotation & DRM_ROTATE_180) |
3034 | dspcntr |= DISPPLANE_ROTATE_180; | |
3035 | ||
4ea7be2b VS |
3036 | if (rotation & DRM_REFLECT_X) |
3037 | dspcntr |= DISPPLANE_MIRROR; | |
3038 | ||
9beb5fea | 3039 | if (IS_G4X(dev_priv)) |
de1aa629 VS |
3040 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
3041 | ||
2949056c | 3042 | intel_add_fb_offsets(&x, &y, plane_state, 0); |
81255565 | 3043 | |
6315b5d3 | 3044 | if (INTEL_GEN(dev_priv) >= 4) |
c2c75131 | 3045 | intel_crtc->dspaddr_offset = |
2949056c | 3046 | intel_compute_tile_offset(&x, &y, plane_state, 0); |
e506a0c6 | 3047 | |
f22aa143 | 3048 | if (rotation & DRM_ROTATE_180) { |
df0cd455 VS |
3049 | x += crtc_state->pipe_src_w - 1; |
3050 | y += crtc_state->pipe_src_h - 1; | |
4ea7be2b VS |
3051 | } else if (rotation & DRM_REFLECT_X) { |
3052 | x += crtc_state->pipe_src_w - 1; | |
48404c1e SJ |
3053 | } |
3054 | ||
2949056c | 3055 | linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); |
6687c906 | 3056 | |
6315b5d3 | 3057 | if (INTEL_GEN(dev_priv) < 4) |
6687c906 VS |
3058 | intel_crtc->dspaddr_offset = linear_offset; |
3059 | ||
2db3366b PZ |
3060 | intel_crtc->adjusted_x = x; |
3061 | intel_crtc->adjusted_y = y; | |
3062 | ||
48404c1e SJ |
3063 | I915_WRITE(reg, dspcntr); |
3064 | ||
01f2c773 | 3065 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
6315b5d3 | 3066 | if (INTEL_GEN(dev_priv) >= 4) { |
85ba7b7d | 3067 | I915_WRITE(DSPSURF(plane), |
be1e3415 | 3068 | intel_plane_ggtt_offset(plane_state) + |
6687c906 | 3069 | intel_crtc->dspaddr_offset); |
5eddb70b | 3070 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 3071 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
bfb81049 VS |
3072 | } else { |
3073 | I915_WRITE(DSPADDR(plane), | |
be1e3415 | 3074 | intel_plane_ggtt_offset(plane_state) + |
bfb81049 VS |
3075 | intel_crtc->dspaddr_offset); |
3076 | } | |
5eddb70b | 3077 | POSTING_READ(reg); |
17638cd6 JB |
3078 | } |
3079 | ||
a8d201af ML |
3080 | static void i9xx_disable_primary_plane(struct drm_plane *primary, |
3081 | struct drm_crtc *crtc) | |
17638cd6 JB |
3082 | { |
3083 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3084 | struct drm_i915_private *dev_priv = to_i915(dev); |
17638cd6 | 3085 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
17638cd6 | 3086 | int plane = intel_crtc->plane; |
f45651ba | 3087 | |
a8d201af ML |
3088 | I915_WRITE(DSPCNTR(plane), 0); |
3089 | if (INTEL_INFO(dev_priv)->gen >= 4) | |
fdd508a6 | 3090 | I915_WRITE(DSPSURF(plane), 0); |
a8d201af ML |
3091 | else |
3092 | I915_WRITE(DSPADDR(plane), 0); | |
3093 | POSTING_READ(DSPCNTR(plane)); | |
3094 | } | |
c9ba6fad | 3095 | |
a8d201af ML |
3096 | static void ironlake_update_primary_plane(struct drm_plane *primary, |
3097 | const struct intel_crtc_state *crtc_state, | |
3098 | const struct intel_plane_state *plane_state) | |
3099 | { | |
3100 | struct drm_device *dev = primary->dev; | |
fac5e23e | 3101 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
3102 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3103 | struct drm_framebuffer *fb = plane_state->base.fb; | |
a8d201af | 3104 | int plane = intel_crtc->plane; |
54ea9da8 | 3105 | u32 linear_offset; |
a8d201af ML |
3106 | u32 dspcntr; |
3107 | i915_reg_t reg = DSPCNTR(plane); | |
8d0deca8 | 3108 | unsigned int rotation = plane_state->base.rotation; |
936e71e3 VS |
3109 | int x = plane_state->base.src.x1 >> 16; |
3110 | int y = plane_state->base.src.y1 >> 16; | |
c9ba6fad | 3111 | |
f45651ba | 3112 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
fdd508a6 | 3113 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba | 3114 | |
8652744b | 3115 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
f45651ba | 3116 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; |
17638cd6 | 3117 | |
438b74a5 | 3118 | switch (fb->format->format) { |
57779d06 | 3119 | case DRM_FORMAT_C8: |
17638cd6 JB |
3120 | dspcntr |= DISPPLANE_8BPP; |
3121 | break; | |
57779d06 VS |
3122 | case DRM_FORMAT_RGB565: |
3123 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 3124 | break; |
57779d06 | 3125 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
3126 | dspcntr |= DISPPLANE_BGRX888; |
3127 | break; | |
3128 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
3129 | dspcntr |= DISPPLANE_RGBX888; |
3130 | break; | |
3131 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
3132 | dspcntr |= DISPPLANE_BGRX101010; |
3133 | break; | |
3134 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 3135 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
3136 | break; |
3137 | default: | |
baba133a | 3138 | BUG(); |
17638cd6 JB |
3139 | } |
3140 | ||
bae781b2 | 3141 | if (fb->modifier == I915_FORMAT_MOD_X_TILED) |
17638cd6 | 3142 | dspcntr |= DISPPLANE_TILED; |
17638cd6 | 3143 | |
df0cd455 VS |
3144 | if (rotation & DRM_ROTATE_180) |
3145 | dspcntr |= DISPPLANE_ROTATE_180; | |
3146 | ||
8652744b | 3147 | if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) |
1f5d76db | 3148 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 3149 | |
2949056c | 3150 | intel_add_fb_offsets(&x, &y, plane_state, 0); |
6687c906 | 3151 | |
c2c75131 | 3152 | intel_crtc->dspaddr_offset = |
2949056c | 3153 | intel_compute_tile_offset(&x, &y, plane_state, 0); |
6687c906 | 3154 | |
df0cd455 VS |
3155 | /* HSW+ does this automagically in hardware */ |
3156 | if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv) && | |
3157 | rotation & DRM_ROTATE_180) { | |
3158 | x += crtc_state->pipe_src_w - 1; | |
3159 | y += crtc_state->pipe_src_h - 1; | |
48404c1e SJ |
3160 | } |
3161 | ||
2949056c | 3162 | linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0); |
6687c906 | 3163 | |
2db3366b PZ |
3164 | intel_crtc->adjusted_x = x; |
3165 | intel_crtc->adjusted_y = y; | |
3166 | ||
48404c1e | 3167 | I915_WRITE(reg, dspcntr); |
17638cd6 | 3168 | |
01f2c773 | 3169 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d | 3170 | I915_WRITE(DSPSURF(plane), |
be1e3415 | 3171 | intel_plane_ggtt_offset(plane_state) + |
6687c906 | 3172 | intel_crtc->dspaddr_offset); |
8652744b | 3173 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
bc1c91eb DL |
3174 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
3175 | } else { | |
3176 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
3177 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
3178 | } | |
17638cd6 | 3179 | POSTING_READ(reg); |
17638cd6 JB |
3180 | } |
3181 | ||
d88c4afd VS |
3182 | static u32 |
3183 | intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane) | |
b321803d | 3184 | { |
d88c4afd | 3185 | if (fb->modifier == DRM_FORMAT_MOD_NONE) |
b321803d | 3186 | return 64; |
d88c4afd VS |
3187 | else |
3188 | return intel_tile_width_bytes(fb, plane); | |
b321803d DL |
3189 | } |
3190 | ||
e435d6e5 ML |
3191 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
3192 | { | |
3193 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 3194 | struct drm_i915_private *dev_priv = to_i915(dev); |
e435d6e5 ML |
3195 | |
3196 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
3197 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
3198 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
3199 | } |
3200 | ||
a1b2278e CK |
3201 | /* |
3202 | * This function detaches (aka. unbinds) unused scalers in hardware | |
3203 | */ | |
0583236e | 3204 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 3205 | { |
a1b2278e CK |
3206 | struct intel_crtc_scaler_state *scaler_state; |
3207 | int i; | |
3208 | ||
a1b2278e CK |
3209 | scaler_state = &intel_crtc->config->scaler_state; |
3210 | ||
3211 | /* loop through and disable scalers that aren't in use */ | |
3212 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
3213 | if (!scaler_state->scalers[i].in_use) |
3214 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
3215 | } |
3216 | } | |
3217 | ||
d2196774 VS |
3218 | u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane, |
3219 | unsigned int rotation) | |
3220 | { | |
1b500535 VS |
3221 | u32 stride; |
3222 | ||
3223 | if (plane >= fb->format->num_planes) | |
3224 | return 0; | |
3225 | ||
3226 | stride = intel_fb_pitch(fb, plane, rotation); | |
d2196774 VS |
3227 | |
3228 | /* | |
3229 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
3230 | * linear buffers or in number of tiles for tiled buffers. | |
3231 | */ | |
d88c4afd VS |
3232 | if (drm_rotation_90_or_270(rotation)) |
3233 | stride /= intel_tile_height(fb, plane); | |
3234 | else | |
3235 | stride /= intel_fb_stride_alignment(fb, plane); | |
d2196774 VS |
3236 | |
3237 | return stride; | |
3238 | } | |
3239 | ||
6156a456 | 3240 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 3241 | { |
6156a456 | 3242 | switch (pixel_format) { |
d161cf7a | 3243 | case DRM_FORMAT_C8: |
c34ce3d1 | 3244 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 3245 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 3246 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 3247 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 3248 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 3249 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 3250 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
3251 | /* |
3252 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
3253 | * to be already pre-multiplied. We need to add a knob (or a different | |
3254 | * DRM_FORMAT) for user-space to configure that. | |
3255 | */ | |
f75fb42a | 3256 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 3257 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 3258 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 3259 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 3260 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 3261 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 3262 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 3263 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 3264 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 3265 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 3266 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 3267 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 3268 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 3269 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 3270 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 3271 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 3272 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 3273 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 3274 | default: |
4249eeef | 3275 | MISSING_CASE(pixel_format); |
70d21f0e | 3276 | } |
8cfcba41 | 3277 | |
c34ce3d1 | 3278 | return 0; |
6156a456 | 3279 | } |
70d21f0e | 3280 | |
6156a456 CK |
3281 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
3282 | { | |
6156a456 | 3283 | switch (fb_modifier) { |
30af77c4 | 3284 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 3285 | break; |
30af77c4 | 3286 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 3287 | return PLANE_CTL_TILED_X; |
b321803d | 3288 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3289 | return PLANE_CTL_TILED_Y; |
b321803d | 3290 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3291 | return PLANE_CTL_TILED_YF; |
70d21f0e | 3292 | default: |
6156a456 | 3293 | MISSING_CASE(fb_modifier); |
70d21f0e | 3294 | } |
8cfcba41 | 3295 | |
c34ce3d1 | 3296 | return 0; |
6156a456 | 3297 | } |
70d21f0e | 3298 | |
6156a456 CK |
3299 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
3300 | { | |
3b7a5119 | 3301 | switch (rotation) { |
31ad61e4 | 3302 | case DRM_ROTATE_0: |
6156a456 | 3303 | break; |
1e8df167 SJ |
3304 | /* |
3305 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
3306 | * while i915 HW rotation is clockwise, thats why this swapping. | |
3307 | */ | |
31ad61e4 | 3308 | case DRM_ROTATE_90: |
1e8df167 | 3309 | return PLANE_CTL_ROTATE_270; |
31ad61e4 | 3310 | case DRM_ROTATE_180: |
c34ce3d1 | 3311 | return PLANE_CTL_ROTATE_180; |
31ad61e4 | 3312 | case DRM_ROTATE_270: |
1e8df167 | 3313 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3314 | default: |
3315 | MISSING_CASE(rotation); | |
3316 | } | |
3317 | ||
c34ce3d1 | 3318 | return 0; |
6156a456 CK |
3319 | } |
3320 | ||
a8d201af ML |
3321 | static void skylake_update_primary_plane(struct drm_plane *plane, |
3322 | const struct intel_crtc_state *crtc_state, | |
3323 | const struct intel_plane_state *plane_state) | |
6156a456 | 3324 | { |
a8d201af | 3325 | struct drm_device *dev = plane->dev; |
fac5e23e | 3326 | struct drm_i915_private *dev_priv = to_i915(dev); |
a8d201af ML |
3327 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3328 | struct drm_framebuffer *fb = plane_state->base.fb; | |
8e816bb4 VS |
3329 | enum plane_id plane_id = to_intel_plane(plane)->id; |
3330 | enum pipe pipe = to_intel_plane(plane)->pipe; | |
d2196774 | 3331 | u32 plane_ctl; |
a8d201af | 3332 | unsigned int rotation = plane_state->base.rotation; |
d2196774 | 3333 | u32 stride = skl_plane_stride(fb, 0, rotation); |
b63a16f6 | 3334 | u32 surf_addr = plane_state->main.offset; |
a8d201af | 3335 | int scaler_id = plane_state->scaler_id; |
b63a16f6 VS |
3336 | int src_x = plane_state->main.x; |
3337 | int src_y = plane_state->main.y; | |
936e71e3 VS |
3338 | int src_w = drm_rect_width(&plane_state->base.src) >> 16; |
3339 | int src_h = drm_rect_height(&plane_state->base.src) >> 16; | |
3340 | int dst_x = plane_state->base.dst.x1; | |
3341 | int dst_y = plane_state->base.dst.y1; | |
3342 | int dst_w = drm_rect_width(&plane_state->base.dst); | |
3343 | int dst_h = drm_rect_height(&plane_state->base.dst); | |
70d21f0e | 3344 | |
47f9ea8b ACO |
3345 | plane_ctl = PLANE_CTL_ENABLE; |
3346 | ||
3347 | if (IS_GEMINILAKE(dev_priv)) { | |
3348 | I915_WRITE(PLANE_COLOR_CTL(pipe, plane_id), | |
3349 | PLANE_COLOR_PIPE_GAMMA_ENABLE | | |
3bb56da7 | 3350 | PLANE_COLOR_PIPE_CSC_ENABLE | |
47f9ea8b ACO |
3351 | PLANE_COLOR_PLANE_GAMMA_DISABLE); |
3352 | } else { | |
3353 | plane_ctl |= | |
3354 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3355 | PLANE_CTL_PIPE_CSC_ENABLE | | |
3356 | PLANE_CTL_PLANE_GAMMA_DISABLE; | |
3357 | } | |
6156a456 | 3358 | |
438b74a5 | 3359 | plane_ctl |= skl_plane_ctl_format(fb->format->format); |
bae781b2 | 3360 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier); |
6156a456 CK |
3361 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
3362 | ||
6687c906 VS |
3363 | /* Sizes are 0 based */ |
3364 | src_w--; | |
3365 | src_h--; | |
3366 | dst_w--; | |
3367 | dst_h--; | |
3368 | ||
4c0b8a8b PZ |
3369 | intel_crtc->dspaddr_offset = surf_addr; |
3370 | ||
6687c906 VS |
3371 | intel_crtc->adjusted_x = src_x; |
3372 | intel_crtc->adjusted_y = src_y; | |
2db3366b | 3373 | |
8e816bb4 VS |
3374 | I915_WRITE(PLANE_CTL(pipe, plane_id), plane_ctl); |
3375 | I915_WRITE(PLANE_OFFSET(pipe, plane_id), (src_y << 16) | src_x); | |
3376 | I915_WRITE(PLANE_STRIDE(pipe, plane_id), stride); | |
3377 | I915_WRITE(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w); | |
6156a456 CK |
3378 | |
3379 | if (scaler_id >= 0) { | |
3380 | uint32_t ps_ctrl = 0; | |
3381 | ||
3382 | WARN_ON(!dst_w || !dst_h); | |
8e816bb4 | 3383 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(plane_id) | |
6156a456 CK |
3384 | crtc_state->scaler_state.scalers[scaler_id].mode; |
3385 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3386 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3387 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3388 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
8e816bb4 | 3389 | I915_WRITE(PLANE_POS(pipe, plane_id), 0); |
6156a456 | 3390 | } else { |
8e816bb4 | 3391 | I915_WRITE(PLANE_POS(pipe, plane_id), (dst_y << 16) | dst_x); |
6156a456 CK |
3392 | } |
3393 | ||
8e816bb4 | 3394 | I915_WRITE(PLANE_SURF(pipe, plane_id), |
be1e3415 | 3395 | intel_plane_ggtt_offset(plane_state) + surf_addr); |
70d21f0e | 3396 | |
8e816bb4 | 3397 | POSTING_READ(PLANE_SURF(pipe, plane_id)); |
70d21f0e DL |
3398 | } |
3399 | ||
a8d201af ML |
3400 | static void skylake_disable_primary_plane(struct drm_plane *primary, |
3401 | struct drm_crtc *crtc) | |
17638cd6 JB |
3402 | { |
3403 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 3404 | struct drm_i915_private *dev_priv = to_i915(dev); |
8e816bb4 VS |
3405 | enum plane_id plane_id = to_intel_plane(primary)->id; |
3406 | enum pipe pipe = to_intel_plane(primary)->pipe; | |
62e0fb88 | 3407 | |
8e816bb4 VS |
3408 | I915_WRITE(PLANE_CTL(pipe, plane_id), 0); |
3409 | I915_WRITE(PLANE_SURF(pipe, plane_id), 0); | |
3410 | POSTING_READ(PLANE_SURF(pipe, plane_id)); | |
a8d201af | 3411 | } |
29b9bde6 | 3412 | |
a8d201af ML |
3413 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3414 | static int | |
3415 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3416 | int x, int y, enum mode_set_atomic state) | |
3417 | { | |
3418 | /* Support for kgdboc is disabled, this needs a major rework. */ | |
3419 | DRM_ERROR("legacy panic handler not supported any more.\n"); | |
3420 | ||
3421 | return -ENODEV; | |
81255565 JB |
3422 | } |
3423 | ||
5a21b665 DV |
3424 | static void intel_complete_page_flips(struct drm_i915_private *dev_priv) |
3425 | { | |
3426 | struct intel_crtc *crtc; | |
3427 | ||
91c8a326 | 3428 | for_each_intel_crtc(&dev_priv->drm, crtc) |
5a21b665 DV |
3429 | intel_finish_page_flip_cs(dev_priv, crtc->pipe); |
3430 | } | |
3431 | ||
7514747d VS |
3432 | static void intel_update_primary_planes(struct drm_device *dev) |
3433 | { | |
7514747d | 3434 | struct drm_crtc *crtc; |
96a02917 | 3435 | |
70e1e0ec | 3436 | for_each_crtc(dev, crtc) { |
11c22da6 | 3437 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
73974893 ML |
3438 | struct intel_plane_state *plane_state = |
3439 | to_intel_plane_state(plane->base.state); | |
11c22da6 | 3440 | |
72259536 VS |
3441 | if (plane_state->base.visible) { |
3442 | trace_intel_update_plane(&plane->base, | |
3443 | to_intel_crtc(crtc)); | |
3444 | ||
a8d201af ML |
3445 | plane->update_plane(&plane->base, |
3446 | to_intel_crtc_state(crtc->state), | |
3447 | plane_state); | |
72259536 | 3448 | } |
73974893 ML |
3449 | } |
3450 | } | |
3451 | ||
3452 | static int | |
3453 | __intel_display_resume(struct drm_device *dev, | |
581e49fe ML |
3454 | struct drm_atomic_state *state, |
3455 | struct drm_modeset_acquire_ctx *ctx) | |
73974893 ML |
3456 | { |
3457 | struct drm_crtc_state *crtc_state; | |
3458 | struct drm_crtc *crtc; | |
3459 | int i, ret; | |
11c22da6 | 3460 | |
73974893 | 3461 | intel_modeset_setup_hw_state(dev); |
29b74b7f | 3462 | i915_redisable_vga(to_i915(dev)); |
73974893 ML |
3463 | |
3464 | if (!state) | |
3465 | return 0; | |
3466 | ||
3467 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
3468 | /* | |
3469 | * Force recalculation even if we restore | |
3470 | * current state. With fast modeset this may not result | |
3471 | * in a modeset when the state is compatible. | |
3472 | */ | |
3473 | crtc_state->mode_changed = true; | |
96a02917 | 3474 | } |
73974893 ML |
3475 | |
3476 | /* ignore any reset values/BIOS leftovers in the WM registers */ | |
602ae835 VS |
3477 | if (!HAS_GMCH_DISPLAY(to_i915(dev))) |
3478 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
73974893 | 3479 | |
581e49fe | 3480 | ret = drm_atomic_helper_commit_duplicated_state(state, ctx); |
73974893 ML |
3481 | |
3482 | WARN_ON(ret == -EDEADLK); | |
3483 | return ret; | |
96a02917 VS |
3484 | } |
3485 | ||
4ac2ba2f VS |
3486 | static bool gpu_reset_clobbers_display(struct drm_i915_private *dev_priv) |
3487 | { | |
ae98104b VS |
3488 | return intel_has_gpu_reset(dev_priv) && |
3489 | INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv); | |
4ac2ba2f VS |
3490 | } |
3491 | ||
c033666a | 3492 | void intel_prepare_reset(struct drm_i915_private *dev_priv) |
7514747d | 3493 | { |
73974893 ML |
3494 | struct drm_device *dev = &dev_priv->drm; |
3495 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3496 | struct drm_atomic_state *state; | |
3497 | int ret; | |
3498 | ||
73974893 ML |
3499 | /* |
3500 | * Need mode_config.mutex so that we don't | |
3501 | * trample ongoing ->detect() and whatnot. | |
3502 | */ | |
3503 | mutex_lock(&dev->mode_config.mutex); | |
3504 | drm_modeset_acquire_init(ctx, 0); | |
3505 | while (1) { | |
3506 | ret = drm_modeset_lock_all_ctx(dev, ctx); | |
3507 | if (ret != -EDEADLK) | |
3508 | break; | |
3509 | ||
3510 | drm_modeset_backoff(ctx); | |
3511 | } | |
3512 | ||
3513 | /* reset doesn't touch the display, but flips might get nuked anyway, */ | |
522a63de | 3514 | if (!i915.force_reset_modeset_test && |
4ac2ba2f | 3515 | !gpu_reset_clobbers_display(dev_priv)) |
7514747d VS |
3516 | return; |
3517 | ||
f98ce92f VS |
3518 | /* |
3519 | * Disabling the crtcs gracefully seems nicer. Also the | |
3520 | * g33 docs say we should at least disable all the planes. | |
3521 | */ | |
73974893 ML |
3522 | state = drm_atomic_helper_duplicate_state(dev, ctx); |
3523 | if (IS_ERR(state)) { | |
3524 | ret = PTR_ERR(state); | |
73974893 | 3525 | DRM_ERROR("Duplicating state failed with %i\n", ret); |
1e5a15d6 | 3526 | return; |
73974893 ML |
3527 | } |
3528 | ||
3529 | ret = drm_atomic_helper_disable_all(dev, ctx); | |
3530 | if (ret) { | |
3531 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
1e5a15d6 ACO |
3532 | drm_atomic_state_put(state); |
3533 | return; | |
73974893 ML |
3534 | } |
3535 | ||
3536 | dev_priv->modeset_restore_state = state; | |
3537 | state->acquire_ctx = ctx; | |
7514747d VS |
3538 | } |
3539 | ||
c033666a | 3540 | void intel_finish_reset(struct drm_i915_private *dev_priv) |
7514747d | 3541 | { |
73974893 ML |
3542 | struct drm_device *dev = &dev_priv->drm; |
3543 | struct drm_modeset_acquire_ctx *ctx = &dev_priv->reset_ctx; | |
3544 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
3545 | int ret; | |
3546 | ||
5a21b665 DV |
3547 | /* |
3548 | * Flips in the rings will be nuked by the reset, | |
3549 | * so complete all pending flips so that user space | |
3550 | * will get its events and not get stuck. | |
3551 | */ | |
3552 | intel_complete_page_flips(dev_priv); | |
3553 | ||
73974893 ML |
3554 | dev_priv->modeset_restore_state = NULL; |
3555 | ||
7514747d | 3556 | /* reset doesn't touch the display */ |
4ac2ba2f | 3557 | if (!gpu_reset_clobbers_display(dev_priv)) { |
522a63de ML |
3558 | if (!state) { |
3559 | /* | |
3560 | * Flips in the rings have been nuked by the reset, | |
3561 | * so update the base address of all primary | |
3562 | * planes to the the last fb to make sure we're | |
3563 | * showing the correct fb after a reset. | |
3564 | * | |
3565 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3566 | * CS-based flips (which might get lost in gpu resets) any more. | |
3567 | */ | |
3568 | intel_update_primary_planes(dev); | |
3569 | } else { | |
581e49fe | 3570 | ret = __intel_display_resume(dev, state, ctx); |
522a63de ML |
3571 | if (ret) |
3572 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
3573 | } | |
73974893 ML |
3574 | } else { |
3575 | /* | |
3576 | * The display has been reset as well, | |
3577 | * so need a full re-initialization. | |
3578 | */ | |
3579 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3580 | intel_runtime_pm_enable_interrupts(dev_priv); | |
7514747d | 3581 | |
51f59205 | 3582 | intel_pps_unlock_regs_wa(dev_priv); |
73974893 | 3583 | intel_modeset_init_hw(dev); |
7514747d | 3584 | |
73974893 ML |
3585 | spin_lock_irq(&dev_priv->irq_lock); |
3586 | if (dev_priv->display.hpd_irq_setup) | |
3587 | dev_priv->display.hpd_irq_setup(dev_priv); | |
3588 | spin_unlock_irq(&dev_priv->irq_lock); | |
7514747d | 3589 | |
581e49fe | 3590 | ret = __intel_display_resume(dev, state, ctx); |
73974893 ML |
3591 | if (ret) |
3592 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
7514747d | 3593 | |
73974893 ML |
3594 | intel_hpd_init(dev_priv); |
3595 | } | |
7514747d | 3596 | |
0853695c CW |
3597 | if (state) |
3598 | drm_atomic_state_put(state); | |
73974893 ML |
3599 | drm_modeset_drop_locks(ctx); |
3600 | drm_modeset_acquire_fini(ctx); | |
3601 | mutex_unlock(&dev->mode_config.mutex); | |
7514747d VS |
3602 | } |
3603 | ||
8af29b0c CW |
3604 | static bool abort_flip_on_reset(struct intel_crtc *crtc) |
3605 | { | |
3606 | struct i915_gpu_error *error = &to_i915(crtc->base.dev)->gpu_error; | |
3607 | ||
3608 | if (i915_reset_in_progress(error)) | |
3609 | return true; | |
3610 | ||
3611 | if (crtc->reset_count != i915_reset_count(error)) | |
3612 | return true; | |
3613 | ||
3614 | return false; | |
3615 | } | |
3616 | ||
7d5e3799 CW |
3617 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3618 | { | |
5a21b665 DV |
3619 | struct drm_device *dev = crtc->dev; |
3620 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5a21b665 DV |
3621 | bool pending; |
3622 | ||
8af29b0c | 3623 | if (abort_flip_on_reset(intel_crtc)) |
5a21b665 DV |
3624 | return false; |
3625 | ||
3626 | spin_lock_irq(&dev->event_lock); | |
3627 | pending = to_intel_crtc(crtc)->flip_work != NULL; | |
3628 | spin_unlock_irq(&dev->event_lock); | |
3629 | ||
3630 | return pending; | |
7d5e3799 CW |
3631 | } |
3632 | ||
bfd16b2a ML |
3633 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3634 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 | 3635 | { |
6315b5d3 | 3636 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
bfd16b2a ML |
3637 | struct intel_crtc_state *pipe_config = |
3638 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3639 | |
bfd16b2a ML |
3640 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3641 | crtc->base.mode = crtc->base.state->mode; | |
3642 | ||
e30e8f75 GP |
3643 | /* |
3644 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3645 | * that in compute_mode_changes we check the native mode (not the pfit | |
3646 | * mode) to see if we can flip rather than do a full mode set. In the | |
3647 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3648 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3649 | * sized surface. | |
e30e8f75 GP |
3650 | */ |
3651 | ||
e30e8f75 | 3652 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3653 | ((pipe_config->pipe_src_w - 1) << 16) | |
3654 | (pipe_config->pipe_src_h - 1)); | |
3655 | ||
3656 | /* on skylake this is done by detaching scalers */ | |
6315b5d3 | 3657 | if (INTEL_GEN(dev_priv) >= 9) { |
bfd16b2a ML |
3658 | skl_detach_scalers(crtc); |
3659 | ||
3660 | if (pipe_config->pch_pfit.enabled) | |
3661 | skylake_pfit_enable(crtc); | |
6e266956 | 3662 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
bfd16b2a ML |
3663 | if (pipe_config->pch_pfit.enabled) |
3664 | ironlake_pfit_enable(crtc); | |
3665 | else if (old_crtc_state->pch_pfit.enabled) | |
3666 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3667 | } |
e30e8f75 GP |
3668 | } |
3669 | ||
4cbe4b2b | 3670 | static void intel_fdi_normal_train(struct intel_crtc *crtc) |
5e84e1a4 | 3671 | { |
4cbe4b2b | 3672 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3673 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3674 | int pipe = crtc->pipe; |
f0f59a00 VS |
3675 | i915_reg_t reg; |
3676 | u32 temp; | |
5e84e1a4 ZW |
3677 | |
3678 | /* enable normal train */ | |
3679 | reg = FDI_TX_CTL(pipe); | |
3680 | temp = I915_READ(reg); | |
fd6b8f43 | 3681 | if (IS_IVYBRIDGE(dev_priv)) { |
357555c0 JB |
3682 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3683 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3684 | } else { |
3685 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3686 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3687 | } |
5e84e1a4 ZW |
3688 | I915_WRITE(reg, temp); |
3689 | ||
3690 | reg = FDI_RX_CTL(pipe); | |
3691 | temp = I915_READ(reg); | |
6e266956 | 3692 | if (HAS_PCH_CPT(dev_priv)) { |
5e84e1a4 ZW |
3693 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3694 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3695 | } else { | |
3696 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3697 | temp |= FDI_LINK_TRAIN_NONE; | |
3698 | } | |
3699 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3700 | ||
3701 | /* wait one idle pattern time */ | |
3702 | POSTING_READ(reg); | |
3703 | udelay(1000); | |
357555c0 JB |
3704 | |
3705 | /* IVB wants error correction enabled */ | |
fd6b8f43 | 3706 | if (IS_IVYBRIDGE(dev_priv)) |
357555c0 JB |
3707 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | |
3708 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3709 | } |
3710 | ||
8db9d77b | 3711 | /* The FDI link training functions for ILK/Ibexpeak. */ |
dc4a1094 ACO |
3712 | static void ironlake_fdi_link_train(struct intel_crtc *crtc, |
3713 | const struct intel_crtc_state *crtc_state) | |
8db9d77b | 3714 | { |
4cbe4b2b | 3715 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3716 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3717 | int pipe = crtc->pipe; |
f0f59a00 VS |
3718 | i915_reg_t reg; |
3719 | u32 temp, tries; | |
8db9d77b | 3720 | |
1c8562f6 | 3721 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3722 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3723 | |
e1a44743 AJ |
3724 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3725 | for train result */ | |
5eddb70b CW |
3726 | reg = FDI_RX_IMR(pipe); |
3727 | temp = I915_READ(reg); | |
e1a44743 AJ |
3728 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3729 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3730 | I915_WRITE(reg, temp); |
3731 | I915_READ(reg); | |
e1a44743 AJ |
3732 | udelay(150); |
3733 | ||
8db9d77b | 3734 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3735 | reg = FDI_TX_CTL(pipe); |
3736 | temp = I915_READ(reg); | |
627eb5a3 | 3737 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 3738 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
8db9d77b ZW |
3739 | temp &= ~FDI_LINK_TRAIN_NONE; |
3740 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3741 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3742 | |
5eddb70b CW |
3743 | reg = FDI_RX_CTL(pipe); |
3744 | temp = I915_READ(reg); | |
8db9d77b ZW |
3745 | temp &= ~FDI_LINK_TRAIN_NONE; |
3746 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3747 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3748 | ||
3749 | POSTING_READ(reg); | |
8db9d77b ZW |
3750 | udelay(150); |
3751 | ||
5b2adf89 | 3752 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3753 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3754 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3755 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3756 | |
5eddb70b | 3757 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3758 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3759 | temp = I915_READ(reg); |
8db9d77b ZW |
3760 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3761 | ||
3762 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3763 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3764 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3765 | break; |
3766 | } | |
8db9d77b | 3767 | } |
e1a44743 | 3768 | if (tries == 5) |
5eddb70b | 3769 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3770 | |
3771 | /* Train 2 */ | |
5eddb70b CW |
3772 | reg = FDI_TX_CTL(pipe); |
3773 | temp = I915_READ(reg); | |
8db9d77b ZW |
3774 | temp &= ~FDI_LINK_TRAIN_NONE; |
3775 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3776 | I915_WRITE(reg, temp); |
8db9d77b | 3777 | |
5eddb70b CW |
3778 | reg = FDI_RX_CTL(pipe); |
3779 | temp = I915_READ(reg); | |
8db9d77b ZW |
3780 | temp &= ~FDI_LINK_TRAIN_NONE; |
3781 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3782 | I915_WRITE(reg, temp); |
8db9d77b | 3783 | |
5eddb70b CW |
3784 | POSTING_READ(reg); |
3785 | udelay(150); | |
8db9d77b | 3786 | |
5eddb70b | 3787 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3788 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3789 | temp = I915_READ(reg); |
8db9d77b ZW |
3790 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3791 | ||
3792 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3793 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3794 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3795 | break; | |
3796 | } | |
8db9d77b | 3797 | } |
e1a44743 | 3798 | if (tries == 5) |
5eddb70b | 3799 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3800 | |
3801 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3802 | |
8db9d77b ZW |
3803 | } |
3804 | ||
0206e353 | 3805 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3806 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3807 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3808 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3809 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3810 | }; | |
3811 | ||
3812 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
dc4a1094 ACO |
3813 | static void gen6_fdi_link_train(struct intel_crtc *crtc, |
3814 | const struct intel_crtc_state *crtc_state) | |
8db9d77b | 3815 | { |
4cbe4b2b | 3816 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3817 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3818 | int pipe = crtc->pipe; |
f0f59a00 VS |
3819 | i915_reg_t reg; |
3820 | u32 temp, i, retry; | |
8db9d77b | 3821 | |
e1a44743 AJ |
3822 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3823 | for train result */ | |
5eddb70b CW |
3824 | reg = FDI_RX_IMR(pipe); |
3825 | temp = I915_READ(reg); | |
e1a44743 AJ |
3826 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3827 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3828 | I915_WRITE(reg, temp); |
3829 | ||
3830 | POSTING_READ(reg); | |
e1a44743 AJ |
3831 | udelay(150); |
3832 | ||
8db9d77b | 3833 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3834 | reg = FDI_TX_CTL(pipe); |
3835 | temp = I915_READ(reg); | |
627eb5a3 | 3836 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 3837 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
8db9d77b ZW |
3838 | temp &= ~FDI_LINK_TRAIN_NONE; |
3839 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3840 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3841 | /* SNB-B */ | |
3842 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3843 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3844 | |
d74cf324 DV |
3845 | I915_WRITE(FDI_RX_MISC(pipe), |
3846 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3847 | ||
5eddb70b CW |
3848 | reg = FDI_RX_CTL(pipe); |
3849 | temp = I915_READ(reg); | |
6e266956 | 3850 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
3851 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3852 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3853 | } else { | |
3854 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3855 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3856 | } | |
5eddb70b CW |
3857 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3858 | ||
3859 | POSTING_READ(reg); | |
8db9d77b ZW |
3860 | udelay(150); |
3861 | ||
0206e353 | 3862 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3863 | reg = FDI_TX_CTL(pipe); |
3864 | temp = I915_READ(reg); | |
8db9d77b ZW |
3865 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3866 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3867 | I915_WRITE(reg, temp); |
3868 | ||
3869 | POSTING_READ(reg); | |
8db9d77b ZW |
3870 | udelay(500); |
3871 | ||
fa37d39e SP |
3872 | for (retry = 0; retry < 5; retry++) { |
3873 | reg = FDI_RX_IIR(pipe); | |
3874 | temp = I915_READ(reg); | |
3875 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3876 | if (temp & FDI_RX_BIT_LOCK) { | |
3877 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3878 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3879 | break; | |
3880 | } | |
3881 | udelay(50); | |
8db9d77b | 3882 | } |
fa37d39e SP |
3883 | if (retry < 5) |
3884 | break; | |
8db9d77b ZW |
3885 | } |
3886 | if (i == 4) | |
5eddb70b | 3887 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3888 | |
3889 | /* Train 2 */ | |
5eddb70b CW |
3890 | reg = FDI_TX_CTL(pipe); |
3891 | temp = I915_READ(reg); | |
8db9d77b ZW |
3892 | temp &= ~FDI_LINK_TRAIN_NONE; |
3893 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5db94019 | 3894 | if (IS_GEN6(dev_priv)) { |
8db9d77b ZW |
3895 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3896 | /* SNB-B */ | |
3897 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3898 | } | |
5eddb70b | 3899 | I915_WRITE(reg, temp); |
8db9d77b | 3900 | |
5eddb70b CW |
3901 | reg = FDI_RX_CTL(pipe); |
3902 | temp = I915_READ(reg); | |
6e266956 | 3903 | if (HAS_PCH_CPT(dev_priv)) { |
8db9d77b ZW |
3904 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
3905 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3906 | } else { | |
3907 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3908 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3909 | } | |
5eddb70b CW |
3910 | I915_WRITE(reg, temp); |
3911 | ||
3912 | POSTING_READ(reg); | |
8db9d77b ZW |
3913 | udelay(150); |
3914 | ||
0206e353 | 3915 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3916 | reg = FDI_TX_CTL(pipe); |
3917 | temp = I915_READ(reg); | |
8db9d77b ZW |
3918 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3919 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3920 | I915_WRITE(reg, temp); |
3921 | ||
3922 | POSTING_READ(reg); | |
8db9d77b ZW |
3923 | udelay(500); |
3924 | ||
fa37d39e SP |
3925 | for (retry = 0; retry < 5; retry++) { |
3926 | reg = FDI_RX_IIR(pipe); | |
3927 | temp = I915_READ(reg); | |
3928 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3929 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3930 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3931 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3932 | break; | |
3933 | } | |
3934 | udelay(50); | |
8db9d77b | 3935 | } |
fa37d39e SP |
3936 | if (retry < 5) |
3937 | break; | |
8db9d77b ZW |
3938 | } |
3939 | if (i == 4) | |
5eddb70b | 3940 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3941 | |
3942 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3943 | } | |
3944 | ||
357555c0 | 3945 | /* Manual link training for Ivy Bridge A0 parts */ |
dc4a1094 ACO |
3946 | static void ivb_manual_fdi_link_train(struct intel_crtc *crtc, |
3947 | const struct intel_crtc_state *crtc_state) | |
357555c0 | 3948 | { |
4cbe4b2b | 3949 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 3950 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 3951 | int pipe = crtc->pipe; |
f0f59a00 VS |
3952 | i915_reg_t reg; |
3953 | u32 temp, i, j; | |
357555c0 JB |
3954 | |
3955 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3956 | for train result */ | |
3957 | reg = FDI_RX_IMR(pipe); | |
3958 | temp = I915_READ(reg); | |
3959 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3960 | temp &= ~FDI_RX_BIT_LOCK; | |
3961 | I915_WRITE(reg, temp); | |
3962 | ||
3963 | POSTING_READ(reg); | |
3964 | udelay(150); | |
3965 | ||
01a415fd DV |
3966 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3967 | I915_READ(FDI_RX_IIR(pipe))); | |
3968 | ||
139ccd3f JB |
3969 | /* Try each vswing and preemphasis setting twice before moving on */ |
3970 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3971 | /* disable first in case we need to retry */ | |
3972 | reg = FDI_TX_CTL(pipe); | |
3973 | temp = I915_READ(reg); | |
3974 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3975 | temp &= ~FDI_TX_ENABLE; | |
3976 | I915_WRITE(reg, temp); | |
357555c0 | 3977 | |
139ccd3f JB |
3978 | reg = FDI_RX_CTL(pipe); |
3979 | temp = I915_READ(reg); | |
3980 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3981 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3982 | temp &= ~FDI_RX_ENABLE; | |
3983 | I915_WRITE(reg, temp); | |
357555c0 | 3984 | |
139ccd3f | 3985 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3986 | reg = FDI_TX_CTL(pipe); |
3987 | temp = I915_READ(reg); | |
139ccd3f | 3988 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
dc4a1094 | 3989 | temp |= FDI_DP_PORT_WIDTH(crtc_state->fdi_lanes); |
139ccd3f | 3990 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3991 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3992 | temp |= snb_b_fdi_train_param[j/2]; |
3993 | temp |= FDI_COMPOSITE_SYNC; | |
3994 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3995 | |
139ccd3f JB |
3996 | I915_WRITE(FDI_RX_MISC(pipe), |
3997 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3998 | |
139ccd3f | 3999 | reg = FDI_RX_CTL(pipe); |
357555c0 | 4000 | temp = I915_READ(reg); |
139ccd3f JB |
4001 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
4002 | temp |= FDI_COMPOSITE_SYNC; | |
4003 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 4004 | |
139ccd3f JB |
4005 | POSTING_READ(reg); |
4006 | udelay(1); /* should be 0.5us */ | |
357555c0 | 4007 | |
139ccd3f JB |
4008 | for (i = 0; i < 4; i++) { |
4009 | reg = FDI_RX_IIR(pipe); | |
4010 | temp = I915_READ(reg); | |
4011 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 4012 | |
139ccd3f JB |
4013 | if (temp & FDI_RX_BIT_LOCK || |
4014 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
4015 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
4016 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
4017 | i); | |
4018 | break; | |
4019 | } | |
4020 | udelay(1); /* should be 0.5us */ | |
4021 | } | |
4022 | if (i == 4) { | |
4023 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
4024 | continue; | |
4025 | } | |
357555c0 | 4026 | |
139ccd3f | 4027 | /* Train 2 */ |
357555c0 JB |
4028 | reg = FDI_TX_CTL(pipe); |
4029 | temp = I915_READ(reg); | |
139ccd3f JB |
4030 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
4031 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
4032 | I915_WRITE(reg, temp); | |
4033 | ||
4034 | reg = FDI_RX_CTL(pipe); | |
4035 | temp = I915_READ(reg); | |
4036 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
4037 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
4038 | I915_WRITE(reg, temp); |
4039 | ||
4040 | POSTING_READ(reg); | |
139ccd3f | 4041 | udelay(2); /* should be 1.5us */ |
357555c0 | 4042 | |
139ccd3f JB |
4043 | for (i = 0; i < 4; i++) { |
4044 | reg = FDI_RX_IIR(pipe); | |
4045 | temp = I915_READ(reg); | |
4046 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 4047 | |
139ccd3f JB |
4048 | if (temp & FDI_RX_SYMBOL_LOCK || |
4049 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
4050 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
4051 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
4052 | i); | |
4053 | goto train_done; | |
4054 | } | |
4055 | udelay(2); /* should be 1.5us */ | |
357555c0 | 4056 | } |
139ccd3f JB |
4057 | if (i == 4) |
4058 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 4059 | } |
357555c0 | 4060 | |
139ccd3f | 4061 | train_done: |
357555c0 JB |
4062 | DRM_DEBUG_KMS("FDI train done.\n"); |
4063 | } | |
4064 | ||
88cefb6c | 4065 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 4066 | { |
88cefb6c | 4067 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 4068 | struct drm_i915_private *dev_priv = to_i915(dev); |
2c07245f | 4069 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
4070 | i915_reg_t reg; |
4071 | u32 temp; | |
c64e311e | 4072 | |
c98e9dcf | 4073 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
4074 | reg = FDI_RX_CTL(pipe); |
4075 | temp = I915_READ(reg); | |
627eb5a3 | 4076 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 4077 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 4078 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
4079 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
4080 | ||
4081 | POSTING_READ(reg); | |
c98e9dcf JB |
4082 | udelay(200); |
4083 | ||
4084 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
4085 | temp = I915_READ(reg); |
4086 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
4087 | ||
4088 | POSTING_READ(reg); | |
c98e9dcf JB |
4089 | udelay(200); |
4090 | ||
20749730 PZ |
4091 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
4092 | reg = FDI_TX_CTL(pipe); | |
4093 | temp = I915_READ(reg); | |
4094 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
4095 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 4096 | |
20749730 PZ |
4097 | POSTING_READ(reg); |
4098 | udelay(100); | |
6be4a607 | 4099 | } |
0e23b99d JB |
4100 | } |
4101 | ||
88cefb6c DV |
4102 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
4103 | { | |
4104 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 4105 | struct drm_i915_private *dev_priv = to_i915(dev); |
88cefb6c | 4106 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
4107 | i915_reg_t reg; |
4108 | u32 temp; | |
88cefb6c DV |
4109 | |
4110 | /* Switch from PCDclk to Rawclk */ | |
4111 | reg = FDI_RX_CTL(pipe); | |
4112 | temp = I915_READ(reg); | |
4113 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
4114 | ||
4115 | /* Disable CPU FDI TX PLL */ | |
4116 | reg = FDI_TX_CTL(pipe); | |
4117 | temp = I915_READ(reg); | |
4118 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
4119 | ||
4120 | POSTING_READ(reg); | |
4121 | udelay(100); | |
4122 | ||
4123 | reg = FDI_RX_CTL(pipe); | |
4124 | temp = I915_READ(reg); | |
4125 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
4126 | ||
4127 | /* Wait for the clocks to turn off. */ | |
4128 | POSTING_READ(reg); | |
4129 | udelay(100); | |
4130 | } | |
4131 | ||
0fc932b8 JB |
4132 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
4133 | { | |
4134 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4135 | struct drm_i915_private *dev_priv = to_i915(dev); |
0fc932b8 JB |
4136 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4137 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
4138 | i915_reg_t reg; |
4139 | u32 temp; | |
0fc932b8 JB |
4140 | |
4141 | /* disable CPU FDI tx and PCH FDI rx */ | |
4142 | reg = FDI_TX_CTL(pipe); | |
4143 | temp = I915_READ(reg); | |
4144 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
4145 | POSTING_READ(reg); | |
4146 | ||
4147 | reg = FDI_RX_CTL(pipe); | |
4148 | temp = I915_READ(reg); | |
4149 | temp &= ~(0x7 << 16); | |
dfd07d72 | 4150 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
4151 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
4152 | ||
4153 | POSTING_READ(reg); | |
4154 | udelay(100); | |
4155 | ||
4156 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
6e266956 | 4157 | if (HAS_PCH_IBX(dev_priv)) |
6f06ce18 | 4158 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
4159 | |
4160 | /* still set train pattern 1 */ | |
4161 | reg = FDI_TX_CTL(pipe); | |
4162 | temp = I915_READ(reg); | |
4163 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4164 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4165 | I915_WRITE(reg, temp); | |
4166 | ||
4167 | reg = FDI_RX_CTL(pipe); | |
4168 | temp = I915_READ(reg); | |
6e266956 | 4169 | if (HAS_PCH_CPT(dev_priv)) { |
0fc932b8 JB |
4170 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; |
4171 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
4172 | } else { | |
4173 | temp &= ~FDI_LINK_TRAIN_NONE; | |
4174 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
4175 | } | |
4176 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
4177 | temp &= ~(0x07 << 16); | |
dfd07d72 | 4178 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
4179 | I915_WRITE(reg, temp); |
4180 | ||
4181 | POSTING_READ(reg); | |
4182 | udelay(100); | |
4183 | } | |
4184 | ||
49d73912 | 4185 | bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv) |
5dce5b93 CW |
4186 | { |
4187 | struct intel_crtc *crtc; | |
4188 | ||
4189 | /* Note that we don't need to be called with mode_config.lock here | |
4190 | * as our list of CRTC objects is static for the lifetime of the | |
4191 | * device and so cannot disappear as we iterate. Similarly, we can | |
4192 | * happily treat the predicates as racy, atomic checks as userspace | |
4193 | * cannot claim and pin a new fb without at least acquring the | |
4194 | * struct_mutex and so serialising with us. | |
4195 | */ | |
49d73912 | 4196 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
5dce5b93 CW |
4197 | if (atomic_read(&crtc->unpin_work_count) == 0) |
4198 | continue; | |
4199 | ||
5a21b665 | 4200 | if (crtc->flip_work) |
0f0f74bc | 4201 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
5dce5b93 CW |
4202 | |
4203 | return true; | |
4204 | } | |
4205 | ||
4206 | return false; | |
4207 | } | |
4208 | ||
5a21b665 | 4209 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
d6bbafa1 CW |
4210 | { |
4211 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
5a21b665 DV |
4212 | struct intel_flip_work *work = intel_crtc->flip_work; |
4213 | ||
4214 | intel_crtc->flip_work = NULL; | |
d6bbafa1 CW |
4215 | |
4216 | if (work->event) | |
560ce1dc | 4217 | drm_crtc_send_vblank_event(&intel_crtc->base, work->event); |
d6bbafa1 CW |
4218 | |
4219 | drm_crtc_vblank_put(&intel_crtc->base); | |
4220 | ||
5a21b665 | 4221 | wake_up_all(&dev_priv->pending_flip_queue); |
5a21b665 DV |
4222 | trace_i915_flip_complete(intel_crtc->plane, |
4223 | work->pending_flip_obj); | |
05c41f92 AR |
4224 | |
4225 | queue_work(dev_priv->wq, &work->unpin_work); | |
d6bbafa1 CW |
4226 | } |
4227 | ||
5008e874 | 4228 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 4229 | { |
0f91128d | 4230 | struct drm_device *dev = crtc->dev; |
fac5e23e | 4231 | struct drm_i915_private *dev_priv = to_i915(dev); |
5008e874 | 4232 | long ret; |
e6c3a2a6 | 4233 | |
2c10d571 | 4234 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
4235 | |
4236 | ret = wait_event_interruptible_timeout( | |
4237 | dev_priv->pending_flip_queue, | |
4238 | !intel_crtc_has_pending_flip(crtc), | |
4239 | 60*HZ); | |
4240 | ||
4241 | if (ret < 0) | |
4242 | return ret; | |
4243 | ||
5a21b665 DV |
4244 | if (ret == 0) { |
4245 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4246 | struct intel_flip_work *work; | |
4247 | ||
4248 | spin_lock_irq(&dev->event_lock); | |
4249 | work = intel_crtc->flip_work; | |
4250 | if (work && !is_mmio_work(work)) { | |
4251 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
4252 | page_flip_completed(intel_crtc); | |
4253 | } | |
4254 | spin_unlock_irq(&dev->event_lock); | |
4255 | } | |
5bb61643 | 4256 | |
5008e874 | 4257 | return 0; |
e6c3a2a6 CW |
4258 | } |
4259 | ||
b7076546 | 4260 | void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
060f02d8 VS |
4261 | { |
4262 | u32 temp; | |
4263 | ||
4264 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
4265 | ||
4266 | mutex_lock(&dev_priv->sb_lock); | |
4267 | ||
4268 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4269 | temp |= SBI_SSCCTL_DISABLE; | |
4270 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
4271 | ||
4272 | mutex_unlock(&dev_priv->sb_lock); | |
4273 | } | |
4274 | ||
e615efe4 | 4275 | /* Program iCLKIP clock to the desired frequency */ |
0dcdc382 | 4276 | static void lpt_program_iclkip(struct intel_crtc *crtc) |
e615efe4 | 4277 | { |
0dcdc382 ACO |
4278 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
4279 | int clock = crtc->config->base.adjusted_mode.crtc_clock; | |
e615efe4 ED |
4280 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
4281 | u32 temp; | |
4282 | ||
060f02d8 | 4283 | lpt_disable_iclkip(dev_priv); |
e615efe4 | 4284 | |
64b46a06 VS |
4285 | /* The iCLK virtual clock root frequency is in MHz, |
4286 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
4287 | * divisors, it is necessary to divide one by another, so we | |
4288 | * convert the virtual clock precision to KHz here for higher | |
4289 | * precision. | |
4290 | */ | |
4291 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
e615efe4 ED |
4292 | u32 iclk_virtual_root_freq = 172800 * 1000; |
4293 | u32 iclk_pi_range = 64; | |
64b46a06 | 4294 | u32 desired_divisor; |
e615efe4 | 4295 | |
64b46a06 VS |
4296 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
4297 | clock << auxdiv); | |
4298 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
4299 | phaseinc = desired_divisor % iclk_pi_range; | |
e615efe4 | 4300 | |
64b46a06 VS |
4301 | /* |
4302 | * Near 20MHz is a corner case which is | |
4303 | * out of range for the 7-bit divisor | |
4304 | */ | |
4305 | if (divsel <= 0x7f) | |
4306 | break; | |
e615efe4 ED |
4307 | } |
4308 | ||
4309 | /* This should not happen with any sane values */ | |
4310 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
4311 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
4312 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
4313 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
4314 | ||
4315 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 4316 | clock, |
e615efe4 ED |
4317 | auxdiv, |
4318 | divsel, | |
4319 | phasedir, | |
4320 | phaseinc); | |
4321 | ||
060f02d8 VS |
4322 | mutex_lock(&dev_priv->sb_lock); |
4323 | ||
e615efe4 | 4324 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 4325 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4326 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4327 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4328 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4329 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4330 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4331 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4332 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4333 | |
4334 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4335 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4336 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4337 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4338 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4339 | |
4340 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4341 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4342 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4343 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 4344 | |
060f02d8 VS |
4345 | mutex_unlock(&dev_priv->sb_lock); |
4346 | ||
e615efe4 ED |
4347 | /* Wait for initialization time */ |
4348 | udelay(24); | |
4349 | ||
4350 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
4351 | } | |
4352 | ||
8802e5b6 VS |
4353 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
4354 | { | |
4355 | u32 divsel, phaseinc, auxdiv; | |
4356 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
4357 | u32 iclk_pi_range = 64; | |
4358 | u32 desired_divisor; | |
4359 | u32 temp; | |
4360 | ||
4361 | if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) | |
4362 | return 0; | |
4363 | ||
4364 | mutex_lock(&dev_priv->sb_lock); | |
4365 | ||
4366 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
4367 | if (temp & SBI_SSCCTL_DISABLE) { | |
4368 | mutex_unlock(&dev_priv->sb_lock); | |
4369 | return 0; | |
4370 | } | |
4371 | ||
4372 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
4373 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
4374 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
4375 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
4376 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
4377 | ||
4378 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
4379 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
4380 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
4381 | ||
4382 | mutex_unlock(&dev_priv->sb_lock); | |
4383 | ||
4384 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
4385 | ||
4386 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
4387 | desired_divisor << auxdiv); | |
4388 | } | |
4389 | ||
275f01b2 DV |
4390 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4391 | enum pipe pch_transcoder) | |
4392 | { | |
4393 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4394 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 4395 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4396 | |
4397 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4398 | I915_READ(HTOTAL(cpu_transcoder))); | |
4399 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4400 | I915_READ(HBLANK(cpu_transcoder))); | |
4401 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4402 | I915_READ(HSYNC(cpu_transcoder))); | |
4403 | ||
4404 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4405 | I915_READ(VTOTAL(cpu_transcoder))); | |
4406 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4407 | I915_READ(VBLANK(cpu_transcoder))); | |
4408 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4409 | I915_READ(VSYNC(cpu_transcoder))); | |
4410 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4411 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4412 | } | |
4413 | ||
003632d9 | 4414 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 | 4415 | { |
fac5e23e | 4416 | struct drm_i915_private *dev_priv = to_i915(dev); |
1fbc0d78 DV |
4417 | uint32_t temp; |
4418 | ||
4419 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4420 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4421 | return; |
4422 | ||
4423 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4424 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4425 | ||
003632d9 ACO |
4426 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4427 | if (enable) | |
4428 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4429 | ||
4430 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4431 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4432 | POSTING_READ(SOUTH_CHICKEN1); | |
4433 | } | |
4434 | ||
4435 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4436 | { | |
4437 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4438 | |
4439 | switch (intel_crtc->pipe) { | |
4440 | case PIPE_A: | |
4441 | break; | |
4442 | case PIPE_B: | |
6e3c9717 | 4443 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4444 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4445 | else |
003632d9 | 4446 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4447 | |
4448 | break; | |
4449 | case PIPE_C: | |
003632d9 | 4450 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4451 | |
4452 | break; | |
4453 | default: | |
4454 | BUG(); | |
4455 | } | |
4456 | } | |
4457 | ||
c48b5305 VS |
4458 | /* Return which DP Port should be selected for Transcoder DP control */ |
4459 | static enum port | |
4cbe4b2b | 4460 | intel_trans_dp_port_sel(struct intel_crtc *crtc) |
c48b5305 | 4461 | { |
4cbe4b2b | 4462 | struct drm_device *dev = crtc->base.dev; |
c48b5305 VS |
4463 | struct intel_encoder *encoder; |
4464 | ||
4cbe4b2b | 4465 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { |
cca0502b | 4466 | if (encoder->type == INTEL_OUTPUT_DP || |
c48b5305 VS |
4467 | encoder->type == INTEL_OUTPUT_EDP) |
4468 | return enc_to_dig_port(&encoder->base)->port; | |
4469 | } | |
4470 | ||
4471 | return -1; | |
4472 | } | |
4473 | ||
f67a559d JB |
4474 | /* |
4475 | * Enable PCH resources required for PCH ports: | |
4476 | * - PCH PLLs | |
4477 | * - FDI training & RX/TX | |
4478 | * - update transcoder timings | |
4479 | * - DP transcoding bits | |
4480 | * - transcoder | |
4481 | */ | |
2ce42273 | 4482 | static void ironlake_pch_enable(const struct intel_crtc_state *crtc_state) |
0e23b99d | 4483 | { |
2ce42273 | 4484 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
4cbe4b2b | 4485 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4486 | struct drm_i915_private *dev_priv = to_i915(dev); |
4cbe4b2b | 4487 | int pipe = crtc->pipe; |
f0f59a00 | 4488 | u32 temp; |
2c07245f | 4489 | |
ab9412ba | 4490 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4491 | |
fd6b8f43 | 4492 | if (IS_IVYBRIDGE(dev_priv)) |
4cbe4b2b | 4493 | ivybridge_update_fdi_bc_bifurcation(crtc); |
1fbc0d78 | 4494 | |
cd986abb DV |
4495 | /* Write the TU size bits before fdi link training, so that error |
4496 | * detection works. */ | |
4497 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4498 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4499 | ||
c98e9dcf | 4500 | /* For PCH output, training FDI link */ |
dc4a1094 | 4501 | dev_priv->display.fdi_link_train(crtc, crtc_state); |
2c07245f | 4502 | |
3ad8a208 DV |
4503 | /* We need to program the right clock selection before writing the pixel |
4504 | * mutliplier into the DPLL. */ | |
6e266956 | 4505 | if (HAS_PCH_CPT(dev_priv)) { |
ee7b9f93 | 4506 | u32 sel; |
4b645f14 | 4507 | |
c98e9dcf | 4508 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4509 | temp |= TRANS_DPLL_ENABLE(pipe); |
4510 | sel = TRANS_DPLLB_SEL(pipe); | |
2ce42273 | 4511 | if (crtc_state->shared_dpll == |
8106ddbd | 4512 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) |
ee7b9f93 JB |
4513 | temp |= sel; |
4514 | else | |
4515 | temp &= ~sel; | |
c98e9dcf | 4516 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4517 | } |
5eddb70b | 4518 | |
3ad8a208 DV |
4519 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4520 | * transcoder, and we actually should do this to not upset any PCH | |
4521 | * transcoder that already use the clock when we share it. | |
4522 | * | |
4523 | * Note that enable_shared_dpll tries to do the right thing, but | |
4524 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4525 | * the right LVDS enable sequence. */ | |
4cbe4b2b | 4526 | intel_enable_shared_dpll(crtc); |
3ad8a208 | 4527 | |
d9b6cb56 JB |
4528 | /* set transcoder timing, panel must allow it */ |
4529 | assert_panel_unlocked(dev_priv, pipe); | |
4cbe4b2b | 4530 | ironlake_pch_transcoder_set_timings(crtc, pipe); |
8db9d77b | 4531 | |
303b81e0 | 4532 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4533 | |
c98e9dcf | 4534 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e266956 | 4535 | if (HAS_PCH_CPT(dev_priv) && |
2ce42273 | 4536 | intel_crtc_has_dp_encoder(crtc_state)) { |
9c4edaee | 4537 | const struct drm_display_mode *adjusted_mode = |
2ce42273 | 4538 | &crtc_state->base.adjusted_mode; |
dfd07d72 | 4539 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4540 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4541 | temp = I915_READ(reg); |
4542 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4543 | TRANS_DP_SYNC_MASK | |
4544 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4545 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4546 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4547 | |
9c4edaee | 4548 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4549 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4550 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4551 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4552 | |
4553 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4554 | case PORT_B: |
5eddb70b | 4555 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4556 | break; |
c48b5305 | 4557 | case PORT_C: |
5eddb70b | 4558 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4559 | break; |
c48b5305 | 4560 | case PORT_D: |
5eddb70b | 4561 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4562 | break; |
4563 | default: | |
e95d41e1 | 4564 | BUG(); |
32f9d658 | 4565 | } |
2c07245f | 4566 | |
5eddb70b | 4567 | I915_WRITE(reg, temp); |
6be4a607 | 4568 | } |
b52eb4dc | 4569 | |
b8a4f404 | 4570 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4571 | } |
4572 | ||
2ce42273 | 4573 | static void lpt_pch_enable(const struct intel_crtc_state *crtc_state) |
1507e5bd | 4574 | { |
2ce42273 | 4575 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
0dcdc382 | 4576 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2ce42273 | 4577 | enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; |
1507e5bd | 4578 | |
ab9412ba | 4579 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4580 | |
8c52b5e8 | 4581 | lpt_program_iclkip(crtc); |
1507e5bd | 4582 | |
0540e488 | 4583 | /* Set transcoder timing. */ |
0dcdc382 | 4584 | ironlake_pch_transcoder_set_timings(crtc, PIPE_A); |
1507e5bd | 4585 | |
937bb610 | 4586 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4587 | } |
4588 | ||
a1520318 | 4589 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 | 4590 | { |
fac5e23e | 4591 | struct drm_i915_private *dev_priv = to_i915(dev); |
f0f59a00 | 4592 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4593 | u32 temp; |
4594 | ||
4595 | temp = I915_READ(dslreg); | |
4596 | udelay(500); | |
4597 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4598 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4599 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4600 | } |
4601 | } | |
4602 | ||
86adf9d7 ML |
4603 | static int |
4604 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4605 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4606 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4607 | { |
86adf9d7 ML |
4608 | struct intel_crtc_scaler_state *scaler_state = |
4609 | &crtc_state->scaler_state; | |
4610 | struct intel_crtc *intel_crtc = | |
4611 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4612 | int need_scaling; |
6156a456 | 4613 | |
bd2ef25d | 4614 | need_scaling = drm_rotation_90_or_270(rotation) ? |
6156a456 CK |
4615 | (src_h != dst_w || src_w != dst_h): |
4616 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4617 | |
4618 | /* | |
4619 | * if plane is being disabled or scaler is no more required or force detach | |
4620 | * - free scaler binded to this plane/crtc | |
4621 | * - in order to do this, update crtc->scaler_usage | |
4622 | * | |
4623 | * Here scaler state in crtc_state is set free so that | |
4624 | * scaler can be assigned to other user. Actual register | |
4625 | * update to free the scaler is done in plane/panel-fit programming. | |
4626 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4627 | */ | |
86adf9d7 | 4628 | if (force_detach || !need_scaling) { |
a1b2278e | 4629 | if (*scaler_id >= 0) { |
86adf9d7 | 4630 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4631 | scaler_state->scalers[*scaler_id].in_use = 0; |
4632 | ||
86adf9d7 ML |
4633 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4634 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4635 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4636 | scaler_state->scaler_users); |
4637 | *scaler_id = -1; | |
4638 | } | |
4639 | return 0; | |
4640 | } | |
4641 | ||
4642 | /* range checks */ | |
4643 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4644 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4645 | ||
4646 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4647 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4648 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4649 | "size is out of scaler range\n", |
86adf9d7 | 4650 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4651 | return -EINVAL; |
4652 | } | |
4653 | ||
86adf9d7 ML |
4654 | /* mark this plane as a scaler user in crtc_state */ |
4655 | scaler_state->scaler_users |= (1 << scaler_user); | |
4656 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4657 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4658 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4659 | scaler_state->scaler_users); | |
4660 | ||
4661 | return 0; | |
4662 | } | |
4663 | ||
4664 | /** | |
4665 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4666 | * | |
4667 | * @state: crtc's scaler state | |
86adf9d7 ML |
4668 | * |
4669 | * Return | |
4670 | * 0 - scaler_usage updated successfully | |
4671 | * error - requested scaling cannot be supported or other error condition | |
4672 | */ | |
e435d6e5 | 4673 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 | 4674 | { |
7c5f93b0 | 4675 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 | 4676 | |
e435d6e5 | 4677 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
31ad61e4 | 4678 | &state->scaler_state.scaler_id, DRM_ROTATE_0, |
86adf9d7 | 4679 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4680 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4681 | } |
4682 | ||
4683 | /** | |
4684 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4685 | * | |
4686 | * @state: crtc's scaler state | |
86adf9d7 ML |
4687 | * @plane_state: atomic plane state to update |
4688 | * | |
4689 | * Return | |
4690 | * 0 - scaler_usage updated successfully | |
4691 | * error - requested scaling cannot be supported or other error condition | |
4692 | */ | |
da20eabd ML |
4693 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4694 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4695 | { |
4696 | ||
da20eabd ML |
4697 | struct intel_plane *intel_plane = |
4698 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4699 | struct drm_framebuffer *fb = plane_state->base.fb; |
4700 | int ret; | |
4701 | ||
936e71e3 | 4702 | bool force_detach = !fb || !plane_state->base.visible; |
86adf9d7 | 4703 | |
86adf9d7 ML |
4704 | ret = skl_update_scaler(crtc_state, force_detach, |
4705 | drm_plane_index(&intel_plane->base), | |
4706 | &plane_state->scaler_id, | |
4707 | plane_state->base.rotation, | |
936e71e3 VS |
4708 | drm_rect_width(&plane_state->base.src) >> 16, |
4709 | drm_rect_height(&plane_state->base.src) >> 16, | |
4710 | drm_rect_width(&plane_state->base.dst), | |
4711 | drm_rect_height(&plane_state->base.dst)); | |
86adf9d7 ML |
4712 | |
4713 | if (ret || plane_state->scaler_id < 0) | |
4714 | return ret; | |
4715 | ||
a1b2278e | 4716 | /* check colorkey */ |
818ed961 | 4717 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
72660ce0 VS |
4718 | DRM_DEBUG_KMS("[PLANE:%d:%s] scaling with color key not allowed", |
4719 | intel_plane->base.base.id, | |
4720 | intel_plane->base.name); | |
a1b2278e CK |
4721 | return -EINVAL; |
4722 | } | |
4723 | ||
4724 | /* Check src format */ | |
438b74a5 | 4725 | switch (fb->format->format) { |
86adf9d7 ML |
4726 | case DRM_FORMAT_RGB565: |
4727 | case DRM_FORMAT_XBGR8888: | |
4728 | case DRM_FORMAT_XRGB8888: | |
4729 | case DRM_FORMAT_ABGR8888: | |
4730 | case DRM_FORMAT_ARGB8888: | |
4731 | case DRM_FORMAT_XRGB2101010: | |
4732 | case DRM_FORMAT_XBGR2101010: | |
4733 | case DRM_FORMAT_YUYV: | |
4734 | case DRM_FORMAT_YVYU: | |
4735 | case DRM_FORMAT_UYVY: | |
4736 | case DRM_FORMAT_VYUY: | |
4737 | break; | |
4738 | default: | |
72660ce0 VS |
4739 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n", |
4740 | intel_plane->base.base.id, intel_plane->base.name, | |
438b74a5 | 4741 | fb->base.id, fb->format->format); |
86adf9d7 | 4742 | return -EINVAL; |
a1b2278e CK |
4743 | } |
4744 | ||
a1b2278e CK |
4745 | return 0; |
4746 | } | |
4747 | ||
e435d6e5 ML |
4748 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4749 | { | |
4750 | int i; | |
4751 | ||
4752 | for (i = 0; i < crtc->num_scalers; i++) | |
4753 | skl_detach_scaler(crtc, i); | |
4754 | } | |
4755 | ||
4756 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4757 | { |
4758 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4759 | struct drm_i915_private *dev_priv = to_i915(dev); |
bd2e244f | 4760 | int pipe = crtc->pipe; |
a1b2278e CK |
4761 | struct intel_crtc_scaler_state *scaler_state = |
4762 | &crtc->config->scaler_state; | |
4763 | ||
6e3c9717 | 4764 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4765 | int id; |
4766 | ||
c3f8ad57 | 4767 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) |
a1b2278e | 4768 | return; |
a1b2278e CK |
4769 | |
4770 | id = scaler_state->scaler_id; | |
4771 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4772 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4773 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4774 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
bd2e244f JB |
4775 | } |
4776 | } | |
4777 | ||
b074cec8 JB |
4778 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4779 | { | |
4780 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4781 | struct drm_i915_private *dev_priv = to_i915(dev); |
b074cec8 JB |
4782 | int pipe = crtc->pipe; |
4783 | ||
6e3c9717 | 4784 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4785 | /* Force use of hard-coded filter coefficients |
4786 | * as some pre-programmed values are broken, | |
4787 | * e.g. x201. | |
4788 | */ | |
fd6b8f43 | 4789 | if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) |
b074cec8 JB |
4790 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | |
4791 | PF_PIPE_SEL_IVB(pipe)); | |
4792 | else | |
4793 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4794 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4795 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4796 | } |
4797 | } | |
4798 | ||
20bc8673 | 4799 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4800 | { |
cea165c3 | 4801 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 4802 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4803 | |
6e3c9717 | 4804 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4805 | return; |
4806 | ||
307e4498 ML |
4807 | /* |
4808 | * We can only enable IPS after we enable a plane and wait for a vblank | |
4809 | * This function is called from post_plane_update, which is run after | |
4810 | * a vblank wait. | |
4811 | */ | |
cea165c3 | 4812 | |
d77e4531 | 4813 | assert_plane_enabled(dev_priv, crtc->plane); |
8652744b | 4814 | if (IS_BROADWELL(dev_priv)) { |
2a114cc1 BW |
4815 | mutex_lock(&dev_priv->rps.hw_lock); |
4816 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4817 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4818 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4819 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4820 | * mailbox." Moreover, the mailbox may return a bogus state, |
4821 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4822 | */ |
4823 | } else { | |
4824 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4825 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4826 | * is essentially intel_wait_for_vblank. If we don't have this | |
4827 | * and don't wait for vblanks until the end of crtc_enable, then | |
4828 | * the HW state readout code will complain that the expected | |
4829 | * IPS_CTL value is not the one we read. */ | |
2ec9ba3c CW |
4830 | if (intel_wait_for_register(dev_priv, |
4831 | IPS_CTL, IPS_ENABLE, IPS_ENABLE, | |
4832 | 50)) | |
2a114cc1 BW |
4833 | DRM_ERROR("Timed out waiting for IPS enable\n"); |
4834 | } | |
d77e4531 PZ |
4835 | } |
4836 | ||
20bc8673 | 4837 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4838 | { |
4839 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 4840 | struct drm_i915_private *dev_priv = to_i915(dev); |
d77e4531 | 4841 | |
6e3c9717 | 4842 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4843 | return; |
4844 | ||
4845 | assert_plane_enabled(dev_priv, crtc->plane); | |
8652744b | 4846 | if (IS_BROADWELL(dev_priv)) { |
2a114cc1 BW |
4847 | mutex_lock(&dev_priv->rps.hw_lock); |
4848 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4849 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 | 4850 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
b85c1ecf CW |
4851 | if (intel_wait_for_register(dev_priv, |
4852 | IPS_CTL, IPS_ENABLE, 0, | |
4853 | 42)) | |
23d0b130 | 4854 | DRM_ERROR("Timed out waiting for IPS disable\n"); |
e59150dc | 4855 | } else { |
2a114cc1 | 4856 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4857 | POSTING_READ(IPS_CTL); |
4858 | } | |
d77e4531 PZ |
4859 | |
4860 | /* We need to wait for a vblank before we can disable the plane. */ | |
0f0f74bc | 4861 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
d77e4531 PZ |
4862 | } |
4863 | ||
7cac945f | 4864 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4865 | { |
7cac945f | 4866 | if (intel_crtc->overlay) { |
d3eedb1a | 4867 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 4868 | struct drm_i915_private *dev_priv = to_i915(dev); |
d3eedb1a VS |
4869 | |
4870 | mutex_lock(&dev->struct_mutex); | |
4871 | dev_priv->mm.interruptible = false; | |
4872 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4873 | dev_priv->mm.interruptible = true; | |
4874 | mutex_unlock(&dev->struct_mutex); | |
4875 | } | |
4876 | ||
4877 | /* Let userspace switch the overlay on again. In most cases userspace | |
4878 | * has to recompute where to put it anyway. | |
4879 | */ | |
4880 | } | |
4881 | ||
87d4300a ML |
4882 | /** |
4883 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4884 | * @crtc: the CRTC whose primary plane was just enabled | |
4885 | * | |
4886 | * Performs potentially sleeping operations that must be done after the primary | |
4887 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4888 | * called due to an explicit primary plane update, or due to an implicit | |
4889 | * re-enable that is caused when a sprite plane is updated to no longer | |
4890 | * completely hide the primary plane. | |
4891 | */ | |
4892 | static void | |
4893 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4894 | { |
4895 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4896 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4897 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4898 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4899 | |
87d4300a ML |
4900 | /* |
4901 | * FIXME IPS should be fine as long as one plane is | |
4902 | * enabled, but in practice it seems to have problems | |
4903 | * when going from primary only to sprite only and vice | |
4904 | * versa. | |
4905 | */ | |
a5c4d7bc VS |
4906 | hsw_enable_ips(intel_crtc); |
4907 | ||
f99d7069 | 4908 | /* |
87d4300a ML |
4909 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4910 | * So don't enable underrun reporting before at least some planes | |
4911 | * are enabled. | |
4912 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4913 | * but leave the pipe running. | |
f99d7069 | 4914 | */ |
5db94019 | 4915 | if (IS_GEN2(dev_priv)) |
87d4300a ML |
4916 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4917 | ||
aca7b684 VS |
4918 | /* Underruns don't always raise interrupts, so check manually. */ |
4919 | intel_check_cpu_fifo_underruns(dev_priv); | |
4920 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4921 | } |
4922 | ||
2622a081 | 4923 | /* FIXME move all this to pre_plane_update() with proper state tracking */ |
87d4300a ML |
4924 | static void |
4925 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4926 | { |
4927 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4928 | struct drm_i915_private *dev_priv = to_i915(dev); |
a5c4d7bc VS |
4929 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4930 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4931 | |
87d4300a ML |
4932 | /* |
4933 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4934 | * So diasble underrun reporting before all the planes get disabled. | |
4935 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4936 | * but leave the pipe running. | |
4937 | */ | |
5db94019 | 4938 | if (IS_GEN2(dev_priv)) |
87d4300a | 4939 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
a5c4d7bc | 4940 | |
2622a081 VS |
4941 | /* |
4942 | * FIXME IPS should be fine as long as one plane is | |
4943 | * enabled, but in practice it seems to have problems | |
4944 | * when going from primary only to sprite only and vice | |
4945 | * versa. | |
4946 | */ | |
4947 | hsw_disable_ips(intel_crtc); | |
4948 | } | |
4949 | ||
4950 | /* FIXME get rid of this and use pre_plane_update */ | |
4951 | static void | |
4952 | intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) | |
4953 | { | |
4954 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 4955 | struct drm_i915_private *dev_priv = to_i915(dev); |
2622a081 VS |
4956 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4957 | int pipe = intel_crtc->pipe; | |
4958 | ||
4959 | intel_pre_disable_primary(crtc); | |
4960 | ||
87d4300a ML |
4961 | /* |
4962 | * Vblank time updates from the shadow to live plane control register | |
4963 | * are blocked if the memory self-refresh mode is active at that | |
4964 | * moment. So to make sure the plane gets truly disabled, disable | |
4965 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4966 | * will be checked/applied by the HW only at the next frame start | |
4967 | * event which is after the vblank start event, so we need to have a | |
4968 | * wait-for-vblank between disabling the plane and the pipe. | |
4969 | */ | |
11a85d6a VS |
4970 | if (HAS_GMCH_DISPLAY(dev_priv) && |
4971 | intel_set_memory_cxsr(dev_priv, false)) | |
0f0f74bc | 4972 | intel_wait_for_vblank(dev_priv, pipe); |
87d4300a ML |
4973 | } |
4974 | ||
5a21b665 DV |
4975 | static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) |
4976 | { | |
4977 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); | |
4978 | struct drm_atomic_state *old_state = old_crtc_state->base.state; | |
4979 | struct intel_crtc_state *pipe_config = | |
4980 | to_intel_crtc_state(crtc->base.state); | |
5a21b665 DV |
4981 | struct drm_plane *primary = crtc->base.primary; |
4982 | struct drm_plane_state *old_pri_state = | |
4983 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4984 | ||
5748b6a1 | 4985 | intel_frontbuffer_flip(to_i915(crtc->base.dev), pipe_config->fb_bits); |
5a21b665 | 4986 | |
5a21b665 | 4987 | if (pipe_config->update_wm_post && pipe_config->base.active) |
432081bc | 4988 | intel_update_watermarks(crtc); |
5a21b665 DV |
4989 | |
4990 | if (old_pri_state) { | |
4991 | struct intel_plane_state *primary_state = | |
4992 | to_intel_plane_state(primary->state); | |
4993 | struct intel_plane_state *old_primary_state = | |
4994 | to_intel_plane_state(old_pri_state); | |
4995 | ||
4996 | intel_fbc_post_update(crtc); | |
4997 | ||
936e71e3 | 4998 | if (primary_state->base.visible && |
5a21b665 | 4999 | (needs_modeset(&pipe_config->base) || |
936e71e3 | 5000 | !old_primary_state->base.visible)) |
5a21b665 DV |
5001 | intel_post_enable_primary(&crtc->base); |
5002 | } | |
5003 | } | |
5004 | ||
5c74cd73 | 5005 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 5006 | { |
5c74cd73 | 5007 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 5008 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 5009 | struct drm_i915_private *dev_priv = to_i915(dev); |
ab1d3a0e ML |
5010 | struct intel_crtc_state *pipe_config = |
5011 | to_intel_crtc_state(crtc->base.state); | |
5c74cd73 ML |
5012 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
5013 | struct drm_plane *primary = crtc->base.primary; | |
5014 | struct drm_plane_state *old_pri_state = | |
5015 | drm_atomic_get_existing_plane_state(old_state, primary); | |
5016 | bool modeset = needs_modeset(&pipe_config->base); | |
ccf010fb ML |
5017 | struct intel_atomic_state *old_intel_state = |
5018 | to_intel_atomic_state(old_state); | |
ac21b225 | 5019 | |
5c74cd73 ML |
5020 | if (old_pri_state) { |
5021 | struct intel_plane_state *primary_state = | |
5022 | to_intel_plane_state(primary->state); | |
5023 | struct intel_plane_state *old_primary_state = | |
5024 | to_intel_plane_state(old_pri_state); | |
5025 | ||
faf68d92 | 5026 | intel_fbc_pre_update(crtc, pipe_config, primary_state); |
31ae71fc | 5027 | |
936e71e3 VS |
5028 | if (old_primary_state->base.visible && |
5029 | (modeset || !primary_state->base.visible)) | |
5c74cd73 ML |
5030 | intel_pre_disable_primary(&crtc->base); |
5031 | } | |
852eb00d | 5032 | |
5eeb798b VS |
5033 | /* |
5034 | * Vblank time updates from the shadow to live plane control register | |
5035 | * are blocked if the memory self-refresh mode is active at that | |
5036 | * moment. So to make sure the plane gets truly disabled, disable | |
5037 | * first the self-refresh mode. The self-refresh enable bit in turn | |
5038 | * will be checked/applied by the HW only at the next frame start | |
5039 | * event which is after the vblank start event, so we need to have a | |
5040 | * wait-for-vblank between disabling the plane and the pipe. | |
5041 | */ | |
5042 | if (HAS_GMCH_DISPLAY(dev_priv) && old_crtc_state->base.active && | |
5043 | pipe_config->disable_cxsr && intel_set_memory_cxsr(dev_priv, false)) | |
5044 | intel_wait_for_vblank(dev_priv, crtc->pipe); | |
92826fcd | 5045 | |
ed4a6a7c MR |
5046 | /* |
5047 | * IVB workaround: must disable low power watermarks for at least | |
5048 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
5049 | * when scaling is disabled. | |
5050 | * | |
5051 | * WaCxSRDisabledForSpriteScaling:ivb | |
5052 | */ | |
ddd2b792 | 5053 | if (pipe_config->disable_lp_wm && ilk_disable_lp_wm(dev)) |
0f0f74bc | 5054 | intel_wait_for_vblank(dev_priv, crtc->pipe); |
ed4a6a7c MR |
5055 | |
5056 | /* | |
5057 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
5058 | * watermark programming here. | |
5059 | */ | |
5060 | if (needs_modeset(&pipe_config->base)) | |
5061 | return; | |
5062 | ||
5063 | /* | |
5064 | * For platforms that support atomic watermarks, program the | |
5065 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
5066 | * will be the intermediate values that are safe for both pre- and | |
5067 | * post- vblank; when vblank happens, the 'active' values will be set | |
5068 | * to the final 'target' values and we'll do this again to get the | |
5069 | * optimal watermarks. For gen9+ platforms, the values we program here | |
5070 | * will be the final target values which will get automatically latched | |
5071 | * at vblank time; no further programming will be necessary. | |
5072 | * | |
5073 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
5074 | * we'll continue to update watermarks the old way, if flags tell | |
5075 | * us to. | |
5076 | */ | |
5077 | if (dev_priv->display.initial_watermarks != NULL) | |
ccf010fb ML |
5078 | dev_priv->display.initial_watermarks(old_intel_state, |
5079 | pipe_config); | |
caed361d | 5080 | else if (pipe_config->update_wm_pre) |
432081bc | 5081 | intel_update_watermarks(crtc); |
ac21b225 ML |
5082 | } |
5083 | ||
d032ffa0 | 5084 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
5085 | { |
5086 | struct drm_device *dev = crtc->dev; | |
5087 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 5088 | struct drm_plane *p; |
87d4300a ML |
5089 | int pipe = intel_crtc->pipe; |
5090 | ||
7cac945f | 5091 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 5092 | |
d032ffa0 ML |
5093 | drm_for_each_plane_mask(p, dev, plane_mask) |
5094 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 5095 | |
f99d7069 DV |
5096 | /* |
5097 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
5098 | * to compute the mask of flip planes precisely. For the time being | |
5099 | * consider this a flip to a NULL plane. | |
5100 | */ | |
5748b6a1 | 5101 | intel_frontbuffer_flip(to_i915(dev), INTEL_FRONTBUFFER_ALL_MASK(pipe)); |
a5c4d7bc VS |
5102 | } |
5103 | ||
fb1c98b1 | 5104 | static void intel_encoders_pre_pll_enable(struct drm_crtc *crtc, |
fd6bbda9 | 5105 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5106 | struct drm_atomic_state *old_state) |
5107 | { | |
5108 | struct drm_connector_state *old_conn_state; | |
5109 | struct drm_connector *conn; | |
5110 | int i; | |
5111 | ||
5112 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5113 | struct drm_connector_state *conn_state = conn->state; | |
5114 | struct intel_encoder *encoder = | |
5115 | to_intel_encoder(conn_state->best_encoder); | |
5116 | ||
5117 | if (conn_state->crtc != crtc) | |
5118 | continue; | |
5119 | ||
5120 | if (encoder->pre_pll_enable) | |
fd6bbda9 | 5121 | encoder->pre_pll_enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5122 | } |
5123 | } | |
5124 | ||
5125 | static void intel_encoders_pre_enable(struct drm_crtc *crtc, | |
fd6bbda9 | 5126 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5127 | struct drm_atomic_state *old_state) |
5128 | { | |
5129 | struct drm_connector_state *old_conn_state; | |
5130 | struct drm_connector *conn; | |
5131 | int i; | |
5132 | ||
5133 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5134 | struct drm_connector_state *conn_state = conn->state; | |
5135 | struct intel_encoder *encoder = | |
5136 | to_intel_encoder(conn_state->best_encoder); | |
5137 | ||
5138 | if (conn_state->crtc != crtc) | |
5139 | continue; | |
5140 | ||
5141 | if (encoder->pre_enable) | |
fd6bbda9 | 5142 | encoder->pre_enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5143 | } |
5144 | } | |
5145 | ||
5146 | static void intel_encoders_enable(struct drm_crtc *crtc, | |
fd6bbda9 | 5147 | struct intel_crtc_state *crtc_state, |
fb1c98b1 ML |
5148 | struct drm_atomic_state *old_state) |
5149 | { | |
5150 | struct drm_connector_state *old_conn_state; | |
5151 | struct drm_connector *conn; | |
5152 | int i; | |
5153 | ||
5154 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5155 | struct drm_connector_state *conn_state = conn->state; | |
5156 | struct intel_encoder *encoder = | |
5157 | to_intel_encoder(conn_state->best_encoder); | |
5158 | ||
5159 | if (conn_state->crtc != crtc) | |
5160 | continue; | |
5161 | ||
fd6bbda9 | 5162 | encoder->enable(encoder, crtc_state, conn_state); |
fb1c98b1 ML |
5163 | intel_opregion_notify_encoder(encoder, true); |
5164 | } | |
5165 | } | |
5166 | ||
5167 | static void intel_encoders_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5168 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5169 | struct drm_atomic_state *old_state) |
5170 | { | |
5171 | struct drm_connector_state *old_conn_state; | |
5172 | struct drm_connector *conn; | |
5173 | int i; | |
5174 | ||
5175 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5176 | struct intel_encoder *encoder = | |
5177 | to_intel_encoder(old_conn_state->best_encoder); | |
5178 | ||
5179 | if (old_conn_state->crtc != crtc) | |
5180 | continue; | |
5181 | ||
5182 | intel_opregion_notify_encoder(encoder, false); | |
fd6bbda9 | 5183 | encoder->disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5184 | } |
5185 | } | |
5186 | ||
5187 | static void intel_encoders_post_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5188 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5189 | struct drm_atomic_state *old_state) |
5190 | { | |
5191 | struct drm_connector_state *old_conn_state; | |
5192 | struct drm_connector *conn; | |
5193 | int i; | |
5194 | ||
5195 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5196 | struct intel_encoder *encoder = | |
5197 | to_intel_encoder(old_conn_state->best_encoder); | |
5198 | ||
5199 | if (old_conn_state->crtc != crtc) | |
5200 | continue; | |
5201 | ||
5202 | if (encoder->post_disable) | |
fd6bbda9 | 5203 | encoder->post_disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5204 | } |
5205 | } | |
5206 | ||
5207 | static void intel_encoders_post_pll_disable(struct drm_crtc *crtc, | |
fd6bbda9 | 5208 | struct intel_crtc_state *old_crtc_state, |
fb1c98b1 ML |
5209 | struct drm_atomic_state *old_state) |
5210 | { | |
5211 | struct drm_connector_state *old_conn_state; | |
5212 | struct drm_connector *conn; | |
5213 | int i; | |
5214 | ||
5215 | for_each_connector_in_state(old_state, conn, old_conn_state, i) { | |
5216 | struct intel_encoder *encoder = | |
5217 | to_intel_encoder(old_conn_state->best_encoder); | |
5218 | ||
5219 | if (old_conn_state->crtc != crtc) | |
5220 | continue; | |
5221 | ||
5222 | if (encoder->post_pll_disable) | |
fd6bbda9 | 5223 | encoder->post_pll_disable(encoder, old_crtc_state, old_conn_state); |
fb1c98b1 ML |
5224 | } |
5225 | } | |
5226 | ||
4a806558 ML |
5227 | static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config, |
5228 | struct drm_atomic_state *old_state) | |
f67a559d | 5229 | { |
4a806558 | 5230 | struct drm_crtc *crtc = pipe_config->base.crtc; |
f67a559d | 5231 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5232 | struct drm_i915_private *dev_priv = to_i915(dev); |
f67a559d JB |
5233 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5234 | int pipe = intel_crtc->pipe; | |
ccf010fb ML |
5235 | struct intel_atomic_state *old_intel_state = |
5236 | to_intel_atomic_state(old_state); | |
f67a559d | 5237 | |
53d9f4e9 | 5238 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
5239 | return; |
5240 | ||
b2c0593a VS |
5241 | /* |
5242 | * Sometimes spurious CPU pipe underruns happen during FDI | |
5243 | * training, at least with VGA+HDMI cloning. Suppress them. | |
5244 | * | |
5245 | * On ILK we get an occasional spurious CPU pipe underruns | |
5246 | * between eDP port A enable and vdd enable. Also PCH port | |
5247 | * enable seems to result in the occasional CPU pipe underrun. | |
5248 | * | |
5249 | * Spurious PCH underruns also occur during PCH enabling. | |
5250 | */ | |
5251 | if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv)) | |
5252 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
81b088ca VS |
5253 | if (intel_crtc->config->has_pch_encoder) |
5254 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
5255 | ||
6e3c9717 | 5256 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
5257 | intel_prepare_shared_dpll(intel_crtc); |
5258 | ||
37a5650b | 5259 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5260 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
5261 | |
5262 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 5263 | intel_set_pipe_src_size(intel_crtc); |
29407aab | 5264 | |
6e3c9717 | 5265 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 5266 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5267 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
5268 | } |
5269 | ||
5270 | ironlake_set_pipeconf(crtc); | |
5271 | ||
f67a559d | 5272 | intel_crtc->active = true; |
8664281b | 5273 | |
fd6bbda9 | 5274 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
f67a559d | 5275 | |
6e3c9717 | 5276 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
5277 | /* Note: FDI PLL enabling _must_ be done before we enable the |
5278 | * cpu pipes, hence this is separate from all the other fdi/pch | |
5279 | * enabling. */ | |
88cefb6c | 5280 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
5281 | } else { |
5282 | assert_fdi_tx_disabled(dev_priv, pipe); | |
5283 | assert_fdi_rx_disabled(dev_priv, pipe); | |
5284 | } | |
f67a559d | 5285 | |
b074cec8 | 5286 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 5287 | |
9c54c0dd JB |
5288 | /* |
5289 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5290 | * clocks enabled | |
5291 | */ | |
b95c5321 | 5292 | intel_color_load_luts(&pipe_config->base); |
9c54c0dd | 5293 | |
1d5bf5d9 | 5294 | if (dev_priv->display.initial_watermarks != NULL) |
ccf010fb | 5295 | dev_priv->display.initial_watermarks(old_intel_state, intel_crtc->config); |
e1fdc473 | 5296 | intel_enable_pipe(intel_crtc); |
f67a559d | 5297 | |
6e3c9717 | 5298 | if (intel_crtc->config->has_pch_encoder) |
2ce42273 | 5299 | ironlake_pch_enable(pipe_config); |
c98e9dcf | 5300 | |
f9b61ff6 DV |
5301 | assert_vblank_disabled(crtc); |
5302 | drm_crtc_vblank_on(crtc); | |
5303 | ||
fd6bbda9 | 5304 | intel_encoders_enable(crtc, pipe_config, old_state); |
61b77ddd | 5305 | |
6e266956 | 5306 | if (HAS_PCH_CPT(dev_priv)) |
a1520318 | 5307 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
5308 | |
5309 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
5310 | if (intel_crtc->config->has_pch_encoder) | |
0f0f74bc | 5311 | intel_wait_for_vblank(dev_priv, pipe); |
b2c0593a | 5312 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
37ca8d4c | 5313 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 JB |
5314 | } |
5315 | ||
42db64ef PZ |
5316 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
5317 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
5318 | { | |
50a0bc90 | 5319 | return HAS_IPS(to_i915(crtc->base.dev)) && crtc->pipe == PIPE_A; |
42db64ef PZ |
5320 | } |
5321 | ||
4a806558 ML |
5322 | static void haswell_crtc_enable(struct intel_crtc_state *pipe_config, |
5323 | struct drm_atomic_state *old_state) | |
4f771f10 | 5324 | { |
4a806558 | 5325 | struct drm_crtc *crtc = pipe_config->base.crtc; |
6315b5d3 | 5326 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
4f771f10 | 5327 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
99d736a2 | 5328 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4d1de975 | 5329 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ccf010fb ML |
5330 | struct intel_atomic_state *old_intel_state = |
5331 | to_intel_atomic_state(old_state); | |
4f771f10 | 5332 | |
53d9f4e9 | 5333 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
5334 | return; |
5335 | ||
81b088ca VS |
5336 | if (intel_crtc->config->has_pch_encoder) |
5337 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5338 | false); | |
5339 | ||
fd6bbda9 | 5340 | intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); |
95a7a2ae | 5341 | |
8106ddbd | 5342 | if (intel_crtc->config->shared_dpll) |
df8ad70c DV |
5343 | intel_enable_shared_dpll(intel_crtc); |
5344 | ||
37a5650b | 5345 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
fe3cd48d | 5346 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 | 5347 | |
d7edc4e5 | 5348 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5349 | intel_set_pipe_timings(intel_crtc); |
5350 | ||
bc58be60 | 5351 | intel_set_pipe_src_size(intel_crtc); |
229fca97 | 5352 | |
4d1de975 JN |
5353 | if (cpu_transcoder != TRANSCODER_EDP && |
5354 | !transcoder_is_dsi(cpu_transcoder)) { | |
5355 | I915_WRITE(PIPE_MULT(cpu_transcoder), | |
6e3c9717 | 5356 | intel_crtc->config->pixel_multiplier - 1); |
ebb69c95 CT |
5357 | } |
5358 | ||
6e3c9717 | 5359 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 5360 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 5361 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
5362 | } |
5363 | ||
d7edc4e5 | 5364 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 JN |
5365 | haswell_set_pipeconf(crtc); |
5366 | ||
391bf048 | 5367 | haswell_set_pipemisc(crtc); |
229fca97 | 5368 | |
b95c5321 | 5369 | intel_color_set_csc(&pipe_config->base); |
229fca97 | 5370 | |
4f771f10 | 5371 | intel_crtc->active = true; |
8664281b | 5372 | |
6b698516 DV |
5373 | if (intel_crtc->config->has_pch_encoder) |
5374 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5375 | else | |
5376 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5377 | ||
fd6bbda9 | 5378 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
4f771f10 | 5379 | |
d2d65408 | 5380 | if (intel_crtc->config->has_pch_encoder) |
dc4a1094 | 5381 | dev_priv->display.fdi_link_train(intel_crtc, pipe_config); |
4fe9467d | 5382 | |
d7edc4e5 | 5383 | if (!transcoder_is_dsi(cpu_transcoder)) |
3dc38eea | 5384 | intel_ddi_enable_pipe_clock(pipe_config); |
4f771f10 | 5385 | |
6315b5d3 | 5386 | if (INTEL_GEN(dev_priv) >= 9) |
e435d6e5 | 5387 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 5388 | else |
1c132b44 | 5389 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
5390 | |
5391 | /* | |
5392 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5393 | * clocks enabled | |
5394 | */ | |
b95c5321 | 5395 | intel_color_load_luts(&pipe_config->base); |
4f771f10 | 5396 | |
3dc38eea | 5397 | intel_ddi_set_pipe_settings(pipe_config); |
d7edc4e5 | 5398 | if (!transcoder_is_dsi(cpu_transcoder)) |
3dc38eea | 5399 | intel_ddi_enable_transcoder_func(pipe_config); |
4f771f10 | 5400 | |
1d5bf5d9 | 5401 | if (dev_priv->display.initial_watermarks != NULL) |
3125d39f | 5402 | dev_priv->display.initial_watermarks(old_intel_state, pipe_config); |
4d1de975 JN |
5403 | |
5404 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ | |
d7edc4e5 | 5405 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5406 | intel_enable_pipe(intel_crtc); |
42db64ef | 5407 | |
6e3c9717 | 5408 | if (intel_crtc->config->has_pch_encoder) |
2ce42273 | 5409 | lpt_pch_enable(pipe_config); |
4f771f10 | 5410 | |
0037071d | 5411 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST)) |
3dc38eea | 5412 | intel_ddi_set_vc_payload_alloc(pipe_config, true); |
0e32b39c | 5413 | |
f9b61ff6 DV |
5414 | assert_vblank_disabled(crtc); |
5415 | drm_crtc_vblank_on(crtc); | |
5416 | ||
fd6bbda9 | 5417 | intel_encoders_enable(crtc, pipe_config, old_state); |
4f771f10 | 5418 | |
6b698516 | 5419 | if (intel_crtc->config->has_pch_encoder) { |
0f0f74bc VS |
5420 | intel_wait_for_vblank(dev_priv, pipe); |
5421 | intel_wait_for_vblank(dev_priv, pipe); | |
6b698516 | 5422 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
d2d65408 VS |
5423 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5424 | true); | |
6b698516 | 5425 | } |
d2d65408 | 5426 | |
e4916946 PZ |
5427 | /* If we change the relative order between pipe/planes enabling, we need |
5428 | * to change the workaround. */ | |
99d736a2 | 5429 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
772c2a51 | 5430 | if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) { |
0f0f74bc VS |
5431 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); |
5432 | intel_wait_for_vblank(dev_priv, hsw_workaround_pipe); | |
99d736a2 | 5433 | } |
4f771f10 PZ |
5434 | } |
5435 | ||
bfd16b2a | 5436 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
5437 | { |
5438 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5439 | struct drm_i915_private *dev_priv = to_i915(dev); |
3f8dce3a DV |
5440 | int pipe = crtc->pipe; |
5441 | ||
5442 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5443 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5444 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5445 | I915_WRITE(PF_CTL(pipe), 0); |
5446 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5447 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5448 | } | |
5449 | } | |
5450 | ||
4a806558 ML |
5451 | static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5452 | struct drm_atomic_state *old_state) | |
6be4a607 | 5453 | { |
4a806558 | 5454 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
6be4a607 | 5455 | struct drm_device *dev = crtc->dev; |
fac5e23e | 5456 | struct drm_i915_private *dev_priv = to_i915(dev); |
6be4a607 JB |
5457 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5458 | int pipe = intel_crtc->pipe; | |
b52eb4dc | 5459 | |
b2c0593a VS |
5460 | /* |
5461 | * Sometimes spurious CPU pipe underruns happen when the | |
5462 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
5463 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
5464 | */ | |
5465 | if (intel_crtc->config->has_pch_encoder) { | |
5466 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
37ca8d4c | 5467 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
b2c0593a | 5468 | } |
37ca8d4c | 5469 | |
fd6bbda9 | 5470 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
ea9d758d | 5471 | |
f9b61ff6 DV |
5472 | drm_crtc_vblank_off(crtc); |
5473 | assert_vblank_disabled(crtc); | |
5474 | ||
575f7ab7 | 5475 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5476 | |
bfd16b2a | 5477 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5478 | |
b2c0593a | 5479 | if (intel_crtc->config->has_pch_encoder) |
5a74f70a VS |
5480 | ironlake_fdi_disable(crtc); |
5481 | ||
fd6bbda9 | 5482 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
2c07245f | 5483 | |
6e3c9717 | 5484 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5485 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5486 | |
6e266956 | 5487 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 VS |
5488 | i915_reg_t reg; |
5489 | u32 temp; | |
5490 | ||
d925c59a DV |
5491 | /* disable TRANS_DP_CTL */ |
5492 | reg = TRANS_DP_CTL(pipe); | |
5493 | temp = I915_READ(reg); | |
5494 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5495 | TRANS_DP_PORT_SEL_MASK); | |
5496 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5497 | I915_WRITE(reg, temp); | |
5498 | ||
5499 | /* disable DPLL_SEL */ | |
5500 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5501 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5502 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5503 | } |
e3421a18 | 5504 | |
d925c59a DV |
5505 | ironlake_fdi_pll_disable(intel_crtc); |
5506 | } | |
81b088ca | 5507 | |
b2c0593a | 5508 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
81b088ca | 5509 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 | 5510 | } |
1b3c7a47 | 5511 | |
4a806558 ML |
5512 | static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5513 | struct drm_atomic_state *old_state) | |
ee7b9f93 | 5514 | { |
4a806558 | 5515 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
6315b5d3 | 5516 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee7b9f93 | 5517 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 5518 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5519 | |
d2d65408 VS |
5520 | if (intel_crtc->config->has_pch_encoder) |
5521 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5522 | false); | |
5523 | ||
fd6bbda9 | 5524 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
4f771f10 | 5525 | |
f9b61ff6 DV |
5526 | drm_crtc_vblank_off(crtc); |
5527 | assert_vblank_disabled(crtc); | |
5528 | ||
4d1de975 | 5529 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ |
d7edc4e5 | 5530 | if (!transcoder_is_dsi(cpu_transcoder)) |
4d1de975 | 5531 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5532 | |
0037071d | 5533 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DP_MST)) |
3dc38eea | 5534 | intel_ddi_set_vc_payload_alloc(intel_crtc->config, false); |
a4bf214f | 5535 | |
d7edc4e5 | 5536 | if (!transcoder_is_dsi(cpu_transcoder)) |
7d4aefd0 | 5537 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5538 | |
6315b5d3 | 5539 | if (INTEL_GEN(dev_priv) >= 9) |
e435d6e5 | 5540 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5541 | else |
bfd16b2a | 5542 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5543 | |
d7edc4e5 | 5544 | if (!transcoder_is_dsi(cpu_transcoder)) |
3dc38eea | 5545 | intel_ddi_disable_pipe_clock(intel_crtc->config); |
4f771f10 | 5546 | |
fd6bbda9 | 5547 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
81b088ca | 5548 | |
b7076546 | 5549 | if (old_crtc_state->has_pch_encoder) |
81b088ca VS |
5550 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5551 | true); | |
4f771f10 PZ |
5552 | } |
5553 | ||
2dd24552 JB |
5554 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5555 | { | |
5556 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 5557 | struct drm_i915_private *dev_priv = to_i915(dev); |
6e3c9717 | 5558 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5559 | |
681a8504 | 5560 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5561 | return; |
5562 | ||
2dd24552 | 5563 | /* |
c0b03411 DV |
5564 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5565 | * according to register description and PRM. | |
2dd24552 | 5566 | */ |
c0b03411 DV |
5567 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5568 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5569 | |
b074cec8 JB |
5570 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5571 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5572 | |
5573 | /* Border color in case we don't scale up to the full screen. Black by | |
5574 | * default, change to something else for debugging. */ | |
5575 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5576 | } |
5577 | ||
79f255a0 | 5578 | enum intel_display_power_domain intel_port_to_power_domain(enum port port) |
d05410f9 DA |
5579 | { |
5580 | switch (port) { | |
5581 | case PORT_A: | |
6331a704 | 5582 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5583 | case PORT_B: |
6331a704 | 5584 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5585 | case PORT_C: |
6331a704 | 5586 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5587 | case PORT_D: |
6331a704 | 5588 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5589 | case PORT_E: |
6331a704 | 5590 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5591 | default: |
b9fec167 | 5592 | MISSING_CASE(port); |
d05410f9 DA |
5593 | return POWER_DOMAIN_PORT_OTHER; |
5594 | } | |
5595 | } | |
5596 | ||
d8fc70b7 ACO |
5597 | static u64 get_crtc_power_domains(struct drm_crtc *crtc, |
5598 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5599 | { |
319be8ae | 5600 | struct drm_device *dev = crtc->dev; |
37255d8d | 5601 | struct drm_i915_private *dev_priv = to_i915(dev); |
74bff5f9 | 5602 | struct drm_encoder *encoder; |
319be8ae ID |
5603 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5604 | enum pipe pipe = intel_crtc->pipe; | |
d8fc70b7 | 5605 | u64 mask; |
74bff5f9 | 5606 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 5607 | |
74bff5f9 | 5608 | if (!crtc_state->base.active) |
292b990e ML |
5609 | return 0; |
5610 | ||
77d22dca ID |
5611 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5612 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
5613 | if (crtc_state->pch_pfit.enabled || |
5614 | crtc_state->pch_pfit.force_thru) | |
d8fc70b7 | 5615 | mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
77d22dca | 5616 | |
74bff5f9 ML |
5617 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
5618 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5619 | ||
79f255a0 | 5620 | mask |= BIT_ULL(intel_encoder->power_domain); |
74bff5f9 | 5621 | } |
319be8ae | 5622 | |
37255d8d ML |
5623 | if (HAS_DDI(dev_priv) && crtc_state->has_audio) |
5624 | mask |= BIT(POWER_DOMAIN_AUDIO); | |
5625 | ||
15e7ec29 | 5626 | if (crtc_state->shared_dpll) |
d8fc70b7 | 5627 | mask |= BIT_ULL(POWER_DOMAIN_PLLS); |
15e7ec29 | 5628 | |
77d22dca ID |
5629 | return mask; |
5630 | } | |
5631 | ||
d2d15016 | 5632 | static u64 |
74bff5f9 ML |
5633 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, |
5634 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5635 | { |
fac5e23e | 5636 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
292b990e ML |
5637 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5638 | enum intel_display_power_domain domain; | |
d8fc70b7 | 5639 | u64 domains, new_domains, old_domains; |
77d22dca | 5640 | |
292b990e | 5641 | old_domains = intel_crtc->enabled_power_domains; |
74bff5f9 ML |
5642 | intel_crtc->enabled_power_domains = new_domains = |
5643 | get_crtc_power_domains(crtc, crtc_state); | |
77d22dca | 5644 | |
5a21b665 | 5645 | domains = new_domains & ~old_domains; |
292b990e ML |
5646 | |
5647 | for_each_power_domain(domain, domains) | |
5648 | intel_display_power_get(dev_priv, domain); | |
5649 | ||
5a21b665 | 5650 | return old_domains & ~new_domains; |
292b990e ML |
5651 | } |
5652 | ||
5653 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
d8fc70b7 | 5654 | u64 domains) |
292b990e ML |
5655 | { |
5656 | enum intel_display_power_domain domain; | |
5657 | ||
5658 | for_each_power_domain(domain, domains) | |
5659 | intel_display_power_put(dev_priv, domain); | |
5660 | } | |
77d22dca | 5661 | |
7ff89ca2 VS |
5662 | static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config, |
5663 | struct drm_atomic_state *old_state) | |
adafdc6f | 5664 | { |
ff32c54e VS |
5665 | struct intel_atomic_state *old_intel_state = |
5666 | to_intel_atomic_state(old_state); | |
7ff89ca2 VS |
5667 | struct drm_crtc *crtc = pipe_config->base.crtc; |
5668 | struct drm_device *dev = crtc->dev; | |
5669 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5670 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5671 | int pipe = intel_crtc->pipe; | |
adafdc6f | 5672 | |
7ff89ca2 VS |
5673 | if (WARN_ON(intel_crtc->active)) |
5674 | return; | |
adafdc6f | 5675 | |
7ff89ca2 VS |
5676 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
5677 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
b2045352 | 5678 | |
7ff89ca2 VS |
5679 | intel_set_pipe_timings(intel_crtc); |
5680 | intel_set_pipe_src_size(intel_crtc); | |
b2045352 | 5681 | |
7ff89ca2 VS |
5682 | if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { |
5683 | struct drm_i915_private *dev_priv = to_i915(dev); | |
560a7ae4 | 5684 | |
7ff89ca2 VS |
5685 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); |
5686 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
560a7ae4 DL |
5687 | } |
5688 | ||
7ff89ca2 | 5689 | i9xx_set_pipeconf(intel_crtc); |
560a7ae4 | 5690 | |
7ff89ca2 | 5691 | intel_crtc->active = true; |
92891e45 | 5692 | |
7ff89ca2 | 5693 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5f199dfa | 5694 | |
7ff89ca2 | 5695 | intel_encoders_pre_pll_enable(crtc, pipe_config, old_state); |
5f199dfa | 5696 | |
7ff89ca2 VS |
5697 | if (IS_CHERRYVIEW(dev_priv)) { |
5698 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
5699 | chv_enable_pll(intel_crtc, intel_crtc->config); | |
5700 | } else { | |
5701 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
5702 | vlv_enable_pll(intel_crtc, intel_crtc->config); | |
5f199dfa VS |
5703 | } |
5704 | ||
7ff89ca2 | 5705 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
5f199dfa | 5706 | |
7ff89ca2 | 5707 | i9xx_pfit_enable(intel_crtc); |
89b3c3c7 | 5708 | |
7ff89ca2 | 5709 | intel_color_load_luts(&pipe_config->base); |
89b3c3c7 | 5710 | |
ff32c54e VS |
5711 | dev_priv->display.initial_watermarks(old_intel_state, |
5712 | pipe_config); | |
7ff89ca2 VS |
5713 | intel_enable_pipe(intel_crtc); |
5714 | ||
5715 | assert_vblank_disabled(crtc); | |
5716 | drm_crtc_vblank_on(crtc); | |
89b3c3c7 | 5717 | |
7ff89ca2 | 5718 | intel_encoders_enable(crtc, pipe_config, old_state); |
89b3c3c7 ACO |
5719 | } |
5720 | ||
7ff89ca2 | 5721 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
2b73001e | 5722 | { |
7ff89ca2 VS |
5723 | struct drm_device *dev = crtc->base.dev; |
5724 | struct drm_i915_private *dev_priv = to_i915(dev); | |
83d7c81f | 5725 | |
7ff89ca2 VS |
5726 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
5727 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
2b73001e VS |
5728 | } |
5729 | ||
7ff89ca2 VS |
5730 | static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config, |
5731 | struct drm_atomic_state *old_state) | |
2b73001e | 5732 | { |
7ff89ca2 VS |
5733 | struct drm_crtc *crtc = pipe_config->base.crtc; |
5734 | struct drm_device *dev = crtc->dev; | |
5735 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5736 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5737 | enum pipe pipe = intel_crtc->pipe; | |
2b73001e | 5738 | |
7ff89ca2 VS |
5739 | if (WARN_ON(intel_crtc->active)) |
5740 | return; | |
2b73001e | 5741 | |
7ff89ca2 | 5742 | i9xx_set_pll_dividers(intel_crtc); |
2b73001e | 5743 | |
7ff89ca2 VS |
5744 | if (intel_crtc_has_dp_encoder(intel_crtc->config)) |
5745 | intel_dp_set_m_n(intel_crtc, M1_N1); | |
83d7c81f | 5746 | |
7ff89ca2 VS |
5747 | intel_set_pipe_timings(intel_crtc); |
5748 | intel_set_pipe_src_size(intel_crtc); | |
2b73001e | 5749 | |
7ff89ca2 | 5750 | i9xx_set_pipeconf(intel_crtc); |
f8437dd1 | 5751 | |
7ff89ca2 | 5752 | intel_crtc->active = true; |
5f199dfa | 5753 | |
7ff89ca2 VS |
5754 | if (!IS_GEN2(dev_priv)) |
5755 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
5f199dfa | 5756 | |
7ff89ca2 | 5757 | intel_encoders_pre_enable(crtc, pipe_config, old_state); |
f8437dd1 | 5758 | |
7ff89ca2 | 5759 | i9xx_enable_pll(intel_crtc); |
f8437dd1 | 5760 | |
7ff89ca2 | 5761 | i9xx_pfit_enable(intel_crtc); |
f8437dd1 | 5762 | |
7ff89ca2 | 5763 | intel_color_load_luts(&pipe_config->base); |
f8437dd1 | 5764 | |
7ff89ca2 VS |
5765 | intel_update_watermarks(intel_crtc); |
5766 | intel_enable_pipe(intel_crtc); | |
f8437dd1 | 5767 | |
7ff89ca2 VS |
5768 | assert_vblank_disabled(crtc); |
5769 | drm_crtc_vblank_on(crtc); | |
f8437dd1 | 5770 | |
7ff89ca2 VS |
5771 | intel_encoders_enable(crtc, pipe_config, old_state); |
5772 | } | |
f8437dd1 | 5773 | |
7ff89ca2 VS |
5774 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
5775 | { | |
5776 | struct drm_device *dev = crtc->base.dev; | |
5777 | struct drm_i915_private *dev_priv = to_i915(dev); | |
f8437dd1 | 5778 | |
7ff89ca2 | 5779 | if (!crtc->config->gmch_pfit.control) |
f8437dd1 | 5780 | return; |
f8437dd1 | 5781 | |
7ff89ca2 VS |
5782 | assert_pipe_disabled(dev_priv, crtc->pipe); |
5783 | ||
5784 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", | |
5785 | I915_READ(PFIT_CONTROL)); | |
5786 | I915_WRITE(PFIT_CONTROL, 0); | |
f8437dd1 VK |
5787 | } |
5788 | ||
7ff89ca2 VS |
5789 | static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state, |
5790 | struct drm_atomic_state *old_state) | |
f8437dd1 | 5791 | { |
7ff89ca2 VS |
5792 | struct drm_crtc *crtc = old_crtc_state->base.crtc; |
5793 | struct drm_device *dev = crtc->dev; | |
5794 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5795 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5796 | int pipe = intel_crtc->pipe; | |
d66a2194 | 5797 | |
d66a2194 | 5798 | /* |
7ff89ca2 VS |
5799 | * On gen2 planes are double buffered but the pipe isn't, so we must |
5800 | * wait for planes to fully turn off before disabling the pipe. | |
d66a2194 | 5801 | */ |
7ff89ca2 VS |
5802 | if (IS_GEN2(dev_priv)) |
5803 | intel_wait_for_vblank(dev_priv, pipe); | |
d66a2194 | 5804 | |
7ff89ca2 | 5805 | intel_encoders_disable(crtc, old_crtc_state, old_state); |
d66a2194 | 5806 | |
7ff89ca2 VS |
5807 | drm_crtc_vblank_off(crtc); |
5808 | assert_vblank_disabled(crtc); | |
d66a2194 | 5809 | |
7ff89ca2 | 5810 | intel_disable_pipe(intel_crtc); |
d66a2194 | 5811 | |
7ff89ca2 | 5812 | i9xx_pfit_disable(intel_crtc); |
89b3c3c7 | 5813 | |
7ff89ca2 | 5814 | intel_encoders_post_disable(crtc, old_crtc_state, old_state); |
d66a2194 | 5815 | |
7ff89ca2 VS |
5816 | if (!intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_DSI)) { |
5817 | if (IS_CHERRYVIEW(dev_priv)) | |
5818 | chv_disable_pll(dev_priv, pipe); | |
5819 | else if (IS_VALLEYVIEW(dev_priv)) | |
5820 | vlv_disable_pll(dev_priv, pipe); | |
5821 | else | |
5822 | i9xx_disable_pll(intel_crtc); | |
5823 | } | |
c2e001ef | 5824 | |
7ff89ca2 | 5825 | intel_encoders_post_pll_disable(crtc, old_crtc_state, old_state); |
89b3c3c7 | 5826 | |
7ff89ca2 VS |
5827 | if (!IS_GEN2(dev_priv)) |
5828 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
ff32c54e VS |
5829 | |
5830 | if (!dev_priv->display.initial_watermarks) | |
5831 | intel_update_watermarks(intel_crtc); | |
f8437dd1 VK |
5832 | } |
5833 | ||
7ff89ca2 | 5834 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
f8437dd1 | 5835 | { |
7ff89ca2 VS |
5836 | struct intel_encoder *encoder; |
5837 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5838 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
5839 | enum intel_display_power_domain domain; | |
d2d15016 | 5840 | u64 domains; |
7ff89ca2 VS |
5841 | struct drm_atomic_state *state; |
5842 | struct intel_crtc_state *crtc_state; | |
5843 | int ret; | |
f8437dd1 | 5844 | |
7ff89ca2 VS |
5845 | if (!intel_crtc->active) |
5846 | return; | |
a8ca4934 | 5847 | |
7ff89ca2 VS |
5848 | if (crtc->primary->state->visible) { |
5849 | WARN_ON(intel_crtc->flip_work); | |
5d96d8af | 5850 | |
7ff89ca2 | 5851 | intel_pre_disable_primary_noatomic(crtc); |
709e05c3 | 5852 | |
7ff89ca2 VS |
5853 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); |
5854 | crtc->primary->state->visible = false; | |
5855 | } | |
5d96d8af | 5856 | |
7ff89ca2 VS |
5857 | state = drm_atomic_state_alloc(crtc->dev); |
5858 | if (!state) { | |
5859 | DRM_DEBUG_KMS("failed to disable [CRTC:%d:%s], out of memory", | |
5860 | crtc->base.id, crtc->name); | |
1c3f7700 | 5861 | return; |
7ff89ca2 | 5862 | } |
9f7eb31a | 5863 | |
7ff89ca2 | 5864 | state->acquire_ctx = crtc->dev->mode_config.acquire_ctx; |
ea61791e | 5865 | |
7ff89ca2 VS |
5866 | /* Everything's already locked, -EDEADLK can't happen. */ |
5867 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); | |
5868 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
9f7eb31a | 5869 | |
7ff89ca2 | 5870 | WARN_ON(IS_ERR(crtc_state) || ret); |
5d96d8af | 5871 | |
7ff89ca2 | 5872 | dev_priv->display.crtc_disable(crtc_state, state); |
4a806558 | 5873 | |
0853695c | 5874 | drm_atomic_state_put(state); |
842e0307 | 5875 | |
78108b7c VS |
5876 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n", |
5877 | crtc->base.id, crtc->name); | |
842e0307 ML |
5878 | |
5879 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0); | |
5880 | crtc->state->active = false; | |
37d9078b | 5881 | intel_crtc->active = false; |
842e0307 ML |
5882 | crtc->enabled = false; |
5883 | crtc->state->connector_mask = 0; | |
5884 | crtc->state->encoder_mask = 0; | |
5885 | ||
5886 | for_each_encoder_on_crtc(crtc->dev, crtc, encoder) | |
5887 | encoder->base.crtc = NULL; | |
5888 | ||
58f9c0bc | 5889 | intel_fbc_disable(intel_crtc); |
432081bc | 5890 | intel_update_watermarks(intel_crtc); |
1f7457b1 | 5891 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
5892 | |
5893 | domains = intel_crtc->enabled_power_domains; | |
5894 | for_each_power_domain(domain, domains) | |
5895 | intel_display_power_put(dev_priv, domain); | |
5896 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
5897 | |
5898 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
5899 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
5900 | } |
5901 | ||
6b72d486 ML |
5902 | /* |
5903 | * turn all crtc's off, but do not adjust state | |
5904 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
5905 | */ | |
70e0bd74 | 5906 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 5907 | { |
e2c8b870 | 5908 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 5909 | struct drm_atomic_state *state; |
e2c8b870 | 5910 | int ret; |
70e0bd74 | 5911 | |
e2c8b870 ML |
5912 | state = drm_atomic_helper_suspend(dev); |
5913 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
5914 | if (ret) |
5915 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
5916 | else |
5917 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 5918 | return ret; |
ee7b9f93 JB |
5919 | } |
5920 | ||
ea5b213a | 5921 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 5922 | { |
4ef69c7a | 5923 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 5924 | |
ea5b213a CW |
5925 | drm_encoder_cleanup(encoder); |
5926 | kfree(intel_encoder); | |
7e7d76c3 JB |
5927 | } |
5928 | ||
0a91ca29 DV |
5929 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
5930 | * internal consistency). */ | |
5a21b665 | 5931 | static void intel_connector_verify_state(struct intel_connector *connector) |
79e53945 | 5932 | { |
5a21b665 | 5933 | struct drm_crtc *crtc = connector->base.state->crtc; |
35dd3c64 ML |
5934 | |
5935 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
5936 | connector->base.base.id, | |
5937 | connector->base.name); | |
5938 | ||
0a91ca29 | 5939 | if (connector->get_hw_state(connector)) { |
e85376cb | 5940 | struct intel_encoder *encoder = connector->encoder; |
5a21b665 | 5941 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 5942 | |
35dd3c64 ML |
5943 | I915_STATE_WARN(!crtc, |
5944 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 5945 | |
35dd3c64 ML |
5946 | if (!crtc) |
5947 | return; | |
5948 | ||
5949 | I915_STATE_WARN(!crtc->state->active, | |
5950 | "connector is active, but attached crtc isn't\n"); | |
5951 | ||
e85376cb | 5952 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
5953 | return; |
5954 | ||
e85376cb | 5955 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
5956 | "atomic encoder doesn't match attached encoder\n"); |
5957 | ||
e85376cb | 5958 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
5959 | "attached encoder crtc differs from connector crtc\n"); |
5960 | } else { | |
4d688a2a ML |
5961 | I915_STATE_WARN(crtc && crtc->state->active, |
5962 | "attached crtc is active, but connector isn't\n"); | |
5a21b665 | 5963 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
35dd3c64 | 5964 | "best encoder set without crtc!\n"); |
0a91ca29 | 5965 | } |
79e53945 JB |
5966 | } |
5967 | ||
08d9bc92 ACO |
5968 | int intel_connector_init(struct intel_connector *connector) |
5969 | { | |
5350a031 | 5970 | drm_atomic_helper_connector_reset(&connector->base); |
08d9bc92 | 5971 | |
5350a031 | 5972 | if (!connector->base.state) |
08d9bc92 ACO |
5973 | return -ENOMEM; |
5974 | ||
08d9bc92 ACO |
5975 | return 0; |
5976 | } | |
5977 | ||
5978 | struct intel_connector *intel_connector_alloc(void) | |
5979 | { | |
5980 | struct intel_connector *connector; | |
5981 | ||
5982 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
5983 | if (!connector) | |
5984 | return NULL; | |
5985 | ||
5986 | if (intel_connector_init(connector) < 0) { | |
5987 | kfree(connector); | |
5988 | return NULL; | |
5989 | } | |
5990 | ||
5991 | return connector; | |
5992 | } | |
5993 | ||
f0947c37 DV |
5994 | /* Simple connector->get_hw_state implementation for encoders that support only |
5995 | * one connector and no cloning and hence the encoder state determines the state | |
5996 | * of the connector. */ | |
5997 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 5998 | { |
24929352 | 5999 | enum pipe pipe = 0; |
f0947c37 | 6000 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6001 | |
f0947c37 | 6002 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6003 | } |
6004 | ||
6d293983 | 6005 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6006 | { |
6d293983 ACO |
6007 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6008 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6009 | |
6010 | return 0; | |
6011 | } | |
6012 | ||
6d293983 | 6013 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6014 | struct intel_crtc_state *pipe_config) |
1857e1da | 6015 | { |
8652744b | 6016 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d293983 ACO |
6017 | struct drm_atomic_state *state = pipe_config->base.state; |
6018 | struct intel_crtc *other_crtc; | |
6019 | struct intel_crtc_state *other_crtc_state; | |
6020 | ||
1857e1da DV |
6021 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6022 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6023 | if (pipe_config->fdi_lanes > 4) { | |
6024 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6025 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6026 | return -EINVAL; |
1857e1da DV |
6027 | } |
6028 | ||
8652744b | 6029 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
1857e1da DV |
6030 | if (pipe_config->fdi_lanes > 2) { |
6031 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6032 | pipe_config->fdi_lanes); | |
6d293983 | 6033 | return -EINVAL; |
1857e1da | 6034 | } else { |
6d293983 | 6035 | return 0; |
1857e1da DV |
6036 | } |
6037 | } | |
6038 | ||
b7f05d4a | 6039 | if (INTEL_INFO(dev_priv)->num_pipes == 2) |
6d293983 | 6040 | return 0; |
1857e1da DV |
6041 | |
6042 | /* Ivybridge 3 pipe is really complicated */ | |
6043 | switch (pipe) { | |
6044 | case PIPE_A: | |
6d293983 | 6045 | return 0; |
1857e1da | 6046 | case PIPE_B: |
6d293983 ACO |
6047 | if (pipe_config->fdi_lanes <= 2) |
6048 | return 0; | |
6049 | ||
b91eb5cc | 6050 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_C); |
6d293983 ACO |
6051 | other_crtc_state = |
6052 | intel_atomic_get_crtc_state(state, other_crtc); | |
6053 | if (IS_ERR(other_crtc_state)) | |
6054 | return PTR_ERR(other_crtc_state); | |
6055 | ||
6056 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6057 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6058 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6059 | return -EINVAL; |
1857e1da | 6060 | } |
6d293983 | 6061 | return 0; |
1857e1da | 6062 | case PIPE_C: |
251cc67c VS |
6063 | if (pipe_config->fdi_lanes > 2) { |
6064 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6065 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6066 | return -EINVAL; |
251cc67c | 6067 | } |
6d293983 | 6068 | |
b91eb5cc | 6069 | other_crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_B); |
6d293983 ACO |
6070 | other_crtc_state = |
6071 | intel_atomic_get_crtc_state(state, other_crtc); | |
6072 | if (IS_ERR(other_crtc_state)) | |
6073 | return PTR_ERR(other_crtc_state); | |
6074 | ||
6075 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6076 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6077 | return -EINVAL; |
1857e1da | 6078 | } |
6d293983 | 6079 | return 0; |
1857e1da DV |
6080 | default: |
6081 | BUG(); | |
6082 | } | |
6083 | } | |
6084 | ||
e29c22c0 DV |
6085 | #define RETRY 1 |
6086 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6087 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6088 | { |
1857e1da | 6089 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6090 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6091 | int lane, link_bw, fdi_dotclock, ret; |
6092 | bool needs_recompute = false; | |
877d48d5 | 6093 | |
e29c22c0 | 6094 | retry: |
877d48d5 DV |
6095 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6096 | * each output octet as 10 bits. The actual frequency | |
6097 | * is stored as a divider into a 100MHz clock, and the | |
6098 | * mode pixel clock is stored in units of 1KHz. | |
6099 | * Hence the bw of each lane in terms of the mode signal | |
6100 | * is: | |
6101 | */ | |
21a727b3 | 6102 | link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); |
877d48d5 | 6103 | |
241bfc38 | 6104 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6105 | |
2bd89a07 | 6106 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6107 | pipe_config->pipe_bpp); |
6108 | ||
6109 | pipe_config->fdi_lanes = lane; | |
6110 | ||
2bd89a07 | 6111 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6112 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6113 | |
e3b247da | 6114 | ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
6d293983 | 6115 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
e29c22c0 | 6116 | pipe_config->pipe_bpp -= 2*3; |
7ff89ca2 VS |
6117 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", |
6118 | pipe_config->pipe_bpp); | |
6119 | needs_recompute = true; | |
6120 | pipe_config->bw_constrained = true; | |
257a7ffc | 6121 | |
7ff89ca2 | 6122 | goto retry; |
257a7ffc | 6123 | } |
79e53945 | 6124 | |
7ff89ca2 VS |
6125 | if (needs_recompute) |
6126 | return RETRY; | |
e70236a8 | 6127 | |
7ff89ca2 | 6128 | return ret; |
e70236a8 JB |
6129 | } |
6130 | ||
7ff89ca2 VS |
6131 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6132 | struct intel_crtc_state *pipe_config) | |
e70236a8 | 6133 | { |
7ff89ca2 VS |
6134 | if (pipe_config->pipe_bpp > 24) |
6135 | return false; | |
e70236a8 | 6136 | |
7ff89ca2 VS |
6137 | /* HSW can handle pixel rate up to cdclk? */ |
6138 | if (IS_HASWELL(dev_priv)) | |
6139 | return true; | |
1b1d2716 | 6140 | |
65cd2b3f | 6141 | /* |
7ff89ca2 VS |
6142 | * We compare against max which means we must take |
6143 | * the increased cdclk requirement into account when | |
6144 | * calculating the new cdclk. | |
6145 | * | |
6146 | * Should measure whether using a lower cdclk w/o IPS | |
e70236a8 | 6147 | */ |
7ff89ca2 VS |
6148 | return pipe_config->pixel_rate <= |
6149 | dev_priv->max_cdclk_freq * 95 / 100; | |
e70236a8 | 6150 | } |
79e53945 | 6151 | |
7ff89ca2 VS |
6152 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
6153 | struct intel_crtc_state *pipe_config) | |
6154 | { | |
6155 | struct drm_device *dev = crtc->base.dev; | |
6156 | struct drm_i915_private *dev_priv = to_i915(dev); | |
34edce2f | 6157 | |
7ff89ca2 VS |
6158 | pipe_config->ips_enabled = i915.enable_ips && |
6159 | hsw_crtc_supports_ips(crtc) && | |
6160 | pipe_config_supports_ips(dev_priv, pipe_config); | |
34edce2f VS |
6161 | } |
6162 | ||
7ff89ca2 | 6163 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
34edce2f | 6164 | { |
7ff89ca2 | 6165 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
34edce2f | 6166 | |
7ff89ca2 VS |
6167 | /* GDG double wide on either pipe, otherwise pipe A only */ |
6168 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6169 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
34edce2f VS |
6170 | } |
6171 | ||
ceb99320 VS |
6172 | static uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config) |
6173 | { | |
6174 | uint32_t pixel_rate; | |
6175 | ||
6176 | pixel_rate = pipe_config->base.adjusted_mode.crtc_clock; | |
6177 | ||
6178 | /* | |
6179 | * We only use IF-ID interlacing. If we ever use | |
6180 | * PF-ID we'll need to adjust the pixel_rate here. | |
6181 | */ | |
6182 | ||
6183 | if (pipe_config->pch_pfit.enabled) { | |
6184 | uint64_t pipe_w, pipe_h, pfit_w, pfit_h; | |
6185 | uint32_t pfit_size = pipe_config->pch_pfit.size; | |
6186 | ||
6187 | pipe_w = pipe_config->pipe_src_w; | |
6188 | pipe_h = pipe_config->pipe_src_h; | |
6189 | ||
6190 | pfit_w = (pfit_size >> 16) & 0xFFFF; | |
6191 | pfit_h = pfit_size & 0xFFFF; | |
6192 | if (pipe_w < pfit_w) | |
6193 | pipe_w = pfit_w; | |
6194 | if (pipe_h < pfit_h) | |
6195 | pipe_h = pfit_h; | |
6196 | ||
6197 | if (WARN_ON(!pfit_w || !pfit_h)) | |
6198 | return pixel_rate; | |
6199 | ||
6200 | pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, | |
6201 | pfit_w * pfit_h); | |
6202 | } | |
6203 | ||
6204 | return pixel_rate; | |
6205 | } | |
6206 | ||
7ff89ca2 | 6207 | static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state) |
34edce2f | 6208 | { |
7ff89ca2 | 6209 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); |
34edce2f | 6210 | |
7ff89ca2 VS |
6211 | if (HAS_GMCH_DISPLAY(dev_priv)) |
6212 | /* FIXME calculate proper pipe pixel rate for GMCH pfit */ | |
6213 | crtc_state->pixel_rate = | |
6214 | crtc_state->base.adjusted_mode.crtc_clock; | |
6215 | else | |
6216 | crtc_state->pixel_rate = | |
6217 | ilk_pipe_pixel_rate(crtc_state); | |
6218 | } | |
34edce2f | 6219 | |
7ff89ca2 VS |
6220 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
6221 | struct intel_crtc_state *pipe_config) | |
6222 | { | |
6223 | struct drm_device *dev = crtc->base.dev; | |
6224 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6225 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; | |
6226 | int clock_limit = dev_priv->max_dotclk_freq; | |
34edce2f | 6227 | |
7ff89ca2 VS |
6228 | if (INTEL_GEN(dev_priv) < 4) { |
6229 | clock_limit = dev_priv->max_cdclk_freq * 9 / 10; | |
34edce2f | 6230 | |
7ff89ca2 VS |
6231 | /* |
6232 | * Enable double wide mode when the dot clock | |
6233 | * is > 90% of the (display) core speed. | |
6234 | */ | |
6235 | if (intel_crtc_supports_double_wide(crtc) && | |
6236 | adjusted_mode->crtc_clock > clock_limit) { | |
6237 | clock_limit = dev_priv->max_dotclk_freq; | |
6238 | pipe_config->double_wide = true; | |
6239 | } | |
34edce2f VS |
6240 | } |
6241 | ||
7ff89ca2 VS |
6242 | if (adjusted_mode->crtc_clock > clock_limit) { |
6243 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6244 | adjusted_mode->crtc_clock, clock_limit, | |
6245 | yesno(pipe_config->double_wide)); | |
6246 | return -EINVAL; | |
6247 | } | |
34edce2f | 6248 | |
7ff89ca2 VS |
6249 | /* |
6250 | * Pipe horizontal size must be even in: | |
6251 | * - DVO ganged mode | |
6252 | * - LVDS dual channel mode | |
6253 | * - Double wide pipe | |
6254 | */ | |
6255 | if ((intel_crtc_has_type(pipe_config, INTEL_OUTPUT_LVDS) && | |
6256 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) | |
6257 | pipe_config->pipe_src_w &= ~1; | |
34edce2f | 6258 | |
7ff89ca2 VS |
6259 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6260 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
6261 | */ | |
6262 | if ((INTEL_GEN(dev_priv) > 4 || IS_G4X(dev_priv)) && | |
6263 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) | |
6264 | return -EINVAL; | |
34edce2f | 6265 | |
7ff89ca2 | 6266 | intel_crtc_compute_pixel_rate(pipe_config); |
34edce2f | 6267 | |
7ff89ca2 VS |
6268 | if (HAS_IPS(dev_priv)) |
6269 | hsw_compute_ips_config(crtc, pipe_config); | |
34edce2f | 6270 | |
7ff89ca2 VS |
6271 | if (pipe_config->has_pch_encoder) |
6272 | return ironlake_fdi_compute_config(crtc, pipe_config); | |
34edce2f | 6273 | |
7ff89ca2 | 6274 | return 0; |
34edce2f VS |
6275 | } |
6276 | ||
2c07245f | 6277 | static void |
a65851af | 6278 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 6279 | { |
a65851af VS |
6280 | while (*num > DATA_LINK_M_N_MASK || |
6281 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
6282 | *num >>= 1; |
6283 | *den >>= 1; | |
6284 | } | |
6285 | } | |
6286 | ||
a65851af VS |
6287 | static void compute_m_n(unsigned int m, unsigned int n, |
6288 | uint32_t *ret_m, uint32_t *ret_n) | |
6289 | { | |
6290 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
6291 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
6292 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
6293 | } | |
6294 | ||
e69d0bc1 DV |
6295 | void |
6296 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
6297 | int pixel_clock, int link_clock, | |
6298 | struct intel_link_m_n *m_n) | |
2c07245f | 6299 | { |
e69d0bc1 | 6300 | m_n->tu = 64; |
a65851af VS |
6301 | |
6302 | compute_m_n(bits_per_pixel * pixel_clock, | |
6303 | link_clock * nlanes * 8, | |
6304 | &m_n->gmch_m, &m_n->gmch_n); | |
6305 | ||
6306 | compute_m_n(pixel_clock, link_clock, | |
6307 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
6308 | } |
6309 | ||
a7615030 CW |
6310 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
6311 | { | |
d330a953 JN |
6312 | if (i915.panel_use_ssc >= 0) |
6313 | return i915.panel_use_ssc != 0; | |
41aa3448 | 6314 | return dev_priv->vbt.lvds_use_ssc |
435793df | 6315 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
6316 | } |
6317 | ||
7429e9d4 | 6318 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 6319 | { |
7df00d7a | 6320 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 6321 | } |
f47709a9 | 6322 | |
7429e9d4 DV |
6323 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
6324 | { | |
6325 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
6326 | } |
6327 | ||
f47709a9 | 6328 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 6329 | struct intel_crtc_state *crtc_state, |
9e2c8475 | 6330 | struct dpll *reduced_clock) |
a7516a05 | 6331 | { |
9b1e14f4 | 6332 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
a7516a05 JB |
6333 | u32 fp, fp2 = 0; |
6334 | ||
9b1e14f4 | 6335 | if (IS_PINEVIEW(dev_priv)) { |
190f68c5 | 6336 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6337 | if (reduced_clock) |
7429e9d4 | 6338 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 6339 | } else { |
190f68c5 | 6340 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 6341 | if (reduced_clock) |
7429e9d4 | 6342 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
6343 | } |
6344 | ||
190f68c5 | 6345 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 6346 | |
f47709a9 | 6347 | crtc->lowfreq_avail = false; |
2d84d2b3 | 6348 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 6349 | reduced_clock) { |
190f68c5 | 6350 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 6351 | crtc->lowfreq_avail = true; |
a7516a05 | 6352 | } else { |
190f68c5 | 6353 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
6354 | } |
6355 | } | |
6356 | ||
5e69f97f CML |
6357 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
6358 | pipe) | |
89b667f8 JB |
6359 | { |
6360 | u32 reg_val; | |
6361 | ||
6362 | /* | |
6363 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
6364 | * and set it to a reasonable value instead. | |
6365 | */ | |
ab3c759a | 6366 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
6367 | reg_val &= 0xffffff00; |
6368 | reg_val |= 0x00000030; | |
ab3c759a | 6369 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6370 | |
ab3c759a | 6371 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6372 | reg_val &= 0x8cffffff; |
6373 | reg_val = 0x8c000000; | |
ab3c759a | 6374 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 6375 | |
ab3c759a | 6376 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 6377 | reg_val &= 0xffffff00; |
ab3c759a | 6378 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 6379 | |
ab3c759a | 6380 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
6381 | reg_val &= 0x00ffffff; |
6382 | reg_val |= 0xb0000000; | |
ab3c759a | 6383 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
6384 | } |
6385 | ||
b551842d DV |
6386 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
6387 | struct intel_link_m_n *m_n) | |
6388 | { | |
6389 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6390 | struct drm_i915_private *dev_priv = to_i915(dev); |
b551842d DV |
6391 | int pipe = crtc->pipe; |
6392 | ||
e3b95f1e DV |
6393 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6394 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
6395 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
6396 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
6397 | } |
6398 | ||
6399 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
6400 | struct intel_link_m_n *m_n, |
6401 | struct intel_link_m_n *m2_n2) | |
b551842d | 6402 | { |
6315b5d3 | 6403 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
b551842d | 6404 | int pipe = crtc->pipe; |
6e3c9717 | 6405 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d | 6406 | |
6315b5d3 | 6407 | if (INTEL_GEN(dev_priv) >= 5) { |
b551842d DV |
6408 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6409 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
6410 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
6411 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
6412 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
6413 | * for gen < 8) and if DRRS is supported (to make sure the | |
6414 | * registers are not unnecessarily accessed). | |
6415 | */ | |
920a14b2 TU |
6416 | if (m2_n2 && (IS_CHERRYVIEW(dev_priv) || |
6417 | INTEL_GEN(dev_priv) < 8) && crtc->config->has_drrs) { | |
f769cd24 VK |
6418 | I915_WRITE(PIPE_DATA_M2(transcoder), |
6419 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
6420 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
6421 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
6422 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
6423 | } | |
b551842d | 6424 | } else { |
e3b95f1e DV |
6425 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
6426 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
6427 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
6428 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
6429 | } |
6430 | } | |
6431 | ||
fe3cd48d | 6432 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 6433 | { |
fe3cd48d R |
6434 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
6435 | ||
6436 | if (m_n == M1_N1) { | |
6437 | dp_m_n = &crtc->config->dp_m_n; | |
6438 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
6439 | } else if (m_n == M2_N2) { | |
6440 | ||
6441 | /* | |
6442 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
6443 | * needs to be programmed into M1_N1. | |
6444 | */ | |
6445 | dp_m_n = &crtc->config->dp_m2_n2; | |
6446 | } else { | |
6447 | DRM_ERROR("Unsupported divider value\n"); | |
6448 | return; | |
6449 | } | |
6450 | ||
6e3c9717 ACO |
6451 | if (crtc->config->has_pch_encoder) |
6452 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 6453 | else |
fe3cd48d | 6454 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
6455 | } |
6456 | ||
251ac862 DV |
6457 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
6458 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 | 6459 | { |
03ed5cbf | 6460 | pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | |
cd2d34d9 | 6461 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
6462 | if (crtc->pipe != PIPE_A) |
6463 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
bdd4b6a6 | 6464 | |
cd2d34d9 | 6465 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 6466 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
6467 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | |
6468 | DPLL_EXT_BUFFER_ENABLE_VLV; | |
6469 | ||
03ed5cbf VS |
6470 | pipe_config->dpll_hw_state.dpll_md = |
6471 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
6472 | } | |
bdd4b6a6 | 6473 | |
03ed5cbf VS |
6474 | static void chv_compute_dpll(struct intel_crtc *crtc, |
6475 | struct intel_crtc_state *pipe_config) | |
6476 | { | |
6477 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | | |
cd2d34d9 | 6478 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
6479 | if (crtc->pipe != PIPE_A) |
6480 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
6481 | ||
cd2d34d9 | 6482 | /* DPLL not used with DSI, but still need the rest set up */ |
d7edc4e5 | 6483 | if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) |
cd2d34d9 VS |
6484 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; |
6485 | ||
03ed5cbf VS |
6486 | pipe_config->dpll_hw_state.dpll_md = |
6487 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
bdd4b6a6 DV |
6488 | } |
6489 | ||
d288f65f | 6490 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6491 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 6492 | { |
f47709a9 | 6493 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6494 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 6495 | enum pipe pipe = crtc->pipe; |
bdd4b6a6 | 6496 | u32 mdiv; |
a0c4da24 | 6497 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 6498 | u32 coreclk, reg_val; |
a0c4da24 | 6499 | |
cd2d34d9 VS |
6500 | /* Enable Refclk */ |
6501 | I915_WRITE(DPLL(pipe), | |
6502 | pipe_config->dpll_hw_state.dpll & | |
6503 | ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); | |
6504 | ||
6505 | /* No need to actually set up the DPLL with DSI */ | |
6506 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
6507 | return; | |
6508 | ||
a580516d | 6509 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 6510 | |
d288f65f VS |
6511 | bestn = pipe_config->dpll.n; |
6512 | bestm1 = pipe_config->dpll.m1; | |
6513 | bestm2 = pipe_config->dpll.m2; | |
6514 | bestp1 = pipe_config->dpll.p1; | |
6515 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 6516 | |
89b667f8 JB |
6517 | /* See eDP HDMI DPIO driver vbios notes doc */ |
6518 | ||
6519 | /* PLL B needs special handling */ | |
bdd4b6a6 | 6520 | if (pipe == PIPE_B) |
5e69f97f | 6521 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
6522 | |
6523 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 6524 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
6525 | |
6526 | /* Disable target IRef on PLL */ | |
ab3c759a | 6527 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 6528 | reg_val &= 0x00ffffff; |
ab3c759a | 6529 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
6530 | |
6531 | /* Disable fast lock */ | |
ab3c759a | 6532 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
6533 | |
6534 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
6535 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
6536 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
6537 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 6538 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
6539 | |
6540 | /* | |
6541 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
6542 | * but we don't support that). | |
6543 | * Note: don't use the DAC post divider as it seems unstable. | |
6544 | */ | |
6545 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 6546 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6547 | |
a0c4da24 | 6548 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 6549 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 6550 | |
89b667f8 | 6551 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 6552 | if (pipe_config->port_clock == 162000 || |
2d84d2b3 VS |
6553 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_ANALOG) || |
6554 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 6555 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 6556 | 0x009f0003); |
89b667f8 | 6557 | else |
ab3c759a | 6558 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
6559 | 0x00d0000f); |
6560 | ||
37a5650b | 6561 | if (intel_crtc_has_dp_encoder(pipe_config)) { |
89b667f8 | 6562 | /* Use SSC source */ |
bdd4b6a6 | 6563 | if (pipe == PIPE_A) |
ab3c759a | 6564 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6565 | 0x0df40000); |
6566 | else | |
ab3c759a | 6567 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6568 | 0x0df70000); |
6569 | } else { /* HDMI or VGA */ | |
6570 | /* Use bend source */ | |
bdd4b6a6 | 6571 | if (pipe == PIPE_A) |
ab3c759a | 6572 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6573 | 0x0df70000); |
6574 | else | |
ab3c759a | 6575 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
6576 | 0x0df40000); |
6577 | } | |
a0c4da24 | 6578 | |
ab3c759a | 6579 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 6580 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
2210ce7f | 6581 | if (intel_crtc_has_dp_encoder(crtc->config)) |
89b667f8 | 6582 | coreclk |= 0x01000000; |
ab3c759a | 6583 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 6584 | |
ab3c759a | 6585 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 6586 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
6587 | } |
6588 | ||
d288f65f | 6589 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 6590 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
6591 | { |
6592 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6593 | struct drm_i915_private *dev_priv = to_i915(dev); |
cd2d34d9 | 6594 | enum pipe pipe = crtc->pipe; |
9d556c99 | 6595 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 6596 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 6597 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 6598 | u32 dpio_val; |
9cbe40c1 | 6599 | int vco; |
9d556c99 | 6600 | |
cd2d34d9 VS |
6601 | /* Enable Refclk and SSC */ |
6602 | I915_WRITE(DPLL(pipe), | |
6603 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
6604 | ||
6605 | /* No need to actually set up the DPLL with DSI */ | |
6606 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
6607 | return; | |
6608 | ||
d288f65f VS |
6609 | bestn = pipe_config->dpll.n; |
6610 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
6611 | bestm1 = pipe_config->dpll.m1; | |
6612 | bestm2 = pipe_config->dpll.m2 >> 22; | |
6613 | bestp1 = pipe_config->dpll.p1; | |
6614 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 6615 | vco = pipe_config->dpll.vco; |
a945ce7e | 6616 | dpio_val = 0; |
9cbe40c1 | 6617 | loopfilter = 0; |
9d556c99 | 6618 | |
a580516d | 6619 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 6620 | |
9d556c99 CML |
6621 | /* p1 and p2 divider */ |
6622 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
6623 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
6624 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
6625 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
6626 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
6627 | ||
6628 | /* Feedback post-divider - m2 */ | |
6629 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
6630 | ||
6631 | /* Feedback refclk divider - n and m1 */ | |
6632 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
6633 | DPIO_CHV_M1_DIV_BY_2 | | |
6634 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
6635 | ||
6636 | /* M2 fraction division */ | |
25a25dfc | 6637 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
6638 | |
6639 | /* M2 fraction division enable */ | |
a945ce7e VP |
6640 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
6641 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
6642 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
6643 | if (bestm2_frac) | |
6644 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
6645 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 6646 | |
de3a0fde VP |
6647 | /* Program digital lock detect threshold */ |
6648 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
6649 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
6650 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
6651 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
6652 | if (!bestm2_frac) | |
6653 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
6654 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
6655 | ||
9d556c99 | 6656 | /* Loop filter */ |
9cbe40c1 VP |
6657 | if (vco == 5400000) { |
6658 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6659 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
6660 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6661 | tribuf_calcntr = 0x9; | |
6662 | } else if (vco <= 6200000) { | |
6663 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6664 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
6665 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6666 | tribuf_calcntr = 0x9; | |
6667 | } else if (vco <= 6480000) { | |
6668 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6669 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6670 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6671 | tribuf_calcntr = 0x8; | |
6672 | } else { | |
6673 | /* Not supported. Apply the same limits as in the max case */ | |
6674 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
6675 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
6676 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
6677 | tribuf_calcntr = 0; | |
6678 | } | |
9d556c99 CML |
6679 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
6680 | ||
968040b2 | 6681 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
6682 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
6683 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
6684 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
6685 | ||
9d556c99 CML |
6686 | /* AFC Recal */ |
6687 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
6688 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
6689 | DPIO_AFC_RECAL); | |
6690 | ||
a580516d | 6691 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
6692 | } |
6693 | ||
d288f65f VS |
6694 | /** |
6695 | * vlv_force_pll_on - forcibly enable just the PLL | |
6696 | * @dev_priv: i915 private structure | |
6697 | * @pipe: pipe PLL to enable | |
6698 | * @dpll: PLL configuration | |
6699 | * | |
6700 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
6701 | * in cases where we need the PLL enabled even when @pipe is not going to | |
6702 | * be enabled. | |
6703 | */ | |
30ad9814 | 6704 | int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, |
3f36b937 | 6705 | const struct dpll *dpll) |
d288f65f | 6706 | { |
b91eb5cc | 6707 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
3f36b937 TU |
6708 | struct intel_crtc_state *pipe_config; |
6709 | ||
6710 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
6711 | if (!pipe_config) | |
6712 | return -ENOMEM; | |
6713 | ||
6714 | pipe_config->base.crtc = &crtc->base; | |
6715 | pipe_config->pixel_multiplier = 1; | |
6716 | pipe_config->dpll = *dpll; | |
d288f65f | 6717 | |
30ad9814 | 6718 | if (IS_CHERRYVIEW(dev_priv)) { |
3f36b937 TU |
6719 | chv_compute_dpll(crtc, pipe_config); |
6720 | chv_prepare_pll(crtc, pipe_config); | |
6721 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 6722 | } else { |
3f36b937 TU |
6723 | vlv_compute_dpll(crtc, pipe_config); |
6724 | vlv_prepare_pll(crtc, pipe_config); | |
6725 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 6726 | } |
3f36b937 TU |
6727 | |
6728 | kfree(pipe_config); | |
6729 | ||
6730 | return 0; | |
d288f65f VS |
6731 | } |
6732 | ||
6733 | /** | |
6734 | * vlv_force_pll_off - forcibly disable just the PLL | |
6735 | * @dev_priv: i915 private structure | |
6736 | * @pipe: pipe PLL to disable | |
6737 | * | |
6738 | * Disable the PLL for @pipe. To be used in cases where we need | |
6739 | * the PLL enabled even when @pipe is not going to be enabled. | |
6740 | */ | |
30ad9814 | 6741 | void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe) |
d288f65f | 6742 | { |
30ad9814 VS |
6743 | if (IS_CHERRYVIEW(dev_priv)) |
6744 | chv_disable_pll(dev_priv, pipe); | |
d288f65f | 6745 | else |
30ad9814 | 6746 | vlv_disable_pll(dev_priv, pipe); |
d288f65f VS |
6747 | } |
6748 | ||
251ac862 DV |
6749 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
6750 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 6751 | struct dpll *reduced_clock) |
eb1cbe48 | 6752 | { |
9b1e14f4 | 6753 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
eb1cbe48 | 6754 | u32 dpll; |
190f68c5 | 6755 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 6756 | |
190f68c5 | 6757 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 6758 | |
eb1cbe48 DV |
6759 | dpll = DPLL_VGA_MODE_DIS; |
6760 | ||
2d84d2b3 | 6761 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
6762 | dpll |= DPLLB_MODE_LVDS; |
6763 | else | |
6764 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 6765 | |
73f67aa8 JN |
6766 | if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || |
6767 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { | |
190f68c5 | 6768 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 6769 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 6770 | } |
198a037f | 6771 | |
3d6e9ee0 VS |
6772 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
6773 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 6774 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 6775 | |
37a5650b | 6776 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 6777 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
6778 | |
6779 | /* compute bitmask from p1 value */ | |
9b1e14f4 | 6780 | if (IS_PINEVIEW(dev_priv)) |
eb1cbe48 DV |
6781 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; |
6782 | else { | |
6783 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
9beb5fea | 6784 | if (IS_G4X(dev_priv) && reduced_clock) |
eb1cbe48 DV |
6785 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
6786 | } | |
6787 | switch (clock->p2) { | |
6788 | case 5: | |
6789 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
6790 | break; | |
6791 | case 7: | |
6792 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
6793 | break; | |
6794 | case 10: | |
6795 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
6796 | break; | |
6797 | case 14: | |
6798 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
6799 | break; | |
6800 | } | |
9b1e14f4 | 6801 | if (INTEL_GEN(dev_priv) >= 4) |
eb1cbe48 DV |
6802 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); |
6803 | ||
190f68c5 | 6804 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 6805 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
2d84d2b3 | 6806 | else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 6807 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
6808 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
6809 | else | |
6810 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6811 | ||
6812 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 6813 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 6814 | |
9b1e14f4 | 6815 | if (INTEL_GEN(dev_priv) >= 4) { |
190f68c5 | 6816 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 6817 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 6818 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
6819 | } |
6820 | } | |
6821 | ||
251ac862 DV |
6822 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
6823 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 6824 | struct dpll *reduced_clock) |
eb1cbe48 | 6825 | { |
f47709a9 | 6826 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 6827 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb1cbe48 | 6828 | u32 dpll; |
190f68c5 | 6829 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 6830 | |
190f68c5 | 6831 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 6832 | |
eb1cbe48 DV |
6833 | dpll = DPLL_VGA_MODE_DIS; |
6834 | ||
2d84d2b3 | 6835 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
6836 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
6837 | } else { | |
6838 | if (clock->p1 == 2) | |
6839 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
6840 | else | |
6841 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
6842 | if (clock->p2 == 4) | |
6843 | dpll |= PLL_P2_DIVIDE_BY_4; | |
6844 | } | |
6845 | ||
50a0bc90 TU |
6846 | if (!IS_I830(dev_priv) && |
6847 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) | |
4a33e48d DV |
6848 | dpll |= DPLL_DVO_2X_MODE; |
6849 | ||
2d84d2b3 | 6850 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 6851 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
6852 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
6853 | else | |
6854 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6855 | ||
6856 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 6857 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
6858 | } |
6859 | ||
8a654f3b | 6860 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c | 6861 | { |
6315b5d3 | 6862 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
b0e77b9c | 6863 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 6864 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 6865 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
6866 | uint32_t crtc_vtotal, crtc_vblank_end; |
6867 | int vsyncshift = 0; | |
4d8a62ea DV |
6868 | |
6869 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
6870 | * the hw state checker will get angry at the mismatch. */ | |
6871 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
6872 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 6873 | |
609aeaca | 6874 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 6875 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
6876 | crtc_vtotal -= 1; |
6877 | crtc_vblank_end -= 1; | |
609aeaca | 6878 | |
2d84d2b3 | 6879 | if (intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
6880 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
6881 | else | |
6882 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
6883 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
6884 | if (vsyncshift < 0) |
6885 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
6886 | } |
6887 | ||
6315b5d3 | 6888 | if (INTEL_GEN(dev_priv) > 3) |
fe2b8f9d | 6889 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 6890 | |
fe2b8f9d | 6891 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
6892 | (adjusted_mode->crtc_hdisplay - 1) | |
6893 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 6894 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
6895 | (adjusted_mode->crtc_hblank_start - 1) | |
6896 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 6897 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
6898 | (adjusted_mode->crtc_hsync_start - 1) | |
6899 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
6900 | ||
fe2b8f9d | 6901 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 6902 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 6903 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 6904 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 6905 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 6906 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 6907 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
6908 | (adjusted_mode->crtc_vsync_start - 1) | |
6909 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
6910 | ||
b5e508d4 PZ |
6911 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
6912 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
6913 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
6914 | * bits. */ | |
772c2a51 | 6915 | if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP && |
b5e508d4 PZ |
6916 | (pipe == PIPE_B || pipe == PIPE_C)) |
6917 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
6918 | ||
bc58be60 JN |
6919 | } |
6920 | ||
6921 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) | |
6922 | { | |
6923 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 6924 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 JN |
6925 | enum pipe pipe = intel_crtc->pipe; |
6926 | ||
b0e77b9c PZ |
6927 | /* pipesrc controls the size that is scaled from, which should |
6928 | * always be the user's requested size. | |
6929 | */ | |
6930 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
6931 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
6932 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
6933 | } |
6934 | ||
1bd1bd80 | 6935 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 6936 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
6937 | { |
6938 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6939 | struct drm_i915_private *dev_priv = to_i915(dev); |
1bd1bd80 DV |
6940 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
6941 | uint32_t tmp; | |
6942 | ||
6943 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
6944 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
6945 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6946 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
6947 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
6948 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6949 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
6950 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
6951 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
6952 | |
6953 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
6954 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
6955 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6956 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
6957 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
6958 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 6959 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
6960 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
6961 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
6962 | |
6963 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
6964 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
6965 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
6966 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 | 6967 | } |
bc58be60 JN |
6968 | } |
6969 | ||
6970 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, | |
6971 | struct intel_crtc_state *pipe_config) | |
6972 | { | |
6973 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 6974 | struct drm_i915_private *dev_priv = to_i915(dev); |
bc58be60 | 6975 | u32 tmp; |
1bd1bd80 DV |
6976 | |
6977 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
6978 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
6979 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
6980 | ||
2d112de7 ACO |
6981 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
6982 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
6983 | } |
6984 | ||
f6a83288 | 6985 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 6986 | struct intel_crtc_state *pipe_config) |
babea61d | 6987 | { |
2d112de7 ACO |
6988 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
6989 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
6990 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
6991 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 6992 | |
2d112de7 ACO |
6993 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
6994 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
6995 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
6996 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 6997 | |
2d112de7 | 6998 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 6999 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7000 | |
2d112de7 | 7001 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
cd13f5ab ML |
7002 | |
7003 | mode->hsync = drm_mode_hsync(mode); | |
7004 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7005 | drm_mode_set_name(mode); | |
babea61d JB |
7006 | } |
7007 | ||
84b046f3 DV |
7008 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7009 | { | |
6315b5d3 | 7010 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
84b046f3 DV |
7011 | uint32_t pipeconf; |
7012 | ||
9f11a9e4 | 7013 | pipeconf = 0; |
84b046f3 | 7014 | |
b6b5d049 VS |
7015 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7016 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7017 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7018 | |
6e3c9717 | 7019 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7020 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7021 | |
ff9ce46e | 7022 | /* only g4x and later have fancy bpc/dither controls */ |
9beb5fea TU |
7023 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
7024 | IS_CHERRYVIEW(dev_priv)) { | |
ff9ce46e | 7025 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7026 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7027 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7028 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7029 | |
6e3c9717 | 7030 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7031 | case 18: |
7032 | pipeconf |= PIPECONF_6BPC; | |
7033 | break; | |
7034 | case 24: | |
7035 | pipeconf |= PIPECONF_8BPC; | |
7036 | break; | |
7037 | case 30: | |
7038 | pipeconf |= PIPECONF_10BPC; | |
7039 | break; | |
7040 | default: | |
7041 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7042 | BUG(); | |
84b046f3 DV |
7043 | } |
7044 | } | |
7045 | ||
56b857a5 | 7046 | if (HAS_PIPE_CXSR(dev_priv)) { |
84b046f3 DV |
7047 | if (intel_crtc->lowfreq_avail) { |
7048 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7049 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7050 | } else { | |
7051 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7052 | } |
7053 | } | |
7054 | ||
6e3c9717 | 7055 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
6315b5d3 | 7056 | if (INTEL_GEN(dev_priv) < 4 || |
2d84d2b3 | 7057 | intel_crtc_has_type(intel_crtc->config, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7058 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7059 | else | |
7060 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7061 | } else | |
84b046f3 DV |
7062 | pipeconf |= PIPECONF_PROGRESSIVE; |
7063 | ||
920a14b2 | 7064 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 7065 | intel_crtc->config->limited_color_range) |
9f11a9e4 | 7066 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7067 | |
84b046f3 DV |
7068 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7069 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7070 | } | |
7071 | ||
81c97f52 ACO |
7072 | static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, |
7073 | struct intel_crtc_state *crtc_state) | |
7074 | { | |
7075 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7076 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7077 | const struct intel_limit *limit; |
81c97f52 ACO |
7078 | int refclk = 48000; |
7079 | ||
7080 | memset(&crtc_state->dpll_hw_state, 0, | |
7081 | sizeof(crtc_state->dpll_hw_state)); | |
7082 | ||
2d84d2b3 | 7083 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
81c97f52 ACO |
7084 | if (intel_panel_use_ssc(dev_priv)) { |
7085 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7086 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7087 | } | |
7088 | ||
7089 | limit = &intel_limits_i8xx_lvds; | |
2d84d2b3 | 7090 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { |
81c97f52 ACO |
7091 | limit = &intel_limits_i8xx_dvo; |
7092 | } else { | |
7093 | limit = &intel_limits_i8xx_dac; | |
7094 | } | |
7095 | ||
7096 | if (!crtc_state->clock_set && | |
7097 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7098 | refclk, NULL, &crtc_state->dpll)) { | |
7099 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7100 | return -EINVAL; | |
7101 | } | |
7102 | ||
7103 | i8xx_compute_dpll(crtc, crtc_state, NULL); | |
7104 | ||
7105 | return 0; | |
7106 | } | |
7107 | ||
19ec6693 ACO |
7108 | static int g4x_crtc_compute_clock(struct intel_crtc *crtc, |
7109 | struct intel_crtc_state *crtc_state) | |
7110 | { | |
7111 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7112 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7113 | const struct intel_limit *limit; |
19ec6693 ACO |
7114 | int refclk = 96000; |
7115 | ||
7116 | memset(&crtc_state->dpll_hw_state, 0, | |
7117 | sizeof(crtc_state->dpll_hw_state)); | |
7118 | ||
2d84d2b3 | 7119 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
19ec6693 ACO |
7120 | if (intel_panel_use_ssc(dev_priv)) { |
7121 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7122 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7123 | } | |
7124 | ||
7125 | if (intel_is_dual_link_lvds(dev)) | |
7126 | limit = &intel_limits_g4x_dual_channel_lvds; | |
7127 | else | |
7128 | limit = &intel_limits_g4x_single_channel_lvds; | |
2d84d2b3 VS |
7129 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || |
7130 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
19ec6693 | 7131 | limit = &intel_limits_g4x_hdmi; |
2d84d2b3 | 7132 | } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
19ec6693 ACO |
7133 | limit = &intel_limits_g4x_sdvo; |
7134 | } else { | |
7135 | /* The option is for other outputs */ | |
7136 | limit = &intel_limits_i9xx_sdvo; | |
7137 | } | |
7138 | ||
7139 | if (!crtc_state->clock_set && | |
7140 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7141 | refclk, NULL, &crtc_state->dpll)) { | |
7142 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7143 | return -EINVAL; | |
7144 | } | |
7145 | ||
7146 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7147 | ||
7148 | return 0; | |
7149 | } | |
7150 | ||
70e8aa21 ACO |
7151 | static int pnv_crtc_compute_clock(struct intel_crtc *crtc, |
7152 | struct intel_crtc_state *crtc_state) | |
7153 | { | |
7154 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7155 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7156 | const struct intel_limit *limit; |
70e8aa21 ACO |
7157 | int refclk = 96000; |
7158 | ||
7159 | memset(&crtc_state->dpll_hw_state, 0, | |
7160 | sizeof(crtc_state->dpll_hw_state)); | |
7161 | ||
2d84d2b3 | 7162 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
7163 | if (intel_panel_use_ssc(dev_priv)) { |
7164 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7165 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7166 | } | |
7167 | ||
7168 | limit = &intel_limits_pineview_lvds; | |
7169 | } else { | |
7170 | limit = &intel_limits_pineview_sdvo; | |
7171 | } | |
7172 | ||
7173 | if (!crtc_state->clock_set && | |
7174 | !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7175 | refclk, NULL, &crtc_state->dpll)) { | |
7176 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7177 | return -EINVAL; | |
7178 | } | |
7179 | ||
7180 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7181 | ||
7182 | return 0; | |
7183 | } | |
7184 | ||
190f68c5 ACO |
7185 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7186 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7187 | { |
c7653199 | 7188 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 7189 | struct drm_i915_private *dev_priv = to_i915(dev); |
1b6f4958 | 7190 | const struct intel_limit *limit; |
81c97f52 | 7191 | int refclk = 96000; |
79e53945 | 7192 | |
dd3cd74a ACO |
7193 | memset(&crtc_state->dpll_hw_state, 0, |
7194 | sizeof(crtc_state->dpll_hw_state)); | |
7195 | ||
2d84d2b3 | 7196 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
70e8aa21 ACO |
7197 | if (intel_panel_use_ssc(dev_priv)) { |
7198 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7199 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7200 | } | |
43565a06 | 7201 | |
70e8aa21 ACO |
7202 | limit = &intel_limits_i9xx_lvds; |
7203 | } else { | |
7204 | limit = &intel_limits_i9xx_sdvo; | |
81c97f52 | 7205 | } |
79e53945 | 7206 | |
70e8aa21 ACO |
7207 | if (!crtc_state->clock_set && |
7208 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7209 | refclk, NULL, &crtc_state->dpll)) { | |
7210 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7211 | return -EINVAL; | |
f47709a9 | 7212 | } |
7026d4ac | 7213 | |
81c97f52 | 7214 | i9xx_compute_dpll(crtc, crtc_state, NULL); |
79e53945 | 7215 | |
c8f7a0db | 7216 | return 0; |
f564048e EA |
7217 | } |
7218 | ||
65b3d6a9 ACO |
7219 | static int chv_crtc_compute_clock(struct intel_crtc *crtc, |
7220 | struct intel_crtc_state *crtc_state) | |
7221 | { | |
7222 | int refclk = 100000; | |
1b6f4958 | 7223 | const struct intel_limit *limit = &intel_limits_chv; |
65b3d6a9 ACO |
7224 | |
7225 | memset(&crtc_state->dpll_hw_state, 0, | |
7226 | sizeof(crtc_state->dpll_hw_state)); | |
7227 | ||
65b3d6a9 ACO |
7228 | if (!crtc_state->clock_set && |
7229 | !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7230 | refclk, NULL, &crtc_state->dpll)) { | |
7231 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7232 | return -EINVAL; | |
7233 | } | |
7234 | ||
7235 | chv_compute_dpll(crtc, crtc_state); | |
7236 | ||
7237 | return 0; | |
7238 | } | |
7239 | ||
7240 | static int vlv_crtc_compute_clock(struct intel_crtc *crtc, | |
7241 | struct intel_crtc_state *crtc_state) | |
7242 | { | |
7243 | int refclk = 100000; | |
1b6f4958 | 7244 | const struct intel_limit *limit = &intel_limits_vlv; |
65b3d6a9 ACO |
7245 | |
7246 | memset(&crtc_state->dpll_hw_state, 0, | |
7247 | sizeof(crtc_state->dpll_hw_state)); | |
7248 | ||
65b3d6a9 ACO |
7249 | if (!crtc_state->clock_set && |
7250 | !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7251 | refclk, NULL, &crtc_state->dpll)) { | |
7252 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7253 | return -EINVAL; | |
7254 | } | |
7255 | ||
7256 | vlv_compute_dpll(crtc, crtc_state); | |
7257 | ||
7258 | return 0; | |
7259 | } | |
7260 | ||
2fa2fe9a | 7261 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7262 | struct intel_crtc_state *pipe_config) |
2fa2fe9a | 7263 | { |
6315b5d3 | 7264 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
2fa2fe9a DV |
7265 | uint32_t tmp; |
7266 | ||
50a0bc90 TU |
7267 | if (INTEL_GEN(dev_priv) <= 3 && |
7268 | (IS_I830(dev_priv) || !IS_MOBILE(dev_priv))) | |
dc9e7dec VS |
7269 | return; |
7270 | ||
2fa2fe9a | 7271 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7272 | if (!(tmp & PFIT_ENABLE)) |
7273 | return; | |
2fa2fe9a | 7274 | |
06922821 | 7275 | /* Check whether the pfit is attached to our pipe. */ |
6315b5d3 | 7276 | if (INTEL_GEN(dev_priv) < 4) { |
2fa2fe9a DV |
7277 | if (crtc->pipe != PIPE_B) |
7278 | return; | |
2fa2fe9a DV |
7279 | } else { |
7280 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
7281 | return; | |
7282 | } | |
7283 | ||
06922821 | 7284 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a | 7285 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
2fa2fe9a DV |
7286 | } |
7287 | ||
acbec814 | 7288 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7289 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
7290 | { |
7291 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7292 | struct drm_i915_private *dev_priv = to_i915(dev); |
acbec814 | 7293 | int pipe = pipe_config->cpu_transcoder; |
9e2c8475 | 7294 | struct dpll clock; |
acbec814 | 7295 | u32 mdiv; |
662c6ecb | 7296 | int refclk = 100000; |
acbec814 | 7297 | |
b521973b VS |
7298 | /* In case of DSI, DPLL will not be used */ |
7299 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
f573de5a SK |
7300 | return; |
7301 | ||
a580516d | 7302 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 7303 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 7304 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
7305 | |
7306 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
7307 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
7308 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
7309 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
7310 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
7311 | ||
dccbea3b | 7312 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
7313 | } |
7314 | ||
5724dbd1 DL |
7315 | static void |
7316 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
7317 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
7318 | { |
7319 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7320 | struct drm_i915_private *dev_priv = to_i915(dev); |
1ad292b5 JB |
7321 | u32 val, base, offset; |
7322 | int pipe = crtc->pipe, plane = crtc->plane; | |
7323 | int fourcc, pixel_format; | |
6761dd31 | 7324 | unsigned int aligned_height; |
b113d5ee | 7325 | struct drm_framebuffer *fb; |
1b842c89 | 7326 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 7327 | |
42a7b088 DL |
7328 | val = I915_READ(DSPCNTR(plane)); |
7329 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
7330 | return; | |
7331 | ||
d9806c9f | 7332 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 7333 | if (!intel_fb) { |
1ad292b5 JB |
7334 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7335 | return; | |
7336 | } | |
7337 | ||
1b842c89 DL |
7338 | fb = &intel_fb->base; |
7339 | ||
d2e9f5fc VS |
7340 | fb->dev = dev; |
7341 | ||
6315b5d3 | 7342 | if (INTEL_GEN(dev_priv) >= 4) { |
18c5247e | 7343 | if (val & DISPPLANE_TILED) { |
49af449b | 7344 | plane_config->tiling = I915_TILING_X; |
bae781b2 | 7345 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
18c5247e DV |
7346 | } |
7347 | } | |
1ad292b5 JB |
7348 | |
7349 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 7350 | fourcc = i9xx_format_to_fourcc(pixel_format); |
2f3f4763 | 7351 | fb->format = drm_format_info(fourcc); |
1ad292b5 | 7352 | |
6315b5d3 | 7353 | if (INTEL_GEN(dev_priv) >= 4) { |
49af449b | 7354 | if (plane_config->tiling) |
1ad292b5 JB |
7355 | offset = I915_READ(DSPTILEOFF(plane)); |
7356 | else | |
7357 | offset = I915_READ(DSPLINOFF(plane)); | |
7358 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7359 | } else { | |
7360 | base = I915_READ(DSPADDR(plane)); | |
7361 | } | |
7362 | plane_config->base = base; | |
7363 | ||
7364 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
7365 | fb->width = ((val >> 16) & 0xfff) + 1; |
7366 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
7367 | |
7368 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 7369 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 7370 | |
d88c4afd | 7371 | aligned_height = intel_fb_align_height(fb, 0, fb->height); |
1ad292b5 | 7372 | |
f37b5c2b | 7373 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 7374 | |
2844a921 DL |
7375 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
7376 | pipe_name(pipe), plane, fb->width, fb->height, | |
272725c7 | 7377 | fb->format->cpp[0] * 8, base, fb->pitches[0], |
2844a921 | 7378 | plane_config->size); |
1ad292b5 | 7379 | |
2d14030b | 7380 | plane_config->fb = intel_fb; |
1ad292b5 JB |
7381 | } |
7382 | ||
70b23a98 | 7383 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 7384 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
7385 | { |
7386 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 7387 | struct drm_i915_private *dev_priv = to_i915(dev); |
70b23a98 VS |
7388 | int pipe = pipe_config->cpu_transcoder; |
7389 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9e2c8475 | 7390 | struct dpll clock; |
0d7b6b11 | 7391 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
7392 | int refclk = 100000; |
7393 | ||
b521973b VS |
7394 | /* In case of DSI, DPLL will not be used */ |
7395 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7396 | return; | |
7397 | ||
a580516d | 7398 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
7399 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
7400 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
7401 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
7402 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 7403 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 7404 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
7405 | |
7406 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
7407 | clock.m2 = (pll_dw0 & 0xff) << 22; |
7408 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
7409 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
7410 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
7411 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
7412 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
7413 | ||
dccbea3b | 7414 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
7415 | } |
7416 | ||
0e8ffe1b | 7417 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 7418 | struct intel_crtc_state *pipe_config) |
0e8ffe1b | 7419 | { |
6315b5d3 | 7420 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1729050e | 7421 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 7422 | uint32_t tmp; |
1729050e | 7423 | bool ret; |
0e8ffe1b | 7424 | |
1729050e ID |
7425 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
7426 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 ID |
7427 | return false; |
7428 | ||
e143a21c | 7429 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 7430 | pipe_config->shared_dpll = NULL; |
eccb140b | 7431 | |
1729050e ID |
7432 | ret = false; |
7433 | ||
0e8ffe1b DV |
7434 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7435 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 7436 | goto out; |
0e8ffe1b | 7437 | |
9beb5fea TU |
7438 | if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
7439 | IS_CHERRYVIEW(dev_priv)) { | |
42571aef VS |
7440 | switch (tmp & PIPECONF_BPC_MASK) { |
7441 | case PIPECONF_6BPC: | |
7442 | pipe_config->pipe_bpp = 18; | |
7443 | break; | |
7444 | case PIPECONF_8BPC: | |
7445 | pipe_config->pipe_bpp = 24; | |
7446 | break; | |
7447 | case PIPECONF_10BPC: | |
7448 | pipe_config->pipe_bpp = 30; | |
7449 | break; | |
7450 | default: | |
7451 | break; | |
7452 | } | |
7453 | } | |
7454 | ||
920a14b2 | 7455 | if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && |
666a4537 | 7456 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
b5a9fa09 DV |
7457 | pipe_config->limited_color_range = true; |
7458 | ||
6315b5d3 | 7459 | if (INTEL_GEN(dev_priv) < 4) |
282740f7 VS |
7460 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; |
7461 | ||
1bd1bd80 | 7462 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 7463 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 7464 | |
2fa2fe9a DV |
7465 | i9xx_get_pfit_config(crtc, pipe_config); |
7466 | ||
6315b5d3 | 7467 | if (INTEL_GEN(dev_priv) >= 4) { |
c231775c | 7468 | /* No way to read it out on pipes B and C */ |
920a14b2 | 7469 | if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A) |
c231775c VS |
7470 | tmp = dev_priv->chv_dpll_md[crtc->pipe]; |
7471 | else | |
7472 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6c49f241 DV |
7473 | pipe_config->pixel_multiplier = |
7474 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
7475 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 7476 | pipe_config->dpll_hw_state.dpll_md = tmp; |
50a0bc90 | 7477 | } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || |
73f67aa8 | 7478 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { |
6c49f241 DV |
7479 | tmp = I915_READ(DPLL(crtc->pipe)); |
7480 | pipe_config->pixel_multiplier = | |
7481 | ((tmp & SDVO_MULTIPLIER_MASK) | |
7482 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
7483 | } else { | |
7484 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
7485 | * port and will be fixed up in the encoder->get_config | |
7486 | * function. */ | |
7487 | pipe_config->pixel_multiplier = 1; | |
7488 | } | |
8bcc2795 | 7489 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
920a14b2 | 7490 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
1c4e0274 VS |
7491 | /* |
7492 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
7493 | * on 830. Filter it out here so that we don't | |
7494 | * report errors due to that. | |
7495 | */ | |
50a0bc90 | 7496 | if (IS_I830(dev_priv)) |
1c4e0274 VS |
7497 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; |
7498 | ||
8bcc2795 DV |
7499 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
7500 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
7501 | } else { |
7502 | /* Mask out read-only status bits. */ | |
7503 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
7504 | DPLL_PORTC_READY_MASK | | |
7505 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 7506 | } |
6c49f241 | 7507 | |
920a14b2 | 7508 | if (IS_CHERRYVIEW(dev_priv)) |
70b23a98 | 7509 | chv_crtc_clock_get(crtc, pipe_config); |
11a914c2 | 7510 | else if (IS_VALLEYVIEW(dev_priv)) |
acbec814 JB |
7511 | vlv_crtc_clock_get(crtc, pipe_config); |
7512 | else | |
7513 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 7514 | |
0f64614d VS |
7515 | /* |
7516 | * Normally the dotclock is filled in by the encoder .get_config() | |
7517 | * but in case the pipe is enabled w/o any ports we need a sane | |
7518 | * default. | |
7519 | */ | |
7520 | pipe_config->base.adjusted_mode.crtc_clock = | |
7521 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
7522 | ||
1729050e ID |
7523 | ret = true; |
7524 | ||
7525 | out: | |
7526 | intel_display_power_put(dev_priv, power_domain); | |
7527 | ||
7528 | return ret; | |
0e8ffe1b DV |
7529 | } |
7530 | ||
c39055b0 | 7531 | static void ironlake_init_pch_refclk(struct drm_i915_private *dev_priv) |
13d83a67 | 7532 | { |
13d83a67 | 7533 | struct intel_encoder *encoder; |
1c1a24d2 | 7534 | int i; |
74cfd7ac | 7535 | u32 val, final; |
13d83a67 | 7536 | bool has_lvds = false; |
199e5d79 | 7537 | bool has_cpu_edp = false; |
199e5d79 | 7538 | bool has_panel = false; |
99eb6a01 KP |
7539 | bool has_ck505 = false; |
7540 | bool can_ssc = false; | |
1c1a24d2 | 7541 | bool using_ssc_source = false; |
13d83a67 JB |
7542 | |
7543 | /* We need to take the global config into account */ | |
c39055b0 | 7544 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
199e5d79 KP |
7545 | switch (encoder->type) { |
7546 | case INTEL_OUTPUT_LVDS: | |
7547 | has_panel = true; | |
7548 | has_lvds = true; | |
7549 | break; | |
7550 | case INTEL_OUTPUT_EDP: | |
7551 | has_panel = true; | |
2de6905f | 7552 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
7553 | has_cpu_edp = true; |
7554 | break; | |
6847d71b PZ |
7555 | default: |
7556 | break; | |
13d83a67 JB |
7557 | } |
7558 | } | |
7559 | ||
6e266956 | 7560 | if (HAS_PCH_IBX(dev_priv)) { |
41aa3448 | 7561 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
7562 | can_ssc = has_ck505; |
7563 | } else { | |
7564 | has_ck505 = false; | |
7565 | can_ssc = true; | |
7566 | } | |
7567 | ||
1c1a24d2 L |
7568 | /* Check if any DPLLs are using the SSC source */ |
7569 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
7570 | u32 temp = I915_READ(PCH_DPLL(i)); | |
7571 | ||
7572 | if (!(temp & DPLL_VCO_ENABLE)) | |
7573 | continue; | |
7574 | ||
7575 | if ((temp & PLL_REF_INPUT_MASK) == | |
7576 | PLLB_REF_INPUT_SPREADSPECTRUMIN) { | |
7577 | using_ssc_source = true; | |
7578 | break; | |
7579 | } | |
7580 | } | |
7581 | ||
7582 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d using_ssc_source %d\n", | |
7583 | has_panel, has_lvds, has_ck505, using_ssc_source); | |
13d83a67 JB |
7584 | |
7585 | /* Ironlake: try to setup display ref clock before DPLL | |
7586 | * enabling. This is only under driver's control after | |
7587 | * PCH B stepping, previous chipset stepping should be | |
7588 | * ignoring this setting. | |
7589 | */ | |
74cfd7ac CW |
7590 | val = I915_READ(PCH_DREF_CONTROL); |
7591 | ||
7592 | /* As we must carefully and slowly disable/enable each source in turn, | |
7593 | * compute the final state we want first and check if we need to | |
7594 | * make any changes at all. | |
7595 | */ | |
7596 | final = val; | |
7597 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
7598 | if (has_ck505) | |
7599 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
7600 | else | |
7601 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
7602 | ||
8c07eb68 | 7603 | final &= ~DREF_SSC_SOURCE_MASK; |
74cfd7ac | 7604 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
8c07eb68 | 7605 | final &= ~DREF_SSC1_ENABLE; |
74cfd7ac CW |
7606 | |
7607 | if (has_panel) { | |
7608 | final |= DREF_SSC_SOURCE_ENABLE; | |
7609 | ||
7610 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7611 | final |= DREF_SSC1_ENABLE; | |
7612 | ||
7613 | if (has_cpu_edp) { | |
7614 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
7615 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
7616 | else | |
7617 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
7618 | } else | |
7619 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
1c1a24d2 L |
7620 | } else if (using_ssc_source) { |
7621 | final |= DREF_SSC_SOURCE_ENABLE; | |
7622 | final |= DREF_SSC1_ENABLE; | |
74cfd7ac CW |
7623 | } |
7624 | ||
7625 | if (final == val) | |
7626 | return; | |
7627 | ||
13d83a67 | 7628 | /* Always enable nonspread source */ |
74cfd7ac | 7629 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 7630 | |
99eb6a01 | 7631 | if (has_ck505) |
74cfd7ac | 7632 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 7633 | else |
74cfd7ac | 7634 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 7635 | |
199e5d79 | 7636 | if (has_panel) { |
74cfd7ac CW |
7637 | val &= ~DREF_SSC_SOURCE_MASK; |
7638 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 7639 | |
199e5d79 | 7640 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 7641 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7642 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 7643 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 7644 | } else |
74cfd7ac | 7645 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
7646 | |
7647 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 7648 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7649 | POSTING_READ(PCH_DREF_CONTROL); |
7650 | udelay(200); | |
7651 | ||
74cfd7ac | 7652 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
7653 | |
7654 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 7655 | if (has_cpu_edp) { |
99eb6a01 | 7656 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 7657 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 7658 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 7659 | } else |
74cfd7ac | 7660 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 7661 | } else |
74cfd7ac | 7662 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7663 | |
74cfd7ac | 7664 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7665 | POSTING_READ(PCH_DREF_CONTROL); |
7666 | udelay(200); | |
7667 | } else { | |
1c1a24d2 | 7668 | DRM_DEBUG_KMS("Disabling CPU source output\n"); |
199e5d79 | 7669 | |
74cfd7ac | 7670 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
7671 | |
7672 | /* Turn off CPU output */ | |
74cfd7ac | 7673 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 7674 | |
74cfd7ac | 7675 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
7676 | POSTING_READ(PCH_DREF_CONTROL); |
7677 | udelay(200); | |
7678 | ||
1c1a24d2 L |
7679 | if (!using_ssc_source) { |
7680 | DRM_DEBUG_KMS("Disabling SSC source\n"); | |
199e5d79 | 7681 | |
1c1a24d2 L |
7682 | /* Turn off the SSC source */ |
7683 | val &= ~DREF_SSC_SOURCE_MASK; | |
7684 | val |= DREF_SSC_SOURCE_DISABLE; | |
f165d283 | 7685 | |
1c1a24d2 L |
7686 | /* Turn off SSC1 */ |
7687 | val &= ~DREF_SSC1_ENABLE; | |
7688 | ||
7689 | I915_WRITE(PCH_DREF_CONTROL, val); | |
7690 | POSTING_READ(PCH_DREF_CONTROL); | |
7691 | udelay(200); | |
7692 | } | |
13d83a67 | 7693 | } |
74cfd7ac CW |
7694 | |
7695 | BUG_ON(val != final); | |
13d83a67 JB |
7696 | } |
7697 | ||
f31f2d55 | 7698 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 7699 | { |
f31f2d55 | 7700 | uint32_t tmp; |
dde86e2d | 7701 | |
0ff066a9 PZ |
7702 | tmp = I915_READ(SOUTH_CHICKEN2); |
7703 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
7704 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7705 | |
cf3598c2 ID |
7706 | if (wait_for_us(I915_READ(SOUTH_CHICKEN2) & |
7707 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
0ff066a9 | 7708 | DRM_ERROR("FDI mPHY reset assert timeout\n"); |
dde86e2d | 7709 | |
0ff066a9 PZ |
7710 | tmp = I915_READ(SOUTH_CHICKEN2); |
7711 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
7712 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 7713 | |
cf3598c2 ID |
7714 | if (wait_for_us((I915_READ(SOUTH_CHICKEN2) & |
7715 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
0ff066a9 | 7716 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); |
f31f2d55 PZ |
7717 | } |
7718 | ||
7719 | /* WaMPhyProgramming:hsw */ | |
7720 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
7721 | { | |
7722 | uint32_t tmp; | |
dde86e2d PZ |
7723 | |
7724 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
7725 | tmp &= ~(0xFF << 24); | |
7726 | tmp |= (0x12 << 24); | |
7727 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
7728 | ||
dde86e2d PZ |
7729 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
7730 | tmp |= (1 << 11); | |
7731 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
7732 | ||
7733 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
7734 | tmp |= (1 << 11); | |
7735 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
7736 | ||
dde86e2d PZ |
7737 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
7738 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7739 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
7740 | ||
7741 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
7742 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
7743 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
7744 | ||
0ff066a9 PZ |
7745 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
7746 | tmp &= ~(7 << 13); | |
7747 | tmp |= (5 << 13); | |
7748 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 7749 | |
0ff066a9 PZ |
7750 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
7751 | tmp &= ~(7 << 13); | |
7752 | tmp |= (5 << 13); | |
7753 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
7754 | |
7755 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
7756 | tmp &= ~0xFF; | |
7757 | tmp |= 0x1C; | |
7758 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
7759 | ||
7760 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
7761 | tmp &= ~0xFF; | |
7762 | tmp |= 0x1C; | |
7763 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
7764 | ||
7765 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
7766 | tmp &= ~(0xFF << 16); | |
7767 | tmp |= (0x1C << 16); | |
7768 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
7769 | ||
7770 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
7771 | tmp &= ~(0xFF << 16); | |
7772 | tmp |= (0x1C << 16); | |
7773 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
7774 | ||
0ff066a9 PZ |
7775 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
7776 | tmp |= (1 << 27); | |
7777 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 7778 | |
0ff066a9 PZ |
7779 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
7780 | tmp |= (1 << 27); | |
7781 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 7782 | |
0ff066a9 PZ |
7783 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
7784 | tmp &= ~(0xF << 28); | |
7785 | tmp |= (4 << 28); | |
7786 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 7787 | |
0ff066a9 PZ |
7788 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
7789 | tmp &= ~(0xF << 28); | |
7790 | tmp |= (4 << 28); | |
7791 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
7792 | } |
7793 | ||
2fa86a1f PZ |
7794 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
7795 | * Programming" based on the parameters passed: | |
7796 | * - Sequence to enable CLKOUT_DP | |
7797 | * - Sequence to enable CLKOUT_DP without spread | |
7798 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
7799 | */ | |
c39055b0 ACO |
7800 | static void lpt_enable_clkout_dp(struct drm_i915_private *dev_priv, |
7801 | bool with_spread, bool with_fdi) | |
f31f2d55 | 7802 | { |
2fa86a1f PZ |
7803 | uint32_t reg, tmp; |
7804 | ||
7805 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
7806 | with_spread = true; | |
4f8036a2 TU |
7807 | if (WARN(HAS_PCH_LPT_LP(dev_priv) && |
7808 | with_fdi, "LP PCH doesn't have FDI\n")) | |
2fa86a1f | 7809 | with_fdi = false; |
f31f2d55 | 7810 | |
a580516d | 7811 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
7812 | |
7813 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7814 | tmp &= ~SBI_SSCCTL_DISABLE; | |
7815 | tmp |= SBI_SSCCTL_PATHALT; | |
7816 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7817 | ||
7818 | udelay(24); | |
7819 | ||
2fa86a1f PZ |
7820 | if (with_spread) { |
7821 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7822 | tmp &= ~SBI_SSCCTL_PATHALT; | |
7823 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 7824 | |
2fa86a1f PZ |
7825 | if (with_fdi) { |
7826 | lpt_reset_fdi_mphy(dev_priv); | |
7827 | lpt_program_fdi_mphy(dev_priv); | |
7828 | } | |
7829 | } | |
dde86e2d | 7830 | |
4f8036a2 | 7831 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
7832 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
7833 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7834 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 7835 | |
a580516d | 7836 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
7837 | } |
7838 | ||
47701c3b | 7839 | /* Sequence to disable CLKOUT_DP */ |
c39055b0 | 7840 | static void lpt_disable_clkout_dp(struct drm_i915_private *dev_priv) |
47701c3b | 7841 | { |
47701c3b PZ |
7842 | uint32_t reg, tmp; |
7843 | ||
a580516d | 7844 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 7845 | |
4f8036a2 | 7846 | reg = HAS_PCH_LPT_LP(dev_priv) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
7847 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
7848 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
7849 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
7850 | ||
7851 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
7852 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
7853 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
7854 | tmp |= SBI_SSCCTL_PATHALT; | |
7855 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7856 | udelay(32); | |
7857 | } | |
7858 | tmp |= SBI_SSCCTL_DISABLE; | |
7859 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
7860 | } | |
7861 | ||
a580516d | 7862 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
7863 | } |
7864 | ||
f7be2c21 VS |
7865 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
7866 | ||
7867 | static const uint16_t sscdivintphase[] = { | |
7868 | [BEND_IDX( 50)] = 0x3B23, | |
7869 | [BEND_IDX( 45)] = 0x3B23, | |
7870 | [BEND_IDX( 40)] = 0x3C23, | |
7871 | [BEND_IDX( 35)] = 0x3C23, | |
7872 | [BEND_IDX( 30)] = 0x3D23, | |
7873 | [BEND_IDX( 25)] = 0x3D23, | |
7874 | [BEND_IDX( 20)] = 0x3E23, | |
7875 | [BEND_IDX( 15)] = 0x3E23, | |
7876 | [BEND_IDX( 10)] = 0x3F23, | |
7877 | [BEND_IDX( 5)] = 0x3F23, | |
7878 | [BEND_IDX( 0)] = 0x0025, | |
7879 | [BEND_IDX( -5)] = 0x0025, | |
7880 | [BEND_IDX(-10)] = 0x0125, | |
7881 | [BEND_IDX(-15)] = 0x0125, | |
7882 | [BEND_IDX(-20)] = 0x0225, | |
7883 | [BEND_IDX(-25)] = 0x0225, | |
7884 | [BEND_IDX(-30)] = 0x0325, | |
7885 | [BEND_IDX(-35)] = 0x0325, | |
7886 | [BEND_IDX(-40)] = 0x0425, | |
7887 | [BEND_IDX(-45)] = 0x0425, | |
7888 | [BEND_IDX(-50)] = 0x0525, | |
7889 | }; | |
7890 | ||
7891 | /* | |
7892 | * Bend CLKOUT_DP | |
7893 | * steps -50 to 50 inclusive, in steps of 5 | |
7894 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
7895 | * change in clock period = -(steps / 10) * 5.787 ps | |
7896 | */ | |
7897 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
7898 | { | |
7899 | uint32_t tmp; | |
7900 | int idx = BEND_IDX(steps); | |
7901 | ||
7902 | if (WARN_ON(steps % 5 != 0)) | |
7903 | return; | |
7904 | ||
7905 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
7906 | return; | |
7907 | ||
7908 | mutex_lock(&dev_priv->sb_lock); | |
7909 | ||
7910 | if (steps % 10 != 0) | |
7911 | tmp = 0xAAAAAAAB; | |
7912 | else | |
7913 | tmp = 0x00000000; | |
7914 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
7915 | ||
7916 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
7917 | tmp &= 0xffff0000; | |
7918 | tmp |= sscdivintphase[idx]; | |
7919 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
7920 | ||
7921 | mutex_unlock(&dev_priv->sb_lock); | |
7922 | } | |
7923 | ||
7924 | #undef BEND_IDX | |
7925 | ||
c39055b0 | 7926 | static void lpt_init_pch_refclk(struct drm_i915_private *dev_priv) |
bf8fa3d3 | 7927 | { |
bf8fa3d3 PZ |
7928 | struct intel_encoder *encoder; |
7929 | bool has_vga = false; | |
7930 | ||
c39055b0 | 7931 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
bf8fa3d3 PZ |
7932 | switch (encoder->type) { |
7933 | case INTEL_OUTPUT_ANALOG: | |
7934 | has_vga = true; | |
7935 | break; | |
6847d71b PZ |
7936 | default: |
7937 | break; | |
bf8fa3d3 PZ |
7938 | } |
7939 | } | |
7940 | ||
f7be2c21 | 7941 | if (has_vga) { |
c39055b0 ACO |
7942 | lpt_bend_clkout_dp(dev_priv, 0); |
7943 | lpt_enable_clkout_dp(dev_priv, true, true); | |
f7be2c21 | 7944 | } else { |
c39055b0 | 7945 | lpt_disable_clkout_dp(dev_priv); |
f7be2c21 | 7946 | } |
bf8fa3d3 PZ |
7947 | } |
7948 | ||
dde86e2d PZ |
7949 | /* |
7950 | * Initialize reference clocks when the driver loads | |
7951 | */ | |
c39055b0 | 7952 | void intel_init_pch_refclk(struct drm_i915_private *dev_priv) |
dde86e2d | 7953 | { |
6e266956 | 7954 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) |
c39055b0 | 7955 | ironlake_init_pch_refclk(dev_priv); |
6e266956 | 7956 | else if (HAS_PCH_LPT(dev_priv)) |
c39055b0 | 7957 | lpt_init_pch_refclk(dev_priv); |
dde86e2d PZ |
7958 | } |
7959 | ||
6ff93609 | 7960 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 7961 | { |
fac5e23e | 7962 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
79e53945 JB |
7963 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
7964 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
7965 | uint32_t val; |
7966 | ||
78114071 | 7967 | val = 0; |
c8203565 | 7968 | |
6e3c9717 | 7969 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 7970 | case 18: |
dfd07d72 | 7971 | val |= PIPECONF_6BPC; |
c8203565 PZ |
7972 | break; |
7973 | case 24: | |
dfd07d72 | 7974 | val |= PIPECONF_8BPC; |
c8203565 PZ |
7975 | break; |
7976 | case 30: | |
dfd07d72 | 7977 | val |= PIPECONF_10BPC; |
c8203565 PZ |
7978 | break; |
7979 | case 36: | |
dfd07d72 | 7980 | val |= PIPECONF_12BPC; |
c8203565 PZ |
7981 | break; |
7982 | default: | |
cc769b62 PZ |
7983 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
7984 | BUG(); | |
c8203565 PZ |
7985 | } |
7986 | ||
6e3c9717 | 7987 | if (intel_crtc->config->dither) |
c8203565 PZ |
7988 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
7989 | ||
6e3c9717 | 7990 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
7991 | val |= PIPECONF_INTERLACED_ILK; |
7992 | else | |
7993 | val |= PIPECONF_PROGRESSIVE; | |
7994 | ||
6e3c9717 | 7995 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 7996 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 7997 | |
c8203565 PZ |
7998 | I915_WRITE(PIPECONF(pipe), val); |
7999 | POSTING_READ(PIPECONF(pipe)); | |
8000 | } | |
8001 | ||
6ff93609 | 8002 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8003 | { |
fac5e23e | 8004 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
ee2b0b38 | 8005 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 8006 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
391bf048 | 8007 | u32 val = 0; |
ee2b0b38 | 8008 | |
391bf048 | 8009 | if (IS_HASWELL(dev_priv) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8010 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8011 | ||
6e3c9717 | 8012 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8013 | val |= PIPECONF_INTERLACED_ILK; |
8014 | else | |
8015 | val |= PIPECONF_PROGRESSIVE; | |
8016 | ||
702e7a56 PZ |
8017 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8018 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
391bf048 JN |
8019 | } |
8020 | ||
391bf048 JN |
8021 | static void haswell_set_pipemisc(struct drm_crtc *crtc) |
8022 | { | |
fac5e23e | 8023 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
391bf048 | 8024 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 8025 | |
391bf048 JN |
8026 | if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { |
8027 | u32 val = 0; | |
756f85cf | 8028 | |
6e3c9717 | 8029 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8030 | case 18: |
8031 | val |= PIPEMISC_DITHER_6_BPC; | |
8032 | break; | |
8033 | case 24: | |
8034 | val |= PIPEMISC_DITHER_8_BPC; | |
8035 | break; | |
8036 | case 30: | |
8037 | val |= PIPEMISC_DITHER_10_BPC; | |
8038 | break; | |
8039 | case 36: | |
8040 | val |= PIPEMISC_DITHER_12_BPC; | |
8041 | break; | |
8042 | default: | |
8043 | /* Case prevented by pipe_config_set_bpp. */ | |
8044 | BUG(); | |
8045 | } | |
8046 | ||
6e3c9717 | 8047 | if (intel_crtc->config->dither) |
756f85cf PZ |
8048 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8049 | ||
391bf048 | 8050 | I915_WRITE(PIPEMISC(intel_crtc->pipe), val); |
756f85cf | 8051 | } |
ee2b0b38 PZ |
8052 | } |
8053 | ||
d4b1931c PZ |
8054 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8055 | { | |
8056 | /* | |
8057 | * Account for spread spectrum to avoid | |
8058 | * oversubscribing the link. Max center spread | |
8059 | * is 2.5%; use 5% for safety's sake. | |
8060 | */ | |
8061 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8062 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8063 | } |
8064 | ||
7429e9d4 | 8065 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8066 | { |
7429e9d4 | 8067 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8068 | } |
8069 | ||
b75ca6f6 ACO |
8070 | static void ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
8071 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 8072 | struct dpll *reduced_clock) |
79e53945 | 8073 | { |
de13a2e3 | 8074 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 | 8075 | struct drm_device *dev = crtc->dev; |
fac5e23e | 8076 | struct drm_i915_private *dev_priv = to_i915(dev); |
b75ca6f6 | 8077 | u32 dpll, fp, fp2; |
3d6e9ee0 | 8078 | int factor; |
79e53945 | 8079 | |
c1858123 | 8080 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 | 8081 | factor = 21; |
3d6e9ee0 | 8082 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
8febb297 | 8083 | if ((intel_panel_use_ssc(dev_priv) && |
e91e941b | 8084 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
6e266956 | 8085 | (HAS_PCH_IBX(dev_priv) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8086 | factor = 25; |
190f68c5 | 8087 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8088 | factor = 20; |
c1858123 | 8089 | |
b75ca6f6 ACO |
8090 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
8091 | ||
190f68c5 | 8092 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
b75ca6f6 ACO |
8093 | fp |= FP_CB_TUNE; |
8094 | ||
8095 | if (reduced_clock) { | |
8096 | fp2 = i9xx_dpll_compute_fp(reduced_clock); | |
2c07245f | 8097 | |
b75ca6f6 ACO |
8098 | if (reduced_clock->m < factor * reduced_clock->n) |
8099 | fp2 |= FP_CB_TUNE; | |
8100 | } else { | |
8101 | fp2 = fp; | |
8102 | } | |
9a7c7890 | 8103 | |
5eddb70b | 8104 | dpll = 0; |
2c07245f | 8105 | |
3d6e9ee0 | 8106 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a07d6787 EA |
8107 | dpll |= DPLLB_MODE_LVDS; |
8108 | else | |
8109 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8110 | |
190f68c5 | 8111 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8112 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f | 8113 | |
3d6e9ee0 VS |
8114 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || |
8115 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) | |
4a33e48d | 8116 | dpll |= DPLL_SDVO_HIGH_SPEED; |
3d6e9ee0 | 8117 | |
37a5650b | 8118 | if (intel_crtc_has_dp_encoder(crtc_state)) |
4a33e48d | 8119 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8120 | |
7d7f8633 VS |
8121 | /* |
8122 | * The high speed IO clock is only really required for | |
8123 | * SDVO/HDMI/DP, but we also enable it for CRT to make it | |
8124 | * possible to share the DPLL between CRT and HDMI. Enabling | |
8125 | * the clock needlessly does no real harm, except use up a | |
8126 | * bit of power potentially. | |
8127 | * | |
8128 | * We'll limit this to IVB with 3 pipes, since it has only two | |
8129 | * DPLLs and so DPLL sharing is the only way to get three pipes | |
8130 | * driving PCH ports at the same time. On SNB we could do this, | |
8131 | * and potentially avoid enabling the second DPLL, but it's not | |
8132 | * clear if it''s a win or loss power wise. No point in doing | |
8133 | * this on ILK at all since it has a fixed DPLL<->pipe mapping. | |
8134 | */ | |
8135 | if (INTEL_INFO(dev_priv)->num_pipes == 3 && | |
8136 | intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) | |
8137 | dpll |= DPLL_SDVO_HIGH_SPEED; | |
8138 | ||
a07d6787 | 8139 | /* compute bitmask from p1 value */ |
190f68c5 | 8140 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8141 | /* also FPA1 */ |
190f68c5 | 8142 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8143 | |
190f68c5 | 8144 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8145 | case 5: |
8146 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8147 | break; | |
8148 | case 7: | |
8149 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8150 | break; | |
8151 | case 10: | |
8152 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8153 | break; | |
8154 | case 14: | |
8155 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8156 | break; | |
79e53945 JB |
8157 | } |
8158 | ||
3d6e9ee0 VS |
8159 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
8160 | intel_panel_use_ssc(dev_priv)) | |
43565a06 | 8161 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8162 | else |
8163 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8164 | ||
b75ca6f6 ACO |
8165 | dpll |= DPLL_VCO_ENABLE; |
8166 | ||
8167 | crtc_state->dpll_hw_state.dpll = dpll; | |
8168 | crtc_state->dpll_hw_state.fp0 = fp; | |
8169 | crtc_state->dpll_hw_state.fp1 = fp2; | |
de13a2e3 PZ |
8170 | } |
8171 | ||
190f68c5 ACO |
8172 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8173 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8174 | { |
997c030c | 8175 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 8176 | struct drm_i915_private *dev_priv = to_i915(dev); |
9e2c8475 | 8177 | struct dpll reduced_clock; |
7ed9f894 | 8178 | bool has_reduced_clock = false; |
e2b78267 | 8179 | struct intel_shared_dpll *pll; |
1b6f4958 | 8180 | const struct intel_limit *limit; |
997c030c | 8181 | int refclk = 120000; |
de13a2e3 | 8182 | |
dd3cd74a ACO |
8183 | memset(&crtc_state->dpll_hw_state, 0, |
8184 | sizeof(crtc_state->dpll_hw_state)); | |
8185 | ||
ded220e2 ACO |
8186 | crtc->lowfreq_avail = false; |
8187 | ||
8188 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ | |
8189 | if (!crtc_state->has_pch_encoder) | |
8190 | return 0; | |
79e53945 | 8191 | |
2d84d2b3 | 8192 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
997c030c ACO |
8193 | if (intel_panel_use_ssc(dev_priv)) { |
8194 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", | |
8195 | dev_priv->vbt.lvds_ssc_freq); | |
8196 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8197 | } | |
8198 | ||
8199 | if (intel_is_dual_link_lvds(dev)) { | |
8200 | if (refclk == 100000) | |
8201 | limit = &intel_limits_ironlake_dual_lvds_100m; | |
8202 | else | |
8203 | limit = &intel_limits_ironlake_dual_lvds; | |
8204 | } else { | |
8205 | if (refclk == 100000) | |
8206 | limit = &intel_limits_ironlake_single_lvds_100m; | |
8207 | else | |
8208 | limit = &intel_limits_ironlake_single_lvds; | |
8209 | } | |
8210 | } else { | |
8211 | limit = &intel_limits_ironlake_dac; | |
8212 | } | |
8213 | ||
364ee29d | 8214 | if (!crtc_state->clock_set && |
997c030c ACO |
8215 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
8216 | refclk, NULL, &crtc_state->dpll)) { | |
364ee29d ACO |
8217 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8218 | return -EINVAL; | |
f47709a9 | 8219 | } |
79e53945 | 8220 | |
b75ca6f6 ACO |
8221 | ironlake_compute_dpll(crtc, crtc_state, |
8222 | has_reduced_clock ? &reduced_clock : NULL); | |
66e985c0 | 8223 | |
ded220e2 ACO |
8224 | pll = intel_get_shared_dpll(crtc, crtc_state, NULL); |
8225 | if (pll == NULL) { | |
8226 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
8227 | pipe_name(crtc->pipe)); | |
8228 | return -EINVAL; | |
3fb37703 | 8229 | } |
79e53945 | 8230 | |
2d84d2b3 | 8231 | if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ded220e2 | 8232 | has_reduced_clock) |
c7653199 | 8233 | crtc->lowfreq_avail = true; |
e2b78267 | 8234 | |
c8f7a0db | 8235 | return 0; |
79e53945 JB |
8236 | } |
8237 | ||
eb14cb74 VS |
8238 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
8239 | struct intel_link_m_n *m_n) | |
8240 | { | |
8241 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8242 | struct drm_i915_private *dev_priv = to_i915(dev); |
eb14cb74 VS |
8243 | enum pipe pipe = crtc->pipe; |
8244 | ||
8245 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
8246 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
8247 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8248 | & ~TU_SIZE_MASK; | |
8249 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
8250 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8251 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8252 | } | |
8253 | ||
8254 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
8255 | enum transcoder transcoder, | |
b95af8be VK |
8256 | struct intel_link_m_n *m_n, |
8257 | struct intel_link_m_n *m2_n2) | |
72419203 | 8258 | { |
6315b5d3 | 8259 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
eb14cb74 | 8260 | enum pipe pipe = crtc->pipe; |
72419203 | 8261 | |
6315b5d3 | 8262 | if (INTEL_GEN(dev_priv) >= 5) { |
eb14cb74 VS |
8263 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); |
8264 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
8265 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
8266 | & ~TU_SIZE_MASK; | |
8267 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
8268 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
8269 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
8270 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
8271 | * gen < 8) and if DRRS is supported (to make sure the | |
8272 | * registers are not unnecessarily read). | |
8273 | */ | |
6315b5d3 | 8274 | if (m2_n2 && INTEL_GEN(dev_priv) < 8 && |
6e3c9717 | 8275 | crtc->config->has_drrs) { |
b95af8be VK |
8276 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
8277 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
8278 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
8279 | & ~TU_SIZE_MASK; | |
8280 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
8281 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
8282 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8283 | } | |
eb14cb74 VS |
8284 | } else { |
8285 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
8286 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
8287 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8288 | & ~TU_SIZE_MASK; | |
8289 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
8290 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8291 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8292 | } | |
8293 | } | |
8294 | ||
8295 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 8296 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 8297 | { |
681a8504 | 8298 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
8299 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
8300 | else | |
8301 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
8302 | &pipe_config->dp_m_n, |
8303 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 8304 | } |
72419203 | 8305 | |
eb14cb74 | 8306 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 8307 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
8308 | { |
8309 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 8310 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
8311 | } |
8312 | ||
bd2e244f | 8313 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8314 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
8315 | { |
8316 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8317 | struct drm_i915_private *dev_priv = to_i915(dev); |
a1b2278e CK |
8318 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
8319 | uint32_t ps_ctrl = 0; | |
8320 | int id = -1; | |
8321 | int i; | |
bd2e244f | 8322 | |
a1b2278e CK |
8323 | /* find scaler attached to this pipe */ |
8324 | for (i = 0; i < crtc->num_scalers; i++) { | |
8325 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
8326 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
8327 | id = i; | |
8328 | pipe_config->pch_pfit.enabled = true; | |
8329 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
8330 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
8331 | break; | |
8332 | } | |
8333 | } | |
bd2e244f | 8334 | |
a1b2278e CK |
8335 | scaler_state->scaler_id = id; |
8336 | if (id >= 0) { | |
8337 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
8338 | } else { | |
8339 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
8340 | } |
8341 | } | |
8342 | ||
5724dbd1 DL |
8343 | static void |
8344 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
8345 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
8346 | { |
8347 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8348 | struct drm_i915_private *dev_priv = to_i915(dev); |
40f46283 | 8349 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
8350 | int pipe = crtc->pipe; |
8351 | int fourcc, pixel_format; | |
6761dd31 | 8352 | unsigned int aligned_height; |
bc8d7dff | 8353 | struct drm_framebuffer *fb; |
1b842c89 | 8354 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 8355 | |
d9806c9f | 8356 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8357 | if (!intel_fb) { |
bc8d7dff DL |
8358 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8359 | return; | |
8360 | } | |
8361 | ||
1b842c89 DL |
8362 | fb = &intel_fb->base; |
8363 | ||
d2e9f5fc VS |
8364 | fb->dev = dev; |
8365 | ||
bc8d7dff | 8366 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
8367 | if (!(val & PLANE_CTL_ENABLE)) |
8368 | goto error; | |
8369 | ||
bc8d7dff DL |
8370 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
8371 | fourcc = skl_format_to_fourcc(pixel_format, | |
8372 | val & PLANE_CTL_ORDER_RGBX, | |
8373 | val & PLANE_CTL_ALPHA_MASK); | |
2f3f4763 | 8374 | fb->format = drm_format_info(fourcc); |
bc8d7dff | 8375 | |
40f46283 DL |
8376 | tiling = val & PLANE_CTL_TILED_MASK; |
8377 | switch (tiling) { | |
8378 | case PLANE_CTL_TILED_LINEAR: | |
bae781b2 | 8379 | fb->modifier = DRM_FORMAT_MOD_NONE; |
40f46283 DL |
8380 | break; |
8381 | case PLANE_CTL_TILED_X: | |
8382 | plane_config->tiling = I915_TILING_X; | |
bae781b2 | 8383 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
40f46283 DL |
8384 | break; |
8385 | case PLANE_CTL_TILED_Y: | |
bae781b2 | 8386 | fb->modifier = I915_FORMAT_MOD_Y_TILED; |
40f46283 DL |
8387 | break; |
8388 | case PLANE_CTL_TILED_YF: | |
bae781b2 | 8389 | fb->modifier = I915_FORMAT_MOD_Yf_TILED; |
40f46283 DL |
8390 | break; |
8391 | default: | |
8392 | MISSING_CASE(tiling); | |
8393 | goto error; | |
8394 | } | |
8395 | ||
bc8d7dff DL |
8396 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
8397 | plane_config->base = base; | |
8398 | ||
8399 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
8400 | ||
8401 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
8402 | fb->height = ((val >> 16) & 0xfff) + 1; | |
8403 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
8404 | ||
8405 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
d88c4afd | 8406 | stride_mult = intel_fb_stride_alignment(fb, 0); |
bc8d7dff DL |
8407 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
8408 | ||
d88c4afd | 8409 | aligned_height = intel_fb_align_height(fb, 0, fb->height); |
bc8d7dff | 8410 | |
f37b5c2b | 8411 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
8412 | |
8413 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
8414 | pipe_name(pipe), fb->width, fb->height, | |
272725c7 | 8415 | fb->format->cpp[0] * 8, base, fb->pitches[0], |
bc8d7dff DL |
8416 | plane_config->size); |
8417 | ||
2d14030b | 8418 | plane_config->fb = intel_fb; |
bc8d7dff DL |
8419 | return; |
8420 | ||
8421 | error: | |
d1a3a036 | 8422 | kfree(intel_fb); |
bc8d7dff DL |
8423 | } |
8424 | ||
2fa2fe9a | 8425 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8426 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8427 | { |
8428 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8429 | struct drm_i915_private *dev_priv = to_i915(dev); |
2fa2fe9a DV |
8430 | uint32_t tmp; |
8431 | ||
8432 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
8433 | ||
8434 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 8435 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
8436 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
8437 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
8438 | |
8439 | /* We currently do not free assignements of panel fitters on | |
8440 | * ivb/hsw (since we don't use the higher upscaling modes which | |
8441 | * differentiates them) so just WARN about this case for now. */ | |
5db94019 | 8442 | if (IS_GEN7(dev_priv)) { |
cb8b2a30 DV |
8443 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != |
8444 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
8445 | } | |
2fa2fe9a | 8446 | } |
79e53945 JB |
8447 | } |
8448 | ||
5724dbd1 DL |
8449 | static void |
8450 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
8451 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
8452 | { |
8453 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8454 | struct drm_i915_private *dev_priv = to_i915(dev); |
4c6baa59 | 8455 | u32 val, base, offset; |
aeee5a49 | 8456 | int pipe = crtc->pipe; |
4c6baa59 | 8457 | int fourcc, pixel_format; |
6761dd31 | 8458 | unsigned int aligned_height; |
b113d5ee | 8459 | struct drm_framebuffer *fb; |
1b842c89 | 8460 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 8461 | |
42a7b088 DL |
8462 | val = I915_READ(DSPCNTR(pipe)); |
8463 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8464 | return; | |
8465 | ||
d9806c9f | 8466 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8467 | if (!intel_fb) { |
4c6baa59 JB |
8468 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8469 | return; | |
8470 | } | |
8471 | ||
1b842c89 DL |
8472 | fb = &intel_fb->base; |
8473 | ||
d2e9f5fc VS |
8474 | fb->dev = dev; |
8475 | ||
6315b5d3 | 8476 | if (INTEL_GEN(dev_priv) >= 4) { |
18c5247e | 8477 | if (val & DISPPLANE_TILED) { |
49af449b | 8478 | plane_config->tiling = I915_TILING_X; |
bae781b2 | 8479 | fb->modifier = I915_FORMAT_MOD_X_TILED; |
18c5247e DV |
8480 | } |
8481 | } | |
4c6baa59 JB |
8482 | |
8483 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8484 | fourcc = i9xx_format_to_fourcc(pixel_format); |
2f3f4763 | 8485 | fb->format = drm_format_info(fourcc); |
4c6baa59 | 8486 | |
aeee5a49 | 8487 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
8652744b | 8488 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
aeee5a49 | 8489 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 8490 | } else { |
49af449b | 8491 | if (plane_config->tiling) |
aeee5a49 | 8492 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 8493 | else |
aeee5a49 | 8494 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
8495 | } |
8496 | plane_config->base = base; | |
8497 | ||
8498 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8499 | fb->width = ((val >> 16) & 0xfff) + 1; |
8500 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
8501 | |
8502 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8503 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 8504 | |
d88c4afd | 8505 | aligned_height = intel_fb_align_height(fb, 0, fb->height); |
4c6baa59 | 8506 | |
f37b5c2b | 8507 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 8508 | |
2844a921 DL |
8509 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8510 | pipe_name(pipe), fb->width, fb->height, | |
272725c7 | 8511 | fb->format->cpp[0] * 8, base, fb->pitches[0], |
2844a921 | 8512 | plane_config->size); |
b113d5ee | 8513 | |
2d14030b | 8514 | plane_config->fb = intel_fb; |
4c6baa59 JB |
8515 | } |
8516 | ||
0e8ffe1b | 8517 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8518 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8519 | { |
8520 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8521 | struct drm_i915_private *dev_priv = to_i915(dev); |
1729050e | 8522 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 8523 | uint32_t tmp; |
1729050e | 8524 | bool ret; |
0e8ffe1b | 8525 | |
1729050e ID |
8526 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8527 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
930e8c9e PZ |
8528 | return false; |
8529 | ||
e143a21c | 8530 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 8531 | pipe_config->shared_dpll = NULL; |
eccb140b | 8532 | |
1729050e | 8533 | ret = false; |
0e8ffe1b DV |
8534 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8535 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 8536 | goto out; |
0e8ffe1b | 8537 | |
42571aef VS |
8538 | switch (tmp & PIPECONF_BPC_MASK) { |
8539 | case PIPECONF_6BPC: | |
8540 | pipe_config->pipe_bpp = 18; | |
8541 | break; | |
8542 | case PIPECONF_8BPC: | |
8543 | pipe_config->pipe_bpp = 24; | |
8544 | break; | |
8545 | case PIPECONF_10BPC: | |
8546 | pipe_config->pipe_bpp = 30; | |
8547 | break; | |
8548 | case PIPECONF_12BPC: | |
8549 | pipe_config->pipe_bpp = 36; | |
8550 | break; | |
8551 | default: | |
8552 | break; | |
8553 | } | |
8554 | ||
b5a9fa09 DV |
8555 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
8556 | pipe_config->limited_color_range = true; | |
8557 | ||
ab9412ba | 8558 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 | 8559 | struct intel_shared_dpll *pll; |
8106ddbd | 8560 | enum intel_dpll_id pll_id; |
66e985c0 | 8561 | |
88adfff1 DV |
8562 | pipe_config->has_pch_encoder = true; |
8563 | ||
627eb5a3 DV |
8564 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
8565 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
8566 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
8567 | |
8568 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 8569 | |
2d1fe073 | 8570 | if (HAS_PCH_IBX(dev_priv)) { |
d9a7bc67 ID |
8571 | /* |
8572 | * The pipe->pch transcoder and pch transcoder->pll | |
8573 | * mapping is fixed. | |
8574 | */ | |
8106ddbd | 8575 | pll_id = (enum intel_dpll_id) crtc->pipe; |
c0d43d62 DV |
8576 | } else { |
8577 | tmp = I915_READ(PCH_DPLL_SEL); | |
8578 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8106ddbd | 8579 | pll_id = DPLL_ID_PCH_PLL_B; |
c0d43d62 | 8580 | else |
8106ddbd | 8581 | pll_id= DPLL_ID_PCH_PLL_A; |
c0d43d62 | 8582 | } |
66e985c0 | 8583 | |
8106ddbd ACO |
8584 | pipe_config->shared_dpll = |
8585 | intel_get_shared_dpll_by_id(dev_priv, pll_id); | |
8586 | pll = pipe_config->shared_dpll; | |
66e985c0 | 8587 | |
2edd6443 ACO |
8588 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
8589 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
8590 | |
8591 | tmp = pipe_config->dpll_hw_state.dpll; | |
8592 | pipe_config->pixel_multiplier = | |
8593 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
8594 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
8595 | |
8596 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
8597 | } else { |
8598 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
8599 | } |
8600 | ||
1bd1bd80 | 8601 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 8602 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 8603 | |
2fa2fe9a DV |
8604 | ironlake_get_pfit_config(crtc, pipe_config); |
8605 | ||
1729050e ID |
8606 | ret = true; |
8607 | ||
8608 | out: | |
8609 | intel_display_power_put(dev_priv, power_domain); | |
8610 | ||
8611 | return ret; | |
0e8ffe1b DV |
8612 | } |
8613 | ||
be256dc7 PZ |
8614 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
8615 | { | |
91c8a326 | 8616 | struct drm_device *dev = &dev_priv->drm; |
be256dc7 | 8617 | struct intel_crtc *crtc; |
be256dc7 | 8618 | |
d3fcc808 | 8619 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 8620 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
8621 | pipe_name(crtc->pipe)); |
8622 | ||
e2c719b7 RC |
8623 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
8624 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
8625 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
8626 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
44cb734c | 8627 | I915_STATE_WARN(I915_READ(PP_STATUS(0)) & PP_ON, "Panel power on\n"); |
e2c719b7 | 8628 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, |
be256dc7 | 8629 | "CPU PWM1 enabled\n"); |
772c2a51 | 8630 | if (IS_HASWELL(dev_priv)) |
e2c719b7 | 8631 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 8632 | "CPU PWM2 enabled\n"); |
e2c719b7 | 8633 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 8634 | "PCH PWM1 enabled\n"); |
e2c719b7 | 8635 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 8636 | "Utility pin enabled\n"); |
e2c719b7 | 8637 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 8638 | |
9926ada1 PZ |
8639 | /* |
8640 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
8641 | * interrupts remain enabled. We used to check for that, but since it's | |
8642 | * gen-specific and since we only disable LCPLL after we fully disable | |
8643 | * the interrupts, the check below should be enough. | |
8644 | */ | |
e2c719b7 | 8645 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
8646 | } |
8647 | ||
9ccd5aeb PZ |
8648 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
8649 | { | |
772c2a51 | 8650 | if (IS_HASWELL(dev_priv)) |
9ccd5aeb PZ |
8651 | return I915_READ(D_COMP_HSW); |
8652 | else | |
8653 | return I915_READ(D_COMP_BDW); | |
8654 | } | |
8655 | ||
3c4c9b81 PZ |
8656 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
8657 | { | |
772c2a51 | 8658 | if (IS_HASWELL(dev_priv)) { |
3c4c9b81 PZ |
8659 | mutex_lock(&dev_priv->rps.hw_lock); |
8660 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
8661 | val)) | |
79cf219a | 8662 | DRM_DEBUG_KMS("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
8663 | mutex_unlock(&dev_priv->rps.hw_lock); |
8664 | } else { | |
9ccd5aeb PZ |
8665 | I915_WRITE(D_COMP_BDW, val); |
8666 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 8667 | } |
be256dc7 PZ |
8668 | } |
8669 | ||
8670 | /* | |
8671 | * This function implements pieces of two sequences from BSpec: | |
8672 | * - Sequence for display software to disable LCPLL | |
8673 | * - Sequence for display software to allow package C8+ | |
8674 | * The steps implemented here are just the steps that actually touch the LCPLL | |
8675 | * register. Callers should take care of disabling all the display engine | |
8676 | * functions, doing the mode unset, fixing interrupts, etc. | |
8677 | */ | |
6ff58d53 PZ |
8678 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
8679 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
8680 | { |
8681 | uint32_t val; | |
8682 | ||
8683 | assert_can_disable_lcpll(dev_priv); | |
8684 | ||
8685 | val = I915_READ(LCPLL_CTL); | |
8686 | ||
8687 | if (switch_to_fclk) { | |
8688 | val |= LCPLL_CD_SOURCE_FCLK; | |
8689 | I915_WRITE(LCPLL_CTL, val); | |
8690 | ||
f53dd63f ID |
8691 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
8692 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
be256dc7 PZ |
8693 | DRM_ERROR("Switching to FCLK failed\n"); |
8694 | ||
8695 | val = I915_READ(LCPLL_CTL); | |
8696 | } | |
8697 | ||
8698 | val |= LCPLL_PLL_DISABLE; | |
8699 | I915_WRITE(LCPLL_CTL, val); | |
8700 | POSTING_READ(LCPLL_CTL); | |
8701 | ||
24d8441d | 8702 | if (intel_wait_for_register(dev_priv, LCPLL_CTL, LCPLL_PLL_LOCK, 0, 1)) |
be256dc7 PZ |
8703 | DRM_ERROR("LCPLL still locked\n"); |
8704 | ||
9ccd5aeb | 8705 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 8706 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 8707 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8708 | ndelay(100); |
8709 | ||
9ccd5aeb PZ |
8710 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
8711 | 1)) | |
be256dc7 PZ |
8712 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
8713 | ||
8714 | if (allow_power_down) { | |
8715 | val = I915_READ(LCPLL_CTL); | |
8716 | val |= LCPLL_POWER_DOWN_ALLOW; | |
8717 | I915_WRITE(LCPLL_CTL, val); | |
8718 | POSTING_READ(LCPLL_CTL); | |
8719 | } | |
8720 | } | |
8721 | ||
8722 | /* | |
8723 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
8724 | * source. | |
8725 | */ | |
6ff58d53 | 8726 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
8727 | { |
8728 | uint32_t val; | |
8729 | ||
8730 | val = I915_READ(LCPLL_CTL); | |
8731 | ||
8732 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
8733 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
8734 | return; | |
8735 | ||
a8a8bd54 PZ |
8736 | /* |
8737 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
8738 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 8739 | */ |
59bad947 | 8740 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 8741 | |
be256dc7 PZ |
8742 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
8743 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
8744 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 8745 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
8746 | } |
8747 | ||
9ccd5aeb | 8748 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
8749 | val |= D_COMP_COMP_FORCE; |
8750 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 8751 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
8752 | |
8753 | val = I915_READ(LCPLL_CTL); | |
8754 | val &= ~LCPLL_PLL_DISABLE; | |
8755 | I915_WRITE(LCPLL_CTL, val); | |
8756 | ||
93220c08 CW |
8757 | if (intel_wait_for_register(dev_priv, |
8758 | LCPLL_CTL, LCPLL_PLL_LOCK, LCPLL_PLL_LOCK, | |
8759 | 5)) | |
be256dc7 PZ |
8760 | DRM_ERROR("LCPLL not locked yet\n"); |
8761 | ||
8762 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
8763 | val = I915_READ(LCPLL_CTL); | |
8764 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
8765 | I915_WRITE(LCPLL_CTL, val); | |
8766 | ||
f53dd63f ID |
8767 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
8768 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
be256dc7 PZ |
8769 | DRM_ERROR("Switching back to LCPLL failed\n"); |
8770 | } | |
215733fa | 8771 | |
59bad947 | 8772 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
4c75b940 | 8773 | intel_update_cdclk(dev_priv); |
be256dc7 PZ |
8774 | } |
8775 | ||
765dab67 PZ |
8776 | /* |
8777 | * Package states C8 and deeper are really deep PC states that can only be | |
8778 | * reached when all the devices on the system allow it, so even if the graphics | |
8779 | * device allows PC8+, it doesn't mean the system will actually get to these | |
8780 | * states. Our driver only allows PC8+ when going into runtime PM. | |
8781 | * | |
8782 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
8783 | * well is disabled and most interrupts are disabled, and these are also | |
8784 | * requirements for runtime PM. When these conditions are met, we manually do | |
8785 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
8786 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
8787 | * hang the machine. | |
8788 | * | |
8789 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
8790 | * the state of some registers, so when we come back from PC8+ we need to | |
8791 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
8792 | * need to take care of the registers kept by RC6. Notice that this happens even | |
8793 | * if we don't put the device in PCI D3 state (which is what currently happens | |
8794 | * because of the runtime PM support). | |
8795 | * | |
8796 | * For more, read "Display Sequences for Package C8" on the hardware | |
8797 | * documentation. | |
8798 | */ | |
a14cb6fc | 8799 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 8800 | { |
c67a470b PZ |
8801 | uint32_t val; |
8802 | ||
c67a470b PZ |
8803 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
8804 | ||
4f8036a2 | 8805 | if (HAS_PCH_LPT_LP(dev_priv)) { |
c67a470b PZ |
8806 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
8807 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
8808 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8809 | } | |
8810 | ||
c39055b0 | 8811 | lpt_disable_clkout_dp(dev_priv); |
c67a470b PZ |
8812 | hsw_disable_lcpll(dev_priv, true, true); |
8813 | } | |
8814 | ||
a14cb6fc | 8815 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 8816 | { |
c67a470b PZ |
8817 | uint32_t val; |
8818 | ||
c67a470b PZ |
8819 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
8820 | ||
8821 | hsw_restore_lcpll(dev_priv); | |
c39055b0 | 8822 | lpt_init_pch_refclk(dev_priv); |
c67a470b | 8823 | |
4f8036a2 | 8824 | if (HAS_PCH_LPT_LP(dev_priv)) { |
c67a470b PZ |
8825 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
8826 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
8827 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8828 | } | |
c67a470b PZ |
8829 | } |
8830 | ||
190f68c5 ACO |
8831 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
8832 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 8833 | { |
d7edc4e5 | 8834 | if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) { |
af3997b5 MK |
8835 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
8836 | return -EINVAL; | |
8837 | } | |
716c2e55 | 8838 | |
c7653199 | 8839 | crtc->lowfreq_avail = false; |
644cef34 | 8840 | |
c8f7a0db | 8841 | return 0; |
79e53945 JB |
8842 | } |
8843 | ||
3760b59c S |
8844 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
8845 | enum port port, | |
8846 | struct intel_crtc_state *pipe_config) | |
8847 | { | |
8106ddbd ACO |
8848 | enum intel_dpll_id id; |
8849 | ||
3760b59c S |
8850 | switch (port) { |
8851 | case PORT_A: | |
08250c4b | 8852 | id = DPLL_ID_SKL_DPLL0; |
3760b59c S |
8853 | break; |
8854 | case PORT_B: | |
08250c4b | 8855 | id = DPLL_ID_SKL_DPLL1; |
3760b59c S |
8856 | break; |
8857 | case PORT_C: | |
08250c4b | 8858 | id = DPLL_ID_SKL_DPLL2; |
3760b59c S |
8859 | break; |
8860 | default: | |
8861 | DRM_ERROR("Incorrect port type\n"); | |
8106ddbd | 8862 | return; |
3760b59c | 8863 | } |
8106ddbd ACO |
8864 | |
8865 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
3760b59c S |
8866 | } |
8867 | ||
96b7dfb7 S |
8868 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
8869 | enum port port, | |
5cec258b | 8870 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 8871 | { |
8106ddbd | 8872 | enum intel_dpll_id id; |
a3c988ea | 8873 | u32 temp; |
96b7dfb7 S |
8874 | |
8875 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
c856052a | 8876 | id = temp >> (port * 3 + 1); |
96b7dfb7 | 8877 | |
c856052a | 8878 | if (WARN_ON(id < SKL_DPLL0 || id > SKL_DPLL3)) |
8106ddbd | 8879 | return; |
8106ddbd ACO |
8880 | |
8881 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
96b7dfb7 S |
8882 | } |
8883 | ||
7d2c8175 DL |
8884 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
8885 | enum port port, | |
5cec258b | 8886 | struct intel_crtc_state *pipe_config) |
7d2c8175 | 8887 | { |
8106ddbd | 8888 | enum intel_dpll_id id; |
c856052a | 8889 | uint32_t ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
8106ddbd | 8890 | |
c856052a | 8891 | switch (ddi_pll_sel) { |
7d2c8175 | 8892 | case PORT_CLK_SEL_WRPLL1: |
8106ddbd | 8893 | id = DPLL_ID_WRPLL1; |
7d2c8175 DL |
8894 | break; |
8895 | case PORT_CLK_SEL_WRPLL2: | |
8106ddbd | 8896 | id = DPLL_ID_WRPLL2; |
7d2c8175 | 8897 | break; |
00490c22 | 8898 | case PORT_CLK_SEL_SPLL: |
8106ddbd | 8899 | id = DPLL_ID_SPLL; |
79bd23da | 8900 | break; |
9d16da65 ACO |
8901 | case PORT_CLK_SEL_LCPLL_810: |
8902 | id = DPLL_ID_LCPLL_810; | |
8903 | break; | |
8904 | case PORT_CLK_SEL_LCPLL_1350: | |
8905 | id = DPLL_ID_LCPLL_1350; | |
8906 | break; | |
8907 | case PORT_CLK_SEL_LCPLL_2700: | |
8908 | id = DPLL_ID_LCPLL_2700; | |
8909 | break; | |
8106ddbd | 8910 | default: |
c856052a | 8911 | MISSING_CASE(ddi_pll_sel); |
8106ddbd ACO |
8912 | /* fall through */ |
8913 | case PORT_CLK_SEL_NONE: | |
8106ddbd | 8914 | return; |
7d2c8175 | 8915 | } |
8106ddbd ACO |
8916 | |
8917 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
7d2c8175 DL |
8918 | } |
8919 | ||
cf30429e JN |
8920 | static bool hsw_get_transcoder_state(struct intel_crtc *crtc, |
8921 | struct intel_crtc_state *pipe_config, | |
d8fc70b7 | 8922 | u64 *power_domain_mask) |
cf30429e JN |
8923 | { |
8924 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8925 | struct drm_i915_private *dev_priv = to_i915(dev); |
cf30429e JN |
8926 | enum intel_display_power_domain power_domain; |
8927 | u32 tmp; | |
8928 | ||
d9a7bc67 ID |
8929 | /* |
8930 | * The pipe->transcoder mapping is fixed with the exception of the eDP | |
8931 | * transcoder handled below. | |
8932 | */ | |
cf30429e JN |
8933 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8934 | ||
8935 | /* | |
8936 | * XXX: Do intel_display_power_get_if_enabled before reading this (for | |
8937 | * consistency and less surprising code; it's in always on power). | |
8938 | */ | |
8939 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
8940 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
8941 | enum pipe trans_edp_pipe; | |
8942 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
8943 | default: | |
8944 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
8945 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
8946 | case TRANS_DDI_EDP_INPUT_A_ON: | |
8947 | trans_edp_pipe = PIPE_A; | |
8948 | break; | |
8949 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
8950 | trans_edp_pipe = PIPE_B; | |
8951 | break; | |
8952 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
8953 | trans_edp_pipe = PIPE_C; | |
8954 | break; | |
8955 | } | |
8956 | ||
8957 | if (trans_edp_pipe == crtc->pipe) | |
8958 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
8959 | } | |
8960 | ||
8961 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); | |
8962 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
8963 | return false; | |
d8fc70b7 | 8964 | *power_domain_mask |= BIT_ULL(power_domain); |
cf30429e JN |
8965 | |
8966 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); | |
8967 | ||
8968 | return tmp & PIPECONF_ENABLE; | |
8969 | } | |
8970 | ||
4d1de975 JN |
8971 | static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, |
8972 | struct intel_crtc_state *pipe_config, | |
d8fc70b7 | 8973 | u64 *power_domain_mask) |
4d1de975 JN |
8974 | { |
8975 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 8976 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 JN |
8977 | enum intel_display_power_domain power_domain; |
8978 | enum port port; | |
8979 | enum transcoder cpu_transcoder; | |
8980 | u32 tmp; | |
8981 | ||
4d1de975 JN |
8982 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { |
8983 | if (port == PORT_A) | |
8984 | cpu_transcoder = TRANSCODER_DSI_A; | |
8985 | else | |
8986 | cpu_transcoder = TRANSCODER_DSI_C; | |
8987 | ||
8988 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
8989 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
8990 | continue; | |
d8fc70b7 | 8991 | *power_domain_mask |= BIT_ULL(power_domain); |
4d1de975 | 8992 | |
db18b6a6 ID |
8993 | /* |
8994 | * The PLL needs to be enabled with a valid divider | |
8995 | * configuration, otherwise accessing DSI registers will hang | |
8996 | * the machine. See BSpec North Display Engine | |
8997 | * registers/MIPI[BXT]. We can break out here early, since we | |
8998 | * need the same DSI PLL to be enabled for both DSI ports. | |
8999 | */ | |
9000 | if (!intel_dsi_pll_is_enabled(dev_priv)) | |
9001 | break; | |
9002 | ||
4d1de975 JN |
9003 | /* XXX: this works for video mode only */ |
9004 | tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
9005 | if (!(tmp & DPI_ENABLE)) | |
9006 | continue; | |
9007 | ||
9008 | tmp = I915_READ(MIPI_CTRL(port)); | |
9009 | if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) | |
9010 | continue; | |
9011 | ||
9012 | pipe_config->cpu_transcoder = cpu_transcoder; | |
4d1de975 JN |
9013 | break; |
9014 | } | |
9015 | ||
d7edc4e5 | 9016 | return transcoder_is_dsi(pipe_config->cpu_transcoder); |
4d1de975 JN |
9017 | } |
9018 | ||
26804afd | 9019 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9020 | struct intel_crtc_state *pipe_config) |
26804afd | 9021 | { |
6315b5d3 | 9022 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
d452c5b6 | 9023 | struct intel_shared_dpll *pll; |
26804afd DV |
9024 | enum port port; |
9025 | uint32_t tmp; | |
9026 | ||
9027 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9028 | ||
9029 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9030 | ||
b976dc53 | 9031 | if (IS_GEN9_BC(dev_priv)) |
96b7dfb7 | 9032 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
cc3f90f0 | 9033 | else if (IS_GEN9_LP(dev_priv)) |
3760b59c | 9034 | bxt_get_ddi_pll(dev_priv, port, pipe_config); |
96b7dfb7 S |
9035 | else |
9036 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9037 | |
8106ddbd ACO |
9038 | pll = pipe_config->shared_dpll; |
9039 | if (pll) { | |
2edd6443 ACO |
9040 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
9041 | &pipe_config->dpll_hw_state)); | |
d452c5b6 DV |
9042 | } |
9043 | ||
26804afd DV |
9044 | /* |
9045 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9046 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9047 | * the PCH transcoder is on. | |
9048 | */ | |
6315b5d3 | 9049 | if (INTEL_GEN(dev_priv) < 9 && |
ca370455 | 9050 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { |
26804afd DV |
9051 | pipe_config->has_pch_encoder = true; |
9052 | ||
9053 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9054 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9055 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9056 | ||
9057 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9058 | } | |
9059 | } | |
9060 | ||
0e8ffe1b | 9061 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9062 | struct intel_crtc_state *pipe_config) |
0e8ffe1b | 9063 | { |
6315b5d3 | 9064 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1729050e | 9065 | enum intel_display_power_domain power_domain; |
d8fc70b7 | 9066 | u64 power_domain_mask; |
cf30429e | 9067 | bool active; |
0e8ffe1b | 9068 | |
1729050e ID |
9069 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9070 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 | 9071 | return false; |
d8fc70b7 | 9072 | power_domain_mask = BIT_ULL(power_domain); |
1729050e | 9073 | |
8106ddbd | 9074 | pipe_config->shared_dpll = NULL; |
c0d43d62 | 9075 | |
cf30429e | 9076 | active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); |
eccb140b | 9077 | |
cc3f90f0 | 9078 | if (IS_GEN9_LP(dev_priv) && |
d7edc4e5 VS |
9079 | bxt_get_dsi_transcoder_state(crtc, pipe_config, &power_domain_mask)) { |
9080 | WARN_ON(active); | |
9081 | active = true; | |
4d1de975 JN |
9082 | } |
9083 | ||
cf30429e | 9084 | if (!active) |
1729050e | 9085 | goto out; |
0e8ffe1b | 9086 | |
d7edc4e5 | 9087 | if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) { |
4d1de975 JN |
9088 | haswell_get_ddi_port_state(crtc, pipe_config); |
9089 | intel_get_pipe_timings(crtc, pipe_config); | |
9090 | } | |
627eb5a3 | 9091 | |
bc58be60 | 9092 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 9093 | |
05dc698c LL |
9094 | pipe_config->gamma_mode = |
9095 | I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; | |
9096 | ||
6315b5d3 | 9097 | if (INTEL_GEN(dev_priv) >= 9) { |
1c74eeaf | 9098 | intel_crtc_init_scalers(crtc, pipe_config); |
a1b2278e | 9099 | |
af99ceda CK |
9100 | pipe_config->scaler_state.scaler_id = -1; |
9101 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
9102 | } | |
9103 | ||
1729050e ID |
9104 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
9105 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
d8fc70b7 | 9106 | power_domain_mask |= BIT_ULL(power_domain); |
6315b5d3 | 9107 | if (INTEL_GEN(dev_priv) >= 9) |
bd2e244f | 9108 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 9109 | else |
1c132b44 | 9110 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 9111 | } |
88adfff1 | 9112 | |
772c2a51 | 9113 | if (IS_HASWELL(dev_priv)) |
e59150dc JB |
9114 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && |
9115 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 9116 | |
4d1de975 JN |
9117 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && |
9118 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { | |
ebb69c95 CT |
9119 | pipe_config->pixel_multiplier = |
9120 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
9121 | } else { | |
9122 | pipe_config->pixel_multiplier = 1; | |
9123 | } | |
6c49f241 | 9124 | |
1729050e ID |
9125 | out: |
9126 | for_each_power_domain(power_domain, power_domain_mask) | |
9127 | intel_display_power_put(dev_priv, power_domain); | |
9128 | ||
cf30429e | 9129 | return active; |
0e8ffe1b DV |
9130 | } |
9131 | ||
55a08b3f ML |
9132 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, |
9133 | const struct intel_plane_state *plane_state) | |
560b85bb CW |
9134 | { |
9135 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 9136 | struct drm_i915_private *dev_priv = to_i915(dev); |
560b85bb | 9137 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
dc41c154 | 9138 | uint32_t cntl = 0, size = 0; |
560b85bb | 9139 | |
936e71e3 | 9140 | if (plane_state && plane_state->base.visible) { |
55a08b3f ML |
9141 | unsigned int width = plane_state->base.crtc_w; |
9142 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 VS |
9143 | unsigned int stride = roundup_pow_of_two(width) * 4; |
9144 | ||
9145 | switch (stride) { | |
9146 | default: | |
9147 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
9148 | width, stride); | |
9149 | stride = 256; | |
9150 | /* fallthrough */ | |
9151 | case 256: | |
9152 | case 512: | |
9153 | case 1024: | |
9154 | case 2048: | |
9155 | break; | |
4b0e333e CW |
9156 | } |
9157 | ||
dc41c154 VS |
9158 | cntl |= CURSOR_ENABLE | |
9159 | CURSOR_GAMMA_ENABLE | | |
9160 | CURSOR_FORMAT_ARGB | | |
9161 | CURSOR_STRIDE(stride); | |
9162 | ||
9163 | size = (height << 12) | width; | |
4b0e333e | 9164 | } |
560b85bb | 9165 | |
dc41c154 VS |
9166 | if (intel_crtc->cursor_cntl != 0 && |
9167 | (intel_crtc->cursor_base != base || | |
9168 | intel_crtc->cursor_size != size || | |
9169 | intel_crtc->cursor_cntl != cntl)) { | |
9170 | /* On these chipsets we can only modify the base/size/stride | |
9171 | * whilst the cursor is disabled. | |
9172 | */ | |
0b87c24e VS |
9173 | I915_WRITE(CURCNTR(PIPE_A), 0); |
9174 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 9175 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 9176 | } |
560b85bb | 9177 | |
99d1f387 | 9178 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 9179 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
9180 | intel_crtc->cursor_base = base; |
9181 | } | |
4726e0b0 | 9182 | |
dc41c154 VS |
9183 | if (intel_crtc->cursor_size != size) { |
9184 | I915_WRITE(CURSIZE, size); | |
9185 | intel_crtc->cursor_size = size; | |
4b0e333e | 9186 | } |
560b85bb | 9187 | |
4b0e333e | 9188 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
9189 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
9190 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 9191 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 9192 | } |
560b85bb CW |
9193 | } |
9194 | ||
55a08b3f ML |
9195 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, |
9196 | const struct intel_plane_state *plane_state) | |
65a21cd6 JB |
9197 | { |
9198 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 9199 | struct drm_i915_private *dev_priv = to_i915(dev); |
65a21cd6 JB |
9200 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9201 | int pipe = intel_crtc->pipe; | |
663f3122 | 9202 | uint32_t cntl = 0; |
4b0e333e | 9203 | |
936e71e3 | 9204 | if (plane_state && plane_state->base.visible) { |
4b0e333e | 9205 | cntl = MCURSOR_GAMMA_ENABLE; |
55a08b3f | 9206 | switch (plane_state->base.crtc_w) { |
4726e0b0 SK |
9207 | case 64: |
9208 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
9209 | break; | |
9210 | case 128: | |
9211 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
9212 | break; | |
9213 | case 256: | |
9214 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
9215 | break; | |
9216 | default: | |
55a08b3f | 9217 | MISSING_CASE(plane_state->base.crtc_w); |
4726e0b0 | 9218 | return; |
65a21cd6 | 9219 | } |
4b0e333e | 9220 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 9221 | |
4f8036a2 | 9222 | if (HAS_DDI(dev_priv)) |
47bf17a7 | 9223 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
65a21cd6 | 9224 | |
f22aa143 | 9225 | if (plane_state->base.rotation & DRM_ROTATE_180) |
55a08b3f ML |
9226 | cntl |= CURSOR_ROTATE_180; |
9227 | } | |
4398ad45 | 9228 | |
4b0e333e CW |
9229 | if (intel_crtc->cursor_cntl != cntl) { |
9230 | I915_WRITE(CURCNTR(pipe), cntl); | |
9231 | POSTING_READ(CURCNTR(pipe)); | |
9232 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 9233 | } |
4b0e333e | 9234 | |
65a21cd6 | 9235 | /* and commit changes on next vblank */ |
5efb3e28 VS |
9236 | I915_WRITE(CURBASE(pipe), base); |
9237 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
9238 | |
9239 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
9240 | } |
9241 | ||
cda4b7d3 | 9242 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f | 9243 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
55a08b3f | 9244 | const struct intel_plane_state *plane_state) |
cda4b7d3 CW |
9245 | { |
9246 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 9247 | struct drm_i915_private *dev_priv = to_i915(dev); |
cda4b7d3 CW |
9248 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9249 | int pipe = intel_crtc->pipe; | |
55a08b3f ML |
9250 | u32 base = intel_crtc->cursor_addr; |
9251 | u32 pos = 0; | |
cda4b7d3 | 9252 | |
55a08b3f ML |
9253 | if (plane_state) { |
9254 | int x = plane_state->base.crtc_x; | |
9255 | int y = plane_state->base.crtc_y; | |
cda4b7d3 | 9256 | |
55a08b3f ML |
9257 | if (x < 0) { |
9258 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
9259 | x = -x; | |
9260 | } | |
9261 | pos |= x << CURSOR_X_SHIFT; | |
cda4b7d3 | 9262 | |
55a08b3f ML |
9263 | if (y < 0) { |
9264 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
9265 | y = -y; | |
9266 | } | |
9267 | pos |= y << CURSOR_Y_SHIFT; | |
9268 | ||
9269 | /* ILK+ do this automagically */ | |
49cff963 | 9270 | if (HAS_GMCH_DISPLAY(dev_priv) && |
f22aa143 | 9271 | plane_state->base.rotation & DRM_ROTATE_180) { |
55a08b3f ML |
9272 | base += (plane_state->base.crtc_h * |
9273 | plane_state->base.crtc_w - 1) * 4; | |
9274 | } | |
cda4b7d3 | 9275 | } |
cda4b7d3 | 9276 | |
5efb3e28 VS |
9277 | I915_WRITE(CURPOS(pipe), pos); |
9278 | ||
2a307c2e | 9279 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) |
55a08b3f | 9280 | i845_update_cursor(crtc, base, plane_state); |
5efb3e28 | 9281 | else |
55a08b3f | 9282 | i9xx_update_cursor(crtc, base, plane_state); |
cda4b7d3 CW |
9283 | } |
9284 | ||
50a0bc90 | 9285 | static bool cursor_size_ok(struct drm_i915_private *dev_priv, |
dc41c154 VS |
9286 | uint32_t width, uint32_t height) |
9287 | { | |
9288 | if (width == 0 || height == 0) | |
9289 | return false; | |
9290 | ||
9291 | /* | |
9292 | * 845g/865g are special in that they are only limited by | |
9293 | * the width of their cursors, the height is arbitrary up to | |
9294 | * the precision of the register. Everything else requires | |
9295 | * square cursors, limited to a few power-of-two sizes. | |
9296 | */ | |
2a307c2e | 9297 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { |
dc41c154 VS |
9298 | if ((width & 63) != 0) |
9299 | return false; | |
9300 | ||
2a307c2e | 9301 | if (width > (IS_I845G(dev_priv) ? 64 : 512)) |
dc41c154 VS |
9302 | return false; |
9303 | ||
9304 | if (height > 1023) | |
9305 | return false; | |
9306 | } else { | |
9307 | switch (width | height) { | |
9308 | case 256: | |
9309 | case 128: | |
50a0bc90 | 9310 | if (IS_GEN2(dev_priv)) |
dc41c154 VS |
9311 | return false; |
9312 | case 64: | |
9313 | break; | |
9314 | default: | |
9315 | return false; | |
9316 | } | |
9317 | } | |
9318 | ||
9319 | return true; | |
9320 | } | |
9321 | ||
79e53945 JB |
9322 | /* VESA 640x480x72Hz mode to set on the pipe */ |
9323 | static struct drm_display_mode load_detect_mode = { | |
9324 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
9325 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
9326 | }; | |
9327 | ||
a8bb6818 | 9328 | struct drm_framebuffer * |
24dbf51a CW |
9329 | intel_framebuffer_create(struct drm_i915_gem_object *obj, |
9330 | struct drm_mode_fb_cmd2 *mode_cmd) | |
d2dff872 CW |
9331 | { |
9332 | struct intel_framebuffer *intel_fb; | |
9333 | int ret; | |
9334 | ||
9335 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 9336 | if (!intel_fb) |
d2dff872 | 9337 | return ERR_PTR(-ENOMEM); |
d2dff872 | 9338 | |
24dbf51a | 9339 | ret = intel_framebuffer_init(intel_fb, obj, mode_cmd); |
dd4916c5 DV |
9340 | if (ret) |
9341 | goto err; | |
d2dff872 CW |
9342 | |
9343 | return &intel_fb->base; | |
dcb1394e | 9344 | |
dd4916c5 | 9345 | err: |
dd4916c5 | 9346 | kfree(intel_fb); |
dd4916c5 | 9347 | return ERR_PTR(ret); |
d2dff872 CW |
9348 | } |
9349 | ||
9350 | static u32 | |
9351 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
9352 | { | |
9353 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
9354 | return ALIGN(pitch, 64); | |
9355 | } | |
9356 | ||
9357 | static u32 | |
9358 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
9359 | { | |
9360 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 9361 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
9362 | } |
9363 | ||
9364 | static struct drm_framebuffer * | |
9365 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
9366 | struct drm_display_mode *mode, | |
9367 | int depth, int bpp) | |
9368 | { | |
dcb1394e | 9369 | struct drm_framebuffer *fb; |
d2dff872 | 9370 | struct drm_i915_gem_object *obj; |
0fed39bd | 9371 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 | 9372 | |
12d79d78 | 9373 | obj = i915_gem_object_create(to_i915(dev), |
d2dff872 | 9374 | intel_framebuffer_size_for_mode(mode, bpp)); |
fe3db79b CW |
9375 | if (IS_ERR(obj)) |
9376 | return ERR_CAST(obj); | |
d2dff872 CW |
9377 | |
9378 | mode_cmd.width = mode->hdisplay; | |
9379 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
9380 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
9381 | bpp); | |
5ca0c34a | 9382 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 9383 | |
24dbf51a | 9384 | fb = intel_framebuffer_create(obj, &mode_cmd); |
dcb1394e | 9385 | if (IS_ERR(fb)) |
f0cd5182 | 9386 | i915_gem_object_put(obj); |
dcb1394e LW |
9387 | |
9388 | return fb; | |
d2dff872 CW |
9389 | } |
9390 | ||
9391 | static struct drm_framebuffer * | |
9392 | mode_fits_in_fbdev(struct drm_device *dev, | |
9393 | struct drm_display_mode *mode) | |
9394 | { | |
0695726e | 9395 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
fac5e23e | 9396 | struct drm_i915_private *dev_priv = to_i915(dev); |
d2dff872 CW |
9397 | struct drm_i915_gem_object *obj; |
9398 | struct drm_framebuffer *fb; | |
9399 | ||
4c0e5528 | 9400 | if (!dev_priv->fbdev) |
d2dff872 CW |
9401 | return NULL; |
9402 | ||
4c0e5528 | 9403 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
9404 | return NULL; |
9405 | ||
4c0e5528 DV |
9406 | obj = dev_priv->fbdev->fb->obj; |
9407 | BUG_ON(!obj); | |
9408 | ||
8bcd4553 | 9409 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 | 9410 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
272725c7 | 9411 | fb->format->cpp[0] * 8)) |
d2dff872 CW |
9412 | return NULL; |
9413 | ||
01f2c773 | 9414 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
9415 | return NULL; |
9416 | ||
edde3617 | 9417 | drm_framebuffer_reference(fb); |
d2dff872 | 9418 | return fb; |
4520f53a DV |
9419 | #else |
9420 | return NULL; | |
9421 | #endif | |
d2dff872 CW |
9422 | } |
9423 | ||
d3a40d1b ACO |
9424 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
9425 | struct drm_crtc *crtc, | |
9426 | struct drm_display_mode *mode, | |
9427 | struct drm_framebuffer *fb, | |
9428 | int x, int y) | |
9429 | { | |
9430 | struct drm_plane_state *plane_state; | |
9431 | int hdisplay, vdisplay; | |
9432 | int ret; | |
9433 | ||
9434 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
9435 | if (IS_ERR(plane_state)) | |
9436 | return PTR_ERR(plane_state); | |
9437 | ||
9438 | if (mode) | |
196cd5d3 | 9439 | drm_mode_get_hv_timing(mode, &hdisplay, &vdisplay); |
d3a40d1b ACO |
9440 | else |
9441 | hdisplay = vdisplay = 0; | |
9442 | ||
9443 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
9444 | if (ret) | |
9445 | return ret; | |
9446 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
9447 | plane_state->crtc_x = 0; | |
9448 | plane_state->crtc_y = 0; | |
9449 | plane_state->crtc_w = hdisplay; | |
9450 | plane_state->crtc_h = vdisplay; | |
9451 | plane_state->src_x = x << 16; | |
9452 | plane_state->src_y = y << 16; | |
9453 | plane_state->src_w = hdisplay << 16; | |
9454 | plane_state->src_h = vdisplay << 16; | |
9455 | ||
9456 | return 0; | |
9457 | } | |
9458 | ||
d2434ab7 | 9459 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 9460 | struct drm_display_mode *mode, |
51fd371b RC |
9461 | struct intel_load_detect_pipe *old, |
9462 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
9463 | { |
9464 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
9465 | struct intel_encoder *intel_encoder = |
9466 | intel_attached_encoder(connector); | |
79e53945 | 9467 | struct drm_crtc *possible_crtc; |
4ef69c7a | 9468 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
9469 | struct drm_crtc *crtc = NULL; |
9470 | struct drm_device *dev = encoder->dev; | |
0f0f74bc | 9471 | struct drm_i915_private *dev_priv = to_i915(dev); |
94352cf9 | 9472 | struct drm_framebuffer *fb; |
51fd371b | 9473 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 9474 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 9475 | struct drm_connector_state *connector_state; |
4be07317 | 9476 | struct intel_crtc_state *crtc_state; |
51fd371b | 9477 | int ret, i = -1; |
79e53945 | 9478 | |
d2dff872 | 9479 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9480 | connector->base.id, connector->name, |
8e329a03 | 9481 | encoder->base.id, encoder->name); |
d2dff872 | 9482 | |
edde3617 ML |
9483 | old->restore_state = NULL; |
9484 | ||
51fd371b RC |
9485 | retry: |
9486 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
9487 | if (ret) | |
ad3c558f | 9488 | goto fail; |
6e9f798d | 9489 | |
79e53945 JB |
9490 | /* |
9491 | * Algorithm gets a little messy: | |
7a5e4805 | 9492 | * |
79e53945 JB |
9493 | * - if the connector already has an assigned crtc, use it (but make |
9494 | * sure it's on first) | |
7a5e4805 | 9495 | * |
79e53945 JB |
9496 | * - try to find the first unused crtc that can drive this connector, |
9497 | * and use that if we find one | |
79e53945 JB |
9498 | */ |
9499 | ||
9500 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
9501 | if (connector->state->crtc) { |
9502 | crtc = connector->state->crtc; | |
8261b191 | 9503 | |
51fd371b | 9504 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 9505 | if (ret) |
ad3c558f | 9506 | goto fail; |
8261b191 CW |
9507 | |
9508 | /* Make sure the crtc and connector are running */ | |
edde3617 | 9509 | goto found; |
79e53945 JB |
9510 | } |
9511 | ||
9512 | /* Find an unused one (if possible) */ | |
70e1e0ec | 9513 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
9514 | i++; |
9515 | if (!(encoder->possible_crtcs & (1 << i))) | |
9516 | continue; | |
edde3617 ML |
9517 | |
9518 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
9519 | if (ret) | |
9520 | goto fail; | |
9521 | ||
9522 | if (possible_crtc->state->enable) { | |
9523 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 9524 | continue; |
edde3617 | 9525 | } |
a459249c VS |
9526 | |
9527 | crtc = possible_crtc; | |
9528 | break; | |
79e53945 JB |
9529 | } |
9530 | ||
9531 | /* | |
9532 | * If we didn't find an unused CRTC, don't use any. | |
9533 | */ | |
9534 | if (!crtc) { | |
7173188d | 9535 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 9536 | goto fail; |
79e53945 JB |
9537 | } |
9538 | ||
edde3617 ML |
9539 | found: |
9540 | intel_crtc = to_intel_crtc(crtc); | |
9541 | ||
4d02e2de DV |
9542 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
9543 | if (ret) | |
ad3c558f | 9544 | goto fail; |
79e53945 | 9545 | |
83a57153 | 9546 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
9547 | restore_state = drm_atomic_state_alloc(dev); |
9548 | if (!state || !restore_state) { | |
9549 | ret = -ENOMEM; | |
9550 | goto fail; | |
9551 | } | |
83a57153 ACO |
9552 | |
9553 | state->acquire_ctx = ctx; | |
edde3617 | 9554 | restore_state->acquire_ctx = ctx; |
83a57153 | 9555 | |
944b0c76 ACO |
9556 | connector_state = drm_atomic_get_connector_state(state, connector); |
9557 | if (IS_ERR(connector_state)) { | |
9558 | ret = PTR_ERR(connector_state); | |
9559 | goto fail; | |
9560 | } | |
9561 | ||
edde3617 ML |
9562 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
9563 | if (ret) | |
9564 | goto fail; | |
944b0c76 | 9565 | |
4be07317 ACO |
9566 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
9567 | if (IS_ERR(crtc_state)) { | |
9568 | ret = PTR_ERR(crtc_state); | |
9569 | goto fail; | |
9570 | } | |
9571 | ||
49d6fa21 | 9572 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 9573 | |
6492711d CW |
9574 | if (!mode) |
9575 | mode = &load_detect_mode; | |
79e53945 | 9576 | |
d2dff872 CW |
9577 | /* We need a framebuffer large enough to accommodate all accesses |
9578 | * that the plane may generate whilst we perform load detection. | |
9579 | * We can not rely on the fbcon either being present (we get called | |
9580 | * during its initialisation to detect all boot displays, or it may | |
9581 | * not even exist) or that it is large enough to satisfy the | |
9582 | * requested mode. | |
9583 | */ | |
94352cf9 DV |
9584 | fb = mode_fits_in_fbdev(dev, mode); |
9585 | if (fb == NULL) { | |
d2dff872 | 9586 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 | 9587 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
d2dff872 CW |
9588 | } else |
9589 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 9590 | if (IS_ERR(fb)) { |
d2dff872 | 9591 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 9592 | goto fail; |
79e53945 | 9593 | } |
79e53945 | 9594 | |
d3a40d1b ACO |
9595 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
9596 | if (ret) | |
9597 | goto fail; | |
9598 | ||
edde3617 ML |
9599 | drm_framebuffer_unreference(fb); |
9600 | ||
9601 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
9602 | if (ret) | |
9603 | goto fail; | |
9604 | ||
9605 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
9606 | if (!ret) | |
9607 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
9608 | if (!ret) | |
9609 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
9610 | if (ret) { | |
9611 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
9612 | goto fail; | |
9613 | } | |
8c7b5ccb | 9614 | |
3ba86073 ML |
9615 | ret = drm_atomic_commit(state); |
9616 | if (ret) { | |
6492711d | 9617 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
412b61d8 | 9618 | goto fail; |
79e53945 | 9619 | } |
edde3617 ML |
9620 | |
9621 | old->restore_state = restore_state; | |
7abbd11f | 9622 | drm_atomic_state_put(state); |
7173188d | 9623 | |
79e53945 | 9624 | /* let the connector get through one full cycle before testing */ |
0f0f74bc | 9625 | intel_wait_for_vblank(dev_priv, intel_crtc->pipe); |
7173188d | 9626 | return true; |
412b61d8 | 9627 | |
ad3c558f | 9628 | fail: |
7fb71c8f CW |
9629 | if (state) { |
9630 | drm_atomic_state_put(state); | |
9631 | state = NULL; | |
9632 | } | |
9633 | if (restore_state) { | |
9634 | drm_atomic_state_put(restore_state); | |
9635 | restore_state = NULL; | |
9636 | } | |
83a57153 | 9637 | |
51fd371b RC |
9638 | if (ret == -EDEADLK) { |
9639 | drm_modeset_backoff(ctx); | |
9640 | goto retry; | |
9641 | } | |
9642 | ||
412b61d8 | 9643 | return false; |
79e53945 JB |
9644 | } |
9645 | ||
d2434ab7 | 9646 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
9647 | struct intel_load_detect_pipe *old, |
9648 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 9649 | { |
d2434ab7 DV |
9650 | struct intel_encoder *intel_encoder = |
9651 | intel_attached_encoder(connector); | |
4ef69c7a | 9652 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 9653 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 9654 | int ret; |
79e53945 | 9655 | |
d2dff872 | 9656 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 9657 | connector->base.id, connector->name, |
8e329a03 | 9658 | encoder->base.id, encoder->name); |
d2dff872 | 9659 | |
edde3617 | 9660 | if (!state) |
0622a53c | 9661 | return; |
79e53945 | 9662 | |
581e49fe | 9663 | ret = drm_atomic_helper_commit_duplicated_state(state, ctx); |
0853695c | 9664 | if (ret) |
edde3617 | 9665 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); |
0853695c | 9666 | drm_atomic_state_put(state); |
79e53945 JB |
9667 | } |
9668 | ||
da4a1efa | 9669 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 9670 | const struct intel_crtc_state *pipe_config) |
da4a1efa | 9671 | { |
fac5e23e | 9672 | struct drm_i915_private *dev_priv = to_i915(dev); |
da4a1efa VS |
9673 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
9674 | ||
9675 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 9676 | return dev_priv->vbt.lvds_ssc_freq; |
6e266956 | 9677 | else if (HAS_PCH_SPLIT(dev_priv)) |
da4a1efa | 9678 | return 120000; |
5db94019 | 9679 | else if (!IS_GEN2(dev_priv)) |
da4a1efa VS |
9680 | return 96000; |
9681 | else | |
9682 | return 48000; | |
9683 | } | |
9684 | ||
79e53945 | 9685 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 9686 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 9687 | struct intel_crtc_state *pipe_config) |
79e53945 | 9688 | { |
f1f644dc | 9689 | struct drm_device *dev = crtc->base.dev; |
fac5e23e | 9690 | struct drm_i915_private *dev_priv = to_i915(dev); |
f1f644dc | 9691 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 9692 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 | 9693 | u32 fp; |
9e2c8475 | 9694 | struct dpll clock; |
dccbea3b | 9695 | int port_clock; |
da4a1efa | 9696 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
9697 | |
9698 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 9699 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 9700 | else |
293623f7 | 9701 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
9702 | |
9703 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
9b1e14f4 | 9704 | if (IS_PINEVIEW(dev_priv)) { |
f2b115e6 AJ |
9705 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; |
9706 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
9707 | } else { |
9708 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
9709 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
9710 | } | |
9711 | ||
5db94019 | 9712 | if (!IS_GEN2(dev_priv)) { |
9b1e14f4 | 9713 | if (IS_PINEVIEW(dev_priv)) |
f2b115e6 AJ |
9714 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> |
9715 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
9716 | else |
9717 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
9718 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
9719 | ||
9720 | switch (dpll & DPLL_MODE_MASK) { | |
9721 | case DPLLB_MODE_DAC_SERIAL: | |
9722 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
9723 | 5 : 10; | |
9724 | break; | |
9725 | case DPLLB_MODE_LVDS: | |
9726 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
9727 | 7 : 14; | |
9728 | break; | |
9729 | default: | |
28c97730 | 9730 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 9731 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 9732 | return; |
79e53945 JB |
9733 | } |
9734 | ||
9b1e14f4 | 9735 | if (IS_PINEVIEW(dev_priv)) |
dccbea3b | 9736 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 9737 | else |
dccbea3b | 9738 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 9739 | } else { |
50a0bc90 | 9740 | u32 lvds = IS_I830(dev_priv) ? 0 : I915_READ(LVDS); |
b1c560d1 | 9741 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
9742 | |
9743 | if (is_lvds) { | |
9744 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
9745 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
9746 | |
9747 | if (lvds & LVDS_CLKB_POWER_UP) | |
9748 | clock.p2 = 7; | |
9749 | else | |
9750 | clock.p2 = 14; | |
79e53945 JB |
9751 | } else { |
9752 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
9753 | clock.p1 = 2; | |
9754 | else { | |
9755 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
9756 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
9757 | } | |
9758 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
9759 | clock.p2 = 4; | |
9760 | else | |
9761 | clock.p2 = 2; | |
79e53945 | 9762 | } |
da4a1efa | 9763 | |
dccbea3b | 9764 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
9765 | } |
9766 | ||
18442d08 VS |
9767 | /* |
9768 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 9769 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
9770 | * encoder's get_config() function. |
9771 | */ | |
dccbea3b | 9772 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
9773 | } |
9774 | ||
6878da05 VS |
9775 | int intel_dotclock_calculate(int link_freq, |
9776 | const struct intel_link_m_n *m_n) | |
f1f644dc | 9777 | { |
f1f644dc JB |
9778 | /* |
9779 | * The calculation for the data clock is: | |
1041a02f | 9780 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 9781 | * But we want to avoid losing precison if possible, so: |
1041a02f | 9782 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
9783 | * |
9784 | * and the link clock is simpler: | |
1041a02f | 9785 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
9786 | */ |
9787 | ||
6878da05 VS |
9788 | if (!m_n->link_n) |
9789 | return 0; | |
f1f644dc | 9790 | |
6878da05 VS |
9791 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
9792 | } | |
f1f644dc | 9793 | |
18442d08 | 9794 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 9795 | struct intel_crtc_state *pipe_config) |
6878da05 | 9796 | { |
e3b247da | 9797 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
79e53945 | 9798 | |
18442d08 VS |
9799 | /* read out port_clock from the DPLL */ |
9800 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 9801 | |
f1f644dc | 9802 | /* |
e3b247da VS |
9803 | * In case there is an active pipe without active ports, |
9804 | * we may need some idea for the dotclock anyway. | |
9805 | * Calculate one based on the FDI configuration. | |
79e53945 | 9806 | */ |
2d112de7 | 9807 | pipe_config->base.adjusted_mode.crtc_clock = |
21a727b3 | 9808 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
18442d08 | 9809 | &pipe_config->fdi_m_n); |
79e53945 JB |
9810 | } |
9811 | ||
9812 | /** Returns the currently programmed mode of the given pipe. */ | |
9813 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
9814 | struct drm_crtc *crtc) | |
9815 | { | |
fac5e23e | 9816 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 9817 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 9818 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 9819 | struct drm_display_mode *mode; |
3f36b937 | 9820 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
9821 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
9822 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
9823 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
9824 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 9825 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
9826 | |
9827 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
9828 | if (!mode) | |
9829 | return NULL; | |
9830 | ||
3f36b937 TU |
9831 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
9832 | if (!pipe_config) { | |
9833 | kfree(mode); | |
9834 | return NULL; | |
9835 | } | |
9836 | ||
f1f644dc JB |
9837 | /* |
9838 | * Construct a pipe_config sufficient for getting the clock info | |
9839 | * back out of crtc_clock_get. | |
9840 | * | |
9841 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
9842 | * to use a real value here instead. | |
9843 | */ | |
3f36b937 TU |
9844 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
9845 | pipe_config->pixel_multiplier = 1; | |
9846 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
9847 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
9848 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
9849 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
9850 | ||
9851 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
9852 | mode->hdisplay = (htot & 0xffff) + 1; |
9853 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
9854 | mode->hsync_start = (hsync & 0xffff) + 1; | |
9855 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
9856 | mode->vdisplay = (vtot & 0xffff) + 1; | |
9857 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
9858 | mode->vsync_start = (vsync & 0xffff) + 1; | |
9859 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
9860 | ||
9861 | drm_mode_set_name(mode); | |
79e53945 | 9862 | |
3f36b937 TU |
9863 | kfree(pipe_config); |
9864 | ||
79e53945 JB |
9865 | return mode; |
9866 | } | |
9867 | ||
9868 | static void intel_crtc_destroy(struct drm_crtc *crtc) | |
9869 | { | |
9870 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a | 9871 | struct drm_device *dev = crtc->dev; |
51cbaf01 | 9872 | struct intel_flip_work *work; |
67e77c5a | 9873 | |
5e2d7afc | 9874 | spin_lock_irq(&dev->event_lock); |
5a21b665 DV |
9875 | work = intel_crtc->flip_work; |
9876 | intel_crtc->flip_work = NULL; | |
9877 | spin_unlock_irq(&dev->event_lock); | |
67e77c5a | 9878 | |
5a21b665 | 9879 | if (work) { |
51cbaf01 ML |
9880 | cancel_work_sync(&work->mmio_work); |
9881 | cancel_work_sync(&work->unpin_work); | |
5a21b665 | 9882 | kfree(work); |
67e77c5a | 9883 | } |
79e53945 JB |
9884 | |
9885 | drm_crtc_cleanup(crtc); | |
67e77c5a | 9886 | |
79e53945 JB |
9887 | kfree(intel_crtc); |
9888 | } | |
9889 | ||
6b95a207 KH |
9890 | static void intel_unpin_work_fn(struct work_struct *__work) |
9891 | { | |
51cbaf01 ML |
9892 | struct intel_flip_work *work = |
9893 | container_of(__work, struct intel_flip_work, unpin_work); | |
5a21b665 DV |
9894 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
9895 | struct drm_device *dev = crtc->base.dev; | |
9896 | struct drm_plane *primary = crtc->base.primary; | |
03f476e1 | 9897 | |
5a21b665 DV |
9898 | if (is_mmio_work(work)) |
9899 | flush_work(&work->mmio_work); | |
03f476e1 | 9900 | |
5a21b665 | 9901 | mutex_lock(&dev->struct_mutex); |
be1e3415 | 9902 | intel_unpin_fb_vma(work->old_vma); |
f8c417cd | 9903 | i915_gem_object_put(work->pending_flip_obj); |
5a21b665 | 9904 | mutex_unlock(&dev->struct_mutex); |
143f73b3 | 9905 | |
e8a261ea CW |
9906 | i915_gem_request_put(work->flip_queued_req); |
9907 | ||
5748b6a1 CW |
9908 | intel_frontbuffer_flip_complete(to_i915(dev), |
9909 | to_intel_plane(primary)->frontbuffer_bit); | |
5a21b665 DV |
9910 | intel_fbc_post_update(crtc); |
9911 | drm_framebuffer_unreference(work->old_fb); | |
143f73b3 | 9912 | |
5a21b665 DV |
9913 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
9914 | atomic_dec(&crtc->unpin_work_count); | |
a6747b73 | 9915 | |
5a21b665 DV |
9916 | kfree(work); |
9917 | } | |
d9e86c0e | 9918 | |
5a21b665 DV |
9919 | /* Is 'a' after or equal to 'b'? */ |
9920 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
9921 | { | |
9922 | return !((a - b) & 0x80000000); | |
9923 | } | |
143f73b3 | 9924 | |
5a21b665 DV |
9925 | static bool __pageflip_finished_cs(struct intel_crtc *crtc, |
9926 | struct intel_flip_work *work) | |
9927 | { | |
9928 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 9929 | struct drm_i915_private *dev_priv = to_i915(dev); |
143f73b3 | 9930 | |
8af29b0c | 9931 | if (abort_flip_on_reset(crtc)) |
5a21b665 | 9932 | return true; |
143f73b3 | 9933 | |
5a21b665 DV |
9934 | /* |
9935 | * The relevant registers doen't exist on pre-ctg. | |
9936 | * As the flip done interrupt doesn't trigger for mmio | |
9937 | * flips on gmch platforms, a flip count check isn't | |
9938 | * really needed there. But since ctg has the registers, | |
9939 | * include it in the check anyway. | |
9940 | */ | |
9beb5fea | 9941 | if (INTEL_GEN(dev_priv) < 5 && !IS_G4X(dev_priv)) |
5a21b665 | 9942 | return true; |
b4a98e57 | 9943 | |
5a21b665 DV |
9944 | /* |
9945 | * BDW signals flip done immediately if the plane | |
9946 | * is disabled, even if the plane enable is already | |
9947 | * armed to occur at the next vblank :( | |
9948 | */ | |
f99d7069 | 9949 | |
5a21b665 DV |
9950 | /* |
9951 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
9952 | * used the same base address. In that case the mmio flip might | |
9953 | * have completed, but the CS hasn't even executed the flip yet. | |
9954 | * | |
9955 | * A flip count check isn't enough as the CS might have updated | |
9956 | * the base address just after start of vblank, but before we | |
9957 | * managed to process the interrupt. This means we'd complete the | |
9958 | * CS flip too soon. | |
9959 | * | |
9960 | * Combining both checks should get us a good enough result. It may | |
9961 | * still happen that the CS flip has been executed, but has not | |
9962 | * yet actually completed. But in case the base address is the same | |
9963 | * anyway, we don't really care. | |
9964 | */ | |
9965 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
9966 | crtc->flip_work->gtt_offset && | |
9967 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), | |
9968 | crtc->flip_work->flip_count); | |
9969 | } | |
b4a98e57 | 9970 | |
5a21b665 DV |
9971 | static bool |
9972 | __pageflip_finished_mmio(struct intel_crtc *crtc, | |
9973 | struct intel_flip_work *work) | |
9974 | { | |
9975 | /* | |
9976 | * MMIO work completes when vblank is different from | |
9977 | * flip_queued_vblank. | |
9978 | * | |
9979 | * Reset counter value doesn't matter, this is handled by | |
9980 | * i915_wait_request finishing early, so no need to handle | |
9981 | * reset here. | |
9982 | */ | |
9983 | return intel_crtc_get_vblank_counter(crtc) != work->flip_queued_vblank; | |
6b95a207 KH |
9984 | } |
9985 | ||
51cbaf01 ML |
9986 | |
9987 | static bool pageflip_finished(struct intel_crtc *crtc, | |
9988 | struct intel_flip_work *work) | |
9989 | { | |
9990 | if (!atomic_read(&work->pending)) | |
9991 | return false; | |
9992 | ||
9993 | smp_rmb(); | |
9994 | ||
5a21b665 DV |
9995 | if (is_mmio_work(work)) |
9996 | return __pageflip_finished_mmio(crtc, work); | |
9997 | else | |
9998 | return __pageflip_finished_cs(crtc, work); | |
9999 | } | |
10000 | ||
10001 | void intel_finish_page_flip_cs(struct drm_i915_private *dev_priv, int pipe) | |
10002 | { | |
91c8a326 | 10003 | struct drm_device *dev = &dev_priv->drm; |
98187836 | 10004 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
5a21b665 DV |
10005 | struct intel_flip_work *work; |
10006 | unsigned long flags; | |
10007 | ||
10008 | /* Ignore early vblank irqs */ | |
10009 | if (!crtc) | |
10010 | return; | |
10011 | ||
51cbaf01 | 10012 | /* |
5a21b665 DV |
10013 | * This is called both by irq handlers and the reset code (to complete |
10014 | * lost pageflips) so needs the full irqsave spinlocks. | |
51cbaf01 | 10015 | */ |
5a21b665 | 10016 | spin_lock_irqsave(&dev->event_lock, flags); |
e2af48c6 | 10017 | work = crtc->flip_work; |
5a21b665 DV |
10018 | |
10019 | if (work != NULL && | |
10020 | !is_mmio_work(work) && | |
e2af48c6 VS |
10021 | pageflip_finished(crtc, work)) |
10022 | page_flip_completed(crtc); | |
5a21b665 DV |
10023 | |
10024 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
75f7f3ec VS |
10025 | } |
10026 | ||
51cbaf01 | 10027 | void intel_finish_page_flip_mmio(struct drm_i915_private *dev_priv, int pipe) |
6b95a207 | 10028 | { |
91c8a326 | 10029 | struct drm_device *dev = &dev_priv->drm; |
98187836 | 10030 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
51cbaf01 | 10031 | struct intel_flip_work *work; |
6b95a207 KH |
10032 | unsigned long flags; |
10033 | ||
5251f04e ML |
10034 | /* Ignore early vblank irqs */ |
10035 | if (!crtc) | |
10036 | return; | |
f326038a DV |
10037 | |
10038 | /* | |
10039 | * This is called both by irq handlers and the reset code (to complete | |
10040 | * lost pageflips) so needs the full irqsave spinlocks. | |
e7d841ca | 10041 | */ |
6b95a207 | 10042 | spin_lock_irqsave(&dev->event_lock, flags); |
e2af48c6 | 10043 | work = crtc->flip_work; |
5251f04e | 10044 | |
5a21b665 DV |
10045 | if (work != NULL && |
10046 | is_mmio_work(work) && | |
e2af48c6 VS |
10047 | pageflip_finished(crtc, work)) |
10048 | page_flip_completed(crtc); | |
5251f04e | 10049 | |
6b95a207 KH |
10050 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10051 | } | |
10052 | ||
5a21b665 DV |
10053 | static inline void intel_mark_page_flip_active(struct intel_crtc *crtc, |
10054 | struct intel_flip_work *work) | |
84c33a64 | 10055 | { |
5a21b665 | 10056 | work->flip_queued_vblank = intel_crtc_get_vblank_counter(crtc); |
84c33a64 | 10057 | |
5a21b665 DV |
10058 | /* Ensure that the work item is consistent when activating it ... */ |
10059 | smp_mb__before_atomic(); | |
10060 | atomic_set(&work->pending, 1); | |
10061 | } | |
a6747b73 | 10062 | |
5a21b665 DV |
10063 | static int intel_gen2_queue_flip(struct drm_device *dev, |
10064 | struct drm_crtc *crtc, | |
10065 | struct drm_framebuffer *fb, | |
10066 | struct drm_i915_gem_object *obj, | |
10067 | struct drm_i915_gem_request *req, | |
10068 | uint32_t flags) | |
10069 | { | |
5a21b665 | 10070 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
73dec95e | 10071 | u32 flip_mask, *cs; |
143f73b3 | 10072 | |
73dec95e TU |
10073 | cs = intel_ring_begin(req, 6); |
10074 | if (IS_ERR(cs)) | |
10075 | return PTR_ERR(cs); | |
143f73b3 | 10076 | |
5a21b665 DV |
10077 | /* Can't queue multiple flips, so wait for the previous |
10078 | * one to finish before executing the next. | |
10079 | */ | |
10080 | if (intel_crtc->plane) | |
10081 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10082 | else | |
10083 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
73dec95e TU |
10084 | *cs++ = MI_WAIT_FOR_EVENT | flip_mask; |
10085 | *cs++ = MI_NOOP; | |
10086 | *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane); | |
10087 | *cs++ = fb->pitches[0]; | |
10088 | *cs++ = intel_crtc->flip_work->gtt_offset; | |
10089 | *cs++ = 0; /* aux display base address, unused */ | |
143f73b3 | 10090 | |
5a21b665 DV |
10091 | return 0; |
10092 | } | |
84c33a64 | 10093 | |
5a21b665 DV |
10094 | static int intel_gen3_queue_flip(struct drm_device *dev, |
10095 | struct drm_crtc *crtc, | |
10096 | struct drm_framebuffer *fb, | |
10097 | struct drm_i915_gem_object *obj, | |
10098 | struct drm_i915_gem_request *req, | |
10099 | uint32_t flags) | |
10100 | { | |
5a21b665 | 10101 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
73dec95e | 10102 | u32 flip_mask, *cs; |
d55dbd06 | 10103 | |
73dec95e TU |
10104 | cs = intel_ring_begin(req, 6); |
10105 | if (IS_ERR(cs)) | |
10106 | return PTR_ERR(cs); | |
d55dbd06 | 10107 | |
5a21b665 DV |
10108 | if (intel_crtc->plane) |
10109 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10110 | else | |
10111 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
73dec95e TU |
10112 | *cs++ = MI_WAIT_FOR_EVENT | flip_mask; |
10113 | *cs++ = MI_NOOP; | |
10114 | *cs++ = MI_DISPLAY_FLIP_I915 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane); | |
10115 | *cs++ = fb->pitches[0]; | |
10116 | *cs++ = intel_crtc->flip_work->gtt_offset; | |
10117 | *cs++ = MI_NOOP; | |
fd8e058a | 10118 | |
5a21b665 DV |
10119 | return 0; |
10120 | } | |
84c33a64 | 10121 | |
5a21b665 DV |
10122 | static int intel_gen4_queue_flip(struct drm_device *dev, |
10123 | struct drm_crtc *crtc, | |
10124 | struct drm_framebuffer *fb, | |
10125 | struct drm_i915_gem_object *obj, | |
10126 | struct drm_i915_gem_request *req, | |
10127 | uint32_t flags) | |
10128 | { | |
fac5e23e | 10129 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 10130 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
73dec95e | 10131 | u32 pf, pipesrc, *cs; |
143f73b3 | 10132 | |
73dec95e TU |
10133 | cs = intel_ring_begin(req, 4); |
10134 | if (IS_ERR(cs)) | |
10135 | return PTR_ERR(cs); | |
143f73b3 | 10136 | |
5a21b665 DV |
10137 | /* i965+ uses the linear or tiled offsets from the |
10138 | * Display Registers (which do not change across a page-flip) | |
10139 | * so we need only reprogram the base address. | |
10140 | */ | |
73dec95e TU |
10141 | *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane); |
10142 | *cs++ = fb->pitches[0]; | |
10143 | *cs++ = intel_crtc->flip_work->gtt_offset | | |
10144 | intel_fb_modifier_to_tiling(fb->modifier); | |
5a21b665 DV |
10145 | |
10146 | /* XXX Enabling the panel-fitter across page-flip is so far | |
10147 | * untested on non-native modes, so ignore it for now. | |
10148 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
10149 | */ | |
10150 | pf = 0; | |
10151 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
73dec95e | 10152 | *cs++ = pf | pipesrc; |
143f73b3 | 10153 | |
5a21b665 | 10154 | return 0; |
8c9f3aaf JB |
10155 | } |
10156 | ||
5a21b665 DV |
10157 | static int intel_gen6_queue_flip(struct drm_device *dev, |
10158 | struct drm_crtc *crtc, | |
10159 | struct drm_framebuffer *fb, | |
10160 | struct drm_i915_gem_object *obj, | |
10161 | struct drm_i915_gem_request *req, | |
10162 | uint32_t flags) | |
da20eabd | 10163 | { |
fac5e23e | 10164 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 10165 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
73dec95e | 10166 | u32 pf, pipesrc, *cs; |
d21fbe87 | 10167 | |
73dec95e TU |
10168 | cs = intel_ring_begin(req, 4); |
10169 | if (IS_ERR(cs)) | |
10170 | return PTR_ERR(cs); | |
92826fcd | 10171 | |
73dec95e TU |
10172 | *cs++ = MI_DISPLAY_FLIP | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane); |
10173 | *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier); | |
10174 | *cs++ = intel_crtc->flip_work->gtt_offset; | |
92826fcd | 10175 | |
5a21b665 DV |
10176 | /* Contrary to the suggestions in the documentation, |
10177 | * "Enable Panel Fitter" does not seem to be required when page | |
10178 | * flipping with a non-native mode, and worse causes a normal | |
10179 | * modeset to fail. | |
10180 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
10181 | */ | |
10182 | pf = 0; | |
10183 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
73dec95e | 10184 | *cs++ = pf | pipesrc; |
7809e5ae | 10185 | |
5a21b665 | 10186 | return 0; |
7809e5ae MR |
10187 | } |
10188 | ||
5a21b665 DV |
10189 | static int intel_gen7_queue_flip(struct drm_device *dev, |
10190 | struct drm_crtc *crtc, | |
10191 | struct drm_framebuffer *fb, | |
10192 | struct drm_i915_gem_object *obj, | |
10193 | struct drm_i915_gem_request *req, | |
10194 | uint32_t flags) | |
d21fbe87 | 10195 | { |
5db94019 | 10196 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 10197 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
73dec95e | 10198 | u32 *cs, plane_bit = 0; |
5a21b665 | 10199 | int len, ret; |
d21fbe87 | 10200 | |
5a21b665 DV |
10201 | switch (intel_crtc->plane) { |
10202 | case PLANE_A: | |
10203 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
10204 | break; | |
10205 | case PLANE_B: | |
10206 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
10207 | break; | |
10208 | case PLANE_C: | |
10209 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
10210 | break; | |
10211 | default: | |
10212 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
10213 | return -ENODEV; | |
10214 | } | |
10215 | ||
10216 | len = 4; | |
b5321f30 | 10217 | if (req->engine->id == RCS) { |
5a21b665 DV |
10218 | len += 6; |
10219 | /* | |
10220 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
10221 | * 48bits addresses, and we need a NOOP for the batch size to | |
10222 | * stay even. | |
10223 | */ | |
5db94019 | 10224 | if (IS_GEN8(dev_priv)) |
5a21b665 DV |
10225 | len += 2; |
10226 | } | |
10227 | ||
10228 | /* | |
10229 | * BSpec MI_DISPLAY_FLIP for IVB: | |
10230 | * "The full packet must be contained within the same cache line." | |
10231 | * | |
10232 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
10233 | * cacheline, if we ever start emitting more commands before | |
10234 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
10235 | * then do the cacheline alignment, and finally emit the | |
10236 | * MI_DISPLAY_FLIP. | |
10237 | */ | |
10238 | ret = intel_ring_cacheline_align(req); | |
10239 | if (ret) | |
10240 | return ret; | |
10241 | ||
73dec95e TU |
10242 | cs = intel_ring_begin(req, len); |
10243 | if (IS_ERR(cs)) | |
10244 | return PTR_ERR(cs); | |
5a21b665 DV |
10245 | |
10246 | /* Unmask the flip-done completion message. Note that the bspec says that | |
10247 | * we should do this for both the BCS and RCS, and that we must not unmask | |
10248 | * more than one flip event at any time (or ensure that one flip message | |
10249 | * can be sent by waiting for flip-done prior to queueing new flips). | |
10250 | * Experimentation says that BCS works despite DERRMR masking all | |
10251 | * flip-done completion events and that unmasking all planes at once | |
10252 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
10253 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
10254 | */ | |
b5321f30 | 10255 | if (req->engine->id == RCS) { |
73dec95e TU |
10256 | *cs++ = MI_LOAD_REGISTER_IMM(1); |
10257 | *cs++ = i915_mmio_reg_offset(DERRMR); | |
10258 | *cs++ = ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
10259 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
10260 | DERRMR_PIPEC_PRI_FLIP_DONE); | |
5db94019 | 10261 | if (IS_GEN8(dev_priv)) |
73dec95e TU |
10262 | *cs++ = MI_STORE_REGISTER_MEM_GEN8 | |
10263 | MI_SRM_LRM_GLOBAL_GTT; | |
5a21b665 | 10264 | else |
73dec95e TU |
10265 | *cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT; |
10266 | *cs++ = i915_mmio_reg_offset(DERRMR); | |
10267 | *cs++ = i915_ggtt_offset(req->engine->scratch) + 256; | |
5db94019 | 10268 | if (IS_GEN8(dev_priv)) { |
73dec95e TU |
10269 | *cs++ = 0; |
10270 | *cs++ = MI_NOOP; | |
5a21b665 DV |
10271 | } |
10272 | } | |
10273 | ||
73dec95e TU |
10274 | *cs++ = MI_DISPLAY_FLIP_I915 | plane_bit; |
10275 | *cs++ = fb->pitches[0] | intel_fb_modifier_to_tiling(fb->modifier); | |
10276 | *cs++ = intel_crtc->flip_work->gtt_offset; | |
10277 | *cs++ = MI_NOOP; | |
5a21b665 DV |
10278 | |
10279 | return 0; | |
10280 | } | |
10281 | ||
10282 | static bool use_mmio_flip(struct intel_engine_cs *engine, | |
10283 | struct drm_i915_gem_object *obj) | |
10284 | { | |
10285 | /* | |
10286 | * This is not being used for older platforms, because | |
10287 | * non-availability of flip done interrupt forces us to use | |
10288 | * CS flips. Older platforms derive flip done using some clever | |
10289 | * tricks involving the flip_pending status bits and vblank irqs. | |
10290 | * So using MMIO flips there would disrupt this mechanism. | |
10291 | */ | |
10292 | ||
10293 | if (engine == NULL) | |
10294 | return true; | |
10295 | ||
10296 | if (INTEL_GEN(engine->i915) < 5) | |
10297 | return false; | |
10298 | ||
10299 | if (i915.use_mmio_flip < 0) | |
10300 | return false; | |
10301 | else if (i915.use_mmio_flip > 0) | |
10302 | return true; | |
10303 | else if (i915.enable_execlists) | |
10304 | return true; | |
c37efb99 | 10305 | |
d07f0e59 | 10306 | return engine != i915_gem_object_last_write_engine(obj); |
5a21b665 DV |
10307 | } |
10308 | ||
10309 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, | |
10310 | unsigned int rotation, | |
10311 | struct intel_flip_work *work) | |
10312 | { | |
10313 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 10314 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
10315 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; |
10316 | const enum pipe pipe = intel_crtc->pipe; | |
d2196774 | 10317 | u32 ctl, stride = skl_plane_stride(fb, 0, rotation); |
5a21b665 DV |
10318 | |
10319 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
10320 | ctl &= ~PLANE_CTL_TILED_MASK; | |
bae781b2 | 10321 | switch (fb->modifier) { |
5a21b665 DV |
10322 | case DRM_FORMAT_MOD_NONE: |
10323 | break; | |
10324 | case I915_FORMAT_MOD_X_TILED: | |
10325 | ctl |= PLANE_CTL_TILED_X; | |
10326 | break; | |
10327 | case I915_FORMAT_MOD_Y_TILED: | |
10328 | ctl |= PLANE_CTL_TILED_Y; | |
10329 | break; | |
10330 | case I915_FORMAT_MOD_Yf_TILED: | |
10331 | ctl |= PLANE_CTL_TILED_YF; | |
10332 | break; | |
10333 | default: | |
bae781b2 | 10334 | MISSING_CASE(fb->modifier); |
5a21b665 DV |
10335 | } |
10336 | ||
5a21b665 DV |
10337 | /* |
10338 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
10339 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
10340 | */ | |
10341 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
10342 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
10343 | ||
10344 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); | |
10345 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
10346 | } | |
10347 | ||
10348 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, | |
10349 | struct intel_flip_work *work) | |
10350 | { | |
10351 | struct drm_device *dev = intel_crtc->base.dev; | |
fac5e23e | 10352 | struct drm_i915_private *dev_priv = to_i915(dev); |
72618ebf | 10353 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; |
5a21b665 DV |
10354 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); |
10355 | u32 dspcntr; | |
10356 | ||
10357 | dspcntr = I915_READ(reg); | |
10358 | ||
bae781b2 | 10359 | if (fb->modifier == I915_FORMAT_MOD_X_TILED) |
5a21b665 DV |
10360 | dspcntr |= DISPPLANE_TILED; |
10361 | else | |
10362 | dspcntr &= ~DISPPLANE_TILED; | |
10363 | ||
10364 | I915_WRITE(reg, dspcntr); | |
10365 | ||
10366 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); | |
10367 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
10368 | } | |
10369 | ||
10370 | static void intel_mmio_flip_work_func(struct work_struct *w) | |
10371 | { | |
10372 | struct intel_flip_work *work = | |
10373 | container_of(w, struct intel_flip_work, mmio_work); | |
10374 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); | |
10375 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
10376 | struct intel_framebuffer *intel_fb = | |
10377 | to_intel_framebuffer(crtc->base.primary->fb); | |
10378 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
10379 | ||
d07f0e59 | 10380 | WARN_ON(i915_gem_object_wait(obj, 0, MAX_SCHEDULE_TIMEOUT, NULL) < 0); |
5a21b665 DV |
10381 | |
10382 | intel_pipe_update_start(crtc); | |
10383 | ||
10384 | if (INTEL_GEN(dev_priv) >= 9) | |
10385 | skl_do_mmio_flip(crtc, work->rotation, work); | |
10386 | else | |
10387 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
10388 | ilk_do_mmio_flip(crtc, work); | |
10389 | ||
10390 | intel_pipe_update_end(crtc, work); | |
10391 | } | |
10392 | ||
10393 | static int intel_default_queue_flip(struct drm_device *dev, | |
10394 | struct drm_crtc *crtc, | |
10395 | struct drm_framebuffer *fb, | |
10396 | struct drm_i915_gem_object *obj, | |
10397 | struct drm_i915_gem_request *req, | |
10398 | uint32_t flags) | |
10399 | { | |
10400 | return -ENODEV; | |
10401 | } | |
10402 | ||
10403 | static bool __pageflip_stall_check_cs(struct drm_i915_private *dev_priv, | |
10404 | struct intel_crtc *intel_crtc, | |
10405 | struct intel_flip_work *work) | |
10406 | { | |
10407 | u32 addr, vblank; | |
10408 | ||
10409 | if (!atomic_read(&work->pending)) | |
10410 | return false; | |
10411 | ||
10412 | smp_rmb(); | |
10413 | ||
10414 | vblank = intel_crtc_get_vblank_counter(intel_crtc); | |
10415 | if (work->flip_ready_vblank == 0) { | |
10416 | if (work->flip_queued_req && | |
f69a02c9 | 10417 | !i915_gem_request_completed(work->flip_queued_req)) |
5a21b665 DV |
10418 | return false; |
10419 | ||
10420 | work->flip_ready_vblank = vblank; | |
10421 | } | |
10422 | ||
10423 | if (vblank - work->flip_ready_vblank < 3) | |
10424 | return false; | |
10425 | ||
10426 | /* Potential stall - if we see that the flip has happened, | |
10427 | * assume a missed interrupt. */ | |
10428 | if (INTEL_GEN(dev_priv) >= 4) | |
10429 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
10430 | else | |
10431 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
10432 | ||
10433 | /* There is a potential issue here with a false positive after a flip | |
10434 | * to the same address. We could address this by checking for a | |
10435 | * non-incrementing frame counter. | |
10436 | */ | |
10437 | return addr == work->gtt_offset; | |
10438 | } | |
10439 | ||
10440 | void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe) | |
10441 | { | |
91c8a326 | 10442 | struct drm_device *dev = &dev_priv->drm; |
98187836 | 10443 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
5a21b665 DV |
10444 | struct intel_flip_work *work; |
10445 | ||
10446 | WARN_ON(!in_interrupt()); | |
10447 | ||
10448 | if (crtc == NULL) | |
10449 | return; | |
10450 | ||
10451 | spin_lock(&dev->event_lock); | |
e2af48c6 | 10452 | work = crtc->flip_work; |
5a21b665 DV |
10453 | |
10454 | if (work != NULL && !is_mmio_work(work) && | |
e2af48c6 | 10455 | __pageflip_stall_check_cs(dev_priv, crtc, work)) { |
5a21b665 DV |
10456 | WARN_ONCE(1, |
10457 | "Kicking stuck page flip: queued at %d, now %d\n", | |
e2af48c6 VS |
10458 | work->flip_queued_vblank, intel_crtc_get_vblank_counter(crtc)); |
10459 | page_flip_completed(crtc); | |
5a21b665 DV |
10460 | work = NULL; |
10461 | } | |
10462 | ||
10463 | if (work != NULL && !is_mmio_work(work) && | |
e2af48c6 | 10464 | intel_crtc_get_vblank_counter(crtc) - work->flip_queued_vblank > 1) |
5a21b665 DV |
10465 | intel_queue_rps_boost_for_request(work->flip_queued_req); |
10466 | spin_unlock(&dev->event_lock); | |
10467 | } | |
10468 | ||
4c01ded5 | 10469 | __maybe_unused |
5a21b665 DV |
10470 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
10471 | struct drm_framebuffer *fb, | |
10472 | struct drm_pending_vblank_event *event, | |
10473 | uint32_t page_flip_flags) | |
10474 | { | |
10475 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 10476 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 DV |
10477 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
10478 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
10479 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10480 | struct drm_plane *primary = crtc->primary; | |
10481 | enum pipe pipe = intel_crtc->pipe; | |
10482 | struct intel_flip_work *work; | |
10483 | struct intel_engine_cs *engine; | |
10484 | bool mmio_flip; | |
8e637178 | 10485 | struct drm_i915_gem_request *request; |
058d88c4 | 10486 | struct i915_vma *vma; |
5a21b665 DV |
10487 | int ret; |
10488 | ||
10489 | /* | |
10490 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
10491 | * check to be safe. In the future we may enable pageflipping from | |
10492 | * a disabled primary plane. | |
10493 | */ | |
10494 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
10495 | return -EBUSY; | |
10496 | ||
10497 | /* Can't change pixel format via MI display flips. */ | |
dbd4d576 | 10498 | if (fb->format != crtc->primary->fb->format) |
5a21b665 DV |
10499 | return -EINVAL; |
10500 | ||
10501 | /* | |
10502 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
10503 | * Note that pitch changes could also affect these register. | |
10504 | */ | |
6315b5d3 | 10505 | if (INTEL_GEN(dev_priv) > 3 && |
5a21b665 DV |
10506 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
10507 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
10508 | return -EINVAL; | |
10509 | ||
10510 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
10511 | goto out_hang; | |
10512 | ||
10513 | work = kzalloc(sizeof(*work), GFP_KERNEL); | |
10514 | if (work == NULL) | |
10515 | return -ENOMEM; | |
10516 | ||
10517 | work->event = event; | |
10518 | work->crtc = crtc; | |
10519 | work->old_fb = old_fb; | |
10520 | INIT_WORK(&work->unpin_work, intel_unpin_work_fn); | |
10521 | ||
10522 | ret = drm_crtc_vblank_get(crtc); | |
10523 | if (ret) | |
10524 | goto free_work; | |
10525 | ||
10526 | /* We borrow the event spin lock for protecting flip_work */ | |
10527 | spin_lock_irq(&dev->event_lock); | |
10528 | if (intel_crtc->flip_work) { | |
10529 | /* Before declaring the flip queue wedged, check if | |
10530 | * the hardware completed the operation behind our backs. | |
10531 | */ | |
10532 | if (pageflip_finished(intel_crtc, intel_crtc->flip_work)) { | |
10533 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
10534 | page_flip_completed(intel_crtc); | |
10535 | } else { | |
10536 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
10537 | spin_unlock_irq(&dev->event_lock); | |
10538 | ||
10539 | drm_crtc_vblank_put(crtc); | |
10540 | kfree(work); | |
10541 | return -EBUSY; | |
10542 | } | |
10543 | } | |
10544 | intel_crtc->flip_work = work; | |
10545 | spin_unlock_irq(&dev->event_lock); | |
10546 | ||
10547 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) | |
10548 | flush_workqueue(dev_priv->wq); | |
10549 | ||
10550 | /* Reference the objects for the scheduled work. */ | |
10551 | drm_framebuffer_reference(work->old_fb); | |
5a21b665 DV |
10552 | |
10553 | crtc->primary->fb = fb; | |
10554 | update_state_fb(crtc->primary); | |
faf68d92 | 10555 | |
25dc556a | 10556 | work->pending_flip_obj = i915_gem_object_get(obj); |
5a21b665 DV |
10557 | |
10558 | ret = i915_mutex_lock_interruptible(dev); | |
10559 | if (ret) | |
10560 | goto cleanup; | |
10561 | ||
8af29b0c CW |
10562 | intel_crtc->reset_count = i915_reset_count(&dev_priv->gpu_error); |
10563 | if (i915_reset_in_progress_or_wedged(&dev_priv->gpu_error)) { | |
5a21b665 | 10564 | ret = -EIO; |
ddbb271a | 10565 | goto unlock; |
5a21b665 DV |
10566 | } |
10567 | ||
10568 | atomic_inc(&intel_crtc->unpin_work_count); | |
10569 | ||
9beb5fea | 10570 | if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
5a21b665 DV |
10571 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
10572 | ||
920a14b2 | 10573 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
3b3f1650 | 10574 | engine = dev_priv->engine[BCS]; |
bae781b2 | 10575 | if (fb->modifier != old_fb->modifier) |
5a21b665 DV |
10576 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
10577 | engine = NULL; | |
fd6b8f43 | 10578 | } else if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) { |
3b3f1650 | 10579 | engine = dev_priv->engine[BCS]; |
6315b5d3 | 10580 | } else if (INTEL_GEN(dev_priv) >= 7) { |
d07f0e59 | 10581 | engine = i915_gem_object_last_write_engine(obj); |
5a21b665 | 10582 | if (engine == NULL || engine->id != RCS) |
3b3f1650 | 10583 | engine = dev_priv->engine[BCS]; |
5a21b665 | 10584 | } else { |
3b3f1650 | 10585 | engine = dev_priv->engine[RCS]; |
5a21b665 DV |
10586 | } |
10587 | ||
10588 | mmio_flip = use_mmio_flip(engine, obj); | |
10589 | ||
058d88c4 CW |
10590 | vma = intel_pin_and_fence_fb_obj(fb, primary->state->rotation); |
10591 | if (IS_ERR(vma)) { | |
10592 | ret = PTR_ERR(vma); | |
5a21b665 | 10593 | goto cleanup_pending; |
058d88c4 | 10594 | } |
5a21b665 | 10595 | |
be1e3415 CW |
10596 | work->old_vma = to_intel_plane_state(primary->state)->vma; |
10597 | to_intel_plane_state(primary->state)->vma = vma; | |
10598 | ||
10599 | work->gtt_offset = i915_ggtt_offset(vma) + intel_crtc->dspaddr_offset; | |
5a21b665 DV |
10600 | work->rotation = crtc->primary->state->rotation; |
10601 | ||
1f061316 PZ |
10602 | /* |
10603 | * There's the potential that the next frame will not be compatible with | |
10604 | * FBC, so we want to call pre_update() before the actual page flip. | |
10605 | * The problem is that pre_update() caches some information about the fb | |
10606 | * object, so we want to do this only after the object is pinned. Let's | |
10607 | * be on the safe side and do this immediately before scheduling the | |
10608 | * flip. | |
10609 | */ | |
10610 | intel_fbc_pre_update(intel_crtc, intel_crtc->config, | |
10611 | to_intel_plane_state(primary->state)); | |
10612 | ||
5a21b665 DV |
10613 | if (mmio_flip) { |
10614 | INIT_WORK(&work->mmio_work, intel_mmio_flip_work_func); | |
6277c8d0 | 10615 | queue_work(system_unbound_wq, &work->mmio_work); |
5a21b665 | 10616 | } else { |
e8a9c58f CW |
10617 | request = i915_gem_request_alloc(engine, |
10618 | dev_priv->kernel_context); | |
8e637178 CW |
10619 | if (IS_ERR(request)) { |
10620 | ret = PTR_ERR(request); | |
10621 | goto cleanup_unpin; | |
10622 | } | |
10623 | ||
a2bc4695 | 10624 | ret = i915_gem_request_await_object(request, obj, false); |
8e637178 CW |
10625 | if (ret) |
10626 | goto cleanup_request; | |
10627 | ||
5a21b665 DV |
10628 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, |
10629 | page_flip_flags); | |
10630 | if (ret) | |
8e637178 | 10631 | goto cleanup_request; |
5a21b665 DV |
10632 | |
10633 | intel_mark_page_flip_active(intel_crtc, work); | |
10634 | ||
8e637178 | 10635 | work->flip_queued_req = i915_gem_request_get(request); |
5a21b665 DV |
10636 | i915_add_request_no_flush(request); |
10637 | } | |
10638 | ||
92117f0b | 10639 | i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); |
5a21b665 DV |
10640 | i915_gem_track_fb(intel_fb_obj(old_fb), obj, |
10641 | to_intel_plane(primary)->frontbuffer_bit); | |
10642 | mutex_unlock(&dev->struct_mutex); | |
10643 | ||
5748b6a1 | 10644 | intel_frontbuffer_flip_prepare(to_i915(dev), |
5a21b665 DV |
10645 | to_intel_plane(primary)->frontbuffer_bit); |
10646 | ||
10647 | trace_i915_flip_request(intel_crtc->plane, obj); | |
10648 | ||
10649 | return 0; | |
10650 | ||
8e637178 CW |
10651 | cleanup_request: |
10652 | i915_add_request_no_flush(request); | |
5a21b665 | 10653 | cleanup_unpin: |
be1e3415 CW |
10654 | to_intel_plane_state(primary->state)->vma = work->old_vma; |
10655 | intel_unpin_fb_vma(vma); | |
5a21b665 | 10656 | cleanup_pending: |
5a21b665 | 10657 | atomic_dec(&intel_crtc->unpin_work_count); |
ddbb271a | 10658 | unlock: |
5a21b665 DV |
10659 | mutex_unlock(&dev->struct_mutex); |
10660 | cleanup: | |
10661 | crtc->primary->fb = old_fb; | |
10662 | update_state_fb(crtc->primary); | |
10663 | ||
f0cd5182 | 10664 | i915_gem_object_put(obj); |
5a21b665 DV |
10665 | drm_framebuffer_unreference(work->old_fb); |
10666 | ||
10667 | spin_lock_irq(&dev->event_lock); | |
10668 | intel_crtc->flip_work = NULL; | |
10669 | spin_unlock_irq(&dev->event_lock); | |
10670 | ||
10671 | drm_crtc_vblank_put(crtc); | |
10672 | free_work: | |
10673 | kfree(work); | |
10674 | ||
10675 | if (ret == -EIO) { | |
10676 | struct drm_atomic_state *state; | |
10677 | struct drm_plane_state *plane_state; | |
10678 | ||
10679 | out_hang: | |
10680 | state = drm_atomic_state_alloc(dev); | |
10681 | if (!state) | |
10682 | return -ENOMEM; | |
10683 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
10684 | ||
10685 | retry: | |
10686 | plane_state = drm_atomic_get_plane_state(state, primary); | |
10687 | ret = PTR_ERR_OR_ZERO(plane_state); | |
10688 | if (!ret) { | |
10689 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10690 | ||
10691 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
10692 | if (!ret) | |
10693 | ret = drm_atomic_commit(state); | |
10694 | } | |
10695 | ||
10696 | if (ret == -EDEADLK) { | |
10697 | drm_modeset_backoff(state->acquire_ctx); | |
10698 | drm_atomic_state_clear(state); | |
10699 | goto retry; | |
10700 | } | |
10701 | ||
0853695c | 10702 | drm_atomic_state_put(state); |
5a21b665 DV |
10703 | |
10704 | if (ret == 0 && event) { | |
10705 | spin_lock_irq(&dev->event_lock); | |
10706 | drm_crtc_send_vblank_event(crtc, event); | |
10707 | spin_unlock_irq(&dev->event_lock); | |
10708 | } | |
10709 | } | |
10710 | return ret; | |
10711 | } | |
10712 | ||
10713 | ||
10714 | /** | |
10715 | * intel_wm_need_update - Check whether watermarks need updating | |
10716 | * @plane: drm plane | |
10717 | * @state: new plane state | |
10718 | * | |
10719 | * Check current plane state versus the new one to determine whether | |
10720 | * watermarks need to be recalculated. | |
10721 | * | |
10722 | * Returns true or false. | |
10723 | */ | |
10724 | static bool intel_wm_need_update(struct drm_plane *plane, | |
10725 | struct drm_plane_state *state) | |
10726 | { | |
10727 | struct intel_plane_state *new = to_intel_plane_state(state); | |
10728 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
10729 | ||
10730 | /* Update watermarks on tiling or size changes. */ | |
936e71e3 | 10731 | if (new->base.visible != cur->base.visible) |
5a21b665 DV |
10732 | return true; |
10733 | ||
10734 | if (!cur->base.fb || !new->base.fb) | |
10735 | return false; | |
10736 | ||
bae781b2 | 10737 | if (cur->base.fb->modifier != new->base.fb->modifier || |
5a21b665 | 10738 | cur->base.rotation != new->base.rotation || |
936e71e3 VS |
10739 | drm_rect_width(&new->base.src) != drm_rect_width(&cur->base.src) || |
10740 | drm_rect_height(&new->base.src) != drm_rect_height(&cur->base.src) || | |
10741 | drm_rect_width(&new->base.dst) != drm_rect_width(&cur->base.dst) || | |
10742 | drm_rect_height(&new->base.dst) != drm_rect_height(&cur->base.dst)) | |
5a21b665 DV |
10743 | return true; |
10744 | ||
10745 | return false; | |
10746 | } | |
10747 | ||
10748 | static bool needs_scaling(struct intel_plane_state *state) | |
10749 | { | |
936e71e3 VS |
10750 | int src_w = drm_rect_width(&state->base.src) >> 16; |
10751 | int src_h = drm_rect_height(&state->base.src) >> 16; | |
10752 | int dst_w = drm_rect_width(&state->base.dst); | |
10753 | int dst_h = drm_rect_height(&state->base.dst); | |
5a21b665 DV |
10754 | |
10755 | return (src_w != dst_w || src_h != dst_h); | |
10756 | } | |
d21fbe87 | 10757 | |
da20eabd ML |
10758 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
10759 | struct drm_plane_state *plane_state) | |
10760 | { | |
ab1d3a0e | 10761 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
10762 | struct drm_crtc *crtc = crtc_state->crtc; |
10763 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e9728bd8 | 10764 | struct intel_plane *plane = to_intel_plane(plane_state->plane); |
da20eabd | 10765 | struct drm_device *dev = crtc->dev; |
ed4a6a7c | 10766 | struct drm_i915_private *dev_priv = to_i915(dev); |
da20eabd | 10767 | struct intel_plane_state *old_plane_state = |
e9728bd8 | 10768 | to_intel_plane_state(plane->base.state); |
da20eabd ML |
10769 | bool mode_changed = needs_modeset(crtc_state); |
10770 | bool was_crtc_enabled = crtc->state->active; | |
10771 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
10772 | bool turn_off, turn_on, visible, was_visible; |
10773 | struct drm_framebuffer *fb = plane_state->fb; | |
78108b7c | 10774 | int ret; |
da20eabd | 10775 | |
e9728bd8 | 10776 | if (INTEL_GEN(dev_priv) >= 9 && plane->id != PLANE_CURSOR) { |
da20eabd ML |
10777 | ret = skl_update_scaler_plane( |
10778 | to_intel_crtc_state(crtc_state), | |
10779 | to_intel_plane_state(plane_state)); | |
10780 | if (ret) | |
10781 | return ret; | |
10782 | } | |
10783 | ||
936e71e3 | 10784 | was_visible = old_plane_state->base.visible; |
1d4258db | 10785 | visible = plane_state->visible; |
da20eabd ML |
10786 | |
10787 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
10788 | was_visible = false; | |
10789 | ||
35c08f43 ML |
10790 | /* |
10791 | * Visibility is calculated as if the crtc was on, but | |
10792 | * after scaler setup everything depends on it being off | |
10793 | * when the crtc isn't active. | |
f818ffea VS |
10794 | * |
10795 | * FIXME this is wrong for watermarks. Watermarks should also | |
10796 | * be computed as if the pipe would be active. Perhaps move | |
10797 | * per-plane wm computation to the .check_plane() hook, and | |
10798 | * only combine the results from all planes in the current place? | |
35c08f43 | 10799 | */ |
e9728bd8 | 10800 | if (!is_crtc_enabled) { |
1d4258db | 10801 | plane_state->visible = visible = false; |
e9728bd8 VS |
10802 | to_intel_crtc_state(crtc_state)->active_planes &= ~BIT(plane->id); |
10803 | } | |
da20eabd ML |
10804 | |
10805 | if (!was_visible && !visible) | |
10806 | return 0; | |
10807 | ||
e8861675 ML |
10808 | if (fb != old_plane_state->base.fb) |
10809 | pipe_config->fb_changed = true; | |
10810 | ||
da20eabd ML |
10811 | turn_off = was_visible && (!visible || mode_changed); |
10812 | turn_on = visible && (!was_visible || mode_changed); | |
10813 | ||
72660ce0 | 10814 | DRM_DEBUG_ATOMIC("[CRTC:%d:%s] has [PLANE:%d:%s] with fb %i\n", |
e9728bd8 VS |
10815 | intel_crtc->base.base.id, intel_crtc->base.name, |
10816 | plane->base.base.id, plane->base.name, | |
72660ce0 | 10817 | fb ? fb->base.id : -1); |
da20eabd | 10818 | |
72660ce0 | 10819 | DRM_DEBUG_ATOMIC("[PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n", |
e9728bd8 | 10820 | plane->base.base.id, plane->base.name, |
72660ce0 | 10821 | was_visible, visible, |
da20eabd ML |
10822 | turn_off, turn_on, mode_changed); |
10823 | ||
caed361d | 10824 | if (turn_on) { |
b4ede6df VS |
10825 | if (INTEL_GEN(dev_priv) < 5) |
10826 | pipe_config->update_wm_pre = true; | |
caed361d VS |
10827 | |
10828 | /* must disable cxsr around plane enable/disable */ | |
e9728bd8 | 10829 | if (plane->id != PLANE_CURSOR) |
caed361d VS |
10830 | pipe_config->disable_cxsr = true; |
10831 | } else if (turn_off) { | |
b4ede6df VS |
10832 | if (INTEL_GEN(dev_priv) < 5) |
10833 | pipe_config->update_wm_post = true; | |
92826fcd | 10834 | |
852eb00d | 10835 | /* must disable cxsr around plane enable/disable */ |
e9728bd8 | 10836 | if (plane->id != PLANE_CURSOR) |
ab1d3a0e | 10837 | pipe_config->disable_cxsr = true; |
e9728bd8 | 10838 | } else if (intel_wm_need_update(&plane->base, plane_state)) { |
b4ede6df VS |
10839 | if (INTEL_GEN(dev_priv) < 5) { |
10840 | /* FIXME bollocks */ | |
10841 | pipe_config->update_wm_pre = true; | |
10842 | pipe_config->update_wm_post = true; | |
10843 | } | |
852eb00d | 10844 | } |
da20eabd | 10845 | |
8be6ca85 | 10846 | if (visible || was_visible) |
e9728bd8 | 10847 | pipe_config->fb_bits |= plane->frontbuffer_bit; |
a9ff8714 | 10848 | |
31ae71fc ML |
10849 | /* |
10850 | * WaCxSRDisabledForSpriteScaling:ivb | |
10851 | * | |
10852 | * cstate->update_wm was already set above, so this flag will | |
10853 | * take effect when we commit and program watermarks. | |
10854 | */ | |
e9728bd8 | 10855 | if (plane->id == PLANE_SPRITE0 && IS_IVYBRIDGE(dev_priv) && |
31ae71fc ML |
10856 | needs_scaling(to_intel_plane_state(plane_state)) && |
10857 | !needs_scaling(old_plane_state)) | |
10858 | pipe_config->disable_lp_wm = true; | |
d21fbe87 | 10859 | |
da20eabd ML |
10860 | return 0; |
10861 | } | |
10862 | ||
6d3a1ce7 ML |
10863 | static bool encoders_cloneable(const struct intel_encoder *a, |
10864 | const struct intel_encoder *b) | |
10865 | { | |
10866 | /* masks could be asymmetric, so check both ways */ | |
10867 | return a == b || (a->cloneable & (1 << b->type) && | |
10868 | b->cloneable & (1 << a->type)); | |
10869 | } | |
10870 | ||
10871 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
10872 | struct intel_crtc *crtc, | |
10873 | struct intel_encoder *encoder) | |
10874 | { | |
10875 | struct intel_encoder *source_encoder; | |
10876 | struct drm_connector *connector; | |
10877 | struct drm_connector_state *connector_state; | |
10878 | int i; | |
10879 | ||
10880 | for_each_connector_in_state(state, connector, connector_state, i) { | |
10881 | if (connector_state->crtc != &crtc->base) | |
10882 | continue; | |
10883 | ||
10884 | source_encoder = | |
10885 | to_intel_encoder(connector_state->best_encoder); | |
10886 | if (!encoders_cloneable(encoder, source_encoder)) | |
10887 | return false; | |
10888 | } | |
10889 | ||
10890 | return true; | |
10891 | } | |
10892 | ||
6d3a1ce7 ML |
10893 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, |
10894 | struct drm_crtc_state *crtc_state) | |
10895 | { | |
cf5a15be | 10896 | struct drm_device *dev = crtc->dev; |
fac5e23e | 10897 | struct drm_i915_private *dev_priv = to_i915(dev); |
6d3a1ce7 | 10898 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
10899 | struct intel_crtc_state *pipe_config = |
10900 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 10901 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 10902 | int ret; |
6d3a1ce7 ML |
10903 | bool mode_changed = needs_modeset(crtc_state); |
10904 | ||
852eb00d | 10905 | if (mode_changed && !crtc_state->active) |
caed361d | 10906 | pipe_config->update_wm_post = true; |
eddfcbcd | 10907 | |
ad421372 ML |
10908 | if (mode_changed && crtc_state->enable && |
10909 | dev_priv->display.crtc_compute_clock && | |
8106ddbd | 10910 | !WARN_ON(pipe_config->shared_dpll)) { |
ad421372 ML |
10911 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
10912 | pipe_config); | |
10913 | if (ret) | |
10914 | return ret; | |
10915 | } | |
10916 | ||
82cf435b LL |
10917 | if (crtc_state->color_mgmt_changed) { |
10918 | ret = intel_color_check(crtc, crtc_state); | |
10919 | if (ret) | |
10920 | return ret; | |
e7852a4b LL |
10921 | |
10922 | /* | |
10923 | * Changing color management on Intel hardware is | |
10924 | * handled as part of planes update. | |
10925 | */ | |
10926 | crtc_state->planes_changed = true; | |
82cf435b LL |
10927 | } |
10928 | ||
e435d6e5 | 10929 | ret = 0; |
86c8bbbe | 10930 | if (dev_priv->display.compute_pipe_wm) { |
e3bddded | 10931 | ret = dev_priv->display.compute_pipe_wm(pipe_config); |
ed4a6a7c MR |
10932 | if (ret) { |
10933 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
10934 | return ret; | |
10935 | } | |
10936 | } | |
10937 | ||
10938 | if (dev_priv->display.compute_intermediate_wm && | |
10939 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
10940 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
10941 | return 0; | |
10942 | ||
10943 | /* | |
10944 | * Calculate 'intermediate' watermarks that satisfy both the | |
10945 | * old state and the new state. We can program these | |
10946 | * immediately. | |
10947 | */ | |
6315b5d3 | 10948 | ret = dev_priv->display.compute_intermediate_wm(dev, |
ed4a6a7c MR |
10949 | intel_crtc, |
10950 | pipe_config); | |
10951 | if (ret) { | |
10952 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 10953 | return ret; |
ed4a6a7c | 10954 | } |
e3d5457c VS |
10955 | } else if (dev_priv->display.compute_intermediate_wm) { |
10956 | if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9) | |
10957 | pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; | |
86c8bbbe MR |
10958 | } |
10959 | ||
6315b5d3 | 10960 | if (INTEL_GEN(dev_priv) >= 9) { |
e435d6e5 ML |
10961 | if (mode_changed) |
10962 | ret = skl_update_scaler_crtc(pipe_config); | |
10963 | ||
10964 | if (!ret) | |
6ebc6923 | 10965 | ret = intel_atomic_setup_scalers(dev_priv, intel_crtc, |
e435d6e5 ML |
10966 | pipe_config); |
10967 | } | |
10968 | ||
10969 | return ret; | |
6d3a1ce7 ML |
10970 | } |
10971 | ||
65b38e0d | 10972 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 | 10973 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
5a21b665 DV |
10974 | .atomic_begin = intel_begin_crtc_commit, |
10975 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 10976 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
10977 | }; |
10978 | ||
d29b2f9d ACO |
10979 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
10980 | { | |
10981 | struct intel_connector *connector; | |
10982 | ||
10983 | for_each_intel_connector(dev, connector) { | |
8863dc7f DV |
10984 | if (connector->base.state->crtc) |
10985 | drm_connector_unreference(&connector->base); | |
10986 | ||
d29b2f9d ACO |
10987 | if (connector->base.encoder) { |
10988 | connector->base.state->best_encoder = | |
10989 | connector->base.encoder; | |
10990 | connector->base.state->crtc = | |
10991 | connector->base.encoder->crtc; | |
8863dc7f DV |
10992 | |
10993 | drm_connector_reference(&connector->base); | |
d29b2f9d ACO |
10994 | } else { |
10995 | connector->base.state->best_encoder = NULL; | |
10996 | connector->base.state->crtc = NULL; | |
10997 | } | |
10998 | } | |
10999 | } | |
11000 | ||
050f7aeb | 11001 | static void |
eba905b2 | 11002 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 11003 | struct intel_crtc_state *pipe_config) |
050f7aeb | 11004 | { |
6a2a5c5d | 11005 | const struct drm_display_info *info = &connector->base.display_info; |
050f7aeb DV |
11006 | int bpp = pipe_config->pipe_bpp; |
11007 | ||
11008 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
6a2a5c5d VS |
11009 | connector->base.base.id, |
11010 | connector->base.name); | |
050f7aeb DV |
11011 | |
11012 | /* Don't use an invalid EDID bpc value */ | |
6a2a5c5d | 11013 | if (info->bpc != 0 && info->bpc * 3 < bpp) { |
050f7aeb | 11014 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", |
6a2a5c5d VS |
11015 | bpp, info->bpc * 3); |
11016 | pipe_config->pipe_bpp = info->bpc * 3; | |
050f7aeb DV |
11017 | } |
11018 | ||
196f954e | 11019 | /* Clamp bpp to 8 on screens without EDID 1.4 */ |
6a2a5c5d | 11020 | if (info->bpc == 0 && bpp > 24) { |
196f954e MK |
11021 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", |
11022 | bpp); | |
11023 | pipe_config->pipe_bpp = 24; | |
050f7aeb DV |
11024 | } |
11025 | } | |
11026 | ||
4e53c2e0 | 11027 | static int |
050f7aeb | 11028 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 11029 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 11030 | { |
9beb5fea | 11031 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
1486017f | 11032 | struct drm_atomic_state *state; |
da3ced29 ACO |
11033 | struct drm_connector *connector; |
11034 | struct drm_connector_state *connector_state; | |
1486017f | 11035 | int bpp, i; |
4e53c2e0 | 11036 | |
9beb5fea TU |
11037 | if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) || |
11038 | IS_CHERRYVIEW(dev_priv))) | |
4e53c2e0 | 11039 | bpp = 10*3; |
9beb5fea | 11040 | else if (INTEL_GEN(dev_priv) >= 5) |
d328c9d7 DV |
11041 | bpp = 12*3; |
11042 | else | |
11043 | bpp = 8*3; | |
11044 | ||
4e53c2e0 | 11045 | |
4e53c2e0 DV |
11046 | pipe_config->pipe_bpp = bpp; |
11047 | ||
1486017f ACO |
11048 | state = pipe_config->base.state; |
11049 | ||
4e53c2e0 | 11050 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
11051 | for_each_connector_in_state(state, connector, connector_state, i) { |
11052 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
11053 | continue; |
11054 | ||
da3ced29 ACO |
11055 | connected_sink_compute_bpp(to_intel_connector(connector), |
11056 | pipe_config); | |
4e53c2e0 DV |
11057 | } |
11058 | ||
11059 | return bpp; | |
11060 | } | |
11061 | ||
644db711 DV |
11062 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
11063 | { | |
11064 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
11065 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 11066 | mode->crtc_clock, |
644db711 DV |
11067 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
11068 | mode->crtc_hsync_end, mode->crtc_htotal, | |
11069 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
11070 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
11071 | } | |
11072 | ||
f6982332 TU |
11073 | static inline void |
11074 | intel_dump_m_n_config(struct intel_crtc_state *pipe_config, char *id, | |
a4309657 | 11075 | unsigned int lane_count, struct intel_link_m_n *m_n) |
f6982332 | 11076 | { |
a4309657 TU |
11077 | DRM_DEBUG_KMS("%s: lanes: %i; gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
11078 | id, lane_count, | |
f6982332 TU |
11079 | m_n->gmch_m, m_n->gmch_n, |
11080 | m_n->link_m, m_n->link_n, m_n->tu); | |
11081 | } | |
11082 | ||
c0b03411 | 11083 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 11084 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
11085 | const char *context) |
11086 | { | |
6a60cd87 | 11087 | struct drm_device *dev = crtc->base.dev; |
4f8036a2 | 11088 | struct drm_i915_private *dev_priv = to_i915(dev); |
6a60cd87 CK |
11089 | struct drm_plane *plane; |
11090 | struct intel_plane *intel_plane; | |
11091 | struct intel_plane_state *state; | |
11092 | struct drm_framebuffer *fb; | |
11093 | ||
66766e4f TU |
11094 | DRM_DEBUG_KMS("[CRTC:%d:%s]%s\n", |
11095 | crtc->base.base.id, crtc->base.name, context); | |
c0b03411 | 11096 | |
2c89429e TU |
11097 | DRM_DEBUG_KMS("cpu_transcoder: %s, pipe bpp: %i, dithering: %i\n", |
11098 | transcoder_name(pipe_config->cpu_transcoder), | |
c0b03411 | 11099 | pipe_config->pipe_bpp, pipe_config->dither); |
a4309657 TU |
11100 | |
11101 | if (pipe_config->has_pch_encoder) | |
11102 | intel_dump_m_n_config(pipe_config, "fdi", | |
11103 | pipe_config->fdi_lanes, | |
11104 | &pipe_config->fdi_m_n); | |
f6982332 TU |
11105 | |
11106 | if (intel_crtc_has_dp_encoder(pipe_config)) { | |
a4309657 TU |
11107 | intel_dump_m_n_config(pipe_config, "dp m_n", |
11108 | pipe_config->lane_count, &pipe_config->dp_m_n); | |
d806e682 TU |
11109 | if (pipe_config->has_drrs) |
11110 | intel_dump_m_n_config(pipe_config, "dp m2_n2", | |
11111 | pipe_config->lane_count, | |
11112 | &pipe_config->dp_m2_n2); | |
f6982332 | 11113 | } |
b95af8be | 11114 | |
55072d19 | 11115 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
2c89429e | 11116 | pipe_config->has_audio, pipe_config->has_infoframe); |
55072d19 | 11117 | |
c0b03411 | 11118 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 11119 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 11120 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
11121 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
11122 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
a7d1b3f4 | 11123 | DRM_DEBUG_KMS("port clock: %d, pipe src size: %dx%d, pixel rate %d\n", |
2c89429e | 11124 | pipe_config->port_clock, |
a7d1b3f4 VS |
11125 | pipe_config->pipe_src_w, pipe_config->pipe_src_h, |
11126 | pipe_config->pixel_rate); | |
dd2f616d TU |
11127 | |
11128 | if (INTEL_GEN(dev_priv) >= 9) | |
11129 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", | |
11130 | crtc->num_scalers, | |
11131 | pipe_config->scaler_state.scaler_users, | |
11132 | pipe_config->scaler_state.scaler_id); | |
a74f8375 TU |
11133 | |
11134 | if (HAS_GMCH_DISPLAY(dev_priv)) | |
11135 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", | |
11136 | pipe_config->gmch_pfit.control, | |
11137 | pipe_config->gmch_pfit.pgm_ratios, | |
11138 | pipe_config->gmch_pfit.lvds_border_bits); | |
11139 | else | |
11140 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", | |
11141 | pipe_config->pch_pfit.pos, | |
11142 | pipe_config->pch_pfit.size, | |
08c4d7fc | 11143 | enableddisabled(pipe_config->pch_pfit.enabled)); |
a74f8375 | 11144 | |
2c89429e TU |
11145 | DRM_DEBUG_KMS("ips: %i, double wide: %i\n", |
11146 | pipe_config->ips_enabled, pipe_config->double_wide); | |
6a60cd87 | 11147 | |
f50b79f0 | 11148 | intel_dpll_dump_hw_state(dev_priv, &pipe_config->dpll_hw_state); |
415ff0f6 | 11149 | |
6a60cd87 CK |
11150 | DRM_DEBUG_KMS("planes on this crtc\n"); |
11151 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
b3c11ac2 | 11152 | struct drm_format_name_buf format_name; |
6a60cd87 CK |
11153 | intel_plane = to_intel_plane(plane); |
11154 | if (intel_plane->pipe != crtc->pipe) | |
11155 | continue; | |
11156 | ||
11157 | state = to_intel_plane_state(plane->state); | |
11158 | fb = state->base.fb; | |
11159 | if (!fb) { | |
1d577e02 VS |
11160 | DRM_DEBUG_KMS("[PLANE:%d:%s] disabled, scaler_id = %d\n", |
11161 | plane->base.id, plane->name, state->scaler_id); | |
6a60cd87 CK |
11162 | continue; |
11163 | } | |
11164 | ||
dd2f616d TU |
11165 | DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d, fb = %ux%u format = %s\n", |
11166 | plane->base.id, plane->name, | |
b3c11ac2 | 11167 | fb->base.id, fb->width, fb->height, |
438b74a5 | 11168 | drm_get_format_name(fb->format->format, &format_name)); |
dd2f616d TU |
11169 | if (INTEL_GEN(dev_priv) >= 9) |
11170 | DRM_DEBUG_KMS("\tscaler:%d src %dx%d+%d+%d dst %dx%d+%d+%d\n", | |
11171 | state->scaler_id, | |
11172 | state->base.src.x1 >> 16, | |
11173 | state->base.src.y1 >> 16, | |
11174 | drm_rect_width(&state->base.src) >> 16, | |
11175 | drm_rect_height(&state->base.src) >> 16, | |
11176 | state->base.dst.x1, state->base.dst.y1, | |
11177 | drm_rect_width(&state->base.dst), | |
11178 | drm_rect_height(&state->base.dst)); | |
6a60cd87 | 11179 | } |
c0b03411 DV |
11180 | } |
11181 | ||
5448a00d | 11182 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 11183 | { |
5448a00d | 11184 | struct drm_device *dev = state->dev; |
da3ced29 | 11185 | struct drm_connector *connector; |
00f0b378 | 11186 | unsigned int used_ports = 0; |
477321e0 | 11187 | unsigned int used_mst_ports = 0; |
00f0b378 VS |
11188 | |
11189 | /* | |
11190 | * Walk the connector list instead of the encoder | |
11191 | * list to detect the problem on ddi platforms | |
11192 | * where there's just one encoder per digital port. | |
11193 | */ | |
0bff4858 VS |
11194 | drm_for_each_connector(connector, dev) { |
11195 | struct drm_connector_state *connector_state; | |
11196 | struct intel_encoder *encoder; | |
11197 | ||
11198 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
11199 | if (!connector_state) | |
11200 | connector_state = connector->state; | |
11201 | ||
5448a00d | 11202 | if (!connector_state->best_encoder) |
00f0b378 VS |
11203 | continue; |
11204 | ||
5448a00d ACO |
11205 | encoder = to_intel_encoder(connector_state->best_encoder); |
11206 | ||
11207 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
11208 | |
11209 | switch (encoder->type) { | |
11210 | unsigned int port_mask; | |
11211 | case INTEL_OUTPUT_UNKNOWN: | |
4f8036a2 | 11212 | if (WARN_ON(!HAS_DDI(to_i915(dev)))) |
00f0b378 | 11213 | break; |
cca0502b | 11214 | case INTEL_OUTPUT_DP: |
00f0b378 VS |
11215 | case INTEL_OUTPUT_HDMI: |
11216 | case INTEL_OUTPUT_EDP: | |
11217 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
11218 | ||
11219 | /* the same port mustn't appear more than once */ | |
11220 | if (used_ports & port_mask) | |
11221 | return false; | |
11222 | ||
11223 | used_ports |= port_mask; | |
477321e0 VS |
11224 | break; |
11225 | case INTEL_OUTPUT_DP_MST: | |
11226 | used_mst_ports |= | |
11227 | 1 << enc_to_mst(&encoder->base)->primary->port; | |
11228 | break; | |
00f0b378 VS |
11229 | default: |
11230 | break; | |
11231 | } | |
11232 | } | |
11233 | ||
477321e0 VS |
11234 | /* can't mix MST and SST/HDMI on the same port */ |
11235 | if (used_ports & used_mst_ports) | |
11236 | return false; | |
11237 | ||
00f0b378 VS |
11238 | return true; |
11239 | } | |
11240 | ||
83a57153 ACO |
11241 | static void |
11242 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
11243 | { | |
ff32c54e VS |
11244 | struct drm_i915_private *dev_priv = |
11245 | to_i915(crtc_state->base.crtc->dev); | |
663a3640 | 11246 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 | 11247 | struct intel_dpll_hw_state dpll_hw_state; |
8106ddbd | 11248 | struct intel_shared_dpll *shared_dpll; |
ff32c54e | 11249 | struct intel_crtc_wm_state wm_state; |
c4e2d043 | 11250 | bool force_thru; |
83a57153 | 11251 | |
7546a384 ACO |
11252 | /* FIXME: before the switch to atomic started, a new pipe_config was |
11253 | * kzalloc'd. Code that depends on any field being zero should be | |
11254 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
11255 | * only fields that are know to not cause problems are preserved. */ | |
11256 | ||
663a3640 | 11257 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
11258 | shared_dpll = crtc_state->shared_dpll; |
11259 | dpll_hw_state = crtc_state->dpll_hw_state; | |
c4e2d043 | 11260 | force_thru = crtc_state->pch_pfit.force_thru; |
ff32c54e VS |
11261 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
11262 | wm_state = crtc_state->wm; | |
4978cc93 | 11263 | |
d2fa80a5 CW |
11264 | /* Keep base drm_crtc_state intact, only clear our extended struct */ |
11265 | BUILD_BUG_ON(offsetof(struct intel_crtc_state, base)); | |
11266 | memset(&crtc_state->base + 1, 0, | |
11267 | sizeof(*crtc_state) - sizeof(crtc_state->base)); | |
4978cc93 | 11268 | |
663a3640 | 11269 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
11270 | crtc_state->shared_dpll = shared_dpll; |
11271 | crtc_state->dpll_hw_state = dpll_hw_state; | |
c4e2d043 | 11272 | crtc_state->pch_pfit.force_thru = force_thru; |
ff32c54e VS |
11273 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
11274 | crtc_state->wm = wm_state; | |
83a57153 ACO |
11275 | } |
11276 | ||
548ee15b | 11277 | static int |
b8cecdf5 | 11278 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 11279 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 11280 | { |
b359283a | 11281 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 11282 | struct intel_encoder *encoder; |
da3ced29 | 11283 | struct drm_connector *connector; |
0b901879 | 11284 | struct drm_connector_state *connector_state; |
d328c9d7 | 11285 | int base_bpp, ret = -EINVAL; |
0b901879 | 11286 | int i; |
e29c22c0 | 11287 | bool retry = true; |
ee7b9f93 | 11288 | |
83a57153 | 11289 | clear_intel_crtc_state(pipe_config); |
7758a113 | 11290 | |
e143a21c DV |
11291 | pipe_config->cpu_transcoder = |
11292 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 11293 | |
2960bc9c ID |
11294 | /* |
11295 | * Sanitize sync polarity flags based on requested ones. If neither | |
11296 | * positive or negative polarity is requested, treat this as meaning | |
11297 | * negative polarity. | |
11298 | */ | |
2d112de7 | 11299 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 11300 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 11301 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 11302 | |
2d112de7 | 11303 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 11304 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 11305 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 11306 | |
d328c9d7 DV |
11307 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
11308 | pipe_config); | |
11309 | if (base_bpp < 0) | |
4e53c2e0 DV |
11310 | goto fail; |
11311 | ||
e41a56be VS |
11312 | /* |
11313 | * Determine the real pipe dimensions. Note that stereo modes can | |
11314 | * increase the actual pipe size due to the frame doubling and | |
11315 | * insertion of additional space for blanks between the frame. This | |
11316 | * is stored in the crtc timings. We use the requested mode to do this | |
11317 | * computation to clearly distinguish it from the adjusted mode, which | |
11318 | * can be changed by the connectors in the below retry loop. | |
11319 | */ | |
196cd5d3 | 11320 | drm_mode_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
11321 | &pipe_config->pipe_src_w, |
11322 | &pipe_config->pipe_src_h); | |
e41a56be | 11323 | |
253c84c8 VS |
11324 | for_each_connector_in_state(state, connector, connector_state, i) { |
11325 | if (connector_state->crtc != crtc) | |
11326 | continue; | |
11327 | ||
11328 | encoder = to_intel_encoder(connector_state->best_encoder); | |
11329 | ||
e25148d0 VS |
11330 | if (!check_single_encoder_cloning(state, to_intel_crtc(crtc), encoder)) { |
11331 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
11332 | goto fail; | |
11333 | } | |
11334 | ||
253c84c8 VS |
11335 | /* |
11336 | * Determine output_types before calling the .compute_config() | |
11337 | * hooks so that the hooks can use this information safely. | |
11338 | */ | |
11339 | pipe_config->output_types |= 1 << encoder->type; | |
11340 | } | |
11341 | ||
e29c22c0 | 11342 | encoder_retry: |
ef1b460d | 11343 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 11344 | pipe_config->port_clock = 0; |
ef1b460d | 11345 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 11346 | |
135c81b8 | 11347 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
11348 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
11349 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 11350 | |
7758a113 DV |
11351 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
11352 | * adjust it according to limitations or connector properties, and also | |
11353 | * a chance to reject the mode entirely. | |
47f1c6c9 | 11354 | */ |
da3ced29 | 11355 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 11356 | if (connector_state->crtc != crtc) |
7758a113 | 11357 | continue; |
7ae89233 | 11358 | |
0b901879 ACO |
11359 | encoder = to_intel_encoder(connector_state->best_encoder); |
11360 | ||
0a478c27 | 11361 | if (!(encoder->compute_config(encoder, pipe_config, connector_state))) { |
efea6e8e | 11362 | DRM_DEBUG_KMS("Encoder config failure\n"); |
7758a113 DV |
11363 | goto fail; |
11364 | } | |
ee7b9f93 | 11365 | } |
47f1c6c9 | 11366 | |
ff9a6750 DV |
11367 | /* Set default port clock if not overwritten by the encoder. Needs to be |
11368 | * done afterwards in case the encoder adjusts the mode. */ | |
11369 | if (!pipe_config->port_clock) | |
2d112de7 | 11370 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 11371 | * pipe_config->pixel_multiplier; |
ff9a6750 | 11372 | |
a43f6e0f | 11373 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 11374 | if (ret < 0) { |
7758a113 DV |
11375 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
11376 | goto fail; | |
ee7b9f93 | 11377 | } |
e29c22c0 DV |
11378 | |
11379 | if (ret == RETRY) { | |
11380 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
11381 | ret = -EINVAL; | |
11382 | goto fail; | |
11383 | } | |
11384 | ||
11385 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
11386 | retry = false; | |
11387 | goto encoder_retry; | |
11388 | } | |
11389 | ||
e8fa4270 | 11390 | /* Dithering seems to not pass-through bits correctly when it should, so |
611032bf MN |
11391 | * only enable it on 6bpc panels and when its not a compliance |
11392 | * test requesting 6bpc video pattern. | |
11393 | */ | |
11394 | pipe_config->dither = (pipe_config->pipe_bpp == 6*3) && | |
11395 | !pipe_config->dither_force_disable; | |
62f0ace5 | 11396 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 11397 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 11398 | |
7758a113 | 11399 | fail: |
548ee15b | 11400 | return ret; |
ee7b9f93 | 11401 | } |
47f1c6c9 | 11402 | |
ea9d758d | 11403 | static void |
4740b0f2 | 11404 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 11405 | { |
0a9ab303 ACO |
11406 | struct drm_crtc *crtc; |
11407 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 11408 | int i; |
ea9d758d | 11409 | |
7668851f | 11410 | /* Double check state. */ |
8a75d157 | 11411 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 11412 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
11413 | |
11414 | /* Update hwmode for vblank functions */ | |
11415 | if (crtc->state->active) | |
11416 | crtc->hwmode = crtc->state->adjusted_mode; | |
11417 | else | |
11418 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
11419 | |
11420 | /* | |
11421 | * Update legacy state to satisfy fbc code. This can | |
11422 | * be removed when fbc uses the atomic state. | |
11423 | */ | |
11424 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
11425 | struct drm_plane_state *plane_state = crtc->primary->state; | |
11426 | ||
11427 | crtc->primary->fb = plane_state->fb; | |
11428 | crtc->x = plane_state->src_x >> 16; | |
11429 | crtc->y = plane_state->src_y >> 16; | |
11430 | } | |
ea9d758d | 11431 | } |
ea9d758d DV |
11432 | } |
11433 | ||
3bd26263 | 11434 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 11435 | { |
3bd26263 | 11436 | int diff; |
f1f644dc JB |
11437 | |
11438 | if (clock1 == clock2) | |
11439 | return true; | |
11440 | ||
11441 | if (!clock1 || !clock2) | |
11442 | return false; | |
11443 | ||
11444 | diff = abs(clock1 - clock2); | |
11445 | ||
11446 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
11447 | return true; | |
11448 | ||
11449 | return false; | |
11450 | } | |
11451 | ||
cfb23ed6 ML |
11452 | static bool |
11453 | intel_compare_m_n(unsigned int m, unsigned int n, | |
11454 | unsigned int m2, unsigned int n2, | |
11455 | bool exact) | |
11456 | { | |
11457 | if (m == m2 && n == n2) | |
11458 | return true; | |
11459 | ||
11460 | if (exact || !m || !n || !m2 || !n2) | |
11461 | return false; | |
11462 | ||
11463 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
11464 | ||
31d10b57 ML |
11465 | if (n > n2) { |
11466 | while (n > n2) { | |
cfb23ed6 ML |
11467 | m2 <<= 1; |
11468 | n2 <<= 1; | |
11469 | } | |
31d10b57 ML |
11470 | } else if (n < n2) { |
11471 | while (n < n2) { | |
cfb23ed6 ML |
11472 | m <<= 1; |
11473 | n <<= 1; | |
11474 | } | |
11475 | } | |
11476 | ||
31d10b57 ML |
11477 | if (n != n2) |
11478 | return false; | |
11479 | ||
11480 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
11481 | } |
11482 | ||
11483 | static bool | |
11484 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
11485 | struct intel_link_m_n *m2_n2, | |
11486 | bool adjust) | |
11487 | { | |
11488 | if (m_n->tu == m2_n2->tu && | |
11489 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
11490 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
11491 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
11492 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
11493 | if (adjust) | |
11494 | *m2_n2 = *m_n; | |
11495 | ||
11496 | return true; | |
11497 | } | |
11498 | ||
11499 | return false; | |
11500 | } | |
11501 | ||
4e8048f8 TU |
11502 | static void __printf(3, 4) |
11503 | pipe_config_err(bool adjust, const char *name, const char *format, ...) | |
11504 | { | |
11505 | char *level; | |
11506 | unsigned int category; | |
11507 | struct va_format vaf; | |
11508 | va_list args; | |
11509 | ||
11510 | if (adjust) { | |
11511 | level = KERN_DEBUG; | |
11512 | category = DRM_UT_KMS; | |
11513 | } else { | |
11514 | level = KERN_ERR; | |
11515 | category = DRM_UT_NONE; | |
11516 | } | |
11517 | ||
11518 | va_start(args, format); | |
11519 | vaf.fmt = format; | |
11520 | vaf.va = &args; | |
11521 | ||
11522 | drm_printk(level, category, "mismatch in %s %pV", name, &vaf); | |
11523 | ||
11524 | va_end(args); | |
11525 | } | |
11526 | ||
0e8ffe1b | 11527 | static bool |
6315b5d3 | 11528 | intel_pipe_config_compare(struct drm_i915_private *dev_priv, |
5cec258b | 11529 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
11530 | struct intel_crtc_state *pipe_config, |
11531 | bool adjust) | |
0e8ffe1b | 11532 | { |
cfb23ed6 ML |
11533 | bool ret = true; |
11534 | ||
66e985c0 DV |
11535 | #define PIPE_CONF_CHECK_X(name) \ |
11536 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 11537 | pipe_config_err(adjust, __stringify(name), \ |
66e985c0 DV |
11538 | "(expected 0x%08x, found 0x%08x)\n", \ |
11539 | current_config->name, \ | |
11540 | pipe_config->name); \ | |
cfb23ed6 | 11541 | ret = false; \ |
66e985c0 DV |
11542 | } |
11543 | ||
08a24034 DV |
11544 | #define PIPE_CONF_CHECK_I(name) \ |
11545 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 11546 | pipe_config_err(adjust, __stringify(name), \ |
08a24034 DV |
11547 | "(expected %i, found %i)\n", \ |
11548 | current_config->name, \ | |
11549 | pipe_config->name); \ | |
cfb23ed6 ML |
11550 | ret = false; \ |
11551 | } | |
11552 | ||
8106ddbd ACO |
11553 | #define PIPE_CONF_CHECK_P(name) \ |
11554 | if (current_config->name != pipe_config->name) { \ | |
4e8048f8 | 11555 | pipe_config_err(adjust, __stringify(name), \ |
8106ddbd ACO |
11556 | "(expected %p, found %p)\n", \ |
11557 | current_config->name, \ | |
11558 | pipe_config->name); \ | |
11559 | ret = false; \ | |
11560 | } | |
11561 | ||
cfb23ed6 ML |
11562 | #define PIPE_CONF_CHECK_M_N(name) \ |
11563 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
11564 | &pipe_config->name,\ | |
11565 | adjust)) { \ | |
4e8048f8 | 11566 | pipe_config_err(adjust, __stringify(name), \ |
cfb23ed6 ML |
11567 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
11568 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
11569 | current_config->name.tu, \ | |
11570 | current_config->name.gmch_m, \ | |
11571 | current_config->name.gmch_n, \ | |
11572 | current_config->name.link_m, \ | |
11573 | current_config->name.link_n, \ | |
11574 | pipe_config->name.tu, \ | |
11575 | pipe_config->name.gmch_m, \ | |
11576 | pipe_config->name.gmch_n, \ | |
11577 | pipe_config->name.link_m, \ | |
11578 | pipe_config->name.link_n); \ | |
11579 | ret = false; \ | |
11580 | } | |
11581 | ||
55c561a7 DV |
11582 | /* This is required for BDW+ where there is only one set of registers for |
11583 | * switching between high and low RR. | |
11584 | * This macro can be used whenever a comparison has to be made between one | |
11585 | * hw state and multiple sw state variables. | |
11586 | */ | |
cfb23ed6 ML |
11587 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ |
11588 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
11589 | &pipe_config->name, adjust) && \ | |
11590 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
11591 | &pipe_config->name, adjust)) { \ | |
4e8048f8 | 11592 | pipe_config_err(adjust, __stringify(name), \ |
cfb23ed6 ML |
11593 | "(expected tu %i gmch %i/%i link %i/%i, " \ |
11594 | "or tu %i gmch %i/%i link %i/%i, " \ | |
11595 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
11596 | current_config->name.tu, \ | |
11597 | current_config->name.gmch_m, \ | |
11598 | current_config->name.gmch_n, \ | |
11599 | current_config->name.link_m, \ | |
11600 | current_config->name.link_n, \ | |
11601 | current_config->alt_name.tu, \ | |
11602 | current_config->alt_name.gmch_m, \ | |
11603 | current_config->alt_name.gmch_n, \ | |
11604 | current_config->alt_name.link_m, \ | |
11605 | current_config->alt_name.link_n, \ | |
11606 | pipe_config->name.tu, \ | |
11607 | pipe_config->name.gmch_m, \ | |
11608 | pipe_config->name.gmch_n, \ | |
11609 | pipe_config->name.link_m, \ | |
11610 | pipe_config->name.link_n); \ | |
11611 | ret = false; \ | |
88adfff1 DV |
11612 | } |
11613 | ||
1bd1bd80 DV |
11614 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
11615 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
4e8048f8 TU |
11616 | pipe_config_err(adjust, __stringify(name), \ |
11617 | "(%x) (expected %i, found %i)\n", \ | |
11618 | (mask), \ | |
1bd1bd80 DV |
11619 | current_config->name & (mask), \ |
11620 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 11621 | ret = false; \ |
1bd1bd80 DV |
11622 | } |
11623 | ||
5e550656 VS |
11624 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
11625 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
4e8048f8 | 11626 | pipe_config_err(adjust, __stringify(name), \ |
5e550656 VS |
11627 | "(expected %i, found %i)\n", \ |
11628 | current_config->name, \ | |
11629 | pipe_config->name); \ | |
cfb23ed6 | 11630 | ret = false; \ |
5e550656 VS |
11631 | } |
11632 | ||
bb760063 DV |
11633 | #define PIPE_CONF_QUIRK(quirk) \ |
11634 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
11635 | ||
eccb140b DV |
11636 | PIPE_CONF_CHECK_I(cpu_transcoder); |
11637 | ||
08a24034 DV |
11638 | PIPE_CONF_CHECK_I(has_pch_encoder); |
11639 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 11640 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 11641 | |
90a6b7b0 | 11642 | PIPE_CONF_CHECK_I(lane_count); |
95a7a2ae | 11643 | PIPE_CONF_CHECK_X(lane_lat_optim_mask); |
b95af8be | 11644 | |
6315b5d3 | 11645 | if (INTEL_GEN(dev_priv) < 8) { |
cfb23ed6 ML |
11646 | PIPE_CONF_CHECK_M_N(dp_m_n); |
11647 | ||
cfb23ed6 ML |
11648 | if (current_config->has_drrs) |
11649 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
11650 | } else | |
11651 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 11652 | |
253c84c8 | 11653 | PIPE_CONF_CHECK_X(output_types); |
a65347ba | 11654 | |
2d112de7 ACO |
11655 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
11656 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
11657 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
11658 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
11659 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
11660 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 11661 | |
2d112de7 ACO |
11662 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
11663 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
11664 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
11665 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
11666 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
11667 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 11668 | |
c93f54cf | 11669 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 11670 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
772c2a51 | 11671 | if ((INTEL_GEN(dev_priv) < 8 && !IS_HASWELL(dev_priv)) || |
920a14b2 | 11672 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
b5a9fa09 | 11673 | PIPE_CONF_CHECK_I(limited_color_range); |
e43823ec | 11674 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 11675 | |
9ed109a7 DV |
11676 | PIPE_CONF_CHECK_I(has_audio); |
11677 | ||
2d112de7 | 11678 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
11679 | DRM_MODE_FLAG_INTERLACE); |
11680 | ||
bb760063 | 11681 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 11682 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11683 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 11684 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11685 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 11686 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 11687 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 11688 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
11689 | DRM_MODE_FLAG_NVSYNC); |
11690 | } | |
045ac3b5 | 11691 | |
333b8ca8 | 11692 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a | 11693 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
6315b5d3 | 11694 | if (INTEL_GEN(dev_priv) < 4) |
7f7d8dd6 | 11695 | PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); |
333b8ca8 | 11696 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 11697 | |
bfd16b2a ML |
11698 | if (!adjust) { |
11699 | PIPE_CONF_CHECK_I(pipe_src_w); | |
11700 | PIPE_CONF_CHECK_I(pipe_src_h); | |
11701 | ||
11702 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
11703 | if (current_config->pch_pfit.enabled) { | |
11704 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
11705 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
11706 | } | |
2fa2fe9a | 11707 | |
7aefe2b5 | 11708 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
a7d1b3f4 | 11709 | PIPE_CONF_CHECK_CLOCK_FUZZY(pixel_rate); |
7aefe2b5 | 11710 | } |
a1b2278e | 11711 | |
e59150dc | 11712 | /* BDW+ don't expose a synchronous way to read the state */ |
772c2a51 | 11713 | if (IS_HASWELL(dev_priv)) |
e59150dc | 11714 | PIPE_CONF_CHECK_I(ips_enabled); |
42db64ef | 11715 | |
282740f7 VS |
11716 | PIPE_CONF_CHECK_I(double_wide); |
11717 | ||
8106ddbd | 11718 | PIPE_CONF_CHECK_P(shared_dpll); |
66e985c0 | 11719 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 11720 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
11721 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
11722 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 11723 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 11724 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
11725 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
11726 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
11727 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 11728 | |
47eacbab VS |
11729 | PIPE_CONF_CHECK_X(dsi_pll.ctrl); |
11730 | PIPE_CONF_CHECK_X(dsi_pll.div); | |
11731 | ||
9beb5fea | 11732 | if (IS_G4X(dev_priv) || INTEL_GEN(dev_priv) >= 5) |
42571aef VS |
11733 | PIPE_CONF_CHECK_I(pipe_bpp); |
11734 | ||
2d112de7 | 11735 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 11736 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 11737 | |
66e985c0 | 11738 | #undef PIPE_CONF_CHECK_X |
08a24034 | 11739 | #undef PIPE_CONF_CHECK_I |
8106ddbd | 11740 | #undef PIPE_CONF_CHECK_P |
1bd1bd80 | 11741 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 11742 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 11743 | #undef PIPE_CONF_QUIRK |
88adfff1 | 11744 | |
cfb23ed6 | 11745 | return ret; |
0e8ffe1b DV |
11746 | } |
11747 | ||
e3b247da VS |
11748 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
11749 | const struct intel_crtc_state *pipe_config) | |
11750 | { | |
11751 | if (pipe_config->has_pch_encoder) { | |
21a727b3 | 11752 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
e3b247da VS |
11753 | &pipe_config->fdi_m_n); |
11754 | int dotclock = pipe_config->base.adjusted_mode.crtc_clock; | |
11755 | ||
11756 | /* | |
11757 | * FDI already provided one idea for the dotclock. | |
11758 | * Yell if the encoder disagrees. | |
11759 | */ | |
11760 | WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
11761 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
11762 | fdi_dotclock, dotclock); | |
11763 | } | |
11764 | } | |
11765 | ||
c0ead703 ML |
11766 | static void verify_wm_state(struct drm_crtc *crtc, |
11767 | struct drm_crtc_state *new_state) | |
08db6652 | 11768 | { |
6315b5d3 | 11769 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
08db6652 | 11770 | struct skl_ddb_allocation hw_ddb, *sw_ddb; |
3de8a14c | 11771 | struct skl_pipe_wm hw_wm, *sw_wm; |
11772 | struct skl_plane_wm *hw_plane_wm, *sw_plane_wm; | |
11773 | struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry; | |
e7c84544 ML |
11774 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11775 | const enum pipe pipe = intel_crtc->pipe; | |
3de8a14c | 11776 | int plane, level, max_level = ilk_wm_max_level(dev_priv); |
08db6652 | 11777 | |
6315b5d3 | 11778 | if (INTEL_GEN(dev_priv) < 9 || !new_state->active) |
08db6652 DL |
11779 | return; |
11780 | ||
3de8a14c | 11781 | skl_pipe_wm_get_hw_state(crtc, &hw_wm); |
03af79e0 | 11782 | sw_wm = &to_intel_crtc_state(new_state)->wm.skl.optimal; |
3de8a14c | 11783 | |
08db6652 DL |
11784 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); |
11785 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
11786 | ||
e7c84544 | 11787 | /* planes */ |
8b364b41 | 11788 | for_each_universal_plane(dev_priv, pipe, plane) { |
3de8a14c | 11789 | hw_plane_wm = &hw_wm.planes[plane]; |
11790 | sw_plane_wm = &sw_wm->planes[plane]; | |
08db6652 | 11791 | |
3de8a14c | 11792 | /* Watermarks */ |
11793 | for (level = 0; level <= max_level; level++) { | |
11794 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
11795 | &sw_plane_wm->wm[level])) | |
11796 | continue; | |
11797 | ||
11798 | DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11799 | pipe_name(pipe), plane + 1, level, | |
11800 | sw_plane_wm->wm[level].plane_en, | |
11801 | sw_plane_wm->wm[level].plane_res_b, | |
11802 | sw_plane_wm->wm[level].plane_res_l, | |
11803 | hw_plane_wm->wm[level].plane_en, | |
11804 | hw_plane_wm->wm[level].plane_res_b, | |
11805 | hw_plane_wm->wm[level].plane_res_l); | |
11806 | } | |
08db6652 | 11807 | |
3de8a14c | 11808 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, |
11809 | &sw_plane_wm->trans_wm)) { | |
11810 | DRM_ERROR("mismatch in trans WM pipe %c plane %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11811 | pipe_name(pipe), plane + 1, | |
11812 | sw_plane_wm->trans_wm.plane_en, | |
11813 | sw_plane_wm->trans_wm.plane_res_b, | |
11814 | sw_plane_wm->trans_wm.plane_res_l, | |
11815 | hw_plane_wm->trans_wm.plane_en, | |
11816 | hw_plane_wm->trans_wm.plane_res_b, | |
11817 | hw_plane_wm->trans_wm.plane_res_l); | |
11818 | } | |
11819 | ||
11820 | /* DDB */ | |
11821 | hw_ddb_entry = &hw_ddb.plane[pipe][plane]; | |
11822 | sw_ddb_entry = &sw_ddb->plane[pipe][plane]; | |
11823 | ||
11824 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { | |
faccd994 | 11825 | DRM_ERROR("mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u))\n", |
3de8a14c | 11826 | pipe_name(pipe), plane + 1, |
11827 | sw_ddb_entry->start, sw_ddb_entry->end, | |
11828 | hw_ddb_entry->start, hw_ddb_entry->end); | |
11829 | } | |
e7c84544 | 11830 | } |
08db6652 | 11831 | |
27082493 L |
11832 | /* |
11833 | * cursor | |
11834 | * If the cursor plane isn't active, we may not have updated it's ddb | |
11835 | * allocation. In that case since the ddb allocation will be updated | |
11836 | * once the plane becomes visible, we can skip this check | |
11837 | */ | |
11838 | if (intel_crtc->cursor_addr) { | |
3de8a14c | 11839 | hw_plane_wm = &hw_wm.planes[PLANE_CURSOR]; |
11840 | sw_plane_wm = &sw_wm->planes[PLANE_CURSOR]; | |
11841 | ||
11842 | /* Watermarks */ | |
11843 | for (level = 0; level <= max_level; level++) { | |
11844 | if (skl_wm_level_equals(&hw_plane_wm->wm[level], | |
11845 | &sw_plane_wm->wm[level])) | |
11846 | continue; | |
11847 | ||
11848 | DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11849 | pipe_name(pipe), level, | |
11850 | sw_plane_wm->wm[level].plane_en, | |
11851 | sw_plane_wm->wm[level].plane_res_b, | |
11852 | sw_plane_wm->wm[level].plane_res_l, | |
11853 | hw_plane_wm->wm[level].plane_en, | |
11854 | hw_plane_wm->wm[level].plane_res_b, | |
11855 | hw_plane_wm->wm[level].plane_res_l); | |
11856 | } | |
11857 | ||
11858 | if (!skl_wm_level_equals(&hw_plane_wm->trans_wm, | |
11859 | &sw_plane_wm->trans_wm)) { | |
11860 | DRM_ERROR("mismatch in trans WM pipe %c cursor (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n", | |
11861 | pipe_name(pipe), | |
11862 | sw_plane_wm->trans_wm.plane_en, | |
11863 | sw_plane_wm->trans_wm.plane_res_b, | |
11864 | sw_plane_wm->trans_wm.plane_res_l, | |
11865 | hw_plane_wm->trans_wm.plane_en, | |
11866 | hw_plane_wm->trans_wm.plane_res_b, | |
11867 | hw_plane_wm->trans_wm.plane_res_l); | |
11868 | } | |
11869 | ||
11870 | /* DDB */ | |
11871 | hw_ddb_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; | |
11872 | sw_ddb_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
27082493 | 11873 | |
3de8a14c | 11874 | if (!skl_ddb_entry_equal(hw_ddb_entry, sw_ddb_entry)) { |
faccd994 | 11875 | DRM_ERROR("mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u))\n", |
27082493 | 11876 | pipe_name(pipe), |
3de8a14c | 11877 | sw_ddb_entry->start, sw_ddb_entry->end, |
11878 | hw_ddb_entry->start, hw_ddb_entry->end); | |
27082493 | 11879 | } |
08db6652 DL |
11880 | } |
11881 | } | |
11882 | ||
91d1b4bd | 11883 | static void |
677100ce ML |
11884 | verify_connector_state(struct drm_device *dev, |
11885 | struct drm_atomic_state *state, | |
11886 | struct drm_crtc *crtc) | |
8af6cf88 | 11887 | { |
35dd3c64 | 11888 | struct drm_connector *connector; |
677100ce ML |
11889 | struct drm_connector_state *old_conn_state; |
11890 | int i; | |
8af6cf88 | 11891 | |
677100ce | 11892 | for_each_connector_in_state(state, connector, old_conn_state, i) { |
35dd3c64 ML |
11893 | struct drm_encoder *encoder = connector->encoder; |
11894 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 11895 | |
e7c84544 ML |
11896 | if (state->crtc != crtc) |
11897 | continue; | |
11898 | ||
5a21b665 | 11899 | intel_connector_verify_state(to_intel_connector(connector)); |
8af6cf88 | 11900 | |
ad3c558f | 11901 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 11902 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 11903 | } |
91d1b4bd DV |
11904 | } |
11905 | ||
11906 | static void | |
c0ead703 | 11907 | verify_encoder_state(struct drm_device *dev) |
91d1b4bd DV |
11908 | { |
11909 | struct intel_encoder *encoder; | |
11910 | struct intel_connector *connector; | |
8af6cf88 | 11911 | |
b2784e15 | 11912 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 11913 | bool enabled = false; |
4d20cd86 | 11914 | enum pipe pipe; |
8af6cf88 DV |
11915 | |
11916 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
11917 | encoder->base.base.id, | |
8e329a03 | 11918 | encoder->base.name); |
8af6cf88 | 11919 | |
3a3371ff | 11920 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 11921 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
11922 | continue; |
11923 | enabled = true; | |
ad3c558f ML |
11924 | |
11925 | I915_STATE_WARN(connector->base.state->crtc != | |
11926 | encoder->base.crtc, | |
11927 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 11928 | } |
0e32b39c | 11929 | |
e2c719b7 | 11930 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
11931 | "encoder's enabled state mismatch " |
11932 | "(expected %i, found %i)\n", | |
11933 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
11934 | |
11935 | if (!encoder->base.crtc) { | |
4d20cd86 | 11936 | bool active; |
7c60d198 | 11937 | |
4d20cd86 ML |
11938 | active = encoder->get_hw_state(encoder, &pipe); |
11939 | I915_STATE_WARN(active, | |
11940 | "encoder detached but still enabled on pipe %c.\n", | |
11941 | pipe_name(pipe)); | |
7c60d198 | 11942 | } |
8af6cf88 | 11943 | } |
91d1b4bd DV |
11944 | } |
11945 | ||
11946 | static void | |
c0ead703 ML |
11947 | verify_crtc_state(struct drm_crtc *crtc, |
11948 | struct drm_crtc_state *old_crtc_state, | |
11949 | struct drm_crtc_state *new_crtc_state) | |
91d1b4bd | 11950 | { |
e7c84544 | 11951 | struct drm_device *dev = crtc->dev; |
fac5e23e | 11952 | struct drm_i915_private *dev_priv = to_i915(dev); |
91d1b4bd | 11953 | struct intel_encoder *encoder; |
e7c84544 ML |
11954 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
11955 | struct intel_crtc_state *pipe_config, *sw_config; | |
11956 | struct drm_atomic_state *old_state; | |
11957 | bool active; | |
045ac3b5 | 11958 | |
e7c84544 | 11959 | old_state = old_crtc_state->state; |
ec2dc6a0 | 11960 | __drm_atomic_helper_crtc_destroy_state(old_crtc_state); |
e7c84544 ML |
11961 | pipe_config = to_intel_crtc_state(old_crtc_state); |
11962 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
11963 | pipe_config->base.crtc = crtc; | |
11964 | pipe_config->base.state = old_state; | |
8af6cf88 | 11965 | |
78108b7c | 11966 | DRM_DEBUG_KMS("[CRTC:%d:%s]\n", crtc->base.id, crtc->name); |
8af6cf88 | 11967 | |
e7c84544 | 11968 | active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config); |
d62cf62a | 11969 | |
e7c84544 ML |
11970 | /* hw state is inconsistent with the pipe quirk */ |
11971 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
11972 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
11973 | active = new_crtc_state->active; | |
6c49f241 | 11974 | |
e7c84544 ML |
11975 | I915_STATE_WARN(new_crtc_state->active != active, |
11976 | "crtc active state doesn't match with hw state " | |
11977 | "(expected %i, found %i)\n", new_crtc_state->active, active); | |
0e8ffe1b | 11978 | |
e7c84544 ML |
11979 | I915_STATE_WARN(intel_crtc->active != new_crtc_state->active, |
11980 | "transitional active state does not match atomic hw state " | |
11981 | "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active); | |
4d20cd86 | 11982 | |
e7c84544 ML |
11983 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
11984 | enum pipe pipe; | |
4d20cd86 | 11985 | |
e7c84544 ML |
11986 | active = encoder->get_hw_state(encoder, &pipe); |
11987 | I915_STATE_WARN(active != new_crtc_state->active, | |
11988 | "[ENCODER:%i] active %i with crtc active %i\n", | |
11989 | encoder->base.base.id, active, new_crtc_state->active); | |
4d20cd86 | 11990 | |
e7c84544 ML |
11991 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, |
11992 | "Encoder connected to wrong pipe %c\n", | |
11993 | pipe_name(pipe)); | |
4d20cd86 | 11994 | |
253c84c8 VS |
11995 | if (active) { |
11996 | pipe_config->output_types |= 1 << encoder->type; | |
e7c84544 | 11997 | encoder->get_config(encoder, pipe_config); |
253c84c8 | 11998 | } |
e7c84544 | 11999 | } |
53d9f4e9 | 12000 | |
a7d1b3f4 VS |
12001 | intel_crtc_compute_pixel_rate(pipe_config); |
12002 | ||
e7c84544 ML |
12003 | if (!new_crtc_state->active) |
12004 | return; | |
cfb23ed6 | 12005 | |
e7c84544 | 12006 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
e3b247da | 12007 | |
e7c84544 | 12008 | sw_config = to_intel_crtc_state(crtc->state); |
6315b5d3 | 12009 | if (!intel_pipe_config_compare(dev_priv, sw_config, |
e7c84544 ML |
12010 | pipe_config, false)) { |
12011 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); | |
12012 | intel_dump_pipe_config(intel_crtc, pipe_config, | |
12013 | "[hw state]"); | |
12014 | intel_dump_pipe_config(intel_crtc, sw_config, | |
12015 | "[sw state]"); | |
8af6cf88 DV |
12016 | } |
12017 | } | |
12018 | ||
91d1b4bd | 12019 | static void |
c0ead703 ML |
12020 | verify_single_dpll_state(struct drm_i915_private *dev_priv, |
12021 | struct intel_shared_dpll *pll, | |
12022 | struct drm_crtc *crtc, | |
12023 | struct drm_crtc_state *new_state) | |
91d1b4bd | 12024 | { |
91d1b4bd | 12025 | struct intel_dpll_hw_state dpll_hw_state; |
e7c84544 ML |
12026 | unsigned crtc_mask; |
12027 | bool active; | |
5358901f | 12028 | |
e7c84544 | 12029 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
5358901f | 12030 | |
e7c84544 | 12031 | DRM_DEBUG_KMS("%s\n", pll->name); |
5358901f | 12032 | |
e7c84544 | 12033 | active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state); |
5358901f | 12034 | |
e7c84544 ML |
12035 | if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) { |
12036 | I915_STATE_WARN(!pll->on && pll->active_mask, | |
12037 | "pll in active use but not on in sw tracking\n"); | |
12038 | I915_STATE_WARN(pll->on && !pll->active_mask, | |
12039 | "pll is on but not used by any active crtc\n"); | |
12040 | I915_STATE_WARN(pll->on != active, | |
12041 | "pll on state mismatch (expected %i, found %i)\n", | |
12042 | pll->on, active); | |
12043 | } | |
5358901f | 12044 | |
e7c84544 | 12045 | if (!crtc) { |
2c42e535 | 12046 | I915_STATE_WARN(pll->active_mask & ~pll->state.crtc_mask, |
e7c84544 | 12047 | "more active pll users than references: %x vs %x\n", |
2c42e535 | 12048 | pll->active_mask, pll->state.crtc_mask); |
5358901f | 12049 | |
e7c84544 ML |
12050 | return; |
12051 | } | |
12052 | ||
12053 | crtc_mask = 1 << drm_crtc_index(crtc); | |
12054 | ||
12055 | if (new_state->active) | |
12056 | I915_STATE_WARN(!(pll->active_mask & crtc_mask), | |
12057 | "pll active mismatch (expected pipe %c in active mask 0x%02x)\n", | |
12058 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
12059 | else | |
12060 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
12061 | "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n", | |
12062 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
2dd66ebd | 12063 | |
2c42e535 | 12064 | I915_STATE_WARN(!(pll->state.crtc_mask & crtc_mask), |
e7c84544 | 12065 | "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", |
2c42e535 | 12066 | crtc_mask, pll->state.crtc_mask); |
66e985c0 | 12067 | |
2c42e535 | 12068 | I915_STATE_WARN(pll->on && memcmp(&pll->state.hw_state, |
e7c84544 ML |
12069 | &dpll_hw_state, |
12070 | sizeof(dpll_hw_state)), | |
12071 | "pll hw state mismatch\n"); | |
12072 | } | |
12073 | ||
12074 | static void | |
c0ead703 ML |
12075 | verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc, |
12076 | struct drm_crtc_state *old_crtc_state, | |
12077 | struct drm_crtc_state *new_crtc_state) | |
e7c84544 | 12078 | { |
fac5e23e | 12079 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
12080 | struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state); |
12081 | struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state); | |
12082 | ||
12083 | if (new_state->shared_dpll) | |
c0ead703 | 12084 | verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state); |
e7c84544 ML |
12085 | |
12086 | if (old_state->shared_dpll && | |
12087 | old_state->shared_dpll != new_state->shared_dpll) { | |
12088 | unsigned crtc_mask = 1 << drm_crtc_index(crtc); | |
12089 | struct intel_shared_dpll *pll = old_state->shared_dpll; | |
12090 | ||
12091 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
12092 | "pll active mismatch (didn't expect pipe %c in active mask)\n", | |
12093 | pipe_name(drm_crtc_index(crtc))); | |
2c42e535 | 12094 | I915_STATE_WARN(pll->state.crtc_mask & crtc_mask, |
e7c84544 ML |
12095 | "pll enabled crtcs mismatch (found %x in enabled mask)\n", |
12096 | pipe_name(drm_crtc_index(crtc))); | |
5358901f | 12097 | } |
8af6cf88 DV |
12098 | } |
12099 | ||
e7c84544 | 12100 | static void |
c0ead703 | 12101 | intel_modeset_verify_crtc(struct drm_crtc *crtc, |
677100ce ML |
12102 | struct drm_atomic_state *state, |
12103 | struct drm_crtc_state *old_state, | |
12104 | struct drm_crtc_state *new_state) | |
e7c84544 | 12105 | { |
5a21b665 DV |
12106 | if (!needs_modeset(new_state) && |
12107 | !to_intel_crtc_state(new_state)->update_pipe) | |
12108 | return; | |
12109 | ||
c0ead703 | 12110 | verify_wm_state(crtc, new_state); |
677100ce | 12111 | verify_connector_state(crtc->dev, state, crtc); |
c0ead703 ML |
12112 | verify_crtc_state(crtc, old_state, new_state); |
12113 | verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state); | |
e7c84544 ML |
12114 | } |
12115 | ||
12116 | static void | |
c0ead703 | 12117 | verify_disabled_dpll_state(struct drm_device *dev) |
e7c84544 | 12118 | { |
fac5e23e | 12119 | struct drm_i915_private *dev_priv = to_i915(dev); |
e7c84544 ML |
12120 | int i; |
12121 | ||
12122 | for (i = 0; i < dev_priv->num_shared_dpll; i++) | |
c0ead703 | 12123 | verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL); |
e7c84544 ML |
12124 | } |
12125 | ||
12126 | static void | |
677100ce ML |
12127 | intel_modeset_verify_disabled(struct drm_device *dev, |
12128 | struct drm_atomic_state *state) | |
e7c84544 | 12129 | { |
c0ead703 | 12130 | verify_encoder_state(dev); |
677100ce | 12131 | verify_connector_state(dev, state, NULL); |
c0ead703 | 12132 | verify_disabled_dpll_state(dev); |
e7c84544 ML |
12133 | } |
12134 | ||
80715b2f VS |
12135 | static void update_scanline_offset(struct intel_crtc *crtc) |
12136 | { | |
4f8036a2 | 12137 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
80715b2f VS |
12138 | |
12139 | /* | |
12140 | * The scanline counter increments at the leading edge of hsync. | |
12141 | * | |
12142 | * On most platforms it starts counting from vtotal-1 on the | |
12143 | * first active line. That means the scanline counter value is | |
12144 | * always one less than what we would expect. Ie. just after | |
12145 | * start of vblank, which also occurs at start of hsync (on the | |
12146 | * last active line), the scanline counter will read vblank_start-1. | |
12147 | * | |
12148 | * On gen2 the scanline counter starts counting from 1 instead | |
12149 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
12150 | * to keep the value positive), instead of adding one. | |
12151 | * | |
12152 | * On HSW+ the behaviour of the scanline counter depends on the output | |
12153 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
12154 | * there's an extra 1 line difference. So we need to add two instead of | |
12155 | * one to the value. | |
12156 | */ | |
4f8036a2 | 12157 | if (IS_GEN2(dev_priv)) { |
124abe07 | 12158 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
12159 | int vtotal; |
12160 | ||
124abe07 VS |
12161 | vtotal = adjusted_mode->crtc_vtotal; |
12162 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
12163 | vtotal /= 2; |
12164 | ||
12165 | crtc->scanline_offset = vtotal - 1; | |
4f8036a2 | 12166 | } else if (HAS_DDI(dev_priv) && |
2d84d2b3 | 12167 | intel_crtc_has_type(crtc->config, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
12168 | crtc->scanline_offset = 2; |
12169 | } else | |
12170 | crtc->scanline_offset = 1; | |
12171 | } | |
12172 | ||
ad421372 | 12173 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 12174 | { |
225da59b | 12175 | struct drm_device *dev = state->dev; |
ed6739ef | 12176 | struct drm_i915_private *dev_priv = to_i915(dev); |
0a9ab303 ACO |
12177 | struct drm_crtc *crtc; |
12178 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 12179 | int i; |
ed6739ef ACO |
12180 | |
12181 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 12182 | return; |
ed6739ef | 12183 | |
0a9ab303 | 12184 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
fb1a38a9 | 12185 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8106ddbd ACO |
12186 | struct intel_shared_dpll *old_dpll = |
12187 | to_intel_crtc_state(crtc->state)->shared_dpll; | |
0a9ab303 | 12188 | |
fb1a38a9 | 12189 | if (!needs_modeset(crtc_state)) |
225da59b ACO |
12190 | continue; |
12191 | ||
8106ddbd | 12192 | to_intel_crtc_state(crtc_state)->shared_dpll = NULL; |
fb1a38a9 | 12193 | |
8106ddbd | 12194 | if (!old_dpll) |
fb1a38a9 | 12195 | continue; |
0a9ab303 | 12196 | |
a1c414ee | 12197 | intel_release_shared_dpll(old_dpll, intel_crtc, state); |
ad421372 | 12198 | } |
ed6739ef ACO |
12199 | } |
12200 | ||
99d736a2 ML |
12201 | /* |
12202 | * This implements the workaround described in the "notes" section of the mode | |
12203 | * set sequence documentation. When going from no pipes or single pipe to | |
12204 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
12205 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
12206 | */ | |
12207 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
12208 | { | |
12209 | struct drm_crtc_state *crtc_state; | |
12210 | struct intel_crtc *intel_crtc; | |
12211 | struct drm_crtc *crtc; | |
12212 | struct intel_crtc_state *first_crtc_state = NULL; | |
12213 | struct intel_crtc_state *other_crtc_state = NULL; | |
12214 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
12215 | int i; | |
12216 | ||
12217 | /* look at all crtc's that are going to be enabled in during modeset */ | |
12218 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
12219 | intel_crtc = to_intel_crtc(crtc); | |
12220 | ||
12221 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
12222 | continue; | |
12223 | ||
12224 | if (first_crtc_state) { | |
12225 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
12226 | break; | |
12227 | } else { | |
12228 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
12229 | first_pipe = intel_crtc->pipe; | |
12230 | } | |
12231 | } | |
12232 | ||
12233 | /* No workaround needed? */ | |
12234 | if (!first_crtc_state) | |
12235 | return 0; | |
12236 | ||
12237 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
12238 | for_each_intel_crtc(state->dev, intel_crtc) { | |
12239 | struct intel_crtc_state *pipe_config; | |
12240 | ||
12241 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
12242 | if (IS_ERR(pipe_config)) | |
12243 | return PTR_ERR(pipe_config); | |
12244 | ||
12245 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
12246 | ||
12247 | if (!pipe_config->base.active || | |
12248 | needs_modeset(&pipe_config->base)) | |
12249 | continue; | |
12250 | ||
12251 | /* 2 or more enabled crtcs means no need for w/a */ | |
12252 | if (enabled_pipe != INVALID_PIPE) | |
12253 | return 0; | |
12254 | ||
12255 | enabled_pipe = intel_crtc->pipe; | |
12256 | } | |
12257 | ||
12258 | if (enabled_pipe != INVALID_PIPE) | |
12259 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
12260 | else if (other_crtc_state) | |
12261 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
12262 | ||
12263 | return 0; | |
12264 | } | |
12265 | ||
8d96561a VS |
12266 | static int intel_lock_all_pipes(struct drm_atomic_state *state) |
12267 | { | |
12268 | struct drm_crtc *crtc; | |
12269 | ||
12270 | /* Add all pipes to the state */ | |
12271 | for_each_crtc(state->dev, crtc) { | |
12272 | struct drm_crtc_state *crtc_state; | |
12273 | ||
12274 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
12275 | if (IS_ERR(crtc_state)) | |
12276 | return PTR_ERR(crtc_state); | |
12277 | } | |
12278 | ||
12279 | return 0; | |
12280 | } | |
12281 | ||
27c329ed ML |
12282 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
12283 | { | |
12284 | struct drm_crtc *crtc; | |
27c329ed | 12285 | |
8d96561a VS |
12286 | /* |
12287 | * Add all pipes to the state, and force | |
12288 | * a modeset on all the active ones. | |
12289 | */ | |
27c329ed | 12290 | for_each_crtc(state->dev, crtc) { |
9780aad5 VS |
12291 | struct drm_crtc_state *crtc_state; |
12292 | int ret; | |
12293 | ||
27c329ed ML |
12294 | crtc_state = drm_atomic_get_crtc_state(state, crtc); |
12295 | if (IS_ERR(crtc_state)) | |
12296 | return PTR_ERR(crtc_state); | |
12297 | ||
12298 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
12299 | continue; | |
12300 | ||
12301 | crtc_state->mode_changed = true; | |
12302 | ||
12303 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
12304 | if (ret) | |
9780aad5 | 12305 | return ret; |
27c329ed ML |
12306 | |
12307 | ret = drm_atomic_add_affected_planes(state, crtc); | |
12308 | if (ret) | |
9780aad5 | 12309 | return ret; |
27c329ed ML |
12310 | } |
12311 | ||
9780aad5 | 12312 | return 0; |
27c329ed ML |
12313 | } |
12314 | ||
c347a676 | 12315 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 12316 | { |
565602d7 | 12317 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 12318 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
565602d7 ML |
12319 | struct drm_crtc *crtc; |
12320 | struct drm_crtc_state *crtc_state; | |
12321 | int ret = 0, i; | |
054518dd | 12322 | |
b359283a ML |
12323 | if (!check_digital_port_conflicts(state)) { |
12324 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
12325 | return -EINVAL; | |
12326 | } | |
12327 | ||
565602d7 ML |
12328 | intel_state->modeset = true; |
12329 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
bb0f4aab VS |
12330 | intel_state->cdclk.logical = dev_priv->cdclk.logical; |
12331 | intel_state->cdclk.actual = dev_priv->cdclk.actual; | |
565602d7 ML |
12332 | |
12333 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
12334 | if (crtc_state->active) | |
12335 | intel_state->active_crtcs |= 1 << i; | |
12336 | else | |
12337 | intel_state->active_crtcs &= ~(1 << i); | |
8b4a7d05 MR |
12338 | |
12339 | if (crtc_state->active != crtc->state->active) | |
12340 | intel_state->active_pipe_changes |= drm_crtc_mask(crtc); | |
565602d7 ML |
12341 | } |
12342 | ||
054518dd ACO |
12343 | /* |
12344 | * See if the config requires any additional preparation, e.g. | |
12345 | * to adjust global state with pipes off. We need to do this | |
12346 | * here so we can get the modeset_pipe updated config for the new | |
12347 | * mode set on this crtc. For other crtcs we need to use the | |
12348 | * adjusted_mode bits in the crtc directly. | |
12349 | */ | |
27c329ed | 12350 | if (dev_priv->display.modeset_calc_cdclk) { |
27c329ed | 12351 | ret = dev_priv->display.modeset_calc_cdclk(state); |
c89e39f3 CT |
12352 | if (ret < 0) |
12353 | return ret; | |
27c329ed | 12354 | |
8d96561a | 12355 | /* |
bb0f4aab | 12356 | * Writes to dev_priv->cdclk.logical must protected by |
8d96561a VS |
12357 | * holding all the crtc locks, even if we don't end up |
12358 | * touching the hardware | |
12359 | */ | |
bb0f4aab VS |
12360 | if (!intel_cdclk_state_compare(&dev_priv->cdclk.logical, |
12361 | &intel_state->cdclk.logical)) { | |
8d96561a VS |
12362 | ret = intel_lock_all_pipes(state); |
12363 | if (ret < 0) | |
12364 | return ret; | |
12365 | } | |
12366 | ||
12367 | /* All pipes must be switched off while we change the cdclk. */ | |
bb0f4aab VS |
12368 | if (!intel_cdclk_state_compare(&dev_priv->cdclk.actual, |
12369 | &intel_state->cdclk.actual)) { | |
27c329ed | 12370 | ret = intel_modeset_all_pipes(state); |
8d96561a VS |
12371 | if (ret < 0) |
12372 | return ret; | |
12373 | } | |
e8788cbc | 12374 | |
bb0f4aab VS |
12375 | DRM_DEBUG_KMS("New cdclk calculated to be logical %u kHz, actual %u kHz\n", |
12376 | intel_state->cdclk.logical.cdclk, | |
12377 | intel_state->cdclk.actual.cdclk); | |
e0ca7a6b | 12378 | } else { |
bb0f4aab | 12379 | to_intel_atomic_state(state)->cdclk.logical = dev_priv->cdclk.logical; |
e0ca7a6b | 12380 | } |
054518dd | 12381 | |
ad421372 | 12382 | intel_modeset_clear_plls(state); |
054518dd | 12383 | |
565602d7 | 12384 | if (IS_HASWELL(dev_priv)) |
ad421372 | 12385 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 12386 | |
ad421372 | 12387 | return 0; |
c347a676 ACO |
12388 | } |
12389 | ||
aa363136 MR |
12390 | /* |
12391 | * Handle calculation of various watermark data at the end of the atomic check | |
12392 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
12393 | * handlers to ensure that all derived state has been updated. | |
12394 | */ | |
55994c2c | 12395 | static int calc_watermark_data(struct drm_atomic_state *state) |
aa363136 MR |
12396 | { |
12397 | struct drm_device *dev = state->dev; | |
98d39494 | 12398 | struct drm_i915_private *dev_priv = to_i915(dev); |
98d39494 MR |
12399 | |
12400 | /* Is there platform-specific watermark information to calculate? */ | |
12401 | if (dev_priv->display.compute_global_watermarks) | |
55994c2c MR |
12402 | return dev_priv->display.compute_global_watermarks(state); |
12403 | ||
12404 | return 0; | |
aa363136 MR |
12405 | } |
12406 | ||
74c090b1 ML |
12407 | /** |
12408 | * intel_atomic_check - validate state object | |
12409 | * @dev: drm device | |
12410 | * @state: state to validate | |
12411 | */ | |
12412 | static int intel_atomic_check(struct drm_device *dev, | |
12413 | struct drm_atomic_state *state) | |
c347a676 | 12414 | { |
dd8b3bdb | 12415 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 12416 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
12417 | struct drm_crtc *crtc; |
12418 | struct drm_crtc_state *crtc_state; | |
12419 | int ret, i; | |
61333b60 | 12420 | bool any_ms = false; |
c347a676 | 12421 | |
74c090b1 | 12422 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
12423 | if (ret) |
12424 | return ret; | |
12425 | ||
c347a676 | 12426 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
12427 | struct intel_crtc_state *pipe_config = |
12428 | to_intel_crtc_state(crtc_state); | |
1ed51de9 DV |
12429 | |
12430 | /* Catch I915_MODE_FLAG_INHERITED */ | |
12431 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
12432 | crtc_state->mode_changed = true; | |
cfb23ed6 | 12433 | |
af4a879e | 12434 | if (!needs_modeset(crtc_state)) |
c347a676 ACO |
12435 | continue; |
12436 | ||
af4a879e DV |
12437 | if (!crtc_state->enable) { |
12438 | any_ms = true; | |
cfb23ed6 | 12439 | continue; |
af4a879e | 12440 | } |
cfb23ed6 | 12441 | |
26495481 DV |
12442 | /* FIXME: For only active_changed we shouldn't need to do any |
12443 | * state recomputation at all. */ | |
12444 | ||
1ed51de9 DV |
12445 | ret = drm_atomic_add_affected_connectors(state, crtc); |
12446 | if (ret) | |
12447 | return ret; | |
b359283a | 12448 | |
cfb23ed6 | 12449 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
25aa1c39 ML |
12450 | if (ret) { |
12451 | intel_dump_pipe_config(to_intel_crtc(crtc), | |
12452 | pipe_config, "[failed]"); | |
c347a676 | 12453 | return ret; |
25aa1c39 | 12454 | } |
c347a676 | 12455 | |
73831236 | 12456 | if (i915.fastboot && |
6315b5d3 | 12457 | intel_pipe_config_compare(dev_priv, |
cfb23ed6 | 12458 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 12459 | pipe_config, true)) { |
26495481 | 12460 | crtc_state->mode_changed = false; |
bfd16b2a | 12461 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
12462 | } |
12463 | ||
af4a879e | 12464 | if (needs_modeset(crtc_state)) |
26495481 | 12465 | any_ms = true; |
cfb23ed6 | 12466 | |
af4a879e DV |
12467 | ret = drm_atomic_add_affected_planes(state, crtc); |
12468 | if (ret) | |
12469 | return ret; | |
61333b60 | 12470 | |
26495481 DV |
12471 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
12472 | needs_modeset(crtc_state) ? | |
12473 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
12474 | } |
12475 | ||
61333b60 ML |
12476 | if (any_ms) { |
12477 | ret = intel_modeset_checks(state); | |
12478 | ||
12479 | if (ret) | |
12480 | return ret; | |
e0ca7a6b | 12481 | } else { |
bb0f4aab | 12482 | intel_state->cdclk.logical = dev_priv->cdclk.logical; |
e0ca7a6b | 12483 | } |
76305b1a | 12484 | |
dd8b3bdb | 12485 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
12486 | if (ret) |
12487 | return ret; | |
12488 | ||
f51be2e0 | 12489 | intel_fbc_choose_crtc(dev_priv, state); |
55994c2c | 12490 | return calc_watermark_data(state); |
054518dd ACO |
12491 | } |
12492 | ||
5008e874 | 12493 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
d07f0e59 | 12494 | struct drm_atomic_state *state) |
5008e874 | 12495 | { |
fac5e23e | 12496 | struct drm_i915_private *dev_priv = to_i915(dev); |
5008e874 ML |
12497 | struct drm_crtc_state *crtc_state; |
12498 | struct drm_crtc *crtc; | |
12499 | int i, ret; | |
12500 | ||
5a21b665 DV |
12501 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
12502 | if (state->legacy_cursor_update) | |
a6747b73 ML |
12503 | continue; |
12504 | ||
5a21b665 DV |
12505 | ret = intel_crtc_wait_for_pending_flips(crtc); |
12506 | if (ret) | |
12507 | return ret; | |
5008e874 | 12508 | |
5a21b665 DV |
12509 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) |
12510 | flush_workqueue(dev_priv->wq); | |
d55dbd06 ML |
12511 | } |
12512 | ||
f935675f ML |
12513 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
12514 | if (ret) | |
12515 | return ret; | |
12516 | ||
5008e874 | 12517 | ret = drm_atomic_helper_prepare_planes(dev, state); |
f7e5838b | 12518 | mutex_unlock(&dev->struct_mutex); |
7580d774 | 12519 | |
5008e874 ML |
12520 | return ret; |
12521 | } | |
12522 | ||
a2991414 ML |
12523 | u32 intel_crtc_get_vblank_counter(struct intel_crtc *crtc) |
12524 | { | |
12525 | struct drm_device *dev = crtc->base.dev; | |
12526 | ||
12527 | if (!dev->max_vblank_count) | |
12528 | return drm_accurate_vblank_count(&crtc->base); | |
12529 | ||
12530 | return dev->driver->get_vblank_counter(dev, crtc->pipe); | |
12531 | } | |
12532 | ||
5a21b665 DV |
12533 | static void intel_atomic_wait_for_vblanks(struct drm_device *dev, |
12534 | struct drm_i915_private *dev_priv, | |
12535 | unsigned crtc_mask) | |
e8861675 | 12536 | { |
5a21b665 DV |
12537 | unsigned last_vblank_count[I915_MAX_PIPES]; |
12538 | enum pipe pipe; | |
12539 | int ret; | |
e8861675 | 12540 | |
5a21b665 DV |
12541 | if (!crtc_mask) |
12542 | return; | |
e8861675 | 12543 | |
5a21b665 | 12544 | for_each_pipe(dev_priv, pipe) { |
98187836 VS |
12545 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, |
12546 | pipe); | |
e8861675 | 12547 | |
5a21b665 | 12548 | if (!((1 << pipe) & crtc_mask)) |
e8861675 ML |
12549 | continue; |
12550 | ||
e2af48c6 | 12551 | ret = drm_crtc_vblank_get(&crtc->base); |
5a21b665 DV |
12552 | if (WARN_ON(ret != 0)) { |
12553 | crtc_mask &= ~(1 << pipe); | |
12554 | continue; | |
e8861675 ML |
12555 | } |
12556 | ||
e2af48c6 | 12557 | last_vblank_count[pipe] = drm_crtc_vblank_count(&crtc->base); |
e8861675 ML |
12558 | } |
12559 | ||
5a21b665 | 12560 | for_each_pipe(dev_priv, pipe) { |
98187836 VS |
12561 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, |
12562 | pipe); | |
5a21b665 | 12563 | long lret; |
e8861675 | 12564 | |
5a21b665 DV |
12565 | if (!((1 << pipe) & crtc_mask)) |
12566 | continue; | |
d55dbd06 | 12567 | |
5a21b665 DV |
12568 | lret = wait_event_timeout(dev->vblank[pipe].queue, |
12569 | last_vblank_count[pipe] != | |
e2af48c6 | 12570 | drm_crtc_vblank_count(&crtc->base), |
5a21b665 | 12571 | msecs_to_jiffies(50)); |
d55dbd06 | 12572 | |
5a21b665 | 12573 | WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe)); |
d55dbd06 | 12574 | |
e2af48c6 | 12575 | drm_crtc_vblank_put(&crtc->base); |
d55dbd06 ML |
12576 | } |
12577 | } | |
12578 | ||
5a21b665 | 12579 | static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) |
a6747b73 | 12580 | { |
5a21b665 DV |
12581 | /* fb updated, need to unpin old fb */ |
12582 | if (crtc_state->fb_changed) | |
12583 | return true; | |
a6747b73 | 12584 | |
5a21b665 DV |
12585 | /* wm changes, need vblank before final wm's */ |
12586 | if (crtc_state->update_wm_post) | |
12587 | return true; | |
a6747b73 | 12588 | |
5eeb798b | 12589 | if (crtc_state->wm.need_postvbl_update) |
5a21b665 | 12590 | return true; |
a6747b73 | 12591 | |
5a21b665 | 12592 | return false; |
e8861675 ML |
12593 | } |
12594 | ||
896e5bb0 L |
12595 | static void intel_update_crtc(struct drm_crtc *crtc, |
12596 | struct drm_atomic_state *state, | |
12597 | struct drm_crtc_state *old_crtc_state, | |
12598 | unsigned int *crtc_vblank_mask) | |
12599 | { | |
12600 | struct drm_device *dev = crtc->dev; | |
12601 | struct drm_i915_private *dev_priv = to_i915(dev); | |
12602 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12603 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc->state); | |
12604 | bool modeset = needs_modeset(crtc->state); | |
12605 | ||
12606 | if (modeset) { | |
12607 | update_scanline_offset(intel_crtc); | |
12608 | dev_priv->display.crtc_enable(pipe_config, state); | |
12609 | } else { | |
12610 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); | |
12611 | } | |
12612 | ||
12613 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12614 | intel_fbc_enable( | |
12615 | intel_crtc, pipe_config, | |
12616 | to_intel_plane_state(crtc->primary->state)); | |
12617 | } | |
12618 | ||
12619 | drm_atomic_helper_commit_planes_on_crtc(old_crtc_state); | |
12620 | ||
12621 | if (needs_vblank_wait(pipe_config)) | |
12622 | *crtc_vblank_mask |= drm_crtc_mask(crtc); | |
12623 | } | |
12624 | ||
12625 | static void intel_update_crtcs(struct drm_atomic_state *state, | |
12626 | unsigned int *crtc_vblank_mask) | |
12627 | { | |
12628 | struct drm_crtc *crtc; | |
12629 | struct drm_crtc_state *old_crtc_state; | |
12630 | int i; | |
12631 | ||
12632 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
12633 | if (!crtc->state->active) | |
12634 | continue; | |
12635 | ||
12636 | intel_update_crtc(crtc, state, old_crtc_state, | |
12637 | crtc_vblank_mask); | |
12638 | } | |
12639 | } | |
12640 | ||
27082493 L |
12641 | static void skl_update_crtcs(struct drm_atomic_state *state, |
12642 | unsigned int *crtc_vblank_mask) | |
12643 | { | |
0f0f74bc | 12644 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
27082493 L |
12645 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
12646 | struct drm_crtc *crtc; | |
ce0ba283 | 12647 | struct intel_crtc *intel_crtc; |
27082493 | 12648 | struct drm_crtc_state *old_crtc_state; |
ce0ba283 | 12649 | struct intel_crtc_state *cstate; |
27082493 L |
12650 | unsigned int updated = 0; |
12651 | bool progress; | |
12652 | enum pipe pipe; | |
5eff503b ML |
12653 | int i; |
12654 | ||
12655 | const struct skl_ddb_entry *entries[I915_MAX_PIPES] = {}; | |
12656 | ||
12657 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) | |
12658 | /* ignore allocations for crtc's that have been turned off. */ | |
12659 | if (crtc->state->active) | |
12660 | entries[i] = &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb; | |
27082493 L |
12661 | |
12662 | /* | |
12663 | * Whenever the number of active pipes changes, we need to make sure we | |
12664 | * update the pipes in the right order so that their ddb allocations | |
12665 | * never overlap with eachother inbetween CRTC updates. Otherwise we'll | |
12666 | * cause pipe underruns and other bad stuff. | |
12667 | */ | |
12668 | do { | |
27082493 L |
12669 | progress = false; |
12670 | ||
12671 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
12672 | bool vbl_wait = false; | |
12673 | unsigned int cmask = drm_crtc_mask(crtc); | |
ce0ba283 L |
12674 | |
12675 | intel_crtc = to_intel_crtc(crtc); | |
12676 | cstate = to_intel_crtc_state(crtc->state); | |
12677 | pipe = intel_crtc->pipe; | |
27082493 | 12678 | |
5eff503b | 12679 | if (updated & cmask || !cstate->base.active) |
27082493 | 12680 | continue; |
5eff503b ML |
12681 | |
12682 | if (skl_ddb_allocation_overlaps(entries, &cstate->wm.skl.ddb, i)) | |
27082493 L |
12683 | continue; |
12684 | ||
12685 | updated |= cmask; | |
5eff503b | 12686 | entries[i] = &cstate->wm.skl.ddb; |
27082493 L |
12687 | |
12688 | /* | |
12689 | * If this is an already active pipe, it's DDB changed, | |
12690 | * and this isn't the last pipe that needs updating | |
12691 | * then we need to wait for a vblank to pass for the | |
12692 | * new ddb allocation to take effect. | |
12693 | */ | |
ce0ba283 | 12694 | if (!skl_ddb_entry_equal(&cstate->wm.skl.ddb, |
512b5527 | 12695 | &to_intel_crtc_state(old_crtc_state)->wm.skl.ddb) && |
27082493 L |
12696 | !crtc->state->active_changed && |
12697 | intel_state->wm_results.dirty_pipes != updated) | |
12698 | vbl_wait = true; | |
12699 | ||
12700 | intel_update_crtc(crtc, state, old_crtc_state, | |
12701 | crtc_vblank_mask); | |
12702 | ||
12703 | if (vbl_wait) | |
0f0f74bc | 12704 | intel_wait_for_vblank(dev_priv, pipe); |
27082493 L |
12705 | |
12706 | progress = true; | |
12707 | } | |
12708 | } while (progress); | |
12709 | } | |
12710 | ||
ba318c61 CW |
12711 | static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv) |
12712 | { | |
12713 | struct intel_atomic_state *state, *next; | |
12714 | struct llist_node *freed; | |
12715 | ||
12716 | freed = llist_del_all(&dev_priv->atomic_helper.free_list); | |
12717 | llist_for_each_entry_safe(state, next, freed, freed) | |
12718 | drm_atomic_state_put(&state->base); | |
12719 | } | |
12720 | ||
12721 | static void intel_atomic_helper_free_state_worker(struct work_struct *work) | |
12722 | { | |
12723 | struct drm_i915_private *dev_priv = | |
12724 | container_of(work, typeof(*dev_priv), atomic_helper.free_work); | |
12725 | ||
12726 | intel_atomic_helper_free_state(dev_priv); | |
12727 | } | |
12728 | ||
94f05024 | 12729 | static void intel_atomic_commit_tail(struct drm_atomic_state *state) |
a6778b3c | 12730 | { |
94f05024 | 12731 | struct drm_device *dev = state->dev; |
565602d7 | 12732 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fac5e23e | 12733 | struct drm_i915_private *dev_priv = to_i915(dev); |
29ceb0e6 | 12734 | struct drm_crtc_state *old_crtc_state; |
7580d774 | 12735 | struct drm_crtc *crtc; |
5a21b665 | 12736 | struct intel_crtc_state *intel_cstate; |
5a21b665 | 12737 | bool hw_check = intel_state->modeset; |
d8fc70b7 | 12738 | u64 put_domains[I915_MAX_PIPES] = {}; |
5a21b665 | 12739 | unsigned crtc_vblank_mask = 0; |
e95433c7 | 12740 | int i; |
a6778b3c | 12741 | |
ea0000f0 DV |
12742 | drm_atomic_helper_wait_for_dependencies(state); |
12743 | ||
c3b32658 | 12744 | if (intel_state->modeset) |
5a21b665 | 12745 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); |
565602d7 | 12746 | |
29ceb0e6 | 12747 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
a539205a ML |
12748 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
12749 | ||
5a21b665 DV |
12750 | if (needs_modeset(crtc->state) || |
12751 | to_intel_crtc_state(crtc->state)->update_pipe) { | |
12752 | hw_check = true; | |
12753 | ||
12754 | put_domains[to_intel_crtc(crtc)->pipe] = | |
12755 | modeset_get_crtc_power_domains(crtc, | |
12756 | to_intel_crtc_state(crtc->state)); | |
12757 | } | |
12758 | ||
61333b60 ML |
12759 | if (!needs_modeset(crtc->state)) |
12760 | continue; | |
12761 | ||
29ceb0e6 | 12762 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
460da916 | 12763 | |
29ceb0e6 VS |
12764 | if (old_crtc_state->active) { |
12765 | intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); | |
4a806558 | 12766 | dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state); |
eddfcbcd | 12767 | intel_crtc->active = false; |
58f9c0bc | 12768 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 12769 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
12770 | |
12771 | /* | |
12772 | * Underruns don't always raise | |
12773 | * interrupts, so check manually. | |
12774 | */ | |
12775 | intel_check_cpu_fifo_underruns(dev_priv); | |
12776 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 | 12777 | |
e62929b3 ML |
12778 | if (!crtc->state->active) { |
12779 | /* | |
12780 | * Make sure we don't call initial_watermarks | |
12781 | * for ILK-style watermark updates. | |
ff32c54e VS |
12782 | * |
12783 | * No clue what this is supposed to achieve. | |
e62929b3 | 12784 | */ |
ff32c54e | 12785 | if (INTEL_GEN(dev_priv) >= 9) |
e62929b3 ML |
12786 | dev_priv->display.initial_watermarks(intel_state, |
12787 | to_intel_crtc_state(crtc->state)); | |
e62929b3 | 12788 | } |
a539205a | 12789 | } |
b8cecdf5 | 12790 | } |
7758a113 | 12791 | |
ea9d758d DV |
12792 | /* Only after disabling all output pipelines that will be changed can we |
12793 | * update the the output configuration. */ | |
4740b0f2 | 12794 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 12795 | |
565602d7 | 12796 | if (intel_state->modeset) { |
4740b0f2 | 12797 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
33c8df89 | 12798 | |
b0587e4d | 12799 | intel_set_cdclk(dev_priv, &dev_priv->cdclk.actual); |
f6d1973d | 12800 | |
656d1b89 L |
12801 | /* |
12802 | * SKL workaround: bspec recommends we disable the SAGV when we | |
12803 | * have more then one pipe enabled | |
12804 | */ | |
56feca91 | 12805 | if (!intel_can_enable_sagv(state)) |
16dcdc4e | 12806 | intel_disable_sagv(dev_priv); |
656d1b89 | 12807 | |
677100ce | 12808 | intel_modeset_verify_disabled(dev, state); |
4740b0f2 | 12809 | } |
47fab737 | 12810 | |
896e5bb0 | 12811 | /* Complete the events for pipes that have now been disabled */ |
29ceb0e6 | 12812 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
f6ac4b2a | 12813 | bool modeset = needs_modeset(crtc->state); |
80715b2f | 12814 | |
1f7528c4 DV |
12815 | /* Complete events for now disable pipes here. */ |
12816 | if (modeset && !crtc->state->active && crtc->state->event) { | |
12817 | spin_lock_irq(&dev->event_lock); | |
12818 | drm_crtc_send_vblank_event(crtc, crtc->state->event); | |
12819 | spin_unlock_irq(&dev->event_lock); | |
12820 | ||
12821 | crtc->state->event = NULL; | |
12822 | } | |
177246a8 MR |
12823 | } |
12824 | ||
896e5bb0 L |
12825 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
12826 | dev_priv->display.update_crtcs(state, &crtc_vblank_mask); | |
12827 | ||
94f05024 DV |
12828 | /* FIXME: We should call drm_atomic_helper_commit_hw_done() here |
12829 | * already, but still need the state for the delayed optimization. To | |
12830 | * fix this: | |
12831 | * - wrap the optimization/post_plane_update stuff into a per-crtc work. | |
12832 | * - schedule that vblank worker _before_ calling hw_done | |
12833 | * - at the start of commit_tail, cancel it _synchrously | |
12834 | * - switch over to the vblank wait helper in the core after that since | |
12835 | * we don't need out special handling any more. | |
12836 | */ | |
5a21b665 DV |
12837 | if (!state->legacy_cursor_update) |
12838 | intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); | |
12839 | ||
12840 | /* | |
12841 | * Now that the vblank has passed, we can go ahead and program the | |
12842 | * optimal watermarks on platforms that need two-step watermark | |
12843 | * programming. | |
12844 | * | |
12845 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
12846 | */ | |
12847 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
12848 | intel_cstate = to_intel_crtc_state(crtc->state); | |
12849 | ||
12850 | if (dev_priv->display.optimize_watermarks) | |
ccf010fb ML |
12851 | dev_priv->display.optimize_watermarks(intel_state, |
12852 | intel_cstate); | |
5a21b665 DV |
12853 | } |
12854 | ||
12855 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { | |
12856 | intel_post_plane_update(to_intel_crtc_state(old_crtc_state)); | |
12857 | ||
12858 | if (put_domains[i]) | |
12859 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
12860 | ||
677100ce | 12861 | intel_modeset_verify_crtc(crtc, state, old_crtc_state, crtc->state); |
5a21b665 DV |
12862 | } |
12863 | ||
56feca91 | 12864 | if (intel_state->modeset && intel_can_enable_sagv(state)) |
16dcdc4e | 12865 | intel_enable_sagv(dev_priv); |
656d1b89 | 12866 | |
94f05024 DV |
12867 | drm_atomic_helper_commit_hw_done(state); |
12868 | ||
5a21b665 DV |
12869 | if (intel_state->modeset) |
12870 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
12871 | ||
12872 | mutex_lock(&dev->struct_mutex); | |
12873 | drm_atomic_helper_cleanup_planes(dev, state); | |
12874 | mutex_unlock(&dev->struct_mutex); | |
12875 | ||
ea0000f0 DV |
12876 | drm_atomic_helper_commit_cleanup_done(state); |
12877 | ||
0853695c | 12878 | drm_atomic_state_put(state); |
f30da187 | 12879 | |
75714940 MK |
12880 | /* As one of the primary mmio accessors, KMS has a high likelihood |
12881 | * of triggering bugs in unclaimed access. After we finish | |
12882 | * modesetting, see if an error has been flagged, and if so | |
12883 | * enable debugging for the next modeset - and hope we catch | |
12884 | * the culprit. | |
12885 | * | |
12886 | * XXX note that we assume display power is on at this point. | |
12887 | * This might hold true now but we need to add pm helper to check | |
12888 | * unclaimed only when the hardware is on, as atomic commits | |
12889 | * can happen also when the device is completely off. | |
12890 | */ | |
12891 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
ba318c61 CW |
12892 | |
12893 | intel_atomic_helper_free_state(dev_priv); | |
94f05024 DV |
12894 | } |
12895 | ||
12896 | static void intel_atomic_commit_work(struct work_struct *work) | |
12897 | { | |
c004a90b CW |
12898 | struct drm_atomic_state *state = |
12899 | container_of(work, struct drm_atomic_state, commit_work); | |
12900 | ||
94f05024 DV |
12901 | intel_atomic_commit_tail(state); |
12902 | } | |
12903 | ||
c004a90b CW |
12904 | static int __i915_sw_fence_call |
12905 | intel_atomic_commit_ready(struct i915_sw_fence *fence, | |
12906 | enum i915_sw_fence_notify notify) | |
12907 | { | |
12908 | struct intel_atomic_state *state = | |
12909 | container_of(fence, struct intel_atomic_state, commit_ready); | |
12910 | ||
12911 | switch (notify) { | |
12912 | case FENCE_COMPLETE: | |
12913 | if (state->base.commit_work.func) | |
12914 | queue_work(system_unbound_wq, &state->base.commit_work); | |
12915 | break; | |
12916 | ||
12917 | case FENCE_FREE: | |
eb955eee CW |
12918 | { |
12919 | struct intel_atomic_helper *helper = | |
12920 | &to_i915(state->base.dev)->atomic_helper; | |
12921 | ||
12922 | if (llist_add(&state->freed, &helper->free_list)) | |
12923 | schedule_work(&helper->free_work); | |
12924 | break; | |
12925 | } | |
c004a90b CW |
12926 | } |
12927 | ||
12928 | return NOTIFY_DONE; | |
12929 | } | |
12930 | ||
6c9c1b38 DV |
12931 | static void intel_atomic_track_fbs(struct drm_atomic_state *state) |
12932 | { | |
12933 | struct drm_plane_state *old_plane_state; | |
12934 | struct drm_plane *plane; | |
6c9c1b38 DV |
12935 | int i; |
12936 | ||
faf5bf0a CW |
12937 | for_each_plane_in_state(state, plane, old_plane_state, i) |
12938 | i915_gem_track_fb(intel_fb_obj(old_plane_state->fb), | |
12939 | intel_fb_obj(plane->state->fb), | |
12940 | to_intel_plane(plane)->frontbuffer_bit); | |
6c9c1b38 DV |
12941 | } |
12942 | ||
94f05024 DV |
12943 | /** |
12944 | * intel_atomic_commit - commit validated state object | |
12945 | * @dev: DRM device | |
12946 | * @state: the top-level driver state object | |
12947 | * @nonblock: nonblocking commit | |
12948 | * | |
12949 | * This function commits a top-level state object that has been validated | |
12950 | * with drm_atomic_helper_check(). | |
12951 | * | |
94f05024 DV |
12952 | * RETURNS |
12953 | * Zero for success or -errno. | |
12954 | */ | |
12955 | static int intel_atomic_commit(struct drm_device *dev, | |
12956 | struct drm_atomic_state *state, | |
12957 | bool nonblock) | |
12958 | { | |
12959 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
fac5e23e | 12960 | struct drm_i915_private *dev_priv = to_i915(dev); |
94f05024 DV |
12961 | int ret = 0; |
12962 | ||
a5509abd VS |
12963 | /* |
12964 | * The intel_legacy_cursor_update() fast path takes care | |
12965 | * of avoiding the vblank waits for simple cursor | |
12966 | * movement and flips. For cursor on/off and size changes, | |
12967 | * we want to perform the vblank waits so that watermark | |
12968 | * updates happen during the correct frames. Gen9+ have | |
12969 | * double buffered watermarks and so shouldn't need this. | |
12970 | */ | |
12971 | if (INTEL_GEN(dev_priv) < 9) | |
12972 | state->legacy_cursor_update = false; | |
12973 | ||
94f05024 DV |
12974 | ret = drm_atomic_helper_setup_commit(state, nonblock); |
12975 | if (ret) | |
12976 | return ret; | |
12977 | ||
c004a90b CW |
12978 | drm_atomic_state_get(state); |
12979 | i915_sw_fence_init(&intel_state->commit_ready, | |
12980 | intel_atomic_commit_ready); | |
94f05024 | 12981 | |
d07f0e59 | 12982 | ret = intel_atomic_prepare_commit(dev, state); |
94f05024 DV |
12983 | if (ret) { |
12984 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
c004a90b | 12985 | i915_sw_fence_commit(&intel_state->commit_ready); |
94f05024 DV |
12986 | return ret; |
12987 | } | |
12988 | ||
12989 | drm_atomic_helper_swap_state(state, true); | |
12990 | dev_priv->wm.distrust_bios_wm = false; | |
3c0fb588 | 12991 | intel_shared_dpll_swap_state(state); |
6c9c1b38 | 12992 | intel_atomic_track_fbs(state); |
94f05024 | 12993 | |
c3b32658 ML |
12994 | if (intel_state->modeset) { |
12995 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
12996 | sizeof(intel_state->min_pixclk)); | |
12997 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
bb0f4aab VS |
12998 | dev_priv->cdclk.logical = intel_state->cdclk.logical; |
12999 | dev_priv->cdclk.actual = intel_state->cdclk.actual; | |
c3b32658 ML |
13000 | } |
13001 | ||
0853695c | 13002 | drm_atomic_state_get(state); |
c004a90b CW |
13003 | INIT_WORK(&state->commit_work, |
13004 | nonblock ? intel_atomic_commit_work : NULL); | |
13005 | ||
13006 | i915_sw_fence_commit(&intel_state->commit_ready); | |
13007 | if (!nonblock) { | |
13008 | i915_sw_fence_wait(&intel_state->commit_ready); | |
94f05024 | 13009 | intel_atomic_commit_tail(state); |
c004a90b | 13010 | } |
75714940 | 13011 | |
74c090b1 | 13012 | return 0; |
7f27126e JB |
13013 | } |
13014 | ||
c0c36b94 CW |
13015 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13016 | { | |
83a57153 ACO |
13017 | struct drm_device *dev = crtc->dev; |
13018 | struct drm_atomic_state *state; | |
e694eb02 | 13019 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 13020 | int ret; |
83a57153 ACO |
13021 | |
13022 | state = drm_atomic_state_alloc(dev); | |
13023 | if (!state) { | |
78108b7c VS |
13024 | DRM_DEBUG_KMS("[CRTC:%d:%s] crtc restore failed, out of memory", |
13025 | crtc->base.id, crtc->name); | |
83a57153 ACO |
13026 | return; |
13027 | } | |
13028 | ||
e694eb02 | 13029 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 13030 | |
e694eb02 ML |
13031 | retry: |
13032 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13033 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
13034 | if (!ret) { | |
13035 | if (!crtc_state->active) | |
13036 | goto out; | |
83a57153 | 13037 | |
e694eb02 | 13038 | crtc_state->mode_changed = true; |
74c090b1 | 13039 | ret = drm_atomic_commit(state); |
83a57153 ACO |
13040 | } |
13041 | ||
e694eb02 ML |
13042 | if (ret == -EDEADLK) { |
13043 | drm_atomic_state_clear(state); | |
13044 | drm_modeset_backoff(state->acquire_ctx); | |
13045 | goto retry; | |
4ed9fb37 | 13046 | } |
4be07317 | 13047 | |
e694eb02 | 13048 | out: |
0853695c | 13049 | drm_atomic_state_put(state); |
c0c36b94 CW |
13050 | } |
13051 | ||
a8784875 BP |
13052 | /* |
13053 | * FIXME: Remove this once i915 is fully DRIVER_ATOMIC by calling | |
13054 | * drm_atomic_helper_legacy_gamma_set() directly. | |
13055 | */ | |
13056 | static int intel_atomic_legacy_gamma_set(struct drm_crtc *crtc, | |
13057 | u16 *red, u16 *green, u16 *blue, | |
13058 | uint32_t size) | |
13059 | { | |
13060 | struct drm_device *dev = crtc->dev; | |
13061 | struct drm_mode_config *config = &dev->mode_config; | |
13062 | struct drm_crtc_state *state; | |
13063 | int ret; | |
13064 | ||
13065 | ret = drm_atomic_helper_legacy_gamma_set(crtc, red, green, blue, size); | |
13066 | if (ret) | |
13067 | return ret; | |
13068 | ||
13069 | /* | |
13070 | * Make sure we update the legacy properties so this works when | |
13071 | * atomic is not enabled. | |
13072 | */ | |
13073 | ||
13074 | state = crtc->state; | |
13075 | ||
13076 | drm_object_property_set_value(&crtc->base, | |
13077 | config->degamma_lut_property, | |
13078 | (state->degamma_lut) ? | |
13079 | state->degamma_lut->base.id : 0); | |
13080 | ||
13081 | drm_object_property_set_value(&crtc->base, | |
13082 | config->ctm_property, | |
13083 | (state->ctm) ? | |
13084 | state->ctm->base.id : 0); | |
13085 | ||
13086 | drm_object_property_set_value(&crtc->base, | |
13087 | config->gamma_lut_property, | |
13088 | (state->gamma_lut) ? | |
13089 | state->gamma_lut->base.id : 0); | |
13090 | ||
13091 | return 0; | |
13092 | } | |
13093 | ||
f6e5b160 | 13094 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
a8784875 | 13095 | .gamma_set = intel_atomic_legacy_gamma_set, |
74c090b1 | 13096 | .set_config = drm_atomic_helper_set_config, |
82cf435b | 13097 | .set_property = drm_atomic_helper_crtc_set_property, |
f6e5b160 | 13098 | .destroy = intel_crtc_destroy, |
4c01ded5 | 13099 | .page_flip = drm_atomic_helper_page_flip, |
1356837e MR |
13100 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13101 | .atomic_destroy_state = intel_crtc_destroy_state, | |
8c6b709d | 13102 | .set_crc_source = intel_crtc_set_crc_source, |
f6e5b160 CW |
13103 | }; |
13104 | ||
6beb8c23 MR |
13105 | /** |
13106 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13107 | * @plane: drm plane to prepare for | |
13108 | * @fb: framebuffer to prepare for presentation | |
13109 | * | |
13110 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13111 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13112 | * bits. Some older platforms need special physical address handling for | |
13113 | * cursor planes. | |
13114 | * | |
f935675f ML |
13115 | * Must be called with struct_mutex held. |
13116 | * | |
6beb8c23 MR |
13117 | * Returns 0 on success, negative error code on failure. |
13118 | */ | |
13119 | int | |
13120 | intel_prepare_plane_fb(struct drm_plane *plane, | |
1832040d | 13121 | struct drm_plane_state *new_state) |
465c120c | 13122 | { |
c004a90b CW |
13123 | struct intel_atomic_state *intel_state = |
13124 | to_intel_atomic_state(new_state->state); | |
b7f05d4a | 13125 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
844f9111 | 13126 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 13127 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 13128 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
c004a90b | 13129 | int ret; |
465c120c | 13130 | |
57822dc6 CW |
13131 | if (obj) { |
13132 | if (plane->type == DRM_PLANE_TYPE_CURSOR && | |
13133 | INTEL_INFO(dev_priv)->cursor_needs_physical) { | |
13134 | const int align = IS_I830(dev_priv) ? 16 * 1024 : 256; | |
13135 | ||
13136 | ret = i915_gem_object_attach_phys(obj, align); | |
13137 | if (ret) { | |
13138 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13139 | return ret; | |
13140 | } | |
13141 | } else { | |
13142 | struct i915_vma *vma; | |
13143 | ||
13144 | vma = intel_pin_and_fence_fb_obj(fb, new_state->rotation); | |
13145 | if (IS_ERR(vma)) { | |
13146 | DRM_DEBUG_KMS("failed to pin object\n"); | |
13147 | return PTR_ERR(vma); | |
13148 | } | |
13149 | ||
13150 | to_intel_plane_state(new_state)->vma = vma; | |
13151 | } | |
13152 | } | |
13153 | ||
1ee49399 | 13154 | if (!obj && !old_obj) |
465c120c MR |
13155 | return 0; |
13156 | ||
5008e874 ML |
13157 | if (old_obj) { |
13158 | struct drm_crtc_state *crtc_state = | |
c004a90b CW |
13159 | drm_atomic_get_existing_crtc_state(new_state->state, |
13160 | plane->state->crtc); | |
5008e874 ML |
13161 | |
13162 | /* Big Hammer, we also need to ensure that any pending | |
13163 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
13164 | * current scanout is retired before unpinning the old | |
13165 | * framebuffer. Note that we rely on userspace rendering | |
13166 | * into the buffer attached to the pipe they are waiting | |
13167 | * on. If not, userspace generates a GPU hang with IPEHR | |
13168 | * point to the MI_WAIT_FOR_EVENT. | |
13169 | * | |
13170 | * This should only fail upon a hung GPU, in which case we | |
13171 | * can safely continue. | |
13172 | */ | |
c004a90b CW |
13173 | if (needs_modeset(crtc_state)) { |
13174 | ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, | |
13175 | old_obj->resv, NULL, | |
13176 | false, 0, | |
13177 | GFP_KERNEL); | |
13178 | if (ret < 0) | |
13179 | return ret; | |
f4457ae7 | 13180 | } |
5008e874 ML |
13181 | } |
13182 | ||
c004a90b CW |
13183 | if (new_state->fence) { /* explicit fencing */ |
13184 | ret = i915_sw_fence_await_dma_fence(&intel_state->commit_ready, | |
13185 | new_state->fence, | |
13186 | I915_FENCE_TIMEOUT, | |
13187 | GFP_KERNEL); | |
13188 | if (ret < 0) | |
13189 | return ret; | |
13190 | } | |
13191 | ||
c37efb99 CW |
13192 | if (!obj) |
13193 | return 0; | |
13194 | ||
c004a90b CW |
13195 | if (!new_state->fence) { /* implicit fencing */ |
13196 | ret = i915_sw_fence_await_reservation(&intel_state->commit_ready, | |
13197 | obj->resv, NULL, | |
13198 | false, I915_FENCE_TIMEOUT, | |
13199 | GFP_KERNEL); | |
13200 | if (ret < 0) | |
13201 | return ret; | |
6b5e90f5 CW |
13202 | |
13203 | i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DISPLAY); | |
c004a90b | 13204 | } |
5a21b665 | 13205 | |
d07f0e59 | 13206 | return 0; |
6beb8c23 MR |
13207 | } |
13208 | ||
38f3ce3a MR |
13209 | /** |
13210 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13211 | * @plane: drm plane to clean up for | |
13212 | * @fb: old framebuffer that was on plane | |
13213 | * | |
13214 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
13215 | * |
13216 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
13217 | */ |
13218 | void | |
13219 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
1832040d | 13220 | struct drm_plane_state *old_state) |
38f3ce3a | 13221 | { |
be1e3415 | 13222 | struct i915_vma *vma; |
38f3ce3a | 13223 | |
be1e3415 CW |
13224 | /* Should only be called after a successful intel_prepare_plane_fb()! */ |
13225 | vma = fetch_and_zero(&to_intel_plane_state(old_state)->vma); | |
13226 | if (vma) | |
13227 | intel_unpin_fb_vma(vma); | |
465c120c MR |
13228 | } |
13229 | ||
6156a456 CK |
13230 | int |
13231 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
13232 | { | |
5b7280f0 | 13233 | struct drm_i915_private *dev_priv; |
6156a456 | 13234 | int max_scale; |
5b7280f0 | 13235 | int crtc_clock, max_dotclk; |
6156a456 | 13236 | |
bf8a0af0 | 13237 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
13238 | return DRM_PLANE_HELPER_NO_SCALING; |
13239 | ||
5b7280f0 ACO |
13240 | dev_priv = to_i915(intel_crtc->base.dev); |
13241 | ||
6156a456 | 13242 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; |
5b7280f0 ACO |
13243 | max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk; |
13244 | ||
13245 | if (IS_GEMINILAKE(dev_priv)) | |
13246 | max_dotclk *= 2; | |
6156a456 | 13247 | |
5b7280f0 | 13248 | if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock)) |
6156a456 CK |
13249 | return DRM_PLANE_HELPER_NO_SCALING; |
13250 | ||
13251 | /* | |
13252 | * skl max scale is lower of: | |
13253 | * close to 3 but not 3, -1 is for that purpose | |
13254 | * or | |
13255 | * cdclk/crtc_clock | |
13256 | */ | |
5b7280f0 ACO |
13257 | max_scale = min((1 << 16) * 3 - 1, |
13258 | (1 << 8) * ((max_dotclk << 8) / crtc_clock)); | |
6156a456 CK |
13259 | |
13260 | return max_scale; | |
13261 | } | |
13262 | ||
465c120c | 13263 | static int |
3c692a41 | 13264 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 13265 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
13266 | struct intel_plane_state *state) |
13267 | { | |
b63a16f6 | 13268 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
2b875c22 | 13269 | struct drm_crtc *crtc = state->base.crtc; |
6156a456 | 13270 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
13271 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
13272 | bool can_position = false; | |
b63a16f6 | 13273 | int ret; |
465c120c | 13274 | |
b63a16f6 | 13275 | if (INTEL_GEN(dev_priv) >= 9) { |
693bdc28 VS |
13276 | /* use scaler when colorkey is not required */ |
13277 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
13278 | min_scale = 1; | |
13279 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
13280 | } | |
d8106366 | 13281 | can_position = true; |
6156a456 | 13282 | } |
d8106366 | 13283 | |
cc926387 DV |
13284 | ret = drm_plane_helper_check_state(&state->base, |
13285 | &state->clip, | |
13286 | min_scale, max_scale, | |
13287 | can_position, true); | |
b63a16f6 VS |
13288 | if (ret) |
13289 | return ret; | |
13290 | ||
cc926387 | 13291 | if (!state->base.fb) |
b63a16f6 VS |
13292 | return 0; |
13293 | ||
13294 | if (INTEL_GEN(dev_priv) >= 9) { | |
13295 | ret = skl_check_plane_surface(state); | |
13296 | if (ret) | |
13297 | return ret; | |
13298 | } | |
13299 | ||
13300 | return 0; | |
14af293f GP |
13301 | } |
13302 | ||
5a21b665 DV |
13303 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
13304 | struct drm_crtc_state *old_crtc_state) | |
13305 | { | |
13306 | struct drm_device *dev = crtc->dev; | |
62e0fb88 | 13307 | struct drm_i915_private *dev_priv = to_i915(dev); |
5a21b665 | 13308 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
b707aa50 L |
13309 | struct intel_crtc_state *intel_cstate = |
13310 | to_intel_crtc_state(crtc->state); | |
ccf010fb | 13311 | struct intel_crtc_state *old_intel_cstate = |
5a21b665 | 13312 | to_intel_crtc_state(old_crtc_state); |
ccf010fb ML |
13313 | struct intel_atomic_state *old_intel_state = |
13314 | to_intel_atomic_state(old_crtc_state->state); | |
5a21b665 DV |
13315 | bool modeset = needs_modeset(crtc->state); |
13316 | ||
567f0792 ML |
13317 | if (!modeset && |
13318 | (intel_cstate->base.color_mgmt_changed || | |
13319 | intel_cstate->update_pipe)) { | |
13320 | intel_color_set_csc(crtc->state); | |
13321 | intel_color_load_luts(crtc->state); | |
13322 | } | |
13323 | ||
5a21b665 DV |
13324 | /* Perform vblank evasion around commit operation */ |
13325 | intel_pipe_update_start(intel_crtc); | |
13326 | ||
13327 | if (modeset) | |
e62929b3 | 13328 | goto out; |
5a21b665 | 13329 | |
ccf010fb ML |
13330 | if (intel_cstate->update_pipe) |
13331 | intel_update_pipe_config(intel_crtc, old_intel_cstate); | |
13332 | else if (INTEL_GEN(dev_priv) >= 9) | |
5a21b665 | 13333 | skl_detach_scalers(intel_crtc); |
62e0fb88 | 13334 | |
e62929b3 | 13335 | out: |
ccf010fb ML |
13336 | if (dev_priv->display.atomic_update_watermarks) |
13337 | dev_priv->display.atomic_update_watermarks(old_intel_state, | |
13338 | intel_cstate); | |
5a21b665 DV |
13339 | } |
13340 | ||
13341 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, | |
13342 | struct drm_crtc_state *old_crtc_state) | |
13343 | { | |
13344 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
13345 | ||
13346 | intel_pipe_update_end(intel_crtc, NULL); | |
13347 | } | |
13348 | ||
cf4c7c12 | 13349 | /** |
4a3b8769 MR |
13350 | * intel_plane_destroy - destroy a plane |
13351 | * @plane: plane to destroy | |
cf4c7c12 | 13352 | * |
4a3b8769 MR |
13353 | * Common destruction function for all types of planes (primary, cursor, |
13354 | * sprite). | |
cf4c7c12 | 13355 | */ |
4a3b8769 | 13356 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c | 13357 | { |
465c120c | 13358 | drm_plane_cleanup(plane); |
69ae561f | 13359 | kfree(to_intel_plane(plane)); |
465c120c MR |
13360 | } |
13361 | ||
65a3fea0 | 13362 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
13363 | .update_plane = drm_atomic_helper_update_plane, |
13364 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 13365 | .destroy = intel_plane_destroy, |
c196e1d6 | 13366 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
13367 | .atomic_get_property = intel_plane_atomic_get_property, |
13368 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
13369 | .atomic_duplicate_state = intel_plane_duplicate_state, |
13370 | .atomic_destroy_state = intel_plane_destroy_state, | |
465c120c MR |
13371 | }; |
13372 | ||
f79f2692 ML |
13373 | static int |
13374 | intel_legacy_cursor_update(struct drm_plane *plane, | |
13375 | struct drm_crtc *crtc, | |
13376 | struct drm_framebuffer *fb, | |
13377 | int crtc_x, int crtc_y, | |
13378 | unsigned int crtc_w, unsigned int crtc_h, | |
13379 | uint32_t src_x, uint32_t src_y, | |
13380 | uint32_t src_w, uint32_t src_h) | |
13381 | { | |
13382 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
13383 | int ret; | |
13384 | struct drm_plane_state *old_plane_state, *new_plane_state; | |
13385 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13386 | struct drm_framebuffer *old_fb; | |
13387 | struct drm_crtc_state *crtc_state = crtc->state; | |
be1e3415 | 13388 | struct i915_vma *old_vma; |
f79f2692 ML |
13389 | |
13390 | /* | |
13391 | * When crtc is inactive or there is a modeset pending, | |
13392 | * wait for it to complete in the slowpath | |
13393 | */ | |
13394 | if (!crtc_state->active || needs_modeset(crtc_state) || | |
13395 | to_intel_crtc_state(crtc_state)->update_pipe) | |
13396 | goto slow; | |
13397 | ||
13398 | old_plane_state = plane->state; | |
13399 | ||
13400 | /* | |
13401 | * If any parameters change that may affect watermarks, | |
13402 | * take the slowpath. Only changing fb or position should be | |
13403 | * in the fastpath. | |
13404 | */ | |
13405 | if (old_plane_state->crtc != crtc || | |
13406 | old_plane_state->src_w != src_w || | |
13407 | old_plane_state->src_h != src_h || | |
13408 | old_plane_state->crtc_w != crtc_w || | |
13409 | old_plane_state->crtc_h != crtc_h || | |
a5509abd | 13410 | !old_plane_state->fb != !fb) |
f79f2692 ML |
13411 | goto slow; |
13412 | ||
13413 | new_plane_state = intel_plane_duplicate_state(plane); | |
13414 | if (!new_plane_state) | |
13415 | return -ENOMEM; | |
13416 | ||
13417 | drm_atomic_set_fb_for_plane(new_plane_state, fb); | |
13418 | ||
13419 | new_plane_state->src_x = src_x; | |
13420 | new_plane_state->src_y = src_y; | |
13421 | new_plane_state->src_w = src_w; | |
13422 | new_plane_state->src_h = src_h; | |
13423 | new_plane_state->crtc_x = crtc_x; | |
13424 | new_plane_state->crtc_y = crtc_y; | |
13425 | new_plane_state->crtc_w = crtc_w; | |
13426 | new_plane_state->crtc_h = crtc_h; | |
13427 | ||
13428 | ret = intel_plane_atomic_check_with_state(to_intel_crtc_state(crtc->state), | |
13429 | to_intel_plane_state(new_plane_state)); | |
13430 | if (ret) | |
13431 | goto out_free; | |
13432 | ||
f79f2692 ML |
13433 | ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex); |
13434 | if (ret) | |
13435 | goto out_free; | |
13436 | ||
13437 | if (INTEL_INFO(dev_priv)->cursor_needs_physical) { | |
13438 | int align = IS_I830(dev_priv) ? 16 * 1024 : 256; | |
13439 | ||
13440 | ret = i915_gem_object_attach_phys(intel_fb_obj(fb), align); | |
13441 | if (ret) { | |
13442 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13443 | goto out_unlock; | |
13444 | } | |
13445 | } else { | |
13446 | struct i915_vma *vma; | |
13447 | ||
13448 | vma = intel_pin_and_fence_fb_obj(fb, new_plane_state->rotation); | |
13449 | if (IS_ERR(vma)) { | |
13450 | DRM_DEBUG_KMS("failed to pin object\n"); | |
13451 | ||
13452 | ret = PTR_ERR(vma); | |
13453 | goto out_unlock; | |
13454 | } | |
be1e3415 CW |
13455 | |
13456 | to_intel_plane_state(new_plane_state)->vma = vma; | |
f79f2692 ML |
13457 | } |
13458 | ||
13459 | old_fb = old_plane_state->fb; | |
be1e3415 | 13460 | old_vma = to_intel_plane_state(old_plane_state)->vma; |
f79f2692 ML |
13461 | |
13462 | i915_gem_track_fb(intel_fb_obj(old_fb), intel_fb_obj(fb), | |
13463 | intel_plane->frontbuffer_bit); | |
13464 | ||
13465 | /* Swap plane state */ | |
13466 | new_plane_state->fence = old_plane_state->fence; | |
13467 | *to_intel_plane_state(old_plane_state) = *to_intel_plane_state(new_plane_state); | |
13468 | new_plane_state->fence = NULL; | |
13469 | new_plane_state->fb = old_fb; | |
be1e3415 | 13470 | to_intel_plane_state(new_plane_state)->vma = old_vma; |
f79f2692 | 13471 | |
72259536 VS |
13472 | if (plane->state->visible) { |
13473 | trace_intel_update_plane(plane, to_intel_crtc(crtc)); | |
a5509abd VS |
13474 | intel_plane->update_plane(plane, |
13475 | to_intel_crtc_state(crtc->state), | |
13476 | to_intel_plane_state(plane->state)); | |
72259536 VS |
13477 | } else { |
13478 | trace_intel_disable_plane(plane, to_intel_crtc(crtc)); | |
a5509abd | 13479 | intel_plane->disable_plane(plane, crtc); |
72259536 | 13480 | } |
f79f2692 ML |
13481 | |
13482 | intel_cleanup_plane_fb(plane, new_plane_state); | |
13483 | ||
13484 | out_unlock: | |
13485 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
13486 | out_free: | |
13487 | intel_plane_destroy_state(plane, new_plane_state); | |
13488 | return ret; | |
13489 | ||
f79f2692 ML |
13490 | slow: |
13491 | return drm_atomic_helper_update_plane(plane, crtc, fb, | |
13492 | crtc_x, crtc_y, crtc_w, crtc_h, | |
13493 | src_x, src_y, src_w, src_h); | |
13494 | } | |
13495 | ||
13496 | static const struct drm_plane_funcs intel_cursor_plane_funcs = { | |
13497 | .update_plane = intel_legacy_cursor_update, | |
13498 | .disable_plane = drm_atomic_helper_disable_plane, | |
13499 | .destroy = intel_plane_destroy, | |
13500 | .set_property = drm_atomic_helper_plane_set_property, | |
13501 | .atomic_get_property = intel_plane_atomic_get_property, | |
13502 | .atomic_set_property = intel_plane_atomic_set_property, | |
13503 | .atomic_duplicate_state = intel_plane_duplicate_state, | |
13504 | .atomic_destroy_state = intel_plane_destroy_state, | |
13505 | }; | |
13506 | ||
b079bd17 | 13507 | static struct intel_plane * |
580503c7 | 13508 | intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) |
465c120c | 13509 | { |
fca0ce2a VS |
13510 | struct intel_plane *primary = NULL; |
13511 | struct intel_plane_state *state = NULL; | |
465c120c | 13512 | const uint32_t *intel_primary_formats; |
93ca7e00 | 13513 | unsigned int supported_rotations; |
45e3743a | 13514 | unsigned int num_formats; |
fca0ce2a | 13515 | int ret; |
465c120c MR |
13516 | |
13517 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
b079bd17 VS |
13518 | if (!primary) { |
13519 | ret = -ENOMEM; | |
fca0ce2a | 13520 | goto fail; |
b079bd17 | 13521 | } |
465c120c | 13522 | |
8e7d688b | 13523 | state = intel_create_plane_state(&primary->base); |
b079bd17 VS |
13524 | if (!state) { |
13525 | ret = -ENOMEM; | |
fca0ce2a | 13526 | goto fail; |
b079bd17 VS |
13527 | } |
13528 | ||
8e7d688b | 13529 | primary->base.state = &state->base; |
ea2c67bb | 13530 | |
465c120c MR |
13531 | primary->can_scale = false; |
13532 | primary->max_downscale = 1; | |
580503c7 | 13533 | if (INTEL_GEN(dev_priv) >= 9) { |
6156a456 | 13534 | primary->can_scale = true; |
af99ceda | 13535 | state->scaler_id = -1; |
6156a456 | 13536 | } |
465c120c | 13537 | primary->pipe = pipe; |
e3c566df VS |
13538 | /* |
13539 | * On gen2/3 only plane A can do FBC, but the panel fitter and LVDS | |
13540 | * port is hooked to pipe B. Hence we want plane A feeding pipe B. | |
13541 | */ | |
13542 | if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) < 4) | |
13543 | primary->plane = (enum plane) !pipe; | |
13544 | else | |
13545 | primary->plane = (enum plane) pipe; | |
b14e5848 | 13546 | primary->id = PLANE_PRIMARY; |
a9ff8714 | 13547 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 13548 | primary->check_plane = intel_check_primary_plane; |
465c120c | 13549 | |
580503c7 | 13550 | if (INTEL_GEN(dev_priv) >= 9) { |
6c0fd451 DL |
13551 | intel_primary_formats = skl_primary_formats; |
13552 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
a8d201af ML |
13553 | |
13554 | primary->update_plane = skylake_update_primary_plane; | |
13555 | primary->disable_plane = skylake_disable_primary_plane; | |
6e266956 | 13556 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
a8d201af ML |
13557 | intel_primary_formats = i965_primary_formats; |
13558 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
13559 | ||
13560 | primary->update_plane = ironlake_update_primary_plane; | |
13561 | primary->disable_plane = i9xx_disable_primary_plane; | |
580503c7 | 13562 | } else if (INTEL_GEN(dev_priv) >= 4) { |
568db4f2 DL |
13563 | intel_primary_formats = i965_primary_formats; |
13564 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
a8d201af ML |
13565 | |
13566 | primary->update_plane = i9xx_update_primary_plane; | |
13567 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
13568 | } else { |
13569 | intel_primary_formats = i8xx_primary_formats; | |
13570 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
a8d201af ML |
13571 | |
13572 | primary->update_plane = i9xx_update_primary_plane; | |
13573 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
13574 | } |
13575 | ||
580503c7 VS |
13576 | if (INTEL_GEN(dev_priv) >= 9) |
13577 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, | |
13578 | 0, &intel_plane_funcs, | |
38573dc1 VS |
13579 | intel_primary_formats, num_formats, |
13580 | DRM_PLANE_TYPE_PRIMARY, | |
13581 | "plane 1%c", pipe_name(pipe)); | |
9beb5fea | 13582 | else if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
580503c7 VS |
13583 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, |
13584 | 0, &intel_plane_funcs, | |
38573dc1 VS |
13585 | intel_primary_formats, num_formats, |
13586 | DRM_PLANE_TYPE_PRIMARY, | |
13587 | "primary %c", pipe_name(pipe)); | |
13588 | else | |
580503c7 VS |
13589 | ret = drm_universal_plane_init(&dev_priv->drm, &primary->base, |
13590 | 0, &intel_plane_funcs, | |
38573dc1 VS |
13591 | intel_primary_formats, num_formats, |
13592 | DRM_PLANE_TYPE_PRIMARY, | |
13593 | "plane %c", plane_name(primary->plane)); | |
fca0ce2a VS |
13594 | if (ret) |
13595 | goto fail; | |
48404c1e | 13596 | |
5481e27f | 13597 | if (INTEL_GEN(dev_priv) >= 9) { |
93ca7e00 VS |
13598 | supported_rotations = |
13599 | DRM_ROTATE_0 | DRM_ROTATE_90 | | |
13600 | DRM_ROTATE_180 | DRM_ROTATE_270; | |
4ea7be2b VS |
13601 | } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) { |
13602 | supported_rotations = | |
13603 | DRM_ROTATE_0 | DRM_ROTATE_180 | | |
13604 | DRM_REFLECT_X; | |
5481e27f | 13605 | } else if (INTEL_GEN(dev_priv) >= 4) { |
93ca7e00 VS |
13606 | supported_rotations = |
13607 | DRM_ROTATE_0 | DRM_ROTATE_180; | |
13608 | } else { | |
13609 | supported_rotations = DRM_ROTATE_0; | |
13610 | } | |
13611 | ||
5481e27f | 13612 | if (INTEL_GEN(dev_priv) >= 4) |
93ca7e00 VS |
13613 | drm_plane_create_rotation_property(&primary->base, |
13614 | DRM_ROTATE_0, | |
13615 | supported_rotations); | |
48404c1e | 13616 | |
ea2c67bb MR |
13617 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
13618 | ||
b079bd17 | 13619 | return primary; |
fca0ce2a VS |
13620 | |
13621 | fail: | |
13622 | kfree(state); | |
13623 | kfree(primary); | |
13624 | ||
b079bd17 | 13625 | return ERR_PTR(ret); |
465c120c MR |
13626 | } |
13627 | ||
3d7d6510 | 13628 | static int |
852e787c | 13629 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 13630 | struct intel_crtc_state *crtc_state, |
852e787c | 13631 | struct intel_plane_state *state) |
3d7d6510 | 13632 | { |
2b875c22 | 13633 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 13634 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
b29ec92c | 13635 | enum pipe pipe = to_intel_plane(plane)->pipe; |
757f9a3e GP |
13636 | unsigned stride; |
13637 | int ret; | |
3d7d6510 | 13638 | |
f8856a44 VS |
13639 | ret = drm_plane_helper_check_state(&state->base, |
13640 | &state->clip, | |
13641 | DRM_PLANE_HELPER_NO_SCALING, | |
13642 | DRM_PLANE_HELPER_NO_SCALING, | |
13643 | true, true); | |
757f9a3e GP |
13644 | if (ret) |
13645 | return ret; | |
13646 | ||
757f9a3e GP |
13647 | /* if we want to turn off the cursor ignore width and height */ |
13648 | if (!obj) | |
da20eabd | 13649 | return 0; |
757f9a3e | 13650 | |
757f9a3e | 13651 | /* Check for which cursor types we support */ |
50a0bc90 TU |
13652 | if (!cursor_size_ok(to_i915(plane->dev), state->base.crtc_w, |
13653 | state->base.crtc_h)) { | |
ea2c67bb MR |
13654 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
13655 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
13656 | return -EINVAL; |
13657 | } | |
13658 | ||
ea2c67bb MR |
13659 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
13660 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
13661 | DRM_DEBUG_KMS("buffer is too small\n"); |
13662 | return -ENOMEM; | |
13663 | } | |
13664 | ||
bae781b2 | 13665 | if (fb->modifier != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 13666 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 13667 | return -EINVAL; |
32b7eeec MR |
13668 | } |
13669 | ||
b29ec92c VS |
13670 | /* |
13671 | * There's something wrong with the cursor on CHV pipe C. | |
13672 | * If it straddles the left edge of the screen then | |
13673 | * moving it away from the edge or disabling it often | |
13674 | * results in a pipe underrun, and often that can lead to | |
13675 | * dead pipe (constant underrun reported, and it scans | |
13676 | * out just a solid color). To recover from that, the | |
13677 | * display power well must be turned off and on again. | |
13678 | * Refuse the put the cursor into that compromised position. | |
13679 | */ | |
920a14b2 | 13680 | if (IS_CHERRYVIEW(to_i915(plane->dev)) && pipe == PIPE_C && |
936e71e3 | 13681 | state->base.visible && state->base.crtc_x < 0) { |
b29ec92c VS |
13682 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); |
13683 | return -EINVAL; | |
13684 | } | |
13685 | ||
da20eabd | 13686 | return 0; |
852e787c | 13687 | } |
3d7d6510 | 13688 | |
a8ad0d8e ML |
13689 | static void |
13690 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 13691 | struct drm_crtc *crtc) |
a8ad0d8e | 13692 | { |
f2858021 ML |
13693 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13694 | ||
13695 | intel_crtc->cursor_addr = 0; | |
55a08b3f | 13696 | intel_crtc_update_cursor(crtc, NULL); |
a8ad0d8e ML |
13697 | } |
13698 | ||
f4a2cf29 | 13699 | static void |
55a08b3f ML |
13700 | intel_update_cursor_plane(struct drm_plane *plane, |
13701 | const struct intel_crtc_state *crtc_state, | |
13702 | const struct intel_plane_state *state) | |
852e787c | 13703 | { |
55a08b3f ML |
13704 | struct drm_crtc *crtc = crtc_state->base.crtc; |
13705 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b7f05d4a | 13706 | struct drm_i915_private *dev_priv = to_i915(plane->dev); |
2b875c22 | 13707 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 13708 | uint32_t addr; |
852e787c | 13709 | |
f4a2cf29 | 13710 | if (!obj) |
a912f12f | 13711 | addr = 0; |
b7f05d4a | 13712 | else if (!INTEL_INFO(dev_priv)->cursor_needs_physical) |
be1e3415 | 13713 | addr = intel_plane_ggtt_offset(state); |
f4a2cf29 | 13714 | else |
a912f12f | 13715 | addr = obj->phys_handle->busaddr; |
852e787c | 13716 | |
a912f12f | 13717 | intel_crtc->cursor_addr = addr; |
55a08b3f | 13718 | intel_crtc_update_cursor(crtc, state); |
852e787c GP |
13719 | } |
13720 | ||
b079bd17 | 13721 | static struct intel_plane * |
580503c7 | 13722 | intel_cursor_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) |
3d7d6510 | 13723 | { |
fca0ce2a VS |
13724 | struct intel_plane *cursor = NULL; |
13725 | struct intel_plane_state *state = NULL; | |
13726 | int ret; | |
3d7d6510 MR |
13727 | |
13728 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
b079bd17 VS |
13729 | if (!cursor) { |
13730 | ret = -ENOMEM; | |
fca0ce2a | 13731 | goto fail; |
b079bd17 | 13732 | } |
3d7d6510 | 13733 | |
8e7d688b | 13734 | state = intel_create_plane_state(&cursor->base); |
b079bd17 VS |
13735 | if (!state) { |
13736 | ret = -ENOMEM; | |
fca0ce2a | 13737 | goto fail; |
b079bd17 VS |
13738 | } |
13739 | ||
8e7d688b | 13740 | cursor->base.state = &state->base; |
ea2c67bb | 13741 | |
3d7d6510 MR |
13742 | cursor->can_scale = false; |
13743 | cursor->max_downscale = 1; | |
13744 | cursor->pipe = pipe; | |
13745 | cursor->plane = pipe; | |
b14e5848 | 13746 | cursor->id = PLANE_CURSOR; |
a9ff8714 | 13747 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 | 13748 | cursor->check_plane = intel_check_cursor_plane; |
55a08b3f | 13749 | cursor->update_plane = intel_update_cursor_plane; |
a8ad0d8e | 13750 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 | 13751 | |
580503c7 | 13752 | ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base, |
f79f2692 | 13753 | 0, &intel_cursor_plane_funcs, |
fca0ce2a VS |
13754 | intel_cursor_formats, |
13755 | ARRAY_SIZE(intel_cursor_formats), | |
38573dc1 VS |
13756 | DRM_PLANE_TYPE_CURSOR, |
13757 | "cursor %c", pipe_name(pipe)); | |
fca0ce2a VS |
13758 | if (ret) |
13759 | goto fail; | |
4398ad45 | 13760 | |
5481e27f | 13761 | if (INTEL_GEN(dev_priv) >= 4) |
93ca7e00 VS |
13762 | drm_plane_create_rotation_property(&cursor->base, |
13763 | DRM_ROTATE_0, | |
13764 | DRM_ROTATE_0 | | |
13765 | DRM_ROTATE_180); | |
4398ad45 | 13766 | |
580503c7 | 13767 | if (INTEL_GEN(dev_priv) >= 9) |
af99ceda CK |
13768 | state->scaler_id = -1; |
13769 | ||
ea2c67bb MR |
13770 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
13771 | ||
b079bd17 | 13772 | return cursor; |
fca0ce2a VS |
13773 | |
13774 | fail: | |
13775 | kfree(state); | |
13776 | kfree(cursor); | |
13777 | ||
b079bd17 | 13778 | return ERR_PTR(ret); |
3d7d6510 MR |
13779 | } |
13780 | ||
1c74eeaf NM |
13781 | static void intel_crtc_init_scalers(struct intel_crtc *crtc, |
13782 | struct intel_crtc_state *crtc_state) | |
549e2bfb | 13783 | { |
65edccce VS |
13784 | struct intel_crtc_scaler_state *scaler_state = |
13785 | &crtc_state->scaler_state; | |
1c74eeaf | 13786 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
549e2bfb | 13787 | int i; |
549e2bfb | 13788 | |
1c74eeaf NM |
13789 | crtc->num_scalers = dev_priv->info.num_scalers[crtc->pipe]; |
13790 | if (!crtc->num_scalers) | |
13791 | return; | |
13792 | ||
65edccce VS |
13793 | for (i = 0; i < crtc->num_scalers; i++) { |
13794 | struct intel_scaler *scaler = &scaler_state->scalers[i]; | |
13795 | ||
13796 | scaler->in_use = 0; | |
13797 | scaler->mode = PS_SCALER_MODE_DYN; | |
549e2bfb CK |
13798 | } |
13799 | ||
13800 | scaler_state->scaler_id = -1; | |
13801 | } | |
13802 | ||
5ab0d85b | 13803 | static int intel_crtc_init(struct drm_i915_private *dev_priv, enum pipe pipe) |
79e53945 JB |
13804 | { |
13805 | struct intel_crtc *intel_crtc; | |
f5de6e07 | 13806 | struct intel_crtc_state *crtc_state = NULL; |
b079bd17 VS |
13807 | struct intel_plane *primary = NULL; |
13808 | struct intel_plane *cursor = NULL; | |
a81d6fa0 | 13809 | int sprite, ret; |
79e53945 | 13810 | |
955382f3 | 13811 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
b079bd17 VS |
13812 | if (!intel_crtc) |
13813 | return -ENOMEM; | |
79e53945 | 13814 | |
f5de6e07 | 13815 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
b079bd17 VS |
13816 | if (!crtc_state) { |
13817 | ret = -ENOMEM; | |
f5de6e07 | 13818 | goto fail; |
b079bd17 | 13819 | } |
550acefd ACO |
13820 | intel_crtc->config = crtc_state; |
13821 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 13822 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 13823 | |
580503c7 | 13824 | primary = intel_primary_plane_create(dev_priv, pipe); |
b079bd17 VS |
13825 | if (IS_ERR(primary)) { |
13826 | ret = PTR_ERR(primary); | |
3d7d6510 | 13827 | goto fail; |
b079bd17 | 13828 | } |
d97d7b48 | 13829 | intel_crtc->plane_ids_mask |= BIT(primary->id); |
3d7d6510 | 13830 | |
a81d6fa0 | 13831 | for_each_sprite(dev_priv, pipe, sprite) { |
b079bd17 VS |
13832 | struct intel_plane *plane; |
13833 | ||
580503c7 | 13834 | plane = intel_sprite_plane_create(dev_priv, pipe, sprite); |
d2b2cbce | 13835 | if (IS_ERR(plane)) { |
b079bd17 VS |
13836 | ret = PTR_ERR(plane); |
13837 | goto fail; | |
13838 | } | |
d97d7b48 | 13839 | intel_crtc->plane_ids_mask |= BIT(plane->id); |
a81d6fa0 VS |
13840 | } |
13841 | ||
580503c7 | 13842 | cursor = intel_cursor_plane_create(dev_priv, pipe); |
d2b2cbce | 13843 | if (IS_ERR(cursor)) { |
b079bd17 | 13844 | ret = PTR_ERR(cursor); |
3d7d6510 | 13845 | goto fail; |
b079bd17 | 13846 | } |
d97d7b48 | 13847 | intel_crtc->plane_ids_mask |= BIT(cursor->id); |
3d7d6510 | 13848 | |
5ab0d85b | 13849 | ret = drm_crtc_init_with_planes(&dev_priv->drm, &intel_crtc->base, |
b079bd17 VS |
13850 | &primary->base, &cursor->base, |
13851 | &intel_crtc_funcs, | |
4d5d72b7 | 13852 | "pipe %c", pipe_name(pipe)); |
3d7d6510 MR |
13853 | if (ret) |
13854 | goto fail; | |
79e53945 | 13855 | |
80824003 | 13856 | intel_crtc->pipe = pipe; |
e3c566df | 13857 | intel_crtc->plane = primary->plane; |
80824003 | 13858 | |
4b0e333e CW |
13859 | intel_crtc->cursor_base = ~0; |
13860 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 13861 | intel_crtc->cursor_size = ~0; |
8d7849db | 13862 | |
1c74eeaf NM |
13863 | /* initialize shared scalers */ |
13864 | intel_crtc_init_scalers(intel_crtc, crtc_state); | |
13865 | ||
22fd0fab JB |
13866 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
13867 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
e2af48c6 VS |
13868 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = intel_crtc; |
13869 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = intel_crtc; | |
22fd0fab | 13870 | |
79e53945 | 13871 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 | 13872 | |
8563b1e8 LL |
13873 | intel_color_init(&intel_crtc->base); |
13874 | ||
87b6b101 | 13875 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
b079bd17 VS |
13876 | |
13877 | return 0; | |
3d7d6510 MR |
13878 | |
13879 | fail: | |
b079bd17 VS |
13880 | /* |
13881 | * drm_mode_config_cleanup() will free up any | |
13882 | * crtcs/planes already initialized. | |
13883 | */ | |
f5de6e07 | 13884 | kfree(crtc_state); |
3d7d6510 | 13885 | kfree(intel_crtc); |
b079bd17 VS |
13886 | |
13887 | return ret; | |
79e53945 JB |
13888 | } |
13889 | ||
752aa88a JB |
13890 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
13891 | { | |
6e9f798d | 13892 | struct drm_device *dev = connector->base.dev; |
752aa88a | 13893 | |
51fd371b | 13894 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 13895 | |
51ec53da | 13896 | if (!connector->base.state->crtc) |
752aa88a JB |
13897 | return INVALID_PIPE; |
13898 | ||
51ec53da | 13899 | return to_intel_crtc(connector->base.state->crtc)->pipe; |
752aa88a JB |
13900 | } |
13901 | ||
08d7b3d1 | 13902 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 13903 | struct drm_file *file) |
08d7b3d1 | 13904 | { |
08d7b3d1 | 13905 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 13906 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 13907 | struct intel_crtc *crtc; |
08d7b3d1 | 13908 | |
7707e653 | 13909 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
71240ed2 | 13910 | if (!drmmode_crtc) |
3f2c2057 | 13911 | return -ENOENT; |
08d7b3d1 | 13912 | |
7707e653 | 13913 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 13914 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 13915 | |
c05422d5 | 13916 | return 0; |
08d7b3d1 CW |
13917 | } |
13918 | ||
66a9278e | 13919 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 13920 | { |
66a9278e DV |
13921 | struct drm_device *dev = encoder->base.dev; |
13922 | struct intel_encoder *source_encoder; | |
79e53945 | 13923 | int index_mask = 0; |
79e53945 JB |
13924 | int entry = 0; |
13925 | ||
b2784e15 | 13926 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 13927 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
13928 | index_mask |= (1 << entry); |
13929 | ||
79e53945 JB |
13930 | entry++; |
13931 | } | |
4ef69c7a | 13932 | |
79e53945 JB |
13933 | return index_mask; |
13934 | } | |
13935 | ||
646d5772 | 13936 | static bool has_edp_a(struct drm_i915_private *dev_priv) |
4d302442 | 13937 | { |
646d5772 | 13938 | if (!IS_MOBILE(dev_priv)) |
4d302442 CW |
13939 | return false; |
13940 | ||
13941 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
13942 | return false; | |
13943 | ||
5db94019 | 13944 | if (IS_GEN5(dev_priv) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
13945 | return false; |
13946 | ||
13947 | return true; | |
13948 | } | |
13949 | ||
6315b5d3 | 13950 | static bool intel_crt_present(struct drm_i915_private *dev_priv) |
84b4e042 | 13951 | { |
6315b5d3 | 13952 | if (INTEL_GEN(dev_priv) >= 9) |
884497ed DL |
13953 | return false; |
13954 | ||
50a0bc90 | 13955 | if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv)) |
84b4e042 JB |
13956 | return false; |
13957 | ||
920a14b2 | 13958 | if (IS_CHERRYVIEW(dev_priv)) |
84b4e042 JB |
13959 | return false; |
13960 | ||
4f8036a2 TU |
13961 | if (HAS_PCH_LPT_H(dev_priv) && |
13962 | I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) | |
65e472e4 VS |
13963 | return false; |
13964 | ||
70ac54d0 | 13965 | /* DDI E can't be used if DDI A requires 4 lanes */ |
4f8036a2 | 13966 | if (HAS_DDI(dev_priv) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) |
70ac54d0 VS |
13967 | return false; |
13968 | ||
e4abb733 | 13969 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
13970 | return false; |
13971 | ||
13972 | return true; | |
13973 | } | |
13974 | ||
8090ba8c ID |
13975 | void intel_pps_unlock_regs_wa(struct drm_i915_private *dev_priv) |
13976 | { | |
13977 | int pps_num; | |
13978 | int pps_idx; | |
13979 | ||
13980 | if (HAS_DDI(dev_priv)) | |
13981 | return; | |
13982 | /* | |
13983 | * This w/a is needed at least on CPT/PPT, but to be sure apply it | |
13984 | * everywhere where registers can be write protected. | |
13985 | */ | |
13986 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
13987 | pps_num = 2; | |
13988 | else | |
13989 | pps_num = 1; | |
13990 | ||
13991 | for (pps_idx = 0; pps_idx < pps_num; pps_idx++) { | |
13992 | u32 val = I915_READ(PP_CONTROL(pps_idx)); | |
13993 | ||
13994 | val = (val & ~PANEL_UNLOCK_MASK) | PANEL_UNLOCK_REGS; | |
13995 | I915_WRITE(PP_CONTROL(pps_idx), val); | |
13996 | } | |
13997 | } | |
13998 | ||
44cb734c ID |
13999 | static void intel_pps_init(struct drm_i915_private *dev_priv) |
14000 | { | |
cc3f90f0 | 14001 | if (HAS_PCH_SPLIT(dev_priv) || IS_GEN9_LP(dev_priv)) |
44cb734c ID |
14002 | dev_priv->pps_mmio_base = PCH_PPS_BASE; |
14003 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
14004 | dev_priv->pps_mmio_base = VLV_PPS_BASE; | |
14005 | else | |
14006 | dev_priv->pps_mmio_base = PPS_BASE; | |
8090ba8c ID |
14007 | |
14008 | intel_pps_unlock_regs_wa(dev_priv); | |
44cb734c ID |
14009 | } |
14010 | ||
c39055b0 | 14011 | static void intel_setup_outputs(struct drm_i915_private *dev_priv) |
79e53945 | 14012 | { |
4ef69c7a | 14013 | struct intel_encoder *encoder; |
cb0953d7 | 14014 | bool dpd_is_edp = false; |
79e53945 | 14015 | |
44cb734c ID |
14016 | intel_pps_init(dev_priv); |
14017 | ||
97a824e1 ID |
14018 | /* |
14019 | * intel_edp_init_connector() depends on this completing first, to | |
14020 | * prevent the registeration of both eDP and LVDS and the incorrect | |
14021 | * sharing of the PPS. | |
14022 | */ | |
c39055b0 | 14023 | intel_lvds_init(dev_priv); |
79e53945 | 14024 | |
6315b5d3 | 14025 | if (intel_crt_present(dev_priv)) |
c39055b0 | 14026 | intel_crt_init(dev_priv); |
cb0953d7 | 14027 | |
cc3f90f0 | 14028 | if (IS_GEN9_LP(dev_priv)) { |
c776eb2e VK |
14029 | /* |
14030 | * FIXME: Broxton doesn't support port detection via the | |
14031 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14032 | * detect the ports. | |
14033 | */ | |
c39055b0 ACO |
14034 | intel_ddi_init(dev_priv, PORT_A); |
14035 | intel_ddi_init(dev_priv, PORT_B); | |
14036 | intel_ddi_init(dev_priv, PORT_C); | |
c6c794a2 | 14037 | |
c39055b0 | 14038 | intel_dsi_init(dev_priv); |
4f8036a2 | 14039 | } else if (HAS_DDI(dev_priv)) { |
0e72a5b5 ED |
14040 | int found; |
14041 | ||
de31facd JB |
14042 | /* |
14043 | * Haswell uses DDI functions to detect digital outputs. | |
14044 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14045 | * it's there. | |
14046 | */ | |
77179400 | 14047 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 14048 | /* WaIgnoreDDIAStrap: skl */ |
b976dc53 | 14049 | if (found || IS_GEN9_BC(dev_priv)) |
c39055b0 | 14050 | intel_ddi_init(dev_priv, PORT_A); |
0e72a5b5 ED |
14051 | |
14052 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14053 | * register */ | |
14054 | found = I915_READ(SFUSE_STRAP); | |
14055 | ||
14056 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
c39055b0 | 14057 | intel_ddi_init(dev_priv, PORT_B); |
0e72a5b5 | 14058 | if (found & SFUSE_STRAP_DDIC_DETECTED) |
c39055b0 | 14059 | intel_ddi_init(dev_priv, PORT_C); |
0e72a5b5 | 14060 | if (found & SFUSE_STRAP_DDID_DETECTED) |
c39055b0 | 14061 | intel_ddi_init(dev_priv, PORT_D); |
2800e4c2 RV |
14062 | /* |
14063 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
14064 | */ | |
b976dc53 | 14065 | if (IS_GEN9_BC(dev_priv) && |
2800e4c2 RV |
14066 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
14067 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
14068 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
c39055b0 | 14069 | intel_ddi_init(dev_priv, PORT_E); |
2800e4c2 | 14070 | |
6e266956 | 14071 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
cb0953d7 | 14072 | int found; |
dd11bc10 | 14073 | dpd_is_edp = intel_dp_is_edp(dev_priv, PORT_D); |
270b3042 | 14074 | |
646d5772 | 14075 | if (has_edp_a(dev_priv)) |
c39055b0 | 14076 | intel_dp_init(dev_priv, DP_A, PORT_A); |
cb0953d7 | 14077 | |
dc0fa718 | 14078 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14079 | /* PCH SDVOB multiplex with HDMIB */ |
c39055b0 | 14080 | found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B); |
30ad48b7 | 14081 | if (!found) |
c39055b0 | 14082 | intel_hdmi_init(dev_priv, PCH_HDMIB, PORT_B); |
5eb08b69 | 14083 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
c39055b0 | 14084 | intel_dp_init(dev_priv, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14085 | } |
14086 | ||
dc0fa718 | 14087 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
c39055b0 | 14088 | intel_hdmi_init(dev_priv, PCH_HDMIC, PORT_C); |
30ad48b7 | 14089 | |
dc0fa718 | 14090 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
c39055b0 | 14091 | intel_hdmi_init(dev_priv, PCH_HDMID, PORT_D); |
30ad48b7 | 14092 | |
5eb08b69 | 14093 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
c39055b0 | 14094 | intel_dp_init(dev_priv, PCH_DP_C, PORT_C); |
5eb08b69 | 14095 | |
270b3042 | 14096 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
c39055b0 | 14097 | intel_dp_init(dev_priv, PCH_DP_D, PORT_D); |
920a14b2 | 14098 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
22f35042 | 14099 | bool has_edp, has_port; |
457c52d8 | 14100 | |
e17ac6db VS |
14101 | /* |
14102 | * The DP_DETECTED bit is the latched state of the DDC | |
14103 | * SDA pin at boot. However since eDP doesn't require DDC | |
14104 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14105 | * eDP ports may have been muxed to an alternate function. | |
14106 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14107 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14108 | * detect eDP ports. | |
22f35042 VS |
14109 | * |
14110 | * Sadly the straps seem to be missing sometimes even for HDMI | |
14111 | * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap | |
14112 | * and VBT for the presence of the port. Additionally we can't | |
14113 | * trust the port type the VBT declares as we've seen at least | |
14114 | * HDMI ports that the VBT claim are DP or eDP. | |
e17ac6db | 14115 | */ |
dd11bc10 | 14116 | has_edp = intel_dp_is_edp(dev_priv, PORT_B); |
22f35042 VS |
14117 | has_port = intel_bios_is_port_present(dev_priv, PORT_B); |
14118 | if (I915_READ(VLV_DP_B) & DP_DETECTED || has_port) | |
c39055b0 | 14119 | has_edp &= intel_dp_init(dev_priv, VLV_DP_B, PORT_B); |
22f35042 | 14120 | if ((I915_READ(VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp) |
c39055b0 | 14121 | intel_hdmi_init(dev_priv, VLV_HDMIB, PORT_B); |
585a94b8 | 14122 | |
dd11bc10 | 14123 | has_edp = intel_dp_is_edp(dev_priv, PORT_C); |
22f35042 VS |
14124 | has_port = intel_bios_is_port_present(dev_priv, PORT_C); |
14125 | if (I915_READ(VLV_DP_C) & DP_DETECTED || has_port) | |
c39055b0 | 14126 | has_edp &= intel_dp_init(dev_priv, VLV_DP_C, PORT_C); |
22f35042 | 14127 | if ((I915_READ(VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp) |
c39055b0 | 14128 | intel_hdmi_init(dev_priv, VLV_HDMIC, PORT_C); |
19c03924 | 14129 | |
920a14b2 | 14130 | if (IS_CHERRYVIEW(dev_priv)) { |
22f35042 VS |
14131 | /* |
14132 | * eDP not supported on port D, | |
14133 | * so no need to worry about it | |
14134 | */ | |
14135 | has_port = intel_bios_is_port_present(dev_priv, PORT_D); | |
14136 | if (I915_READ(CHV_DP_D) & DP_DETECTED || has_port) | |
c39055b0 | 14137 | intel_dp_init(dev_priv, CHV_DP_D, PORT_D); |
22f35042 | 14138 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED || has_port) |
c39055b0 | 14139 | intel_hdmi_init(dev_priv, CHV_HDMID, PORT_D); |
9418c1f1 VS |
14140 | } |
14141 | ||
c39055b0 | 14142 | intel_dsi_init(dev_priv); |
5db94019 | 14143 | } else if (!IS_GEN2(dev_priv) && !IS_PINEVIEW(dev_priv)) { |
27185ae1 | 14144 | bool found = false; |
7d57382e | 14145 | |
e2debe91 | 14146 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14147 | DRM_DEBUG_KMS("probing SDVOB\n"); |
c39055b0 | 14148 | found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B); |
9beb5fea | 14149 | if (!found && IS_G4X(dev_priv)) { |
b01f2c3a | 14150 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
c39055b0 | 14151 | intel_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14152 | } |
27185ae1 | 14153 | |
9beb5fea | 14154 | if (!found && IS_G4X(dev_priv)) |
c39055b0 | 14155 | intel_dp_init(dev_priv, DP_B, PORT_B); |
725e30ad | 14156 | } |
13520b05 KH |
14157 | |
14158 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14159 | |
e2debe91 | 14160 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14161 | DRM_DEBUG_KMS("probing SDVOC\n"); |
c39055b0 | 14162 | found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C); |
b01f2c3a | 14163 | } |
27185ae1 | 14164 | |
e2debe91 | 14165 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14166 | |
9beb5fea | 14167 | if (IS_G4X(dev_priv)) { |
b01f2c3a | 14168 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
c39055b0 | 14169 | intel_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14170 | } |
9beb5fea | 14171 | if (IS_G4X(dev_priv)) |
c39055b0 | 14172 | intel_dp_init(dev_priv, DP_C, PORT_C); |
725e30ad | 14173 | } |
27185ae1 | 14174 | |
9beb5fea | 14175 | if (IS_G4X(dev_priv) && (I915_READ(DP_D) & DP_DETECTED)) |
c39055b0 | 14176 | intel_dp_init(dev_priv, DP_D, PORT_D); |
5db94019 | 14177 | } else if (IS_GEN2(dev_priv)) |
c39055b0 | 14178 | intel_dvo_init(dev_priv); |
79e53945 | 14179 | |
56b857a5 | 14180 | if (SUPPORTS_TV(dev_priv)) |
c39055b0 | 14181 | intel_tv_init(dev_priv); |
79e53945 | 14182 | |
c39055b0 | 14183 | intel_psr_init(dev_priv); |
7c8f8a70 | 14184 | |
c39055b0 | 14185 | for_each_intel_encoder(&dev_priv->drm, encoder) { |
4ef69c7a CW |
14186 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14187 | encoder->base.possible_clones = | |
66a9278e | 14188 | intel_encoder_clones(encoder); |
79e53945 | 14189 | } |
47356eb6 | 14190 | |
c39055b0 | 14191 | intel_init_pch_refclk(dev_priv); |
270b3042 | 14192 | |
c39055b0 | 14193 | drm_helper_move_panel_connectors_to_head(&dev_priv->drm); |
79e53945 JB |
14194 | } |
14195 | ||
14196 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14197 | { | |
14198 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
79e53945 | 14199 | |
ef2d633e | 14200 | drm_framebuffer_cleanup(fb); |
70001cd2 | 14201 | |
dd689287 CW |
14202 | i915_gem_object_lock(intel_fb->obj); |
14203 | WARN_ON(!intel_fb->obj->framebuffer_references--); | |
14204 | i915_gem_object_unlock(intel_fb->obj); | |
14205 | ||
f8c417cd | 14206 | i915_gem_object_put(intel_fb->obj); |
70001cd2 | 14207 | |
79e53945 JB |
14208 | kfree(intel_fb); |
14209 | } | |
14210 | ||
14211 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14212 | struct drm_file *file, |
79e53945 JB |
14213 | unsigned int *handle) |
14214 | { | |
14215 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14216 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14217 | |
cc917ab4 CW |
14218 | if (obj->userptr.mm) { |
14219 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
14220 | return -EINVAL; | |
14221 | } | |
14222 | ||
05394f39 | 14223 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14224 | } |
14225 | ||
86c98588 RV |
14226 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
14227 | struct drm_file *file, | |
14228 | unsigned flags, unsigned color, | |
14229 | struct drm_clip_rect *clips, | |
14230 | unsigned num_clips) | |
14231 | { | |
5a97bcc6 | 14232 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
86c98588 | 14233 | |
5a97bcc6 | 14234 | i915_gem_object_flush_if_display(obj); |
d59b21ec | 14235 | intel_fb_obj_flush(obj, ORIGIN_DIRTYFB); |
86c98588 RV |
14236 | |
14237 | return 0; | |
14238 | } | |
14239 | ||
79e53945 JB |
14240 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
14241 | .destroy = intel_user_framebuffer_destroy, | |
14242 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 14243 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
14244 | }; |
14245 | ||
b321803d | 14246 | static |
920a14b2 TU |
14247 | u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv, |
14248 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 14249 | { |
24dbf51a | 14250 | u32 gen = INTEL_GEN(dev_priv); |
b321803d DL |
14251 | |
14252 | if (gen >= 9) { | |
ac484963 VS |
14253 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
14254 | ||
b321803d DL |
14255 | /* "The stride in bytes must not exceed the of the size of 8K |
14256 | * pixels and 32K bytes." | |
14257 | */ | |
ac484963 | 14258 | return min(8192 * cpp, 32768); |
6401c37d | 14259 | } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) { |
b321803d DL |
14260 | return 32*1024; |
14261 | } else if (gen >= 4) { | |
14262 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14263 | return 16*1024; | |
14264 | else | |
14265 | return 32*1024; | |
14266 | } else if (gen >= 3) { | |
14267 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14268 | return 8*1024; | |
14269 | else | |
14270 | return 16*1024; | |
14271 | } else { | |
14272 | /* XXX DSPC is limited to 4k tiled */ | |
14273 | return 8*1024; | |
14274 | } | |
14275 | } | |
14276 | ||
24dbf51a CW |
14277 | static int intel_framebuffer_init(struct intel_framebuffer *intel_fb, |
14278 | struct drm_i915_gem_object *obj, | |
14279 | struct drm_mode_fb_cmd2 *mode_cmd) | |
79e53945 | 14280 | { |
24dbf51a | 14281 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
b3c11ac2 | 14282 | struct drm_format_name_buf format_name; |
dd689287 CW |
14283 | u32 pitch_limit, stride_alignment; |
14284 | unsigned int tiling, stride; | |
24dbf51a | 14285 | int ret = -EINVAL; |
79e53945 | 14286 | |
dd689287 CW |
14287 | i915_gem_object_lock(obj); |
14288 | obj->framebuffer_references++; | |
14289 | tiling = i915_gem_object_get_tiling(obj); | |
14290 | stride = i915_gem_object_get_stride(obj); | |
14291 | i915_gem_object_unlock(obj); | |
dd4916c5 | 14292 | |
2a80eada | 14293 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
c2ff7370 VS |
14294 | /* |
14295 | * If there's a fence, enforce that | |
14296 | * the fb modifier and tiling mode match. | |
14297 | */ | |
14298 | if (tiling != I915_TILING_NONE && | |
14299 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
144cc143 | 14300 | DRM_DEBUG_KMS("tiling_mode doesn't match fb modifier\n"); |
24dbf51a | 14301 | goto err; |
2a80eada DV |
14302 | } |
14303 | } else { | |
c2ff7370 | 14304 | if (tiling == I915_TILING_X) { |
2a80eada | 14305 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; |
c2ff7370 | 14306 | } else if (tiling == I915_TILING_Y) { |
144cc143 | 14307 | DRM_DEBUG_KMS("No Y tiling for legacy addfb\n"); |
24dbf51a | 14308 | goto err; |
2a80eada DV |
14309 | } |
14310 | } | |
14311 | ||
9a8f0a12 TU |
14312 | /* Passed in modifier sanity checking. */ |
14313 | switch (mode_cmd->modifier[0]) { | |
14314 | case I915_FORMAT_MOD_Y_TILED: | |
14315 | case I915_FORMAT_MOD_Yf_TILED: | |
6315b5d3 | 14316 | if (INTEL_GEN(dev_priv) < 9) { |
144cc143 VS |
14317 | DRM_DEBUG_KMS("Unsupported tiling 0x%llx!\n", |
14318 | mode_cmd->modifier[0]); | |
24dbf51a | 14319 | goto err; |
9a8f0a12 TU |
14320 | } |
14321 | case DRM_FORMAT_MOD_NONE: | |
14322 | case I915_FORMAT_MOD_X_TILED: | |
14323 | break; | |
14324 | default: | |
144cc143 VS |
14325 | DRM_DEBUG_KMS("Unsupported fb modifier 0x%llx!\n", |
14326 | mode_cmd->modifier[0]); | |
24dbf51a | 14327 | goto err; |
c16ed4be | 14328 | } |
57cd6508 | 14329 | |
c2ff7370 VS |
14330 | /* |
14331 | * gen2/3 display engine uses the fence if present, | |
14332 | * so the tiling mode must match the fb modifier exactly. | |
14333 | */ | |
14334 | if (INTEL_INFO(dev_priv)->gen < 4 && | |
14335 | tiling != intel_fb_modifier_to_tiling(mode_cmd->modifier[0])) { | |
144cc143 | 14336 | DRM_DEBUG_KMS("tiling_mode must match fb modifier exactly on gen2/3\n"); |
9aceb5c1 | 14337 | goto err; |
c2ff7370 VS |
14338 | } |
14339 | ||
920a14b2 | 14340 | pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0], |
b321803d | 14341 | mode_cmd->pixel_format); |
a35cdaa0 | 14342 | if (mode_cmd->pitches[0] > pitch_limit) { |
144cc143 VS |
14343 | DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n", |
14344 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
14345 | "tiled" : "linear", | |
14346 | mode_cmd->pitches[0], pitch_limit); | |
24dbf51a | 14347 | goto err; |
c16ed4be | 14348 | } |
5d7bd705 | 14349 | |
c2ff7370 VS |
14350 | /* |
14351 | * If there's a fence, enforce that | |
14352 | * the fb pitch and fence stride match. | |
14353 | */ | |
144cc143 VS |
14354 | if (tiling != I915_TILING_NONE && mode_cmd->pitches[0] != stride) { |
14355 | DRM_DEBUG_KMS("pitch (%d) must match tiling stride (%d)\n", | |
14356 | mode_cmd->pitches[0], stride); | |
24dbf51a | 14357 | goto err; |
c16ed4be | 14358 | } |
5d7bd705 | 14359 | |
57779d06 | 14360 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14361 | switch (mode_cmd->pixel_format) { |
57779d06 | 14362 | case DRM_FORMAT_C8: |
04b3924d VS |
14363 | case DRM_FORMAT_RGB565: |
14364 | case DRM_FORMAT_XRGB8888: | |
14365 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14366 | break; |
14367 | case DRM_FORMAT_XRGB1555: | |
6315b5d3 | 14368 | if (INTEL_GEN(dev_priv) > 3) { |
144cc143 VS |
14369 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
14370 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14371 | goto err; |
c16ed4be | 14372 | } |
57779d06 | 14373 | break; |
57779d06 | 14374 | case DRM_FORMAT_ABGR8888: |
920a14b2 | 14375 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && |
6315b5d3 | 14376 | INTEL_GEN(dev_priv) < 9) { |
144cc143 VS |
14377 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
14378 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14379 | goto err; |
6c0fd451 DL |
14380 | } |
14381 | break; | |
14382 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 14383 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 14384 | case DRM_FORMAT_XBGR2101010: |
6315b5d3 | 14385 | if (INTEL_GEN(dev_priv) < 4) { |
144cc143 VS |
14386 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
14387 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14388 | goto err; |
c16ed4be | 14389 | } |
b5626747 | 14390 | break; |
7531208b | 14391 | case DRM_FORMAT_ABGR2101010: |
920a14b2 | 14392 | if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) { |
144cc143 VS |
14393 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
14394 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14395 | goto err; |
7531208b DL |
14396 | } |
14397 | break; | |
04b3924d VS |
14398 | case DRM_FORMAT_YUYV: |
14399 | case DRM_FORMAT_UYVY: | |
14400 | case DRM_FORMAT_YVYU: | |
14401 | case DRM_FORMAT_VYUY: | |
6315b5d3 | 14402 | if (INTEL_GEN(dev_priv) < 5) { |
144cc143 VS |
14403 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
14404 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14405 | goto err; |
c16ed4be | 14406 | } |
57cd6508 CW |
14407 | break; |
14408 | default: | |
144cc143 VS |
14409 | DRM_DEBUG_KMS("unsupported pixel format: %s\n", |
14410 | drm_get_format_name(mode_cmd->pixel_format, &format_name)); | |
9aceb5c1 | 14411 | goto err; |
57cd6508 CW |
14412 | } |
14413 | ||
90f9a336 VS |
14414 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14415 | if (mode_cmd->offsets[0] != 0) | |
24dbf51a | 14416 | goto err; |
90f9a336 | 14417 | |
24dbf51a CW |
14418 | drm_helper_mode_fill_fb_struct(&dev_priv->drm, |
14419 | &intel_fb->base, mode_cmd); | |
d88c4afd VS |
14420 | |
14421 | stride_alignment = intel_fb_stride_alignment(&intel_fb->base, 0); | |
14422 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
144cc143 VS |
14423 | DRM_DEBUG_KMS("pitch (%d) must be at least %u byte aligned\n", |
14424 | mode_cmd->pitches[0], stride_alignment); | |
d88c4afd VS |
14425 | goto err; |
14426 | } | |
14427 | ||
c7d73f6a DV |
14428 | intel_fb->obj = obj; |
14429 | ||
6687c906 VS |
14430 | ret = intel_fill_fb_info(dev_priv, &intel_fb->base); |
14431 | if (ret) | |
9aceb5c1 | 14432 | goto err; |
2d7a215f | 14433 | |
24dbf51a CW |
14434 | ret = drm_framebuffer_init(obj->base.dev, |
14435 | &intel_fb->base, | |
14436 | &intel_fb_funcs); | |
79e53945 JB |
14437 | if (ret) { |
14438 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
24dbf51a | 14439 | goto err; |
79e53945 JB |
14440 | } |
14441 | ||
79e53945 | 14442 | return 0; |
24dbf51a CW |
14443 | |
14444 | err: | |
dd689287 CW |
14445 | i915_gem_object_lock(obj); |
14446 | obj->framebuffer_references--; | |
14447 | i915_gem_object_unlock(obj); | |
24dbf51a | 14448 | return ret; |
79e53945 JB |
14449 | } |
14450 | ||
79e53945 JB |
14451 | static struct drm_framebuffer * |
14452 | intel_user_framebuffer_create(struct drm_device *dev, | |
14453 | struct drm_file *filp, | |
1eb83451 | 14454 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 14455 | { |
dcb1394e | 14456 | struct drm_framebuffer *fb; |
05394f39 | 14457 | struct drm_i915_gem_object *obj; |
76dc3769 | 14458 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 14459 | |
03ac0642 CW |
14460 | obj = i915_gem_object_lookup(filp, mode_cmd.handles[0]); |
14461 | if (!obj) | |
cce13ff7 | 14462 | return ERR_PTR(-ENOENT); |
79e53945 | 14463 | |
24dbf51a | 14464 | fb = intel_framebuffer_create(obj, &mode_cmd); |
dcb1394e | 14465 | if (IS_ERR(fb)) |
f0cd5182 | 14466 | i915_gem_object_put(obj); |
dcb1394e LW |
14467 | |
14468 | return fb; | |
79e53945 JB |
14469 | } |
14470 | ||
778e23a9 CW |
14471 | static void intel_atomic_state_free(struct drm_atomic_state *state) |
14472 | { | |
14473 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
14474 | ||
14475 | drm_atomic_state_default_release(state); | |
14476 | ||
14477 | i915_sw_fence_fini(&intel_state->commit_ready); | |
14478 | ||
14479 | kfree(state); | |
14480 | } | |
14481 | ||
79e53945 | 14482 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14483 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14484 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14485 | .atomic_check = intel_atomic_check, |
14486 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
14487 | .atomic_state_alloc = intel_atomic_state_alloc, |
14488 | .atomic_state_clear = intel_atomic_state_clear, | |
778e23a9 | 14489 | .atomic_state_free = intel_atomic_state_free, |
79e53945 JB |
14490 | }; |
14491 | ||
88212941 ID |
14492 | /** |
14493 | * intel_init_display_hooks - initialize the display modesetting hooks | |
14494 | * @dev_priv: device private | |
14495 | */ | |
14496 | void intel_init_display_hooks(struct drm_i915_private *dev_priv) | |
e70236a8 | 14497 | { |
7ff89ca2 VS |
14498 | intel_init_cdclk_hooks(dev_priv); |
14499 | ||
88212941 | 14500 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
bc8d7dff | 14501 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14502 | dev_priv->display.get_initial_plane_config = |
14503 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14504 | dev_priv->display.crtc_compute_clock = |
14505 | haswell_crtc_compute_clock; | |
14506 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14507 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 14508 | } else if (HAS_DDI(dev_priv)) { |
0e8ffe1b | 14509 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14510 | dev_priv->display.get_initial_plane_config = |
14511 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14512 | dev_priv->display.crtc_compute_clock = |
14513 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14514 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14515 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 14516 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
0e8ffe1b | 14517 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14518 | dev_priv->display.get_initial_plane_config = |
14519 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14520 | dev_priv->display.crtc_compute_clock = |
14521 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14522 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14523 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
65b3d6a9 | 14524 | } else if (IS_CHERRYVIEW(dev_priv)) { |
89b667f8 | 14525 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14526 | dev_priv->display.get_initial_plane_config = |
14527 | i9xx_get_initial_plane_config; | |
65b3d6a9 ACO |
14528 | dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; |
14529 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
14530 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
14531 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
14532 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14533 | dev_priv->display.get_initial_plane_config = | |
14534 | i9xx_get_initial_plane_config; | |
14535 | dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; | |
89b667f8 JB |
14536 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14537 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
19ec6693 ACO |
14538 | } else if (IS_G4X(dev_priv)) { |
14539 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14540 | dev_priv->display.get_initial_plane_config = | |
14541 | i9xx_get_initial_plane_config; | |
14542 | dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; | |
14543 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14544 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
70e8aa21 ACO |
14545 | } else if (IS_PINEVIEW(dev_priv)) { |
14546 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14547 | dev_priv->display.get_initial_plane_config = | |
14548 | i9xx_get_initial_plane_config; | |
14549 | dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; | |
14550 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14551 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 | 14552 | } else if (!IS_GEN2(dev_priv)) { |
0e8ffe1b | 14553 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14554 | dev_priv->display.get_initial_plane_config = |
14555 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14556 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14557 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14558 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 ACO |
14559 | } else { |
14560 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14561 | dev_priv->display.get_initial_plane_config = | |
14562 | i9xx_get_initial_plane_config; | |
14563 | dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; | |
14564 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14565 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 14566 | } |
e70236a8 | 14567 | |
88212941 | 14568 | if (IS_GEN5(dev_priv)) { |
3bb11b53 | 14569 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
88212941 | 14570 | } else if (IS_GEN6(dev_priv)) { |
3bb11b53 | 14571 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
88212941 | 14572 | } else if (IS_IVYBRIDGE(dev_priv)) { |
3bb11b53 SJ |
14573 | /* FIXME: detect B0+ stepping and use auto training */ |
14574 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
88212941 | 14575 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3bb11b53 | 14576 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
445e780b VS |
14577 | } |
14578 | ||
27082493 L |
14579 | if (dev_priv->info.gen >= 9) |
14580 | dev_priv->display.update_crtcs = skl_update_crtcs; | |
14581 | else | |
14582 | dev_priv->display.update_crtcs = intel_update_crtcs; | |
14583 | ||
5a21b665 DV |
14584 | switch (INTEL_INFO(dev_priv)->gen) { |
14585 | case 2: | |
14586 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
14587 | break; | |
14588 | ||
14589 | case 3: | |
14590 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
14591 | break; | |
14592 | ||
14593 | case 4: | |
14594 | case 5: | |
14595 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
14596 | break; | |
14597 | ||
14598 | case 6: | |
14599 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
14600 | break; | |
14601 | case 7: | |
14602 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ | |
14603 | dev_priv->display.queue_flip = intel_gen7_queue_flip; | |
14604 | break; | |
14605 | case 9: | |
14606 | /* Drop through - unsupported since execlist only. */ | |
14607 | default: | |
14608 | /* Default just returns -ENODEV to indicate unsupported */ | |
14609 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
14610 | } | |
e70236a8 JB |
14611 | } |
14612 | ||
b690e96c JB |
14613 | /* |
14614 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
14615 | * resume, or other times. This quirk makes sure that's the case for | |
14616 | * affected systems. | |
14617 | */ | |
0206e353 | 14618 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c | 14619 | { |
fac5e23e | 14620 | struct drm_i915_private *dev_priv = to_i915(dev); |
b690e96c JB |
14621 | |
14622 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 14623 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
14624 | } |
14625 | ||
b6b5d049 VS |
14626 | static void quirk_pipeb_force(struct drm_device *dev) |
14627 | { | |
fac5e23e | 14628 | struct drm_i915_private *dev_priv = to_i915(dev); |
b6b5d049 VS |
14629 | |
14630 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
14631 | DRM_INFO("applying pipe b force quirk\n"); | |
14632 | } | |
14633 | ||
435793df KP |
14634 | /* |
14635 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
14636 | */ | |
14637 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
14638 | { | |
fac5e23e | 14639 | struct drm_i915_private *dev_priv = to_i915(dev); |
435793df | 14640 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; |
bc0daf48 | 14641 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
14642 | } |
14643 | ||
4dca20ef | 14644 | /* |
5a15ab5b CE |
14645 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
14646 | * brightness value | |
4dca20ef CE |
14647 | */ |
14648 | static void quirk_invert_brightness(struct drm_device *dev) | |
14649 | { | |
fac5e23e | 14650 | struct drm_i915_private *dev_priv = to_i915(dev); |
4dca20ef | 14651 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; |
bc0daf48 | 14652 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
14653 | } |
14654 | ||
9c72cc6f SD |
14655 | /* Some VBT's incorrectly indicate no backlight is present */ |
14656 | static void quirk_backlight_present(struct drm_device *dev) | |
14657 | { | |
fac5e23e | 14658 | struct drm_i915_private *dev_priv = to_i915(dev); |
9c72cc6f SD |
14659 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; |
14660 | DRM_INFO("applying backlight present quirk\n"); | |
14661 | } | |
14662 | ||
b690e96c JB |
14663 | struct intel_quirk { |
14664 | int device; | |
14665 | int subsystem_vendor; | |
14666 | int subsystem_device; | |
14667 | void (*hook)(struct drm_device *dev); | |
14668 | }; | |
14669 | ||
5f85f176 EE |
14670 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
14671 | struct intel_dmi_quirk { | |
14672 | void (*hook)(struct drm_device *dev); | |
14673 | const struct dmi_system_id (*dmi_id_list)[]; | |
14674 | }; | |
14675 | ||
14676 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
14677 | { | |
14678 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
14679 | return 1; | |
14680 | } | |
14681 | ||
14682 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
14683 | { | |
14684 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
14685 | { | |
14686 | .callback = intel_dmi_reverse_brightness, | |
14687 | .ident = "NCR Corporation", | |
14688 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
14689 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
14690 | }, | |
14691 | }, | |
14692 | { } /* terminating entry */ | |
14693 | }, | |
14694 | .hook = quirk_invert_brightness, | |
14695 | }, | |
14696 | }; | |
14697 | ||
c43b5634 | 14698 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
14699 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
14700 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
14701 | ||
b690e96c JB |
14702 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
14703 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
14704 | ||
5f080c0f VS |
14705 | /* 830 needs to leave pipe A & dpll A up */ |
14706 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
14707 | ||
b6b5d049 VS |
14708 | /* 830 needs to leave pipe B & dpll B up */ |
14709 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
14710 | ||
435793df KP |
14711 | /* Lenovo U160 cannot use SSC on LVDS */ |
14712 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
14713 | |
14714 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
14715 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 14716 | |
be505f64 AH |
14717 | /* Acer Aspire 5734Z must invert backlight brightness */ |
14718 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
14719 | ||
14720 | /* Acer/eMachines G725 */ | |
14721 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
14722 | ||
14723 | /* Acer/eMachines e725 */ | |
14724 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
14725 | ||
14726 | /* Acer/Packard Bell NCL20 */ | |
14727 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
14728 | ||
14729 | /* Acer Aspire 4736Z */ | |
14730 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
14731 | |
14732 | /* Acer Aspire 5336 */ | |
14733 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
14734 | |
14735 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
14736 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 14737 | |
dfb3d47b SD |
14738 | /* Acer C720 Chromebook (Core i3 4005U) */ |
14739 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
14740 | ||
b2a9601c | 14741 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
14742 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
14743 | ||
1b9448b0 JN |
14744 | /* Apple Macbook 4,1 */ |
14745 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
14746 | ||
d4967d8c SD |
14747 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
14748 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
14749 | |
14750 | /* HP Chromebook 14 (Celeron 2955U) */ | |
14751 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
14752 | |
14753 | /* Dell Chromebook 11 */ | |
14754 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
14755 | |
14756 | /* Dell Chromebook 11 (2015 version) */ | |
14757 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
14758 | }; |
14759 | ||
14760 | static void intel_init_quirks(struct drm_device *dev) | |
14761 | { | |
14762 | struct pci_dev *d = dev->pdev; | |
14763 | int i; | |
14764 | ||
14765 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
14766 | struct intel_quirk *q = &intel_quirks[i]; | |
14767 | ||
14768 | if (d->device == q->device && | |
14769 | (d->subsystem_vendor == q->subsystem_vendor || | |
14770 | q->subsystem_vendor == PCI_ANY_ID) && | |
14771 | (d->subsystem_device == q->subsystem_device || | |
14772 | q->subsystem_device == PCI_ANY_ID)) | |
14773 | q->hook(dev); | |
14774 | } | |
5f85f176 EE |
14775 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
14776 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
14777 | intel_dmi_quirks[i].hook(dev); | |
14778 | } | |
b690e96c JB |
14779 | } |
14780 | ||
9cce37f4 | 14781 | /* Disable the VGA plane that we never use */ |
29b74b7f | 14782 | static void i915_disable_vga(struct drm_i915_private *dev_priv) |
9cce37f4 | 14783 | { |
52a05c30 | 14784 | struct pci_dev *pdev = dev_priv->drm.pdev; |
9cce37f4 | 14785 | u8 sr1; |
920a14b2 | 14786 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); |
9cce37f4 | 14787 | |
2b37c616 | 14788 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
52a05c30 | 14789 | vga_get_uninterruptible(pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 14790 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
14791 | sr1 = inb(VGA_SR_DATA); |
14792 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
52a05c30 | 14793 | vga_put(pdev, VGA_RSRC_LEGACY_IO); |
9cce37f4 JB |
14794 | udelay(300); |
14795 | ||
01f5a626 | 14796 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
14797 | POSTING_READ(vga_reg); |
14798 | } | |
14799 | ||
f817586c DV |
14800 | void intel_modeset_init_hw(struct drm_device *dev) |
14801 | { | |
fac5e23e | 14802 | struct drm_i915_private *dev_priv = to_i915(dev); |
1a617b77 | 14803 | |
4c75b940 | 14804 | intel_update_cdclk(dev_priv); |
bb0f4aab | 14805 | dev_priv->cdclk.logical = dev_priv->cdclk.actual = dev_priv->cdclk.hw; |
1a617b77 | 14806 | |
46f16e63 | 14807 | intel_init_clock_gating(dev_priv); |
f817586c DV |
14808 | } |
14809 | ||
d93c0372 MR |
14810 | /* |
14811 | * Calculate what we think the watermarks should be for the state we've read | |
14812 | * out of the hardware and then immediately program those watermarks so that | |
14813 | * we ensure the hardware settings match our internal state. | |
14814 | * | |
14815 | * We can calculate what we think WM's should be by creating a duplicate of the | |
14816 | * current state (which was constructed during hardware readout) and running it | |
14817 | * through the atomic check code to calculate new watermark values in the | |
14818 | * state object. | |
14819 | */ | |
14820 | static void sanitize_watermarks(struct drm_device *dev) | |
14821 | { | |
14822 | struct drm_i915_private *dev_priv = to_i915(dev); | |
14823 | struct drm_atomic_state *state; | |
ccf010fb | 14824 | struct intel_atomic_state *intel_state; |
d93c0372 MR |
14825 | struct drm_crtc *crtc; |
14826 | struct drm_crtc_state *cstate; | |
14827 | struct drm_modeset_acquire_ctx ctx; | |
14828 | int ret; | |
14829 | int i; | |
14830 | ||
14831 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 14832 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
14833 | return; |
14834 | ||
14835 | /* | |
14836 | * We need to hold connection_mutex before calling duplicate_state so | |
14837 | * that the connector loop is protected. | |
14838 | */ | |
14839 | drm_modeset_acquire_init(&ctx, 0); | |
14840 | retry: | |
0cd1262d | 14841 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
14842 | if (ret == -EDEADLK) { |
14843 | drm_modeset_backoff(&ctx); | |
14844 | goto retry; | |
14845 | } else if (WARN_ON(ret)) { | |
0cd1262d | 14846 | goto fail; |
d93c0372 MR |
14847 | } |
14848 | ||
14849 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
14850 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 14851 | goto fail; |
d93c0372 | 14852 | |
ccf010fb ML |
14853 | intel_state = to_intel_atomic_state(state); |
14854 | ||
ed4a6a7c MR |
14855 | /* |
14856 | * Hardware readout is the only time we don't want to calculate | |
14857 | * intermediate watermarks (since we don't trust the current | |
14858 | * watermarks). | |
14859 | */ | |
602ae835 VS |
14860 | if (!HAS_GMCH_DISPLAY(dev_priv)) |
14861 | intel_state->skip_intermediate_wm = true; | |
ed4a6a7c | 14862 | |
d93c0372 MR |
14863 | ret = intel_atomic_check(dev, state); |
14864 | if (ret) { | |
14865 | /* | |
14866 | * If we fail here, it means that the hardware appears to be | |
14867 | * programmed in a way that shouldn't be possible, given our | |
14868 | * understanding of watermark requirements. This might mean a | |
14869 | * mistake in the hardware readout code or a mistake in the | |
14870 | * watermark calculations for a given platform. Raise a WARN | |
14871 | * so that this is noticeable. | |
14872 | * | |
14873 | * If this actually happens, we'll have to just leave the | |
14874 | * BIOS-programmed watermarks untouched and hope for the best. | |
14875 | */ | |
14876 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
b9a1b717 | 14877 | goto put_state; |
d93c0372 MR |
14878 | } |
14879 | ||
14880 | /* Write calculated watermark values back */ | |
d93c0372 MR |
14881 | for_each_crtc_in_state(state, crtc, cstate, i) { |
14882 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); | |
14883 | ||
ed4a6a7c | 14884 | cs->wm.need_postvbl_update = true; |
ccf010fb | 14885 | dev_priv->display.optimize_watermarks(intel_state, cs); |
d93c0372 MR |
14886 | } |
14887 | ||
b9a1b717 | 14888 | put_state: |
0853695c | 14889 | drm_atomic_state_put(state); |
0cd1262d | 14890 | fail: |
d93c0372 MR |
14891 | drm_modeset_drop_locks(&ctx); |
14892 | drm_modeset_acquire_fini(&ctx); | |
14893 | } | |
14894 | ||
b079bd17 | 14895 | int intel_modeset_init(struct drm_device *dev) |
79e53945 | 14896 | { |
72e96d64 JL |
14897 | struct drm_i915_private *dev_priv = to_i915(dev); |
14898 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
8cc87b75 | 14899 | enum pipe pipe; |
46f297fb | 14900 | struct intel_crtc *crtc; |
79e53945 JB |
14901 | |
14902 | drm_mode_config_init(dev); | |
14903 | ||
14904 | dev->mode_config.min_width = 0; | |
14905 | dev->mode_config.min_height = 0; | |
14906 | ||
019d96cb DA |
14907 | dev->mode_config.preferred_depth = 24; |
14908 | dev->mode_config.prefer_shadow = 1; | |
14909 | ||
25bab385 TU |
14910 | dev->mode_config.allow_fb_modifiers = true; |
14911 | ||
e6ecefaa | 14912 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 14913 | |
eb955eee | 14914 | INIT_WORK(&dev_priv->atomic_helper.free_work, |
ba318c61 | 14915 | intel_atomic_helper_free_state_worker); |
eb955eee | 14916 | |
b690e96c JB |
14917 | intel_init_quirks(dev); |
14918 | ||
62d75df7 | 14919 | intel_init_pm(dev_priv); |
1fa61106 | 14920 | |
b7f05d4a | 14921 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
b079bd17 | 14922 | return 0; |
e3c74757 | 14923 | |
69f92f67 LW |
14924 | /* |
14925 | * There may be no VBT; and if the BIOS enabled SSC we can | |
14926 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
14927 | * BIOS isn't using it, don't assume it will work even if the VBT | |
14928 | * indicates as much. | |
14929 | */ | |
6e266956 | 14930 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { |
69f92f67 LW |
14931 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & |
14932 | DREF_SSC1_ENABLE); | |
14933 | ||
14934 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
14935 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
14936 | bios_lvds_use_ssc ? "en" : "dis", | |
14937 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
14938 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
14939 | } | |
14940 | } | |
14941 | ||
5db94019 | 14942 | if (IS_GEN2(dev_priv)) { |
a6c45cf0 CW |
14943 | dev->mode_config.max_width = 2048; |
14944 | dev->mode_config.max_height = 2048; | |
5db94019 | 14945 | } else if (IS_GEN3(dev_priv)) { |
5e4d6fa7 KP |
14946 | dev->mode_config.max_width = 4096; |
14947 | dev->mode_config.max_height = 4096; | |
79e53945 | 14948 | } else { |
a6c45cf0 CW |
14949 | dev->mode_config.max_width = 8192; |
14950 | dev->mode_config.max_height = 8192; | |
79e53945 | 14951 | } |
068be561 | 14952 | |
2a307c2e JN |
14953 | if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) { |
14954 | dev->mode_config.cursor_width = IS_I845G(dev_priv) ? 64 : 512; | |
dc41c154 | 14955 | dev->mode_config.cursor_height = 1023; |
5db94019 | 14956 | } else if (IS_GEN2(dev_priv)) { |
068be561 DL |
14957 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
14958 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
14959 | } else { | |
14960 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
14961 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
14962 | } | |
14963 | ||
72e96d64 | 14964 | dev->mode_config.fb_base = ggtt->mappable_base; |
79e53945 | 14965 | |
28c97730 | 14966 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
b7f05d4a TU |
14967 | INTEL_INFO(dev_priv)->num_pipes, |
14968 | INTEL_INFO(dev_priv)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 14969 | |
055e393f | 14970 | for_each_pipe(dev_priv, pipe) { |
b079bd17 VS |
14971 | int ret; |
14972 | ||
5ab0d85b | 14973 | ret = intel_crtc_init(dev_priv, pipe); |
b079bd17 VS |
14974 | if (ret) { |
14975 | drm_mode_config_cleanup(dev); | |
14976 | return ret; | |
14977 | } | |
79e53945 JB |
14978 | } |
14979 | ||
e72f9fbf | 14980 | intel_shared_dpll_init(dev); |
ee7b9f93 | 14981 | |
5be6e334 VS |
14982 | intel_update_czclk(dev_priv); |
14983 | intel_modeset_init_hw(dev); | |
14984 | ||
b2045352 | 14985 | if (dev_priv->max_cdclk_freq == 0) |
4c75b940 | 14986 | intel_update_max_cdclk(dev_priv); |
b2045352 | 14987 | |
9cce37f4 | 14988 | /* Just disable it once at startup */ |
29b74b7f | 14989 | i915_disable_vga(dev_priv); |
c39055b0 | 14990 | intel_setup_outputs(dev_priv); |
11be49eb | 14991 | |
6e9f798d | 14992 | drm_modeset_lock_all(dev); |
043e9bda | 14993 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 14994 | drm_modeset_unlock_all(dev); |
46f297fb | 14995 | |
d3fcc808 | 14996 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
14997 | struct intel_initial_plane_config plane_config = {}; |
14998 | ||
46f297fb JB |
14999 | if (!crtc->active) |
15000 | continue; | |
15001 | ||
46f297fb | 15002 | /* |
46f297fb JB |
15003 | * Note that reserving the BIOS fb up front prevents us |
15004 | * from stuffing other stolen allocations like the ring | |
15005 | * on top. This prevents some ugliness at boot time, and | |
15006 | * can even allow for smooth boot transitions if the BIOS | |
15007 | * fb is large enough for the active pipe configuration. | |
15008 | */ | |
eeebeac5 ML |
15009 | dev_priv->display.get_initial_plane_config(crtc, |
15010 | &plane_config); | |
15011 | ||
15012 | /* | |
15013 | * If the fb is shared between multiple heads, we'll | |
15014 | * just get the first one. | |
15015 | */ | |
15016 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 15017 | } |
d93c0372 MR |
15018 | |
15019 | /* | |
15020 | * Make sure hardware watermarks really match the state we read out. | |
15021 | * Note that we need to do this after reconstructing the BIOS fb's | |
15022 | * since the watermark calculation done here will use pstate->fb. | |
15023 | */ | |
602ae835 VS |
15024 | if (!HAS_GMCH_DISPLAY(dev_priv)) |
15025 | sanitize_watermarks(dev); | |
b079bd17 VS |
15026 | |
15027 | return 0; | |
2c7111db CW |
15028 | } |
15029 | ||
7fad798e DV |
15030 | static void intel_enable_pipe_a(struct drm_device *dev) |
15031 | { | |
15032 | struct intel_connector *connector; | |
15033 | struct drm_connector *crt = NULL; | |
15034 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 15035 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
15036 | |
15037 | /* We can't just switch on the pipe A, we need to set things up with a | |
15038 | * proper mode and output configuration. As a gross hack, enable pipe A | |
15039 | * by enabling the load detect pipe once. */ | |
3a3371ff | 15040 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
15041 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
15042 | crt = &connector->base; | |
15043 | break; | |
15044 | } | |
15045 | } | |
15046 | ||
15047 | if (!crt) | |
15048 | return; | |
15049 | ||
208bf9fd | 15050 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 15051 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
15052 | } |
15053 | ||
fa555837 DV |
15054 | static bool |
15055 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15056 | { | |
b7f05d4a | 15057 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
649636ef | 15058 | u32 val; |
fa555837 | 15059 | |
b7f05d4a | 15060 | if (INTEL_INFO(dev_priv)->num_pipes == 1) |
fa555837 DV |
15061 | return true; |
15062 | ||
649636ef | 15063 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
15064 | |
15065 | if ((val & DISPLAY_PLANE_ENABLE) && | |
15066 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
15067 | return false; | |
15068 | ||
15069 | return true; | |
15070 | } | |
15071 | ||
02e93c35 VS |
15072 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
15073 | { | |
15074 | struct drm_device *dev = crtc->base.dev; | |
15075 | struct intel_encoder *encoder; | |
15076 | ||
15077 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
15078 | return true; | |
15079 | ||
15080 | return false; | |
15081 | } | |
15082 | ||
496b0fc3 ML |
15083 | static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder) |
15084 | { | |
15085 | struct drm_device *dev = encoder->base.dev; | |
15086 | struct intel_connector *connector; | |
15087 | ||
15088 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
15089 | return connector; | |
15090 | ||
15091 | return NULL; | |
15092 | } | |
15093 | ||
a168f5b3 VS |
15094 | static bool has_pch_trancoder(struct drm_i915_private *dev_priv, |
15095 | enum transcoder pch_transcoder) | |
15096 | { | |
15097 | return HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv) || | |
15098 | (HAS_PCH_LPT_H(dev_priv) && pch_transcoder == TRANSCODER_A); | |
15099 | } | |
15100 | ||
24929352 DV |
15101 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15102 | { | |
15103 | struct drm_device *dev = crtc->base.dev; | |
fac5e23e | 15104 | struct drm_i915_private *dev_priv = to_i915(dev); |
4d1de975 | 15105 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
24929352 | 15106 | |
24929352 | 15107 | /* Clear any frame start delays used for debugging left by the BIOS */ |
4d1de975 JN |
15108 | if (!transcoder_is_dsi(cpu_transcoder)) { |
15109 | i915_reg_t reg = PIPECONF(cpu_transcoder); | |
15110 | ||
15111 | I915_WRITE(reg, | |
15112 | I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | |
15113 | } | |
24929352 | 15114 | |
d3eaf884 | 15115 | /* restore vblank interrupts to correct state */ |
9625604c | 15116 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 15117 | if (crtc->active) { |
f9cd7b88 VS |
15118 | struct intel_plane *plane; |
15119 | ||
9625604c | 15120 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
15121 | |
15122 | /* Disable everything but the primary plane */ | |
15123 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
15124 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
15125 | continue; | |
15126 | ||
72259536 | 15127 | trace_intel_disable_plane(&plane->base, crtc); |
f9cd7b88 VS |
15128 | plane->disable_plane(&plane->base, &crtc->base); |
15129 | } | |
9625604c | 15130 | } |
d3eaf884 | 15131 | |
24929352 | 15132 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
15133 | * disable the crtc (and hence change the state) if it is wrong. Note |
15134 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
6315b5d3 | 15135 | if (INTEL_GEN(dev_priv) < 4 && !intel_check_plane_mapping(crtc)) { |
24929352 DV |
15136 | bool plane; |
15137 | ||
78108b7c VS |
15138 | DRM_DEBUG_KMS("[CRTC:%d:%s] wrong plane connection detected!\n", |
15139 | crtc->base.base.id, crtc->base.name); | |
24929352 DV |
15140 | |
15141 | /* Pipe has the wrong plane attached and the plane is active. | |
15142 | * Temporarily change the plane mapping and disable everything | |
15143 | * ... */ | |
15144 | plane = crtc->plane; | |
1d4258db | 15145 | crtc->base.primary->state->visible = true; |
24929352 | 15146 | crtc->plane = !plane; |
b17d48e2 | 15147 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15148 | crtc->plane = plane; |
24929352 | 15149 | } |
24929352 | 15150 | |
7fad798e DV |
15151 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
15152 | crtc->pipe == PIPE_A && !crtc->active) { | |
15153 | /* BIOS forgot to enable pipe A, this mostly happens after | |
15154 | * resume. Force-enable the pipe to fix this, the update_dpms | |
15155 | * call below we restore the pipe to the right state, but leave | |
15156 | * the required bits on. */ | |
15157 | intel_enable_pipe_a(dev); | |
15158 | } | |
15159 | ||
24929352 DV |
15160 | /* Adjust the state of the output pipe according to whether we |
15161 | * have active connectors/encoders. */ | |
842e0307 | 15162 | if (crtc->active && !intel_crtc_has_encoders(crtc)) |
b17d48e2 | 15163 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15164 | |
49cff963 | 15165 | if (crtc->active || HAS_GMCH_DISPLAY(dev_priv)) { |
4cc31489 DV |
15166 | /* |
15167 | * We start out with underrun reporting disabled to avoid races. | |
15168 | * For correct bookkeeping mark this on active crtcs. | |
15169 | * | |
c5ab3bc0 DV |
15170 | * Also on gmch platforms we dont have any hardware bits to |
15171 | * disable the underrun reporting. Which means we need to start | |
15172 | * out with underrun reporting disabled also on inactive pipes, | |
15173 | * since otherwise we'll complain about the garbage we read when | |
15174 | * e.g. coming up after runtime pm. | |
15175 | * | |
4cc31489 DV |
15176 | * No protection against concurrent access is required - at |
15177 | * worst a fifo underrun happens which also sets this to false. | |
15178 | */ | |
15179 | crtc->cpu_fifo_underrun_disabled = true; | |
a168f5b3 VS |
15180 | /* |
15181 | * We track the PCH trancoder underrun reporting state | |
15182 | * within the crtc. With crtc for pipe A housing the underrun | |
15183 | * reporting state for PCH transcoder A, crtc for pipe B housing | |
15184 | * it for PCH transcoder B, etc. LPT-H has only PCH transcoder A, | |
15185 | * and marking underrun reporting as disabled for the non-existing | |
15186 | * PCH transcoders B and C would prevent enabling the south | |
15187 | * error interrupt (see cpt_can_enable_serr_int()). | |
15188 | */ | |
15189 | if (has_pch_trancoder(dev_priv, (enum transcoder)crtc->pipe)) | |
15190 | crtc->pch_fifo_underrun_disabled = true; | |
4cc31489 | 15191 | } |
24929352 DV |
15192 | } |
15193 | ||
15194 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15195 | { | |
15196 | struct intel_connector *connector; | |
24929352 DV |
15197 | |
15198 | /* We need to check both for a crtc link (meaning that the | |
15199 | * encoder is active and trying to read from a pipe) and the | |
15200 | * pipe itself being active. */ | |
15201 | bool has_active_crtc = encoder->base.crtc && | |
15202 | to_intel_crtc(encoder->base.crtc)->active; | |
15203 | ||
496b0fc3 ML |
15204 | connector = intel_encoder_find_connector(encoder); |
15205 | if (connector && !has_active_crtc) { | |
24929352 DV |
15206 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
15207 | encoder->base.base.id, | |
8e329a03 | 15208 | encoder->base.name); |
24929352 DV |
15209 | |
15210 | /* Connector is active, but has no active pipe. This is | |
15211 | * fallout from our resume register restoring. Disable | |
15212 | * the encoder manually again. */ | |
15213 | if (encoder->base.crtc) { | |
fd6bbda9 ML |
15214 | struct drm_crtc_state *crtc_state = encoder->base.crtc->state; |
15215 | ||
24929352 DV |
15216 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", |
15217 | encoder->base.base.id, | |
8e329a03 | 15218 | encoder->base.name); |
fd6bbda9 | 15219 | encoder->disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); |
a62d1497 | 15220 | if (encoder->post_disable) |
fd6bbda9 | 15221 | encoder->post_disable(encoder, to_intel_crtc_state(crtc_state), connector->base.state); |
24929352 | 15222 | } |
7f1950fb | 15223 | encoder->base.crtc = NULL; |
24929352 DV |
15224 | |
15225 | /* Inconsistent output/port/pipe state happens presumably due to | |
15226 | * a bug in one of the get_hw_state functions. Or someplace else | |
15227 | * in our code, like the register restore mess on resume. Clamp | |
15228 | * things to off as a safer default. */ | |
fd6bbda9 ML |
15229 | |
15230 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15231 | connector->base.encoder = NULL; | |
24929352 DV |
15232 | } |
15233 | /* Enabled encoders without active connectors will be fixed in | |
15234 | * the crtc fixup. */ | |
15235 | } | |
15236 | ||
29b74b7f | 15237 | void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv) |
0fde901f | 15238 | { |
920a14b2 | 15239 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev_priv); |
0fde901f | 15240 | |
04098753 ID |
15241 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15242 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
29b74b7f | 15243 | i915_disable_vga(dev_priv); |
04098753 ID |
15244 | } |
15245 | } | |
15246 | ||
29b74b7f | 15247 | void i915_redisable_vga(struct drm_i915_private *dev_priv) |
04098753 | 15248 | { |
8dc8a27c PZ |
15249 | /* This function can be called both from intel_modeset_setup_hw_state or |
15250 | * at a very early point in our resume sequence, where the power well | |
15251 | * structures are not yet restored. Since this function is at a very | |
15252 | * paranoid "someone might have enabled VGA while we were not looking" | |
15253 | * level, just check if the power well is enabled instead of trying to | |
15254 | * follow the "don't touch the power well if we don't need it" policy | |
15255 | * the rest of the driver uses. */ | |
6392f847 | 15256 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15257 | return; |
15258 | ||
29b74b7f | 15259 | i915_redisable_vga_power_on(dev_priv); |
6392f847 ID |
15260 | |
15261 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
0fde901f KM |
15262 | } |
15263 | ||
f9cd7b88 | 15264 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 15265 | { |
f9cd7b88 | 15266 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 15267 | |
f9cd7b88 | 15268 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
15269 | } |
15270 | ||
f9cd7b88 VS |
15271 | /* FIXME read out full plane state for all planes */ |
15272 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 15273 | { |
e9728bd8 VS |
15274 | struct intel_plane *primary = to_intel_plane(crtc->base.primary); |
15275 | bool visible; | |
d032ffa0 | 15276 | |
e9728bd8 | 15277 | visible = crtc->active && primary_get_hw_state(primary); |
b26d3ea3 | 15278 | |
e9728bd8 VS |
15279 | intel_set_plane_visible(to_intel_crtc_state(crtc->base.state), |
15280 | to_intel_plane_state(primary->base.state), | |
15281 | visible); | |
98ec7739 VS |
15282 | } |
15283 | ||
30e984df | 15284 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 | 15285 | { |
fac5e23e | 15286 | struct drm_i915_private *dev_priv = to_i915(dev); |
24929352 | 15287 | enum pipe pipe; |
24929352 DV |
15288 | struct intel_crtc *crtc; |
15289 | struct intel_encoder *encoder; | |
15290 | struct intel_connector *connector; | |
5358901f | 15291 | int i; |
24929352 | 15292 | |
565602d7 ML |
15293 | dev_priv->active_crtcs = 0; |
15294 | ||
d3fcc808 | 15295 | for_each_intel_crtc(dev, crtc) { |
a8cd6da0 VS |
15296 | struct intel_crtc_state *crtc_state = |
15297 | to_intel_crtc_state(crtc->base.state); | |
3b117c8f | 15298 | |
ec2dc6a0 | 15299 | __drm_atomic_helper_crtc_destroy_state(&crtc_state->base); |
565602d7 ML |
15300 | memset(crtc_state, 0, sizeof(*crtc_state)); |
15301 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 15302 | |
565602d7 ML |
15303 | crtc_state->base.active = crtc_state->base.enable = |
15304 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
15305 | ||
15306 | crtc->base.enabled = crtc_state->base.enable; | |
15307 | crtc->active = crtc_state->base.active; | |
15308 | ||
aca1ebf4 | 15309 | if (crtc_state->base.active) |
565602d7 ML |
15310 | dev_priv->active_crtcs |= 1 << crtc->pipe; |
15311 | ||
f9cd7b88 | 15312 | readout_plane_state(crtc); |
24929352 | 15313 | |
78108b7c VS |
15314 | DRM_DEBUG_KMS("[CRTC:%d:%s] hw state readout: %s\n", |
15315 | crtc->base.base.id, crtc->base.name, | |
a8cd6da0 | 15316 | enableddisabled(crtc_state->base.active)); |
24929352 DV |
15317 | } |
15318 | ||
5358901f DV |
15319 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15320 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15321 | ||
2edd6443 | 15322 | pll->on = pll->funcs.get_hw_state(dev_priv, pll, |
2c42e535 ACO |
15323 | &pll->state.hw_state); |
15324 | pll->state.crtc_mask = 0; | |
d3fcc808 | 15325 | for_each_intel_crtc(dev, crtc) { |
a8cd6da0 VS |
15326 | struct intel_crtc_state *crtc_state = |
15327 | to_intel_crtc_state(crtc->base.state); | |
15328 | ||
15329 | if (crtc_state->base.active && | |
15330 | crtc_state->shared_dpll == pll) | |
2c42e535 | 15331 | pll->state.crtc_mask |= 1 << crtc->pipe; |
5358901f | 15332 | } |
2c42e535 | 15333 | pll->active_mask = pll->state.crtc_mask; |
5358901f | 15334 | |
1e6f2ddc | 15335 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
2c42e535 | 15336 | pll->name, pll->state.crtc_mask, pll->on); |
5358901f DV |
15337 | } |
15338 | ||
b2784e15 | 15339 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15340 | pipe = 0; |
15341 | ||
15342 | if (encoder->get_hw_state(encoder, &pipe)) { | |
a8cd6da0 VS |
15343 | struct intel_crtc_state *crtc_state; |
15344 | ||
98187836 | 15345 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
a8cd6da0 | 15346 | crtc_state = to_intel_crtc_state(crtc->base.state); |
e2af48c6 | 15347 | |
045ac3b5 | 15348 | encoder->base.crtc = &crtc->base; |
a8cd6da0 VS |
15349 | crtc_state->output_types |= 1 << encoder->type; |
15350 | encoder->get_config(encoder, crtc_state); | |
24929352 DV |
15351 | } else { |
15352 | encoder->base.crtc = NULL; | |
15353 | } | |
15354 | ||
6f2bcceb | 15355 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
08c4d7fc TU |
15356 | encoder->base.base.id, encoder->base.name, |
15357 | enableddisabled(encoder->base.crtc), | |
6f2bcceb | 15358 | pipe_name(pipe)); |
24929352 DV |
15359 | } |
15360 | ||
3a3371ff | 15361 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15362 | if (connector->get_hw_state(connector)) { |
15363 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
15364 | |
15365 | encoder = connector->encoder; | |
15366 | connector->base.encoder = &encoder->base; | |
15367 | ||
15368 | if (encoder->base.crtc && | |
15369 | encoder->base.crtc->state->active) { | |
15370 | /* | |
15371 | * This has to be done during hardware readout | |
15372 | * because anything calling .crtc_disable may | |
15373 | * rely on the connector_mask being accurate. | |
15374 | */ | |
15375 | encoder->base.crtc->state->connector_mask |= | |
15376 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
15377 | encoder->base.crtc->state->encoder_mask |= |
15378 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
15379 | } |
15380 | ||
24929352 DV |
15381 | } else { |
15382 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15383 | connector->base.encoder = NULL; | |
15384 | } | |
15385 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
08c4d7fc TU |
15386 | connector->base.base.id, connector->base.name, |
15387 | enableddisabled(connector->base.encoder)); | |
24929352 | 15388 | } |
7f4c6284 VS |
15389 | |
15390 | for_each_intel_crtc(dev, crtc) { | |
a8cd6da0 VS |
15391 | struct intel_crtc_state *crtc_state = |
15392 | to_intel_crtc_state(crtc->base.state); | |
aca1ebf4 VS |
15393 | int pixclk = 0; |
15394 | ||
a8cd6da0 | 15395 | crtc->base.hwmode = crtc_state->base.adjusted_mode; |
7f4c6284 VS |
15396 | |
15397 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
a8cd6da0 VS |
15398 | if (crtc_state->base.active) { |
15399 | intel_mode_from_pipe_config(&crtc->base.mode, crtc_state); | |
15400 | intel_mode_from_pipe_config(&crtc_state->base.adjusted_mode, crtc_state); | |
7f4c6284 VS |
15401 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); |
15402 | ||
15403 | /* | |
15404 | * The initial mode needs to be set in order to keep | |
15405 | * the atomic core happy. It wants a valid mode if the | |
15406 | * crtc's enabled, so we do the above call. | |
15407 | * | |
7800fb69 DV |
15408 | * But we don't set all the derived state fully, hence |
15409 | * set a flag to indicate that a full recalculation is | |
15410 | * needed on the next commit. | |
7f4c6284 | 15411 | */ |
a8cd6da0 | 15412 | crtc_state->base.mode.private_flags = I915_MODE_FLAG_INHERITED; |
9eca6832 | 15413 | |
a7d1b3f4 VS |
15414 | intel_crtc_compute_pixel_rate(crtc_state); |
15415 | ||
15416 | if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv) || | |
15417 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
15418 | pixclk = crtc_state->pixel_rate; | |
aca1ebf4 VS |
15419 | else |
15420 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
15421 | ||
15422 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
a8cd6da0 | 15423 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
aca1ebf4 VS |
15424 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); |
15425 | ||
9eca6832 VS |
15426 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); |
15427 | update_scanline_offset(crtc); | |
7f4c6284 | 15428 | } |
e3b247da | 15429 | |
aca1ebf4 VS |
15430 | dev_priv->min_pixclk[crtc->pipe] = pixclk; |
15431 | ||
a8cd6da0 | 15432 | intel_pipe_config_sanity_check(dev_priv, crtc_state); |
7f4c6284 | 15433 | } |
30e984df DV |
15434 | } |
15435 | ||
62b69566 ACO |
15436 | static void |
15437 | get_encoder_power_domains(struct drm_i915_private *dev_priv) | |
15438 | { | |
15439 | struct intel_encoder *encoder; | |
15440 | ||
15441 | for_each_intel_encoder(&dev_priv->drm, encoder) { | |
15442 | u64 get_domains; | |
15443 | enum intel_display_power_domain domain; | |
15444 | ||
15445 | if (!encoder->get_power_domains) | |
15446 | continue; | |
15447 | ||
15448 | get_domains = encoder->get_power_domains(encoder); | |
15449 | for_each_power_domain(domain, get_domains) | |
15450 | intel_display_power_get(dev_priv, domain); | |
15451 | } | |
15452 | } | |
15453 | ||
043e9bda ML |
15454 | /* Scan out the current hw modeset state, |
15455 | * and sanitizes it to the current state | |
15456 | */ | |
15457 | static void | |
15458 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df | 15459 | { |
fac5e23e | 15460 | struct drm_i915_private *dev_priv = to_i915(dev); |
30e984df | 15461 | enum pipe pipe; |
30e984df DV |
15462 | struct intel_crtc *crtc; |
15463 | struct intel_encoder *encoder; | |
35c95375 | 15464 | int i; |
30e984df DV |
15465 | |
15466 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
15467 | |
15468 | /* HW state is read out, now we need to sanitize this mess. */ | |
62b69566 ACO |
15469 | get_encoder_power_domains(dev_priv); |
15470 | ||
b2784e15 | 15471 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15472 | intel_sanitize_encoder(encoder); |
15473 | } | |
15474 | ||
055e393f | 15475 | for_each_pipe(dev_priv, pipe) { |
98187836 | 15476 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
e2af48c6 | 15477 | |
24929352 | 15478 | intel_sanitize_crtc(crtc); |
6e3c9717 ACO |
15479 | intel_dump_pipe_config(crtc, crtc->config, |
15480 | "[setup_hw_state]"); | |
24929352 | 15481 | } |
9a935856 | 15482 | |
d29b2f9d ACO |
15483 | intel_modeset_update_connector_atomic_state(dev); |
15484 | ||
35c95375 DV |
15485 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15486 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15487 | ||
2dd66ebd | 15488 | if (!pll->on || pll->active_mask) |
35c95375 DV |
15489 | continue; |
15490 | ||
15491 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15492 | ||
2edd6443 | 15493 | pll->funcs.disable(dev_priv, pll); |
35c95375 DV |
15494 | pll->on = false; |
15495 | } | |
15496 | ||
602ae835 | 15497 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
6eb1a681 | 15498 | vlv_wm_get_hw_state(dev); |
602ae835 VS |
15499 | vlv_wm_sanitize(dev_priv); |
15500 | } else if (IS_GEN9(dev_priv)) { | |
3078999f | 15501 | skl_wm_get_hw_state(dev); |
602ae835 | 15502 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
243e6a44 | 15503 | ilk_wm_get_hw_state(dev); |
602ae835 | 15504 | } |
292b990e ML |
15505 | |
15506 | for_each_intel_crtc(dev, crtc) { | |
d8fc70b7 | 15507 | u64 put_domains; |
292b990e | 15508 | |
74bff5f9 | 15509 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
292b990e ML |
15510 | if (WARN_ON(put_domains)) |
15511 | modeset_put_power_domains(dev_priv, put_domains); | |
15512 | } | |
15513 | intel_display_set_init_power(dev_priv, false); | |
010cf73d | 15514 | |
8d8c386c ID |
15515 | intel_power_domains_verify_state(dev_priv); |
15516 | ||
010cf73d | 15517 | intel_fbc_init_pipe_state(dev_priv); |
043e9bda | 15518 | } |
7d0bc1ea | 15519 | |
043e9bda ML |
15520 | void intel_display_resume(struct drm_device *dev) |
15521 | { | |
e2c8b870 ML |
15522 | struct drm_i915_private *dev_priv = to_i915(dev); |
15523 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
15524 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 15525 | int ret; |
f30da187 | 15526 | |
e2c8b870 | 15527 | dev_priv->modeset_restore_state = NULL; |
73974893 ML |
15528 | if (state) |
15529 | state->acquire_ctx = &ctx; | |
043e9bda | 15530 | |
ea49c9ac ML |
15531 | /* |
15532 | * This is a cludge because with real atomic modeset mode_config.mutex | |
15533 | * won't be taken. Unfortunately some probed state like | |
15534 | * audio_codec_enable is still protected by mode_config.mutex, so lock | |
15535 | * it here for now. | |
15536 | */ | |
15537 | mutex_lock(&dev->mode_config.mutex); | |
e2c8b870 | 15538 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 15539 | |
73974893 ML |
15540 | while (1) { |
15541 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
15542 | if (ret != -EDEADLK) | |
15543 | break; | |
043e9bda | 15544 | |
e2c8b870 | 15545 | drm_modeset_backoff(&ctx); |
e2c8b870 | 15546 | } |
043e9bda | 15547 | |
73974893 | 15548 | if (!ret) |
581e49fe | 15549 | ret = __intel_display_resume(dev, state, &ctx); |
73974893 | 15550 | |
e2c8b870 ML |
15551 | drm_modeset_drop_locks(&ctx); |
15552 | drm_modeset_acquire_fini(&ctx); | |
ea49c9ac | 15553 | mutex_unlock(&dev->mode_config.mutex); |
043e9bda | 15554 | |
0853695c | 15555 | if (ret) |
e2c8b870 | 15556 | DRM_ERROR("Restoring old state failed with %i\n", ret); |
3c5e37f1 CW |
15557 | if (state) |
15558 | drm_atomic_state_put(state); | |
2c7111db CW |
15559 | } |
15560 | ||
15561 | void intel_modeset_gem_init(struct drm_device *dev) | |
15562 | { | |
dc97997a | 15563 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 15564 | |
dc97997a | 15565 | intel_init_gt_powersave(dev_priv); |
ae48434c | 15566 | |
1ee8da6d | 15567 | intel_setup_overlay(dev_priv); |
1ebaa0b9 CW |
15568 | } |
15569 | ||
15570 | int intel_connector_register(struct drm_connector *connector) | |
15571 | { | |
15572 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
15573 | int ret; | |
15574 | ||
15575 | ret = intel_backlight_device_register(intel_connector); | |
15576 | if (ret) | |
15577 | goto err; | |
15578 | ||
15579 | return 0; | |
0962c3c9 | 15580 | |
1ebaa0b9 CW |
15581 | err: |
15582 | return ret; | |
79e53945 JB |
15583 | } |
15584 | ||
c191eca1 | 15585 | void intel_connector_unregister(struct drm_connector *connector) |
4932e2c3 | 15586 | { |
e63d87c0 | 15587 | struct intel_connector *intel_connector = to_intel_connector(connector); |
4932e2c3 | 15588 | |
e63d87c0 | 15589 | intel_backlight_device_unregister(intel_connector); |
4932e2c3 | 15590 | intel_panel_destroy_backlight(connector); |
4932e2c3 ID |
15591 | } |
15592 | ||
79e53945 JB |
15593 | void intel_modeset_cleanup(struct drm_device *dev) |
15594 | { | |
fac5e23e | 15595 | struct drm_i915_private *dev_priv = to_i915(dev); |
652c393a | 15596 | |
eb955eee CW |
15597 | flush_work(&dev_priv->atomic_helper.free_work); |
15598 | WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list)); | |
15599 | ||
dc97997a | 15600 | intel_disable_gt_powersave(dev_priv); |
2eb5252e | 15601 | |
fd0c0642 DV |
15602 | /* |
15603 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 15604 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
15605 | * experience fancy races otherwise. |
15606 | */ | |
2aeb7d3a | 15607 | intel_irq_uninstall(dev_priv); |
eb21b92b | 15608 | |
fd0c0642 DV |
15609 | /* |
15610 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
15611 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
15612 | */ | |
f87ea761 | 15613 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 15614 | |
723bfd70 JB |
15615 | intel_unregister_dsm_handler(); |
15616 | ||
c937ab3e | 15617 | intel_fbc_global_disable(dev_priv); |
69341a5e | 15618 | |
1630fe75 CW |
15619 | /* flush any delayed tasks or pending work */ |
15620 | flush_scheduled_work(); | |
15621 | ||
79e53945 | 15622 | drm_mode_config_cleanup(dev); |
4d7bb011 | 15623 | |
1ee8da6d | 15624 | intel_cleanup_overlay(dev_priv); |
ae48434c | 15625 | |
dc97997a | 15626 | intel_cleanup_gt_powersave(dev_priv); |
f5949141 | 15627 | |
40196446 | 15628 | intel_teardown_gmbus(dev_priv); |
79e53945 JB |
15629 | } |
15630 | ||
df0e9248 CW |
15631 | void intel_connector_attach_encoder(struct intel_connector *connector, |
15632 | struct intel_encoder *encoder) | |
15633 | { | |
15634 | connector->encoder = encoder; | |
15635 | drm_mode_connector_attach_encoder(&connector->base, | |
15636 | &encoder->base); | |
79e53945 | 15637 | } |
28d52043 DA |
15638 | |
15639 | /* | |
15640 | * set vga decode state - true == enable VGA decode | |
15641 | */ | |
6315b5d3 | 15642 | int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, bool state) |
28d52043 | 15643 | { |
6315b5d3 | 15644 | unsigned reg = INTEL_GEN(dev_priv) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
15645 | u16 gmch_ctrl; |
15646 | ||
75fa041d CW |
15647 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
15648 | DRM_ERROR("failed to read control word\n"); | |
15649 | return -EIO; | |
15650 | } | |
15651 | ||
c0cc8a55 CW |
15652 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
15653 | return 0; | |
15654 | ||
28d52043 DA |
15655 | if (state) |
15656 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
15657 | else | |
15658 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
15659 | |
15660 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
15661 | DRM_ERROR("failed to write control word\n"); | |
15662 | return -EIO; | |
15663 | } | |
15664 | ||
28d52043 DA |
15665 | return 0; |
15666 | } | |
c4a1d9e4 | 15667 | |
98a2f411 CW |
15668 | #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) |
15669 | ||
c4a1d9e4 | 15670 | struct intel_display_error_state { |
ff57f1b0 PZ |
15671 | |
15672 | u32 power_well_driver; | |
15673 | ||
63b66e5b CW |
15674 | int num_transcoders; |
15675 | ||
c4a1d9e4 CW |
15676 | struct intel_cursor_error_state { |
15677 | u32 control; | |
15678 | u32 position; | |
15679 | u32 base; | |
15680 | u32 size; | |
52331309 | 15681 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15682 | |
15683 | struct intel_pipe_error_state { | |
ddf9c536 | 15684 | bool power_domain_on; |
c4a1d9e4 | 15685 | u32 source; |
f301b1e1 | 15686 | u32 stat; |
52331309 | 15687 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
15688 | |
15689 | struct intel_plane_error_state { | |
15690 | u32 control; | |
15691 | u32 stride; | |
15692 | u32 size; | |
15693 | u32 pos; | |
15694 | u32 addr; | |
15695 | u32 surface; | |
15696 | u32 tile_offset; | |
52331309 | 15697 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
15698 | |
15699 | struct intel_transcoder_error_state { | |
ddf9c536 | 15700 | bool power_domain_on; |
63b66e5b CW |
15701 | enum transcoder cpu_transcoder; |
15702 | ||
15703 | u32 conf; | |
15704 | ||
15705 | u32 htotal; | |
15706 | u32 hblank; | |
15707 | u32 hsync; | |
15708 | u32 vtotal; | |
15709 | u32 vblank; | |
15710 | u32 vsync; | |
15711 | } transcoder[4]; | |
c4a1d9e4 CW |
15712 | }; |
15713 | ||
15714 | struct intel_display_error_state * | |
c033666a | 15715 | intel_display_capture_error_state(struct drm_i915_private *dev_priv) |
c4a1d9e4 | 15716 | { |
c4a1d9e4 | 15717 | struct intel_display_error_state *error; |
63b66e5b CW |
15718 | int transcoders[] = { |
15719 | TRANSCODER_A, | |
15720 | TRANSCODER_B, | |
15721 | TRANSCODER_C, | |
15722 | TRANSCODER_EDP, | |
15723 | }; | |
c4a1d9e4 CW |
15724 | int i; |
15725 | ||
c033666a | 15726 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
63b66e5b CW |
15727 | return NULL; |
15728 | ||
9d1cb914 | 15729 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
15730 | if (error == NULL) |
15731 | return NULL; | |
15732 | ||
c033666a | 15733 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ff57f1b0 PZ |
15734 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
15735 | ||
055e393f | 15736 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 15737 | error->pipe[i].power_domain_on = |
f458ebbc DV |
15738 | __intel_display_power_is_enabled(dev_priv, |
15739 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 15740 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
15741 | continue; |
15742 | ||
5efb3e28 VS |
15743 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
15744 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
15745 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
15746 | |
15747 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
15748 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
c033666a | 15749 | if (INTEL_GEN(dev_priv) <= 3) { |
51889b35 | 15750 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
15751 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
15752 | } | |
c033666a | 15753 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
ca291363 | 15754 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
c033666a | 15755 | if (INTEL_GEN(dev_priv) >= 4) { |
c4a1d9e4 CW |
15756 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
15757 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
15758 | } | |
15759 | ||
c4a1d9e4 | 15760 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 15761 | |
c033666a | 15762 | if (HAS_GMCH_DISPLAY(dev_priv)) |
f301b1e1 | 15763 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
15764 | } |
15765 | ||
4d1de975 | 15766 | /* Note: this does not include DSI transcoders. */ |
c033666a | 15767 | error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes; |
2d1fe073 | 15768 | if (HAS_DDI(dev_priv)) |
63b66e5b CW |
15769 | error->num_transcoders++; /* Account for eDP. */ |
15770 | ||
15771 | for (i = 0; i < error->num_transcoders; i++) { | |
15772 | enum transcoder cpu_transcoder = transcoders[i]; | |
15773 | ||
ddf9c536 | 15774 | error->transcoder[i].power_domain_on = |
f458ebbc | 15775 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 15776 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 15777 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
15778 | continue; |
15779 | ||
63b66e5b CW |
15780 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
15781 | ||
15782 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
15783 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
15784 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
15785 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
15786 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
15787 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
15788 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
15789 | } |
15790 | ||
15791 | return error; | |
15792 | } | |
15793 | ||
edc3d884 MK |
15794 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
15795 | ||
c4a1d9e4 | 15796 | void |
edc3d884 | 15797 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
15798 | struct intel_display_error_state *error) |
15799 | { | |
5a4c6f1b | 15800 | struct drm_i915_private *dev_priv = m->i915; |
c4a1d9e4 CW |
15801 | int i; |
15802 | ||
63b66e5b CW |
15803 | if (!error) |
15804 | return; | |
15805 | ||
b7f05d4a | 15806 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev_priv)->num_pipes); |
8652744b | 15807 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
edc3d884 | 15808 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 15809 | error->power_well_driver); |
055e393f | 15810 | for_each_pipe(dev_priv, i) { |
edc3d884 | 15811 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 15812 | err_printf(m, " Power: %s\n", |
87ad3212 | 15813 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 15814 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 15815 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
15816 | |
15817 | err_printf(m, "Plane [%d]:\n", i); | |
15818 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
15819 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
5f56d5f9 | 15820 | if (INTEL_GEN(dev_priv) <= 3) { |
edc3d884 MK |
15821 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
15822 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 15823 | } |
772c2a51 | 15824 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
edc3d884 | 15825 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
5f56d5f9 | 15826 | if (INTEL_GEN(dev_priv) >= 4) { |
edc3d884 MK |
15827 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
15828 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
15829 | } |
15830 | ||
edc3d884 MK |
15831 | err_printf(m, "Cursor [%d]:\n", i); |
15832 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
15833 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
15834 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 15835 | } |
63b66e5b CW |
15836 | |
15837 | for (i = 0; i < error->num_transcoders; i++) { | |
da205630 | 15838 | err_printf(m, "CPU transcoder: %s\n", |
63b66e5b | 15839 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 15840 | err_printf(m, " Power: %s\n", |
87ad3212 | 15841 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
15842 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
15843 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
15844 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
15845 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
15846 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
15847 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
15848 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
15849 | } | |
c4a1d9e4 | 15850 | } |
98a2f411 CW |
15851 | |
15852 | #endif |