]>
Commit | Line | Data |
---|---|---|
79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
db18b6a6 | 39 | #include "intel_dsi.h" |
e5510fac | 40 | #include "i915_trace.h" |
319c1d42 | 41 | #include <drm/drm_atomic.h> |
c196e1d6 | 42 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
43 | #include <drm/drm_dp_helper.h> |
44 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
45 | #include <drm/drm_plane_helper.h> |
46 | #include <drm/drm_rect.h> | |
c0f372b3 | 47 | #include <linux/dma_remapping.h> |
fd8e058a AG |
48 | #include <linux/reservation.h> |
49 | #include <linux/dma-buf.h> | |
79e53945 | 50 | |
465c120c | 51 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 52 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
53 | DRM_FORMAT_C8, |
54 | DRM_FORMAT_RGB565, | |
465c120c | 55 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 56 | DRM_FORMAT_XRGB8888, |
465c120c MR |
57 | }; |
58 | ||
59 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 60 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
61 | DRM_FORMAT_C8, |
62 | DRM_FORMAT_RGB565, | |
63 | DRM_FORMAT_XRGB8888, | |
64 | DRM_FORMAT_XBGR8888, | |
65 | DRM_FORMAT_XRGB2101010, | |
66 | DRM_FORMAT_XBGR2101010, | |
67 | }; | |
68 | ||
69 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
70 | DRM_FORMAT_C8, |
71 | DRM_FORMAT_RGB565, | |
72 | DRM_FORMAT_XRGB8888, | |
465c120c | 73 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 74 | DRM_FORMAT_ARGB8888, |
465c120c MR |
75 | DRM_FORMAT_ABGR8888, |
76 | DRM_FORMAT_XRGB2101010, | |
465c120c | 77 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
78 | DRM_FORMAT_YUYV, |
79 | DRM_FORMAT_YVYU, | |
80 | DRM_FORMAT_UYVY, | |
81 | DRM_FORMAT_VYUY, | |
465c120c MR |
82 | }; |
83 | ||
3d7d6510 MR |
84 | /* Cursor formats */ |
85 | static const uint32_t intel_cursor_formats[] = { | |
86 | DRM_FORMAT_ARGB8888, | |
87 | }; | |
88 | ||
f1f644dc | 89 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 90 | struct intel_crtc_state *pipe_config); |
18442d08 | 91 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 92 | struct intel_crtc_state *pipe_config); |
f1f644dc | 93 | |
eb1bfe80 JB |
94 | static int intel_framebuffer_init(struct drm_device *dev, |
95 | struct intel_framebuffer *ifb, | |
96 | struct drm_mode_fb_cmd2 *mode_cmd, | |
97 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
98 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
99 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
bc58be60 | 100 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc); |
29407aab | 101 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
102 | struct intel_link_m_n *m_n, |
103 | struct intel_link_m_n *m2_n2); | |
29407aab | 104 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 | 105 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
391bf048 | 106 | static void haswell_set_pipemisc(struct drm_crtc *crtc); |
d288f65f | 107 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 108 | const struct intel_crtc_state *pipe_config); |
d288f65f | 109 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 110 | const struct intel_crtc_state *pipe_config); |
613d2b27 ML |
111 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
112 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
549e2bfb CK |
113 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
114 | struct intel_crtc_state *crtc_state); | |
bfd16b2a ML |
115 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
116 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
117 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 118 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
2622a081 | 119 | static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc); |
4e5ca60f | 120 | static int ilk_max_pixel_rate(struct drm_atomic_state *state); |
e7457a9a | 121 | |
d4906093 | 122 | struct intel_limit { |
4c5def93 ACO |
123 | struct { |
124 | int min, max; | |
125 | } dot, vco, n, m, m1, m2, p, p1; | |
126 | ||
127 | struct { | |
128 | int dot_limit; | |
129 | int p2_slow, p2_fast; | |
130 | } p2; | |
d4906093 | 131 | }; |
79e53945 | 132 | |
bfa7df01 VS |
133 | /* returns HPLL frequency in kHz */ |
134 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) | |
135 | { | |
136 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
137 | ||
138 | /* Obtain SKU information */ | |
139 | mutex_lock(&dev_priv->sb_lock); | |
140 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
141 | CCK_FUSE_HPLL_FREQ_MASK; | |
142 | mutex_unlock(&dev_priv->sb_lock); | |
143 | ||
144 | return vco_freq[hpll_freq] * 1000; | |
145 | } | |
146 | ||
c30fec65 VS |
147 | int vlv_get_cck_clock(struct drm_i915_private *dev_priv, |
148 | const char *name, u32 reg, int ref_freq) | |
bfa7df01 VS |
149 | { |
150 | u32 val; | |
151 | int divider; | |
152 | ||
bfa7df01 VS |
153 | mutex_lock(&dev_priv->sb_lock); |
154 | val = vlv_cck_read(dev_priv, reg); | |
155 | mutex_unlock(&dev_priv->sb_lock); | |
156 | ||
157 | divider = val & CCK_FREQUENCY_VALUES; | |
158 | ||
159 | WARN((val & CCK_FREQUENCY_STATUS) != | |
160 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
161 | "%s change in progress\n", name); | |
162 | ||
c30fec65 VS |
163 | return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1); |
164 | } | |
165 | ||
166 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
167 | const char *name, u32 reg) | |
168 | { | |
169 | if (dev_priv->hpll_freq == 0) | |
170 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
171 | ||
172 | return vlv_get_cck_clock(dev_priv, name, reg, | |
173 | dev_priv->hpll_freq); | |
bfa7df01 VS |
174 | } |
175 | ||
e7dc33f3 VS |
176 | static int |
177 | intel_pch_rawclk(struct drm_i915_private *dev_priv) | |
d2acd215 | 178 | { |
e7dc33f3 VS |
179 | return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000; |
180 | } | |
d2acd215 | 181 | |
e7dc33f3 VS |
182 | static int |
183 | intel_vlv_hrawclk(struct drm_i915_private *dev_priv) | |
184 | { | |
19ab4ed3 | 185 | /* RAWCLK_FREQ_VLV register updated from power well code */ |
35d38d1f VS |
186 | return vlv_get_cck_clock_hpll(dev_priv, "hrawclk", |
187 | CCK_DISPLAY_REF_CLOCK_CONTROL); | |
d2acd215 DV |
188 | } |
189 | ||
e7dc33f3 VS |
190 | static int |
191 | intel_g4x_hrawclk(struct drm_i915_private *dev_priv) | |
79e50a4f | 192 | { |
79e50a4f JN |
193 | uint32_t clkcfg; |
194 | ||
e7dc33f3 | 195 | /* hrawclock is 1/4 the FSB frequency */ |
79e50a4f JN |
196 | clkcfg = I915_READ(CLKCFG); |
197 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
198 | case CLKCFG_FSB_400: | |
e7dc33f3 | 199 | return 100000; |
79e50a4f | 200 | case CLKCFG_FSB_533: |
e7dc33f3 | 201 | return 133333; |
79e50a4f | 202 | case CLKCFG_FSB_667: |
e7dc33f3 | 203 | return 166667; |
79e50a4f | 204 | case CLKCFG_FSB_800: |
e7dc33f3 | 205 | return 200000; |
79e50a4f | 206 | case CLKCFG_FSB_1067: |
e7dc33f3 | 207 | return 266667; |
79e50a4f | 208 | case CLKCFG_FSB_1333: |
e7dc33f3 | 209 | return 333333; |
79e50a4f JN |
210 | /* these two are just a guess; one of them might be right */ |
211 | case CLKCFG_FSB_1600: | |
212 | case CLKCFG_FSB_1600_ALT: | |
e7dc33f3 | 213 | return 400000; |
79e50a4f | 214 | default: |
e7dc33f3 | 215 | return 133333; |
79e50a4f JN |
216 | } |
217 | } | |
218 | ||
19ab4ed3 | 219 | void intel_update_rawclk(struct drm_i915_private *dev_priv) |
e7dc33f3 VS |
220 | { |
221 | if (HAS_PCH_SPLIT(dev_priv)) | |
222 | dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv); | |
223 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
224 | dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv); | |
225 | else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv)) | |
226 | dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv); | |
227 | else | |
228 | return; /* no rawclk on other platforms, or no need to know it */ | |
229 | ||
230 | DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq); | |
231 | } | |
232 | ||
bfa7df01 VS |
233 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
234 | { | |
666a4537 | 235 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
236 | return; |
237 | ||
238 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
239 | CCK_CZ_CLOCK_CONTROL); | |
240 | ||
241 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
242 | } | |
243 | ||
021357ac | 244 | static inline u32 /* units of 100MHz */ |
21a727b3 VS |
245 | intel_fdi_link_freq(struct drm_i915_private *dev_priv, |
246 | const struct intel_crtc_state *pipe_config) | |
021357ac | 247 | { |
21a727b3 VS |
248 | if (HAS_DDI(dev_priv)) |
249 | return pipe_config->port_clock; /* SPLL */ | |
250 | else if (IS_GEN5(dev_priv)) | |
251 | return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; | |
e3b247da | 252 | else |
21a727b3 | 253 | return 270000; |
021357ac CW |
254 | } |
255 | ||
1b6f4958 | 256 | static const struct intel_limit intel_limits_i8xx_dac = { |
0206e353 | 257 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 258 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 259 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
260 | .m = { .min = 96, .max = 140 }, |
261 | .m1 = { .min = 18, .max = 26 }, | |
262 | .m2 = { .min = 6, .max = 16 }, | |
263 | .p = { .min = 4, .max = 128 }, | |
264 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
265 | .p2 = { .dot_limit = 165000, |
266 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
267 | }; |
268 | ||
1b6f4958 | 269 | static const struct intel_limit intel_limits_i8xx_dvo = { |
5d536e28 | 270 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 271 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 272 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
273 | .m = { .min = 96, .max = 140 }, |
274 | .m1 = { .min = 18, .max = 26 }, | |
275 | .m2 = { .min = 6, .max = 16 }, | |
276 | .p = { .min = 4, .max = 128 }, | |
277 | .p1 = { .min = 2, .max = 33 }, | |
278 | .p2 = { .dot_limit = 165000, | |
279 | .p2_slow = 4, .p2_fast = 4 }, | |
280 | }; | |
281 | ||
1b6f4958 | 282 | static const struct intel_limit intel_limits_i8xx_lvds = { |
0206e353 | 283 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 284 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 285 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
286 | .m = { .min = 96, .max = 140 }, |
287 | .m1 = { .min = 18, .max = 26 }, | |
288 | .m2 = { .min = 6, .max = 16 }, | |
289 | .p = { .min = 4, .max = 128 }, | |
290 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
291 | .p2 = { .dot_limit = 165000, |
292 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 293 | }; |
273e27ca | 294 | |
1b6f4958 | 295 | static const struct intel_limit intel_limits_i9xx_sdvo = { |
0206e353 AJ |
296 | .dot = { .min = 20000, .max = 400000 }, |
297 | .vco = { .min = 1400000, .max = 2800000 }, | |
298 | .n = { .min = 1, .max = 6 }, | |
299 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
300 | .m1 = { .min = 8, .max = 18 }, |
301 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
302 | .p = { .min = 5, .max = 80 }, |
303 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
304 | .p2 = { .dot_limit = 200000, |
305 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
306 | }; |
307 | ||
1b6f4958 | 308 | static const struct intel_limit intel_limits_i9xx_lvds = { |
0206e353 AJ |
309 | .dot = { .min = 20000, .max = 400000 }, |
310 | .vco = { .min = 1400000, .max = 2800000 }, | |
311 | .n = { .min = 1, .max = 6 }, | |
312 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
313 | .m1 = { .min = 8, .max = 18 }, |
314 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
315 | .p = { .min = 7, .max = 98 }, |
316 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
317 | .p2 = { .dot_limit = 112000, |
318 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
319 | }; |
320 | ||
273e27ca | 321 | |
1b6f4958 | 322 | static const struct intel_limit intel_limits_g4x_sdvo = { |
273e27ca EA |
323 | .dot = { .min = 25000, .max = 270000 }, |
324 | .vco = { .min = 1750000, .max = 3500000}, | |
325 | .n = { .min = 1, .max = 4 }, | |
326 | .m = { .min = 104, .max = 138 }, | |
327 | .m1 = { .min = 17, .max = 23 }, | |
328 | .m2 = { .min = 5, .max = 11 }, | |
329 | .p = { .min = 10, .max = 30 }, | |
330 | .p1 = { .min = 1, .max = 3}, | |
331 | .p2 = { .dot_limit = 270000, | |
332 | .p2_slow = 10, | |
333 | .p2_fast = 10 | |
044c7c41 | 334 | }, |
e4b36699 KP |
335 | }; |
336 | ||
1b6f4958 | 337 | static const struct intel_limit intel_limits_g4x_hdmi = { |
273e27ca EA |
338 | .dot = { .min = 22000, .max = 400000 }, |
339 | .vco = { .min = 1750000, .max = 3500000}, | |
340 | .n = { .min = 1, .max = 4 }, | |
341 | .m = { .min = 104, .max = 138 }, | |
342 | .m1 = { .min = 16, .max = 23 }, | |
343 | .m2 = { .min = 5, .max = 11 }, | |
344 | .p = { .min = 5, .max = 80 }, | |
345 | .p1 = { .min = 1, .max = 8}, | |
346 | .p2 = { .dot_limit = 165000, | |
347 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
348 | }; |
349 | ||
1b6f4958 | 350 | static const struct intel_limit intel_limits_g4x_single_channel_lvds = { |
273e27ca EA |
351 | .dot = { .min = 20000, .max = 115000 }, |
352 | .vco = { .min = 1750000, .max = 3500000 }, | |
353 | .n = { .min = 1, .max = 3 }, | |
354 | .m = { .min = 104, .max = 138 }, | |
355 | .m1 = { .min = 17, .max = 23 }, | |
356 | .m2 = { .min = 5, .max = 11 }, | |
357 | .p = { .min = 28, .max = 112 }, | |
358 | .p1 = { .min = 2, .max = 8 }, | |
359 | .p2 = { .dot_limit = 0, | |
360 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 361 | }, |
e4b36699 KP |
362 | }; |
363 | ||
1b6f4958 | 364 | static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { |
273e27ca EA |
365 | .dot = { .min = 80000, .max = 224000 }, |
366 | .vco = { .min = 1750000, .max = 3500000 }, | |
367 | .n = { .min = 1, .max = 3 }, | |
368 | .m = { .min = 104, .max = 138 }, | |
369 | .m1 = { .min = 17, .max = 23 }, | |
370 | .m2 = { .min = 5, .max = 11 }, | |
371 | .p = { .min = 14, .max = 42 }, | |
372 | .p1 = { .min = 2, .max = 6 }, | |
373 | .p2 = { .dot_limit = 0, | |
374 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 375 | }, |
e4b36699 KP |
376 | }; |
377 | ||
1b6f4958 | 378 | static const struct intel_limit intel_limits_pineview_sdvo = { |
0206e353 AJ |
379 | .dot = { .min = 20000, .max = 400000}, |
380 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 381 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
382 | .n = { .min = 3, .max = 6 }, |
383 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 384 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
385 | .m1 = { .min = 0, .max = 0 }, |
386 | .m2 = { .min = 0, .max = 254 }, | |
387 | .p = { .min = 5, .max = 80 }, | |
388 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
389 | .p2 = { .dot_limit = 200000, |
390 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
391 | }; |
392 | ||
1b6f4958 | 393 | static const struct intel_limit intel_limits_pineview_lvds = { |
0206e353 AJ |
394 | .dot = { .min = 20000, .max = 400000 }, |
395 | .vco = { .min = 1700000, .max = 3500000 }, | |
396 | .n = { .min = 3, .max = 6 }, | |
397 | .m = { .min = 2, .max = 256 }, | |
398 | .m1 = { .min = 0, .max = 0 }, | |
399 | .m2 = { .min = 0, .max = 254 }, | |
400 | .p = { .min = 7, .max = 112 }, | |
401 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
402 | .p2 = { .dot_limit = 112000, |
403 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
404 | }; |
405 | ||
273e27ca EA |
406 | /* Ironlake / Sandybridge |
407 | * | |
408 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
409 | * the range value for them is (actual_value - 2). | |
410 | */ | |
1b6f4958 | 411 | static const struct intel_limit intel_limits_ironlake_dac = { |
273e27ca EA |
412 | .dot = { .min = 25000, .max = 350000 }, |
413 | .vco = { .min = 1760000, .max = 3510000 }, | |
414 | .n = { .min = 1, .max = 5 }, | |
415 | .m = { .min = 79, .max = 127 }, | |
416 | .m1 = { .min = 12, .max = 22 }, | |
417 | .m2 = { .min = 5, .max = 9 }, | |
418 | .p = { .min = 5, .max = 80 }, | |
419 | .p1 = { .min = 1, .max = 8 }, | |
420 | .p2 = { .dot_limit = 225000, | |
421 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
422 | }; |
423 | ||
1b6f4958 | 424 | static const struct intel_limit intel_limits_ironlake_single_lvds = { |
273e27ca EA |
425 | .dot = { .min = 25000, .max = 350000 }, |
426 | .vco = { .min = 1760000, .max = 3510000 }, | |
427 | .n = { .min = 1, .max = 3 }, | |
428 | .m = { .min = 79, .max = 118 }, | |
429 | .m1 = { .min = 12, .max = 22 }, | |
430 | .m2 = { .min = 5, .max = 9 }, | |
431 | .p = { .min = 28, .max = 112 }, | |
432 | .p1 = { .min = 2, .max = 8 }, | |
433 | .p2 = { .dot_limit = 225000, | |
434 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
435 | }; |
436 | ||
1b6f4958 | 437 | static const struct intel_limit intel_limits_ironlake_dual_lvds = { |
273e27ca EA |
438 | .dot = { .min = 25000, .max = 350000 }, |
439 | .vco = { .min = 1760000, .max = 3510000 }, | |
440 | .n = { .min = 1, .max = 3 }, | |
441 | .m = { .min = 79, .max = 127 }, | |
442 | .m1 = { .min = 12, .max = 22 }, | |
443 | .m2 = { .min = 5, .max = 9 }, | |
444 | .p = { .min = 14, .max = 56 }, | |
445 | .p1 = { .min = 2, .max = 8 }, | |
446 | .p2 = { .dot_limit = 225000, | |
447 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
448 | }; |
449 | ||
273e27ca | 450 | /* LVDS 100mhz refclk limits. */ |
1b6f4958 | 451 | static const struct intel_limit intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
452 | .dot = { .min = 25000, .max = 350000 }, |
453 | .vco = { .min = 1760000, .max = 3510000 }, | |
454 | .n = { .min = 1, .max = 2 }, | |
455 | .m = { .min = 79, .max = 126 }, | |
456 | .m1 = { .min = 12, .max = 22 }, | |
457 | .m2 = { .min = 5, .max = 9 }, | |
458 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 459 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
460 | .p2 = { .dot_limit = 225000, |
461 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
462 | }; |
463 | ||
1b6f4958 | 464 | static const struct intel_limit intel_limits_ironlake_dual_lvds_100m = { |
273e27ca EA |
465 | .dot = { .min = 25000, .max = 350000 }, |
466 | .vco = { .min = 1760000, .max = 3510000 }, | |
467 | .n = { .min = 1, .max = 3 }, | |
468 | .m = { .min = 79, .max = 126 }, | |
469 | .m1 = { .min = 12, .max = 22 }, | |
470 | .m2 = { .min = 5, .max = 9 }, | |
471 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 472 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
473 | .p2 = { .dot_limit = 225000, |
474 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
475 | }; |
476 | ||
1b6f4958 | 477 | static const struct intel_limit intel_limits_vlv = { |
f01b7962 VS |
478 | /* |
479 | * These are the data rate limits (measured in fast clocks) | |
480 | * since those are the strictest limits we have. The fast | |
481 | * clock and actual rate limits are more relaxed, so checking | |
482 | * them would make no difference. | |
483 | */ | |
484 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 485 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 486 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
487 | .m1 = { .min = 2, .max = 3 }, |
488 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 489 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 490 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
491 | }; |
492 | ||
1b6f4958 | 493 | static const struct intel_limit intel_limits_chv = { |
ef9348c8 CML |
494 | /* |
495 | * These are the data rate limits (measured in fast clocks) | |
496 | * since those are the strictest limits we have. The fast | |
497 | * clock and actual rate limits are more relaxed, so checking | |
498 | * them would make no difference. | |
499 | */ | |
500 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 501 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
502 | .n = { .min = 1, .max = 1 }, |
503 | .m1 = { .min = 2, .max = 2 }, | |
504 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
505 | .p1 = { .min = 2, .max = 4 }, | |
506 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
507 | }; | |
508 | ||
1b6f4958 | 509 | static const struct intel_limit intel_limits_bxt = { |
5ab7b0b7 ID |
510 | /* FIXME: find real dot limits */ |
511 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 512 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
513 | .n = { .min = 1, .max = 1 }, |
514 | .m1 = { .min = 2, .max = 2 }, | |
515 | /* FIXME: find real m2 limits */ | |
516 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
517 | .p1 = { .min = 2, .max = 4 }, | |
518 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
519 | }; | |
520 | ||
cdba954e ACO |
521 | static bool |
522 | needs_modeset(struct drm_crtc_state *state) | |
523 | { | |
fc596660 | 524 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
525 | } |
526 | ||
e0638cdf PZ |
527 | /** |
528 | * Returns whether any output on the specified pipe is of the specified type | |
529 | */ | |
4093561b | 530 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 531 | { |
409ee761 | 532 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
533 | struct intel_encoder *encoder; |
534 | ||
409ee761 | 535 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
536 | if (encoder->type == type) |
537 | return true; | |
538 | ||
539 | return false; | |
540 | } | |
541 | ||
d0737e1d ACO |
542 | /** |
543 | * Returns whether any output on the specified pipe will have the specified | |
544 | * type after a staged modeset is complete, i.e., the same as | |
545 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
546 | * encoder->crtc. | |
547 | */ | |
a93e255f ACO |
548 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
549 | int type) | |
d0737e1d | 550 | { |
a93e255f | 551 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 552 | struct drm_connector *connector; |
a93e255f | 553 | struct drm_connector_state *connector_state; |
d0737e1d | 554 | struct intel_encoder *encoder; |
a93e255f ACO |
555 | int i, num_connectors = 0; |
556 | ||
da3ced29 | 557 | for_each_connector_in_state(state, connector, connector_state, i) { |
a93e255f ACO |
558 | if (connector_state->crtc != crtc_state->base.crtc) |
559 | continue; | |
560 | ||
561 | num_connectors++; | |
d0737e1d | 562 | |
a93e255f ACO |
563 | encoder = to_intel_encoder(connector_state->best_encoder); |
564 | if (encoder->type == type) | |
d0737e1d | 565 | return true; |
a93e255f ACO |
566 | } |
567 | ||
568 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
569 | |
570 | return false; | |
571 | } | |
572 | ||
dccbea3b ID |
573 | /* |
574 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
575 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
576 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
577 | * The helpers' return value is the rate of the clock that is fed to the | |
578 | * display engine's pipe which can be the above fast dot clock rate or a | |
579 | * divided-down version of it. | |
580 | */ | |
f2b115e6 | 581 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
9e2c8475 | 582 | static int pnv_calc_dpll_params(int refclk, struct dpll *clock) |
79e53945 | 583 | { |
2177832f SL |
584 | clock->m = clock->m2 + 2; |
585 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 586 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 587 | return 0; |
fb03ac01 VS |
588 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
589 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
590 | |
591 | return clock->dot; | |
2177832f SL |
592 | } |
593 | ||
7429e9d4 DV |
594 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
595 | { | |
596 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
597 | } | |
598 | ||
9e2c8475 | 599 | static int i9xx_calc_dpll_params(int refclk, struct dpll *clock) |
2177832f | 600 | { |
7429e9d4 | 601 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 602 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 603 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 604 | return 0; |
fb03ac01 VS |
605 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
606 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
607 | |
608 | return clock->dot; | |
79e53945 JB |
609 | } |
610 | ||
9e2c8475 | 611 | static int vlv_calc_dpll_params(int refclk, struct dpll *clock) |
589eca67 ID |
612 | { |
613 | clock->m = clock->m1 * clock->m2; | |
614 | clock->p = clock->p1 * clock->p2; | |
615 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 616 | return 0; |
589eca67 ID |
617 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
618 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
619 | |
620 | return clock->dot / 5; | |
589eca67 ID |
621 | } |
622 | ||
9e2c8475 | 623 | int chv_calc_dpll_params(int refclk, struct dpll *clock) |
ef9348c8 CML |
624 | { |
625 | clock->m = clock->m1 * clock->m2; | |
626 | clock->p = clock->p1 * clock->p2; | |
627 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 628 | return 0; |
ef9348c8 CML |
629 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
630 | clock->n << 22); | |
631 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
632 | |
633 | return clock->dot / 5; | |
ef9348c8 CML |
634 | } |
635 | ||
7c04d1d9 | 636 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
637 | /** |
638 | * Returns whether the given set of divisors are valid for a given refclk with | |
639 | * the given connectors. | |
640 | */ | |
641 | ||
1b894b59 | 642 | static bool intel_PLL_is_valid(struct drm_device *dev, |
1b6f4958 | 643 | const struct intel_limit *limit, |
9e2c8475 | 644 | const struct dpll *clock) |
79e53945 | 645 | { |
f01b7962 VS |
646 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
647 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 648 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 649 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 650 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 651 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 652 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 653 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 654 | |
666a4537 WB |
655 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && |
656 | !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) | |
f01b7962 VS |
657 | if (clock->m1 <= clock->m2) |
658 | INTELPllInvalid("m1 <= m2\n"); | |
659 | ||
666a4537 | 660 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
661 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
662 | INTELPllInvalid("p out of range\n"); | |
663 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
664 | INTELPllInvalid("m out of range\n"); | |
665 | } | |
666 | ||
79e53945 | 667 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 668 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
669 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
670 | * connector, etc., rather than just a single range. | |
671 | */ | |
672 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 673 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
674 | |
675 | return true; | |
676 | } | |
677 | ||
3b1429d9 | 678 | static int |
1b6f4958 | 679 | i9xx_select_p2_div(const struct intel_limit *limit, |
3b1429d9 VS |
680 | const struct intel_crtc_state *crtc_state, |
681 | int target) | |
79e53945 | 682 | { |
3b1429d9 | 683 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 684 | |
a93e255f | 685 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 686 | /* |
a210b028 DV |
687 | * For LVDS just rely on its current settings for dual-channel. |
688 | * We haven't figured out how to reliably set up different | |
689 | * single/dual channel state, if we even can. | |
79e53945 | 690 | */ |
1974cad0 | 691 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 692 | return limit->p2.p2_fast; |
79e53945 | 693 | else |
3b1429d9 | 694 | return limit->p2.p2_slow; |
79e53945 JB |
695 | } else { |
696 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 697 | return limit->p2.p2_slow; |
79e53945 | 698 | else |
3b1429d9 | 699 | return limit->p2.p2_fast; |
79e53945 | 700 | } |
3b1429d9 VS |
701 | } |
702 | ||
70e8aa21 ACO |
703 | /* |
704 | * Returns a set of divisors for the desired target clock with the given | |
705 | * refclk, or FALSE. The returned values represent the clock equation: | |
706 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
707 | * | |
708 | * Target and reference clocks are specified in kHz. | |
709 | * | |
710 | * If match_clock is provided, then best_clock P divider must match the P | |
711 | * divider from @match_clock used for LVDS downclocking. | |
712 | */ | |
3b1429d9 | 713 | static bool |
1b6f4958 | 714 | i9xx_find_best_dpll(const struct intel_limit *limit, |
3b1429d9 | 715 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
716 | int target, int refclk, struct dpll *match_clock, |
717 | struct dpll *best_clock) | |
3b1429d9 VS |
718 | { |
719 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
9e2c8475 | 720 | struct dpll clock; |
3b1429d9 | 721 | int err = target; |
79e53945 | 722 | |
0206e353 | 723 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 724 | |
3b1429d9 VS |
725 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
726 | ||
42158660 ZY |
727 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
728 | clock.m1++) { | |
729 | for (clock.m2 = limit->m2.min; | |
730 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 731 | if (clock.m2 >= clock.m1) |
42158660 ZY |
732 | break; |
733 | for (clock.n = limit->n.min; | |
734 | clock.n <= limit->n.max; clock.n++) { | |
735 | for (clock.p1 = limit->p1.min; | |
736 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
737 | int this_err; |
738 | ||
dccbea3b | 739 | i9xx_calc_dpll_params(refclk, &clock); |
ac58c3f0 DV |
740 | if (!intel_PLL_is_valid(dev, limit, |
741 | &clock)) | |
742 | continue; | |
743 | if (match_clock && | |
744 | clock.p != match_clock->p) | |
745 | continue; | |
746 | ||
747 | this_err = abs(clock.dot - target); | |
748 | if (this_err < err) { | |
749 | *best_clock = clock; | |
750 | err = this_err; | |
751 | } | |
752 | } | |
753 | } | |
754 | } | |
755 | } | |
756 | ||
757 | return (err != target); | |
758 | } | |
759 | ||
70e8aa21 ACO |
760 | /* |
761 | * Returns a set of divisors for the desired target clock with the given | |
762 | * refclk, or FALSE. The returned values represent the clock equation: | |
763 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
764 | * | |
765 | * Target and reference clocks are specified in kHz. | |
766 | * | |
767 | * If match_clock is provided, then best_clock P divider must match the P | |
768 | * divider from @match_clock used for LVDS downclocking. | |
769 | */ | |
ac58c3f0 | 770 | static bool |
1b6f4958 | 771 | pnv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 772 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
773 | int target, int refclk, struct dpll *match_clock, |
774 | struct dpll *best_clock) | |
79e53945 | 775 | { |
3b1429d9 | 776 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 777 | struct dpll clock; |
79e53945 JB |
778 | int err = target; |
779 | ||
0206e353 | 780 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 781 | |
3b1429d9 VS |
782 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
783 | ||
42158660 ZY |
784 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
785 | clock.m1++) { | |
786 | for (clock.m2 = limit->m2.min; | |
787 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
788 | for (clock.n = limit->n.min; |
789 | clock.n <= limit->n.max; clock.n++) { | |
790 | for (clock.p1 = limit->p1.min; | |
791 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
792 | int this_err; |
793 | ||
dccbea3b | 794 | pnv_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
795 | if (!intel_PLL_is_valid(dev, limit, |
796 | &clock)) | |
79e53945 | 797 | continue; |
cec2f356 SP |
798 | if (match_clock && |
799 | clock.p != match_clock->p) | |
800 | continue; | |
79e53945 JB |
801 | |
802 | this_err = abs(clock.dot - target); | |
803 | if (this_err < err) { | |
804 | *best_clock = clock; | |
805 | err = this_err; | |
806 | } | |
807 | } | |
808 | } | |
809 | } | |
810 | } | |
811 | ||
812 | return (err != target); | |
813 | } | |
814 | ||
997c030c ACO |
815 | /* |
816 | * Returns a set of divisors for the desired target clock with the given | |
817 | * refclk, or FALSE. The returned values represent the clock equation: | |
818 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
70e8aa21 ACO |
819 | * |
820 | * Target and reference clocks are specified in kHz. | |
821 | * | |
822 | * If match_clock is provided, then best_clock P divider must match the P | |
823 | * divider from @match_clock used for LVDS downclocking. | |
997c030c | 824 | */ |
d4906093 | 825 | static bool |
1b6f4958 | 826 | g4x_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 827 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
828 | int target, int refclk, struct dpll *match_clock, |
829 | struct dpll *best_clock) | |
d4906093 | 830 | { |
3b1429d9 | 831 | struct drm_device *dev = crtc_state->base.crtc->dev; |
9e2c8475 | 832 | struct dpll clock; |
d4906093 | 833 | int max_n; |
3b1429d9 | 834 | bool found = false; |
6ba770dc AJ |
835 | /* approximately equals target * 0.00585 */ |
836 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
837 | |
838 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
839 | |
840 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
841 | ||
d4906093 | 842 | max_n = limit->n.max; |
f77f13e2 | 843 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 844 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 845 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
846 | for (clock.m1 = limit->m1.max; |
847 | clock.m1 >= limit->m1.min; clock.m1--) { | |
848 | for (clock.m2 = limit->m2.max; | |
849 | clock.m2 >= limit->m2.min; clock.m2--) { | |
850 | for (clock.p1 = limit->p1.max; | |
851 | clock.p1 >= limit->p1.min; clock.p1--) { | |
852 | int this_err; | |
853 | ||
dccbea3b | 854 | i9xx_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
855 | if (!intel_PLL_is_valid(dev, limit, |
856 | &clock)) | |
d4906093 | 857 | continue; |
1b894b59 CW |
858 | |
859 | this_err = abs(clock.dot - target); | |
d4906093 ML |
860 | if (this_err < err_most) { |
861 | *best_clock = clock; | |
862 | err_most = this_err; | |
863 | max_n = clock.n; | |
864 | found = true; | |
865 | } | |
866 | } | |
867 | } | |
868 | } | |
869 | } | |
2c07245f ZW |
870 | return found; |
871 | } | |
872 | ||
d5dd62bd ID |
873 | /* |
874 | * Check if the calculated PLL configuration is more optimal compared to the | |
875 | * best configuration and error found so far. Return the calculated error. | |
876 | */ | |
877 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
9e2c8475 ACO |
878 | const struct dpll *calculated_clock, |
879 | const struct dpll *best_clock, | |
d5dd62bd ID |
880 | unsigned int best_error_ppm, |
881 | unsigned int *error_ppm) | |
882 | { | |
9ca3ba01 ID |
883 | /* |
884 | * For CHV ignore the error and consider only the P value. | |
885 | * Prefer a bigger P value based on HW requirements. | |
886 | */ | |
887 | if (IS_CHERRYVIEW(dev)) { | |
888 | *error_ppm = 0; | |
889 | ||
890 | return calculated_clock->p > best_clock->p; | |
891 | } | |
892 | ||
24be4e46 ID |
893 | if (WARN_ON_ONCE(!target_freq)) |
894 | return false; | |
895 | ||
d5dd62bd ID |
896 | *error_ppm = div_u64(1000000ULL * |
897 | abs(target_freq - calculated_clock->dot), | |
898 | target_freq); | |
899 | /* | |
900 | * Prefer a better P value over a better (smaller) error if the error | |
901 | * is small. Ensure this preference for future configurations too by | |
902 | * setting the error to 0. | |
903 | */ | |
904 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
905 | *error_ppm = 0; | |
906 | ||
907 | return true; | |
908 | } | |
909 | ||
910 | return *error_ppm + 10 < best_error_ppm; | |
911 | } | |
912 | ||
65b3d6a9 ACO |
913 | /* |
914 | * Returns a set of divisors for the desired target clock with the given | |
915 | * refclk, or FALSE. The returned values represent the clock equation: | |
916 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
917 | */ | |
a0c4da24 | 918 | static bool |
1b6f4958 | 919 | vlv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 920 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
921 | int target, int refclk, struct dpll *match_clock, |
922 | struct dpll *best_clock) | |
a0c4da24 | 923 | { |
a93e255f | 924 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 925 | struct drm_device *dev = crtc->base.dev; |
9e2c8475 | 926 | struct dpll clock; |
69e4f900 | 927 | unsigned int bestppm = 1000000; |
27e639bf VS |
928 | /* min update 19.2 MHz */ |
929 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 930 | bool found = false; |
a0c4da24 | 931 | |
6b4bf1c4 VS |
932 | target *= 5; /* fast clock */ |
933 | ||
934 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
935 | |
936 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 937 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 938 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 939 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 940 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 941 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 942 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 943 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 944 | unsigned int ppm; |
69e4f900 | 945 | |
6b4bf1c4 VS |
946 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
947 | refclk * clock.m1); | |
948 | ||
dccbea3b | 949 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 950 | |
f01b7962 VS |
951 | if (!intel_PLL_is_valid(dev, limit, |
952 | &clock)) | |
43b0ac53 VS |
953 | continue; |
954 | ||
d5dd62bd ID |
955 | if (!vlv_PLL_is_optimal(dev, target, |
956 | &clock, | |
957 | best_clock, | |
958 | bestppm, &ppm)) | |
959 | continue; | |
6b4bf1c4 | 960 | |
d5dd62bd ID |
961 | *best_clock = clock; |
962 | bestppm = ppm; | |
963 | found = true; | |
a0c4da24 JB |
964 | } |
965 | } | |
966 | } | |
967 | } | |
a0c4da24 | 968 | |
49e497ef | 969 | return found; |
a0c4da24 | 970 | } |
a4fc5ed6 | 971 | |
65b3d6a9 ACO |
972 | /* |
973 | * Returns a set of divisors for the desired target clock with the given | |
974 | * refclk, or FALSE. The returned values represent the clock equation: | |
975 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
976 | */ | |
ef9348c8 | 977 | static bool |
1b6f4958 | 978 | chv_find_best_dpll(const struct intel_limit *limit, |
a93e255f | 979 | struct intel_crtc_state *crtc_state, |
9e2c8475 ACO |
980 | int target, int refclk, struct dpll *match_clock, |
981 | struct dpll *best_clock) | |
ef9348c8 | 982 | { |
a93e255f | 983 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 984 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 985 | unsigned int best_error_ppm; |
9e2c8475 | 986 | struct dpll clock; |
ef9348c8 CML |
987 | uint64_t m2; |
988 | int found = false; | |
989 | ||
990 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 991 | best_error_ppm = 1000000; |
ef9348c8 CML |
992 | |
993 | /* | |
994 | * Based on hardware doc, the n always set to 1, and m1 always | |
995 | * set to 2. If requires to support 200Mhz refclk, we need to | |
996 | * revisit this because n may not 1 anymore. | |
997 | */ | |
998 | clock.n = 1, clock.m1 = 2; | |
999 | target *= 5; /* fast clock */ | |
1000 | ||
1001 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
1002 | for (clock.p2 = limit->p2.p2_fast; | |
1003 | clock.p2 >= limit->p2.p2_slow; | |
1004 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 1005 | unsigned int error_ppm; |
ef9348c8 CML |
1006 | |
1007 | clock.p = clock.p1 * clock.p2; | |
1008 | ||
1009 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
1010 | clock.n) << 22, refclk * clock.m1); | |
1011 | ||
1012 | if (m2 > INT_MAX/clock.m1) | |
1013 | continue; | |
1014 | ||
1015 | clock.m2 = m2; | |
1016 | ||
dccbea3b | 1017 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 CML |
1018 | |
1019 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
1020 | continue; | |
1021 | ||
9ca3ba01 ID |
1022 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
1023 | best_error_ppm, &error_ppm)) | |
1024 | continue; | |
1025 | ||
1026 | *best_clock = clock; | |
1027 | best_error_ppm = error_ppm; | |
1028 | found = true; | |
ef9348c8 CML |
1029 | } |
1030 | } | |
1031 | ||
1032 | return found; | |
1033 | } | |
1034 | ||
5ab7b0b7 | 1035 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
9e2c8475 | 1036 | struct dpll *best_clock) |
5ab7b0b7 | 1037 | { |
65b3d6a9 | 1038 | int refclk = 100000; |
1b6f4958 | 1039 | const struct intel_limit *limit = &intel_limits_bxt; |
5ab7b0b7 | 1040 | |
65b3d6a9 | 1041 | return chv_find_best_dpll(limit, crtc_state, |
5ab7b0b7 ID |
1042 | target_clock, refclk, NULL, best_clock); |
1043 | } | |
1044 | ||
20ddf665 VS |
1045 | bool intel_crtc_active(struct drm_crtc *crtc) |
1046 | { | |
1047 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1048 | ||
1049 | /* Be paranoid as we can arrive here with only partial | |
1050 | * state retrieved from the hardware during setup. | |
1051 | * | |
241bfc38 | 1052 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1053 | * as Haswell has gained clock readout/fastboot support. |
1054 | * | |
66e514c1 | 1055 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1056 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1057 | * |
1058 | * FIXME: The intel_crtc->active here should be switched to | |
1059 | * crtc->state->active once we have proper CRTC states wired up | |
1060 | * for atomic. | |
20ddf665 | 1061 | */ |
c3d1f436 | 1062 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1063 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1064 | } |
1065 | ||
a5c961d1 PZ |
1066 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1067 | enum pipe pipe) | |
1068 | { | |
1069 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1070 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1071 | ||
6e3c9717 | 1072 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1073 | } |
1074 | ||
fbf49ea2 VS |
1075 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1076 | { | |
1077 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1078 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1079 | u32 line1, line2; |
1080 | u32 line_mask; | |
1081 | ||
1082 | if (IS_GEN2(dev)) | |
1083 | line_mask = DSL_LINEMASK_GEN2; | |
1084 | else | |
1085 | line_mask = DSL_LINEMASK_GEN3; | |
1086 | ||
1087 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1088 | msleep(5); |
fbf49ea2 VS |
1089 | line2 = I915_READ(reg) & line_mask; |
1090 | ||
1091 | return line1 == line2; | |
1092 | } | |
1093 | ||
ab7ad7f6 KP |
1094 | /* |
1095 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1096 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1097 | * |
1098 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1099 | * spinning on the vblank interrupt status bit, since we won't actually | |
1100 | * see an interrupt when the pipe is disabled. | |
1101 | * | |
ab7ad7f6 KP |
1102 | * On Gen4 and above: |
1103 | * wait for the pipe register state bit to turn off | |
1104 | * | |
1105 | * Otherwise: | |
1106 | * wait for the display line value to settle (it usually | |
1107 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1108 | * |
9d0498a2 | 1109 | */ |
575f7ab7 | 1110 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1111 | { |
575f7ab7 | 1112 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1113 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1114 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1115 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1116 | |
1117 | if (INTEL_INFO(dev)->gen >= 4) { | |
f0f59a00 | 1118 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1119 | |
1120 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1121 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1122 | 100)) | |
284637d9 | 1123 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1124 | } else { |
ab7ad7f6 | 1125 | /* Wait for the display line to settle */ |
fbf49ea2 | 1126 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1127 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1128 | } |
79e53945 JB |
1129 | } |
1130 | ||
b24e7179 | 1131 | /* Only for pre-ILK configs */ |
55607e8a DV |
1132 | void assert_pll(struct drm_i915_private *dev_priv, |
1133 | enum pipe pipe, bool state) | |
b24e7179 | 1134 | { |
b24e7179 JB |
1135 | u32 val; |
1136 | bool cur_state; | |
1137 | ||
649636ef | 1138 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1139 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1140 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1141 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1142 | onoff(state), onoff(cur_state)); |
b24e7179 | 1143 | } |
b24e7179 | 1144 | |
23538ef1 | 1145 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
8563b1e8 | 1146 | void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) |
23538ef1 JN |
1147 | { |
1148 | u32 val; | |
1149 | bool cur_state; | |
1150 | ||
a580516d | 1151 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1152 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1153 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1154 | |
1155 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1156 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1157 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1158 | onoff(state), onoff(cur_state)); |
23538ef1 | 1159 | } |
23538ef1 | 1160 | |
040484af JB |
1161 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, |
1162 | enum pipe pipe, bool state) | |
1163 | { | |
040484af | 1164 | bool cur_state; |
ad80a810 PZ |
1165 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1166 | pipe); | |
040484af | 1167 | |
2d1fe073 | 1168 | if (HAS_DDI(dev_priv)) { |
affa9354 | 1169 | /* DDI does not have a specific FDI_TX register */ |
649636ef | 1170 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1171 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1172 | } else { |
649636ef | 1173 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1174 | cur_state = !!(val & FDI_TX_ENABLE); |
1175 | } | |
e2c719b7 | 1176 | I915_STATE_WARN(cur_state != state, |
040484af | 1177 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1178 | onoff(state), onoff(cur_state)); |
040484af JB |
1179 | } |
1180 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1181 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1182 | ||
1183 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1184 | enum pipe pipe, bool state) | |
1185 | { | |
040484af JB |
1186 | u32 val; |
1187 | bool cur_state; | |
1188 | ||
649636ef | 1189 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1190 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1191 | I915_STATE_WARN(cur_state != state, |
040484af | 1192 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1193 | onoff(state), onoff(cur_state)); |
040484af JB |
1194 | } |
1195 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1196 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1197 | ||
1198 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1199 | enum pipe pipe) | |
1200 | { | |
040484af JB |
1201 | u32 val; |
1202 | ||
1203 | /* ILK FDI PLL is always enabled */ | |
7e22dbbb | 1204 | if (IS_GEN5(dev_priv)) |
040484af JB |
1205 | return; |
1206 | ||
bf507ef7 | 1207 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
2d1fe073 | 1208 | if (HAS_DDI(dev_priv)) |
bf507ef7 ED |
1209 | return; |
1210 | ||
649636ef | 1211 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1212 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1213 | } |
1214 | ||
55607e8a DV |
1215 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1216 | enum pipe pipe, bool state) | |
040484af | 1217 | { |
040484af | 1218 | u32 val; |
55607e8a | 1219 | bool cur_state; |
040484af | 1220 | |
649636ef | 1221 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1222 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1223 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1224 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1225 | onoff(state), onoff(cur_state)); |
040484af JB |
1226 | } |
1227 | ||
b680c37a DV |
1228 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1229 | enum pipe pipe) | |
ea0760cf | 1230 | { |
bedd4dba | 1231 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 | 1232 | i915_reg_t pp_reg; |
ea0760cf JB |
1233 | u32 val; |
1234 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1235 | bool locked = true; |
ea0760cf | 1236 | |
bedd4dba JN |
1237 | if (WARN_ON(HAS_DDI(dev))) |
1238 | return; | |
1239 | ||
1240 | if (HAS_PCH_SPLIT(dev)) { | |
1241 | u32 port_sel; | |
1242 | ||
ea0760cf | 1243 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1244 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1245 | ||
1246 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1247 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1248 | panel_pipe = PIPE_B; | |
1249 | /* XXX: else fix for eDP */ | |
666a4537 | 1250 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
bedd4dba JN |
1251 | /* presumably write lock depends on pipe, not port select */ |
1252 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1253 | panel_pipe = pipe; | |
ea0760cf JB |
1254 | } else { |
1255 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1256 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1257 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1258 | } |
1259 | ||
1260 | val = I915_READ(pp_reg); | |
1261 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1262 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1263 | locked = false; |
1264 | ||
e2c719b7 | 1265 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1266 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1267 | pipe_name(pipe)); |
ea0760cf JB |
1268 | } |
1269 | ||
93ce0ba6 JN |
1270 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1271 | enum pipe pipe, bool state) | |
1272 | { | |
1273 | struct drm_device *dev = dev_priv->dev; | |
1274 | bool cur_state; | |
1275 | ||
d9d82081 | 1276 | if (IS_845G(dev) || IS_I865G(dev)) |
0b87c24e | 1277 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1278 | else |
5efb3e28 | 1279 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1280 | |
e2c719b7 | 1281 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1282 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1283 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1284 | } |
1285 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1286 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1287 | ||
b840d907 JB |
1288 | void assert_pipe(struct drm_i915_private *dev_priv, |
1289 | enum pipe pipe, bool state) | |
b24e7179 | 1290 | { |
63d7bbe9 | 1291 | bool cur_state; |
702e7a56 PZ |
1292 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1293 | pipe); | |
4feed0eb | 1294 | enum intel_display_power_domain power_domain; |
b24e7179 | 1295 | |
b6b5d049 VS |
1296 | /* if we need the pipe quirk it must be always on */ |
1297 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1298 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1299 | state = true; |
1300 | ||
4feed0eb ID |
1301 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); |
1302 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
649636ef | 1303 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 | 1304 | cur_state = !!(val & PIPECONF_ENABLE); |
4feed0eb ID |
1305 | |
1306 | intel_display_power_put(dev_priv, power_domain); | |
1307 | } else { | |
1308 | cur_state = false; | |
69310161 PZ |
1309 | } |
1310 | ||
e2c719b7 | 1311 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1312 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1313 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1314 | } |
1315 | ||
931872fc CW |
1316 | static void assert_plane(struct drm_i915_private *dev_priv, |
1317 | enum plane plane, bool state) | |
b24e7179 | 1318 | { |
b24e7179 | 1319 | u32 val; |
931872fc | 1320 | bool cur_state; |
b24e7179 | 1321 | |
649636ef | 1322 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1323 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1324 | I915_STATE_WARN(cur_state != state, |
931872fc | 1325 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1326 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1327 | } |
1328 | ||
931872fc CW |
1329 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1330 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1331 | ||
b24e7179 JB |
1332 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1333 | enum pipe pipe) | |
1334 | { | |
653e1026 | 1335 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1336 | int i; |
b24e7179 | 1337 | |
653e1026 VS |
1338 | /* Primary planes are fixed to pipes on gen4+ */ |
1339 | if (INTEL_INFO(dev)->gen >= 4) { | |
649636ef | 1340 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1341 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1342 | "plane %c assertion failure, should be disabled but not\n", |
1343 | plane_name(pipe)); | |
19ec1358 | 1344 | return; |
28c05794 | 1345 | } |
19ec1358 | 1346 | |
b24e7179 | 1347 | /* Need to check both planes against the pipe */ |
055e393f | 1348 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1349 | u32 val = I915_READ(DSPCNTR(i)); |
1350 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1351 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1352 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1353 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1354 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1355 | } |
1356 | } | |
1357 | ||
19332d7a JB |
1358 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1359 | enum pipe pipe) | |
1360 | { | |
20674eef | 1361 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1362 | int sprite; |
19332d7a | 1363 | |
7feb8b88 | 1364 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1365 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1366 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1367 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1368 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1369 | sprite, pipe_name(pipe)); | |
1370 | } | |
666a4537 | 1371 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
3bdcfc0c | 1372 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1373 | u32 val = I915_READ(SPCNTR(pipe, sprite)); |
e2c719b7 | 1374 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1375 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1376 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1377 | } |
1378 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
649636ef | 1379 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1380 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1381 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1382 | plane_name(pipe), pipe_name(pipe)); |
1383 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
649636ef | 1384 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1385 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1386 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1387 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1388 | } |
1389 | } | |
1390 | ||
08c71e5e VS |
1391 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1392 | { | |
e2c719b7 | 1393 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1394 | drm_crtc_vblank_put(crtc); |
1395 | } | |
1396 | ||
7abd4b35 ACO |
1397 | void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1398 | enum pipe pipe) | |
92f2584a | 1399 | { |
92f2584a JB |
1400 | u32 val; |
1401 | bool enabled; | |
1402 | ||
649636ef | 1403 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1404 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1405 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1406 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1407 | pipe_name(pipe)); | |
92f2584a JB |
1408 | } |
1409 | ||
4e634389 KP |
1410 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1411 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1412 | { |
1413 | if ((val & DP_PORT_EN) == 0) | |
1414 | return false; | |
1415 | ||
2d1fe073 | 1416 | if (HAS_PCH_CPT(dev_priv)) { |
f0f59a00 | 1417 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1418 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1419 | return false; | |
2d1fe073 | 1420 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1421 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) |
1422 | return false; | |
f0575e92 KP |
1423 | } else { |
1424 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1425 | return false; | |
1426 | } | |
1427 | return true; | |
1428 | } | |
1429 | ||
1519b995 KP |
1430 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1431 | enum pipe pipe, u32 val) | |
1432 | { | |
dc0fa718 | 1433 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1434 | return false; |
1435 | ||
2d1fe073 | 1436 | if (HAS_PCH_CPT(dev_priv)) { |
dc0fa718 | 1437 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1438 | return false; |
2d1fe073 | 1439 | } else if (IS_CHERRYVIEW(dev_priv)) { |
44f37d1f CML |
1440 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) |
1441 | return false; | |
1519b995 | 1442 | } else { |
dc0fa718 | 1443 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1444 | return false; |
1445 | } | |
1446 | return true; | |
1447 | } | |
1448 | ||
1449 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1450 | enum pipe pipe, u32 val) | |
1451 | { | |
1452 | if ((val & LVDS_PORT_EN) == 0) | |
1453 | return false; | |
1454 | ||
2d1fe073 | 1455 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1456 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1457 | return false; | |
1458 | } else { | |
1459 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1460 | return false; | |
1461 | } | |
1462 | return true; | |
1463 | } | |
1464 | ||
1465 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1466 | enum pipe pipe, u32 val) | |
1467 | { | |
1468 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1469 | return false; | |
2d1fe073 | 1470 | if (HAS_PCH_CPT(dev_priv)) { |
1519b995 KP |
1471 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) |
1472 | return false; | |
1473 | } else { | |
1474 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1475 | return false; | |
1476 | } | |
1477 | return true; | |
1478 | } | |
1479 | ||
291906f1 | 1480 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1481 | enum pipe pipe, i915_reg_t reg, |
1482 | u32 port_sel) | |
291906f1 | 1483 | { |
47a05eca | 1484 | u32 val = I915_READ(reg); |
e2c719b7 | 1485 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1486 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1487 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1488 | |
2d1fe073 | 1489 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1490 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1491 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1492 | } |
1493 | ||
1494 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1495 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1496 | { |
47a05eca | 1497 | u32 val = I915_READ(reg); |
e2c719b7 | 1498 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1499 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1500 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1501 | |
2d1fe073 | 1502 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1503 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1504 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1505 | } |
1506 | ||
1507 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1508 | enum pipe pipe) | |
1509 | { | |
291906f1 | 1510 | u32 val; |
291906f1 | 1511 | |
f0575e92 KP |
1512 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1513 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1514 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1515 | |
649636ef | 1516 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1517 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1518 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1519 | pipe_name(pipe)); |
291906f1 | 1520 | |
649636ef | 1521 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1522 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1523 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1524 | pipe_name(pipe)); |
291906f1 | 1525 | |
e2debe91 PZ |
1526 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1527 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1528 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1529 | } |
1530 | ||
cd2d34d9 VS |
1531 | static void _vlv_enable_pll(struct intel_crtc *crtc, |
1532 | const struct intel_crtc_state *pipe_config) | |
1533 | { | |
1534 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1535 | enum pipe pipe = crtc->pipe; | |
1536 | ||
1537 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); | |
1538 | POSTING_READ(DPLL(pipe)); | |
1539 | udelay(150); | |
1540 | ||
1541 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1542 | DRM_ERROR("DPLL %d failed to lock\n", pipe); | |
1543 | } | |
1544 | ||
d288f65f | 1545 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1546 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1547 | { |
cd2d34d9 | 1548 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1549 | enum pipe pipe = crtc->pipe; |
87442f73 | 1550 | |
8bd3f301 | 1551 | assert_pipe_disabled(dev_priv, pipe); |
87442f73 | 1552 | |
87442f73 | 1553 | /* PLL is protected by panel, make sure we can write it */ |
7d1a83cb | 1554 | assert_panel_unlocked(dev_priv, pipe); |
87442f73 | 1555 | |
cd2d34d9 VS |
1556 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) |
1557 | _vlv_enable_pll(crtc, pipe_config); | |
426115cf | 1558 | |
8bd3f301 VS |
1559 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
1560 | POSTING_READ(DPLL_MD(pipe)); | |
87442f73 DV |
1561 | } |
1562 | ||
cd2d34d9 VS |
1563 | |
1564 | static void _chv_enable_pll(struct intel_crtc *crtc, | |
1565 | const struct intel_crtc_state *pipe_config) | |
9d556c99 | 1566 | { |
cd2d34d9 | 1567 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
8bd3f301 | 1568 | enum pipe pipe = crtc->pipe; |
9d556c99 | 1569 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9d556c99 CML |
1570 | u32 tmp; |
1571 | ||
a580516d | 1572 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1573 | |
1574 | /* Enable back the 10bit clock to display controller */ | |
1575 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1576 | tmp |= DPIO_DCLKP_EN; | |
1577 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1578 | ||
54433e91 VS |
1579 | mutex_unlock(&dev_priv->sb_lock); |
1580 | ||
9d556c99 CML |
1581 | /* |
1582 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1583 | */ | |
1584 | udelay(1); | |
1585 | ||
1586 | /* Enable PLL */ | |
d288f65f | 1587 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1588 | |
1589 | /* Check PLL is locked */ | |
a11b0703 | 1590 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 | 1591 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
cd2d34d9 VS |
1592 | } |
1593 | ||
1594 | static void chv_enable_pll(struct intel_crtc *crtc, | |
1595 | const struct intel_crtc_state *pipe_config) | |
1596 | { | |
1597 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1598 | enum pipe pipe = crtc->pipe; | |
1599 | ||
1600 | assert_pipe_disabled(dev_priv, pipe); | |
1601 | ||
1602 | /* PLL is protected by panel, make sure we can write it */ | |
1603 | assert_panel_unlocked(dev_priv, pipe); | |
1604 | ||
1605 | if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) | |
1606 | _chv_enable_pll(crtc, pipe_config); | |
9d556c99 | 1607 | |
c231775c VS |
1608 | if (pipe != PIPE_A) { |
1609 | /* | |
1610 | * WaPixelRepeatModeFixForC0:chv | |
1611 | * | |
1612 | * DPLLCMD is AWOL. Use chicken bits to propagate | |
1613 | * the value from DPLLBMD to either pipe B or C. | |
1614 | */ | |
1615 | I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C); | |
1616 | I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md); | |
1617 | I915_WRITE(CBR4_VLV, 0); | |
1618 | dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; | |
1619 | ||
1620 | /* | |
1621 | * DPLLB VGA mode also seems to cause problems. | |
1622 | * We should always have it disabled. | |
1623 | */ | |
1624 | WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0); | |
1625 | } else { | |
1626 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); | |
1627 | POSTING_READ(DPLL_MD(pipe)); | |
1628 | } | |
9d556c99 CML |
1629 | } |
1630 | ||
1c4e0274 VS |
1631 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1632 | { | |
1633 | struct intel_crtc *crtc; | |
1634 | int count = 0; | |
1635 | ||
1636 | for_each_intel_crtc(dev, crtc) | |
3538b9df | 1637 | count += crtc->base.state->active && |
409ee761 | 1638 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1639 | |
1640 | return count; | |
1641 | } | |
1642 | ||
66e3d5c0 | 1643 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1644 | { |
66e3d5c0 DV |
1645 | struct drm_device *dev = crtc->base.dev; |
1646 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1647 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1648 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1649 | |
66e3d5c0 | 1650 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1651 | |
63d7bbe9 | 1652 | /* PLL is protected by panel, make sure we can write it */ |
66e3d5c0 DV |
1653 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1654 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1655 | |
1c4e0274 VS |
1656 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1657 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1658 | /* | |
1659 | * It appears to be important that we don't enable this | |
1660 | * for the current pipe before otherwise configuring the | |
1661 | * PLL. No idea how this should be handled if multiple | |
1662 | * DVO outputs are enabled simultaneosly. | |
1663 | */ | |
1664 | dpll |= DPLL_DVO_2X_MODE; | |
1665 | I915_WRITE(DPLL(!crtc->pipe), | |
1666 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1667 | } | |
66e3d5c0 | 1668 | |
c2b63374 VS |
1669 | /* |
1670 | * Apparently we need to have VGA mode enabled prior to changing | |
1671 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1672 | * dividers, even though the register value does change. | |
1673 | */ | |
1674 | I915_WRITE(reg, 0); | |
1675 | ||
8e7a65aa VS |
1676 | I915_WRITE(reg, dpll); |
1677 | ||
66e3d5c0 DV |
1678 | /* Wait for the clocks to stabilize. */ |
1679 | POSTING_READ(reg); | |
1680 | udelay(150); | |
1681 | ||
1682 | if (INTEL_INFO(dev)->gen >= 4) { | |
1683 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1684 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1685 | } else { |
1686 | /* The pixel multiplier can only be updated once the | |
1687 | * DPLL is enabled and the clocks are stable. | |
1688 | * | |
1689 | * So write it again. | |
1690 | */ | |
1691 | I915_WRITE(reg, dpll); | |
1692 | } | |
63d7bbe9 JB |
1693 | |
1694 | /* We do this three times for luck */ | |
66e3d5c0 | 1695 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1696 | POSTING_READ(reg); |
1697 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1698 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1699 | POSTING_READ(reg); |
1700 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1701 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1702 | POSTING_READ(reg); |
1703 | udelay(150); /* wait for warmup */ | |
1704 | } | |
1705 | ||
1706 | /** | |
50b44a44 | 1707 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1708 | * @dev_priv: i915 private structure |
1709 | * @pipe: pipe PLL to disable | |
1710 | * | |
1711 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1712 | * | |
1713 | * Note! This is for pre-ILK only. | |
1714 | */ | |
1c4e0274 | 1715 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1716 | { |
1c4e0274 VS |
1717 | struct drm_device *dev = crtc->base.dev; |
1718 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1719 | enum pipe pipe = crtc->pipe; | |
1720 | ||
1721 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1722 | if (IS_I830(dev) && | |
409ee761 | 1723 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
3538b9df | 1724 | !intel_num_dvo_pipes(dev)) { |
1c4e0274 VS |
1725 | I915_WRITE(DPLL(PIPE_B), |
1726 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1727 | I915_WRITE(DPLL(PIPE_A), | |
1728 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1729 | } | |
1730 | ||
b6b5d049 VS |
1731 | /* Don't disable pipe or pipe PLLs if needed */ |
1732 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1733 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1734 | return; |
1735 | ||
1736 | /* Make sure the pipe isn't still relying on us */ | |
1737 | assert_pipe_disabled(dev_priv, pipe); | |
1738 | ||
b8afb911 | 1739 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1740 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1741 | } |
1742 | ||
f6071166 JB |
1743 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1744 | { | |
b8afb911 | 1745 | u32 val; |
f6071166 JB |
1746 | |
1747 | /* Make sure the pipe isn't still relying on us */ | |
1748 | assert_pipe_disabled(dev_priv, pipe); | |
1749 | ||
03ed5cbf VS |
1750 | val = DPLL_INTEGRATED_REF_CLK_VLV | |
1751 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
1752 | if (pipe != PIPE_A) | |
1753 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1754 | ||
f6071166 JB |
1755 | I915_WRITE(DPLL(pipe), val); |
1756 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1757 | } |
1758 | ||
1759 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1760 | { | |
d752048d | 1761 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1762 | u32 val; |
1763 | ||
a11b0703 VS |
1764 | /* Make sure the pipe isn't still relying on us */ |
1765 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1766 | |
60bfe44f VS |
1767 | val = DPLL_SSC_REF_CLK_CHV | |
1768 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1769 | if (pipe != PIPE_A) |
1770 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
03ed5cbf | 1771 | |
a11b0703 VS |
1772 | I915_WRITE(DPLL(pipe), val); |
1773 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1774 | |
a580516d | 1775 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1776 | |
1777 | /* Disable 10bit clock to display controller */ | |
1778 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1779 | val &= ~DPIO_DCLKP_EN; | |
1780 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1781 | ||
a580516d | 1782 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1783 | } |
1784 | ||
e4607fcf | 1785 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1786 | struct intel_digital_port *dport, |
1787 | unsigned int expected_mask) | |
89b667f8 JB |
1788 | { |
1789 | u32 port_mask; | |
f0f59a00 | 1790 | i915_reg_t dpll_reg; |
89b667f8 | 1791 | |
e4607fcf CML |
1792 | switch (dport->port) { |
1793 | case PORT_B: | |
89b667f8 | 1794 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1795 | dpll_reg = DPLL(0); |
e4607fcf CML |
1796 | break; |
1797 | case PORT_C: | |
89b667f8 | 1798 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1799 | dpll_reg = DPLL(0); |
9b6de0a1 | 1800 | expected_mask <<= 4; |
00fc31b7 CML |
1801 | break; |
1802 | case PORT_D: | |
1803 | port_mask = DPLL_PORTD_READY_MASK; | |
1804 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1805 | break; |
1806 | default: | |
1807 | BUG(); | |
1808 | } | |
89b667f8 | 1809 | |
9b6de0a1 VS |
1810 | if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) |
1811 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", | |
1812 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1813 | } |
1814 | ||
b8a4f404 PZ |
1815 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1816 | enum pipe pipe) | |
040484af | 1817 | { |
23670b32 | 1818 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1819 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1820 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
f0f59a00 VS |
1821 | i915_reg_t reg; |
1822 | uint32_t val, pipeconf_val; | |
040484af | 1823 | |
040484af | 1824 | /* Make sure PCH DPLL is enabled */ |
8106ddbd | 1825 | assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll); |
040484af JB |
1826 | |
1827 | /* FDI must be feeding us bits for PCH ports */ | |
1828 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1829 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1830 | ||
23670b32 DV |
1831 | if (HAS_PCH_CPT(dev)) { |
1832 | /* Workaround: Set the timing override bit before enabling the | |
1833 | * pch transcoder. */ | |
1834 | reg = TRANS_CHICKEN2(pipe); | |
1835 | val = I915_READ(reg); | |
1836 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1837 | I915_WRITE(reg, val); | |
59c859d6 | 1838 | } |
23670b32 | 1839 | |
ab9412ba | 1840 | reg = PCH_TRANSCONF(pipe); |
040484af | 1841 | val = I915_READ(reg); |
5f7f726d | 1842 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c | 1843 | |
2d1fe073 | 1844 | if (HAS_PCH_IBX(dev_priv)) { |
e9bcff5c | 1845 | /* |
c5de7c6f VS |
1846 | * Make the BPC in transcoder be consistent with |
1847 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1848 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1849 | */ |
dfd07d72 | 1850 | val &= ~PIPECONF_BPC_MASK; |
c5de7c6f VS |
1851 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) |
1852 | val |= PIPECONF_8BPC; | |
1853 | else | |
1854 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1855 | } |
5f7f726d PZ |
1856 | |
1857 | val &= ~TRANS_INTERLACE_MASK; | |
1858 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
2d1fe073 | 1859 | if (HAS_PCH_IBX(dev_priv) && |
409ee761 | 1860 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
1861 | val |= TRANS_LEGACY_INTERLACED_ILK; |
1862 | else | |
1863 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1864 | else |
1865 | val |= TRANS_PROGRESSIVE; | |
1866 | ||
040484af JB |
1867 | I915_WRITE(reg, val | TRANS_ENABLE); |
1868 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1869 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1870 | } |
1871 | ||
8fb033d7 | 1872 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1873 | enum transcoder cpu_transcoder) |
040484af | 1874 | { |
8fb033d7 | 1875 | u32 val, pipeconf_val; |
8fb033d7 | 1876 | |
8fb033d7 | 1877 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1878 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1879 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1880 | |
223a6fdf | 1881 | /* Workaround: set timing override bit. */ |
36c0d0cf | 1882 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1883 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1884 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 1885 | |
25f3ef11 | 1886 | val = TRANS_ENABLE; |
937bb610 | 1887 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1888 | |
9a76b1c6 PZ |
1889 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1890 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1891 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1892 | else |
1893 | val |= TRANS_PROGRESSIVE; | |
1894 | ||
ab9412ba DV |
1895 | I915_WRITE(LPT_TRANSCONF, val); |
1896 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1897 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1898 | } |
1899 | ||
b8a4f404 PZ |
1900 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1901 | enum pipe pipe) | |
040484af | 1902 | { |
23670b32 | 1903 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 VS |
1904 | i915_reg_t reg; |
1905 | uint32_t val; | |
040484af JB |
1906 | |
1907 | /* FDI relies on the transcoder */ | |
1908 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1909 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1910 | ||
291906f1 JB |
1911 | /* Ports must be off as well */ |
1912 | assert_pch_ports_disabled(dev_priv, pipe); | |
1913 | ||
ab9412ba | 1914 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1915 | val = I915_READ(reg); |
1916 | val &= ~TRANS_ENABLE; | |
1917 | I915_WRITE(reg, val); | |
1918 | /* wait for PCH transcoder off, transcoder state */ | |
1919 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 1920 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 1921 | |
c465613b | 1922 | if (HAS_PCH_CPT(dev)) { |
23670b32 DV |
1923 | /* Workaround: Clear the timing override chicken bit again. */ |
1924 | reg = TRANS_CHICKEN2(pipe); | |
1925 | val = I915_READ(reg); | |
1926 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1927 | I915_WRITE(reg, val); | |
1928 | } | |
040484af JB |
1929 | } |
1930 | ||
ab4d966c | 1931 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 1932 | { |
8fb033d7 PZ |
1933 | u32 val; |
1934 | ||
ab9412ba | 1935 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 1936 | val &= ~TRANS_ENABLE; |
ab9412ba | 1937 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 1938 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 1939 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 1940 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
1941 | |
1942 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 1943 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 1944 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 1945 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
1946 | } |
1947 | ||
b24e7179 | 1948 | /** |
309cfea8 | 1949 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 1950 | * @crtc: crtc responsible for the pipe |
b24e7179 | 1951 | * |
0372264a | 1952 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 1953 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 1954 | */ |
e1fdc473 | 1955 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 1956 | { |
0372264a PZ |
1957 | struct drm_device *dev = crtc->base.dev; |
1958 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1959 | enum pipe pipe = crtc->pipe; | |
1a70a728 | 1960 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
1a240d4d | 1961 | enum pipe pch_transcoder; |
f0f59a00 | 1962 | i915_reg_t reg; |
b24e7179 JB |
1963 | u32 val; |
1964 | ||
9e2ee2dd VS |
1965 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
1966 | ||
58c6eaa2 | 1967 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 1968 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
1969 | assert_sprites_disabled(dev_priv, pipe); |
1970 | ||
2d1fe073 | 1971 | if (HAS_PCH_LPT(dev_priv)) |
cc391bbb PZ |
1972 | pch_transcoder = TRANSCODER_A; |
1973 | else | |
1974 | pch_transcoder = pipe; | |
1975 | ||
b24e7179 JB |
1976 | /* |
1977 | * A pipe without a PLL won't actually be able to drive bits from | |
1978 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
1979 | * need the check. | |
1980 | */ | |
2d1fe073 | 1981 | if (HAS_GMCH_DISPLAY(dev_priv)) |
a65347ba | 1982 | if (crtc->config->has_dsi_encoder) |
23538ef1 JN |
1983 | assert_dsi_pll_enabled(dev_priv); |
1984 | else | |
1985 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 1986 | else { |
6e3c9717 | 1987 | if (crtc->config->has_pch_encoder) { |
040484af | 1988 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 1989 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
1990 | assert_fdi_tx_pll_enabled(dev_priv, |
1991 | (enum pipe) cpu_transcoder); | |
040484af JB |
1992 | } |
1993 | /* FIXME: assert CPU port conditions for SNB+ */ | |
1994 | } | |
b24e7179 | 1995 | |
702e7a56 | 1996 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 1997 | val = I915_READ(reg); |
7ad25d48 | 1998 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
1999 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2000 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2001 | return; |
7ad25d48 | 2002 | } |
00d70b15 CW |
2003 | |
2004 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2005 | POSTING_READ(reg); |
b7792d8b VS |
2006 | |
2007 | /* | |
2008 | * Until the pipe starts DSL will read as 0, which would cause | |
2009 | * an apparent vblank timestamp jump, which messes up also the | |
2010 | * frame count when it's derived from the timestamps. So let's | |
2011 | * wait for the pipe to start properly before we call | |
2012 | * drm_crtc_vblank_on() | |
2013 | */ | |
2014 | if (dev->max_vblank_count == 0 && | |
2015 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
2016 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
2017 | } |
2018 | ||
2019 | /** | |
309cfea8 | 2020 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2021 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2022 | * |
575f7ab7 VS |
2023 | * Disable the pipe of @crtc, making sure that various hardware |
2024 | * specific requirements are met, if applicable, e.g. plane | |
2025 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2026 | * |
2027 | * Will wait until the pipe has shut down before returning. | |
2028 | */ | |
575f7ab7 | 2029 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2030 | { |
575f7ab7 | 2031 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2032 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2033 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 2034 | i915_reg_t reg; |
b24e7179 JB |
2035 | u32 val; |
2036 | ||
9e2ee2dd VS |
2037 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2038 | ||
b24e7179 JB |
2039 | /* |
2040 | * Make sure planes won't keep trying to pump pixels to us, | |
2041 | * or we might hang the display. | |
2042 | */ | |
2043 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2044 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2045 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2046 | |
702e7a56 | 2047 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2048 | val = I915_READ(reg); |
00d70b15 CW |
2049 | if ((val & PIPECONF_ENABLE) == 0) |
2050 | return; | |
2051 | ||
67adc644 VS |
2052 | /* |
2053 | * Double wide has implications for planes | |
2054 | * so best keep it disabled when not needed. | |
2055 | */ | |
6e3c9717 | 2056 | if (crtc->config->double_wide) |
67adc644 VS |
2057 | val &= ~PIPECONF_DOUBLE_WIDE; |
2058 | ||
2059 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2060 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2061 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2062 | val &= ~PIPECONF_ENABLE; |
2063 | ||
2064 | I915_WRITE(reg, val); | |
2065 | if ((val & PIPECONF_ENABLE) == 0) | |
2066 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2067 | } |
2068 | ||
693db184 CW |
2069 | static bool need_vtd_wa(struct drm_device *dev) |
2070 | { | |
2071 | #ifdef CONFIG_INTEL_IOMMU | |
2072 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2073 | return true; | |
2074 | #endif | |
2075 | return false; | |
2076 | } | |
2077 | ||
832be82f VS |
2078 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
2079 | { | |
2080 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
2081 | } | |
2082 | ||
27ba3910 VS |
2083 | static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv, |
2084 | uint64_t fb_modifier, unsigned int cpp) | |
7b49f948 VS |
2085 | { |
2086 | switch (fb_modifier) { | |
2087 | case DRM_FORMAT_MOD_NONE: | |
2088 | return cpp; | |
2089 | case I915_FORMAT_MOD_X_TILED: | |
2090 | if (IS_GEN2(dev_priv)) | |
2091 | return 128; | |
2092 | else | |
2093 | return 512; | |
2094 | case I915_FORMAT_MOD_Y_TILED: | |
2095 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2096 | return 128; | |
2097 | else | |
2098 | return 512; | |
2099 | case I915_FORMAT_MOD_Yf_TILED: | |
2100 | switch (cpp) { | |
2101 | case 1: | |
2102 | return 64; | |
2103 | case 2: | |
2104 | case 4: | |
2105 | return 128; | |
2106 | case 8: | |
2107 | case 16: | |
2108 | return 256; | |
2109 | default: | |
2110 | MISSING_CASE(cpp); | |
2111 | return cpp; | |
2112 | } | |
2113 | break; | |
2114 | default: | |
2115 | MISSING_CASE(fb_modifier); | |
2116 | return cpp; | |
2117 | } | |
2118 | } | |
2119 | ||
832be82f VS |
2120 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
2121 | uint64_t fb_modifier, unsigned int cpp) | |
a57ce0b2 | 2122 | { |
832be82f VS |
2123 | if (fb_modifier == DRM_FORMAT_MOD_NONE) |
2124 | return 1; | |
2125 | else | |
2126 | return intel_tile_size(dev_priv) / | |
27ba3910 | 2127 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
6761dd31 TU |
2128 | } |
2129 | ||
8d0deca8 VS |
2130 | /* Return the tile dimensions in pixel units */ |
2131 | static void intel_tile_dims(const struct drm_i915_private *dev_priv, | |
2132 | unsigned int *tile_width, | |
2133 | unsigned int *tile_height, | |
2134 | uint64_t fb_modifier, | |
2135 | unsigned int cpp) | |
2136 | { | |
2137 | unsigned int tile_width_bytes = | |
2138 | intel_tile_width_bytes(dev_priv, fb_modifier, cpp); | |
2139 | ||
2140 | *tile_width = tile_width_bytes / cpp; | |
2141 | *tile_height = intel_tile_size(dev_priv) / tile_width_bytes; | |
2142 | } | |
2143 | ||
6761dd31 TU |
2144 | unsigned int |
2145 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
832be82f | 2146 | uint32_t pixel_format, uint64_t fb_modifier) |
6761dd31 | 2147 | { |
832be82f VS |
2148 | unsigned int cpp = drm_format_plane_cpp(pixel_format, 0); |
2149 | unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp); | |
2150 | ||
2151 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2152 | } |
2153 | ||
1663b9d6 VS |
2154 | unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info) |
2155 | { | |
2156 | unsigned int size = 0; | |
2157 | int i; | |
2158 | ||
2159 | for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++) | |
2160 | size += rot_info->plane[i].width * rot_info->plane[i].height; | |
2161 | ||
2162 | return size; | |
2163 | } | |
2164 | ||
75c82a53 | 2165 | static void |
3465c580 VS |
2166 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, |
2167 | const struct drm_framebuffer *fb, | |
2168 | unsigned int rotation) | |
f64b98cd | 2169 | { |
2d7a215f VS |
2170 | if (intel_rotation_90_or_270(rotation)) { |
2171 | *view = i915_ggtt_view_rotated; | |
2172 | view->params.rotated = to_intel_framebuffer(fb)->rot_info; | |
2173 | } else { | |
2174 | *view = i915_ggtt_view_normal; | |
2175 | } | |
2176 | } | |
50470bb0 | 2177 | |
2d7a215f VS |
2178 | static void |
2179 | intel_fill_fb_info(struct drm_i915_private *dev_priv, | |
2180 | struct drm_framebuffer *fb) | |
2181 | { | |
2182 | struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info; | |
2183 | unsigned int tile_size, tile_width, tile_height, cpp; | |
50470bb0 | 2184 | |
d9b3288e VS |
2185 | tile_size = intel_tile_size(dev_priv); |
2186 | ||
2187 | cpp = drm_format_plane_cpp(fb->pixel_format, 0); | |
8d0deca8 VS |
2188 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2189 | fb->modifier[0], cpp); | |
d9b3288e | 2190 | |
1663b9d6 VS |
2191 | info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp); |
2192 | info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height); | |
84fe03f7 | 2193 | |
89e3e142 | 2194 | if (info->pixel_format == DRM_FORMAT_NV12) { |
832be82f | 2195 | cpp = drm_format_plane_cpp(fb->pixel_format, 1); |
8d0deca8 VS |
2196 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2197 | fb->modifier[1], cpp); | |
d9b3288e | 2198 | |
2d7a215f | 2199 | info->uv_offset = fb->offsets[1]; |
1663b9d6 VS |
2200 | info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp); |
2201 | info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height); | |
89e3e142 | 2202 | } |
f64b98cd TU |
2203 | } |
2204 | ||
603525d7 | 2205 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2206 | { |
2207 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2208 | return 256 * 1024; | |
985b8bb4 | 2209 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
666a4537 | 2210 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2211 | return 128 * 1024; |
2212 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2213 | return 4 * 1024; | |
2214 | else | |
44c5905e | 2215 | return 0; |
4e9a86b6 VS |
2216 | } |
2217 | ||
603525d7 VS |
2218 | static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv, |
2219 | uint64_t fb_modifier) | |
2220 | { | |
2221 | switch (fb_modifier) { | |
2222 | case DRM_FORMAT_MOD_NONE: | |
2223 | return intel_linear_alignment(dev_priv); | |
2224 | case I915_FORMAT_MOD_X_TILED: | |
2225 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2226 | return 256 * 1024; | |
2227 | return 0; | |
2228 | case I915_FORMAT_MOD_Y_TILED: | |
2229 | case I915_FORMAT_MOD_Yf_TILED: | |
2230 | return 1 * 1024 * 1024; | |
2231 | default: | |
2232 | MISSING_CASE(fb_modifier); | |
2233 | return 0; | |
2234 | } | |
2235 | } | |
2236 | ||
127bd2ac | 2237 | int |
3465c580 VS |
2238 | intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb, |
2239 | unsigned int rotation) | |
6b95a207 | 2240 | { |
850c4cdc | 2241 | struct drm_device *dev = fb->dev; |
ce453d81 | 2242 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2243 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2244 | struct i915_ggtt_view view; |
6b95a207 KH |
2245 | u32 alignment; |
2246 | int ret; | |
2247 | ||
ebcdd39e MR |
2248 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2249 | ||
603525d7 | 2250 | alignment = intel_surf_alignment(dev_priv, fb->modifier[0]); |
6b95a207 | 2251 | |
3465c580 | 2252 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2253 | |
693db184 CW |
2254 | /* Note that the w/a also requires 64 PTE of padding following the |
2255 | * bo. We currently fill all unused PTE with the shadow page and so | |
2256 | * we should always have valid PTE following the scanout preventing | |
2257 | * the VT-d warning. | |
2258 | */ | |
2259 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2260 | alignment = 256 * 1024; | |
2261 | ||
d6dd6843 PZ |
2262 | /* |
2263 | * Global gtt pte registers are special registers which actually forward | |
2264 | * writes to a chunk of system memory. Which means that there is no risk | |
2265 | * that the register values disappear as soon as we call | |
2266 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2267 | * pin/unpin/fence and not more. | |
2268 | */ | |
2269 | intel_runtime_pm_get(dev_priv); | |
2270 | ||
7580d774 ML |
2271 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, |
2272 | &view); | |
48b956c5 | 2273 | if (ret) |
b26a6b35 | 2274 | goto err_pm; |
6b95a207 KH |
2275 | |
2276 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2277 | * fence, whereas 965+ only requires a fence if using | |
2278 | * framebuffer compression. For simplicity, we always install | |
2279 | * a fence as the cost is not that onerous. | |
2280 | */ | |
9807216f VK |
2281 | if (view.type == I915_GGTT_VIEW_NORMAL) { |
2282 | ret = i915_gem_object_get_fence(obj); | |
2283 | if (ret == -EDEADLK) { | |
2284 | /* | |
2285 | * -EDEADLK means there are no free fences | |
2286 | * no pending flips. | |
2287 | * | |
2288 | * This is propagated to atomic, but it uses | |
2289 | * -EDEADLK to force a locking recovery, so | |
2290 | * change the returned error to -EBUSY. | |
2291 | */ | |
2292 | ret = -EBUSY; | |
2293 | goto err_unpin; | |
2294 | } else if (ret) | |
2295 | goto err_unpin; | |
1690e1eb | 2296 | |
9807216f VK |
2297 | i915_gem_object_pin_fence(obj); |
2298 | } | |
6b95a207 | 2299 | |
d6dd6843 | 2300 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2301 | return 0; |
48b956c5 CW |
2302 | |
2303 | err_unpin: | |
f64b98cd | 2304 | i915_gem_object_unpin_from_display_plane(obj, &view); |
b26a6b35 | 2305 | err_pm: |
d6dd6843 | 2306 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2307 | return ret; |
6b95a207 KH |
2308 | } |
2309 | ||
fb4b8ce1 | 2310 | void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation) |
1690e1eb | 2311 | { |
82bc3b2d | 2312 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2313 | struct i915_ggtt_view view; |
82bc3b2d | 2314 | |
ebcdd39e MR |
2315 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2316 | ||
3465c580 | 2317 | intel_fill_fb_ggtt_view(&view, fb, rotation); |
f64b98cd | 2318 | |
9807216f VK |
2319 | if (view.type == I915_GGTT_VIEW_NORMAL) |
2320 | i915_gem_object_unpin_fence(obj); | |
2321 | ||
f64b98cd | 2322 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2323 | } |
2324 | ||
29cf9491 VS |
2325 | /* |
2326 | * Adjust the tile offset by moving the difference into | |
2327 | * the x/y offsets. | |
2328 | * | |
2329 | * Input tile dimensions and pitch must already be | |
2330 | * rotated to match x and y, and in pixel units. | |
2331 | */ | |
2332 | static u32 intel_adjust_tile_offset(int *x, int *y, | |
2333 | unsigned int tile_width, | |
2334 | unsigned int tile_height, | |
2335 | unsigned int tile_size, | |
2336 | unsigned int pitch_tiles, | |
2337 | u32 old_offset, | |
2338 | u32 new_offset) | |
2339 | { | |
2340 | unsigned int tiles; | |
2341 | ||
2342 | WARN_ON(old_offset & (tile_size - 1)); | |
2343 | WARN_ON(new_offset & (tile_size - 1)); | |
2344 | WARN_ON(new_offset > old_offset); | |
2345 | ||
2346 | tiles = (old_offset - new_offset) / tile_size; | |
2347 | ||
2348 | *y += tiles / pitch_tiles * tile_height; | |
2349 | *x += tiles % pitch_tiles * tile_width; | |
2350 | ||
2351 | return new_offset; | |
2352 | } | |
2353 | ||
8d0deca8 VS |
2354 | /* |
2355 | * Computes the linear offset to the base tile and adjusts | |
2356 | * x, y. bytes per pixel is assumed to be a power-of-two. | |
2357 | * | |
2358 | * In the 90/270 rotated case, x and y are assumed | |
2359 | * to be already rotated to match the rotated GTT view, and | |
2360 | * pitch is the tile_height aligned framebuffer height. | |
2361 | */ | |
4f2d9934 VS |
2362 | u32 intel_compute_tile_offset(int *x, int *y, |
2363 | const struct drm_framebuffer *fb, int plane, | |
8d0deca8 VS |
2364 | unsigned int pitch, |
2365 | unsigned int rotation) | |
c2c75131 | 2366 | { |
4f2d9934 VS |
2367 | const struct drm_i915_private *dev_priv = to_i915(fb->dev); |
2368 | uint64_t fb_modifier = fb->modifier[plane]; | |
2369 | unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane); | |
29cf9491 VS |
2370 | u32 offset, offset_aligned, alignment; |
2371 | ||
2372 | alignment = intel_surf_alignment(dev_priv, fb_modifier); | |
2373 | if (alignment) | |
2374 | alignment--; | |
2375 | ||
b5c65338 | 2376 | if (fb_modifier != DRM_FORMAT_MOD_NONE) { |
8d0deca8 VS |
2377 | unsigned int tile_size, tile_width, tile_height; |
2378 | unsigned int tile_rows, tiles, pitch_tiles; | |
c2c75131 | 2379 | |
d843310d | 2380 | tile_size = intel_tile_size(dev_priv); |
8d0deca8 VS |
2381 | intel_tile_dims(dev_priv, &tile_width, &tile_height, |
2382 | fb_modifier, cpp); | |
2383 | ||
2384 | if (intel_rotation_90_or_270(rotation)) { | |
2385 | pitch_tiles = pitch / tile_height; | |
2386 | swap(tile_width, tile_height); | |
2387 | } else { | |
2388 | pitch_tiles = pitch / (tile_width * cpp); | |
2389 | } | |
d843310d VS |
2390 | |
2391 | tile_rows = *y / tile_height; | |
2392 | *y %= tile_height; | |
c2c75131 | 2393 | |
8d0deca8 VS |
2394 | tiles = *x / tile_width; |
2395 | *x %= tile_width; | |
bc752862 | 2396 | |
29cf9491 VS |
2397 | offset = (tile_rows * pitch_tiles + tiles) * tile_size; |
2398 | offset_aligned = offset & ~alignment; | |
bc752862 | 2399 | |
29cf9491 VS |
2400 | intel_adjust_tile_offset(x, y, tile_width, tile_height, |
2401 | tile_size, pitch_tiles, | |
2402 | offset, offset_aligned); | |
2403 | } else { | |
bc752862 | 2404 | offset = *y * pitch + *x * cpp; |
29cf9491 VS |
2405 | offset_aligned = offset & ~alignment; |
2406 | ||
4e9a86b6 VS |
2407 | *y = (offset & alignment) / pitch; |
2408 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
bc752862 | 2409 | } |
29cf9491 VS |
2410 | |
2411 | return offset_aligned; | |
c2c75131 DV |
2412 | } |
2413 | ||
b35d63fa | 2414 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2415 | { |
2416 | switch (format) { | |
2417 | case DISPPLANE_8BPP: | |
2418 | return DRM_FORMAT_C8; | |
2419 | case DISPPLANE_BGRX555: | |
2420 | return DRM_FORMAT_XRGB1555; | |
2421 | case DISPPLANE_BGRX565: | |
2422 | return DRM_FORMAT_RGB565; | |
2423 | default: | |
2424 | case DISPPLANE_BGRX888: | |
2425 | return DRM_FORMAT_XRGB8888; | |
2426 | case DISPPLANE_RGBX888: | |
2427 | return DRM_FORMAT_XBGR8888; | |
2428 | case DISPPLANE_BGRX101010: | |
2429 | return DRM_FORMAT_XRGB2101010; | |
2430 | case DISPPLANE_RGBX101010: | |
2431 | return DRM_FORMAT_XBGR2101010; | |
2432 | } | |
2433 | } | |
2434 | ||
bc8d7dff DL |
2435 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2436 | { | |
2437 | switch (format) { | |
2438 | case PLANE_CTL_FORMAT_RGB_565: | |
2439 | return DRM_FORMAT_RGB565; | |
2440 | default: | |
2441 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2442 | if (rgb_order) { | |
2443 | if (alpha) | |
2444 | return DRM_FORMAT_ABGR8888; | |
2445 | else | |
2446 | return DRM_FORMAT_XBGR8888; | |
2447 | } else { | |
2448 | if (alpha) | |
2449 | return DRM_FORMAT_ARGB8888; | |
2450 | else | |
2451 | return DRM_FORMAT_XRGB8888; | |
2452 | } | |
2453 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2454 | if (rgb_order) | |
2455 | return DRM_FORMAT_XBGR2101010; | |
2456 | else | |
2457 | return DRM_FORMAT_XRGB2101010; | |
2458 | } | |
2459 | } | |
2460 | ||
5724dbd1 | 2461 | static bool |
f6936e29 DV |
2462 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2463 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2464 | { |
2465 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2466 | struct drm_i915_private *dev_priv = to_i915(dev); |
72e96d64 | 2467 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
46f297fb JB |
2468 | struct drm_i915_gem_object *obj = NULL; |
2469 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2470 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2471 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2472 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2473 | PAGE_SIZE); | |
2474 | ||
2475 | size_aligned -= base_aligned; | |
46f297fb | 2476 | |
ff2652ea CW |
2477 | if (plane_config->size == 0) |
2478 | return false; | |
2479 | ||
3badb49f PZ |
2480 | /* If the FB is too big, just don't use it since fbdev is not very |
2481 | * important and we should probably use that space with FBC or other | |
2482 | * features. */ | |
72e96d64 | 2483 | if (size_aligned * 2 > ggtt->stolen_usable_size) |
3badb49f PZ |
2484 | return false; |
2485 | ||
12c83d99 TU |
2486 | mutex_lock(&dev->struct_mutex); |
2487 | ||
f37b5c2b DV |
2488 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2489 | base_aligned, | |
2490 | base_aligned, | |
2491 | size_aligned); | |
12c83d99 TU |
2492 | if (!obj) { |
2493 | mutex_unlock(&dev->struct_mutex); | |
484b41dd | 2494 | return false; |
12c83d99 | 2495 | } |
46f297fb | 2496 | |
49af449b DL |
2497 | obj->tiling_mode = plane_config->tiling; |
2498 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2499 | obj->stride = fb->pitches[0]; |
46f297fb | 2500 | |
6bf129df DL |
2501 | mode_cmd.pixel_format = fb->pixel_format; |
2502 | mode_cmd.width = fb->width; | |
2503 | mode_cmd.height = fb->height; | |
2504 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2505 | mode_cmd.modifier[0] = fb->modifier[0]; |
2506 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb | 2507 | |
6bf129df | 2508 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2509 | &mode_cmd, obj)) { |
46f297fb JB |
2510 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2511 | goto out_unref_obj; | |
2512 | } | |
12c83d99 | 2513 | |
46f297fb | 2514 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2515 | |
f6936e29 | 2516 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2517 | return true; |
46f297fb JB |
2518 | |
2519 | out_unref_obj: | |
2520 | drm_gem_object_unreference(&obj->base); | |
2521 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2522 | return false; |
2523 | } | |
2524 | ||
afd65eb4 MR |
2525 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2526 | static void | |
2527 | update_state_fb(struct drm_plane *plane) | |
2528 | { | |
2529 | if (plane->fb == plane->state->fb) | |
2530 | return; | |
2531 | ||
2532 | if (plane->state->fb) | |
2533 | drm_framebuffer_unreference(plane->state->fb); | |
2534 | plane->state->fb = plane->fb; | |
2535 | if (plane->state->fb) | |
2536 | drm_framebuffer_reference(plane->state->fb); | |
2537 | } | |
2538 | ||
5724dbd1 | 2539 | static void |
f6936e29 DV |
2540 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2541 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2542 | { |
2543 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2544 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2545 | struct drm_crtc *c; |
2546 | struct intel_crtc *i; | |
2ff8fde1 | 2547 | struct drm_i915_gem_object *obj; |
88595ac9 | 2548 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2549 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2550 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2551 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2552 | struct intel_plane_state *intel_state = |
2553 | to_intel_plane_state(plane_state); | |
88595ac9 | 2554 | struct drm_framebuffer *fb; |
484b41dd | 2555 | |
2d14030b | 2556 | if (!plane_config->fb) |
484b41dd JB |
2557 | return; |
2558 | ||
f6936e29 | 2559 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2560 | fb = &plane_config->fb->base; |
2561 | goto valid_fb; | |
f55548b5 | 2562 | } |
484b41dd | 2563 | |
2d14030b | 2564 | kfree(plane_config->fb); |
484b41dd JB |
2565 | |
2566 | /* | |
2567 | * Failed to alloc the obj, check to see if we should share | |
2568 | * an fb with another CRTC instead | |
2569 | */ | |
70e1e0ec | 2570 | for_each_crtc(dev, c) { |
484b41dd JB |
2571 | i = to_intel_crtc(c); |
2572 | ||
2573 | if (c == &intel_crtc->base) | |
2574 | continue; | |
2575 | ||
2ff8fde1 MR |
2576 | if (!i->active) |
2577 | continue; | |
2578 | ||
88595ac9 DV |
2579 | fb = c->primary->fb; |
2580 | if (!fb) | |
484b41dd JB |
2581 | continue; |
2582 | ||
88595ac9 | 2583 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2584 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2585 | drm_framebuffer_reference(fb); |
2586 | goto valid_fb; | |
484b41dd JB |
2587 | } |
2588 | } | |
88595ac9 | 2589 | |
200757f5 MR |
2590 | /* |
2591 | * We've failed to reconstruct the BIOS FB. Current display state | |
2592 | * indicates that the primary plane is visible, but has a NULL FB, | |
2593 | * which will lead to problems later if we don't fix it up. The | |
2594 | * simplest solution is to just disable the primary plane now and | |
2595 | * pretend the BIOS never had it enabled. | |
2596 | */ | |
2597 | to_intel_plane_state(plane_state)->visible = false; | |
2598 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); | |
2622a081 | 2599 | intel_pre_disable_primary_noatomic(&intel_crtc->base); |
200757f5 MR |
2600 | intel_plane->disable_plane(primary, &intel_crtc->base); |
2601 | ||
88595ac9 DV |
2602 | return; |
2603 | ||
2604 | valid_fb: | |
f44e2659 VS |
2605 | plane_state->src_x = 0; |
2606 | plane_state->src_y = 0; | |
be5651f2 ML |
2607 | plane_state->src_w = fb->width << 16; |
2608 | plane_state->src_h = fb->height << 16; | |
2609 | ||
f44e2659 VS |
2610 | plane_state->crtc_x = 0; |
2611 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2612 | plane_state->crtc_w = fb->width; |
2613 | plane_state->crtc_h = fb->height; | |
2614 | ||
0a8d8a86 MR |
2615 | intel_state->src.x1 = plane_state->src_x; |
2616 | intel_state->src.y1 = plane_state->src_y; | |
2617 | intel_state->src.x2 = plane_state->src_x + plane_state->src_w; | |
2618 | intel_state->src.y2 = plane_state->src_y + plane_state->src_h; | |
2619 | intel_state->dst.x1 = plane_state->crtc_x; | |
2620 | intel_state->dst.y1 = plane_state->crtc_y; | |
2621 | intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w; | |
2622 | intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h; | |
2623 | ||
88595ac9 DV |
2624 | obj = intel_fb_obj(fb); |
2625 | if (obj->tiling_mode != I915_TILING_NONE) | |
2626 | dev_priv->preserve_bios_swizzle = true; | |
2627 | ||
be5651f2 ML |
2628 | drm_framebuffer_reference(fb); |
2629 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2630 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2631 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
a9ff8714 | 2632 | obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit; |
46f297fb JB |
2633 | } |
2634 | ||
a8d201af ML |
2635 | static void i9xx_update_primary_plane(struct drm_plane *primary, |
2636 | const struct intel_crtc_state *crtc_state, | |
2637 | const struct intel_plane_state *plane_state) | |
81255565 | 2638 | { |
a8d201af | 2639 | struct drm_device *dev = primary->dev; |
81255565 | 2640 | struct drm_i915_private *dev_priv = dev->dev_private; |
a8d201af ML |
2641 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2642 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2643 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
81255565 | 2644 | int plane = intel_crtc->plane; |
54ea9da8 | 2645 | u32 linear_offset; |
81255565 | 2646 | u32 dspcntr; |
f0f59a00 | 2647 | i915_reg_t reg = DSPCNTR(plane); |
8d0deca8 | 2648 | unsigned int rotation = plane_state->base.rotation; |
ac484963 | 2649 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
54ea9da8 VS |
2650 | int x = plane_state->src.x1 >> 16; |
2651 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2652 | |
f45651ba VS |
2653 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2654 | ||
fdd508a6 | 2655 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2656 | |
2657 | if (INTEL_INFO(dev)->gen < 4) { | |
2658 | if (intel_crtc->pipe == PIPE_B) | |
2659 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2660 | ||
2661 | /* pipesrc and dspsize control the size that is scaled from, | |
2662 | * which should always be the user's requested size. | |
2663 | */ | |
2664 | I915_WRITE(DSPSIZE(plane), | |
a8d201af ML |
2665 | ((crtc_state->pipe_src_h - 1) << 16) | |
2666 | (crtc_state->pipe_src_w - 1)); | |
f45651ba | 2667 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2668 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2669 | I915_WRITE(PRIMSIZE(plane), | |
a8d201af ML |
2670 | ((crtc_state->pipe_src_h - 1) << 16) | |
2671 | (crtc_state->pipe_src_w - 1)); | |
c14b0485 VS |
2672 | I915_WRITE(PRIMPOS(plane), 0); |
2673 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2674 | } |
81255565 | 2675 | |
57779d06 VS |
2676 | switch (fb->pixel_format) { |
2677 | case DRM_FORMAT_C8: | |
81255565 JB |
2678 | dspcntr |= DISPPLANE_8BPP; |
2679 | break; | |
57779d06 | 2680 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2681 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2682 | break; |
57779d06 VS |
2683 | case DRM_FORMAT_RGB565: |
2684 | dspcntr |= DISPPLANE_BGRX565; | |
2685 | break; | |
2686 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2687 | dspcntr |= DISPPLANE_BGRX888; |
2688 | break; | |
2689 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2690 | dspcntr |= DISPPLANE_RGBX888; |
2691 | break; | |
2692 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2693 | dspcntr |= DISPPLANE_BGRX101010; |
2694 | break; | |
2695 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2696 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
2697 | break; |
2698 | default: | |
baba133a | 2699 | BUG(); |
81255565 | 2700 | } |
57779d06 | 2701 | |
f45651ba VS |
2702 | if (INTEL_INFO(dev)->gen >= 4 && |
2703 | obj->tiling_mode != I915_TILING_NONE) | |
2704 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2705 | |
de1aa629 VS |
2706 | if (IS_G4X(dev)) |
2707 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2708 | ||
ac484963 | 2709 | linear_offset = y * fb->pitches[0] + x * cpp; |
81255565 | 2710 | |
c2c75131 DV |
2711 | if (INTEL_INFO(dev)->gen >= 4) { |
2712 | intel_crtc->dspaddr_offset = | |
4f2d9934 | 2713 | intel_compute_tile_offset(&x, &y, fb, 0, |
8d0deca8 | 2714 | fb->pitches[0], rotation); |
c2c75131 DV |
2715 | linear_offset -= intel_crtc->dspaddr_offset; |
2716 | } else { | |
e506a0c6 | 2717 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2718 | } |
e506a0c6 | 2719 | |
8d0deca8 | 2720 | if (rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2721 | dspcntr |= DISPPLANE_ROTATE_180; |
2722 | ||
a8d201af ML |
2723 | x += (crtc_state->pipe_src_w - 1); |
2724 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2725 | |
2726 | /* Finding the last pixel of the last line of the display | |
2727 | data and adding to linear_offset*/ | |
2728 | linear_offset += | |
a8d201af | 2729 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2730 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2731 | } |
2732 | ||
2db3366b PZ |
2733 | intel_crtc->adjusted_x = x; |
2734 | intel_crtc->adjusted_y = y; | |
2735 | ||
48404c1e SJ |
2736 | I915_WRITE(reg, dspcntr); |
2737 | ||
01f2c773 | 2738 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2739 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2740 | I915_WRITE(DSPSURF(plane), |
2741 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2742 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2743 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2744 | } else |
f343c5f6 | 2745 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2746 | POSTING_READ(reg); |
17638cd6 JB |
2747 | } |
2748 | ||
a8d201af ML |
2749 | static void i9xx_disable_primary_plane(struct drm_plane *primary, |
2750 | struct drm_crtc *crtc) | |
17638cd6 JB |
2751 | { |
2752 | struct drm_device *dev = crtc->dev; | |
2753 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2754 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
17638cd6 | 2755 | int plane = intel_crtc->plane; |
f45651ba | 2756 | |
a8d201af ML |
2757 | I915_WRITE(DSPCNTR(plane), 0); |
2758 | if (INTEL_INFO(dev_priv)->gen >= 4) | |
fdd508a6 | 2759 | I915_WRITE(DSPSURF(plane), 0); |
a8d201af ML |
2760 | else |
2761 | I915_WRITE(DSPADDR(plane), 0); | |
2762 | POSTING_READ(DSPCNTR(plane)); | |
2763 | } | |
c9ba6fad | 2764 | |
a8d201af ML |
2765 | static void ironlake_update_primary_plane(struct drm_plane *primary, |
2766 | const struct intel_crtc_state *crtc_state, | |
2767 | const struct intel_plane_state *plane_state) | |
2768 | { | |
2769 | struct drm_device *dev = primary->dev; | |
2770 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2771 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
2772 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2773 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
2774 | int plane = intel_crtc->plane; | |
54ea9da8 | 2775 | u32 linear_offset; |
a8d201af ML |
2776 | u32 dspcntr; |
2777 | i915_reg_t reg = DSPCNTR(plane); | |
8d0deca8 | 2778 | unsigned int rotation = plane_state->base.rotation; |
ac484963 | 2779 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
a8d201af ML |
2780 | int x = plane_state->src.x1 >> 16; |
2781 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2782 | |
f45651ba | 2783 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
fdd508a6 | 2784 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2785 | |
2786 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2787 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2788 | |
57779d06 VS |
2789 | switch (fb->pixel_format) { |
2790 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2791 | dspcntr |= DISPPLANE_8BPP; |
2792 | break; | |
57779d06 VS |
2793 | case DRM_FORMAT_RGB565: |
2794 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2795 | break; |
57779d06 | 2796 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
2797 | dspcntr |= DISPPLANE_BGRX888; |
2798 | break; | |
2799 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2800 | dspcntr |= DISPPLANE_RGBX888; |
2801 | break; | |
2802 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2803 | dspcntr |= DISPPLANE_BGRX101010; |
2804 | break; | |
2805 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2806 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
2807 | break; |
2808 | default: | |
baba133a | 2809 | BUG(); |
17638cd6 JB |
2810 | } |
2811 | ||
2812 | if (obj->tiling_mode != I915_TILING_NONE) | |
2813 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2814 | |
f45651ba | 2815 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2816 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2817 | |
ac484963 | 2818 | linear_offset = y * fb->pitches[0] + x * cpp; |
c2c75131 | 2819 | intel_crtc->dspaddr_offset = |
4f2d9934 | 2820 | intel_compute_tile_offset(&x, &y, fb, 0, |
8d0deca8 | 2821 | fb->pitches[0], rotation); |
c2c75131 | 2822 | linear_offset -= intel_crtc->dspaddr_offset; |
8d0deca8 | 2823 | if (rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2824 | dspcntr |= DISPPLANE_ROTATE_180; |
2825 | ||
2826 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
a8d201af ML |
2827 | x += (crtc_state->pipe_src_w - 1); |
2828 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2829 | |
2830 | /* Finding the last pixel of the last line of the display | |
2831 | data and adding to linear_offset*/ | |
2832 | linear_offset += | |
a8d201af | 2833 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2834 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2835 | } |
2836 | } | |
2837 | ||
2db3366b PZ |
2838 | intel_crtc->adjusted_x = x; |
2839 | intel_crtc->adjusted_y = y; | |
2840 | ||
48404c1e | 2841 | I915_WRITE(reg, dspcntr); |
17638cd6 | 2842 | |
01f2c773 | 2843 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2844 | I915_WRITE(DSPSURF(plane), |
2845 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2846 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2847 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2848 | } else { | |
2849 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2850 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2851 | } | |
17638cd6 | 2852 | POSTING_READ(reg); |
17638cd6 JB |
2853 | } |
2854 | ||
7b49f948 VS |
2855 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
2856 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 2857 | { |
7b49f948 | 2858 | if (fb_modifier == DRM_FORMAT_MOD_NONE) { |
b321803d | 2859 | return 64; |
7b49f948 VS |
2860 | } else { |
2861 | int cpp = drm_format_plane_cpp(pixel_format, 0); | |
2862 | ||
27ba3910 | 2863 | return intel_tile_width_bytes(dev_priv, fb_modifier, cpp); |
b321803d DL |
2864 | } |
2865 | } | |
2866 | ||
44eb0cb9 MK |
2867 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, |
2868 | struct drm_i915_gem_object *obj, | |
2869 | unsigned int plane) | |
121920fa | 2870 | { |
ce7f1728 | 2871 | struct i915_ggtt_view view; |
dedf278c | 2872 | struct i915_vma *vma; |
44eb0cb9 | 2873 | u64 offset; |
121920fa | 2874 | |
e7941294 | 2875 | intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb, |
3465c580 | 2876 | intel_plane->base.state->rotation); |
121920fa | 2877 | |
ce7f1728 | 2878 | vma = i915_gem_obj_to_ggtt_view(obj, &view); |
dedf278c | 2879 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", |
ce7f1728 | 2880 | view.type)) |
dedf278c TU |
2881 | return -1; |
2882 | ||
44eb0cb9 | 2883 | offset = vma->node.start; |
dedf278c TU |
2884 | |
2885 | if (plane == 1) { | |
7723f47d | 2886 | offset += vma->ggtt_view.params.rotated.uv_start_page * |
dedf278c TU |
2887 | PAGE_SIZE; |
2888 | } | |
2889 | ||
44eb0cb9 MK |
2890 | WARN_ON(upper_32_bits(offset)); |
2891 | ||
2892 | return lower_32_bits(offset); | |
121920fa TU |
2893 | } |
2894 | ||
e435d6e5 ML |
2895 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
2896 | { | |
2897 | struct drm_device *dev = intel_crtc->base.dev; | |
2898 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2899 | ||
2900 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
2901 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
2902 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
2903 | } |
2904 | ||
a1b2278e CK |
2905 | /* |
2906 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2907 | */ | |
0583236e | 2908 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 2909 | { |
a1b2278e CK |
2910 | struct intel_crtc_scaler_state *scaler_state; |
2911 | int i; | |
2912 | ||
a1b2278e CK |
2913 | scaler_state = &intel_crtc->config->scaler_state; |
2914 | ||
2915 | /* loop through and disable scalers that aren't in use */ | |
2916 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
2917 | if (!scaler_state->scalers[i].in_use) |
2918 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
2919 | } |
2920 | } | |
2921 | ||
6156a456 | 2922 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 2923 | { |
6156a456 | 2924 | switch (pixel_format) { |
d161cf7a | 2925 | case DRM_FORMAT_C8: |
c34ce3d1 | 2926 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 2927 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 2928 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 2929 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 2930 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 2931 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 2932 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
2933 | /* |
2934 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
2935 | * to be already pre-multiplied. We need to add a knob (or a different | |
2936 | * DRM_FORMAT) for user-space to configure that. | |
2937 | */ | |
f75fb42a | 2938 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 2939 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 2940 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 2941 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 2942 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 2943 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 2944 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 2945 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 2946 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 2947 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 2948 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 2949 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 2950 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 2951 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 2952 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 2953 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 2954 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 2955 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 2956 | default: |
4249eeef | 2957 | MISSING_CASE(pixel_format); |
70d21f0e | 2958 | } |
8cfcba41 | 2959 | |
c34ce3d1 | 2960 | return 0; |
6156a456 | 2961 | } |
70d21f0e | 2962 | |
6156a456 CK |
2963 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
2964 | { | |
6156a456 | 2965 | switch (fb_modifier) { |
30af77c4 | 2966 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 2967 | break; |
30af77c4 | 2968 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 2969 | return PLANE_CTL_TILED_X; |
b321803d | 2970 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 2971 | return PLANE_CTL_TILED_Y; |
b321803d | 2972 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 2973 | return PLANE_CTL_TILED_YF; |
70d21f0e | 2974 | default: |
6156a456 | 2975 | MISSING_CASE(fb_modifier); |
70d21f0e | 2976 | } |
8cfcba41 | 2977 | |
c34ce3d1 | 2978 | return 0; |
6156a456 | 2979 | } |
70d21f0e | 2980 | |
6156a456 CK |
2981 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
2982 | { | |
3b7a5119 | 2983 | switch (rotation) { |
6156a456 CK |
2984 | case BIT(DRM_ROTATE_0): |
2985 | break; | |
1e8df167 SJ |
2986 | /* |
2987 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
2988 | * while i915 HW rotation is clockwise, thats why this swapping. | |
2989 | */ | |
3b7a5119 | 2990 | case BIT(DRM_ROTATE_90): |
1e8df167 | 2991 | return PLANE_CTL_ROTATE_270; |
3b7a5119 | 2992 | case BIT(DRM_ROTATE_180): |
c34ce3d1 | 2993 | return PLANE_CTL_ROTATE_180; |
3b7a5119 | 2994 | case BIT(DRM_ROTATE_270): |
1e8df167 | 2995 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
2996 | default: |
2997 | MISSING_CASE(rotation); | |
2998 | } | |
2999 | ||
c34ce3d1 | 3000 | return 0; |
6156a456 CK |
3001 | } |
3002 | ||
a8d201af ML |
3003 | static void skylake_update_primary_plane(struct drm_plane *plane, |
3004 | const struct intel_crtc_state *crtc_state, | |
3005 | const struct intel_plane_state *plane_state) | |
6156a456 | 3006 | { |
a8d201af | 3007 | struct drm_device *dev = plane->dev; |
6156a456 | 3008 | struct drm_i915_private *dev_priv = dev->dev_private; |
a8d201af ML |
3009 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3010 | struct drm_framebuffer *fb = plane_state->base.fb; | |
3011 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
6156a456 CK |
3012 | int pipe = intel_crtc->pipe; |
3013 | u32 plane_ctl, stride_div, stride; | |
3014 | u32 tile_height, plane_offset, plane_size; | |
a8d201af | 3015 | unsigned int rotation = plane_state->base.rotation; |
6156a456 | 3016 | int x_offset, y_offset; |
44eb0cb9 | 3017 | u32 surf_addr; |
a8d201af ML |
3018 | int scaler_id = plane_state->scaler_id; |
3019 | int src_x = plane_state->src.x1 >> 16; | |
3020 | int src_y = plane_state->src.y1 >> 16; | |
3021 | int src_w = drm_rect_width(&plane_state->src) >> 16; | |
3022 | int src_h = drm_rect_height(&plane_state->src) >> 16; | |
3023 | int dst_x = plane_state->dst.x1; | |
3024 | int dst_y = plane_state->dst.y1; | |
3025 | int dst_w = drm_rect_width(&plane_state->dst); | |
3026 | int dst_h = drm_rect_height(&plane_state->dst); | |
70d21f0e | 3027 | |
6156a456 CK |
3028 | plane_ctl = PLANE_CTL_ENABLE | |
3029 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3030 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3031 | ||
3032 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3033 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3034 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
6156a456 CK |
3035 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
3036 | ||
7b49f948 | 3037 | stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
b321803d | 3038 | fb->pixel_format); |
dedf278c | 3039 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); |
3b7a5119 | 3040 | |
a42e5a23 PZ |
3041 | WARN_ON(drm_rect_width(&plane_state->src) == 0); |
3042 | ||
3b7a5119 | 3043 | if (intel_rotation_90_or_270(rotation)) { |
832be82f VS |
3044 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
3045 | ||
3b7a5119 | 3046 | /* stride = Surface height in tiles */ |
832be82f | 3047 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp); |
3b7a5119 | 3048 | stride = DIV_ROUND_UP(fb->height, tile_height); |
a8d201af ML |
3049 | x_offset = stride * tile_height - src_y - src_h; |
3050 | y_offset = src_x; | |
6156a456 | 3051 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3052 | } else { |
3053 | stride = fb->pitches[0] / stride_div; | |
a8d201af ML |
3054 | x_offset = src_x; |
3055 | y_offset = src_y; | |
6156a456 | 3056 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3057 | } |
3058 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3059 | |
2db3366b PZ |
3060 | intel_crtc->adjusted_x = x_offset; |
3061 | intel_crtc->adjusted_y = y_offset; | |
3062 | ||
70d21f0e | 3063 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3064 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3065 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3066 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3067 | |
3068 | if (scaler_id >= 0) { | |
3069 | uint32_t ps_ctrl = 0; | |
3070 | ||
3071 | WARN_ON(!dst_w || !dst_h); | |
3072 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3073 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3074 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3075 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3076 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3077 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3078 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3079 | } else { | |
3080 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3081 | } | |
3082 | ||
121920fa | 3083 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3084 | |
3085 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3086 | } | |
3087 | ||
a8d201af ML |
3088 | static void skylake_disable_primary_plane(struct drm_plane *primary, |
3089 | struct drm_crtc *crtc) | |
17638cd6 JB |
3090 | { |
3091 | struct drm_device *dev = crtc->dev; | |
3092 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a8d201af | 3093 | int pipe = to_intel_crtc(crtc)->pipe; |
17638cd6 | 3094 | |
a8d201af ML |
3095 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3096 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3097 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3098 | } | |
29b9bde6 | 3099 | |
a8d201af ML |
3100 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3101 | static int | |
3102 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3103 | int x, int y, enum mode_set_atomic state) | |
3104 | { | |
3105 | /* Support for kgdboc is disabled, this needs a major rework. */ | |
3106 | DRM_ERROR("legacy panic handler not supported any more.\n"); | |
3107 | ||
3108 | return -ENODEV; | |
81255565 JB |
3109 | } |
3110 | ||
91d14251 | 3111 | static void intel_complete_page_flips(struct drm_i915_private *dev_priv) |
96a02917 | 3112 | { |
ef58319d | 3113 | struct intel_crtc *crtc; |
96a02917 | 3114 | |
5251f04e | 3115 | for_each_intel_crtc(dev_priv->dev, crtc) |
ef58319d | 3116 | intel_finish_page_flip(dev_priv, crtc->pipe); |
7514747d VS |
3117 | } |
3118 | ||
3119 | static void intel_update_primary_planes(struct drm_device *dev) | |
3120 | { | |
7514747d | 3121 | struct drm_crtc *crtc; |
96a02917 | 3122 | |
70e1e0ec | 3123 | for_each_crtc(dev, crtc) { |
11c22da6 ML |
3124 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
3125 | struct intel_plane_state *plane_state; | |
96a02917 | 3126 | |
11c22da6 | 3127 | drm_modeset_lock_crtc(crtc, &plane->base); |
11c22da6 ML |
3128 | plane_state = to_intel_plane_state(plane->base.state); |
3129 | ||
a8d201af ML |
3130 | if (plane_state->visible) |
3131 | plane->update_plane(&plane->base, | |
3132 | to_intel_crtc_state(crtc->state), | |
3133 | plane_state); | |
11c22da6 ML |
3134 | |
3135 | drm_modeset_unlock_crtc(crtc); | |
96a02917 VS |
3136 | } |
3137 | } | |
3138 | ||
c033666a | 3139 | void intel_prepare_reset(struct drm_i915_private *dev_priv) |
7514747d VS |
3140 | { |
3141 | /* no reset support for gen2 */ | |
c033666a | 3142 | if (IS_GEN2(dev_priv)) |
7514747d VS |
3143 | return; |
3144 | ||
3145 | /* reset doesn't touch the display */ | |
c033666a | 3146 | if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) |
7514747d VS |
3147 | return; |
3148 | ||
c033666a | 3149 | drm_modeset_lock_all(dev_priv->dev); |
f98ce92f VS |
3150 | /* |
3151 | * Disabling the crtcs gracefully seems nicer. Also the | |
3152 | * g33 docs say we should at least disable all the planes. | |
3153 | */ | |
c033666a | 3154 | intel_display_suspend(dev_priv->dev); |
7514747d VS |
3155 | } |
3156 | ||
c033666a | 3157 | void intel_finish_reset(struct drm_i915_private *dev_priv) |
7514747d | 3158 | { |
7514747d VS |
3159 | /* |
3160 | * Flips in the rings will be nuked by the reset, | |
3161 | * so complete all pending flips so that user space | |
3162 | * will get its events and not get stuck. | |
3163 | */ | |
91d14251 | 3164 | intel_complete_page_flips(dev_priv); |
7514747d VS |
3165 | |
3166 | /* no reset support for gen2 */ | |
c033666a | 3167 | if (IS_GEN2(dev_priv)) |
7514747d VS |
3168 | return; |
3169 | ||
3170 | /* reset doesn't touch the display */ | |
c033666a | 3171 | if (INTEL_GEN(dev_priv) >= 5 || IS_G4X(dev_priv)) { |
7514747d VS |
3172 | /* |
3173 | * Flips in the rings have been nuked by the reset, | |
3174 | * so update the base address of all primary | |
3175 | * planes to the the last fb to make sure we're | |
3176 | * showing the correct fb after a reset. | |
11c22da6 ML |
3177 | * |
3178 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3179 | * CS-based flips (which might get lost in gpu resets) any more. | |
7514747d | 3180 | */ |
c033666a | 3181 | intel_update_primary_planes(dev_priv->dev); |
7514747d VS |
3182 | return; |
3183 | } | |
3184 | ||
3185 | /* | |
3186 | * The display has been reset as well, | |
3187 | * so need a full re-initialization. | |
3188 | */ | |
3189 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3190 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3191 | ||
c033666a | 3192 | intel_modeset_init_hw(dev_priv->dev); |
7514747d VS |
3193 | |
3194 | spin_lock_irq(&dev_priv->irq_lock); | |
3195 | if (dev_priv->display.hpd_irq_setup) | |
91d14251 | 3196 | dev_priv->display.hpd_irq_setup(dev_priv); |
7514747d VS |
3197 | spin_unlock_irq(&dev_priv->irq_lock); |
3198 | ||
c033666a | 3199 | intel_display_resume(dev_priv->dev); |
7514747d VS |
3200 | |
3201 | intel_hpd_init(dev_priv); | |
3202 | ||
c033666a | 3203 | drm_modeset_unlock_all(dev_priv->dev); |
7514747d VS |
3204 | } |
3205 | ||
7d5e3799 CW |
3206 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3207 | { | |
3208 | struct drm_device *dev = crtc->dev; | |
7d5e3799 | 3209 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
c19ae989 | 3210 | unsigned reset_counter; |
7d5e3799 CW |
3211 | bool pending; |
3212 | ||
7f1847eb CW |
3213 | reset_counter = i915_reset_counter(&to_i915(dev)->gpu_error); |
3214 | if (intel_crtc->reset_counter != reset_counter) | |
7d5e3799 CW |
3215 | return false; |
3216 | ||
5e2d7afc | 3217 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3218 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3219 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3220 | |
3221 | return pending; | |
3222 | } | |
3223 | ||
bfd16b2a ML |
3224 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3225 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 GP |
3226 | { |
3227 | struct drm_device *dev = crtc->base.dev; | |
3228 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bfd16b2a ML |
3229 | struct intel_crtc_state *pipe_config = |
3230 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3231 | |
bfd16b2a ML |
3232 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3233 | crtc->base.mode = crtc->base.state->mode; | |
3234 | ||
3235 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3236 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3237 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 GP |
3238 | |
3239 | /* | |
3240 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3241 | * that in compute_mode_changes we check the native mode (not the pfit | |
3242 | * mode) to see if we can flip rather than do a full mode set. In the | |
3243 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3244 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3245 | * sized surface. | |
e30e8f75 GP |
3246 | */ |
3247 | ||
e30e8f75 | 3248 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3249 | ((pipe_config->pipe_src_w - 1) << 16) | |
3250 | (pipe_config->pipe_src_h - 1)); | |
3251 | ||
3252 | /* on skylake this is done by detaching scalers */ | |
3253 | if (INTEL_INFO(dev)->gen >= 9) { | |
3254 | skl_detach_scalers(crtc); | |
3255 | ||
3256 | if (pipe_config->pch_pfit.enabled) | |
3257 | skylake_pfit_enable(crtc); | |
3258 | } else if (HAS_PCH_SPLIT(dev)) { | |
3259 | if (pipe_config->pch_pfit.enabled) | |
3260 | ironlake_pfit_enable(crtc); | |
3261 | else if (old_crtc_state->pch_pfit.enabled) | |
3262 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3263 | } |
e30e8f75 GP |
3264 | } |
3265 | ||
5e84e1a4 ZW |
3266 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3267 | { | |
3268 | struct drm_device *dev = crtc->dev; | |
3269 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3270 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3271 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3272 | i915_reg_t reg; |
3273 | u32 temp; | |
5e84e1a4 ZW |
3274 | |
3275 | /* enable normal train */ | |
3276 | reg = FDI_TX_CTL(pipe); | |
3277 | temp = I915_READ(reg); | |
61e499bf | 3278 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3279 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3280 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3281 | } else { |
3282 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3283 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3284 | } |
5e84e1a4 ZW |
3285 | I915_WRITE(reg, temp); |
3286 | ||
3287 | reg = FDI_RX_CTL(pipe); | |
3288 | temp = I915_READ(reg); | |
3289 | if (HAS_PCH_CPT(dev)) { | |
3290 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3291 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3292 | } else { | |
3293 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3294 | temp |= FDI_LINK_TRAIN_NONE; | |
3295 | } | |
3296 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3297 | ||
3298 | /* wait one idle pattern time */ | |
3299 | POSTING_READ(reg); | |
3300 | udelay(1000); | |
357555c0 JB |
3301 | |
3302 | /* IVB wants error correction enabled */ | |
3303 | if (IS_IVYBRIDGE(dev)) | |
3304 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3305 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3306 | } |
3307 | ||
8db9d77b ZW |
3308 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3309 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3310 | { | |
3311 | struct drm_device *dev = crtc->dev; | |
3312 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3313 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3314 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3315 | i915_reg_t reg; |
3316 | u32 temp, tries; | |
8db9d77b | 3317 | |
1c8562f6 | 3318 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3319 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3320 | |
e1a44743 AJ |
3321 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3322 | for train result */ | |
5eddb70b CW |
3323 | reg = FDI_RX_IMR(pipe); |
3324 | temp = I915_READ(reg); | |
e1a44743 AJ |
3325 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3326 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3327 | I915_WRITE(reg, temp); |
3328 | I915_READ(reg); | |
e1a44743 AJ |
3329 | udelay(150); |
3330 | ||
8db9d77b | 3331 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3332 | reg = FDI_TX_CTL(pipe); |
3333 | temp = I915_READ(reg); | |
627eb5a3 | 3334 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3335 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3336 | temp &= ~FDI_LINK_TRAIN_NONE; |
3337 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3338 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3339 | |
5eddb70b CW |
3340 | reg = FDI_RX_CTL(pipe); |
3341 | temp = I915_READ(reg); | |
8db9d77b ZW |
3342 | temp &= ~FDI_LINK_TRAIN_NONE; |
3343 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3344 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3345 | ||
3346 | POSTING_READ(reg); | |
8db9d77b ZW |
3347 | udelay(150); |
3348 | ||
5b2adf89 | 3349 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3350 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3351 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3352 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3353 | |
5eddb70b | 3354 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3355 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3356 | temp = I915_READ(reg); |
8db9d77b ZW |
3357 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3358 | ||
3359 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3360 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3361 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3362 | break; |
3363 | } | |
8db9d77b | 3364 | } |
e1a44743 | 3365 | if (tries == 5) |
5eddb70b | 3366 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3367 | |
3368 | /* Train 2 */ | |
5eddb70b CW |
3369 | reg = FDI_TX_CTL(pipe); |
3370 | temp = I915_READ(reg); | |
8db9d77b ZW |
3371 | temp &= ~FDI_LINK_TRAIN_NONE; |
3372 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3373 | I915_WRITE(reg, temp); |
8db9d77b | 3374 | |
5eddb70b CW |
3375 | reg = FDI_RX_CTL(pipe); |
3376 | temp = I915_READ(reg); | |
8db9d77b ZW |
3377 | temp &= ~FDI_LINK_TRAIN_NONE; |
3378 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3379 | I915_WRITE(reg, temp); |
8db9d77b | 3380 | |
5eddb70b CW |
3381 | POSTING_READ(reg); |
3382 | udelay(150); | |
8db9d77b | 3383 | |
5eddb70b | 3384 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3385 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3386 | temp = I915_READ(reg); |
8db9d77b ZW |
3387 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3388 | ||
3389 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3390 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3391 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3392 | break; | |
3393 | } | |
8db9d77b | 3394 | } |
e1a44743 | 3395 | if (tries == 5) |
5eddb70b | 3396 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3397 | |
3398 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3399 | |
8db9d77b ZW |
3400 | } |
3401 | ||
0206e353 | 3402 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3403 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3404 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3405 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3406 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3407 | }; | |
3408 | ||
3409 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3410 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3411 | { | |
3412 | struct drm_device *dev = crtc->dev; | |
3413 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3414 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3415 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3416 | i915_reg_t reg; |
3417 | u32 temp, i, retry; | |
8db9d77b | 3418 | |
e1a44743 AJ |
3419 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3420 | for train result */ | |
5eddb70b CW |
3421 | reg = FDI_RX_IMR(pipe); |
3422 | temp = I915_READ(reg); | |
e1a44743 AJ |
3423 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3424 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3425 | I915_WRITE(reg, temp); |
3426 | ||
3427 | POSTING_READ(reg); | |
e1a44743 AJ |
3428 | udelay(150); |
3429 | ||
8db9d77b | 3430 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3431 | reg = FDI_TX_CTL(pipe); |
3432 | temp = I915_READ(reg); | |
627eb5a3 | 3433 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3434 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3435 | temp &= ~FDI_LINK_TRAIN_NONE; |
3436 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3437 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3438 | /* SNB-B */ | |
3439 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3440 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3441 | |
d74cf324 DV |
3442 | I915_WRITE(FDI_RX_MISC(pipe), |
3443 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3444 | ||
5eddb70b CW |
3445 | reg = FDI_RX_CTL(pipe); |
3446 | temp = I915_READ(reg); | |
8db9d77b ZW |
3447 | if (HAS_PCH_CPT(dev)) { |
3448 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3449 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3450 | } else { | |
3451 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3452 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3453 | } | |
5eddb70b CW |
3454 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3455 | ||
3456 | POSTING_READ(reg); | |
8db9d77b ZW |
3457 | udelay(150); |
3458 | ||
0206e353 | 3459 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3460 | reg = FDI_TX_CTL(pipe); |
3461 | temp = I915_READ(reg); | |
8db9d77b ZW |
3462 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3463 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3464 | I915_WRITE(reg, temp); |
3465 | ||
3466 | POSTING_READ(reg); | |
8db9d77b ZW |
3467 | udelay(500); |
3468 | ||
fa37d39e SP |
3469 | for (retry = 0; retry < 5; retry++) { |
3470 | reg = FDI_RX_IIR(pipe); | |
3471 | temp = I915_READ(reg); | |
3472 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3473 | if (temp & FDI_RX_BIT_LOCK) { | |
3474 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3475 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3476 | break; | |
3477 | } | |
3478 | udelay(50); | |
8db9d77b | 3479 | } |
fa37d39e SP |
3480 | if (retry < 5) |
3481 | break; | |
8db9d77b ZW |
3482 | } |
3483 | if (i == 4) | |
5eddb70b | 3484 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3485 | |
3486 | /* Train 2 */ | |
5eddb70b CW |
3487 | reg = FDI_TX_CTL(pipe); |
3488 | temp = I915_READ(reg); | |
8db9d77b ZW |
3489 | temp &= ~FDI_LINK_TRAIN_NONE; |
3490 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3491 | if (IS_GEN6(dev)) { | |
3492 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3493 | /* SNB-B */ | |
3494 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3495 | } | |
5eddb70b | 3496 | I915_WRITE(reg, temp); |
8db9d77b | 3497 | |
5eddb70b CW |
3498 | reg = FDI_RX_CTL(pipe); |
3499 | temp = I915_READ(reg); | |
8db9d77b ZW |
3500 | if (HAS_PCH_CPT(dev)) { |
3501 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3502 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3503 | } else { | |
3504 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3505 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3506 | } | |
5eddb70b CW |
3507 | I915_WRITE(reg, temp); |
3508 | ||
3509 | POSTING_READ(reg); | |
8db9d77b ZW |
3510 | udelay(150); |
3511 | ||
0206e353 | 3512 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3513 | reg = FDI_TX_CTL(pipe); |
3514 | temp = I915_READ(reg); | |
8db9d77b ZW |
3515 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3516 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3517 | I915_WRITE(reg, temp); |
3518 | ||
3519 | POSTING_READ(reg); | |
8db9d77b ZW |
3520 | udelay(500); |
3521 | ||
fa37d39e SP |
3522 | for (retry = 0; retry < 5; retry++) { |
3523 | reg = FDI_RX_IIR(pipe); | |
3524 | temp = I915_READ(reg); | |
3525 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3526 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3527 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3528 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3529 | break; | |
3530 | } | |
3531 | udelay(50); | |
8db9d77b | 3532 | } |
fa37d39e SP |
3533 | if (retry < 5) |
3534 | break; | |
8db9d77b ZW |
3535 | } |
3536 | if (i == 4) | |
5eddb70b | 3537 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3538 | |
3539 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3540 | } | |
3541 | ||
357555c0 JB |
3542 | /* Manual link training for Ivy Bridge A0 parts */ |
3543 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3544 | { | |
3545 | struct drm_device *dev = crtc->dev; | |
3546 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3547 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3548 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3549 | i915_reg_t reg; |
3550 | u32 temp, i, j; | |
357555c0 JB |
3551 | |
3552 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3553 | for train result */ | |
3554 | reg = FDI_RX_IMR(pipe); | |
3555 | temp = I915_READ(reg); | |
3556 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3557 | temp &= ~FDI_RX_BIT_LOCK; | |
3558 | I915_WRITE(reg, temp); | |
3559 | ||
3560 | POSTING_READ(reg); | |
3561 | udelay(150); | |
3562 | ||
01a415fd DV |
3563 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3564 | I915_READ(FDI_RX_IIR(pipe))); | |
3565 | ||
139ccd3f JB |
3566 | /* Try each vswing and preemphasis setting twice before moving on */ |
3567 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3568 | /* disable first in case we need to retry */ | |
3569 | reg = FDI_TX_CTL(pipe); | |
3570 | temp = I915_READ(reg); | |
3571 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3572 | temp &= ~FDI_TX_ENABLE; | |
3573 | I915_WRITE(reg, temp); | |
357555c0 | 3574 | |
139ccd3f JB |
3575 | reg = FDI_RX_CTL(pipe); |
3576 | temp = I915_READ(reg); | |
3577 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3578 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3579 | temp &= ~FDI_RX_ENABLE; | |
3580 | I915_WRITE(reg, temp); | |
357555c0 | 3581 | |
139ccd3f | 3582 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3583 | reg = FDI_TX_CTL(pipe); |
3584 | temp = I915_READ(reg); | |
139ccd3f | 3585 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3586 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3587 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3588 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3589 | temp |= snb_b_fdi_train_param[j/2]; |
3590 | temp |= FDI_COMPOSITE_SYNC; | |
3591 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3592 | |
139ccd3f JB |
3593 | I915_WRITE(FDI_RX_MISC(pipe), |
3594 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3595 | |
139ccd3f | 3596 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3597 | temp = I915_READ(reg); |
139ccd3f JB |
3598 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3599 | temp |= FDI_COMPOSITE_SYNC; | |
3600 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3601 | |
139ccd3f JB |
3602 | POSTING_READ(reg); |
3603 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3604 | |
139ccd3f JB |
3605 | for (i = 0; i < 4; i++) { |
3606 | reg = FDI_RX_IIR(pipe); | |
3607 | temp = I915_READ(reg); | |
3608 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3609 | |
139ccd3f JB |
3610 | if (temp & FDI_RX_BIT_LOCK || |
3611 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3612 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3613 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3614 | i); | |
3615 | break; | |
3616 | } | |
3617 | udelay(1); /* should be 0.5us */ | |
3618 | } | |
3619 | if (i == 4) { | |
3620 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3621 | continue; | |
3622 | } | |
357555c0 | 3623 | |
139ccd3f | 3624 | /* Train 2 */ |
357555c0 JB |
3625 | reg = FDI_TX_CTL(pipe); |
3626 | temp = I915_READ(reg); | |
139ccd3f JB |
3627 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3628 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3629 | I915_WRITE(reg, temp); | |
3630 | ||
3631 | reg = FDI_RX_CTL(pipe); | |
3632 | temp = I915_READ(reg); | |
3633 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3634 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3635 | I915_WRITE(reg, temp); |
3636 | ||
3637 | POSTING_READ(reg); | |
139ccd3f | 3638 | udelay(2); /* should be 1.5us */ |
357555c0 | 3639 | |
139ccd3f JB |
3640 | for (i = 0; i < 4; i++) { |
3641 | reg = FDI_RX_IIR(pipe); | |
3642 | temp = I915_READ(reg); | |
3643 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3644 | |
139ccd3f JB |
3645 | if (temp & FDI_RX_SYMBOL_LOCK || |
3646 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3647 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3648 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3649 | i); | |
3650 | goto train_done; | |
3651 | } | |
3652 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3653 | } |
139ccd3f JB |
3654 | if (i == 4) |
3655 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3656 | } |
357555c0 | 3657 | |
139ccd3f | 3658 | train_done: |
357555c0 JB |
3659 | DRM_DEBUG_KMS("FDI train done.\n"); |
3660 | } | |
3661 | ||
88cefb6c | 3662 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3663 | { |
88cefb6c | 3664 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3665 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3666 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
3667 | i915_reg_t reg; |
3668 | u32 temp; | |
c64e311e | 3669 | |
c98e9dcf | 3670 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3671 | reg = FDI_RX_CTL(pipe); |
3672 | temp = I915_READ(reg); | |
627eb5a3 | 3673 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3674 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3675 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3676 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3677 | ||
3678 | POSTING_READ(reg); | |
c98e9dcf JB |
3679 | udelay(200); |
3680 | ||
3681 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3682 | temp = I915_READ(reg); |
3683 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3684 | ||
3685 | POSTING_READ(reg); | |
c98e9dcf JB |
3686 | udelay(200); |
3687 | ||
20749730 PZ |
3688 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3689 | reg = FDI_TX_CTL(pipe); | |
3690 | temp = I915_READ(reg); | |
3691 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3692 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3693 | |
20749730 PZ |
3694 | POSTING_READ(reg); |
3695 | udelay(100); | |
6be4a607 | 3696 | } |
0e23b99d JB |
3697 | } |
3698 | ||
88cefb6c DV |
3699 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3700 | { | |
3701 | struct drm_device *dev = intel_crtc->base.dev; | |
3702 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3703 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3704 | i915_reg_t reg; |
3705 | u32 temp; | |
88cefb6c DV |
3706 | |
3707 | /* Switch from PCDclk to Rawclk */ | |
3708 | reg = FDI_RX_CTL(pipe); | |
3709 | temp = I915_READ(reg); | |
3710 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3711 | ||
3712 | /* Disable CPU FDI TX PLL */ | |
3713 | reg = FDI_TX_CTL(pipe); | |
3714 | temp = I915_READ(reg); | |
3715 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3716 | ||
3717 | POSTING_READ(reg); | |
3718 | udelay(100); | |
3719 | ||
3720 | reg = FDI_RX_CTL(pipe); | |
3721 | temp = I915_READ(reg); | |
3722 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3723 | ||
3724 | /* Wait for the clocks to turn off. */ | |
3725 | POSTING_READ(reg); | |
3726 | udelay(100); | |
3727 | } | |
3728 | ||
0fc932b8 JB |
3729 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3730 | { | |
3731 | struct drm_device *dev = crtc->dev; | |
3732 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3733 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3734 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3735 | i915_reg_t reg; |
3736 | u32 temp; | |
0fc932b8 JB |
3737 | |
3738 | /* disable CPU FDI tx and PCH FDI rx */ | |
3739 | reg = FDI_TX_CTL(pipe); | |
3740 | temp = I915_READ(reg); | |
3741 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3742 | POSTING_READ(reg); | |
3743 | ||
3744 | reg = FDI_RX_CTL(pipe); | |
3745 | temp = I915_READ(reg); | |
3746 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3747 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3748 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3749 | ||
3750 | POSTING_READ(reg); | |
3751 | udelay(100); | |
3752 | ||
3753 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3754 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3755 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3756 | |
3757 | /* still set train pattern 1 */ | |
3758 | reg = FDI_TX_CTL(pipe); | |
3759 | temp = I915_READ(reg); | |
3760 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3761 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3762 | I915_WRITE(reg, temp); | |
3763 | ||
3764 | reg = FDI_RX_CTL(pipe); | |
3765 | temp = I915_READ(reg); | |
3766 | if (HAS_PCH_CPT(dev)) { | |
3767 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3768 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3769 | } else { | |
3770 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3771 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3772 | } | |
3773 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3774 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3775 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3776 | I915_WRITE(reg, temp); |
3777 | ||
3778 | POSTING_READ(reg); | |
3779 | udelay(100); | |
3780 | } | |
3781 | ||
5dce5b93 CW |
3782 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3783 | { | |
3784 | struct intel_crtc *crtc; | |
3785 | ||
3786 | /* Note that we don't need to be called with mode_config.lock here | |
3787 | * as our list of CRTC objects is static for the lifetime of the | |
3788 | * device and so cannot disappear as we iterate. Similarly, we can | |
3789 | * happily treat the predicates as racy, atomic checks as userspace | |
3790 | * cannot claim and pin a new fb without at least acquring the | |
3791 | * struct_mutex and so serialising with us. | |
3792 | */ | |
d3fcc808 | 3793 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3794 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3795 | continue; | |
3796 | ||
3797 | if (crtc->unpin_work) | |
3798 | intel_wait_for_vblank(dev, crtc->pipe); | |
3799 | ||
3800 | return true; | |
3801 | } | |
3802 | ||
3803 | return false; | |
3804 | } | |
3805 | ||
d6bbafa1 CW |
3806 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3807 | { | |
3808 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3809 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3810 | ||
d6bbafa1 CW |
3811 | intel_crtc->unpin_work = NULL; |
3812 | ||
3813 | if (work->event) | |
560ce1dc | 3814 | drm_crtc_send_vblank_event(&intel_crtc->base, work->event); |
d6bbafa1 CW |
3815 | |
3816 | drm_crtc_vblank_put(&intel_crtc->base); | |
3817 | ||
3818 | wake_up_all(&dev_priv->pending_flip_queue); | |
3819 | queue_work(dev_priv->wq, &work->work); | |
3820 | ||
3821 | trace_i915_flip_complete(intel_crtc->plane, | |
3822 | work->pending_flip_obj); | |
3823 | } | |
3824 | ||
5008e874 | 3825 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3826 | { |
0f91128d | 3827 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3828 | struct drm_i915_private *dev_priv = dev->dev_private; |
5008e874 | 3829 | long ret; |
e6c3a2a6 | 3830 | |
2c10d571 | 3831 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
3832 | |
3833 | ret = wait_event_interruptible_timeout( | |
3834 | dev_priv->pending_flip_queue, | |
3835 | !intel_crtc_has_pending_flip(crtc), | |
3836 | 60*HZ); | |
3837 | ||
3838 | if (ret < 0) | |
3839 | return ret; | |
3840 | ||
3841 | if (ret == 0) { | |
9c787942 | 3842 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2c10d571 | 3843 | |
5e2d7afc | 3844 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3845 | if (intel_crtc->unpin_work) { |
3846 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3847 | page_flip_completed(intel_crtc); | |
3848 | } | |
5e2d7afc | 3849 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3850 | } |
5bb61643 | 3851 | |
5008e874 | 3852 | return 0; |
e6c3a2a6 CW |
3853 | } |
3854 | ||
060f02d8 VS |
3855 | static void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
3856 | { | |
3857 | u32 temp; | |
3858 | ||
3859 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3860 | ||
3861 | mutex_lock(&dev_priv->sb_lock); | |
3862 | ||
3863 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
3864 | temp |= SBI_SSCCTL_DISABLE; | |
3865 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
3866 | ||
3867 | mutex_unlock(&dev_priv->sb_lock); | |
3868 | } | |
3869 | ||
e615efe4 ED |
3870 | /* Program iCLKIP clock to the desired frequency */ |
3871 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3872 | { | |
64b46a06 | 3873 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
6e3c9717 | 3874 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3875 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3876 | u32 temp; | |
3877 | ||
060f02d8 | 3878 | lpt_disable_iclkip(dev_priv); |
e615efe4 | 3879 | |
64b46a06 VS |
3880 | /* The iCLK virtual clock root frequency is in MHz, |
3881 | * but the adjusted_mode->crtc_clock in in KHz. To get the | |
3882 | * divisors, it is necessary to divide one by another, so we | |
3883 | * convert the virtual clock precision to KHz here for higher | |
3884 | * precision. | |
3885 | */ | |
3886 | for (auxdiv = 0; auxdiv < 2; auxdiv++) { | |
e615efe4 ED |
3887 | u32 iclk_virtual_root_freq = 172800 * 1000; |
3888 | u32 iclk_pi_range = 64; | |
64b46a06 | 3889 | u32 desired_divisor; |
e615efe4 | 3890 | |
64b46a06 VS |
3891 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, |
3892 | clock << auxdiv); | |
3893 | divsel = (desired_divisor / iclk_pi_range) - 2; | |
3894 | phaseinc = desired_divisor % iclk_pi_range; | |
e615efe4 | 3895 | |
64b46a06 VS |
3896 | /* |
3897 | * Near 20MHz is a corner case which is | |
3898 | * out of range for the 7-bit divisor | |
3899 | */ | |
3900 | if (divsel <= 0x7f) | |
3901 | break; | |
e615efe4 ED |
3902 | } |
3903 | ||
3904 | /* This should not happen with any sane values */ | |
3905 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3906 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3907 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3908 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3909 | ||
3910 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3911 | clock, |
e615efe4 ED |
3912 | auxdiv, |
3913 | divsel, | |
3914 | phasedir, | |
3915 | phaseinc); | |
3916 | ||
060f02d8 VS |
3917 | mutex_lock(&dev_priv->sb_lock); |
3918 | ||
e615efe4 | 3919 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 3920 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3921 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3922 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3923 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3924 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3925 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3926 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3927 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3928 | |
3929 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3930 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3931 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3932 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3933 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3934 | |
3935 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3936 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3937 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3938 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 3939 | |
060f02d8 VS |
3940 | mutex_unlock(&dev_priv->sb_lock); |
3941 | ||
e615efe4 ED |
3942 | /* Wait for initialization time */ |
3943 | udelay(24); | |
3944 | ||
3945 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
3946 | } | |
3947 | ||
8802e5b6 VS |
3948 | int lpt_get_iclkip(struct drm_i915_private *dev_priv) |
3949 | { | |
3950 | u32 divsel, phaseinc, auxdiv; | |
3951 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3952 | u32 iclk_pi_range = 64; | |
3953 | u32 desired_divisor; | |
3954 | u32 temp; | |
3955 | ||
3956 | if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) | |
3957 | return 0; | |
3958 | ||
3959 | mutex_lock(&dev_priv->sb_lock); | |
3960 | ||
3961 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
3962 | if (temp & SBI_SSCCTL_DISABLE) { | |
3963 | mutex_unlock(&dev_priv->sb_lock); | |
3964 | return 0; | |
3965 | } | |
3966 | ||
3967 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); | |
3968 | divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> | |
3969 | SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; | |
3970 | phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> | |
3971 | SBI_SSCDIVINTPHASE_INCVAL_SHIFT; | |
3972 | ||
3973 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); | |
3974 | auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> | |
3975 | SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; | |
3976 | ||
3977 | mutex_unlock(&dev_priv->sb_lock); | |
3978 | ||
3979 | desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; | |
3980 | ||
3981 | return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, | |
3982 | desired_divisor << auxdiv); | |
3983 | } | |
3984 | ||
275f01b2 DV |
3985 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3986 | enum pipe pch_transcoder) | |
3987 | { | |
3988 | struct drm_device *dev = crtc->base.dev; | |
3989 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3990 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
3991 | |
3992 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3993 | I915_READ(HTOTAL(cpu_transcoder))); | |
3994 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3995 | I915_READ(HBLANK(cpu_transcoder))); | |
3996 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3997 | I915_READ(HSYNC(cpu_transcoder))); | |
3998 | ||
3999 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4000 | I915_READ(VTOTAL(cpu_transcoder))); | |
4001 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4002 | I915_READ(VBLANK(cpu_transcoder))); | |
4003 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4004 | I915_READ(VSYNC(cpu_transcoder))); | |
4005 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4006 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4007 | } | |
4008 | ||
003632d9 | 4009 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
4010 | { |
4011 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4012 | uint32_t temp; | |
4013 | ||
4014 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4015 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4016 | return; |
4017 | ||
4018 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4019 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4020 | ||
003632d9 ACO |
4021 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4022 | if (enable) | |
4023 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4024 | ||
4025 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4026 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4027 | POSTING_READ(SOUTH_CHICKEN1); | |
4028 | } | |
4029 | ||
4030 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4031 | { | |
4032 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4033 | |
4034 | switch (intel_crtc->pipe) { | |
4035 | case PIPE_A: | |
4036 | break; | |
4037 | case PIPE_B: | |
6e3c9717 | 4038 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4039 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4040 | else |
003632d9 | 4041 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4042 | |
4043 | break; | |
4044 | case PIPE_C: | |
003632d9 | 4045 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4046 | |
4047 | break; | |
4048 | default: | |
4049 | BUG(); | |
4050 | } | |
4051 | } | |
4052 | ||
c48b5305 VS |
4053 | /* Return which DP Port should be selected for Transcoder DP control */ |
4054 | static enum port | |
4055 | intel_trans_dp_port_sel(struct drm_crtc *crtc) | |
4056 | { | |
4057 | struct drm_device *dev = crtc->dev; | |
4058 | struct intel_encoder *encoder; | |
4059 | ||
4060 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
4061 | if (encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
4062 | encoder->type == INTEL_OUTPUT_EDP) | |
4063 | return enc_to_dig_port(&encoder->base)->port; | |
4064 | } | |
4065 | ||
4066 | return -1; | |
4067 | } | |
4068 | ||
f67a559d JB |
4069 | /* |
4070 | * Enable PCH resources required for PCH ports: | |
4071 | * - PCH PLLs | |
4072 | * - FDI training & RX/TX | |
4073 | * - update transcoder timings | |
4074 | * - DP transcoding bits | |
4075 | * - transcoder | |
4076 | */ | |
4077 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4078 | { |
4079 | struct drm_device *dev = crtc->dev; | |
4080 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4081 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4082 | int pipe = intel_crtc->pipe; | |
f0f59a00 | 4083 | u32 temp; |
2c07245f | 4084 | |
ab9412ba | 4085 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4086 | |
1fbc0d78 DV |
4087 | if (IS_IVYBRIDGE(dev)) |
4088 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4089 | ||
cd986abb DV |
4090 | /* Write the TU size bits before fdi link training, so that error |
4091 | * detection works. */ | |
4092 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4093 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4094 | ||
c98e9dcf | 4095 | /* For PCH output, training FDI link */ |
674cf967 | 4096 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4097 | |
3ad8a208 DV |
4098 | /* We need to program the right clock selection before writing the pixel |
4099 | * mutliplier into the DPLL. */ | |
303b81e0 | 4100 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4101 | u32 sel; |
4b645f14 | 4102 | |
c98e9dcf | 4103 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4104 | temp |= TRANS_DPLL_ENABLE(pipe); |
4105 | sel = TRANS_DPLLB_SEL(pipe); | |
8106ddbd ACO |
4106 | if (intel_crtc->config->shared_dpll == |
4107 | intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B)) | |
ee7b9f93 JB |
4108 | temp |= sel; |
4109 | else | |
4110 | temp &= ~sel; | |
c98e9dcf | 4111 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4112 | } |
5eddb70b | 4113 | |
3ad8a208 DV |
4114 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4115 | * transcoder, and we actually should do this to not upset any PCH | |
4116 | * transcoder that already use the clock when we share it. | |
4117 | * | |
4118 | * Note that enable_shared_dpll tries to do the right thing, but | |
4119 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4120 | * the right LVDS enable sequence. */ | |
85b3894f | 4121 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4122 | |
d9b6cb56 JB |
4123 | /* set transcoder timing, panel must allow it */ |
4124 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4125 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4126 | |
303b81e0 | 4127 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4128 | |
c98e9dcf | 4129 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4130 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
9c4edaee VS |
4131 | const struct drm_display_mode *adjusted_mode = |
4132 | &intel_crtc->config->base.adjusted_mode; | |
dfd07d72 | 4133 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4134 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4135 | temp = I915_READ(reg); |
4136 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4137 | TRANS_DP_SYNC_MASK | |
4138 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4139 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4140 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4141 | |
9c4edaee | 4142 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4143 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4144 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4145 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4146 | |
4147 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4148 | case PORT_B: |
5eddb70b | 4149 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4150 | break; |
c48b5305 | 4151 | case PORT_C: |
5eddb70b | 4152 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4153 | break; |
c48b5305 | 4154 | case PORT_D: |
5eddb70b | 4155 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4156 | break; |
4157 | default: | |
e95d41e1 | 4158 | BUG(); |
32f9d658 | 4159 | } |
2c07245f | 4160 | |
5eddb70b | 4161 | I915_WRITE(reg, temp); |
6be4a607 | 4162 | } |
b52eb4dc | 4163 | |
b8a4f404 | 4164 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4165 | } |
4166 | ||
1507e5bd PZ |
4167 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4168 | { | |
4169 | struct drm_device *dev = crtc->dev; | |
4170 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4171 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4172 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4173 | |
ab9412ba | 4174 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4175 | |
8c52b5e8 | 4176 | lpt_program_iclkip(crtc); |
1507e5bd | 4177 | |
0540e488 | 4178 | /* Set transcoder timing. */ |
275f01b2 | 4179 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4180 | |
937bb610 | 4181 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4182 | } |
4183 | ||
a1520318 | 4184 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4185 | { |
4186 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 4187 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4188 | u32 temp; |
4189 | ||
4190 | temp = I915_READ(dslreg); | |
4191 | udelay(500); | |
4192 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4193 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4194 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4195 | } |
4196 | } | |
4197 | ||
86adf9d7 ML |
4198 | static int |
4199 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4200 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4201 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4202 | { |
86adf9d7 ML |
4203 | struct intel_crtc_scaler_state *scaler_state = |
4204 | &crtc_state->scaler_state; | |
4205 | struct intel_crtc *intel_crtc = | |
4206 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4207 | int need_scaling; |
6156a456 CK |
4208 | |
4209 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4210 | (src_h != dst_w || src_w != dst_h): | |
4211 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4212 | |
4213 | /* | |
4214 | * if plane is being disabled or scaler is no more required or force detach | |
4215 | * - free scaler binded to this plane/crtc | |
4216 | * - in order to do this, update crtc->scaler_usage | |
4217 | * | |
4218 | * Here scaler state in crtc_state is set free so that | |
4219 | * scaler can be assigned to other user. Actual register | |
4220 | * update to free the scaler is done in plane/panel-fit programming. | |
4221 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4222 | */ | |
86adf9d7 | 4223 | if (force_detach || !need_scaling) { |
a1b2278e | 4224 | if (*scaler_id >= 0) { |
86adf9d7 | 4225 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4226 | scaler_state->scalers[*scaler_id].in_use = 0; |
4227 | ||
86adf9d7 ML |
4228 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4229 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4230 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4231 | scaler_state->scaler_users); |
4232 | *scaler_id = -1; | |
4233 | } | |
4234 | return 0; | |
4235 | } | |
4236 | ||
4237 | /* range checks */ | |
4238 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4239 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4240 | ||
4241 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4242 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4243 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4244 | "size is out of scaler range\n", |
86adf9d7 | 4245 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4246 | return -EINVAL; |
4247 | } | |
4248 | ||
86adf9d7 ML |
4249 | /* mark this plane as a scaler user in crtc_state */ |
4250 | scaler_state->scaler_users |= (1 << scaler_user); | |
4251 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4252 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4253 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4254 | scaler_state->scaler_users); | |
4255 | ||
4256 | return 0; | |
4257 | } | |
4258 | ||
4259 | /** | |
4260 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4261 | * | |
4262 | * @state: crtc's scaler state | |
86adf9d7 ML |
4263 | * |
4264 | * Return | |
4265 | * 0 - scaler_usage updated successfully | |
4266 | * error - requested scaling cannot be supported or other error condition | |
4267 | */ | |
e435d6e5 | 4268 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 ML |
4269 | { |
4270 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); | |
7c5f93b0 | 4271 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 ML |
4272 | |
4273 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n", | |
4274 | intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX); | |
4275 | ||
e435d6e5 | 4276 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
fa5a7970 | 4277 | &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0), |
86adf9d7 | 4278 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4279 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4280 | } |
4281 | ||
4282 | /** | |
4283 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4284 | * | |
4285 | * @state: crtc's scaler state | |
86adf9d7 ML |
4286 | * @plane_state: atomic plane state to update |
4287 | * | |
4288 | * Return | |
4289 | * 0 - scaler_usage updated successfully | |
4290 | * error - requested scaling cannot be supported or other error condition | |
4291 | */ | |
da20eabd ML |
4292 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4293 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4294 | { |
4295 | ||
4296 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
da20eabd ML |
4297 | struct intel_plane *intel_plane = |
4298 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4299 | struct drm_framebuffer *fb = plane_state->base.fb; |
4300 | int ret; | |
4301 | ||
4302 | bool force_detach = !fb || !plane_state->visible; | |
4303 | ||
4304 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n", | |
4305 | intel_plane->base.base.id, intel_crtc->pipe, | |
4306 | drm_plane_index(&intel_plane->base)); | |
4307 | ||
4308 | ret = skl_update_scaler(crtc_state, force_detach, | |
4309 | drm_plane_index(&intel_plane->base), | |
4310 | &plane_state->scaler_id, | |
4311 | plane_state->base.rotation, | |
4312 | drm_rect_width(&plane_state->src) >> 16, | |
4313 | drm_rect_height(&plane_state->src) >> 16, | |
4314 | drm_rect_width(&plane_state->dst), | |
4315 | drm_rect_height(&plane_state->dst)); | |
4316 | ||
4317 | if (ret || plane_state->scaler_id < 0) | |
4318 | return ret; | |
4319 | ||
a1b2278e | 4320 | /* check colorkey */ |
818ed961 | 4321 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
86adf9d7 | 4322 | DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed", |
818ed961 | 4323 | intel_plane->base.base.id); |
a1b2278e CK |
4324 | return -EINVAL; |
4325 | } | |
4326 | ||
4327 | /* Check src format */ | |
86adf9d7 ML |
4328 | switch (fb->pixel_format) { |
4329 | case DRM_FORMAT_RGB565: | |
4330 | case DRM_FORMAT_XBGR8888: | |
4331 | case DRM_FORMAT_XRGB8888: | |
4332 | case DRM_FORMAT_ABGR8888: | |
4333 | case DRM_FORMAT_ARGB8888: | |
4334 | case DRM_FORMAT_XRGB2101010: | |
4335 | case DRM_FORMAT_XBGR2101010: | |
4336 | case DRM_FORMAT_YUYV: | |
4337 | case DRM_FORMAT_YVYU: | |
4338 | case DRM_FORMAT_UYVY: | |
4339 | case DRM_FORMAT_VYUY: | |
4340 | break; | |
4341 | default: | |
4342 | DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n", | |
4343 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); | |
4344 | return -EINVAL; | |
a1b2278e CK |
4345 | } |
4346 | ||
a1b2278e CK |
4347 | return 0; |
4348 | } | |
4349 | ||
e435d6e5 ML |
4350 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4351 | { | |
4352 | int i; | |
4353 | ||
4354 | for (i = 0; i < crtc->num_scalers; i++) | |
4355 | skl_detach_scaler(crtc, i); | |
4356 | } | |
4357 | ||
4358 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4359 | { |
4360 | struct drm_device *dev = crtc->base.dev; | |
4361 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4362 | int pipe = crtc->pipe; | |
a1b2278e CK |
4363 | struct intel_crtc_scaler_state *scaler_state = |
4364 | &crtc->config->scaler_state; | |
4365 | ||
4366 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4367 | ||
6e3c9717 | 4368 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4369 | int id; |
4370 | ||
4371 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4372 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4373 | return; | |
4374 | } | |
4375 | ||
4376 | id = scaler_state->scaler_id; | |
4377 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4378 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4379 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4380 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4381 | ||
4382 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4383 | } |
4384 | } | |
4385 | ||
b074cec8 JB |
4386 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4387 | { | |
4388 | struct drm_device *dev = crtc->base.dev; | |
4389 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4390 | int pipe = crtc->pipe; | |
4391 | ||
6e3c9717 | 4392 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4393 | /* Force use of hard-coded filter coefficients |
4394 | * as some pre-programmed values are broken, | |
4395 | * e.g. x201. | |
4396 | */ | |
4397 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4398 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4399 | PF_PIPE_SEL_IVB(pipe)); | |
4400 | else | |
4401 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4402 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4403 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4404 | } |
4405 | } | |
4406 | ||
20bc8673 | 4407 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4408 | { |
cea165c3 VS |
4409 | struct drm_device *dev = crtc->base.dev; |
4410 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4411 | |
6e3c9717 | 4412 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4413 | return; |
4414 | ||
307e4498 ML |
4415 | /* |
4416 | * We can only enable IPS after we enable a plane and wait for a vblank | |
4417 | * This function is called from post_plane_update, which is run after | |
4418 | * a vblank wait. | |
4419 | */ | |
cea165c3 | 4420 | |
d77e4531 | 4421 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4422 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4423 | mutex_lock(&dev_priv->rps.hw_lock); |
4424 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4425 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4426 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4427 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4428 | * mailbox." Moreover, the mailbox may return a bogus state, |
4429 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4430 | */ |
4431 | } else { | |
4432 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4433 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4434 | * is essentially intel_wait_for_vblank. If we don't have this | |
4435 | * and don't wait for vblanks until the end of crtc_enable, then | |
4436 | * the HW state readout code will complain that the expected | |
4437 | * IPS_CTL value is not the one we read. */ | |
4438 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4439 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4440 | } | |
d77e4531 PZ |
4441 | } |
4442 | ||
20bc8673 | 4443 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4444 | { |
4445 | struct drm_device *dev = crtc->base.dev; | |
4446 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4447 | ||
6e3c9717 | 4448 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4449 | return; |
4450 | ||
4451 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4452 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4453 | mutex_lock(&dev_priv->rps.hw_lock); |
4454 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4455 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4456 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4457 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4458 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4459 | } else { |
2a114cc1 | 4460 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4461 | POSTING_READ(IPS_CTL); |
4462 | } | |
d77e4531 PZ |
4463 | |
4464 | /* We need to wait for a vblank before we can disable the plane. */ | |
4465 | intel_wait_for_vblank(dev, crtc->pipe); | |
4466 | } | |
4467 | ||
7cac945f | 4468 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4469 | { |
7cac945f | 4470 | if (intel_crtc->overlay) { |
d3eedb1a VS |
4471 | struct drm_device *dev = intel_crtc->base.dev; |
4472 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4473 | ||
4474 | mutex_lock(&dev->struct_mutex); | |
4475 | dev_priv->mm.interruptible = false; | |
4476 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4477 | dev_priv->mm.interruptible = true; | |
4478 | mutex_unlock(&dev->struct_mutex); | |
4479 | } | |
4480 | ||
4481 | /* Let userspace switch the overlay on again. In most cases userspace | |
4482 | * has to recompute where to put it anyway. | |
4483 | */ | |
4484 | } | |
4485 | ||
87d4300a ML |
4486 | /** |
4487 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4488 | * @crtc: the CRTC whose primary plane was just enabled | |
4489 | * | |
4490 | * Performs potentially sleeping operations that must be done after the primary | |
4491 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4492 | * called due to an explicit primary plane update, or due to an implicit | |
4493 | * re-enable that is caused when a sprite plane is updated to no longer | |
4494 | * completely hide the primary plane. | |
4495 | */ | |
4496 | static void | |
4497 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4498 | { |
4499 | struct drm_device *dev = crtc->dev; | |
87d4300a | 4500 | struct drm_i915_private *dev_priv = dev->dev_private; |
a5c4d7bc VS |
4501 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4502 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4503 | |
87d4300a ML |
4504 | /* |
4505 | * FIXME IPS should be fine as long as one plane is | |
4506 | * enabled, but in practice it seems to have problems | |
4507 | * when going from primary only to sprite only and vice | |
4508 | * versa. | |
4509 | */ | |
a5c4d7bc VS |
4510 | hsw_enable_ips(intel_crtc); |
4511 | ||
f99d7069 | 4512 | /* |
87d4300a ML |
4513 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4514 | * So don't enable underrun reporting before at least some planes | |
4515 | * are enabled. | |
4516 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4517 | * but leave the pipe running. | |
f99d7069 | 4518 | */ |
87d4300a ML |
4519 | if (IS_GEN2(dev)) |
4520 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4521 | ||
aca7b684 VS |
4522 | /* Underruns don't always raise interrupts, so check manually. */ |
4523 | intel_check_cpu_fifo_underruns(dev_priv); | |
4524 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4525 | } |
4526 | ||
2622a081 | 4527 | /* FIXME move all this to pre_plane_update() with proper state tracking */ |
87d4300a ML |
4528 | static void |
4529 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4530 | { |
4531 | struct drm_device *dev = crtc->dev; | |
4532 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4533 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4534 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4535 | |
87d4300a ML |
4536 | /* |
4537 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4538 | * So diasble underrun reporting before all the planes get disabled. | |
4539 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4540 | * but leave the pipe running. | |
4541 | */ | |
4542 | if (IS_GEN2(dev)) | |
4543 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4544 | |
2622a081 VS |
4545 | /* |
4546 | * FIXME IPS should be fine as long as one plane is | |
4547 | * enabled, but in practice it seems to have problems | |
4548 | * when going from primary only to sprite only and vice | |
4549 | * versa. | |
4550 | */ | |
4551 | hsw_disable_ips(intel_crtc); | |
4552 | } | |
4553 | ||
4554 | /* FIXME get rid of this and use pre_plane_update */ | |
4555 | static void | |
4556 | intel_pre_disable_primary_noatomic(struct drm_crtc *crtc) | |
4557 | { | |
4558 | struct drm_device *dev = crtc->dev; | |
4559 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4560 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4561 | int pipe = intel_crtc->pipe; | |
4562 | ||
4563 | intel_pre_disable_primary(crtc); | |
4564 | ||
87d4300a ML |
4565 | /* |
4566 | * Vblank time updates from the shadow to live plane control register | |
4567 | * are blocked if the memory self-refresh mode is active at that | |
4568 | * moment. So to make sure the plane gets truly disabled, disable | |
4569 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4570 | * will be checked/applied by the HW only at the next frame start | |
4571 | * event which is after the vblank start event, so we need to have a | |
4572 | * wait-for-vblank between disabling the plane and the pipe. | |
4573 | */ | |
262cd2e1 | 4574 | if (HAS_GMCH_DISPLAY(dev)) { |
87d4300a | 4575 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 VS |
4576 | dev_priv->wm.vlv.cxsr = false; |
4577 | intel_wait_for_vblank(dev, pipe); | |
4578 | } | |
87d4300a ML |
4579 | } |
4580 | ||
cd202f69 | 4581 | static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 4582 | { |
cd202f69 ML |
4583 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
4584 | struct drm_atomic_state *old_state = old_crtc_state->base.state; | |
92826fcd ML |
4585 | struct intel_crtc_state *pipe_config = |
4586 | to_intel_crtc_state(crtc->base.state); | |
ac21b225 | 4587 | struct drm_device *dev = crtc->base.dev; |
cd202f69 ML |
4588 | struct drm_plane *primary = crtc->base.primary; |
4589 | struct drm_plane_state *old_pri_state = | |
4590 | drm_atomic_get_existing_plane_state(old_state, primary); | |
ac21b225 | 4591 | |
cd202f69 | 4592 | intel_frontbuffer_flip(dev, pipe_config->fb_bits); |
ac21b225 | 4593 | |
ab1d3a0e | 4594 | crtc->wm.cxsr_allowed = true; |
852eb00d | 4595 | |
caed361d | 4596 | if (pipe_config->update_wm_post && pipe_config->base.active) |
f015c551 VS |
4597 | intel_update_watermarks(&crtc->base); |
4598 | ||
cd202f69 ML |
4599 | if (old_pri_state) { |
4600 | struct intel_plane_state *primary_state = | |
4601 | to_intel_plane_state(primary->state); | |
4602 | struct intel_plane_state *old_primary_state = | |
4603 | to_intel_plane_state(old_pri_state); | |
4604 | ||
31ae71fc ML |
4605 | intel_fbc_post_update(crtc); |
4606 | ||
cd202f69 ML |
4607 | if (primary_state->visible && |
4608 | (needs_modeset(&pipe_config->base) || | |
4609 | !old_primary_state->visible)) | |
4610 | intel_post_enable_primary(&crtc->base); | |
4611 | } | |
ac21b225 ML |
4612 | } |
4613 | ||
5c74cd73 | 4614 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 4615 | { |
5c74cd73 | 4616 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 4617 | struct drm_device *dev = crtc->base.dev; |
eddfcbcd | 4618 | struct drm_i915_private *dev_priv = dev->dev_private; |
ab1d3a0e ML |
4619 | struct intel_crtc_state *pipe_config = |
4620 | to_intel_crtc_state(crtc->base.state); | |
5c74cd73 ML |
4621 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
4622 | struct drm_plane *primary = crtc->base.primary; | |
4623 | struct drm_plane_state *old_pri_state = | |
4624 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4625 | bool modeset = needs_modeset(&pipe_config->base); | |
ac21b225 | 4626 | |
5c74cd73 ML |
4627 | if (old_pri_state) { |
4628 | struct intel_plane_state *primary_state = | |
4629 | to_intel_plane_state(primary->state); | |
4630 | struct intel_plane_state *old_primary_state = | |
4631 | to_intel_plane_state(old_pri_state); | |
4632 | ||
31ae71fc ML |
4633 | intel_fbc_pre_update(crtc); |
4634 | ||
5c74cd73 ML |
4635 | if (old_primary_state->visible && |
4636 | (modeset || !primary_state->visible)) | |
4637 | intel_pre_disable_primary(&crtc->base); | |
4638 | } | |
852eb00d | 4639 | |
ab1d3a0e | 4640 | if (pipe_config->disable_cxsr) { |
852eb00d | 4641 | crtc->wm.cxsr_allowed = false; |
2dfd178d | 4642 | |
2622a081 VS |
4643 | /* |
4644 | * Vblank time updates from the shadow to live plane control register | |
4645 | * are blocked if the memory self-refresh mode is active at that | |
4646 | * moment. So to make sure the plane gets truly disabled, disable | |
4647 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4648 | * will be checked/applied by the HW only at the next frame start | |
4649 | * event which is after the vblank start event, so we need to have a | |
4650 | * wait-for-vblank between disabling the plane and the pipe. | |
4651 | */ | |
4652 | if (old_crtc_state->base.active) { | |
2dfd178d | 4653 | intel_set_memory_cxsr(dev_priv, false); |
2622a081 VS |
4654 | dev_priv->wm.vlv.cxsr = false; |
4655 | intel_wait_for_vblank(dev, crtc->pipe); | |
4656 | } | |
852eb00d | 4657 | } |
92826fcd | 4658 | |
ed4a6a7c MR |
4659 | /* |
4660 | * IVB workaround: must disable low power watermarks for at least | |
4661 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
4662 | * when scaling is disabled. | |
4663 | * | |
4664 | * WaCxSRDisabledForSpriteScaling:ivb | |
4665 | */ | |
4666 | if (pipe_config->disable_lp_wm) { | |
4667 | ilk_disable_lp_wm(dev); | |
4668 | intel_wait_for_vblank(dev, crtc->pipe); | |
4669 | } | |
4670 | ||
4671 | /* | |
4672 | * If we're doing a modeset, we're done. No need to do any pre-vblank | |
4673 | * watermark programming here. | |
4674 | */ | |
4675 | if (needs_modeset(&pipe_config->base)) | |
4676 | return; | |
4677 | ||
4678 | /* | |
4679 | * For platforms that support atomic watermarks, program the | |
4680 | * 'intermediate' watermarks immediately. On pre-gen9 platforms, these | |
4681 | * will be the intermediate values that are safe for both pre- and | |
4682 | * post- vblank; when vblank happens, the 'active' values will be set | |
4683 | * to the final 'target' values and we'll do this again to get the | |
4684 | * optimal watermarks. For gen9+ platforms, the values we program here | |
4685 | * will be the final target values which will get automatically latched | |
4686 | * at vblank time; no further programming will be necessary. | |
4687 | * | |
4688 | * If a platform hasn't been transitioned to atomic watermarks yet, | |
4689 | * we'll continue to update watermarks the old way, if flags tell | |
4690 | * us to. | |
4691 | */ | |
4692 | if (dev_priv->display.initial_watermarks != NULL) | |
4693 | dev_priv->display.initial_watermarks(pipe_config); | |
caed361d | 4694 | else if (pipe_config->update_wm_pre) |
92826fcd | 4695 | intel_update_watermarks(&crtc->base); |
ac21b225 ML |
4696 | } |
4697 | ||
d032ffa0 | 4698 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
4699 | { |
4700 | struct drm_device *dev = crtc->dev; | |
4701 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 4702 | struct drm_plane *p; |
87d4300a ML |
4703 | int pipe = intel_crtc->pipe; |
4704 | ||
7cac945f | 4705 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 4706 | |
d032ffa0 ML |
4707 | drm_for_each_plane_mask(p, dev, plane_mask) |
4708 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 4709 | |
f99d7069 DV |
4710 | /* |
4711 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4712 | * to compute the mask of flip planes precisely. For the time being | |
4713 | * consider this a flip to a NULL plane. | |
4714 | */ | |
4715 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4716 | } |
4717 | ||
f67a559d JB |
4718 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4719 | { | |
4720 | struct drm_device *dev = crtc->dev; | |
4721 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4722 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4723 | struct intel_encoder *encoder; |
f67a559d | 4724 | int pipe = intel_crtc->pipe; |
b95c5321 ML |
4725 | struct intel_crtc_state *pipe_config = |
4726 | to_intel_crtc_state(crtc->state); | |
f67a559d | 4727 | |
53d9f4e9 | 4728 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
4729 | return; |
4730 | ||
b2c0593a VS |
4731 | /* |
4732 | * Sometimes spurious CPU pipe underruns happen during FDI | |
4733 | * training, at least with VGA+HDMI cloning. Suppress them. | |
4734 | * | |
4735 | * On ILK we get an occasional spurious CPU pipe underruns | |
4736 | * between eDP port A enable and vdd enable. Also PCH port | |
4737 | * enable seems to result in the occasional CPU pipe underrun. | |
4738 | * | |
4739 | * Spurious PCH underruns also occur during PCH enabling. | |
4740 | */ | |
4741 | if (intel_crtc->config->has_pch_encoder || IS_GEN5(dev_priv)) | |
4742 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
81b088ca VS |
4743 | if (intel_crtc->config->has_pch_encoder) |
4744 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
4745 | ||
6e3c9717 | 4746 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4747 | intel_prepare_shared_dpll(intel_crtc); |
4748 | ||
6e3c9717 | 4749 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4750 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4751 | |
4752 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 4753 | intel_set_pipe_src_size(intel_crtc); |
29407aab | 4754 | |
6e3c9717 | 4755 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4756 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4757 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4758 | } |
4759 | ||
4760 | ironlake_set_pipeconf(crtc); | |
4761 | ||
f67a559d | 4762 | intel_crtc->active = true; |
8664281b | 4763 | |
f6736a1a | 4764 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4765 | if (encoder->pre_enable) |
4766 | encoder->pre_enable(encoder); | |
f67a559d | 4767 | |
6e3c9717 | 4768 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4769 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4770 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4771 | * enabling. */ | |
88cefb6c | 4772 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4773 | } else { |
4774 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4775 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4776 | } | |
f67a559d | 4777 | |
b074cec8 | 4778 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4779 | |
9c54c0dd JB |
4780 | /* |
4781 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4782 | * clocks enabled | |
4783 | */ | |
b95c5321 | 4784 | intel_color_load_luts(&pipe_config->base); |
9c54c0dd | 4785 | |
1d5bf5d9 ID |
4786 | if (dev_priv->display.initial_watermarks != NULL) |
4787 | dev_priv->display.initial_watermarks(intel_crtc->config); | |
e1fdc473 | 4788 | intel_enable_pipe(intel_crtc); |
f67a559d | 4789 | |
6e3c9717 | 4790 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4791 | ironlake_pch_enable(crtc); |
c98e9dcf | 4792 | |
f9b61ff6 DV |
4793 | assert_vblank_disabled(crtc); |
4794 | drm_crtc_vblank_on(crtc); | |
4795 | ||
fa5c73b1 DV |
4796 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4797 | encoder->enable(encoder); | |
61b77ddd DV |
4798 | |
4799 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4800 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
4801 | |
4802 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
4803 | if (intel_crtc->config->has_pch_encoder) | |
4804 | intel_wait_for_vblank(dev, pipe); | |
b2c0593a | 4805 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
37ca8d4c | 4806 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 JB |
4807 | } |
4808 | ||
42db64ef PZ |
4809 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4810 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4811 | { | |
f5adf94e | 4812 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4813 | } |
4814 | ||
4f771f10 PZ |
4815 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4816 | { | |
4817 | struct drm_device *dev = crtc->dev; | |
4818 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4819 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4820 | struct intel_encoder *encoder; | |
99d736a2 | 4821 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4d1de975 | 4822 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
99d736a2 ML |
4823 | struct intel_crtc_state *pipe_config = |
4824 | to_intel_crtc_state(crtc->state); | |
4f771f10 | 4825 | |
53d9f4e9 | 4826 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
4827 | return; |
4828 | ||
81b088ca VS |
4829 | if (intel_crtc->config->has_pch_encoder) |
4830 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
4831 | false); | |
4832 | ||
8106ddbd | 4833 | if (intel_crtc->config->shared_dpll) |
df8ad70c DV |
4834 | intel_enable_shared_dpll(intel_crtc); |
4835 | ||
6e3c9717 | 4836 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4837 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 | 4838 | |
4d1de975 JN |
4839 | if (!intel_crtc->config->has_dsi_encoder) |
4840 | intel_set_pipe_timings(intel_crtc); | |
4841 | ||
bc58be60 | 4842 | intel_set_pipe_src_size(intel_crtc); |
229fca97 | 4843 | |
4d1de975 JN |
4844 | if (cpu_transcoder != TRANSCODER_EDP && |
4845 | !transcoder_is_dsi(cpu_transcoder)) { | |
4846 | I915_WRITE(PIPE_MULT(cpu_transcoder), | |
6e3c9717 | 4847 | intel_crtc->config->pixel_multiplier - 1); |
ebb69c95 CT |
4848 | } |
4849 | ||
6e3c9717 | 4850 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 4851 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4852 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
4853 | } |
4854 | ||
4d1de975 JN |
4855 | if (!intel_crtc->config->has_dsi_encoder) |
4856 | haswell_set_pipeconf(crtc); | |
4857 | ||
391bf048 | 4858 | haswell_set_pipemisc(crtc); |
229fca97 | 4859 | |
b95c5321 | 4860 | intel_color_set_csc(&pipe_config->base); |
229fca97 | 4861 | |
4f771f10 | 4862 | intel_crtc->active = true; |
8664281b | 4863 | |
6b698516 DV |
4864 | if (intel_crtc->config->has_pch_encoder) |
4865 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4866 | else | |
4867 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4868 | ||
7d4aefd0 | 4869 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 PZ |
4870 | if (encoder->pre_enable) |
4871 | encoder->pre_enable(encoder); | |
7d4aefd0 | 4872 | } |
4f771f10 | 4873 | |
d2d65408 | 4874 | if (intel_crtc->config->has_pch_encoder) |
4fe9467d | 4875 | dev_priv->display.fdi_link_train(crtc); |
4fe9467d | 4876 | |
a65347ba | 4877 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 4878 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4879 | |
1c132b44 | 4880 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 4881 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 4882 | else |
1c132b44 | 4883 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
4884 | |
4885 | /* | |
4886 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4887 | * clocks enabled | |
4888 | */ | |
b95c5321 | 4889 | intel_color_load_luts(&pipe_config->base); |
4f771f10 | 4890 | |
1f544388 | 4891 | intel_ddi_set_pipe_settings(crtc); |
a65347ba | 4892 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 4893 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4894 | |
1d5bf5d9 ID |
4895 | if (dev_priv->display.initial_watermarks != NULL) |
4896 | dev_priv->display.initial_watermarks(pipe_config); | |
4897 | else | |
4898 | intel_update_watermarks(crtc); | |
4d1de975 JN |
4899 | |
4900 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ | |
4901 | if (!intel_crtc->config->has_dsi_encoder) | |
4902 | intel_enable_pipe(intel_crtc); | |
42db64ef | 4903 | |
6e3c9717 | 4904 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 4905 | lpt_pch_enable(crtc); |
4f771f10 | 4906 | |
a65347ba | 4907 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
4908 | intel_ddi_set_vc_payload_alloc(crtc, true); |
4909 | ||
f9b61ff6 DV |
4910 | assert_vblank_disabled(crtc); |
4911 | drm_crtc_vblank_on(crtc); | |
4912 | ||
8807e55b | 4913 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4914 | encoder->enable(encoder); |
8807e55b JN |
4915 | intel_opregion_notify_encoder(encoder, true); |
4916 | } | |
4f771f10 | 4917 | |
6b698516 DV |
4918 | if (intel_crtc->config->has_pch_encoder) { |
4919 | intel_wait_for_vblank(dev, pipe); | |
4920 | intel_wait_for_vblank(dev, pipe); | |
4921 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
d2d65408 VS |
4922 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
4923 | true); | |
6b698516 | 4924 | } |
d2d65408 | 4925 | |
e4916946 PZ |
4926 | /* If we change the relative order between pipe/planes enabling, we need |
4927 | * to change the workaround. */ | |
99d736a2 ML |
4928 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
4929 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { | |
4930 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
4931 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
4932 | } | |
4f771f10 PZ |
4933 | } |
4934 | ||
bfd16b2a | 4935 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
4936 | { |
4937 | struct drm_device *dev = crtc->base.dev; | |
4938 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4939 | int pipe = crtc->pipe; | |
4940 | ||
4941 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4942 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 4943 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
4944 | I915_WRITE(PF_CTL(pipe), 0); |
4945 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4946 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4947 | } | |
4948 | } | |
4949 | ||
6be4a607 JB |
4950 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4951 | { | |
4952 | struct drm_device *dev = crtc->dev; | |
4953 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4954 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4955 | struct intel_encoder *encoder; |
6be4a607 | 4956 | int pipe = intel_crtc->pipe; |
b52eb4dc | 4957 | |
b2c0593a VS |
4958 | /* |
4959 | * Sometimes spurious CPU pipe underruns happen when the | |
4960 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
4961 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
4962 | */ | |
4963 | if (intel_crtc->config->has_pch_encoder) { | |
4964 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
37ca8d4c | 4965 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); |
b2c0593a | 4966 | } |
37ca8d4c | 4967 | |
ea9d758d DV |
4968 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4969 | encoder->disable(encoder); | |
4970 | ||
f9b61ff6 DV |
4971 | drm_crtc_vblank_off(crtc); |
4972 | assert_vblank_disabled(crtc); | |
4973 | ||
575f7ab7 | 4974 | intel_disable_pipe(intel_crtc); |
32f9d658 | 4975 | |
bfd16b2a | 4976 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 4977 | |
b2c0593a | 4978 | if (intel_crtc->config->has_pch_encoder) |
5a74f70a VS |
4979 | ironlake_fdi_disable(crtc); |
4980 | ||
bf49ec8c DV |
4981 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4982 | if (encoder->post_disable) | |
4983 | encoder->post_disable(encoder); | |
2c07245f | 4984 | |
6e3c9717 | 4985 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 4986 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 4987 | |
d925c59a | 4988 | if (HAS_PCH_CPT(dev)) { |
f0f59a00 VS |
4989 | i915_reg_t reg; |
4990 | u32 temp; | |
4991 | ||
d925c59a DV |
4992 | /* disable TRANS_DP_CTL */ |
4993 | reg = TRANS_DP_CTL(pipe); | |
4994 | temp = I915_READ(reg); | |
4995 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
4996 | TRANS_DP_PORT_SEL_MASK); | |
4997 | temp |= TRANS_DP_PORT_SEL_NONE; | |
4998 | I915_WRITE(reg, temp); | |
4999 | ||
5000 | /* disable DPLL_SEL */ | |
5001 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5002 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5003 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5004 | } |
e3421a18 | 5005 | |
d925c59a DV |
5006 | ironlake_fdi_pll_disable(intel_crtc); |
5007 | } | |
81b088ca | 5008 | |
b2c0593a | 5009 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
81b088ca | 5010 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); |
6be4a607 | 5011 | } |
1b3c7a47 | 5012 | |
4f771f10 | 5013 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5014 | { |
4f771f10 PZ |
5015 | struct drm_device *dev = crtc->dev; |
5016 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 5017 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5018 | struct intel_encoder *encoder; |
6e3c9717 | 5019 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5020 | |
d2d65408 VS |
5021 | if (intel_crtc->config->has_pch_encoder) |
5022 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5023 | false); | |
5024 | ||
8807e55b JN |
5025 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5026 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5027 | encoder->disable(encoder); |
8807e55b | 5028 | } |
4f771f10 | 5029 | |
f9b61ff6 DV |
5030 | drm_crtc_vblank_off(crtc); |
5031 | assert_vblank_disabled(crtc); | |
5032 | ||
4d1de975 JN |
5033 | /* XXX: Do the pipe assertions at the right place for BXT DSI. */ |
5034 | if (!intel_crtc->config->has_dsi_encoder) | |
5035 | intel_disable_pipe(intel_crtc); | |
4f771f10 | 5036 | |
6e3c9717 | 5037 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5038 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5039 | ||
a65347ba | 5040 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5041 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5042 | |
1c132b44 | 5043 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5044 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5045 | else |
bfd16b2a | 5046 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5047 | |
a65347ba | 5048 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5049 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5050 | |
97b040aa ID |
5051 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5052 | if (encoder->post_disable) | |
5053 | encoder->post_disable(encoder); | |
81b088ca | 5054 | |
92966a37 VS |
5055 | if (intel_crtc->config->has_pch_encoder) { |
5056 | lpt_disable_pch_transcoder(dev_priv); | |
503a74e9 | 5057 | lpt_disable_iclkip(dev_priv); |
92966a37 VS |
5058 | intel_ddi_fdi_disable(crtc); |
5059 | ||
81b088ca VS |
5060 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5061 | true); | |
92966a37 | 5062 | } |
4f771f10 PZ |
5063 | } |
5064 | ||
2dd24552 JB |
5065 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5066 | { | |
5067 | struct drm_device *dev = crtc->base.dev; | |
5068 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 5069 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5070 | |
681a8504 | 5071 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5072 | return; |
5073 | ||
2dd24552 | 5074 | /* |
c0b03411 DV |
5075 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5076 | * according to register description and PRM. | |
2dd24552 | 5077 | */ |
c0b03411 DV |
5078 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5079 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5080 | |
b074cec8 JB |
5081 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5082 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5083 | |
5084 | /* Border color in case we don't scale up to the full screen. Black by | |
5085 | * default, change to something else for debugging. */ | |
5086 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5087 | } |
5088 | ||
d05410f9 DA |
5089 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5090 | { | |
5091 | switch (port) { | |
5092 | case PORT_A: | |
6331a704 | 5093 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5094 | case PORT_B: |
6331a704 | 5095 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5096 | case PORT_C: |
6331a704 | 5097 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5098 | case PORT_D: |
6331a704 | 5099 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5100 | case PORT_E: |
6331a704 | 5101 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5102 | default: |
b9fec167 | 5103 | MISSING_CASE(port); |
d05410f9 DA |
5104 | return POWER_DOMAIN_PORT_OTHER; |
5105 | } | |
5106 | } | |
5107 | ||
25f78f58 VS |
5108 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
5109 | { | |
5110 | switch (port) { | |
5111 | case PORT_A: | |
5112 | return POWER_DOMAIN_AUX_A; | |
5113 | case PORT_B: | |
5114 | return POWER_DOMAIN_AUX_B; | |
5115 | case PORT_C: | |
5116 | return POWER_DOMAIN_AUX_C; | |
5117 | case PORT_D: | |
5118 | return POWER_DOMAIN_AUX_D; | |
5119 | case PORT_E: | |
5120 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5121 | return POWER_DOMAIN_AUX_D; | |
5122 | default: | |
b9fec167 | 5123 | MISSING_CASE(port); |
25f78f58 VS |
5124 | return POWER_DOMAIN_AUX_A; |
5125 | } | |
5126 | } | |
5127 | ||
319be8ae ID |
5128 | enum intel_display_power_domain |
5129 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5130 | { | |
5131 | struct drm_device *dev = intel_encoder->base.dev; | |
5132 | struct intel_digital_port *intel_dig_port; | |
5133 | ||
5134 | switch (intel_encoder->type) { | |
5135 | case INTEL_OUTPUT_UNKNOWN: | |
5136 | /* Only DDI platforms should ever use this output type */ | |
5137 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5138 | case INTEL_OUTPUT_DISPLAYPORT: | |
5139 | case INTEL_OUTPUT_HDMI: | |
5140 | case INTEL_OUTPUT_EDP: | |
5141 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5142 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5143 | case INTEL_OUTPUT_DP_MST: |
5144 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5145 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5146 | case INTEL_OUTPUT_ANALOG: |
5147 | return POWER_DOMAIN_PORT_CRT; | |
5148 | case INTEL_OUTPUT_DSI: | |
5149 | return POWER_DOMAIN_PORT_DSI; | |
5150 | default: | |
5151 | return POWER_DOMAIN_PORT_OTHER; | |
5152 | } | |
5153 | } | |
5154 | ||
25f78f58 VS |
5155 | enum intel_display_power_domain |
5156 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) | |
5157 | { | |
5158 | struct drm_device *dev = intel_encoder->base.dev; | |
5159 | struct intel_digital_port *intel_dig_port; | |
5160 | ||
5161 | switch (intel_encoder->type) { | |
5162 | case INTEL_OUTPUT_UNKNOWN: | |
651174a4 ID |
5163 | case INTEL_OUTPUT_HDMI: |
5164 | /* | |
5165 | * Only DDI platforms should ever use these output types. | |
5166 | * We can get here after the HDMI detect code has already set | |
5167 | * the type of the shared encoder. Since we can't be sure | |
5168 | * what's the status of the given connectors, play safe and | |
5169 | * run the DP detection too. | |
5170 | */ | |
25f78f58 VS |
5171 | WARN_ON_ONCE(!HAS_DDI(dev)); |
5172 | case INTEL_OUTPUT_DISPLAYPORT: | |
5173 | case INTEL_OUTPUT_EDP: | |
5174 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
5175 | return port_to_aux_power_domain(intel_dig_port->port); | |
5176 | case INTEL_OUTPUT_DP_MST: | |
5177 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5178 | return port_to_aux_power_domain(intel_dig_port->port); | |
5179 | default: | |
b9fec167 | 5180 | MISSING_CASE(intel_encoder->type); |
25f78f58 VS |
5181 | return POWER_DOMAIN_AUX_A; |
5182 | } | |
5183 | } | |
5184 | ||
74bff5f9 ML |
5185 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc, |
5186 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5187 | { |
319be8ae | 5188 | struct drm_device *dev = crtc->dev; |
74bff5f9 | 5189 | struct drm_encoder *encoder; |
319be8ae ID |
5190 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
5191 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca | 5192 | unsigned long mask; |
74bff5f9 | 5193 | enum transcoder transcoder = crtc_state->cpu_transcoder; |
77d22dca | 5194 | |
74bff5f9 | 5195 | if (!crtc_state->base.active) |
292b990e ML |
5196 | return 0; |
5197 | ||
77d22dca ID |
5198 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5199 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
74bff5f9 ML |
5200 | if (crtc_state->pch_pfit.enabled || |
5201 | crtc_state->pch_pfit.force_thru) | |
77d22dca ID |
5202 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5203 | ||
74bff5f9 ML |
5204 | drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) { |
5205 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); | |
5206 | ||
319be8ae | 5207 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); |
74bff5f9 | 5208 | } |
319be8ae | 5209 | |
15e7ec29 ML |
5210 | if (crtc_state->shared_dpll) |
5211 | mask |= BIT(POWER_DOMAIN_PLLS); | |
5212 | ||
77d22dca ID |
5213 | return mask; |
5214 | } | |
5215 | ||
74bff5f9 ML |
5216 | static unsigned long |
5217 | modeset_get_crtc_power_domains(struct drm_crtc *crtc, | |
5218 | struct intel_crtc_state *crtc_state) | |
77d22dca | 5219 | { |
292b990e ML |
5220 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5221 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5222 | enum intel_display_power_domain domain; | |
5223 | unsigned long domains, new_domains, old_domains; | |
77d22dca | 5224 | |
292b990e | 5225 | old_domains = intel_crtc->enabled_power_domains; |
74bff5f9 ML |
5226 | intel_crtc->enabled_power_domains = new_domains = |
5227 | get_crtc_power_domains(crtc, crtc_state); | |
77d22dca | 5228 | |
292b990e ML |
5229 | domains = new_domains & ~old_domains; |
5230 | ||
5231 | for_each_power_domain(domain, domains) | |
5232 | intel_display_power_get(dev_priv, domain); | |
5233 | ||
5234 | return old_domains & ~new_domains; | |
5235 | } | |
5236 | ||
5237 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5238 | unsigned long domains) | |
5239 | { | |
5240 | enum intel_display_power_domain domain; | |
5241 | ||
5242 | for_each_power_domain(domain, domains) | |
5243 | intel_display_power_put(dev_priv, domain); | |
5244 | } | |
77d22dca | 5245 | |
adafdc6f MK |
5246 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5247 | { | |
5248 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5249 | ||
5250 | if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5251 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
5252 | return max_cdclk_freq; | |
5253 | else if (IS_CHERRYVIEW(dev_priv)) | |
5254 | return max_cdclk_freq*95/100; | |
5255 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5256 | return 2*max_cdclk_freq*90/100; | |
5257 | else | |
5258 | return max_cdclk_freq*90/100; | |
5259 | } | |
5260 | ||
560a7ae4 DL |
5261 | static void intel_update_max_cdclk(struct drm_device *dev) |
5262 | { | |
5263 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5264 | ||
ef11bdb3 | 5265 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
560a7ae4 DL |
5266 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
5267 | ||
5268 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) | |
5269 | dev_priv->max_cdclk_freq = 675000; | |
5270 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) | |
5271 | dev_priv->max_cdclk_freq = 540000; | |
5272 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) | |
5273 | dev_priv->max_cdclk_freq = 450000; | |
5274 | else | |
5275 | dev_priv->max_cdclk_freq = 337500; | |
281c114f MR |
5276 | } else if (IS_BROXTON(dev)) { |
5277 | dev_priv->max_cdclk_freq = 624000; | |
560a7ae4 DL |
5278 | } else if (IS_BROADWELL(dev)) { |
5279 | /* | |
5280 | * FIXME with extra cooling we can allow | |
5281 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5282 | * How can we know if extra cooling is | |
5283 | * available? PCI ID, VTB, something else? | |
5284 | */ | |
5285 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5286 | dev_priv->max_cdclk_freq = 450000; | |
5287 | else if (IS_BDW_ULX(dev)) | |
5288 | dev_priv->max_cdclk_freq = 450000; | |
5289 | else if (IS_BDW_ULT(dev)) | |
5290 | dev_priv->max_cdclk_freq = 540000; | |
5291 | else | |
5292 | dev_priv->max_cdclk_freq = 675000; | |
0904deaf MK |
5293 | } else if (IS_CHERRYVIEW(dev)) { |
5294 | dev_priv->max_cdclk_freq = 320000; | |
560a7ae4 DL |
5295 | } else if (IS_VALLEYVIEW(dev)) { |
5296 | dev_priv->max_cdclk_freq = 400000; | |
5297 | } else { | |
5298 | /* otherwise assume cdclk is fixed */ | |
5299 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5300 | } | |
5301 | ||
adafdc6f MK |
5302 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5303 | ||
560a7ae4 DL |
5304 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5305 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5306 | |
5307 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5308 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5309 | } |
5310 | ||
5311 | static void intel_update_cdclk(struct drm_device *dev) | |
5312 | { | |
5313 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5314 | ||
5315 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
5316 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5317 | dev_priv->cdclk_freq); | |
5318 | ||
5319 | /* | |
b5d99ff9 VS |
5320 | * 9:0 CMBUS [sic] CDCLK frequency (cdfreq): |
5321 | * Programmng [sic] note: bit[9:2] should be programmed to the number | |
5322 | * of cdclk that generates 4MHz reference clock freq which is used to | |
5323 | * generate GMBus clock. This will vary with the cdclk freq. | |
560a7ae4 | 5324 | */ |
b5d99ff9 | 5325 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
560a7ae4 | 5326 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); |
560a7ae4 DL |
5327 | |
5328 | if (dev_priv->max_cdclk_freq == 0) | |
5329 | intel_update_max_cdclk(dev); | |
5330 | } | |
5331 | ||
92891e45 VS |
5332 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ |
5333 | static int skl_cdclk_decimal(int cdclk) | |
5334 | { | |
5335 | return DIV_ROUND_CLOSEST(cdclk - 1000, 500); | |
5336 | } | |
5337 | ||
9ef56154 | 5338 | static void broxton_set_cdclk(struct drm_i915_private *dev_priv, int cdclk) |
f8437dd1 | 5339 | { |
f8437dd1 VK |
5340 | uint32_t divider; |
5341 | uint32_t ratio; | |
9ef56154 | 5342 | uint32_t current_cdclk; |
f8437dd1 VK |
5343 | int ret; |
5344 | ||
5345 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ | |
9ef56154 | 5346 | switch (cdclk) { |
f8437dd1 VK |
5347 | case 144000: |
5348 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
5349 | ratio = BXT_DE_PLL_RATIO(60); | |
5350 | break; | |
5351 | case 288000: | |
5352 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
5353 | ratio = BXT_DE_PLL_RATIO(60); | |
5354 | break; | |
5355 | case 384000: | |
5356 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
5357 | ratio = BXT_DE_PLL_RATIO(60); | |
5358 | break; | |
5359 | case 576000: | |
5360 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5361 | ratio = BXT_DE_PLL_RATIO(60); | |
5362 | break; | |
5363 | case 624000: | |
5364 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5365 | ratio = BXT_DE_PLL_RATIO(65); | |
5366 | break; | |
5367 | case 19200: | |
5368 | /* | |
5369 | * Bypass frequency with DE PLL disabled. Init ratio, divider | |
5370 | * to suppress GCC warning. | |
5371 | */ | |
5372 | ratio = 0; | |
5373 | divider = 0; | |
5374 | break; | |
5375 | default: | |
9ef56154 | 5376 | DRM_ERROR("unsupported CDCLK freq %d", cdclk); |
f8437dd1 VK |
5377 | |
5378 | return; | |
5379 | } | |
5380 | ||
5381 | mutex_lock(&dev_priv->rps.hw_lock); | |
5382 | /* Inform power controller of upcoming frequency change */ | |
5383 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5384 | 0x80000000); | |
5385 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5386 | ||
5387 | if (ret) { | |
5388 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
9ef56154 | 5389 | ret, cdclk); |
f8437dd1 VK |
5390 | return; |
5391 | } | |
5392 | ||
9ef56154 | 5393 | current_cdclk = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; |
f8437dd1 | 5394 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ |
9ef56154 | 5395 | current_cdclk = current_cdclk * 500 + 1000; |
f8437dd1 VK |
5396 | |
5397 | /* | |
5398 | * DE PLL has to be disabled when | |
5399 | * - setting to 19.2MHz (bypass, PLL isn't used) | |
5400 | * - before setting to 624MHz (PLL needs toggling) | |
5401 | * - before setting to any frequency from 624MHz (PLL needs toggling) | |
5402 | */ | |
9ef56154 VS |
5403 | if (cdclk == 19200 || cdclk == 624000 || |
5404 | current_cdclk == 624000) { | |
f8437dd1 VK |
5405 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); |
5406 | /* Timeout 200us */ | |
5407 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), | |
5408 | 1)) | |
5409 | DRM_ERROR("timout waiting for DE PLL unlock\n"); | |
5410 | } | |
5411 | ||
9ef56154 | 5412 | if (cdclk != 19200) { |
f8437dd1 VK |
5413 | uint32_t val; |
5414 | ||
5415 | val = I915_READ(BXT_DE_PLL_CTL); | |
5416 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5417 | val |= ratio; | |
5418 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
5419 | ||
5420 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5421 | /* Timeout 200us */ | |
5422 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) | |
5423 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
5424 | ||
b8e75705 | 5425 | val = divider | skl_cdclk_decimal(cdclk); |
7fe62757 VS |
5426 | /* |
5427 | * FIXME if only the cd2x divider needs changing, it could be done | |
5428 | * without shutting off the pipe (if only one pipe is active). | |
5429 | */ | |
5430 | val |= BXT_CDCLK_CD2X_PIPE_NONE; | |
f8437dd1 VK |
5431 | /* |
5432 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5433 | * enable otherwise. | |
5434 | */ | |
9ef56154 | 5435 | if (cdclk >= 500000) |
f8437dd1 | 5436 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; |
f8437dd1 VK |
5437 | I915_WRITE(CDCLK_CTL, val); |
5438 | } | |
5439 | ||
5440 | mutex_lock(&dev_priv->rps.hw_lock); | |
5441 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
9ef56154 | 5442 | DIV_ROUND_UP(cdclk, 25000)); |
f8437dd1 VK |
5443 | mutex_unlock(&dev_priv->rps.hw_lock); |
5444 | ||
5445 | if (ret) { | |
5446 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
9ef56154 | 5447 | ret, cdclk); |
f8437dd1 VK |
5448 | return; |
5449 | } | |
5450 | ||
c6c4696f | 5451 | intel_update_cdclk(dev_priv->dev); |
f8437dd1 VK |
5452 | } |
5453 | ||
c2e001ef ID |
5454 | static bool broxton_cdclk_is_enabled(struct drm_i915_private *dev_priv) |
5455 | { | |
5456 | if (!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE)) | |
5457 | return false; | |
5458 | ||
5459 | /* TODO: Check for a valid CDCLK rate */ | |
5460 | ||
5461 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_REQUEST)) { | |
5462 | DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power not requested\n"); | |
5463 | ||
5464 | return false; | |
5465 | } | |
5466 | ||
5467 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) { | |
5468 | DRM_DEBUG_DRIVER("CDCLK enabled, but DBUF power hasn't settled\n"); | |
5469 | ||
5470 | return false; | |
5471 | } | |
5472 | ||
5473 | return true; | |
5474 | } | |
5475 | ||
adc7f04b ID |
5476 | bool broxton_cdclk_verify_state(struct drm_i915_private *dev_priv) |
5477 | { | |
5478 | return broxton_cdclk_is_enabled(dev_priv); | |
5479 | } | |
5480 | ||
c6c4696f | 5481 | void broxton_init_cdclk(struct drm_i915_private *dev_priv) |
f8437dd1 | 5482 | { |
f8437dd1 | 5483 | /* check if cd clock is enabled */ |
c2e001ef ID |
5484 | if (broxton_cdclk_is_enabled(dev_priv)) { |
5485 | DRM_DEBUG_KMS("CDCLK already enabled, won't reprogram it\n"); | |
f8437dd1 VK |
5486 | return; |
5487 | } | |
5488 | ||
c2e001ef ID |
5489 | DRM_DEBUG_KMS("CDCLK not enabled, enabling it\n"); |
5490 | ||
f8437dd1 VK |
5491 | /* |
5492 | * FIXME: | |
5493 | * - The initial CDCLK needs to be read from VBT. | |
5494 | * Need to make this change after VBT has changes for BXT. | |
5495 | * - check if setting the max (or any) cdclk freq is really necessary | |
5496 | * here, it belongs to modeset time | |
5497 | */ | |
c6c4696f | 5498 | broxton_set_cdclk(dev_priv, 624000); |
f8437dd1 VK |
5499 | |
5500 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
22e02c0b VS |
5501 | POSTING_READ(DBUF_CTL); |
5502 | ||
f8437dd1 VK |
5503 | udelay(10); |
5504 | ||
5505 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5506 | DRM_ERROR("DBuf power enable timeout!\n"); | |
5507 | } | |
5508 | ||
c6c4696f | 5509 | void broxton_uninit_cdclk(struct drm_i915_private *dev_priv) |
f8437dd1 | 5510 | { |
f8437dd1 | 5511 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); |
22e02c0b VS |
5512 | POSTING_READ(DBUF_CTL); |
5513 | ||
f8437dd1 VK |
5514 | udelay(10); |
5515 | ||
5516 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5517 | DRM_ERROR("DBuf power disable timeout!\n"); | |
5518 | ||
5519 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ | |
c6c4696f | 5520 | broxton_set_cdclk(dev_priv, 19200); |
f8437dd1 VK |
5521 | } |
5522 | ||
5d96d8af DL |
5523 | static const struct skl_cdclk_entry { |
5524 | unsigned int freq; | |
5525 | unsigned int vco; | |
5526 | } skl_cdclk_frequencies[] = { | |
5527 | { .freq = 308570, .vco = 8640 }, | |
5528 | { .freq = 337500, .vco = 8100 }, | |
5529 | { .freq = 432000, .vco = 8640 }, | |
5530 | { .freq = 450000, .vco = 8100 }, | |
5531 | { .freq = 540000, .vco = 8100 }, | |
5532 | { .freq = 617140, .vco = 8640 }, | |
5533 | { .freq = 675000, .vco = 8100 }, | |
5534 | }; | |
5535 | ||
5d96d8af DL |
5536 | static unsigned int skl_cdclk_get_vco(unsigned int freq) |
5537 | { | |
5538 | unsigned int i; | |
5539 | ||
5540 | for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) { | |
5541 | const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i]; | |
5542 | ||
5543 | if (e->freq == freq) | |
5544 | return e->vco; | |
5545 | } | |
5546 | ||
5547 | return 8100; | |
5548 | } | |
5549 | ||
5550 | static void | |
3861fc60 | 5551 | skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) |
5d96d8af | 5552 | { |
9ef56154 | 5553 | int min_cdclk; |
5d96d8af DL |
5554 | u32 val; |
5555 | ||
5556 | /* select the minimum CDCLK before enabling DPLL 0 */ | |
3861fc60 | 5557 | if (vco == 8640) |
9ef56154 | 5558 | min_cdclk = 308570; |
5d96d8af | 5559 | else |
9ef56154 | 5560 | min_cdclk = 337500; |
5d96d8af | 5561 | |
9ef56154 | 5562 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk); |
5d96d8af DL |
5563 | I915_WRITE(CDCLK_CTL, val); |
5564 | POSTING_READ(CDCLK_CTL); | |
5565 | ||
5566 | /* | |
5567 | * We always enable DPLL0 with the lowest link rate possible, but still | |
5568 | * taking into account the VCO required to operate the eDP panel at the | |
5569 | * desired frequency. The usual DP link rates operate with a VCO of | |
5570 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
5571 | * The modeset code is responsible for the selection of the exact link | |
5572 | * rate later on, with the constraint of choosing a frequency that | |
5573 | * works with required_vco. | |
5574 | */ | |
5575 | val = I915_READ(DPLL_CTRL1); | |
5576 | ||
5577 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5578 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
5579 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
3861fc60 | 5580 | if (vco == 8640) |
5d96d8af DL |
5581 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, |
5582 | SKL_DPLL0); | |
5583 | else | |
5584 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
5585 | SKL_DPLL0); | |
5586 | ||
5587 | I915_WRITE(DPLL_CTRL1, val); | |
5588 | POSTING_READ(DPLL_CTRL1); | |
5589 | ||
5590 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
5591 | ||
5592 | if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) | |
5593 | DRM_ERROR("DPLL0 not locked\n"); | |
5594 | } | |
5595 | ||
430e05de VS |
5596 | static void |
5597 | skl_dpll0_disable(struct drm_i915_private *dev_priv) | |
5598 | { | |
5599 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
5600 | if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) | |
5601 | DRM_ERROR("Couldn't disable DPLL0\n"); | |
5602 | } | |
5603 | ||
5d96d8af DL |
5604 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) |
5605 | { | |
5606 | int ret; | |
5607 | u32 val; | |
5608 | ||
5609 | /* inform PCU we want to change CDCLK */ | |
5610 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
5611 | mutex_lock(&dev_priv->rps.hw_lock); | |
5612 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
5613 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5614 | ||
5615 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
5616 | } | |
5617 | ||
5618 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
5619 | { | |
5620 | unsigned int i; | |
5621 | ||
5622 | for (i = 0; i < 15; i++) { | |
5623 | if (skl_cdclk_pcu_ready(dev_priv)) | |
5624 | return true; | |
5625 | udelay(10); | |
5626 | } | |
5627 | ||
5628 | return false; | |
5629 | } | |
5630 | ||
9ef56154 | 5631 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, int cdclk) |
5d96d8af | 5632 | { |
560a7ae4 | 5633 | struct drm_device *dev = dev_priv->dev; |
5d96d8af DL |
5634 | u32 freq_select, pcu_ack; |
5635 | ||
9ef56154 | 5636 | DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", cdclk); |
5d96d8af DL |
5637 | |
5638 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
5639 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
5640 | return; | |
5641 | } | |
5642 | ||
5643 | /* set CDCLK_CTL */ | |
9ef56154 | 5644 | switch (cdclk) { |
5d96d8af DL |
5645 | case 450000: |
5646 | case 432000: | |
5647 | freq_select = CDCLK_FREQ_450_432; | |
5648 | pcu_ack = 1; | |
5649 | break; | |
5650 | case 540000: | |
5651 | freq_select = CDCLK_FREQ_540; | |
5652 | pcu_ack = 2; | |
5653 | break; | |
5654 | case 308570: | |
5655 | case 337500: | |
5656 | default: | |
5657 | freq_select = CDCLK_FREQ_337_308; | |
5658 | pcu_ack = 0; | |
5659 | break; | |
5660 | case 617140: | |
5661 | case 675000: | |
5662 | freq_select = CDCLK_FREQ_675_617; | |
5663 | pcu_ack = 3; | |
5664 | break; | |
5665 | } | |
5666 | ||
9ef56154 | 5667 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk)); |
5d96d8af DL |
5668 | POSTING_READ(CDCLK_CTL); |
5669 | ||
5670 | /* inform PCU of the change */ | |
5671 | mutex_lock(&dev_priv->rps.hw_lock); | |
5672 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
5673 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 DL |
5674 | |
5675 | intel_update_cdclk(dev); | |
5d96d8af DL |
5676 | } |
5677 | ||
5678 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
5679 | { | |
5680 | /* disable DBUF power */ | |
5681 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
5682 | POSTING_READ(DBUF_CTL); | |
5683 | ||
5684 | udelay(10); | |
5685 | ||
5686 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5687 | DRM_ERROR("DBuf power disable timeout\n"); | |
5688 | ||
430e05de | 5689 | skl_dpll0_disable(dev_priv); |
5d96d8af DL |
5690 | } |
5691 | ||
5692 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
5693 | { | |
3861fc60 | 5694 | unsigned int vco; |
5d96d8af | 5695 | |
39d9b85a GW |
5696 | /* DPLL0 not enabled (happens on early BIOS versions) */ |
5697 | if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) { | |
5698 | /* enable DPLL0 */ | |
3861fc60 VS |
5699 | vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); |
5700 | skl_dpll0_enable(dev_priv, vco); | |
5d96d8af DL |
5701 | } |
5702 | ||
5d96d8af DL |
5703 | /* set CDCLK to the frequency the BIOS chose */ |
5704 | skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); | |
5705 | ||
5706 | /* enable DBUF power */ | |
5707 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
5708 | POSTING_READ(DBUF_CTL); | |
5709 | ||
5710 | udelay(10); | |
5711 | ||
5712 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5713 | DRM_ERROR("DBuf power enable timeout\n"); | |
5714 | } | |
5715 | ||
c73666f3 SK |
5716 | int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
5717 | { | |
5718 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
5719 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
5720 | int freq = dev_priv->skl_boot_cdclk; | |
5721 | ||
f1b391a5 SK |
5722 | /* |
5723 | * check if the pre-os intialized the display | |
5724 | * There is SWF18 scratchpad register defined which is set by the | |
5725 | * pre-os which can be used by the OS drivers to check the status | |
5726 | */ | |
5727 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
5728 | goto sanitize; | |
5729 | ||
c73666f3 SK |
5730 | /* Is PLL enabled and locked ? */ |
5731 | if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK))) | |
5732 | goto sanitize; | |
5733 | ||
5734 | /* DPLL okay; verify the cdclock | |
5735 | * | |
5736 | * Noticed in some instances that the freq selection is correct but | |
5737 | * decimal part is programmed wrong from BIOS where pre-os does not | |
5738 | * enable display. Verify the same as well. | |
5739 | */ | |
5740 | if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq))) | |
5741 | /* All well; nothing to sanitize */ | |
5742 | return false; | |
5743 | sanitize: | |
5744 | /* | |
5745 | * As of now initialize with max cdclk till | |
5746 | * we get dynamic cdclk support | |
5747 | * */ | |
5748 | dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq; | |
5749 | skl_init_cdclk(dev_priv); | |
5750 | ||
5751 | /* we did have to sanitize */ | |
5752 | return true; | |
5753 | } | |
5754 | ||
30a970c6 JB |
5755 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5756 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5757 | { | |
5758 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5759 | u32 val, cmd; | |
5760 | ||
164dfd28 VK |
5761 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5762 | != dev_priv->cdclk_freq); | |
d60c4473 | 5763 | |
dfcab17e | 5764 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5765 | cmd = 2; |
dfcab17e | 5766 | else if (cdclk == 266667) |
30a970c6 JB |
5767 | cmd = 1; |
5768 | else | |
5769 | cmd = 0; | |
5770 | ||
5771 | mutex_lock(&dev_priv->rps.hw_lock); | |
5772 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5773 | val &= ~DSPFREQGUAR_MASK; | |
5774 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5775 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5776 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5777 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5778 | 50)) { | |
5779 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5780 | } | |
5781 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5782 | ||
54433e91 VS |
5783 | mutex_lock(&dev_priv->sb_lock); |
5784 | ||
dfcab17e | 5785 | if (cdclk == 400000) { |
6bcda4f0 | 5786 | u32 divider; |
30a970c6 | 5787 | |
6bcda4f0 | 5788 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 5789 | |
30a970c6 JB |
5790 | /* adjust cdclk divider */ |
5791 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
87d5d259 | 5792 | val &= ~CCK_FREQUENCY_VALUES; |
30a970c6 JB |
5793 | val |= divider; |
5794 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5795 | |
5796 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
87d5d259 | 5797 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
a877e801 VS |
5798 | 50)) |
5799 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5800 | } |
5801 | ||
30a970c6 JB |
5802 | /* adjust self-refresh exit latency value */ |
5803 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5804 | val &= ~0x7f; | |
5805 | ||
5806 | /* | |
5807 | * For high bandwidth configs, we set a higher latency in the bunit | |
5808 | * so that the core display fetch happens in time to avoid underruns. | |
5809 | */ | |
dfcab17e | 5810 | if (cdclk == 400000) |
30a970c6 JB |
5811 | val |= 4500 / 250; /* 4.5 usec */ |
5812 | else | |
5813 | val |= 3000 / 250; /* 3.0 usec */ | |
5814 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 5815 | |
a580516d | 5816 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5817 | |
b6283055 | 5818 | intel_update_cdclk(dev); |
30a970c6 JB |
5819 | } |
5820 | ||
383c5a6a VS |
5821 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5822 | { | |
5823 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5824 | u32 val, cmd; | |
5825 | ||
164dfd28 VK |
5826 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5827 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5828 | |
5829 | switch (cdclk) { | |
383c5a6a VS |
5830 | case 333333: |
5831 | case 320000: | |
383c5a6a | 5832 | case 266667: |
383c5a6a | 5833 | case 200000: |
383c5a6a VS |
5834 | break; |
5835 | default: | |
5f77eeb0 | 5836 | MISSING_CASE(cdclk); |
383c5a6a VS |
5837 | return; |
5838 | } | |
5839 | ||
9d0d3fda VS |
5840 | /* |
5841 | * Specs are full of misinformation, but testing on actual | |
5842 | * hardware has shown that we just need to write the desired | |
5843 | * CCK divider into the Punit register. | |
5844 | */ | |
5845 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5846 | ||
383c5a6a VS |
5847 | mutex_lock(&dev_priv->rps.hw_lock); |
5848 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5849 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5850 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5851 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5852 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5853 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5854 | 50)) { | |
5855 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5856 | } | |
5857 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5858 | ||
b6283055 | 5859 | intel_update_cdclk(dev); |
383c5a6a VS |
5860 | } |
5861 | ||
30a970c6 JB |
5862 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5863 | int max_pixclk) | |
5864 | { | |
6bcda4f0 | 5865 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 5866 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 5867 | |
30a970c6 JB |
5868 | /* |
5869 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
5870 | * 200MHz | |
5871 | * 267MHz | |
29dc7ef3 | 5872 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
5873 | * 400MHz (VLV only) |
5874 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
5875 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
5876 | * |
5877 | * We seem to get an unstable or solid color picture at 200MHz. | |
5878 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
5879 | * are off. | |
30a970c6 | 5880 | */ |
6cca3195 VS |
5881 | if (!IS_CHERRYVIEW(dev_priv) && |
5882 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 5883 | return 400000; |
6cca3195 | 5884 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 5885 | return freq_320; |
e37c67a1 | 5886 | else if (max_pixclk > 0) |
dfcab17e | 5887 | return 266667; |
e37c67a1 VS |
5888 | else |
5889 | return 200000; | |
30a970c6 JB |
5890 | } |
5891 | ||
c44deb6c | 5892 | static int broxton_calc_cdclk(int max_pixclk) |
f8437dd1 VK |
5893 | { |
5894 | /* | |
5895 | * FIXME: | |
f8437dd1 VK |
5896 | * - set 19.2MHz bypass frequency if there are no active pipes |
5897 | */ | |
760e1477 | 5898 | if (max_pixclk > 576000) |
f8437dd1 | 5899 | return 624000; |
760e1477 | 5900 | else if (max_pixclk > 384000) |
f8437dd1 | 5901 | return 576000; |
760e1477 | 5902 | else if (max_pixclk > 288000) |
f8437dd1 | 5903 | return 384000; |
760e1477 | 5904 | else if (max_pixclk > 144000) |
f8437dd1 VK |
5905 | return 288000; |
5906 | else | |
5907 | return 144000; | |
5908 | } | |
5909 | ||
e8788cbc | 5910 | /* Compute the max pixel clock for new configuration. */ |
a821fc46 ACO |
5911 | static int intel_mode_max_pixclk(struct drm_device *dev, |
5912 | struct drm_atomic_state *state) | |
30a970c6 | 5913 | { |
565602d7 ML |
5914 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
5915 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5916 | struct drm_crtc *crtc; | |
5917 | struct drm_crtc_state *crtc_state; | |
5918 | unsigned max_pixclk = 0, i; | |
5919 | enum pipe pipe; | |
30a970c6 | 5920 | |
565602d7 ML |
5921 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
5922 | sizeof(intel_state->min_pixclk)); | |
304603f4 | 5923 | |
565602d7 ML |
5924 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
5925 | int pixclk = 0; | |
5926 | ||
5927 | if (crtc_state->enable) | |
5928 | pixclk = crtc_state->adjusted_mode.crtc_clock; | |
304603f4 | 5929 | |
565602d7 | 5930 | intel_state->min_pixclk[i] = pixclk; |
30a970c6 JB |
5931 | } |
5932 | ||
565602d7 ML |
5933 | for_each_pipe(dev_priv, pipe) |
5934 | max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); | |
5935 | ||
30a970c6 JB |
5936 | return max_pixclk; |
5937 | } | |
5938 | ||
27c329ed | 5939 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 5940 | { |
27c329ed ML |
5941 | struct drm_device *dev = state->dev; |
5942 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5943 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
1a617b77 ML |
5944 | struct intel_atomic_state *intel_state = |
5945 | to_intel_atomic_state(state); | |
30a970c6 | 5946 | |
1a617b77 | 5947 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 5948 | valleyview_calc_cdclk(dev_priv, max_pixclk); |
0a9ab303 | 5949 | |
1a617b77 ML |
5950 | if (!intel_state->active_crtcs) |
5951 | intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); | |
5952 | ||
27c329ed ML |
5953 | return 0; |
5954 | } | |
304603f4 | 5955 | |
27c329ed ML |
5956 | static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state) |
5957 | { | |
4e5ca60f | 5958 | int max_pixclk = ilk_max_pixel_rate(state); |
1a617b77 ML |
5959 | struct intel_atomic_state *intel_state = |
5960 | to_intel_atomic_state(state); | |
85a96e7a | 5961 | |
1a617b77 | 5962 | intel_state->cdclk = intel_state->dev_cdclk = |
c44deb6c | 5963 | broxton_calc_cdclk(max_pixclk); |
85a96e7a | 5964 | |
1a617b77 | 5965 | if (!intel_state->active_crtcs) |
c44deb6c | 5966 | intel_state->dev_cdclk = broxton_calc_cdclk(0); |
1a617b77 | 5967 | |
27c329ed | 5968 | return 0; |
30a970c6 JB |
5969 | } |
5970 | ||
1e69cd74 VS |
5971 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
5972 | { | |
5973 | unsigned int credits, default_credits; | |
5974 | ||
5975 | if (IS_CHERRYVIEW(dev_priv)) | |
5976 | default_credits = PFI_CREDIT(12); | |
5977 | else | |
5978 | default_credits = PFI_CREDIT(8); | |
5979 | ||
bfa7df01 | 5980 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
1e69cd74 VS |
5981 | /* CHV suggested value is 31 or 63 */ |
5982 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 5983 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
5984 | else |
5985 | credits = PFI_CREDIT(15); | |
5986 | } else { | |
5987 | credits = default_credits; | |
5988 | } | |
5989 | ||
5990 | /* | |
5991 | * WA - write default credits before re-programming | |
5992 | * FIXME: should we also set the resend bit here? | |
5993 | */ | |
5994 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
5995 | default_credits); | |
5996 | ||
5997 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
5998 | credits | PFI_CREDIT_RESEND); | |
5999 | ||
6000 | /* | |
6001 | * FIXME is this guaranteed to clear | |
6002 | * immediately or should we poll for it? | |
6003 | */ | |
6004 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6005 | } | |
6006 | ||
27c329ed | 6007 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 6008 | { |
a821fc46 | 6009 | struct drm_device *dev = old_state->dev; |
30a970c6 | 6010 | struct drm_i915_private *dev_priv = dev->dev_private; |
1a617b77 ML |
6011 | struct intel_atomic_state *old_intel_state = |
6012 | to_intel_atomic_state(old_state); | |
6013 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
30a970c6 | 6014 | |
27c329ed ML |
6015 | /* |
6016 | * FIXME: We can end up here with all power domains off, yet | |
6017 | * with a CDCLK frequency other than the minimum. To account | |
6018 | * for this take the PIPE-A power domain, which covers the HW | |
6019 | * blocks needed for the following programming. This can be | |
6020 | * removed once it's guaranteed that we get here either with | |
6021 | * the minimum CDCLK set, or the required power domains | |
6022 | * enabled. | |
6023 | */ | |
6024 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6025 | |
27c329ed ML |
6026 | if (IS_CHERRYVIEW(dev)) |
6027 | cherryview_set_cdclk(dev, req_cdclk); | |
6028 | else | |
6029 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6030 | |
27c329ed | 6031 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6032 | |
27c329ed | 6033 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6034 | } |
6035 | ||
89b667f8 JB |
6036 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
6037 | { | |
6038 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6039 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
6040 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6041 | struct intel_encoder *encoder; | |
b95c5321 ML |
6042 | struct intel_crtc_state *pipe_config = |
6043 | to_intel_crtc_state(crtc->state); | |
89b667f8 | 6044 | int pipe = intel_crtc->pipe; |
89b667f8 | 6045 | |
53d9f4e9 | 6046 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6047 | return; |
6048 | ||
6e3c9717 | 6049 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6050 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6051 | |
6052 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6053 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6054 | |
c14b0485 VS |
6055 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
6056 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6057 | ||
6058 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6059 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6060 | } | |
6061 | ||
5b18e57c DV |
6062 | i9xx_set_pipeconf(intel_crtc); |
6063 | ||
89b667f8 | 6064 | intel_crtc->active = true; |
89b667f8 | 6065 | |
a72e4c9f | 6066 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6067 | |
89b667f8 JB |
6068 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6069 | if (encoder->pre_pll_enable) | |
6070 | encoder->pre_pll_enable(encoder); | |
6071 | ||
cd2d34d9 VS |
6072 | if (IS_CHERRYVIEW(dev)) { |
6073 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
6074 | chv_enable_pll(intel_crtc, intel_crtc->config); | |
6075 | } else { | |
6076 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6077 | vlv_enable_pll(intel_crtc, intel_crtc->config); | |
9d556c99 | 6078 | } |
89b667f8 JB |
6079 | |
6080 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6081 | if (encoder->pre_enable) | |
6082 | encoder->pre_enable(encoder); | |
6083 | ||
2dd24552 JB |
6084 | i9xx_pfit_enable(intel_crtc); |
6085 | ||
b95c5321 | 6086 | intel_color_load_luts(&pipe_config->base); |
63cbb074 | 6087 | |
caed361d | 6088 | intel_update_watermarks(crtc); |
e1fdc473 | 6089 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6090 | |
4b3a9526 VS |
6091 | assert_vblank_disabled(crtc); |
6092 | drm_crtc_vblank_on(crtc); | |
6093 | ||
f9b61ff6 DV |
6094 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6095 | encoder->enable(encoder); | |
89b667f8 JB |
6096 | } |
6097 | ||
f13c2ef3 DV |
6098 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6099 | { | |
6100 | struct drm_device *dev = crtc->base.dev; | |
6101 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6102 | ||
6e3c9717 ACO |
6103 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6104 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6105 | } |
6106 | ||
0b8765c6 | 6107 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
6108 | { |
6109 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6110 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6111 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6112 | struct intel_encoder *encoder; |
b95c5321 ML |
6113 | struct intel_crtc_state *pipe_config = |
6114 | to_intel_crtc_state(crtc->state); | |
cd2d34d9 | 6115 | enum pipe pipe = intel_crtc->pipe; |
79e53945 | 6116 | |
53d9f4e9 | 6117 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6118 | return; |
6119 | ||
f13c2ef3 DV |
6120 | i9xx_set_pll_dividers(intel_crtc); |
6121 | ||
6e3c9717 | 6122 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6123 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6124 | |
6125 | intel_set_pipe_timings(intel_crtc); | |
bc58be60 | 6126 | intel_set_pipe_src_size(intel_crtc); |
5b18e57c | 6127 | |
5b18e57c DV |
6128 | i9xx_set_pipeconf(intel_crtc); |
6129 | ||
f7abfe8b | 6130 | intel_crtc->active = true; |
6b383a7f | 6131 | |
4a3436e8 | 6132 | if (!IS_GEN2(dev)) |
a72e4c9f | 6133 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6134 | |
9d6d9f19 MK |
6135 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6136 | if (encoder->pre_enable) | |
6137 | encoder->pre_enable(encoder); | |
6138 | ||
f6736a1a DV |
6139 | i9xx_enable_pll(intel_crtc); |
6140 | ||
2dd24552 JB |
6141 | i9xx_pfit_enable(intel_crtc); |
6142 | ||
b95c5321 | 6143 | intel_color_load_luts(&pipe_config->base); |
63cbb074 | 6144 | |
f37fcc2a | 6145 | intel_update_watermarks(crtc); |
e1fdc473 | 6146 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6147 | |
4b3a9526 VS |
6148 | assert_vblank_disabled(crtc); |
6149 | drm_crtc_vblank_on(crtc); | |
6150 | ||
f9b61ff6 DV |
6151 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6152 | encoder->enable(encoder); | |
0b8765c6 | 6153 | } |
79e53945 | 6154 | |
87476d63 DV |
6155 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6156 | { | |
6157 | struct drm_device *dev = crtc->base.dev; | |
6158 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 6159 | |
6e3c9717 | 6160 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6161 | return; |
87476d63 | 6162 | |
328d8e82 | 6163 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6164 | |
328d8e82 DV |
6165 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6166 | I915_READ(PFIT_CONTROL)); | |
6167 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6168 | } |
6169 | ||
0b8765c6 JB |
6170 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6171 | { | |
6172 | struct drm_device *dev = crtc->dev; | |
6173 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6174 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 6175 | struct intel_encoder *encoder; |
0b8765c6 | 6176 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6177 | |
6304cd91 VS |
6178 | /* |
6179 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6180 | * wait for planes to fully turn off before disabling the pipe. | |
6181 | */ | |
90e83e53 ACO |
6182 | if (IS_GEN2(dev)) |
6183 | intel_wait_for_vblank(dev, pipe); | |
6304cd91 | 6184 | |
4b3a9526 VS |
6185 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6186 | encoder->disable(encoder); | |
6187 | ||
f9b61ff6 DV |
6188 | drm_crtc_vblank_off(crtc); |
6189 | assert_vblank_disabled(crtc); | |
6190 | ||
575f7ab7 | 6191 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6192 | |
87476d63 | 6193 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6194 | |
89b667f8 JB |
6195 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6196 | if (encoder->post_disable) | |
6197 | encoder->post_disable(encoder); | |
6198 | ||
a65347ba | 6199 | if (!intel_crtc->config->has_dsi_encoder) { |
076ed3b2 CML |
6200 | if (IS_CHERRYVIEW(dev)) |
6201 | chv_disable_pll(dev_priv, pipe); | |
6202 | else if (IS_VALLEYVIEW(dev)) | |
6203 | vlv_disable_pll(dev_priv, pipe); | |
6204 | else | |
1c4e0274 | 6205 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6206 | } |
0b8765c6 | 6207 | |
d6db995f VS |
6208 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6209 | if (encoder->post_pll_disable) | |
6210 | encoder->post_pll_disable(encoder); | |
6211 | ||
4a3436e8 | 6212 | if (!IS_GEN2(dev)) |
a72e4c9f | 6213 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
0b8765c6 JB |
6214 | } |
6215 | ||
b17d48e2 ML |
6216 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6217 | { | |
842e0307 | 6218 | struct intel_encoder *encoder; |
b17d48e2 ML |
6219 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6220 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6221 | enum intel_display_power_domain domain; | |
6222 | unsigned long domains; | |
6223 | ||
6224 | if (!intel_crtc->active) | |
6225 | return; | |
6226 | ||
a539205a | 6227 | if (to_intel_plane_state(crtc->primary->state)->visible) { |
fc32b1fd ML |
6228 | WARN_ON(intel_crtc->unpin_work); |
6229 | ||
2622a081 | 6230 | intel_pre_disable_primary_noatomic(crtc); |
54a41961 ML |
6231 | |
6232 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); | |
6233 | to_intel_plane_state(crtc->primary->state)->visible = false; | |
a539205a ML |
6234 | } |
6235 | ||
b17d48e2 | 6236 | dev_priv->display.crtc_disable(crtc); |
842e0307 ML |
6237 | |
6238 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was enabled, now disabled\n", | |
6239 | crtc->base.id); | |
6240 | ||
6241 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0); | |
6242 | crtc->state->active = false; | |
37d9078b | 6243 | intel_crtc->active = false; |
842e0307 ML |
6244 | crtc->enabled = false; |
6245 | crtc->state->connector_mask = 0; | |
6246 | crtc->state->encoder_mask = 0; | |
6247 | ||
6248 | for_each_encoder_on_crtc(crtc->dev, crtc, encoder) | |
6249 | encoder->base.crtc = NULL; | |
6250 | ||
58f9c0bc | 6251 | intel_fbc_disable(intel_crtc); |
37d9078b | 6252 | intel_update_watermarks(crtc); |
1f7457b1 | 6253 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6254 | |
6255 | domains = intel_crtc->enabled_power_domains; | |
6256 | for_each_power_domain(domain, domains) | |
6257 | intel_display_power_put(dev_priv, domain); | |
6258 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
6259 | |
6260 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
6261 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
6262 | } |
6263 | ||
6b72d486 ML |
6264 | /* |
6265 | * turn all crtc's off, but do not adjust state | |
6266 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6267 | */ | |
70e0bd74 | 6268 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6269 | { |
e2c8b870 | 6270 | struct drm_i915_private *dev_priv = to_i915(dev); |
70e0bd74 | 6271 | struct drm_atomic_state *state; |
e2c8b870 | 6272 | int ret; |
70e0bd74 | 6273 | |
e2c8b870 ML |
6274 | state = drm_atomic_helper_suspend(dev); |
6275 | ret = PTR_ERR_OR_ZERO(state); | |
70e0bd74 ML |
6276 | if (ret) |
6277 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
e2c8b870 ML |
6278 | else |
6279 | dev_priv->modeset_restore_state = state; | |
70e0bd74 | 6280 | return ret; |
ee7b9f93 JB |
6281 | } |
6282 | ||
ea5b213a | 6283 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6284 | { |
4ef69c7a | 6285 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6286 | |
ea5b213a CW |
6287 | drm_encoder_cleanup(encoder); |
6288 | kfree(intel_encoder); | |
7e7d76c3 JB |
6289 | } |
6290 | ||
0a91ca29 DV |
6291 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6292 | * internal consistency). */ | |
c0ead703 | 6293 | static void intel_connector_verify_state(struct intel_connector *connector) |
79e53945 | 6294 | { |
35dd3c64 ML |
6295 | struct drm_crtc *crtc = connector->base.state->crtc; |
6296 | ||
6297 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6298 | connector->base.base.id, | |
6299 | connector->base.name); | |
6300 | ||
0a91ca29 | 6301 | if (connector->get_hw_state(connector)) { |
e85376cb | 6302 | struct intel_encoder *encoder = connector->encoder; |
35dd3c64 | 6303 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 6304 | |
35dd3c64 ML |
6305 | I915_STATE_WARN(!crtc, |
6306 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6307 | |
35dd3c64 ML |
6308 | if (!crtc) |
6309 | return; | |
6310 | ||
6311 | I915_STATE_WARN(!crtc->state->active, | |
6312 | "connector is active, but attached crtc isn't\n"); | |
6313 | ||
e85376cb | 6314 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6315 | return; |
6316 | ||
e85376cb | 6317 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6318 | "atomic encoder doesn't match attached encoder\n"); |
6319 | ||
e85376cb | 6320 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6321 | "attached encoder crtc differs from connector crtc\n"); |
6322 | } else { | |
4d688a2a ML |
6323 | I915_STATE_WARN(crtc && crtc->state->active, |
6324 | "attached crtc is active, but connector isn't\n"); | |
35dd3c64 ML |
6325 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
6326 | "best encoder set without crtc!\n"); | |
0a91ca29 | 6327 | } |
79e53945 JB |
6328 | } |
6329 | ||
08d9bc92 ACO |
6330 | int intel_connector_init(struct intel_connector *connector) |
6331 | { | |
5350a031 | 6332 | drm_atomic_helper_connector_reset(&connector->base); |
08d9bc92 | 6333 | |
5350a031 | 6334 | if (!connector->base.state) |
08d9bc92 ACO |
6335 | return -ENOMEM; |
6336 | ||
08d9bc92 ACO |
6337 | return 0; |
6338 | } | |
6339 | ||
6340 | struct intel_connector *intel_connector_alloc(void) | |
6341 | { | |
6342 | struct intel_connector *connector; | |
6343 | ||
6344 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6345 | if (!connector) | |
6346 | return NULL; | |
6347 | ||
6348 | if (intel_connector_init(connector) < 0) { | |
6349 | kfree(connector); | |
6350 | return NULL; | |
6351 | } | |
6352 | ||
6353 | return connector; | |
6354 | } | |
6355 | ||
f0947c37 DV |
6356 | /* Simple connector->get_hw_state implementation for encoders that support only |
6357 | * one connector and no cloning and hence the encoder state determines the state | |
6358 | * of the connector. */ | |
6359 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6360 | { |
24929352 | 6361 | enum pipe pipe = 0; |
f0947c37 | 6362 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6363 | |
f0947c37 | 6364 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6365 | } |
6366 | ||
6d293983 | 6367 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6368 | { |
6d293983 ACO |
6369 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6370 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6371 | |
6372 | return 0; | |
6373 | } | |
6374 | ||
6d293983 | 6375 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6376 | struct intel_crtc_state *pipe_config) |
1857e1da | 6377 | { |
6d293983 ACO |
6378 | struct drm_atomic_state *state = pipe_config->base.state; |
6379 | struct intel_crtc *other_crtc; | |
6380 | struct intel_crtc_state *other_crtc_state; | |
6381 | ||
1857e1da DV |
6382 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6383 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6384 | if (pipe_config->fdi_lanes > 4) { | |
6385 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6386 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6387 | return -EINVAL; |
1857e1da DV |
6388 | } |
6389 | ||
bafb6553 | 6390 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6391 | if (pipe_config->fdi_lanes > 2) { |
6392 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6393 | pipe_config->fdi_lanes); | |
6d293983 | 6394 | return -EINVAL; |
1857e1da | 6395 | } else { |
6d293983 | 6396 | return 0; |
1857e1da DV |
6397 | } |
6398 | } | |
6399 | ||
6400 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6401 | return 0; |
1857e1da DV |
6402 | |
6403 | /* Ivybridge 3 pipe is really complicated */ | |
6404 | switch (pipe) { | |
6405 | case PIPE_A: | |
6d293983 | 6406 | return 0; |
1857e1da | 6407 | case PIPE_B: |
6d293983 ACO |
6408 | if (pipe_config->fdi_lanes <= 2) |
6409 | return 0; | |
6410 | ||
6411 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6412 | other_crtc_state = | |
6413 | intel_atomic_get_crtc_state(state, other_crtc); | |
6414 | if (IS_ERR(other_crtc_state)) | |
6415 | return PTR_ERR(other_crtc_state); | |
6416 | ||
6417 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6418 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6419 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6420 | return -EINVAL; |
1857e1da | 6421 | } |
6d293983 | 6422 | return 0; |
1857e1da | 6423 | case PIPE_C: |
251cc67c VS |
6424 | if (pipe_config->fdi_lanes > 2) { |
6425 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6426 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6427 | return -EINVAL; |
251cc67c | 6428 | } |
6d293983 ACO |
6429 | |
6430 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6431 | other_crtc_state = | |
6432 | intel_atomic_get_crtc_state(state, other_crtc); | |
6433 | if (IS_ERR(other_crtc_state)) | |
6434 | return PTR_ERR(other_crtc_state); | |
6435 | ||
6436 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6437 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6438 | return -EINVAL; |
1857e1da | 6439 | } |
6d293983 | 6440 | return 0; |
1857e1da DV |
6441 | default: |
6442 | BUG(); | |
6443 | } | |
6444 | } | |
6445 | ||
e29c22c0 DV |
6446 | #define RETRY 1 |
6447 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6448 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6449 | { |
1857e1da | 6450 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6451 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6452 | int lane, link_bw, fdi_dotclock, ret; |
6453 | bool needs_recompute = false; | |
877d48d5 | 6454 | |
e29c22c0 | 6455 | retry: |
877d48d5 DV |
6456 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6457 | * each output octet as 10 bits. The actual frequency | |
6458 | * is stored as a divider into a 100MHz clock, and the | |
6459 | * mode pixel clock is stored in units of 1KHz. | |
6460 | * Hence the bw of each lane in terms of the mode signal | |
6461 | * is: | |
6462 | */ | |
21a727b3 | 6463 | link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config); |
877d48d5 | 6464 | |
241bfc38 | 6465 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6466 | |
2bd89a07 | 6467 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6468 | pipe_config->pipe_bpp); |
6469 | ||
6470 | pipe_config->fdi_lanes = lane; | |
6471 | ||
2bd89a07 | 6472 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6473 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6474 | |
e3b247da | 6475 | ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config); |
6d293983 | 6476 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { |
e29c22c0 DV |
6477 | pipe_config->pipe_bpp -= 2*3; |
6478 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6479 | pipe_config->pipe_bpp); | |
6480 | needs_recompute = true; | |
6481 | pipe_config->bw_constrained = true; | |
6482 | ||
6483 | goto retry; | |
6484 | } | |
6485 | ||
6486 | if (needs_recompute) | |
6487 | return RETRY; | |
6488 | ||
6d293983 | 6489 | return ret; |
877d48d5 DV |
6490 | } |
6491 | ||
8cfb3407 VS |
6492 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6493 | struct intel_crtc_state *pipe_config) | |
6494 | { | |
6495 | if (pipe_config->pipe_bpp > 24) | |
6496 | return false; | |
6497 | ||
6498 | /* HSW can handle pixel rate up to cdclk? */ | |
2d1fe073 | 6499 | if (IS_HASWELL(dev_priv)) |
8cfb3407 VS |
6500 | return true; |
6501 | ||
6502 | /* | |
b432e5cf VS |
6503 | * We compare against max which means we must take |
6504 | * the increased cdclk requirement into account when | |
6505 | * calculating the new cdclk. | |
6506 | * | |
6507 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
6508 | */ |
6509 | return ilk_pipe_pixel_rate(pipe_config) <= | |
6510 | dev_priv->max_cdclk_freq * 95 / 100; | |
6511 | } | |
6512 | ||
42db64ef | 6513 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6514 | struct intel_crtc_state *pipe_config) |
42db64ef | 6515 | { |
8cfb3407 VS |
6516 | struct drm_device *dev = crtc->base.dev; |
6517 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6518 | ||
d330a953 | 6519 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
6520 | hsw_crtc_supports_ips(crtc) && |
6521 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
6522 | } |
6523 | ||
39acb4aa VS |
6524 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
6525 | { | |
6526 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
6527 | ||
6528 | /* GDG double wide on either pipe, otherwise pipe A only */ | |
6529 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6530 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
6531 | } | |
6532 | ||
a43f6e0f | 6533 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6534 | struct intel_crtc_state *pipe_config) |
79e53945 | 6535 | { |
a43f6e0f | 6536 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 6537 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c5f93b0 | 6538 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
89749350 | 6539 | |
ad3a4479 | 6540 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 6541 | if (INTEL_INFO(dev)->gen < 4) { |
39acb4aa | 6542 | int clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
cf532bb2 VS |
6543 | |
6544 | /* | |
39acb4aa | 6545 | * Enable double wide mode when the dot clock |
cf532bb2 | 6546 | * is > 90% of the (display) core speed. |
cf532bb2 | 6547 | */ |
39acb4aa VS |
6548 | if (intel_crtc_supports_double_wide(crtc) && |
6549 | adjusted_mode->crtc_clock > clock_limit) { | |
ad3a4479 | 6550 | clock_limit *= 2; |
cf532bb2 | 6551 | pipe_config->double_wide = true; |
ad3a4479 VS |
6552 | } |
6553 | ||
39acb4aa VS |
6554 | if (adjusted_mode->crtc_clock > clock_limit) { |
6555 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6556 | adjusted_mode->crtc_clock, clock_limit, | |
6557 | yesno(pipe_config->double_wide)); | |
e29c22c0 | 6558 | return -EINVAL; |
39acb4aa | 6559 | } |
2c07245f | 6560 | } |
89749350 | 6561 | |
1d1d0e27 VS |
6562 | /* |
6563 | * Pipe horizontal size must be even in: | |
6564 | * - DVO ganged mode | |
6565 | * - LVDS dual channel mode | |
6566 | * - Double wide pipe | |
6567 | */ | |
a93e255f | 6568 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6569 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6570 | pipe_config->pipe_src_w &= ~1; | |
6571 | ||
8693a824 DL |
6572 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6573 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6574 | */ |
6575 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
aad941d5 | 6576 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
e29c22c0 | 6577 | return -EINVAL; |
44f46b42 | 6578 | |
f5adf94e | 6579 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6580 | hsw_compute_ips_config(crtc, pipe_config); |
6581 | ||
877d48d5 | 6582 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6583 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6584 | |
cf5a15be | 6585 | return 0; |
79e53945 JB |
6586 | } |
6587 | ||
1652d19e VS |
6588 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6589 | { | |
6590 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6591 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
6592 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6593 | uint32_t linkrate; | |
6594 | ||
414355a7 | 6595 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) |
1652d19e | 6596 | return 24000; /* 24MHz is the cd freq with NSSC ref */ |
1652d19e VS |
6597 | |
6598 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
6599 | return 540000; | |
6600 | ||
6601 | linkrate = (I915_READ(DPLL_CTRL1) & | |
71cd8423 | 6602 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; |
1652d19e | 6603 | |
71cd8423 DL |
6604 | if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || |
6605 | linkrate == DPLL_CTRL1_LINK_RATE_1080) { | |
1652d19e VS |
6606 | /* vco 8640 */ |
6607 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6608 | case CDCLK_FREQ_450_432: | |
6609 | return 432000; | |
6610 | case CDCLK_FREQ_337_308: | |
6611 | return 308570; | |
6612 | case CDCLK_FREQ_675_617: | |
6613 | return 617140; | |
6614 | default: | |
6615 | WARN(1, "Unknown cd freq selection\n"); | |
6616 | } | |
6617 | } else { | |
6618 | /* vco 8100 */ | |
6619 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6620 | case CDCLK_FREQ_450_432: | |
6621 | return 450000; | |
6622 | case CDCLK_FREQ_337_308: | |
6623 | return 337500; | |
6624 | case CDCLK_FREQ_675_617: | |
6625 | return 675000; | |
6626 | default: | |
6627 | WARN(1, "Unknown cd freq selection\n"); | |
6628 | } | |
6629 | } | |
6630 | ||
6631 | /* error case, do as if DPLL0 isn't enabled */ | |
6632 | return 24000; | |
6633 | } | |
6634 | ||
acd3f3d3 BP |
6635 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
6636 | { | |
6637 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6638 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6639 | uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; | |
6640 | uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE); | |
6641 | int cdclk; | |
6642 | ||
6643 | if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE)) | |
6644 | return 19200; | |
6645 | ||
6646 | cdclk = 19200 * pll_ratio / 2; | |
6647 | ||
6648 | switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) { | |
6649 | case BXT_CDCLK_CD2X_DIV_SEL_1: | |
6650 | return cdclk; /* 576MHz or 624MHz */ | |
6651 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: | |
6652 | return cdclk * 2 / 3; /* 384MHz */ | |
6653 | case BXT_CDCLK_CD2X_DIV_SEL_2: | |
6654 | return cdclk / 2; /* 288MHz */ | |
6655 | case BXT_CDCLK_CD2X_DIV_SEL_4: | |
6656 | return cdclk / 4; /* 144MHz */ | |
6657 | } | |
6658 | ||
6659 | /* error case, do as if DE PLL isn't enabled */ | |
6660 | return 19200; | |
6661 | } | |
6662 | ||
1652d19e VS |
6663 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
6664 | { | |
6665 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6666 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6667 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6668 | ||
6669 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6670 | return 800000; | |
6671 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6672 | return 450000; | |
6673 | else if (freq == LCPLL_CLK_FREQ_450) | |
6674 | return 450000; | |
6675 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6676 | return 540000; | |
6677 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6678 | return 337500; | |
6679 | else | |
6680 | return 675000; | |
6681 | } | |
6682 | ||
6683 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6684 | { | |
6685 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6686 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6687 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6688 | ||
6689 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6690 | return 800000; | |
6691 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6692 | return 450000; | |
6693 | else if (freq == LCPLL_CLK_FREQ_450) | |
6694 | return 450000; | |
6695 | else if (IS_HSW_ULT(dev)) | |
6696 | return 337500; | |
6697 | else | |
6698 | return 540000; | |
79e53945 JB |
6699 | } |
6700 | ||
25eb05fc JB |
6701 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6702 | { | |
bfa7df01 VS |
6703 | return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", |
6704 | CCK_DISPLAY_CLOCK_CONTROL); | |
25eb05fc JB |
6705 | } |
6706 | ||
b37a6434 VS |
6707 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6708 | { | |
6709 | return 450000; | |
6710 | } | |
6711 | ||
e70236a8 JB |
6712 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6713 | { | |
6714 | return 400000; | |
6715 | } | |
79e53945 | 6716 | |
e70236a8 | 6717 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6718 | { |
e907f170 | 6719 | return 333333; |
e70236a8 | 6720 | } |
79e53945 | 6721 | |
e70236a8 JB |
6722 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6723 | { | |
6724 | return 200000; | |
6725 | } | |
79e53945 | 6726 | |
257a7ffc DV |
6727 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6728 | { | |
6729 | u16 gcfgc = 0; | |
6730 | ||
6731 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6732 | ||
6733 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6734 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6735 | return 266667; |
257a7ffc | 6736 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6737 | return 333333; |
257a7ffc | 6738 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6739 | return 444444; |
257a7ffc DV |
6740 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6741 | return 200000; | |
6742 | default: | |
6743 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6744 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6745 | return 133333; |
257a7ffc | 6746 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6747 | return 166667; |
257a7ffc DV |
6748 | } |
6749 | } | |
6750 | ||
e70236a8 JB |
6751 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6752 | { | |
6753 | u16 gcfgc = 0; | |
79e53945 | 6754 | |
e70236a8 JB |
6755 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6756 | ||
6757 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6758 | return 133333; |
e70236a8 JB |
6759 | else { |
6760 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6761 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6762 | return 333333; |
e70236a8 JB |
6763 | default: |
6764 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6765 | return 190000; | |
79e53945 | 6766 | } |
e70236a8 JB |
6767 | } |
6768 | } | |
6769 | ||
6770 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6771 | { | |
e907f170 | 6772 | return 266667; |
e70236a8 JB |
6773 | } |
6774 | ||
1b1d2716 | 6775 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 JB |
6776 | { |
6777 | u16 hpllcc = 0; | |
1b1d2716 | 6778 | |
65cd2b3f VS |
6779 | /* |
6780 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
6781 | * encoding is different :( | |
6782 | * FIXME is this the right way to detect 852GM/852GMV? | |
6783 | */ | |
6784 | if (dev->pdev->revision == 0x1) | |
6785 | return 133333; | |
6786 | ||
1b1d2716 VS |
6787 | pci_bus_read_config_word(dev->pdev->bus, |
6788 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
6789 | ||
e70236a8 JB |
6790 | /* Assume that the hardware is in the high speed state. This |
6791 | * should be the default. | |
6792 | */ | |
6793 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6794 | case GC_CLOCK_133_200: | |
1b1d2716 | 6795 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
6796 | case GC_CLOCK_100_200: |
6797 | return 200000; | |
6798 | case GC_CLOCK_166_250: | |
6799 | return 250000; | |
6800 | case GC_CLOCK_100_133: | |
e907f170 | 6801 | return 133333; |
1b1d2716 VS |
6802 | case GC_CLOCK_133_266: |
6803 | case GC_CLOCK_133_266_2: | |
6804 | case GC_CLOCK_166_266: | |
6805 | return 266667; | |
e70236a8 | 6806 | } |
79e53945 | 6807 | |
e70236a8 JB |
6808 | /* Shouldn't happen */ |
6809 | return 0; | |
6810 | } | |
79e53945 | 6811 | |
e70236a8 JB |
6812 | static int i830_get_display_clock_speed(struct drm_device *dev) |
6813 | { | |
e907f170 | 6814 | return 133333; |
79e53945 JB |
6815 | } |
6816 | ||
34edce2f VS |
6817 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
6818 | { | |
6819 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6820 | static const unsigned int blb_vco[8] = { | |
6821 | [0] = 3200000, | |
6822 | [1] = 4000000, | |
6823 | [2] = 5333333, | |
6824 | [3] = 4800000, | |
6825 | [4] = 6400000, | |
6826 | }; | |
6827 | static const unsigned int pnv_vco[8] = { | |
6828 | [0] = 3200000, | |
6829 | [1] = 4000000, | |
6830 | [2] = 5333333, | |
6831 | [3] = 4800000, | |
6832 | [4] = 2666667, | |
6833 | }; | |
6834 | static const unsigned int cl_vco[8] = { | |
6835 | [0] = 3200000, | |
6836 | [1] = 4000000, | |
6837 | [2] = 5333333, | |
6838 | [3] = 6400000, | |
6839 | [4] = 3333333, | |
6840 | [5] = 3566667, | |
6841 | [6] = 4266667, | |
6842 | }; | |
6843 | static const unsigned int elk_vco[8] = { | |
6844 | [0] = 3200000, | |
6845 | [1] = 4000000, | |
6846 | [2] = 5333333, | |
6847 | [3] = 4800000, | |
6848 | }; | |
6849 | static const unsigned int ctg_vco[8] = { | |
6850 | [0] = 3200000, | |
6851 | [1] = 4000000, | |
6852 | [2] = 5333333, | |
6853 | [3] = 6400000, | |
6854 | [4] = 2666667, | |
6855 | [5] = 4266667, | |
6856 | }; | |
6857 | const unsigned int *vco_table; | |
6858 | unsigned int vco; | |
6859 | uint8_t tmp = 0; | |
6860 | ||
6861 | /* FIXME other chipsets? */ | |
6862 | if (IS_GM45(dev)) | |
6863 | vco_table = ctg_vco; | |
6864 | else if (IS_G4X(dev)) | |
6865 | vco_table = elk_vco; | |
6866 | else if (IS_CRESTLINE(dev)) | |
6867 | vco_table = cl_vco; | |
6868 | else if (IS_PINEVIEW(dev)) | |
6869 | vco_table = pnv_vco; | |
6870 | else if (IS_G33(dev)) | |
6871 | vco_table = blb_vco; | |
6872 | else | |
6873 | return 0; | |
6874 | ||
6875 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
6876 | ||
6877 | vco = vco_table[tmp & 0x7]; | |
6878 | if (vco == 0) | |
6879 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
6880 | else | |
6881 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
6882 | ||
6883 | return vco; | |
6884 | } | |
6885 | ||
6886 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
6887 | { | |
6888 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6889 | uint16_t tmp = 0; | |
6890 | ||
6891 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6892 | ||
6893 | cdclk_sel = (tmp >> 12) & 0x1; | |
6894 | ||
6895 | switch (vco) { | |
6896 | case 2666667: | |
6897 | case 4000000: | |
6898 | case 5333333: | |
6899 | return cdclk_sel ? 333333 : 222222; | |
6900 | case 3200000: | |
6901 | return cdclk_sel ? 320000 : 228571; | |
6902 | default: | |
6903 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
6904 | return 222222; | |
6905 | } | |
6906 | } | |
6907 | ||
6908 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
6909 | { | |
6910 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
6911 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
6912 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
6913 | const uint8_t *div_table; | |
6914 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6915 | uint16_t tmp = 0; | |
6916 | ||
6917 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6918 | ||
6919 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
6920 | ||
6921 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
6922 | goto fail; | |
6923 | ||
6924 | switch (vco) { | |
6925 | case 3200000: | |
6926 | div_table = div_3200; | |
6927 | break; | |
6928 | case 4000000: | |
6929 | div_table = div_4000; | |
6930 | break; | |
6931 | case 5333333: | |
6932 | div_table = div_5333; | |
6933 | break; | |
6934 | default: | |
6935 | goto fail; | |
6936 | } | |
6937 | ||
6938 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
6939 | ||
caf4e252 | 6940 | fail: |
34edce2f VS |
6941 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
6942 | return 200000; | |
6943 | } | |
6944 | ||
6945 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
6946 | { | |
6947 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
6948 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
6949 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
6950 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
6951 | const uint8_t *div_table; | |
6952 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
6953 | uint16_t tmp = 0; | |
6954 | ||
6955 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
6956 | ||
6957 | cdclk_sel = (tmp >> 4) & 0x7; | |
6958 | ||
6959 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
6960 | goto fail; | |
6961 | ||
6962 | switch (vco) { | |
6963 | case 3200000: | |
6964 | div_table = div_3200; | |
6965 | break; | |
6966 | case 4000000: | |
6967 | div_table = div_4000; | |
6968 | break; | |
6969 | case 4800000: | |
6970 | div_table = div_4800; | |
6971 | break; | |
6972 | case 5333333: | |
6973 | div_table = div_5333; | |
6974 | break; | |
6975 | default: | |
6976 | goto fail; | |
6977 | } | |
6978 | ||
6979 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
6980 | ||
caf4e252 | 6981 | fail: |
34edce2f VS |
6982 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
6983 | return 190476; | |
6984 | } | |
6985 | ||
2c07245f | 6986 | static void |
a65851af | 6987 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 6988 | { |
a65851af VS |
6989 | while (*num > DATA_LINK_M_N_MASK || |
6990 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
6991 | *num >>= 1; |
6992 | *den >>= 1; | |
6993 | } | |
6994 | } | |
6995 | ||
a65851af VS |
6996 | static void compute_m_n(unsigned int m, unsigned int n, |
6997 | uint32_t *ret_m, uint32_t *ret_n) | |
6998 | { | |
6999 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7000 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7001 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7002 | } | |
7003 | ||
e69d0bc1 DV |
7004 | void |
7005 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7006 | int pixel_clock, int link_clock, | |
7007 | struct intel_link_m_n *m_n) | |
2c07245f | 7008 | { |
e69d0bc1 | 7009 | m_n->tu = 64; |
a65851af VS |
7010 | |
7011 | compute_m_n(bits_per_pixel * pixel_clock, | |
7012 | link_clock * nlanes * 8, | |
7013 | &m_n->gmch_m, &m_n->gmch_n); | |
7014 | ||
7015 | compute_m_n(pixel_clock, link_clock, | |
7016 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7017 | } |
7018 | ||
a7615030 CW |
7019 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7020 | { | |
d330a953 JN |
7021 | if (i915.panel_use_ssc >= 0) |
7022 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7023 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7024 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7025 | } |
7026 | ||
7429e9d4 | 7027 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7028 | { |
7df00d7a | 7029 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7030 | } |
f47709a9 | 7031 | |
7429e9d4 DV |
7032 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7033 | { | |
7034 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7035 | } |
7036 | ||
f47709a9 | 7037 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7038 | struct intel_crtc_state *crtc_state, |
9e2c8475 | 7039 | struct dpll *reduced_clock) |
a7516a05 | 7040 | { |
f47709a9 | 7041 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
7042 | u32 fp, fp2 = 0; |
7043 | ||
7044 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 7045 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7046 | if (reduced_clock) |
7429e9d4 | 7047 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7048 | } else { |
190f68c5 | 7049 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7050 | if (reduced_clock) |
7429e9d4 | 7051 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7052 | } |
7053 | ||
190f68c5 | 7054 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7055 | |
f47709a9 | 7056 | crtc->lowfreq_avail = false; |
a93e255f | 7057 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7058 | reduced_clock) { |
190f68c5 | 7059 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7060 | crtc->lowfreq_avail = true; |
a7516a05 | 7061 | } else { |
190f68c5 | 7062 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7063 | } |
7064 | } | |
7065 | ||
5e69f97f CML |
7066 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7067 | pipe) | |
89b667f8 JB |
7068 | { |
7069 | u32 reg_val; | |
7070 | ||
7071 | /* | |
7072 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7073 | * and set it to a reasonable value instead. | |
7074 | */ | |
ab3c759a | 7075 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7076 | reg_val &= 0xffffff00; |
7077 | reg_val |= 0x00000030; | |
ab3c759a | 7078 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7079 | |
ab3c759a | 7080 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7081 | reg_val &= 0x8cffffff; |
7082 | reg_val = 0x8c000000; | |
ab3c759a | 7083 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7084 | |
ab3c759a | 7085 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7086 | reg_val &= 0xffffff00; |
ab3c759a | 7087 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7088 | |
ab3c759a | 7089 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7090 | reg_val &= 0x00ffffff; |
7091 | reg_val |= 0xb0000000; | |
ab3c759a | 7092 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7093 | } |
7094 | ||
b551842d DV |
7095 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7096 | struct intel_link_m_n *m_n) | |
7097 | { | |
7098 | struct drm_device *dev = crtc->base.dev; | |
7099 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7100 | int pipe = crtc->pipe; | |
7101 | ||
e3b95f1e DV |
7102 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7103 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7104 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7105 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7106 | } |
7107 | ||
7108 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7109 | struct intel_link_m_n *m_n, |
7110 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7111 | { |
7112 | struct drm_device *dev = crtc->base.dev; | |
7113 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7114 | int pipe = crtc->pipe; | |
6e3c9717 | 7115 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7116 | |
7117 | if (INTEL_INFO(dev)->gen >= 5) { | |
7118 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7119 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7120 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7121 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7122 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7123 | * for gen < 8) and if DRRS is supported (to make sure the | |
7124 | * registers are not unnecessarily accessed). | |
7125 | */ | |
44395bfe | 7126 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 7127 | crtc->config->has_drrs) { |
f769cd24 VK |
7128 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7129 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7130 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7131 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7132 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7133 | } | |
b551842d | 7134 | } else { |
e3b95f1e DV |
7135 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7136 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7137 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7138 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7139 | } |
7140 | } | |
7141 | ||
fe3cd48d | 7142 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7143 | { |
fe3cd48d R |
7144 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7145 | ||
7146 | if (m_n == M1_N1) { | |
7147 | dp_m_n = &crtc->config->dp_m_n; | |
7148 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7149 | } else if (m_n == M2_N2) { | |
7150 | ||
7151 | /* | |
7152 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7153 | * needs to be programmed into M1_N1. | |
7154 | */ | |
7155 | dp_m_n = &crtc->config->dp_m2_n2; | |
7156 | } else { | |
7157 | DRM_ERROR("Unsupported divider value\n"); | |
7158 | return; | |
7159 | } | |
7160 | ||
6e3c9717 ACO |
7161 | if (crtc->config->has_pch_encoder) |
7162 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7163 | else |
fe3cd48d | 7164 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7165 | } |
7166 | ||
251ac862 DV |
7167 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7168 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 | 7169 | { |
03ed5cbf | 7170 | pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | |
cd2d34d9 | 7171 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
7172 | if (crtc->pipe != PIPE_A) |
7173 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
bdd4b6a6 | 7174 | |
cd2d34d9 | 7175 | /* DPLL not used with DSI, but still need the rest set up */ |
187a1c07 | 7176 | if (!pipe_config->has_dsi_encoder) |
cd2d34d9 VS |
7177 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | |
7178 | DPLL_EXT_BUFFER_ENABLE_VLV; | |
7179 | ||
03ed5cbf VS |
7180 | pipe_config->dpll_hw_state.dpll_md = |
7181 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
7182 | } | |
bdd4b6a6 | 7183 | |
03ed5cbf VS |
7184 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7185 | struct intel_crtc_state *pipe_config) | |
7186 | { | |
7187 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | | |
cd2d34d9 | 7188 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
03ed5cbf VS |
7189 | if (crtc->pipe != PIPE_A) |
7190 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7191 | ||
cd2d34d9 | 7192 | /* DPLL not used with DSI, but still need the rest set up */ |
187a1c07 | 7193 | if (!pipe_config->has_dsi_encoder) |
cd2d34d9 VS |
7194 | pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; |
7195 | ||
03ed5cbf VS |
7196 | pipe_config->dpll_hw_state.dpll_md = |
7197 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
bdd4b6a6 DV |
7198 | } |
7199 | ||
d288f65f | 7200 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7201 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7202 | { |
f47709a9 | 7203 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 7204 | struct drm_i915_private *dev_priv = dev->dev_private; |
cd2d34d9 | 7205 | enum pipe pipe = crtc->pipe; |
bdd4b6a6 | 7206 | u32 mdiv; |
a0c4da24 | 7207 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7208 | u32 coreclk, reg_val; |
a0c4da24 | 7209 | |
cd2d34d9 VS |
7210 | /* Enable Refclk */ |
7211 | I915_WRITE(DPLL(pipe), | |
7212 | pipe_config->dpll_hw_state.dpll & | |
7213 | ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); | |
7214 | ||
7215 | /* No need to actually set up the DPLL with DSI */ | |
7216 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7217 | return; | |
7218 | ||
a580516d | 7219 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7220 | |
d288f65f VS |
7221 | bestn = pipe_config->dpll.n; |
7222 | bestm1 = pipe_config->dpll.m1; | |
7223 | bestm2 = pipe_config->dpll.m2; | |
7224 | bestp1 = pipe_config->dpll.p1; | |
7225 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7226 | |
89b667f8 JB |
7227 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7228 | ||
7229 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7230 | if (pipe == PIPE_B) |
5e69f97f | 7231 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7232 | |
7233 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7234 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7235 | |
7236 | /* Disable target IRef on PLL */ | |
ab3c759a | 7237 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7238 | reg_val &= 0x00ffffff; |
ab3c759a | 7239 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7240 | |
7241 | /* Disable fast lock */ | |
ab3c759a | 7242 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7243 | |
7244 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7245 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7246 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7247 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7248 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7249 | |
7250 | /* | |
7251 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7252 | * but we don't support that). | |
7253 | * Note: don't use the DAC post divider as it seems unstable. | |
7254 | */ | |
7255 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7256 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7257 | |
a0c4da24 | 7258 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7259 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7260 | |
89b667f8 | 7261 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7262 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
7263 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
7264 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7265 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7266 | 0x009f0003); |
89b667f8 | 7267 | else |
ab3c759a | 7268 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7269 | 0x00d0000f); |
7270 | ||
681a8504 | 7271 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 7272 | /* Use SSC source */ |
bdd4b6a6 | 7273 | if (pipe == PIPE_A) |
ab3c759a | 7274 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7275 | 0x0df40000); |
7276 | else | |
ab3c759a | 7277 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7278 | 0x0df70000); |
7279 | } else { /* HDMI or VGA */ | |
7280 | /* Use bend source */ | |
bdd4b6a6 | 7281 | if (pipe == PIPE_A) |
ab3c759a | 7282 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7283 | 0x0df70000); |
7284 | else | |
ab3c759a | 7285 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7286 | 0x0df40000); |
7287 | } | |
a0c4da24 | 7288 | |
ab3c759a | 7289 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7290 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
7291 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
7292 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 7293 | coreclk |= 0x01000000; |
ab3c759a | 7294 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7295 | |
ab3c759a | 7296 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7297 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7298 | } |
7299 | ||
d288f65f | 7300 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7301 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7302 | { |
7303 | struct drm_device *dev = crtc->base.dev; | |
7304 | struct drm_i915_private *dev_priv = dev->dev_private; | |
cd2d34d9 | 7305 | enum pipe pipe = crtc->pipe; |
9d556c99 | 7306 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 7307 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7308 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7309 | u32 dpio_val; |
9cbe40c1 | 7310 | int vco; |
9d556c99 | 7311 | |
cd2d34d9 VS |
7312 | /* Enable Refclk and SSC */ |
7313 | I915_WRITE(DPLL(pipe), | |
7314 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
7315 | ||
7316 | /* No need to actually set up the DPLL with DSI */ | |
7317 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
7318 | return; | |
7319 | ||
d288f65f VS |
7320 | bestn = pipe_config->dpll.n; |
7321 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7322 | bestm1 = pipe_config->dpll.m1; | |
7323 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7324 | bestp1 = pipe_config->dpll.p1; | |
7325 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7326 | vco = pipe_config->dpll.vco; |
a945ce7e | 7327 | dpio_val = 0; |
9cbe40c1 | 7328 | loopfilter = 0; |
9d556c99 | 7329 | |
a580516d | 7330 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7331 | |
9d556c99 CML |
7332 | /* p1 and p2 divider */ |
7333 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7334 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7335 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7336 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7337 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7338 | ||
7339 | /* Feedback post-divider - m2 */ | |
7340 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7341 | ||
7342 | /* Feedback refclk divider - n and m1 */ | |
7343 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7344 | DPIO_CHV_M1_DIV_BY_2 | | |
7345 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7346 | ||
7347 | /* M2 fraction division */ | |
25a25dfc | 7348 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
7349 | |
7350 | /* M2 fraction division enable */ | |
a945ce7e VP |
7351 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7352 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7353 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7354 | if (bestm2_frac) | |
7355 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7356 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7357 | |
de3a0fde VP |
7358 | /* Program digital lock detect threshold */ |
7359 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7360 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7361 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7362 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7363 | if (!bestm2_frac) | |
7364 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7365 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7366 | ||
9d556c99 | 7367 | /* Loop filter */ |
9cbe40c1 VP |
7368 | if (vco == 5400000) { |
7369 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7370 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7371 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7372 | tribuf_calcntr = 0x9; | |
7373 | } else if (vco <= 6200000) { | |
7374 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7375 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7376 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7377 | tribuf_calcntr = 0x9; | |
7378 | } else if (vco <= 6480000) { | |
7379 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7380 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7381 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7382 | tribuf_calcntr = 0x8; | |
7383 | } else { | |
7384 | /* Not supported. Apply the same limits as in the max case */ | |
7385 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7386 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7387 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7388 | tribuf_calcntr = 0; | |
7389 | } | |
9d556c99 CML |
7390 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7391 | ||
968040b2 | 7392 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7393 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7394 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7395 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7396 | ||
9d556c99 CML |
7397 | /* AFC Recal */ |
7398 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7399 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7400 | DPIO_AFC_RECAL); | |
7401 | ||
a580516d | 7402 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
7403 | } |
7404 | ||
d288f65f VS |
7405 | /** |
7406 | * vlv_force_pll_on - forcibly enable just the PLL | |
7407 | * @dev_priv: i915 private structure | |
7408 | * @pipe: pipe PLL to enable | |
7409 | * @dpll: PLL configuration | |
7410 | * | |
7411 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7412 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7413 | * be enabled. | |
7414 | */ | |
3f36b937 TU |
7415 | int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
7416 | const struct dpll *dpll) | |
d288f65f VS |
7417 | { |
7418 | struct intel_crtc *crtc = | |
7419 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
3f36b937 TU |
7420 | struct intel_crtc_state *pipe_config; |
7421 | ||
7422 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
7423 | if (!pipe_config) | |
7424 | return -ENOMEM; | |
7425 | ||
7426 | pipe_config->base.crtc = &crtc->base; | |
7427 | pipe_config->pixel_multiplier = 1; | |
7428 | pipe_config->dpll = *dpll; | |
d288f65f VS |
7429 | |
7430 | if (IS_CHERRYVIEW(dev)) { | |
3f36b937 TU |
7431 | chv_compute_dpll(crtc, pipe_config); |
7432 | chv_prepare_pll(crtc, pipe_config); | |
7433 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 7434 | } else { |
3f36b937 TU |
7435 | vlv_compute_dpll(crtc, pipe_config); |
7436 | vlv_prepare_pll(crtc, pipe_config); | |
7437 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 7438 | } |
3f36b937 TU |
7439 | |
7440 | kfree(pipe_config); | |
7441 | ||
7442 | return 0; | |
d288f65f VS |
7443 | } |
7444 | ||
7445 | /** | |
7446 | * vlv_force_pll_off - forcibly disable just the PLL | |
7447 | * @dev_priv: i915 private structure | |
7448 | * @pipe: pipe PLL to disable | |
7449 | * | |
7450 | * Disable the PLL for @pipe. To be used in cases where we need | |
7451 | * the PLL enabled even when @pipe is not going to be enabled. | |
7452 | */ | |
7453 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7454 | { | |
7455 | if (IS_CHERRYVIEW(dev)) | |
7456 | chv_disable_pll(to_i915(dev), pipe); | |
7457 | else | |
7458 | vlv_disable_pll(to_i915(dev), pipe); | |
7459 | } | |
7460 | ||
251ac862 DV |
7461 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
7462 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 7463 | struct dpll *reduced_clock) |
eb1cbe48 | 7464 | { |
f47709a9 | 7465 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7466 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
7467 | u32 dpll; |
7468 | bool is_sdvo; | |
190f68c5 | 7469 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7470 | |
190f68c5 | 7471 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7472 | |
a93e255f ACO |
7473 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7474 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
7475 | |
7476 | dpll = DPLL_VGA_MODE_DIS; | |
7477 | ||
a93e255f | 7478 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7479 | dpll |= DPLLB_MODE_LVDS; |
7480 | else | |
7481 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7482 | |
ef1b460d | 7483 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7484 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7485 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7486 | } |
198a037f DV |
7487 | |
7488 | if (is_sdvo) | |
4a33e48d | 7489 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7490 | |
190f68c5 | 7491 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7492 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7493 | |
7494 | /* compute bitmask from p1 value */ | |
7495 | if (IS_PINEVIEW(dev)) | |
7496 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7497 | else { | |
7498 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7499 | if (IS_G4X(dev) && reduced_clock) | |
7500 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7501 | } | |
7502 | switch (clock->p2) { | |
7503 | case 5: | |
7504 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7505 | break; | |
7506 | case 7: | |
7507 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7508 | break; | |
7509 | case 10: | |
7510 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7511 | break; | |
7512 | case 14: | |
7513 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7514 | break; | |
7515 | } | |
7516 | if (INTEL_INFO(dev)->gen >= 4) | |
7517 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7518 | ||
190f68c5 | 7519 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7520 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 7521 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 7522 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
7523 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
7524 | else | |
7525 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7526 | ||
7527 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7528 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7529 | |
eb1cbe48 | 7530 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7531 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7532 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7533 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7534 | } |
7535 | } | |
7536 | ||
251ac862 DV |
7537 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
7538 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 7539 | struct dpll *reduced_clock) |
eb1cbe48 | 7540 | { |
f47709a9 | 7541 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7542 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 7543 | u32 dpll; |
190f68c5 | 7544 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7545 | |
190f68c5 | 7546 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7547 | |
eb1cbe48 DV |
7548 | dpll = DPLL_VGA_MODE_DIS; |
7549 | ||
a93e255f | 7550 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7551 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7552 | } else { | |
7553 | if (clock->p1 == 2) | |
7554 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7555 | else | |
7556 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7557 | if (clock->p2 == 4) | |
7558 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7559 | } | |
7560 | ||
a93e255f | 7561 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7562 | dpll |= DPLL_DVO_2X_MODE; |
7563 | ||
a93e255f | 7564 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ceb41007 | 7565 | intel_panel_use_ssc(dev_priv)) |
eb1cbe48 DV |
7566 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
7567 | else | |
7568 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7569 | ||
7570 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7571 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7572 | } |
7573 | ||
8a654f3b | 7574 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7575 | { |
7576 | struct drm_device *dev = intel_crtc->base.dev; | |
7577 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7578 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 7579 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 7580 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7581 | uint32_t crtc_vtotal, crtc_vblank_end; |
7582 | int vsyncshift = 0; | |
4d8a62ea DV |
7583 | |
7584 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7585 | * the hw state checker will get angry at the mismatch. */ | |
7586 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7587 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7588 | |
609aeaca | 7589 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7590 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7591 | crtc_vtotal -= 1; |
7592 | crtc_vblank_end -= 1; | |
609aeaca | 7593 | |
409ee761 | 7594 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7595 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7596 | else | |
7597 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7598 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7599 | if (vsyncshift < 0) |
7600 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7601 | } |
7602 | ||
7603 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7604 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7605 | |
fe2b8f9d | 7606 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7607 | (adjusted_mode->crtc_hdisplay - 1) | |
7608 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7609 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7610 | (adjusted_mode->crtc_hblank_start - 1) | |
7611 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7612 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7613 | (adjusted_mode->crtc_hsync_start - 1) | |
7614 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7615 | ||
fe2b8f9d | 7616 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7617 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7618 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7619 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7620 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7621 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7622 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7623 | (adjusted_mode->crtc_vsync_start - 1) | |
7624 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7625 | ||
b5e508d4 PZ |
7626 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7627 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7628 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7629 | * bits. */ | |
7630 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7631 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7632 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7633 | ||
bc58be60 JN |
7634 | } |
7635 | ||
7636 | static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc) | |
7637 | { | |
7638 | struct drm_device *dev = intel_crtc->base.dev; | |
7639 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7640 | enum pipe pipe = intel_crtc->pipe; | |
7641 | ||
b0e77b9c PZ |
7642 | /* pipesrc controls the size that is scaled from, which should |
7643 | * always be the user's requested size. | |
7644 | */ | |
7645 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7646 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7647 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7648 | } |
7649 | ||
1bd1bd80 | 7650 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7651 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7652 | { |
7653 | struct drm_device *dev = crtc->base.dev; | |
7654 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7655 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7656 | uint32_t tmp; | |
7657 | ||
7658 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7659 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7660 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7661 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7662 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7663 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7664 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7665 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7666 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7667 | |
7668 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7669 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7670 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7671 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7672 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7673 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7674 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7675 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7676 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7677 | |
7678 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7679 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7680 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7681 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 | 7682 | } |
bc58be60 JN |
7683 | } |
7684 | ||
7685 | static void intel_get_pipe_src_size(struct intel_crtc *crtc, | |
7686 | struct intel_crtc_state *pipe_config) | |
7687 | { | |
7688 | struct drm_device *dev = crtc->base.dev; | |
7689 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7690 | u32 tmp; | |
1bd1bd80 DV |
7691 | |
7692 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7693 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7694 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7695 | ||
2d112de7 ACO |
7696 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7697 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7698 | } |
7699 | ||
f6a83288 | 7700 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7701 | struct intel_crtc_state *pipe_config) |
babea61d | 7702 | { |
2d112de7 ACO |
7703 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7704 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7705 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7706 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7707 | |
2d112de7 ACO |
7708 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7709 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7710 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7711 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7712 | |
2d112de7 | 7713 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7714 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7715 | |
2d112de7 ACO |
7716 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7717 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
7718 | |
7719 | mode->hsync = drm_mode_hsync(mode); | |
7720 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7721 | drm_mode_set_name(mode); | |
babea61d JB |
7722 | } |
7723 | ||
84b046f3 DV |
7724 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7725 | { | |
7726 | struct drm_device *dev = intel_crtc->base.dev; | |
7727 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7728 | uint32_t pipeconf; | |
7729 | ||
9f11a9e4 | 7730 | pipeconf = 0; |
84b046f3 | 7731 | |
b6b5d049 VS |
7732 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7733 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7734 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7735 | |
6e3c9717 | 7736 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7737 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7738 | |
ff9ce46e | 7739 | /* only g4x and later have fancy bpc/dither controls */ |
666a4537 | 7740 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
ff9ce46e | 7741 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7742 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7743 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7744 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7745 | |
6e3c9717 | 7746 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7747 | case 18: |
7748 | pipeconf |= PIPECONF_6BPC; | |
7749 | break; | |
7750 | case 24: | |
7751 | pipeconf |= PIPECONF_8BPC; | |
7752 | break; | |
7753 | case 30: | |
7754 | pipeconf |= PIPECONF_10BPC; | |
7755 | break; | |
7756 | default: | |
7757 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7758 | BUG(); | |
84b046f3 DV |
7759 | } |
7760 | } | |
7761 | ||
7762 | if (HAS_PIPE_CXSR(dev)) { | |
7763 | if (intel_crtc->lowfreq_avail) { | |
7764 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7765 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7766 | } else { | |
7767 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7768 | } |
7769 | } | |
7770 | ||
6e3c9717 | 7771 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7772 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 7773 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7774 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7775 | else | |
7776 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7777 | } else | |
84b046f3 DV |
7778 | pipeconf |= PIPECONF_PROGRESSIVE; |
7779 | ||
666a4537 WB |
7780 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
7781 | intel_crtc->config->limited_color_range) | |
9f11a9e4 | 7782 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7783 | |
84b046f3 DV |
7784 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7785 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7786 | } | |
7787 | ||
81c97f52 ACO |
7788 | static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, |
7789 | struct intel_crtc_state *crtc_state) | |
7790 | { | |
7791 | struct drm_device *dev = crtc->base.dev; | |
7792 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1b6f4958 | 7793 | const struct intel_limit *limit; |
81c97f52 ACO |
7794 | int refclk = 48000; |
7795 | ||
7796 | memset(&crtc_state->dpll_hw_state, 0, | |
7797 | sizeof(crtc_state->dpll_hw_state)); | |
7798 | ||
7799 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { | |
7800 | if (intel_panel_use_ssc(dev_priv)) { | |
7801 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7802 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7803 | } | |
7804 | ||
7805 | limit = &intel_limits_i8xx_lvds; | |
7806 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) { | |
7807 | limit = &intel_limits_i8xx_dvo; | |
7808 | } else { | |
7809 | limit = &intel_limits_i8xx_dac; | |
7810 | } | |
7811 | ||
7812 | if (!crtc_state->clock_set && | |
7813 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7814 | refclk, NULL, &crtc_state->dpll)) { | |
7815 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7816 | return -EINVAL; | |
7817 | } | |
7818 | ||
7819 | i8xx_compute_dpll(crtc, crtc_state, NULL); | |
7820 | ||
7821 | return 0; | |
7822 | } | |
7823 | ||
19ec6693 ACO |
7824 | static int g4x_crtc_compute_clock(struct intel_crtc *crtc, |
7825 | struct intel_crtc_state *crtc_state) | |
7826 | { | |
7827 | struct drm_device *dev = crtc->base.dev; | |
7828 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1b6f4958 | 7829 | const struct intel_limit *limit; |
19ec6693 ACO |
7830 | int refclk = 96000; |
7831 | ||
7832 | memset(&crtc_state->dpll_hw_state, 0, | |
7833 | sizeof(crtc_state->dpll_hw_state)); | |
7834 | ||
7835 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { | |
7836 | if (intel_panel_use_ssc(dev_priv)) { | |
7837 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7838 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7839 | } | |
7840 | ||
7841 | if (intel_is_dual_link_lvds(dev)) | |
7842 | limit = &intel_limits_g4x_dual_channel_lvds; | |
7843 | else | |
7844 | limit = &intel_limits_g4x_single_channel_lvds; | |
7845 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || | |
7846 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
7847 | limit = &intel_limits_g4x_hdmi; | |
7848 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { | |
7849 | limit = &intel_limits_g4x_sdvo; | |
7850 | } else { | |
7851 | /* The option is for other outputs */ | |
7852 | limit = &intel_limits_i9xx_sdvo; | |
7853 | } | |
7854 | ||
7855 | if (!crtc_state->clock_set && | |
7856 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7857 | refclk, NULL, &crtc_state->dpll)) { | |
7858 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7859 | return -EINVAL; | |
7860 | } | |
7861 | ||
7862 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7863 | ||
7864 | return 0; | |
7865 | } | |
7866 | ||
70e8aa21 ACO |
7867 | static int pnv_crtc_compute_clock(struct intel_crtc *crtc, |
7868 | struct intel_crtc_state *crtc_state) | |
7869 | { | |
7870 | struct drm_device *dev = crtc->base.dev; | |
7871 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1b6f4958 | 7872 | const struct intel_limit *limit; |
70e8aa21 ACO |
7873 | int refclk = 96000; |
7874 | ||
7875 | memset(&crtc_state->dpll_hw_state, 0, | |
7876 | sizeof(crtc_state->dpll_hw_state)); | |
7877 | ||
7878 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { | |
7879 | if (intel_panel_use_ssc(dev_priv)) { | |
7880 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7881 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7882 | } | |
7883 | ||
7884 | limit = &intel_limits_pineview_lvds; | |
7885 | } else { | |
7886 | limit = &intel_limits_pineview_sdvo; | |
7887 | } | |
7888 | ||
7889 | if (!crtc_state->clock_set && | |
7890 | !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7891 | refclk, NULL, &crtc_state->dpll)) { | |
7892 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7893 | return -EINVAL; | |
7894 | } | |
7895 | ||
7896 | i9xx_compute_dpll(crtc, crtc_state, NULL); | |
7897 | ||
7898 | return 0; | |
7899 | } | |
7900 | ||
190f68c5 ACO |
7901 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7902 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7903 | { |
c7653199 | 7904 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7905 | struct drm_i915_private *dev_priv = dev->dev_private; |
1b6f4958 | 7906 | const struct intel_limit *limit; |
81c97f52 | 7907 | int refclk = 96000; |
79e53945 | 7908 | |
dd3cd74a ACO |
7909 | memset(&crtc_state->dpll_hw_state, 0, |
7910 | sizeof(crtc_state->dpll_hw_state)); | |
7911 | ||
70e8aa21 ACO |
7912 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
7913 | if (intel_panel_use_ssc(dev_priv)) { | |
7914 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
7915 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
7916 | } | |
43565a06 | 7917 | |
70e8aa21 ACO |
7918 | limit = &intel_limits_i9xx_lvds; |
7919 | } else { | |
7920 | limit = &intel_limits_i9xx_sdvo; | |
81c97f52 | 7921 | } |
79e53945 | 7922 | |
70e8aa21 ACO |
7923 | if (!crtc_state->clock_set && |
7924 | !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7925 | refclk, NULL, &crtc_state->dpll)) { | |
7926 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7927 | return -EINVAL; | |
f47709a9 | 7928 | } |
7026d4ac | 7929 | |
81c97f52 | 7930 | i9xx_compute_dpll(crtc, crtc_state, NULL); |
79e53945 | 7931 | |
c8f7a0db | 7932 | return 0; |
f564048e EA |
7933 | } |
7934 | ||
65b3d6a9 ACO |
7935 | static int chv_crtc_compute_clock(struct intel_crtc *crtc, |
7936 | struct intel_crtc_state *crtc_state) | |
7937 | { | |
7938 | int refclk = 100000; | |
1b6f4958 | 7939 | const struct intel_limit *limit = &intel_limits_chv; |
65b3d6a9 ACO |
7940 | |
7941 | memset(&crtc_state->dpll_hw_state, 0, | |
7942 | sizeof(crtc_state->dpll_hw_state)); | |
7943 | ||
65b3d6a9 ACO |
7944 | if (!crtc_state->clock_set && |
7945 | !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7946 | refclk, NULL, &crtc_state->dpll)) { | |
7947 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7948 | return -EINVAL; | |
7949 | } | |
7950 | ||
7951 | chv_compute_dpll(crtc, crtc_state); | |
7952 | ||
7953 | return 0; | |
7954 | } | |
7955 | ||
7956 | static int vlv_crtc_compute_clock(struct intel_crtc *crtc, | |
7957 | struct intel_crtc_state *crtc_state) | |
7958 | { | |
7959 | int refclk = 100000; | |
1b6f4958 | 7960 | const struct intel_limit *limit = &intel_limits_vlv; |
65b3d6a9 ACO |
7961 | |
7962 | memset(&crtc_state->dpll_hw_state, 0, | |
7963 | sizeof(crtc_state->dpll_hw_state)); | |
7964 | ||
65b3d6a9 ACO |
7965 | if (!crtc_state->clock_set && |
7966 | !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, | |
7967 | refclk, NULL, &crtc_state->dpll)) { | |
7968 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); | |
7969 | return -EINVAL; | |
7970 | } | |
7971 | ||
7972 | vlv_compute_dpll(crtc, crtc_state); | |
7973 | ||
7974 | return 0; | |
7975 | } | |
7976 | ||
2fa2fe9a | 7977 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 7978 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
7979 | { |
7980 | struct drm_device *dev = crtc->base.dev; | |
7981 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7982 | uint32_t tmp; | |
7983 | ||
dc9e7dec VS |
7984 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
7985 | return; | |
7986 | ||
2fa2fe9a | 7987 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
7988 | if (!(tmp & PFIT_ENABLE)) |
7989 | return; | |
2fa2fe9a | 7990 | |
06922821 | 7991 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
7992 | if (INTEL_INFO(dev)->gen < 4) { |
7993 | if (crtc->pipe != PIPE_B) | |
7994 | return; | |
2fa2fe9a DV |
7995 | } else { |
7996 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
7997 | return; | |
7998 | } | |
7999 | ||
06922821 | 8000 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a | 8001 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
2fa2fe9a DV |
8002 | } |
8003 | ||
acbec814 | 8004 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8005 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
8006 | { |
8007 | struct drm_device *dev = crtc->base.dev; | |
8008 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8009 | int pipe = pipe_config->cpu_transcoder; | |
9e2c8475 | 8010 | struct dpll clock; |
acbec814 | 8011 | u32 mdiv; |
662c6ecb | 8012 | int refclk = 100000; |
acbec814 | 8013 | |
b521973b VS |
8014 | /* In case of DSI, DPLL will not be used */ |
8015 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
f573de5a SK |
8016 | return; |
8017 | ||
a580516d | 8018 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 8019 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 8020 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
8021 | |
8022 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
8023 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
8024 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
8025 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
8026 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
8027 | ||
dccbea3b | 8028 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
8029 | } |
8030 | ||
5724dbd1 DL |
8031 | static void |
8032 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
8033 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
8034 | { |
8035 | struct drm_device *dev = crtc->base.dev; | |
8036 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8037 | u32 val, base, offset; | |
8038 | int pipe = crtc->pipe, plane = crtc->plane; | |
8039 | int fourcc, pixel_format; | |
6761dd31 | 8040 | unsigned int aligned_height; |
b113d5ee | 8041 | struct drm_framebuffer *fb; |
1b842c89 | 8042 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 8043 | |
42a7b088 DL |
8044 | val = I915_READ(DSPCNTR(plane)); |
8045 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8046 | return; | |
8047 | ||
d9806c9f | 8048 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8049 | if (!intel_fb) { |
1ad292b5 JB |
8050 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8051 | return; | |
8052 | } | |
8053 | ||
1b842c89 DL |
8054 | fb = &intel_fb->base; |
8055 | ||
18c5247e DV |
8056 | if (INTEL_INFO(dev)->gen >= 4) { |
8057 | if (val & DISPPLANE_TILED) { | |
49af449b | 8058 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8059 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8060 | } | |
8061 | } | |
1ad292b5 JB |
8062 | |
8063 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8064 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8065 | fb->pixel_format = fourcc; |
8066 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
8067 | |
8068 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 8069 | if (plane_config->tiling) |
1ad292b5 JB |
8070 | offset = I915_READ(DSPTILEOFF(plane)); |
8071 | else | |
8072 | offset = I915_READ(DSPLINOFF(plane)); | |
8073 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8074 | } else { | |
8075 | base = I915_READ(DSPADDR(plane)); | |
8076 | } | |
8077 | plane_config->base = base; | |
8078 | ||
8079 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8080 | fb->width = ((val >> 16) & 0xfff) + 1; |
8081 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8082 | |
8083 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8084 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8085 | |
b113d5ee | 8086 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8087 | fb->pixel_format, |
8088 | fb->modifier[0]); | |
1ad292b5 | 8089 | |
f37b5c2b | 8090 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8091 | |
2844a921 DL |
8092 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8093 | pipe_name(pipe), plane, fb->width, fb->height, | |
8094 | fb->bits_per_pixel, base, fb->pitches[0], | |
8095 | plane_config->size); | |
1ad292b5 | 8096 | |
2d14030b | 8097 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8098 | } |
8099 | ||
70b23a98 | 8100 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8101 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8102 | { |
8103 | struct drm_device *dev = crtc->base.dev; | |
8104 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8105 | int pipe = pipe_config->cpu_transcoder; | |
8106 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9e2c8475 | 8107 | struct dpll clock; |
0d7b6b11 | 8108 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8109 | int refclk = 100000; |
8110 | ||
b521973b VS |
8111 | /* In case of DSI, DPLL will not be used */ |
8112 | if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) | |
8113 | return; | |
8114 | ||
a580516d | 8115 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8116 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8117 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8118 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8119 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8120 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8121 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8122 | |
8123 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8124 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8125 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8126 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8127 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8128 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8129 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8130 | ||
dccbea3b | 8131 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8132 | } |
8133 | ||
0e8ffe1b | 8134 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8135 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8136 | { |
8137 | struct drm_device *dev = crtc->base.dev; | |
8138 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e | 8139 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 8140 | uint32_t tmp; |
1729050e | 8141 | bool ret; |
0e8ffe1b | 8142 | |
1729050e ID |
8143 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
8144 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 ID |
8145 | return false; |
8146 | ||
e143a21c | 8147 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 8148 | pipe_config->shared_dpll = NULL; |
eccb140b | 8149 | |
1729050e ID |
8150 | ret = false; |
8151 | ||
0e8ffe1b DV |
8152 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8153 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 8154 | goto out; |
0e8ffe1b | 8155 | |
666a4537 | 8156 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
42571aef VS |
8157 | switch (tmp & PIPECONF_BPC_MASK) { |
8158 | case PIPECONF_6BPC: | |
8159 | pipe_config->pipe_bpp = 18; | |
8160 | break; | |
8161 | case PIPECONF_8BPC: | |
8162 | pipe_config->pipe_bpp = 24; | |
8163 | break; | |
8164 | case PIPECONF_10BPC: | |
8165 | pipe_config->pipe_bpp = 30; | |
8166 | break; | |
8167 | default: | |
8168 | break; | |
8169 | } | |
8170 | } | |
8171 | ||
666a4537 WB |
8172 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
8173 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) | |
b5a9fa09 DV |
8174 | pipe_config->limited_color_range = true; |
8175 | ||
282740f7 VS |
8176 | if (INTEL_INFO(dev)->gen < 4) |
8177 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8178 | ||
1bd1bd80 | 8179 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 8180 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 8181 | |
2fa2fe9a DV |
8182 | i9xx_get_pfit_config(crtc, pipe_config); |
8183 | ||
6c49f241 | 8184 | if (INTEL_INFO(dev)->gen >= 4) { |
c231775c VS |
8185 | /* No way to read it out on pipes B and C */ |
8186 | if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A) | |
8187 | tmp = dev_priv->chv_dpll_md[crtc->pipe]; | |
8188 | else | |
8189 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6c49f241 DV |
8190 | pipe_config->pixel_multiplier = |
8191 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8192 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8193 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
8194 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
8195 | tmp = I915_READ(DPLL(crtc->pipe)); | |
8196 | pipe_config->pixel_multiplier = | |
8197 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8198 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8199 | } else { | |
8200 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8201 | * port and will be fixed up in the encoder->get_config | |
8202 | * function. */ | |
8203 | pipe_config->pixel_multiplier = 1; | |
8204 | } | |
8bcc2795 | 8205 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
666a4537 | 8206 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
1c4e0274 VS |
8207 | /* |
8208 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8209 | * on 830. Filter it out here so that we don't | |
8210 | * report errors due to that. | |
8211 | */ | |
8212 | if (IS_I830(dev)) | |
8213 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
8214 | ||
8bcc2795 DV |
8215 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8216 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8217 | } else { |
8218 | /* Mask out read-only status bits. */ | |
8219 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8220 | DPLL_PORTC_READY_MASK | | |
8221 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8222 | } |
6c49f241 | 8223 | |
70b23a98 VS |
8224 | if (IS_CHERRYVIEW(dev)) |
8225 | chv_crtc_clock_get(crtc, pipe_config); | |
8226 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
8227 | vlv_crtc_clock_get(crtc, pipe_config); |
8228 | else | |
8229 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8230 | |
0f64614d VS |
8231 | /* |
8232 | * Normally the dotclock is filled in by the encoder .get_config() | |
8233 | * but in case the pipe is enabled w/o any ports we need a sane | |
8234 | * default. | |
8235 | */ | |
8236 | pipe_config->base.adjusted_mode.crtc_clock = | |
8237 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8238 | ||
1729050e ID |
8239 | ret = true; |
8240 | ||
8241 | out: | |
8242 | intel_display_power_put(dev_priv, power_domain); | |
8243 | ||
8244 | return ret; | |
0e8ffe1b DV |
8245 | } |
8246 | ||
dde86e2d | 8247 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
8248 | { |
8249 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 8250 | struct intel_encoder *encoder; |
74cfd7ac | 8251 | u32 val, final; |
13d83a67 | 8252 | bool has_lvds = false; |
199e5d79 | 8253 | bool has_cpu_edp = false; |
199e5d79 | 8254 | bool has_panel = false; |
99eb6a01 KP |
8255 | bool has_ck505 = false; |
8256 | bool can_ssc = false; | |
13d83a67 JB |
8257 | |
8258 | /* We need to take the global config into account */ | |
b2784e15 | 8259 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8260 | switch (encoder->type) { |
8261 | case INTEL_OUTPUT_LVDS: | |
8262 | has_panel = true; | |
8263 | has_lvds = true; | |
8264 | break; | |
8265 | case INTEL_OUTPUT_EDP: | |
8266 | has_panel = true; | |
2de6905f | 8267 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8268 | has_cpu_edp = true; |
8269 | break; | |
6847d71b PZ |
8270 | default: |
8271 | break; | |
13d83a67 JB |
8272 | } |
8273 | } | |
8274 | ||
99eb6a01 | 8275 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 8276 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8277 | can_ssc = has_ck505; |
8278 | } else { | |
8279 | has_ck505 = false; | |
8280 | can_ssc = true; | |
8281 | } | |
8282 | ||
2de6905f ID |
8283 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
8284 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
8285 | |
8286 | /* Ironlake: try to setup display ref clock before DPLL | |
8287 | * enabling. This is only under driver's control after | |
8288 | * PCH B stepping, previous chipset stepping should be | |
8289 | * ignoring this setting. | |
8290 | */ | |
74cfd7ac CW |
8291 | val = I915_READ(PCH_DREF_CONTROL); |
8292 | ||
8293 | /* As we must carefully and slowly disable/enable each source in turn, | |
8294 | * compute the final state we want first and check if we need to | |
8295 | * make any changes at all. | |
8296 | */ | |
8297 | final = val; | |
8298 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8299 | if (has_ck505) | |
8300 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8301 | else | |
8302 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8303 | ||
8304 | final &= ~DREF_SSC_SOURCE_MASK; | |
8305 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
8306 | final &= ~DREF_SSC1_ENABLE; | |
8307 | ||
8308 | if (has_panel) { | |
8309 | final |= DREF_SSC_SOURCE_ENABLE; | |
8310 | ||
8311 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8312 | final |= DREF_SSC1_ENABLE; | |
8313 | ||
8314 | if (has_cpu_edp) { | |
8315 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8316 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8317 | else | |
8318 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8319 | } else | |
8320 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8321 | } else { | |
8322 | final |= DREF_SSC_SOURCE_DISABLE; | |
8323 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8324 | } | |
8325 | ||
8326 | if (final == val) | |
8327 | return; | |
8328 | ||
13d83a67 | 8329 | /* Always enable nonspread source */ |
74cfd7ac | 8330 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8331 | |
99eb6a01 | 8332 | if (has_ck505) |
74cfd7ac | 8333 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 8334 | else |
74cfd7ac | 8335 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 8336 | |
199e5d79 | 8337 | if (has_panel) { |
74cfd7ac CW |
8338 | val &= ~DREF_SSC_SOURCE_MASK; |
8339 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 8340 | |
199e5d79 | 8341 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 8342 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8343 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 8344 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 8345 | } else |
74cfd7ac | 8346 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
8347 | |
8348 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 8349 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8350 | POSTING_READ(PCH_DREF_CONTROL); |
8351 | udelay(200); | |
8352 | ||
74cfd7ac | 8353 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
8354 | |
8355 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 8356 | if (has_cpu_edp) { |
99eb6a01 | 8357 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8358 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 8359 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 8360 | } else |
74cfd7ac | 8361 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 8362 | } else |
74cfd7ac | 8363 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8364 | |
74cfd7ac | 8365 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8366 | POSTING_READ(PCH_DREF_CONTROL); |
8367 | udelay(200); | |
8368 | } else { | |
8369 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
8370 | ||
74cfd7ac | 8371 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
8372 | |
8373 | /* Turn off CPU output */ | |
74cfd7ac | 8374 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8375 | |
74cfd7ac | 8376 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8377 | POSTING_READ(PCH_DREF_CONTROL); |
8378 | udelay(200); | |
8379 | ||
8380 | /* Turn off the SSC source */ | |
74cfd7ac CW |
8381 | val &= ~DREF_SSC_SOURCE_MASK; |
8382 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
8383 | |
8384 | /* Turn off SSC1 */ | |
74cfd7ac | 8385 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 8386 | |
74cfd7ac | 8387 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
8388 | POSTING_READ(PCH_DREF_CONTROL); |
8389 | udelay(200); | |
8390 | } | |
74cfd7ac CW |
8391 | |
8392 | BUG_ON(val != final); | |
13d83a67 JB |
8393 | } |
8394 | ||
f31f2d55 | 8395 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 8396 | { |
f31f2d55 | 8397 | uint32_t tmp; |
dde86e2d | 8398 | |
0ff066a9 PZ |
8399 | tmp = I915_READ(SOUTH_CHICKEN2); |
8400 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8401 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8402 | |
0ff066a9 PZ |
8403 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
8404 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
8405 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 8406 | |
0ff066a9 PZ |
8407 | tmp = I915_READ(SOUTH_CHICKEN2); |
8408 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8409 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8410 | |
0ff066a9 PZ |
8411 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
8412 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
8413 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
8414 | } |
8415 | ||
8416 | /* WaMPhyProgramming:hsw */ | |
8417 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8418 | { | |
8419 | uint32_t tmp; | |
dde86e2d PZ |
8420 | |
8421 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8422 | tmp &= ~(0xFF << 24); | |
8423 | tmp |= (0x12 << 24); | |
8424 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8425 | ||
dde86e2d PZ |
8426 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
8427 | tmp |= (1 << 11); | |
8428 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8429 | ||
8430 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8431 | tmp |= (1 << 11); | |
8432 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8433 | ||
dde86e2d PZ |
8434 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
8435 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8436 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
8437 | ||
8438 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
8439 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8440 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8441 | ||
0ff066a9 PZ |
8442 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
8443 | tmp &= ~(7 << 13); | |
8444 | tmp |= (5 << 13); | |
8445 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 8446 | |
0ff066a9 PZ |
8447 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
8448 | tmp &= ~(7 << 13); | |
8449 | tmp |= (5 << 13); | |
8450 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
8451 | |
8452 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8453 | tmp &= ~0xFF; | |
8454 | tmp |= 0x1C; | |
8455 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8456 | ||
8457 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8458 | tmp &= ~0xFF; | |
8459 | tmp |= 0x1C; | |
8460 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8461 | ||
8462 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8463 | tmp &= ~(0xFF << 16); | |
8464 | tmp |= (0x1C << 16); | |
8465 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8466 | ||
8467 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8468 | tmp &= ~(0xFF << 16); | |
8469 | tmp |= (0x1C << 16); | |
8470 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8471 | ||
0ff066a9 PZ |
8472 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8473 | tmp |= (1 << 27); | |
8474 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8475 | |
0ff066a9 PZ |
8476 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8477 | tmp |= (1 << 27); | |
8478 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8479 | |
0ff066a9 PZ |
8480 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8481 | tmp &= ~(0xF << 28); | |
8482 | tmp |= (4 << 28); | |
8483 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8484 | |
0ff066a9 PZ |
8485 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8486 | tmp &= ~(0xF << 28); | |
8487 | tmp |= (4 << 28); | |
8488 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8489 | } |
8490 | ||
2fa86a1f PZ |
8491 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8492 | * Programming" based on the parameters passed: | |
8493 | * - Sequence to enable CLKOUT_DP | |
8494 | * - Sequence to enable CLKOUT_DP without spread | |
8495 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8496 | */ | |
8497 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8498 | bool with_fdi) | |
f31f2d55 PZ |
8499 | { |
8500 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
8501 | uint32_t reg, tmp; |
8502 | ||
8503 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8504 | with_spread = true; | |
c2699524 | 8505 | if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) |
2fa86a1f | 8506 | with_fdi = false; |
f31f2d55 | 8507 | |
a580516d | 8508 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
8509 | |
8510 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8511 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8512 | tmp |= SBI_SSCCTL_PATHALT; | |
8513 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8514 | ||
8515 | udelay(24); | |
8516 | ||
2fa86a1f PZ |
8517 | if (with_spread) { |
8518 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8519 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8520 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8521 | |
2fa86a1f PZ |
8522 | if (with_fdi) { |
8523 | lpt_reset_fdi_mphy(dev_priv); | |
8524 | lpt_program_fdi_mphy(dev_priv); | |
8525 | } | |
8526 | } | |
dde86e2d | 8527 | |
c2699524 | 8528 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
8529 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8530 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8531 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 8532 | |
a580516d | 8533 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
8534 | } |
8535 | ||
47701c3b PZ |
8536 | /* Sequence to disable CLKOUT_DP */ |
8537 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8538 | { | |
8539 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8540 | uint32_t reg, tmp; | |
8541 | ||
a580516d | 8542 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 8543 | |
c2699524 | 8544 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
8545 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8546 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8547 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8548 | ||
8549 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8550 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8551 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8552 | tmp |= SBI_SSCCTL_PATHALT; | |
8553 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8554 | udelay(32); | |
8555 | } | |
8556 | tmp |= SBI_SSCCTL_DISABLE; | |
8557 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8558 | } | |
8559 | ||
a580516d | 8560 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8561 | } |
8562 | ||
f7be2c21 VS |
8563 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
8564 | ||
8565 | static const uint16_t sscdivintphase[] = { | |
8566 | [BEND_IDX( 50)] = 0x3B23, | |
8567 | [BEND_IDX( 45)] = 0x3B23, | |
8568 | [BEND_IDX( 40)] = 0x3C23, | |
8569 | [BEND_IDX( 35)] = 0x3C23, | |
8570 | [BEND_IDX( 30)] = 0x3D23, | |
8571 | [BEND_IDX( 25)] = 0x3D23, | |
8572 | [BEND_IDX( 20)] = 0x3E23, | |
8573 | [BEND_IDX( 15)] = 0x3E23, | |
8574 | [BEND_IDX( 10)] = 0x3F23, | |
8575 | [BEND_IDX( 5)] = 0x3F23, | |
8576 | [BEND_IDX( 0)] = 0x0025, | |
8577 | [BEND_IDX( -5)] = 0x0025, | |
8578 | [BEND_IDX(-10)] = 0x0125, | |
8579 | [BEND_IDX(-15)] = 0x0125, | |
8580 | [BEND_IDX(-20)] = 0x0225, | |
8581 | [BEND_IDX(-25)] = 0x0225, | |
8582 | [BEND_IDX(-30)] = 0x0325, | |
8583 | [BEND_IDX(-35)] = 0x0325, | |
8584 | [BEND_IDX(-40)] = 0x0425, | |
8585 | [BEND_IDX(-45)] = 0x0425, | |
8586 | [BEND_IDX(-50)] = 0x0525, | |
8587 | }; | |
8588 | ||
8589 | /* | |
8590 | * Bend CLKOUT_DP | |
8591 | * steps -50 to 50 inclusive, in steps of 5 | |
8592 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
8593 | * change in clock period = -(steps / 10) * 5.787 ps | |
8594 | */ | |
8595 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
8596 | { | |
8597 | uint32_t tmp; | |
8598 | int idx = BEND_IDX(steps); | |
8599 | ||
8600 | if (WARN_ON(steps % 5 != 0)) | |
8601 | return; | |
8602 | ||
8603 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
8604 | return; | |
8605 | ||
8606 | mutex_lock(&dev_priv->sb_lock); | |
8607 | ||
8608 | if (steps % 10 != 0) | |
8609 | tmp = 0xAAAAAAAB; | |
8610 | else | |
8611 | tmp = 0x00000000; | |
8612 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
8613 | ||
8614 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
8615 | tmp &= 0xffff0000; | |
8616 | tmp |= sscdivintphase[idx]; | |
8617 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
8618 | ||
8619 | mutex_unlock(&dev_priv->sb_lock); | |
8620 | } | |
8621 | ||
8622 | #undef BEND_IDX | |
8623 | ||
bf8fa3d3 PZ |
8624 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8625 | { | |
bf8fa3d3 PZ |
8626 | struct intel_encoder *encoder; |
8627 | bool has_vga = false; | |
8628 | ||
b2784e15 | 8629 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8630 | switch (encoder->type) { |
8631 | case INTEL_OUTPUT_ANALOG: | |
8632 | has_vga = true; | |
8633 | break; | |
6847d71b PZ |
8634 | default: |
8635 | break; | |
bf8fa3d3 PZ |
8636 | } |
8637 | } | |
8638 | ||
f7be2c21 VS |
8639 | if (has_vga) { |
8640 | lpt_bend_clkout_dp(to_i915(dev), 0); | |
47701c3b | 8641 | lpt_enable_clkout_dp(dev, true, true); |
f7be2c21 | 8642 | } else { |
47701c3b | 8643 | lpt_disable_clkout_dp(dev); |
f7be2c21 | 8644 | } |
bf8fa3d3 PZ |
8645 | } |
8646 | ||
dde86e2d PZ |
8647 | /* |
8648 | * Initialize reference clocks when the driver loads | |
8649 | */ | |
8650 | void intel_init_pch_refclk(struct drm_device *dev) | |
8651 | { | |
8652 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8653 | ironlake_init_pch_refclk(dev); | |
8654 | else if (HAS_PCH_LPT(dev)) | |
8655 | lpt_init_pch_refclk(dev); | |
8656 | } | |
8657 | ||
6ff93609 | 8658 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8659 | { |
c8203565 | 8660 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
8661 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8662 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8663 | uint32_t val; |
8664 | ||
78114071 | 8665 | val = 0; |
c8203565 | 8666 | |
6e3c9717 | 8667 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8668 | case 18: |
dfd07d72 | 8669 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8670 | break; |
8671 | case 24: | |
dfd07d72 | 8672 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8673 | break; |
8674 | case 30: | |
dfd07d72 | 8675 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8676 | break; |
8677 | case 36: | |
dfd07d72 | 8678 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8679 | break; |
8680 | default: | |
cc769b62 PZ |
8681 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8682 | BUG(); | |
c8203565 PZ |
8683 | } |
8684 | ||
6e3c9717 | 8685 | if (intel_crtc->config->dither) |
c8203565 PZ |
8686 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8687 | ||
6e3c9717 | 8688 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8689 | val |= PIPECONF_INTERLACED_ILK; |
8690 | else | |
8691 | val |= PIPECONF_PROGRESSIVE; | |
8692 | ||
6e3c9717 | 8693 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8694 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8695 | |
c8203565 PZ |
8696 | I915_WRITE(PIPECONF(pipe), val); |
8697 | POSTING_READ(PIPECONF(pipe)); | |
8698 | } | |
8699 | ||
6ff93609 | 8700 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8701 | { |
391bf048 | 8702 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
ee2b0b38 | 8703 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 8704 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
391bf048 | 8705 | u32 val = 0; |
ee2b0b38 | 8706 | |
391bf048 | 8707 | if (IS_HASWELL(dev_priv) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8708 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8709 | ||
6e3c9717 | 8710 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8711 | val |= PIPECONF_INTERLACED_ILK; |
8712 | else | |
8713 | val |= PIPECONF_PROGRESSIVE; | |
8714 | ||
702e7a56 PZ |
8715 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8716 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
391bf048 JN |
8717 | } |
8718 | ||
391bf048 JN |
8719 | static void haswell_set_pipemisc(struct drm_crtc *crtc) |
8720 | { | |
8721 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
8722 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
756f85cf | 8723 | |
391bf048 JN |
8724 | if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) { |
8725 | u32 val = 0; | |
756f85cf | 8726 | |
6e3c9717 | 8727 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8728 | case 18: |
8729 | val |= PIPEMISC_DITHER_6_BPC; | |
8730 | break; | |
8731 | case 24: | |
8732 | val |= PIPEMISC_DITHER_8_BPC; | |
8733 | break; | |
8734 | case 30: | |
8735 | val |= PIPEMISC_DITHER_10_BPC; | |
8736 | break; | |
8737 | case 36: | |
8738 | val |= PIPEMISC_DITHER_12_BPC; | |
8739 | break; | |
8740 | default: | |
8741 | /* Case prevented by pipe_config_set_bpp. */ | |
8742 | BUG(); | |
8743 | } | |
8744 | ||
6e3c9717 | 8745 | if (intel_crtc->config->dither) |
756f85cf PZ |
8746 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8747 | ||
391bf048 | 8748 | I915_WRITE(PIPEMISC(intel_crtc->pipe), val); |
756f85cf | 8749 | } |
ee2b0b38 PZ |
8750 | } |
8751 | ||
d4b1931c PZ |
8752 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8753 | { | |
8754 | /* | |
8755 | * Account for spread spectrum to avoid | |
8756 | * oversubscribing the link. Max center spread | |
8757 | * is 2.5%; use 5% for safety's sake. | |
8758 | */ | |
8759 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8760 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8761 | } |
8762 | ||
7429e9d4 | 8763 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8764 | { |
7429e9d4 | 8765 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8766 | } |
8767 | ||
b75ca6f6 ACO |
8768 | static void ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
8769 | struct intel_crtc_state *crtc_state, | |
9e2c8475 | 8770 | struct dpll *reduced_clock) |
79e53945 | 8771 | { |
de13a2e3 | 8772 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
8773 | struct drm_device *dev = crtc->dev; |
8774 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 | 8775 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8776 | struct drm_connector *connector; |
55bb9992 ACO |
8777 | struct drm_connector_state *connector_state; |
8778 | struct intel_encoder *encoder; | |
b75ca6f6 | 8779 | u32 dpll, fp, fp2; |
ceb41007 | 8780 | int factor, i; |
09ede541 | 8781 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 8782 | |
da3ced29 | 8783 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8784 | if (connector_state->crtc != crtc_state->base.crtc) |
8785 | continue; | |
8786 | ||
8787 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8788 | ||
8789 | switch (encoder->type) { | |
79e53945 JB |
8790 | case INTEL_OUTPUT_LVDS: |
8791 | is_lvds = true; | |
8792 | break; | |
8793 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 8794 | case INTEL_OUTPUT_HDMI: |
79e53945 | 8795 | is_sdvo = true; |
79e53945 | 8796 | break; |
6847d71b PZ |
8797 | default: |
8798 | break; | |
79e53945 JB |
8799 | } |
8800 | } | |
79e53945 | 8801 | |
c1858123 | 8802 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
8803 | factor = 21; |
8804 | if (is_lvds) { | |
8805 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 8806 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 8807 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8808 | factor = 25; |
190f68c5 | 8809 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8810 | factor = 20; |
c1858123 | 8811 | |
b75ca6f6 ACO |
8812 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
8813 | ||
190f68c5 | 8814 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
b75ca6f6 ACO |
8815 | fp |= FP_CB_TUNE; |
8816 | ||
8817 | if (reduced_clock) { | |
8818 | fp2 = i9xx_dpll_compute_fp(reduced_clock); | |
2c07245f | 8819 | |
b75ca6f6 ACO |
8820 | if (reduced_clock->m < factor * reduced_clock->n) |
8821 | fp2 |= FP_CB_TUNE; | |
8822 | } else { | |
8823 | fp2 = fp; | |
8824 | } | |
9a7c7890 | 8825 | |
5eddb70b | 8826 | dpll = 0; |
2c07245f | 8827 | |
a07d6787 EA |
8828 | if (is_lvds) |
8829 | dpll |= DPLLB_MODE_LVDS; | |
8830 | else | |
8831 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8832 | |
190f68c5 | 8833 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8834 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
8835 | |
8836 | if (is_sdvo) | |
4a33e48d | 8837 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 8838 | if (crtc_state->has_dp_encoder) |
4a33e48d | 8839 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8840 | |
a07d6787 | 8841 | /* compute bitmask from p1 value */ |
190f68c5 | 8842 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8843 | /* also FPA1 */ |
190f68c5 | 8844 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8845 | |
190f68c5 | 8846 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
8847 | case 5: |
8848 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
8849 | break; | |
8850 | case 7: | |
8851 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
8852 | break; | |
8853 | case 10: | |
8854 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
8855 | break; | |
8856 | case 14: | |
8857 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
8858 | break; | |
79e53945 JB |
8859 | } |
8860 | ||
ceb41007 | 8861 | if (is_lvds && intel_panel_use_ssc(dev_priv)) |
43565a06 | 8862 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
8863 | else |
8864 | dpll |= PLL_REF_INPUT_DREFCLK; | |
8865 | ||
b75ca6f6 ACO |
8866 | dpll |= DPLL_VCO_ENABLE; |
8867 | ||
8868 | crtc_state->dpll_hw_state.dpll = dpll; | |
8869 | crtc_state->dpll_hw_state.fp0 = fp; | |
8870 | crtc_state->dpll_hw_state.fp1 = fp2; | |
de13a2e3 PZ |
8871 | } |
8872 | ||
190f68c5 ACO |
8873 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
8874 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 8875 | { |
997c030c ACO |
8876 | struct drm_device *dev = crtc->base.dev; |
8877 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9e2c8475 | 8878 | struct dpll reduced_clock; |
7ed9f894 | 8879 | bool has_reduced_clock = false; |
e2b78267 | 8880 | struct intel_shared_dpll *pll; |
1b6f4958 | 8881 | const struct intel_limit *limit; |
997c030c | 8882 | int refclk = 120000; |
de13a2e3 | 8883 | |
dd3cd74a ACO |
8884 | memset(&crtc_state->dpll_hw_state, 0, |
8885 | sizeof(crtc_state->dpll_hw_state)); | |
8886 | ||
ded220e2 ACO |
8887 | crtc->lowfreq_avail = false; |
8888 | ||
8889 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ | |
8890 | if (!crtc_state->has_pch_encoder) | |
8891 | return 0; | |
79e53945 | 8892 | |
997c030c ACO |
8893 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
8894 | if (intel_panel_use_ssc(dev_priv)) { | |
8895 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", | |
8896 | dev_priv->vbt.lvds_ssc_freq); | |
8897 | refclk = dev_priv->vbt.lvds_ssc_freq; | |
8898 | } | |
8899 | ||
8900 | if (intel_is_dual_link_lvds(dev)) { | |
8901 | if (refclk == 100000) | |
8902 | limit = &intel_limits_ironlake_dual_lvds_100m; | |
8903 | else | |
8904 | limit = &intel_limits_ironlake_dual_lvds; | |
8905 | } else { | |
8906 | if (refclk == 100000) | |
8907 | limit = &intel_limits_ironlake_single_lvds_100m; | |
8908 | else | |
8909 | limit = &intel_limits_ironlake_single_lvds; | |
8910 | } | |
8911 | } else { | |
8912 | limit = &intel_limits_ironlake_dac; | |
8913 | } | |
8914 | ||
364ee29d | 8915 | if (!crtc_state->clock_set && |
997c030c ACO |
8916 | !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, |
8917 | refclk, NULL, &crtc_state->dpll)) { | |
364ee29d ACO |
8918 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
8919 | return -EINVAL; | |
f47709a9 | 8920 | } |
79e53945 | 8921 | |
b75ca6f6 ACO |
8922 | ironlake_compute_dpll(crtc, crtc_state, |
8923 | has_reduced_clock ? &reduced_clock : NULL); | |
66e985c0 | 8924 | |
ded220e2 ACO |
8925 | pll = intel_get_shared_dpll(crtc, crtc_state, NULL); |
8926 | if (pll == NULL) { | |
8927 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
8928 | pipe_name(crtc->pipe)); | |
8929 | return -EINVAL; | |
3fb37703 | 8930 | } |
79e53945 | 8931 | |
ded220e2 ACO |
8932 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
8933 | has_reduced_clock) | |
c7653199 | 8934 | crtc->lowfreq_avail = true; |
e2b78267 | 8935 | |
c8f7a0db | 8936 | return 0; |
79e53945 JB |
8937 | } |
8938 | ||
eb14cb74 VS |
8939 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
8940 | struct intel_link_m_n *m_n) | |
8941 | { | |
8942 | struct drm_device *dev = crtc->base.dev; | |
8943 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8944 | enum pipe pipe = crtc->pipe; | |
8945 | ||
8946 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
8947 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
8948 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8949 | & ~TU_SIZE_MASK; | |
8950 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
8951 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
8952 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8953 | } | |
8954 | ||
8955 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
8956 | enum transcoder transcoder, | |
b95af8be VK |
8957 | struct intel_link_m_n *m_n, |
8958 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
8959 | { |
8960 | struct drm_device *dev = crtc->base.dev; | |
8961 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 8962 | enum pipe pipe = crtc->pipe; |
72419203 | 8963 | |
eb14cb74 VS |
8964 | if (INTEL_INFO(dev)->gen >= 5) { |
8965 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
8966 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
8967 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
8968 | & ~TU_SIZE_MASK; | |
8969 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
8970 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
8971 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
8972 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
8973 | * gen < 8) and if DRRS is supported (to make sure the | |
8974 | * registers are not unnecessarily read). | |
8975 | */ | |
8976 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 8977 | crtc->config->has_drrs) { |
b95af8be VK |
8978 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
8979 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
8980 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
8981 | & ~TU_SIZE_MASK; | |
8982 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
8983 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
8984 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8985 | } | |
eb14cb74 VS |
8986 | } else { |
8987 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
8988 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
8989 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8990 | & ~TU_SIZE_MASK; | |
8991 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
8992 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
8993 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
8994 | } | |
8995 | } | |
8996 | ||
8997 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 8998 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 8999 | { |
681a8504 | 9000 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
9001 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
9002 | else | |
9003 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
9004 | &pipe_config->dp_m_n, |
9005 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 9006 | } |
72419203 | 9007 | |
eb14cb74 | 9008 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 9009 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
9010 | { |
9011 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 9012 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
9013 | } |
9014 | ||
bd2e244f | 9015 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9016 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
9017 | { |
9018 | struct drm_device *dev = crtc->base.dev; | |
9019 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a1b2278e CK |
9020 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
9021 | uint32_t ps_ctrl = 0; | |
9022 | int id = -1; | |
9023 | int i; | |
bd2e244f | 9024 | |
a1b2278e CK |
9025 | /* find scaler attached to this pipe */ |
9026 | for (i = 0; i < crtc->num_scalers; i++) { | |
9027 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9028 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9029 | id = i; | |
9030 | pipe_config->pch_pfit.enabled = true; | |
9031 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9032 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9033 | break; | |
9034 | } | |
9035 | } | |
bd2e244f | 9036 | |
a1b2278e CK |
9037 | scaler_state->scaler_id = id; |
9038 | if (id >= 0) { | |
9039 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9040 | } else { | |
9041 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9042 | } |
9043 | } | |
9044 | ||
5724dbd1 DL |
9045 | static void |
9046 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9047 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9048 | { |
9049 | struct drm_device *dev = crtc->base.dev; | |
9050 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 9051 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9052 | int pipe = crtc->pipe; |
9053 | int fourcc, pixel_format; | |
6761dd31 | 9054 | unsigned int aligned_height; |
bc8d7dff | 9055 | struct drm_framebuffer *fb; |
1b842c89 | 9056 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9057 | |
d9806c9f | 9058 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9059 | if (!intel_fb) { |
bc8d7dff DL |
9060 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9061 | return; | |
9062 | } | |
9063 | ||
1b842c89 DL |
9064 | fb = &intel_fb->base; |
9065 | ||
bc8d7dff | 9066 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9067 | if (!(val & PLANE_CTL_ENABLE)) |
9068 | goto error; | |
9069 | ||
bc8d7dff DL |
9070 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9071 | fourcc = skl_format_to_fourcc(pixel_format, | |
9072 | val & PLANE_CTL_ORDER_RGBX, | |
9073 | val & PLANE_CTL_ALPHA_MASK); | |
9074 | fb->pixel_format = fourcc; | |
9075 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9076 | ||
40f46283 DL |
9077 | tiling = val & PLANE_CTL_TILED_MASK; |
9078 | switch (tiling) { | |
9079 | case PLANE_CTL_TILED_LINEAR: | |
9080 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9081 | break; | |
9082 | case PLANE_CTL_TILED_X: | |
9083 | plane_config->tiling = I915_TILING_X; | |
9084 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9085 | break; | |
9086 | case PLANE_CTL_TILED_Y: | |
9087 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9088 | break; | |
9089 | case PLANE_CTL_TILED_YF: | |
9090 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9091 | break; | |
9092 | default: | |
9093 | MISSING_CASE(tiling); | |
9094 | goto error; | |
9095 | } | |
9096 | ||
bc8d7dff DL |
9097 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9098 | plane_config->base = base; | |
9099 | ||
9100 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9101 | ||
9102 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9103 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9104 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9105 | ||
9106 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
7b49f948 | 9107 | stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
40f46283 | 9108 | fb->pixel_format); |
bc8d7dff DL |
9109 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9110 | ||
9111 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9112 | fb->pixel_format, |
9113 | fb->modifier[0]); | |
bc8d7dff | 9114 | |
f37b5c2b | 9115 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9116 | |
9117 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9118 | pipe_name(pipe), fb->width, fb->height, | |
9119 | fb->bits_per_pixel, base, fb->pitches[0], | |
9120 | plane_config->size); | |
9121 | ||
2d14030b | 9122 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9123 | return; |
9124 | ||
9125 | error: | |
9126 | kfree(fb); | |
9127 | } | |
9128 | ||
2fa2fe9a | 9129 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9130 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9131 | { |
9132 | struct drm_device *dev = crtc->base.dev; | |
9133 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9134 | uint32_t tmp; | |
9135 | ||
9136 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9137 | ||
9138 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9139 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9140 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9141 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9142 | |
9143 | /* We currently do not free assignements of panel fitters on | |
9144 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9145 | * differentiates them) so just WARN about this case for now. */ | |
9146 | if (IS_GEN7(dev)) { | |
9147 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
9148 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9149 | } | |
2fa2fe9a | 9150 | } |
79e53945 JB |
9151 | } |
9152 | ||
5724dbd1 DL |
9153 | static void |
9154 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9155 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9156 | { |
9157 | struct drm_device *dev = crtc->base.dev; | |
9158 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9159 | u32 val, base, offset; | |
aeee5a49 | 9160 | int pipe = crtc->pipe; |
4c6baa59 | 9161 | int fourcc, pixel_format; |
6761dd31 | 9162 | unsigned int aligned_height; |
b113d5ee | 9163 | struct drm_framebuffer *fb; |
1b842c89 | 9164 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9165 | |
42a7b088 DL |
9166 | val = I915_READ(DSPCNTR(pipe)); |
9167 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9168 | return; | |
9169 | ||
d9806c9f | 9170 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9171 | if (!intel_fb) { |
4c6baa59 JB |
9172 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9173 | return; | |
9174 | } | |
9175 | ||
1b842c89 DL |
9176 | fb = &intel_fb->base; |
9177 | ||
18c5247e DV |
9178 | if (INTEL_INFO(dev)->gen >= 4) { |
9179 | if (val & DISPPLANE_TILED) { | |
49af449b | 9180 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9181 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9182 | } | |
9183 | } | |
4c6baa59 JB |
9184 | |
9185 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9186 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9187 | fb->pixel_format = fourcc; |
9188 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9189 | |
aeee5a49 | 9190 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 9191 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 9192 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9193 | } else { |
49af449b | 9194 | if (plane_config->tiling) |
aeee5a49 | 9195 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9196 | else |
aeee5a49 | 9197 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9198 | } |
9199 | plane_config->base = base; | |
9200 | ||
9201 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9202 | fb->width = ((val >> 16) & 0xfff) + 1; |
9203 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9204 | |
9205 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9206 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9207 | |
b113d5ee | 9208 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9209 | fb->pixel_format, |
9210 | fb->modifier[0]); | |
4c6baa59 | 9211 | |
f37b5c2b | 9212 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9213 | |
2844a921 DL |
9214 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9215 | pipe_name(pipe), fb->width, fb->height, | |
9216 | fb->bits_per_pixel, base, fb->pitches[0], | |
9217 | plane_config->size); | |
b113d5ee | 9218 | |
2d14030b | 9219 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9220 | } |
9221 | ||
0e8ffe1b | 9222 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9223 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9224 | { |
9225 | struct drm_device *dev = crtc->base.dev; | |
9226 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e | 9227 | enum intel_display_power_domain power_domain; |
0e8ffe1b | 9228 | uint32_t tmp; |
1729050e | 9229 | bool ret; |
0e8ffe1b | 9230 | |
1729050e ID |
9231 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9232 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
930e8c9e PZ |
9233 | return false; |
9234 | ||
e143a21c | 9235 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
8106ddbd | 9236 | pipe_config->shared_dpll = NULL; |
eccb140b | 9237 | |
1729050e | 9238 | ret = false; |
0e8ffe1b DV |
9239 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9240 | if (!(tmp & PIPECONF_ENABLE)) | |
1729050e | 9241 | goto out; |
0e8ffe1b | 9242 | |
42571aef VS |
9243 | switch (tmp & PIPECONF_BPC_MASK) { |
9244 | case PIPECONF_6BPC: | |
9245 | pipe_config->pipe_bpp = 18; | |
9246 | break; | |
9247 | case PIPECONF_8BPC: | |
9248 | pipe_config->pipe_bpp = 24; | |
9249 | break; | |
9250 | case PIPECONF_10BPC: | |
9251 | pipe_config->pipe_bpp = 30; | |
9252 | break; | |
9253 | case PIPECONF_12BPC: | |
9254 | pipe_config->pipe_bpp = 36; | |
9255 | break; | |
9256 | default: | |
9257 | break; | |
9258 | } | |
9259 | ||
b5a9fa09 DV |
9260 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9261 | pipe_config->limited_color_range = true; | |
9262 | ||
ab9412ba | 9263 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 | 9264 | struct intel_shared_dpll *pll; |
8106ddbd | 9265 | enum intel_dpll_id pll_id; |
66e985c0 | 9266 | |
88adfff1 DV |
9267 | pipe_config->has_pch_encoder = true; |
9268 | ||
627eb5a3 DV |
9269 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9270 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9271 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9272 | |
9273 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9274 | |
2d1fe073 | 9275 | if (HAS_PCH_IBX(dev_priv)) { |
d9a7bc67 ID |
9276 | /* |
9277 | * The pipe->pch transcoder and pch transcoder->pll | |
9278 | * mapping is fixed. | |
9279 | */ | |
8106ddbd | 9280 | pll_id = (enum intel_dpll_id) crtc->pipe; |
c0d43d62 DV |
9281 | } else { |
9282 | tmp = I915_READ(PCH_DPLL_SEL); | |
9283 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
8106ddbd | 9284 | pll_id = DPLL_ID_PCH_PLL_B; |
c0d43d62 | 9285 | else |
8106ddbd | 9286 | pll_id= DPLL_ID_PCH_PLL_A; |
c0d43d62 | 9287 | } |
66e985c0 | 9288 | |
8106ddbd ACO |
9289 | pipe_config->shared_dpll = |
9290 | intel_get_shared_dpll_by_id(dev_priv, pll_id); | |
9291 | pll = pipe_config->shared_dpll; | |
66e985c0 | 9292 | |
2edd6443 ACO |
9293 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
9294 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9295 | |
9296 | tmp = pipe_config->dpll_hw_state.dpll; | |
9297 | pipe_config->pixel_multiplier = | |
9298 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9299 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9300 | |
9301 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9302 | } else { |
9303 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9304 | } |
9305 | ||
1bd1bd80 | 9306 | intel_get_pipe_timings(crtc, pipe_config); |
bc58be60 | 9307 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 9308 | |
2fa2fe9a DV |
9309 | ironlake_get_pfit_config(crtc, pipe_config); |
9310 | ||
1729050e ID |
9311 | ret = true; |
9312 | ||
9313 | out: | |
9314 | intel_display_power_put(dev_priv, power_domain); | |
9315 | ||
9316 | return ret; | |
0e8ffe1b DV |
9317 | } |
9318 | ||
be256dc7 PZ |
9319 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9320 | { | |
9321 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 9322 | struct intel_crtc *crtc; |
be256dc7 | 9323 | |
d3fcc808 | 9324 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9325 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9326 | pipe_name(crtc->pipe)); |
9327 | ||
e2c719b7 RC |
9328 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9329 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
9330 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
9331 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
e2c719b7 RC |
9332 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
9333 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 9334 | "CPU PWM1 enabled\n"); |
c5107b87 | 9335 | if (IS_HASWELL(dev)) |
e2c719b7 | 9336 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 9337 | "CPU PWM2 enabled\n"); |
e2c719b7 | 9338 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 9339 | "PCH PWM1 enabled\n"); |
e2c719b7 | 9340 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 9341 | "Utility pin enabled\n"); |
e2c719b7 | 9342 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 9343 | |
9926ada1 PZ |
9344 | /* |
9345 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9346 | * interrupts remain enabled. We used to check for that, but since it's | |
9347 | * gen-specific and since we only disable LCPLL after we fully disable | |
9348 | * the interrupts, the check below should be enough. | |
9349 | */ | |
e2c719b7 | 9350 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
9351 | } |
9352 | ||
9ccd5aeb PZ |
9353 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
9354 | { | |
9355 | struct drm_device *dev = dev_priv->dev; | |
9356 | ||
9357 | if (IS_HASWELL(dev)) | |
9358 | return I915_READ(D_COMP_HSW); | |
9359 | else | |
9360 | return I915_READ(D_COMP_BDW); | |
9361 | } | |
9362 | ||
3c4c9b81 PZ |
9363 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
9364 | { | |
9365 | struct drm_device *dev = dev_priv->dev; | |
9366 | ||
9367 | if (IS_HASWELL(dev)) { | |
9368 | mutex_lock(&dev_priv->rps.hw_lock); | |
9369 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9370 | val)) | |
f475dadf | 9371 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
9372 | mutex_unlock(&dev_priv->rps.hw_lock); |
9373 | } else { | |
9ccd5aeb PZ |
9374 | I915_WRITE(D_COMP_BDW, val); |
9375 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 9376 | } |
be256dc7 PZ |
9377 | } |
9378 | ||
9379 | /* | |
9380 | * This function implements pieces of two sequences from BSpec: | |
9381 | * - Sequence for display software to disable LCPLL | |
9382 | * - Sequence for display software to allow package C8+ | |
9383 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9384 | * register. Callers should take care of disabling all the display engine | |
9385 | * functions, doing the mode unset, fixing interrupts, etc. | |
9386 | */ | |
6ff58d53 PZ |
9387 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9388 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9389 | { |
9390 | uint32_t val; | |
9391 | ||
9392 | assert_can_disable_lcpll(dev_priv); | |
9393 | ||
9394 | val = I915_READ(LCPLL_CTL); | |
9395 | ||
9396 | if (switch_to_fclk) { | |
9397 | val |= LCPLL_CD_SOURCE_FCLK; | |
9398 | I915_WRITE(LCPLL_CTL, val); | |
9399 | ||
9400 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9401 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9402 | DRM_ERROR("Switching to FCLK failed\n"); | |
9403 | ||
9404 | val = I915_READ(LCPLL_CTL); | |
9405 | } | |
9406 | ||
9407 | val |= LCPLL_PLL_DISABLE; | |
9408 | I915_WRITE(LCPLL_CTL, val); | |
9409 | POSTING_READ(LCPLL_CTL); | |
9410 | ||
9411 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
9412 | DRM_ERROR("LCPLL still locked\n"); | |
9413 | ||
9ccd5aeb | 9414 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9415 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9416 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9417 | ndelay(100); |
9418 | ||
9ccd5aeb PZ |
9419 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9420 | 1)) | |
be256dc7 PZ |
9421 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9422 | ||
9423 | if (allow_power_down) { | |
9424 | val = I915_READ(LCPLL_CTL); | |
9425 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9426 | I915_WRITE(LCPLL_CTL, val); | |
9427 | POSTING_READ(LCPLL_CTL); | |
9428 | } | |
9429 | } | |
9430 | ||
9431 | /* | |
9432 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9433 | * source. | |
9434 | */ | |
6ff58d53 | 9435 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9436 | { |
9437 | uint32_t val; | |
9438 | ||
9439 | val = I915_READ(LCPLL_CTL); | |
9440 | ||
9441 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9442 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9443 | return; | |
9444 | ||
a8a8bd54 PZ |
9445 | /* |
9446 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9447 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9448 | */ |
59bad947 | 9449 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9450 | |
be256dc7 PZ |
9451 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9452 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9453 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9454 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9455 | } |
9456 | ||
9ccd5aeb | 9457 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9458 | val |= D_COMP_COMP_FORCE; |
9459 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9460 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9461 | |
9462 | val = I915_READ(LCPLL_CTL); | |
9463 | val &= ~LCPLL_PLL_DISABLE; | |
9464 | I915_WRITE(LCPLL_CTL, val); | |
9465 | ||
9466 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
9467 | DRM_ERROR("LCPLL not locked yet\n"); | |
9468 | ||
9469 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9470 | val = I915_READ(LCPLL_CTL); | |
9471 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9472 | I915_WRITE(LCPLL_CTL, val); | |
9473 | ||
9474 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9475 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9476 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9477 | } | |
215733fa | 9478 | |
59bad947 | 9479 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b6283055 | 9480 | intel_update_cdclk(dev_priv->dev); |
be256dc7 PZ |
9481 | } |
9482 | ||
765dab67 PZ |
9483 | /* |
9484 | * Package states C8 and deeper are really deep PC states that can only be | |
9485 | * reached when all the devices on the system allow it, so even if the graphics | |
9486 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9487 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9488 | * | |
9489 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9490 | * well is disabled and most interrupts are disabled, and these are also | |
9491 | * requirements for runtime PM. When these conditions are met, we manually do | |
9492 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9493 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9494 | * hang the machine. | |
9495 | * | |
9496 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9497 | * the state of some registers, so when we come back from PC8+ we need to | |
9498 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9499 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9500 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9501 | * because of the runtime PM support). | |
9502 | * | |
9503 | * For more, read "Display Sequences for Package C8" on the hardware | |
9504 | * documentation. | |
9505 | */ | |
a14cb6fc | 9506 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9507 | { |
c67a470b PZ |
9508 | struct drm_device *dev = dev_priv->dev; |
9509 | uint32_t val; | |
9510 | ||
c67a470b PZ |
9511 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9512 | ||
c2699524 | 9513 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9514 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9515 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9516 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9517 | } | |
9518 | ||
9519 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9520 | hsw_disable_lcpll(dev_priv, true, true); |
9521 | } | |
9522 | ||
a14cb6fc | 9523 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
9524 | { |
9525 | struct drm_device *dev = dev_priv->dev; | |
9526 | uint32_t val; | |
9527 | ||
c67a470b PZ |
9528 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9529 | ||
9530 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9531 | lpt_init_pch_refclk(dev); |
9532 | ||
c2699524 | 9533 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9534 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9535 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9536 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9537 | } | |
c67a470b PZ |
9538 | } |
9539 | ||
27c329ed | 9540 | static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 9541 | { |
a821fc46 | 9542 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9543 | struct intel_atomic_state *old_intel_state = |
9544 | to_intel_atomic_state(old_state); | |
9545 | unsigned int req_cdclk = old_intel_state->dev_cdclk; | |
f8437dd1 | 9546 | |
c6c4696f | 9547 | broxton_set_cdclk(to_i915(dev), req_cdclk); |
f8437dd1 VK |
9548 | } |
9549 | ||
b432e5cf | 9550 | /* compute the max rate for new configuration */ |
27c329ed | 9551 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 9552 | { |
565602d7 ML |
9553 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
9554 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
9555 | struct drm_crtc *crtc; | |
9556 | struct drm_crtc_state *cstate; | |
27c329ed | 9557 | struct intel_crtc_state *crtc_state; |
565602d7 ML |
9558 | unsigned max_pixel_rate = 0, i; |
9559 | enum pipe pipe; | |
b432e5cf | 9560 | |
565602d7 ML |
9561 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
9562 | sizeof(intel_state->min_pixclk)); | |
27c329ed | 9563 | |
565602d7 ML |
9564 | for_each_crtc_in_state(state, crtc, cstate, i) { |
9565 | int pixel_rate; | |
27c329ed | 9566 | |
565602d7 ML |
9567 | crtc_state = to_intel_crtc_state(cstate); |
9568 | if (!crtc_state->base.enable) { | |
9569 | intel_state->min_pixclk[i] = 0; | |
b432e5cf | 9570 | continue; |
565602d7 | 9571 | } |
b432e5cf | 9572 | |
27c329ed | 9573 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf VS |
9574 | |
9575 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
565602d7 | 9576 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
b432e5cf VS |
9577 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
9578 | ||
565602d7 | 9579 | intel_state->min_pixclk[i] = pixel_rate; |
b432e5cf VS |
9580 | } |
9581 | ||
565602d7 ML |
9582 | for_each_pipe(dev_priv, pipe) |
9583 | max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate); | |
9584 | ||
b432e5cf VS |
9585 | return max_pixel_rate; |
9586 | } | |
9587 | ||
9588 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
9589 | { | |
9590 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9591 | uint32_t val, data; | |
9592 | int ret; | |
9593 | ||
9594 | if (WARN((I915_READ(LCPLL_CTL) & | |
9595 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
9596 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
9597 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
9598 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
9599 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
9600 | return; | |
9601 | ||
9602 | mutex_lock(&dev_priv->rps.hw_lock); | |
9603 | ret = sandybridge_pcode_write(dev_priv, | |
9604 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
9605 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9606 | if (ret) { | |
9607 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
9608 | return; | |
9609 | } | |
9610 | ||
9611 | val = I915_READ(LCPLL_CTL); | |
9612 | val |= LCPLL_CD_SOURCE_FCLK; | |
9613 | I915_WRITE(LCPLL_CTL, val); | |
9614 | ||
5ba00178 TU |
9615 | if (wait_for_us(I915_READ(LCPLL_CTL) & |
9616 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
b432e5cf VS |
9617 | DRM_ERROR("Switching to FCLK failed\n"); |
9618 | ||
9619 | val = I915_READ(LCPLL_CTL); | |
9620 | val &= ~LCPLL_CLK_FREQ_MASK; | |
9621 | ||
9622 | switch (cdclk) { | |
9623 | case 450000: | |
9624 | val |= LCPLL_CLK_FREQ_450; | |
9625 | data = 0; | |
9626 | break; | |
9627 | case 540000: | |
9628 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
9629 | data = 1; | |
9630 | break; | |
9631 | case 337500: | |
9632 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
9633 | data = 2; | |
9634 | break; | |
9635 | case 675000: | |
9636 | val |= LCPLL_CLK_FREQ_675_BDW; | |
9637 | data = 3; | |
9638 | break; | |
9639 | default: | |
9640 | WARN(1, "invalid cdclk frequency\n"); | |
9641 | return; | |
9642 | } | |
9643 | ||
9644 | I915_WRITE(LCPLL_CTL, val); | |
9645 | ||
9646 | val = I915_READ(LCPLL_CTL); | |
9647 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9648 | I915_WRITE(LCPLL_CTL, val); | |
9649 | ||
5ba00178 TU |
9650 | if (wait_for_us((I915_READ(LCPLL_CTL) & |
9651 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
b432e5cf VS |
9652 | DRM_ERROR("Switching back to LCPLL failed\n"); |
9653 | ||
9654 | mutex_lock(&dev_priv->rps.hw_lock); | |
9655 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
9656 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9657 | ||
7f1052a8 VS |
9658 | I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1); |
9659 | ||
b432e5cf VS |
9660 | intel_update_cdclk(dev); |
9661 | ||
9662 | WARN(cdclk != dev_priv->cdclk_freq, | |
9663 | "cdclk requested %d kHz but got %d kHz\n", | |
9664 | cdclk, dev_priv->cdclk_freq); | |
9665 | } | |
9666 | ||
587c7914 VS |
9667 | static int broadwell_calc_cdclk(int max_pixclk) |
9668 | { | |
9669 | if (max_pixclk > 540000) | |
9670 | return 675000; | |
9671 | else if (max_pixclk > 450000) | |
9672 | return 540000; | |
9673 | else if (max_pixclk > 337500) | |
9674 | return 450000; | |
9675 | else | |
9676 | return 337500; | |
9677 | } | |
9678 | ||
27c329ed | 9679 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 9680 | { |
27c329ed | 9681 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
1a617b77 | 9682 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
27c329ed | 9683 | int max_pixclk = ilk_max_pixel_rate(state); |
b432e5cf VS |
9684 | int cdclk; |
9685 | ||
9686 | /* | |
9687 | * FIXME should also account for plane ratio | |
9688 | * once 64bpp pixel formats are supported. | |
9689 | */ | |
587c7914 | 9690 | cdclk = broadwell_calc_cdclk(max_pixclk); |
b432e5cf | 9691 | |
b432e5cf | 9692 | if (cdclk > dev_priv->max_cdclk_freq) { |
63ba534e ML |
9693 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
9694 | cdclk, dev_priv->max_cdclk_freq); | |
9695 | return -EINVAL; | |
b432e5cf VS |
9696 | } |
9697 | ||
1a617b77 ML |
9698 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
9699 | if (!intel_state->active_crtcs) | |
587c7914 | 9700 | intel_state->dev_cdclk = broadwell_calc_cdclk(0); |
b432e5cf VS |
9701 | |
9702 | return 0; | |
9703 | } | |
9704 | ||
27c329ed | 9705 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 9706 | { |
27c329ed | 9707 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9708 | struct intel_atomic_state *old_intel_state = |
9709 | to_intel_atomic_state(old_state); | |
9710 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
b432e5cf | 9711 | |
27c329ed | 9712 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
9713 | } |
9714 | ||
190f68c5 ACO |
9715 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9716 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9717 | { |
af3997b5 MK |
9718 | struct intel_encoder *intel_encoder = |
9719 | intel_ddi_get_crtc_new_encoder(crtc_state); | |
9720 | ||
9721 | if (intel_encoder->type != INTEL_OUTPUT_DSI) { | |
9722 | if (!intel_ddi_pll_select(crtc, crtc_state)) | |
9723 | return -EINVAL; | |
9724 | } | |
716c2e55 | 9725 | |
c7653199 | 9726 | crtc->lowfreq_avail = false; |
644cef34 | 9727 | |
c8f7a0db | 9728 | return 0; |
79e53945 JB |
9729 | } |
9730 | ||
3760b59c S |
9731 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9732 | enum port port, | |
9733 | struct intel_crtc_state *pipe_config) | |
9734 | { | |
8106ddbd ACO |
9735 | enum intel_dpll_id id; |
9736 | ||
3760b59c S |
9737 | switch (port) { |
9738 | case PORT_A: | |
9739 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
08250c4b | 9740 | id = DPLL_ID_SKL_DPLL0; |
3760b59c S |
9741 | break; |
9742 | case PORT_B: | |
9743 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
08250c4b | 9744 | id = DPLL_ID_SKL_DPLL1; |
3760b59c S |
9745 | break; |
9746 | case PORT_C: | |
9747 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
08250c4b | 9748 | id = DPLL_ID_SKL_DPLL2; |
3760b59c S |
9749 | break; |
9750 | default: | |
9751 | DRM_ERROR("Incorrect port type\n"); | |
8106ddbd | 9752 | return; |
3760b59c | 9753 | } |
8106ddbd ACO |
9754 | |
9755 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
3760b59c S |
9756 | } |
9757 | ||
96b7dfb7 S |
9758 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9759 | enum port port, | |
5cec258b | 9760 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9761 | { |
8106ddbd | 9762 | enum intel_dpll_id id; |
a3c988ea | 9763 | u32 temp; |
96b7dfb7 S |
9764 | |
9765 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9766 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9767 | ||
9768 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 | 9769 | case SKL_DPLL0: |
a3c988ea ACO |
9770 | id = DPLL_ID_SKL_DPLL0; |
9771 | break; | |
96b7dfb7 | 9772 | case SKL_DPLL1: |
8106ddbd | 9773 | id = DPLL_ID_SKL_DPLL1; |
96b7dfb7 S |
9774 | break; |
9775 | case SKL_DPLL2: | |
8106ddbd | 9776 | id = DPLL_ID_SKL_DPLL2; |
96b7dfb7 S |
9777 | break; |
9778 | case SKL_DPLL3: | |
8106ddbd | 9779 | id = DPLL_ID_SKL_DPLL3; |
96b7dfb7 | 9780 | break; |
8106ddbd ACO |
9781 | default: |
9782 | MISSING_CASE(pipe_config->ddi_pll_sel); | |
9783 | return; | |
96b7dfb7 | 9784 | } |
8106ddbd ACO |
9785 | |
9786 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
96b7dfb7 S |
9787 | } |
9788 | ||
7d2c8175 DL |
9789 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9790 | enum port port, | |
5cec258b | 9791 | struct intel_crtc_state *pipe_config) |
7d2c8175 | 9792 | { |
8106ddbd ACO |
9793 | enum intel_dpll_id id; |
9794 | ||
7d2c8175 DL |
9795 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); |
9796 | ||
9797 | switch (pipe_config->ddi_pll_sel) { | |
9798 | case PORT_CLK_SEL_WRPLL1: | |
8106ddbd | 9799 | id = DPLL_ID_WRPLL1; |
7d2c8175 DL |
9800 | break; |
9801 | case PORT_CLK_SEL_WRPLL2: | |
8106ddbd | 9802 | id = DPLL_ID_WRPLL2; |
7d2c8175 | 9803 | break; |
00490c22 | 9804 | case PORT_CLK_SEL_SPLL: |
8106ddbd | 9805 | id = DPLL_ID_SPLL; |
79bd23da | 9806 | break; |
9d16da65 ACO |
9807 | case PORT_CLK_SEL_LCPLL_810: |
9808 | id = DPLL_ID_LCPLL_810; | |
9809 | break; | |
9810 | case PORT_CLK_SEL_LCPLL_1350: | |
9811 | id = DPLL_ID_LCPLL_1350; | |
9812 | break; | |
9813 | case PORT_CLK_SEL_LCPLL_2700: | |
9814 | id = DPLL_ID_LCPLL_2700; | |
9815 | break; | |
8106ddbd ACO |
9816 | default: |
9817 | MISSING_CASE(pipe_config->ddi_pll_sel); | |
9818 | /* fall through */ | |
9819 | case PORT_CLK_SEL_NONE: | |
8106ddbd | 9820 | return; |
7d2c8175 | 9821 | } |
8106ddbd ACO |
9822 | |
9823 | pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id); | |
7d2c8175 DL |
9824 | } |
9825 | ||
cf30429e JN |
9826 | static bool hsw_get_transcoder_state(struct intel_crtc *crtc, |
9827 | struct intel_crtc_state *pipe_config, | |
9828 | unsigned long *power_domain_mask) | |
9829 | { | |
9830 | struct drm_device *dev = crtc->base.dev; | |
9831 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9832 | enum intel_display_power_domain power_domain; | |
9833 | u32 tmp; | |
9834 | ||
d9a7bc67 ID |
9835 | /* |
9836 | * The pipe->transcoder mapping is fixed with the exception of the eDP | |
9837 | * transcoder handled below. | |
9838 | */ | |
cf30429e JN |
9839 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
9840 | ||
9841 | /* | |
9842 | * XXX: Do intel_display_power_get_if_enabled before reading this (for | |
9843 | * consistency and less surprising code; it's in always on power). | |
9844 | */ | |
9845 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
9846 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9847 | enum pipe trans_edp_pipe; | |
9848 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9849 | default: | |
9850 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9851 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9852 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9853 | trans_edp_pipe = PIPE_A; | |
9854 | break; | |
9855 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9856 | trans_edp_pipe = PIPE_B; | |
9857 | break; | |
9858 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
9859 | trans_edp_pipe = PIPE_C; | |
9860 | break; | |
9861 | } | |
9862 | ||
9863 | if (trans_edp_pipe == crtc->pipe) | |
9864 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
9865 | } | |
9866 | ||
9867 | power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder); | |
9868 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
9869 | return false; | |
9870 | *power_domain_mask |= BIT(power_domain); | |
9871 | ||
9872 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); | |
9873 | ||
9874 | return tmp & PIPECONF_ENABLE; | |
9875 | } | |
9876 | ||
4d1de975 JN |
9877 | static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc, |
9878 | struct intel_crtc_state *pipe_config, | |
9879 | unsigned long *power_domain_mask) | |
9880 | { | |
9881 | struct drm_device *dev = crtc->base.dev; | |
9882 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9883 | enum intel_display_power_domain power_domain; | |
9884 | enum port port; | |
9885 | enum transcoder cpu_transcoder; | |
9886 | u32 tmp; | |
9887 | ||
9888 | pipe_config->has_dsi_encoder = false; | |
9889 | ||
9890 | for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) { | |
9891 | if (port == PORT_A) | |
9892 | cpu_transcoder = TRANSCODER_DSI_A; | |
9893 | else | |
9894 | cpu_transcoder = TRANSCODER_DSI_C; | |
9895 | ||
9896 | power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder); | |
9897 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
9898 | continue; | |
9899 | *power_domain_mask |= BIT(power_domain); | |
9900 | ||
db18b6a6 ID |
9901 | /* |
9902 | * The PLL needs to be enabled with a valid divider | |
9903 | * configuration, otherwise accessing DSI registers will hang | |
9904 | * the machine. See BSpec North Display Engine | |
9905 | * registers/MIPI[BXT]. We can break out here early, since we | |
9906 | * need the same DSI PLL to be enabled for both DSI ports. | |
9907 | */ | |
9908 | if (!intel_dsi_pll_is_enabled(dev_priv)) | |
9909 | break; | |
9910 | ||
4d1de975 JN |
9911 | /* XXX: this works for video mode only */ |
9912 | tmp = I915_READ(BXT_MIPI_PORT_CTRL(port)); | |
9913 | if (!(tmp & DPI_ENABLE)) | |
9914 | continue; | |
9915 | ||
9916 | tmp = I915_READ(MIPI_CTRL(port)); | |
9917 | if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe)) | |
9918 | continue; | |
9919 | ||
9920 | pipe_config->cpu_transcoder = cpu_transcoder; | |
9921 | pipe_config->has_dsi_encoder = true; | |
9922 | break; | |
9923 | } | |
9924 | ||
9925 | return pipe_config->has_dsi_encoder; | |
9926 | } | |
9927 | ||
26804afd | 9928 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9929 | struct intel_crtc_state *pipe_config) |
26804afd DV |
9930 | { |
9931 | struct drm_device *dev = crtc->base.dev; | |
9932 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 9933 | struct intel_shared_dpll *pll; |
26804afd DV |
9934 | enum port port; |
9935 | uint32_t tmp; | |
9936 | ||
9937 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9938 | ||
9939 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9940 | ||
ef11bdb3 | 9941 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
96b7dfb7 | 9942 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
3760b59c S |
9943 | else if (IS_BROXTON(dev)) |
9944 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
9945 | else |
9946 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9947 | |
8106ddbd ACO |
9948 | pll = pipe_config->shared_dpll; |
9949 | if (pll) { | |
2edd6443 ACO |
9950 | WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll, |
9951 | &pipe_config->dpll_hw_state)); | |
d452c5b6 DV |
9952 | } |
9953 | ||
26804afd DV |
9954 | /* |
9955 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9956 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9957 | * the PCH transcoder is on. | |
9958 | */ | |
ca370455 DL |
9959 | if (INTEL_INFO(dev)->gen < 9 && |
9960 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
9961 | pipe_config->has_pch_encoder = true; |
9962 | ||
9963 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9964 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9965 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9966 | ||
9967 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9968 | } | |
9969 | } | |
9970 | ||
0e8ffe1b | 9971 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9972 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9973 | { |
9974 | struct drm_device *dev = crtc->base.dev; | |
9975 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1729050e ID |
9976 | enum intel_display_power_domain power_domain; |
9977 | unsigned long power_domain_mask; | |
cf30429e | 9978 | bool active; |
0e8ffe1b | 9979 | |
1729050e ID |
9980 | power_domain = POWER_DOMAIN_PIPE(crtc->pipe); |
9981 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b5482bd0 | 9982 | return false; |
1729050e ID |
9983 | power_domain_mask = BIT(power_domain); |
9984 | ||
8106ddbd | 9985 | pipe_config->shared_dpll = NULL; |
c0d43d62 | 9986 | |
cf30429e | 9987 | active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask); |
eccb140b | 9988 | |
4d1de975 JN |
9989 | if (IS_BROXTON(dev_priv)) { |
9990 | bxt_get_dsi_transcoder_state(crtc, pipe_config, | |
9991 | &power_domain_mask); | |
9992 | WARN_ON(active && pipe_config->has_dsi_encoder); | |
9993 | if (pipe_config->has_dsi_encoder) | |
9994 | active = true; | |
9995 | } | |
9996 | ||
cf30429e | 9997 | if (!active) |
1729050e | 9998 | goto out; |
0e8ffe1b | 9999 | |
4d1de975 JN |
10000 | if (!pipe_config->has_dsi_encoder) { |
10001 | haswell_get_ddi_port_state(crtc, pipe_config); | |
10002 | intel_get_pipe_timings(crtc, pipe_config); | |
10003 | } | |
627eb5a3 | 10004 | |
bc58be60 | 10005 | intel_get_pipe_src_size(crtc, pipe_config); |
1bd1bd80 | 10006 | |
05dc698c LL |
10007 | pipe_config->gamma_mode = |
10008 | I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK; | |
10009 | ||
a1b2278e CK |
10010 | if (INTEL_INFO(dev)->gen >= 9) { |
10011 | skl_init_scalers(dev, crtc, pipe_config); | |
10012 | } | |
10013 | ||
af99ceda CK |
10014 | if (INTEL_INFO(dev)->gen >= 9) { |
10015 | pipe_config->scaler_state.scaler_id = -1; | |
10016 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
10017 | } | |
10018 | ||
1729050e ID |
10019 | power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
10020 | if (intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
10021 | power_domain_mask |= BIT(power_domain); | |
1c132b44 | 10022 | if (INTEL_INFO(dev)->gen >= 9) |
bd2e244f | 10023 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 10024 | else |
1c132b44 | 10025 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 10026 | } |
88adfff1 | 10027 | |
e59150dc JB |
10028 | if (IS_HASWELL(dev)) |
10029 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
10030 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 10031 | |
4d1de975 JN |
10032 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP && |
10033 | !transcoder_is_dsi(pipe_config->cpu_transcoder)) { | |
ebb69c95 CT |
10034 | pipe_config->pixel_multiplier = |
10035 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
10036 | } else { | |
10037 | pipe_config->pixel_multiplier = 1; | |
10038 | } | |
6c49f241 | 10039 | |
1729050e ID |
10040 | out: |
10041 | for_each_power_domain(power_domain, power_domain_mask) | |
10042 | intel_display_power_put(dev_priv, power_domain); | |
10043 | ||
cf30429e | 10044 | return active; |
0e8ffe1b DV |
10045 | } |
10046 | ||
55a08b3f ML |
10047 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, |
10048 | const struct intel_plane_state *plane_state) | |
560b85bb CW |
10049 | { |
10050 | struct drm_device *dev = crtc->dev; | |
10051 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10052 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 10053 | uint32_t cntl = 0, size = 0; |
560b85bb | 10054 | |
55a08b3f ML |
10055 | if (plane_state && plane_state->visible) { |
10056 | unsigned int width = plane_state->base.crtc_w; | |
10057 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 VS |
10058 | unsigned int stride = roundup_pow_of_two(width) * 4; |
10059 | ||
10060 | switch (stride) { | |
10061 | default: | |
10062 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
10063 | width, stride); | |
10064 | stride = 256; | |
10065 | /* fallthrough */ | |
10066 | case 256: | |
10067 | case 512: | |
10068 | case 1024: | |
10069 | case 2048: | |
10070 | break; | |
4b0e333e CW |
10071 | } |
10072 | ||
dc41c154 VS |
10073 | cntl |= CURSOR_ENABLE | |
10074 | CURSOR_GAMMA_ENABLE | | |
10075 | CURSOR_FORMAT_ARGB | | |
10076 | CURSOR_STRIDE(stride); | |
10077 | ||
10078 | size = (height << 12) | width; | |
4b0e333e | 10079 | } |
560b85bb | 10080 | |
dc41c154 VS |
10081 | if (intel_crtc->cursor_cntl != 0 && |
10082 | (intel_crtc->cursor_base != base || | |
10083 | intel_crtc->cursor_size != size || | |
10084 | intel_crtc->cursor_cntl != cntl)) { | |
10085 | /* On these chipsets we can only modify the base/size/stride | |
10086 | * whilst the cursor is disabled. | |
10087 | */ | |
0b87c24e VS |
10088 | I915_WRITE(CURCNTR(PIPE_A), 0); |
10089 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 10090 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 10091 | } |
560b85bb | 10092 | |
99d1f387 | 10093 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 10094 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
10095 | intel_crtc->cursor_base = base; |
10096 | } | |
4726e0b0 | 10097 | |
dc41c154 VS |
10098 | if (intel_crtc->cursor_size != size) { |
10099 | I915_WRITE(CURSIZE, size); | |
10100 | intel_crtc->cursor_size = size; | |
4b0e333e | 10101 | } |
560b85bb | 10102 | |
4b0e333e | 10103 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
10104 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
10105 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 10106 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 10107 | } |
560b85bb CW |
10108 | } |
10109 | ||
55a08b3f ML |
10110 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, |
10111 | const struct intel_plane_state *plane_state) | |
65a21cd6 JB |
10112 | { |
10113 | struct drm_device *dev = crtc->dev; | |
10114 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10115 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10116 | int pipe = intel_crtc->pipe; | |
663f3122 | 10117 | uint32_t cntl = 0; |
4b0e333e | 10118 | |
55a08b3f | 10119 | if (plane_state && plane_state->visible) { |
4b0e333e | 10120 | cntl = MCURSOR_GAMMA_ENABLE; |
55a08b3f | 10121 | switch (plane_state->base.crtc_w) { |
4726e0b0 SK |
10122 | case 64: |
10123 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
10124 | break; | |
10125 | case 128: | |
10126 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
10127 | break; | |
10128 | case 256: | |
10129 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
10130 | break; | |
10131 | default: | |
55a08b3f | 10132 | MISSING_CASE(plane_state->base.crtc_w); |
4726e0b0 | 10133 | return; |
65a21cd6 | 10134 | } |
4b0e333e | 10135 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 10136 | |
fc6f93bc | 10137 | if (HAS_DDI(dev)) |
47bf17a7 | 10138 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
65a21cd6 | 10139 | |
55a08b3f ML |
10140 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) |
10141 | cntl |= CURSOR_ROTATE_180; | |
10142 | } | |
4398ad45 | 10143 | |
4b0e333e CW |
10144 | if (intel_crtc->cursor_cntl != cntl) { |
10145 | I915_WRITE(CURCNTR(pipe), cntl); | |
10146 | POSTING_READ(CURCNTR(pipe)); | |
10147 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 10148 | } |
4b0e333e | 10149 | |
65a21cd6 | 10150 | /* and commit changes on next vblank */ |
5efb3e28 VS |
10151 | I915_WRITE(CURBASE(pipe), base); |
10152 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
10153 | |
10154 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
10155 | } |
10156 | ||
cda4b7d3 | 10157 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f | 10158 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
55a08b3f | 10159 | const struct intel_plane_state *plane_state) |
cda4b7d3 CW |
10160 | { |
10161 | struct drm_device *dev = crtc->dev; | |
10162 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10163 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10164 | int pipe = intel_crtc->pipe; | |
55a08b3f ML |
10165 | u32 base = intel_crtc->cursor_addr; |
10166 | u32 pos = 0; | |
cda4b7d3 | 10167 | |
55a08b3f ML |
10168 | if (plane_state) { |
10169 | int x = plane_state->base.crtc_x; | |
10170 | int y = plane_state->base.crtc_y; | |
cda4b7d3 | 10171 | |
55a08b3f ML |
10172 | if (x < 0) { |
10173 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10174 | x = -x; | |
10175 | } | |
10176 | pos |= x << CURSOR_X_SHIFT; | |
cda4b7d3 | 10177 | |
55a08b3f ML |
10178 | if (y < 0) { |
10179 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10180 | y = -y; | |
10181 | } | |
10182 | pos |= y << CURSOR_Y_SHIFT; | |
10183 | ||
10184 | /* ILK+ do this automagically */ | |
10185 | if (HAS_GMCH_DISPLAY(dev) && | |
10186 | plane_state->base.rotation == BIT(DRM_ROTATE_180)) { | |
10187 | base += (plane_state->base.crtc_h * | |
10188 | plane_state->base.crtc_w - 1) * 4; | |
10189 | } | |
cda4b7d3 | 10190 | } |
cda4b7d3 | 10191 | |
5efb3e28 VS |
10192 | I915_WRITE(CURPOS(pipe), pos); |
10193 | ||
8ac54669 | 10194 | if (IS_845G(dev) || IS_I865G(dev)) |
55a08b3f | 10195 | i845_update_cursor(crtc, base, plane_state); |
5efb3e28 | 10196 | else |
55a08b3f | 10197 | i9xx_update_cursor(crtc, base, plane_state); |
cda4b7d3 CW |
10198 | } |
10199 | ||
dc41c154 VS |
10200 | static bool cursor_size_ok(struct drm_device *dev, |
10201 | uint32_t width, uint32_t height) | |
10202 | { | |
10203 | if (width == 0 || height == 0) | |
10204 | return false; | |
10205 | ||
10206 | /* | |
10207 | * 845g/865g are special in that they are only limited by | |
10208 | * the width of their cursors, the height is arbitrary up to | |
10209 | * the precision of the register. Everything else requires | |
10210 | * square cursors, limited to a few power-of-two sizes. | |
10211 | */ | |
10212 | if (IS_845G(dev) || IS_I865G(dev)) { | |
10213 | if ((width & 63) != 0) | |
10214 | return false; | |
10215 | ||
10216 | if (width > (IS_845G(dev) ? 64 : 512)) | |
10217 | return false; | |
10218 | ||
10219 | if (height > 1023) | |
10220 | return false; | |
10221 | } else { | |
10222 | switch (width | height) { | |
10223 | case 256: | |
10224 | case 128: | |
10225 | if (IS_GEN2(dev)) | |
10226 | return false; | |
10227 | case 64: | |
10228 | break; | |
10229 | default: | |
10230 | return false; | |
10231 | } | |
10232 | } | |
10233 | ||
10234 | return true; | |
10235 | } | |
10236 | ||
79e53945 JB |
10237 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10238 | static struct drm_display_mode load_detect_mode = { | |
10239 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10240 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10241 | }; | |
10242 | ||
a8bb6818 DV |
10243 | struct drm_framebuffer * |
10244 | __intel_framebuffer_create(struct drm_device *dev, | |
10245 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10246 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10247 | { |
10248 | struct intel_framebuffer *intel_fb; | |
10249 | int ret; | |
10250 | ||
10251 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 10252 | if (!intel_fb) |
d2dff872 | 10253 | return ERR_PTR(-ENOMEM); |
d2dff872 CW |
10254 | |
10255 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10256 | if (ret) |
10257 | goto err; | |
d2dff872 CW |
10258 | |
10259 | return &intel_fb->base; | |
dcb1394e | 10260 | |
dd4916c5 | 10261 | err: |
dd4916c5 | 10262 | kfree(intel_fb); |
dd4916c5 | 10263 | return ERR_PTR(ret); |
d2dff872 CW |
10264 | } |
10265 | ||
b5ea642a | 10266 | static struct drm_framebuffer * |
a8bb6818 DV |
10267 | intel_framebuffer_create(struct drm_device *dev, |
10268 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10269 | struct drm_i915_gem_object *obj) | |
10270 | { | |
10271 | struct drm_framebuffer *fb; | |
10272 | int ret; | |
10273 | ||
10274 | ret = i915_mutex_lock_interruptible(dev); | |
10275 | if (ret) | |
10276 | return ERR_PTR(ret); | |
10277 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10278 | mutex_unlock(&dev->struct_mutex); | |
10279 | ||
10280 | return fb; | |
10281 | } | |
10282 | ||
d2dff872 CW |
10283 | static u32 |
10284 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10285 | { | |
10286 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10287 | return ALIGN(pitch, 64); | |
10288 | } | |
10289 | ||
10290 | static u32 | |
10291 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10292 | { | |
10293 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 10294 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
10295 | } |
10296 | ||
10297 | static struct drm_framebuffer * | |
10298 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10299 | struct drm_display_mode *mode, | |
10300 | int depth, int bpp) | |
10301 | { | |
dcb1394e | 10302 | struct drm_framebuffer *fb; |
d2dff872 | 10303 | struct drm_i915_gem_object *obj; |
0fed39bd | 10304 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 | 10305 | |
d37cd8a8 | 10306 | obj = i915_gem_object_create(dev, |
d2dff872 | 10307 | intel_framebuffer_size_for_mode(mode, bpp)); |
fe3db79b CW |
10308 | if (IS_ERR(obj)) |
10309 | return ERR_CAST(obj); | |
d2dff872 CW |
10310 | |
10311 | mode_cmd.width = mode->hdisplay; | |
10312 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
10313 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10314 | bpp); | |
5ca0c34a | 10315 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 10316 | |
dcb1394e LW |
10317 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
10318 | if (IS_ERR(fb)) | |
10319 | drm_gem_object_unreference_unlocked(&obj->base); | |
10320 | ||
10321 | return fb; | |
d2dff872 CW |
10322 | } |
10323 | ||
10324 | static struct drm_framebuffer * | |
10325 | mode_fits_in_fbdev(struct drm_device *dev, | |
10326 | struct drm_display_mode *mode) | |
10327 | { | |
0695726e | 10328 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
d2dff872 CW |
10329 | struct drm_i915_private *dev_priv = dev->dev_private; |
10330 | struct drm_i915_gem_object *obj; | |
10331 | struct drm_framebuffer *fb; | |
10332 | ||
4c0e5528 | 10333 | if (!dev_priv->fbdev) |
d2dff872 CW |
10334 | return NULL; |
10335 | ||
4c0e5528 | 10336 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
10337 | return NULL; |
10338 | ||
4c0e5528 DV |
10339 | obj = dev_priv->fbdev->fb->obj; |
10340 | BUG_ON(!obj); | |
10341 | ||
8bcd4553 | 10342 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
10343 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
10344 | fb->bits_per_pixel)) | |
d2dff872 CW |
10345 | return NULL; |
10346 | ||
01f2c773 | 10347 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
10348 | return NULL; |
10349 | ||
edde3617 | 10350 | drm_framebuffer_reference(fb); |
d2dff872 | 10351 | return fb; |
4520f53a DV |
10352 | #else |
10353 | return NULL; | |
10354 | #endif | |
d2dff872 CW |
10355 | } |
10356 | ||
d3a40d1b ACO |
10357 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
10358 | struct drm_crtc *crtc, | |
10359 | struct drm_display_mode *mode, | |
10360 | struct drm_framebuffer *fb, | |
10361 | int x, int y) | |
10362 | { | |
10363 | struct drm_plane_state *plane_state; | |
10364 | int hdisplay, vdisplay; | |
10365 | int ret; | |
10366 | ||
10367 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
10368 | if (IS_ERR(plane_state)) | |
10369 | return PTR_ERR(plane_state); | |
10370 | ||
10371 | if (mode) | |
10372 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
10373 | else | |
10374 | hdisplay = vdisplay = 0; | |
10375 | ||
10376 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
10377 | if (ret) | |
10378 | return ret; | |
10379 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10380 | plane_state->crtc_x = 0; | |
10381 | plane_state->crtc_y = 0; | |
10382 | plane_state->crtc_w = hdisplay; | |
10383 | plane_state->crtc_h = vdisplay; | |
10384 | plane_state->src_x = x << 16; | |
10385 | plane_state->src_y = y << 16; | |
10386 | plane_state->src_w = hdisplay << 16; | |
10387 | plane_state->src_h = vdisplay << 16; | |
10388 | ||
10389 | return 0; | |
10390 | } | |
10391 | ||
d2434ab7 | 10392 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 10393 | struct drm_display_mode *mode, |
51fd371b RC |
10394 | struct intel_load_detect_pipe *old, |
10395 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
10396 | { |
10397 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
10398 | struct intel_encoder *intel_encoder = |
10399 | intel_attached_encoder(connector); | |
79e53945 | 10400 | struct drm_crtc *possible_crtc; |
4ef69c7a | 10401 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
10402 | struct drm_crtc *crtc = NULL; |
10403 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 10404 | struct drm_framebuffer *fb; |
51fd371b | 10405 | struct drm_mode_config *config = &dev->mode_config; |
edde3617 | 10406 | struct drm_atomic_state *state = NULL, *restore_state = NULL; |
944b0c76 | 10407 | struct drm_connector_state *connector_state; |
4be07317 | 10408 | struct intel_crtc_state *crtc_state; |
51fd371b | 10409 | int ret, i = -1; |
79e53945 | 10410 | |
d2dff872 | 10411 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10412 | connector->base.id, connector->name, |
8e329a03 | 10413 | encoder->base.id, encoder->name); |
d2dff872 | 10414 | |
edde3617 ML |
10415 | old->restore_state = NULL; |
10416 | ||
51fd371b RC |
10417 | retry: |
10418 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
10419 | if (ret) | |
ad3c558f | 10420 | goto fail; |
6e9f798d | 10421 | |
79e53945 JB |
10422 | /* |
10423 | * Algorithm gets a little messy: | |
7a5e4805 | 10424 | * |
79e53945 JB |
10425 | * - if the connector already has an assigned crtc, use it (but make |
10426 | * sure it's on first) | |
7a5e4805 | 10427 | * |
79e53945 JB |
10428 | * - try to find the first unused crtc that can drive this connector, |
10429 | * and use that if we find one | |
79e53945 JB |
10430 | */ |
10431 | ||
10432 | /* See if we already have a CRTC for this connector */ | |
edde3617 ML |
10433 | if (connector->state->crtc) { |
10434 | crtc = connector->state->crtc; | |
8261b191 | 10435 | |
51fd371b | 10436 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 10437 | if (ret) |
ad3c558f | 10438 | goto fail; |
8261b191 CW |
10439 | |
10440 | /* Make sure the crtc and connector are running */ | |
edde3617 | 10441 | goto found; |
79e53945 JB |
10442 | } |
10443 | ||
10444 | /* Find an unused one (if possible) */ | |
70e1e0ec | 10445 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
10446 | i++; |
10447 | if (!(encoder->possible_crtcs & (1 << i))) | |
10448 | continue; | |
edde3617 ML |
10449 | |
10450 | ret = drm_modeset_lock(&possible_crtc->mutex, ctx); | |
10451 | if (ret) | |
10452 | goto fail; | |
10453 | ||
10454 | if (possible_crtc->state->enable) { | |
10455 | drm_modeset_unlock(&possible_crtc->mutex); | |
a459249c | 10456 | continue; |
edde3617 | 10457 | } |
a459249c VS |
10458 | |
10459 | crtc = possible_crtc; | |
10460 | break; | |
79e53945 JB |
10461 | } |
10462 | ||
10463 | /* | |
10464 | * If we didn't find an unused CRTC, don't use any. | |
10465 | */ | |
10466 | if (!crtc) { | |
7173188d | 10467 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 10468 | goto fail; |
79e53945 JB |
10469 | } |
10470 | ||
edde3617 ML |
10471 | found: |
10472 | intel_crtc = to_intel_crtc(crtc); | |
10473 | ||
4d02e2de DV |
10474 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
10475 | if (ret) | |
ad3c558f | 10476 | goto fail; |
79e53945 | 10477 | |
83a57153 | 10478 | state = drm_atomic_state_alloc(dev); |
edde3617 ML |
10479 | restore_state = drm_atomic_state_alloc(dev); |
10480 | if (!state || !restore_state) { | |
10481 | ret = -ENOMEM; | |
10482 | goto fail; | |
10483 | } | |
83a57153 ACO |
10484 | |
10485 | state->acquire_ctx = ctx; | |
edde3617 | 10486 | restore_state->acquire_ctx = ctx; |
83a57153 | 10487 | |
944b0c76 ACO |
10488 | connector_state = drm_atomic_get_connector_state(state, connector); |
10489 | if (IS_ERR(connector_state)) { | |
10490 | ret = PTR_ERR(connector_state); | |
10491 | goto fail; | |
10492 | } | |
10493 | ||
edde3617 ML |
10494 | ret = drm_atomic_set_crtc_for_connector(connector_state, crtc); |
10495 | if (ret) | |
10496 | goto fail; | |
944b0c76 | 10497 | |
4be07317 ACO |
10498 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10499 | if (IS_ERR(crtc_state)) { | |
10500 | ret = PTR_ERR(crtc_state); | |
10501 | goto fail; | |
10502 | } | |
10503 | ||
49d6fa21 | 10504 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 10505 | |
6492711d CW |
10506 | if (!mode) |
10507 | mode = &load_detect_mode; | |
79e53945 | 10508 | |
d2dff872 CW |
10509 | /* We need a framebuffer large enough to accommodate all accesses |
10510 | * that the plane may generate whilst we perform load detection. | |
10511 | * We can not rely on the fbcon either being present (we get called | |
10512 | * during its initialisation to detect all boot displays, or it may | |
10513 | * not even exist) or that it is large enough to satisfy the | |
10514 | * requested mode. | |
10515 | */ | |
94352cf9 DV |
10516 | fb = mode_fits_in_fbdev(dev, mode); |
10517 | if (fb == NULL) { | |
d2dff872 | 10518 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 | 10519 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
d2dff872 CW |
10520 | } else |
10521 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10522 | if (IS_ERR(fb)) { |
d2dff872 | 10523 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 10524 | goto fail; |
79e53945 | 10525 | } |
79e53945 | 10526 | |
d3a40d1b ACO |
10527 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10528 | if (ret) | |
10529 | goto fail; | |
10530 | ||
edde3617 ML |
10531 | drm_framebuffer_unreference(fb); |
10532 | ||
10533 | ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode); | |
10534 | if (ret) | |
10535 | goto fail; | |
10536 | ||
10537 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector)); | |
10538 | if (!ret) | |
10539 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc)); | |
10540 | if (!ret) | |
10541 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary)); | |
10542 | if (ret) { | |
10543 | DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret); | |
10544 | goto fail; | |
10545 | } | |
8c7b5ccb | 10546 | |
3ba86073 ML |
10547 | ret = drm_atomic_commit(state); |
10548 | if (ret) { | |
6492711d | 10549 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
412b61d8 | 10550 | goto fail; |
79e53945 | 10551 | } |
edde3617 ML |
10552 | |
10553 | old->restore_state = restore_state; | |
7173188d | 10554 | |
79e53945 | 10555 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 10556 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 10557 | return true; |
412b61d8 | 10558 | |
ad3c558f | 10559 | fail: |
e5d958ef | 10560 | drm_atomic_state_free(state); |
edde3617 ML |
10561 | drm_atomic_state_free(restore_state); |
10562 | restore_state = state = NULL; | |
83a57153 | 10563 | |
51fd371b RC |
10564 | if (ret == -EDEADLK) { |
10565 | drm_modeset_backoff(ctx); | |
10566 | goto retry; | |
10567 | } | |
10568 | ||
412b61d8 | 10569 | return false; |
79e53945 JB |
10570 | } |
10571 | ||
d2434ab7 | 10572 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10573 | struct intel_load_detect_pipe *old, |
10574 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10575 | { |
d2434ab7 DV |
10576 | struct intel_encoder *intel_encoder = |
10577 | intel_attached_encoder(connector); | |
4ef69c7a | 10578 | struct drm_encoder *encoder = &intel_encoder->base; |
edde3617 | 10579 | struct drm_atomic_state *state = old->restore_state; |
d3a40d1b | 10580 | int ret; |
79e53945 | 10581 | |
d2dff872 | 10582 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10583 | connector->base.id, connector->name, |
8e329a03 | 10584 | encoder->base.id, encoder->name); |
d2dff872 | 10585 | |
edde3617 | 10586 | if (!state) |
0622a53c | 10587 | return; |
79e53945 | 10588 | |
edde3617 ML |
10589 | ret = drm_atomic_commit(state); |
10590 | if (ret) { | |
10591 | DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret); | |
10592 | drm_atomic_state_free(state); | |
10593 | } | |
79e53945 JB |
10594 | } |
10595 | ||
da4a1efa | 10596 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10597 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
10598 | { |
10599 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10600 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
10601 | ||
10602 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10603 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
10604 | else if (HAS_PCH_SPLIT(dev)) |
10605 | return 120000; | |
10606 | else if (!IS_GEN2(dev)) | |
10607 | return 96000; | |
10608 | else | |
10609 | return 48000; | |
10610 | } | |
10611 | ||
79e53945 | 10612 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10613 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10614 | struct intel_crtc_state *pipe_config) |
79e53945 | 10615 | { |
f1f644dc | 10616 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 10617 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 10618 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10619 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 | 10620 | u32 fp; |
9e2c8475 | 10621 | struct dpll clock; |
dccbea3b | 10622 | int port_clock; |
da4a1efa | 10623 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10624 | |
10625 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10626 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10627 | else |
293623f7 | 10628 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10629 | |
10630 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10631 | if (IS_PINEVIEW(dev)) { |
10632 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10633 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10634 | } else { |
10635 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10636 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10637 | } | |
10638 | ||
a6c45cf0 | 10639 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10640 | if (IS_PINEVIEW(dev)) |
10641 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10642 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10643 | else |
10644 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10645 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10646 | ||
10647 | switch (dpll & DPLL_MODE_MASK) { | |
10648 | case DPLLB_MODE_DAC_SERIAL: | |
10649 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10650 | 5 : 10; | |
10651 | break; | |
10652 | case DPLLB_MODE_LVDS: | |
10653 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10654 | 7 : 14; | |
10655 | break; | |
10656 | default: | |
28c97730 | 10657 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10658 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10659 | return; |
79e53945 JB |
10660 | } |
10661 | ||
ac58c3f0 | 10662 | if (IS_PINEVIEW(dev)) |
dccbea3b | 10663 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 10664 | else |
dccbea3b | 10665 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 10666 | } else { |
0fb58223 | 10667 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10668 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10669 | |
10670 | if (is_lvds) { | |
10671 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10672 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10673 | |
10674 | if (lvds & LVDS_CLKB_POWER_UP) | |
10675 | clock.p2 = 7; | |
10676 | else | |
10677 | clock.p2 = 14; | |
79e53945 JB |
10678 | } else { |
10679 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10680 | clock.p1 = 2; | |
10681 | else { | |
10682 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10683 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10684 | } | |
10685 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10686 | clock.p2 = 4; | |
10687 | else | |
10688 | clock.p2 = 2; | |
79e53945 | 10689 | } |
da4a1efa | 10690 | |
dccbea3b | 10691 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
10692 | } |
10693 | ||
18442d08 VS |
10694 | /* |
10695 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10696 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10697 | * encoder's get_config() function. |
10698 | */ | |
dccbea3b | 10699 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
10700 | } |
10701 | ||
6878da05 VS |
10702 | int intel_dotclock_calculate(int link_freq, |
10703 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10704 | { |
f1f644dc JB |
10705 | /* |
10706 | * The calculation for the data clock is: | |
1041a02f | 10707 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10708 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10709 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10710 | * |
10711 | * and the link clock is simpler: | |
1041a02f | 10712 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10713 | */ |
10714 | ||
6878da05 VS |
10715 | if (!m_n->link_n) |
10716 | return 0; | |
f1f644dc | 10717 | |
6878da05 VS |
10718 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10719 | } | |
f1f644dc | 10720 | |
18442d08 | 10721 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10722 | struct intel_crtc_state *pipe_config) |
6878da05 | 10723 | { |
e3b247da | 10724 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
79e53945 | 10725 | |
18442d08 VS |
10726 | /* read out port_clock from the DPLL */ |
10727 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10728 | |
f1f644dc | 10729 | /* |
e3b247da VS |
10730 | * In case there is an active pipe without active ports, |
10731 | * we may need some idea for the dotclock anyway. | |
10732 | * Calculate one based on the FDI configuration. | |
79e53945 | 10733 | */ |
2d112de7 | 10734 | pipe_config->base.adjusted_mode.crtc_clock = |
21a727b3 | 10735 | intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
18442d08 | 10736 | &pipe_config->fdi_m_n); |
79e53945 JB |
10737 | } |
10738 | ||
10739 | /** Returns the currently programmed mode of the given pipe. */ | |
10740 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10741 | struct drm_crtc *crtc) | |
10742 | { | |
548f245b | 10743 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 10744 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10745 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10746 | struct drm_display_mode *mode; |
3f36b937 | 10747 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
10748 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10749 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10750 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10751 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10752 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10753 | |
10754 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10755 | if (!mode) | |
10756 | return NULL; | |
10757 | ||
3f36b937 TU |
10758 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
10759 | if (!pipe_config) { | |
10760 | kfree(mode); | |
10761 | return NULL; | |
10762 | } | |
10763 | ||
f1f644dc JB |
10764 | /* |
10765 | * Construct a pipe_config sufficient for getting the clock info | |
10766 | * back out of crtc_clock_get. | |
10767 | * | |
10768 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10769 | * to use a real value here instead. | |
10770 | */ | |
3f36b937 TU |
10771 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
10772 | pipe_config->pixel_multiplier = 1; | |
10773 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
10774 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10775 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
10776 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
10777 | ||
10778 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
10779 | mode->hdisplay = (htot & 0xffff) + 1; |
10780 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10781 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10782 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10783 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10784 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10785 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10786 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10787 | ||
10788 | drm_mode_set_name(mode); | |
79e53945 | 10789 | |
3f36b937 TU |
10790 | kfree(pipe_config); |
10791 | ||
79e53945 JB |
10792 | return mode; |
10793 | } | |
10794 | ||
7d993739 | 10795 | void intel_mark_busy(struct drm_i915_private *dev_priv) |
f047e395 | 10796 | { |
f62a0076 CW |
10797 | if (dev_priv->mm.busy) |
10798 | return; | |
10799 | ||
43694d69 | 10800 | intel_runtime_pm_get(dev_priv); |
c67a470b | 10801 | i915_update_gfx_val(dev_priv); |
7d993739 | 10802 | if (INTEL_GEN(dev_priv) >= 6) |
43cf3bf0 | 10803 | gen6_rps_busy(dev_priv); |
f62a0076 | 10804 | dev_priv->mm.busy = true; |
f047e395 CW |
10805 | } |
10806 | ||
7d993739 | 10807 | void intel_mark_idle(struct drm_i915_private *dev_priv) |
652c393a | 10808 | { |
f62a0076 CW |
10809 | if (!dev_priv->mm.busy) |
10810 | return; | |
10811 | ||
10812 | dev_priv->mm.busy = false; | |
10813 | ||
7d993739 TU |
10814 | if (INTEL_GEN(dev_priv) >= 6) |
10815 | gen6_rps_idle(dev_priv); | |
bb4cdd53 | 10816 | |
43694d69 | 10817 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
10818 | } |
10819 | ||
79e53945 JB |
10820 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
10821 | { | |
10822 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
10823 | struct drm_device *dev = crtc->dev; |
10824 | struct intel_unpin_work *work; | |
67e77c5a | 10825 | |
5e2d7afc | 10826 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
10827 | work = intel_crtc->unpin_work; |
10828 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 10829 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
10830 | |
10831 | if (work) { | |
10832 | cancel_work_sync(&work->work); | |
10833 | kfree(work); | |
10834 | } | |
79e53945 JB |
10835 | |
10836 | drm_crtc_cleanup(crtc); | |
67e77c5a | 10837 | |
79e53945 JB |
10838 | kfree(intel_crtc); |
10839 | } | |
10840 | ||
6b95a207 KH |
10841 | static void intel_unpin_work_fn(struct work_struct *__work) |
10842 | { | |
10843 | struct intel_unpin_work *work = | |
10844 | container_of(__work, struct intel_unpin_work, work); | |
a9ff8714 VS |
10845 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
10846 | struct drm_device *dev = crtc->base.dev; | |
10847 | struct drm_plane *primary = crtc->base.primary; | |
6b95a207 | 10848 | |
b4a98e57 | 10849 | mutex_lock(&dev->struct_mutex); |
3465c580 | 10850 | intel_unpin_fb_obj(work->old_fb, primary->state->rotation); |
05394f39 | 10851 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 10852 | |
f06cc1b9 | 10853 | if (work->flip_queued_req) |
146d84f0 | 10854 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
10855 | mutex_unlock(&dev->struct_mutex); |
10856 | ||
a9ff8714 | 10857 | intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit); |
1eb52238 | 10858 | intel_fbc_post_update(crtc); |
89ed88ba | 10859 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 10860 | |
a9ff8714 VS |
10861 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
10862 | atomic_dec(&crtc->unpin_work_count); | |
b4a98e57 | 10863 | |
6b95a207 KH |
10864 | kfree(work); |
10865 | } | |
10866 | ||
75f7f3ec VS |
10867 | /* Is 'a' after or equal to 'b'? */ |
10868 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
10869 | { | |
10870 | return !((a - b) & 0x80000000); | |
10871 | } | |
10872 | ||
10873 | static bool page_flip_finished(struct intel_crtc *crtc) | |
10874 | { | |
10875 | struct drm_device *dev = crtc->base.dev; | |
10876 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c19ae989 | 10877 | unsigned reset_counter; |
75f7f3ec | 10878 | |
5251f04e ML |
10879 | /* ensure that the unpin work is consistent wrt ->pending. */ |
10880 | smp_rmb(); | |
10881 | ||
c19ae989 | 10882 | reset_counter = i915_reset_counter(&dev_priv->gpu_error); |
7f1847eb | 10883 | if (crtc->reset_counter != reset_counter) |
bdfa7542 VS |
10884 | return true; |
10885 | ||
75f7f3ec VS |
10886 | /* |
10887 | * The relevant registers doen't exist on pre-ctg. | |
10888 | * As the flip done interrupt doesn't trigger for mmio | |
10889 | * flips on gmch platforms, a flip count check isn't | |
10890 | * really needed there. But since ctg has the registers, | |
10891 | * include it in the check anyway. | |
10892 | */ | |
10893 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
10894 | return true; | |
10895 | ||
e8861675 ML |
10896 | /* |
10897 | * BDW signals flip done immediately if the plane | |
10898 | * is disabled, even if the plane enable is already | |
10899 | * armed to occur at the next vblank :( | |
10900 | */ | |
10901 | ||
75f7f3ec VS |
10902 | /* |
10903 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
10904 | * used the same base address. In that case the mmio flip might | |
10905 | * have completed, but the CS hasn't even executed the flip yet. | |
10906 | * | |
10907 | * A flip count check isn't enough as the CS might have updated | |
10908 | * the base address just after start of vblank, but before we | |
10909 | * managed to process the interrupt. This means we'd complete the | |
10910 | * CS flip too soon. | |
10911 | * | |
10912 | * Combining both checks should get us a good enough result. It may | |
10913 | * still happen that the CS flip has been executed, but has not | |
10914 | * yet actually completed. But in case the base address is the same | |
10915 | * anyway, we don't really care. | |
10916 | */ | |
10917 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
10918 | crtc->unpin_work->gtt_offset && | |
fd8f507c | 10919 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), |
75f7f3ec VS |
10920 | crtc->unpin_work->flip_count); |
10921 | } | |
10922 | ||
5251f04e | 10923 | void intel_finish_page_flip(struct drm_i915_private *dev_priv, int pipe) |
6b95a207 | 10924 | { |
91d14251 | 10925 | struct drm_device *dev = dev_priv->dev; |
5251f04e ML |
10926 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
10927 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10928 | struct intel_unpin_work *work; | |
6b95a207 KH |
10929 | unsigned long flags; |
10930 | ||
5251f04e ML |
10931 | /* Ignore early vblank irqs */ |
10932 | if (!crtc) | |
10933 | return; | |
f326038a DV |
10934 | |
10935 | /* | |
10936 | * This is called both by irq handlers and the reset code (to complete | |
10937 | * lost pageflips) so needs the full irqsave spinlocks. | |
e7d841ca | 10938 | */ |
6b95a207 | 10939 | spin_lock_irqsave(&dev->event_lock, flags); |
5251f04e ML |
10940 | work = intel_crtc->unpin_work; |
10941 | ||
10942 | if (work != NULL && | |
10943 | atomic_read(&work->pending) && | |
10944 | page_flip_finished(intel_crtc)) | |
10945 | page_flip_completed(intel_crtc); | |
10946 | ||
6b95a207 KH |
10947 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10948 | } | |
10949 | ||
6042639c | 10950 | static inline void intel_mark_page_flip_active(struct intel_unpin_work *work) |
e7d841ca CW |
10951 | { |
10952 | /* Ensure that the work item is consistent when activating it ... */ | |
55d80d23 | 10953 | smp_mb__before_atomic(); |
5251f04e | 10954 | atomic_set(&work->pending, 1); |
e7d841ca CW |
10955 | } |
10956 | ||
8c9f3aaf JB |
10957 | static int intel_gen2_queue_flip(struct drm_device *dev, |
10958 | struct drm_crtc *crtc, | |
10959 | struct drm_framebuffer *fb, | |
ed8d1975 | 10960 | struct drm_i915_gem_object *obj, |
6258fbe2 | 10961 | struct drm_i915_gem_request *req, |
ed8d1975 | 10962 | uint32_t flags) |
8c9f3aaf | 10963 | { |
4a570db5 | 10964 | struct intel_engine_cs *engine = req->engine; |
8c9f3aaf | 10965 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
10966 | u32 flip_mask; |
10967 | int ret; | |
10968 | ||
5fb9de1a | 10969 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 10970 | if (ret) |
4fa62c89 | 10971 | return ret; |
8c9f3aaf JB |
10972 | |
10973 | /* Can't queue multiple flips, so wait for the previous | |
10974 | * one to finish before executing the next. | |
10975 | */ | |
10976 | if (intel_crtc->plane) | |
10977 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
10978 | else | |
10979 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
e2f80391 TU |
10980 | intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask); |
10981 | intel_ring_emit(engine, MI_NOOP); | |
10982 | intel_ring_emit(engine, MI_DISPLAY_FLIP | | |
6d90c952 | 10983 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
e2f80391 TU |
10984 | intel_ring_emit(engine, fb->pitches[0]); |
10985 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset); | |
10986 | intel_ring_emit(engine, 0); /* aux display base address, unused */ | |
e7d841ca | 10987 | |
83d4092b | 10988 | return 0; |
8c9f3aaf JB |
10989 | } |
10990 | ||
10991 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
10992 | struct drm_crtc *crtc, | |
10993 | struct drm_framebuffer *fb, | |
ed8d1975 | 10994 | struct drm_i915_gem_object *obj, |
6258fbe2 | 10995 | struct drm_i915_gem_request *req, |
ed8d1975 | 10996 | uint32_t flags) |
8c9f3aaf | 10997 | { |
4a570db5 | 10998 | struct intel_engine_cs *engine = req->engine; |
8c9f3aaf | 10999 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
11000 | u32 flip_mask; |
11001 | int ret; | |
11002 | ||
5fb9de1a | 11003 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 11004 | if (ret) |
4fa62c89 | 11005 | return ret; |
8c9f3aaf JB |
11006 | |
11007 | if (intel_crtc->plane) | |
11008 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11009 | else | |
11010 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
e2f80391 TU |
11011 | intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask); |
11012 | intel_ring_emit(engine, MI_NOOP); | |
11013 | intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | | |
6d90c952 | 11014 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
e2f80391 TU |
11015 | intel_ring_emit(engine, fb->pitches[0]); |
11016 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset); | |
11017 | intel_ring_emit(engine, MI_NOOP); | |
6d90c952 | 11018 | |
83d4092b | 11019 | return 0; |
8c9f3aaf JB |
11020 | } |
11021 | ||
11022 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
11023 | struct drm_crtc *crtc, | |
11024 | struct drm_framebuffer *fb, | |
ed8d1975 | 11025 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11026 | struct drm_i915_gem_request *req, |
ed8d1975 | 11027 | uint32_t flags) |
8c9f3aaf | 11028 | { |
4a570db5 | 11029 | struct intel_engine_cs *engine = req->engine; |
8c9f3aaf JB |
11030 | struct drm_i915_private *dev_priv = dev->dev_private; |
11031 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11032 | uint32_t pf, pipesrc; | |
11033 | int ret; | |
11034 | ||
5fb9de1a | 11035 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11036 | if (ret) |
4fa62c89 | 11037 | return ret; |
8c9f3aaf JB |
11038 | |
11039 | /* i965+ uses the linear or tiled offsets from the | |
11040 | * Display Registers (which do not change across a page-flip) | |
11041 | * so we need only reprogram the base address. | |
11042 | */ | |
e2f80391 | 11043 | intel_ring_emit(engine, MI_DISPLAY_FLIP | |
6d90c952 | 11044 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
e2f80391 TU |
11045 | intel_ring_emit(engine, fb->pitches[0]); |
11046 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset | | |
c2c75131 | 11047 | obj->tiling_mode); |
8c9f3aaf JB |
11048 | |
11049 | /* XXX Enabling the panel-fitter across page-flip is so far | |
11050 | * untested on non-native modes, so ignore it for now. | |
11051 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
11052 | */ | |
11053 | pf = 0; | |
11054 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
e2f80391 | 11055 | intel_ring_emit(engine, pf | pipesrc); |
e7d841ca | 11056 | |
83d4092b | 11057 | return 0; |
8c9f3aaf JB |
11058 | } |
11059 | ||
11060 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
11061 | struct drm_crtc *crtc, | |
11062 | struct drm_framebuffer *fb, | |
ed8d1975 | 11063 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11064 | struct drm_i915_gem_request *req, |
ed8d1975 | 11065 | uint32_t flags) |
8c9f3aaf | 11066 | { |
4a570db5 | 11067 | struct intel_engine_cs *engine = req->engine; |
8c9f3aaf JB |
11068 | struct drm_i915_private *dev_priv = dev->dev_private; |
11069 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11070 | uint32_t pf, pipesrc; | |
11071 | int ret; | |
11072 | ||
5fb9de1a | 11073 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11074 | if (ret) |
4fa62c89 | 11075 | return ret; |
8c9f3aaf | 11076 | |
e2f80391 | 11077 | intel_ring_emit(engine, MI_DISPLAY_FLIP | |
6d90c952 | 11078 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); |
e2f80391 TU |
11079 | intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode); |
11080 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset); | |
8c9f3aaf | 11081 | |
dc257cf1 DV |
11082 | /* Contrary to the suggestions in the documentation, |
11083 | * "Enable Panel Fitter" does not seem to be required when page | |
11084 | * flipping with a non-native mode, and worse causes a normal | |
11085 | * modeset to fail. | |
11086 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
11087 | */ | |
11088 | pf = 0; | |
8c9f3aaf | 11089 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
e2f80391 | 11090 | intel_ring_emit(engine, pf | pipesrc); |
e7d841ca | 11091 | |
83d4092b | 11092 | return 0; |
8c9f3aaf JB |
11093 | } |
11094 | ||
7c9017e5 JB |
11095 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11096 | struct drm_crtc *crtc, | |
11097 | struct drm_framebuffer *fb, | |
ed8d1975 | 11098 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11099 | struct drm_i915_gem_request *req, |
ed8d1975 | 11100 | uint32_t flags) |
7c9017e5 | 11101 | { |
4a570db5 | 11102 | struct intel_engine_cs *engine = req->engine; |
7c9017e5 | 11103 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 11104 | uint32_t plane_bit = 0; |
ffe74d75 CW |
11105 | int len, ret; |
11106 | ||
eba905b2 | 11107 | switch (intel_crtc->plane) { |
cb05d8de DV |
11108 | case PLANE_A: |
11109 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11110 | break; | |
11111 | case PLANE_B: | |
11112 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11113 | break; | |
11114 | case PLANE_C: | |
11115 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11116 | break; | |
11117 | default: | |
11118 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 11119 | return -ENODEV; |
cb05d8de DV |
11120 | } |
11121 | ||
ffe74d75 | 11122 | len = 4; |
e2f80391 | 11123 | if (engine->id == RCS) { |
ffe74d75 | 11124 | len += 6; |
f476828a DL |
11125 | /* |
11126 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11127 | * 48bits addresses, and we need a NOOP for the batch size to | |
11128 | * stay even. | |
11129 | */ | |
11130 | if (IS_GEN8(dev)) | |
11131 | len += 2; | |
11132 | } | |
ffe74d75 | 11133 | |
f66fab8e VS |
11134 | /* |
11135 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11136 | * "The full packet must be contained within the same cache line." | |
11137 | * | |
11138 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11139 | * cacheline, if we ever start emitting more commands before | |
11140 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11141 | * then do the cacheline alignment, and finally emit the | |
11142 | * MI_DISPLAY_FLIP. | |
11143 | */ | |
bba09b12 | 11144 | ret = intel_ring_cacheline_align(req); |
f66fab8e | 11145 | if (ret) |
4fa62c89 | 11146 | return ret; |
f66fab8e | 11147 | |
5fb9de1a | 11148 | ret = intel_ring_begin(req, len); |
7c9017e5 | 11149 | if (ret) |
4fa62c89 | 11150 | return ret; |
7c9017e5 | 11151 | |
ffe74d75 CW |
11152 | /* Unmask the flip-done completion message. Note that the bspec says that |
11153 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11154 | * more than one flip event at any time (or ensure that one flip message | |
11155 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11156 | * Experimentation says that BCS works despite DERRMR masking all | |
11157 | * flip-done completion events and that unmasking all planes at once | |
11158 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11159 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11160 | */ | |
e2f80391 TU |
11161 | if (engine->id == RCS) { |
11162 | intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1)); | |
11163 | intel_ring_emit_reg(engine, DERRMR); | |
11164 | intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
11165 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
11166 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a | 11167 | if (IS_GEN8(dev)) |
e2f80391 | 11168 | intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 | |
f476828a DL |
11169 | MI_SRM_LRM_GLOBAL_GTT); |
11170 | else | |
e2f80391 | 11171 | intel_ring_emit(engine, MI_STORE_REGISTER_MEM | |
f476828a | 11172 | MI_SRM_LRM_GLOBAL_GTT); |
e2f80391 TU |
11173 | intel_ring_emit_reg(engine, DERRMR); |
11174 | intel_ring_emit(engine, engine->scratch.gtt_offset + 256); | |
f476828a | 11175 | if (IS_GEN8(dev)) { |
e2f80391 TU |
11176 | intel_ring_emit(engine, 0); |
11177 | intel_ring_emit(engine, MI_NOOP); | |
f476828a | 11178 | } |
ffe74d75 CW |
11179 | } |
11180 | ||
e2f80391 TU |
11181 | intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit); |
11182 | intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode)); | |
11183 | intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset); | |
11184 | intel_ring_emit(engine, (MI_NOOP)); | |
e7d841ca | 11185 | |
83d4092b | 11186 | return 0; |
7c9017e5 JB |
11187 | } |
11188 | ||
0bc40be8 | 11189 | static bool use_mmio_flip(struct intel_engine_cs *engine, |
84c33a64 SG |
11190 | struct drm_i915_gem_object *obj) |
11191 | { | |
11192 | /* | |
11193 | * This is not being used for older platforms, because | |
11194 | * non-availability of flip done interrupt forces us to use | |
11195 | * CS flips. Older platforms derive flip done using some clever | |
11196 | * tricks involving the flip_pending status bits and vblank irqs. | |
11197 | * So using MMIO flips there would disrupt this mechanism. | |
11198 | */ | |
11199 | ||
0bc40be8 | 11200 | if (engine == NULL) |
8e09bf83 CW |
11201 | return true; |
11202 | ||
c033666a | 11203 | if (INTEL_GEN(engine->i915) < 5) |
84c33a64 SG |
11204 | return false; |
11205 | ||
11206 | if (i915.use_mmio_flip < 0) | |
11207 | return false; | |
11208 | else if (i915.use_mmio_flip > 0) | |
11209 | return true; | |
14bf993e OM |
11210 | else if (i915.enable_execlists) |
11211 | return true; | |
fd8e058a AG |
11212 | else if (obj->base.dma_buf && |
11213 | !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv, | |
11214 | false)) | |
11215 | return true; | |
84c33a64 | 11216 | else |
666796da | 11217 | return engine != i915_gem_request_get_engine(obj->last_write_req); |
84c33a64 SG |
11218 | } |
11219 | ||
6042639c | 11220 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, |
86efe24a | 11221 | unsigned int rotation, |
6042639c | 11222 | struct intel_unpin_work *work) |
ff944564 DL |
11223 | { |
11224 | struct drm_device *dev = intel_crtc->base.dev; | |
11225 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11226 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
ff944564 | 11227 | const enum pipe pipe = intel_crtc->pipe; |
86efe24a | 11228 | u32 ctl, stride, tile_height; |
ff944564 DL |
11229 | |
11230 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
11231 | ctl &= ~PLANE_CTL_TILED_MASK; | |
2ebef630 TU |
11232 | switch (fb->modifier[0]) { |
11233 | case DRM_FORMAT_MOD_NONE: | |
11234 | break; | |
11235 | case I915_FORMAT_MOD_X_TILED: | |
ff944564 | 11236 | ctl |= PLANE_CTL_TILED_X; |
2ebef630 TU |
11237 | break; |
11238 | case I915_FORMAT_MOD_Y_TILED: | |
11239 | ctl |= PLANE_CTL_TILED_Y; | |
11240 | break; | |
11241 | case I915_FORMAT_MOD_Yf_TILED: | |
11242 | ctl |= PLANE_CTL_TILED_YF; | |
11243 | break; | |
11244 | default: | |
11245 | MISSING_CASE(fb->modifier[0]); | |
11246 | } | |
ff944564 DL |
11247 | |
11248 | /* | |
11249 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
11250 | * linear buffers or in number of tiles for tiled buffers. | |
11251 | */ | |
86efe24a TU |
11252 | if (intel_rotation_90_or_270(rotation)) { |
11253 | /* stride = Surface height in tiles */ | |
832be82f | 11254 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0); |
86efe24a TU |
11255 | stride = DIV_ROUND_UP(fb->height, tile_height); |
11256 | } else { | |
11257 | stride = fb->pitches[0] / | |
7b49f948 VS |
11258 | intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
11259 | fb->pixel_format); | |
86efe24a | 11260 | } |
ff944564 DL |
11261 | |
11262 | /* | |
11263 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
11264 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
11265 | */ | |
11266 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
11267 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
11268 | ||
6042639c | 11269 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); |
ff944564 DL |
11270 | POSTING_READ(PLANE_SURF(pipe, 0)); |
11271 | } | |
11272 | ||
6042639c CW |
11273 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, |
11274 | struct intel_unpin_work *work) | |
84c33a64 SG |
11275 | { |
11276 | struct drm_device *dev = intel_crtc->base.dev; | |
11277 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11278 | struct intel_framebuffer *intel_fb = | |
11279 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
11280 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
f0f59a00 | 11281 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); |
84c33a64 | 11282 | u32 dspcntr; |
84c33a64 | 11283 | |
84c33a64 SG |
11284 | dspcntr = I915_READ(reg); |
11285 | ||
c5d97472 DL |
11286 | if (obj->tiling_mode != I915_TILING_NONE) |
11287 | dspcntr |= DISPPLANE_TILED; | |
11288 | else | |
11289 | dspcntr &= ~DISPPLANE_TILED; | |
11290 | ||
84c33a64 SG |
11291 | I915_WRITE(reg, dspcntr); |
11292 | ||
6042639c | 11293 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); |
84c33a64 | 11294 | POSTING_READ(DSPSURF(intel_crtc->plane)); |
ff944564 DL |
11295 | } |
11296 | ||
11297 | /* | |
11298 | * XXX: This is the temporary way to update the plane registers until we get | |
11299 | * around to using the usual plane update functions for MMIO flips | |
11300 | */ | |
6042639c | 11301 | static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip) |
ff944564 | 11302 | { |
6042639c CW |
11303 | struct intel_crtc *crtc = mmio_flip->crtc; |
11304 | struct intel_unpin_work *work; | |
11305 | ||
11306 | spin_lock_irq(&crtc->base.dev->event_lock); | |
11307 | work = crtc->unpin_work; | |
11308 | spin_unlock_irq(&crtc->base.dev->event_lock); | |
11309 | if (work == NULL) | |
11310 | return; | |
ff944564 | 11311 | |
6042639c | 11312 | intel_pipe_update_start(crtc); |
ff944564 | 11313 | |
6042639c | 11314 | if (INTEL_INFO(mmio_flip->i915)->gen >= 9) |
86efe24a | 11315 | skl_do_mmio_flip(crtc, mmio_flip->rotation, work); |
ff944564 DL |
11316 | else |
11317 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
6042639c | 11318 | ilk_do_mmio_flip(crtc, work); |
ff944564 | 11319 | |
6042639c | 11320 | intel_pipe_update_end(crtc); |
55d80d23 ML |
11321 | |
11322 | intel_mark_page_flip_active(work); | |
84c33a64 SG |
11323 | } |
11324 | ||
9362c7c5 | 11325 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 11326 | { |
b2cfe0ab CW |
11327 | struct intel_mmio_flip *mmio_flip = |
11328 | container_of(work, struct intel_mmio_flip, work); | |
fd8e058a AG |
11329 | struct intel_framebuffer *intel_fb = |
11330 | to_intel_framebuffer(mmio_flip->crtc->base.primary->fb); | |
11331 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
84c33a64 | 11332 | |
6042639c | 11333 | if (mmio_flip->req) { |
eed29a5b | 11334 | WARN_ON(__i915_wait_request(mmio_flip->req, |
bcafc4e3 CW |
11335 | false, NULL, |
11336 | &mmio_flip->i915->rps.mmioflips)); | |
73db04cf | 11337 | i915_gem_request_unreference(mmio_flip->req); |
6042639c | 11338 | } |
84c33a64 | 11339 | |
fd8e058a AG |
11340 | /* For framebuffer backed by dmabuf, wait for fence */ |
11341 | if (obj->base.dma_buf) | |
11342 | WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
11343 | false, false, | |
11344 | MAX_SCHEDULE_TIMEOUT) < 0); | |
11345 | ||
6042639c | 11346 | intel_do_mmio_flip(mmio_flip); |
b2cfe0ab | 11347 | kfree(mmio_flip); |
84c33a64 SG |
11348 | } |
11349 | ||
11350 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
11351 | struct drm_crtc *crtc, | |
86efe24a | 11352 | struct drm_i915_gem_object *obj) |
84c33a64 | 11353 | { |
b2cfe0ab CW |
11354 | struct intel_mmio_flip *mmio_flip; |
11355 | ||
11356 | mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); | |
11357 | if (mmio_flip == NULL) | |
11358 | return -ENOMEM; | |
84c33a64 | 11359 | |
bcafc4e3 | 11360 | mmio_flip->i915 = to_i915(dev); |
eed29a5b | 11361 | mmio_flip->req = i915_gem_request_reference(obj->last_write_req); |
b2cfe0ab | 11362 | mmio_flip->crtc = to_intel_crtc(crtc); |
86efe24a | 11363 | mmio_flip->rotation = crtc->primary->state->rotation; |
536f5b5e | 11364 | |
b2cfe0ab CW |
11365 | INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); |
11366 | schedule_work(&mmio_flip->work); | |
84c33a64 | 11367 | |
84c33a64 SG |
11368 | return 0; |
11369 | } | |
11370 | ||
8c9f3aaf JB |
11371 | static int intel_default_queue_flip(struct drm_device *dev, |
11372 | struct drm_crtc *crtc, | |
11373 | struct drm_framebuffer *fb, | |
ed8d1975 | 11374 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11375 | struct drm_i915_gem_request *req, |
ed8d1975 | 11376 | uint32_t flags) |
8c9f3aaf JB |
11377 | { |
11378 | return -ENODEV; | |
11379 | } | |
11380 | ||
d6bbafa1 CW |
11381 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
11382 | struct drm_crtc *crtc) | |
11383 | { | |
11384 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11385 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11386 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
11387 | u32 addr; | |
55d80d23 | 11388 | u32 pending; |
d6bbafa1 | 11389 | |
55d80d23 ML |
11390 | pending = atomic_read(&work->pending); |
11391 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
11392 | smp_rmb(); | |
908565c2 | 11393 | |
5251f04e ML |
11394 | if (!pending) |
11395 | return false; | |
d6bbafa1 CW |
11396 | |
11397 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
11398 | if (work->flip_queued_req && |
11399 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
11400 | return false; |
11401 | ||
1e3feefd | 11402 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
11403 | } |
11404 | ||
1e3feefd | 11405 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
11406 | return false; |
11407 | ||
11408 | /* Potential stall - if we see that the flip has happened, | |
11409 | * assume a missed interrupt. */ | |
11410 | if (INTEL_INFO(dev)->gen >= 4) | |
11411 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
11412 | else | |
11413 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
11414 | ||
11415 | /* There is a potential issue here with a false positive after a flip | |
11416 | * to the same address. We could address this by checking for a | |
11417 | * non-incrementing frame counter. | |
11418 | */ | |
11419 | return addr == work->gtt_offset; | |
11420 | } | |
11421 | ||
91d14251 | 11422 | void intel_check_page_flip(struct drm_i915_private *dev_priv, int pipe) |
d6bbafa1 | 11423 | { |
91d14251 | 11424 | struct drm_device *dev = dev_priv->dev; |
d6bbafa1 CW |
11425 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
11426 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6ad790c0 | 11427 | struct intel_unpin_work *work; |
f326038a | 11428 | |
6c51d46f | 11429 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
11430 | |
11431 | if (crtc == NULL) | |
11432 | return; | |
11433 | ||
f326038a | 11434 | spin_lock(&dev->event_lock); |
6ad790c0 CW |
11435 | work = intel_crtc->unpin_work; |
11436 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
d6bbafa1 | 11437 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
6ad790c0 | 11438 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
d6bbafa1 | 11439 | page_flip_completed(intel_crtc); |
6ad790c0 | 11440 | work = NULL; |
d6bbafa1 | 11441 | } |
6ad790c0 CW |
11442 | if (work != NULL && |
11443 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
91d14251 | 11444 | intel_queue_rps_boost_for_request(work->flip_queued_req); |
f326038a | 11445 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
11446 | } |
11447 | ||
6b95a207 KH |
11448 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
11449 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
11450 | struct drm_pending_vblank_event *event, |
11451 | uint32_t page_flip_flags) | |
6b95a207 KH |
11452 | { |
11453 | struct drm_device *dev = crtc->dev; | |
11454 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 11455 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 11456 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 11457 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 11458 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 11459 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 11460 | struct intel_unpin_work *work; |
e2f80391 | 11461 | struct intel_engine_cs *engine; |
cf5d8a46 | 11462 | bool mmio_flip; |
91af127f | 11463 | struct drm_i915_gem_request *request = NULL; |
52e68630 | 11464 | int ret; |
6b95a207 | 11465 | |
2ff8fde1 MR |
11466 | /* |
11467 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
11468 | * check to be safe. In the future we may enable pageflipping from | |
11469 | * a disabled primary plane. | |
11470 | */ | |
11471 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
11472 | return -EBUSY; | |
11473 | ||
e6a595d2 | 11474 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 11475 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
11476 | return -EINVAL; |
11477 | ||
11478 | /* | |
11479 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
11480 | * Note that pitch changes could also affect these register. | |
11481 | */ | |
11482 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
11483 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
11484 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
11485 | return -EINVAL; |
11486 | ||
f900db47 CW |
11487 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
11488 | goto out_hang; | |
11489 | ||
b14c5679 | 11490 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
11491 | if (work == NULL) |
11492 | return -ENOMEM; | |
11493 | ||
6b95a207 | 11494 | work->event = event; |
b4a98e57 | 11495 | work->crtc = crtc; |
ab8d6675 | 11496 | work->old_fb = old_fb; |
6b95a207 KH |
11497 | INIT_WORK(&work->work, intel_unpin_work_fn); |
11498 | ||
87b6b101 | 11499 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
11500 | if (ret) |
11501 | goto free_work; | |
11502 | ||
6b95a207 | 11503 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 11504 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 11505 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
11506 | /* Before declaring the flip queue wedged, check if |
11507 | * the hardware completed the operation behind our backs. | |
11508 | */ | |
11509 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
11510 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
11511 | page_flip_completed(intel_crtc); | |
11512 | } else { | |
11513 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 11514 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 11515 | |
d6bbafa1 CW |
11516 | drm_crtc_vblank_put(crtc); |
11517 | kfree(work); | |
11518 | return -EBUSY; | |
11519 | } | |
6b95a207 KH |
11520 | } |
11521 | intel_crtc->unpin_work = work; | |
5e2d7afc | 11522 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 11523 | |
b4a98e57 CW |
11524 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
11525 | flush_workqueue(dev_priv->wq); | |
11526 | ||
75dfca80 | 11527 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 11528 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 11529 | drm_gem_object_reference(&obj->base); |
6b95a207 | 11530 | |
f4510a27 | 11531 | crtc->primary->fb = fb; |
afd65eb4 | 11532 | update_state_fb(crtc->primary); |
e8216e50 | 11533 | intel_fbc_pre_update(intel_crtc); |
1ed1f968 | 11534 | |
e1f99ce6 | 11535 | work->pending_flip_obj = obj; |
e1f99ce6 | 11536 | |
89ed88ba CW |
11537 | ret = i915_mutex_lock_interruptible(dev); |
11538 | if (ret) | |
11539 | goto cleanup; | |
11540 | ||
c19ae989 | 11541 | intel_crtc->reset_counter = i915_reset_counter(&dev_priv->gpu_error); |
7f1847eb CW |
11542 | if (__i915_reset_in_progress_or_wedged(intel_crtc->reset_counter)) { |
11543 | ret = -EIO; | |
11544 | goto cleanup; | |
11545 | } | |
11546 | ||
11547 | atomic_inc(&intel_crtc->unpin_work_count); | |
e1f99ce6 | 11548 | |
75f7f3ec | 11549 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
fd8f507c | 11550 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
75f7f3ec | 11551 | |
666a4537 | 11552 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
4a570db5 | 11553 | engine = &dev_priv->engine[BCS]; |
ab8d6675 | 11554 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 | 11555 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
e2f80391 | 11556 | engine = NULL; |
48bf5b2d | 11557 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
4a570db5 | 11558 | engine = &dev_priv->engine[BCS]; |
4fa62c89 | 11559 | } else if (INTEL_INFO(dev)->gen >= 7) { |
666796da | 11560 | engine = i915_gem_request_get_engine(obj->last_write_req); |
e2f80391 | 11561 | if (engine == NULL || engine->id != RCS) |
4a570db5 | 11562 | engine = &dev_priv->engine[BCS]; |
4fa62c89 | 11563 | } else { |
4a570db5 | 11564 | engine = &dev_priv->engine[RCS]; |
4fa62c89 VS |
11565 | } |
11566 | ||
e2f80391 | 11567 | mmio_flip = use_mmio_flip(engine, obj); |
cf5d8a46 CW |
11568 | |
11569 | /* When using CS flips, we want to emit semaphores between rings. | |
11570 | * However, when using mmio flips we will create a task to do the | |
11571 | * synchronisation, so all we want here is to pin the framebuffer | |
11572 | * into the display plane and skip any waits. | |
11573 | */ | |
7580d774 | 11574 | if (!mmio_flip) { |
e2f80391 | 11575 | ret = i915_gem_object_sync(obj, engine, &request); |
55d80d23 ML |
11576 | if (!ret && !request) { |
11577 | request = i915_gem_request_alloc(engine, NULL); | |
11578 | ret = PTR_ERR_OR_ZERO(request); | |
11579 | } | |
11580 | ||
7580d774 ML |
11581 | if (ret) |
11582 | goto cleanup_pending; | |
11583 | } | |
11584 | ||
3465c580 | 11585 | ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation); |
8c9f3aaf JB |
11586 | if (ret) |
11587 | goto cleanup_pending; | |
6b95a207 | 11588 | |
dedf278c TU |
11589 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), |
11590 | obj, 0); | |
11591 | work->gtt_offset += intel_crtc->dspaddr_offset; | |
4fa62c89 | 11592 | |
cf5d8a46 | 11593 | if (mmio_flip) { |
55d80d23 | 11594 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 11595 | |
f06cc1b9 JH |
11596 | i915_gem_request_assign(&work->flip_queued_req, |
11597 | obj->last_write_req); | |
6258fbe2 | 11598 | |
55d80d23 ML |
11599 | ret = intel_queue_mmio_flip(dev, crtc, obj); |
11600 | if (ret) | |
11601 | goto cleanup_unpin; | |
11602 | } else { | |
6258fbe2 | 11603 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, |
d6bbafa1 CW |
11604 | page_flip_flags); |
11605 | if (ret) | |
11606 | goto cleanup_unpin; | |
11607 | ||
6258fbe2 | 11608 | i915_gem_request_assign(&work->flip_queued_req, request); |
d6bbafa1 | 11609 | |
55d80d23 ML |
11610 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
11611 | intel_mark_page_flip_active(work); | |
91af127f | 11612 | |
55d80d23 ML |
11613 | i915_add_request_no_flush(request); |
11614 | } | |
4fa62c89 | 11615 | |
55d80d23 | 11616 | i915_gem_track_fb(intel_fb_obj(old_fb), obj, |
a9ff8714 | 11617 | to_intel_plane(primary)->frontbuffer_bit); |
c80ac854 | 11618 | mutex_unlock(&dev->struct_mutex); |
a071fa00 | 11619 | |
a9ff8714 VS |
11620 | intel_frontbuffer_flip_prepare(dev, |
11621 | to_intel_plane(primary)->frontbuffer_bit); | |
6b95a207 | 11622 | |
e5510fac JB |
11623 | trace_i915_flip_request(intel_crtc->plane, obj); |
11624 | ||
6b95a207 | 11625 | return 0; |
96b099fd | 11626 | |
4fa62c89 | 11627 | cleanup_unpin: |
3465c580 | 11628 | intel_unpin_fb_obj(fb, crtc->primary->state->rotation); |
8c9f3aaf | 11629 | cleanup_pending: |
0aa498d5 | 11630 | if (!IS_ERR_OR_NULL(request)) |
aa9b7810 | 11631 | i915_add_request_no_flush(request); |
b4a98e57 | 11632 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
11633 | mutex_unlock(&dev->struct_mutex); |
11634 | cleanup: | |
f4510a27 | 11635 | crtc->primary->fb = old_fb; |
afd65eb4 | 11636 | update_state_fb(crtc->primary); |
89ed88ba CW |
11637 | |
11638 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 11639 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 11640 | |
5e2d7afc | 11641 | spin_lock_irq(&dev->event_lock); |
96b099fd | 11642 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 11643 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 11644 | |
87b6b101 | 11645 | drm_crtc_vblank_put(crtc); |
7317c75e | 11646 | free_work: |
96b099fd CW |
11647 | kfree(work); |
11648 | ||
f900db47 | 11649 | if (ret == -EIO) { |
02e0efb5 ML |
11650 | struct drm_atomic_state *state; |
11651 | struct drm_plane_state *plane_state; | |
11652 | ||
f900db47 | 11653 | out_hang: |
02e0efb5 ML |
11654 | state = drm_atomic_state_alloc(dev); |
11655 | if (!state) | |
11656 | return -ENOMEM; | |
11657 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
11658 | ||
11659 | retry: | |
11660 | plane_state = drm_atomic_get_plane_state(state, primary); | |
11661 | ret = PTR_ERR_OR_ZERO(plane_state); | |
11662 | if (!ret) { | |
11663 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11664 | ||
11665 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
11666 | if (!ret) | |
11667 | ret = drm_atomic_commit(state); | |
11668 | } | |
11669 | ||
11670 | if (ret == -EDEADLK) { | |
11671 | drm_modeset_backoff(state->acquire_ctx); | |
11672 | drm_atomic_state_clear(state); | |
11673 | goto retry; | |
11674 | } | |
11675 | ||
11676 | if (ret) | |
11677 | drm_atomic_state_free(state); | |
11678 | ||
f0d3dad3 | 11679 | if (ret == 0 && event) { |
5e2d7afc | 11680 | spin_lock_irq(&dev->event_lock); |
560ce1dc | 11681 | drm_crtc_send_vblank_event(crtc, event); |
5e2d7afc | 11682 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 11683 | } |
f900db47 | 11684 | } |
96b099fd | 11685 | return ret; |
6b95a207 KH |
11686 | } |
11687 | ||
da20eabd ML |
11688 | |
11689 | /** | |
11690 | * intel_wm_need_update - Check whether watermarks need updating | |
11691 | * @plane: drm plane | |
11692 | * @state: new plane state | |
11693 | * | |
11694 | * Check current plane state versus the new one to determine whether | |
11695 | * watermarks need to be recalculated. | |
11696 | * | |
11697 | * Returns true or false. | |
11698 | */ | |
11699 | static bool intel_wm_need_update(struct drm_plane *plane, | |
11700 | struct drm_plane_state *state) | |
11701 | { | |
d21fbe87 MR |
11702 | struct intel_plane_state *new = to_intel_plane_state(state); |
11703 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
11704 | ||
11705 | /* Update watermarks on tiling or size changes. */ | |
92826fcd ML |
11706 | if (new->visible != cur->visible) |
11707 | return true; | |
11708 | ||
11709 | if (!cur->base.fb || !new->base.fb) | |
11710 | return false; | |
11711 | ||
11712 | if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] || | |
11713 | cur->base.rotation != new->base.rotation || | |
d21fbe87 MR |
11714 | drm_rect_width(&new->src) != drm_rect_width(&cur->src) || |
11715 | drm_rect_height(&new->src) != drm_rect_height(&cur->src) || | |
11716 | drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) || | |
11717 | drm_rect_height(&new->dst) != drm_rect_height(&cur->dst)) | |
2791a16c | 11718 | return true; |
7809e5ae | 11719 | |
2791a16c | 11720 | return false; |
7809e5ae MR |
11721 | } |
11722 | ||
d21fbe87 MR |
11723 | static bool needs_scaling(struct intel_plane_state *state) |
11724 | { | |
11725 | int src_w = drm_rect_width(&state->src) >> 16; | |
11726 | int src_h = drm_rect_height(&state->src) >> 16; | |
11727 | int dst_w = drm_rect_width(&state->dst); | |
11728 | int dst_h = drm_rect_height(&state->dst); | |
11729 | ||
11730 | return (src_w != dst_w || src_h != dst_h); | |
11731 | } | |
11732 | ||
da20eabd ML |
11733 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
11734 | struct drm_plane_state *plane_state) | |
11735 | { | |
ab1d3a0e | 11736 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
11737 | struct drm_crtc *crtc = crtc_state->crtc; |
11738 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11739 | struct drm_plane *plane = plane_state->plane; | |
11740 | struct drm_device *dev = crtc->dev; | |
ed4a6a7c | 11741 | struct drm_i915_private *dev_priv = to_i915(dev); |
da20eabd ML |
11742 | struct intel_plane_state *old_plane_state = |
11743 | to_intel_plane_state(plane->state); | |
11744 | int idx = intel_crtc->base.base.id, ret; | |
da20eabd ML |
11745 | bool mode_changed = needs_modeset(crtc_state); |
11746 | bool was_crtc_enabled = crtc->state->active; | |
11747 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
11748 | bool turn_off, turn_on, visible, was_visible; |
11749 | struct drm_framebuffer *fb = plane_state->fb; | |
11750 | ||
11751 | if (crtc_state && INTEL_INFO(dev)->gen >= 9 && | |
11752 | plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11753 | ret = skl_update_scaler_plane( | |
11754 | to_intel_crtc_state(crtc_state), | |
11755 | to_intel_plane_state(plane_state)); | |
11756 | if (ret) | |
11757 | return ret; | |
11758 | } | |
11759 | ||
da20eabd ML |
11760 | was_visible = old_plane_state->visible; |
11761 | visible = to_intel_plane_state(plane_state)->visible; | |
11762 | ||
11763 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
11764 | was_visible = false; | |
11765 | ||
35c08f43 ML |
11766 | /* |
11767 | * Visibility is calculated as if the crtc was on, but | |
11768 | * after scaler setup everything depends on it being off | |
11769 | * when the crtc isn't active. | |
f818ffea VS |
11770 | * |
11771 | * FIXME this is wrong for watermarks. Watermarks should also | |
11772 | * be computed as if the pipe would be active. Perhaps move | |
11773 | * per-plane wm computation to the .check_plane() hook, and | |
11774 | * only combine the results from all planes in the current place? | |
35c08f43 ML |
11775 | */ |
11776 | if (!is_crtc_enabled) | |
11777 | to_intel_plane_state(plane_state)->visible = visible = false; | |
da20eabd ML |
11778 | |
11779 | if (!was_visible && !visible) | |
11780 | return 0; | |
11781 | ||
e8861675 ML |
11782 | if (fb != old_plane_state->base.fb) |
11783 | pipe_config->fb_changed = true; | |
11784 | ||
da20eabd ML |
11785 | turn_off = was_visible && (!visible || mode_changed); |
11786 | turn_on = visible && (!was_visible || mode_changed); | |
11787 | ||
11788 | DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx, | |
11789 | plane->base.id, fb ? fb->base.id : -1); | |
11790 | ||
11791 | DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n", | |
11792 | plane->base.id, was_visible, visible, | |
11793 | turn_off, turn_on, mode_changed); | |
11794 | ||
caed361d VS |
11795 | if (turn_on) { |
11796 | pipe_config->update_wm_pre = true; | |
11797 | ||
11798 | /* must disable cxsr around plane enable/disable */ | |
11799 | if (plane->type != DRM_PLANE_TYPE_CURSOR) | |
11800 | pipe_config->disable_cxsr = true; | |
11801 | } else if (turn_off) { | |
11802 | pipe_config->update_wm_post = true; | |
92826fcd | 11803 | |
852eb00d | 11804 | /* must disable cxsr around plane enable/disable */ |
e8861675 | 11805 | if (plane->type != DRM_PLANE_TYPE_CURSOR) |
ab1d3a0e | 11806 | pipe_config->disable_cxsr = true; |
852eb00d | 11807 | } else if (intel_wm_need_update(plane, plane_state)) { |
caed361d VS |
11808 | /* FIXME bollocks */ |
11809 | pipe_config->update_wm_pre = true; | |
11810 | pipe_config->update_wm_post = true; | |
852eb00d | 11811 | } |
da20eabd | 11812 | |
ed4a6a7c | 11813 | /* Pre-gen9 platforms need two-step watermark updates */ |
caed361d VS |
11814 | if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) && |
11815 | INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks) | |
ed4a6a7c MR |
11816 | to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true; |
11817 | ||
8be6ca85 | 11818 | if (visible || was_visible) |
cd202f69 | 11819 | pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit; |
a9ff8714 | 11820 | |
31ae71fc ML |
11821 | /* |
11822 | * WaCxSRDisabledForSpriteScaling:ivb | |
11823 | * | |
11824 | * cstate->update_wm was already set above, so this flag will | |
11825 | * take effect when we commit and program watermarks. | |
11826 | */ | |
11827 | if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) && | |
11828 | needs_scaling(to_intel_plane_state(plane_state)) && | |
11829 | !needs_scaling(old_plane_state)) | |
11830 | pipe_config->disable_lp_wm = true; | |
d21fbe87 | 11831 | |
da20eabd ML |
11832 | return 0; |
11833 | } | |
11834 | ||
6d3a1ce7 ML |
11835 | static bool encoders_cloneable(const struct intel_encoder *a, |
11836 | const struct intel_encoder *b) | |
11837 | { | |
11838 | /* masks could be asymmetric, so check both ways */ | |
11839 | return a == b || (a->cloneable & (1 << b->type) && | |
11840 | b->cloneable & (1 << a->type)); | |
11841 | } | |
11842 | ||
11843 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
11844 | struct intel_crtc *crtc, | |
11845 | struct intel_encoder *encoder) | |
11846 | { | |
11847 | struct intel_encoder *source_encoder; | |
11848 | struct drm_connector *connector; | |
11849 | struct drm_connector_state *connector_state; | |
11850 | int i; | |
11851 | ||
11852 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11853 | if (connector_state->crtc != &crtc->base) | |
11854 | continue; | |
11855 | ||
11856 | source_encoder = | |
11857 | to_intel_encoder(connector_state->best_encoder); | |
11858 | if (!encoders_cloneable(encoder, source_encoder)) | |
11859 | return false; | |
11860 | } | |
11861 | ||
11862 | return true; | |
11863 | } | |
11864 | ||
11865 | static bool check_encoder_cloning(struct drm_atomic_state *state, | |
11866 | struct intel_crtc *crtc) | |
11867 | { | |
11868 | struct intel_encoder *encoder; | |
11869 | struct drm_connector *connector; | |
11870 | struct drm_connector_state *connector_state; | |
11871 | int i; | |
11872 | ||
11873 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11874 | if (connector_state->crtc != &crtc->base) | |
11875 | continue; | |
11876 | ||
11877 | encoder = to_intel_encoder(connector_state->best_encoder); | |
11878 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
11879 | return false; | |
11880 | } | |
11881 | ||
11882 | return true; | |
11883 | } | |
11884 | ||
11885 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, | |
11886 | struct drm_crtc_state *crtc_state) | |
11887 | { | |
cf5a15be | 11888 | struct drm_device *dev = crtc->dev; |
ad421372 | 11889 | struct drm_i915_private *dev_priv = dev->dev_private; |
6d3a1ce7 | 11890 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
11891 | struct intel_crtc_state *pipe_config = |
11892 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 11893 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 11894 | int ret; |
6d3a1ce7 ML |
11895 | bool mode_changed = needs_modeset(crtc_state); |
11896 | ||
11897 | if (mode_changed && !check_encoder_cloning(state, intel_crtc)) { | |
11898 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
11899 | return -EINVAL; | |
11900 | } | |
11901 | ||
852eb00d | 11902 | if (mode_changed && !crtc_state->active) |
caed361d | 11903 | pipe_config->update_wm_post = true; |
eddfcbcd | 11904 | |
ad421372 ML |
11905 | if (mode_changed && crtc_state->enable && |
11906 | dev_priv->display.crtc_compute_clock && | |
8106ddbd | 11907 | !WARN_ON(pipe_config->shared_dpll)) { |
ad421372 ML |
11908 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, |
11909 | pipe_config); | |
11910 | if (ret) | |
11911 | return ret; | |
11912 | } | |
11913 | ||
82cf435b LL |
11914 | if (crtc_state->color_mgmt_changed) { |
11915 | ret = intel_color_check(crtc, crtc_state); | |
11916 | if (ret) | |
11917 | return ret; | |
11918 | } | |
11919 | ||
e435d6e5 | 11920 | ret = 0; |
86c8bbbe | 11921 | if (dev_priv->display.compute_pipe_wm) { |
e3bddded | 11922 | ret = dev_priv->display.compute_pipe_wm(pipe_config); |
ed4a6a7c MR |
11923 | if (ret) { |
11924 | DRM_DEBUG_KMS("Target pipe watermarks are invalid\n"); | |
11925 | return ret; | |
11926 | } | |
11927 | } | |
11928 | ||
11929 | if (dev_priv->display.compute_intermediate_wm && | |
11930 | !to_intel_atomic_state(state)->skip_intermediate_wm) { | |
11931 | if (WARN_ON(!dev_priv->display.compute_pipe_wm)) | |
11932 | return 0; | |
11933 | ||
11934 | /* | |
11935 | * Calculate 'intermediate' watermarks that satisfy both the | |
11936 | * old state and the new state. We can program these | |
11937 | * immediately. | |
11938 | */ | |
11939 | ret = dev_priv->display.compute_intermediate_wm(crtc->dev, | |
11940 | intel_crtc, | |
11941 | pipe_config); | |
11942 | if (ret) { | |
11943 | DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n"); | |
86c8bbbe | 11944 | return ret; |
ed4a6a7c | 11945 | } |
e3d5457c VS |
11946 | } else if (dev_priv->display.compute_intermediate_wm) { |
11947 | if (HAS_PCH_SPLIT(dev_priv) && INTEL_GEN(dev_priv) < 9) | |
11948 | pipe_config->wm.ilk.intermediate = pipe_config->wm.ilk.optimal; | |
86c8bbbe MR |
11949 | } |
11950 | ||
e435d6e5 ML |
11951 | if (INTEL_INFO(dev)->gen >= 9) { |
11952 | if (mode_changed) | |
11953 | ret = skl_update_scaler_crtc(pipe_config); | |
11954 | ||
11955 | if (!ret) | |
11956 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
11957 | pipe_config); | |
11958 | } | |
11959 | ||
11960 | return ret; | |
6d3a1ce7 ML |
11961 | } |
11962 | ||
65b38e0d | 11963 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 | 11964 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
ea2c67bb MR |
11965 | .atomic_begin = intel_begin_crtc_commit, |
11966 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 11967 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
11968 | }; |
11969 | ||
d29b2f9d ACO |
11970 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
11971 | { | |
11972 | struct intel_connector *connector; | |
11973 | ||
11974 | for_each_intel_connector(dev, connector) { | |
8863dc7f DV |
11975 | if (connector->base.state->crtc) |
11976 | drm_connector_unreference(&connector->base); | |
11977 | ||
d29b2f9d ACO |
11978 | if (connector->base.encoder) { |
11979 | connector->base.state->best_encoder = | |
11980 | connector->base.encoder; | |
11981 | connector->base.state->crtc = | |
11982 | connector->base.encoder->crtc; | |
8863dc7f DV |
11983 | |
11984 | drm_connector_reference(&connector->base); | |
d29b2f9d ACO |
11985 | } else { |
11986 | connector->base.state->best_encoder = NULL; | |
11987 | connector->base.state->crtc = NULL; | |
11988 | } | |
11989 | } | |
11990 | } | |
11991 | ||
050f7aeb | 11992 | static void |
eba905b2 | 11993 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 11994 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
11995 | { |
11996 | int bpp = pipe_config->pipe_bpp; | |
11997 | ||
11998 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
11999 | connector->base.base.id, | |
c23cc417 | 12000 | connector->base.name); |
050f7aeb DV |
12001 | |
12002 | /* Don't use an invalid EDID bpc value */ | |
12003 | if (connector->base.display_info.bpc && | |
12004 | connector->base.display_info.bpc * 3 < bpp) { | |
12005 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
12006 | bpp, connector->base.display_info.bpc*3); | |
12007 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
12008 | } | |
12009 | ||
013dd9e0 JN |
12010 | /* Clamp bpp to default limit on screens without EDID 1.4 */ |
12011 | if (connector->base.display_info.bpc == 0) { | |
12012 | int type = connector->base.connector_type; | |
12013 | int clamp_bpp = 24; | |
12014 | ||
12015 | /* Fall back to 18 bpp when DP sink capability is unknown. */ | |
12016 | if (type == DRM_MODE_CONNECTOR_DisplayPort || | |
12017 | type == DRM_MODE_CONNECTOR_eDP) | |
12018 | clamp_bpp = 18; | |
12019 | ||
12020 | if (bpp > clamp_bpp) { | |
12021 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n", | |
12022 | bpp, clamp_bpp); | |
12023 | pipe_config->pipe_bpp = clamp_bpp; | |
12024 | } | |
050f7aeb DV |
12025 | } |
12026 | } | |
12027 | ||
4e53c2e0 | 12028 | static int |
050f7aeb | 12029 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 12030 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 12031 | { |
050f7aeb | 12032 | struct drm_device *dev = crtc->base.dev; |
1486017f | 12033 | struct drm_atomic_state *state; |
da3ced29 ACO |
12034 | struct drm_connector *connector; |
12035 | struct drm_connector_state *connector_state; | |
1486017f | 12036 | int bpp, i; |
4e53c2e0 | 12037 | |
666a4537 | 12038 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) |
4e53c2e0 | 12039 | bpp = 10*3; |
d328c9d7 DV |
12040 | else if (INTEL_INFO(dev)->gen >= 5) |
12041 | bpp = 12*3; | |
12042 | else | |
12043 | bpp = 8*3; | |
12044 | ||
4e53c2e0 | 12045 | |
4e53c2e0 DV |
12046 | pipe_config->pipe_bpp = bpp; |
12047 | ||
1486017f ACO |
12048 | state = pipe_config->base.state; |
12049 | ||
4e53c2e0 | 12050 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
12051 | for_each_connector_in_state(state, connector, connector_state, i) { |
12052 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
12053 | continue; |
12054 | ||
da3ced29 ACO |
12055 | connected_sink_compute_bpp(to_intel_connector(connector), |
12056 | pipe_config); | |
4e53c2e0 DV |
12057 | } |
12058 | ||
12059 | return bpp; | |
12060 | } | |
12061 | ||
644db711 DV |
12062 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
12063 | { | |
12064 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
12065 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 12066 | mode->crtc_clock, |
644db711 DV |
12067 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
12068 | mode->crtc_hsync_end, mode->crtc_htotal, | |
12069 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
12070 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
12071 | } | |
12072 | ||
c0b03411 | 12073 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 12074 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
12075 | const char *context) |
12076 | { | |
6a60cd87 CK |
12077 | struct drm_device *dev = crtc->base.dev; |
12078 | struct drm_plane *plane; | |
12079 | struct intel_plane *intel_plane; | |
12080 | struct intel_plane_state *state; | |
12081 | struct drm_framebuffer *fb; | |
12082 | ||
12083 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
12084 | context, pipe_config, pipe_name(crtc->pipe)); | |
c0b03411 | 12085 | |
da205630 | 12086 | DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder)); |
c0b03411 DV |
12087 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", |
12088 | pipe_config->pipe_bpp, pipe_config->dither); | |
12089 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
12090 | pipe_config->has_pch_encoder, | |
12091 | pipe_config->fdi_lanes, | |
12092 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
12093 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
12094 | pipe_config->fdi_m_n.tu); | |
90a6b7b0 | 12095 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
eb14cb74 | 12096 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12097 | pipe_config->lane_count, |
eb14cb74 VS |
12098 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
12099 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
12100 | pipe_config->dp_m_n.tu); | |
b95af8be | 12101 | |
90a6b7b0 | 12102 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
b95af8be | 12103 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12104 | pipe_config->lane_count, |
b95af8be VK |
12105 | pipe_config->dp_m2_n2.gmch_m, |
12106 | pipe_config->dp_m2_n2.gmch_n, | |
12107 | pipe_config->dp_m2_n2.link_m, | |
12108 | pipe_config->dp_m2_n2.link_n, | |
12109 | pipe_config->dp_m2_n2.tu); | |
12110 | ||
55072d19 DV |
12111 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
12112 | pipe_config->has_audio, | |
12113 | pipe_config->has_infoframe); | |
12114 | ||
c0b03411 | 12115 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 12116 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 12117 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
12118 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
12119 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 12120 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
12121 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
12122 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
12123 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
12124 | crtc->num_scalers, | |
12125 | pipe_config->scaler_state.scaler_users, | |
12126 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
12127 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
12128 | pipe_config->gmch_pfit.control, | |
12129 | pipe_config->gmch_pfit.pgm_ratios, | |
12130 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 12131 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 12132 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
12133 | pipe_config->pch_pfit.size, |
12134 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 12135 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 12136 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 12137 | |
415ff0f6 | 12138 | if (IS_BROXTON(dev)) { |
05712c15 | 12139 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 12140 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 12141 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 TU |
12142 | pipe_config->ddi_pll_sel, |
12143 | pipe_config->dpll_hw_state.ebb0, | |
05712c15 | 12144 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
12145 | pipe_config->dpll_hw_state.pll0, |
12146 | pipe_config->dpll_hw_state.pll1, | |
12147 | pipe_config->dpll_hw_state.pll2, | |
12148 | pipe_config->dpll_hw_state.pll3, | |
12149 | pipe_config->dpll_hw_state.pll6, | |
12150 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 12151 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 12152 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 | 12153 | pipe_config->dpll_hw_state.pcsdw12); |
ef11bdb3 | 12154 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
415ff0f6 TU |
12155 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " |
12156 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
12157 | pipe_config->ddi_pll_sel, | |
12158 | pipe_config->dpll_hw_state.ctrl1, | |
12159 | pipe_config->dpll_hw_state.cfgcr1, | |
12160 | pipe_config->dpll_hw_state.cfgcr2); | |
12161 | } else if (HAS_DDI(dev)) { | |
1260f07e | 12162 | DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
415ff0f6 | 12163 | pipe_config->ddi_pll_sel, |
00490c22 ML |
12164 | pipe_config->dpll_hw_state.wrpll, |
12165 | pipe_config->dpll_hw_state.spll); | |
415ff0f6 TU |
12166 | } else { |
12167 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12168 | "fp0: 0x%x, fp1: 0x%x\n", | |
12169 | pipe_config->dpll_hw_state.dpll, | |
12170 | pipe_config->dpll_hw_state.dpll_md, | |
12171 | pipe_config->dpll_hw_state.fp0, | |
12172 | pipe_config->dpll_hw_state.fp1); | |
12173 | } | |
12174 | ||
6a60cd87 CK |
12175 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12176 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
12177 | intel_plane = to_intel_plane(plane); | |
12178 | if (intel_plane->pipe != crtc->pipe) | |
12179 | continue; | |
12180 | ||
12181 | state = to_intel_plane_state(plane->state); | |
12182 | fb = state->base.fb; | |
12183 | if (!fb) { | |
12184 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
12185 | "disabled, scaler_id = %d\n", | |
12186 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12187 | plane->base.id, intel_plane->pipe, | |
12188 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
12189 | drm_plane_index(plane), state->scaler_id); | |
12190 | continue; | |
12191 | } | |
12192 | ||
12193 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
12194 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12195 | plane->base.id, intel_plane->pipe, | |
12196 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
12197 | drm_plane_index(plane)); | |
12198 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
12199 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
12200 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
12201 | state->scaler_id, | |
12202 | state->src.x1 >> 16, state->src.y1 >> 16, | |
12203 | drm_rect_width(&state->src) >> 16, | |
12204 | drm_rect_height(&state->src) >> 16, | |
12205 | state->dst.x1, state->dst.y1, | |
12206 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
12207 | } | |
c0b03411 DV |
12208 | } |
12209 | ||
5448a00d | 12210 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12211 | { |
5448a00d | 12212 | struct drm_device *dev = state->dev; |
da3ced29 | 12213 | struct drm_connector *connector; |
00f0b378 VS |
12214 | unsigned int used_ports = 0; |
12215 | ||
12216 | /* | |
12217 | * Walk the connector list instead of the encoder | |
12218 | * list to detect the problem on ddi platforms | |
12219 | * where there's just one encoder per digital port. | |
12220 | */ | |
0bff4858 VS |
12221 | drm_for_each_connector(connector, dev) { |
12222 | struct drm_connector_state *connector_state; | |
12223 | struct intel_encoder *encoder; | |
12224 | ||
12225 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
12226 | if (!connector_state) | |
12227 | connector_state = connector->state; | |
12228 | ||
5448a00d | 12229 | if (!connector_state->best_encoder) |
00f0b378 VS |
12230 | continue; |
12231 | ||
5448a00d ACO |
12232 | encoder = to_intel_encoder(connector_state->best_encoder); |
12233 | ||
12234 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12235 | |
12236 | switch (encoder->type) { | |
12237 | unsigned int port_mask; | |
12238 | case INTEL_OUTPUT_UNKNOWN: | |
12239 | if (WARN_ON(!HAS_DDI(dev))) | |
12240 | break; | |
12241 | case INTEL_OUTPUT_DISPLAYPORT: | |
12242 | case INTEL_OUTPUT_HDMI: | |
12243 | case INTEL_OUTPUT_EDP: | |
12244 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12245 | ||
12246 | /* the same port mustn't appear more than once */ | |
12247 | if (used_ports & port_mask) | |
12248 | return false; | |
12249 | ||
12250 | used_ports |= port_mask; | |
12251 | default: | |
12252 | break; | |
12253 | } | |
12254 | } | |
12255 | ||
12256 | return true; | |
12257 | } | |
12258 | ||
83a57153 ACO |
12259 | static void |
12260 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12261 | { | |
12262 | struct drm_crtc_state tmp_state; | |
663a3640 | 12263 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 | 12264 | struct intel_dpll_hw_state dpll_hw_state; |
8106ddbd | 12265 | struct intel_shared_dpll *shared_dpll; |
8504c74c | 12266 | uint32_t ddi_pll_sel; |
c4e2d043 | 12267 | bool force_thru; |
83a57153 | 12268 | |
7546a384 ACO |
12269 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12270 | * kzalloc'd. Code that depends on any field being zero should be | |
12271 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12272 | * only fields that are know to not cause problems are preserved. */ | |
12273 | ||
83a57153 | 12274 | tmp_state = crtc_state->base; |
663a3640 | 12275 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12276 | shared_dpll = crtc_state->shared_dpll; |
12277 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 12278 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
c4e2d043 | 12279 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 12280 | |
83a57153 | 12281 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12282 | |
83a57153 | 12283 | crtc_state->base = tmp_state; |
663a3640 | 12284 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12285 | crtc_state->shared_dpll = shared_dpll; |
12286 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 12287 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
c4e2d043 | 12288 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
12289 | } |
12290 | ||
548ee15b | 12291 | static int |
b8cecdf5 | 12292 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12293 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12294 | { |
b359283a | 12295 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12296 | struct intel_encoder *encoder; |
da3ced29 | 12297 | struct drm_connector *connector; |
0b901879 | 12298 | struct drm_connector_state *connector_state; |
d328c9d7 | 12299 | int base_bpp, ret = -EINVAL; |
0b901879 | 12300 | int i; |
e29c22c0 | 12301 | bool retry = true; |
ee7b9f93 | 12302 | |
83a57153 | 12303 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12304 | |
e143a21c DV |
12305 | pipe_config->cpu_transcoder = |
12306 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12307 | |
2960bc9c ID |
12308 | /* |
12309 | * Sanitize sync polarity flags based on requested ones. If neither | |
12310 | * positive or negative polarity is requested, treat this as meaning | |
12311 | * negative polarity. | |
12312 | */ | |
2d112de7 | 12313 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12314 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12315 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 12316 | |
2d112de7 | 12317 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12318 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 12319 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 12320 | |
d328c9d7 DV |
12321 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
12322 | pipe_config); | |
12323 | if (base_bpp < 0) | |
4e53c2e0 DV |
12324 | goto fail; |
12325 | ||
e41a56be VS |
12326 | /* |
12327 | * Determine the real pipe dimensions. Note that stereo modes can | |
12328 | * increase the actual pipe size due to the frame doubling and | |
12329 | * insertion of additional space for blanks between the frame. This | |
12330 | * is stored in the crtc timings. We use the requested mode to do this | |
12331 | * computation to clearly distinguish it from the adjusted mode, which | |
12332 | * can be changed by the connectors in the below retry loop. | |
12333 | */ | |
2d112de7 | 12334 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
12335 | &pipe_config->pipe_src_w, |
12336 | &pipe_config->pipe_src_h); | |
e41a56be | 12337 | |
e29c22c0 | 12338 | encoder_retry: |
ef1b460d | 12339 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 12340 | pipe_config->port_clock = 0; |
ef1b460d | 12341 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 12342 | |
135c81b8 | 12343 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
12344 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
12345 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 12346 | |
7758a113 DV |
12347 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
12348 | * adjust it according to limitations or connector properties, and also | |
12349 | * a chance to reject the mode entirely. | |
47f1c6c9 | 12350 | */ |
da3ced29 | 12351 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 12352 | if (connector_state->crtc != crtc) |
7758a113 | 12353 | continue; |
7ae89233 | 12354 | |
0b901879 ACO |
12355 | encoder = to_intel_encoder(connector_state->best_encoder); |
12356 | ||
efea6e8e DV |
12357 | if (!(encoder->compute_config(encoder, pipe_config))) { |
12358 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
12359 | goto fail; |
12360 | } | |
ee7b9f93 | 12361 | } |
47f1c6c9 | 12362 | |
ff9a6750 DV |
12363 | /* Set default port clock if not overwritten by the encoder. Needs to be |
12364 | * done afterwards in case the encoder adjusts the mode. */ | |
12365 | if (!pipe_config->port_clock) | |
2d112de7 | 12366 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 12367 | * pipe_config->pixel_multiplier; |
ff9a6750 | 12368 | |
a43f6e0f | 12369 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 12370 | if (ret < 0) { |
7758a113 DV |
12371 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
12372 | goto fail; | |
ee7b9f93 | 12373 | } |
e29c22c0 DV |
12374 | |
12375 | if (ret == RETRY) { | |
12376 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
12377 | ret = -EINVAL; | |
12378 | goto fail; | |
12379 | } | |
12380 | ||
12381 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
12382 | retry = false; | |
12383 | goto encoder_retry; | |
12384 | } | |
12385 | ||
e8fa4270 DV |
12386 | /* Dithering seems to not pass-through bits correctly when it should, so |
12387 | * only enable it on 6bpc panels. */ | |
12388 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 12389 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 12390 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 12391 | |
7758a113 | 12392 | fail: |
548ee15b | 12393 | return ret; |
ee7b9f93 | 12394 | } |
47f1c6c9 | 12395 | |
ea9d758d | 12396 | static void |
4740b0f2 | 12397 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 12398 | { |
0a9ab303 ACO |
12399 | struct drm_crtc *crtc; |
12400 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 12401 | int i; |
ea9d758d | 12402 | |
7668851f | 12403 | /* Double check state. */ |
8a75d157 | 12404 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 12405 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
12406 | |
12407 | /* Update hwmode for vblank functions */ | |
12408 | if (crtc->state->active) | |
12409 | crtc->hwmode = crtc->state->adjusted_mode; | |
12410 | else | |
12411 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
12412 | |
12413 | /* | |
12414 | * Update legacy state to satisfy fbc code. This can | |
12415 | * be removed when fbc uses the atomic state. | |
12416 | */ | |
12417 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12418 | struct drm_plane_state *plane_state = crtc->primary->state; | |
12419 | ||
12420 | crtc->primary->fb = plane_state->fb; | |
12421 | crtc->x = plane_state->src_x >> 16; | |
12422 | crtc->y = plane_state->src_y >> 16; | |
12423 | } | |
ea9d758d | 12424 | } |
ea9d758d DV |
12425 | } |
12426 | ||
3bd26263 | 12427 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 12428 | { |
3bd26263 | 12429 | int diff; |
f1f644dc JB |
12430 | |
12431 | if (clock1 == clock2) | |
12432 | return true; | |
12433 | ||
12434 | if (!clock1 || !clock2) | |
12435 | return false; | |
12436 | ||
12437 | diff = abs(clock1 - clock2); | |
12438 | ||
12439 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
12440 | return true; | |
12441 | ||
12442 | return false; | |
12443 | } | |
12444 | ||
25c5b266 DV |
12445 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
12446 | list_for_each_entry((intel_crtc), \ | |
12447 | &(dev)->mode_config.crtc_list, \ | |
12448 | base.head) \ | |
95150bdf | 12449 | for_each_if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 12450 | |
cfb23ed6 ML |
12451 | static bool |
12452 | intel_compare_m_n(unsigned int m, unsigned int n, | |
12453 | unsigned int m2, unsigned int n2, | |
12454 | bool exact) | |
12455 | { | |
12456 | if (m == m2 && n == n2) | |
12457 | return true; | |
12458 | ||
12459 | if (exact || !m || !n || !m2 || !n2) | |
12460 | return false; | |
12461 | ||
12462 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
12463 | ||
31d10b57 ML |
12464 | if (n > n2) { |
12465 | while (n > n2) { | |
cfb23ed6 ML |
12466 | m2 <<= 1; |
12467 | n2 <<= 1; | |
12468 | } | |
31d10b57 ML |
12469 | } else if (n < n2) { |
12470 | while (n < n2) { | |
cfb23ed6 ML |
12471 | m <<= 1; |
12472 | n <<= 1; | |
12473 | } | |
12474 | } | |
12475 | ||
31d10b57 ML |
12476 | if (n != n2) |
12477 | return false; | |
12478 | ||
12479 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
12480 | } |
12481 | ||
12482 | static bool | |
12483 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
12484 | struct intel_link_m_n *m2_n2, | |
12485 | bool adjust) | |
12486 | { | |
12487 | if (m_n->tu == m2_n2->tu && | |
12488 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
12489 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
12490 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
12491 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
12492 | if (adjust) | |
12493 | *m2_n2 = *m_n; | |
12494 | ||
12495 | return true; | |
12496 | } | |
12497 | ||
12498 | return false; | |
12499 | } | |
12500 | ||
0e8ffe1b | 12501 | static bool |
2fa2fe9a | 12502 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b | 12503 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
12504 | struct intel_crtc_state *pipe_config, |
12505 | bool adjust) | |
0e8ffe1b | 12506 | { |
cfb23ed6 ML |
12507 | bool ret = true; |
12508 | ||
12509 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
12510 | do { \ | |
12511 | if (!adjust) \ | |
12512 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
12513 | else \ | |
12514 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
12515 | } while (0) | |
12516 | ||
66e985c0 DV |
12517 | #define PIPE_CONF_CHECK_X(name) \ |
12518 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12519 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
12520 | "(expected 0x%08x, found 0x%08x)\n", \ |
12521 | current_config->name, \ | |
12522 | pipe_config->name); \ | |
cfb23ed6 | 12523 | ret = false; \ |
66e985c0 DV |
12524 | } |
12525 | ||
08a24034 DV |
12526 | #define PIPE_CONF_CHECK_I(name) \ |
12527 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12528 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
12529 | "(expected %i, found %i)\n", \ |
12530 | current_config->name, \ | |
12531 | pipe_config->name); \ | |
cfb23ed6 ML |
12532 | ret = false; \ |
12533 | } | |
12534 | ||
8106ddbd ACO |
12535 | #define PIPE_CONF_CHECK_P(name) \ |
12536 | if (current_config->name != pipe_config->name) { \ | |
12537 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12538 | "(expected %p, found %p)\n", \ | |
12539 | current_config->name, \ | |
12540 | pipe_config->name); \ | |
12541 | ret = false; \ | |
12542 | } | |
12543 | ||
cfb23ed6 ML |
12544 | #define PIPE_CONF_CHECK_M_N(name) \ |
12545 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12546 | &pipe_config->name,\ | |
12547 | adjust)) { \ | |
12548 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12549 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12550 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12551 | current_config->name.tu, \ | |
12552 | current_config->name.gmch_m, \ | |
12553 | current_config->name.gmch_n, \ | |
12554 | current_config->name.link_m, \ | |
12555 | current_config->name.link_n, \ | |
12556 | pipe_config->name.tu, \ | |
12557 | pipe_config->name.gmch_m, \ | |
12558 | pipe_config->name.gmch_n, \ | |
12559 | pipe_config->name.link_m, \ | |
12560 | pipe_config->name.link_n); \ | |
12561 | ret = false; \ | |
12562 | } | |
12563 | ||
55c561a7 DV |
12564 | /* This is required for BDW+ where there is only one set of registers for |
12565 | * switching between high and low RR. | |
12566 | * This macro can be used whenever a comparison has to be made between one | |
12567 | * hw state and multiple sw state variables. | |
12568 | */ | |
cfb23ed6 ML |
12569 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ |
12570 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12571 | &pipe_config->name, adjust) && \ | |
12572 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
12573 | &pipe_config->name, adjust)) { \ | |
12574 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12575 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12576 | "or tu %i gmch %i/%i link %i/%i, " \ | |
12577 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12578 | current_config->name.tu, \ | |
12579 | current_config->name.gmch_m, \ | |
12580 | current_config->name.gmch_n, \ | |
12581 | current_config->name.link_m, \ | |
12582 | current_config->name.link_n, \ | |
12583 | current_config->alt_name.tu, \ | |
12584 | current_config->alt_name.gmch_m, \ | |
12585 | current_config->alt_name.gmch_n, \ | |
12586 | current_config->alt_name.link_m, \ | |
12587 | current_config->alt_name.link_n, \ | |
12588 | pipe_config->name.tu, \ | |
12589 | pipe_config->name.gmch_m, \ | |
12590 | pipe_config->name.gmch_n, \ | |
12591 | pipe_config->name.link_m, \ | |
12592 | pipe_config->name.link_n); \ | |
12593 | ret = false; \ | |
88adfff1 DV |
12594 | } |
12595 | ||
1bd1bd80 DV |
12596 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
12597 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 12598 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
12599 | "(expected %i, found %i)\n", \ |
12600 | current_config->name & (mask), \ | |
12601 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 12602 | ret = false; \ |
1bd1bd80 DV |
12603 | } |
12604 | ||
5e550656 VS |
12605 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
12606 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 12607 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
12608 | "(expected %i, found %i)\n", \ |
12609 | current_config->name, \ | |
12610 | pipe_config->name); \ | |
cfb23ed6 | 12611 | ret = false; \ |
5e550656 VS |
12612 | } |
12613 | ||
bb760063 DV |
12614 | #define PIPE_CONF_QUIRK(quirk) \ |
12615 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
12616 | ||
eccb140b DV |
12617 | PIPE_CONF_CHECK_I(cpu_transcoder); |
12618 | ||
08a24034 DV |
12619 | PIPE_CONF_CHECK_I(has_pch_encoder); |
12620 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 12621 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 12622 | |
eb14cb74 | 12623 | PIPE_CONF_CHECK_I(has_dp_encoder); |
90a6b7b0 | 12624 | PIPE_CONF_CHECK_I(lane_count); |
b95af8be VK |
12625 | |
12626 | if (INTEL_INFO(dev)->gen < 8) { | |
cfb23ed6 ML |
12627 | PIPE_CONF_CHECK_M_N(dp_m_n); |
12628 | ||
cfb23ed6 ML |
12629 | if (current_config->has_drrs) |
12630 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
12631 | } else | |
12632 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 12633 | |
a65347ba JN |
12634 | PIPE_CONF_CHECK_I(has_dsi_encoder); |
12635 | ||
2d112de7 ACO |
12636 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12637 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
12638 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
12639 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
12640 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
12641 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 12642 | |
2d112de7 ACO |
12643 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
12644 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
12645 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
12646 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
12647 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
12648 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 12649 | |
c93f54cf | 12650 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 12651 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 | 12652 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
666a4537 | 12653 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
b5a9fa09 | 12654 | PIPE_CONF_CHECK_I(limited_color_range); |
e43823ec | 12655 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 12656 | |
9ed109a7 DV |
12657 | PIPE_CONF_CHECK_I(has_audio); |
12658 | ||
2d112de7 | 12659 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
12660 | DRM_MODE_FLAG_INTERLACE); |
12661 | ||
bb760063 | 12662 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 12663 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12664 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 12665 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12666 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 12667 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12668 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 12669 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
12670 | DRM_MODE_FLAG_NVSYNC); |
12671 | } | |
045ac3b5 | 12672 | |
333b8ca8 | 12673 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a DV |
12674 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
12675 | if (INTEL_INFO(dev)->gen < 4) | |
7f7d8dd6 | 12676 | PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios); |
333b8ca8 | 12677 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 12678 | |
bfd16b2a ML |
12679 | if (!adjust) { |
12680 | PIPE_CONF_CHECK_I(pipe_src_w); | |
12681 | PIPE_CONF_CHECK_I(pipe_src_h); | |
12682 | ||
12683 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
12684 | if (current_config->pch_pfit.enabled) { | |
12685 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
12686 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
12687 | } | |
2fa2fe9a | 12688 | |
7aefe2b5 ML |
12689 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
12690 | } | |
a1b2278e | 12691 | |
e59150dc JB |
12692 | /* BDW+ don't expose a synchronous way to read the state */ |
12693 | if (IS_HASWELL(dev)) | |
12694 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 12695 | |
282740f7 VS |
12696 | PIPE_CONF_CHECK_I(double_wide); |
12697 | ||
26804afd DV |
12698 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
12699 | ||
8106ddbd | 12700 | PIPE_CONF_CHECK_P(shared_dpll); |
66e985c0 | 12701 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 12702 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
12703 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
12704 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 12705 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 12706 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
12707 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
12708 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
12709 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 12710 | |
47eacbab VS |
12711 | PIPE_CONF_CHECK_X(dsi_pll.ctrl); |
12712 | PIPE_CONF_CHECK_X(dsi_pll.div); | |
12713 | ||
42571aef VS |
12714 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
12715 | PIPE_CONF_CHECK_I(pipe_bpp); | |
12716 | ||
2d112de7 | 12717 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 12718 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 12719 | |
66e985c0 | 12720 | #undef PIPE_CONF_CHECK_X |
08a24034 | 12721 | #undef PIPE_CONF_CHECK_I |
8106ddbd | 12722 | #undef PIPE_CONF_CHECK_P |
1bd1bd80 | 12723 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 12724 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 12725 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 12726 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 12727 | |
cfb23ed6 | 12728 | return ret; |
0e8ffe1b DV |
12729 | } |
12730 | ||
e3b247da VS |
12731 | static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv, |
12732 | const struct intel_crtc_state *pipe_config) | |
12733 | { | |
12734 | if (pipe_config->has_pch_encoder) { | |
21a727b3 | 12735 | int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config), |
e3b247da VS |
12736 | &pipe_config->fdi_m_n); |
12737 | int dotclock = pipe_config->base.adjusted_mode.crtc_clock; | |
12738 | ||
12739 | /* | |
12740 | * FDI already provided one idea for the dotclock. | |
12741 | * Yell if the encoder disagrees. | |
12742 | */ | |
12743 | WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock), | |
12744 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", | |
12745 | fdi_dotclock, dotclock); | |
12746 | } | |
12747 | } | |
12748 | ||
c0ead703 ML |
12749 | static void verify_wm_state(struct drm_crtc *crtc, |
12750 | struct drm_crtc_state *new_state) | |
08db6652 | 12751 | { |
e7c84544 | 12752 | struct drm_device *dev = crtc->dev; |
08db6652 DL |
12753 | struct drm_i915_private *dev_priv = dev->dev_private; |
12754 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
e7c84544 ML |
12755 | struct skl_ddb_entry *hw_entry, *sw_entry; |
12756 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12757 | const enum pipe pipe = intel_crtc->pipe; | |
08db6652 DL |
12758 | int plane; |
12759 | ||
e7c84544 | 12760 | if (INTEL_INFO(dev)->gen < 9 || !new_state->active) |
08db6652 DL |
12761 | return; |
12762 | ||
12763 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
12764 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
12765 | ||
e7c84544 ML |
12766 | /* planes */ |
12767 | for_each_plane(dev_priv, pipe, plane) { | |
12768 | hw_entry = &hw_ddb.plane[pipe][plane]; | |
12769 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
08db6652 | 12770 | |
e7c84544 | 12771 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) |
08db6652 DL |
12772 | continue; |
12773 | ||
e7c84544 ML |
12774 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " |
12775 | "(expected (%u,%u), found (%u,%u))\n", | |
12776 | pipe_name(pipe), plane + 1, | |
12777 | sw_entry->start, sw_entry->end, | |
12778 | hw_entry->start, hw_entry->end); | |
12779 | } | |
08db6652 | 12780 | |
e7c84544 ML |
12781 | /* cursor */ |
12782 | hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; | |
12783 | sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
08db6652 | 12784 | |
e7c84544 | 12785 | if (!skl_ddb_entry_equal(hw_entry, sw_entry)) { |
08db6652 DL |
12786 | DRM_ERROR("mismatch in DDB state pipe %c cursor " |
12787 | "(expected (%u,%u), found (%u,%u))\n", | |
12788 | pipe_name(pipe), | |
12789 | sw_entry->start, sw_entry->end, | |
12790 | hw_entry->start, hw_entry->end); | |
12791 | } | |
12792 | } | |
12793 | ||
91d1b4bd | 12794 | static void |
c0ead703 | 12795 | verify_connector_state(struct drm_device *dev, struct drm_crtc *crtc) |
8af6cf88 | 12796 | { |
35dd3c64 | 12797 | struct drm_connector *connector; |
8af6cf88 | 12798 | |
e7c84544 | 12799 | drm_for_each_connector(connector, dev) { |
35dd3c64 ML |
12800 | struct drm_encoder *encoder = connector->encoder; |
12801 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 12802 | |
e7c84544 ML |
12803 | if (state->crtc != crtc) |
12804 | continue; | |
12805 | ||
c0ead703 | 12806 | intel_connector_verify_state(to_intel_connector(connector)); |
8af6cf88 | 12807 | |
ad3c558f | 12808 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 12809 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 12810 | } |
91d1b4bd DV |
12811 | } |
12812 | ||
12813 | static void | |
c0ead703 | 12814 | verify_encoder_state(struct drm_device *dev) |
91d1b4bd DV |
12815 | { |
12816 | struct intel_encoder *encoder; | |
12817 | struct intel_connector *connector; | |
8af6cf88 | 12818 | |
b2784e15 | 12819 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 12820 | bool enabled = false; |
4d20cd86 | 12821 | enum pipe pipe; |
8af6cf88 DV |
12822 | |
12823 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
12824 | encoder->base.base.id, | |
8e329a03 | 12825 | encoder->base.name); |
8af6cf88 | 12826 | |
3a3371ff | 12827 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 12828 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
12829 | continue; |
12830 | enabled = true; | |
ad3c558f ML |
12831 | |
12832 | I915_STATE_WARN(connector->base.state->crtc != | |
12833 | encoder->base.crtc, | |
12834 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 12835 | } |
0e32b39c | 12836 | |
e2c719b7 | 12837 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
12838 | "encoder's enabled state mismatch " |
12839 | "(expected %i, found %i)\n", | |
12840 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
12841 | |
12842 | if (!encoder->base.crtc) { | |
4d20cd86 | 12843 | bool active; |
7c60d198 | 12844 | |
4d20cd86 ML |
12845 | active = encoder->get_hw_state(encoder, &pipe); |
12846 | I915_STATE_WARN(active, | |
12847 | "encoder detached but still enabled on pipe %c.\n", | |
12848 | pipe_name(pipe)); | |
7c60d198 | 12849 | } |
8af6cf88 | 12850 | } |
91d1b4bd DV |
12851 | } |
12852 | ||
12853 | static void | |
c0ead703 ML |
12854 | verify_crtc_state(struct drm_crtc *crtc, |
12855 | struct drm_crtc_state *old_crtc_state, | |
12856 | struct drm_crtc_state *new_crtc_state) | |
91d1b4bd | 12857 | { |
e7c84544 | 12858 | struct drm_device *dev = crtc->dev; |
fbee40df | 12859 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd | 12860 | struct intel_encoder *encoder; |
e7c84544 ML |
12861 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
12862 | struct intel_crtc_state *pipe_config, *sw_config; | |
12863 | struct drm_atomic_state *old_state; | |
12864 | bool active; | |
045ac3b5 | 12865 | |
e7c84544 ML |
12866 | old_state = old_crtc_state->state; |
12867 | __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state); | |
12868 | pipe_config = to_intel_crtc_state(old_crtc_state); | |
12869 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
12870 | pipe_config->base.crtc = crtc; | |
12871 | pipe_config->base.state = old_state; | |
8af6cf88 | 12872 | |
e7c84544 | 12873 | DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id); |
8af6cf88 | 12874 | |
e7c84544 | 12875 | active = dev_priv->display.get_pipe_config(intel_crtc, pipe_config); |
d62cf62a | 12876 | |
e7c84544 ML |
12877 | /* hw state is inconsistent with the pipe quirk */ |
12878 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
12879 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
12880 | active = new_crtc_state->active; | |
6c49f241 | 12881 | |
e7c84544 ML |
12882 | I915_STATE_WARN(new_crtc_state->active != active, |
12883 | "crtc active state doesn't match with hw state " | |
12884 | "(expected %i, found %i)\n", new_crtc_state->active, active); | |
0e8ffe1b | 12885 | |
e7c84544 ML |
12886 | I915_STATE_WARN(intel_crtc->active != new_crtc_state->active, |
12887 | "transitional active state does not match atomic hw state " | |
12888 | "(expected %i, found %i)\n", new_crtc_state->active, intel_crtc->active); | |
4d20cd86 | 12889 | |
e7c84544 ML |
12890 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
12891 | enum pipe pipe; | |
4d20cd86 | 12892 | |
e7c84544 ML |
12893 | active = encoder->get_hw_state(encoder, &pipe); |
12894 | I915_STATE_WARN(active != new_crtc_state->active, | |
12895 | "[ENCODER:%i] active %i with crtc active %i\n", | |
12896 | encoder->base.base.id, active, new_crtc_state->active); | |
4d20cd86 | 12897 | |
e7c84544 ML |
12898 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, |
12899 | "Encoder connected to wrong pipe %c\n", | |
12900 | pipe_name(pipe)); | |
4d20cd86 | 12901 | |
e7c84544 ML |
12902 | if (active) |
12903 | encoder->get_config(encoder, pipe_config); | |
12904 | } | |
53d9f4e9 | 12905 | |
e7c84544 ML |
12906 | if (!new_crtc_state->active) |
12907 | return; | |
cfb23ed6 | 12908 | |
e7c84544 | 12909 | intel_pipe_config_sanity_check(dev_priv, pipe_config); |
e3b247da | 12910 | |
e7c84544 ML |
12911 | sw_config = to_intel_crtc_state(crtc->state); |
12912 | if (!intel_pipe_config_compare(dev, sw_config, | |
12913 | pipe_config, false)) { | |
12914 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); | |
12915 | intel_dump_pipe_config(intel_crtc, pipe_config, | |
12916 | "[hw state]"); | |
12917 | intel_dump_pipe_config(intel_crtc, sw_config, | |
12918 | "[sw state]"); | |
8af6cf88 DV |
12919 | } |
12920 | } | |
12921 | ||
91d1b4bd | 12922 | static void |
c0ead703 ML |
12923 | verify_single_dpll_state(struct drm_i915_private *dev_priv, |
12924 | struct intel_shared_dpll *pll, | |
12925 | struct drm_crtc *crtc, | |
12926 | struct drm_crtc_state *new_state) | |
91d1b4bd | 12927 | { |
91d1b4bd | 12928 | struct intel_dpll_hw_state dpll_hw_state; |
e7c84544 ML |
12929 | unsigned crtc_mask; |
12930 | bool active; | |
5358901f | 12931 | |
e7c84544 | 12932 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); |
5358901f | 12933 | |
e7c84544 | 12934 | DRM_DEBUG_KMS("%s\n", pll->name); |
5358901f | 12935 | |
e7c84544 | 12936 | active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state); |
5358901f | 12937 | |
e7c84544 ML |
12938 | if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) { |
12939 | I915_STATE_WARN(!pll->on && pll->active_mask, | |
12940 | "pll in active use but not on in sw tracking\n"); | |
12941 | I915_STATE_WARN(pll->on && !pll->active_mask, | |
12942 | "pll is on but not used by any active crtc\n"); | |
12943 | I915_STATE_WARN(pll->on != active, | |
12944 | "pll on state mismatch (expected %i, found %i)\n", | |
12945 | pll->on, active); | |
12946 | } | |
5358901f | 12947 | |
e7c84544 | 12948 | if (!crtc) { |
2dd66ebd | 12949 | I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask, |
e7c84544 ML |
12950 | "more active pll users than references: %x vs %x\n", |
12951 | pll->active_mask, pll->config.crtc_mask); | |
5358901f | 12952 | |
e7c84544 ML |
12953 | return; |
12954 | } | |
12955 | ||
12956 | crtc_mask = 1 << drm_crtc_index(crtc); | |
12957 | ||
12958 | if (new_state->active) | |
12959 | I915_STATE_WARN(!(pll->active_mask & crtc_mask), | |
12960 | "pll active mismatch (expected pipe %c in active mask 0x%02x)\n", | |
12961 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
12962 | else | |
12963 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
12964 | "pll active mismatch (didn't expect pipe %c in active mask 0x%02x)\n", | |
12965 | pipe_name(drm_crtc_index(crtc)), pll->active_mask); | |
2dd66ebd | 12966 | |
e7c84544 ML |
12967 | I915_STATE_WARN(!(pll->config.crtc_mask & crtc_mask), |
12968 | "pll enabled crtcs mismatch (expected 0x%x in 0x%02x)\n", | |
12969 | crtc_mask, pll->config.crtc_mask); | |
66e985c0 | 12970 | |
e7c84544 ML |
12971 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, |
12972 | &dpll_hw_state, | |
12973 | sizeof(dpll_hw_state)), | |
12974 | "pll hw state mismatch\n"); | |
12975 | } | |
12976 | ||
12977 | static void | |
c0ead703 ML |
12978 | verify_shared_dpll_state(struct drm_device *dev, struct drm_crtc *crtc, |
12979 | struct drm_crtc_state *old_crtc_state, | |
12980 | struct drm_crtc_state *new_crtc_state) | |
e7c84544 ML |
12981 | { |
12982 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12983 | struct intel_crtc_state *old_state = to_intel_crtc_state(old_crtc_state); | |
12984 | struct intel_crtc_state *new_state = to_intel_crtc_state(new_crtc_state); | |
12985 | ||
12986 | if (new_state->shared_dpll) | |
c0ead703 | 12987 | verify_single_dpll_state(dev_priv, new_state->shared_dpll, crtc, new_crtc_state); |
e7c84544 ML |
12988 | |
12989 | if (old_state->shared_dpll && | |
12990 | old_state->shared_dpll != new_state->shared_dpll) { | |
12991 | unsigned crtc_mask = 1 << drm_crtc_index(crtc); | |
12992 | struct intel_shared_dpll *pll = old_state->shared_dpll; | |
12993 | ||
12994 | I915_STATE_WARN(pll->active_mask & crtc_mask, | |
12995 | "pll active mismatch (didn't expect pipe %c in active mask)\n", | |
12996 | pipe_name(drm_crtc_index(crtc))); | |
12997 | I915_STATE_WARN(pll->config.crtc_mask & crtc_mask, | |
12998 | "pll enabled crtcs mismatch (found %x in enabled mask)\n", | |
12999 | pipe_name(drm_crtc_index(crtc))); | |
5358901f | 13000 | } |
8af6cf88 DV |
13001 | } |
13002 | ||
e7c84544 | 13003 | static void |
c0ead703 | 13004 | intel_modeset_verify_crtc(struct drm_crtc *crtc, |
e7c84544 ML |
13005 | struct drm_crtc_state *old_state, |
13006 | struct drm_crtc_state *new_state) | |
13007 | { | |
13008 | if (!needs_modeset(new_state) && | |
13009 | !to_intel_crtc_state(new_state)->update_pipe) | |
13010 | return; | |
13011 | ||
c0ead703 ML |
13012 | verify_wm_state(crtc, new_state); |
13013 | verify_connector_state(crtc->dev, crtc); | |
13014 | verify_crtc_state(crtc, old_state, new_state); | |
13015 | verify_shared_dpll_state(crtc->dev, crtc, old_state, new_state); | |
e7c84544 ML |
13016 | } |
13017 | ||
13018 | static void | |
c0ead703 | 13019 | verify_disabled_dpll_state(struct drm_device *dev) |
e7c84544 ML |
13020 | { |
13021 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13022 | int i; | |
13023 | ||
13024 | for (i = 0; i < dev_priv->num_shared_dpll; i++) | |
c0ead703 | 13025 | verify_single_dpll_state(dev_priv, &dev_priv->shared_dplls[i], NULL, NULL); |
e7c84544 ML |
13026 | } |
13027 | ||
13028 | static void | |
c0ead703 | 13029 | intel_modeset_verify_disabled(struct drm_device *dev) |
e7c84544 | 13030 | { |
c0ead703 ML |
13031 | verify_encoder_state(dev); |
13032 | verify_connector_state(dev, NULL); | |
13033 | verify_disabled_dpll_state(dev); | |
e7c84544 ML |
13034 | } |
13035 | ||
80715b2f VS |
13036 | static void update_scanline_offset(struct intel_crtc *crtc) |
13037 | { | |
13038 | struct drm_device *dev = crtc->base.dev; | |
13039 | ||
13040 | /* | |
13041 | * The scanline counter increments at the leading edge of hsync. | |
13042 | * | |
13043 | * On most platforms it starts counting from vtotal-1 on the | |
13044 | * first active line. That means the scanline counter value is | |
13045 | * always one less than what we would expect. Ie. just after | |
13046 | * start of vblank, which also occurs at start of hsync (on the | |
13047 | * last active line), the scanline counter will read vblank_start-1. | |
13048 | * | |
13049 | * On gen2 the scanline counter starts counting from 1 instead | |
13050 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
13051 | * to keep the value positive), instead of adding one. | |
13052 | * | |
13053 | * On HSW+ the behaviour of the scanline counter depends on the output | |
13054 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
13055 | * there's an extra 1 line difference. So we need to add two instead of | |
13056 | * one to the value. | |
13057 | */ | |
13058 | if (IS_GEN2(dev)) { | |
124abe07 | 13059 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
13060 | int vtotal; |
13061 | ||
124abe07 VS |
13062 | vtotal = adjusted_mode->crtc_vtotal; |
13063 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
13064 | vtotal /= 2; |
13065 | ||
13066 | crtc->scanline_offset = vtotal - 1; | |
13067 | } else if (HAS_DDI(dev) && | |
409ee761 | 13068 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
13069 | crtc->scanline_offset = 2; |
13070 | } else | |
13071 | crtc->scanline_offset = 1; | |
13072 | } | |
13073 | ||
ad421372 | 13074 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 13075 | { |
225da59b | 13076 | struct drm_device *dev = state->dev; |
ed6739ef | 13077 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 13078 | struct intel_shared_dpll_config *shared_dpll = NULL; |
0a9ab303 ACO |
13079 | struct drm_crtc *crtc; |
13080 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 13081 | int i; |
ed6739ef ACO |
13082 | |
13083 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 13084 | return; |
ed6739ef | 13085 | |
0a9ab303 | 13086 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
fb1a38a9 | 13087 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8106ddbd ACO |
13088 | struct intel_shared_dpll *old_dpll = |
13089 | to_intel_crtc_state(crtc->state)->shared_dpll; | |
0a9ab303 | 13090 | |
fb1a38a9 | 13091 | if (!needs_modeset(crtc_state)) |
225da59b ACO |
13092 | continue; |
13093 | ||
8106ddbd | 13094 | to_intel_crtc_state(crtc_state)->shared_dpll = NULL; |
fb1a38a9 | 13095 | |
8106ddbd | 13096 | if (!old_dpll) |
fb1a38a9 | 13097 | continue; |
0a9ab303 | 13098 | |
ad421372 ML |
13099 | if (!shared_dpll) |
13100 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 13101 | |
8106ddbd | 13102 | intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc); |
ad421372 | 13103 | } |
ed6739ef ACO |
13104 | } |
13105 | ||
99d736a2 ML |
13106 | /* |
13107 | * This implements the workaround described in the "notes" section of the mode | |
13108 | * set sequence documentation. When going from no pipes or single pipe to | |
13109 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
13110 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
13111 | */ | |
13112 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
13113 | { | |
13114 | struct drm_crtc_state *crtc_state; | |
13115 | struct intel_crtc *intel_crtc; | |
13116 | struct drm_crtc *crtc; | |
13117 | struct intel_crtc_state *first_crtc_state = NULL; | |
13118 | struct intel_crtc_state *other_crtc_state = NULL; | |
13119 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
13120 | int i; | |
13121 | ||
13122 | /* look at all crtc's that are going to be enabled in during modeset */ | |
13123 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13124 | intel_crtc = to_intel_crtc(crtc); | |
13125 | ||
13126 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
13127 | continue; | |
13128 | ||
13129 | if (first_crtc_state) { | |
13130 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
13131 | break; | |
13132 | } else { | |
13133 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
13134 | first_pipe = intel_crtc->pipe; | |
13135 | } | |
13136 | } | |
13137 | ||
13138 | /* No workaround needed? */ | |
13139 | if (!first_crtc_state) | |
13140 | return 0; | |
13141 | ||
13142 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
13143 | for_each_intel_crtc(state->dev, intel_crtc) { | |
13144 | struct intel_crtc_state *pipe_config; | |
13145 | ||
13146 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
13147 | if (IS_ERR(pipe_config)) | |
13148 | return PTR_ERR(pipe_config); | |
13149 | ||
13150 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
13151 | ||
13152 | if (!pipe_config->base.active || | |
13153 | needs_modeset(&pipe_config->base)) | |
13154 | continue; | |
13155 | ||
13156 | /* 2 or more enabled crtcs means no need for w/a */ | |
13157 | if (enabled_pipe != INVALID_PIPE) | |
13158 | return 0; | |
13159 | ||
13160 | enabled_pipe = intel_crtc->pipe; | |
13161 | } | |
13162 | ||
13163 | if (enabled_pipe != INVALID_PIPE) | |
13164 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
13165 | else if (other_crtc_state) | |
13166 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
13167 | ||
13168 | return 0; | |
13169 | } | |
13170 | ||
27c329ed ML |
13171 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
13172 | { | |
13173 | struct drm_crtc *crtc; | |
13174 | struct drm_crtc_state *crtc_state; | |
13175 | int ret = 0; | |
13176 | ||
13177 | /* add all active pipes to the state */ | |
13178 | for_each_crtc(state->dev, crtc) { | |
13179 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13180 | if (IS_ERR(crtc_state)) | |
13181 | return PTR_ERR(crtc_state); | |
13182 | ||
13183 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
13184 | continue; | |
13185 | ||
13186 | crtc_state->mode_changed = true; | |
13187 | ||
13188 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
13189 | if (ret) | |
13190 | break; | |
13191 | ||
13192 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13193 | if (ret) | |
13194 | break; | |
13195 | } | |
13196 | ||
13197 | return ret; | |
13198 | } | |
13199 | ||
c347a676 | 13200 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 13201 | { |
565602d7 ML |
13202 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
13203 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
13204 | struct drm_crtc *crtc; | |
13205 | struct drm_crtc_state *crtc_state; | |
13206 | int ret = 0, i; | |
054518dd | 13207 | |
b359283a ML |
13208 | if (!check_digital_port_conflicts(state)) { |
13209 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
13210 | return -EINVAL; | |
13211 | } | |
13212 | ||
565602d7 ML |
13213 | intel_state->modeset = true; |
13214 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
13215 | ||
13216 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13217 | if (crtc_state->active) | |
13218 | intel_state->active_crtcs |= 1 << i; | |
13219 | else | |
13220 | intel_state->active_crtcs &= ~(1 << i); | |
8b4a7d05 MR |
13221 | |
13222 | if (crtc_state->active != crtc->state->active) | |
13223 | intel_state->active_pipe_changes |= drm_crtc_mask(crtc); | |
565602d7 ML |
13224 | } |
13225 | ||
054518dd ACO |
13226 | /* |
13227 | * See if the config requires any additional preparation, e.g. | |
13228 | * to adjust global state with pipes off. We need to do this | |
13229 | * here so we can get the modeset_pipe updated config for the new | |
13230 | * mode set on this crtc. For other crtcs we need to use the | |
13231 | * adjusted_mode bits in the crtc directly. | |
13232 | */ | |
27c329ed | 13233 | if (dev_priv->display.modeset_calc_cdclk) { |
27c329ed ML |
13234 | ret = dev_priv->display.modeset_calc_cdclk(state); |
13235 | ||
1a617b77 | 13236 | if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq) |
27c329ed ML |
13237 | ret = intel_modeset_all_pipes(state); |
13238 | ||
13239 | if (ret < 0) | |
054518dd | 13240 | return ret; |
e8788cbc ML |
13241 | |
13242 | DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n", | |
13243 | intel_state->cdclk, intel_state->dev_cdclk); | |
27c329ed | 13244 | } else |
1a617b77 | 13245 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; |
054518dd | 13246 | |
ad421372 | 13247 | intel_modeset_clear_plls(state); |
054518dd | 13248 | |
565602d7 | 13249 | if (IS_HASWELL(dev_priv)) |
ad421372 | 13250 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 13251 | |
ad421372 | 13252 | return 0; |
c347a676 ACO |
13253 | } |
13254 | ||
aa363136 MR |
13255 | /* |
13256 | * Handle calculation of various watermark data at the end of the atomic check | |
13257 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
13258 | * handlers to ensure that all derived state has been updated. | |
13259 | */ | |
55994c2c | 13260 | static int calc_watermark_data(struct drm_atomic_state *state) |
aa363136 MR |
13261 | { |
13262 | struct drm_device *dev = state->dev; | |
98d39494 | 13263 | struct drm_i915_private *dev_priv = to_i915(dev); |
98d39494 MR |
13264 | |
13265 | /* Is there platform-specific watermark information to calculate? */ | |
13266 | if (dev_priv->display.compute_global_watermarks) | |
55994c2c MR |
13267 | return dev_priv->display.compute_global_watermarks(state); |
13268 | ||
13269 | return 0; | |
aa363136 MR |
13270 | } |
13271 | ||
74c090b1 ML |
13272 | /** |
13273 | * intel_atomic_check - validate state object | |
13274 | * @dev: drm device | |
13275 | * @state: state to validate | |
13276 | */ | |
13277 | static int intel_atomic_check(struct drm_device *dev, | |
13278 | struct drm_atomic_state *state) | |
c347a676 | 13279 | { |
dd8b3bdb | 13280 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 13281 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
13282 | struct drm_crtc *crtc; |
13283 | struct drm_crtc_state *crtc_state; | |
13284 | int ret, i; | |
61333b60 | 13285 | bool any_ms = false; |
c347a676 | 13286 | |
74c090b1 | 13287 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
13288 | if (ret) |
13289 | return ret; | |
13290 | ||
c347a676 | 13291 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
13292 | struct intel_crtc_state *pipe_config = |
13293 | to_intel_crtc_state(crtc_state); | |
1ed51de9 DV |
13294 | |
13295 | /* Catch I915_MODE_FLAG_INHERITED */ | |
13296 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
13297 | crtc_state->mode_changed = true; | |
cfb23ed6 | 13298 | |
af4a879e | 13299 | if (!needs_modeset(crtc_state)) |
c347a676 ACO |
13300 | continue; |
13301 | ||
af4a879e DV |
13302 | if (!crtc_state->enable) { |
13303 | any_ms = true; | |
cfb23ed6 | 13304 | continue; |
af4a879e | 13305 | } |
cfb23ed6 | 13306 | |
26495481 DV |
13307 | /* FIXME: For only active_changed we shouldn't need to do any |
13308 | * state recomputation at all. */ | |
13309 | ||
1ed51de9 DV |
13310 | ret = drm_atomic_add_affected_connectors(state, crtc); |
13311 | if (ret) | |
13312 | return ret; | |
b359283a | 13313 | |
cfb23ed6 | 13314 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
25aa1c39 ML |
13315 | if (ret) { |
13316 | intel_dump_pipe_config(to_intel_crtc(crtc), | |
13317 | pipe_config, "[failed]"); | |
c347a676 | 13318 | return ret; |
25aa1c39 | 13319 | } |
c347a676 | 13320 | |
73831236 | 13321 | if (i915.fastboot && |
dd8b3bdb | 13322 | intel_pipe_config_compare(dev, |
cfb23ed6 | 13323 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 13324 | pipe_config, true)) { |
26495481 | 13325 | crtc_state->mode_changed = false; |
bfd16b2a | 13326 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
13327 | } |
13328 | ||
af4a879e | 13329 | if (needs_modeset(crtc_state)) |
26495481 | 13330 | any_ms = true; |
cfb23ed6 | 13331 | |
af4a879e DV |
13332 | ret = drm_atomic_add_affected_planes(state, crtc); |
13333 | if (ret) | |
13334 | return ret; | |
61333b60 | 13335 | |
26495481 DV |
13336 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
13337 | needs_modeset(crtc_state) ? | |
13338 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
13339 | } |
13340 | ||
61333b60 ML |
13341 | if (any_ms) { |
13342 | ret = intel_modeset_checks(state); | |
13343 | ||
13344 | if (ret) | |
13345 | return ret; | |
27c329ed | 13346 | } else |
dd8b3bdb | 13347 | intel_state->cdclk = dev_priv->cdclk_freq; |
76305b1a | 13348 | |
dd8b3bdb | 13349 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
13350 | if (ret) |
13351 | return ret; | |
13352 | ||
f51be2e0 | 13353 | intel_fbc_choose_crtc(dev_priv, state); |
55994c2c | 13354 | return calc_watermark_data(state); |
054518dd ACO |
13355 | } |
13356 | ||
5008e874 ML |
13357 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
13358 | struct drm_atomic_state *state, | |
81072bfd | 13359 | bool nonblock) |
5008e874 | 13360 | { |
7580d774 ML |
13361 | struct drm_i915_private *dev_priv = dev->dev_private; |
13362 | struct drm_plane_state *plane_state; | |
5008e874 | 13363 | struct drm_crtc_state *crtc_state; |
7580d774 | 13364 | struct drm_plane *plane; |
5008e874 ML |
13365 | struct drm_crtc *crtc; |
13366 | int i, ret; | |
13367 | ||
81072bfd ML |
13368 | if (nonblock) { |
13369 | DRM_DEBUG_KMS("i915 does not yet support nonblocking commit\n"); | |
5008e874 ML |
13370 | return -EINVAL; |
13371 | } | |
13372 | ||
13373 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
acf4e84d CW |
13374 | if (state->legacy_cursor_update) |
13375 | continue; | |
13376 | ||
5008e874 ML |
13377 | ret = intel_crtc_wait_for_pending_flips(crtc); |
13378 | if (ret) | |
13379 | return ret; | |
7580d774 ML |
13380 | |
13381 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) | |
13382 | flush_workqueue(dev_priv->wq); | |
5008e874 ML |
13383 | } |
13384 | ||
f935675f ML |
13385 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
13386 | if (ret) | |
13387 | return ret; | |
13388 | ||
5008e874 | 13389 | ret = drm_atomic_helper_prepare_planes(dev, state); |
f7e5838b | 13390 | mutex_unlock(&dev->struct_mutex); |
7580d774 | 13391 | |
21daaeee | 13392 | if (!ret && !nonblock) { |
7580d774 ML |
13393 | for_each_plane_in_state(state, plane, plane_state, i) { |
13394 | struct intel_plane_state *intel_plane_state = | |
13395 | to_intel_plane_state(plane_state); | |
13396 | ||
13397 | if (!intel_plane_state->wait_req) | |
13398 | continue; | |
13399 | ||
13400 | ret = __i915_wait_request(intel_plane_state->wait_req, | |
299259a3 | 13401 | true, NULL, NULL); |
f7e5838b | 13402 | if (ret) { |
f4457ae7 CW |
13403 | /* Any hang should be swallowed by the wait */ |
13404 | WARN_ON(ret == -EIO); | |
f7e5838b CW |
13405 | mutex_lock(&dev->struct_mutex); |
13406 | drm_atomic_helper_cleanup_planes(dev, state); | |
13407 | mutex_unlock(&dev->struct_mutex); | |
7580d774 | 13408 | break; |
f7e5838b | 13409 | } |
7580d774 | 13410 | } |
7580d774 | 13411 | } |
5008e874 ML |
13412 | |
13413 | return ret; | |
13414 | } | |
13415 | ||
e8861675 ML |
13416 | static void intel_atomic_wait_for_vblanks(struct drm_device *dev, |
13417 | struct drm_i915_private *dev_priv, | |
13418 | unsigned crtc_mask) | |
13419 | { | |
13420 | unsigned last_vblank_count[I915_MAX_PIPES]; | |
13421 | enum pipe pipe; | |
13422 | int ret; | |
13423 | ||
13424 | if (!crtc_mask) | |
13425 | return; | |
13426 | ||
13427 | for_each_pipe(dev_priv, pipe) { | |
13428 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
13429 | ||
13430 | if (!((1 << pipe) & crtc_mask)) | |
13431 | continue; | |
13432 | ||
13433 | ret = drm_crtc_vblank_get(crtc); | |
13434 | if (WARN_ON(ret != 0)) { | |
13435 | crtc_mask &= ~(1 << pipe); | |
13436 | continue; | |
13437 | } | |
13438 | ||
13439 | last_vblank_count[pipe] = drm_crtc_vblank_count(crtc); | |
13440 | } | |
13441 | ||
13442 | for_each_pipe(dev_priv, pipe) { | |
13443 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
13444 | long lret; | |
13445 | ||
13446 | if (!((1 << pipe) & crtc_mask)) | |
13447 | continue; | |
13448 | ||
13449 | lret = wait_event_timeout(dev->vblank[pipe].queue, | |
13450 | last_vblank_count[pipe] != | |
13451 | drm_crtc_vblank_count(crtc), | |
13452 | msecs_to_jiffies(50)); | |
13453 | ||
8a8dae26 | 13454 | WARN(!lret, "pipe %c vblank wait timed out\n", pipe_name(pipe)); |
e8861675 ML |
13455 | |
13456 | drm_crtc_vblank_put(crtc); | |
13457 | } | |
13458 | } | |
13459 | ||
13460 | static bool needs_vblank_wait(struct intel_crtc_state *crtc_state) | |
13461 | { | |
13462 | /* fb updated, need to unpin old fb */ | |
13463 | if (crtc_state->fb_changed) | |
13464 | return true; | |
13465 | ||
13466 | /* wm changes, need vblank before final wm's */ | |
caed361d | 13467 | if (crtc_state->update_wm_post) |
e8861675 ML |
13468 | return true; |
13469 | ||
13470 | /* | |
13471 | * cxsr is re-enabled after vblank. | |
caed361d | 13472 | * This is already handled by crtc_state->update_wm_post, |
e8861675 ML |
13473 | * but added for clarity. |
13474 | */ | |
13475 | if (crtc_state->disable_cxsr) | |
13476 | return true; | |
13477 | ||
13478 | return false; | |
13479 | } | |
13480 | ||
74c090b1 ML |
13481 | /** |
13482 | * intel_atomic_commit - commit validated state object | |
13483 | * @dev: DRM device | |
13484 | * @state: the top-level driver state object | |
81072bfd | 13485 | * @nonblock: nonblocking commit |
74c090b1 ML |
13486 | * |
13487 | * This function commits a top-level state object that has been validated | |
13488 | * with drm_atomic_helper_check(). | |
13489 | * | |
13490 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment | |
13491 | * we can only handle plane-related operations and do not yet support | |
81072bfd | 13492 | * nonblocking commit. |
74c090b1 ML |
13493 | * |
13494 | * RETURNS | |
13495 | * Zero for success or -errno. | |
13496 | */ | |
13497 | static int intel_atomic_commit(struct drm_device *dev, | |
13498 | struct drm_atomic_state *state, | |
81072bfd | 13499 | bool nonblock) |
a6778b3c | 13500 | { |
565602d7 | 13501 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fbee40df | 13502 | struct drm_i915_private *dev_priv = dev->dev_private; |
29ceb0e6 | 13503 | struct drm_crtc_state *old_crtc_state; |
7580d774 | 13504 | struct drm_crtc *crtc; |
ed4a6a7c | 13505 | struct intel_crtc_state *intel_cstate; |
565602d7 ML |
13506 | int ret = 0, i; |
13507 | bool hw_check = intel_state->modeset; | |
33c8df89 | 13508 | unsigned long put_domains[I915_MAX_PIPES] = {}; |
e8861675 | 13509 | unsigned crtc_vblank_mask = 0; |
a6778b3c | 13510 | |
81072bfd | 13511 | ret = intel_atomic_prepare_commit(dev, state, nonblock); |
7580d774 ML |
13512 | if (ret) { |
13513 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
d4afb8cc | 13514 | return ret; |
7580d774 | 13515 | } |
d4afb8cc | 13516 | |
1c5e19f8 | 13517 | drm_atomic_helper_swap_state(dev, state); |
279e99d7 | 13518 | dev_priv->wm.distrust_bios_wm = false; |
734fa01f | 13519 | dev_priv->wm.skl_results = intel_state->wm_results; |
a1475e77 | 13520 | intel_shared_dpll_commit(state); |
1c5e19f8 | 13521 | |
565602d7 ML |
13522 | if (intel_state->modeset) { |
13523 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
13524 | sizeof(intel_state->min_pixclk)); | |
13525 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
1a617b77 | 13526 | dev_priv->atomic_cdclk_freq = intel_state->cdclk; |
33c8df89 ML |
13527 | |
13528 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); | |
565602d7 ML |
13529 | } |
13530 | ||
29ceb0e6 | 13531 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
a539205a ML |
13532 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13533 | ||
33c8df89 ML |
13534 | if (needs_modeset(crtc->state) || |
13535 | to_intel_crtc_state(crtc->state)->update_pipe) { | |
13536 | hw_check = true; | |
13537 | ||
13538 | put_domains[to_intel_crtc(crtc)->pipe] = | |
13539 | modeset_get_crtc_power_domains(crtc, | |
13540 | to_intel_crtc_state(crtc->state)); | |
13541 | } | |
13542 | ||
61333b60 ML |
13543 | if (!needs_modeset(crtc->state)) |
13544 | continue; | |
13545 | ||
29ceb0e6 | 13546 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
460da916 | 13547 | |
29ceb0e6 VS |
13548 | if (old_crtc_state->active) { |
13549 | intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask); | |
a539205a | 13550 | dev_priv->display.crtc_disable(crtc); |
eddfcbcd | 13551 | intel_crtc->active = false; |
58f9c0bc | 13552 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 13553 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
13554 | |
13555 | /* | |
13556 | * Underruns don't always raise | |
13557 | * interrupts, so check manually. | |
13558 | */ | |
13559 | intel_check_cpu_fifo_underruns(dev_priv); | |
13560 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 ML |
13561 | |
13562 | if (!crtc->state->active) | |
13563 | intel_update_watermarks(crtc); | |
a539205a | 13564 | } |
b8cecdf5 | 13565 | } |
7758a113 | 13566 | |
ea9d758d DV |
13567 | /* Only after disabling all output pipelines that will be changed can we |
13568 | * update the the output configuration. */ | |
4740b0f2 | 13569 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 13570 | |
565602d7 | 13571 | if (intel_state->modeset) { |
4740b0f2 | 13572 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); |
33c8df89 ML |
13573 | |
13574 | if (dev_priv->display.modeset_commit_cdclk && | |
13575 | intel_state->dev_cdclk != dev_priv->cdclk_freq) | |
13576 | dev_priv->display.modeset_commit_cdclk(state); | |
f6d1973d | 13577 | |
c0ead703 | 13578 | intel_modeset_verify_disabled(dev); |
4740b0f2 | 13579 | } |
47fab737 | 13580 | |
a6778b3c | 13581 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
29ceb0e6 | 13582 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
f6ac4b2a ML |
13583 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13584 | bool modeset = needs_modeset(crtc->state); | |
e8861675 ML |
13585 | struct intel_crtc_state *pipe_config = |
13586 | to_intel_crtc_state(crtc->state); | |
13587 | bool update_pipe = !modeset && pipe_config->update_pipe; | |
9f836f90 | 13588 | |
f6ac4b2a | 13589 | if (modeset && crtc->state->active) { |
a539205a ML |
13590 | update_scanline_offset(to_intel_crtc(crtc)); |
13591 | dev_priv->display.crtc_enable(crtc); | |
13592 | } | |
80715b2f | 13593 | |
f6ac4b2a | 13594 | if (!modeset) |
29ceb0e6 | 13595 | intel_pre_plane_update(to_intel_crtc_state(old_crtc_state)); |
f6ac4b2a | 13596 | |
31ae71fc ML |
13597 | if (crtc->state->active && |
13598 | drm_atomic_get_existing_plane_state(state, crtc->primary)) | |
49227c4a PZ |
13599 | intel_fbc_enable(intel_crtc); |
13600 | ||
6173ee28 ML |
13601 | if (crtc->state->active && |
13602 | (crtc->state->planes_changed || update_pipe)) | |
29ceb0e6 | 13603 | drm_atomic_helper_commit_planes_on_crtc(old_crtc_state); |
bfd16b2a | 13604 | |
e8861675 ML |
13605 | if (pipe_config->base.active && needs_vblank_wait(pipe_config)) |
13606 | crtc_vblank_mask |= 1 << i; | |
80715b2f | 13607 | } |
a6778b3c | 13608 | |
a6778b3c | 13609 | /* FIXME: add subpixel order */ |
83a57153 | 13610 | |
e8861675 ML |
13611 | if (!state->legacy_cursor_update) |
13612 | intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask); | |
f935675f | 13613 | |
ed4a6a7c MR |
13614 | /* |
13615 | * Now that the vblank has passed, we can go ahead and program the | |
13616 | * optimal watermarks on platforms that need two-step watermark | |
13617 | * programming. | |
13618 | * | |
13619 | * TODO: Move this (and other cleanup) to an async worker eventually. | |
13620 | */ | |
29ceb0e6 | 13621 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
ed4a6a7c MR |
13622 | intel_cstate = to_intel_crtc_state(crtc->state); |
13623 | ||
13624 | if (dev_priv->display.optimize_watermarks) | |
13625 | dev_priv->display.optimize_watermarks(intel_cstate); | |
13626 | } | |
13627 | ||
177246a8 MR |
13628 | for_each_crtc_in_state(state, crtc, old_crtc_state, i) { |
13629 | intel_post_plane_update(to_intel_crtc_state(old_crtc_state)); | |
13630 | ||
13631 | if (put_domains[i]) | |
13632 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
f6d1973d | 13633 | |
c0ead703 | 13634 | intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state); |
177246a8 MR |
13635 | } |
13636 | ||
13637 | if (intel_state->modeset) | |
13638 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
13639 | ||
f935675f | 13640 | mutex_lock(&dev->struct_mutex); |
d4afb8cc | 13641 | drm_atomic_helper_cleanup_planes(dev, state); |
f935675f | 13642 | mutex_unlock(&dev->struct_mutex); |
2bfb4627 | 13643 | |
ee165b1a | 13644 | drm_atomic_state_free(state); |
f30da187 | 13645 | |
75714940 MK |
13646 | /* As one of the primary mmio accessors, KMS has a high likelihood |
13647 | * of triggering bugs in unclaimed access. After we finish | |
13648 | * modesetting, see if an error has been flagged, and if so | |
13649 | * enable debugging for the next modeset - and hope we catch | |
13650 | * the culprit. | |
13651 | * | |
13652 | * XXX note that we assume display power is on at this point. | |
13653 | * This might hold true now but we need to add pm helper to check | |
13654 | * unclaimed only when the hardware is on, as atomic commits | |
13655 | * can happen also when the device is completely off. | |
13656 | */ | |
13657 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
13658 | ||
74c090b1 | 13659 | return 0; |
7f27126e JB |
13660 | } |
13661 | ||
c0c36b94 CW |
13662 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13663 | { | |
83a57153 ACO |
13664 | struct drm_device *dev = crtc->dev; |
13665 | struct drm_atomic_state *state; | |
e694eb02 | 13666 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 13667 | int ret; |
83a57153 ACO |
13668 | |
13669 | state = drm_atomic_state_alloc(dev); | |
13670 | if (!state) { | |
e694eb02 | 13671 | DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory", |
83a57153 ACO |
13672 | crtc->base.id); |
13673 | return; | |
13674 | } | |
13675 | ||
e694eb02 | 13676 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 13677 | |
e694eb02 ML |
13678 | retry: |
13679 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13680 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
13681 | if (!ret) { | |
13682 | if (!crtc_state->active) | |
13683 | goto out; | |
83a57153 | 13684 | |
e694eb02 | 13685 | crtc_state->mode_changed = true; |
74c090b1 | 13686 | ret = drm_atomic_commit(state); |
83a57153 ACO |
13687 | } |
13688 | ||
e694eb02 ML |
13689 | if (ret == -EDEADLK) { |
13690 | drm_atomic_state_clear(state); | |
13691 | drm_modeset_backoff(state->acquire_ctx); | |
13692 | goto retry; | |
4ed9fb37 | 13693 | } |
4be07317 | 13694 | |
2bfb4627 | 13695 | if (ret) |
e694eb02 | 13696 | out: |
2bfb4627 | 13697 | drm_atomic_state_free(state); |
c0c36b94 CW |
13698 | } |
13699 | ||
25c5b266 DV |
13700 | #undef for_each_intel_crtc_masked |
13701 | ||
f6e5b160 | 13702 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
82cf435b | 13703 | .gamma_set = drm_atomic_helper_legacy_gamma_set, |
74c090b1 | 13704 | .set_config = drm_atomic_helper_set_config, |
82cf435b | 13705 | .set_property = drm_atomic_helper_crtc_set_property, |
f6e5b160 CW |
13706 | .destroy = intel_crtc_destroy, |
13707 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
13708 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13709 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
13710 | }; |
13711 | ||
6beb8c23 MR |
13712 | /** |
13713 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13714 | * @plane: drm plane to prepare for | |
13715 | * @fb: framebuffer to prepare for presentation | |
13716 | * | |
13717 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13718 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13719 | * bits. Some older platforms need special physical address handling for | |
13720 | * cursor planes. | |
13721 | * | |
f935675f ML |
13722 | * Must be called with struct_mutex held. |
13723 | * | |
6beb8c23 MR |
13724 | * Returns 0 on success, negative error code on failure. |
13725 | */ | |
13726 | int | |
13727 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee | 13728 | const struct drm_plane_state *new_state) |
465c120c MR |
13729 | { |
13730 | struct drm_device *dev = plane->dev; | |
844f9111 | 13731 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 13732 | struct intel_plane *intel_plane = to_intel_plane(plane); |
6beb8c23 | 13733 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 13734 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
6beb8c23 | 13735 | int ret = 0; |
465c120c | 13736 | |
1ee49399 | 13737 | if (!obj && !old_obj) |
465c120c MR |
13738 | return 0; |
13739 | ||
5008e874 ML |
13740 | if (old_obj) { |
13741 | struct drm_crtc_state *crtc_state = | |
13742 | drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc); | |
13743 | ||
13744 | /* Big Hammer, we also need to ensure that any pending | |
13745 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
13746 | * current scanout is retired before unpinning the old | |
13747 | * framebuffer. Note that we rely on userspace rendering | |
13748 | * into the buffer attached to the pipe they are waiting | |
13749 | * on. If not, userspace generates a GPU hang with IPEHR | |
13750 | * point to the MI_WAIT_FOR_EVENT. | |
13751 | * | |
13752 | * This should only fail upon a hung GPU, in which case we | |
13753 | * can safely continue. | |
13754 | */ | |
13755 | if (needs_modeset(crtc_state)) | |
13756 | ret = i915_gem_object_wait_rendering(old_obj, true); | |
f4457ae7 CW |
13757 | if (ret) { |
13758 | /* GPU hangs should have been swallowed by the wait */ | |
13759 | WARN_ON(ret == -EIO); | |
f935675f | 13760 | return ret; |
f4457ae7 | 13761 | } |
5008e874 ML |
13762 | } |
13763 | ||
3c28ff22 AG |
13764 | /* For framebuffer backed by dmabuf, wait for fence */ |
13765 | if (obj && obj->base.dma_buf) { | |
bcf8be27 ML |
13766 | long lret; |
13767 | ||
13768 | lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
13769 | false, true, | |
13770 | MAX_SCHEDULE_TIMEOUT); | |
13771 | if (lret == -ERESTARTSYS) | |
13772 | return lret; | |
3c28ff22 | 13773 | |
bcf8be27 | 13774 | WARN(lret < 0, "waiting returns %li\n", lret); |
3c28ff22 AG |
13775 | } |
13776 | ||
1ee49399 ML |
13777 | if (!obj) { |
13778 | ret = 0; | |
13779 | } else if (plane->type == DRM_PLANE_TYPE_CURSOR && | |
6beb8c23 MR |
13780 | INTEL_INFO(dev)->cursor_needs_physical) { |
13781 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
13782 | ret = i915_gem_object_attach_phys(obj, align); | |
13783 | if (ret) | |
13784 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13785 | } else { | |
3465c580 | 13786 | ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation); |
6beb8c23 | 13787 | } |
465c120c | 13788 | |
7580d774 ML |
13789 | if (ret == 0) { |
13790 | if (obj) { | |
13791 | struct intel_plane_state *plane_state = | |
13792 | to_intel_plane_state(new_state); | |
13793 | ||
13794 | i915_gem_request_assign(&plane_state->wait_req, | |
13795 | obj->last_write_req); | |
13796 | } | |
13797 | ||
a9ff8714 | 13798 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); |
7580d774 | 13799 | } |
fdd508a6 | 13800 | |
6beb8c23 MR |
13801 | return ret; |
13802 | } | |
13803 | ||
38f3ce3a MR |
13804 | /** |
13805 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13806 | * @plane: drm plane to clean up for | |
13807 | * @fb: old framebuffer that was on plane | |
13808 | * | |
13809 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
13810 | * |
13811 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
13812 | */ |
13813 | void | |
13814 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee | 13815 | const struct drm_plane_state *old_state) |
38f3ce3a MR |
13816 | { |
13817 | struct drm_device *dev = plane->dev; | |
1ee49399 | 13818 | struct intel_plane *intel_plane = to_intel_plane(plane); |
7580d774 | 13819 | struct intel_plane_state *old_intel_state; |
1ee49399 ML |
13820 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
13821 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); | |
38f3ce3a | 13822 | |
7580d774 ML |
13823 | old_intel_state = to_intel_plane_state(old_state); |
13824 | ||
1ee49399 | 13825 | if (!obj && !old_obj) |
38f3ce3a MR |
13826 | return; |
13827 | ||
1ee49399 ML |
13828 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
13829 | !INTEL_INFO(dev)->cursor_needs_physical)) | |
3465c580 | 13830 | intel_unpin_fb_obj(old_state->fb, old_state->rotation); |
1ee49399 ML |
13831 | |
13832 | /* prepare_fb aborted? */ | |
13833 | if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) || | |
13834 | (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit))) | |
13835 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); | |
7580d774 ML |
13836 | |
13837 | i915_gem_request_assign(&old_intel_state->wait_req, NULL); | |
465c120c MR |
13838 | } |
13839 | ||
6156a456 CK |
13840 | int |
13841 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
13842 | { | |
13843 | int max_scale; | |
13844 | struct drm_device *dev; | |
13845 | struct drm_i915_private *dev_priv; | |
13846 | int crtc_clock, cdclk; | |
13847 | ||
bf8a0af0 | 13848 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
13849 | return DRM_PLANE_HELPER_NO_SCALING; |
13850 | ||
13851 | dev = intel_crtc->base.dev; | |
13852 | dev_priv = dev->dev_private; | |
13853 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; | |
27c329ed | 13854 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 | 13855 | |
54bf1ce6 | 13856 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
6156a456 CK |
13857 | return DRM_PLANE_HELPER_NO_SCALING; |
13858 | ||
13859 | /* | |
13860 | * skl max scale is lower of: | |
13861 | * close to 3 but not 3, -1 is for that purpose | |
13862 | * or | |
13863 | * cdclk/crtc_clock | |
13864 | */ | |
13865 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
13866 | ||
13867 | return max_scale; | |
13868 | } | |
13869 | ||
465c120c | 13870 | static int |
3c692a41 | 13871 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 13872 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
13873 | struct intel_plane_state *state) |
13874 | { | |
2b875c22 MR |
13875 | struct drm_crtc *crtc = state->base.crtc; |
13876 | struct drm_framebuffer *fb = state->base.fb; | |
6156a456 | 13877 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
13878 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
13879 | bool can_position = false; | |
465c120c | 13880 | |
693bdc28 VS |
13881 | if (INTEL_INFO(plane->dev)->gen >= 9) { |
13882 | /* use scaler when colorkey is not required */ | |
13883 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
13884 | min_scale = 1; | |
13885 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
13886 | } | |
d8106366 | 13887 | can_position = true; |
6156a456 | 13888 | } |
d8106366 | 13889 | |
061e4b8d ML |
13890 | return drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
13891 | &state->dst, &state->clip, | |
da20eabd ML |
13892 | min_scale, max_scale, |
13893 | can_position, true, | |
13894 | &state->visible); | |
14af293f GP |
13895 | } |
13896 | ||
613d2b27 ML |
13897 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
13898 | struct drm_crtc_state *old_crtc_state) | |
3c692a41 | 13899 | { |
32b7eeec | 13900 | struct drm_device *dev = crtc->dev; |
3c692a41 | 13901 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
bfd16b2a ML |
13902 | struct intel_crtc_state *old_intel_state = |
13903 | to_intel_crtc_state(old_crtc_state); | |
13904 | bool modeset = needs_modeset(crtc->state); | |
3c692a41 | 13905 | |
c34c9ee4 | 13906 | /* Perform vblank evasion around commit operation */ |
62852622 | 13907 | intel_pipe_update_start(intel_crtc); |
0583236e | 13908 | |
bfd16b2a ML |
13909 | if (modeset) |
13910 | return; | |
13911 | ||
20a34e78 ML |
13912 | if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) { |
13913 | intel_color_set_csc(crtc->state); | |
13914 | intel_color_load_luts(crtc->state); | |
13915 | } | |
13916 | ||
bfd16b2a ML |
13917 | if (to_intel_crtc_state(crtc->state)->update_pipe) |
13918 | intel_update_pipe_config(intel_crtc, old_intel_state); | |
13919 | else if (INTEL_INFO(dev)->gen >= 9) | |
0583236e | 13920 | skl_detach_scalers(intel_crtc); |
32b7eeec MR |
13921 | } |
13922 | ||
613d2b27 ML |
13923 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, |
13924 | struct drm_crtc_state *old_crtc_state) | |
32b7eeec | 13925 | { |
32b7eeec | 13926 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
32b7eeec | 13927 | |
62852622 | 13928 | intel_pipe_update_end(intel_crtc); |
3c692a41 GP |
13929 | } |
13930 | ||
cf4c7c12 | 13931 | /** |
4a3b8769 MR |
13932 | * intel_plane_destroy - destroy a plane |
13933 | * @plane: plane to destroy | |
cf4c7c12 | 13934 | * |
4a3b8769 MR |
13935 | * Common destruction function for all types of planes (primary, cursor, |
13936 | * sprite). | |
cf4c7c12 | 13937 | */ |
4a3b8769 | 13938 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
13939 | { |
13940 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13941 | drm_plane_cleanup(plane); | |
13942 | kfree(intel_plane); | |
13943 | } | |
13944 | ||
65a3fea0 | 13945 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
13946 | .update_plane = drm_atomic_helper_update_plane, |
13947 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 13948 | .destroy = intel_plane_destroy, |
c196e1d6 | 13949 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
13950 | .atomic_get_property = intel_plane_atomic_get_property, |
13951 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
13952 | .atomic_duplicate_state = intel_plane_duplicate_state, |
13953 | .atomic_destroy_state = intel_plane_destroy_state, | |
13954 | ||
465c120c MR |
13955 | }; |
13956 | ||
13957 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
13958 | int pipe) | |
13959 | { | |
fca0ce2a VS |
13960 | struct intel_plane *primary = NULL; |
13961 | struct intel_plane_state *state = NULL; | |
465c120c | 13962 | const uint32_t *intel_primary_formats; |
45e3743a | 13963 | unsigned int num_formats; |
fca0ce2a | 13964 | int ret; |
465c120c MR |
13965 | |
13966 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
fca0ce2a VS |
13967 | if (!primary) |
13968 | goto fail; | |
465c120c | 13969 | |
8e7d688b | 13970 | state = intel_create_plane_state(&primary->base); |
fca0ce2a VS |
13971 | if (!state) |
13972 | goto fail; | |
8e7d688b | 13973 | primary->base.state = &state->base; |
ea2c67bb | 13974 | |
465c120c MR |
13975 | primary->can_scale = false; |
13976 | primary->max_downscale = 1; | |
6156a456 CK |
13977 | if (INTEL_INFO(dev)->gen >= 9) { |
13978 | primary->can_scale = true; | |
af99ceda | 13979 | state->scaler_id = -1; |
6156a456 | 13980 | } |
465c120c MR |
13981 | primary->pipe = pipe; |
13982 | primary->plane = pipe; | |
a9ff8714 | 13983 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 13984 | primary->check_plane = intel_check_primary_plane; |
465c120c MR |
13985 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
13986 | primary->plane = !pipe; | |
13987 | ||
6c0fd451 DL |
13988 | if (INTEL_INFO(dev)->gen >= 9) { |
13989 | intel_primary_formats = skl_primary_formats; | |
13990 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
a8d201af ML |
13991 | |
13992 | primary->update_plane = skylake_update_primary_plane; | |
13993 | primary->disable_plane = skylake_disable_primary_plane; | |
13994 | } else if (HAS_PCH_SPLIT(dev)) { | |
13995 | intel_primary_formats = i965_primary_formats; | |
13996 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
13997 | ||
13998 | primary->update_plane = ironlake_update_primary_plane; | |
13999 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 | 14000 | } else if (INTEL_INFO(dev)->gen >= 4) { |
568db4f2 DL |
14001 | intel_primary_formats = i965_primary_formats; |
14002 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
a8d201af ML |
14003 | |
14004 | primary->update_plane = i9xx_update_primary_plane; | |
14005 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
14006 | } else { |
14007 | intel_primary_formats = i8xx_primary_formats; | |
14008 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
a8d201af ML |
14009 | |
14010 | primary->update_plane = i9xx_update_primary_plane; | |
14011 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
14012 | } |
14013 | ||
fca0ce2a VS |
14014 | ret = drm_universal_plane_init(dev, &primary->base, 0, |
14015 | &intel_plane_funcs, | |
14016 | intel_primary_formats, num_formats, | |
14017 | DRM_PLANE_TYPE_PRIMARY, NULL); | |
14018 | if (ret) | |
14019 | goto fail; | |
48404c1e | 14020 | |
3b7a5119 SJ |
14021 | if (INTEL_INFO(dev)->gen >= 4) |
14022 | intel_create_rotation_property(dev, primary); | |
48404c1e | 14023 | |
ea2c67bb MR |
14024 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
14025 | ||
465c120c | 14026 | return &primary->base; |
fca0ce2a VS |
14027 | |
14028 | fail: | |
14029 | kfree(state); | |
14030 | kfree(primary); | |
14031 | ||
14032 | return NULL; | |
465c120c MR |
14033 | } |
14034 | ||
3b7a5119 SJ |
14035 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
14036 | { | |
14037 | if (!dev->mode_config.rotation_property) { | |
14038 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
14039 | BIT(DRM_ROTATE_180); | |
14040 | ||
14041 | if (INTEL_INFO(dev)->gen >= 9) | |
14042 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
14043 | ||
14044 | dev->mode_config.rotation_property = | |
14045 | drm_mode_create_rotation_property(dev, flags); | |
14046 | } | |
14047 | if (dev->mode_config.rotation_property) | |
14048 | drm_object_attach_property(&plane->base.base, | |
14049 | dev->mode_config.rotation_property, | |
14050 | plane->base.state->rotation); | |
14051 | } | |
14052 | ||
3d7d6510 | 14053 | static int |
852e787c | 14054 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 14055 | struct intel_crtc_state *crtc_state, |
852e787c | 14056 | struct intel_plane_state *state) |
3d7d6510 | 14057 | { |
061e4b8d | 14058 | struct drm_crtc *crtc = crtc_state->base.crtc; |
2b875c22 | 14059 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 14060 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
b29ec92c | 14061 | enum pipe pipe = to_intel_plane(plane)->pipe; |
757f9a3e GP |
14062 | unsigned stride; |
14063 | int ret; | |
3d7d6510 | 14064 | |
061e4b8d ML |
14065 | ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
14066 | &state->dst, &state->clip, | |
3d7d6510 MR |
14067 | DRM_PLANE_HELPER_NO_SCALING, |
14068 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 14069 | true, true, &state->visible); |
757f9a3e GP |
14070 | if (ret) |
14071 | return ret; | |
14072 | ||
757f9a3e GP |
14073 | /* if we want to turn off the cursor ignore width and height */ |
14074 | if (!obj) | |
da20eabd | 14075 | return 0; |
757f9a3e | 14076 | |
757f9a3e | 14077 | /* Check for which cursor types we support */ |
061e4b8d | 14078 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
ea2c67bb MR |
14079 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
14080 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
14081 | return -EINVAL; |
14082 | } | |
14083 | ||
ea2c67bb MR |
14084 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
14085 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
14086 | DRM_DEBUG_KMS("buffer is too small\n"); |
14087 | return -ENOMEM; | |
14088 | } | |
14089 | ||
3a656b54 | 14090 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 14091 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 14092 | return -EINVAL; |
32b7eeec MR |
14093 | } |
14094 | ||
b29ec92c VS |
14095 | /* |
14096 | * There's something wrong with the cursor on CHV pipe C. | |
14097 | * If it straddles the left edge of the screen then | |
14098 | * moving it away from the edge or disabling it often | |
14099 | * results in a pipe underrun, and often that can lead to | |
14100 | * dead pipe (constant underrun reported, and it scans | |
14101 | * out just a solid color). To recover from that, the | |
14102 | * display power well must be turned off and on again. | |
14103 | * Refuse the put the cursor into that compromised position. | |
14104 | */ | |
14105 | if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C && | |
14106 | state->visible && state->base.crtc_x < 0) { | |
14107 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); | |
14108 | return -EINVAL; | |
14109 | } | |
14110 | ||
da20eabd | 14111 | return 0; |
852e787c | 14112 | } |
3d7d6510 | 14113 | |
a8ad0d8e ML |
14114 | static void |
14115 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 14116 | struct drm_crtc *crtc) |
a8ad0d8e | 14117 | { |
f2858021 ML |
14118 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
14119 | ||
14120 | intel_crtc->cursor_addr = 0; | |
55a08b3f | 14121 | intel_crtc_update_cursor(crtc, NULL); |
a8ad0d8e ML |
14122 | } |
14123 | ||
f4a2cf29 | 14124 | static void |
55a08b3f ML |
14125 | intel_update_cursor_plane(struct drm_plane *plane, |
14126 | const struct intel_crtc_state *crtc_state, | |
14127 | const struct intel_plane_state *state) | |
852e787c | 14128 | { |
55a08b3f ML |
14129 | struct drm_crtc *crtc = crtc_state->base.crtc; |
14130 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ea2c67bb | 14131 | struct drm_device *dev = plane->dev; |
2b875c22 | 14132 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 14133 | uint32_t addr; |
852e787c | 14134 | |
f4a2cf29 | 14135 | if (!obj) |
a912f12f | 14136 | addr = 0; |
f4a2cf29 | 14137 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 14138 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 14139 | else |
a912f12f | 14140 | addr = obj->phys_handle->busaddr; |
852e787c | 14141 | |
a912f12f | 14142 | intel_crtc->cursor_addr = addr; |
55a08b3f | 14143 | intel_crtc_update_cursor(crtc, state); |
852e787c GP |
14144 | } |
14145 | ||
3d7d6510 MR |
14146 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
14147 | int pipe) | |
14148 | { | |
fca0ce2a VS |
14149 | struct intel_plane *cursor = NULL; |
14150 | struct intel_plane_state *state = NULL; | |
14151 | int ret; | |
3d7d6510 MR |
14152 | |
14153 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
fca0ce2a VS |
14154 | if (!cursor) |
14155 | goto fail; | |
3d7d6510 | 14156 | |
8e7d688b | 14157 | state = intel_create_plane_state(&cursor->base); |
fca0ce2a VS |
14158 | if (!state) |
14159 | goto fail; | |
8e7d688b | 14160 | cursor->base.state = &state->base; |
ea2c67bb | 14161 | |
3d7d6510 MR |
14162 | cursor->can_scale = false; |
14163 | cursor->max_downscale = 1; | |
14164 | cursor->pipe = pipe; | |
14165 | cursor->plane = pipe; | |
a9ff8714 | 14166 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 | 14167 | cursor->check_plane = intel_check_cursor_plane; |
55a08b3f | 14168 | cursor->update_plane = intel_update_cursor_plane; |
a8ad0d8e | 14169 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 | 14170 | |
fca0ce2a VS |
14171 | ret = drm_universal_plane_init(dev, &cursor->base, 0, |
14172 | &intel_plane_funcs, | |
14173 | intel_cursor_formats, | |
14174 | ARRAY_SIZE(intel_cursor_formats), | |
14175 | DRM_PLANE_TYPE_CURSOR, NULL); | |
14176 | if (ret) | |
14177 | goto fail; | |
4398ad45 VS |
14178 | |
14179 | if (INTEL_INFO(dev)->gen >= 4) { | |
14180 | if (!dev->mode_config.rotation_property) | |
14181 | dev->mode_config.rotation_property = | |
14182 | drm_mode_create_rotation_property(dev, | |
14183 | BIT(DRM_ROTATE_0) | | |
14184 | BIT(DRM_ROTATE_180)); | |
14185 | if (dev->mode_config.rotation_property) | |
14186 | drm_object_attach_property(&cursor->base.base, | |
14187 | dev->mode_config.rotation_property, | |
8e7d688b | 14188 | state->base.rotation); |
4398ad45 VS |
14189 | } |
14190 | ||
af99ceda CK |
14191 | if (INTEL_INFO(dev)->gen >=9) |
14192 | state->scaler_id = -1; | |
14193 | ||
ea2c67bb MR |
14194 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
14195 | ||
3d7d6510 | 14196 | return &cursor->base; |
fca0ce2a VS |
14197 | |
14198 | fail: | |
14199 | kfree(state); | |
14200 | kfree(cursor); | |
14201 | ||
14202 | return NULL; | |
3d7d6510 MR |
14203 | } |
14204 | ||
549e2bfb CK |
14205 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
14206 | struct intel_crtc_state *crtc_state) | |
14207 | { | |
14208 | int i; | |
14209 | struct intel_scaler *intel_scaler; | |
14210 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
14211 | ||
14212 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
14213 | intel_scaler = &scaler_state->scalers[i]; | |
14214 | intel_scaler->in_use = 0; | |
549e2bfb CK |
14215 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
14216 | } | |
14217 | ||
14218 | scaler_state->scaler_id = -1; | |
14219 | } | |
14220 | ||
b358d0a6 | 14221 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 14222 | { |
fbee40df | 14223 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 14224 | struct intel_crtc *intel_crtc; |
f5de6e07 | 14225 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
14226 | struct drm_plane *primary = NULL; |
14227 | struct drm_plane *cursor = NULL; | |
8563b1e8 | 14228 | int ret; |
79e53945 | 14229 | |
955382f3 | 14230 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
14231 | if (intel_crtc == NULL) |
14232 | return; | |
14233 | ||
f5de6e07 ACO |
14234 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
14235 | if (!crtc_state) | |
14236 | goto fail; | |
550acefd ACO |
14237 | intel_crtc->config = crtc_state; |
14238 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 14239 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 14240 | |
549e2bfb CK |
14241 | /* initialize shared scalers */ |
14242 | if (INTEL_INFO(dev)->gen >= 9) { | |
14243 | if (pipe == PIPE_C) | |
14244 | intel_crtc->num_scalers = 1; | |
14245 | else | |
14246 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
14247 | ||
14248 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
14249 | } | |
14250 | ||
465c120c | 14251 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
14252 | if (!primary) |
14253 | goto fail; | |
14254 | ||
14255 | cursor = intel_cursor_plane_create(dev, pipe); | |
14256 | if (!cursor) | |
14257 | goto fail; | |
14258 | ||
465c120c | 14259 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
f9882876 | 14260 | cursor, &intel_crtc_funcs, NULL); |
3d7d6510 MR |
14261 | if (ret) |
14262 | goto fail; | |
79e53945 | 14263 | |
1f1c2e24 VS |
14264 | /* |
14265 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 14266 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 14267 | */ |
80824003 JB |
14268 | intel_crtc->pipe = pipe; |
14269 | intel_crtc->plane = pipe; | |
3a77c4c4 | 14270 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 14271 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 14272 | intel_crtc->plane = !pipe; |
80824003 JB |
14273 | } |
14274 | ||
4b0e333e CW |
14275 | intel_crtc->cursor_base = ~0; |
14276 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 14277 | intel_crtc->cursor_size = ~0; |
8d7849db | 14278 | |
852eb00d VS |
14279 | intel_crtc->wm.cxsr_allowed = true; |
14280 | ||
22fd0fab JB |
14281 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
14282 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
14283 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
14284 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
14285 | ||
79e53945 | 14286 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 | 14287 | |
8563b1e8 LL |
14288 | intel_color_init(&intel_crtc->base); |
14289 | ||
87b6b101 | 14290 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); |
3d7d6510 MR |
14291 | return; |
14292 | ||
14293 | fail: | |
14294 | if (primary) | |
14295 | drm_plane_cleanup(primary); | |
14296 | if (cursor) | |
14297 | drm_plane_cleanup(cursor); | |
f5de6e07 | 14298 | kfree(crtc_state); |
3d7d6510 | 14299 | kfree(intel_crtc); |
79e53945 JB |
14300 | } |
14301 | ||
752aa88a JB |
14302 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
14303 | { | |
14304 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 14305 | struct drm_device *dev = connector->base.dev; |
752aa88a | 14306 | |
51fd371b | 14307 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 14308 | |
d3babd3f | 14309 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
14310 | return INVALID_PIPE; |
14311 | ||
14312 | return to_intel_crtc(encoder->crtc)->pipe; | |
14313 | } | |
14314 | ||
08d7b3d1 | 14315 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 14316 | struct drm_file *file) |
08d7b3d1 | 14317 | { |
08d7b3d1 | 14318 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 14319 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 14320 | struct intel_crtc *crtc; |
08d7b3d1 | 14321 | |
7707e653 | 14322 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 14323 | |
7707e653 | 14324 | if (!drmmode_crtc) { |
08d7b3d1 | 14325 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 14326 | return -ENOENT; |
08d7b3d1 CW |
14327 | } |
14328 | ||
7707e653 | 14329 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 14330 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 14331 | |
c05422d5 | 14332 | return 0; |
08d7b3d1 CW |
14333 | } |
14334 | ||
66a9278e | 14335 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 14336 | { |
66a9278e DV |
14337 | struct drm_device *dev = encoder->base.dev; |
14338 | struct intel_encoder *source_encoder; | |
79e53945 | 14339 | int index_mask = 0; |
79e53945 JB |
14340 | int entry = 0; |
14341 | ||
b2784e15 | 14342 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 14343 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
14344 | index_mask |= (1 << entry); |
14345 | ||
79e53945 JB |
14346 | entry++; |
14347 | } | |
4ef69c7a | 14348 | |
79e53945 JB |
14349 | return index_mask; |
14350 | } | |
14351 | ||
4d302442 CW |
14352 | static bool has_edp_a(struct drm_device *dev) |
14353 | { | |
14354 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14355 | ||
14356 | if (!IS_MOBILE(dev)) | |
14357 | return false; | |
14358 | ||
14359 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
14360 | return false; | |
14361 | ||
e3589908 | 14362 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
14363 | return false; |
14364 | ||
14365 | return true; | |
14366 | } | |
14367 | ||
84b4e042 JB |
14368 | static bool intel_crt_present(struct drm_device *dev) |
14369 | { | |
14370 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14371 | ||
884497ed DL |
14372 | if (INTEL_INFO(dev)->gen >= 9) |
14373 | return false; | |
14374 | ||
cf404ce4 | 14375 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
14376 | return false; |
14377 | ||
14378 | if (IS_CHERRYVIEW(dev)) | |
14379 | return false; | |
14380 | ||
65e472e4 VS |
14381 | if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) |
14382 | return false; | |
14383 | ||
70ac54d0 VS |
14384 | /* DDI E can't be used if DDI A requires 4 lanes */ |
14385 | if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) | |
14386 | return false; | |
14387 | ||
e4abb733 | 14388 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
14389 | return false; |
14390 | ||
14391 | return true; | |
14392 | } | |
14393 | ||
79e53945 JB |
14394 | static void intel_setup_outputs(struct drm_device *dev) |
14395 | { | |
725e30ad | 14396 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 14397 | struct intel_encoder *encoder; |
cb0953d7 | 14398 | bool dpd_is_edp = false; |
79e53945 | 14399 | |
c9093354 | 14400 | intel_lvds_init(dev); |
79e53945 | 14401 | |
84b4e042 | 14402 | if (intel_crt_present(dev)) |
79935fca | 14403 | intel_crt_init(dev); |
cb0953d7 | 14404 | |
c776eb2e VK |
14405 | if (IS_BROXTON(dev)) { |
14406 | /* | |
14407 | * FIXME: Broxton doesn't support port detection via the | |
14408 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14409 | * detect the ports. | |
14410 | */ | |
14411 | intel_ddi_init(dev, PORT_A); | |
14412 | intel_ddi_init(dev, PORT_B); | |
14413 | intel_ddi_init(dev, PORT_C); | |
c6c794a2 SS |
14414 | |
14415 | intel_dsi_init(dev); | |
c776eb2e | 14416 | } else if (HAS_DDI(dev)) { |
0e72a5b5 ED |
14417 | int found; |
14418 | ||
de31facd JB |
14419 | /* |
14420 | * Haswell uses DDI functions to detect digital outputs. | |
14421 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14422 | * it's there. | |
14423 | */ | |
77179400 | 14424 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 14425 | /* WaIgnoreDDIAStrap: skl */ |
ef11bdb3 | 14426 | if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
0e72a5b5 ED |
14427 | intel_ddi_init(dev, PORT_A); |
14428 | ||
14429 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14430 | * register */ | |
14431 | found = I915_READ(SFUSE_STRAP); | |
14432 | ||
14433 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
14434 | intel_ddi_init(dev, PORT_B); | |
14435 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
14436 | intel_ddi_init(dev, PORT_C); | |
14437 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
14438 | intel_ddi_init(dev, PORT_D); | |
2800e4c2 RV |
14439 | /* |
14440 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
14441 | */ | |
ef11bdb3 | 14442 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && |
2800e4c2 RV |
14443 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
14444 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
14445 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
14446 | intel_ddi_init(dev, PORT_E); | |
14447 | ||
0e72a5b5 | 14448 | } else if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 14449 | int found; |
5d8a7752 | 14450 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
14451 | |
14452 | if (has_edp_a(dev)) | |
14453 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 14454 | |
dc0fa718 | 14455 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14456 | /* PCH SDVOB multiplex with HDMIB */ |
2a5c0832 | 14457 | found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); |
30ad48b7 | 14458 | if (!found) |
e2debe91 | 14459 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 14460 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 14461 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14462 | } |
14463 | ||
dc0fa718 | 14464 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 14465 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 14466 | |
dc0fa718 | 14467 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 14468 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 14469 | |
5eb08b69 | 14470 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 14471 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 14472 | |
270b3042 | 14473 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 14474 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
666a4537 | 14475 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
e17ac6db VS |
14476 | /* |
14477 | * The DP_DETECTED bit is the latched state of the DDC | |
14478 | * SDA pin at boot. However since eDP doesn't require DDC | |
14479 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14480 | * eDP ports may have been muxed to an alternate function. | |
14481 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14482 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14483 | * detect eDP ports. | |
14484 | */ | |
e66eb81d | 14485 | if (I915_READ(VLV_HDMIB) & SDVO_DETECTED && |
d2182a66 | 14486 | !intel_dp_is_edp(dev, PORT_B)) |
e66eb81d VS |
14487 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
14488 | if (I915_READ(VLV_DP_B) & DP_DETECTED || | |
e17ac6db | 14489 | intel_dp_is_edp(dev, PORT_B)) |
e66eb81d | 14490 | intel_dp_init(dev, VLV_DP_B, PORT_B); |
585a94b8 | 14491 | |
e66eb81d | 14492 | if (I915_READ(VLV_HDMIC) & SDVO_DETECTED && |
d2182a66 | 14493 | !intel_dp_is_edp(dev, PORT_C)) |
e66eb81d VS |
14494 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
14495 | if (I915_READ(VLV_DP_C) & DP_DETECTED || | |
e17ac6db | 14496 | intel_dp_is_edp(dev, PORT_C)) |
e66eb81d | 14497 | intel_dp_init(dev, VLV_DP_C, PORT_C); |
19c03924 | 14498 | |
9418c1f1 | 14499 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 14500 | /* eDP not supported on port D, so don't check VBT */ |
e66eb81d VS |
14501 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED) |
14502 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); | |
14503 | if (I915_READ(CHV_DP_D) & DP_DETECTED) | |
14504 | intel_dp_init(dev, CHV_DP_D, PORT_D); | |
9418c1f1 VS |
14505 | } |
14506 | ||
3cfca973 | 14507 | intel_dsi_init(dev); |
09da55dc | 14508 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
27185ae1 | 14509 | bool found = false; |
7d57382e | 14510 | |
e2debe91 | 14511 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14512 | DRM_DEBUG_KMS("probing SDVOB\n"); |
2a5c0832 | 14513 | found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B); |
3fec3d2f | 14514 | if (!found && IS_G4X(dev)) { |
b01f2c3a | 14515 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
e2debe91 | 14516 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14517 | } |
27185ae1 | 14518 | |
3fec3d2f | 14519 | if (!found && IS_G4X(dev)) |
ab9d7c30 | 14520 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 14521 | } |
13520b05 KH |
14522 | |
14523 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14524 | |
e2debe91 | 14525 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14526 | DRM_DEBUG_KMS("probing SDVOC\n"); |
2a5c0832 | 14527 | found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); |
b01f2c3a | 14528 | } |
27185ae1 | 14529 | |
e2debe91 | 14530 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14531 | |
3fec3d2f | 14532 | if (IS_G4X(dev)) { |
b01f2c3a | 14533 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
e2debe91 | 14534 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14535 | } |
3fec3d2f | 14536 | if (IS_G4X(dev)) |
ab9d7c30 | 14537 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 14538 | } |
27185ae1 | 14539 | |
3fec3d2f | 14540 | if (IS_G4X(dev) && |
e7281eab | 14541 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 14542 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 14543 | } else if (IS_GEN2(dev)) |
79e53945 JB |
14544 | intel_dvo_init(dev); |
14545 | ||
103a196f | 14546 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
14547 | intel_tv_init(dev); |
14548 | ||
0bc12bcb | 14549 | intel_psr_init(dev); |
7c8f8a70 | 14550 | |
b2784e15 | 14551 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
14552 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14553 | encoder->base.possible_clones = | |
66a9278e | 14554 | intel_encoder_clones(encoder); |
79e53945 | 14555 | } |
47356eb6 | 14556 | |
dde86e2d | 14557 | intel_init_pch_refclk(dev); |
270b3042 DV |
14558 | |
14559 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
14560 | } |
14561 | ||
14562 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14563 | { | |
60a5ca01 | 14564 | struct drm_device *dev = fb->dev; |
79e53945 | 14565 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 14566 | |
ef2d633e | 14567 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 14568 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 14569 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
14570 | drm_gem_object_unreference(&intel_fb->obj->base); |
14571 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14572 | kfree(intel_fb); |
14573 | } | |
14574 | ||
14575 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14576 | struct drm_file *file, |
79e53945 JB |
14577 | unsigned int *handle) |
14578 | { | |
14579 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14580 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14581 | |
cc917ab4 CW |
14582 | if (obj->userptr.mm) { |
14583 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
14584 | return -EINVAL; | |
14585 | } | |
14586 | ||
05394f39 | 14587 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14588 | } |
14589 | ||
86c98588 RV |
14590 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
14591 | struct drm_file *file, | |
14592 | unsigned flags, unsigned color, | |
14593 | struct drm_clip_rect *clips, | |
14594 | unsigned num_clips) | |
14595 | { | |
14596 | struct drm_device *dev = fb->dev; | |
14597 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
14598 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
14599 | ||
14600 | mutex_lock(&dev->struct_mutex); | |
74b4ea1e | 14601 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
14602 | mutex_unlock(&dev->struct_mutex); |
14603 | ||
14604 | return 0; | |
14605 | } | |
14606 | ||
79e53945 JB |
14607 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
14608 | .destroy = intel_user_framebuffer_destroy, | |
14609 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 14610 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
14611 | }; |
14612 | ||
b321803d DL |
14613 | static |
14614 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
14615 | uint32_t pixel_format) | |
14616 | { | |
14617 | u32 gen = INTEL_INFO(dev)->gen; | |
14618 | ||
14619 | if (gen >= 9) { | |
ac484963 VS |
14620 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
14621 | ||
b321803d DL |
14622 | /* "The stride in bytes must not exceed the of the size of 8K |
14623 | * pixels and 32K bytes." | |
14624 | */ | |
ac484963 | 14625 | return min(8192 * cpp, 32768); |
666a4537 | 14626 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
b321803d DL |
14627 | return 32*1024; |
14628 | } else if (gen >= 4) { | |
14629 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14630 | return 16*1024; | |
14631 | else | |
14632 | return 32*1024; | |
14633 | } else if (gen >= 3) { | |
14634 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14635 | return 8*1024; | |
14636 | else | |
14637 | return 16*1024; | |
14638 | } else { | |
14639 | /* XXX DSPC is limited to 4k tiled */ | |
14640 | return 8*1024; | |
14641 | } | |
14642 | } | |
14643 | ||
b5ea642a DV |
14644 | static int intel_framebuffer_init(struct drm_device *dev, |
14645 | struct intel_framebuffer *intel_fb, | |
14646 | struct drm_mode_fb_cmd2 *mode_cmd, | |
14647 | struct drm_i915_gem_object *obj) | |
79e53945 | 14648 | { |
7b49f948 | 14649 | struct drm_i915_private *dev_priv = to_i915(dev); |
6761dd31 | 14650 | unsigned int aligned_height; |
79e53945 | 14651 | int ret; |
b321803d | 14652 | u32 pitch_limit, stride_alignment; |
79e53945 | 14653 | |
dd4916c5 DV |
14654 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
14655 | ||
2a80eada DV |
14656 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
14657 | /* Enforce that fb modifier and tiling mode match, but only for | |
14658 | * X-tiled. This is needed for FBC. */ | |
14659 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
14660 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
14661 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
14662 | return -EINVAL; | |
14663 | } | |
14664 | } else { | |
14665 | if (obj->tiling_mode == I915_TILING_X) | |
14666 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
14667 | else if (obj->tiling_mode == I915_TILING_Y) { | |
14668 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
14669 | return -EINVAL; | |
14670 | } | |
14671 | } | |
14672 | ||
9a8f0a12 TU |
14673 | /* Passed in modifier sanity checking. */ |
14674 | switch (mode_cmd->modifier[0]) { | |
14675 | case I915_FORMAT_MOD_Y_TILED: | |
14676 | case I915_FORMAT_MOD_Yf_TILED: | |
14677 | if (INTEL_INFO(dev)->gen < 9) { | |
14678 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
14679 | mode_cmd->modifier[0]); | |
14680 | return -EINVAL; | |
14681 | } | |
14682 | case DRM_FORMAT_MOD_NONE: | |
14683 | case I915_FORMAT_MOD_X_TILED: | |
14684 | break; | |
14685 | default: | |
c0f40428 JB |
14686 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14687 | mode_cmd->modifier[0]); | |
57cd6508 | 14688 | return -EINVAL; |
c16ed4be | 14689 | } |
57cd6508 | 14690 | |
7b49f948 VS |
14691 | stride_alignment = intel_fb_stride_alignment(dev_priv, |
14692 | mode_cmd->modifier[0], | |
b321803d DL |
14693 | mode_cmd->pixel_format); |
14694 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
14695 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
14696 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 14697 | return -EINVAL; |
c16ed4be | 14698 | } |
57cd6508 | 14699 | |
b321803d DL |
14700 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
14701 | mode_cmd->pixel_format); | |
a35cdaa0 | 14702 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
14703 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
14704 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 14705 | "tiled" : "linear", |
a35cdaa0 | 14706 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 14707 | return -EINVAL; |
c16ed4be | 14708 | } |
5d7bd705 | 14709 | |
2a80eada | 14710 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
14711 | mode_cmd->pitches[0] != obj->stride) { |
14712 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
14713 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 14714 | return -EINVAL; |
c16ed4be | 14715 | } |
5d7bd705 | 14716 | |
57779d06 | 14717 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14718 | switch (mode_cmd->pixel_format) { |
57779d06 | 14719 | case DRM_FORMAT_C8: |
04b3924d VS |
14720 | case DRM_FORMAT_RGB565: |
14721 | case DRM_FORMAT_XRGB8888: | |
14722 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14723 | break; |
14724 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 14725 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
14726 | DRM_DEBUG("unsupported pixel format: %s\n", |
14727 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14728 | return -EINVAL; |
c16ed4be | 14729 | } |
57779d06 | 14730 | break; |
57779d06 | 14731 | case DRM_FORMAT_ABGR8888: |
666a4537 WB |
14732 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
14733 | INTEL_INFO(dev)->gen < 9) { | |
6c0fd451 DL |
14734 | DRM_DEBUG("unsupported pixel format: %s\n", |
14735 | drm_get_format_name(mode_cmd->pixel_format)); | |
14736 | return -EINVAL; | |
14737 | } | |
14738 | break; | |
14739 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 14740 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 14741 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 14742 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
14743 | DRM_DEBUG("unsupported pixel format: %s\n", |
14744 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14745 | return -EINVAL; |
c16ed4be | 14746 | } |
b5626747 | 14747 | break; |
7531208b | 14748 | case DRM_FORMAT_ABGR2101010: |
666a4537 | 14749 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
7531208b DL |
14750 | DRM_DEBUG("unsupported pixel format: %s\n", |
14751 | drm_get_format_name(mode_cmd->pixel_format)); | |
14752 | return -EINVAL; | |
14753 | } | |
14754 | break; | |
04b3924d VS |
14755 | case DRM_FORMAT_YUYV: |
14756 | case DRM_FORMAT_UYVY: | |
14757 | case DRM_FORMAT_YVYU: | |
14758 | case DRM_FORMAT_VYUY: | |
c16ed4be | 14759 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
14760 | DRM_DEBUG("unsupported pixel format: %s\n", |
14761 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14762 | return -EINVAL; |
c16ed4be | 14763 | } |
57cd6508 CW |
14764 | break; |
14765 | default: | |
4ee62c76 VS |
14766 | DRM_DEBUG("unsupported pixel format: %s\n", |
14767 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
14768 | return -EINVAL; |
14769 | } | |
14770 | ||
90f9a336 VS |
14771 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14772 | if (mode_cmd->offsets[0] != 0) | |
14773 | return -EINVAL; | |
14774 | ||
ec2c981e | 14775 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
14776 | mode_cmd->pixel_format, |
14777 | mode_cmd->modifier[0]); | |
53155c0a DV |
14778 | /* FIXME drm helper for size checks (especially planar formats)? */ |
14779 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
14780 | return -EINVAL; | |
14781 | ||
c7d73f6a DV |
14782 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
14783 | intel_fb->obj = obj; | |
14784 | ||
2d7a215f VS |
14785 | intel_fill_fb_info(dev_priv, &intel_fb->base); |
14786 | ||
79e53945 JB |
14787 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
14788 | if (ret) { | |
14789 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
14790 | return ret; | |
14791 | } | |
14792 | ||
0b05e1e0 VS |
14793 | intel_fb->obj->framebuffer_references++; |
14794 | ||
79e53945 JB |
14795 | return 0; |
14796 | } | |
14797 | ||
79e53945 JB |
14798 | static struct drm_framebuffer * |
14799 | intel_user_framebuffer_create(struct drm_device *dev, | |
14800 | struct drm_file *filp, | |
1eb83451 | 14801 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 14802 | { |
dcb1394e | 14803 | struct drm_framebuffer *fb; |
05394f39 | 14804 | struct drm_i915_gem_object *obj; |
76dc3769 | 14805 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 14806 | |
308e5bcb | 14807 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
76dc3769 | 14808 | mode_cmd.handles[0])); |
c8725226 | 14809 | if (&obj->base == NULL) |
cce13ff7 | 14810 | return ERR_PTR(-ENOENT); |
79e53945 | 14811 | |
92907cbb | 14812 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
dcb1394e LW |
14813 | if (IS_ERR(fb)) |
14814 | drm_gem_object_unreference_unlocked(&obj->base); | |
14815 | ||
14816 | return fb; | |
79e53945 JB |
14817 | } |
14818 | ||
0695726e | 14819 | #ifndef CONFIG_DRM_FBDEV_EMULATION |
0632fef6 | 14820 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
14821 | { |
14822 | } | |
14823 | #endif | |
14824 | ||
79e53945 | 14825 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14826 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14827 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14828 | .atomic_check = intel_atomic_check, |
14829 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
14830 | .atomic_state_alloc = intel_atomic_state_alloc, |
14831 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
14832 | }; |
14833 | ||
88212941 ID |
14834 | /** |
14835 | * intel_init_display_hooks - initialize the display modesetting hooks | |
14836 | * @dev_priv: device private | |
14837 | */ | |
14838 | void intel_init_display_hooks(struct drm_i915_private *dev_priv) | |
e70236a8 | 14839 | { |
88212941 | 14840 | if (INTEL_INFO(dev_priv)->gen >= 9) { |
bc8d7dff | 14841 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14842 | dev_priv->display.get_initial_plane_config = |
14843 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14844 | dev_priv->display.crtc_compute_clock = |
14845 | haswell_crtc_compute_clock; | |
14846 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14847 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 14848 | } else if (HAS_DDI(dev_priv)) { |
0e8ffe1b | 14849 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14850 | dev_priv->display.get_initial_plane_config = |
14851 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14852 | dev_priv->display.crtc_compute_clock = |
14853 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14854 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14855 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
88212941 | 14856 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
0e8ffe1b | 14857 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14858 | dev_priv->display.get_initial_plane_config = |
14859 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14860 | dev_priv->display.crtc_compute_clock = |
14861 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14862 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14863 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
65b3d6a9 | 14864 | } else if (IS_CHERRYVIEW(dev_priv)) { |
89b667f8 | 14865 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14866 | dev_priv->display.get_initial_plane_config = |
14867 | i9xx_get_initial_plane_config; | |
65b3d6a9 ACO |
14868 | dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; |
14869 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
14870 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
14871 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
14872 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14873 | dev_priv->display.get_initial_plane_config = | |
14874 | i9xx_get_initial_plane_config; | |
14875 | dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; | |
89b667f8 JB |
14876 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14877 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
19ec6693 ACO |
14878 | } else if (IS_G4X(dev_priv)) { |
14879 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14880 | dev_priv->display.get_initial_plane_config = | |
14881 | i9xx_get_initial_plane_config; | |
14882 | dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; | |
14883 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14884 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
70e8aa21 ACO |
14885 | } else if (IS_PINEVIEW(dev_priv)) { |
14886 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14887 | dev_priv->display.get_initial_plane_config = | |
14888 | i9xx_get_initial_plane_config; | |
14889 | dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; | |
14890 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14891 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 | 14892 | } else if (!IS_GEN2(dev_priv)) { |
0e8ffe1b | 14893 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14894 | dev_priv->display.get_initial_plane_config = |
14895 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14896 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14897 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14898 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
81c97f52 ACO |
14899 | } else { |
14900 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
14901 | dev_priv->display.get_initial_plane_config = | |
14902 | i9xx_get_initial_plane_config; | |
14903 | dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; | |
14904 | dev_priv->display.crtc_enable = i9xx_crtc_enable; | |
14905 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 14906 | } |
e70236a8 | 14907 | |
e70236a8 | 14908 | /* Returns the core display clock speed */ |
88212941 | 14909 | if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) |
1652d19e VS |
14910 | dev_priv->display.get_display_clock_speed = |
14911 | skylake_get_display_clock_speed; | |
88212941 | 14912 | else if (IS_BROXTON(dev_priv)) |
acd3f3d3 BP |
14913 | dev_priv->display.get_display_clock_speed = |
14914 | broxton_get_display_clock_speed; | |
88212941 | 14915 | else if (IS_BROADWELL(dev_priv)) |
1652d19e VS |
14916 | dev_priv->display.get_display_clock_speed = |
14917 | broadwell_get_display_clock_speed; | |
88212941 | 14918 | else if (IS_HASWELL(dev_priv)) |
1652d19e VS |
14919 | dev_priv->display.get_display_clock_speed = |
14920 | haswell_get_display_clock_speed; | |
88212941 | 14921 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
25eb05fc JB |
14922 | dev_priv->display.get_display_clock_speed = |
14923 | valleyview_get_display_clock_speed; | |
88212941 | 14924 | else if (IS_GEN5(dev_priv)) |
b37a6434 VS |
14925 | dev_priv->display.get_display_clock_speed = |
14926 | ilk_get_display_clock_speed; | |
88212941 ID |
14927 | else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) || |
14928 | IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv)) | |
e70236a8 JB |
14929 | dev_priv->display.get_display_clock_speed = |
14930 | i945_get_display_clock_speed; | |
88212941 | 14931 | else if (IS_GM45(dev_priv)) |
34edce2f VS |
14932 | dev_priv->display.get_display_clock_speed = |
14933 | gm45_get_display_clock_speed; | |
88212941 | 14934 | else if (IS_CRESTLINE(dev_priv)) |
34edce2f VS |
14935 | dev_priv->display.get_display_clock_speed = |
14936 | i965gm_get_display_clock_speed; | |
88212941 | 14937 | else if (IS_PINEVIEW(dev_priv)) |
34edce2f VS |
14938 | dev_priv->display.get_display_clock_speed = |
14939 | pnv_get_display_clock_speed; | |
88212941 | 14940 | else if (IS_G33(dev_priv) || IS_G4X(dev_priv)) |
34edce2f VS |
14941 | dev_priv->display.get_display_clock_speed = |
14942 | g33_get_display_clock_speed; | |
88212941 | 14943 | else if (IS_I915G(dev_priv)) |
e70236a8 JB |
14944 | dev_priv->display.get_display_clock_speed = |
14945 | i915_get_display_clock_speed; | |
88212941 | 14946 | else if (IS_I945GM(dev_priv) || IS_845G(dev_priv)) |
e70236a8 JB |
14947 | dev_priv->display.get_display_clock_speed = |
14948 | i9xx_misc_get_display_clock_speed; | |
88212941 | 14949 | else if (IS_I915GM(dev_priv)) |
e70236a8 JB |
14950 | dev_priv->display.get_display_clock_speed = |
14951 | i915gm_get_display_clock_speed; | |
88212941 | 14952 | else if (IS_I865G(dev_priv)) |
e70236a8 JB |
14953 | dev_priv->display.get_display_clock_speed = |
14954 | i865_get_display_clock_speed; | |
88212941 | 14955 | else if (IS_I85X(dev_priv)) |
e70236a8 | 14956 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 14957 | i85x_get_display_clock_speed; |
623e01e5 | 14958 | else { /* 830 */ |
88212941 | 14959 | WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n"); |
e70236a8 JB |
14960 | dev_priv->display.get_display_clock_speed = |
14961 | i830_get_display_clock_speed; | |
623e01e5 | 14962 | } |
e70236a8 | 14963 | |
88212941 | 14964 | if (IS_GEN5(dev_priv)) { |
3bb11b53 | 14965 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
88212941 | 14966 | } else if (IS_GEN6(dev_priv)) { |
3bb11b53 | 14967 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; |
88212941 | 14968 | } else if (IS_IVYBRIDGE(dev_priv)) { |
3bb11b53 SJ |
14969 | /* FIXME: detect B0+ stepping and use auto training */ |
14970 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
88212941 | 14971 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
3bb11b53 | 14972 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
445e780b VS |
14973 | } |
14974 | ||
14975 | if (IS_BROADWELL(dev_priv)) { | |
14976 | dev_priv->display.modeset_commit_cdclk = | |
14977 | broadwell_modeset_commit_cdclk; | |
14978 | dev_priv->display.modeset_calc_cdclk = | |
14979 | broadwell_modeset_calc_cdclk; | |
88212941 | 14980 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
27c329ed ML |
14981 | dev_priv->display.modeset_commit_cdclk = |
14982 | valleyview_modeset_commit_cdclk; | |
14983 | dev_priv->display.modeset_calc_cdclk = | |
14984 | valleyview_modeset_calc_cdclk; | |
88212941 | 14985 | } else if (IS_BROXTON(dev_priv)) { |
27c329ed ML |
14986 | dev_priv->display.modeset_commit_cdclk = |
14987 | broxton_modeset_commit_cdclk; | |
14988 | dev_priv->display.modeset_calc_cdclk = | |
14989 | broxton_modeset_calc_cdclk; | |
e70236a8 | 14990 | } |
8c9f3aaf | 14991 | |
88212941 | 14992 | switch (INTEL_INFO(dev_priv)->gen) { |
8c9f3aaf JB |
14993 | case 2: |
14994 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
14995 | break; | |
14996 | ||
14997 | case 3: | |
14998 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
14999 | break; | |
15000 | ||
15001 | case 4: | |
15002 | case 5: | |
15003 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
15004 | break; | |
15005 | ||
15006 | case 6: | |
15007 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
15008 | break; | |
7c9017e5 | 15009 | case 7: |
4e0bbc31 | 15010 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
15011 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
15012 | break; | |
830c81db | 15013 | case 9: |
ba343e02 TU |
15014 | /* Drop through - unsupported since execlist only. */ |
15015 | default: | |
15016 | /* Default just returns -ENODEV to indicate unsupported */ | |
15017 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 15018 | } |
e70236a8 JB |
15019 | } |
15020 | ||
b690e96c JB |
15021 | /* |
15022 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
15023 | * resume, or other times. This quirk makes sure that's the case for | |
15024 | * affected systems. | |
15025 | */ | |
0206e353 | 15026 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
15027 | { |
15028 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15029 | ||
15030 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 15031 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
15032 | } |
15033 | ||
b6b5d049 VS |
15034 | static void quirk_pipeb_force(struct drm_device *dev) |
15035 | { | |
15036 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15037 | ||
15038 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
15039 | DRM_INFO("applying pipe b force quirk\n"); | |
15040 | } | |
15041 | ||
435793df KP |
15042 | /* |
15043 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
15044 | */ | |
15045 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
15046 | { | |
15047 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15048 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 15049 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
15050 | } |
15051 | ||
4dca20ef | 15052 | /* |
5a15ab5b CE |
15053 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
15054 | * brightness value | |
4dca20ef CE |
15055 | */ |
15056 | static void quirk_invert_brightness(struct drm_device *dev) | |
15057 | { | |
15058 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15059 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 15060 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
15061 | } |
15062 | ||
9c72cc6f SD |
15063 | /* Some VBT's incorrectly indicate no backlight is present */ |
15064 | static void quirk_backlight_present(struct drm_device *dev) | |
15065 | { | |
15066 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15067 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
15068 | DRM_INFO("applying backlight present quirk\n"); | |
15069 | } | |
15070 | ||
b690e96c JB |
15071 | struct intel_quirk { |
15072 | int device; | |
15073 | int subsystem_vendor; | |
15074 | int subsystem_device; | |
15075 | void (*hook)(struct drm_device *dev); | |
15076 | }; | |
15077 | ||
5f85f176 EE |
15078 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
15079 | struct intel_dmi_quirk { | |
15080 | void (*hook)(struct drm_device *dev); | |
15081 | const struct dmi_system_id (*dmi_id_list)[]; | |
15082 | }; | |
15083 | ||
15084 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
15085 | { | |
15086 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
15087 | return 1; | |
15088 | } | |
15089 | ||
15090 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
15091 | { | |
15092 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
15093 | { | |
15094 | .callback = intel_dmi_reverse_brightness, | |
15095 | .ident = "NCR Corporation", | |
15096 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
15097 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
15098 | }, | |
15099 | }, | |
15100 | { } /* terminating entry */ | |
15101 | }, | |
15102 | .hook = quirk_invert_brightness, | |
15103 | }, | |
15104 | }; | |
15105 | ||
c43b5634 | 15106 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
15107 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
15108 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
15109 | ||
b690e96c JB |
15110 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
15111 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
15112 | ||
5f080c0f VS |
15113 | /* 830 needs to leave pipe A & dpll A up */ |
15114 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
15115 | ||
b6b5d049 VS |
15116 | /* 830 needs to leave pipe B & dpll B up */ |
15117 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
15118 | ||
435793df KP |
15119 | /* Lenovo U160 cannot use SSC on LVDS */ |
15120 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
15121 | |
15122 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
15123 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 15124 | |
be505f64 AH |
15125 | /* Acer Aspire 5734Z must invert backlight brightness */ |
15126 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
15127 | ||
15128 | /* Acer/eMachines G725 */ | |
15129 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
15130 | ||
15131 | /* Acer/eMachines e725 */ | |
15132 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
15133 | ||
15134 | /* Acer/Packard Bell NCL20 */ | |
15135 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
15136 | ||
15137 | /* Acer Aspire 4736Z */ | |
15138 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
15139 | |
15140 | /* Acer Aspire 5336 */ | |
15141 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
15142 | |
15143 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
15144 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 15145 | |
dfb3d47b SD |
15146 | /* Acer C720 Chromebook (Core i3 4005U) */ |
15147 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
15148 | ||
b2a9601c | 15149 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
15150 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
15151 | ||
1b9448b0 JN |
15152 | /* Apple Macbook 4,1 */ |
15153 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
15154 | ||
d4967d8c SD |
15155 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
15156 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
15157 | |
15158 | /* HP Chromebook 14 (Celeron 2955U) */ | |
15159 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
15160 | |
15161 | /* Dell Chromebook 11 */ | |
15162 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
15163 | |
15164 | /* Dell Chromebook 11 (2015 version) */ | |
15165 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
15166 | }; |
15167 | ||
15168 | static void intel_init_quirks(struct drm_device *dev) | |
15169 | { | |
15170 | struct pci_dev *d = dev->pdev; | |
15171 | int i; | |
15172 | ||
15173 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
15174 | struct intel_quirk *q = &intel_quirks[i]; | |
15175 | ||
15176 | if (d->device == q->device && | |
15177 | (d->subsystem_vendor == q->subsystem_vendor || | |
15178 | q->subsystem_vendor == PCI_ANY_ID) && | |
15179 | (d->subsystem_device == q->subsystem_device || | |
15180 | q->subsystem_device == PCI_ANY_ID)) | |
15181 | q->hook(dev); | |
15182 | } | |
5f85f176 EE |
15183 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
15184 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
15185 | intel_dmi_quirks[i].hook(dev); | |
15186 | } | |
b690e96c JB |
15187 | } |
15188 | ||
9cce37f4 JB |
15189 | /* Disable the VGA plane that we never use */ |
15190 | static void i915_disable_vga(struct drm_device *dev) | |
15191 | { | |
15192 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15193 | u8 sr1; | |
f0f59a00 | 15194 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 15195 | |
2b37c616 | 15196 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 15197 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 15198 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
15199 | sr1 = inb(VGA_SR_DATA); |
15200 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
15201 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
15202 | udelay(300); | |
15203 | ||
01f5a626 | 15204 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
15205 | POSTING_READ(vga_reg); |
15206 | } | |
15207 | ||
f817586c DV |
15208 | void intel_modeset_init_hw(struct drm_device *dev) |
15209 | { | |
1a617b77 ML |
15210 | struct drm_i915_private *dev_priv = dev->dev_private; |
15211 | ||
b6283055 | 15212 | intel_update_cdclk(dev); |
1a617b77 ML |
15213 | |
15214 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; | |
15215 | ||
f817586c | 15216 | intel_init_clock_gating(dev); |
dc97997a | 15217 | intel_enable_gt_powersave(dev_priv); |
f817586c DV |
15218 | } |
15219 | ||
d93c0372 MR |
15220 | /* |
15221 | * Calculate what we think the watermarks should be for the state we've read | |
15222 | * out of the hardware and then immediately program those watermarks so that | |
15223 | * we ensure the hardware settings match our internal state. | |
15224 | * | |
15225 | * We can calculate what we think WM's should be by creating a duplicate of the | |
15226 | * current state (which was constructed during hardware readout) and running it | |
15227 | * through the atomic check code to calculate new watermark values in the | |
15228 | * state object. | |
15229 | */ | |
15230 | static void sanitize_watermarks(struct drm_device *dev) | |
15231 | { | |
15232 | struct drm_i915_private *dev_priv = to_i915(dev); | |
15233 | struct drm_atomic_state *state; | |
15234 | struct drm_crtc *crtc; | |
15235 | struct drm_crtc_state *cstate; | |
15236 | struct drm_modeset_acquire_ctx ctx; | |
15237 | int ret; | |
15238 | int i; | |
15239 | ||
15240 | /* Only supported on platforms that use atomic watermark design */ | |
ed4a6a7c | 15241 | if (!dev_priv->display.optimize_watermarks) |
d93c0372 MR |
15242 | return; |
15243 | ||
15244 | /* | |
15245 | * We need to hold connection_mutex before calling duplicate_state so | |
15246 | * that the connector loop is protected. | |
15247 | */ | |
15248 | drm_modeset_acquire_init(&ctx, 0); | |
15249 | retry: | |
0cd1262d | 15250 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
15251 | if (ret == -EDEADLK) { |
15252 | drm_modeset_backoff(&ctx); | |
15253 | goto retry; | |
15254 | } else if (WARN_ON(ret)) { | |
0cd1262d | 15255 | goto fail; |
d93c0372 MR |
15256 | } |
15257 | ||
15258 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
15259 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 15260 | goto fail; |
d93c0372 | 15261 | |
ed4a6a7c MR |
15262 | /* |
15263 | * Hardware readout is the only time we don't want to calculate | |
15264 | * intermediate watermarks (since we don't trust the current | |
15265 | * watermarks). | |
15266 | */ | |
15267 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
15268 | ||
d93c0372 MR |
15269 | ret = intel_atomic_check(dev, state); |
15270 | if (ret) { | |
15271 | /* | |
15272 | * If we fail here, it means that the hardware appears to be | |
15273 | * programmed in a way that shouldn't be possible, given our | |
15274 | * understanding of watermark requirements. This might mean a | |
15275 | * mistake in the hardware readout code or a mistake in the | |
15276 | * watermark calculations for a given platform. Raise a WARN | |
15277 | * so that this is noticeable. | |
15278 | * | |
15279 | * If this actually happens, we'll have to just leave the | |
15280 | * BIOS-programmed watermarks untouched and hope for the best. | |
15281 | */ | |
15282 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
0cd1262d | 15283 | goto fail; |
d93c0372 MR |
15284 | } |
15285 | ||
15286 | /* Write calculated watermark values back */ | |
d93c0372 MR |
15287 | for_each_crtc_in_state(state, crtc, cstate, i) { |
15288 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); | |
15289 | ||
ed4a6a7c MR |
15290 | cs->wm.need_postvbl_update = true; |
15291 | dev_priv->display.optimize_watermarks(cs); | |
d93c0372 MR |
15292 | } |
15293 | ||
15294 | drm_atomic_state_free(state); | |
0cd1262d | 15295 | fail: |
d93c0372 MR |
15296 | drm_modeset_drop_locks(&ctx); |
15297 | drm_modeset_acquire_fini(&ctx); | |
15298 | } | |
15299 | ||
79e53945 JB |
15300 | void intel_modeset_init(struct drm_device *dev) |
15301 | { | |
72e96d64 JL |
15302 | struct drm_i915_private *dev_priv = to_i915(dev); |
15303 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
1fe47785 | 15304 | int sprite, ret; |
8cc87b75 | 15305 | enum pipe pipe; |
46f297fb | 15306 | struct intel_crtc *crtc; |
79e53945 JB |
15307 | |
15308 | drm_mode_config_init(dev); | |
15309 | ||
15310 | dev->mode_config.min_width = 0; | |
15311 | dev->mode_config.min_height = 0; | |
15312 | ||
019d96cb DA |
15313 | dev->mode_config.preferred_depth = 24; |
15314 | dev->mode_config.prefer_shadow = 1; | |
15315 | ||
25bab385 TU |
15316 | dev->mode_config.allow_fb_modifiers = true; |
15317 | ||
e6ecefaa | 15318 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 15319 | |
b690e96c JB |
15320 | intel_init_quirks(dev); |
15321 | ||
1fa61106 ED |
15322 | intel_init_pm(dev); |
15323 | ||
e3c74757 BW |
15324 | if (INTEL_INFO(dev)->num_pipes == 0) |
15325 | return; | |
15326 | ||
69f92f67 LW |
15327 | /* |
15328 | * There may be no VBT; and if the BIOS enabled SSC we can | |
15329 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
15330 | * BIOS isn't using it, don't assume it will work even if the VBT | |
15331 | * indicates as much. | |
15332 | */ | |
15333 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { | |
15334 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
15335 | DREF_SSC1_ENABLE); | |
15336 | ||
15337 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
15338 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
15339 | bios_lvds_use_ssc ? "en" : "dis", | |
15340 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
15341 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
15342 | } | |
15343 | } | |
15344 | ||
a6c45cf0 CW |
15345 | if (IS_GEN2(dev)) { |
15346 | dev->mode_config.max_width = 2048; | |
15347 | dev->mode_config.max_height = 2048; | |
15348 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
15349 | dev->mode_config.max_width = 4096; |
15350 | dev->mode_config.max_height = 4096; | |
79e53945 | 15351 | } else { |
a6c45cf0 CW |
15352 | dev->mode_config.max_width = 8192; |
15353 | dev->mode_config.max_height = 8192; | |
79e53945 | 15354 | } |
068be561 | 15355 | |
dc41c154 VS |
15356 | if (IS_845G(dev) || IS_I865G(dev)) { |
15357 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
15358 | dev->mode_config.cursor_height = 1023; | |
15359 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
15360 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
15361 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
15362 | } else { | |
15363 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
15364 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
15365 | } | |
15366 | ||
72e96d64 | 15367 | dev->mode_config.fb_base = ggtt->mappable_base; |
79e53945 | 15368 | |
28c97730 | 15369 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
15370 | INTEL_INFO(dev)->num_pipes, |
15371 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 15372 | |
055e393f | 15373 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 15374 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 15375 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 15376 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 15377 | if (ret) |
06da8da2 | 15378 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 15379 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 15380 | } |
79e53945 JB |
15381 | } |
15382 | ||
bfa7df01 VS |
15383 | intel_update_czclk(dev_priv); |
15384 | intel_update_cdclk(dev); | |
15385 | ||
e72f9fbf | 15386 | intel_shared_dpll_init(dev); |
ee7b9f93 | 15387 | |
9cce37f4 JB |
15388 | /* Just disable it once at startup */ |
15389 | i915_disable_vga(dev); | |
79e53945 | 15390 | intel_setup_outputs(dev); |
11be49eb | 15391 | |
6e9f798d | 15392 | drm_modeset_lock_all(dev); |
043e9bda | 15393 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 15394 | drm_modeset_unlock_all(dev); |
46f297fb | 15395 | |
d3fcc808 | 15396 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
15397 | struct intel_initial_plane_config plane_config = {}; |
15398 | ||
46f297fb JB |
15399 | if (!crtc->active) |
15400 | continue; | |
15401 | ||
46f297fb | 15402 | /* |
46f297fb JB |
15403 | * Note that reserving the BIOS fb up front prevents us |
15404 | * from stuffing other stolen allocations like the ring | |
15405 | * on top. This prevents some ugliness at boot time, and | |
15406 | * can even allow for smooth boot transitions if the BIOS | |
15407 | * fb is large enough for the active pipe configuration. | |
15408 | */ | |
eeebeac5 ML |
15409 | dev_priv->display.get_initial_plane_config(crtc, |
15410 | &plane_config); | |
15411 | ||
15412 | /* | |
15413 | * If the fb is shared between multiple heads, we'll | |
15414 | * just get the first one. | |
15415 | */ | |
15416 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 15417 | } |
d93c0372 MR |
15418 | |
15419 | /* | |
15420 | * Make sure hardware watermarks really match the state we read out. | |
15421 | * Note that we need to do this after reconstructing the BIOS fb's | |
15422 | * since the watermark calculation done here will use pstate->fb. | |
15423 | */ | |
15424 | sanitize_watermarks(dev); | |
2c7111db CW |
15425 | } |
15426 | ||
7fad798e DV |
15427 | static void intel_enable_pipe_a(struct drm_device *dev) |
15428 | { | |
15429 | struct intel_connector *connector; | |
15430 | struct drm_connector *crt = NULL; | |
15431 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 15432 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
15433 | |
15434 | /* We can't just switch on the pipe A, we need to set things up with a | |
15435 | * proper mode and output configuration. As a gross hack, enable pipe A | |
15436 | * by enabling the load detect pipe once. */ | |
3a3371ff | 15437 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
15438 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
15439 | crt = &connector->base; | |
15440 | break; | |
15441 | } | |
15442 | } | |
15443 | ||
15444 | if (!crt) | |
15445 | return; | |
15446 | ||
208bf9fd | 15447 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 15448 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
15449 | } |
15450 | ||
fa555837 DV |
15451 | static bool |
15452 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15453 | { | |
7eb552ae BW |
15454 | struct drm_device *dev = crtc->base.dev; |
15455 | struct drm_i915_private *dev_priv = dev->dev_private; | |
649636ef | 15456 | u32 val; |
fa555837 | 15457 | |
7eb552ae | 15458 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
15459 | return true; |
15460 | ||
649636ef | 15461 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
15462 | |
15463 | if ((val & DISPLAY_PLANE_ENABLE) && | |
15464 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
15465 | return false; | |
15466 | ||
15467 | return true; | |
15468 | } | |
15469 | ||
02e93c35 VS |
15470 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
15471 | { | |
15472 | struct drm_device *dev = crtc->base.dev; | |
15473 | struct intel_encoder *encoder; | |
15474 | ||
15475 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
15476 | return true; | |
15477 | ||
15478 | return false; | |
15479 | } | |
15480 | ||
dd756198 VS |
15481 | static bool intel_encoder_has_connectors(struct intel_encoder *encoder) |
15482 | { | |
15483 | struct drm_device *dev = encoder->base.dev; | |
15484 | struct intel_connector *connector; | |
15485 | ||
15486 | for_each_connector_on_encoder(dev, &encoder->base, connector) | |
15487 | return true; | |
15488 | ||
15489 | return false; | |
15490 | } | |
15491 | ||
24929352 DV |
15492 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15493 | { | |
15494 | struct drm_device *dev = crtc->base.dev; | |
15495 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4d1de975 | 15496 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
24929352 | 15497 | |
24929352 | 15498 | /* Clear any frame start delays used for debugging left by the BIOS */ |
4d1de975 JN |
15499 | if (!transcoder_is_dsi(cpu_transcoder)) { |
15500 | i915_reg_t reg = PIPECONF(cpu_transcoder); | |
15501 | ||
15502 | I915_WRITE(reg, | |
15503 | I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); | |
15504 | } | |
24929352 | 15505 | |
d3eaf884 | 15506 | /* restore vblank interrupts to correct state */ |
9625604c | 15507 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 15508 | if (crtc->active) { |
f9cd7b88 VS |
15509 | struct intel_plane *plane; |
15510 | ||
9625604c | 15511 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
15512 | |
15513 | /* Disable everything but the primary plane */ | |
15514 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
15515 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
15516 | continue; | |
15517 | ||
15518 | plane->disable_plane(&plane->base, &crtc->base); | |
15519 | } | |
9625604c | 15520 | } |
d3eaf884 | 15521 | |
24929352 | 15522 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
15523 | * disable the crtc (and hence change the state) if it is wrong. Note |
15524 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
15525 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
15526 | bool plane; |
15527 | ||
24929352 DV |
15528 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
15529 | crtc->base.base.id); | |
15530 | ||
15531 | /* Pipe has the wrong plane attached and the plane is active. | |
15532 | * Temporarily change the plane mapping and disable everything | |
15533 | * ... */ | |
15534 | plane = crtc->plane; | |
b70709a6 | 15535 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 15536 | crtc->plane = !plane; |
b17d48e2 | 15537 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15538 | crtc->plane = plane; |
24929352 | 15539 | } |
24929352 | 15540 | |
7fad798e DV |
15541 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
15542 | crtc->pipe == PIPE_A && !crtc->active) { | |
15543 | /* BIOS forgot to enable pipe A, this mostly happens after | |
15544 | * resume. Force-enable the pipe to fix this, the update_dpms | |
15545 | * call below we restore the pipe to the right state, but leave | |
15546 | * the required bits on. */ | |
15547 | intel_enable_pipe_a(dev); | |
15548 | } | |
15549 | ||
24929352 DV |
15550 | /* Adjust the state of the output pipe according to whether we |
15551 | * have active connectors/encoders. */ | |
842e0307 | 15552 | if (crtc->active && !intel_crtc_has_encoders(crtc)) |
b17d48e2 | 15553 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15554 | |
a3ed6aad | 15555 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
15556 | /* |
15557 | * We start out with underrun reporting disabled to avoid races. | |
15558 | * For correct bookkeeping mark this on active crtcs. | |
15559 | * | |
c5ab3bc0 DV |
15560 | * Also on gmch platforms we dont have any hardware bits to |
15561 | * disable the underrun reporting. Which means we need to start | |
15562 | * out with underrun reporting disabled also on inactive pipes, | |
15563 | * since otherwise we'll complain about the garbage we read when | |
15564 | * e.g. coming up after runtime pm. | |
15565 | * | |
4cc31489 DV |
15566 | * No protection against concurrent access is required - at |
15567 | * worst a fifo underrun happens which also sets this to false. | |
15568 | */ | |
15569 | crtc->cpu_fifo_underrun_disabled = true; | |
15570 | crtc->pch_fifo_underrun_disabled = true; | |
15571 | } | |
24929352 DV |
15572 | } |
15573 | ||
15574 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15575 | { | |
15576 | struct intel_connector *connector; | |
15577 | struct drm_device *dev = encoder->base.dev; | |
15578 | ||
15579 | /* We need to check both for a crtc link (meaning that the | |
15580 | * encoder is active and trying to read from a pipe) and the | |
15581 | * pipe itself being active. */ | |
15582 | bool has_active_crtc = encoder->base.crtc && | |
15583 | to_intel_crtc(encoder->base.crtc)->active; | |
15584 | ||
dd756198 | 15585 | if (intel_encoder_has_connectors(encoder) && !has_active_crtc) { |
24929352 DV |
15586 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
15587 | encoder->base.base.id, | |
8e329a03 | 15588 | encoder->base.name); |
24929352 DV |
15589 | |
15590 | /* Connector is active, but has no active pipe. This is | |
15591 | * fallout from our resume register restoring. Disable | |
15592 | * the encoder manually again. */ | |
15593 | if (encoder->base.crtc) { | |
15594 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
15595 | encoder->base.base.id, | |
8e329a03 | 15596 | encoder->base.name); |
24929352 | 15597 | encoder->disable(encoder); |
a62d1497 VS |
15598 | if (encoder->post_disable) |
15599 | encoder->post_disable(encoder); | |
24929352 | 15600 | } |
7f1950fb | 15601 | encoder->base.crtc = NULL; |
24929352 DV |
15602 | |
15603 | /* Inconsistent output/port/pipe state happens presumably due to | |
15604 | * a bug in one of the get_hw_state functions. Or someplace else | |
15605 | * in our code, like the register restore mess on resume. Clamp | |
15606 | * things to off as a safer default. */ | |
3a3371ff | 15607 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15608 | if (connector->encoder != encoder) |
15609 | continue; | |
7f1950fb EE |
15610 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
15611 | connector->base.encoder = NULL; | |
24929352 DV |
15612 | } |
15613 | } | |
15614 | /* Enabled encoders without active connectors will be fixed in | |
15615 | * the crtc fixup. */ | |
15616 | } | |
15617 | ||
04098753 | 15618 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
15619 | { |
15620 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 15621 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 15622 | |
04098753 ID |
15623 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15624 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
15625 | i915_disable_vga(dev); | |
15626 | } | |
15627 | } | |
15628 | ||
15629 | void i915_redisable_vga(struct drm_device *dev) | |
15630 | { | |
15631 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15632 | ||
8dc8a27c PZ |
15633 | /* This function can be called both from intel_modeset_setup_hw_state or |
15634 | * at a very early point in our resume sequence, where the power well | |
15635 | * structures are not yet restored. Since this function is at a very | |
15636 | * paranoid "someone might have enabled VGA while we were not looking" | |
15637 | * level, just check if the power well is enabled instead of trying to | |
15638 | * follow the "don't touch the power well if we don't need it" policy | |
15639 | * the rest of the driver uses. */ | |
6392f847 | 15640 | if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15641 | return; |
15642 | ||
04098753 | 15643 | i915_redisable_vga_power_on(dev); |
6392f847 ID |
15644 | |
15645 | intel_display_power_put(dev_priv, POWER_DOMAIN_VGA); | |
0fde901f KM |
15646 | } |
15647 | ||
f9cd7b88 | 15648 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 15649 | { |
f9cd7b88 | 15650 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 15651 | |
f9cd7b88 | 15652 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
15653 | } |
15654 | ||
f9cd7b88 VS |
15655 | /* FIXME read out full plane state for all planes */ |
15656 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 15657 | { |
b26d3ea3 | 15658 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 15659 | struct intel_plane_state *plane_state = |
b26d3ea3 | 15660 | to_intel_plane_state(primary->state); |
d032ffa0 | 15661 | |
19b8d387 | 15662 | plane_state->visible = crtc->active && |
b26d3ea3 ML |
15663 | primary_get_hw_state(to_intel_plane(primary)); |
15664 | ||
15665 | if (plane_state->visible) | |
15666 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); | |
98ec7739 VS |
15667 | } |
15668 | ||
30e984df | 15669 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
15670 | { |
15671 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15672 | enum pipe pipe; | |
24929352 DV |
15673 | struct intel_crtc *crtc; |
15674 | struct intel_encoder *encoder; | |
15675 | struct intel_connector *connector; | |
5358901f | 15676 | int i; |
24929352 | 15677 | |
565602d7 ML |
15678 | dev_priv->active_crtcs = 0; |
15679 | ||
d3fcc808 | 15680 | for_each_intel_crtc(dev, crtc) { |
565602d7 ML |
15681 | struct intel_crtc_state *crtc_state = crtc->config; |
15682 | int pixclk = 0; | |
3b117c8f | 15683 | |
565602d7 ML |
15684 | __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base); |
15685 | memset(crtc_state, 0, sizeof(*crtc_state)); | |
15686 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 15687 | |
565602d7 ML |
15688 | crtc_state->base.active = crtc_state->base.enable = |
15689 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
15690 | ||
15691 | crtc->base.enabled = crtc_state->base.enable; | |
15692 | crtc->active = crtc_state->base.active; | |
15693 | ||
15694 | if (crtc_state->base.active) { | |
15695 | dev_priv->active_crtcs |= 1 << crtc->pipe; | |
15696 | ||
15697 | if (IS_BROADWELL(dev_priv)) { | |
15698 | pixclk = ilk_pipe_pixel_rate(crtc_state); | |
15699 | ||
15700 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
15701 | if (crtc_state->ips_enabled) | |
15702 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); | |
15703 | } else if (IS_VALLEYVIEW(dev_priv) || | |
15704 | IS_CHERRYVIEW(dev_priv) || | |
15705 | IS_BROXTON(dev_priv)) | |
15706 | pixclk = crtc_state->base.adjusted_mode.crtc_clock; | |
15707 | else | |
15708 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
15709 | } | |
15710 | ||
15711 | dev_priv->min_pixclk[crtc->pipe] = pixclk; | |
b70709a6 | 15712 | |
f9cd7b88 | 15713 | readout_plane_state(crtc); |
24929352 DV |
15714 | |
15715 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
15716 | crtc->base.base.id, | |
15717 | crtc->active ? "enabled" : "disabled"); | |
15718 | } | |
15719 | ||
5358901f DV |
15720 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15721 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15722 | ||
2edd6443 ACO |
15723 | pll->on = pll->funcs.get_hw_state(dev_priv, pll, |
15724 | &pll->config.hw_state); | |
3e369b76 | 15725 | pll->config.crtc_mask = 0; |
d3fcc808 | 15726 | for_each_intel_crtc(dev, crtc) { |
2dd66ebd | 15727 | if (crtc->active && crtc->config->shared_dpll == pll) |
3e369b76 | 15728 | pll->config.crtc_mask |= 1 << crtc->pipe; |
5358901f | 15729 | } |
2dd66ebd | 15730 | pll->active_mask = pll->config.crtc_mask; |
5358901f | 15731 | |
1e6f2ddc | 15732 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 15733 | pll->name, pll->config.crtc_mask, pll->on); |
5358901f DV |
15734 | } |
15735 | ||
b2784e15 | 15736 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15737 | pipe = 0; |
15738 | ||
15739 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
15740 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15741 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 15742 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
15743 | } else { |
15744 | encoder->base.crtc = NULL; | |
15745 | } | |
15746 | ||
6f2bcceb | 15747 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 15748 | encoder->base.base.id, |
8e329a03 | 15749 | encoder->base.name, |
24929352 | 15750 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 15751 | pipe_name(pipe)); |
24929352 DV |
15752 | } |
15753 | ||
3a3371ff | 15754 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15755 | if (connector->get_hw_state(connector)) { |
15756 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
15757 | |
15758 | encoder = connector->encoder; | |
15759 | connector->base.encoder = &encoder->base; | |
15760 | ||
15761 | if (encoder->base.crtc && | |
15762 | encoder->base.crtc->state->active) { | |
15763 | /* | |
15764 | * This has to be done during hardware readout | |
15765 | * because anything calling .crtc_disable may | |
15766 | * rely on the connector_mask being accurate. | |
15767 | */ | |
15768 | encoder->base.crtc->state->connector_mask |= | |
15769 | 1 << drm_connector_index(&connector->base); | |
e87a52b3 ML |
15770 | encoder->base.crtc->state->encoder_mask |= |
15771 | 1 << drm_encoder_index(&encoder->base); | |
2aa974c9 ML |
15772 | } |
15773 | ||
24929352 DV |
15774 | } else { |
15775 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15776 | connector->base.encoder = NULL; | |
15777 | } | |
15778 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
15779 | connector->base.base.id, | |
c23cc417 | 15780 | connector->base.name, |
24929352 DV |
15781 | connector->base.encoder ? "enabled" : "disabled"); |
15782 | } | |
7f4c6284 VS |
15783 | |
15784 | for_each_intel_crtc(dev, crtc) { | |
15785 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
15786 | ||
15787 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
15788 | if (crtc->base.state->active) { | |
15789 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
15790 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
15791 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
15792 | ||
15793 | /* | |
15794 | * The initial mode needs to be set in order to keep | |
15795 | * the atomic core happy. It wants a valid mode if the | |
15796 | * crtc's enabled, so we do the above call. | |
15797 | * | |
15798 | * At this point some state updated by the connectors | |
15799 | * in their ->detect() callback has not run yet, so | |
15800 | * no recalculation can be done yet. | |
15801 | * | |
15802 | * Even if we could do a recalculation and modeset | |
15803 | * right now it would cause a double modeset if | |
15804 | * fbdev or userspace chooses a different initial mode. | |
15805 | * | |
15806 | * If that happens, someone indicated they wanted a | |
15807 | * mode change, which means it's safe to do a full | |
15808 | * recalculation. | |
15809 | */ | |
15810 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
15811 | |
15812 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
15813 | update_scanline_offset(crtc); | |
7f4c6284 | 15814 | } |
e3b247da VS |
15815 | |
15816 | intel_pipe_config_sanity_check(dev_priv, crtc->config); | |
7f4c6284 | 15817 | } |
30e984df DV |
15818 | } |
15819 | ||
043e9bda ML |
15820 | /* Scan out the current hw modeset state, |
15821 | * and sanitizes it to the current state | |
15822 | */ | |
15823 | static void | |
15824 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df DV |
15825 | { |
15826 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15827 | enum pipe pipe; | |
30e984df DV |
15828 | struct intel_crtc *crtc; |
15829 | struct intel_encoder *encoder; | |
35c95375 | 15830 | int i; |
30e984df DV |
15831 | |
15832 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
15833 | |
15834 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 15835 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15836 | intel_sanitize_encoder(encoder); |
15837 | } | |
15838 | ||
055e393f | 15839 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
15840 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15841 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
15842 | intel_dump_pipe_config(crtc, crtc->config, |
15843 | "[setup_hw_state]"); | |
24929352 | 15844 | } |
9a935856 | 15845 | |
d29b2f9d ACO |
15846 | intel_modeset_update_connector_atomic_state(dev); |
15847 | ||
35c95375 DV |
15848 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15849 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15850 | ||
2dd66ebd | 15851 | if (!pll->on || pll->active_mask) |
35c95375 DV |
15852 | continue; |
15853 | ||
15854 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15855 | ||
2edd6443 | 15856 | pll->funcs.disable(dev_priv, pll); |
35c95375 DV |
15857 | pll->on = false; |
15858 | } | |
15859 | ||
666a4537 | 15860 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6eb1a681 VS |
15861 | vlv_wm_get_hw_state(dev); |
15862 | else if (IS_GEN9(dev)) | |
3078999f PB |
15863 | skl_wm_get_hw_state(dev); |
15864 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 | 15865 | ilk_wm_get_hw_state(dev); |
292b990e ML |
15866 | |
15867 | for_each_intel_crtc(dev, crtc) { | |
15868 | unsigned long put_domains; | |
15869 | ||
74bff5f9 | 15870 | put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config); |
292b990e ML |
15871 | if (WARN_ON(put_domains)) |
15872 | modeset_put_power_domains(dev_priv, put_domains); | |
15873 | } | |
15874 | intel_display_set_init_power(dev_priv, false); | |
010cf73d PZ |
15875 | |
15876 | intel_fbc_init_pipe_state(dev_priv); | |
043e9bda | 15877 | } |
7d0bc1ea | 15878 | |
043e9bda ML |
15879 | void intel_display_resume(struct drm_device *dev) |
15880 | { | |
e2c8b870 ML |
15881 | struct drm_i915_private *dev_priv = to_i915(dev); |
15882 | struct drm_atomic_state *state = dev_priv->modeset_restore_state; | |
15883 | struct drm_modeset_acquire_ctx ctx; | |
043e9bda | 15884 | int ret; |
e2c8b870 | 15885 | bool setup = false; |
f30da187 | 15886 | |
e2c8b870 | 15887 | dev_priv->modeset_restore_state = NULL; |
043e9bda | 15888 | |
ea49c9ac ML |
15889 | /* |
15890 | * This is a cludge because with real atomic modeset mode_config.mutex | |
15891 | * won't be taken. Unfortunately some probed state like | |
15892 | * audio_codec_enable is still protected by mode_config.mutex, so lock | |
15893 | * it here for now. | |
15894 | */ | |
15895 | mutex_lock(&dev->mode_config.mutex); | |
e2c8b870 | 15896 | drm_modeset_acquire_init(&ctx, 0); |
043e9bda | 15897 | |
e2c8b870 ML |
15898 | retry: |
15899 | ret = drm_modeset_lock_all_ctx(dev, &ctx); | |
043e9bda | 15900 | |
e2c8b870 ML |
15901 | if (ret == 0 && !setup) { |
15902 | setup = true; | |
043e9bda | 15903 | |
e2c8b870 ML |
15904 | intel_modeset_setup_hw_state(dev); |
15905 | i915_redisable_vga(dev); | |
45e2b5f6 | 15906 | } |
8af6cf88 | 15907 | |
e2c8b870 ML |
15908 | if (ret == 0 && state) { |
15909 | struct drm_crtc_state *crtc_state; | |
15910 | struct drm_crtc *crtc; | |
15911 | int i; | |
043e9bda | 15912 | |
e2c8b870 ML |
15913 | state->acquire_ctx = &ctx; |
15914 | ||
e3d5457c VS |
15915 | /* ignore any reset values/BIOS leftovers in the WM registers */ |
15916 | to_intel_atomic_state(state)->skip_intermediate_wm = true; | |
15917 | ||
e2c8b870 ML |
15918 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
15919 | /* | |
15920 | * Force recalculation even if we restore | |
15921 | * current state. With fast modeset this may not result | |
15922 | * in a modeset when the state is compatible. | |
15923 | */ | |
15924 | crtc_state->mode_changed = true; | |
15925 | } | |
15926 | ||
15927 | ret = drm_atomic_commit(state); | |
043e9bda ML |
15928 | } |
15929 | ||
e2c8b870 ML |
15930 | if (ret == -EDEADLK) { |
15931 | drm_modeset_backoff(&ctx); | |
15932 | goto retry; | |
15933 | } | |
043e9bda | 15934 | |
e2c8b870 ML |
15935 | drm_modeset_drop_locks(&ctx); |
15936 | drm_modeset_acquire_fini(&ctx); | |
ea49c9ac | 15937 | mutex_unlock(&dev->mode_config.mutex); |
043e9bda | 15938 | |
e2c8b870 ML |
15939 | if (ret) { |
15940 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
15941 | drm_atomic_state_free(state); | |
15942 | } | |
2c7111db CW |
15943 | } |
15944 | ||
15945 | void intel_modeset_gem_init(struct drm_device *dev) | |
15946 | { | |
dc97997a | 15947 | struct drm_i915_private *dev_priv = to_i915(dev); |
484b41dd | 15948 | struct drm_crtc *c; |
2ff8fde1 | 15949 | struct drm_i915_gem_object *obj; |
e0d6149b | 15950 | int ret; |
484b41dd | 15951 | |
dc97997a | 15952 | intel_init_gt_powersave(dev_priv); |
ae48434c | 15953 | |
1833b134 | 15954 | intel_modeset_init_hw(dev); |
02e792fb | 15955 | |
1ee8da6d | 15956 | intel_setup_overlay(dev_priv); |
484b41dd JB |
15957 | |
15958 | /* | |
15959 | * Make sure any fbs we allocated at startup are properly | |
15960 | * pinned & fenced. When we do the allocation it's too early | |
15961 | * for this. | |
15962 | */ | |
70e1e0ec | 15963 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
15964 | obj = intel_fb_obj(c->primary->fb); |
15965 | if (obj == NULL) | |
484b41dd JB |
15966 | continue; |
15967 | ||
e0d6149b | 15968 | mutex_lock(&dev->struct_mutex); |
3465c580 VS |
15969 | ret = intel_pin_and_fence_fb_obj(c->primary->fb, |
15970 | c->primary->state->rotation); | |
e0d6149b TU |
15971 | mutex_unlock(&dev->struct_mutex); |
15972 | if (ret) { | |
484b41dd JB |
15973 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
15974 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
15975 | drm_framebuffer_unreference(c->primary->fb); |
15976 | c->primary->fb = NULL; | |
36750f28 | 15977 | c->primary->crtc = c->primary->state->crtc = NULL; |
afd65eb4 | 15978 | update_state_fb(c->primary); |
36750f28 | 15979 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
15980 | } |
15981 | } | |
0962c3c9 VS |
15982 | |
15983 | intel_backlight_register(dev); | |
79e53945 JB |
15984 | } |
15985 | ||
4932e2c3 ID |
15986 | void intel_connector_unregister(struct intel_connector *intel_connector) |
15987 | { | |
15988 | struct drm_connector *connector = &intel_connector->base; | |
15989 | ||
15990 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 15991 | drm_connector_unregister(connector); |
4932e2c3 ID |
15992 | } |
15993 | ||
79e53945 JB |
15994 | void intel_modeset_cleanup(struct drm_device *dev) |
15995 | { | |
652c393a | 15996 | struct drm_i915_private *dev_priv = dev->dev_private; |
19c8054c | 15997 | struct intel_connector *connector; |
652c393a | 15998 | |
dc97997a | 15999 | intel_disable_gt_powersave(dev_priv); |
2eb5252e | 16000 | |
0962c3c9 VS |
16001 | intel_backlight_unregister(dev); |
16002 | ||
fd0c0642 DV |
16003 | /* |
16004 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 16005 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
16006 | * experience fancy races otherwise. |
16007 | */ | |
2aeb7d3a | 16008 | intel_irq_uninstall(dev_priv); |
eb21b92b | 16009 | |
fd0c0642 DV |
16010 | /* |
16011 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
16012 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
16013 | */ | |
f87ea761 | 16014 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 16015 | |
723bfd70 JB |
16016 | intel_unregister_dsm_handler(); |
16017 | ||
c937ab3e | 16018 | intel_fbc_global_disable(dev_priv); |
69341a5e | 16019 | |
1630fe75 CW |
16020 | /* flush any delayed tasks or pending work */ |
16021 | flush_scheduled_work(); | |
16022 | ||
db31af1d | 16023 | /* destroy the backlight and sysfs files before encoders/connectors */ |
19c8054c JN |
16024 | for_each_intel_connector(dev, connector) |
16025 | connector->unregister(connector); | |
d9255d57 | 16026 | |
79e53945 | 16027 | drm_mode_config_cleanup(dev); |
4d7bb011 | 16028 | |
1ee8da6d | 16029 | intel_cleanup_overlay(dev_priv); |
ae48434c | 16030 | |
dc97997a | 16031 | intel_cleanup_gt_powersave(dev_priv); |
f5949141 DV |
16032 | |
16033 | intel_teardown_gmbus(dev); | |
79e53945 JB |
16034 | } |
16035 | ||
f1c79df3 ZW |
16036 | /* |
16037 | * Return which encoder is currently attached for connector. | |
16038 | */ | |
df0e9248 | 16039 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 16040 | { |
df0e9248 CW |
16041 | return &intel_attached_encoder(connector)->base; |
16042 | } | |
f1c79df3 | 16043 | |
df0e9248 CW |
16044 | void intel_connector_attach_encoder(struct intel_connector *connector, |
16045 | struct intel_encoder *encoder) | |
16046 | { | |
16047 | connector->encoder = encoder; | |
16048 | drm_mode_connector_attach_encoder(&connector->base, | |
16049 | &encoder->base); | |
79e53945 | 16050 | } |
28d52043 DA |
16051 | |
16052 | /* | |
16053 | * set vga decode state - true == enable VGA decode | |
16054 | */ | |
16055 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
16056 | { | |
16057 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 16058 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
16059 | u16 gmch_ctrl; |
16060 | ||
75fa041d CW |
16061 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
16062 | DRM_ERROR("failed to read control word\n"); | |
16063 | return -EIO; | |
16064 | } | |
16065 | ||
c0cc8a55 CW |
16066 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
16067 | return 0; | |
16068 | ||
28d52043 DA |
16069 | if (state) |
16070 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
16071 | else | |
16072 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
16073 | |
16074 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
16075 | DRM_ERROR("failed to write control word\n"); | |
16076 | return -EIO; | |
16077 | } | |
16078 | ||
28d52043 DA |
16079 | return 0; |
16080 | } | |
c4a1d9e4 | 16081 | |
c4a1d9e4 | 16082 | struct intel_display_error_state { |
ff57f1b0 PZ |
16083 | |
16084 | u32 power_well_driver; | |
16085 | ||
63b66e5b CW |
16086 | int num_transcoders; |
16087 | ||
c4a1d9e4 CW |
16088 | struct intel_cursor_error_state { |
16089 | u32 control; | |
16090 | u32 position; | |
16091 | u32 base; | |
16092 | u32 size; | |
52331309 | 16093 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16094 | |
16095 | struct intel_pipe_error_state { | |
ddf9c536 | 16096 | bool power_domain_on; |
c4a1d9e4 | 16097 | u32 source; |
f301b1e1 | 16098 | u32 stat; |
52331309 | 16099 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16100 | |
16101 | struct intel_plane_error_state { | |
16102 | u32 control; | |
16103 | u32 stride; | |
16104 | u32 size; | |
16105 | u32 pos; | |
16106 | u32 addr; | |
16107 | u32 surface; | |
16108 | u32 tile_offset; | |
52331309 | 16109 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
16110 | |
16111 | struct intel_transcoder_error_state { | |
ddf9c536 | 16112 | bool power_domain_on; |
63b66e5b CW |
16113 | enum transcoder cpu_transcoder; |
16114 | ||
16115 | u32 conf; | |
16116 | ||
16117 | u32 htotal; | |
16118 | u32 hblank; | |
16119 | u32 hsync; | |
16120 | u32 vtotal; | |
16121 | u32 vblank; | |
16122 | u32 vsync; | |
16123 | } transcoder[4]; | |
c4a1d9e4 CW |
16124 | }; |
16125 | ||
16126 | struct intel_display_error_state * | |
c033666a | 16127 | intel_display_capture_error_state(struct drm_i915_private *dev_priv) |
c4a1d9e4 | 16128 | { |
c4a1d9e4 | 16129 | struct intel_display_error_state *error; |
63b66e5b CW |
16130 | int transcoders[] = { |
16131 | TRANSCODER_A, | |
16132 | TRANSCODER_B, | |
16133 | TRANSCODER_C, | |
16134 | TRANSCODER_EDP, | |
16135 | }; | |
c4a1d9e4 CW |
16136 | int i; |
16137 | ||
c033666a | 16138 | if (INTEL_INFO(dev_priv)->num_pipes == 0) |
63b66e5b CW |
16139 | return NULL; |
16140 | ||
9d1cb914 | 16141 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
16142 | if (error == NULL) |
16143 | return NULL; | |
16144 | ||
c033666a | 16145 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ff57f1b0 PZ |
16146 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
16147 | ||
055e393f | 16148 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 16149 | error->pipe[i].power_domain_on = |
f458ebbc DV |
16150 | __intel_display_power_is_enabled(dev_priv, |
16151 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 16152 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
16153 | continue; |
16154 | ||
5efb3e28 VS |
16155 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
16156 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
16157 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
16158 | |
16159 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
16160 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
c033666a | 16161 | if (INTEL_GEN(dev_priv) <= 3) { |
51889b35 | 16162 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
16163 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
16164 | } | |
c033666a | 16165 | if (INTEL_GEN(dev_priv) <= 7 && !IS_HASWELL(dev_priv)) |
ca291363 | 16166 | error->plane[i].addr = I915_READ(DSPADDR(i)); |
c033666a | 16167 | if (INTEL_GEN(dev_priv) >= 4) { |
c4a1d9e4 CW |
16168 | error->plane[i].surface = I915_READ(DSPSURF(i)); |
16169 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
16170 | } | |
16171 | ||
c4a1d9e4 | 16172 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 16173 | |
c033666a | 16174 | if (HAS_GMCH_DISPLAY(dev_priv)) |
f301b1e1 | 16175 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
16176 | } |
16177 | ||
4d1de975 | 16178 | /* Note: this does not include DSI transcoders. */ |
c033666a | 16179 | error->num_transcoders = INTEL_INFO(dev_priv)->num_pipes; |
2d1fe073 | 16180 | if (HAS_DDI(dev_priv)) |
63b66e5b CW |
16181 | error->num_transcoders++; /* Account for eDP. */ |
16182 | ||
16183 | for (i = 0; i < error->num_transcoders; i++) { | |
16184 | enum transcoder cpu_transcoder = transcoders[i]; | |
16185 | ||
ddf9c536 | 16186 | error->transcoder[i].power_domain_on = |
f458ebbc | 16187 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 16188 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 16189 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
16190 | continue; |
16191 | ||
63b66e5b CW |
16192 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
16193 | ||
16194 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
16195 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
16196 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
16197 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
16198 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
16199 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
16200 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
16201 | } |
16202 | ||
16203 | return error; | |
16204 | } | |
16205 | ||
edc3d884 MK |
16206 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
16207 | ||
c4a1d9e4 | 16208 | void |
edc3d884 | 16209 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
16210 | struct drm_device *dev, |
16211 | struct intel_display_error_state *error) | |
16212 | { | |
055e393f | 16213 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
16214 | int i; |
16215 | ||
63b66e5b CW |
16216 | if (!error) |
16217 | return; | |
16218 | ||
edc3d884 | 16219 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 16220 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 16221 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 16222 | error->power_well_driver); |
055e393f | 16223 | for_each_pipe(dev_priv, i) { |
edc3d884 | 16224 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 16225 | err_printf(m, " Power: %s\n", |
87ad3212 | 16226 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 16227 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 16228 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
16229 | |
16230 | err_printf(m, "Plane [%d]:\n", i); | |
16231 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
16232 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 16233 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
16234 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
16235 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 16236 | } |
4b71a570 | 16237 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 16238 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 16239 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
16240 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
16241 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
16242 | } |
16243 | ||
edc3d884 MK |
16244 | err_printf(m, "Cursor [%d]:\n", i); |
16245 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
16246 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
16247 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 16248 | } |
63b66e5b CW |
16249 | |
16250 | for (i = 0; i < error->num_transcoders; i++) { | |
da205630 | 16251 | err_printf(m, "CPU transcoder: %s\n", |
63b66e5b | 16252 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 16253 | err_printf(m, " Power: %s\n", |
87ad3212 | 16254 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
16255 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
16256 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
16257 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
16258 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
16259 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
16260 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
16261 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
16262 | } | |
c4a1d9e4 | 16263 | } |