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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
319c1d42 | 40 | #include <drm/drm_atomic.h> |
c196e1d6 | 41 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
42 | #include <drm/drm_dp_helper.h> |
43 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
44 | #include <drm/drm_plane_helper.h> |
45 | #include <drm/drm_rect.h> | |
c0f372b3 | 46 | #include <linux/dma_remapping.h> |
fd8e058a AG |
47 | #include <linux/reservation.h> |
48 | #include <linux/dma-buf.h> | |
79e53945 | 49 | |
465c120c | 50 | /* Primary plane formats for gen <= 3 */ |
568db4f2 | 51 | static const uint32_t i8xx_primary_formats[] = { |
67fe7dc5 DL |
52 | DRM_FORMAT_C8, |
53 | DRM_FORMAT_RGB565, | |
465c120c | 54 | DRM_FORMAT_XRGB1555, |
67fe7dc5 | 55 | DRM_FORMAT_XRGB8888, |
465c120c MR |
56 | }; |
57 | ||
58 | /* Primary plane formats for gen >= 4 */ | |
568db4f2 | 59 | static const uint32_t i965_primary_formats[] = { |
6c0fd451 DL |
60 | DRM_FORMAT_C8, |
61 | DRM_FORMAT_RGB565, | |
62 | DRM_FORMAT_XRGB8888, | |
63 | DRM_FORMAT_XBGR8888, | |
64 | DRM_FORMAT_XRGB2101010, | |
65 | DRM_FORMAT_XBGR2101010, | |
66 | }; | |
67 | ||
68 | static const uint32_t skl_primary_formats[] = { | |
67fe7dc5 DL |
69 | DRM_FORMAT_C8, |
70 | DRM_FORMAT_RGB565, | |
71 | DRM_FORMAT_XRGB8888, | |
465c120c | 72 | DRM_FORMAT_XBGR8888, |
67fe7dc5 | 73 | DRM_FORMAT_ARGB8888, |
465c120c MR |
74 | DRM_FORMAT_ABGR8888, |
75 | DRM_FORMAT_XRGB2101010, | |
465c120c | 76 | DRM_FORMAT_XBGR2101010, |
ea916ea0 KM |
77 | DRM_FORMAT_YUYV, |
78 | DRM_FORMAT_YVYU, | |
79 | DRM_FORMAT_UYVY, | |
80 | DRM_FORMAT_VYUY, | |
465c120c MR |
81 | }; |
82 | ||
3d7d6510 MR |
83 | /* Cursor formats */ |
84 | static const uint32_t intel_cursor_formats[] = { | |
85 | DRM_FORMAT_ARGB8888, | |
86 | }; | |
87 | ||
f1f644dc | 88 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 89 | struct intel_crtc_state *pipe_config); |
18442d08 | 90 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 91 | struct intel_crtc_state *pipe_config); |
f1f644dc | 92 | |
eb1bfe80 JB |
93 | static int intel_framebuffer_init(struct drm_device *dev, |
94 | struct intel_framebuffer *ifb, | |
95 | struct drm_mode_fb_cmd2 *mode_cmd, | |
96 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
97 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
98 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 99 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
100 | struct intel_link_m_n *m_n, |
101 | struct intel_link_m_n *m2_n2); | |
29407aab | 102 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
103 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
104 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
d288f65f | 105 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 106 | const struct intel_crtc_state *pipe_config); |
d288f65f | 107 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 108 | const struct intel_crtc_state *pipe_config); |
613d2b27 ML |
109 | static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); |
110 | static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *); | |
549e2bfb CK |
111 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
112 | struct intel_crtc_state *crtc_state); | |
5ab7b0b7 ID |
113 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
114 | int num_connectors); | |
bfd16b2a ML |
115 | static void skylake_pfit_enable(struct intel_crtc *crtc); |
116 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force); | |
117 | static void ironlake_pfit_enable(struct intel_crtc *crtc); | |
043e9bda | 118 | static void intel_modeset_setup_hw_state(struct drm_device *dev); |
200757f5 | 119 | static void intel_pre_disable_primary(struct drm_crtc *crtc); |
e7457a9a | 120 | |
79e53945 | 121 | typedef struct { |
0206e353 | 122 | int min, max; |
79e53945 JB |
123 | } intel_range_t; |
124 | ||
125 | typedef struct { | |
0206e353 AJ |
126 | int dot_limit; |
127 | int p2_slow, p2_fast; | |
79e53945 JB |
128 | } intel_p2_t; |
129 | ||
d4906093 ML |
130 | typedef struct intel_limit intel_limit_t; |
131 | struct intel_limit { | |
0206e353 AJ |
132 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
133 | intel_p2_t p2; | |
d4906093 | 134 | }; |
79e53945 | 135 | |
bfa7df01 VS |
136 | /* returns HPLL frequency in kHz */ |
137 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) | |
138 | { | |
139 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; | |
140 | ||
141 | /* Obtain SKU information */ | |
142 | mutex_lock(&dev_priv->sb_lock); | |
143 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
144 | CCK_FUSE_HPLL_FREQ_MASK; | |
145 | mutex_unlock(&dev_priv->sb_lock); | |
146 | ||
147 | return vco_freq[hpll_freq] * 1000; | |
148 | } | |
149 | ||
150 | static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv, | |
151 | const char *name, u32 reg) | |
152 | { | |
153 | u32 val; | |
154 | int divider; | |
155 | ||
156 | if (dev_priv->hpll_freq == 0) | |
157 | dev_priv->hpll_freq = valleyview_get_vco(dev_priv); | |
158 | ||
159 | mutex_lock(&dev_priv->sb_lock); | |
160 | val = vlv_cck_read(dev_priv, reg); | |
161 | mutex_unlock(&dev_priv->sb_lock); | |
162 | ||
163 | divider = val & CCK_FREQUENCY_VALUES; | |
164 | ||
165 | WARN((val & CCK_FREQUENCY_STATUS) != | |
166 | (divider << CCK_FREQUENCY_STATUS_SHIFT), | |
167 | "%s change in progress\n", name); | |
168 | ||
169 | return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1); | |
170 | } | |
171 | ||
d2acd215 DV |
172 | int |
173 | intel_pch_rawclk(struct drm_device *dev) | |
174 | { | |
175 | struct drm_i915_private *dev_priv = dev->dev_private; | |
176 | ||
177 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
178 | ||
179 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
180 | } | |
181 | ||
79e50a4f JN |
182 | /* hrawclock is 1/4 the FSB frequency */ |
183 | int intel_hrawclk(struct drm_device *dev) | |
184 | { | |
185 | struct drm_i915_private *dev_priv = dev->dev_private; | |
186 | uint32_t clkcfg; | |
187 | ||
188 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ | |
666a4537 | 189 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
79e50a4f JN |
190 | return 200; |
191 | ||
192 | clkcfg = I915_READ(CLKCFG); | |
193 | switch (clkcfg & CLKCFG_FSB_MASK) { | |
194 | case CLKCFG_FSB_400: | |
195 | return 100; | |
196 | case CLKCFG_FSB_533: | |
197 | return 133; | |
198 | case CLKCFG_FSB_667: | |
199 | return 166; | |
200 | case CLKCFG_FSB_800: | |
201 | return 200; | |
202 | case CLKCFG_FSB_1067: | |
203 | return 266; | |
204 | case CLKCFG_FSB_1333: | |
205 | return 333; | |
206 | /* these two are just a guess; one of them might be right */ | |
207 | case CLKCFG_FSB_1600: | |
208 | case CLKCFG_FSB_1600_ALT: | |
209 | return 400; | |
210 | default: | |
211 | return 133; | |
212 | } | |
213 | } | |
214 | ||
bfa7df01 VS |
215 | static void intel_update_czclk(struct drm_i915_private *dev_priv) |
216 | { | |
666a4537 | 217 | if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) |
bfa7df01 VS |
218 | return; |
219 | ||
220 | dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", | |
221 | CCK_CZ_CLOCK_CONTROL); | |
222 | ||
223 | DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq); | |
224 | } | |
225 | ||
021357ac CW |
226 | static inline u32 /* units of 100MHz */ |
227 | intel_fdi_link_freq(struct drm_device *dev) | |
228 | { | |
8b99e68c CW |
229 | if (IS_GEN5(dev)) { |
230 | struct drm_i915_private *dev_priv = dev->dev_private; | |
231 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
232 | } else | |
233 | return 27; | |
021357ac CW |
234 | } |
235 | ||
5d536e28 | 236 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 237 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 238 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 239 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
240 | .m = { .min = 96, .max = 140 }, |
241 | .m1 = { .min = 18, .max = 26 }, | |
242 | .m2 = { .min = 6, .max = 16 }, | |
243 | .p = { .min = 4, .max = 128 }, | |
244 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
245 | .p2 = { .dot_limit = 165000, |
246 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
247 | }; |
248 | ||
5d536e28 DV |
249 | static const intel_limit_t intel_limits_i8xx_dvo = { |
250 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 251 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 252 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
253 | .m = { .min = 96, .max = 140 }, |
254 | .m1 = { .min = 18, .max = 26 }, | |
255 | .m2 = { .min = 6, .max = 16 }, | |
256 | .p = { .min = 4, .max = 128 }, | |
257 | .p1 = { .min = 2, .max = 33 }, | |
258 | .p2 = { .dot_limit = 165000, | |
259 | .p2_slow = 4, .p2_fast = 4 }, | |
260 | }; | |
261 | ||
e4b36699 | 262 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 263 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 264 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 265 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
266 | .m = { .min = 96, .max = 140 }, |
267 | .m1 = { .min = 18, .max = 26 }, | |
268 | .m2 = { .min = 6, .max = 16 }, | |
269 | .p = { .min = 4, .max = 128 }, | |
270 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
271 | .p2 = { .dot_limit = 165000, |
272 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 273 | }; |
273e27ca | 274 | |
e4b36699 | 275 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
276 | .dot = { .min = 20000, .max = 400000 }, |
277 | .vco = { .min = 1400000, .max = 2800000 }, | |
278 | .n = { .min = 1, .max = 6 }, | |
279 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
280 | .m1 = { .min = 8, .max = 18 }, |
281 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
282 | .p = { .min = 5, .max = 80 }, |
283 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
284 | .p2 = { .dot_limit = 200000, |
285 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
286 | }; |
287 | ||
288 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
289 | .dot = { .min = 20000, .max = 400000 }, |
290 | .vco = { .min = 1400000, .max = 2800000 }, | |
291 | .n = { .min = 1, .max = 6 }, | |
292 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
293 | .m1 = { .min = 8, .max = 18 }, |
294 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
295 | .p = { .min = 7, .max = 98 }, |
296 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
297 | .p2 = { .dot_limit = 112000, |
298 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
299 | }; |
300 | ||
273e27ca | 301 | |
e4b36699 | 302 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
303 | .dot = { .min = 25000, .max = 270000 }, |
304 | .vco = { .min = 1750000, .max = 3500000}, | |
305 | .n = { .min = 1, .max = 4 }, | |
306 | .m = { .min = 104, .max = 138 }, | |
307 | .m1 = { .min = 17, .max = 23 }, | |
308 | .m2 = { .min = 5, .max = 11 }, | |
309 | .p = { .min = 10, .max = 30 }, | |
310 | .p1 = { .min = 1, .max = 3}, | |
311 | .p2 = { .dot_limit = 270000, | |
312 | .p2_slow = 10, | |
313 | .p2_fast = 10 | |
044c7c41 | 314 | }, |
e4b36699 KP |
315 | }; |
316 | ||
317 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
318 | .dot = { .min = 22000, .max = 400000 }, |
319 | .vco = { .min = 1750000, .max = 3500000}, | |
320 | .n = { .min = 1, .max = 4 }, | |
321 | .m = { .min = 104, .max = 138 }, | |
322 | .m1 = { .min = 16, .max = 23 }, | |
323 | .m2 = { .min = 5, .max = 11 }, | |
324 | .p = { .min = 5, .max = 80 }, | |
325 | .p1 = { .min = 1, .max = 8}, | |
326 | .p2 = { .dot_limit = 165000, | |
327 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
328 | }; |
329 | ||
330 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
331 | .dot = { .min = 20000, .max = 115000 }, |
332 | .vco = { .min = 1750000, .max = 3500000 }, | |
333 | .n = { .min = 1, .max = 3 }, | |
334 | .m = { .min = 104, .max = 138 }, | |
335 | .m1 = { .min = 17, .max = 23 }, | |
336 | .m2 = { .min = 5, .max = 11 }, | |
337 | .p = { .min = 28, .max = 112 }, | |
338 | .p1 = { .min = 2, .max = 8 }, | |
339 | .p2 = { .dot_limit = 0, | |
340 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 341 | }, |
e4b36699 KP |
342 | }; |
343 | ||
344 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
345 | .dot = { .min = 80000, .max = 224000 }, |
346 | .vco = { .min = 1750000, .max = 3500000 }, | |
347 | .n = { .min = 1, .max = 3 }, | |
348 | .m = { .min = 104, .max = 138 }, | |
349 | .m1 = { .min = 17, .max = 23 }, | |
350 | .m2 = { .min = 5, .max = 11 }, | |
351 | .p = { .min = 14, .max = 42 }, | |
352 | .p1 = { .min = 2, .max = 6 }, | |
353 | .p2 = { .dot_limit = 0, | |
354 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 355 | }, |
e4b36699 KP |
356 | }; |
357 | ||
f2b115e6 | 358 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
359 | .dot = { .min = 20000, .max = 400000}, |
360 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 361 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
362 | .n = { .min = 3, .max = 6 }, |
363 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 364 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
365 | .m1 = { .min = 0, .max = 0 }, |
366 | .m2 = { .min = 0, .max = 254 }, | |
367 | .p = { .min = 5, .max = 80 }, | |
368 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
369 | .p2 = { .dot_limit = 200000, |
370 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
371 | }; |
372 | ||
f2b115e6 | 373 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
374 | .dot = { .min = 20000, .max = 400000 }, |
375 | .vco = { .min = 1700000, .max = 3500000 }, | |
376 | .n = { .min = 3, .max = 6 }, | |
377 | .m = { .min = 2, .max = 256 }, | |
378 | .m1 = { .min = 0, .max = 0 }, | |
379 | .m2 = { .min = 0, .max = 254 }, | |
380 | .p = { .min = 7, .max = 112 }, | |
381 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
382 | .p2 = { .dot_limit = 112000, |
383 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
384 | }; |
385 | ||
273e27ca EA |
386 | /* Ironlake / Sandybridge |
387 | * | |
388 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
389 | * the range value for them is (actual_value - 2). | |
390 | */ | |
b91ad0ec | 391 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
392 | .dot = { .min = 25000, .max = 350000 }, |
393 | .vco = { .min = 1760000, .max = 3510000 }, | |
394 | .n = { .min = 1, .max = 5 }, | |
395 | .m = { .min = 79, .max = 127 }, | |
396 | .m1 = { .min = 12, .max = 22 }, | |
397 | .m2 = { .min = 5, .max = 9 }, | |
398 | .p = { .min = 5, .max = 80 }, | |
399 | .p1 = { .min = 1, .max = 8 }, | |
400 | .p2 = { .dot_limit = 225000, | |
401 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
402 | }; |
403 | ||
b91ad0ec | 404 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
405 | .dot = { .min = 25000, .max = 350000 }, |
406 | .vco = { .min = 1760000, .max = 3510000 }, | |
407 | .n = { .min = 1, .max = 3 }, | |
408 | .m = { .min = 79, .max = 118 }, | |
409 | .m1 = { .min = 12, .max = 22 }, | |
410 | .m2 = { .min = 5, .max = 9 }, | |
411 | .p = { .min = 28, .max = 112 }, | |
412 | .p1 = { .min = 2, .max = 8 }, | |
413 | .p2 = { .dot_limit = 225000, | |
414 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
415 | }; |
416 | ||
417 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
418 | .dot = { .min = 25000, .max = 350000 }, |
419 | .vco = { .min = 1760000, .max = 3510000 }, | |
420 | .n = { .min = 1, .max = 3 }, | |
421 | .m = { .min = 79, .max = 127 }, | |
422 | .m1 = { .min = 12, .max = 22 }, | |
423 | .m2 = { .min = 5, .max = 9 }, | |
424 | .p = { .min = 14, .max = 56 }, | |
425 | .p1 = { .min = 2, .max = 8 }, | |
426 | .p2 = { .dot_limit = 225000, | |
427 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
428 | }; |
429 | ||
273e27ca | 430 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 431 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
432 | .dot = { .min = 25000, .max = 350000 }, |
433 | .vco = { .min = 1760000, .max = 3510000 }, | |
434 | .n = { .min = 1, .max = 2 }, | |
435 | .m = { .min = 79, .max = 126 }, | |
436 | .m1 = { .min = 12, .max = 22 }, | |
437 | .m2 = { .min = 5, .max = 9 }, | |
438 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 439 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
440 | .p2 = { .dot_limit = 225000, |
441 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
442 | }; |
443 | ||
444 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
445 | .dot = { .min = 25000, .max = 350000 }, |
446 | .vco = { .min = 1760000, .max = 3510000 }, | |
447 | .n = { .min = 1, .max = 3 }, | |
448 | .m = { .min = 79, .max = 126 }, | |
449 | .m1 = { .min = 12, .max = 22 }, | |
450 | .m2 = { .min = 5, .max = 9 }, | |
451 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 452 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
453 | .p2 = { .dot_limit = 225000, |
454 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
455 | }; |
456 | ||
dc730512 | 457 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
458 | /* |
459 | * These are the data rate limits (measured in fast clocks) | |
460 | * since those are the strictest limits we have. The fast | |
461 | * clock and actual rate limits are more relaxed, so checking | |
462 | * them would make no difference. | |
463 | */ | |
464 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 465 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 466 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
467 | .m1 = { .min = 2, .max = 3 }, |
468 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 469 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 470 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
471 | }; |
472 | ||
ef9348c8 CML |
473 | static const intel_limit_t intel_limits_chv = { |
474 | /* | |
475 | * These are the data rate limits (measured in fast clocks) | |
476 | * since those are the strictest limits we have. The fast | |
477 | * clock and actual rate limits are more relaxed, so checking | |
478 | * them would make no difference. | |
479 | */ | |
480 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
17fe1021 | 481 | .vco = { .min = 4800000, .max = 6480000 }, |
ef9348c8 CML |
482 | .n = { .min = 1, .max = 1 }, |
483 | .m1 = { .min = 2, .max = 2 }, | |
484 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
485 | .p1 = { .min = 2, .max = 4 }, | |
486 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
487 | }; | |
488 | ||
5ab7b0b7 ID |
489 | static const intel_limit_t intel_limits_bxt = { |
490 | /* FIXME: find real dot limits */ | |
491 | .dot = { .min = 0, .max = INT_MAX }, | |
e6292556 | 492 | .vco = { .min = 4800000, .max = 6700000 }, |
5ab7b0b7 ID |
493 | .n = { .min = 1, .max = 1 }, |
494 | .m1 = { .min = 2, .max = 2 }, | |
495 | /* FIXME: find real m2 limits */ | |
496 | .m2 = { .min = 2 << 22, .max = 255 << 22 }, | |
497 | .p1 = { .min = 2, .max = 4 }, | |
498 | .p2 = { .p2_slow = 1, .p2_fast = 20 }, | |
499 | }; | |
500 | ||
cdba954e ACO |
501 | static bool |
502 | needs_modeset(struct drm_crtc_state *state) | |
503 | { | |
fc596660 | 504 | return drm_atomic_crtc_needs_modeset(state); |
cdba954e ACO |
505 | } |
506 | ||
e0638cdf PZ |
507 | /** |
508 | * Returns whether any output on the specified pipe is of the specified type | |
509 | */ | |
4093561b | 510 | bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type) |
e0638cdf | 511 | { |
409ee761 | 512 | struct drm_device *dev = crtc->base.dev; |
e0638cdf PZ |
513 | struct intel_encoder *encoder; |
514 | ||
409ee761 | 515 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
e0638cdf PZ |
516 | if (encoder->type == type) |
517 | return true; | |
518 | ||
519 | return false; | |
520 | } | |
521 | ||
d0737e1d ACO |
522 | /** |
523 | * Returns whether any output on the specified pipe will have the specified | |
524 | * type after a staged modeset is complete, i.e., the same as | |
525 | * intel_pipe_has_type() but looking at encoder->new_crtc instead of | |
526 | * encoder->crtc. | |
527 | */ | |
a93e255f ACO |
528 | static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state, |
529 | int type) | |
d0737e1d | 530 | { |
a93e255f | 531 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 532 | struct drm_connector *connector; |
a93e255f | 533 | struct drm_connector_state *connector_state; |
d0737e1d | 534 | struct intel_encoder *encoder; |
a93e255f ACO |
535 | int i, num_connectors = 0; |
536 | ||
da3ced29 | 537 | for_each_connector_in_state(state, connector, connector_state, i) { |
a93e255f ACO |
538 | if (connector_state->crtc != crtc_state->base.crtc) |
539 | continue; | |
540 | ||
541 | num_connectors++; | |
d0737e1d | 542 | |
a93e255f ACO |
543 | encoder = to_intel_encoder(connector_state->best_encoder); |
544 | if (encoder->type == type) | |
d0737e1d | 545 | return true; |
a93e255f ACO |
546 | } |
547 | ||
548 | WARN_ON(num_connectors == 0); | |
d0737e1d ACO |
549 | |
550 | return false; | |
551 | } | |
552 | ||
a93e255f ACO |
553 | static const intel_limit_t * |
554 | intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk) | |
2c07245f | 555 | { |
a93e255f | 556 | struct drm_device *dev = crtc_state->base.crtc->dev; |
2c07245f | 557 | const intel_limit_t *limit; |
b91ad0ec | 558 | |
a93e255f | 559 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 560 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 561 | if (refclk == 100000) |
b91ad0ec ZW |
562 | limit = &intel_limits_ironlake_dual_lvds_100m; |
563 | else | |
564 | limit = &intel_limits_ironlake_dual_lvds; | |
565 | } else { | |
1b894b59 | 566 | if (refclk == 100000) |
b91ad0ec ZW |
567 | limit = &intel_limits_ironlake_single_lvds_100m; |
568 | else | |
569 | limit = &intel_limits_ironlake_single_lvds; | |
570 | } | |
c6bb3538 | 571 | } else |
b91ad0ec | 572 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
573 | |
574 | return limit; | |
575 | } | |
576 | ||
a93e255f ACO |
577 | static const intel_limit_t * |
578 | intel_g4x_limit(struct intel_crtc_state *crtc_state) | |
044c7c41 | 579 | { |
a93e255f | 580 | struct drm_device *dev = crtc_state->base.crtc->dev; |
044c7c41 ML |
581 | const intel_limit_t *limit; |
582 | ||
a93e255f | 583 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
1974cad0 | 584 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 585 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 586 | else |
e4b36699 | 587 | limit = &intel_limits_g4x_single_channel_lvds; |
a93e255f ACO |
588 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) || |
589 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 590 | limit = &intel_limits_g4x_hdmi; |
a93e255f | 591 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 592 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 593 | } else /* The option is for other outputs */ |
e4b36699 | 594 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
595 | |
596 | return limit; | |
597 | } | |
598 | ||
a93e255f ACO |
599 | static const intel_limit_t * |
600 | intel_limit(struct intel_crtc_state *crtc_state, int refclk) | |
79e53945 | 601 | { |
a93e255f | 602 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 JB |
603 | const intel_limit_t *limit; |
604 | ||
5ab7b0b7 ID |
605 | if (IS_BROXTON(dev)) |
606 | limit = &intel_limits_bxt; | |
607 | else if (HAS_PCH_SPLIT(dev)) | |
a93e255f | 608 | limit = intel_ironlake_limit(crtc_state, refclk); |
2c07245f | 609 | else if (IS_G4X(dev)) { |
a93e255f | 610 | limit = intel_g4x_limit(crtc_state); |
f2b115e6 | 611 | } else if (IS_PINEVIEW(dev)) { |
a93e255f | 612 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 613 | limit = &intel_limits_pineview_lvds; |
2177832f | 614 | else |
f2b115e6 | 615 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
616 | } else if (IS_CHERRYVIEW(dev)) { |
617 | limit = &intel_limits_chv; | |
a0c4da24 | 618 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 619 | limit = &intel_limits_vlv; |
a6c45cf0 | 620 | } else if (!IS_GEN2(dev)) { |
a93e255f | 621 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
a6c45cf0 CW |
622 | limit = &intel_limits_i9xx_lvds; |
623 | else | |
624 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 | 625 | } else { |
a93e255f | 626 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
e4b36699 | 627 | limit = &intel_limits_i8xx_lvds; |
a93e255f | 628 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
e4b36699 | 629 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
630 | else |
631 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
632 | } |
633 | return limit; | |
634 | } | |
635 | ||
dccbea3b ID |
636 | /* |
637 | * Platform specific helpers to calculate the port PLL loopback- (clock.m), | |
638 | * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast | |
639 | * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. | |
640 | * The helpers' return value is the rate of the clock that is fed to the | |
641 | * display engine's pipe which can be the above fast dot clock rate or a | |
642 | * divided-down version of it. | |
643 | */ | |
f2b115e6 | 644 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
dccbea3b | 645 | static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock) |
79e53945 | 646 | { |
2177832f SL |
647 | clock->m = clock->m2 + 2; |
648 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e | 649 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
dccbea3b | 650 | return 0; |
fb03ac01 VS |
651 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
652 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
653 | |
654 | return clock->dot; | |
2177832f SL |
655 | } |
656 | ||
7429e9d4 DV |
657 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
658 | { | |
659 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
660 | } | |
661 | ||
dccbea3b | 662 | static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock) |
2177832f | 663 | { |
7429e9d4 | 664 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 665 | clock->p = clock->p1 * clock->p2; |
ed5ca77e | 666 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
dccbea3b | 667 | return 0; |
fb03ac01 VS |
668 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
669 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
670 | |
671 | return clock->dot; | |
79e53945 JB |
672 | } |
673 | ||
dccbea3b | 674 | static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock) |
589eca67 ID |
675 | { |
676 | clock->m = clock->m1 * clock->m2; | |
677 | clock->p = clock->p1 * clock->p2; | |
678 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 679 | return 0; |
589eca67 ID |
680 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
681 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
682 | |
683 | return clock->dot / 5; | |
589eca67 ID |
684 | } |
685 | ||
dccbea3b | 686 | int chv_calc_dpll_params(int refclk, intel_clock_t *clock) |
ef9348c8 CML |
687 | { |
688 | clock->m = clock->m1 * clock->m2; | |
689 | clock->p = clock->p1 * clock->p2; | |
690 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
dccbea3b | 691 | return 0; |
ef9348c8 CML |
692 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, |
693 | clock->n << 22); | |
694 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
dccbea3b ID |
695 | |
696 | return clock->dot / 5; | |
ef9348c8 CML |
697 | } |
698 | ||
7c04d1d9 | 699 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
700 | /** |
701 | * Returns whether the given set of divisors are valid for a given refclk with | |
702 | * the given connectors. | |
703 | */ | |
704 | ||
1b894b59 CW |
705 | static bool intel_PLL_is_valid(struct drm_device *dev, |
706 | const intel_limit_t *limit, | |
707 | const intel_clock_t *clock) | |
79e53945 | 708 | { |
f01b7962 VS |
709 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
710 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 711 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 712 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 713 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 714 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 715 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 716 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 | 717 | |
666a4537 WB |
718 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && |
719 | !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) | |
f01b7962 VS |
720 | if (clock->m1 <= clock->m2) |
721 | INTELPllInvalid("m1 <= m2\n"); | |
722 | ||
666a4537 | 723 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) { |
f01b7962 VS |
724 | if (clock->p < limit->p.min || limit->p.max < clock->p) |
725 | INTELPllInvalid("p out of range\n"); | |
726 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
727 | INTELPllInvalid("m out of range\n"); | |
728 | } | |
729 | ||
79e53945 | 730 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 731 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
732 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
733 | * connector, etc., rather than just a single range. | |
734 | */ | |
735 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 736 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
737 | |
738 | return true; | |
739 | } | |
740 | ||
3b1429d9 VS |
741 | static int |
742 | i9xx_select_p2_div(const intel_limit_t *limit, | |
743 | const struct intel_crtc_state *crtc_state, | |
744 | int target) | |
79e53945 | 745 | { |
3b1429d9 | 746 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 747 | |
a93e255f | 748 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
79e53945 | 749 | /* |
a210b028 DV |
750 | * For LVDS just rely on its current settings for dual-channel. |
751 | * We haven't figured out how to reliably set up different | |
752 | * single/dual channel state, if we even can. | |
79e53945 | 753 | */ |
1974cad0 | 754 | if (intel_is_dual_link_lvds(dev)) |
3b1429d9 | 755 | return limit->p2.p2_fast; |
79e53945 | 756 | else |
3b1429d9 | 757 | return limit->p2.p2_slow; |
79e53945 JB |
758 | } else { |
759 | if (target < limit->p2.dot_limit) | |
3b1429d9 | 760 | return limit->p2.p2_slow; |
79e53945 | 761 | else |
3b1429d9 | 762 | return limit->p2.p2_fast; |
79e53945 | 763 | } |
3b1429d9 VS |
764 | } |
765 | ||
766 | static bool | |
767 | i9xx_find_best_dpll(const intel_limit_t *limit, | |
768 | struct intel_crtc_state *crtc_state, | |
769 | int target, int refclk, intel_clock_t *match_clock, | |
770 | intel_clock_t *best_clock) | |
771 | { | |
772 | struct drm_device *dev = crtc_state->base.crtc->dev; | |
773 | intel_clock_t clock; | |
774 | int err = target; | |
79e53945 | 775 | |
0206e353 | 776 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 777 | |
3b1429d9 VS |
778 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
779 | ||
42158660 ZY |
780 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
781 | clock.m1++) { | |
782 | for (clock.m2 = limit->m2.min; | |
783 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 784 | if (clock.m2 >= clock.m1) |
42158660 ZY |
785 | break; |
786 | for (clock.n = limit->n.min; | |
787 | clock.n <= limit->n.max; clock.n++) { | |
788 | for (clock.p1 = limit->p1.min; | |
789 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
790 | int this_err; |
791 | ||
dccbea3b | 792 | i9xx_calc_dpll_params(refclk, &clock); |
ac58c3f0 DV |
793 | if (!intel_PLL_is_valid(dev, limit, |
794 | &clock)) | |
795 | continue; | |
796 | if (match_clock && | |
797 | clock.p != match_clock->p) | |
798 | continue; | |
799 | ||
800 | this_err = abs(clock.dot - target); | |
801 | if (this_err < err) { | |
802 | *best_clock = clock; | |
803 | err = this_err; | |
804 | } | |
805 | } | |
806 | } | |
807 | } | |
808 | } | |
809 | ||
810 | return (err != target); | |
811 | } | |
812 | ||
813 | static bool | |
a93e255f ACO |
814 | pnv_find_best_dpll(const intel_limit_t *limit, |
815 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
816 | int target, int refclk, intel_clock_t *match_clock, |
817 | intel_clock_t *best_clock) | |
79e53945 | 818 | { |
3b1429d9 | 819 | struct drm_device *dev = crtc_state->base.crtc->dev; |
79e53945 | 820 | intel_clock_t clock; |
79e53945 JB |
821 | int err = target; |
822 | ||
0206e353 | 823 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 824 | |
3b1429d9 VS |
825 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); |
826 | ||
42158660 ZY |
827 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
828 | clock.m1++) { | |
829 | for (clock.m2 = limit->m2.min; | |
830 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
831 | for (clock.n = limit->n.min; |
832 | clock.n <= limit->n.max; clock.n++) { | |
833 | for (clock.p1 = limit->p1.min; | |
834 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
835 | int this_err; |
836 | ||
dccbea3b | 837 | pnv_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
838 | if (!intel_PLL_is_valid(dev, limit, |
839 | &clock)) | |
79e53945 | 840 | continue; |
cec2f356 SP |
841 | if (match_clock && |
842 | clock.p != match_clock->p) | |
843 | continue; | |
79e53945 JB |
844 | |
845 | this_err = abs(clock.dot - target); | |
846 | if (this_err < err) { | |
847 | *best_clock = clock; | |
848 | err = this_err; | |
849 | } | |
850 | } | |
851 | } | |
852 | } | |
853 | } | |
854 | ||
855 | return (err != target); | |
856 | } | |
857 | ||
d4906093 | 858 | static bool |
a93e255f ACO |
859 | g4x_find_best_dpll(const intel_limit_t *limit, |
860 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
861 | int target, int refclk, intel_clock_t *match_clock, |
862 | intel_clock_t *best_clock) | |
d4906093 | 863 | { |
3b1429d9 | 864 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d4906093 ML |
865 | intel_clock_t clock; |
866 | int max_n; | |
3b1429d9 | 867 | bool found = false; |
6ba770dc AJ |
868 | /* approximately equals target * 0.00585 */ |
869 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
870 | |
871 | memset(best_clock, 0, sizeof(*best_clock)); | |
3b1429d9 VS |
872 | |
873 | clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); | |
874 | ||
d4906093 | 875 | max_n = limit->n.max; |
f77f13e2 | 876 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 877 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 878 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
879 | for (clock.m1 = limit->m1.max; |
880 | clock.m1 >= limit->m1.min; clock.m1--) { | |
881 | for (clock.m2 = limit->m2.max; | |
882 | clock.m2 >= limit->m2.min; clock.m2--) { | |
883 | for (clock.p1 = limit->p1.max; | |
884 | clock.p1 >= limit->p1.min; clock.p1--) { | |
885 | int this_err; | |
886 | ||
dccbea3b | 887 | i9xx_calc_dpll_params(refclk, &clock); |
1b894b59 CW |
888 | if (!intel_PLL_is_valid(dev, limit, |
889 | &clock)) | |
d4906093 | 890 | continue; |
1b894b59 CW |
891 | |
892 | this_err = abs(clock.dot - target); | |
d4906093 ML |
893 | if (this_err < err_most) { |
894 | *best_clock = clock; | |
895 | err_most = this_err; | |
896 | max_n = clock.n; | |
897 | found = true; | |
898 | } | |
899 | } | |
900 | } | |
901 | } | |
902 | } | |
2c07245f ZW |
903 | return found; |
904 | } | |
905 | ||
d5dd62bd ID |
906 | /* |
907 | * Check if the calculated PLL configuration is more optimal compared to the | |
908 | * best configuration and error found so far. Return the calculated error. | |
909 | */ | |
910 | static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, | |
911 | const intel_clock_t *calculated_clock, | |
912 | const intel_clock_t *best_clock, | |
913 | unsigned int best_error_ppm, | |
914 | unsigned int *error_ppm) | |
915 | { | |
9ca3ba01 ID |
916 | /* |
917 | * For CHV ignore the error and consider only the P value. | |
918 | * Prefer a bigger P value based on HW requirements. | |
919 | */ | |
920 | if (IS_CHERRYVIEW(dev)) { | |
921 | *error_ppm = 0; | |
922 | ||
923 | return calculated_clock->p > best_clock->p; | |
924 | } | |
925 | ||
24be4e46 ID |
926 | if (WARN_ON_ONCE(!target_freq)) |
927 | return false; | |
928 | ||
d5dd62bd ID |
929 | *error_ppm = div_u64(1000000ULL * |
930 | abs(target_freq - calculated_clock->dot), | |
931 | target_freq); | |
932 | /* | |
933 | * Prefer a better P value over a better (smaller) error if the error | |
934 | * is small. Ensure this preference for future configurations too by | |
935 | * setting the error to 0. | |
936 | */ | |
937 | if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { | |
938 | *error_ppm = 0; | |
939 | ||
940 | return true; | |
941 | } | |
942 | ||
943 | return *error_ppm + 10 < best_error_ppm; | |
944 | } | |
945 | ||
a0c4da24 | 946 | static bool |
a93e255f ACO |
947 | vlv_find_best_dpll(const intel_limit_t *limit, |
948 | struct intel_crtc_state *crtc_state, | |
ee9300bb DV |
949 | int target, int refclk, intel_clock_t *match_clock, |
950 | intel_clock_t *best_clock) | |
a0c4da24 | 951 | { |
a93e255f | 952 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 953 | struct drm_device *dev = crtc->base.dev; |
6b4bf1c4 | 954 | intel_clock_t clock; |
69e4f900 | 955 | unsigned int bestppm = 1000000; |
27e639bf VS |
956 | /* min update 19.2 MHz */ |
957 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 958 | bool found = false; |
a0c4da24 | 959 | |
6b4bf1c4 VS |
960 | target *= 5; /* fast clock */ |
961 | ||
962 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
963 | |
964 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 965 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 966 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 967 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 968 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 969 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 970 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 971 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
d5dd62bd | 972 | unsigned int ppm; |
69e4f900 | 973 | |
6b4bf1c4 VS |
974 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
975 | refclk * clock.m1); | |
976 | ||
dccbea3b | 977 | vlv_calc_dpll_params(refclk, &clock); |
43b0ac53 | 978 | |
f01b7962 VS |
979 | if (!intel_PLL_is_valid(dev, limit, |
980 | &clock)) | |
43b0ac53 VS |
981 | continue; |
982 | ||
d5dd62bd ID |
983 | if (!vlv_PLL_is_optimal(dev, target, |
984 | &clock, | |
985 | best_clock, | |
986 | bestppm, &ppm)) | |
987 | continue; | |
6b4bf1c4 | 988 | |
d5dd62bd ID |
989 | *best_clock = clock; |
990 | bestppm = ppm; | |
991 | found = true; | |
a0c4da24 JB |
992 | } |
993 | } | |
994 | } | |
995 | } | |
a0c4da24 | 996 | |
49e497ef | 997 | return found; |
a0c4da24 | 998 | } |
a4fc5ed6 | 999 | |
ef9348c8 | 1000 | static bool |
a93e255f ACO |
1001 | chv_find_best_dpll(const intel_limit_t *limit, |
1002 | struct intel_crtc_state *crtc_state, | |
ef9348c8 CML |
1003 | int target, int refclk, intel_clock_t *match_clock, |
1004 | intel_clock_t *best_clock) | |
1005 | { | |
a93e255f | 1006 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
a919ff14 | 1007 | struct drm_device *dev = crtc->base.dev; |
9ca3ba01 | 1008 | unsigned int best_error_ppm; |
ef9348c8 CML |
1009 | intel_clock_t clock; |
1010 | uint64_t m2; | |
1011 | int found = false; | |
1012 | ||
1013 | memset(best_clock, 0, sizeof(*best_clock)); | |
9ca3ba01 | 1014 | best_error_ppm = 1000000; |
ef9348c8 CML |
1015 | |
1016 | /* | |
1017 | * Based on hardware doc, the n always set to 1, and m1 always | |
1018 | * set to 2. If requires to support 200Mhz refclk, we need to | |
1019 | * revisit this because n may not 1 anymore. | |
1020 | */ | |
1021 | clock.n = 1, clock.m1 = 2; | |
1022 | target *= 5; /* fast clock */ | |
1023 | ||
1024 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
1025 | for (clock.p2 = limit->p2.p2_fast; | |
1026 | clock.p2 >= limit->p2.p2_slow; | |
1027 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
9ca3ba01 | 1028 | unsigned int error_ppm; |
ef9348c8 CML |
1029 | |
1030 | clock.p = clock.p1 * clock.p2; | |
1031 | ||
1032 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
1033 | clock.n) << 22, refclk * clock.m1); | |
1034 | ||
1035 | if (m2 > INT_MAX/clock.m1) | |
1036 | continue; | |
1037 | ||
1038 | clock.m2 = m2; | |
1039 | ||
dccbea3b | 1040 | chv_calc_dpll_params(refclk, &clock); |
ef9348c8 CML |
1041 | |
1042 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
1043 | continue; | |
1044 | ||
9ca3ba01 ID |
1045 | if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, |
1046 | best_error_ppm, &error_ppm)) | |
1047 | continue; | |
1048 | ||
1049 | *best_clock = clock; | |
1050 | best_error_ppm = error_ppm; | |
1051 | found = true; | |
ef9348c8 CML |
1052 | } |
1053 | } | |
1054 | ||
1055 | return found; | |
1056 | } | |
1057 | ||
5ab7b0b7 ID |
1058 | bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock, |
1059 | intel_clock_t *best_clock) | |
1060 | { | |
1061 | int refclk = i9xx_get_refclk(crtc_state, 0); | |
1062 | ||
1063 | return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state, | |
1064 | target_clock, refclk, NULL, best_clock); | |
1065 | } | |
1066 | ||
20ddf665 VS |
1067 | bool intel_crtc_active(struct drm_crtc *crtc) |
1068 | { | |
1069 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1070 | ||
1071 | /* Be paranoid as we can arrive here with only partial | |
1072 | * state retrieved from the hardware during setup. | |
1073 | * | |
241bfc38 | 1074 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
1075 | * as Haswell has gained clock readout/fastboot support. |
1076 | * | |
66e514c1 | 1077 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 | 1078 | * properly reconstruct framebuffers. |
c3d1f436 MR |
1079 | * |
1080 | * FIXME: The intel_crtc->active here should be switched to | |
1081 | * crtc->state->active once we have proper CRTC states wired up | |
1082 | * for atomic. | |
20ddf665 | 1083 | */ |
c3d1f436 | 1084 | return intel_crtc->active && crtc->primary->state->fb && |
6e3c9717 | 1085 | intel_crtc->config->base.adjusted_mode.crtc_clock; |
20ddf665 VS |
1086 | } |
1087 | ||
a5c961d1 PZ |
1088 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
1089 | enum pipe pipe) | |
1090 | { | |
1091 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1092 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1093 | ||
6e3c9717 | 1094 | return intel_crtc->config->cpu_transcoder; |
a5c961d1 PZ |
1095 | } |
1096 | ||
fbf49ea2 VS |
1097 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
1098 | { | |
1099 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1100 | i915_reg_t reg = PIPEDSL(pipe); |
fbf49ea2 VS |
1101 | u32 line1, line2; |
1102 | u32 line_mask; | |
1103 | ||
1104 | if (IS_GEN2(dev)) | |
1105 | line_mask = DSL_LINEMASK_GEN2; | |
1106 | else | |
1107 | line_mask = DSL_LINEMASK_GEN3; | |
1108 | ||
1109 | line1 = I915_READ(reg) & line_mask; | |
6adfb1ef | 1110 | msleep(5); |
fbf49ea2 VS |
1111 | line2 = I915_READ(reg) & line_mask; |
1112 | ||
1113 | return line1 == line2; | |
1114 | } | |
1115 | ||
ab7ad7f6 KP |
1116 | /* |
1117 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 1118 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
1119 | * |
1120 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
1121 | * spinning on the vblank interrupt status bit, since we won't actually | |
1122 | * see an interrupt when the pipe is disabled. | |
1123 | * | |
ab7ad7f6 KP |
1124 | * On Gen4 and above: |
1125 | * wait for the pipe register state bit to turn off | |
1126 | * | |
1127 | * Otherwise: | |
1128 | * wait for the display line value to settle (it usually | |
1129 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 1130 | * |
9d0498a2 | 1131 | */ |
575f7ab7 | 1132 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 1133 | { |
575f7ab7 | 1134 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 1135 | struct drm_i915_private *dev_priv = dev->dev_private; |
6e3c9717 | 1136 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 1137 | enum pipe pipe = crtc->pipe; |
ab7ad7f6 KP |
1138 | |
1139 | if (INTEL_INFO(dev)->gen >= 4) { | |
f0f59a00 | 1140 | i915_reg_t reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
1141 | |
1142 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
1143 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
1144 | 100)) | |
284637d9 | 1145 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1146 | } else { |
ab7ad7f6 | 1147 | /* Wait for the display line to settle */ |
fbf49ea2 | 1148 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1149 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1150 | } |
79e53945 JB |
1151 | } |
1152 | ||
b24e7179 | 1153 | /* Only for pre-ILK configs */ |
55607e8a DV |
1154 | void assert_pll(struct drm_i915_private *dev_priv, |
1155 | enum pipe pipe, bool state) | |
b24e7179 | 1156 | { |
b24e7179 JB |
1157 | u32 val; |
1158 | bool cur_state; | |
1159 | ||
649636ef | 1160 | val = I915_READ(DPLL(pipe)); |
b24e7179 | 1161 | cur_state = !!(val & DPLL_VCO_ENABLE); |
e2c719b7 | 1162 | I915_STATE_WARN(cur_state != state, |
b24e7179 | 1163 | "PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1164 | onoff(state), onoff(cur_state)); |
b24e7179 | 1165 | } |
b24e7179 | 1166 | |
23538ef1 JN |
1167 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1168 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1169 | { | |
1170 | u32 val; | |
1171 | bool cur_state; | |
1172 | ||
a580516d | 1173 | mutex_lock(&dev_priv->sb_lock); |
23538ef1 | 1174 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); |
a580516d | 1175 | mutex_unlock(&dev_priv->sb_lock); |
23538ef1 JN |
1176 | |
1177 | cur_state = val & DSI_PLL_VCO_EN; | |
e2c719b7 | 1178 | I915_STATE_WARN(cur_state != state, |
23538ef1 | 1179 | "DSI PLL state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1180 | onoff(state), onoff(cur_state)); |
23538ef1 JN |
1181 | } |
1182 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1183 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1184 | ||
55607e8a | 1185 | struct intel_shared_dpll * |
e2b78267 DV |
1186 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1187 | { | |
1188 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1189 | ||
6e3c9717 | 1190 | if (crtc->config->shared_dpll < 0) |
e2b78267 DV |
1191 | return NULL; |
1192 | ||
6e3c9717 | 1193 | return &dev_priv->shared_dplls[crtc->config->shared_dpll]; |
e2b78267 DV |
1194 | } |
1195 | ||
040484af | 1196 | /* For ILK+ */ |
55607e8a DV |
1197 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1198 | struct intel_shared_dpll *pll, | |
1199 | bool state) | |
040484af | 1200 | { |
040484af | 1201 | bool cur_state; |
5358901f | 1202 | struct intel_dpll_hw_state hw_state; |
040484af | 1203 | |
87ad3212 | 1204 | if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state))) |
ee7b9f93 | 1205 | return; |
ee7b9f93 | 1206 | |
5358901f | 1207 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
e2c719b7 | 1208 | I915_STATE_WARN(cur_state != state, |
5358901f | 1209 | "%s assertion failure (expected %s, current %s)\n", |
87ad3212 | 1210 | pll->name, onoff(state), onoff(cur_state)); |
040484af | 1211 | } |
040484af JB |
1212 | |
1213 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1214 | enum pipe pipe, bool state) | |
1215 | { | |
040484af | 1216 | bool cur_state; |
ad80a810 PZ |
1217 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1218 | pipe); | |
040484af | 1219 | |
affa9354 PZ |
1220 | if (HAS_DDI(dev_priv->dev)) { |
1221 | /* DDI does not have a specific FDI_TX register */ | |
649636ef | 1222 | u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); |
ad80a810 | 1223 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 | 1224 | } else { |
649636ef | 1225 | u32 val = I915_READ(FDI_TX_CTL(pipe)); |
bf507ef7 ED |
1226 | cur_state = !!(val & FDI_TX_ENABLE); |
1227 | } | |
e2c719b7 | 1228 | I915_STATE_WARN(cur_state != state, |
040484af | 1229 | "FDI TX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1230 | onoff(state), onoff(cur_state)); |
040484af JB |
1231 | } |
1232 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1233 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1234 | ||
1235 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1236 | enum pipe pipe, bool state) | |
1237 | { | |
040484af JB |
1238 | u32 val; |
1239 | bool cur_state; | |
1240 | ||
649636ef | 1241 | val = I915_READ(FDI_RX_CTL(pipe)); |
d63fa0dc | 1242 | cur_state = !!(val & FDI_RX_ENABLE); |
e2c719b7 | 1243 | I915_STATE_WARN(cur_state != state, |
040484af | 1244 | "FDI RX state assertion failure (expected %s, current %s)\n", |
87ad3212 | 1245 | onoff(state), onoff(cur_state)); |
040484af JB |
1246 | } |
1247 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1248 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1249 | ||
1250 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1251 | enum pipe pipe) | |
1252 | { | |
040484af JB |
1253 | u32 val; |
1254 | ||
1255 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1256 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1257 | return; |
1258 | ||
bf507ef7 | 1259 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1260 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1261 | return; |
1262 | ||
649636ef | 1263 | val = I915_READ(FDI_TX_CTL(pipe)); |
e2c719b7 | 1264 | I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); |
040484af JB |
1265 | } |
1266 | ||
55607e8a DV |
1267 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1268 | enum pipe pipe, bool state) | |
040484af | 1269 | { |
040484af | 1270 | u32 val; |
55607e8a | 1271 | bool cur_state; |
040484af | 1272 | |
649636ef | 1273 | val = I915_READ(FDI_RX_CTL(pipe)); |
55607e8a | 1274 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
e2c719b7 | 1275 | I915_STATE_WARN(cur_state != state, |
55607e8a | 1276 | "FDI RX PLL assertion failure (expected %s, current %s)\n", |
87ad3212 | 1277 | onoff(state), onoff(cur_state)); |
040484af JB |
1278 | } |
1279 | ||
b680c37a DV |
1280 | void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1281 | enum pipe pipe) | |
ea0760cf | 1282 | { |
bedd4dba | 1283 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 | 1284 | i915_reg_t pp_reg; |
ea0760cf JB |
1285 | u32 val; |
1286 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1287 | bool locked = true; |
ea0760cf | 1288 | |
bedd4dba JN |
1289 | if (WARN_ON(HAS_DDI(dev))) |
1290 | return; | |
1291 | ||
1292 | if (HAS_PCH_SPLIT(dev)) { | |
1293 | u32 port_sel; | |
1294 | ||
ea0760cf | 1295 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1296 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1297 | ||
1298 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1299 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1300 | panel_pipe = PIPE_B; | |
1301 | /* XXX: else fix for eDP */ | |
666a4537 | 1302 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
bedd4dba JN |
1303 | /* presumably write lock depends on pipe, not port select */ |
1304 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1305 | panel_pipe = pipe; | |
ea0760cf JB |
1306 | } else { |
1307 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1308 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1309 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1310 | } |
1311 | ||
1312 | val = I915_READ(pp_reg); | |
1313 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1314 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1315 | locked = false; |
1316 | ||
e2c719b7 | 1317 | I915_STATE_WARN(panel_pipe == pipe && locked, |
ea0760cf | 1318 | "panel assertion failure, pipe %c regs locked\n", |
9db4a9c7 | 1319 | pipe_name(pipe)); |
ea0760cf JB |
1320 | } |
1321 | ||
93ce0ba6 JN |
1322 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1323 | enum pipe pipe, bool state) | |
1324 | { | |
1325 | struct drm_device *dev = dev_priv->dev; | |
1326 | bool cur_state; | |
1327 | ||
d9d82081 | 1328 | if (IS_845G(dev) || IS_I865G(dev)) |
0b87c24e | 1329 | cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE; |
d9d82081 | 1330 | else |
5efb3e28 | 1331 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 | 1332 | |
e2c719b7 | 1333 | I915_STATE_WARN(cur_state != state, |
93ce0ba6 | 1334 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1335 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
93ce0ba6 JN |
1336 | } |
1337 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1338 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1339 | ||
b840d907 JB |
1340 | void assert_pipe(struct drm_i915_private *dev_priv, |
1341 | enum pipe pipe, bool state) | |
b24e7179 | 1342 | { |
63d7bbe9 | 1343 | bool cur_state; |
702e7a56 PZ |
1344 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1345 | pipe); | |
b24e7179 | 1346 | |
b6b5d049 VS |
1347 | /* if we need the pipe quirk it must be always on */ |
1348 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1349 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1350 | state = true; |
1351 | ||
f458ebbc | 1352 | if (!intel_display_power_is_enabled(dev_priv, |
b97186f0 | 1353 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1354 | cur_state = false; |
1355 | } else { | |
649636ef | 1356 | u32 val = I915_READ(PIPECONF(cpu_transcoder)); |
69310161 PZ |
1357 | cur_state = !!(val & PIPECONF_ENABLE); |
1358 | } | |
1359 | ||
e2c719b7 | 1360 | I915_STATE_WARN(cur_state != state, |
63d7bbe9 | 1361 | "pipe %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1362 | pipe_name(pipe), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1363 | } |
1364 | ||
931872fc CW |
1365 | static void assert_plane(struct drm_i915_private *dev_priv, |
1366 | enum plane plane, bool state) | |
b24e7179 | 1367 | { |
b24e7179 | 1368 | u32 val; |
931872fc | 1369 | bool cur_state; |
b24e7179 | 1370 | |
649636ef | 1371 | val = I915_READ(DSPCNTR(plane)); |
931872fc | 1372 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
e2c719b7 | 1373 | I915_STATE_WARN(cur_state != state, |
931872fc | 1374 | "plane %c assertion failure (expected %s, current %s)\n", |
87ad3212 | 1375 | plane_name(plane), onoff(state), onoff(cur_state)); |
b24e7179 JB |
1376 | } |
1377 | ||
931872fc CW |
1378 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1379 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1380 | ||
b24e7179 JB |
1381 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1382 | enum pipe pipe) | |
1383 | { | |
653e1026 | 1384 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1385 | int i; |
b24e7179 | 1386 | |
653e1026 VS |
1387 | /* Primary planes are fixed to pipes on gen4+ */ |
1388 | if (INTEL_INFO(dev)->gen >= 4) { | |
649636ef | 1389 | u32 val = I915_READ(DSPCNTR(pipe)); |
e2c719b7 | 1390 | I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1391 | "plane %c assertion failure, should be disabled but not\n", |
1392 | plane_name(pipe)); | |
19ec1358 | 1393 | return; |
28c05794 | 1394 | } |
19ec1358 | 1395 | |
b24e7179 | 1396 | /* Need to check both planes against the pipe */ |
055e393f | 1397 | for_each_pipe(dev_priv, i) { |
649636ef VS |
1398 | u32 val = I915_READ(DSPCNTR(i)); |
1399 | enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
b24e7179 | 1400 | DISPPLANE_SEL_PIPE_SHIFT; |
e2c719b7 | 1401 | I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, |
9db4a9c7 JB |
1402 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1403 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1404 | } |
1405 | } | |
1406 | ||
19332d7a JB |
1407 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1408 | enum pipe pipe) | |
1409 | { | |
20674eef | 1410 | struct drm_device *dev = dev_priv->dev; |
649636ef | 1411 | int sprite; |
19332d7a | 1412 | |
7feb8b88 | 1413 | if (INTEL_INFO(dev)->gen >= 9) { |
3bdcfc0c | 1414 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1415 | u32 val = I915_READ(PLANE_CTL(pipe, sprite)); |
e2c719b7 | 1416 | I915_STATE_WARN(val & PLANE_CTL_ENABLE, |
7feb8b88 DL |
1417 | "plane %d assertion failure, should be off on pipe %c but is still active\n", |
1418 | sprite, pipe_name(pipe)); | |
1419 | } | |
666a4537 | 1420 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
3bdcfc0c | 1421 | for_each_sprite(dev_priv, pipe, sprite) { |
649636ef | 1422 | u32 val = I915_READ(SPCNTR(pipe, sprite)); |
e2c719b7 | 1423 | I915_STATE_WARN(val & SP_ENABLE, |
20674eef | 1424 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1425 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1426 | } |
1427 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
649636ef | 1428 | u32 val = I915_READ(SPRCTL(pipe)); |
e2c719b7 | 1429 | I915_STATE_WARN(val & SPRITE_ENABLE, |
06da8da2 | 1430 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1431 | plane_name(pipe), pipe_name(pipe)); |
1432 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
649636ef | 1433 | u32 val = I915_READ(DVSCNTR(pipe)); |
e2c719b7 | 1434 | I915_STATE_WARN(val & DVS_ENABLE, |
06da8da2 | 1435 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1436 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1437 | } |
1438 | } | |
1439 | ||
08c71e5e VS |
1440 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1441 | { | |
e2c719b7 | 1442 | if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0)) |
08c71e5e VS |
1443 | drm_crtc_vblank_put(crtc); |
1444 | } | |
1445 | ||
89eff4be | 1446 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1447 | { |
1448 | u32 val; | |
1449 | bool enabled; | |
1450 | ||
e2c719b7 | 1451 | I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1452 | |
92f2584a JB |
1453 | val = I915_READ(PCH_DREF_CONTROL); |
1454 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1455 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
e2c719b7 | 1456 | I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); |
92f2584a JB |
1457 | } |
1458 | ||
ab9412ba DV |
1459 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1460 | enum pipe pipe) | |
92f2584a | 1461 | { |
92f2584a JB |
1462 | u32 val; |
1463 | bool enabled; | |
1464 | ||
649636ef | 1465 | val = I915_READ(PCH_TRANSCONF(pipe)); |
92f2584a | 1466 | enabled = !!(val & TRANS_ENABLE); |
e2c719b7 | 1467 | I915_STATE_WARN(enabled, |
9db4a9c7 JB |
1468 | "transcoder assertion failed, should be off on pipe %c but is still active\n", |
1469 | pipe_name(pipe)); | |
92f2584a JB |
1470 | } |
1471 | ||
4e634389 KP |
1472 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1473 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1474 | { |
1475 | if ((val & DP_PORT_EN) == 0) | |
1476 | return false; | |
1477 | ||
1478 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
f0f59a00 | 1479 | u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe)); |
f0575e92 KP |
1480 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) |
1481 | return false; | |
44f37d1f CML |
1482 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1483 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1484 | return false; | |
f0575e92 KP |
1485 | } else { |
1486 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1487 | return false; | |
1488 | } | |
1489 | return true; | |
1490 | } | |
1491 | ||
1519b995 KP |
1492 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1493 | enum pipe pipe, u32 val) | |
1494 | { | |
dc0fa718 | 1495 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1496 | return false; |
1497 | ||
1498 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1499 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1500 | return false; |
44f37d1f CML |
1501 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1502 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1503 | return false; | |
1519b995 | 1504 | } else { |
dc0fa718 | 1505 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1506 | return false; |
1507 | } | |
1508 | return true; | |
1509 | } | |
1510 | ||
1511 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1512 | enum pipe pipe, u32 val) | |
1513 | { | |
1514 | if ((val & LVDS_PORT_EN) == 0) | |
1515 | return false; | |
1516 | ||
1517 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1518 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1519 | return false; | |
1520 | } else { | |
1521 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1522 | return false; | |
1523 | } | |
1524 | return true; | |
1525 | } | |
1526 | ||
1527 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1528 | enum pipe pipe, u32 val) | |
1529 | { | |
1530 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1531 | return false; | |
1532 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1533 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1534 | return false; | |
1535 | } else { | |
1536 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1537 | return false; | |
1538 | } | |
1539 | return true; | |
1540 | } | |
1541 | ||
291906f1 | 1542 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0f59a00 VS |
1543 | enum pipe pipe, i915_reg_t reg, |
1544 | u32 port_sel) | |
291906f1 | 1545 | { |
47a05eca | 1546 | u32 val = I915_READ(reg); |
e2c719b7 | 1547 | I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1548 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1549 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1550 | |
e2c719b7 | 1551 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
75c5da27 | 1552 | && (val & DP_PIPEB_SELECT), |
de9a35ab | 1553 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1554 | } |
1555 | ||
1556 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
f0f59a00 | 1557 | enum pipe pipe, i915_reg_t reg) |
291906f1 | 1558 | { |
47a05eca | 1559 | u32 val = I915_READ(reg); |
e2c719b7 | 1560 | I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1561 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
f0f59a00 | 1562 | i915_mmio_reg_offset(reg), pipe_name(pipe)); |
de9a35ab | 1563 | |
e2c719b7 | 1564 | I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1565 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1566 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1567 | } |
1568 | ||
1569 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1570 | enum pipe pipe) | |
1571 | { | |
291906f1 | 1572 | u32 val; |
291906f1 | 1573 | |
f0575e92 KP |
1574 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1575 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1576 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 | 1577 | |
649636ef | 1578 | val = I915_READ(PCH_ADPA); |
e2c719b7 | 1579 | I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1580 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1581 | pipe_name(pipe)); |
291906f1 | 1582 | |
649636ef | 1583 | val = I915_READ(PCH_LVDS); |
e2c719b7 | 1584 | I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1585 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1586 | pipe_name(pipe)); |
291906f1 | 1587 | |
e2debe91 PZ |
1588 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1589 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1590 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1591 | } |
1592 | ||
d288f65f | 1593 | static void vlv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1594 | const struct intel_crtc_state *pipe_config) |
87442f73 | 1595 | { |
426115cf DV |
1596 | struct drm_device *dev = crtc->base.dev; |
1597 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1598 | i915_reg_t reg = DPLL(crtc->pipe); |
d288f65f | 1599 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
87442f73 | 1600 | |
426115cf | 1601 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 | 1602 | |
87442f73 | 1603 | /* PLL is protected by panel, make sure we can write it */ |
6a9e7363 | 1604 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1605 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1606 | |
426115cf DV |
1607 | I915_WRITE(reg, dpll); |
1608 | POSTING_READ(reg); | |
1609 | udelay(150); | |
1610 | ||
1611 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1612 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1613 | ||
d288f65f | 1614 | I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md); |
426115cf | 1615 | POSTING_READ(DPLL_MD(crtc->pipe)); |
87442f73 DV |
1616 | |
1617 | /* We do this three times for luck */ | |
426115cf | 1618 | I915_WRITE(reg, dpll); |
87442f73 DV |
1619 | POSTING_READ(reg); |
1620 | udelay(150); /* wait for warmup */ | |
426115cf | 1621 | I915_WRITE(reg, dpll); |
87442f73 DV |
1622 | POSTING_READ(reg); |
1623 | udelay(150); /* wait for warmup */ | |
426115cf | 1624 | I915_WRITE(reg, dpll); |
87442f73 DV |
1625 | POSTING_READ(reg); |
1626 | udelay(150); /* wait for warmup */ | |
1627 | } | |
1628 | ||
d288f65f | 1629 | static void chv_enable_pll(struct intel_crtc *crtc, |
5cec258b | 1630 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
1631 | { |
1632 | struct drm_device *dev = crtc->base.dev; | |
1633 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1634 | int pipe = crtc->pipe; | |
1635 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1636 | u32 tmp; |
1637 | ||
1638 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1639 | ||
a580516d | 1640 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 CML |
1641 | |
1642 | /* Enable back the 10bit clock to display controller */ | |
1643 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1644 | tmp |= DPIO_DCLKP_EN; | |
1645 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1646 | ||
54433e91 VS |
1647 | mutex_unlock(&dev_priv->sb_lock); |
1648 | ||
9d556c99 CML |
1649 | /* |
1650 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1651 | */ | |
1652 | udelay(1); | |
1653 | ||
1654 | /* Enable PLL */ | |
d288f65f | 1655 | I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll); |
9d556c99 CML |
1656 | |
1657 | /* Check PLL is locked */ | |
a11b0703 | 1658 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1659 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1660 | ||
a11b0703 | 1661 | /* not sure when this should be written */ |
d288f65f | 1662 | I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md); |
a11b0703 | 1663 | POSTING_READ(DPLL_MD(pipe)); |
9d556c99 CML |
1664 | } |
1665 | ||
1c4e0274 VS |
1666 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1667 | { | |
1668 | struct intel_crtc *crtc; | |
1669 | int count = 0; | |
1670 | ||
1671 | for_each_intel_crtc(dev, crtc) | |
3538b9df | 1672 | count += crtc->base.state->active && |
409ee761 | 1673 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO); |
1c4e0274 VS |
1674 | |
1675 | return count; | |
1676 | } | |
1677 | ||
66e3d5c0 | 1678 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1679 | { |
66e3d5c0 DV |
1680 | struct drm_device *dev = crtc->base.dev; |
1681 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 1682 | i915_reg_t reg = DPLL(crtc->pipe); |
6e3c9717 | 1683 | u32 dpll = crtc->config->dpll_hw_state.dpll; |
63d7bbe9 | 1684 | |
66e3d5c0 | 1685 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1686 | |
63d7bbe9 | 1687 | /* No really, not for ILK+ */ |
3d13ef2e | 1688 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1689 | |
1690 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1691 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1692 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1693 | |
1c4e0274 VS |
1694 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1695 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1696 | /* | |
1697 | * It appears to be important that we don't enable this | |
1698 | * for the current pipe before otherwise configuring the | |
1699 | * PLL. No idea how this should be handled if multiple | |
1700 | * DVO outputs are enabled simultaneosly. | |
1701 | */ | |
1702 | dpll |= DPLL_DVO_2X_MODE; | |
1703 | I915_WRITE(DPLL(!crtc->pipe), | |
1704 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1705 | } | |
66e3d5c0 | 1706 | |
c2b63374 VS |
1707 | /* |
1708 | * Apparently we need to have VGA mode enabled prior to changing | |
1709 | * the P1/P2 dividers. Otherwise the DPLL will keep using the old | |
1710 | * dividers, even though the register value does change. | |
1711 | */ | |
1712 | I915_WRITE(reg, 0); | |
1713 | ||
8e7a65aa VS |
1714 | I915_WRITE(reg, dpll); |
1715 | ||
66e3d5c0 DV |
1716 | /* Wait for the clocks to stabilize. */ |
1717 | POSTING_READ(reg); | |
1718 | udelay(150); | |
1719 | ||
1720 | if (INTEL_INFO(dev)->gen >= 4) { | |
1721 | I915_WRITE(DPLL_MD(crtc->pipe), | |
6e3c9717 | 1722 | crtc->config->dpll_hw_state.dpll_md); |
66e3d5c0 DV |
1723 | } else { |
1724 | /* The pixel multiplier can only be updated once the | |
1725 | * DPLL is enabled and the clocks are stable. | |
1726 | * | |
1727 | * So write it again. | |
1728 | */ | |
1729 | I915_WRITE(reg, dpll); | |
1730 | } | |
63d7bbe9 JB |
1731 | |
1732 | /* We do this three times for luck */ | |
66e3d5c0 | 1733 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1734 | POSTING_READ(reg); |
1735 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1736 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1737 | POSTING_READ(reg); |
1738 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1739 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1740 | POSTING_READ(reg); |
1741 | udelay(150); /* wait for warmup */ | |
1742 | } | |
1743 | ||
1744 | /** | |
50b44a44 | 1745 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1746 | * @dev_priv: i915 private structure |
1747 | * @pipe: pipe PLL to disable | |
1748 | * | |
1749 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1750 | * | |
1751 | * Note! This is for pre-ILK only. | |
1752 | */ | |
1c4e0274 | 1753 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1754 | { |
1c4e0274 VS |
1755 | struct drm_device *dev = crtc->base.dev; |
1756 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1757 | enum pipe pipe = crtc->pipe; | |
1758 | ||
1759 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1760 | if (IS_I830(dev) && | |
409ee761 | 1761 | intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) && |
3538b9df | 1762 | !intel_num_dvo_pipes(dev)) { |
1c4e0274 VS |
1763 | I915_WRITE(DPLL(PIPE_B), |
1764 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1765 | I915_WRITE(DPLL(PIPE_A), | |
1766 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1767 | } | |
1768 | ||
b6b5d049 VS |
1769 | /* Don't disable pipe or pipe PLLs if needed */ |
1770 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1771 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1772 | return; |
1773 | ||
1774 | /* Make sure the pipe isn't still relying on us */ | |
1775 | assert_pipe_disabled(dev_priv, pipe); | |
1776 | ||
b8afb911 | 1777 | I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS); |
50b44a44 | 1778 | POSTING_READ(DPLL(pipe)); |
63d7bbe9 JB |
1779 | } |
1780 | ||
f6071166 JB |
1781 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1782 | { | |
b8afb911 | 1783 | u32 val; |
f6071166 JB |
1784 | |
1785 | /* Make sure the pipe isn't still relying on us */ | |
1786 | assert_pipe_disabled(dev_priv, pipe); | |
1787 | ||
e5cbfbfb ID |
1788 | /* |
1789 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1790 | * The latter is needed for VGA hotplug / manual detection. | |
1791 | */ | |
b8afb911 | 1792 | val = DPLL_VGA_MODE_DIS; |
f6071166 | 1793 | if (pipe == PIPE_B) |
60bfe44f | 1794 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV; |
f6071166 JB |
1795 | I915_WRITE(DPLL(pipe), val); |
1796 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1797 | |
1798 | } | |
1799 | ||
1800 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1801 | { | |
d752048d | 1802 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1803 | u32 val; |
1804 | ||
a11b0703 VS |
1805 | /* Make sure the pipe isn't still relying on us */ |
1806 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1807 | |
a11b0703 | 1808 | /* Set PLL en = 0 */ |
60bfe44f VS |
1809 | val = DPLL_SSC_REF_CLK_CHV | |
1810 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; | |
a11b0703 VS |
1811 | if (pipe != PIPE_A) |
1812 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1813 | I915_WRITE(DPLL(pipe), val); | |
1814 | POSTING_READ(DPLL(pipe)); | |
d752048d | 1815 | |
a580516d | 1816 | mutex_lock(&dev_priv->sb_lock); |
d752048d VS |
1817 | |
1818 | /* Disable 10bit clock to display controller */ | |
1819 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1820 | val &= ~DPIO_DCLKP_EN; | |
1821 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1822 | ||
a580516d | 1823 | mutex_unlock(&dev_priv->sb_lock); |
f6071166 JB |
1824 | } |
1825 | ||
e4607fcf | 1826 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
9b6de0a1 VS |
1827 | struct intel_digital_port *dport, |
1828 | unsigned int expected_mask) | |
89b667f8 JB |
1829 | { |
1830 | u32 port_mask; | |
f0f59a00 | 1831 | i915_reg_t dpll_reg; |
89b667f8 | 1832 | |
e4607fcf CML |
1833 | switch (dport->port) { |
1834 | case PORT_B: | |
89b667f8 | 1835 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1836 | dpll_reg = DPLL(0); |
e4607fcf CML |
1837 | break; |
1838 | case PORT_C: | |
89b667f8 | 1839 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 | 1840 | dpll_reg = DPLL(0); |
9b6de0a1 | 1841 | expected_mask <<= 4; |
00fc31b7 CML |
1842 | break; |
1843 | case PORT_D: | |
1844 | port_mask = DPLL_PORTD_READY_MASK; | |
1845 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1846 | break; |
1847 | default: | |
1848 | BUG(); | |
1849 | } | |
89b667f8 | 1850 | |
9b6de0a1 VS |
1851 | if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000)) |
1852 | WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n", | |
1853 | port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask); | |
89b667f8 JB |
1854 | } |
1855 | ||
b14b1055 DV |
1856 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1857 | { | |
1858 | struct drm_device *dev = crtc->base.dev; | |
1859 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1860 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1861 | ||
be19f0ff CW |
1862 | if (WARN_ON(pll == NULL)) |
1863 | return; | |
1864 | ||
3e369b76 | 1865 | WARN_ON(!pll->config.crtc_mask); |
b14b1055 DV |
1866 | if (pll->active == 0) { |
1867 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1868 | WARN_ON(pll->on); | |
1869 | assert_shared_dpll_disabled(dev_priv, pll); | |
1870 | ||
1871 | pll->mode_set(dev_priv, pll); | |
1872 | } | |
1873 | } | |
1874 | ||
92f2584a | 1875 | /** |
85b3894f | 1876 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1877 | * @dev_priv: i915 private structure |
1878 | * @pipe: pipe PLL to enable | |
1879 | * | |
1880 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1881 | * drives the transcoder clock. | |
1882 | */ | |
85b3894f | 1883 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1884 | { |
3d13ef2e DL |
1885 | struct drm_device *dev = crtc->base.dev; |
1886 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1887 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1888 | |
87a875bb | 1889 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1890 | return; |
1891 | ||
3e369b76 | 1892 | if (WARN_ON(pll->config.crtc_mask == 0)) |
48da64a8 | 1893 | return; |
ee7b9f93 | 1894 | |
74dd6928 | 1895 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1896 | pll->name, pll->active, pll->on, |
e2b78267 | 1897 | crtc->base.base.id); |
92f2584a | 1898 | |
cdbd2316 DV |
1899 | if (pll->active++) { |
1900 | WARN_ON(!pll->on); | |
e9d6944e | 1901 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1902 | return; |
1903 | } | |
f4a091c7 | 1904 | WARN_ON(pll->on); |
ee7b9f93 | 1905 | |
bd2bb1b9 PZ |
1906 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1907 | ||
46edb027 | 1908 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1909 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1910 | pll->on = true; |
92f2584a JB |
1911 | } |
1912 | ||
f6daaec2 | 1913 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1914 | { |
3d13ef2e DL |
1915 | struct drm_device *dev = crtc->base.dev; |
1916 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1917 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1918 | |
92f2584a | 1919 | /* PCH only available on ILK+ */ |
80aa9312 JB |
1920 | if (INTEL_INFO(dev)->gen < 5) |
1921 | return; | |
1922 | ||
eddfcbcd ML |
1923 | if (pll == NULL) |
1924 | return; | |
92f2584a | 1925 | |
eddfcbcd | 1926 | if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base))))) |
48da64a8 | 1927 | return; |
7a419866 | 1928 | |
46edb027 DV |
1929 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1930 | pll->name, pll->active, pll->on, | |
e2b78267 | 1931 | crtc->base.base.id); |
7a419866 | 1932 | |
48da64a8 | 1933 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1934 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1935 | return; |
1936 | } | |
1937 | ||
e9d6944e | 1938 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1939 | WARN_ON(!pll->on); |
cdbd2316 | 1940 | if (--pll->active) |
7a419866 | 1941 | return; |
ee7b9f93 | 1942 | |
46edb027 | 1943 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1944 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1945 | pll->on = false; |
bd2bb1b9 PZ |
1946 | |
1947 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1948 | } |
1949 | ||
b8a4f404 PZ |
1950 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1951 | enum pipe pipe) | |
040484af | 1952 | { |
23670b32 | 1953 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1954 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1955 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
f0f59a00 VS |
1956 | i915_reg_t reg; |
1957 | uint32_t val, pipeconf_val; | |
040484af JB |
1958 | |
1959 | /* PCH only available on ILK+ */ | |
55522f37 | 1960 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1961 | |
1962 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1963 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1964 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1965 | |
1966 | /* FDI must be feeding us bits for PCH ports */ | |
1967 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1968 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1969 | ||
23670b32 DV |
1970 | if (HAS_PCH_CPT(dev)) { |
1971 | /* Workaround: Set the timing override bit before enabling the | |
1972 | * pch transcoder. */ | |
1973 | reg = TRANS_CHICKEN2(pipe); | |
1974 | val = I915_READ(reg); | |
1975 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1976 | I915_WRITE(reg, val); | |
59c859d6 | 1977 | } |
23670b32 | 1978 | |
ab9412ba | 1979 | reg = PCH_TRANSCONF(pipe); |
040484af | 1980 | val = I915_READ(reg); |
5f7f726d | 1981 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1982 | |
1983 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1984 | /* | |
c5de7c6f VS |
1985 | * Make the BPC in transcoder be consistent with |
1986 | * that in pipeconf reg. For HDMI we must use 8bpc | |
1987 | * here for both 8bpc and 12bpc. | |
e9bcff5c | 1988 | */ |
dfd07d72 | 1989 | val &= ~PIPECONF_BPC_MASK; |
c5de7c6f VS |
1990 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI)) |
1991 | val |= PIPECONF_8BPC; | |
1992 | else | |
1993 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1994 | } |
5f7f726d PZ |
1995 | |
1996 | val &= ~TRANS_INTERLACE_MASK; | |
1997 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 | 1998 | if (HAS_PCH_IBX(dev_priv->dev) && |
409ee761 | 1999 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
7c26e5c6 PZ |
2000 | val |= TRANS_LEGACY_INTERLACED_ILK; |
2001 | else | |
2002 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
2003 | else |
2004 | val |= TRANS_PROGRESSIVE; | |
2005 | ||
040484af JB |
2006 | I915_WRITE(reg, val | TRANS_ENABLE); |
2007 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 2008 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
2009 | } |
2010 | ||
8fb033d7 | 2011 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 2012 | enum transcoder cpu_transcoder) |
040484af | 2013 | { |
8fb033d7 | 2014 | u32 val, pipeconf_val; |
8fb033d7 PZ |
2015 | |
2016 | /* PCH only available on ILK+ */ | |
55522f37 | 2017 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 2018 | |
8fb033d7 | 2019 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 2020 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 2021 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 2022 | |
223a6fdf | 2023 | /* Workaround: set timing override bit. */ |
36c0d0cf | 2024 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 2025 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 2026 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
223a6fdf | 2027 | |
25f3ef11 | 2028 | val = TRANS_ENABLE; |
937bb610 | 2029 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 2030 | |
9a76b1c6 PZ |
2031 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
2032 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 2033 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
2034 | else |
2035 | val |= TRANS_PROGRESSIVE; | |
2036 | ||
ab9412ba DV |
2037 | I915_WRITE(LPT_TRANSCONF, val); |
2038 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 2039 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
2040 | } |
2041 | ||
b8a4f404 PZ |
2042 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
2043 | enum pipe pipe) | |
040484af | 2044 | { |
23670b32 | 2045 | struct drm_device *dev = dev_priv->dev; |
f0f59a00 VS |
2046 | i915_reg_t reg; |
2047 | uint32_t val; | |
040484af JB |
2048 | |
2049 | /* FDI relies on the transcoder */ | |
2050 | assert_fdi_tx_disabled(dev_priv, pipe); | |
2051 | assert_fdi_rx_disabled(dev_priv, pipe); | |
2052 | ||
291906f1 JB |
2053 | /* Ports must be off as well */ |
2054 | assert_pch_ports_disabled(dev_priv, pipe); | |
2055 | ||
ab9412ba | 2056 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
2057 | val = I915_READ(reg); |
2058 | val &= ~TRANS_ENABLE; | |
2059 | I915_WRITE(reg, val); | |
2060 | /* wait for PCH transcoder off, transcoder state */ | |
2061 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 2062 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 | 2063 | |
c465613b | 2064 | if (HAS_PCH_CPT(dev)) { |
23670b32 DV |
2065 | /* Workaround: Clear the timing override chicken bit again. */ |
2066 | reg = TRANS_CHICKEN2(pipe); | |
2067 | val = I915_READ(reg); | |
2068 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2069 | I915_WRITE(reg, val); | |
2070 | } | |
040484af JB |
2071 | } |
2072 | ||
ab4d966c | 2073 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 2074 | { |
8fb033d7 PZ |
2075 | u32 val; |
2076 | ||
ab9412ba | 2077 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 2078 | val &= ~TRANS_ENABLE; |
ab9412ba | 2079 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 2080 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 2081 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 2082 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
2083 | |
2084 | /* Workaround: clear timing override bit. */ | |
36c0d0cf | 2085 | val = I915_READ(TRANS_CHICKEN2(PIPE_A)); |
23670b32 | 2086 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
36c0d0cf | 2087 | I915_WRITE(TRANS_CHICKEN2(PIPE_A), val); |
040484af JB |
2088 | } |
2089 | ||
b24e7179 | 2090 | /** |
309cfea8 | 2091 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2092 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2093 | * |
0372264a | 2094 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2095 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2096 | */ |
e1fdc473 | 2097 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2098 | { |
0372264a PZ |
2099 | struct drm_device *dev = crtc->base.dev; |
2100 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2101 | enum pipe pipe = crtc->pipe; | |
1a70a728 | 2102 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
1a240d4d | 2103 | enum pipe pch_transcoder; |
f0f59a00 | 2104 | i915_reg_t reg; |
b24e7179 JB |
2105 | u32 val; |
2106 | ||
9e2ee2dd VS |
2107 | DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe)); |
2108 | ||
58c6eaa2 | 2109 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2110 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2111 | assert_sprites_disabled(dev_priv, pipe); |
2112 | ||
681e5811 | 2113 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2114 | pch_transcoder = TRANSCODER_A; |
2115 | else | |
2116 | pch_transcoder = pipe; | |
2117 | ||
b24e7179 JB |
2118 | /* |
2119 | * A pipe without a PLL won't actually be able to drive bits from | |
2120 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2121 | * need the check. | |
2122 | */ | |
50360403 | 2123 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) |
a65347ba | 2124 | if (crtc->config->has_dsi_encoder) |
23538ef1 JN |
2125 | assert_dsi_pll_enabled(dev_priv); |
2126 | else | |
2127 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2128 | else { |
6e3c9717 | 2129 | if (crtc->config->has_pch_encoder) { |
040484af | 2130 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2131 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2132 | assert_fdi_tx_pll_enabled(dev_priv, |
2133 | (enum pipe) cpu_transcoder); | |
040484af JB |
2134 | } |
2135 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2136 | } | |
b24e7179 | 2137 | |
702e7a56 | 2138 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2139 | val = I915_READ(reg); |
7ad25d48 | 2140 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2141 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2142 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2143 | return; |
7ad25d48 | 2144 | } |
00d70b15 CW |
2145 | |
2146 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2147 | POSTING_READ(reg); |
b7792d8b VS |
2148 | |
2149 | /* | |
2150 | * Until the pipe starts DSL will read as 0, which would cause | |
2151 | * an apparent vblank timestamp jump, which messes up also the | |
2152 | * frame count when it's derived from the timestamps. So let's | |
2153 | * wait for the pipe to start properly before we call | |
2154 | * drm_crtc_vblank_on() | |
2155 | */ | |
2156 | if (dev->max_vblank_count == 0 && | |
2157 | wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50)) | |
2158 | DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe)); | |
b24e7179 JB |
2159 | } |
2160 | ||
2161 | /** | |
309cfea8 | 2162 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2163 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2164 | * |
575f7ab7 VS |
2165 | * Disable the pipe of @crtc, making sure that various hardware |
2166 | * specific requirements are met, if applicable, e.g. plane | |
2167 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2168 | * |
2169 | * Will wait until the pipe has shut down before returning. | |
2170 | */ | |
575f7ab7 | 2171 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2172 | { |
575f7ab7 | 2173 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
6e3c9717 | 2174 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
575f7ab7 | 2175 | enum pipe pipe = crtc->pipe; |
f0f59a00 | 2176 | i915_reg_t reg; |
b24e7179 JB |
2177 | u32 val; |
2178 | ||
9e2ee2dd VS |
2179 | DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe)); |
2180 | ||
b24e7179 JB |
2181 | /* |
2182 | * Make sure planes won't keep trying to pump pixels to us, | |
2183 | * or we might hang the display. | |
2184 | */ | |
2185 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2186 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2187 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2188 | |
702e7a56 | 2189 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2190 | val = I915_READ(reg); |
00d70b15 CW |
2191 | if ((val & PIPECONF_ENABLE) == 0) |
2192 | return; | |
2193 | ||
67adc644 VS |
2194 | /* |
2195 | * Double wide has implications for planes | |
2196 | * so best keep it disabled when not needed. | |
2197 | */ | |
6e3c9717 | 2198 | if (crtc->config->double_wide) |
67adc644 VS |
2199 | val &= ~PIPECONF_DOUBLE_WIDE; |
2200 | ||
2201 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2202 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2203 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2204 | val &= ~PIPECONF_ENABLE; |
2205 | ||
2206 | I915_WRITE(reg, val); | |
2207 | if ((val & PIPECONF_ENABLE) == 0) | |
2208 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2209 | } |
2210 | ||
693db184 CW |
2211 | static bool need_vtd_wa(struct drm_device *dev) |
2212 | { | |
2213 | #ifdef CONFIG_INTEL_IOMMU | |
2214 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2215 | return true; | |
2216 | #endif | |
2217 | return false; | |
2218 | } | |
2219 | ||
832be82f VS |
2220 | static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv) |
2221 | { | |
2222 | return IS_GEN2(dev_priv) ? 2048 : 4096; | |
2223 | } | |
2224 | ||
7b49f948 VS |
2225 | static unsigned int intel_tile_width(const struct drm_i915_private *dev_priv, |
2226 | uint64_t fb_modifier, unsigned int cpp) | |
2227 | { | |
2228 | switch (fb_modifier) { | |
2229 | case DRM_FORMAT_MOD_NONE: | |
2230 | return cpp; | |
2231 | case I915_FORMAT_MOD_X_TILED: | |
2232 | if (IS_GEN2(dev_priv)) | |
2233 | return 128; | |
2234 | else | |
2235 | return 512; | |
2236 | case I915_FORMAT_MOD_Y_TILED: | |
2237 | if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv)) | |
2238 | return 128; | |
2239 | else | |
2240 | return 512; | |
2241 | case I915_FORMAT_MOD_Yf_TILED: | |
2242 | switch (cpp) { | |
2243 | case 1: | |
2244 | return 64; | |
2245 | case 2: | |
2246 | case 4: | |
2247 | return 128; | |
2248 | case 8: | |
2249 | case 16: | |
2250 | return 256; | |
2251 | default: | |
2252 | MISSING_CASE(cpp); | |
2253 | return cpp; | |
2254 | } | |
2255 | break; | |
2256 | default: | |
2257 | MISSING_CASE(fb_modifier); | |
2258 | return cpp; | |
2259 | } | |
2260 | } | |
2261 | ||
832be82f VS |
2262 | unsigned int intel_tile_height(const struct drm_i915_private *dev_priv, |
2263 | uint64_t fb_modifier, unsigned int cpp) | |
a57ce0b2 | 2264 | { |
832be82f VS |
2265 | if (fb_modifier == DRM_FORMAT_MOD_NONE) |
2266 | return 1; | |
2267 | else | |
2268 | return intel_tile_size(dev_priv) / | |
2269 | intel_tile_width(dev_priv, fb_modifier, cpp); | |
6761dd31 TU |
2270 | } |
2271 | ||
2272 | unsigned int | |
2273 | intel_fb_align_height(struct drm_device *dev, unsigned int height, | |
832be82f | 2274 | uint32_t pixel_format, uint64_t fb_modifier) |
6761dd31 | 2275 | { |
832be82f VS |
2276 | unsigned int cpp = drm_format_plane_cpp(pixel_format, 0); |
2277 | unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp); | |
2278 | ||
2279 | return ALIGN(height, tile_height); | |
a57ce0b2 JB |
2280 | } |
2281 | ||
75c82a53 | 2282 | static void |
f64b98cd TU |
2283 | intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb, |
2284 | const struct drm_plane_state *plane_state) | |
2285 | { | |
832be82f | 2286 | struct drm_i915_private *dev_priv = to_i915(fb->dev); |
7723f47d | 2287 | struct intel_rotation_info *info = &view->params.rotated; |
d9b3288e | 2288 | unsigned int tile_size, tile_width, tile_height, cpp; |
50470bb0 | 2289 | |
f64b98cd TU |
2290 | *view = i915_ggtt_view_normal; |
2291 | ||
50470bb0 | 2292 | if (!plane_state) |
75c82a53 | 2293 | return; |
50470bb0 | 2294 | |
121920fa | 2295 | if (!intel_rotation_90_or_270(plane_state->rotation)) |
75c82a53 | 2296 | return; |
50470bb0 | 2297 | |
9abc4648 | 2298 | *view = i915_ggtt_view_rotated; |
50470bb0 TU |
2299 | |
2300 | info->height = fb->height; | |
2301 | info->pixel_format = fb->pixel_format; | |
2302 | info->pitch = fb->pitches[0]; | |
89e3e142 | 2303 | info->uv_offset = fb->offsets[1]; |
50470bb0 TU |
2304 | info->fb_modifier = fb->modifier[0]; |
2305 | ||
d9b3288e VS |
2306 | tile_size = intel_tile_size(dev_priv); |
2307 | ||
2308 | cpp = drm_format_plane_cpp(fb->pixel_format, 0); | |
b16bb01f | 2309 | tile_width = intel_tile_width(dev_priv, fb->modifier[0], cpp); |
d9b3288e VS |
2310 | tile_height = tile_size / tile_width; |
2311 | ||
2312 | info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_width); | |
84fe03f7 | 2313 | info->height_pages = DIV_ROUND_UP(fb->height, tile_height); |
d9b3288e | 2314 | info->size = info->width_pages * info->height_pages * tile_size; |
84fe03f7 | 2315 | |
89e3e142 | 2316 | if (info->pixel_format == DRM_FORMAT_NV12) { |
832be82f | 2317 | cpp = drm_format_plane_cpp(fb->pixel_format, 1); |
d9b3288e VS |
2318 | tile_width = intel_tile_width(dev_priv, fb->modifier[1], cpp); |
2319 | tile_height = tile_size / tile_width; | |
2320 | ||
2321 | info->width_pages_uv = DIV_ROUND_UP(fb->pitches[1], tile_width); | |
832be82f | 2322 | info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, tile_height); |
d9b3288e | 2323 | info->size_uv = info->width_pages_uv * info->height_pages_uv * tile_size; |
89e3e142 | 2324 | } |
f64b98cd TU |
2325 | } |
2326 | ||
603525d7 | 2327 | static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv) |
4e9a86b6 VS |
2328 | { |
2329 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2330 | return 256 * 1024; | |
985b8bb4 | 2331 | else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) || |
666a4537 | 2332 | IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
4e9a86b6 VS |
2333 | return 128 * 1024; |
2334 | else if (INTEL_INFO(dev_priv)->gen >= 4) | |
2335 | return 4 * 1024; | |
2336 | else | |
44c5905e | 2337 | return 0; |
4e9a86b6 VS |
2338 | } |
2339 | ||
603525d7 VS |
2340 | static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv, |
2341 | uint64_t fb_modifier) | |
2342 | { | |
2343 | switch (fb_modifier) { | |
2344 | case DRM_FORMAT_MOD_NONE: | |
2345 | return intel_linear_alignment(dev_priv); | |
2346 | case I915_FORMAT_MOD_X_TILED: | |
2347 | if (INTEL_INFO(dev_priv)->gen >= 9) | |
2348 | return 256 * 1024; | |
2349 | return 0; | |
2350 | case I915_FORMAT_MOD_Y_TILED: | |
2351 | case I915_FORMAT_MOD_Yf_TILED: | |
2352 | return 1 * 1024 * 1024; | |
2353 | default: | |
2354 | MISSING_CASE(fb_modifier); | |
2355 | return 0; | |
2356 | } | |
2357 | } | |
2358 | ||
127bd2ac | 2359 | int |
850c4cdc TU |
2360 | intel_pin_and_fence_fb_obj(struct drm_plane *plane, |
2361 | struct drm_framebuffer *fb, | |
7580d774 | 2362 | const struct drm_plane_state *plane_state) |
6b95a207 | 2363 | { |
850c4cdc | 2364 | struct drm_device *dev = fb->dev; |
ce453d81 | 2365 | struct drm_i915_private *dev_priv = dev->dev_private; |
850c4cdc | 2366 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2367 | struct i915_ggtt_view view; |
6b95a207 KH |
2368 | u32 alignment; |
2369 | int ret; | |
2370 | ||
ebcdd39e MR |
2371 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2372 | ||
603525d7 | 2373 | alignment = intel_surf_alignment(dev_priv, fb->modifier[0]); |
6b95a207 | 2374 | |
75c82a53 | 2375 | intel_fill_fb_ggtt_view(&view, fb, plane_state); |
f64b98cd | 2376 | |
693db184 CW |
2377 | /* Note that the w/a also requires 64 PTE of padding following the |
2378 | * bo. We currently fill all unused PTE with the shadow page and so | |
2379 | * we should always have valid PTE following the scanout preventing | |
2380 | * the VT-d warning. | |
2381 | */ | |
2382 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2383 | alignment = 256 * 1024; | |
2384 | ||
d6dd6843 PZ |
2385 | /* |
2386 | * Global gtt pte registers are special registers which actually forward | |
2387 | * writes to a chunk of system memory. Which means that there is no risk | |
2388 | * that the register values disappear as soon as we call | |
2389 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2390 | * pin/unpin/fence and not more. | |
2391 | */ | |
2392 | intel_runtime_pm_get(dev_priv); | |
2393 | ||
7580d774 ML |
2394 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, |
2395 | &view); | |
48b956c5 | 2396 | if (ret) |
b26a6b35 | 2397 | goto err_pm; |
6b95a207 KH |
2398 | |
2399 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2400 | * fence, whereas 965+ only requires a fence if using | |
2401 | * framebuffer compression. For simplicity, we always install | |
2402 | * a fence as the cost is not that onerous. | |
2403 | */ | |
9807216f VK |
2404 | if (view.type == I915_GGTT_VIEW_NORMAL) { |
2405 | ret = i915_gem_object_get_fence(obj); | |
2406 | if (ret == -EDEADLK) { | |
2407 | /* | |
2408 | * -EDEADLK means there are no free fences | |
2409 | * no pending flips. | |
2410 | * | |
2411 | * This is propagated to atomic, but it uses | |
2412 | * -EDEADLK to force a locking recovery, so | |
2413 | * change the returned error to -EBUSY. | |
2414 | */ | |
2415 | ret = -EBUSY; | |
2416 | goto err_unpin; | |
2417 | } else if (ret) | |
2418 | goto err_unpin; | |
1690e1eb | 2419 | |
9807216f VK |
2420 | i915_gem_object_pin_fence(obj); |
2421 | } | |
6b95a207 | 2422 | |
d6dd6843 | 2423 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2424 | return 0; |
48b956c5 CW |
2425 | |
2426 | err_unpin: | |
f64b98cd | 2427 | i915_gem_object_unpin_from_display_plane(obj, &view); |
b26a6b35 | 2428 | err_pm: |
d6dd6843 | 2429 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2430 | return ret; |
6b95a207 KH |
2431 | } |
2432 | ||
82bc3b2d TU |
2433 | static void intel_unpin_fb_obj(struct drm_framebuffer *fb, |
2434 | const struct drm_plane_state *plane_state) | |
1690e1eb | 2435 | { |
82bc3b2d | 2436 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
f64b98cd | 2437 | struct i915_ggtt_view view; |
82bc3b2d | 2438 | |
ebcdd39e MR |
2439 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2440 | ||
75c82a53 | 2441 | intel_fill_fb_ggtt_view(&view, fb, plane_state); |
f64b98cd | 2442 | |
9807216f VK |
2443 | if (view.type == I915_GGTT_VIEW_NORMAL) |
2444 | i915_gem_object_unpin_fence(obj); | |
2445 | ||
f64b98cd | 2446 | i915_gem_object_unpin_from_display_plane(obj, &view); |
1690e1eb CW |
2447 | } |
2448 | ||
c2c75131 DV |
2449 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2450 | * is assumed to be a power-of-two. */ | |
54ea9da8 VS |
2451 | u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv, |
2452 | int *x, int *y, | |
2453 | uint64_t fb_modifier, | |
2454 | unsigned int cpp, | |
2455 | unsigned int pitch) | |
c2c75131 | 2456 | { |
b5c65338 | 2457 | if (fb_modifier != DRM_FORMAT_MOD_NONE) { |
d843310d | 2458 | unsigned int tile_size, tile_width, tile_height; |
bc752862 | 2459 | unsigned int tile_rows, tiles; |
c2c75131 | 2460 | |
d843310d VS |
2461 | tile_size = intel_tile_size(dev_priv); |
2462 | tile_width = intel_tile_width(dev_priv, fb_modifier, cpp); | |
2463 | tile_height = tile_size / tile_width; | |
2464 | ||
2465 | tile_rows = *y / tile_height; | |
2466 | *y %= tile_height; | |
c2c75131 | 2467 | |
d843310d VS |
2468 | tiles = *x / (tile_width/cpp); |
2469 | *x %= tile_width/cpp; | |
bc752862 | 2470 | |
d843310d | 2471 | return tile_rows * pitch * tile_height + tiles * tile_size; |
bc752862 | 2472 | } else { |
4e9a86b6 | 2473 | unsigned int alignment = intel_linear_alignment(dev_priv) - 1; |
bc752862 CW |
2474 | unsigned int offset; |
2475 | ||
2476 | offset = *y * pitch + *x * cpp; | |
4e9a86b6 VS |
2477 | *y = (offset & alignment) / pitch; |
2478 | *x = ((offset & alignment) - *y * pitch) / cpp; | |
2479 | return offset & ~alignment; | |
bc752862 | 2480 | } |
c2c75131 DV |
2481 | } |
2482 | ||
b35d63fa | 2483 | static int i9xx_format_to_fourcc(int format) |
46f297fb JB |
2484 | { |
2485 | switch (format) { | |
2486 | case DISPPLANE_8BPP: | |
2487 | return DRM_FORMAT_C8; | |
2488 | case DISPPLANE_BGRX555: | |
2489 | return DRM_FORMAT_XRGB1555; | |
2490 | case DISPPLANE_BGRX565: | |
2491 | return DRM_FORMAT_RGB565; | |
2492 | default: | |
2493 | case DISPPLANE_BGRX888: | |
2494 | return DRM_FORMAT_XRGB8888; | |
2495 | case DISPPLANE_RGBX888: | |
2496 | return DRM_FORMAT_XBGR8888; | |
2497 | case DISPPLANE_BGRX101010: | |
2498 | return DRM_FORMAT_XRGB2101010; | |
2499 | case DISPPLANE_RGBX101010: | |
2500 | return DRM_FORMAT_XBGR2101010; | |
2501 | } | |
2502 | } | |
2503 | ||
bc8d7dff DL |
2504 | static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) |
2505 | { | |
2506 | switch (format) { | |
2507 | case PLANE_CTL_FORMAT_RGB_565: | |
2508 | return DRM_FORMAT_RGB565; | |
2509 | default: | |
2510 | case PLANE_CTL_FORMAT_XRGB_8888: | |
2511 | if (rgb_order) { | |
2512 | if (alpha) | |
2513 | return DRM_FORMAT_ABGR8888; | |
2514 | else | |
2515 | return DRM_FORMAT_XBGR8888; | |
2516 | } else { | |
2517 | if (alpha) | |
2518 | return DRM_FORMAT_ARGB8888; | |
2519 | else | |
2520 | return DRM_FORMAT_XRGB8888; | |
2521 | } | |
2522 | case PLANE_CTL_FORMAT_XRGB_2101010: | |
2523 | if (rgb_order) | |
2524 | return DRM_FORMAT_XBGR2101010; | |
2525 | else | |
2526 | return DRM_FORMAT_XRGB2101010; | |
2527 | } | |
2528 | } | |
2529 | ||
5724dbd1 | 2530 | static bool |
f6936e29 DV |
2531 | intel_alloc_initial_plane_obj(struct intel_crtc *crtc, |
2532 | struct intel_initial_plane_config *plane_config) | |
46f297fb JB |
2533 | { |
2534 | struct drm_device *dev = crtc->base.dev; | |
3badb49f | 2535 | struct drm_i915_private *dev_priv = to_i915(dev); |
46f297fb JB |
2536 | struct drm_i915_gem_object *obj = NULL; |
2537 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2d14030b | 2538 | struct drm_framebuffer *fb = &plane_config->fb->base; |
f37b5c2b DV |
2539 | u32 base_aligned = round_down(plane_config->base, PAGE_SIZE); |
2540 | u32 size_aligned = round_up(plane_config->base + plane_config->size, | |
2541 | PAGE_SIZE); | |
2542 | ||
2543 | size_aligned -= base_aligned; | |
46f297fb | 2544 | |
ff2652ea CW |
2545 | if (plane_config->size == 0) |
2546 | return false; | |
2547 | ||
3badb49f PZ |
2548 | /* If the FB is too big, just don't use it since fbdev is not very |
2549 | * important and we should probably use that space with FBC or other | |
2550 | * features. */ | |
2551 | if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size) | |
2552 | return false; | |
2553 | ||
f37b5c2b DV |
2554 | obj = i915_gem_object_create_stolen_for_preallocated(dev, |
2555 | base_aligned, | |
2556 | base_aligned, | |
2557 | size_aligned); | |
46f297fb | 2558 | if (!obj) |
484b41dd | 2559 | return false; |
46f297fb | 2560 | |
49af449b DL |
2561 | obj->tiling_mode = plane_config->tiling; |
2562 | if (obj->tiling_mode == I915_TILING_X) | |
6bf129df | 2563 | obj->stride = fb->pitches[0]; |
46f297fb | 2564 | |
6bf129df DL |
2565 | mode_cmd.pixel_format = fb->pixel_format; |
2566 | mode_cmd.width = fb->width; | |
2567 | mode_cmd.height = fb->height; | |
2568 | mode_cmd.pitches[0] = fb->pitches[0]; | |
18c5247e DV |
2569 | mode_cmd.modifier[0] = fb->modifier[0]; |
2570 | mode_cmd.flags = DRM_MODE_FB_MODIFIERS; | |
46f297fb JB |
2571 | |
2572 | mutex_lock(&dev->struct_mutex); | |
6bf129df | 2573 | if (intel_framebuffer_init(dev, to_intel_framebuffer(fb), |
484b41dd | 2574 | &mode_cmd, obj)) { |
46f297fb JB |
2575 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2576 | goto out_unref_obj; | |
2577 | } | |
46f297fb | 2578 | mutex_unlock(&dev->struct_mutex); |
484b41dd | 2579 | |
f6936e29 | 2580 | DRM_DEBUG_KMS("initial plane fb obj %p\n", obj); |
484b41dd | 2581 | return true; |
46f297fb JB |
2582 | |
2583 | out_unref_obj: | |
2584 | drm_gem_object_unreference(&obj->base); | |
2585 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2586 | return false; |
2587 | } | |
2588 | ||
afd65eb4 MR |
2589 | /* Update plane->state->fb to match plane->fb after driver-internal updates */ |
2590 | static void | |
2591 | update_state_fb(struct drm_plane *plane) | |
2592 | { | |
2593 | if (plane->fb == plane->state->fb) | |
2594 | return; | |
2595 | ||
2596 | if (plane->state->fb) | |
2597 | drm_framebuffer_unreference(plane->state->fb); | |
2598 | plane->state->fb = plane->fb; | |
2599 | if (plane->state->fb) | |
2600 | drm_framebuffer_reference(plane->state->fb); | |
2601 | } | |
2602 | ||
5724dbd1 | 2603 | static void |
f6936e29 DV |
2604 | intel_find_initial_plane_obj(struct intel_crtc *intel_crtc, |
2605 | struct intel_initial_plane_config *plane_config) | |
484b41dd JB |
2606 | { |
2607 | struct drm_device *dev = intel_crtc->base.dev; | |
d9ceb816 | 2608 | struct drm_i915_private *dev_priv = dev->dev_private; |
484b41dd JB |
2609 | struct drm_crtc *c; |
2610 | struct intel_crtc *i; | |
2ff8fde1 | 2611 | struct drm_i915_gem_object *obj; |
88595ac9 | 2612 | struct drm_plane *primary = intel_crtc->base.primary; |
be5651f2 | 2613 | struct drm_plane_state *plane_state = primary->state; |
200757f5 MR |
2614 | struct drm_crtc_state *crtc_state = intel_crtc->base.state; |
2615 | struct intel_plane *intel_plane = to_intel_plane(primary); | |
0a8d8a86 MR |
2616 | struct intel_plane_state *intel_state = |
2617 | to_intel_plane_state(plane_state); | |
88595ac9 | 2618 | struct drm_framebuffer *fb; |
484b41dd | 2619 | |
2d14030b | 2620 | if (!plane_config->fb) |
484b41dd JB |
2621 | return; |
2622 | ||
f6936e29 | 2623 | if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) { |
88595ac9 DV |
2624 | fb = &plane_config->fb->base; |
2625 | goto valid_fb; | |
f55548b5 | 2626 | } |
484b41dd | 2627 | |
2d14030b | 2628 | kfree(plane_config->fb); |
484b41dd JB |
2629 | |
2630 | /* | |
2631 | * Failed to alloc the obj, check to see if we should share | |
2632 | * an fb with another CRTC instead | |
2633 | */ | |
70e1e0ec | 2634 | for_each_crtc(dev, c) { |
484b41dd JB |
2635 | i = to_intel_crtc(c); |
2636 | ||
2637 | if (c == &intel_crtc->base) | |
2638 | continue; | |
2639 | ||
2ff8fde1 MR |
2640 | if (!i->active) |
2641 | continue; | |
2642 | ||
88595ac9 DV |
2643 | fb = c->primary->fb; |
2644 | if (!fb) | |
484b41dd JB |
2645 | continue; |
2646 | ||
88595ac9 | 2647 | obj = intel_fb_obj(fb); |
2ff8fde1 | 2648 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
88595ac9 DV |
2649 | drm_framebuffer_reference(fb); |
2650 | goto valid_fb; | |
484b41dd JB |
2651 | } |
2652 | } | |
88595ac9 | 2653 | |
200757f5 MR |
2654 | /* |
2655 | * We've failed to reconstruct the BIOS FB. Current display state | |
2656 | * indicates that the primary plane is visible, but has a NULL FB, | |
2657 | * which will lead to problems later if we don't fix it up. The | |
2658 | * simplest solution is to just disable the primary plane now and | |
2659 | * pretend the BIOS never had it enabled. | |
2660 | */ | |
2661 | to_intel_plane_state(plane_state)->visible = false; | |
2662 | crtc_state->plane_mask &= ~(1 << drm_plane_index(primary)); | |
2663 | intel_pre_disable_primary(&intel_crtc->base); | |
2664 | intel_plane->disable_plane(primary, &intel_crtc->base); | |
2665 | ||
88595ac9 DV |
2666 | return; |
2667 | ||
2668 | valid_fb: | |
f44e2659 VS |
2669 | plane_state->src_x = 0; |
2670 | plane_state->src_y = 0; | |
be5651f2 ML |
2671 | plane_state->src_w = fb->width << 16; |
2672 | plane_state->src_h = fb->height << 16; | |
2673 | ||
f44e2659 VS |
2674 | plane_state->crtc_x = 0; |
2675 | plane_state->crtc_y = 0; | |
be5651f2 ML |
2676 | plane_state->crtc_w = fb->width; |
2677 | plane_state->crtc_h = fb->height; | |
2678 | ||
0a8d8a86 MR |
2679 | intel_state->src.x1 = plane_state->src_x; |
2680 | intel_state->src.y1 = plane_state->src_y; | |
2681 | intel_state->src.x2 = plane_state->src_x + plane_state->src_w; | |
2682 | intel_state->src.y2 = plane_state->src_y + plane_state->src_h; | |
2683 | intel_state->dst.x1 = plane_state->crtc_x; | |
2684 | intel_state->dst.y1 = plane_state->crtc_y; | |
2685 | intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w; | |
2686 | intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h; | |
2687 | ||
88595ac9 DV |
2688 | obj = intel_fb_obj(fb); |
2689 | if (obj->tiling_mode != I915_TILING_NONE) | |
2690 | dev_priv->preserve_bios_swizzle = true; | |
2691 | ||
be5651f2 ML |
2692 | drm_framebuffer_reference(fb); |
2693 | primary->fb = primary->state->fb = fb; | |
36750f28 | 2694 | primary->crtc = primary->state->crtc = &intel_crtc->base; |
36750f28 | 2695 | intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary)); |
a9ff8714 | 2696 | obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit; |
46f297fb JB |
2697 | } |
2698 | ||
a8d201af ML |
2699 | static void i9xx_update_primary_plane(struct drm_plane *primary, |
2700 | const struct intel_crtc_state *crtc_state, | |
2701 | const struct intel_plane_state *plane_state) | |
81255565 | 2702 | { |
a8d201af | 2703 | struct drm_device *dev = primary->dev; |
81255565 | 2704 | struct drm_i915_private *dev_priv = dev->dev_private; |
a8d201af ML |
2705 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
2706 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2707 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
81255565 | 2708 | int plane = intel_crtc->plane; |
54ea9da8 | 2709 | u32 linear_offset; |
81255565 | 2710 | u32 dspcntr; |
f0f59a00 | 2711 | i915_reg_t reg = DSPCNTR(plane); |
ac484963 | 2712 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
54ea9da8 VS |
2713 | int x = plane_state->src.x1 >> 16; |
2714 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2715 | |
f45651ba VS |
2716 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2717 | ||
fdd508a6 | 2718 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2719 | |
2720 | if (INTEL_INFO(dev)->gen < 4) { | |
2721 | if (intel_crtc->pipe == PIPE_B) | |
2722 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2723 | ||
2724 | /* pipesrc and dspsize control the size that is scaled from, | |
2725 | * which should always be the user's requested size. | |
2726 | */ | |
2727 | I915_WRITE(DSPSIZE(plane), | |
a8d201af ML |
2728 | ((crtc_state->pipe_src_h - 1) << 16) | |
2729 | (crtc_state->pipe_src_w - 1)); | |
f45651ba | 2730 | I915_WRITE(DSPPOS(plane), 0); |
c14b0485 VS |
2731 | } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) { |
2732 | I915_WRITE(PRIMSIZE(plane), | |
a8d201af ML |
2733 | ((crtc_state->pipe_src_h - 1) << 16) | |
2734 | (crtc_state->pipe_src_w - 1)); | |
c14b0485 VS |
2735 | I915_WRITE(PRIMPOS(plane), 0); |
2736 | I915_WRITE(PRIMCNSTALPHA(plane), 0); | |
f45651ba | 2737 | } |
81255565 | 2738 | |
57779d06 VS |
2739 | switch (fb->pixel_format) { |
2740 | case DRM_FORMAT_C8: | |
81255565 JB |
2741 | dspcntr |= DISPPLANE_8BPP; |
2742 | break; | |
57779d06 | 2743 | case DRM_FORMAT_XRGB1555: |
57779d06 | 2744 | dspcntr |= DISPPLANE_BGRX555; |
81255565 | 2745 | break; |
57779d06 VS |
2746 | case DRM_FORMAT_RGB565: |
2747 | dspcntr |= DISPPLANE_BGRX565; | |
2748 | break; | |
2749 | case DRM_FORMAT_XRGB8888: | |
57779d06 VS |
2750 | dspcntr |= DISPPLANE_BGRX888; |
2751 | break; | |
2752 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2753 | dspcntr |= DISPPLANE_RGBX888; |
2754 | break; | |
2755 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2756 | dspcntr |= DISPPLANE_BGRX101010; |
2757 | break; | |
2758 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2759 | dspcntr |= DISPPLANE_RGBX101010; |
81255565 JB |
2760 | break; |
2761 | default: | |
baba133a | 2762 | BUG(); |
81255565 | 2763 | } |
57779d06 | 2764 | |
f45651ba VS |
2765 | if (INTEL_INFO(dev)->gen >= 4 && |
2766 | obj->tiling_mode != I915_TILING_NONE) | |
2767 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2768 | |
de1aa629 VS |
2769 | if (IS_G4X(dev)) |
2770 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2771 | ||
ac484963 | 2772 | linear_offset = y * fb->pitches[0] + x * cpp; |
81255565 | 2773 | |
c2c75131 DV |
2774 | if (INTEL_INFO(dev)->gen >= 4) { |
2775 | intel_crtc->dspaddr_offset = | |
ce1e5c14 | 2776 | intel_compute_tile_offset(dev_priv, &x, &y, |
ac484963 | 2777 | fb->modifier[0], cpp, |
ce1e5c14 | 2778 | fb->pitches[0]); |
c2c75131 DV |
2779 | linear_offset -= intel_crtc->dspaddr_offset; |
2780 | } else { | |
e506a0c6 | 2781 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2782 | } |
e506a0c6 | 2783 | |
a8d201af | 2784 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2785 | dspcntr |= DISPPLANE_ROTATE_180; |
2786 | ||
a8d201af ML |
2787 | x += (crtc_state->pipe_src_w - 1); |
2788 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2789 | |
2790 | /* Finding the last pixel of the last line of the display | |
2791 | data and adding to linear_offset*/ | |
2792 | linear_offset += | |
a8d201af | 2793 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2794 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2795 | } |
2796 | ||
2db3366b PZ |
2797 | intel_crtc->adjusted_x = x; |
2798 | intel_crtc->adjusted_y = y; | |
2799 | ||
48404c1e SJ |
2800 | I915_WRITE(reg, dspcntr); |
2801 | ||
01f2c773 | 2802 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2803 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2804 | I915_WRITE(DSPSURF(plane), |
2805 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2806 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2807 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2808 | } else |
f343c5f6 | 2809 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2810 | POSTING_READ(reg); |
17638cd6 JB |
2811 | } |
2812 | ||
a8d201af ML |
2813 | static void i9xx_disable_primary_plane(struct drm_plane *primary, |
2814 | struct drm_crtc *crtc) | |
17638cd6 JB |
2815 | { |
2816 | struct drm_device *dev = crtc->dev; | |
2817 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2818 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
17638cd6 | 2819 | int plane = intel_crtc->plane; |
f45651ba | 2820 | |
a8d201af ML |
2821 | I915_WRITE(DSPCNTR(plane), 0); |
2822 | if (INTEL_INFO(dev_priv)->gen >= 4) | |
fdd508a6 | 2823 | I915_WRITE(DSPSURF(plane), 0); |
a8d201af ML |
2824 | else |
2825 | I915_WRITE(DSPADDR(plane), 0); | |
2826 | POSTING_READ(DSPCNTR(plane)); | |
2827 | } | |
c9ba6fad | 2828 | |
a8d201af ML |
2829 | static void ironlake_update_primary_plane(struct drm_plane *primary, |
2830 | const struct intel_crtc_state *crtc_state, | |
2831 | const struct intel_plane_state *plane_state) | |
2832 | { | |
2833 | struct drm_device *dev = primary->dev; | |
2834 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2835 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
2836 | struct drm_framebuffer *fb = plane_state->base.fb; | |
2837 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
2838 | int plane = intel_crtc->plane; | |
54ea9da8 | 2839 | u32 linear_offset; |
a8d201af ML |
2840 | u32 dspcntr; |
2841 | i915_reg_t reg = DSPCNTR(plane); | |
ac484963 | 2842 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
a8d201af ML |
2843 | int x = plane_state->src.x1 >> 16; |
2844 | int y = plane_state->src.y1 >> 16; | |
c9ba6fad | 2845 | |
f45651ba | 2846 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
fdd508a6 | 2847 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2848 | |
2849 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2850 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2851 | |
57779d06 VS |
2852 | switch (fb->pixel_format) { |
2853 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2854 | dspcntr |= DISPPLANE_8BPP; |
2855 | break; | |
57779d06 VS |
2856 | case DRM_FORMAT_RGB565: |
2857 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2858 | break; |
57779d06 | 2859 | case DRM_FORMAT_XRGB8888: |
57779d06 VS |
2860 | dspcntr |= DISPPLANE_BGRX888; |
2861 | break; | |
2862 | case DRM_FORMAT_XBGR8888: | |
57779d06 VS |
2863 | dspcntr |= DISPPLANE_RGBX888; |
2864 | break; | |
2865 | case DRM_FORMAT_XRGB2101010: | |
57779d06 VS |
2866 | dspcntr |= DISPPLANE_BGRX101010; |
2867 | break; | |
2868 | case DRM_FORMAT_XBGR2101010: | |
57779d06 | 2869 | dspcntr |= DISPPLANE_RGBX101010; |
17638cd6 JB |
2870 | break; |
2871 | default: | |
baba133a | 2872 | BUG(); |
17638cd6 JB |
2873 | } |
2874 | ||
2875 | if (obj->tiling_mode != I915_TILING_NONE) | |
2876 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2877 | |
f45651ba | 2878 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2879 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2880 | |
ac484963 | 2881 | linear_offset = y * fb->pitches[0] + x * cpp; |
c2c75131 | 2882 | intel_crtc->dspaddr_offset = |
ce1e5c14 | 2883 | intel_compute_tile_offset(dev_priv, &x, &y, |
ac484963 | 2884 | fb->modifier[0], cpp, |
ce1e5c14 | 2885 | fb->pitches[0]); |
c2c75131 | 2886 | linear_offset -= intel_crtc->dspaddr_offset; |
a8d201af | 2887 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) { |
48404c1e SJ |
2888 | dspcntr |= DISPPLANE_ROTATE_180; |
2889 | ||
2890 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
a8d201af ML |
2891 | x += (crtc_state->pipe_src_w - 1); |
2892 | y += (crtc_state->pipe_src_h - 1); | |
48404c1e SJ |
2893 | |
2894 | /* Finding the last pixel of the last line of the display | |
2895 | data and adding to linear_offset*/ | |
2896 | linear_offset += | |
a8d201af | 2897 | (crtc_state->pipe_src_h - 1) * fb->pitches[0] + |
ac484963 | 2898 | (crtc_state->pipe_src_w - 1) * cpp; |
48404c1e SJ |
2899 | } |
2900 | } | |
2901 | ||
2db3366b PZ |
2902 | intel_crtc->adjusted_x = x; |
2903 | intel_crtc->adjusted_y = y; | |
2904 | ||
48404c1e | 2905 | I915_WRITE(reg, dspcntr); |
17638cd6 | 2906 | |
01f2c773 | 2907 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2908 | I915_WRITE(DSPSURF(plane), |
2909 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2910 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2911 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2912 | } else { | |
2913 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2914 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2915 | } | |
17638cd6 | 2916 | POSTING_READ(reg); |
17638cd6 JB |
2917 | } |
2918 | ||
7b49f948 VS |
2919 | u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv, |
2920 | uint64_t fb_modifier, uint32_t pixel_format) | |
b321803d | 2921 | { |
7b49f948 | 2922 | if (fb_modifier == DRM_FORMAT_MOD_NONE) { |
b321803d | 2923 | return 64; |
7b49f948 VS |
2924 | } else { |
2925 | int cpp = drm_format_plane_cpp(pixel_format, 0); | |
2926 | ||
2927 | return intel_tile_width(dev_priv, fb_modifier, cpp); | |
b321803d DL |
2928 | } |
2929 | } | |
2930 | ||
44eb0cb9 MK |
2931 | u32 intel_plane_obj_offset(struct intel_plane *intel_plane, |
2932 | struct drm_i915_gem_object *obj, | |
2933 | unsigned int plane) | |
121920fa | 2934 | { |
ce7f1728 | 2935 | struct i915_ggtt_view view; |
dedf278c | 2936 | struct i915_vma *vma; |
44eb0cb9 | 2937 | u64 offset; |
121920fa | 2938 | |
e7941294 | 2939 | intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb, |
ce7f1728 | 2940 | intel_plane->base.state); |
121920fa | 2941 | |
ce7f1728 | 2942 | vma = i915_gem_obj_to_ggtt_view(obj, &view); |
dedf278c | 2943 | if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n", |
ce7f1728 | 2944 | view.type)) |
dedf278c TU |
2945 | return -1; |
2946 | ||
44eb0cb9 | 2947 | offset = vma->node.start; |
dedf278c TU |
2948 | |
2949 | if (plane == 1) { | |
7723f47d | 2950 | offset += vma->ggtt_view.params.rotated.uv_start_page * |
dedf278c TU |
2951 | PAGE_SIZE; |
2952 | } | |
2953 | ||
44eb0cb9 MK |
2954 | WARN_ON(upper_32_bits(offset)); |
2955 | ||
2956 | return lower_32_bits(offset); | |
121920fa TU |
2957 | } |
2958 | ||
e435d6e5 ML |
2959 | static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id) |
2960 | { | |
2961 | struct drm_device *dev = intel_crtc->base.dev; | |
2962 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2963 | ||
2964 | I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0); | |
2965 | I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0); | |
2966 | I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0); | |
e435d6e5 ML |
2967 | } |
2968 | ||
a1b2278e CK |
2969 | /* |
2970 | * This function detaches (aka. unbinds) unused scalers in hardware | |
2971 | */ | |
0583236e | 2972 | static void skl_detach_scalers(struct intel_crtc *intel_crtc) |
a1b2278e | 2973 | { |
a1b2278e CK |
2974 | struct intel_crtc_scaler_state *scaler_state; |
2975 | int i; | |
2976 | ||
a1b2278e CK |
2977 | scaler_state = &intel_crtc->config->scaler_state; |
2978 | ||
2979 | /* loop through and disable scalers that aren't in use */ | |
2980 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
e435d6e5 ML |
2981 | if (!scaler_state->scalers[i].in_use) |
2982 | skl_detach_scaler(intel_crtc, i); | |
a1b2278e CK |
2983 | } |
2984 | } | |
2985 | ||
6156a456 | 2986 | u32 skl_plane_ctl_format(uint32_t pixel_format) |
70d21f0e | 2987 | { |
6156a456 | 2988 | switch (pixel_format) { |
d161cf7a | 2989 | case DRM_FORMAT_C8: |
c34ce3d1 | 2990 | return PLANE_CTL_FORMAT_INDEXED; |
70d21f0e | 2991 | case DRM_FORMAT_RGB565: |
c34ce3d1 | 2992 | return PLANE_CTL_FORMAT_RGB_565; |
70d21f0e | 2993 | case DRM_FORMAT_XBGR8888: |
c34ce3d1 | 2994 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX; |
6156a456 | 2995 | case DRM_FORMAT_XRGB8888: |
c34ce3d1 | 2996 | return PLANE_CTL_FORMAT_XRGB_8888; |
6156a456 CK |
2997 | /* |
2998 | * XXX: For ARBG/ABGR formats we default to expecting scanout buffers | |
2999 | * to be already pre-multiplied. We need to add a knob (or a different | |
3000 | * DRM_FORMAT) for user-space to configure that. | |
3001 | */ | |
f75fb42a | 3002 | case DRM_FORMAT_ABGR8888: |
c34ce3d1 | 3003 | return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX | |
6156a456 | 3004 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
6156a456 | 3005 | case DRM_FORMAT_ARGB8888: |
c34ce3d1 | 3006 | return PLANE_CTL_FORMAT_XRGB_8888 | |
6156a456 | 3007 | PLANE_CTL_ALPHA_SW_PREMULTIPLY; |
70d21f0e | 3008 | case DRM_FORMAT_XRGB2101010: |
c34ce3d1 | 3009 | return PLANE_CTL_FORMAT_XRGB_2101010; |
70d21f0e | 3010 | case DRM_FORMAT_XBGR2101010: |
c34ce3d1 | 3011 | return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010; |
6156a456 | 3012 | case DRM_FORMAT_YUYV: |
c34ce3d1 | 3013 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV; |
6156a456 | 3014 | case DRM_FORMAT_YVYU: |
c34ce3d1 | 3015 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU; |
6156a456 | 3016 | case DRM_FORMAT_UYVY: |
c34ce3d1 | 3017 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY; |
6156a456 | 3018 | case DRM_FORMAT_VYUY: |
c34ce3d1 | 3019 | return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY; |
70d21f0e | 3020 | default: |
4249eeef | 3021 | MISSING_CASE(pixel_format); |
70d21f0e | 3022 | } |
8cfcba41 | 3023 | |
c34ce3d1 | 3024 | return 0; |
6156a456 | 3025 | } |
70d21f0e | 3026 | |
6156a456 CK |
3027 | u32 skl_plane_ctl_tiling(uint64_t fb_modifier) |
3028 | { | |
6156a456 | 3029 | switch (fb_modifier) { |
30af77c4 | 3030 | case DRM_FORMAT_MOD_NONE: |
70d21f0e | 3031 | break; |
30af77c4 | 3032 | case I915_FORMAT_MOD_X_TILED: |
c34ce3d1 | 3033 | return PLANE_CTL_TILED_X; |
b321803d | 3034 | case I915_FORMAT_MOD_Y_TILED: |
c34ce3d1 | 3035 | return PLANE_CTL_TILED_Y; |
b321803d | 3036 | case I915_FORMAT_MOD_Yf_TILED: |
c34ce3d1 | 3037 | return PLANE_CTL_TILED_YF; |
70d21f0e | 3038 | default: |
6156a456 | 3039 | MISSING_CASE(fb_modifier); |
70d21f0e | 3040 | } |
8cfcba41 | 3041 | |
c34ce3d1 | 3042 | return 0; |
6156a456 | 3043 | } |
70d21f0e | 3044 | |
6156a456 CK |
3045 | u32 skl_plane_ctl_rotation(unsigned int rotation) |
3046 | { | |
3b7a5119 | 3047 | switch (rotation) { |
6156a456 CK |
3048 | case BIT(DRM_ROTATE_0): |
3049 | break; | |
1e8df167 SJ |
3050 | /* |
3051 | * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr | |
3052 | * while i915 HW rotation is clockwise, thats why this swapping. | |
3053 | */ | |
3b7a5119 | 3054 | case BIT(DRM_ROTATE_90): |
1e8df167 | 3055 | return PLANE_CTL_ROTATE_270; |
3b7a5119 | 3056 | case BIT(DRM_ROTATE_180): |
c34ce3d1 | 3057 | return PLANE_CTL_ROTATE_180; |
3b7a5119 | 3058 | case BIT(DRM_ROTATE_270): |
1e8df167 | 3059 | return PLANE_CTL_ROTATE_90; |
6156a456 CK |
3060 | default: |
3061 | MISSING_CASE(rotation); | |
3062 | } | |
3063 | ||
c34ce3d1 | 3064 | return 0; |
6156a456 CK |
3065 | } |
3066 | ||
a8d201af ML |
3067 | static void skylake_update_primary_plane(struct drm_plane *plane, |
3068 | const struct intel_crtc_state *crtc_state, | |
3069 | const struct intel_plane_state *plane_state) | |
6156a456 | 3070 | { |
a8d201af | 3071 | struct drm_device *dev = plane->dev; |
6156a456 | 3072 | struct drm_i915_private *dev_priv = dev->dev_private; |
a8d201af ML |
3073 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); |
3074 | struct drm_framebuffer *fb = plane_state->base.fb; | |
3075 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
6156a456 CK |
3076 | int pipe = intel_crtc->pipe; |
3077 | u32 plane_ctl, stride_div, stride; | |
3078 | u32 tile_height, plane_offset, plane_size; | |
a8d201af | 3079 | unsigned int rotation = plane_state->base.rotation; |
6156a456 | 3080 | int x_offset, y_offset; |
44eb0cb9 | 3081 | u32 surf_addr; |
a8d201af ML |
3082 | int scaler_id = plane_state->scaler_id; |
3083 | int src_x = plane_state->src.x1 >> 16; | |
3084 | int src_y = plane_state->src.y1 >> 16; | |
3085 | int src_w = drm_rect_width(&plane_state->src) >> 16; | |
3086 | int src_h = drm_rect_height(&plane_state->src) >> 16; | |
3087 | int dst_x = plane_state->dst.x1; | |
3088 | int dst_y = plane_state->dst.y1; | |
3089 | int dst_w = drm_rect_width(&plane_state->dst); | |
3090 | int dst_h = drm_rect_height(&plane_state->dst); | |
70d21f0e | 3091 | |
6156a456 CK |
3092 | plane_ctl = PLANE_CTL_ENABLE | |
3093 | PLANE_CTL_PIPE_GAMMA_ENABLE | | |
3094 | PLANE_CTL_PIPE_CSC_ENABLE; | |
3095 | ||
3096 | plane_ctl |= skl_plane_ctl_format(fb->pixel_format); | |
3097 | plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]); | |
3098 | plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE; | |
6156a456 CK |
3099 | plane_ctl |= skl_plane_ctl_rotation(rotation); |
3100 | ||
7b49f948 | 3101 | stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
b321803d | 3102 | fb->pixel_format); |
dedf278c | 3103 | surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0); |
3b7a5119 | 3104 | |
a42e5a23 PZ |
3105 | WARN_ON(drm_rect_width(&plane_state->src) == 0); |
3106 | ||
3b7a5119 | 3107 | if (intel_rotation_90_or_270(rotation)) { |
832be82f VS |
3108 | int cpp = drm_format_plane_cpp(fb->pixel_format, 0); |
3109 | ||
3b7a5119 | 3110 | /* stride = Surface height in tiles */ |
832be82f | 3111 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp); |
3b7a5119 | 3112 | stride = DIV_ROUND_UP(fb->height, tile_height); |
a8d201af ML |
3113 | x_offset = stride * tile_height - src_y - src_h; |
3114 | y_offset = src_x; | |
6156a456 | 3115 | plane_size = (src_w - 1) << 16 | (src_h - 1); |
3b7a5119 SJ |
3116 | } else { |
3117 | stride = fb->pitches[0] / stride_div; | |
a8d201af ML |
3118 | x_offset = src_x; |
3119 | y_offset = src_y; | |
6156a456 | 3120 | plane_size = (src_h - 1) << 16 | (src_w - 1); |
3b7a5119 SJ |
3121 | } |
3122 | plane_offset = y_offset << 16 | x_offset; | |
b321803d | 3123 | |
2db3366b PZ |
3124 | intel_crtc->adjusted_x = x_offset; |
3125 | intel_crtc->adjusted_y = y_offset; | |
3126 | ||
70d21f0e | 3127 | I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl); |
3b7a5119 SJ |
3128 | I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset); |
3129 | I915_WRITE(PLANE_SIZE(pipe, 0), plane_size); | |
3130 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
6156a456 CK |
3131 | |
3132 | if (scaler_id >= 0) { | |
3133 | uint32_t ps_ctrl = 0; | |
3134 | ||
3135 | WARN_ON(!dst_w || !dst_h); | |
3136 | ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) | | |
3137 | crtc_state->scaler_state.scalers[scaler_id].mode; | |
3138 | I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl); | |
3139 | I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0); | |
3140 | I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y); | |
3141 | I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h); | |
3142 | I915_WRITE(PLANE_POS(pipe, 0), 0); | |
3143 | } else { | |
3144 | I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x); | |
3145 | } | |
3146 | ||
121920fa | 3147 | I915_WRITE(PLANE_SURF(pipe, 0), surf_addr); |
70d21f0e DL |
3148 | |
3149 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3150 | } | |
3151 | ||
a8d201af ML |
3152 | static void skylake_disable_primary_plane(struct drm_plane *primary, |
3153 | struct drm_crtc *crtc) | |
17638cd6 JB |
3154 | { |
3155 | struct drm_device *dev = crtc->dev; | |
3156 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a8d201af | 3157 | int pipe = to_intel_crtc(crtc)->pipe; |
17638cd6 | 3158 | |
a8d201af ML |
3159 | I915_WRITE(PLANE_CTL(pipe, 0), 0); |
3160 | I915_WRITE(PLANE_SURF(pipe, 0), 0); | |
3161 | POSTING_READ(PLANE_SURF(pipe, 0)); | |
3162 | } | |
29b9bde6 | 3163 | |
a8d201af ML |
3164 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ |
3165 | static int | |
3166 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
3167 | int x, int y, enum mode_set_atomic state) | |
3168 | { | |
3169 | /* Support for kgdboc is disabled, this needs a major rework. */ | |
3170 | DRM_ERROR("legacy panic handler not supported any more.\n"); | |
3171 | ||
3172 | return -ENODEV; | |
81255565 JB |
3173 | } |
3174 | ||
7514747d | 3175 | static void intel_complete_page_flips(struct drm_device *dev) |
96a02917 | 3176 | { |
96a02917 VS |
3177 | struct drm_crtc *crtc; |
3178 | ||
70e1e0ec | 3179 | for_each_crtc(dev, crtc) { |
96a02917 VS |
3180 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3181 | enum plane plane = intel_crtc->plane; | |
3182 | ||
3183 | intel_prepare_page_flip(dev, plane); | |
3184 | intel_finish_page_flip_plane(dev, plane); | |
3185 | } | |
7514747d VS |
3186 | } |
3187 | ||
3188 | static void intel_update_primary_planes(struct drm_device *dev) | |
3189 | { | |
7514747d | 3190 | struct drm_crtc *crtc; |
96a02917 | 3191 | |
70e1e0ec | 3192 | for_each_crtc(dev, crtc) { |
11c22da6 ML |
3193 | struct intel_plane *plane = to_intel_plane(crtc->primary); |
3194 | struct intel_plane_state *plane_state; | |
96a02917 | 3195 | |
11c22da6 | 3196 | drm_modeset_lock_crtc(crtc, &plane->base); |
11c22da6 ML |
3197 | plane_state = to_intel_plane_state(plane->base.state); |
3198 | ||
a8d201af ML |
3199 | if (plane_state->visible) |
3200 | plane->update_plane(&plane->base, | |
3201 | to_intel_crtc_state(crtc->state), | |
3202 | plane_state); | |
11c22da6 ML |
3203 | |
3204 | drm_modeset_unlock_crtc(crtc); | |
96a02917 VS |
3205 | } |
3206 | } | |
3207 | ||
7514747d VS |
3208 | void intel_prepare_reset(struct drm_device *dev) |
3209 | { | |
3210 | /* no reset support for gen2 */ | |
3211 | if (IS_GEN2(dev)) | |
3212 | return; | |
3213 | ||
3214 | /* reset doesn't touch the display */ | |
3215 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) | |
3216 | return; | |
3217 | ||
3218 | drm_modeset_lock_all(dev); | |
f98ce92f VS |
3219 | /* |
3220 | * Disabling the crtcs gracefully seems nicer. Also the | |
3221 | * g33 docs say we should at least disable all the planes. | |
3222 | */ | |
6b72d486 | 3223 | intel_display_suspend(dev); |
7514747d VS |
3224 | } |
3225 | ||
3226 | void intel_finish_reset(struct drm_device *dev) | |
3227 | { | |
3228 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3229 | ||
3230 | /* | |
3231 | * Flips in the rings will be nuked by the reset, | |
3232 | * so complete all pending flips so that user space | |
3233 | * will get its events and not get stuck. | |
3234 | */ | |
3235 | intel_complete_page_flips(dev); | |
3236 | ||
3237 | /* no reset support for gen2 */ | |
3238 | if (IS_GEN2(dev)) | |
3239 | return; | |
3240 | ||
3241 | /* reset doesn't touch the display */ | |
3242 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) { | |
3243 | /* | |
3244 | * Flips in the rings have been nuked by the reset, | |
3245 | * so update the base address of all primary | |
3246 | * planes to the the last fb to make sure we're | |
3247 | * showing the correct fb after a reset. | |
11c22da6 ML |
3248 | * |
3249 | * FIXME: Atomic will make this obsolete since we won't schedule | |
3250 | * CS-based flips (which might get lost in gpu resets) any more. | |
7514747d VS |
3251 | */ |
3252 | intel_update_primary_planes(dev); | |
3253 | return; | |
3254 | } | |
3255 | ||
3256 | /* | |
3257 | * The display has been reset as well, | |
3258 | * so need a full re-initialization. | |
3259 | */ | |
3260 | intel_runtime_pm_disable_interrupts(dev_priv); | |
3261 | intel_runtime_pm_enable_interrupts(dev_priv); | |
3262 | ||
3263 | intel_modeset_init_hw(dev); | |
3264 | ||
3265 | spin_lock_irq(&dev_priv->irq_lock); | |
3266 | if (dev_priv->display.hpd_irq_setup) | |
3267 | dev_priv->display.hpd_irq_setup(dev); | |
3268 | spin_unlock_irq(&dev_priv->irq_lock); | |
3269 | ||
043e9bda | 3270 | intel_display_resume(dev); |
7514747d VS |
3271 | |
3272 | intel_hpd_init(dev_priv); | |
3273 | ||
3274 | drm_modeset_unlock_all(dev); | |
3275 | } | |
3276 | ||
7d5e3799 CW |
3277 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
3278 | { | |
3279 | struct drm_device *dev = crtc->dev; | |
3280 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3281 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
7d5e3799 CW |
3282 | bool pending; |
3283 | ||
3284 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
3285 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
3286 | return false; | |
3287 | ||
5e2d7afc | 3288 | spin_lock_irq(&dev->event_lock); |
7d5e3799 | 3289 | pending = to_intel_crtc(crtc)->unpin_work != NULL; |
5e2d7afc | 3290 | spin_unlock_irq(&dev->event_lock); |
7d5e3799 CW |
3291 | |
3292 | return pending; | |
3293 | } | |
3294 | ||
bfd16b2a ML |
3295 | static void intel_update_pipe_config(struct intel_crtc *crtc, |
3296 | struct intel_crtc_state *old_crtc_state) | |
e30e8f75 GP |
3297 | { |
3298 | struct drm_device *dev = crtc->base.dev; | |
3299 | struct drm_i915_private *dev_priv = dev->dev_private; | |
bfd16b2a ML |
3300 | struct intel_crtc_state *pipe_config = |
3301 | to_intel_crtc_state(crtc->base.state); | |
e30e8f75 | 3302 | |
bfd16b2a ML |
3303 | /* drm_atomic_helper_update_legacy_modeset_state might not be called. */ |
3304 | crtc->base.mode = crtc->base.state->mode; | |
3305 | ||
3306 | DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n", | |
3307 | old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h, | |
3308 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
e30e8f75 | 3309 | |
44522d85 ML |
3310 | if (HAS_DDI(dev)) |
3311 | intel_set_pipe_csc(&crtc->base); | |
3312 | ||
e30e8f75 GP |
3313 | /* |
3314 | * Update pipe size and adjust fitter if needed: the reason for this is | |
3315 | * that in compute_mode_changes we check the native mode (not the pfit | |
3316 | * mode) to see if we can flip rather than do a full mode set. In the | |
3317 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
3318 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
3319 | * sized surface. | |
e30e8f75 GP |
3320 | */ |
3321 | ||
e30e8f75 | 3322 | I915_WRITE(PIPESRC(crtc->pipe), |
bfd16b2a ML |
3323 | ((pipe_config->pipe_src_w - 1) << 16) | |
3324 | (pipe_config->pipe_src_h - 1)); | |
3325 | ||
3326 | /* on skylake this is done by detaching scalers */ | |
3327 | if (INTEL_INFO(dev)->gen >= 9) { | |
3328 | skl_detach_scalers(crtc); | |
3329 | ||
3330 | if (pipe_config->pch_pfit.enabled) | |
3331 | skylake_pfit_enable(crtc); | |
3332 | } else if (HAS_PCH_SPLIT(dev)) { | |
3333 | if (pipe_config->pch_pfit.enabled) | |
3334 | ironlake_pfit_enable(crtc); | |
3335 | else if (old_crtc_state->pch_pfit.enabled) | |
3336 | ironlake_pfit_disable(crtc, true); | |
e30e8f75 | 3337 | } |
e30e8f75 GP |
3338 | } |
3339 | ||
5e84e1a4 ZW |
3340 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
3341 | { | |
3342 | struct drm_device *dev = crtc->dev; | |
3343 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3344 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3345 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3346 | i915_reg_t reg; |
3347 | u32 temp; | |
5e84e1a4 ZW |
3348 | |
3349 | /* enable normal train */ | |
3350 | reg = FDI_TX_CTL(pipe); | |
3351 | temp = I915_READ(reg); | |
61e499bf | 3352 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
3353 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3354 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
3355 | } else { |
3356 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3357 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 3358 | } |
5e84e1a4 ZW |
3359 | I915_WRITE(reg, temp); |
3360 | ||
3361 | reg = FDI_RX_CTL(pipe); | |
3362 | temp = I915_READ(reg); | |
3363 | if (HAS_PCH_CPT(dev)) { | |
3364 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3365 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
3366 | } else { | |
3367 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3368 | temp |= FDI_LINK_TRAIN_NONE; | |
3369 | } | |
3370 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
3371 | ||
3372 | /* wait one idle pattern time */ | |
3373 | POSTING_READ(reg); | |
3374 | udelay(1000); | |
357555c0 JB |
3375 | |
3376 | /* IVB wants error correction enabled */ | |
3377 | if (IS_IVYBRIDGE(dev)) | |
3378 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
3379 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
3380 | } |
3381 | ||
8db9d77b ZW |
3382 | /* The FDI link training functions for ILK/Ibexpeak. */ |
3383 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
3384 | { | |
3385 | struct drm_device *dev = crtc->dev; | |
3386 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3387 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3388 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3389 | i915_reg_t reg; |
3390 | u32 temp, tries; | |
8db9d77b | 3391 | |
1c8562f6 | 3392 | /* FDI needs bits from pipe first */ |
0fc932b8 | 3393 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 3394 | |
e1a44743 AJ |
3395 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3396 | for train result */ | |
5eddb70b CW |
3397 | reg = FDI_RX_IMR(pipe); |
3398 | temp = I915_READ(reg); | |
e1a44743 AJ |
3399 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3400 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3401 | I915_WRITE(reg, temp); |
3402 | I915_READ(reg); | |
e1a44743 AJ |
3403 | udelay(150); |
3404 | ||
8db9d77b | 3405 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3406 | reg = FDI_TX_CTL(pipe); |
3407 | temp = I915_READ(reg); | |
627eb5a3 | 3408 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3409 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3410 | temp &= ~FDI_LINK_TRAIN_NONE; |
3411 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 3412 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3413 | |
5eddb70b CW |
3414 | reg = FDI_RX_CTL(pipe); |
3415 | temp = I915_READ(reg); | |
8db9d77b ZW |
3416 | temp &= ~FDI_LINK_TRAIN_NONE; |
3417 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
3418 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3419 | ||
3420 | POSTING_READ(reg); | |
8db9d77b ZW |
3421 | udelay(150); |
3422 | ||
5b2adf89 | 3423 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3424 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3425 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3426 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3427 | |
5eddb70b | 3428 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3429 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3430 | temp = I915_READ(reg); |
8db9d77b ZW |
3431 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3432 | ||
3433 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3434 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3435 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3436 | break; |
3437 | } | |
8db9d77b | 3438 | } |
e1a44743 | 3439 | if (tries == 5) |
5eddb70b | 3440 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3441 | |
3442 | /* Train 2 */ | |
5eddb70b CW |
3443 | reg = FDI_TX_CTL(pipe); |
3444 | temp = I915_READ(reg); | |
8db9d77b ZW |
3445 | temp &= ~FDI_LINK_TRAIN_NONE; |
3446 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3447 | I915_WRITE(reg, temp); |
8db9d77b | 3448 | |
5eddb70b CW |
3449 | reg = FDI_RX_CTL(pipe); |
3450 | temp = I915_READ(reg); | |
8db9d77b ZW |
3451 | temp &= ~FDI_LINK_TRAIN_NONE; |
3452 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3453 | I915_WRITE(reg, temp); |
8db9d77b | 3454 | |
5eddb70b CW |
3455 | POSTING_READ(reg); |
3456 | udelay(150); | |
8db9d77b | 3457 | |
5eddb70b | 3458 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3459 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3460 | temp = I915_READ(reg); |
8db9d77b ZW |
3461 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3462 | ||
3463 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3464 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3465 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3466 | break; | |
3467 | } | |
8db9d77b | 3468 | } |
e1a44743 | 3469 | if (tries == 5) |
5eddb70b | 3470 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3471 | |
3472 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3473 | |
8db9d77b ZW |
3474 | } |
3475 | ||
0206e353 | 3476 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3477 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3478 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3479 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3480 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3481 | }; | |
3482 | ||
3483 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3484 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3485 | { | |
3486 | struct drm_device *dev = crtc->dev; | |
3487 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3488 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3489 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3490 | i915_reg_t reg; |
3491 | u32 temp, i, retry; | |
8db9d77b | 3492 | |
e1a44743 AJ |
3493 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3494 | for train result */ | |
5eddb70b CW |
3495 | reg = FDI_RX_IMR(pipe); |
3496 | temp = I915_READ(reg); | |
e1a44743 AJ |
3497 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3498 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3499 | I915_WRITE(reg, temp); |
3500 | ||
3501 | POSTING_READ(reg); | |
e1a44743 AJ |
3502 | udelay(150); |
3503 | ||
8db9d77b | 3504 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3505 | reg = FDI_TX_CTL(pipe); |
3506 | temp = I915_READ(reg); | |
627eb5a3 | 3507 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3508 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
8db9d77b ZW |
3509 | temp &= ~FDI_LINK_TRAIN_NONE; |
3510 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3511 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3512 | /* SNB-B */ | |
3513 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3514 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3515 | |
d74cf324 DV |
3516 | I915_WRITE(FDI_RX_MISC(pipe), |
3517 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3518 | ||
5eddb70b CW |
3519 | reg = FDI_RX_CTL(pipe); |
3520 | temp = I915_READ(reg); | |
8db9d77b ZW |
3521 | if (HAS_PCH_CPT(dev)) { |
3522 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3523 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3524 | } else { | |
3525 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3526 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3527 | } | |
5eddb70b CW |
3528 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3529 | ||
3530 | POSTING_READ(reg); | |
8db9d77b ZW |
3531 | udelay(150); |
3532 | ||
0206e353 | 3533 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3534 | reg = FDI_TX_CTL(pipe); |
3535 | temp = I915_READ(reg); | |
8db9d77b ZW |
3536 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3537 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3538 | I915_WRITE(reg, temp); |
3539 | ||
3540 | POSTING_READ(reg); | |
8db9d77b ZW |
3541 | udelay(500); |
3542 | ||
fa37d39e SP |
3543 | for (retry = 0; retry < 5; retry++) { |
3544 | reg = FDI_RX_IIR(pipe); | |
3545 | temp = I915_READ(reg); | |
3546 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3547 | if (temp & FDI_RX_BIT_LOCK) { | |
3548 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3549 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3550 | break; | |
3551 | } | |
3552 | udelay(50); | |
8db9d77b | 3553 | } |
fa37d39e SP |
3554 | if (retry < 5) |
3555 | break; | |
8db9d77b ZW |
3556 | } |
3557 | if (i == 4) | |
5eddb70b | 3558 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3559 | |
3560 | /* Train 2 */ | |
5eddb70b CW |
3561 | reg = FDI_TX_CTL(pipe); |
3562 | temp = I915_READ(reg); | |
8db9d77b ZW |
3563 | temp &= ~FDI_LINK_TRAIN_NONE; |
3564 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3565 | if (IS_GEN6(dev)) { | |
3566 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3567 | /* SNB-B */ | |
3568 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3569 | } | |
5eddb70b | 3570 | I915_WRITE(reg, temp); |
8db9d77b | 3571 | |
5eddb70b CW |
3572 | reg = FDI_RX_CTL(pipe); |
3573 | temp = I915_READ(reg); | |
8db9d77b ZW |
3574 | if (HAS_PCH_CPT(dev)) { |
3575 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3576 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3577 | } else { | |
3578 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3579 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3580 | } | |
5eddb70b CW |
3581 | I915_WRITE(reg, temp); |
3582 | ||
3583 | POSTING_READ(reg); | |
8db9d77b ZW |
3584 | udelay(150); |
3585 | ||
0206e353 | 3586 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3587 | reg = FDI_TX_CTL(pipe); |
3588 | temp = I915_READ(reg); | |
8db9d77b ZW |
3589 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3590 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3591 | I915_WRITE(reg, temp); |
3592 | ||
3593 | POSTING_READ(reg); | |
8db9d77b ZW |
3594 | udelay(500); |
3595 | ||
fa37d39e SP |
3596 | for (retry = 0; retry < 5; retry++) { |
3597 | reg = FDI_RX_IIR(pipe); | |
3598 | temp = I915_READ(reg); | |
3599 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3600 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3601 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3602 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3603 | break; | |
3604 | } | |
3605 | udelay(50); | |
8db9d77b | 3606 | } |
fa37d39e SP |
3607 | if (retry < 5) |
3608 | break; | |
8db9d77b ZW |
3609 | } |
3610 | if (i == 4) | |
5eddb70b | 3611 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3612 | |
3613 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3614 | } | |
3615 | ||
357555c0 JB |
3616 | /* Manual link training for Ivy Bridge A0 parts */ |
3617 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3618 | { | |
3619 | struct drm_device *dev = crtc->dev; | |
3620 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3621 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3622 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3623 | i915_reg_t reg; |
3624 | u32 temp, i, j; | |
357555c0 JB |
3625 | |
3626 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3627 | for train result */ | |
3628 | reg = FDI_RX_IMR(pipe); | |
3629 | temp = I915_READ(reg); | |
3630 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3631 | temp &= ~FDI_RX_BIT_LOCK; | |
3632 | I915_WRITE(reg, temp); | |
3633 | ||
3634 | POSTING_READ(reg); | |
3635 | udelay(150); | |
3636 | ||
01a415fd DV |
3637 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3638 | I915_READ(FDI_RX_IIR(pipe))); | |
3639 | ||
139ccd3f JB |
3640 | /* Try each vswing and preemphasis setting twice before moving on */ |
3641 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3642 | /* disable first in case we need to retry */ | |
3643 | reg = FDI_TX_CTL(pipe); | |
3644 | temp = I915_READ(reg); | |
3645 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3646 | temp &= ~FDI_TX_ENABLE; | |
3647 | I915_WRITE(reg, temp); | |
357555c0 | 3648 | |
139ccd3f JB |
3649 | reg = FDI_RX_CTL(pipe); |
3650 | temp = I915_READ(reg); | |
3651 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3652 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3653 | temp &= ~FDI_RX_ENABLE; | |
3654 | I915_WRITE(reg, temp); | |
357555c0 | 3655 | |
139ccd3f | 3656 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3657 | reg = FDI_TX_CTL(pipe); |
3658 | temp = I915_READ(reg); | |
139ccd3f | 3659 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
6e3c9717 | 3660 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
139ccd3f | 3661 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; |
357555c0 | 3662 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3663 | temp |= snb_b_fdi_train_param[j/2]; |
3664 | temp |= FDI_COMPOSITE_SYNC; | |
3665 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3666 | |
139ccd3f JB |
3667 | I915_WRITE(FDI_RX_MISC(pipe), |
3668 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3669 | |
139ccd3f | 3670 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3671 | temp = I915_READ(reg); |
139ccd3f JB |
3672 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3673 | temp |= FDI_COMPOSITE_SYNC; | |
3674 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3675 | |
139ccd3f JB |
3676 | POSTING_READ(reg); |
3677 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3678 | |
139ccd3f JB |
3679 | for (i = 0; i < 4; i++) { |
3680 | reg = FDI_RX_IIR(pipe); | |
3681 | temp = I915_READ(reg); | |
3682 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3683 | |
139ccd3f JB |
3684 | if (temp & FDI_RX_BIT_LOCK || |
3685 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3686 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3687 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3688 | i); | |
3689 | break; | |
3690 | } | |
3691 | udelay(1); /* should be 0.5us */ | |
3692 | } | |
3693 | if (i == 4) { | |
3694 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3695 | continue; | |
3696 | } | |
357555c0 | 3697 | |
139ccd3f | 3698 | /* Train 2 */ |
357555c0 JB |
3699 | reg = FDI_TX_CTL(pipe); |
3700 | temp = I915_READ(reg); | |
139ccd3f JB |
3701 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3702 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3703 | I915_WRITE(reg, temp); | |
3704 | ||
3705 | reg = FDI_RX_CTL(pipe); | |
3706 | temp = I915_READ(reg); | |
3707 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3708 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3709 | I915_WRITE(reg, temp); |
3710 | ||
3711 | POSTING_READ(reg); | |
139ccd3f | 3712 | udelay(2); /* should be 1.5us */ |
357555c0 | 3713 | |
139ccd3f JB |
3714 | for (i = 0; i < 4; i++) { |
3715 | reg = FDI_RX_IIR(pipe); | |
3716 | temp = I915_READ(reg); | |
3717 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3718 | |
139ccd3f JB |
3719 | if (temp & FDI_RX_SYMBOL_LOCK || |
3720 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3721 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3722 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3723 | i); | |
3724 | goto train_done; | |
3725 | } | |
3726 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3727 | } |
139ccd3f JB |
3728 | if (i == 4) |
3729 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3730 | } |
357555c0 | 3731 | |
139ccd3f | 3732 | train_done: |
357555c0 JB |
3733 | DRM_DEBUG_KMS("FDI train done.\n"); |
3734 | } | |
3735 | ||
88cefb6c | 3736 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3737 | { |
88cefb6c | 3738 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3739 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3740 | int pipe = intel_crtc->pipe; |
f0f59a00 VS |
3741 | i915_reg_t reg; |
3742 | u32 temp; | |
c64e311e | 3743 | |
c98e9dcf | 3744 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3745 | reg = FDI_RX_CTL(pipe); |
3746 | temp = I915_READ(reg); | |
627eb5a3 | 3747 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
6e3c9717 | 3748 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
dfd07d72 | 3749 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3750 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3751 | ||
3752 | POSTING_READ(reg); | |
c98e9dcf JB |
3753 | udelay(200); |
3754 | ||
3755 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3756 | temp = I915_READ(reg); |
3757 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3758 | ||
3759 | POSTING_READ(reg); | |
c98e9dcf JB |
3760 | udelay(200); |
3761 | ||
20749730 PZ |
3762 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3763 | reg = FDI_TX_CTL(pipe); | |
3764 | temp = I915_READ(reg); | |
3765 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3766 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3767 | |
20749730 PZ |
3768 | POSTING_READ(reg); |
3769 | udelay(100); | |
6be4a607 | 3770 | } |
0e23b99d JB |
3771 | } |
3772 | ||
88cefb6c DV |
3773 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3774 | { | |
3775 | struct drm_device *dev = intel_crtc->base.dev; | |
3776 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3777 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3778 | i915_reg_t reg; |
3779 | u32 temp; | |
88cefb6c DV |
3780 | |
3781 | /* Switch from PCDclk to Rawclk */ | |
3782 | reg = FDI_RX_CTL(pipe); | |
3783 | temp = I915_READ(reg); | |
3784 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3785 | ||
3786 | /* Disable CPU FDI TX PLL */ | |
3787 | reg = FDI_TX_CTL(pipe); | |
3788 | temp = I915_READ(reg); | |
3789 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3790 | ||
3791 | POSTING_READ(reg); | |
3792 | udelay(100); | |
3793 | ||
3794 | reg = FDI_RX_CTL(pipe); | |
3795 | temp = I915_READ(reg); | |
3796 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3797 | ||
3798 | /* Wait for the clocks to turn off. */ | |
3799 | POSTING_READ(reg); | |
3800 | udelay(100); | |
3801 | } | |
3802 | ||
0fc932b8 JB |
3803 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3804 | { | |
3805 | struct drm_device *dev = crtc->dev; | |
3806 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3807 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3808 | int pipe = intel_crtc->pipe; | |
f0f59a00 VS |
3809 | i915_reg_t reg; |
3810 | u32 temp; | |
0fc932b8 JB |
3811 | |
3812 | /* disable CPU FDI tx and PCH FDI rx */ | |
3813 | reg = FDI_TX_CTL(pipe); | |
3814 | temp = I915_READ(reg); | |
3815 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3816 | POSTING_READ(reg); | |
3817 | ||
3818 | reg = FDI_RX_CTL(pipe); | |
3819 | temp = I915_READ(reg); | |
3820 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3821 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3822 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3823 | ||
3824 | POSTING_READ(reg); | |
3825 | udelay(100); | |
3826 | ||
3827 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3828 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3829 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3830 | |
3831 | /* still set train pattern 1 */ | |
3832 | reg = FDI_TX_CTL(pipe); | |
3833 | temp = I915_READ(reg); | |
3834 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3835 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3836 | I915_WRITE(reg, temp); | |
3837 | ||
3838 | reg = FDI_RX_CTL(pipe); | |
3839 | temp = I915_READ(reg); | |
3840 | if (HAS_PCH_CPT(dev)) { | |
3841 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3842 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3843 | } else { | |
3844 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3845 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3846 | } | |
3847 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3848 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3849 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3850 | I915_WRITE(reg, temp); |
3851 | ||
3852 | POSTING_READ(reg); | |
3853 | udelay(100); | |
3854 | } | |
3855 | ||
5dce5b93 CW |
3856 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3857 | { | |
3858 | struct intel_crtc *crtc; | |
3859 | ||
3860 | /* Note that we don't need to be called with mode_config.lock here | |
3861 | * as our list of CRTC objects is static for the lifetime of the | |
3862 | * device and so cannot disappear as we iterate. Similarly, we can | |
3863 | * happily treat the predicates as racy, atomic checks as userspace | |
3864 | * cannot claim and pin a new fb without at least acquring the | |
3865 | * struct_mutex and so serialising with us. | |
3866 | */ | |
d3fcc808 | 3867 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3868 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3869 | continue; | |
3870 | ||
3871 | if (crtc->unpin_work) | |
3872 | intel_wait_for_vblank(dev, crtc->pipe); | |
3873 | ||
3874 | return true; | |
3875 | } | |
3876 | ||
3877 | return false; | |
3878 | } | |
3879 | ||
d6bbafa1 CW |
3880 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3881 | { | |
3882 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3883 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3884 | ||
3885 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3886 | smp_rmb(); | |
3887 | intel_crtc->unpin_work = NULL; | |
3888 | ||
3889 | if (work->event) | |
3890 | drm_send_vblank_event(intel_crtc->base.dev, | |
3891 | intel_crtc->pipe, | |
3892 | work->event); | |
3893 | ||
3894 | drm_crtc_vblank_put(&intel_crtc->base); | |
3895 | ||
3896 | wake_up_all(&dev_priv->pending_flip_queue); | |
3897 | queue_work(dev_priv->wq, &work->work); | |
3898 | ||
3899 | trace_i915_flip_complete(intel_crtc->plane, | |
3900 | work->pending_flip_obj); | |
3901 | } | |
3902 | ||
5008e874 | 3903 | static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3904 | { |
0f91128d | 3905 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3906 | struct drm_i915_private *dev_priv = dev->dev_private; |
5008e874 | 3907 | long ret; |
e6c3a2a6 | 3908 | |
2c10d571 | 3909 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
5008e874 ML |
3910 | |
3911 | ret = wait_event_interruptible_timeout( | |
3912 | dev_priv->pending_flip_queue, | |
3913 | !intel_crtc_has_pending_flip(crtc), | |
3914 | 60*HZ); | |
3915 | ||
3916 | if (ret < 0) | |
3917 | return ret; | |
3918 | ||
3919 | if (ret == 0) { | |
9c787942 | 3920 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2c10d571 | 3921 | |
5e2d7afc | 3922 | spin_lock_irq(&dev->event_lock); |
9c787942 CW |
3923 | if (intel_crtc->unpin_work) { |
3924 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3925 | page_flip_completed(intel_crtc); | |
3926 | } | |
5e2d7afc | 3927 | spin_unlock_irq(&dev->event_lock); |
9c787942 | 3928 | } |
5bb61643 | 3929 | |
5008e874 | 3930 | return 0; |
e6c3a2a6 CW |
3931 | } |
3932 | ||
060f02d8 VS |
3933 | static void lpt_disable_iclkip(struct drm_i915_private *dev_priv) |
3934 | { | |
3935 | u32 temp; | |
3936 | ||
3937 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3938 | ||
3939 | mutex_lock(&dev_priv->sb_lock); | |
3940 | ||
3941 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); | |
3942 | temp |= SBI_SSCCTL_DISABLE; | |
3943 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); | |
3944 | ||
3945 | mutex_unlock(&dev_priv->sb_lock); | |
3946 | } | |
3947 | ||
e615efe4 ED |
3948 | /* Program iCLKIP clock to the desired frequency */ |
3949 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3950 | { | |
3951 | struct drm_device *dev = crtc->dev; | |
3952 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 3953 | int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock; |
e615efe4 ED |
3954 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3955 | u32 temp; | |
3956 | ||
060f02d8 | 3957 | lpt_disable_iclkip(dev_priv); |
e615efe4 ED |
3958 | |
3959 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3960 | if (clock == 20000) { |
e615efe4 ED |
3961 | auxdiv = 1; |
3962 | divsel = 0x41; | |
3963 | phaseinc = 0x20; | |
3964 | } else { | |
3965 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3966 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3967 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3968 | * convert the virtual clock precision to KHz here for higher |
3969 | * precision. | |
3970 | */ | |
3971 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3972 | u32 iclk_pi_range = 64; | |
3973 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3974 | ||
a2572f5c | 3975 | desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, clock); |
e615efe4 ED |
3976 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3977 | pi_value = desired_divisor % iclk_pi_range; | |
3978 | ||
3979 | auxdiv = 0; | |
3980 | divsel = msb_divisor_value - 2; | |
3981 | phaseinc = pi_value; | |
3982 | } | |
3983 | ||
3984 | /* This should not happen with any sane values */ | |
3985 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3986 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3987 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3988 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3989 | ||
3990 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3991 | clock, |
e615efe4 ED |
3992 | auxdiv, |
3993 | divsel, | |
3994 | phasedir, | |
3995 | phaseinc); | |
3996 | ||
060f02d8 VS |
3997 | mutex_lock(&dev_priv->sb_lock); |
3998 | ||
e615efe4 | 3999 | /* Program SSCDIVINTPHASE6 */ |
988d6ee8 | 4000 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
4001 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
4002 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
4003 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
4004 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
4005 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
4006 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 4007 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
4008 | |
4009 | /* Program SSCAUXDIV */ | |
988d6ee8 | 4010 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
4011 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
4012 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 4013 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
4014 | |
4015 | /* Enable modulator and associated divider */ | |
988d6ee8 | 4016 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 4017 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 4018 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 | 4019 | |
060f02d8 VS |
4020 | mutex_unlock(&dev_priv->sb_lock); |
4021 | ||
e615efe4 ED |
4022 | /* Wait for initialization time */ |
4023 | udelay(24); | |
4024 | ||
4025 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
4026 | } | |
4027 | ||
275f01b2 DV |
4028 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
4029 | enum pipe pch_transcoder) | |
4030 | { | |
4031 | struct drm_device *dev = crtc->base.dev; | |
4032 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 4033 | enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; |
275f01b2 DV |
4034 | |
4035 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
4036 | I915_READ(HTOTAL(cpu_transcoder))); | |
4037 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
4038 | I915_READ(HBLANK(cpu_transcoder))); | |
4039 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
4040 | I915_READ(HSYNC(cpu_transcoder))); | |
4041 | ||
4042 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
4043 | I915_READ(VTOTAL(cpu_transcoder))); | |
4044 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
4045 | I915_READ(VBLANK(cpu_transcoder))); | |
4046 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
4047 | I915_READ(VSYNC(cpu_transcoder))); | |
4048 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
4049 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
4050 | } | |
4051 | ||
003632d9 | 4052 | static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable) |
1fbc0d78 DV |
4053 | { |
4054 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4055 | uint32_t temp; | |
4056 | ||
4057 | temp = I915_READ(SOUTH_CHICKEN1); | |
003632d9 | 4058 | if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable) |
1fbc0d78 DV |
4059 | return; |
4060 | ||
4061 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
4062 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
4063 | ||
003632d9 ACO |
4064 | temp &= ~FDI_BC_BIFURCATION_SELECT; |
4065 | if (enable) | |
4066 | temp |= FDI_BC_BIFURCATION_SELECT; | |
4067 | ||
4068 | DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis"); | |
1fbc0d78 DV |
4069 | I915_WRITE(SOUTH_CHICKEN1, temp); |
4070 | POSTING_READ(SOUTH_CHICKEN1); | |
4071 | } | |
4072 | ||
4073 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
4074 | { | |
4075 | struct drm_device *dev = intel_crtc->base.dev; | |
1fbc0d78 DV |
4076 | |
4077 | switch (intel_crtc->pipe) { | |
4078 | case PIPE_A: | |
4079 | break; | |
4080 | case PIPE_B: | |
6e3c9717 | 4081 | if (intel_crtc->config->fdi_lanes > 2) |
003632d9 | 4082 | cpt_set_fdi_bc_bifurcation(dev, false); |
1fbc0d78 | 4083 | else |
003632d9 | 4084 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4085 | |
4086 | break; | |
4087 | case PIPE_C: | |
003632d9 | 4088 | cpt_set_fdi_bc_bifurcation(dev, true); |
1fbc0d78 DV |
4089 | |
4090 | break; | |
4091 | default: | |
4092 | BUG(); | |
4093 | } | |
4094 | } | |
4095 | ||
c48b5305 VS |
4096 | /* Return which DP Port should be selected for Transcoder DP control */ |
4097 | static enum port | |
4098 | intel_trans_dp_port_sel(struct drm_crtc *crtc) | |
4099 | { | |
4100 | struct drm_device *dev = crtc->dev; | |
4101 | struct intel_encoder *encoder; | |
4102 | ||
4103 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
4104 | if (encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
4105 | encoder->type == INTEL_OUTPUT_EDP) | |
4106 | return enc_to_dig_port(&encoder->base)->port; | |
4107 | } | |
4108 | ||
4109 | return -1; | |
4110 | } | |
4111 | ||
f67a559d JB |
4112 | /* |
4113 | * Enable PCH resources required for PCH ports: | |
4114 | * - PCH PLLs | |
4115 | * - FDI training & RX/TX | |
4116 | * - update transcoder timings | |
4117 | * - DP transcoding bits | |
4118 | * - transcoder | |
4119 | */ | |
4120 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
4121 | { |
4122 | struct drm_device *dev = crtc->dev; | |
4123 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4124 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4125 | int pipe = intel_crtc->pipe; | |
f0f59a00 | 4126 | u32 temp; |
2c07245f | 4127 | |
ab9412ba | 4128 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 4129 | |
1fbc0d78 DV |
4130 | if (IS_IVYBRIDGE(dev)) |
4131 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
4132 | ||
cd986abb DV |
4133 | /* Write the TU size bits before fdi link training, so that error |
4134 | * detection works. */ | |
4135 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
4136 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
4137 | ||
3860b2ec VS |
4138 | /* |
4139 | * Sometimes spurious CPU pipe underruns happen during FDI | |
4140 | * training, at least with VGA+HDMI cloning. Suppress them. | |
4141 | */ | |
4142 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4143 | ||
c98e9dcf | 4144 | /* For PCH output, training FDI link */ |
674cf967 | 4145 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 4146 | |
3ad8a208 DV |
4147 | /* We need to program the right clock selection before writing the pixel |
4148 | * mutliplier into the DPLL. */ | |
303b81e0 | 4149 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 4150 | u32 sel; |
4b645f14 | 4151 | |
c98e9dcf | 4152 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
4153 | temp |= TRANS_DPLL_ENABLE(pipe); |
4154 | sel = TRANS_DPLLB_SEL(pipe); | |
6e3c9717 | 4155 | if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
4156 | temp |= sel; |
4157 | else | |
4158 | temp &= ~sel; | |
c98e9dcf | 4159 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 4160 | } |
5eddb70b | 4161 | |
3ad8a208 DV |
4162 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
4163 | * transcoder, and we actually should do this to not upset any PCH | |
4164 | * transcoder that already use the clock when we share it. | |
4165 | * | |
4166 | * Note that enable_shared_dpll tries to do the right thing, but | |
4167 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
4168 | * the right LVDS enable sequence. */ | |
85b3894f | 4169 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 4170 | |
d9b6cb56 JB |
4171 | /* set transcoder timing, panel must allow it */ |
4172 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 4173 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 4174 | |
303b81e0 | 4175 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 4176 | |
3860b2ec VS |
4177 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4178 | ||
c98e9dcf | 4179 | /* For PCH DP, enable TRANS_DP_CTL */ |
6e3c9717 | 4180 | if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) { |
9c4edaee VS |
4181 | const struct drm_display_mode *adjusted_mode = |
4182 | &intel_crtc->config->base.adjusted_mode; | |
dfd07d72 | 4183 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
f0f59a00 | 4184 | i915_reg_t reg = TRANS_DP_CTL(pipe); |
5eddb70b CW |
4185 | temp = I915_READ(reg); |
4186 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
4187 | TRANS_DP_SYNC_MASK | |
4188 | TRANS_DP_BPC_MASK); | |
e3ef4479 | 4189 | temp |= TRANS_DP_OUTPUT_ENABLE; |
9325c9f0 | 4190 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf | 4191 | |
9c4edaee | 4192 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
5eddb70b | 4193 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
9c4edaee | 4194 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 4195 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
4196 | |
4197 | switch (intel_trans_dp_port_sel(crtc)) { | |
c48b5305 | 4198 | case PORT_B: |
5eddb70b | 4199 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf | 4200 | break; |
c48b5305 | 4201 | case PORT_C: |
5eddb70b | 4202 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf | 4203 | break; |
c48b5305 | 4204 | case PORT_D: |
5eddb70b | 4205 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
4206 | break; |
4207 | default: | |
e95d41e1 | 4208 | BUG(); |
32f9d658 | 4209 | } |
2c07245f | 4210 | |
5eddb70b | 4211 | I915_WRITE(reg, temp); |
6be4a607 | 4212 | } |
b52eb4dc | 4213 | |
b8a4f404 | 4214 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
4215 | } |
4216 | ||
1507e5bd PZ |
4217 | static void lpt_pch_enable(struct drm_crtc *crtc) |
4218 | { | |
4219 | struct drm_device *dev = crtc->dev; | |
4220 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4221 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6e3c9717 | 4222 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
1507e5bd | 4223 | |
ab9412ba | 4224 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 4225 | |
8c52b5e8 | 4226 | lpt_program_iclkip(crtc); |
1507e5bd | 4227 | |
0540e488 | 4228 | /* Set transcoder timing. */ |
275f01b2 | 4229 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 4230 | |
937bb610 | 4231 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
4232 | } |
4233 | ||
190f68c5 ACO |
4234 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, |
4235 | struct intel_crtc_state *crtc_state) | |
ee7b9f93 | 4236 | { |
e2b78267 | 4237 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
8bd31e67 | 4238 | struct intel_shared_dpll *pll; |
de419ab6 | 4239 | struct intel_shared_dpll_config *shared_dpll; |
e2b78267 | 4240 | enum intel_dpll_id i; |
00490c22 | 4241 | int max = dev_priv->num_shared_dpll; |
ee7b9f93 | 4242 | |
de419ab6 ML |
4243 | shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state); |
4244 | ||
98b6bd99 DV |
4245 | if (HAS_PCH_IBX(dev_priv->dev)) { |
4246 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 4247 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 4248 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 4249 | |
46edb027 DV |
4250 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
4251 | crtc->base.base.id, pll->name); | |
98b6bd99 | 4252 | |
de419ab6 | 4253 | WARN_ON(shared_dpll[i].crtc_mask); |
f2a69f44 | 4254 | |
98b6bd99 DV |
4255 | goto found; |
4256 | } | |
4257 | ||
bcddf610 S |
4258 | if (IS_BROXTON(dev_priv->dev)) { |
4259 | /* PLL is attached to port in bxt */ | |
4260 | struct intel_encoder *encoder; | |
4261 | struct intel_digital_port *intel_dig_port; | |
4262 | ||
4263 | encoder = intel_ddi_get_crtc_new_encoder(crtc_state); | |
4264 | if (WARN_ON(!encoder)) | |
4265 | return NULL; | |
4266 | ||
4267 | intel_dig_port = enc_to_dig_port(&encoder->base); | |
4268 | /* 1:1 mapping between ports and PLLs */ | |
4269 | i = (enum intel_dpll_id)intel_dig_port->port; | |
4270 | pll = &dev_priv->shared_dplls[i]; | |
4271 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", | |
4272 | crtc->base.base.id, pll->name); | |
de419ab6 | 4273 | WARN_ON(shared_dpll[i].crtc_mask); |
bcddf610 S |
4274 | |
4275 | goto found; | |
00490c22 ML |
4276 | } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv)) |
4277 | /* Do not consider SPLL */ | |
4278 | max = 2; | |
bcddf610 | 4279 | |
00490c22 | 4280 | for (i = 0; i < max; i++) { |
e72f9fbf | 4281 | pll = &dev_priv->shared_dplls[i]; |
ee7b9f93 JB |
4282 | |
4283 | /* Only want to check enabled timings first */ | |
de419ab6 | 4284 | if (shared_dpll[i].crtc_mask == 0) |
ee7b9f93 JB |
4285 | continue; |
4286 | ||
190f68c5 | 4287 | if (memcmp(&crtc_state->dpll_hw_state, |
de419ab6 ML |
4288 | &shared_dpll[i].hw_state, |
4289 | sizeof(crtc_state->dpll_hw_state)) == 0) { | |
8bd31e67 | 4290 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n", |
1e6f2ddc | 4291 | crtc->base.base.id, pll->name, |
de419ab6 | 4292 | shared_dpll[i].crtc_mask, |
8bd31e67 | 4293 | pll->active); |
ee7b9f93 JB |
4294 | goto found; |
4295 | } | |
4296 | } | |
4297 | ||
4298 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
4299 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4300 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4301 | if (shared_dpll[i].crtc_mask == 0) { |
46edb027 DV |
4302 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
4303 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
4304 | goto found; |
4305 | } | |
4306 | } | |
4307 | ||
4308 | return NULL; | |
4309 | ||
4310 | found: | |
de419ab6 ML |
4311 | if (shared_dpll[i].crtc_mask == 0) |
4312 | shared_dpll[i].hw_state = | |
4313 | crtc_state->dpll_hw_state; | |
f2a69f44 | 4314 | |
190f68c5 | 4315 | crtc_state->shared_dpll = i; |
46edb027 DV |
4316 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
4317 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 4318 | |
de419ab6 | 4319 | shared_dpll[i].crtc_mask |= 1 << crtc->pipe; |
e04c7350 | 4320 | |
ee7b9f93 JB |
4321 | return pll; |
4322 | } | |
4323 | ||
de419ab6 | 4324 | static void intel_shared_dpll_commit(struct drm_atomic_state *state) |
8bd31e67 | 4325 | { |
de419ab6 ML |
4326 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
4327 | struct intel_shared_dpll_config *shared_dpll; | |
8bd31e67 ACO |
4328 | struct intel_shared_dpll *pll; |
4329 | enum intel_dpll_id i; | |
4330 | ||
de419ab6 ML |
4331 | if (!to_intel_atomic_state(state)->dpll_set) |
4332 | return; | |
8bd31e67 | 4333 | |
de419ab6 | 4334 | shared_dpll = to_intel_atomic_state(state)->shared_dpll; |
8bd31e67 ACO |
4335 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
4336 | pll = &dev_priv->shared_dplls[i]; | |
de419ab6 | 4337 | pll->config = shared_dpll[i]; |
8bd31e67 ACO |
4338 | } |
4339 | } | |
4340 | ||
a1520318 | 4341 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
4342 | { |
4343 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 4344 | i915_reg_t dslreg = PIPEDSL(pipe); |
d4270e57 JB |
4345 | u32 temp; |
4346 | ||
4347 | temp = I915_READ(dslreg); | |
4348 | udelay(500); | |
4349 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 4350 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 4351 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
4352 | } |
4353 | } | |
4354 | ||
86adf9d7 ML |
4355 | static int |
4356 | skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach, | |
4357 | unsigned scaler_user, int *scaler_id, unsigned int rotation, | |
4358 | int src_w, int src_h, int dst_w, int dst_h) | |
a1b2278e | 4359 | { |
86adf9d7 ML |
4360 | struct intel_crtc_scaler_state *scaler_state = |
4361 | &crtc_state->scaler_state; | |
4362 | struct intel_crtc *intel_crtc = | |
4363 | to_intel_crtc(crtc_state->base.crtc); | |
a1b2278e | 4364 | int need_scaling; |
6156a456 CK |
4365 | |
4366 | need_scaling = intel_rotation_90_or_270(rotation) ? | |
4367 | (src_h != dst_w || src_w != dst_h): | |
4368 | (src_w != dst_w || src_h != dst_h); | |
a1b2278e CK |
4369 | |
4370 | /* | |
4371 | * if plane is being disabled or scaler is no more required or force detach | |
4372 | * - free scaler binded to this plane/crtc | |
4373 | * - in order to do this, update crtc->scaler_usage | |
4374 | * | |
4375 | * Here scaler state in crtc_state is set free so that | |
4376 | * scaler can be assigned to other user. Actual register | |
4377 | * update to free the scaler is done in plane/panel-fit programming. | |
4378 | * For this purpose crtc/plane_state->scaler_id isn't reset here. | |
4379 | */ | |
86adf9d7 | 4380 | if (force_detach || !need_scaling) { |
a1b2278e | 4381 | if (*scaler_id >= 0) { |
86adf9d7 | 4382 | scaler_state->scaler_users &= ~(1 << scaler_user); |
a1b2278e CK |
4383 | scaler_state->scalers[*scaler_id].in_use = 0; |
4384 | ||
86adf9d7 ML |
4385 | DRM_DEBUG_KMS("scaler_user index %u.%u: " |
4386 | "Staged freeing scaler id %d scaler_users = 0x%x\n", | |
4387 | intel_crtc->pipe, scaler_user, *scaler_id, | |
a1b2278e CK |
4388 | scaler_state->scaler_users); |
4389 | *scaler_id = -1; | |
4390 | } | |
4391 | return 0; | |
4392 | } | |
4393 | ||
4394 | /* range checks */ | |
4395 | if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H || | |
4396 | dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H || | |
4397 | ||
4398 | src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H || | |
4399 | dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) { | |
86adf9d7 | 4400 | DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u " |
a1b2278e | 4401 | "size is out of scaler range\n", |
86adf9d7 | 4402 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h); |
a1b2278e CK |
4403 | return -EINVAL; |
4404 | } | |
4405 | ||
86adf9d7 ML |
4406 | /* mark this plane as a scaler user in crtc_state */ |
4407 | scaler_state->scaler_users |= (1 << scaler_user); | |
4408 | DRM_DEBUG_KMS("scaler_user index %u.%u: " | |
4409 | "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n", | |
4410 | intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h, | |
4411 | scaler_state->scaler_users); | |
4412 | ||
4413 | return 0; | |
4414 | } | |
4415 | ||
4416 | /** | |
4417 | * skl_update_scaler_crtc - Stages update to scaler state for a given crtc. | |
4418 | * | |
4419 | * @state: crtc's scaler state | |
86adf9d7 ML |
4420 | * |
4421 | * Return | |
4422 | * 0 - scaler_usage updated successfully | |
4423 | * error - requested scaling cannot be supported or other error condition | |
4424 | */ | |
e435d6e5 | 4425 | int skl_update_scaler_crtc(struct intel_crtc_state *state) |
86adf9d7 ML |
4426 | { |
4427 | struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc); | |
7c5f93b0 | 4428 | const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode; |
86adf9d7 ML |
4429 | |
4430 | DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n", | |
4431 | intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX); | |
4432 | ||
e435d6e5 | 4433 | return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX, |
fa5a7970 | 4434 | &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0), |
86adf9d7 | 4435 | state->pipe_src_w, state->pipe_src_h, |
aad941d5 | 4436 | adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay); |
86adf9d7 ML |
4437 | } |
4438 | ||
4439 | /** | |
4440 | * skl_update_scaler_plane - Stages update to scaler state for a given plane. | |
4441 | * | |
4442 | * @state: crtc's scaler state | |
86adf9d7 ML |
4443 | * @plane_state: atomic plane state to update |
4444 | * | |
4445 | * Return | |
4446 | * 0 - scaler_usage updated successfully | |
4447 | * error - requested scaling cannot be supported or other error condition | |
4448 | */ | |
da20eabd ML |
4449 | static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state, |
4450 | struct intel_plane_state *plane_state) | |
86adf9d7 ML |
4451 | { |
4452 | ||
4453 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
da20eabd ML |
4454 | struct intel_plane *intel_plane = |
4455 | to_intel_plane(plane_state->base.plane); | |
86adf9d7 ML |
4456 | struct drm_framebuffer *fb = plane_state->base.fb; |
4457 | int ret; | |
4458 | ||
4459 | bool force_detach = !fb || !plane_state->visible; | |
4460 | ||
4461 | DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n", | |
4462 | intel_plane->base.base.id, intel_crtc->pipe, | |
4463 | drm_plane_index(&intel_plane->base)); | |
4464 | ||
4465 | ret = skl_update_scaler(crtc_state, force_detach, | |
4466 | drm_plane_index(&intel_plane->base), | |
4467 | &plane_state->scaler_id, | |
4468 | plane_state->base.rotation, | |
4469 | drm_rect_width(&plane_state->src) >> 16, | |
4470 | drm_rect_height(&plane_state->src) >> 16, | |
4471 | drm_rect_width(&plane_state->dst), | |
4472 | drm_rect_height(&plane_state->dst)); | |
4473 | ||
4474 | if (ret || plane_state->scaler_id < 0) | |
4475 | return ret; | |
4476 | ||
a1b2278e | 4477 | /* check colorkey */ |
818ed961 | 4478 | if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) { |
86adf9d7 | 4479 | DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed", |
818ed961 | 4480 | intel_plane->base.base.id); |
a1b2278e CK |
4481 | return -EINVAL; |
4482 | } | |
4483 | ||
4484 | /* Check src format */ | |
86adf9d7 ML |
4485 | switch (fb->pixel_format) { |
4486 | case DRM_FORMAT_RGB565: | |
4487 | case DRM_FORMAT_XBGR8888: | |
4488 | case DRM_FORMAT_XRGB8888: | |
4489 | case DRM_FORMAT_ABGR8888: | |
4490 | case DRM_FORMAT_ARGB8888: | |
4491 | case DRM_FORMAT_XRGB2101010: | |
4492 | case DRM_FORMAT_XBGR2101010: | |
4493 | case DRM_FORMAT_YUYV: | |
4494 | case DRM_FORMAT_YVYU: | |
4495 | case DRM_FORMAT_UYVY: | |
4496 | case DRM_FORMAT_VYUY: | |
4497 | break; | |
4498 | default: | |
4499 | DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n", | |
4500 | intel_plane->base.base.id, fb->base.id, fb->pixel_format); | |
4501 | return -EINVAL; | |
a1b2278e CK |
4502 | } |
4503 | ||
a1b2278e CK |
4504 | return 0; |
4505 | } | |
4506 | ||
e435d6e5 ML |
4507 | static void skylake_scaler_disable(struct intel_crtc *crtc) |
4508 | { | |
4509 | int i; | |
4510 | ||
4511 | for (i = 0; i < crtc->num_scalers; i++) | |
4512 | skl_detach_scaler(crtc, i); | |
4513 | } | |
4514 | ||
4515 | static void skylake_pfit_enable(struct intel_crtc *crtc) | |
bd2e244f JB |
4516 | { |
4517 | struct drm_device *dev = crtc->base.dev; | |
4518 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4519 | int pipe = crtc->pipe; | |
a1b2278e CK |
4520 | struct intel_crtc_scaler_state *scaler_state = |
4521 | &crtc->config->scaler_state; | |
4522 | ||
4523 | DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config); | |
4524 | ||
6e3c9717 | 4525 | if (crtc->config->pch_pfit.enabled) { |
a1b2278e CK |
4526 | int id; |
4527 | ||
4528 | if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) { | |
4529 | DRM_ERROR("Requesting pfit without getting a scaler first\n"); | |
4530 | return; | |
4531 | } | |
4532 | ||
4533 | id = scaler_state->scaler_id; | |
4534 | I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN | | |
4535 | PS_FILTER_MEDIUM | scaler_state->scalers[id].mode); | |
4536 | I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos); | |
4537 | I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size); | |
4538 | ||
4539 | DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id); | |
bd2e244f JB |
4540 | } |
4541 | } | |
4542 | ||
b074cec8 JB |
4543 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
4544 | { | |
4545 | struct drm_device *dev = crtc->base.dev; | |
4546 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4547 | int pipe = crtc->pipe; | |
4548 | ||
6e3c9717 | 4549 | if (crtc->config->pch_pfit.enabled) { |
b074cec8 JB |
4550 | /* Force use of hard-coded filter coefficients |
4551 | * as some pre-programmed values are broken, | |
4552 | * e.g. x201. | |
4553 | */ | |
4554 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4555 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
4556 | PF_PIPE_SEL_IVB(pipe)); | |
4557 | else | |
4558 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
6e3c9717 ACO |
4559 | I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos); |
4560 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size); | |
d4270e57 JB |
4561 | } |
4562 | } | |
4563 | ||
20bc8673 | 4564 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 4565 | { |
cea165c3 VS |
4566 | struct drm_device *dev = crtc->base.dev; |
4567 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 | 4568 | |
6e3c9717 | 4569 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4570 | return; |
4571 | ||
cea165c3 VS |
4572 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
4573 | intel_wait_for_vblank(dev, crtc->pipe); | |
4574 | ||
d77e4531 | 4575 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 4576 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4577 | mutex_lock(&dev_priv->rps.hw_lock); |
4578 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
4579 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4580 | /* Quoting Art Runyan: "its not safe to expect any particular | |
4581 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
4582 | * mailbox." Moreover, the mailbox may return a bogus state, |
4583 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
4584 | */ |
4585 | } else { | |
4586 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
4587 | /* The bit only becomes 1 in the next vblank, so this wait here | |
4588 | * is essentially intel_wait_for_vblank. If we don't have this | |
4589 | * and don't wait for vblanks until the end of crtc_enable, then | |
4590 | * the HW state readout code will complain that the expected | |
4591 | * IPS_CTL value is not the one we read. */ | |
4592 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
4593 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
4594 | } | |
d77e4531 PZ |
4595 | } |
4596 | ||
20bc8673 | 4597 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
4598 | { |
4599 | struct drm_device *dev = crtc->base.dev; | |
4600 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4601 | ||
6e3c9717 | 4602 | if (!crtc->config->ips_enabled) |
d77e4531 PZ |
4603 | return; |
4604 | ||
4605 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 4606 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
4607 | mutex_lock(&dev_priv->rps.hw_lock); |
4608 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
4609 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
4610 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
4611 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
4612 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 4613 | } else { |
2a114cc1 | 4614 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
4615 | POSTING_READ(IPS_CTL); |
4616 | } | |
d77e4531 PZ |
4617 | |
4618 | /* We need to wait for a vblank before we can disable the plane. */ | |
4619 | intel_wait_for_vblank(dev, crtc->pipe); | |
4620 | } | |
4621 | ||
4622 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
4623 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
4624 | { | |
4625 | struct drm_device *dev = crtc->dev; | |
4626 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4627 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4628 | enum pipe pipe = intel_crtc->pipe; | |
d77e4531 PZ |
4629 | int i; |
4630 | bool reenable_ips = false; | |
4631 | ||
4632 | /* The clocks have to be on to load the palette. */ | |
53d9f4e9 | 4633 | if (!crtc->state->active) |
d77e4531 PZ |
4634 | return; |
4635 | ||
50360403 | 4636 | if (HAS_GMCH_DISPLAY(dev_priv->dev)) { |
a65347ba | 4637 | if (intel_crtc->config->has_dsi_encoder) |
d77e4531 PZ |
4638 | assert_dsi_pll_enabled(dev_priv); |
4639 | else | |
4640 | assert_pll_enabled(dev_priv, pipe); | |
4641 | } | |
4642 | ||
d77e4531 PZ |
4643 | /* Workaround : Do not read or write the pipe palette/gamma data while |
4644 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4645 | */ | |
6e3c9717 | 4646 | if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled && |
d77e4531 PZ |
4647 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4648 | GAMMA_MODE_MODE_SPLIT)) { | |
4649 | hsw_disable_ips(intel_crtc); | |
4650 | reenable_ips = true; | |
4651 | } | |
4652 | ||
4653 | for (i = 0; i < 256; i++) { | |
f0f59a00 | 4654 | i915_reg_t palreg; |
f65a9c5b VS |
4655 | |
4656 | if (HAS_GMCH_DISPLAY(dev)) | |
4657 | palreg = PALETTE(pipe, i); | |
4658 | else | |
4659 | palreg = LGC_PALETTE(pipe, i); | |
4660 | ||
4661 | I915_WRITE(palreg, | |
d77e4531 PZ |
4662 | (intel_crtc->lut_r[i] << 16) | |
4663 | (intel_crtc->lut_g[i] << 8) | | |
4664 | intel_crtc->lut_b[i]); | |
4665 | } | |
4666 | ||
4667 | if (reenable_ips) | |
4668 | hsw_enable_ips(intel_crtc); | |
4669 | } | |
4670 | ||
7cac945f | 4671 | static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc) |
d3eedb1a | 4672 | { |
7cac945f | 4673 | if (intel_crtc->overlay) { |
d3eedb1a VS |
4674 | struct drm_device *dev = intel_crtc->base.dev; |
4675 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4676 | ||
4677 | mutex_lock(&dev->struct_mutex); | |
4678 | dev_priv->mm.interruptible = false; | |
4679 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4680 | dev_priv->mm.interruptible = true; | |
4681 | mutex_unlock(&dev->struct_mutex); | |
4682 | } | |
4683 | ||
4684 | /* Let userspace switch the overlay on again. In most cases userspace | |
4685 | * has to recompute where to put it anyway. | |
4686 | */ | |
4687 | } | |
4688 | ||
87d4300a ML |
4689 | /** |
4690 | * intel_post_enable_primary - Perform operations after enabling primary plane | |
4691 | * @crtc: the CRTC whose primary plane was just enabled | |
4692 | * | |
4693 | * Performs potentially sleeping operations that must be done after the primary | |
4694 | * plane is enabled, such as updating FBC and IPS. Note that this may be | |
4695 | * called due to an explicit primary plane update, or due to an implicit | |
4696 | * re-enable that is caused when a sprite plane is updated to no longer | |
4697 | * completely hide the primary plane. | |
4698 | */ | |
4699 | static void | |
4700 | intel_post_enable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4701 | { |
4702 | struct drm_device *dev = crtc->dev; | |
87d4300a | 4703 | struct drm_i915_private *dev_priv = dev->dev_private; |
a5c4d7bc VS |
4704 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4705 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4706 | |
87d4300a ML |
4707 | /* |
4708 | * FIXME IPS should be fine as long as one plane is | |
4709 | * enabled, but in practice it seems to have problems | |
4710 | * when going from primary only to sprite only and vice | |
4711 | * versa. | |
4712 | */ | |
a5c4d7bc VS |
4713 | hsw_enable_ips(intel_crtc); |
4714 | ||
f99d7069 | 4715 | /* |
87d4300a ML |
4716 | * Gen2 reports pipe underruns whenever all planes are disabled. |
4717 | * So don't enable underrun reporting before at least some planes | |
4718 | * are enabled. | |
4719 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4720 | * but leave the pipe running. | |
f99d7069 | 4721 | */ |
87d4300a ML |
4722 | if (IS_GEN2(dev)) |
4723 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4724 | ||
aca7b684 VS |
4725 | /* Underruns don't always raise interrupts, so check manually. */ |
4726 | intel_check_cpu_fifo_underruns(dev_priv); | |
4727 | intel_check_pch_fifo_underruns(dev_priv); | |
a5c4d7bc VS |
4728 | } |
4729 | ||
87d4300a ML |
4730 | /** |
4731 | * intel_pre_disable_primary - Perform operations before disabling primary plane | |
4732 | * @crtc: the CRTC whose primary plane is to be disabled | |
4733 | * | |
4734 | * Performs potentially sleeping operations that must be done before the | |
4735 | * primary plane is disabled, such as updating FBC and IPS. Note that this may | |
4736 | * be called due to an explicit primary plane update, or due to an implicit | |
4737 | * disable that is caused when a sprite plane completely hides the primary | |
4738 | * plane. | |
4739 | */ | |
4740 | static void | |
4741 | intel_pre_disable_primary(struct drm_crtc *crtc) | |
a5c4d7bc VS |
4742 | { |
4743 | struct drm_device *dev = crtc->dev; | |
4744 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4745 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4746 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4747 | |
87d4300a ML |
4748 | /* |
4749 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4750 | * So diasble underrun reporting before all the planes get disabled. | |
4751 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4752 | * but leave the pipe running. | |
4753 | */ | |
4754 | if (IS_GEN2(dev)) | |
4755 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
a5c4d7bc | 4756 | |
87d4300a ML |
4757 | /* |
4758 | * Vblank time updates from the shadow to live plane control register | |
4759 | * are blocked if the memory self-refresh mode is active at that | |
4760 | * moment. So to make sure the plane gets truly disabled, disable | |
4761 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4762 | * will be checked/applied by the HW only at the next frame start | |
4763 | * event which is after the vblank start event, so we need to have a | |
4764 | * wait-for-vblank between disabling the plane and the pipe. | |
4765 | */ | |
262cd2e1 | 4766 | if (HAS_GMCH_DISPLAY(dev)) { |
87d4300a | 4767 | intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 VS |
4768 | dev_priv->wm.vlv.cxsr = false; |
4769 | intel_wait_for_vblank(dev, pipe); | |
4770 | } | |
87d4300a | 4771 | |
87d4300a ML |
4772 | /* |
4773 | * FIXME IPS should be fine as long as one plane is | |
4774 | * enabled, but in practice it seems to have problems | |
4775 | * when going from primary only to sprite only and vice | |
4776 | * versa. | |
4777 | */ | |
a5c4d7bc | 4778 | hsw_disable_ips(intel_crtc); |
87d4300a ML |
4779 | } |
4780 | ||
ac21b225 ML |
4781 | static void intel_post_plane_update(struct intel_crtc *crtc) |
4782 | { | |
4783 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; | |
92826fcd ML |
4784 | struct intel_crtc_state *pipe_config = |
4785 | to_intel_crtc_state(crtc->base.state); | |
ac21b225 | 4786 | struct drm_device *dev = crtc->base.dev; |
ac21b225 ML |
4787 | |
4788 | if (atomic->wait_vblank) | |
4789 | intel_wait_for_vblank(dev, crtc->pipe); | |
4790 | ||
4791 | intel_frontbuffer_flip(dev, atomic->fb_bits); | |
4792 | ||
ab1d3a0e | 4793 | crtc->wm.cxsr_allowed = true; |
852eb00d | 4794 | |
b9001114 | 4795 | if (pipe_config->wm_changed && pipe_config->base.active) |
f015c551 VS |
4796 | intel_update_watermarks(&crtc->base); |
4797 | ||
c80ac854 | 4798 | if (atomic->update_fbc) |
1eb52238 | 4799 | intel_fbc_post_update(crtc); |
ac21b225 ML |
4800 | |
4801 | if (atomic->post_enable_primary) | |
4802 | intel_post_enable_primary(&crtc->base); | |
4803 | ||
ac21b225 ML |
4804 | memset(atomic, 0, sizeof(*atomic)); |
4805 | } | |
4806 | ||
5c74cd73 | 4807 | static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state) |
ac21b225 | 4808 | { |
5c74cd73 | 4809 | struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); |
ac21b225 | 4810 | struct drm_device *dev = crtc->base.dev; |
eddfcbcd | 4811 | struct drm_i915_private *dev_priv = dev->dev_private; |
ac21b225 | 4812 | struct intel_crtc_atomic_commit *atomic = &crtc->atomic; |
ab1d3a0e ML |
4813 | struct intel_crtc_state *pipe_config = |
4814 | to_intel_crtc_state(crtc->base.state); | |
5c74cd73 ML |
4815 | struct drm_atomic_state *old_state = old_crtc_state->base.state; |
4816 | struct drm_plane *primary = crtc->base.primary; | |
4817 | struct drm_plane_state *old_pri_state = | |
4818 | drm_atomic_get_existing_plane_state(old_state, primary); | |
4819 | bool modeset = needs_modeset(&pipe_config->base); | |
ac21b225 | 4820 | |
1eb52238 PZ |
4821 | if (atomic->update_fbc) |
4822 | intel_fbc_pre_update(crtc); | |
ac21b225 | 4823 | |
5c74cd73 ML |
4824 | if (old_pri_state) { |
4825 | struct intel_plane_state *primary_state = | |
4826 | to_intel_plane_state(primary->state); | |
4827 | struct intel_plane_state *old_primary_state = | |
4828 | to_intel_plane_state(old_pri_state); | |
4829 | ||
4830 | if (old_primary_state->visible && | |
4831 | (modeset || !primary_state->visible)) | |
4832 | intel_pre_disable_primary(&crtc->base); | |
4833 | } | |
852eb00d | 4834 | |
ab1d3a0e | 4835 | if (pipe_config->disable_cxsr) { |
852eb00d VS |
4836 | crtc->wm.cxsr_allowed = false; |
4837 | intel_set_memory_cxsr(dev_priv, false); | |
4838 | } | |
92826fcd | 4839 | |
bf220452 | 4840 | if (!needs_modeset(&pipe_config->base) && pipe_config->wm_changed) |
92826fcd | 4841 | intel_update_watermarks(&crtc->base); |
ac21b225 ML |
4842 | } |
4843 | ||
d032ffa0 | 4844 | static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask) |
87d4300a ML |
4845 | { |
4846 | struct drm_device *dev = crtc->dev; | |
4847 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d032ffa0 | 4848 | struct drm_plane *p; |
87d4300a ML |
4849 | int pipe = intel_crtc->pipe; |
4850 | ||
7cac945f | 4851 | intel_crtc_dpms_overlay_disable(intel_crtc); |
27321ae8 | 4852 | |
d032ffa0 ML |
4853 | drm_for_each_plane_mask(p, dev, plane_mask) |
4854 | to_intel_plane(p)->disable_plane(p, crtc); | |
f98551ae | 4855 | |
f99d7069 DV |
4856 | /* |
4857 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4858 | * to compute the mask of flip planes precisely. For the time being | |
4859 | * consider this a flip to a NULL plane. | |
4860 | */ | |
4861 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4862 | } |
4863 | ||
f67a559d JB |
4864 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4865 | { | |
4866 | struct drm_device *dev = crtc->dev; | |
4867 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4868 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4869 | struct intel_encoder *encoder; |
f67a559d | 4870 | int pipe = intel_crtc->pipe; |
f67a559d | 4871 | |
53d9f4e9 | 4872 | if (WARN_ON(intel_crtc->active)) |
f67a559d JB |
4873 | return; |
4874 | ||
81b088ca VS |
4875 | if (intel_crtc->config->has_pch_encoder) |
4876 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
4877 | ||
6e3c9717 | 4878 | if (intel_crtc->config->has_pch_encoder) |
b14b1055 DV |
4879 | intel_prepare_shared_dpll(intel_crtc); |
4880 | ||
6e3c9717 | 4881 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4882 | intel_dp_set_m_n(intel_crtc, M1_N1); |
29407aab DV |
4883 | |
4884 | intel_set_pipe_timings(intel_crtc); | |
4885 | ||
6e3c9717 | 4886 | if (intel_crtc->config->has_pch_encoder) { |
29407aab | 4887 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4888 | &intel_crtc->config->fdi_m_n, NULL); |
29407aab DV |
4889 | } |
4890 | ||
4891 | ironlake_set_pipeconf(crtc); | |
4892 | ||
f67a559d | 4893 | intel_crtc->active = true; |
8664281b | 4894 | |
a72e4c9f | 4895 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
8664281b | 4896 | |
f6736a1a | 4897 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4898 | if (encoder->pre_enable) |
4899 | encoder->pre_enable(encoder); | |
f67a559d | 4900 | |
6e3c9717 | 4901 | if (intel_crtc->config->has_pch_encoder) { |
fff367c7 DV |
4902 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4903 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4904 | * enabling. */ | |
88cefb6c | 4905 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4906 | } else { |
4907 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4908 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4909 | } | |
f67a559d | 4910 | |
b074cec8 | 4911 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4912 | |
9c54c0dd JB |
4913 | /* |
4914 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4915 | * clocks enabled | |
4916 | */ | |
4917 | intel_crtc_load_lut(crtc); | |
4918 | ||
f37fcc2a | 4919 | intel_update_watermarks(crtc); |
e1fdc473 | 4920 | intel_enable_pipe(intel_crtc); |
f67a559d | 4921 | |
6e3c9717 | 4922 | if (intel_crtc->config->has_pch_encoder) |
f67a559d | 4923 | ironlake_pch_enable(crtc); |
c98e9dcf | 4924 | |
f9b61ff6 DV |
4925 | assert_vblank_disabled(crtc); |
4926 | drm_crtc_vblank_on(crtc); | |
4927 | ||
fa5c73b1 DV |
4928 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4929 | encoder->enable(encoder); | |
61b77ddd DV |
4930 | |
4931 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4932 | cpt_verify_modeset(dev, intel_crtc->pipe); |
37ca8d4c VS |
4933 | |
4934 | /* Must wait for vblank to avoid spurious PCH FIFO underruns */ | |
4935 | if (intel_crtc->config->has_pch_encoder) | |
4936 | intel_wait_for_vblank(dev, pipe); | |
4937 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
6be4a607 JB |
4938 | } |
4939 | ||
42db64ef PZ |
4940 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4941 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4942 | { | |
f5adf94e | 4943 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4944 | } |
4945 | ||
4f771f10 PZ |
4946 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4947 | { | |
4948 | struct drm_device *dev = crtc->dev; | |
4949 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4950 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4951 | struct intel_encoder *encoder; | |
99d736a2 ML |
4952 | int pipe = intel_crtc->pipe, hsw_workaround_pipe; |
4953 | struct intel_crtc_state *pipe_config = | |
4954 | to_intel_crtc_state(crtc->state); | |
4f771f10 | 4955 | |
53d9f4e9 | 4956 | if (WARN_ON(intel_crtc->active)) |
4f771f10 PZ |
4957 | return; |
4958 | ||
81b088ca VS |
4959 | if (intel_crtc->config->has_pch_encoder) |
4960 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
4961 | false); | |
4962 | ||
df8ad70c DV |
4963 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4964 | intel_enable_shared_dpll(intel_crtc); | |
4965 | ||
6e3c9717 | 4966 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 4967 | intel_dp_set_m_n(intel_crtc, M1_N1); |
229fca97 DV |
4968 | |
4969 | intel_set_pipe_timings(intel_crtc); | |
4970 | ||
6e3c9717 ACO |
4971 | if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) { |
4972 | I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder), | |
4973 | intel_crtc->config->pixel_multiplier - 1); | |
ebb69c95 CT |
4974 | } |
4975 | ||
6e3c9717 | 4976 | if (intel_crtc->config->has_pch_encoder) { |
229fca97 | 4977 | intel_cpu_transcoder_set_m_n(intel_crtc, |
6e3c9717 | 4978 | &intel_crtc->config->fdi_m_n, NULL); |
229fca97 DV |
4979 | } |
4980 | ||
4981 | haswell_set_pipeconf(crtc); | |
4982 | ||
4983 | intel_set_pipe_csc(crtc); | |
4984 | ||
4f771f10 | 4985 | intel_crtc->active = true; |
8664281b | 4986 | |
6b698516 DV |
4987 | if (intel_crtc->config->has_pch_encoder) |
4988 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
4989 | else | |
4990 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
4991 | ||
7d4aefd0 | 4992 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 PZ |
4993 | if (encoder->pre_enable) |
4994 | encoder->pre_enable(encoder); | |
7d4aefd0 | 4995 | } |
4f771f10 | 4996 | |
d2d65408 | 4997 | if (intel_crtc->config->has_pch_encoder) |
4fe9467d | 4998 | dev_priv->display.fdi_link_train(crtc); |
4fe9467d | 4999 | |
a65347ba | 5000 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5001 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 5002 | |
1c132b44 | 5003 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5004 | skylake_pfit_enable(intel_crtc); |
ff6d9f55 | 5005 | else |
1c132b44 | 5006 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
5007 | |
5008 | /* | |
5009 | * On ILK+ LUT must be loaded before the pipe is running but with | |
5010 | * clocks enabled | |
5011 | */ | |
5012 | intel_crtc_load_lut(crtc); | |
5013 | ||
1f544388 | 5014 | intel_ddi_set_pipe_settings(crtc); |
a65347ba | 5015 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5016 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 5017 | |
f37fcc2a | 5018 | intel_update_watermarks(crtc); |
e1fdc473 | 5019 | intel_enable_pipe(intel_crtc); |
42db64ef | 5020 | |
6e3c9717 | 5021 | if (intel_crtc->config->has_pch_encoder) |
1507e5bd | 5022 | lpt_pch_enable(crtc); |
4f771f10 | 5023 | |
a65347ba | 5024 | if (intel_crtc->config->dp_encoder_is_mst) |
0e32b39c DA |
5025 | intel_ddi_set_vc_payload_alloc(crtc, true); |
5026 | ||
f9b61ff6 DV |
5027 | assert_vblank_disabled(crtc); |
5028 | drm_crtc_vblank_on(crtc); | |
5029 | ||
8807e55b | 5030 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 5031 | encoder->enable(encoder); |
8807e55b JN |
5032 | intel_opregion_notify_encoder(encoder, true); |
5033 | } | |
4f771f10 | 5034 | |
6b698516 DV |
5035 | if (intel_crtc->config->has_pch_encoder) { |
5036 | intel_wait_for_vblank(dev, pipe); | |
5037 | intel_wait_for_vblank(dev, pipe); | |
5038 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); | |
d2d65408 VS |
5039 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5040 | true); | |
6b698516 | 5041 | } |
d2d65408 | 5042 | |
e4916946 PZ |
5043 | /* If we change the relative order between pipe/planes enabling, we need |
5044 | * to change the workaround. */ | |
99d736a2 ML |
5045 | hsw_workaround_pipe = pipe_config->hsw_workaround_pipe; |
5046 | if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) { | |
5047 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5048 | intel_wait_for_vblank(dev, hsw_workaround_pipe); | |
5049 | } | |
4f771f10 PZ |
5050 | } |
5051 | ||
bfd16b2a | 5052 | static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force) |
3f8dce3a DV |
5053 | { |
5054 | struct drm_device *dev = crtc->base.dev; | |
5055 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5056 | int pipe = crtc->pipe; | |
5057 | ||
5058 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
5059 | * it's in use. The hw state code will make sure we get this right. */ | |
bfd16b2a | 5060 | if (force || crtc->config->pch_pfit.enabled) { |
3f8dce3a DV |
5061 | I915_WRITE(PF_CTL(pipe), 0); |
5062 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
5063 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
5064 | } | |
5065 | } | |
5066 | ||
6be4a607 JB |
5067 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
5068 | { | |
5069 | struct drm_device *dev = crtc->dev; | |
5070 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5071 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 5072 | struct intel_encoder *encoder; |
6be4a607 | 5073 | int pipe = intel_crtc->pipe; |
b52eb4dc | 5074 | |
37ca8d4c VS |
5075 | if (intel_crtc->config->has_pch_encoder) |
5076 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false); | |
5077 | ||
ea9d758d DV |
5078 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5079 | encoder->disable(encoder); | |
5080 | ||
f9b61ff6 DV |
5081 | drm_crtc_vblank_off(crtc); |
5082 | assert_vblank_disabled(crtc); | |
5083 | ||
3860b2ec VS |
5084 | /* |
5085 | * Sometimes spurious CPU pipe underruns happen when the | |
5086 | * pipe is already disabled, but FDI RX/TX is still enabled. | |
5087 | * Happens at least with VGA+HDMI cloning. Suppress them. | |
5088 | */ | |
5089 | if (intel_crtc->config->has_pch_encoder) | |
5090 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); | |
5091 | ||
575f7ab7 | 5092 | intel_disable_pipe(intel_crtc); |
32f9d658 | 5093 | |
bfd16b2a | 5094 | ironlake_pfit_disable(intel_crtc, false); |
2c07245f | 5095 | |
3860b2ec | 5096 | if (intel_crtc->config->has_pch_encoder) { |
5a74f70a | 5097 | ironlake_fdi_disable(crtc); |
3860b2ec VS |
5098 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
5099 | } | |
5a74f70a | 5100 | |
bf49ec8c DV |
5101 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5102 | if (encoder->post_disable) | |
5103 | encoder->post_disable(encoder); | |
2c07245f | 5104 | |
6e3c9717 | 5105 | if (intel_crtc->config->has_pch_encoder) { |
d925c59a | 5106 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
6be4a607 | 5107 | |
d925c59a | 5108 | if (HAS_PCH_CPT(dev)) { |
f0f59a00 VS |
5109 | i915_reg_t reg; |
5110 | u32 temp; | |
5111 | ||
d925c59a DV |
5112 | /* disable TRANS_DP_CTL */ |
5113 | reg = TRANS_DP_CTL(pipe); | |
5114 | temp = I915_READ(reg); | |
5115 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
5116 | TRANS_DP_PORT_SEL_MASK); | |
5117 | temp |= TRANS_DP_PORT_SEL_NONE; | |
5118 | I915_WRITE(reg, temp); | |
5119 | ||
5120 | /* disable DPLL_SEL */ | |
5121 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 5122 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 5123 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 5124 | } |
e3421a18 | 5125 | |
d925c59a DV |
5126 | ironlake_fdi_pll_disable(intel_crtc); |
5127 | } | |
81b088ca VS |
5128 | |
5129 | intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true); | |
6be4a607 | 5130 | } |
1b3c7a47 | 5131 | |
4f771f10 | 5132 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 5133 | { |
4f771f10 PZ |
5134 | struct drm_device *dev = crtc->dev; |
5135 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 5136 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 5137 | struct intel_encoder *encoder; |
6e3c9717 | 5138 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee7b9f93 | 5139 | |
d2d65408 VS |
5140 | if (intel_crtc->config->has_pch_encoder) |
5141 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, | |
5142 | false); | |
5143 | ||
8807e55b JN |
5144 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5145 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 5146 | encoder->disable(encoder); |
8807e55b | 5147 | } |
4f771f10 | 5148 | |
f9b61ff6 DV |
5149 | drm_crtc_vblank_off(crtc); |
5150 | assert_vblank_disabled(crtc); | |
5151 | ||
575f7ab7 | 5152 | intel_disable_pipe(intel_crtc); |
4f771f10 | 5153 | |
6e3c9717 | 5154 | if (intel_crtc->config->dp_encoder_is_mst) |
a4bf214f VS |
5155 | intel_ddi_set_vc_payload_alloc(crtc, false); |
5156 | ||
a65347ba | 5157 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5158 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 5159 | |
1c132b44 | 5160 | if (INTEL_INFO(dev)->gen >= 9) |
e435d6e5 | 5161 | skylake_scaler_disable(intel_crtc); |
ff6d9f55 | 5162 | else |
bfd16b2a | 5163 | ironlake_pfit_disable(intel_crtc, false); |
4f771f10 | 5164 | |
a65347ba | 5165 | if (!intel_crtc->config->has_dsi_encoder) |
7d4aefd0 | 5166 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 5167 | |
97b040aa ID |
5168 | for_each_encoder_on_crtc(dev, crtc, encoder) |
5169 | if (encoder->post_disable) | |
5170 | encoder->post_disable(encoder); | |
81b088ca | 5171 | |
92966a37 VS |
5172 | if (intel_crtc->config->has_pch_encoder) { |
5173 | lpt_disable_pch_transcoder(dev_priv); | |
503a74e9 | 5174 | lpt_disable_iclkip(dev_priv); |
92966a37 VS |
5175 | intel_ddi_fdi_disable(crtc); |
5176 | ||
81b088ca VS |
5177 | intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, |
5178 | true); | |
92966a37 | 5179 | } |
4f771f10 PZ |
5180 | } |
5181 | ||
2dd24552 JB |
5182 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
5183 | { | |
5184 | struct drm_device *dev = crtc->base.dev; | |
5185 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 5186 | struct intel_crtc_state *pipe_config = crtc->config; |
2dd24552 | 5187 | |
681a8504 | 5188 | if (!pipe_config->gmch_pfit.control) |
2dd24552 JB |
5189 | return; |
5190 | ||
2dd24552 | 5191 | /* |
c0b03411 DV |
5192 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
5193 | * according to register description and PRM. | |
2dd24552 | 5194 | */ |
c0b03411 DV |
5195 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
5196 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 5197 | |
b074cec8 JB |
5198 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
5199 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
5200 | |
5201 | /* Border color in case we don't scale up to the full screen. Black by | |
5202 | * default, change to something else for debugging. */ | |
5203 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
5204 | } |
5205 | ||
d05410f9 DA |
5206 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
5207 | { | |
5208 | switch (port) { | |
5209 | case PORT_A: | |
6331a704 | 5210 | return POWER_DOMAIN_PORT_DDI_A_LANES; |
d05410f9 | 5211 | case PORT_B: |
6331a704 | 5212 | return POWER_DOMAIN_PORT_DDI_B_LANES; |
d05410f9 | 5213 | case PORT_C: |
6331a704 | 5214 | return POWER_DOMAIN_PORT_DDI_C_LANES; |
d05410f9 | 5215 | case PORT_D: |
6331a704 | 5216 | return POWER_DOMAIN_PORT_DDI_D_LANES; |
d8e19f99 | 5217 | case PORT_E: |
6331a704 | 5218 | return POWER_DOMAIN_PORT_DDI_E_LANES; |
d05410f9 | 5219 | default: |
b9fec167 | 5220 | MISSING_CASE(port); |
d05410f9 DA |
5221 | return POWER_DOMAIN_PORT_OTHER; |
5222 | } | |
5223 | } | |
5224 | ||
25f78f58 VS |
5225 | static enum intel_display_power_domain port_to_aux_power_domain(enum port port) |
5226 | { | |
5227 | switch (port) { | |
5228 | case PORT_A: | |
5229 | return POWER_DOMAIN_AUX_A; | |
5230 | case PORT_B: | |
5231 | return POWER_DOMAIN_AUX_B; | |
5232 | case PORT_C: | |
5233 | return POWER_DOMAIN_AUX_C; | |
5234 | case PORT_D: | |
5235 | return POWER_DOMAIN_AUX_D; | |
5236 | case PORT_E: | |
5237 | /* FIXME: Check VBT for actual wiring of PORT E */ | |
5238 | return POWER_DOMAIN_AUX_D; | |
5239 | default: | |
b9fec167 | 5240 | MISSING_CASE(port); |
25f78f58 VS |
5241 | return POWER_DOMAIN_AUX_A; |
5242 | } | |
5243 | } | |
5244 | ||
319be8ae ID |
5245 | enum intel_display_power_domain |
5246 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
5247 | { | |
5248 | struct drm_device *dev = intel_encoder->base.dev; | |
5249 | struct intel_digital_port *intel_dig_port; | |
5250 | ||
5251 | switch (intel_encoder->type) { | |
5252 | case INTEL_OUTPUT_UNKNOWN: | |
5253 | /* Only DDI platforms should ever use this output type */ | |
5254 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
5255 | case INTEL_OUTPUT_DISPLAYPORT: | |
5256 | case INTEL_OUTPUT_HDMI: | |
5257 | case INTEL_OUTPUT_EDP: | |
5258 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 5259 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
5260 | case INTEL_OUTPUT_DP_MST: |
5261 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5262 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
5263 | case INTEL_OUTPUT_ANALOG: |
5264 | return POWER_DOMAIN_PORT_CRT; | |
5265 | case INTEL_OUTPUT_DSI: | |
5266 | return POWER_DOMAIN_PORT_DSI; | |
5267 | default: | |
5268 | return POWER_DOMAIN_PORT_OTHER; | |
5269 | } | |
5270 | } | |
5271 | ||
25f78f58 VS |
5272 | enum intel_display_power_domain |
5273 | intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder) | |
5274 | { | |
5275 | struct drm_device *dev = intel_encoder->base.dev; | |
5276 | struct intel_digital_port *intel_dig_port; | |
5277 | ||
5278 | switch (intel_encoder->type) { | |
5279 | case INTEL_OUTPUT_UNKNOWN: | |
651174a4 ID |
5280 | case INTEL_OUTPUT_HDMI: |
5281 | /* | |
5282 | * Only DDI platforms should ever use these output types. | |
5283 | * We can get here after the HDMI detect code has already set | |
5284 | * the type of the shared encoder. Since we can't be sure | |
5285 | * what's the status of the given connectors, play safe and | |
5286 | * run the DP detection too. | |
5287 | */ | |
25f78f58 VS |
5288 | WARN_ON_ONCE(!HAS_DDI(dev)); |
5289 | case INTEL_OUTPUT_DISPLAYPORT: | |
5290 | case INTEL_OUTPUT_EDP: | |
5291 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
5292 | return port_to_aux_power_domain(intel_dig_port->port); | |
5293 | case INTEL_OUTPUT_DP_MST: | |
5294 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
5295 | return port_to_aux_power_domain(intel_dig_port->port); | |
5296 | default: | |
b9fec167 | 5297 | MISSING_CASE(intel_encoder->type); |
25f78f58 VS |
5298 | return POWER_DOMAIN_AUX_A; |
5299 | } | |
5300 | } | |
5301 | ||
319be8ae | 5302 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) |
77d22dca | 5303 | { |
319be8ae ID |
5304 | struct drm_device *dev = crtc->dev; |
5305 | struct intel_encoder *intel_encoder; | |
5306 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5307 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca | 5308 | unsigned long mask; |
1a70a728 | 5309 | enum transcoder transcoder = intel_crtc->config->cpu_transcoder; |
77d22dca | 5310 | |
292b990e ML |
5311 | if (!crtc->state->active) |
5312 | return 0; | |
5313 | ||
77d22dca ID |
5314 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); |
5315 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
6e3c9717 ACO |
5316 | if (intel_crtc->config->pch_pfit.enabled || |
5317 | intel_crtc->config->pch_pfit.force_thru) | |
77d22dca ID |
5318 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
5319 | ||
319be8ae ID |
5320 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
5321 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
5322 | ||
77d22dca ID |
5323 | return mask; |
5324 | } | |
5325 | ||
292b990e | 5326 | static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc) |
77d22dca | 5327 | { |
292b990e ML |
5328 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
5329 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5330 | enum intel_display_power_domain domain; | |
5331 | unsigned long domains, new_domains, old_domains; | |
77d22dca | 5332 | |
292b990e ML |
5333 | old_domains = intel_crtc->enabled_power_domains; |
5334 | intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc); | |
77d22dca | 5335 | |
292b990e ML |
5336 | domains = new_domains & ~old_domains; |
5337 | ||
5338 | for_each_power_domain(domain, domains) | |
5339 | intel_display_power_get(dev_priv, domain); | |
5340 | ||
5341 | return old_domains & ~new_domains; | |
5342 | } | |
5343 | ||
5344 | static void modeset_put_power_domains(struct drm_i915_private *dev_priv, | |
5345 | unsigned long domains) | |
5346 | { | |
5347 | enum intel_display_power_domain domain; | |
5348 | ||
5349 | for_each_power_domain(domain, domains) | |
5350 | intel_display_power_put(dev_priv, domain); | |
5351 | } | |
77d22dca | 5352 | |
292b990e ML |
5353 | static void modeset_update_crtc_power_domains(struct drm_atomic_state *state) |
5354 | { | |
1a617b77 | 5355 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
292b990e ML |
5356 | struct drm_device *dev = state->dev; |
5357 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5358 | unsigned long put_domains[I915_MAX_PIPES] = {}; | |
5359 | struct drm_crtc_state *crtc_state; | |
5360 | struct drm_crtc *crtc; | |
5361 | int i; | |
77d22dca | 5362 | |
292b990e ML |
5363 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
5364 | if (needs_modeset(crtc->state)) | |
5365 | put_domains[to_intel_crtc(crtc)->pipe] = | |
5366 | modeset_get_crtc_power_domains(crtc); | |
77d22dca ID |
5367 | } |
5368 | ||
1a617b77 ML |
5369 | if (dev_priv->display.modeset_commit_cdclk && |
5370 | intel_state->dev_cdclk != dev_priv->cdclk_freq) | |
5371 | dev_priv->display.modeset_commit_cdclk(state); | |
50f6e502 | 5372 | |
292b990e ML |
5373 | for (i = 0; i < I915_MAX_PIPES; i++) |
5374 | if (put_domains[i]) | |
5375 | modeset_put_power_domains(dev_priv, put_domains[i]); | |
77d22dca ID |
5376 | } |
5377 | ||
adafdc6f MK |
5378 | static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) |
5379 | { | |
5380 | int max_cdclk_freq = dev_priv->max_cdclk_freq; | |
5381 | ||
5382 | if (INTEL_INFO(dev_priv)->gen >= 9 || | |
5383 | IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
5384 | return max_cdclk_freq; | |
5385 | else if (IS_CHERRYVIEW(dev_priv)) | |
5386 | return max_cdclk_freq*95/100; | |
5387 | else if (INTEL_INFO(dev_priv)->gen < 4) | |
5388 | return 2*max_cdclk_freq*90/100; | |
5389 | else | |
5390 | return max_cdclk_freq*90/100; | |
5391 | } | |
5392 | ||
560a7ae4 DL |
5393 | static void intel_update_max_cdclk(struct drm_device *dev) |
5394 | { | |
5395 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5396 | ||
ef11bdb3 | 5397 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
560a7ae4 DL |
5398 | u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK; |
5399 | ||
5400 | if (limit == SKL_DFSM_CDCLK_LIMIT_675) | |
5401 | dev_priv->max_cdclk_freq = 675000; | |
5402 | else if (limit == SKL_DFSM_CDCLK_LIMIT_540) | |
5403 | dev_priv->max_cdclk_freq = 540000; | |
5404 | else if (limit == SKL_DFSM_CDCLK_LIMIT_450) | |
5405 | dev_priv->max_cdclk_freq = 450000; | |
5406 | else | |
5407 | dev_priv->max_cdclk_freq = 337500; | |
5408 | } else if (IS_BROADWELL(dev)) { | |
5409 | /* | |
5410 | * FIXME with extra cooling we can allow | |
5411 | * 540 MHz for ULX and 675 Mhz for ULT. | |
5412 | * How can we know if extra cooling is | |
5413 | * available? PCI ID, VTB, something else? | |
5414 | */ | |
5415 | if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
5416 | dev_priv->max_cdclk_freq = 450000; | |
5417 | else if (IS_BDW_ULX(dev)) | |
5418 | dev_priv->max_cdclk_freq = 450000; | |
5419 | else if (IS_BDW_ULT(dev)) | |
5420 | dev_priv->max_cdclk_freq = 540000; | |
5421 | else | |
5422 | dev_priv->max_cdclk_freq = 675000; | |
0904deaf MK |
5423 | } else if (IS_CHERRYVIEW(dev)) { |
5424 | dev_priv->max_cdclk_freq = 320000; | |
560a7ae4 DL |
5425 | } else if (IS_VALLEYVIEW(dev)) { |
5426 | dev_priv->max_cdclk_freq = 400000; | |
5427 | } else { | |
5428 | /* otherwise assume cdclk is fixed */ | |
5429 | dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; | |
5430 | } | |
5431 | ||
adafdc6f MK |
5432 | dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv); |
5433 | ||
560a7ae4 DL |
5434 | DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", |
5435 | dev_priv->max_cdclk_freq); | |
adafdc6f MK |
5436 | |
5437 | DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n", | |
5438 | dev_priv->max_dotclk_freq); | |
560a7ae4 DL |
5439 | } |
5440 | ||
5441 | static void intel_update_cdclk(struct drm_device *dev) | |
5442 | { | |
5443 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5444 | ||
5445 | dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
5446 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n", | |
5447 | dev_priv->cdclk_freq); | |
5448 | ||
5449 | /* | |
5450 | * Program the gmbus_freq based on the cdclk frequency. | |
5451 | * BSpec erroneously claims we should aim for 4MHz, but | |
5452 | * in fact 1MHz is the correct frequency. | |
5453 | */ | |
666a4537 | 5454 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
560a7ae4 DL |
5455 | /* |
5456 | * Program the gmbus_freq based on the cdclk frequency. | |
5457 | * BSpec erroneously claims we should aim for 4MHz, but | |
5458 | * in fact 1MHz is the correct frequency. | |
5459 | */ | |
5460 | I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000)); | |
5461 | } | |
5462 | ||
5463 | if (dev_priv->max_cdclk_freq == 0) | |
5464 | intel_update_max_cdclk(dev); | |
5465 | } | |
5466 | ||
70d0c574 | 5467 | static void broxton_set_cdclk(struct drm_device *dev, int frequency) |
f8437dd1 VK |
5468 | { |
5469 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5470 | uint32_t divider; | |
5471 | uint32_t ratio; | |
5472 | uint32_t current_freq; | |
5473 | int ret; | |
5474 | ||
5475 | /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */ | |
5476 | switch (frequency) { | |
5477 | case 144000: | |
5478 | divider = BXT_CDCLK_CD2X_DIV_SEL_4; | |
5479 | ratio = BXT_DE_PLL_RATIO(60); | |
5480 | break; | |
5481 | case 288000: | |
5482 | divider = BXT_CDCLK_CD2X_DIV_SEL_2; | |
5483 | ratio = BXT_DE_PLL_RATIO(60); | |
5484 | break; | |
5485 | case 384000: | |
5486 | divider = BXT_CDCLK_CD2X_DIV_SEL_1_5; | |
5487 | ratio = BXT_DE_PLL_RATIO(60); | |
5488 | break; | |
5489 | case 576000: | |
5490 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5491 | ratio = BXT_DE_PLL_RATIO(60); | |
5492 | break; | |
5493 | case 624000: | |
5494 | divider = BXT_CDCLK_CD2X_DIV_SEL_1; | |
5495 | ratio = BXT_DE_PLL_RATIO(65); | |
5496 | break; | |
5497 | case 19200: | |
5498 | /* | |
5499 | * Bypass frequency with DE PLL disabled. Init ratio, divider | |
5500 | * to suppress GCC warning. | |
5501 | */ | |
5502 | ratio = 0; | |
5503 | divider = 0; | |
5504 | break; | |
5505 | default: | |
5506 | DRM_ERROR("unsupported CDCLK freq %d", frequency); | |
5507 | ||
5508 | return; | |
5509 | } | |
5510 | ||
5511 | mutex_lock(&dev_priv->rps.hw_lock); | |
5512 | /* Inform power controller of upcoming frequency change */ | |
5513 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5514 | 0x80000000); | |
5515 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5516 | ||
5517 | if (ret) { | |
5518 | DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n", | |
5519 | ret, frequency); | |
5520 | return; | |
5521 | } | |
5522 | ||
5523 | current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; | |
5524 | /* convert from .1 fixpoint MHz with -1MHz offset to kHz */ | |
5525 | current_freq = current_freq * 500 + 1000; | |
5526 | ||
5527 | /* | |
5528 | * DE PLL has to be disabled when | |
5529 | * - setting to 19.2MHz (bypass, PLL isn't used) | |
5530 | * - before setting to 624MHz (PLL needs toggling) | |
5531 | * - before setting to any frequency from 624MHz (PLL needs toggling) | |
5532 | */ | |
5533 | if (frequency == 19200 || frequency == 624000 || | |
5534 | current_freq == 624000) { | |
5535 | I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE); | |
5536 | /* Timeout 200us */ | |
5537 | if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK), | |
5538 | 1)) | |
5539 | DRM_ERROR("timout waiting for DE PLL unlock\n"); | |
5540 | } | |
5541 | ||
5542 | if (frequency != 19200) { | |
5543 | uint32_t val; | |
5544 | ||
5545 | val = I915_READ(BXT_DE_PLL_CTL); | |
5546 | val &= ~BXT_DE_PLL_RATIO_MASK; | |
5547 | val |= ratio; | |
5548 | I915_WRITE(BXT_DE_PLL_CTL, val); | |
5549 | ||
5550 | I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE); | |
5551 | /* Timeout 200us */ | |
5552 | if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1)) | |
5553 | DRM_ERROR("timeout waiting for DE PLL lock\n"); | |
5554 | ||
5555 | val = I915_READ(CDCLK_CTL); | |
5556 | val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK; | |
5557 | val |= divider; | |
5558 | /* | |
5559 | * Disable SSA Precharge when CD clock frequency < 500 MHz, | |
5560 | * enable otherwise. | |
5561 | */ | |
5562 | val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5563 | if (frequency >= 500000) | |
5564 | val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE; | |
5565 | ||
5566 | val &= ~CDCLK_FREQ_DECIMAL_MASK; | |
5567 | /* convert from kHz to .1 fixpoint MHz with -1MHz offset */ | |
5568 | val |= (frequency - 1000) / 500; | |
5569 | I915_WRITE(CDCLK_CTL, val); | |
5570 | } | |
5571 | ||
5572 | mutex_lock(&dev_priv->rps.hw_lock); | |
5573 | ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, | |
5574 | DIV_ROUND_UP(frequency, 25000)); | |
5575 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5576 | ||
5577 | if (ret) { | |
5578 | DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n", | |
5579 | ret, frequency); | |
5580 | return; | |
5581 | } | |
5582 | ||
a47871bd | 5583 | intel_update_cdclk(dev); |
f8437dd1 VK |
5584 | } |
5585 | ||
5586 | void broxton_init_cdclk(struct drm_device *dev) | |
5587 | { | |
5588 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5589 | uint32_t val; | |
5590 | ||
5591 | /* | |
5592 | * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT | |
5593 | * or else the reset will hang because there is no PCH to respond. | |
5594 | * Move the handshake programming to initialization sequence. | |
5595 | * Previously was left up to BIOS. | |
5596 | */ | |
5597 | val = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5598 | val &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
5599 | I915_WRITE(HSW_NDE_RSTWRN_OPT, val); | |
5600 | ||
5601 | /* Enable PG1 for cdclk */ | |
5602 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5603 | ||
5604 | /* check if cd clock is enabled */ | |
5605 | if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) { | |
5606 | DRM_DEBUG_KMS("Display already initialized\n"); | |
5607 | return; | |
5608 | } | |
5609 | ||
5610 | /* | |
5611 | * FIXME: | |
5612 | * - The initial CDCLK needs to be read from VBT. | |
5613 | * Need to make this change after VBT has changes for BXT. | |
5614 | * - check if setting the max (or any) cdclk freq is really necessary | |
5615 | * here, it belongs to modeset time | |
5616 | */ | |
5617 | broxton_set_cdclk(dev, 624000); | |
5618 | ||
5619 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
22e02c0b VS |
5620 | POSTING_READ(DBUF_CTL); |
5621 | ||
f8437dd1 VK |
5622 | udelay(10); |
5623 | ||
5624 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5625 | DRM_ERROR("DBuf power enable timeout!\n"); | |
5626 | } | |
5627 | ||
5628 | void broxton_uninit_cdclk(struct drm_device *dev) | |
5629 | { | |
5630 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5631 | ||
5632 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
22e02c0b VS |
5633 | POSTING_READ(DBUF_CTL); |
5634 | ||
f8437dd1 VK |
5635 | udelay(10); |
5636 | ||
5637 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5638 | DRM_ERROR("DBuf power disable timeout!\n"); | |
5639 | ||
5640 | /* Set minimum (bypass) frequency, in effect turning off the DE PLL */ | |
5641 | broxton_set_cdclk(dev, 19200); | |
5642 | ||
5643 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
5644 | } | |
5645 | ||
5d96d8af DL |
5646 | static const struct skl_cdclk_entry { |
5647 | unsigned int freq; | |
5648 | unsigned int vco; | |
5649 | } skl_cdclk_frequencies[] = { | |
5650 | { .freq = 308570, .vco = 8640 }, | |
5651 | { .freq = 337500, .vco = 8100 }, | |
5652 | { .freq = 432000, .vco = 8640 }, | |
5653 | { .freq = 450000, .vco = 8100 }, | |
5654 | { .freq = 540000, .vco = 8100 }, | |
5655 | { .freq = 617140, .vco = 8640 }, | |
5656 | { .freq = 675000, .vco = 8100 }, | |
5657 | }; | |
5658 | ||
5659 | static unsigned int skl_cdclk_decimal(unsigned int freq) | |
5660 | { | |
5661 | return (freq - 1000) / 500; | |
5662 | } | |
5663 | ||
5664 | static unsigned int skl_cdclk_get_vco(unsigned int freq) | |
5665 | { | |
5666 | unsigned int i; | |
5667 | ||
5668 | for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) { | |
5669 | const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i]; | |
5670 | ||
5671 | if (e->freq == freq) | |
5672 | return e->vco; | |
5673 | } | |
5674 | ||
5675 | return 8100; | |
5676 | } | |
5677 | ||
5678 | static void | |
5679 | skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco) | |
5680 | { | |
5681 | unsigned int min_freq; | |
5682 | u32 val; | |
5683 | ||
5684 | /* select the minimum CDCLK before enabling DPLL 0 */ | |
5685 | val = I915_READ(CDCLK_CTL); | |
5686 | val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK; | |
5687 | val |= CDCLK_FREQ_337_308; | |
5688 | ||
5689 | if (required_vco == 8640) | |
5690 | min_freq = 308570; | |
5691 | else | |
5692 | min_freq = 337500; | |
5693 | ||
5694 | val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq); | |
5695 | ||
5696 | I915_WRITE(CDCLK_CTL, val); | |
5697 | POSTING_READ(CDCLK_CTL); | |
5698 | ||
5699 | /* | |
5700 | * We always enable DPLL0 with the lowest link rate possible, but still | |
5701 | * taking into account the VCO required to operate the eDP panel at the | |
5702 | * desired frequency. The usual DP link rates operate with a VCO of | |
5703 | * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640. | |
5704 | * The modeset code is responsible for the selection of the exact link | |
5705 | * rate later on, with the constraint of choosing a frequency that | |
5706 | * works with required_vco. | |
5707 | */ | |
5708 | val = I915_READ(DPLL_CTRL1); | |
5709 | ||
5710 | val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) | | |
5711 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); | |
5712 | val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0); | |
5713 | if (required_vco == 8640) | |
5714 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, | |
5715 | SKL_DPLL0); | |
5716 | else | |
5717 | val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, | |
5718 | SKL_DPLL0); | |
5719 | ||
5720 | I915_WRITE(DPLL_CTRL1, val); | |
5721 | POSTING_READ(DPLL_CTRL1); | |
5722 | ||
5723 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); | |
5724 | ||
5725 | if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5)) | |
5726 | DRM_ERROR("DPLL0 not locked\n"); | |
5727 | } | |
5728 | ||
5729 | static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv) | |
5730 | { | |
5731 | int ret; | |
5732 | u32 val; | |
5733 | ||
5734 | /* inform PCU we want to change CDCLK */ | |
5735 | val = SKL_CDCLK_PREPARE_FOR_CHANGE; | |
5736 | mutex_lock(&dev_priv->rps.hw_lock); | |
5737 | ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val); | |
5738 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5739 | ||
5740 | return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE); | |
5741 | } | |
5742 | ||
5743 | static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv) | |
5744 | { | |
5745 | unsigned int i; | |
5746 | ||
5747 | for (i = 0; i < 15; i++) { | |
5748 | if (skl_cdclk_pcu_ready(dev_priv)) | |
5749 | return true; | |
5750 | udelay(10); | |
5751 | } | |
5752 | ||
5753 | return false; | |
5754 | } | |
5755 | ||
5756 | static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq) | |
5757 | { | |
560a7ae4 | 5758 | struct drm_device *dev = dev_priv->dev; |
5d96d8af DL |
5759 | u32 freq_select, pcu_ack; |
5760 | ||
5761 | DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq); | |
5762 | ||
5763 | if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) { | |
5764 | DRM_ERROR("failed to inform PCU about cdclk change\n"); | |
5765 | return; | |
5766 | } | |
5767 | ||
5768 | /* set CDCLK_CTL */ | |
5769 | switch(freq) { | |
5770 | case 450000: | |
5771 | case 432000: | |
5772 | freq_select = CDCLK_FREQ_450_432; | |
5773 | pcu_ack = 1; | |
5774 | break; | |
5775 | case 540000: | |
5776 | freq_select = CDCLK_FREQ_540; | |
5777 | pcu_ack = 2; | |
5778 | break; | |
5779 | case 308570: | |
5780 | case 337500: | |
5781 | default: | |
5782 | freq_select = CDCLK_FREQ_337_308; | |
5783 | pcu_ack = 0; | |
5784 | break; | |
5785 | case 617140: | |
5786 | case 675000: | |
5787 | freq_select = CDCLK_FREQ_675_617; | |
5788 | pcu_ack = 3; | |
5789 | break; | |
5790 | } | |
5791 | ||
5792 | I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq)); | |
5793 | POSTING_READ(CDCLK_CTL); | |
5794 | ||
5795 | /* inform PCU of the change */ | |
5796 | mutex_lock(&dev_priv->rps.hw_lock); | |
5797 | sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); | |
5798 | mutex_unlock(&dev_priv->rps.hw_lock); | |
560a7ae4 DL |
5799 | |
5800 | intel_update_cdclk(dev); | |
5d96d8af DL |
5801 | } |
5802 | ||
5803 | void skl_uninit_cdclk(struct drm_i915_private *dev_priv) | |
5804 | { | |
5805 | /* disable DBUF power */ | |
5806 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST); | |
5807 | POSTING_READ(DBUF_CTL); | |
5808 | ||
5809 | udelay(10); | |
5810 | ||
5811 | if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE) | |
5812 | DRM_ERROR("DBuf power disable timeout\n"); | |
5813 | ||
ab96c1ee ID |
5814 | /* disable DPLL0 */ |
5815 | I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE); | |
5816 | if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1)) | |
5817 | DRM_ERROR("Couldn't disable DPLL0\n"); | |
5d96d8af DL |
5818 | } |
5819 | ||
5820 | void skl_init_cdclk(struct drm_i915_private *dev_priv) | |
5821 | { | |
5d96d8af DL |
5822 | unsigned int required_vco; |
5823 | ||
39d9b85a GW |
5824 | /* DPLL0 not enabled (happens on early BIOS versions) */ |
5825 | if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) { | |
5826 | /* enable DPLL0 */ | |
5827 | required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk); | |
5828 | skl_dpll0_enable(dev_priv, required_vco); | |
5d96d8af DL |
5829 | } |
5830 | ||
5d96d8af DL |
5831 | /* set CDCLK to the frequency the BIOS chose */ |
5832 | skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk); | |
5833 | ||
5834 | /* enable DBUF power */ | |
5835 | I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST); | |
5836 | POSTING_READ(DBUF_CTL); | |
5837 | ||
5838 | udelay(10); | |
5839 | ||
5840 | if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE)) | |
5841 | DRM_ERROR("DBuf power enable timeout\n"); | |
5842 | } | |
5843 | ||
c73666f3 SK |
5844 | int skl_sanitize_cdclk(struct drm_i915_private *dev_priv) |
5845 | { | |
5846 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
5847 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
5848 | int freq = dev_priv->skl_boot_cdclk; | |
5849 | ||
f1b391a5 SK |
5850 | /* |
5851 | * check if the pre-os intialized the display | |
5852 | * There is SWF18 scratchpad register defined which is set by the | |
5853 | * pre-os which can be used by the OS drivers to check the status | |
5854 | */ | |
5855 | if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0) | |
5856 | goto sanitize; | |
5857 | ||
c73666f3 SK |
5858 | /* Is PLL enabled and locked ? */ |
5859 | if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK))) | |
5860 | goto sanitize; | |
5861 | ||
5862 | /* DPLL okay; verify the cdclock | |
5863 | * | |
5864 | * Noticed in some instances that the freq selection is correct but | |
5865 | * decimal part is programmed wrong from BIOS where pre-os does not | |
5866 | * enable display. Verify the same as well. | |
5867 | */ | |
5868 | if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq))) | |
5869 | /* All well; nothing to sanitize */ | |
5870 | return false; | |
5871 | sanitize: | |
5872 | /* | |
5873 | * As of now initialize with max cdclk till | |
5874 | * we get dynamic cdclk support | |
5875 | * */ | |
5876 | dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq; | |
5877 | skl_init_cdclk(dev_priv); | |
5878 | ||
5879 | /* we did have to sanitize */ | |
5880 | return true; | |
5881 | } | |
5882 | ||
30a970c6 JB |
5883 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
5884 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
5885 | { | |
5886 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5887 | u32 val, cmd; | |
5888 | ||
164dfd28 VK |
5889 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5890 | != dev_priv->cdclk_freq); | |
d60c4473 | 5891 | |
dfcab17e | 5892 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 5893 | cmd = 2; |
dfcab17e | 5894 | else if (cdclk == 266667) |
30a970c6 JB |
5895 | cmd = 1; |
5896 | else | |
5897 | cmd = 0; | |
5898 | ||
5899 | mutex_lock(&dev_priv->rps.hw_lock); | |
5900 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5901 | val &= ~DSPFREQGUAR_MASK; | |
5902 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
5903 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5904 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5905 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
5906 | 50)) { | |
5907 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5908 | } | |
5909 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5910 | ||
54433e91 VS |
5911 | mutex_lock(&dev_priv->sb_lock); |
5912 | ||
dfcab17e | 5913 | if (cdclk == 400000) { |
6bcda4f0 | 5914 | u32 divider; |
30a970c6 | 5915 | |
6bcda4f0 | 5916 | divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; |
30a970c6 | 5917 | |
30a970c6 JB |
5918 | /* adjust cdclk divider */ |
5919 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
87d5d259 | 5920 | val &= ~CCK_FREQUENCY_VALUES; |
30a970c6 JB |
5921 | val |= divider; |
5922 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
5923 | |
5924 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
87d5d259 | 5925 | CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT), |
a877e801 VS |
5926 | 50)) |
5927 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
5928 | } |
5929 | ||
30a970c6 JB |
5930 | /* adjust self-refresh exit latency value */ |
5931 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
5932 | val &= ~0x7f; | |
5933 | ||
5934 | /* | |
5935 | * For high bandwidth configs, we set a higher latency in the bunit | |
5936 | * so that the core display fetch happens in time to avoid underruns. | |
5937 | */ | |
dfcab17e | 5938 | if (cdclk == 400000) |
30a970c6 JB |
5939 | val |= 4500 / 250; /* 4.5 usec */ |
5940 | else | |
5941 | val |= 3000 / 250; /* 3.0 usec */ | |
5942 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
54433e91 | 5943 | |
a580516d | 5944 | mutex_unlock(&dev_priv->sb_lock); |
30a970c6 | 5945 | |
b6283055 | 5946 | intel_update_cdclk(dev); |
30a970c6 JB |
5947 | } |
5948 | ||
383c5a6a VS |
5949 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
5950 | { | |
5951 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5952 | u32 val, cmd; | |
5953 | ||
164dfd28 VK |
5954 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) |
5955 | != dev_priv->cdclk_freq); | |
383c5a6a VS |
5956 | |
5957 | switch (cdclk) { | |
383c5a6a VS |
5958 | case 333333: |
5959 | case 320000: | |
383c5a6a | 5960 | case 266667: |
383c5a6a | 5961 | case 200000: |
383c5a6a VS |
5962 | break; |
5963 | default: | |
5f77eeb0 | 5964 | MISSING_CASE(cdclk); |
383c5a6a VS |
5965 | return; |
5966 | } | |
5967 | ||
9d0d3fda VS |
5968 | /* |
5969 | * Specs are full of misinformation, but testing on actual | |
5970 | * hardware has shown that we just need to write the desired | |
5971 | * CCK divider into the Punit register. | |
5972 | */ | |
5973 | cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1; | |
5974 | ||
383c5a6a VS |
5975 | mutex_lock(&dev_priv->rps.hw_lock); |
5976 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5977 | val &= ~DSPFREQGUAR_MASK_CHV; | |
5978 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
5979 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
5980 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
5981 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
5982 | 50)) { | |
5983 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
5984 | } | |
5985 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5986 | ||
b6283055 | 5987 | intel_update_cdclk(dev); |
383c5a6a VS |
5988 | } |
5989 | ||
30a970c6 JB |
5990 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
5991 | int max_pixclk) | |
5992 | { | |
6bcda4f0 | 5993 | int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000; |
6cca3195 | 5994 | int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90; |
29dc7ef3 | 5995 | |
30a970c6 JB |
5996 | /* |
5997 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
5998 | * 200MHz | |
5999 | * 267MHz | |
29dc7ef3 | 6000 | * 320/333MHz (depends on HPLL freq) |
6cca3195 VS |
6001 | * 400MHz (VLV only) |
6002 | * So we check to see whether we're above 90% (VLV) or 95% (CHV) | |
6003 | * of the lower bin and adjust if needed. | |
e37c67a1 VS |
6004 | * |
6005 | * We seem to get an unstable or solid color picture at 200MHz. | |
6006 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
6007 | * are off. | |
30a970c6 | 6008 | */ |
6cca3195 VS |
6009 | if (!IS_CHERRYVIEW(dev_priv) && |
6010 | max_pixclk > freq_320*limit/100) | |
dfcab17e | 6011 | return 400000; |
6cca3195 | 6012 | else if (max_pixclk > 266667*limit/100) |
29dc7ef3 | 6013 | return freq_320; |
e37c67a1 | 6014 | else if (max_pixclk > 0) |
dfcab17e | 6015 | return 266667; |
e37c67a1 VS |
6016 | else |
6017 | return 200000; | |
30a970c6 JB |
6018 | } |
6019 | ||
f8437dd1 VK |
6020 | static int broxton_calc_cdclk(struct drm_i915_private *dev_priv, |
6021 | int max_pixclk) | |
6022 | { | |
6023 | /* | |
6024 | * FIXME: | |
6025 | * - remove the guardband, it's not needed on BXT | |
6026 | * - set 19.2MHz bypass frequency if there are no active pipes | |
6027 | */ | |
6028 | if (max_pixclk > 576000*9/10) | |
6029 | return 624000; | |
6030 | else if (max_pixclk > 384000*9/10) | |
6031 | return 576000; | |
6032 | else if (max_pixclk > 288000*9/10) | |
6033 | return 384000; | |
6034 | else if (max_pixclk > 144000*9/10) | |
6035 | return 288000; | |
6036 | else | |
6037 | return 144000; | |
6038 | } | |
6039 | ||
a821fc46 ACO |
6040 | /* Compute the max pixel clock for new configuration. Uses atomic state if |
6041 | * that's non-NULL, look at current state otherwise. */ | |
6042 | static int intel_mode_max_pixclk(struct drm_device *dev, | |
6043 | struct drm_atomic_state *state) | |
30a970c6 | 6044 | { |
565602d7 ML |
6045 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
6046 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6047 | struct drm_crtc *crtc; | |
6048 | struct drm_crtc_state *crtc_state; | |
6049 | unsigned max_pixclk = 0, i; | |
6050 | enum pipe pipe; | |
30a970c6 | 6051 | |
565602d7 ML |
6052 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
6053 | sizeof(intel_state->min_pixclk)); | |
304603f4 | 6054 | |
565602d7 ML |
6055 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
6056 | int pixclk = 0; | |
6057 | ||
6058 | if (crtc_state->enable) | |
6059 | pixclk = crtc_state->adjusted_mode.crtc_clock; | |
304603f4 | 6060 | |
565602d7 | 6061 | intel_state->min_pixclk[i] = pixclk; |
30a970c6 JB |
6062 | } |
6063 | ||
565602d7 ML |
6064 | if (!intel_state->active_crtcs) |
6065 | return 0; | |
6066 | ||
6067 | for_each_pipe(dev_priv, pipe) | |
6068 | max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk); | |
6069 | ||
30a970c6 JB |
6070 | return max_pixclk; |
6071 | } | |
6072 | ||
27c329ed | 6073 | static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state) |
30a970c6 | 6074 | { |
27c329ed ML |
6075 | struct drm_device *dev = state->dev; |
6076 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6077 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
1a617b77 ML |
6078 | struct intel_atomic_state *intel_state = |
6079 | to_intel_atomic_state(state); | |
30a970c6 | 6080 | |
304603f4 ACO |
6081 | if (max_pixclk < 0) |
6082 | return max_pixclk; | |
30a970c6 | 6083 | |
1a617b77 | 6084 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 6085 | valleyview_calc_cdclk(dev_priv, max_pixclk); |
0a9ab303 | 6086 | |
1a617b77 ML |
6087 | if (!intel_state->active_crtcs) |
6088 | intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0); | |
6089 | ||
27c329ed ML |
6090 | return 0; |
6091 | } | |
304603f4 | 6092 | |
27c329ed ML |
6093 | static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state) |
6094 | { | |
6095 | struct drm_device *dev = state->dev; | |
6096 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6097 | int max_pixclk = intel_mode_max_pixclk(dev, state); | |
1a617b77 ML |
6098 | struct intel_atomic_state *intel_state = |
6099 | to_intel_atomic_state(state); | |
85a96e7a | 6100 | |
27c329ed ML |
6101 | if (max_pixclk < 0) |
6102 | return max_pixclk; | |
85a96e7a | 6103 | |
1a617b77 | 6104 | intel_state->cdclk = intel_state->dev_cdclk = |
27c329ed | 6105 | broxton_calc_cdclk(dev_priv, max_pixclk); |
85a96e7a | 6106 | |
1a617b77 ML |
6107 | if (!intel_state->active_crtcs) |
6108 | intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0); | |
6109 | ||
27c329ed | 6110 | return 0; |
30a970c6 JB |
6111 | } |
6112 | ||
1e69cd74 VS |
6113 | static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv) |
6114 | { | |
6115 | unsigned int credits, default_credits; | |
6116 | ||
6117 | if (IS_CHERRYVIEW(dev_priv)) | |
6118 | default_credits = PFI_CREDIT(12); | |
6119 | else | |
6120 | default_credits = PFI_CREDIT(8); | |
6121 | ||
bfa7df01 | 6122 | if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) { |
1e69cd74 VS |
6123 | /* CHV suggested value is 31 or 63 */ |
6124 | if (IS_CHERRYVIEW(dev_priv)) | |
fcc0008f | 6125 | credits = PFI_CREDIT_63; |
1e69cd74 VS |
6126 | else |
6127 | credits = PFI_CREDIT(15); | |
6128 | } else { | |
6129 | credits = default_credits; | |
6130 | } | |
6131 | ||
6132 | /* | |
6133 | * WA - write default credits before re-programming | |
6134 | * FIXME: should we also set the resend bit here? | |
6135 | */ | |
6136 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6137 | default_credits); | |
6138 | ||
6139 | I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE | | |
6140 | credits | PFI_CREDIT_RESEND); | |
6141 | ||
6142 | /* | |
6143 | * FIXME is this guaranteed to clear | |
6144 | * immediately or should we poll for it? | |
6145 | */ | |
6146 | WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); | |
6147 | } | |
6148 | ||
27c329ed | 6149 | static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
30a970c6 | 6150 | { |
a821fc46 | 6151 | struct drm_device *dev = old_state->dev; |
30a970c6 | 6152 | struct drm_i915_private *dev_priv = dev->dev_private; |
1a617b77 ML |
6153 | struct intel_atomic_state *old_intel_state = |
6154 | to_intel_atomic_state(old_state); | |
6155 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
30a970c6 | 6156 | |
27c329ed ML |
6157 | /* |
6158 | * FIXME: We can end up here with all power domains off, yet | |
6159 | * with a CDCLK frequency other than the minimum. To account | |
6160 | * for this take the PIPE-A power domain, which covers the HW | |
6161 | * blocks needed for the following programming. This can be | |
6162 | * removed once it's guaranteed that we get here either with | |
6163 | * the minimum CDCLK set, or the required power domains | |
6164 | * enabled. | |
6165 | */ | |
6166 | intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A); | |
738c05c0 | 6167 | |
27c329ed ML |
6168 | if (IS_CHERRYVIEW(dev)) |
6169 | cherryview_set_cdclk(dev, req_cdclk); | |
6170 | else | |
6171 | valleyview_set_cdclk(dev, req_cdclk); | |
738c05c0 | 6172 | |
27c329ed | 6173 | vlv_program_pfi_credits(dev_priv); |
1e69cd74 | 6174 | |
27c329ed | 6175 | intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A); |
30a970c6 JB |
6176 | } |
6177 | ||
89b667f8 JB |
6178 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
6179 | { | |
6180 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6181 | struct drm_i915_private *dev_priv = to_i915(dev); |
89b667f8 JB |
6182 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6183 | struct intel_encoder *encoder; | |
6184 | int pipe = intel_crtc->pipe; | |
89b667f8 | 6185 | |
53d9f4e9 | 6186 | if (WARN_ON(intel_crtc->active)) |
89b667f8 JB |
6187 | return; |
6188 | ||
6e3c9717 | 6189 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6190 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6191 | |
6192 | intel_set_pipe_timings(intel_crtc); | |
6193 | ||
c14b0485 VS |
6194 | if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) { |
6195 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6196 | ||
6197 | I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY); | |
6198 | I915_WRITE(CHV_CANVAS(pipe), 0); | |
6199 | } | |
6200 | ||
5b18e57c DV |
6201 | i9xx_set_pipeconf(intel_crtc); |
6202 | ||
89b667f8 | 6203 | intel_crtc->active = true; |
89b667f8 | 6204 | |
a72e4c9f | 6205 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6206 | |
89b667f8 JB |
6207 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6208 | if (encoder->pre_pll_enable) | |
6209 | encoder->pre_pll_enable(encoder); | |
6210 | ||
a65347ba | 6211 | if (!intel_crtc->config->has_dsi_encoder) { |
c0b4c660 VS |
6212 | if (IS_CHERRYVIEW(dev)) { |
6213 | chv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6214 | chv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 VS |
6215 | } else { |
6216 | vlv_prepare_pll(intel_crtc, intel_crtc->config); | |
6e3c9717 | 6217 | vlv_enable_pll(intel_crtc, intel_crtc->config); |
c0b4c660 | 6218 | } |
9d556c99 | 6219 | } |
89b667f8 JB |
6220 | |
6221 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
6222 | if (encoder->pre_enable) | |
6223 | encoder->pre_enable(encoder); | |
6224 | ||
2dd24552 JB |
6225 | i9xx_pfit_enable(intel_crtc); |
6226 | ||
63cbb074 VS |
6227 | intel_crtc_load_lut(crtc); |
6228 | ||
e1fdc473 | 6229 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6230 | |
4b3a9526 VS |
6231 | assert_vblank_disabled(crtc); |
6232 | drm_crtc_vblank_on(crtc); | |
6233 | ||
f9b61ff6 DV |
6234 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6235 | encoder->enable(encoder); | |
89b667f8 JB |
6236 | } |
6237 | ||
f13c2ef3 DV |
6238 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
6239 | { | |
6240 | struct drm_device *dev = crtc->base.dev; | |
6241 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6242 | ||
6e3c9717 ACO |
6243 | I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0); |
6244 | I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1); | |
f13c2ef3 DV |
6245 | } |
6246 | ||
0b8765c6 | 6247 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
6248 | { |
6249 | struct drm_device *dev = crtc->dev; | |
a72e4c9f | 6250 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 6251 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 6252 | struct intel_encoder *encoder; |
79e53945 | 6253 | int pipe = intel_crtc->pipe; |
79e53945 | 6254 | |
53d9f4e9 | 6255 | if (WARN_ON(intel_crtc->active)) |
f7abfe8b CW |
6256 | return; |
6257 | ||
f13c2ef3 DV |
6258 | i9xx_set_pll_dividers(intel_crtc); |
6259 | ||
6e3c9717 | 6260 | if (intel_crtc->config->has_dp_encoder) |
fe3cd48d | 6261 | intel_dp_set_m_n(intel_crtc, M1_N1); |
5b18e57c DV |
6262 | |
6263 | intel_set_pipe_timings(intel_crtc); | |
6264 | ||
5b18e57c DV |
6265 | i9xx_set_pipeconf(intel_crtc); |
6266 | ||
f7abfe8b | 6267 | intel_crtc->active = true; |
6b383a7f | 6268 | |
4a3436e8 | 6269 | if (!IS_GEN2(dev)) |
a72e4c9f | 6270 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true); |
4a3436e8 | 6271 | |
9d6d9f19 MK |
6272 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6273 | if (encoder->pre_enable) | |
6274 | encoder->pre_enable(encoder); | |
6275 | ||
f6736a1a DV |
6276 | i9xx_enable_pll(intel_crtc); |
6277 | ||
2dd24552 JB |
6278 | i9xx_pfit_enable(intel_crtc); |
6279 | ||
63cbb074 VS |
6280 | intel_crtc_load_lut(crtc); |
6281 | ||
f37fcc2a | 6282 | intel_update_watermarks(crtc); |
e1fdc473 | 6283 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 6284 | |
4b3a9526 VS |
6285 | assert_vblank_disabled(crtc); |
6286 | drm_crtc_vblank_on(crtc); | |
6287 | ||
f9b61ff6 DV |
6288 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6289 | encoder->enable(encoder); | |
0b8765c6 | 6290 | } |
79e53945 | 6291 | |
87476d63 DV |
6292 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
6293 | { | |
6294 | struct drm_device *dev = crtc->base.dev; | |
6295 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 6296 | |
6e3c9717 | 6297 | if (!crtc->config->gmch_pfit.control) |
328d8e82 | 6298 | return; |
87476d63 | 6299 | |
328d8e82 | 6300 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 6301 | |
328d8e82 DV |
6302 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
6303 | I915_READ(PFIT_CONTROL)); | |
6304 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
6305 | } |
6306 | ||
0b8765c6 JB |
6307 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
6308 | { | |
6309 | struct drm_device *dev = crtc->dev; | |
6310 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6311 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 6312 | struct intel_encoder *encoder; |
0b8765c6 | 6313 | int pipe = intel_crtc->pipe; |
ef9c3aee | 6314 | |
6304cd91 VS |
6315 | /* |
6316 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
6317 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
6318 | * We also need to wait on all gmch platforms because of the |
6319 | * self-refresh mode constraint explained above. | |
6304cd91 | 6320 | */ |
564ed191 | 6321 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 6322 | |
4b3a9526 VS |
6323 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6324 | encoder->disable(encoder); | |
6325 | ||
f9b61ff6 DV |
6326 | drm_crtc_vblank_off(crtc); |
6327 | assert_vblank_disabled(crtc); | |
6328 | ||
575f7ab7 | 6329 | intel_disable_pipe(intel_crtc); |
24a1f16d | 6330 | |
87476d63 | 6331 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 6332 | |
89b667f8 JB |
6333 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6334 | if (encoder->post_disable) | |
6335 | encoder->post_disable(encoder); | |
6336 | ||
a65347ba | 6337 | if (!intel_crtc->config->has_dsi_encoder) { |
076ed3b2 CML |
6338 | if (IS_CHERRYVIEW(dev)) |
6339 | chv_disable_pll(dev_priv, pipe); | |
6340 | else if (IS_VALLEYVIEW(dev)) | |
6341 | vlv_disable_pll(dev_priv, pipe); | |
6342 | else | |
1c4e0274 | 6343 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 6344 | } |
0b8765c6 | 6345 | |
d6db995f VS |
6346 | for_each_encoder_on_crtc(dev, crtc, encoder) |
6347 | if (encoder->post_pll_disable) | |
6348 | encoder->post_pll_disable(encoder); | |
6349 | ||
4a3436e8 | 6350 | if (!IS_GEN2(dev)) |
a72e4c9f | 6351 | intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false); |
0b8765c6 JB |
6352 | } |
6353 | ||
b17d48e2 ML |
6354 | static void intel_crtc_disable_noatomic(struct drm_crtc *crtc) |
6355 | { | |
6356 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6357 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); | |
6358 | enum intel_display_power_domain domain; | |
6359 | unsigned long domains; | |
6360 | ||
6361 | if (!intel_crtc->active) | |
6362 | return; | |
6363 | ||
a539205a | 6364 | if (to_intel_plane_state(crtc->primary->state)->visible) { |
fc32b1fd ML |
6365 | WARN_ON(intel_crtc->unpin_work); |
6366 | ||
a539205a | 6367 | intel_pre_disable_primary(crtc); |
54a41961 ML |
6368 | |
6369 | intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary)); | |
6370 | to_intel_plane_state(crtc->primary->state)->visible = false; | |
a539205a ML |
6371 | } |
6372 | ||
b17d48e2 | 6373 | dev_priv->display.crtc_disable(crtc); |
37d9078b | 6374 | intel_crtc->active = false; |
58f9c0bc | 6375 | intel_fbc_disable(intel_crtc); |
37d9078b | 6376 | intel_update_watermarks(crtc); |
1f7457b1 | 6377 | intel_disable_shared_dpll(intel_crtc); |
b17d48e2 ML |
6378 | |
6379 | domains = intel_crtc->enabled_power_domains; | |
6380 | for_each_power_domain(domain, domains) | |
6381 | intel_display_power_put(dev_priv, domain); | |
6382 | intel_crtc->enabled_power_domains = 0; | |
565602d7 ML |
6383 | |
6384 | dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe); | |
6385 | dev_priv->min_pixclk[intel_crtc->pipe] = 0; | |
b17d48e2 ML |
6386 | } |
6387 | ||
6b72d486 ML |
6388 | /* |
6389 | * turn all crtc's off, but do not adjust state | |
6390 | * This has to be paired with a call to intel_modeset_setup_hw_state. | |
6391 | */ | |
70e0bd74 | 6392 | int intel_display_suspend(struct drm_device *dev) |
ee7b9f93 | 6393 | { |
70e0bd74 ML |
6394 | struct drm_mode_config *config = &dev->mode_config; |
6395 | struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx; | |
6396 | struct drm_atomic_state *state; | |
6b72d486 | 6397 | struct drm_crtc *crtc; |
70e0bd74 ML |
6398 | unsigned crtc_mask = 0; |
6399 | int ret = 0; | |
6400 | ||
6401 | if (WARN_ON(!ctx)) | |
6402 | return 0; | |
6403 | ||
6404 | lockdep_assert_held(&ctx->ww_ctx); | |
6405 | state = drm_atomic_state_alloc(dev); | |
6406 | if (WARN_ON(!state)) | |
6407 | return -ENOMEM; | |
6408 | ||
6409 | state->acquire_ctx = ctx; | |
6410 | state->allow_modeset = true; | |
6411 | ||
6412 | for_each_crtc(dev, crtc) { | |
6413 | struct drm_crtc_state *crtc_state = | |
6414 | drm_atomic_get_crtc_state(state, crtc); | |
6b72d486 | 6415 | |
70e0bd74 ML |
6416 | ret = PTR_ERR_OR_ZERO(crtc_state); |
6417 | if (ret) | |
6418 | goto free; | |
6419 | ||
6420 | if (!crtc_state->active) | |
6421 | continue; | |
6422 | ||
6423 | crtc_state->active = false; | |
6424 | crtc_mask |= 1 << drm_crtc_index(crtc); | |
6425 | } | |
6426 | ||
6427 | if (crtc_mask) { | |
74c090b1 | 6428 | ret = drm_atomic_commit(state); |
70e0bd74 ML |
6429 | |
6430 | if (!ret) { | |
6431 | for_each_crtc(dev, crtc) | |
6432 | if (crtc_mask & (1 << drm_crtc_index(crtc))) | |
6433 | crtc->state->active = true; | |
6434 | ||
6435 | return ret; | |
6436 | } | |
6437 | } | |
6438 | ||
6439 | free: | |
6440 | if (ret) | |
6441 | DRM_ERROR("Suspending crtc's failed with %i\n", ret); | |
6442 | drm_atomic_state_free(state); | |
6443 | return ret; | |
ee7b9f93 JB |
6444 | } |
6445 | ||
ea5b213a | 6446 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 6447 | { |
4ef69c7a | 6448 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 6449 | |
ea5b213a CW |
6450 | drm_encoder_cleanup(encoder); |
6451 | kfree(intel_encoder); | |
7e7d76c3 JB |
6452 | } |
6453 | ||
0a91ca29 DV |
6454 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
6455 | * internal consistency). */ | |
b980514c | 6456 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 6457 | { |
35dd3c64 ML |
6458 | struct drm_crtc *crtc = connector->base.state->crtc; |
6459 | ||
6460 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
6461 | connector->base.base.id, | |
6462 | connector->base.name); | |
6463 | ||
0a91ca29 | 6464 | if (connector->get_hw_state(connector)) { |
e85376cb | 6465 | struct intel_encoder *encoder = connector->encoder; |
35dd3c64 | 6466 | struct drm_connector_state *conn_state = connector->base.state; |
0a91ca29 | 6467 | |
35dd3c64 ML |
6468 | I915_STATE_WARN(!crtc, |
6469 | "connector enabled without attached crtc\n"); | |
0a91ca29 | 6470 | |
35dd3c64 ML |
6471 | if (!crtc) |
6472 | return; | |
6473 | ||
6474 | I915_STATE_WARN(!crtc->state->active, | |
6475 | "connector is active, but attached crtc isn't\n"); | |
6476 | ||
e85376cb | 6477 | if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST) |
35dd3c64 ML |
6478 | return; |
6479 | ||
e85376cb | 6480 | I915_STATE_WARN(conn_state->best_encoder != &encoder->base, |
35dd3c64 ML |
6481 | "atomic encoder doesn't match attached encoder\n"); |
6482 | ||
e85376cb | 6483 | I915_STATE_WARN(conn_state->crtc != encoder->base.crtc, |
35dd3c64 ML |
6484 | "attached encoder crtc differs from connector crtc\n"); |
6485 | } else { | |
4d688a2a ML |
6486 | I915_STATE_WARN(crtc && crtc->state->active, |
6487 | "attached crtc is active, but connector isn't\n"); | |
35dd3c64 ML |
6488 | I915_STATE_WARN(!crtc && connector->base.state->best_encoder, |
6489 | "best encoder set without crtc!\n"); | |
0a91ca29 | 6490 | } |
79e53945 JB |
6491 | } |
6492 | ||
08d9bc92 ACO |
6493 | int intel_connector_init(struct intel_connector *connector) |
6494 | { | |
5350a031 | 6495 | drm_atomic_helper_connector_reset(&connector->base); |
08d9bc92 | 6496 | |
5350a031 | 6497 | if (!connector->base.state) |
08d9bc92 ACO |
6498 | return -ENOMEM; |
6499 | ||
08d9bc92 ACO |
6500 | return 0; |
6501 | } | |
6502 | ||
6503 | struct intel_connector *intel_connector_alloc(void) | |
6504 | { | |
6505 | struct intel_connector *connector; | |
6506 | ||
6507 | connector = kzalloc(sizeof *connector, GFP_KERNEL); | |
6508 | if (!connector) | |
6509 | return NULL; | |
6510 | ||
6511 | if (intel_connector_init(connector) < 0) { | |
6512 | kfree(connector); | |
6513 | return NULL; | |
6514 | } | |
6515 | ||
6516 | return connector; | |
6517 | } | |
6518 | ||
f0947c37 DV |
6519 | /* Simple connector->get_hw_state implementation for encoders that support only |
6520 | * one connector and no cloning and hence the encoder state determines the state | |
6521 | * of the connector. */ | |
6522 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 6523 | { |
24929352 | 6524 | enum pipe pipe = 0; |
f0947c37 | 6525 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 6526 | |
f0947c37 | 6527 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
6528 | } |
6529 | ||
6d293983 | 6530 | static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state) |
d272ddfa | 6531 | { |
6d293983 ACO |
6532 | if (crtc_state->base.enable && crtc_state->has_pch_encoder) |
6533 | return crtc_state->fdi_lanes; | |
d272ddfa VS |
6534 | |
6535 | return 0; | |
6536 | } | |
6537 | ||
6d293983 | 6538 | static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5cec258b | 6539 | struct intel_crtc_state *pipe_config) |
1857e1da | 6540 | { |
6d293983 ACO |
6541 | struct drm_atomic_state *state = pipe_config->base.state; |
6542 | struct intel_crtc *other_crtc; | |
6543 | struct intel_crtc_state *other_crtc_state; | |
6544 | ||
1857e1da DV |
6545 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", |
6546 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6547 | if (pipe_config->fdi_lanes > 4) { | |
6548 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
6549 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6550 | return -EINVAL; |
1857e1da DV |
6551 | } |
6552 | ||
bafb6553 | 6553 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
6554 | if (pipe_config->fdi_lanes > 2) { |
6555 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
6556 | pipe_config->fdi_lanes); | |
6d293983 | 6557 | return -EINVAL; |
1857e1da | 6558 | } else { |
6d293983 | 6559 | return 0; |
1857e1da DV |
6560 | } |
6561 | } | |
6562 | ||
6563 | if (INTEL_INFO(dev)->num_pipes == 2) | |
6d293983 | 6564 | return 0; |
1857e1da DV |
6565 | |
6566 | /* Ivybridge 3 pipe is really complicated */ | |
6567 | switch (pipe) { | |
6568 | case PIPE_A: | |
6d293983 | 6569 | return 0; |
1857e1da | 6570 | case PIPE_B: |
6d293983 ACO |
6571 | if (pipe_config->fdi_lanes <= 2) |
6572 | return 0; | |
6573 | ||
6574 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C)); | |
6575 | other_crtc_state = | |
6576 | intel_atomic_get_crtc_state(state, other_crtc); | |
6577 | if (IS_ERR(other_crtc_state)) | |
6578 | return PTR_ERR(other_crtc_state); | |
6579 | ||
6580 | if (pipe_required_fdi_lanes(other_crtc_state) > 0) { | |
1857e1da DV |
6581 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", |
6582 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6583 | return -EINVAL; |
1857e1da | 6584 | } |
6d293983 | 6585 | return 0; |
1857e1da | 6586 | case PIPE_C: |
251cc67c VS |
6587 | if (pipe_config->fdi_lanes > 2) { |
6588 | DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n", | |
6589 | pipe_name(pipe), pipe_config->fdi_lanes); | |
6d293983 | 6590 | return -EINVAL; |
251cc67c | 6591 | } |
6d293983 ACO |
6592 | |
6593 | other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B)); | |
6594 | other_crtc_state = | |
6595 | intel_atomic_get_crtc_state(state, other_crtc); | |
6596 | if (IS_ERR(other_crtc_state)) | |
6597 | return PTR_ERR(other_crtc_state); | |
6598 | ||
6599 | if (pipe_required_fdi_lanes(other_crtc_state) > 2) { | |
1857e1da | 6600 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); |
6d293983 | 6601 | return -EINVAL; |
1857e1da | 6602 | } |
6d293983 | 6603 | return 0; |
1857e1da DV |
6604 | default: |
6605 | BUG(); | |
6606 | } | |
6607 | } | |
6608 | ||
e29c22c0 DV |
6609 | #define RETRY 1 |
6610 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5cec258b | 6611 | struct intel_crtc_state *pipe_config) |
877d48d5 | 6612 | { |
1857e1da | 6613 | struct drm_device *dev = intel_crtc->base.dev; |
7c5f93b0 | 6614 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
6d293983 ACO |
6615 | int lane, link_bw, fdi_dotclock, ret; |
6616 | bool needs_recompute = false; | |
877d48d5 | 6617 | |
e29c22c0 | 6618 | retry: |
877d48d5 DV |
6619 | /* FDI is a binary signal running at ~2.7GHz, encoding |
6620 | * each output octet as 10 bits. The actual frequency | |
6621 | * is stored as a divider into a 100MHz clock, and the | |
6622 | * mode pixel clock is stored in units of 1KHz. | |
6623 | * Hence the bw of each lane in terms of the mode signal | |
6624 | * is: | |
6625 | */ | |
6626 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
6627 | ||
241bfc38 | 6628 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 6629 | |
2bd89a07 | 6630 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
6631 | pipe_config->pipe_bpp); |
6632 | ||
6633 | pipe_config->fdi_lanes = lane; | |
6634 | ||
2bd89a07 | 6635 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 6636 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 6637 | |
6d293983 ACO |
6638 | ret = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
6639 | intel_crtc->pipe, pipe_config); | |
6640 | if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) { | |
e29c22c0 DV |
6641 | pipe_config->pipe_bpp -= 2*3; |
6642 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
6643 | pipe_config->pipe_bpp); | |
6644 | needs_recompute = true; | |
6645 | pipe_config->bw_constrained = true; | |
6646 | ||
6647 | goto retry; | |
6648 | } | |
6649 | ||
6650 | if (needs_recompute) | |
6651 | return RETRY; | |
6652 | ||
6d293983 | 6653 | return ret; |
877d48d5 DV |
6654 | } |
6655 | ||
8cfb3407 VS |
6656 | static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv, |
6657 | struct intel_crtc_state *pipe_config) | |
6658 | { | |
6659 | if (pipe_config->pipe_bpp > 24) | |
6660 | return false; | |
6661 | ||
6662 | /* HSW can handle pixel rate up to cdclk? */ | |
6663 | if (IS_HASWELL(dev_priv->dev)) | |
6664 | return true; | |
6665 | ||
6666 | /* | |
b432e5cf VS |
6667 | * We compare against max which means we must take |
6668 | * the increased cdclk requirement into account when | |
6669 | * calculating the new cdclk. | |
6670 | * | |
6671 | * Should measure whether using a lower cdclk w/o IPS | |
8cfb3407 VS |
6672 | */ |
6673 | return ilk_pipe_pixel_rate(pipe_config) <= | |
6674 | dev_priv->max_cdclk_freq * 95 / 100; | |
6675 | } | |
6676 | ||
42db64ef | 6677 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5cec258b | 6678 | struct intel_crtc_state *pipe_config) |
42db64ef | 6679 | { |
8cfb3407 VS |
6680 | struct drm_device *dev = crtc->base.dev; |
6681 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6682 | ||
d330a953 | 6683 | pipe_config->ips_enabled = i915.enable_ips && |
8cfb3407 VS |
6684 | hsw_crtc_supports_ips(crtc) && |
6685 | pipe_config_supports_ips(dev_priv, pipe_config); | |
42db64ef PZ |
6686 | } |
6687 | ||
39acb4aa VS |
6688 | static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc) |
6689 | { | |
6690 | const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
6691 | ||
6692 | /* GDG double wide on either pipe, otherwise pipe A only */ | |
6693 | return INTEL_INFO(dev_priv)->gen < 4 && | |
6694 | (crtc->pipe == PIPE_A || IS_I915G(dev_priv)); | |
6695 | } | |
6696 | ||
a43f6e0f | 6697 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
5cec258b | 6698 | struct intel_crtc_state *pipe_config) |
79e53945 | 6699 | { |
a43f6e0f | 6700 | struct drm_device *dev = crtc->base.dev; |
8bd31e67 | 6701 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c5f93b0 | 6702 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
89749350 | 6703 | |
ad3a4479 | 6704 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 | 6705 | if (INTEL_INFO(dev)->gen < 4) { |
39acb4aa | 6706 | int clock_limit = dev_priv->max_cdclk_freq * 9 / 10; |
cf532bb2 VS |
6707 | |
6708 | /* | |
39acb4aa | 6709 | * Enable double wide mode when the dot clock |
cf532bb2 | 6710 | * is > 90% of the (display) core speed. |
cf532bb2 | 6711 | */ |
39acb4aa VS |
6712 | if (intel_crtc_supports_double_wide(crtc) && |
6713 | adjusted_mode->crtc_clock > clock_limit) { | |
ad3a4479 | 6714 | clock_limit *= 2; |
cf532bb2 | 6715 | pipe_config->double_wide = true; |
ad3a4479 VS |
6716 | } |
6717 | ||
39acb4aa VS |
6718 | if (adjusted_mode->crtc_clock > clock_limit) { |
6719 | DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n", | |
6720 | adjusted_mode->crtc_clock, clock_limit, | |
6721 | yesno(pipe_config->double_wide)); | |
e29c22c0 | 6722 | return -EINVAL; |
39acb4aa | 6723 | } |
2c07245f | 6724 | } |
89749350 | 6725 | |
1d1d0e27 VS |
6726 | /* |
6727 | * Pipe horizontal size must be even in: | |
6728 | * - DVO ganged mode | |
6729 | * - LVDS dual channel mode | |
6730 | * - Double wide pipe | |
6731 | */ | |
a93e255f | 6732 | if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) && |
1d1d0e27 VS |
6733 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) |
6734 | pipe_config->pipe_src_w &= ~1; | |
6735 | ||
8693a824 DL |
6736 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
6737 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
6738 | */ |
6739 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
aad941d5 | 6740 | adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay) |
e29c22c0 | 6741 | return -EINVAL; |
44f46b42 | 6742 | |
f5adf94e | 6743 | if (HAS_IPS(dev)) |
a43f6e0f DV |
6744 | hsw_compute_ips_config(crtc, pipe_config); |
6745 | ||
877d48d5 | 6746 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 6747 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 6748 | |
cf5a15be | 6749 | return 0; |
79e53945 JB |
6750 | } |
6751 | ||
1652d19e VS |
6752 | static int skylake_get_display_clock_speed(struct drm_device *dev) |
6753 | { | |
6754 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6755 | uint32_t lcpll1 = I915_READ(LCPLL1_CTL); | |
6756 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6757 | uint32_t linkrate; | |
6758 | ||
414355a7 | 6759 | if (!(lcpll1 & LCPLL_PLL_ENABLE)) |
1652d19e | 6760 | return 24000; /* 24MHz is the cd freq with NSSC ref */ |
1652d19e VS |
6761 | |
6762 | if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) | |
6763 | return 540000; | |
6764 | ||
6765 | linkrate = (I915_READ(DPLL_CTRL1) & | |
71cd8423 | 6766 | DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; |
1652d19e | 6767 | |
71cd8423 DL |
6768 | if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || |
6769 | linkrate == DPLL_CTRL1_LINK_RATE_1080) { | |
1652d19e VS |
6770 | /* vco 8640 */ |
6771 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6772 | case CDCLK_FREQ_450_432: | |
6773 | return 432000; | |
6774 | case CDCLK_FREQ_337_308: | |
6775 | return 308570; | |
6776 | case CDCLK_FREQ_675_617: | |
6777 | return 617140; | |
6778 | default: | |
6779 | WARN(1, "Unknown cd freq selection\n"); | |
6780 | } | |
6781 | } else { | |
6782 | /* vco 8100 */ | |
6783 | switch (cdctl & CDCLK_FREQ_SEL_MASK) { | |
6784 | case CDCLK_FREQ_450_432: | |
6785 | return 450000; | |
6786 | case CDCLK_FREQ_337_308: | |
6787 | return 337500; | |
6788 | case CDCLK_FREQ_675_617: | |
6789 | return 675000; | |
6790 | default: | |
6791 | WARN(1, "Unknown cd freq selection\n"); | |
6792 | } | |
6793 | } | |
6794 | ||
6795 | /* error case, do as if DPLL0 isn't enabled */ | |
6796 | return 24000; | |
6797 | } | |
6798 | ||
acd3f3d3 BP |
6799 | static int broxton_get_display_clock_speed(struct drm_device *dev) |
6800 | { | |
6801 | struct drm_i915_private *dev_priv = to_i915(dev); | |
6802 | uint32_t cdctl = I915_READ(CDCLK_CTL); | |
6803 | uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK; | |
6804 | uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE); | |
6805 | int cdclk; | |
6806 | ||
6807 | if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE)) | |
6808 | return 19200; | |
6809 | ||
6810 | cdclk = 19200 * pll_ratio / 2; | |
6811 | ||
6812 | switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) { | |
6813 | case BXT_CDCLK_CD2X_DIV_SEL_1: | |
6814 | return cdclk; /* 576MHz or 624MHz */ | |
6815 | case BXT_CDCLK_CD2X_DIV_SEL_1_5: | |
6816 | return cdclk * 2 / 3; /* 384MHz */ | |
6817 | case BXT_CDCLK_CD2X_DIV_SEL_2: | |
6818 | return cdclk / 2; /* 288MHz */ | |
6819 | case BXT_CDCLK_CD2X_DIV_SEL_4: | |
6820 | return cdclk / 4; /* 144MHz */ | |
6821 | } | |
6822 | ||
6823 | /* error case, do as if DE PLL isn't enabled */ | |
6824 | return 19200; | |
6825 | } | |
6826 | ||
1652d19e VS |
6827 | static int broadwell_get_display_clock_speed(struct drm_device *dev) |
6828 | { | |
6829 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6830 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6831 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6832 | ||
6833 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6834 | return 800000; | |
6835 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6836 | return 450000; | |
6837 | else if (freq == LCPLL_CLK_FREQ_450) | |
6838 | return 450000; | |
6839 | else if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
6840 | return 540000; | |
6841 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
6842 | return 337500; | |
6843 | else | |
6844 | return 675000; | |
6845 | } | |
6846 | ||
6847 | static int haswell_get_display_clock_speed(struct drm_device *dev) | |
6848 | { | |
6849 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6850 | uint32_t lcpll = I915_READ(LCPLL_CTL); | |
6851 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; | |
6852 | ||
6853 | if (lcpll & LCPLL_CD_SOURCE_FCLK) | |
6854 | return 800000; | |
6855 | else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) | |
6856 | return 450000; | |
6857 | else if (freq == LCPLL_CLK_FREQ_450) | |
6858 | return 450000; | |
6859 | else if (IS_HSW_ULT(dev)) | |
6860 | return 337500; | |
6861 | else | |
6862 | return 540000; | |
79e53945 JB |
6863 | } |
6864 | ||
25eb05fc JB |
6865 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
6866 | { | |
bfa7df01 VS |
6867 | return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk", |
6868 | CCK_DISPLAY_CLOCK_CONTROL); | |
25eb05fc JB |
6869 | } |
6870 | ||
b37a6434 VS |
6871 | static int ilk_get_display_clock_speed(struct drm_device *dev) |
6872 | { | |
6873 | return 450000; | |
6874 | } | |
6875 | ||
e70236a8 JB |
6876 | static int i945_get_display_clock_speed(struct drm_device *dev) |
6877 | { | |
6878 | return 400000; | |
6879 | } | |
79e53945 | 6880 | |
e70236a8 | 6881 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 6882 | { |
e907f170 | 6883 | return 333333; |
e70236a8 | 6884 | } |
79e53945 | 6885 | |
e70236a8 JB |
6886 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
6887 | { | |
6888 | return 200000; | |
6889 | } | |
79e53945 | 6890 | |
257a7ffc DV |
6891 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
6892 | { | |
6893 | u16 gcfgc = 0; | |
6894 | ||
6895 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
6896 | ||
6897 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6898 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
e907f170 | 6899 | return 266667; |
257a7ffc | 6900 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: |
e907f170 | 6901 | return 333333; |
257a7ffc | 6902 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: |
e907f170 | 6903 | return 444444; |
257a7ffc DV |
6904 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: |
6905 | return 200000; | |
6906 | default: | |
6907 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
6908 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
e907f170 | 6909 | return 133333; |
257a7ffc | 6910 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: |
e907f170 | 6911 | return 166667; |
257a7ffc DV |
6912 | } |
6913 | } | |
6914 | ||
e70236a8 JB |
6915 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
6916 | { | |
6917 | u16 gcfgc = 0; | |
79e53945 | 6918 | |
e70236a8 JB |
6919 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
6920 | ||
6921 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
e907f170 | 6922 | return 133333; |
e70236a8 JB |
6923 | else { |
6924 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
6925 | case GC_DISPLAY_CLOCK_333_MHZ: | |
e907f170 | 6926 | return 333333; |
e70236a8 JB |
6927 | default: |
6928 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
6929 | return 190000; | |
79e53945 | 6930 | } |
e70236a8 JB |
6931 | } |
6932 | } | |
6933 | ||
6934 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
6935 | { | |
e907f170 | 6936 | return 266667; |
e70236a8 JB |
6937 | } |
6938 | ||
1b1d2716 | 6939 | static int i85x_get_display_clock_speed(struct drm_device *dev) |
e70236a8 JB |
6940 | { |
6941 | u16 hpllcc = 0; | |
1b1d2716 | 6942 | |
65cd2b3f VS |
6943 | /* |
6944 | * 852GM/852GMV only supports 133 MHz and the HPLLCC | |
6945 | * encoding is different :( | |
6946 | * FIXME is this the right way to detect 852GM/852GMV? | |
6947 | */ | |
6948 | if (dev->pdev->revision == 0x1) | |
6949 | return 133333; | |
6950 | ||
1b1d2716 VS |
6951 | pci_bus_read_config_word(dev->pdev->bus, |
6952 | PCI_DEVFN(0, 3), HPLLCC, &hpllcc); | |
6953 | ||
e70236a8 JB |
6954 | /* Assume that the hardware is in the high speed state. This |
6955 | * should be the default. | |
6956 | */ | |
6957 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
6958 | case GC_CLOCK_133_200: | |
1b1d2716 | 6959 | case GC_CLOCK_133_200_2: |
e70236a8 JB |
6960 | case GC_CLOCK_100_200: |
6961 | return 200000; | |
6962 | case GC_CLOCK_166_250: | |
6963 | return 250000; | |
6964 | case GC_CLOCK_100_133: | |
e907f170 | 6965 | return 133333; |
1b1d2716 VS |
6966 | case GC_CLOCK_133_266: |
6967 | case GC_CLOCK_133_266_2: | |
6968 | case GC_CLOCK_166_266: | |
6969 | return 266667; | |
e70236a8 | 6970 | } |
79e53945 | 6971 | |
e70236a8 JB |
6972 | /* Shouldn't happen */ |
6973 | return 0; | |
6974 | } | |
79e53945 | 6975 | |
e70236a8 JB |
6976 | static int i830_get_display_clock_speed(struct drm_device *dev) |
6977 | { | |
e907f170 | 6978 | return 133333; |
79e53945 JB |
6979 | } |
6980 | ||
34edce2f VS |
6981 | static unsigned int intel_hpll_vco(struct drm_device *dev) |
6982 | { | |
6983 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6984 | static const unsigned int blb_vco[8] = { | |
6985 | [0] = 3200000, | |
6986 | [1] = 4000000, | |
6987 | [2] = 5333333, | |
6988 | [3] = 4800000, | |
6989 | [4] = 6400000, | |
6990 | }; | |
6991 | static const unsigned int pnv_vco[8] = { | |
6992 | [0] = 3200000, | |
6993 | [1] = 4000000, | |
6994 | [2] = 5333333, | |
6995 | [3] = 4800000, | |
6996 | [4] = 2666667, | |
6997 | }; | |
6998 | static const unsigned int cl_vco[8] = { | |
6999 | [0] = 3200000, | |
7000 | [1] = 4000000, | |
7001 | [2] = 5333333, | |
7002 | [3] = 6400000, | |
7003 | [4] = 3333333, | |
7004 | [5] = 3566667, | |
7005 | [6] = 4266667, | |
7006 | }; | |
7007 | static const unsigned int elk_vco[8] = { | |
7008 | [0] = 3200000, | |
7009 | [1] = 4000000, | |
7010 | [2] = 5333333, | |
7011 | [3] = 4800000, | |
7012 | }; | |
7013 | static const unsigned int ctg_vco[8] = { | |
7014 | [0] = 3200000, | |
7015 | [1] = 4000000, | |
7016 | [2] = 5333333, | |
7017 | [3] = 6400000, | |
7018 | [4] = 2666667, | |
7019 | [5] = 4266667, | |
7020 | }; | |
7021 | const unsigned int *vco_table; | |
7022 | unsigned int vco; | |
7023 | uint8_t tmp = 0; | |
7024 | ||
7025 | /* FIXME other chipsets? */ | |
7026 | if (IS_GM45(dev)) | |
7027 | vco_table = ctg_vco; | |
7028 | else if (IS_G4X(dev)) | |
7029 | vco_table = elk_vco; | |
7030 | else if (IS_CRESTLINE(dev)) | |
7031 | vco_table = cl_vco; | |
7032 | else if (IS_PINEVIEW(dev)) | |
7033 | vco_table = pnv_vco; | |
7034 | else if (IS_G33(dev)) | |
7035 | vco_table = blb_vco; | |
7036 | else | |
7037 | return 0; | |
7038 | ||
7039 | tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO); | |
7040 | ||
7041 | vco = vco_table[tmp & 0x7]; | |
7042 | if (vco == 0) | |
7043 | DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp); | |
7044 | else | |
7045 | DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco); | |
7046 | ||
7047 | return vco; | |
7048 | } | |
7049 | ||
7050 | static int gm45_get_display_clock_speed(struct drm_device *dev) | |
7051 | { | |
7052 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7053 | uint16_t tmp = 0; | |
7054 | ||
7055 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7056 | ||
7057 | cdclk_sel = (tmp >> 12) & 0x1; | |
7058 | ||
7059 | switch (vco) { | |
7060 | case 2666667: | |
7061 | case 4000000: | |
7062 | case 5333333: | |
7063 | return cdclk_sel ? 333333 : 222222; | |
7064 | case 3200000: | |
7065 | return cdclk_sel ? 320000 : 228571; | |
7066 | default: | |
7067 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp); | |
7068 | return 222222; | |
7069 | } | |
7070 | } | |
7071 | ||
7072 | static int i965gm_get_display_clock_speed(struct drm_device *dev) | |
7073 | { | |
7074 | static const uint8_t div_3200[] = { 16, 10, 8 }; | |
7075 | static const uint8_t div_4000[] = { 20, 12, 10 }; | |
7076 | static const uint8_t div_5333[] = { 24, 16, 14 }; | |
7077 | const uint8_t *div_table; | |
7078 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7079 | uint16_t tmp = 0; | |
7080 | ||
7081 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7082 | ||
7083 | cdclk_sel = ((tmp >> 8) & 0x1f) - 1; | |
7084 | ||
7085 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7086 | goto fail; | |
7087 | ||
7088 | switch (vco) { | |
7089 | case 3200000: | |
7090 | div_table = div_3200; | |
7091 | break; | |
7092 | case 4000000: | |
7093 | div_table = div_4000; | |
7094 | break; | |
7095 | case 5333333: | |
7096 | div_table = div_5333; | |
7097 | break; | |
7098 | default: | |
7099 | goto fail; | |
7100 | } | |
7101 | ||
7102 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7103 | ||
caf4e252 | 7104 | fail: |
34edce2f VS |
7105 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp); |
7106 | return 200000; | |
7107 | } | |
7108 | ||
7109 | static int g33_get_display_clock_speed(struct drm_device *dev) | |
7110 | { | |
7111 | static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 }; | |
7112 | static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 }; | |
7113 | static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 }; | |
7114 | static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 }; | |
7115 | const uint8_t *div_table; | |
7116 | unsigned int cdclk_sel, vco = intel_hpll_vco(dev); | |
7117 | uint16_t tmp = 0; | |
7118 | ||
7119 | pci_read_config_word(dev->pdev, GCFGC, &tmp); | |
7120 | ||
7121 | cdclk_sel = (tmp >> 4) & 0x7; | |
7122 | ||
7123 | if (cdclk_sel >= ARRAY_SIZE(div_3200)) | |
7124 | goto fail; | |
7125 | ||
7126 | switch (vco) { | |
7127 | case 3200000: | |
7128 | div_table = div_3200; | |
7129 | break; | |
7130 | case 4000000: | |
7131 | div_table = div_4000; | |
7132 | break; | |
7133 | case 4800000: | |
7134 | div_table = div_4800; | |
7135 | break; | |
7136 | case 5333333: | |
7137 | div_table = div_5333; | |
7138 | break; | |
7139 | default: | |
7140 | goto fail; | |
7141 | } | |
7142 | ||
7143 | return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]); | |
7144 | ||
caf4e252 | 7145 | fail: |
34edce2f VS |
7146 | DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp); |
7147 | return 190476; | |
7148 | } | |
7149 | ||
2c07245f | 7150 | static void |
a65851af | 7151 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 7152 | { |
a65851af VS |
7153 | while (*num > DATA_LINK_M_N_MASK || |
7154 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
7155 | *num >>= 1; |
7156 | *den >>= 1; | |
7157 | } | |
7158 | } | |
7159 | ||
a65851af VS |
7160 | static void compute_m_n(unsigned int m, unsigned int n, |
7161 | uint32_t *ret_m, uint32_t *ret_n) | |
7162 | { | |
7163 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
7164 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
7165 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
7166 | } | |
7167 | ||
e69d0bc1 DV |
7168 | void |
7169 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
7170 | int pixel_clock, int link_clock, | |
7171 | struct intel_link_m_n *m_n) | |
2c07245f | 7172 | { |
e69d0bc1 | 7173 | m_n->tu = 64; |
a65851af VS |
7174 | |
7175 | compute_m_n(bits_per_pixel * pixel_clock, | |
7176 | link_clock * nlanes * 8, | |
7177 | &m_n->gmch_m, &m_n->gmch_n); | |
7178 | ||
7179 | compute_m_n(pixel_clock, link_clock, | |
7180 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
7181 | } |
7182 | ||
a7615030 CW |
7183 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
7184 | { | |
d330a953 JN |
7185 | if (i915.panel_use_ssc >= 0) |
7186 | return i915.panel_use_ssc != 0; | |
41aa3448 | 7187 | return dev_priv->vbt.lvds_use_ssc |
435793df | 7188 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
7189 | } |
7190 | ||
a93e255f ACO |
7191 | static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state, |
7192 | int num_connectors) | |
c65d77d8 | 7193 | { |
a93e255f | 7194 | struct drm_device *dev = crtc_state->base.crtc->dev; |
c65d77d8 JB |
7195 | struct drm_i915_private *dev_priv = dev->dev_private; |
7196 | int refclk; | |
7197 | ||
a93e255f ACO |
7198 | WARN_ON(!crtc_state->base.state); |
7199 | ||
666a4537 | 7200 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) { |
9a0ea498 | 7201 | refclk = 100000; |
a93e255f | 7202 | } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 7203 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
7204 | refclk = dev_priv->vbt.lvds_ssc_freq; |
7205 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
7206 | } else if (!IS_GEN2(dev)) { |
7207 | refclk = 96000; | |
7208 | } else { | |
7209 | refclk = 48000; | |
7210 | } | |
7211 | ||
7212 | return refclk; | |
7213 | } | |
7214 | ||
7429e9d4 | 7215 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 7216 | { |
7df00d7a | 7217 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 7218 | } |
f47709a9 | 7219 | |
7429e9d4 DV |
7220 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
7221 | { | |
7222 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
7223 | } |
7224 | ||
f47709a9 | 7225 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
190f68c5 | 7226 | struct intel_crtc_state *crtc_state, |
a7516a05 JB |
7227 | intel_clock_t *reduced_clock) |
7228 | { | |
f47709a9 | 7229 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
7230 | u32 fp, fp2 = 0; |
7231 | ||
7232 | if (IS_PINEVIEW(dev)) { | |
190f68c5 | 7233 | fp = pnv_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7234 | if (reduced_clock) |
7429e9d4 | 7235 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 7236 | } else { |
190f68c5 | 7237 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); |
a7516a05 | 7238 | if (reduced_clock) |
7429e9d4 | 7239 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
7240 | } |
7241 | ||
190f68c5 | 7242 | crtc_state->dpll_hw_state.fp0 = fp; |
a7516a05 | 7243 | |
f47709a9 | 7244 | crtc->lowfreq_avail = false; |
a93e255f | 7245 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
ab585dea | 7246 | reduced_clock) { |
190f68c5 | 7247 | crtc_state->dpll_hw_state.fp1 = fp2; |
f47709a9 | 7248 | crtc->lowfreq_avail = true; |
a7516a05 | 7249 | } else { |
190f68c5 | 7250 | crtc_state->dpll_hw_state.fp1 = fp; |
a7516a05 JB |
7251 | } |
7252 | } | |
7253 | ||
5e69f97f CML |
7254 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
7255 | pipe) | |
89b667f8 JB |
7256 | { |
7257 | u32 reg_val; | |
7258 | ||
7259 | /* | |
7260 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
7261 | * and set it to a reasonable value instead. | |
7262 | */ | |
ab3c759a | 7263 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
7264 | reg_val &= 0xffffff00; |
7265 | reg_val |= 0x00000030; | |
ab3c759a | 7266 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7267 | |
ab3c759a | 7268 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7269 | reg_val &= 0x8cffffff; |
7270 | reg_val = 0x8c000000; | |
ab3c759a | 7271 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 7272 | |
ab3c759a | 7273 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 7274 | reg_val &= 0xffffff00; |
ab3c759a | 7275 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 7276 | |
ab3c759a | 7277 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
7278 | reg_val &= 0x00ffffff; |
7279 | reg_val |= 0xb0000000; | |
ab3c759a | 7280 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
7281 | } |
7282 | ||
b551842d DV |
7283 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
7284 | struct intel_link_m_n *m_n) | |
7285 | { | |
7286 | struct drm_device *dev = crtc->base.dev; | |
7287 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7288 | int pipe = crtc->pipe; | |
7289 | ||
e3b95f1e DV |
7290 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7291 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
7292 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
7293 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
7294 | } |
7295 | ||
7296 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
7297 | struct intel_link_m_n *m_n, |
7298 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
7299 | { |
7300 | struct drm_device *dev = crtc->base.dev; | |
7301 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7302 | int pipe = crtc->pipe; | |
6e3c9717 | 7303 | enum transcoder transcoder = crtc->config->cpu_transcoder; |
b551842d DV |
7304 | |
7305 | if (INTEL_INFO(dev)->gen >= 5) { | |
7306 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
7307 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
7308 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
7309 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
7310 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
7311 | * for gen < 8) and if DRRS is supported (to make sure the | |
7312 | * registers are not unnecessarily accessed). | |
7313 | */ | |
44395bfe | 7314 | if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) && |
6e3c9717 | 7315 | crtc->config->has_drrs) { |
f769cd24 VK |
7316 | I915_WRITE(PIPE_DATA_M2(transcoder), |
7317 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
7318 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
7319 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
7320 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
7321 | } | |
b551842d | 7322 | } else { |
e3b95f1e DV |
7323 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
7324 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
7325 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
7326 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
7327 | } |
7328 | } | |
7329 | ||
fe3cd48d | 7330 | void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n) |
03afc4a2 | 7331 | { |
fe3cd48d R |
7332 | struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL; |
7333 | ||
7334 | if (m_n == M1_N1) { | |
7335 | dp_m_n = &crtc->config->dp_m_n; | |
7336 | dp_m2_n2 = &crtc->config->dp_m2_n2; | |
7337 | } else if (m_n == M2_N2) { | |
7338 | ||
7339 | /* | |
7340 | * M2_N2 registers are not supported. Hence m2_n2 divider value | |
7341 | * needs to be programmed into M1_N1. | |
7342 | */ | |
7343 | dp_m_n = &crtc->config->dp_m2_n2; | |
7344 | } else { | |
7345 | DRM_ERROR("Unsupported divider value\n"); | |
7346 | return; | |
7347 | } | |
7348 | ||
6e3c9717 ACO |
7349 | if (crtc->config->has_pch_encoder) |
7350 | intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n); | |
03afc4a2 | 7351 | else |
fe3cd48d | 7352 | intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2); |
03afc4a2 DV |
7353 | } |
7354 | ||
251ac862 DV |
7355 | static void vlv_compute_dpll(struct intel_crtc *crtc, |
7356 | struct intel_crtc_state *pipe_config) | |
bdd4b6a6 DV |
7357 | { |
7358 | u32 dpll, dpll_md; | |
7359 | ||
7360 | /* | |
7361 | * Enable DPIO clock input. We should never disable the reference | |
7362 | * clock for pipe B, since VGA hotplug / manual detection depends | |
7363 | * on it. | |
7364 | */ | |
60bfe44f VS |
7365 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV | |
7366 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV; | |
bdd4b6a6 DV |
7367 | /* We should never disable this, set it here for state tracking */ |
7368 | if (crtc->pipe == PIPE_B) | |
7369 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
7370 | dpll |= DPLL_VCO_ENABLE; | |
d288f65f | 7371 | pipe_config->dpll_hw_state.dpll = dpll; |
bdd4b6a6 | 7372 | |
d288f65f | 7373 | dpll_md = (pipe_config->pixel_multiplier - 1) |
bdd4b6a6 | 7374 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
d288f65f | 7375 | pipe_config->dpll_hw_state.dpll_md = dpll_md; |
bdd4b6a6 DV |
7376 | } |
7377 | ||
d288f65f | 7378 | static void vlv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7379 | const struct intel_crtc_state *pipe_config) |
a0c4da24 | 7380 | { |
f47709a9 | 7381 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 7382 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 7383 | int pipe = crtc->pipe; |
bdd4b6a6 | 7384 | u32 mdiv; |
a0c4da24 | 7385 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 7386 | u32 coreclk, reg_val; |
a0c4da24 | 7387 | |
a580516d | 7388 | mutex_lock(&dev_priv->sb_lock); |
09153000 | 7389 | |
d288f65f VS |
7390 | bestn = pipe_config->dpll.n; |
7391 | bestm1 = pipe_config->dpll.m1; | |
7392 | bestm2 = pipe_config->dpll.m2; | |
7393 | bestp1 = pipe_config->dpll.p1; | |
7394 | bestp2 = pipe_config->dpll.p2; | |
a0c4da24 | 7395 | |
89b667f8 JB |
7396 | /* See eDP HDMI DPIO driver vbios notes doc */ |
7397 | ||
7398 | /* PLL B needs special handling */ | |
bdd4b6a6 | 7399 | if (pipe == PIPE_B) |
5e69f97f | 7400 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
7401 | |
7402 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 7403 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
7404 | |
7405 | /* Disable target IRef on PLL */ | |
ab3c759a | 7406 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 7407 | reg_val &= 0x00ffffff; |
ab3c759a | 7408 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
7409 | |
7410 | /* Disable fast lock */ | |
ab3c759a | 7411 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
7412 | |
7413 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
7414 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
7415 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
7416 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 7417 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
7418 | |
7419 | /* | |
7420 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
7421 | * but we don't support that). | |
7422 | * Note: don't use the DAC post divider as it seems unstable. | |
7423 | */ | |
7424 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 7425 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7426 | |
a0c4da24 | 7427 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 7428 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 7429 | |
89b667f8 | 7430 | /* Set HBR and RBR LPF coefficients */ |
d288f65f | 7431 | if (pipe_config->port_clock == 162000 || |
409ee761 ACO |
7432 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) || |
7433 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) | |
ab3c759a | 7434 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 7435 | 0x009f0003); |
89b667f8 | 7436 | else |
ab3c759a | 7437 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
7438 | 0x00d0000f); |
7439 | ||
681a8504 | 7440 | if (pipe_config->has_dp_encoder) { |
89b667f8 | 7441 | /* Use SSC source */ |
bdd4b6a6 | 7442 | if (pipe == PIPE_A) |
ab3c759a | 7443 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7444 | 0x0df40000); |
7445 | else | |
ab3c759a | 7446 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7447 | 0x0df70000); |
7448 | } else { /* HDMI or VGA */ | |
7449 | /* Use bend source */ | |
bdd4b6a6 | 7450 | if (pipe == PIPE_A) |
ab3c759a | 7451 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7452 | 0x0df70000); |
7453 | else | |
ab3c759a | 7454 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
7455 | 0x0df40000); |
7456 | } | |
a0c4da24 | 7457 | |
ab3c759a | 7458 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 | 7459 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
409ee761 ACO |
7460 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
7461 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) | |
89b667f8 | 7462 | coreclk |= 0x01000000; |
ab3c759a | 7463 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 7464 | |
ab3c759a | 7465 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
a580516d | 7466 | mutex_unlock(&dev_priv->sb_lock); |
a0c4da24 JB |
7467 | } |
7468 | ||
251ac862 DV |
7469 | static void chv_compute_dpll(struct intel_crtc *crtc, |
7470 | struct intel_crtc_state *pipe_config) | |
1ae0d137 | 7471 | { |
60bfe44f VS |
7472 | pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | |
7473 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | | |
1ae0d137 VS |
7474 | DPLL_VCO_ENABLE; |
7475 | if (crtc->pipe != PIPE_A) | |
d288f65f | 7476 | pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; |
1ae0d137 | 7477 | |
d288f65f VS |
7478 | pipe_config->dpll_hw_state.dpll_md = |
7479 | (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
1ae0d137 VS |
7480 | } |
7481 | ||
d288f65f | 7482 | static void chv_prepare_pll(struct intel_crtc *crtc, |
5cec258b | 7483 | const struct intel_crtc_state *pipe_config) |
9d556c99 CML |
7484 | { |
7485 | struct drm_device *dev = crtc->base.dev; | |
7486 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7487 | int pipe = crtc->pipe; | |
f0f59a00 | 7488 | i915_reg_t dpll_reg = DPLL(crtc->pipe); |
9d556c99 | 7489 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
9cbe40c1 | 7490 | u32 loopfilter, tribuf_calcntr; |
9d556c99 | 7491 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
a945ce7e | 7492 | u32 dpio_val; |
9cbe40c1 | 7493 | int vco; |
9d556c99 | 7494 | |
d288f65f VS |
7495 | bestn = pipe_config->dpll.n; |
7496 | bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; | |
7497 | bestm1 = pipe_config->dpll.m1; | |
7498 | bestm2 = pipe_config->dpll.m2 >> 22; | |
7499 | bestp1 = pipe_config->dpll.p1; | |
7500 | bestp2 = pipe_config->dpll.p2; | |
9cbe40c1 | 7501 | vco = pipe_config->dpll.vco; |
a945ce7e | 7502 | dpio_val = 0; |
9cbe40c1 | 7503 | loopfilter = 0; |
9d556c99 CML |
7504 | |
7505 | /* | |
7506 | * Enable Refclk and SSC | |
7507 | */ | |
a11b0703 | 7508 | I915_WRITE(dpll_reg, |
d288f65f | 7509 | pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); |
a11b0703 | 7510 | |
a580516d | 7511 | mutex_lock(&dev_priv->sb_lock); |
9d556c99 | 7512 | |
9d556c99 CML |
7513 | /* p1 and p2 divider */ |
7514 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
7515 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
7516 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
7517 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
7518 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
7519 | ||
7520 | /* Feedback post-divider - m2 */ | |
7521 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
7522 | ||
7523 | /* Feedback refclk divider - n and m1 */ | |
7524 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
7525 | DPIO_CHV_M1_DIV_BY_2 | | |
7526 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
7527 | ||
7528 | /* M2 fraction division */ | |
25a25dfc | 7529 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); |
9d556c99 CML |
7530 | |
7531 | /* M2 fraction division enable */ | |
a945ce7e VP |
7532 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
7533 | dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); | |
7534 | dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); | |
7535 | if (bestm2_frac) | |
7536 | dpio_val |= DPIO_CHV_FRAC_DIV_EN; | |
7537 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); | |
9d556c99 | 7538 | |
de3a0fde VP |
7539 | /* Program digital lock detect threshold */ |
7540 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); | |
7541 | dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | | |
7542 | DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); | |
7543 | dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); | |
7544 | if (!bestm2_frac) | |
7545 | dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; | |
7546 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); | |
7547 | ||
9d556c99 | 7548 | /* Loop filter */ |
9cbe40c1 VP |
7549 | if (vco == 5400000) { |
7550 | loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7551 | loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); | |
7552 | loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7553 | tribuf_calcntr = 0x9; | |
7554 | } else if (vco <= 6200000) { | |
7555 | loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7556 | loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); | |
7557 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7558 | tribuf_calcntr = 0x9; | |
7559 | } else if (vco <= 6480000) { | |
7560 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7561 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7562 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7563 | tribuf_calcntr = 0x8; | |
7564 | } else { | |
7565 | /* Not supported. Apply the same limits as in the max case */ | |
7566 | loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); | |
7567 | loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); | |
7568 | loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); | |
7569 | tribuf_calcntr = 0; | |
7570 | } | |
9d556c99 CML |
7571 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); |
7572 | ||
968040b2 | 7573 | dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); |
9cbe40c1 VP |
7574 | dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; |
7575 | dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); | |
7576 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); | |
7577 | ||
9d556c99 CML |
7578 | /* AFC Recal */ |
7579 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
7580 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
7581 | DPIO_AFC_RECAL); | |
7582 | ||
a580516d | 7583 | mutex_unlock(&dev_priv->sb_lock); |
9d556c99 CML |
7584 | } |
7585 | ||
d288f65f VS |
7586 | /** |
7587 | * vlv_force_pll_on - forcibly enable just the PLL | |
7588 | * @dev_priv: i915 private structure | |
7589 | * @pipe: pipe PLL to enable | |
7590 | * @dpll: PLL configuration | |
7591 | * | |
7592 | * Enable the PLL for @pipe using the supplied @dpll config. To be used | |
7593 | * in cases where we need the PLL enabled even when @pipe is not going to | |
7594 | * be enabled. | |
7595 | */ | |
3f36b937 TU |
7596 | int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, |
7597 | const struct dpll *dpll) | |
d288f65f VS |
7598 | { |
7599 | struct intel_crtc *crtc = | |
7600 | to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe)); | |
3f36b937 TU |
7601 | struct intel_crtc_state *pipe_config; |
7602 | ||
7603 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); | |
7604 | if (!pipe_config) | |
7605 | return -ENOMEM; | |
7606 | ||
7607 | pipe_config->base.crtc = &crtc->base; | |
7608 | pipe_config->pixel_multiplier = 1; | |
7609 | pipe_config->dpll = *dpll; | |
d288f65f VS |
7610 | |
7611 | if (IS_CHERRYVIEW(dev)) { | |
3f36b937 TU |
7612 | chv_compute_dpll(crtc, pipe_config); |
7613 | chv_prepare_pll(crtc, pipe_config); | |
7614 | chv_enable_pll(crtc, pipe_config); | |
d288f65f | 7615 | } else { |
3f36b937 TU |
7616 | vlv_compute_dpll(crtc, pipe_config); |
7617 | vlv_prepare_pll(crtc, pipe_config); | |
7618 | vlv_enable_pll(crtc, pipe_config); | |
d288f65f | 7619 | } |
3f36b937 TU |
7620 | |
7621 | kfree(pipe_config); | |
7622 | ||
7623 | return 0; | |
d288f65f VS |
7624 | } |
7625 | ||
7626 | /** | |
7627 | * vlv_force_pll_off - forcibly disable just the PLL | |
7628 | * @dev_priv: i915 private structure | |
7629 | * @pipe: pipe PLL to disable | |
7630 | * | |
7631 | * Disable the PLL for @pipe. To be used in cases where we need | |
7632 | * the PLL enabled even when @pipe is not going to be enabled. | |
7633 | */ | |
7634 | void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe) | |
7635 | { | |
7636 | if (IS_CHERRYVIEW(dev)) | |
7637 | chv_disable_pll(to_i915(dev), pipe); | |
7638 | else | |
7639 | vlv_disable_pll(to_i915(dev), pipe); | |
7640 | } | |
7641 | ||
251ac862 DV |
7642 | static void i9xx_compute_dpll(struct intel_crtc *crtc, |
7643 | struct intel_crtc_state *crtc_state, | |
7644 | intel_clock_t *reduced_clock, | |
7645 | int num_connectors) | |
eb1cbe48 | 7646 | { |
f47709a9 | 7647 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7648 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
7649 | u32 dpll; |
7650 | bool is_sdvo; | |
190f68c5 | 7651 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7652 | |
190f68c5 | 7653 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7654 | |
a93e255f ACO |
7655 | is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) || |
7656 | intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
7657 | |
7658 | dpll = DPLL_VGA_MODE_DIS; | |
7659 | ||
a93e255f | 7660 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
7661 | dpll |= DPLLB_MODE_LVDS; |
7662 | else | |
7663 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 7664 | |
ef1b460d | 7665 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
190f68c5 | 7666 | dpll |= (crtc_state->pixel_multiplier - 1) |
198a037f | 7667 | << SDVO_MULTIPLIER_SHIFT_HIRES; |
eb1cbe48 | 7668 | } |
198a037f DV |
7669 | |
7670 | if (is_sdvo) | |
4a33e48d | 7671 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 7672 | |
190f68c5 | 7673 | if (crtc_state->has_dp_encoder) |
4a33e48d | 7674 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
7675 | |
7676 | /* compute bitmask from p1 value */ | |
7677 | if (IS_PINEVIEW(dev)) | |
7678 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
7679 | else { | |
7680 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7681 | if (IS_G4X(dev) && reduced_clock) | |
7682 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
7683 | } | |
7684 | switch (clock->p2) { | |
7685 | case 5: | |
7686 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7687 | break; | |
7688 | case 7: | |
7689 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7690 | break; | |
7691 | case 10: | |
7692 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7693 | break; | |
7694 | case 14: | |
7695 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7696 | break; | |
7697 | } | |
7698 | if (INTEL_INFO(dev)->gen >= 4) | |
7699 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
7700 | ||
190f68c5 | 7701 | if (crtc_state->sdvo_tv_clock) |
eb1cbe48 | 7702 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
a93e255f | 7703 | else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7704 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7705 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7706 | else | |
7707 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7708 | ||
7709 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7710 | crtc_state->dpll_hw_state.dpll = dpll; |
8bcc2795 | 7711 | |
eb1cbe48 | 7712 | if (INTEL_INFO(dev)->gen >= 4) { |
190f68c5 | 7713 | u32 dpll_md = (crtc_state->pixel_multiplier - 1) |
ef1b460d | 7714 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; |
190f68c5 | 7715 | crtc_state->dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
7716 | } |
7717 | } | |
7718 | ||
251ac862 DV |
7719 | static void i8xx_compute_dpll(struct intel_crtc *crtc, |
7720 | struct intel_crtc_state *crtc_state, | |
7721 | intel_clock_t *reduced_clock, | |
7722 | int num_connectors) | |
eb1cbe48 | 7723 | { |
f47709a9 | 7724 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 7725 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 7726 | u32 dpll; |
190f68c5 | 7727 | struct dpll *clock = &crtc_state->dpll; |
eb1cbe48 | 7728 | |
190f68c5 | 7729 | i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); |
2a8f64ca | 7730 | |
eb1cbe48 DV |
7731 | dpll = DPLL_VGA_MODE_DIS; |
7732 | ||
a93e255f | 7733 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
7734 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
7735 | } else { | |
7736 | if (clock->p1 == 2) | |
7737 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
7738 | else | |
7739 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
7740 | if (clock->p2 == 4) | |
7741 | dpll |= PLL_P2_DIVIDE_BY_4; | |
7742 | } | |
7743 | ||
a93e255f | 7744 | if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
7745 | dpll |= DPLL_DVO_2X_MODE; |
7746 | ||
a93e255f | 7747 | if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
7748 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
7749 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
7750 | else | |
7751 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7752 | ||
7753 | dpll |= DPLL_VCO_ENABLE; | |
190f68c5 | 7754 | crtc_state->dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
7755 | } |
7756 | ||
8a654f3b | 7757 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
7758 | { |
7759 | struct drm_device *dev = intel_crtc->base.dev; | |
7760 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7761 | enum pipe pipe = intel_crtc->pipe; | |
6e3c9717 | 7762 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
7c5f93b0 | 7763 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
1caea6e9 VS |
7764 | uint32_t crtc_vtotal, crtc_vblank_end; |
7765 | int vsyncshift = 0; | |
4d8a62ea DV |
7766 | |
7767 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
7768 | * the hw state checker will get angry at the mismatch. */ | |
7769 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
7770 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 7771 | |
609aeaca | 7772 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 7773 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
7774 | crtc_vtotal -= 1; |
7775 | crtc_vblank_end -= 1; | |
609aeaca | 7776 | |
409ee761 | 7777 | if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
609aeaca VS |
7778 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; |
7779 | else | |
7780 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
7781 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
7782 | if (vsyncshift < 0) |
7783 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
7784 | } |
7785 | ||
7786 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 7787 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 7788 | |
fe2b8f9d | 7789 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
7790 | (adjusted_mode->crtc_hdisplay - 1) | |
7791 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 7792 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
7793 | (adjusted_mode->crtc_hblank_start - 1) | |
7794 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 7795 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
7796 | (adjusted_mode->crtc_hsync_start - 1) | |
7797 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
7798 | ||
fe2b8f9d | 7799 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 7800 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 7801 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 7802 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 7803 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 7804 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 7805 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
7806 | (adjusted_mode->crtc_vsync_start - 1) | |
7807 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
7808 | ||
b5e508d4 PZ |
7809 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
7810 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
7811 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
7812 | * bits. */ | |
7813 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
7814 | (pipe == PIPE_B || pipe == PIPE_C)) | |
7815 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
7816 | ||
b0e77b9c PZ |
7817 | /* pipesrc controls the size that is scaled from, which should |
7818 | * always be the user's requested size. | |
7819 | */ | |
7820 | I915_WRITE(PIPESRC(pipe), | |
6e3c9717 ACO |
7821 | ((intel_crtc->config->pipe_src_w - 1) << 16) | |
7822 | (intel_crtc->config->pipe_src_h - 1)); | |
b0e77b9c PZ |
7823 | } |
7824 | ||
1bd1bd80 | 7825 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
5cec258b | 7826 | struct intel_crtc_state *pipe_config) |
1bd1bd80 DV |
7827 | { |
7828 | struct drm_device *dev = crtc->base.dev; | |
7829 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7830 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
7831 | uint32_t tmp; | |
7832 | ||
7833 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7834 | pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; |
7835 | pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7836 | tmp = I915_READ(HBLANK(cpu_transcoder)); |
2d112de7 ACO |
7837 | pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; |
7838 | pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7839 | tmp = I915_READ(HSYNC(cpu_transcoder)); |
2d112de7 ACO |
7840 | pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; |
7841 | pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7842 | |
7843 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
2d112de7 ACO |
7844 | pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; |
7845 | pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7846 | tmp = I915_READ(VBLANK(cpu_transcoder)); |
2d112de7 ACO |
7847 | pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; |
7848 | pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 | 7849 | tmp = I915_READ(VSYNC(cpu_transcoder)); |
2d112de7 ACO |
7850 | pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; |
7851 | pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
1bd1bd80 DV |
7852 | |
7853 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
2d112de7 ACO |
7854 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; |
7855 | pipe_config->base.adjusted_mode.crtc_vtotal += 1; | |
7856 | pipe_config->base.adjusted_mode.crtc_vblank_end += 1; | |
1bd1bd80 DV |
7857 | } |
7858 | ||
7859 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
7860 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
7861 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
7862 | ||
2d112de7 ACO |
7863 | pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h; |
7864 | pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
7865 | } |
7866 | ||
f6a83288 | 7867 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
5cec258b | 7868 | struct intel_crtc_state *pipe_config) |
babea61d | 7869 | { |
2d112de7 ACO |
7870 | mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay; |
7871 | mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal; | |
7872 | mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start; | |
7873 | mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end; | |
babea61d | 7874 | |
2d112de7 ACO |
7875 | mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay; |
7876 | mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal; | |
7877 | mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start; | |
7878 | mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end; | |
babea61d | 7879 | |
2d112de7 | 7880 | mode->flags = pipe_config->base.adjusted_mode.flags; |
cd13f5ab | 7881 | mode->type = DRM_MODE_TYPE_DRIVER; |
babea61d | 7882 | |
2d112de7 ACO |
7883 | mode->clock = pipe_config->base.adjusted_mode.crtc_clock; |
7884 | mode->flags |= pipe_config->base.adjusted_mode.flags; | |
cd13f5ab ML |
7885 | |
7886 | mode->hsync = drm_mode_hsync(mode); | |
7887 | mode->vrefresh = drm_mode_vrefresh(mode); | |
7888 | drm_mode_set_name(mode); | |
babea61d JB |
7889 | } |
7890 | ||
84b046f3 DV |
7891 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
7892 | { | |
7893 | struct drm_device *dev = intel_crtc->base.dev; | |
7894 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7895 | uint32_t pipeconf; | |
7896 | ||
9f11a9e4 | 7897 | pipeconf = 0; |
84b046f3 | 7898 | |
b6b5d049 VS |
7899 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
7900 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
7901 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 7902 | |
6e3c9717 | 7903 | if (intel_crtc->config->double_wide) |
cf532bb2 | 7904 | pipeconf |= PIPECONF_DOUBLE_WIDE; |
84b046f3 | 7905 | |
ff9ce46e | 7906 | /* only g4x and later have fancy bpc/dither controls */ |
666a4537 | 7907 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
ff9ce46e | 7908 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6e3c9717 | 7909 | if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30) |
ff9ce46e | 7910 | pipeconf |= PIPECONF_DITHER_EN | |
84b046f3 | 7911 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 7912 | |
6e3c9717 | 7913 | switch (intel_crtc->config->pipe_bpp) { |
ff9ce46e DV |
7914 | case 18: |
7915 | pipeconf |= PIPECONF_6BPC; | |
7916 | break; | |
7917 | case 24: | |
7918 | pipeconf |= PIPECONF_8BPC; | |
7919 | break; | |
7920 | case 30: | |
7921 | pipeconf |= PIPECONF_10BPC; | |
7922 | break; | |
7923 | default: | |
7924 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
7925 | BUG(); | |
84b046f3 DV |
7926 | } |
7927 | } | |
7928 | ||
7929 | if (HAS_PIPE_CXSR(dev)) { | |
7930 | if (intel_crtc->lowfreq_avail) { | |
7931 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
7932 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
7933 | } else { | |
7934 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
7935 | } |
7936 | } | |
7937 | ||
6e3c9717 | 7938 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
efc2cfff | 7939 | if (INTEL_INFO(dev)->gen < 4 || |
409ee761 | 7940 | intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO)) |
efc2cfff VS |
7941 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; |
7942 | else | |
7943 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
7944 | } else | |
84b046f3 DV |
7945 | pipeconf |= PIPECONF_PROGRESSIVE; |
7946 | ||
666a4537 WB |
7947 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
7948 | intel_crtc->config->limited_color_range) | |
9f11a9e4 | 7949 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; |
9c8e09b7 | 7950 | |
84b046f3 DV |
7951 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
7952 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
7953 | } | |
7954 | ||
190f68c5 ACO |
7955 | static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, |
7956 | struct intel_crtc_state *crtc_state) | |
79e53945 | 7957 | { |
c7653199 | 7958 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 7959 | struct drm_i915_private *dev_priv = dev->dev_private; |
c751ce4f | 7960 | int refclk, num_connectors = 0; |
c329a4ec DV |
7961 | intel_clock_t clock; |
7962 | bool ok; | |
d4906093 | 7963 | const intel_limit_t *limit; |
55bb9992 | 7964 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 7965 | struct drm_connector *connector; |
55bb9992 ACO |
7966 | struct drm_connector_state *connector_state; |
7967 | int i; | |
79e53945 | 7968 | |
dd3cd74a ACO |
7969 | memset(&crtc_state->dpll_hw_state, 0, |
7970 | sizeof(crtc_state->dpll_hw_state)); | |
7971 | ||
a65347ba JN |
7972 | if (crtc_state->has_dsi_encoder) |
7973 | return 0; | |
43565a06 | 7974 | |
a65347ba JN |
7975 | for_each_connector_in_state(state, connector, connector_state, i) { |
7976 | if (connector_state->crtc == &crtc->base) | |
7977 | num_connectors++; | |
79e53945 JB |
7978 | } |
7979 | ||
190f68c5 | 7980 | if (!crtc_state->clock_set) { |
a93e255f | 7981 | refclk = i9xx_get_refclk(crtc_state, num_connectors); |
79e53945 | 7982 | |
e9fd1c02 JN |
7983 | /* |
7984 | * Returns a set of divisors for the desired target clock with | |
7985 | * the given refclk, or FALSE. The returned values represent | |
7986 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
7987 | * 2) / p1 / p2. | |
7988 | */ | |
a93e255f ACO |
7989 | limit = intel_limit(crtc_state, refclk); |
7990 | ok = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 7991 | crtc_state->port_clock, |
e9fd1c02 | 7992 | refclk, NULL, &clock); |
f2335330 | 7993 | if (!ok) { |
e9fd1c02 JN |
7994 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7995 | return -EINVAL; | |
7996 | } | |
79e53945 | 7997 | |
f2335330 | 7998 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
7999 | crtc_state->dpll.n = clock.n; |
8000 | crtc_state->dpll.m1 = clock.m1; | |
8001 | crtc_state->dpll.m2 = clock.m2; | |
8002 | crtc_state->dpll.p1 = clock.p1; | |
8003 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 8004 | } |
7026d4ac | 8005 | |
e9fd1c02 | 8006 | if (IS_GEN2(dev)) { |
c329a4ec | 8007 | i8xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 8008 | num_connectors); |
9d556c99 | 8009 | } else if (IS_CHERRYVIEW(dev)) { |
251ac862 | 8010 | chv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 8011 | } else if (IS_VALLEYVIEW(dev)) { |
251ac862 | 8012 | vlv_compute_dpll(crtc, crtc_state); |
e9fd1c02 | 8013 | } else { |
c329a4ec | 8014 | i9xx_compute_dpll(crtc, crtc_state, NULL, |
251ac862 | 8015 | num_connectors); |
e9fd1c02 | 8016 | } |
79e53945 | 8017 | |
c8f7a0db | 8018 | return 0; |
f564048e EA |
8019 | } |
8020 | ||
2fa2fe9a | 8021 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 8022 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
8023 | { |
8024 | struct drm_device *dev = crtc->base.dev; | |
8025 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8026 | uint32_t tmp; | |
8027 | ||
dc9e7dec VS |
8028 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
8029 | return; | |
8030 | ||
2fa2fe9a | 8031 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
8032 | if (!(tmp & PFIT_ENABLE)) |
8033 | return; | |
2fa2fe9a | 8034 | |
06922821 | 8035 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
8036 | if (INTEL_INFO(dev)->gen < 4) { |
8037 | if (crtc->pipe != PIPE_B) | |
8038 | return; | |
2fa2fe9a DV |
8039 | } else { |
8040 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
8041 | return; | |
8042 | } | |
8043 | ||
06922821 | 8044 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
8045 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
8046 | if (INTEL_INFO(dev)->gen < 5) | |
8047 | pipe_config->gmch_pfit.lvds_border_bits = | |
8048 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
8049 | } | |
8050 | ||
acbec814 | 8051 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8052 | struct intel_crtc_state *pipe_config) |
acbec814 JB |
8053 | { |
8054 | struct drm_device *dev = crtc->base.dev; | |
8055 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8056 | int pipe = pipe_config->cpu_transcoder; | |
8057 | intel_clock_t clock; | |
8058 | u32 mdiv; | |
662c6ecb | 8059 | int refclk = 100000; |
acbec814 | 8060 | |
f573de5a SK |
8061 | /* In case of MIPI DPLL will not even be used */ |
8062 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
8063 | return; | |
8064 | ||
a580516d | 8065 | mutex_lock(&dev_priv->sb_lock); |
ab3c759a | 8066 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
a580516d | 8067 | mutex_unlock(&dev_priv->sb_lock); |
acbec814 JB |
8068 | |
8069 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
8070 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
8071 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
8072 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
8073 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
8074 | ||
dccbea3b | 8075 | pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock); |
acbec814 JB |
8076 | } |
8077 | ||
5724dbd1 DL |
8078 | static void |
8079 | i9xx_get_initial_plane_config(struct intel_crtc *crtc, | |
8080 | struct intel_initial_plane_config *plane_config) | |
1ad292b5 JB |
8081 | { |
8082 | struct drm_device *dev = crtc->base.dev; | |
8083 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8084 | u32 val, base, offset; | |
8085 | int pipe = crtc->pipe, plane = crtc->plane; | |
8086 | int fourcc, pixel_format; | |
6761dd31 | 8087 | unsigned int aligned_height; |
b113d5ee | 8088 | struct drm_framebuffer *fb; |
1b842c89 | 8089 | struct intel_framebuffer *intel_fb; |
1ad292b5 | 8090 | |
42a7b088 DL |
8091 | val = I915_READ(DSPCNTR(plane)); |
8092 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
8093 | return; | |
8094 | ||
d9806c9f | 8095 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 8096 | if (!intel_fb) { |
1ad292b5 JB |
8097 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
8098 | return; | |
8099 | } | |
8100 | ||
1b842c89 DL |
8101 | fb = &intel_fb->base; |
8102 | ||
18c5247e DV |
8103 | if (INTEL_INFO(dev)->gen >= 4) { |
8104 | if (val & DISPPLANE_TILED) { | |
49af449b | 8105 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
8106 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
8107 | } | |
8108 | } | |
1ad292b5 JB |
8109 | |
8110 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 8111 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
8112 | fb->pixel_format = fourcc; |
8113 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
1ad292b5 JB |
8114 | |
8115 | if (INTEL_INFO(dev)->gen >= 4) { | |
49af449b | 8116 | if (plane_config->tiling) |
1ad292b5 JB |
8117 | offset = I915_READ(DSPTILEOFF(plane)); |
8118 | else | |
8119 | offset = I915_READ(DSPLINOFF(plane)); | |
8120 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
8121 | } else { | |
8122 | base = I915_READ(DSPADDR(plane)); | |
8123 | } | |
8124 | plane_config->base = base; | |
8125 | ||
8126 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
8127 | fb->width = ((val >> 16) & 0xfff) + 1; |
8128 | fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
8129 | |
8130 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 8131 | fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 8132 | |
b113d5ee | 8133 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
8134 | fb->pixel_format, |
8135 | fb->modifier[0]); | |
1ad292b5 | 8136 | |
f37b5c2b | 8137 | plane_config->size = fb->pitches[0] * aligned_height; |
1ad292b5 | 8138 | |
2844a921 DL |
8139 | DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
8140 | pipe_name(pipe), plane, fb->width, fb->height, | |
8141 | fb->bits_per_pixel, base, fb->pitches[0], | |
8142 | plane_config->size); | |
1ad292b5 | 8143 | |
2d14030b | 8144 | plane_config->fb = intel_fb; |
1ad292b5 JB |
8145 | } |
8146 | ||
70b23a98 | 8147 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 8148 | struct intel_crtc_state *pipe_config) |
70b23a98 VS |
8149 | { |
8150 | struct drm_device *dev = crtc->base.dev; | |
8151 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8152 | int pipe = pipe_config->cpu_transcoder; | |
8153 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
8154 | intel_clock_t clock; | |
0d7b6b11 | 8155 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3; |
70b23a98 VS |
8156 | int refclk = 100000; |
8157 | ||
a580516d | 8158 | mutex_lock(&dev_priv->sb_lock); |
70b23a98 VS |
8159 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); |
8160 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
8161 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
8162 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
0d7b6b11 | 8163 | pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); |
a580516d | 8164 | mutex_unlock(&dev_priv->sb_lock); |
70b23a98 VS |
8165 | |
8166 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
0d7b6b11 ID |
8167 | clock.m2 = (pll_dw0 & 0xff) << 22; |
8168 | if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) | |
8169 | clock.m2 |= pll_dw2 & 0x3fffff; | |
70b23a98 VS |
8170 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; |
8171 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
8172 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
8173 | ||
dccbea3b | 8174 | pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock); |
70b23a98 VS |
8175 | } |
8176 | ||
0e8ffe1b | 8177 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 8178 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
8179 | { |
8180 | struct drm_device *dev = crtc->base.dev; | |
8181 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8182 | uint32_t tmp; | |
8183 | ||
f458ebbc DV |
8184 | if (!intel_display_power_is_enabled(dev_priv, |
8185 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
b5482bd0 ID |
8186 | return false; |
8187 | ||
e143a21c | 8188 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 8189 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 8190 | |
0e8ffe1b DV |
8191 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
8192 | if (!(tmp & PIPECONF_ENABLE)) | |
8193 | return false; | |
8194 | ||
666a4537 | 8195 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
42571aef VS |
8196 | switch (tmp & PIPECONF_BPC_MASK) { |
8197 | case PIPECONF_6BPC: | |
8198 | pipe_config->pipe_bpp = 18; | |
8199 | break; | |
8200 | case PIPECONF_8BPC: | |
8201 | pipe_config->pipe_bpp = 24; | |
8202 | break; | |
8203 | case PIPECONF_10BPC: | |
8204 | pipe_config->pipe_bpp = 30; | |
8205 | break; | |
8206 | default: | |
8207 | break; | |
8208 | } | |
8209 | } | |
8210 | ||
666a4537 WB |
8211 | if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) && |
8212 | (tmp & PIPECONF_COLOR_RANGE_SELECT)) | |
b5a9fa09 DV |
8213 | pipe_config->limited_color_range = true; |
8214 | ||
282740f7 VS |
8215 | if (INTEL_INFO(dev)->gen < 4) |
8216 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
8217 | ||
1bd1bd80 DV |
8218 | intel_get_pipe_timings(crtc, pipe_config); |
8219 | ||
2fa2fe9a DV |
8220 | i9xx_get_pfit_config(crtc, pipe_config); |
8221 | ||
6c49f241 DV |
8222 | if (INTEL_INFO(dev)->gen >= 4) { |
8223 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
8224 | pipe_config->pixel_multiplier = | |
8225 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
8226 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 8227 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
8228 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
8229 | tmp = I915_READ(DPLL(crtc->pipe)); | |
8230 | pipe_config->pixel_multiplier = | |
8231 | ((tmp & SDVO_MULTIPLIER_MASK) | |
8232 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
8233 | } else { | |
8234 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
8235 | * port and will be fixed up in the encoder->get_config | |
8236 | * function. */ | |
8237 | pipe_config->pixel_multiplier = 1; | |
8238 | } | |
8bcc2795 | 8239 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
666a4537 | 8240 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
1c4e0274 VS |
8241 | /* |
8242 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
8243 | * on 830. Filter it out here so that we don't | |
8244 | * report errors due to that. | |
8245 | */ | |
8246 | if (IS_I830(dev)) | |
8247 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
8248 | ||
8bcc2795 DV |
8249 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
8250 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
8251 | } else { |
8252 | /* Mask out read-only status bits. */ | |
8253 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
8254 | DPLL_PORTC_READY_MASK | | |
8255 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 8256 | } |
6c49f241 | 8257 | |
70b23a98 VS |
8258 | if (IS_CHERRYVIEW(dev)) |
8259 | chv_crtc_clock_get(crtc, pipe_config); | |
8260 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
8261 | vlv_crtc_clock_get(crtc, pipe_config); |
8262 | else | |
8263 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 8264 | |
0f64614d VS |
8265 | /* |
8266 | * Normally the dotclock is filled in by the encoder .get_config() | |
8267 | * but in case the pipe is enabled w/o any ports we need a sane | |
8268 | * default. | |
8269 | */ | |
8270 | pipe_config->base.adjusted_mode.crtc_clock = | |
8271 | pipe_config->port_clock / pipe_config->pixel_multiplier; | |
8272 | ||
0e8ffe1b DV |
8273 | return true; |
8274 | } | |
8275 | ||
dde86e2d | 8276 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
8277 | { |
8278 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 8279 | struct intel_encoder *encoder; |
74cfd7ac | 8280 | u32 val, final; |
13d83a67 | 8281 | bool has_lvds = false; |
199e5d79 | 8282 | bool has_cpu_edp = false; |
199e5d79 | 8283 | bool has_panel = false; |
99eb6a01 KP |
8284 | bool has_ck505 = false; |
8285 | bool can_ssc = false; | |
13d83a67 JB |
8286 | |
8287 | /* We need to take the global config into account */ | |
b2784e15 | 8288 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
8289 | switch (encoder->type) { |
8290 | case INTEL_OUTPUT_LVDS: | |
8291 | has_panel = true; | |
8292 | has_lvds = true; | |
8293 | break; | |
8294 | case INTEL_OUTPUT_EDP: | |
8295 | has_panel = true; | |
2de6905f | 8296 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
8297 | has_cpu_edp = true; |
8298 | break; | |
6847d71b PZ |
8299 | default: |
8300 | break; | |
13d83a67 JB |
8301 | } |
8302 | } | |
8303 | ||
99eb6a01 | 8304 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 8305 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
8306 | can_ssc = has_ck505; |
8307 | } else { | |
8308 | has_ck505 = false; | |
8309 | can_ssc = true; | |
8310 | } | |
8311 | ||
2de6905f ID |
8312 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
8313 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
8314 | |
8315 | /* Ironlake: try to setup display ref clock before DPLL | |
8316 | * enabling. This is only under driver's control after | |
8317 | * PCH B stepping, previous chipset stepping should be | |
8318 | * ignoring this setting. | |
8319 | */ | |
74cfd7ac CW |
8320 | val = I915_READ(PCH_DREF_CONTROL); |
8321 | ||
8322 | /* As we must carefully and slowly disable/enable each source in turn, | |
8323 | * compute the final state we want first and check if we need to | |
8324 | * make any changes at all. | |
8325 | */ | |
8326 | final = val; | |
8327 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
8328 | if (has_ck505) | |
8329 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
8330 | else | |
8331 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
8332 | ||
8333 | final &= ~DREF_SSC_SOURCE_MASK; | |
8334 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
8335 | final &= ~DREF_SSC1_ENABLE; | |
8336 | ||
8337 | if (has_panel) { | |
8338 | final |= DREF_SSC_SOURCE_ENABLE; | |
8339 | ||
8340 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8341 | final |= DREF_SSC1_ENABLE; | |
8342 | ||
8343 | if (has_cpu_edp) { | |
8344 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
8345 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
8346 | else | |
8347 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
8348 | } else | |
8349 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8350 | } else { | |
8351 | final |= DREF_SSC_SOURCE_DISABLE; | |
8352 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
8353 | } | |
8354 | ||
8355 | if (final == val) | |
8356 | return; | |
8357 | ||
13d83a67 | 8358 | /* Always enable nonspread source */ |
74cfd7ac | 8359 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 8360 | |
99eb6a01 | 8361 | if (has_ck505) |
74cfd7ac | 8362 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 8363 | else |
74cfd7ac | 8364 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 8365 | |
199e5d79 | 8366 | if (has_panel) { |
74cfd7ac CW |
8367 | val &= ~DREF_SSC_SOURCE_MASK; |
8368 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 8369 | |
199e5d79 | 8370 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 8371 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8372 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 8373 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 8374 | } else |
74cfd7ac | 8375 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
8376 | |
8377 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 8378 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8379 | POSTING_READ(PCH_DREF_CONTROL); |
8380 | udelay(200); | |
8381 | ||
74cfd7ac | 8382 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
8383 | |
8384 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 8385 | if (has_cpu_edp) { |
99eb6a01 | 8386 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 8387 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 8388 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 8389 | } else |
74cfd7ac | 8390 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 8391 | } else |
74cfd7ac | 8392 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8393 | |
74cfd7ac | 8394 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8395 | POSTING_READ(PCH_DREF_CONTROL); |
8396 | udelay(200); | |
8397 | } else { | |
8398 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
8399 | ||
74cfd7ac | 8400 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
8401 | |
8402 | /* Turn off CPU output */ | |
74cfd7ac | 8403 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 8404 | |
74cfd7ac | 8405 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
8406 | POSTING_READ(PCH_DREF_CONTROL); |
8407 | udelay(200); | |
8408 | ||
8409 | /* Turn off the SSC source */ | |
74cfd7ac CW |
8410 | val &= ~DREF_SSC_SOURCE_MASK; |
8411 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
8412 | |
8413 | /* Turn off SSC1 */ | |
74cfd7ac | 8414 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 8415 | |
74cfd7ac | 8416 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
8417 | POSTING_READ(PCH_DREF_CONTROL); |
8418 | udelay(200); | |
8419 | } | |
74cfd7ac CW |
8420 | |
8421 | BUG_ON(val != final); | |
13d83a67 JB |
8422 | } |
8423 | ||
f31f2d55 | 8424 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 8425 | { |
f31f2d55 | 8426 | uint32_t tmp; |
dde86e2d | 8427 | |
0ff066a9 PZ |
8428 | tmp = I915_READ(SOUTH_CHICKEN2); |
8429 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
8430 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8431 | |
0ff066a9 PZ |
8432 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
8433 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
8434 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 8435 | |
0ff066a9 PZ |
8436 | tmp = I915_READ(SOUTH_CHICKEN2); |
8437 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
8438 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 8439 | |
0ff066a9 PZ |
8440 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
8441 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
8442 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
8443 | } |
8444 | ||
8445 | /* WaMPhyProgramming:hsw */ | |
8446 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
8447 | { | |
8448 | uint32_t tmp; | |
dde86e2d PZ |
8449 | |
8450 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
8451 | tmp &= ~(0xFF << 24); | |
8452 | tmp |= (0x12 << 24); | |
8453 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
8454 | ||
dde86e2d PZ |
8455 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
8456 | tmp |= (1 << 11); | |
8457 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
8458 | ||
8459 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
8460 | tmp |= (1 << 11); | |
8461 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
8462 | ||
dde86e2d PZ |
8463 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
8464 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8465 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
8466 | ||
8467 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
8468 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
8469 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
8470 | ||
0ff066a9 PZ |
8471 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
8472 | tmp &= ~(7 << 13); | |
8473 | tmp |= (5 << 13); | |
8474 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 8475 | |
0ff066a9 PZ |
8476 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
8477 | tmp &= ~(7 << 13); | |
8478 | tmp |= (5 << 13); | |
8479 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
8480 | |
8481 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
8482 | tmp &= ~0xFF; | |
8483 | tmp |= 0x1C; | |
8484 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
8485 | ||
8486 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
8487 | tmp &= ~0xFF; | |
8488 | tmp |= 0x1C; | |
8489 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
8490 | ||
8491 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
8492 | tmp &= ~(0xFF << 16); | |
8493 | tmp |= (0x1C << 16); | |
8494 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
8495 | ||
8496 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
8497 | tmp &= ~(0xFF << 16); | |
8498 | tmp |= (0x1C << 16); | |
8499 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
8500 | ||
0ff066a9 PZ |
8501 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
8502 | tmp |= (1 << 27); | |
8503 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 8504 | |
0ff066a9 PZ |
8505 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
8506 | tmp |= (1 << 27); | |
8507 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 8508 | |
0ff066a9 PZ |
8509 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
8510 | tmp &= ~(0xF << 28); | |
8511 | tmp |= (4 << 28); | |
8512 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 8513 | |
0ff066a9 PZ |
8514 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
8515 | tmp &= ~(0xF << 28); | |
8516 | tmp |= (4 << 28); | |
8517 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
8518 | } |
8519 | ||
2fa86a1f PZ |
8520 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
8521 | * Programming" based on the parameters passed: | |
8522 | * - Sequence to enable CLKOUT_DP | |
8523 | * - Sequence to enable CLKOUT_DP without spread | |
8524 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
8525 | */ | |
8526 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
8527 | bool with_fdi) | |
f31f2d55 PZ |
8528 | { |
8529 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
8530 | uint32_t reg, tmp; |
8531 | ||
8532 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
8533 | with_spread = true; | |
c2699524 | 8534 | if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n")) |
2fa86a1f | 8535 | with_fdi = false; |
f31f2d55 | 8536 | |
a580516d | 8537 | mutex_lock(&dev_priv->sb_lock); |
f31f2d55 PZ |
8538 | |
8539 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8540 | tmp &= ~SBI_SSCCTL_DISABLE; | |
8541 | tmp |= SBI_SSCCTL_PATHALT; | |
8542 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8543 | ||
8544 | udelay(24); | |
8545 | ||
2fa86a1f PZ |
8546 | if (with_spread) { |
8547 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8548 | tmp &= ~SBI_SSCCTL_PATHALT; | |
8549 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 8550 | |
2fa86a1f PZ |
8551 | if (with_fdi) { |
8552 | lpt_reset_fdi_mphy(dev_priv); | |
8553 | lpt_program_fdi_mphy(dev_priv); | |
8554 | } | |
8555 | } | |
dde86e2d | 8556 | |
c2699524 | 8557 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
2fa86a1f PZ |
8558 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8559 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8560 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 | 8561 | |
a580516d | 8562 | mutex_unlock(&dev_priv->sb_lock); |
dde86e2d PZ |
8563 | } |
8564 | ||
47701c3b PZ |
8565 | /* Sequence to disable CLKOUT_DP */ |
8566 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
8567 | { | |
8568 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8569 | uint32_t reg, tmp; | |
8570 | ||
a580516d | 8571 | mutex_lock(&dev_priv->sb_lock); |
47701c3b | 8572 | |
c2699524 | 8573 | reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0; |
47701c3b PZ |
8574 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); |
8575 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
8576 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
8577 | ||
8578 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
8579 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
8580 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
8581 | tmp |= SBI_SSCCTL_PATHALT; | |
8582 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8583 | udelay(32); | |
8584 | } | |
8585 | tmp |= SBI_SSCCTL_DISABLE; | |
8586 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
8587 | } | |
8588 | ||
a580516d | 8589 | mutex_unlock(&dev_priv->sb_lock); |
47701c3b PZ |
8590 | } |
8591 | ||
f7be2c21 VS |
8592 | #define BEND_IDX(steps) ((50 + (steps)) / 5) |
8593 | ||
8594 | static const uint16_t sscdivintphase[] = { | |
8595 | [BEND_IDX( 50)] = 0x3B23, | |
8596 | [BEND_IDX( 45)] = 0x3B23, | |
8597 | [BEND_IDX( 40)] = 0x3C23, | |
8598 | [BEND_IDX( 35)] = 0x3C23, | |
8599 | [BEND_IDX( 30)] = 0x3D23, | |
8600 | [BEND_IDX( 25)] = 0x3D23, | |
8601 | [BEND_IDX( 20)] = 0x3E23, | |
8602 | [BEND_IDX( 15)] = 0x3E23, | |
8603 | [BEND_IDX( 10)] = 0x3F23, | |
8604 | [BEND_IDX( 5)] = 0x3F23, | |
8605 | [BEND_IDX( 0)] = 0x0025, | |
8606 | [BEND_IDX( -5)] = 0x0025, | |
8607 | [BEND_IDX(-10)] = 0x0125, | |
8608 | [BEND_IDX(-15)] = 0x0125, | |
8609 | [BEND_IDX(-20)] = 0x0225, | |
8610 | [BEND_IDX(-25)] = 0x0225, | |
8611 | [BEND_IDX(-30)] = 0x0325, | |
8612 | [BEND_IDX(-35)] = 0x0325, | |
8613 | [BEND_IDX(-40)] = 0x0425, | |
8614 | [BEND_IDX(-45)] = 0x0425, | |
8615 | [BEND_IDX(-50)] = 0x0525, | |
8616 | }; | |
8617 | ||
8618 | /* | |
8619 | * Bend CLKOUT_DP | |
8620 | * steps -50 to 50 inclusive, in steps of 5 | |
8621 | * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz) | |
8622 | * change in clock period = -(steps / 10) * 5.787 ps | |
8623 | */ | |
8624 | static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps) | |
8625 | { | |
8626 | uint32_t tmp; | |
8627 | int idx = BEND_IDX(steps); | |
8628 | ||
8629 | if (WARN_ON(steps % 5 != 0)) | |
8630 | return; | |
8631 | ||
8632 | if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase))) | |
8633 | return; | |
8634 | ||
8635 | mutex_lock(&dev_priv->sb_lock); | |
8636 | ||
8637 | if (steps % 10 != 0) | |
8638 | tmp = 0xAAAAAAAB; | |
8639 | else | |
8640 | tmp = 0x00000000; | |
8641 | intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK); | |
8642 | ||
8643 | tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK); | |
8644 | tmp &= 0xffff0000; | |
8645 | tmp |= sscdivintphase[idx]; | |
8646 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK); | |
8647 | ||
8648 | mutex_unlock(&dev_priv->sb_lock); | |
8649 | } | |
8650 | ||
8651 | #undef BEND_IDX | |
8652 | ||
bf8fa3d3 PZ |
8653 | static void lpt_init_pch_refclk(struct drm_device *dev) |
8654 | { | |
bf8fa3d3 PZ |
8655 | struct intel_encoder *encoder; |
8656 | bool has_vga = false; | |
8657 | ||
b2784e15 | 8658 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
8659 | switch (encoder->type) { |
8660 | case INTEL_OUTPUT_ANALOG: | |
8661 | has_vga = true; | |
8662 | break; | |
6847d71b PZ |
8663 | default: |
8664 | break; | |
bf8fa3d3 PZ |
8665 | } |
8666 | } | |
8667 | ||
f7be2c21 VS |
8668 | if (has_vga) { |
8669 | lpt_bend_clkout_dp(to_i915(dev), 0); | |
47701c3b | 8670 | lpt_enable_clkout_dp(dev, true, true); |
f7be2c21 | 8671 | } else { |
47701c3b | 8672 | lpt_disable_clkout_dp(dev); |
f7be2c21 | 8673 | } |
bf8fa3d3 PZ |
8674 | } |
8675 | ||
dde86e2d PZ |
8676 | /* |
8677 | * Initialize reference clocks when the driver loads | |
8678 | */ | |
8679 | void intel_init_pch_refclk(struct drm_device *dev) | |
8680 | { | |
8681 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
8682 | ironlake_init_pch_refclk(dev); | |
8683 | else if (HAS_PCH_LPT(dev)) | |
8684 | lpt_init_pch_refclk(dev); | |
8685 | } | |
8686 | ||
55bb9992 | 8687 | static int ironlake_get_refclk(struct intel_crtc_state *crtc_state) |
d9d444cb | 8688 | { |
55bb9992 | 8689 | struct drm_device *dev = crtc_state->base.crtc->dev; |
d9d444cb | 8690 | struct drm_i915_private *dev_priv = dev->dev_private; |
55bb9992 | 8691 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8692 | struct drm_connector *connector; |
55bb9992 | 8693 | struct drm_connector_state *connector_state; |
d9d444cb | 8694 | struct intel_encoder *encoder; |
55bb9992 | 8695 | int num_connectors = 0, i; |
d9d444cb JB |
8696 | bool is_lvds = false; |
8697 | ||
da3ced29 | 8698 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8699 | if (connector_state->crtc != crtc_state->base.crtc) |
8700 | continue; | |
8701 | ||
8702 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8703 | ||
d9d444cb JB |
8704 | switch (encoder->type) { |
8705 | case INTEL_OUTPUT_LVDS: | |
8706 | is_lvds = true; | |
8707 | break; | |
6847d71b PZ |
8708 | default: |
8709 | break; | |
d9d444cb JB |
8710 | } |
8711 | num_connectors++; | |
8712 | } | |
8713 | ||
8714 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 8715 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 8716 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 8717 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
8718 | } |
8719 | ||
8720 | return 120000; | |
8721 | } | |
8722 | ||
6ff93609 | 8723 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 8724 | { |
c8203565 | 8725 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
8726 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8727 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
8728 | uint32_t val; |
8729 | ||
78114071 | 8730 | val = 0; |
c8203565 | 8731 | |
6e3c9717 | 8732 | switch (intel_crtc->config->pipe_bpp) { |
c8203565 | 8733 | case 18: |
dfd07d72 | 8734 | val |= PIPECONF_6BPC; |
c8203565 PZ |
8735 | break; |
8736 | case 24: | |
dfd07d72 | 8737 | val |= PIPECONF_8BPC; |
c8203565 PZ |
8738 | break; |
8739 | case 30: | |
dfd07d72 | 8740 | val |= PIPECONF_10BPC; |
c8203565 PZ |
8741 | break; |
8742 | case 36: | |
dfd07d72 | 8743 | val |= PIPECONF_12BPC; |
c8203565 PZ |
8744 | break; |
8745 | default: | |
cc769b62 PZ |
8746 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
8747 | BUG(); | |
c8203565 PZ |
8748 | } |
8749 | ||
6e3c9717 | 8750 | if (intel_crtc->config->dither) |
c8203565 PZ |
8751 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8752 | ||
6e3c9717 | 8753 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
8754 | val |= PIPECONF_INTERLACED_ILK; |
8755 | else | |
8756 | val |= PIPECONF_PROGRESSIVE; | |
8757 | ||
6e3c9717 | 8758 | if (intel_crtc->config->limited_color_range) |
3685a8f3 | 8759 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 8760 | |
c8203565 PZ |
8761 | I915_WRITE(PIPECONF(pipe), val); |
8762 | POSTING_READ(PIPECONF(pipe)); | |
8763 | } | |
8764 | ||
86d3efce VS |
8765 | /* |
8766 | * Set up the pipe CSC unit. | |
8767 | * | |
8768 | * Currently only full range RGB to limited range RGB conversion | |
8769 | * is supported, but eventually this should handle various | |
8770 | * RGB<->YCbCr scenarios as well. | |
8771 | */ | |
50f3b016 | 8772 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
8773 | { |
8774 | struct drm_device *dev = crtc->dev; | |
8775 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8776 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8777 | int pipe = intel_crtc->pipe; | |
8778 | uint16_t coeff = 0x7800; /* 1.0 */ | |
8779 | ||
8780 | /* | |
8781 | * TODO: Check what kind of values actually come out of the pipe | |
8782 | * with these coeff/postoff values and adjust to get the best | |
8783 | * accuracy. Perhaps we even need to take the bpc value into | |
8784 | * consideration. | |
8785 | */ | |
8786 | ||
6e3c9717 | 8787 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8788 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
8789 | ||
8790 | /* | |
8791 | * GY/GU and RY/RU should be the other way around according | |
8792 | * to BSpec, but reality doesn't agree. Just set them up in | |
8793 | * a way that results in the correct picture. | |
8794 | */ | |
8795 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
8796 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
8797 | ||
8798 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
8799 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
8800 | ||
8801 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
8802 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
8803 | ||
8804 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
8805 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
8806 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
8807 | ||
8808 | if (INTEL_INFO(dev)->gen > 6) { | |
8809 | uint16_t postoff = 0; | |
8810 | ||
6e3c9717 | 8811 | if (intel_crtc->config->limited_color_range) |
32cf0cb0 | 8812 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
8813 | |
8814 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
8815 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
8816 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
8817 | ||
8818 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
8819 | } else { | |
8820 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
8821 | ||
6e3c9717 | 8822 | if (intel_crtc->config->limited_color_range) |
86d3efce VS |
8823 | mode |= CSC_BLACK_SCREEN_OFFSET; |
8824 | ||
8825 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
8826 | } | |
8827 | } | |
8828 | ||
6ff93609 | 8829 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 8830 | { |
756f85cf PZ |
8831 | struct drm_device *dev = crtc->dev; |
8832 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 8833 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 8834 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 8835 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
ee2b0b38 PZ |
8836 | uint32_t val; |
8837 | ||
3eff4faa | 8838 | val = 0; |
ee2b0b38 | 8839 | |
6e3c9717 | 8840 | if (IS_HASWELL(dev) && intel_crtc->config->dither) |
ee2b0b38 PZ |
8841 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
8842 | ||
6e3c9717 | 8843 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
8844 | val |= PIPECONF_INTERLACED_ILK; |
8845 | else | |
8846 | val |= PIPECONF_PROGRESSIVE; | |
8847 | ||
702e7a56 PZ |
8848 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
8849 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
8850 | |
8851 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
8852 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf | 8853 | |
3cdf122c | 8854 | if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) { |
756f85cf PZ |
8855 | val = 0; |
8856 | ||
6e3c9717 | 8857 | switch (intel_crtc->config->pipe_bpp) { |
756f85cf PZ |
8858 | case 18: |
8859 | val |= PIPEMISC_DITHER_6_BPC; | |
8860 | break; | |
8861 | case 24: | |
8862 | val |= PIPEMISC_DITHER_8_BPC; | |
8863 | break; | |
8864 | case 30: | |
8865 | val |= PIPEMISC_DITHER_10_BPC; | |
8866 | break; | |
8867 | case 36: | |
8868 | val |= PIPEMISC_DITHER_12_BPC; | |
8869 | break; | |
8870 | default: | |
8871 | /* Case prevented by pipe_config_set_bpp. */ | |
8872 | BUG(); | |
8873 | } | |
8874 | ||
6e3c9717 | 8875 | if (intel_crtc->config->dither) |
756f85cf PZ |
8876 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; |
8877 | ||
8878 | I915_WRITE(PIPEMISC(pipe), val); | |
8879 | } | |
ee2b0b38 PZ |
8880 | } |
8881 | ||
6591c6e4 | 8882 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
190f68c5 | 8883 | struct intel_crtc_state *crtc_state, |
6591c6e4 PZ |
8884 | intel_clock_t *clock, |
8885 | bool *has_reduced_clock, | |
8886 | intel_clock_t *reduced_clock) | |
8887 | { | |
8888 | struct drm_device *dev = crtc->dev; | |
8889 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6591c6e4 | 8890 | int refclk; |
d4906093 | 8891 | const intel_limit_t *limit; |
c329a4ec | 8892 | bool ret; |
79e53945 | 8893 | |
55bb9992 | 8894 | refclk = ironlake_get_refclk(crtc_state); |
79e53945 | 8895 | |
d4906093 ML |
8896 | /* |
8897 | * Returns a set of divisors for the desired target clock with the given | |
8898 | * refclk, or FALSE. The returned values represent the clock equation: | |
8899 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
8900 | */ | |
a93e255f ACO |
8901 | limit = intel_limit(crtc_state, refclk); |
8902 | ret = dev_priv->display.find_dpll(limit, crtc_state, | |
190f68c5 | 8903 | crtc_state->port_clock, |
ee9300bb | 8904 | refclk, NULL, clock); |
6591c6e4 PZ |
8905 | if (!ret) |
8906 | return false; | |
cda4b7d3 | 8907 | |
6591c6e4 PZ |
8908 | return true; |
8909 | } | |
8910 | ||
d4b1931c PZ |
8911 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
8912 | { | |
8913 | /* | |
8914 | * Account for spread spectrum to avoid | |
8915 | * oversubscribing the link. Max center spread | |
8916 | * is 2.5%; use 5% for safety's sake. | |
8917 | */ | |
8918 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 8919 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
8920 | } |
8921 | ||
7429e9d4 | 8922 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 8923 | { |
7429e9d4 | 8924 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
8925 | } |
8926 | ||
de13a2e3 | 8927 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
190f68c5 | 8928 | struct intel_crtc_state *crtc_state, |
7429e9d4 | 8929 | u32 *fp, |
9a7c7890 | 8930 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 8931 | { |
de13a2e3 | 8932 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
8933 | struct drm_device *dev = crtc->dev; |
8934 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55bb9992 | 8935 | struct drm_atomic_state *state = crtc_state->base.state; |
da3ced29 | 8936 | struct drm_connector *connector; |
55bb9992 ACO |
8937 | struct drm_connector_state *connector_state; |
8938 | struct intel_encoder *encoder; | |
de13a2e3 | 8939 | uint32_t dpll; |
55bb9992 | 8940 | int factor, num_connectors = 0, i; |
09ede541 | 8941 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 8942 | |
da3ced29 | 8943 | for_each_connector_in_state(state, connector, connector_state, i) { |
55bb9992 ACO |
8944 | if (connector_state->crtc != crtc_state->base.crtc) |
8945 | continue; | |
8946 | ||
8947 | encoder = to_intel_encoder(connector_state->best_encoder); | |
8948 | ||
8949 | switch (encoder->type) { | |
79e53945 JB |
8950 | case INTEL_OUTPUT_LVDS: |
8951 | is_lvds = true; | |
8952 | break; | |
8953 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 8954 | case INTEL_OUTPUT_HDMI: |
79e53945 | 8955 | is_sdvo = true; |
79e53945 | 8956 | break; |
6847d71b PZ |
8957 | default: |
8958 | break; | |
79e53945 | 8959 | } |
43565a06 | 8960 | |
c751ce4f | 8961 | num_connectors++; |
79e53945 | 8962 | } |
79e53945 | 8963 | |
c1858123 | 8964 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
8965 | factor = 21; |
8966 | if (is_lvds) { | |
8967 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 8968 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 8969 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 8970 | factor = 25; |
190f68c5 | 8971 | } else if (crtc_state->sdvo_tv_clock) |
8febb297 | 8972 | factor = 20; |
c1858123 | 8973 | |
190f68c5 | 8974 | if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor)) |
7d0ac5b7 | 8975 | *fp |= FP_CB_TUNE; |
2c07245f | 8976 | |
9a7c7890 DV |
8977 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
8978 | *fp2 |= FP_CB_TUNE; | |
8979 | ||
5eddb70b | 8980 | dpll = 0; |
2c07245f | 8981 | |
a07d6787 EA |
8982 | if (is_lvds) |
8983 | dpll |= DPLLB_MODE_LVDS; | |
8984 | else | |
8985 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 8986 | |
190f68c5 | 8987 | dpll |= (crtc_state->pixel_multiplier - 1) |
ef1b460d | 8988 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; |
198a037f DV |
8989 | |
8990 | if (is_sdvo) | |
4a33e48d | 8991 | dpll |= DPLL_SDVO_HIGH_SPEED; |
190f68c5 | 8992 | if (crtc_state->has_dp_encoder) |
4a33e48d | 8993 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 8994 | |
a07d6787 | 8995 | /* compute bitmask from p1 value */ |
190f68c5 | 8996 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 8997 | /* also FPA1 */ |
190f68c5 | 8998 | dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 8999 | |
190f68c5 | 9000 | switch (crtc_state->dpll.p2) { |
a07d6787 EA |
9001 | case 5: |
9002 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
9003 | break; | |
9004 | case 7: | |
9005 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
9006 | break; | |
9007 | case 10: | |
9008 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
9009 | break; | |
9010 | case 14: | |
9011 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
9012 | break; | |
79e53945 JB |
9013 | } |
9014 | ||
b4c09f3b | 9015 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 9016 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
9017 | else |
9018 | dpll |= PLL_REF_INPUT_DREFCLK; | |
9019 | ||
959e16d6 | 9020 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
9021 | } |
9022 | ||
190f68c5 ACO |
9023 | static int ironlake_crtc_compute_clock(struct intel_crtc *crtc, |
9024 | struct intel_crtc_state *crtc_state) | |
de13a2e3 | 9025 | { |
c7653199 | 9026 | struct drm_device *dev = crtc->base.dev; |
de13a2e3 | 9027 | intel_clock_t clock, reduced_clock; |
cbbab5bd | 9028 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 9029 | bool ok, has_reduced_clock = false; |
8b47047b | 9030 | bool is_lvds = false; |
e2b78267 | 9031 | struct intel_shared_dpll *pll; |
de13a2e3 | 9032 | |
dd3cd74a ACO |
9033 | memset(&crtc_state->dpll_hw_state, 0, |
9034 | sizeof(crtc_state->dpll_hw_state)); | |
9035 | ||
7905df29 | 9036 | is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS); |
79e53945 | 9037 | |
5dc5298b PZ |
9038 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
9039 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 9040 | |
190f68c5 | 9041 | ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock, |
de13a2e3 | 9042 | &has_reduced_clock, &reduced_clock); |
190f68c5 | 9043 | if (!ok && !crtc_state->clock_set) { |
de13a2e3 PZ |
9044 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
9045 | return -EINVAL; | |
79e53945 | 9046 | } |
f47709a9 | 9047 | /* Compat-code for transition, will disappear. */ |
190f68c5 ACO |
9048 | if (!crtc_state->clock_set) { |
9049 | crtc_state->dpll.n = clock.n; | |
9050 | crtc_state->dpll.m1 = clock.m1; | |
9051 | crtc_state->dpll.m2 = clock.m2; | |
9052 | crtc_state->dpll.p1 = clock.p1; | |
9053 | crtc_state->dpll.p2 = clock.p2; | |
f47709a9 | 9054 | } |
79e53945 | 9055 | |
5dc5298b | 9056 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
190f68c5 ACO |
9057 | if (crtc_state->has_pch_encoder) { |
9058 | fp = i9xx_dpll_compute_fp(&crtc_state->dpll); | |
cbbab5bd | 9059 | if (has_reduced_clock) |
7429e9d4 | 9060 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 9061 | |
190f68c5 | 9062 | dpll = ironlake_compute_dpll(crtc, crtc_state, |
cbbab5bd DV |
9063 | &fp, &reduced_clock, |
9064 | has_reduced_clock ? &fp2 : NULL); | |
9065 | ||
190f68c5 ACO |
9066 | crtc_state->dpll_hw_state.dpll = dpll; |
9067 | crtc_state->dpll_hw_state.fp0 = fp; | |
66e985c0 | 9068 | if (has_reduced_clock) |
190f68c5 | 9069 | crtc_state->dpll_hw_state.fp1 = fp2; |
66e985c0 | 9070 | else |
190f68c5 | 9071 | crtc_state->dpll_hw_state.fp1 = fp; |
66e985c0 | 9072 | |
190f68c5 | 9073 | pll = intel_get_shared_dpll(crtc, crtc_state); |
ee7b9f93 | 9074 | if (pll == NULL) { |
84f44ce7 | 9075 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
c7653199 | 9076 | pipe_name(crtc->pipe)); |
4b645f14 JB |
9077 | return -EINVAL; |
9078 | } | |
3fb37703 | 9079 | } |
79e53945 | 9080 | |
ab585dea | 9081 | if (is_lvds && has_reduced_clock) |
c7653199 | 9082 | crtc->lowfreq_avail = true; |
bcd644e0 | 9083 | else |
c7653199 | 9084 | crtc->lowfreq_avail = false; |
e2b78267 | 9085 | |
c8f7a0db | 9086 | return 0; |
79e53945 JB |
9087 | } |
9088 | ||
eb14cb74 VS |
9089 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
9090 | struct intel_link_m_n *m_n) | |
9091 | { | |
9092 | struct drm_device *dev = crtc->base.dev; | |
9093 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9094 | enum pipe pipe = crtc->pipe; | |
9095 | ||
9096 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
9097 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
9098 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9099 | & ~TU_SIZE_MASK; | |
9100 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
9101 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
9102 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9103 | } | |
9104 | ||
9105 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
9106 | enum transcoder transcoder, | |
b95af8be VK |
9107 | struct intel_link_m_n *m_n, |
9108 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
9109 | { |
9110 | struct drm_device *dev = crtc->base.dev; | |
9111 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 9112 | enum pipe pipe = crtc->pipe; |
72419203 | 9113 | |
eb14cb74 VS |
9114 | if (INTEL_INFO(dev)->gen >= 5) { |
9115 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
9116 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
9117 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
9118 | & ~TU_SIZE_MASK; | |
9119 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
9120 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
9121 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
9122 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
9123 | * gen < 8) and if DRRS is supported (to make sure the | |
9124 | * registers are not unnecessarily read). | |
9125 | */ | |
9126 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
6e3c9717 | 9127 | crtc->config->has_drrs) { |
b95af8be VK |
9128 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); |
9129 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
9130 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
9131 | & ~TU_SIZE_MASK; | |
9132 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
9133 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
9134 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9135 | } | |
eb14cb74 VS |
9136 | } else { |
9137 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
9138 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
9139 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9140 | & ~TU_SIZE_MASK; | |
9141 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
9142 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
9143 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
9144 | } | |
9145 | } | |
9146 | ||
9147 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
5cec258b | 9148 | struct intel_crtc_state *pipe_config) |
eb14cb74 | 9149 | { |
681a8504 | 9150 | if (pipe_config->has_pch_encoder) |
eb14cb74 VS |
9151 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); |
9152 | else | |
9153 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
9154 | &pipe_config->dp_m_n, |
9155 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 9156 | } |
72419203 | 9157 | |
eb14cb74 | 9158 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
5cec258b | 9159 | struct intel_crtc_state *pipe_config) |
eb14cb74 VS |
9160 | { |
9161 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 9162 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
9163 | } |
9164 | ||
bd2e244f | 9165 | static void skylake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9166 | struct intel_crtc_state *pipe_config) |
bd2e244f JB |
9167 | { |
9168 | struct drm_device *dev = crtc->base.dev; | |
9169 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a1b2278e CK |
9170 | struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state; |
9171 | uint32_t ps_ctrl = 0; | |
9172 | int id = -1; | |
9173 | int i; | |
bd2e244f | 9174 | |
a1b2278e CK |
9175 | /* find scaler attached to this pipe */ |
9176 | for (i = 0; i < crtc->num_scalers; i++) { | |
9177 | ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i)); | |
9178 | if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) { | |
9179 | id = i; | |
9180 | pipe_config->pch_pfit.enabled = true; | |
9181 | pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i)); | |
9182 | pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i)); | |
9183 | break; | |
9184 | } | |
9185 | } | |
bd2e244f | 9186 | |
a1b2278e CK |
9187 | scaler_state->scaler_id = id; |
9188 | if (id >= 0) { | |
9189 | scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX); | |
9190 | } else { | |
9191 | scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
bd2e244f JB |
9192 | } |
9193 | } | |
9194 | ||
5724dbd1 DL |
9195 | static void |
9196 | skylake_get_initial_plane_config(struct intel_crtc *crtc, | |
9197 | struct intel_initial_plane_config *plane_config) | |
bc8d7dff DL |
9198 | { |
9199 | struct drm_device *dev = crtc->base.dev; | |
9200 | struct drm_i915_private *dev_priv = dev->dev_private; | |
40f46283 | 9201 | u32 val, base, offset, stride_mult, tiling; |
bc8d7dff DL |
9202 | int pipe = crtc->pipe; |
9203 | int fourcc, pixel_format; | |
6761dd31 | 9204 | unsigned int aligned_height; |
bc8d7dff | 9205 | struct drm_framebuffer *fb; |
1b842c89 | 9206 | struct intel_framebuffer *intel_fb; |
bc8d7dff | 9207 | |
d9806c9f | 9208 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9209 | if (!intel_fb) { |
bc8d7dff DL |
9210 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9211 | return; | |
9212 | } | |
9213 | ||
1b842c89 DL |
9214 | fb = &intel_fb->base; |
9215 | ||
bc8d7dff | 9216 | val = I915_READ(PLANE_CTL(pipe, 0)); |
42a7b088 DL |
9217 | if (!(val & PLANE_CTL_ENABLE)) |
9218 | goto error; | |
9219 | ||
bc8d7dff DL |
9220 | pixel_format = val & PLANE_CTL_FORMAT_MASK; |
9221 | fourcc = skl_format_to_fourcc(pixel_format, | |
9222 | val & PLANE_CTL_ORDER_RGBX, | |
9223 | val & PLANE_CTL_ALPHA_MASK); | |
9224 | fb->pixel_format = fourcc; | |
9225 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
9226 | ||
40f46283 DL |
9227 | tiling = val & PLANE_CTL_TILED_MASK; |
9228 | switch (tiling) { | |
9229 | case PLANE_CTL_TILED_LINEAR: | |
9230 | fb->modifier[0] = DRM_FORMAT_MOD_NONE; | |
9231 | break; | |
9232 | case PLANE_CTL_TILED_X: | |
9233 | plane_config->tiling = I915_TILING_X; | |
9234 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
9235 | break; | |
9236 | case PLANE_CTL_TILED_Y: | |
9237 | fb->modifier[0] = I915_FORMAT_MOD_Y_TILED; | |
9238 | break; | |
9239 | case PLANE_CTL_TILED_YF: | |
9240 | fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED; | |
9241 | break; | |
9242 | default: | |
9243 | MISSING_CASE(tiling); | |
9244 | goto error; | |
9245 | } | |
9246 | ||
bc8d7dff DL |
9247 | base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000; |
9248 | plane_config->base = base; | |
9249 | ||
9250 | offset = I915_READ(PLANE_OFFSET(pipe, 0)); | |
9251 | ||
9252 | val = I915_READ(PLANE_SIZE(pipe, 0)); | |
9253 | fb->height = ((val >> 16) & 0xfff) + 1; | |
9254 | fb->width = ((val >> 0) & 0x1fff) + 1; | |
9255 | ||
9256 | val = I915_READ(PLANE_STRIDE(pipe, 0)); | |
7b49f948 | 9257 | stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
40f46283 | 9258 | fb->pixel_format); |
bc8d7dff DL |
9259 | fb->pitches[0] = (val & 0x3ff) * stride_mult; |
9260 | ||
9261 | aligned_height = intel_fb_align_height(dev, fb->height, | |
091df6cb DV |
9262 | fb->pixel_format, |
9263 | fb->modifier[0]); | |
bc8d7dff | 9264 | |
f37b5c2b | 9265 | plane_config->size = fb->pitches[0] * aligned_height; |
bc8d7dff DL |
9266 | |
9267 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
9268 | pipe_name(pipe), fb->width, fb->height, | |
9269 | fb->bits_per_pixel, base, fb->pitches[0], | |
9270 | plane_config->size); | |
9271 | ||
2d14030b | 9272 | plane_config->fb = intel_fb; |
bc8d7dff DL |
9273 | return; |
9274 | ||
9275 | error: | |
9276 | kfree(fb); | |
9277 | } | |
9278 | ||
2fa2fe9a | 9279 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
5cec258b | 9280 | struct intel_crtc_state *pipe_config) |
2fa2fe9a DV |
9281 | { |
9282 | struct drm_device *dev = crtc->base.dev; | |
9283 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9284 | uint32_t tmp; | |
9285 | ||
9286 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
9287 | ||
9288 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 9289 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
9290 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
9291 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
9292 | |
9293 | /* We currently do not free assignements of panel fitters on | |
9294 | * ivb/hsw (since we don't use the higher upscaling modes which | |
9295 | * differentiates them) so just WARN about this case for now. */ | |
9296 | if (IS_GEN7(dev)) { | |
9297 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
9298 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
9299 | } | |
2fa2fe9a | 9300 | } |
79e53945 JB |
9301 | } |
9302 | ||
5724dbd1 DL |
9303 | static void |
9304 | ironlake_get_initial_plane_config(struct intel_crtc *crtc, | |
9305 | struct intel_initial_plane_config *plane_config) | |
4c6baa59 JB |
9306 | { |
9307 | struct drm_device *dev = crtc->base.dev; | |
9308 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9309 | u32 val, base, offset; | |
aeee5a49 | 9310 | int pipe = crtc->pipe; |
4c6baa59 | 9311 | int fourcc, pixel_format; |
6761dd31 | 9312 | unsigned int aligned_height; |
b113d5ee | 9313 | struct drm_framebuffer *fb; |
1b842c89 | 9314 | struct intel_framebuffer *intel_fb; |
4c6baa59 | 9315 | |
42a7b088 DL |
9316 | val = I915_READ(DSPCNTR(pipe)); |
9317 | if (!(val & DISPLAY_PLANE_ENABLE)) | |
9318 | return; | |
9319 | ||
d9806c9f | 9320 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); |
1b842c89 | 9321 | if (!intel_fb) { |
4c6baa59 JB |
9322 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
9323 | return; | |
9324 | } | |
9325 | ||
1b842c89 DL |
9326 | fb = &intel_fb->base; |
9327 | ||
18c5247e DV |
9328 | if (INTEL_INFO(dev)->gen >= 4) { |
9329 | if (val & DISPPLANE_TILED) { | |
49af449b | 9330 | plane_config->tiling = I915_TILING_X; |
18c5247e DV |
9331 | fb->modifier[0] = I915_FORMAT_MOD_X_TILED; |
9332 | } | |
9333 | } | |
4c6baa59 JB |
9334 | |
9335 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
b35d63fa | 9336 | fourcc = i9xx_format_to_fourcc(pixel_format); |
b113d5ee DL |
9337 | fb->pixel_format = fourcc; |
9338 | fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8; | |
4c6baa59 | 9339 | |
aeee5a49 | 9340 | base = I915_READ(DSPSURF(pipe)) & 0xfffff000; |
4c6baa59 | 9341 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
aeee5a49 | 9342 | offset = I915_READ(DSPOFFSET(pipe)); |
4c6baa59 | 9343 | } else { |
49af449b | 9344 | if (plane_config->tiling) |
aeee5a49 | 9345 | offset = I915_READ(DSPTILEOFF(pipe)); |
4c6baa59 | 9346 | else |
aeee5a49 | 9347 | offset = I915_READ(DSPLINOFF(pipe)); |
4c6baa59 JB |
9348 | } |
9349 | plane_config->base = base; | |
9350 | ||
9351 | val = I915_READ(PIPESRC(pipe)); | |
b113d5ee DL |
9352 | fb->width = ((val >> 16) & 0xfff) + 1; |
9353 | fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
9354 | |
9355 | val = I915_READ(DSPSTRIDE(pipe)); | |
b113d5ee | 9356 | fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 9357 | |
b113d5ee | 9358 | aligned_height = intel_fb_align_height(dev, fb->height, |
091df6cb DV |
9359 | fb->pixel_format, |
9360 | fb->modifier[0]); | |
4c6baa59 | 9361 | |
f37b5c2b | 9362 | plane_config->size = fb->pitches[0] * aligned_height; |
4c6baa59 | 9363 | |
2844a921 DL |
9364 | DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", |
9365 | pipe_name(pipe), fb->width, fb->height, | |
9366 | fb->bits_per_pixel, base, fb->pitches[0], | |
9367 | plane_config->size); | |
b113d5ee | 9368 | |
2d14030b | 9369 | plane_config->fb = intel_fb; |
4c6baa59 JB |
9370 | } |
9371 | ||
0e8ffe1b | 9372 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9373 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9374 | { |
9375 | struct drm_device *dev = crtc->base.dev; | |
9376 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9377 | uint32_t tmp; | |
9378 | ||
f458ebbc DV |
9379 | if (!intel_display_power_is_enabled(dev_priv, |
9380 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
930e8c9e PZ |
9381 | return false; |
9382 | ||
e143a21c | 9383 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 9384 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 9385 | |
0e8ffe1b DV |
9386 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
9387 | if (!(tmp & PIPECONF_ENABLE)) | |
9388 | return false; | |
9389 | ||
42571aef VS |
9390 | switch (tmp & PIPECONF_BPC_MASK) { |
9391 | case PIPECONF_6BPC: | |
9392 | pipe_config->pipe_bpp = 18; | |
9393 | break; | |
9394 | case PIPECONF_8BPC: | |
9395 | pipe_config->pipe_bpp = 24; | |
9396 | break; | |
9397 | case PIPECONF_10BPC: | |
9398 | pipe_config->pipe_bpp = 30; | |
9399 | break; | |
9400 | case PIPECONF_12BPC: | |
9401 | pipe_config->pipe_bpp = 36; | |
9402 | break; | |
9403 | default: | |
9404 | break; | |
9405 | } | |
9406 | ||
b5a9fa09 DV |
9407 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
9408 | pipe_config->limited_color_range = true; | |
9409 | ||
ab9412ba | 9410 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
9411 | struct intel_shared_dpll *pll; |
9412 | ||
88adfff1 DV |
9413 | pipe_config->has_pch_encoder = true; |
9414 | ||
627eb5a3 DV |
9415 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
9416 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9417 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
9418 | |
9419 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 9420 | |
c0d43d62 | 9421 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
9422 | pipe_config->shared_dpll = |
9423 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
9424 | } else { |
9425 | tmp = I915_READ(PCH_DPLL_SEL); | |
9426 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
9427 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
9428 | else | |
9429 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
9430 | } | |
66e985c0 DV |
9431 | |
9432 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9433 | ||
9434 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9435 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
9436 | |
9437 | tmp = pipe_config->dpll_hw_state.dpll; | |
9438 | pipe_config->pixel_multiplier = | |
9439 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
9440 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
9441 | |
9442 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
9443 | } else { |
9444 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
9445 | } |
9446 | ||
1bd1bd80 DV |
9447 | intel_get_pipe_timings(crtc, pipe_config); |
9448 | ||
2fa2fe9a DV |
9449 | ironlake_get_pfit_config(crtc, pipe_config); |
9450 | ||
0e8ffe1b DV |
9451 | return true; |
9452 | } | |
9453 | ||
be256dc7 PZ |
9454 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
9455 | { | |
9456 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 9457 | struct intel_crtc *crtc; |
be256dc7 | 9458 | |
d3fcc808 | 9459 | for_each_intel_crtc(dev, crtc) |
e2c719b7 | 9460 | I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
9461 | pipe_name(crtc->pipe)); |
9462 | ||
e2c719b7 RC |
9463 | I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); |
9464 | I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); | |
01403de3 VS |
9465 | I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); |
9466 | I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
e2c719b7 RC |
9467 | I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
9468 | I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
be256dc7 | 9469 | "CPU PWM1 enabled\n"); |
c5107b87 | 9470 | if (IS_HASWELL(dev)) |
e2c719b7 | 9471 | I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, |
c5107b87 | 9472 | "CPU PWM2 enabled\n"); |
e2c719b7 | 9473 | I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
be256dc7 | 9474 | "PCH PWM1 enabled\n"); |
e2c719b7 | 9475 | I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, |
be256dc7 | 9476 | "Utility pin enabled\n"); |
e2c719b7 | 9477 | I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); |
be256dc7 | 9478 | |
9926ada1 PZ |
9479 | /* |
9480 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
9481 | * interrupts remain enabled. We used to check for that, but since it's | |
9482 | * gen-specific and since we only disable LCPLL after we fully disable | |
9483 | * the interrupts, the check below should be enough. | |
9484 | */ | |
e2c719b7 | 9485 | I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
9486 | } |
9487 | ||
9ccd5aeb PZ |
9488 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
9489 | { | |
9490 | struct drm_device *dev = dev_priv->dev; | |
9491 | ||
9492 | if (IS_HASWELL(dev)) | |
9493 | return I915_READ(D_COMP_HSW); | |
9494 | else | |
9495 | return I915_READ(D_COMP_BDW); | |
9496 | } | |
9497 | ||
3c4c9b81 PZ |
9498 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
9499 | { | |
9500 | struct drm_device *dev = dev_priv->dev; | |
9501 | ||
9502 | if (IS_HASWELL(dev)) { | |
9503 | mutex_lock(&dev_priv->rps.hw_lock); | |
9504 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
9505 | val)) | |
f475dadf | 9506 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
9507 | mutex_unlock(&dev_priv->rps.hw_lock); |
9508 | } else { | |
9ccd5aeb PZ |
9509 | I915_WRITE(D_COMP_BDW, val); |
9510 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 9511 | } |
be256dc7 PZ |
9512 | } |
9513 | ||
9514 | /* | |
9515 | * This function implements pieces of two sequences from BSpec: | |
9516 | * - Sequence for display software to disable LCPLL | |
9517 | * - Sequence for display software to allow package C8+ | |
9518 | * The steps implemented here are just the steps that actually touch the LCPLL | |
9519 | * register. Callers should take care of disabling all the display engine | |
9520 | * functions, doing the mode unset, fixing interrupts, etc. | |
9521 | */ | |
6ff58d53 PZ |
9522 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
9523 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
9524 | { |
9525 | uint32_t val; | |
9526 | ||
9527 | assert_can_disable_lcpll(dev_priv); | |
9528 | ||
9529 | val = I915_READ(LCPLL_CTL); | |
9530 | ||
9531 | if (switch_to_fclk) { | |
9532 | val |= LCPLL_CD_SOURCE_FCLK; | |
9533 | I915_WRITE(LCPLL_CTL, val); | |
9534 | ||
9535 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9536 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9537 | DRM_ERROR("Switching to FCLK failed\n"); | |
9538 | ||
9539 | val = I915_READ(LCPLL_CTL); | |
9540 | } | |
9541 | ||
9542 | val |= LCPLL_PLL_DISABLE; | |
9543 | I915_WRITE(LCPLL_CTL, val); | |
9544 | POSTING_READ(LCPLL_CTL); | |
9545 | ||
9546 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
9547 | DRM_ERROR("LCPLL still locked\n"); | |
9548 | ||
9ccd5aeb | 9549 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 9550 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 9551 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9552 | ndelay(100); |
9553 | ||
9ccd5aeb PZ |
9554 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
9555 | 1)) | |
be256dc7 PZ |
9556 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
9557 | ||
9558 | if (allow_power_down) { | |
9559 | val = I915_READ(LCPLL_CTL); | |
9560 | val |= LCPLL_POWER_DOWN_ALLOW; | |
9561 | I915_WRITE(LCPLL_CTL, val); | |
9562 | POSTING_READ(LCPLL_CTL); | |
9563 | } | |
9564 | } | |
9565 | ||
9566 | /* | |
9567 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
9568 | * source. | |
9569 | */ | |
6ff58d53 | 9570 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
9571 | { |
9572 | uint32_t val; | |
9573 | ||
9574 | val = I915_READ(LCPLL_CTL); | |
9575 | ||
9576 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
9577 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
9578 | return; | |
9579 | ||
a8a8bd54 PZ |
9580 | /* |
9581 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
9582 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
a8a8bd54 | 9583 | */ |
59bad947 | 9584 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
215733fa | 9585 | |
be256dc7 PZ |
9586 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
9587 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
9588 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 9589 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
9590 | } |
9591 | ||
9ccd5aeb | 9592 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
9593 | val |= D_COMP_COMP_FORCE; |
9594 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 9595 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
9596 | |
9597 | val = I915_READ(LCPLL_CTL); | |
9598 | val &= ~LCPLL_PLL_DISABLE; | |
9599 | I915_WRITE(LCPLL_CTL, val); | |
9600 | ||
9601 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
9602 | DRM_ERROR("LCPLL not locked yet\n"); | |
9603 | ||
9604 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
9605 | val = I915_READ(LCPLL_CTL); | |
9606 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9607 | I915_WRITE(LCPLL_CTL, val); | |
9608 | ||
9609 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9610 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9611 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9612 | } | |
215733fa | 9613 | |
59bad947 | 9614 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
b6283055 | 9615 | intel_update_cdclk(dev_priv->dev); |
be256dc7 PZ |
9616 | } |
9617 | ||
765dab67 PZ |
9618 | /* |
9619 | * Package states C8 and deeper are really deep PC states that can only be | |
9620 | * reached when all the devices on the system allow it, so even if the graphics | |
9621 | * device allows PC8+, it doesn't mean the system will actually get to these | |
9622 | * states. Our driver only allows PC8+ when going into runtime PM. | |
9623 | * | |
9624 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
9625 | * well is disabled and most interrupts are disabled, and these are also | |
9626 | * requirements for runtime PM. When these conditions are met, we manually do | |
9627 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
9628 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
9629 | * hang the machine. | |
9630 | * | |
9631 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
9632 | * the state of some registers, so when we come back from PC8+ we need to | |
9633 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
9634 | * need to take care of the registers kept by RC6. Notice that this happens even | |
9635 | * if we don't put the device in PCI D3 state (which is what currently happens | |
9636 | * because of the runtime PM support). | |
9637 | * | |
9638 | * For more, read "Display Sequences for Package C8" on the hardware | |
9639 | * documentation. | |
9640 | */ | |
a14cb6fc | 9641 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 9642 | { |
c67a470b PZ |
9643 | struct drm_device *dev = dev_priv->dev; |
9644 | uint32_t val; | |
9645 | ||
c67a470b PZ |
9646 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
9647 | ||
c2699524 | 9648 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9649 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9650 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
9651 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9652 | } | |
9653 | ||
9654 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
9655 | hsw_disable_lcpll(dev_priv, true, true); |
9656 | } | |
9657 | ||
a14cb6fc | 9658 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
9659 | { |
9660 | struct drm_device *dev = dev_priv->dev; | |
9661 | uint32_t val; | |
9662 | ||
c67a470b PZ |
9663 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
9664 | ||
9665 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
9666 | lpt_init_pch_refclk(dev); |
9667 | ||
c2699524 | 9668 | if (HAS_PCH_LPT_LP(dev)) { |
c67a470b PZ |
9669 | val = I915_READ(SOUTH_DSPCLK_GATE_D); |
9670 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
9671 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
9672 | } | |
c67a470b PZ |
9673 | } |
9674 | ||
27c329ed | 9675 | static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
f8437dd1 | 9676 | { |
a821fc46 | 9677 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9678 | struct intel_atomic_state *old_intel_state = |
9679 | to_intel_atomic_state(old_state); | |
9680 | unsigned int req_cdclk = old_intel_state->dev_cdclk; | |
f8437dd1 | 9681 | |
27c329ed | 9682 | broxton_set_cdclk(dev, req_cdclk); |
f8437dd1 VK |
9683 | } |
9684 | ||
b432e5cf | 9685 | /* compute the max rate for new configuration */ |
27c329ed | 9686 | static int ilk_max_pixel_rate(struct drm_atomic_state *state) |
b432e5cf | 9687 | { |
565602d7 ML |
9688 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
9689 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
9690 | struct drm_crtc *crtc; | |
9691 | struct drm_crtc_state *cstate; | |
27c329ed | 9692 | struct intel_crtc_state *crtc_state; |
565602d7 ML |
9693 | unsigned max_pixel_rate = 0, i; |
9694 | enum pipe pipe; | |
b432e5cf | 9695 | |
565602d7 ML |
9696 | memcpy(intel_state->min_pixclk, dev_priv->min_pixclk, |
9697 | sizeof(intel_state->min_pixclk)); | |
27c329ed | 9698 | |
565602d7 ML |
9699 | for_each_crtc_in_state(state, crtc, cstate, i) { |
9700 | int pixel_rate; | |
27c329ed | 9701 | |
565602d7 ML |
9702 | crtc_state = to_intel_crtc_state(cstate); |
9703 | if (!crtc_state->base.enable) { | |
9704 | intel_state->min_pixclk[i] = 0; | |
b432e5cf | 9705 | continue; |
565602d7 | 9706 | } |
b432e5cf | 9707 | |
27c329ed | 9708 | pixel_rate = ilk_pipe_pixel_rate(crtc_state); |
b432e5cf VS |
9709 | |
9710 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
565602d7 | 9711 | if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled) |
b432e5cf VS |
9712 | pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95); |
9713 | ||
565602d7 | 9714 | intel_state->min_pixclk[i] = pixel_rate; |
b432e5cf VS |
9715 | } |
9716 | ||
565602d7 ML |
9717 | if (!intel_state->active_crtcs) |
9718 | return 0; | |
9719 | ||
9720 | for_each_pipe(dev_priv, pipe) | |
9721 | max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate); | |
9722 | ||
b432e5cf VS |
9723 | return max_pixel_rate; |
9724 | } | |
9725 | ||
9726 | static void broadwell_set_cdclk(struct drm_device *dev, int cdclk) | |
9727 | { | |
9728 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9729 | uint32_t val, data; | |
9730 | int ret; | |
9731 | ||
9732 | if (WARN((I915_READ(LCPLL_CTL) & | |
9733 | (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK | | |
9734 | LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE | | |
9735 | LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW | | |
9736 | LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK, | |
9737 | "trying to change cdclk frequency with cdclk not enabled\n")) | |
9738 | return; | |
9739 | ||
9740 | mutex_lock(&dev_priv->rps.hw_lock); | |
9741 | ret = sandybridge_pcode_write(dev_priv, | |
9742 | BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); | |
9743 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9744 | if (ret) { | |
9745 | DRM_ERROR("failed to inform pcode about cdclk change\n"); | |
9746 | return; | |
9747 | } | |
9748 | ||
9749 | val = I915_READ(LCPLL_CTL); | |
9750 | val |= LCPLL_CD_SOURCE_FCLK; | |
9751 | I915_WRITE(LCPLL_CTL, val); | |
9752 | ||
9753 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
9754 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
9755 | DRM_ERROR("Switching to FCLK failed\n"); | |
9756 | ||
9757 | val = I915_READ(LCPLL_CTL); | |
9758 | val &= ~LCPLL_CLK_FREQ_MASK; | |
9759 | ||
9760 | switch (cdclk) { | |
9761 | case 450000: | |
9762 | val |= LCPLL_CLK_FREQ_450; | |
9763 | data = 0; | |
9764 | break; | |
9765 | case 540000: | |
9766 | val |= LCPLL_CLK_FREQ_54O_BDW; | |
9767 | data = 1; | |
9768 | break; | |
9769 | case 337500: | |
9770 | val |= LCPLL_CLK_FREQ_337_5_BDW; | |
9771 | data = 2; | |
9772 | break; | |
9773 | case 675000: | |
9774 | val |= LCPLL_CLK_FREQ_675_BDW; | |
9775 | data = 3; | |
9776 | break; | |
9777 | default: | |
9778 | WARN(1, "invalid cdclk frequency\n"); | |
9779 | return; | |
9780 | } | |
9781 | ||
9782 | I915_WRITE(LCPLL_CTL, val); | |
9783 | ||
9784 | val = I915_READ(LCPLL_CTL); | |
9785 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
9786 | I915_WRITE(LCPLL_CTL, val); | |
9787 | ||
9788 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
9789 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
9790 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
9791 | ||
9792 | mutex_lock(&dev_priv->rps.hw_lock); | |
9793 | sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data); | |
9794 | mutex_unlock(&dev_priv->rps.hw_lock); | |
9795 | ||
9796 | intel_update_cdclk(dev); | |
9797 | ||
9798 | WARN(cdclk != dev_priv->cdclk_freq, | |
9799 | "cdclk requested %d kHz but got %d kHz\n", | |
9800 | cdclk, dev_priv->cdclk_freq); | |
9801 | } | |
9802 | ||
27c329ed | 9803 | static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state) |
b432e5cf | 9804 | { |
27c329ed | 9805 | struct drm_i915_private *dev_priv = to_i915(state->dev); |
1a617b77 | 9806 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
27c329ed | 9807 | int max_pixclk = ilk_max_pixel_rate(state); |
b432e5cf VS |
9808 | int cdclk; |
9809 | ||
9810 | /* | |
9811 | * FIXME should also account for plane ratio | |
9812 | * once 64bpp pixel formats are supported. | |
9813 | */ | |
27c329ed | 9814 | if (max_pixclk > 540000) |
b432e5cf | 9815 | cdclk = 675000; |
27c329ed | 9816 | else if (max_pixclk > 450000) |
b432e5cf | 9817 | cdclk = 540000; |
27c329ed | 9818 | else if (max_pixclk > 337500) |
b432e5cf VS |
9819 | cdclk = 450000; |
9820 | else | |
9821 | cdclk = 337500; | |
9822 | ||
b432e5cf | 9823 | if (cdclk > dev_priv->max_cdclk_freq) { |
63ba534e ML |
9824 | DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n", |
9825 | cdclk, dev_priv->max_cdclk_freq); | |
9826 | return -EINVAL; | |
b432e5cf VS |
9827 | } |
9828 | ||
1a617b77 ML |
9829 | intel_state->cdclk = intel_state->dev_cdclk = cdclk; |
9830 | if (!intel_state->active_crtcs) | |
9831 | intel_state->dev_cdclk = 337500; | |
b432e5cf VS |
9832 | |
9833 | return 0; | |
9834 | } | |
9835 | ||
27c329ed | 9836 | static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state) |
b432e5cf | 9837 | { |
27c329ed | 9838 | struct drm_device *dev = old_state->dev; |
1a617b77 ML |
9839 | struct intel_atomic_state *old_intel_state = |
9840 | to_intel_atomic_state(old_state); | |
9841 | unsigned req_cdclk = old_intel_state->dev_cdclk; | |
b432e5cf | 9842 | |
27c329ed | 9843 | broadwell_set_cdclk(dev, req_cdclk); |
b432e5cf VS |
9844 | } |
9845 | ||
190f68c5 ACO |
9846 | static int haswell_crtc_compute_clock(struct intel_crtc *crtc, |
9847 | struct intel_crtc_state *crtc_state) | |
09b4ddf9 | 9848 | { |
190f68c5 | 9849 | if (!intel_ddi_pll_select(crtc, crtc_state)) |
6441ab5f | 9850 | return -EINVAL; |
716c2e55 | 9851 | |
c7653199 | 9852 | crtc->lowfreq_avail = false; |
644cef34 | 9853 | |
c8f7a0db | 9854 | return 0; |
79e53945 JB |
9855 | } |
9856 | ||
3760b59c S |
9857 | static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv, |
9858 | enum port port, | |
9859 | struct intel_crtc_state *pipe_config) | |
9860 | { | |
9861 | switch (port) { | |
9862 | case PORT_A: | |
9863 | pipe_config->ddi_pll_sel = SKL_DPLL0; | |
9864 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9865 | break; | |
9866 | case PORT_B: | |
9867 | pipe_config->ddi_pll_sel = SKL_DPLL1; | |
9868 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9869 | break; | |
9870 | case PORT_C: | |
9871 | pipe_config->ddi_pll_sel = SKL_DPLL2; | |
9872 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9873 | break; | |
9874 | default: | |
9875 | DRM_ERROR("Incorrect port type\n"); | |
9876 | } | |
9877 | } | |
9878 | ||
96b7dfb7 S |
9879 | static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv, |
9880 | enum port port, | |
5cec258b | 9881 | struct intel_crtc_state *pipe_config) |
96b7dfb7 | 9882 | { |
3148ade7 | 9883 | u32 temp, dpll_ctl1; |
96b7dfb7 S |
9884 | |
9885 | temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port); | |
9886 | pipe_config->ddi_pll_sel = temp >> (port * 3 + 1); | |
9887 | ||
9888 | switch (pipe_config->ddi_pll_sel) { | |
3148ade7 DL |
9889 | case SKL_DPLL0: |
9890 | /* | |
9891 | * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part | |
9892 | * of the shared DPLL framework and thus needs to be read out | |
9893 | * separately | |
9894 | */ | |
9895 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
9896 | pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f; | |
9897 | break; | |
96b7dfb7 S |
9898 | case SKL_DPLL1: |
9899 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1; | |
9900 | break; | |
9901 | case SKL_DPLL2: | |
9902 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2; | |
9903 | break; | |
9904 | case SKL_DPLL3: | |
9905 | pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3; | |
9906 | break; | |
96b7dfb7 S |
9907 | } |
9908 | } | |
9909 | ||
7d2c8175 DL |
9910 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
9911 | enum port port, | |
5cec258b | 9912 | struct intel_crtc_state *pipe_config) |
7d2c8175 DL |
9913 | { |
9914 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
9915 | ||
9916 | switch (pipe_config->ddi_pll_sel) { | |
9917 | case PORT_CLK_SEL_WRPLL1: | |
9918 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
9919 | break; | |
9920 | case PORT_CLK_SEL_WRPLL2: | |
9921 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
9922 | break; | |
00490c22 ML |
9923 | case PORT_CLK_SEL_SPLL: |
9924 | pipe_config->shared_dpll = DPLL_ID_SPLL; | |
79bd23da | 9925 | break; |
7d2c8175 DL |
9926 | } |
9927 | } | |
9928 | ||
26804afd | 9929 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
5cec258b | 9930 | struct intel_crtc_state *pipe_config) |
26804afd DV |
9931 | { |
9932 | struct drm_device *dev = crtc->base.dev; | |
9933 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 9934 | struct intel_shared_dpll *pll; |
26804afd DV |
9935 | enum port port; |
9936 | uint32_t tmp; | |
9937 | ||
9938 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
9939 | ||
9940 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
9941 | ||
ef11bdb3 | 9942 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
96b7dfb7 | 9943 | skylake_get_ddi_pll(dev_priv, port, pipe_config); |
3760b59c S |
9944 | else if (IS_BROXTON(dev)) |
9945 | bxt_get_ddi_pll(dev_priv, port, pipe_config); | |
96b7dfb7 S |
9946 | else |
9947 | haswell_get_ddi_pll(dev_priv, port, pipe_config); | |
9cd86933 | 9948 | |
d452c5b6 DV |
9949 | if (pipe_config->shared_dpll >= 0) { |
9950 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
9951 | ||
9952 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
9953 | &pipe_config->dpll_hw_state)); | |
9954 | } | |
9955 | ||
26804afd DV |
9956 | /* |
9957 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
9958 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
9959 | * the PCH transcoder is on. | |
9960 | */ | |
ca370455 DL |
9961 | if (INTEL_INFO(dev)->gen < 9 && |
9962 | (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
26804afd DV |
9963 | pipe_config->has_pch_encoder = true; |
9964 | ||
9965 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
9966 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
9967 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
9968 | ||
9969 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
9970 | } | |
9971 | } | |
9972 | ||
0e8ffe1b | 9973 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
5cec258b | 9974 | struct intel_crtc_state *pipe_config) |
0e8ffe1b DV |
9975 | { |
9976 | struct drm_device *dev = crtc->base.dev; | |
9977 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 9978 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
9979 | uint32_t tmp; |
9980 | ||
f458ebbc | 9981 | if (!intel_display_power_is_enabled(dev_priv, |
b5482bd0 ID |
9982 | POWER_DOMAIN_PIPE(crtc->pipe))) |
9983 | return false; | |
9984 | ||
e143a21c | 9985 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
9986 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
9987 | ||
eccb140b DV |
9988 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
9989 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
9990 | enum pipe trans_edp_pipe; | |
9991 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
9992 | default: | |
9993 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
9994 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
9995 | case TRANS_DDI_EDP_INPUT_A_ON: | |
9996 | trans_edp_pipe = PIPE_A; | |
9997 | break; | |
9998 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
9999 | trans_edp_pipe = PIPE_B; | |
10000 | break; | |
10001 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
10002 | trans_edp_pipe = PIPE_C; | |
10003 | break; | |
10004 | } | |
10005 | ||
10006 | if (trans_edp_pipe == crtc->pipe) | |
10007 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
10008 | } | |
10009 | ||
f458ebbc | 10010 | if (!intel_display_power_is_enabled(dev_priv, |
eccb140b | 10011 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
10012 | return false; |
10013 | ||
eccb140b | 10014 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
10015 | if (!(tmp & PIPECONF_ENABLE)) |
10016 | return false; | |
10017 | ||
26804afd | 10018 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 10019 | |
1bd1bd80 DV |
10020 | intel_get_pipe_timings(crtc, pipe_config); |
10021 | ||
a1b2278e CK |
10022 | if (INTEL_INFO(dev)->gen >= 9) { |
10023 | skl_init_scalers(dev, crtc, pipe_config); | |
10024 | } | |
10025 | ||
2fa2fe9a | 10026 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
af99ceda CK |
10027 | |
10028 | if (INTEL_INFO(dev)->gen >= 9) { | |
10029 | pipe_config->scaler_state.scaler_id = -1; | |
10030 | pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX); | |
10031 | } | |
10032 | ||
bd2e244f | 10033 | if (intel_display_power_is_enabled(dev_priv, pfit_domain)) { |
1c132b44 | 10034 | if (INTEL_INFO(dev)->gen >= 9) |
bd2e244f | 10035 | skylake_get_pfit_config(crtc, pipe_config); |
ff6d9f55 | 10036 | else |
1c132b44 | 10037 | ironlake_get_pfit_config(crtc, pipe_config); |
bd2e244f | 10038 | } |
88adfff1 | 10039 | |
e59150dc JB |
10040 | if (IS_HASWELL(dev)) |
10041 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
10042 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 10043 | |
ebb69c95 CT |
10044 | if (pipe_config->cpu_transcoder != TRANSCODER_EDP) { |
10045 | pipe_config->pixel_multiplier = | |
10046 | I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1; | |
10047 | } else { | |
10048 | pipe_config->pixel_multiplier = 1; | |
10049 | } | |
6c49f241 | 10050 | |
0e8ffe1b DV |
10051 | return true; |
10052 | } | |
10053 | ||
55a08b3f ML |
10054 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base, |
10055 | const struct intel_plane_state *plane_state) | |
560b85bb CW |
10056 | { |
10057 | struct drm_device *dev = crtc->dev; | |
10058 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10059 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 10060 | uint32_t cntl = 0, size = 0; |
560b85bb | 10061 | |
55a08b3f ML |
10062 | if (plane_state && plane_state->visible) { |
10063 | unsigned int width = plane_state->base.crtc_w; | |
10064 | unsigned int height = plane_state->base.crtc_h; | |
dc41c154 VS |
10065 | unsigned int stride = roundup_pow_of_two(width) * 4; |
10066 | ||
10067 | switch (stride) { | |
10068 | default: | |
10069 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
10070 | width, stride); | |
10071 | stride = 256; | |
10072 | /* fallthrough */ | |
10073 | case 256: | |
10074 | case 512: | |
10075 | case 1024: | |
10076 | case 2048: | |
10077 | break; | |
4b0e333e CW |
10078 | } |
10079 | ||
dc41c154 VS |
10080 | cntl |= CURSOR_ENABLE | |
10081 | CURSOR_GAMMA_ENABLE | | |
10082 | CURSOR_FORMAT_ARGB | | |
10083 | CURSOR_STRIDE(stride); | |
10084 | ||
10085 | size = (height << 12) | width; | |
4b0e333e | 10086 | } |
560b85bb | 10087 | |
dc41c154 VS |
10088 | if (intel_crtc->cursor_cntl != 0 && |
10089 | (intel_crtc->cursor_base != base || | |
10090 | intel_crtc->cursor_size != size || | |
10091 | intel_crtc->cursor_cntl != cntl)) { | |
10092 | /* On these chipsets we can only modify the base/size/stride | |
10093 | * whilst the cursor is disabled. | |
10094 | */ | |
0b87c24e VS |
10095 | I915_WRITE(CURCNTR(PIPE_A), 0); |
10096 | POSTING_READ(CURCNTR(PIPE_A)); | |
dc41c154 | 10097 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 10098 | } |
560b85bb | 10099 | |
99d1f387 | 10100 | if (intel_crtc->cursor_base != base) { |
0b87c24e | 10101 | I915_WRITE(CURBASE(PIPE_A), base); |
99d1f387 VS |
10102 | intel_crtc->cursor_base = base; |
10103 | } | |
4726e0b0 | 10104 | |
dc41c154 VS |
10105 | if (intel_crtc->cursor_size != size) { |
10106 | I915_WRITE(CURSIZE, size); | |
10107 | intel_crtc->cursor_size = size; | |
4b0e333e | 10108 | } |
560b85bb | 10109 | |
4b0e333e | 10110 | if (intel_crtc->cursor_cntl != cntl) { |
0b87c24e VS |
10111 | I915_WRITE(CURCNTR(PIPE_A), cntl); |
10112 | POSTING_READ(CURCNTR(PIPE_A)); | |
4b0e333e | 10113 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 10114 | } |
560b85bb CW |
10115 | } |
10116 | ||
55a08b3f ML |
10117 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base, |
10118 | const struct intel_plane_state *plane_state) | |
65a21cd6 JB |
10119 | { |
10120 | struct drm_device *dev = crtc->dev; | |
10121 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10122 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10123 | int pipe = intel_crtc->pipe; | |
663f3122 | 10124 | uint32_t cntl = 0; |
4b0e333e | 10125 | |
55a08b3f | 10126 | if (plane_state && plane_state->visible) { |
4b0e333e | 10127 | cntl = MCURSOR_GAMMA_ENABLE; |
55a08b3f | 10128 | switch (plane_state->base.crtc_w) { |
4726e0b0 SK |
10129 | case 64: |
10130 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
10131 | break; | |
10132 | case 128: | |
10133 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
10134 | break; | |
10135 | case 256: | |
10136 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
10137 | break; | |
10138 | default: | |
55a08b3f | 10139 | MISSING_CASE(plane_state->base.crtc_w); |
4726e0b0 | 10140 | return; |
65a21cd6 | 10141 | } |
4b0e333e | 10142 | cntl |= pipe << 28; /* Connect to correct pipe */ |
47bf17a7 | 10143 | |
fc6f93bc | 10144 | if (HAS_DDI(dev)) |
47bf17a7 | 10145 | cntl |= CURSOR_PIPE_CSC_ENABLE; |
65a21cd6 | 10146 | |
55a08b3f ML |
10147 | if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) |
10148 | cntl |= CURSOR_ROTATE_180; | |
10149 | } | |
4398ad45 | 10150 | |
4b0e333e CW |
10151 | if (intel_crtc->cursor_cntl != cntl) { |
10152 | I915_WRITE(CURCNTR(pipe), cntl); | |
10153 | POSTING_READ(CURCNTR(pipe)); | |
10154 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 10155 | } |
4b0e333e | 10156 | |
65a21cd6 | 10157 | /* and commit changes on next vblank */ |
5efb3e28 VS |
10158 | I915_WRITE(CURBASE(pipe), base); |
10159 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
10160 | |
10161 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
10162 | } |
10163 | ||
cda4b7d3 | 10164 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f | 10165 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
55a08b3f | 10166 | const struct intel_plane_state *plane_state) |
cda4b7d3 CW |
10167 | { |
10168 | struct drm_device *dev = crtc->dev; | |
10169 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10170 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
10171 | int pipe = intel_crtc->pipe; | |
55a08b3f ML |
10172 | u32 base = intel_crtc->cursor_addr; |
10173 | u32 pos = 0; | |
cda4b7d3 | 10174 | |
55a08b3f ML |
10175 | if (plane_state) { |
10176 | int x = plane_state->base.crtc_x; | |
10177 | int y = plane_state->base.crtc_y; | |
cda4b7d3 | 10178 | |
55a08b3f ML |
10179 | if (x < 0) { |
10180 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
10181 | x = -x; | |
10182 | } | |
10183 | pos |= x << CURSOR_X_SHIFT; | |
cda4b7d3 | 10184 | |
55a08b3f ML |
10185 | if (y < 0) { |
10186 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
10187 | y = -y; | |
10188 | } | |
10189 | pos |= y << CURSOR_Y_SHIFT; | |
10190 | ||
10191 | /* ILK+ do this automagically */ | |
10192 | if (HAS_GMCH_DISPLAY(dev) && | |
10193 | plane_state->base.rotation == BIT(DRM_ROTATE_180)) { | |
10194 | base += (plane_state->base.crtc_h * | |
10195 | plane_state->base.crtc_w - 1) * 4; | |
10196 | } | |
cda4b7d3 | 10197 | } |
cda4b7d3 | 10198 | |
5efb3e28 VS |
10199 | I915_WRITE(CURPOS(pipe), pos); |
10200 | ||
8ac54669 | 10201 | if (IS_845G(dev) || IS_I865G(dev)) |
55a08b3f | 10202 | i845_update_cursor(crtc, base, plane_state); |
5efb3e28 | 10203 | else |
55a08b3f | 10204 | i9xx_update_cursor(crtc, base, plane_state); |
cda4b7d3 CW |
10205 | } |
10206 | ||
dc41c154 VS |
10207 | static bool cursor_size_ok(struct drm_device *dev, |
10208 | uint32_t width, uint32_t height) | |
10209 | { | |
10210 | if (width == 0 || height == 0) | |
10211 | return false; | |
10212 | ||
10213 | /* | |
10214 | * 845g/865g are special in that they are only limited by | |
10215 | * the width of their cursors, the height is arbitrary up to | |
10216 | * the precision of the register. Everything else requires | |
10217 | * square cursors, limited to a few power-of-two sizes. | |
10218 | */ | |
10219 | if (IS_845G(dev) || IS_I865G(dev)) { | |
10220 | if ((width & 63) != 0) | |
10221 | return false; | |
10222 | ||
10223 | if (width > (IS_845G(dev) ? 64 : 512)) | |
10224 | return false; | |
10225 | ||
10226 | if (height > 1023) | |
10227 | return false; | |
10228 | } else { | |
10229 | switch (width | height) { | |
10230 | case 256: | |
10231 | case 128: | |
10232 | if (IS_GEN2(dev)) | |
10233 | return false; | |
10234 | case 64: | |
10235 | break; | |
10236 | default: | |
10237 | return false; | |
10238 | } | |
10239 | } | |
10240 | ||
10241 | return true; | |
10242 | } | |
10243 | ||
79e53945 | 10244 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 10245 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 10246 | { |
7203425a | 10247 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 10248 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 10249 | |
7203425a | 10250 | for (i = start; i < end; i++) { |
79e53945 JB |
10251 | intel_crtc->lut_r[i] = red[i] >> 8; |
10252 | intel_crtc->lut_g[i] = green[i] >> 8; | |
10253 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
10254 | } | |
10255 | ||
10256 | intel_crtc_load_lut(crtc); | |
10257 | } | |
10258 | ||
79e53945 JB |
10259 | /* VESA 640x480x72Hz mode to set on the pipe */ |
10260 | static struct drm_display_mode load_detect_mode = { | |
10261 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
10262 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
10263 | }; | |
10264 | ||
a8bb6818 DV |
10265 | struct drm_framebuffer * |
10266 | __intel_framebuffer_create(struct drm_device *dev, | |
10267 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10268 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
10269 | { |
10270 | struct intel_framebuffer *intel_fb; | |
10271 | int ret; | |
10272 | ||
10273 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
dcb1394e | 10274 | if (!intel_fb) |
d2dff872 | 10275 | return ERR_PTR(-ENOMEM); |
d2dff872 CW |
10276 | |
10277 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
10278 | if (ret) |
10279 | goto err; | |
d2dff872 CW |
10280 | |
10281 | return &intel_fb->base; | |
dcb1394e | 10282 | |
dd4916c5 | 10283 | err: |
dd4916c5 | 10284 | kfree(intel_fb); |
dd4916c5 | 10285 | return ERR_PTR(ret); |
d2dff872 CW |
10286 | } |
10287 | ||
b5ea642a | 10288 | static struct drm_framebuffer * |
a8bb6818 DV |
10289 | intel_framebuffer_create(struct drm_device *dev, |
10290 | struct drm_mode_fb_cmd2 *mode_cmd, | |
10291 | struct drm_i915_gem_object *obj) | |
10292 | { | |
10293 | struct drm_framebuffer *fb; | |
10294 | int ret; | |
10295 | ||
10296 | ret = i915_mutex_lock_interruptible(dev); | |
10297 | if (ret) | |
10298 | return ERR_PTR(ret); | |
10299 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
10300 | mutex_unlock(&dev->struct_mutex); | |
10301 | ||
10302 | return fb; | |
10303 | } | |
10304 | ||
d2dff872 CW |
10305 | static u32 |
10306 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
10307 | { | |
10308 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
10309 | return ALIGN(pitch, 64); | |
10310 | } | |
10311 | ||
10312 | static u32 | |
10313 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
10314 | { | |
10315 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 10316 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
10317 | } |
10318 | ||
10319 | static struct drm_framebuffer * | |
10320 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
10321 | struct drm_display_mode *mode, | |
10322 | int depth, int bpp) | |
10323 | { | |
dcb1394e | 10324 | struct drm_framebuffer *fb; |
d2dff872 | 10325 | struct drm_i915_gem_object *obj; |
0fed39bd | 10326 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
10327 | |
10328 | obj = i915_gem_alloc_object(dev, | |
10329 | intel_framebuffer_size_for_mode(mode, bpp)); | |
10330 | if (obj == NULL) | |
10331 | return ERR_PTR(-ENOMEM); | |
10332 | ||
10333 | mode_cmd.width = mode->hdisplay; | |
10334 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
10335 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
10336 | bpp); | |
5ca0c34a | 10337 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 | 10338 | |
dcb1394e LW |
10339 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
10340 | if (IS_ERR(fb)) | |
10341 | drm_gem_object_unreference_unlocked(&obj->base); | |
10342 | ||
10343 | return fb; | |
d2dff872 CW |
10344 | } |
10345 | ||
10346 | static struct drm_framebuffer * | |
10347 | mode_fits_in_fbdev(struct drm_device *dev, | |
10348 | struct drm_display_mode *mode) | |
10349 | { | |
0695726e | 10350 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
d2dff872 CW |
10351 | struct drm_i915_private *dev_priv = dev->dev_private; |
10352 | struct drm_i915_gem_object *obj; | |
10353 | struct drm_framebuffer *fb; | |
10354 | ||
4c0e5528 | 10355 | if (!dev_priv->fbdev) |
d2dff872 CW |
10356 | return NULL; |
10357 | ||
4c0e5528 | 10358 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
10359 | return NULL; |
10360 | ||
4c0e5528 DV |
10361 | obj = dev_priv->fbdev->fb->obj; |
10362 | BUG_ON(!obj); | |
10363 | ||
8bcd4553 | 10364 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
10365 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
10366 | fb->bits_per_pixel)) | |
d2dff872 CW |
10367 | return NULL; |
10368 | ||
01f2c773 | 10369 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
10370 | return NULL; |
10371 | ||
10372 | return fb; | |
4520f53a DV |
10373 | #else |
10374 | return NULL; | |
10375 | #endif | |
d2dff872 CW |
10376 | } |
10377 | ||
d3a40d1b ACO |
10378 | static int intel_modeset_setup_plane_state(struct drm_atomic_state *state, |
10379 | struct drm_crtc *crtc, | |
10380 | struct drm_display_mode *mode, | |
10381 | struct drm_framebuffer *fb, | |
10382 | int x, int y) | |
10383 | { | |
10384 | struct drm_plane_state *plane_state; | |
10385 | int hdisplay, vdisplay; | |
10386 | int ret; | |
10387 | ||
10388 | plane_state = drm_atomic_get_plane_state(state, crtc->primary); | |
10389 | if (IS_ERR(plane_state)) | |
10390 | return PTR_ERR(plane_state); | |
10391 | ||
10392 | if (mode) | |
10393 | drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay); | |
10394 | else | |
10395 | hdisplay = vdisplay = 0; | |
10396 | ||
10397 | ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL); | |
10398 | if (ret) | |
10399 | return ret; | |
10400 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
10401 | plane_state->crtc_x = 0; | |
10402 | plane_state->crtc_y = 0; | |
10403 | plane_state->crtc_w = hdisplay; | |
10404 | plane_state->crtc_h = vdisplay; | |
10405 | plane_state->src_x = x << 16; | |
10406 | plane_state->src_y = y << 16; | |
10407 | plane_state->src_w = hdisplay << 16; | |
10408 | plane_state->src_h = vdisplay << 16; | |
10409 | ||
10410 | return 0; | |
10411 | } | |
10412 | ||
d2434ab7 | 10413 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 10414 | struct drm_display_mode *mode, |
51fd371b RC |
10415 | struct intel_load_detect_pipe *old, |
10416 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
10417 | { |
10418 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
10419 | struct intel_encoder *intel_encoder = |
10420 | intel_attached_encoder(connector); | |
79e53945 | 10421 | struct drm_crtc *possible_crtc; |
4ef69c7a | 10422 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
10423 | struct drm_crtc *crtc = NULL; |
10424 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 10425 | struct drm_framebuffer *fb; |
51fd371b | 10426 | struct drm_mode_config *config = &dev->mode_config; |
83a57153 | 10427 | struct drm_atomic_state *state = NULL; |
944b0c76 | 10428 | struct drm_connector_state *connector_state; |
4be07317 | 10429 | struct intel_crtc_state *crtc_state; |
51fd371b | 10430 | int ret, i = -1; |
79e53945 | 10431 | |
d2dff872 | 10432 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10433 | connector->base.id, connector->name, |
8e329a03 | 10434 | encoder->base.id, encoder->name); |
d2dff872 | 10435 | |
51fd371b RC |
10436 | retry: |
10437 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
10438 | if (ret) | |
ad3c558f | 10439 | goto fail; |
6e9f798d | 10440 | |
79e53945 JB |
10441 | /* |
10442 | * Algorithm gets a little messy: | |
7a5e4805 | 10443 | * |
79e53945 JB |
10444 | * - if the connector already has an assigned crtc, use it (but make |
10445 | * sure it's on first) | |
7a5e4805 | 10446 | * |
79e53945 JB |
10447 | * - try to find the first unused crtc that can drive this connector, |
10448 | * and use that if we find one | |
79e53945 JB |
10449 | */ |
10450 | ||
10451 | /* See if we already have a CRTC for this connector */ | |
10452 | if (encoder->crtc) { | |
10453 | crtc = encoder->crtc; | |
8261b191 | 10454 | |
51fd371b | 10455 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
4d02e2de | 10456 | if (ret) |
ad3c558f | 10457 | goto fail; |
4d02e2de | 10458 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
51fd371b | 10459 | if (ret) |
ad3c558f | 10460 | goto fail; |
7b24056b | 10461 | |
24218aac | 10462 | old->dpms_mode = connector->dpms; |
8261b191 CW |
10463 | old->load_detect_temp = false; |
10464 | ||
10465 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
10466 | if (connector->dpms != DRM_MODE_DPMS_ON) |
10467 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 10468 | |
7173188d | 10469 | return true; |
79e53945 JB |
10470 | } |
10471 | ||
10472 | /* Find an unused one (if possible) */ | |
70e1e0ec | 10473 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
10474 | i++; |
10475 | if (!(encoder->possible_crtcs & (1 << i))) | |
10476 | continue; | |
83d65738 | 10477 | if (possible_crtc->state->enable) |
a459249c | 10478 | continue; |
a459249c VS |
10479 | |
10480 | crtc = possible_crtc; | |
10481 | break; | |
79e53945 JB |
10482 | } |
10483 | ||
10484 | /* | |
10485 | * If we didn't find an unused CRTC, don't use any. | |
10486 | */ | |
10487 | if (!crtc) { | |
7173188d | 10488 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
ad3c558f | 10489 | goto fail; |
79e53945 JB |
10490 | } |
10491 | ||
51fd371b RC |
10492 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
10493 | if (ret) | |
ad3c558f | 10494 | goto fail; |
4d02e2de DV |
10495 | ret = drm_modeset_lock(&crtc->primary->mutex, ctx); |
10496 | if (ret) | |
ad3c558f | 10497 | goto fail; |
79e53945 JB |
10498 | |
10499 | intel_crtc = to_intel_crtc(crtc); | |
24218aac | 10500 | old->dpms_mode = connector->dpms; |
8261b191 | 10501 | old->load_detect_temp = true; |
d2dff872 | 10502 | old->release_fb = NULL; |
79e53945 | 10503 | |
83a57153 ACO |
10504 | state = drm_atomic_state_alloc(dev); |
10505 | if (!state) | |
10506 | return false; | |
10507 | ||
10508 | state->acquire_ctx = ctx; | |
10509 | ||
944b0c76 ACO |
10510 | connector_state = drm_atomic_get_connector_state(state, connector); |
10511 | if (IS_ERR(connector_state)) { | |
10512 | ret = PTR_ERR(connector_state); | |
10513 | goto fail; | |
10514 | } | |
10515 | ||
10516 | connector_state->crtc = crtc; | |
10517 | connector_state->best_encoder = &intel_encoder->base; | |
10518 | ||
4be07317 ACO |
10519 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10520 | if (IS_ERR(crtc_state)) { | |
10521 | ret = PTR_ERR(crtc_state); | |
10522 | goto fail; | |
10523 | } | |
10524 | ||
49d6fa21 | 10525 | crtc_state->base.active = crtc_state->base.enable = true; |
4be07317 | 10526 | |
6492711d CW |
10527 | if (!mode) |
10528 | mode = &load_detect_mode; | |
79e53945 | 10529 | |
d2dff872 CW |
10530 | /* We need a framebuffer large enough to accommodate all accesses |
10531 | * that the plane may generate whilst we perform load detection. | |
10532 | * We can not rely on the fbcon either being present (we get called | |
10533 | * during its initialisation to detect all boot displays, or it may | |
10534 | * not even exist) or that it is large enough to satisfy the | |
10535 | * requested mode. | |
10536 | */ | |
94352cf9 DV |
10537 | fb = mode_fits_in_fbdev(dev, mode); |
10538 | if (fb == NULL) { | |
d2dff872 | 10539 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
10540 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
10541 | old->release_fb = fb; | |
d2dff872 CW |
10542 | } else |
10543 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 10544 | if (IS_ERR(fb)) { |
d2dff872 | 10545 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 10546 | goto fail; |
79e53945 | 10547 | } |
79e53945 | 10548 | |
d3a40d1b ACO |
10549 | ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0); |
10550 | if (ret) | |
10551 | goto fail; | |
10552 | ||
8c7b5ccb ACO |
10553 | drm_mode_copy(&crtc_state->base.mode, mode); |
10554 | ||
74c090b1 | 10555 | if (drm_atomic_commit(state)) { |
6492711d | 10556 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
10557 | if (old->release_fb) |
10558 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 10559 | goto fail; |
79e53945 | 10560 | } |
9128b040 | 10561 | crtc->primary->crtc = crtc; |
7173188d | 10562 | |
79e53945 | 10563 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 10564 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 10565 | return true; |
412b61d8 | 10566 | |
ad3c558f | 10567 | fail: |
e5d958ef ACO |
10568 | drm_atomic_state_free(state); |
10569 | state = NULL; | |
83a57153 | 10570 | |
51fd371b RC |
10571 | if (ret == -EDEADLK) { |
10572 | drm_modeset_backoff(ctx); | |
10573 | goto retry; | |
10574 | } | |
10575 | ||
412b61d8 | 10576 | return false; |
79e53945 JB |
10577 | } |
10578 | ||
d2434ab7 | 10579 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
49172fee ACO |
10580 | struct intel_load_detect_pipe *old, |
10581 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 | 10582 | { |
83a57153 | 10583 | struct drm_device *dev = connector->dev; |
d2434ab7 DV |
10584 | struct intel_encoder *intel_encoder = |
10585 | intel_attached_encoder(connector); | |
4ef69c7a | 10586 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 10587 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 10588 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
83a57153 | 10589 | struct drm_atomic_state *state; |
944b0c76 | 10590 | struct drm_connector_state *connector_state; |
4be07317 | 10591 | struct intel_crtc_state *crtc_state; |
d3a40d1b | 10592 | int ret; |
79e53945 | 10593 | |
d2dff872 | 10594 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 10595 | connector->base.id, connector->name, |
8e329a03 | 10596 | encoder->base.id, encoder->name); |
d2dff872 | 10597 | |
8261b191 | 10598 | if (old->load_detect_temp) { |
83a57153 | 10599 | state = drm_atomic_state_alloc(dev); |
944b0c76 ACO |
10600 | if (!state) |
10601 | goto fail; | |
83a57153 ACO |
10602 | |
10603 | state->acquire_ctx = ctx; | |
10604 | ||
944b0c76 ACO |
10605 | connector_state = drm_atomic_get_connector_state(state, connector); |
10606 | if (IS_ERR(connector_state)) | |
10607 | goto fail; | |
10608 | ||
4be07317 ACO |
10609 | crtc_state = intel_atomic_get_crtc_state(state, intel_crtc); |
10610 | if (IS_ERR(crtc_state)) | |
10611 | goto fail; | |
10612 | ||
944b0c76 ACO |
10613 | connector_state->best_encoder = NULL; |
10614 | connector_state->crtc = NULL; | |
10615 | ||
49d6fa21 | 10616 | crtc_state->base.enable = crtc_state->base.active = false; |
4be07317 | 10617 | |
d3a40d1b ACO |
10618 | ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL, |
10619 | 0, 0); | |
10620 | if (ret) | |
10621 | goto fail; | |
10622 | ||
74c090b1 | 10623 | ret = drm_atomic_commit(state); |
2bfb4627 ACO |
10624 | if (ret) |
10625 | goto fail; | |
d2dff872 | 10626 | |
36206361 DV |
10627 | if (old->release_fb) { |
10628 | drm_framebuffer_unregister_private(old->release_fb); | |
10629 | drm_framebuffer_unreference(old->release_fb); | |
10630 | } | |
d2dff872 | 10631 | |
0622a53c | 10632 | return; |
79e53945 JB |
10633 | } |
10634 | ||
c751ce4f | 10635 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
10636 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
10637 | connector->funcs->dpms(connector, old->dpms_mode); | |
944b0c76 ACO |
10638 | |
10639 | return; | |
10640 | fail: | |
10641 | DRM_DEBUG_KMS("Couldn't release load detect pipe.\n"); | |
10642 | drm_atomic_state_free(state); | |
79e53945 JB |
10643 | } |
10644 | ||
da4a1efa | 10645 | static int i9xx_pll_refclk(struct drm_device *dev, |
5cec258b | 10646 | const struct intel_crtc_state *pipe_config) |
da4a1efa VS |
10647 | { |
10648 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10649 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
10650 | ||
10651 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 10652 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
10653 | else if (HAS_PCH_SPLIT(dev)) |
10654 | return 120000; | |
10655 | else if (!IS_GEN2(dev)) | |
10656 | return 96000; | |
10657 | else | |
10658 | return 48000; | |
10659 | } | |
10660 | ||
79e53945 | 10661 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc | 10662 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
5cec258b | 10663 | struct intel_crtc_state *pipe_config) |
79e53945 | 10664 | { |
f1f644dc | 10665 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 10666 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 10667 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 10668 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
10669 | u32 fp; |
10670 | intel_clock_t clock; | |
dccbea3b | 10671 | int port_clock; |
da4a1efa | 10672 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
10673 | |
10674 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 10675 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 10676 | else |
293623f7 | 10677 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
10678 | |
10679 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
10680 | if (IS_PINEVIEW(dev)) { |
10681 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
10682 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
10683 | } else { |
10684 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
10685 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
10686 | } | |
10687 | ||
a6c45cf0 | 10688 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
10689 | if (IS_PINEVIEW(dev)) |
10690 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
10691 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
10692 | else |
10693 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
10694 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
10695 | ||
10696 | switch (dpll & DPLL_MODE_MASK) { | |
10697 | case DPLLB_MODE_DAC_SERIAL: | |
10698 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
10699 | 5 : 10; | |
10700 | break; | |
10701 | case DPLLB_MODE_LVDS: | |
10702 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
10703 | 7 : 14; | |
10704 | break; | |
10705 | default: | |
28c97730 | 10706 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 10707 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 10708 | return; |
79e53945 JB |
10709 | } |
10710 | ||
ac58c3f0 | 10711 | if (IS_PINEVIEW(dev)) |
dccbea3b | 10712 | port_clock = pnv_calc_dpll_params(refclk, &clock); |
ac58c3f0 | 10713 | else |
dccbea3b | 10714 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 | 10715 | } else { |
0fb58223 | 10716 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 10717 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
10718 | |
10719 | if (is_lvds) { | |
10720 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
10721 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
10722 | |
10723 | if (lvds & LVDS_CLKB_POWER_UP) | |
10724 | clock.p2 = 7; | |
10725 | else | |
10726 | clock.p2 = 14; | |
79e53945 JB |
10727 | } else { |
10728 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
10729 | clock.p1 = 2; | |
10730 | else { | |
10731 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
10732 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
10733 | } | |
10734 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
10735 | clock.p2 = 4; | |
10736 | else | |
10737 | clock.p2 = 2; | |
79e53945 | 10738 | } |
da4a1efa | 10739 | |
dccbea3b | 10740 | port_clock = i9xx_calc_dpll_params(refclk, &clock); |
79e53945 JB |
10741 | } |
10742 | ||
18442d08 VS |
10743 | /* |
10744 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 10745 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
10746 | * encoder's get_config() function. |
10747 | */ | |
dccbea3b | 10748 | pipe_config->port_clock = port_clock; |
f1f644dc JB |
10749 | } |
10750 | ||
6878da05 VS |
10751 | int intel_dotclock_calculate(int link_freq, |
10752 | const struct intel_link_m_n *m_n) | |
f1f644dc | 10753 | { |
f1f644dc JB |
10754 | /* |
10755 | * The calculation for the data clock is: | |
1041a02f | 10756 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 10757 | * But we want to avoid losing precison if possible, so: |
1041a02f | 10758 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
10759 | * |
10760 | * and the link clock is simpler: | |
1041a02f | 10761 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
10762 | */ |
10763 | ||
6878da05 VS |
10764 | if (!m_n->link_n) |
10765 | return 0; | |
f1f644dc | 10766 | |
6878da05 VS |
10767 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
10768 | } | |
f1f644dc | 10769 | |
18442d08 | 10770 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
5cec258b | 10771 | struct intel_crtc_state *pipe_config) |
6878da05 VS |
10772 | { |
10773 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 10774 | |
18442d08 VS |
10775 | /* read out port_clock from the DPLL */ |
10776 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 10777 | |
f1f644dc | 10778 | /* |
18442d08 | 10779 | * This value does not include pixel_multiplier. |
241bfc38 | 10780 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
10781 | * agree once we know their relationship in the encoder's |
10782 | * get_config() function. | |
79e53945 | 10783 | */ |
2d112de7 | 10784 | pipe_config->base.adjusted_mode.crtc_clock = |
18442d08 VS |
10785 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
10786 | &pipe_config->fdi_m_n); | |
79e53945 JB |
10787 | } |
10788 | ||
10789 | /** Returns the currently programmed mode of the given pipe. */ | |
10790 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
10791 | struct drm_crtc *crtc) | |
10792 | { | |
548f245b | 10793 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 10794 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 10795 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
79e53945 | 10796 | struct drm_display_mode *mode; |
3f36b937 | 10797 | struct intel_crtc_state *pipe_config; |
fe2b8f9d PZ |
10798 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
10799 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
10800 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
10801 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 10802 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
10803 | |
10804 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
10805 | if (!mode) | |
10806 | return NULL; | |
10807 | ||
3f36b937 TU |
10808 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
10809 | if (!pipe_config) { | |
10810 | kfree(mode); | |
10811 | return NULL; | |
10812 | } | |
10813 | ||
f1f644dc JB |
10814 | /* |
10815 | * Construct a pipe_config sufficient for getting the clock info | |
10816 | * back out of crtc_clock_get. | |
10817 | * | |
10818 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
10819 | * to use a real value here instead. | |
10820 | */ | |
3f36b937 TU |
10821 | pipe_config->cpu_transcoder = (enum transcoder) pipe; |
10822 | pipe_config->pixel_multiplier = 1; | |
10823 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe)); | |
10824 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
10825 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
10826 | i9xx_crtc_clock_get(intel_crtc, pipe_config); | |
10827 | ||
10828 | mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier; | |
79e53945 JB |
10829 | mode->hdisplay = (htot & 0xffff) + 1; |
10830 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
10831 | mode->hsync_start = (hsync & 0xffff) + 1; | |
10832 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
10833 | mode->vdisplay = (vtot & 0xffff) + 1; | |
10834 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
10835 | mode->vsync_start = (vsync & 0xffff) + 1; | |
10836 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
10837 | ||
10838 | drm_mode_set_name(mode); | |
79e53945 | 10839 | |
3f36b937 TU |
10840 | kfree(pipe_config); |
10841 | ||
79e53945 JB |
10842 | return mode; |
10843 | } | |
10844 | ||
f047e395 CW |
10845 | void intel_mark_busy(struct drm_device *dev) |
10846 | { | |
c67a470b PZ |
10847 | struct drm_i915_private *dev_priv = dev->dev_private; |
10848 | ||
f62a0076 CW |
10849 | if (dev_priv->mm.busy) |
10850 | return; | |
10851 | ||
43694d69 | 10852 | intel_runtime_pm_get(dev_priv); |
c67a470b | 10853 | i915_update_gfx_val(dev_priv); |
43cf3bf0 CW |
10854 | if (INTEL_INFO(dev)->gen >= 6) |
10855 | gen6_rps_busy(dev_priv); | |
f62a0076 | 10856 | dev_priv->mm.busy = true; |
f047e395 CW |
10857 | } |
10858 | ||
10859 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 10860 | { |
c67a470b | 10861 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 10862 | |
f62a0076 CW |
10863 | if (!dev_priv->mm.busy) |
10864 | return; | |
10865 | ||
10866 | dev_priv->mm.busy = false; | |
10867 | ||
3d13ef2e | 10868 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 10869 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 | 10870 | |
43694d69 | 10871 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
10872 | } |
10873 | ||
79e53945 JB |
10874 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
10875 | { | |
10876 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
10877 | struct drm_device *dev = crtc->dev; |
10878 | struct intel_unpin_work *work; | |
67e77c5a | 10879 | |
5e2d7afc | 10880 | spin_lock_irq(&dev->event_lock); |
67e77c5a DV |
10881 | work = intel_crtc->unpin_work; |
10882 | intel_crtc->unpin_work = NULL; | |
5e2d7afc | 10883 | spin_unlock_irq(&dev->event_lock); |
67e77c5a DV |
10884 | |
10885 | if (work) { | |
10886 | cancel_work_sync(&work->work); | |
10887 | kfree(work); | |
10888 | } | |
79e53945 JB |
10889 | |
10890 | drm_crtc_cleanup(crtc); | |
67e77c5a | 10891 | |
79e53945 JB |
10892 | kfree(intel_crtc); |
10893 | } | |
10894 | ||
6b95a207 KH |
10895 | static void intel_unpin_work_fn(struct work_struct *__work) |
10896 | { | |
10897 | struct intel_unpin_work *work = | |
10898 | container_of(__work, struct intel_unpin_work, work); | |
a9ff8714 VS |
10899 | struct intel_crtc *crtc = to_intel_crtc(work->crtc); |
10900 | struct drm_device *dev = crtc->base.dev; | |
10901 | struct drm_plane *primary = crtc->base.primary; | |
6b95a207 | 10902 | |
b4a98e57 | 10903 | mutex_lock(&dev->struct_mutex); |
a9ff8714 | 10904 | intel_unpin_fb_obj(work->old_fb, primary->state); |
05394f39 | 10905 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
d9e86c0e | 10906 | |
f06cc1b9 | 10907 | if (work->flip_queued_req) |
146d84f0 | 10908 | i915_gem_request_assign(&work->flip_queued_req, NULL); |
b4a98e57 CW |
10909 | mutex_unlock(&dev->struct_mutex); |
10910 | ||
a9ff8714 | 10911 | intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit); |
1eb52238 | 10912 | intel_fbc_post_update(crtc); |
89ed88ba | 10913 | drm_framebuffer_unreference(work->old_fb); |
f99d7069 | 10914 | |
a9ff8714 VS |
10915 | BUG_ON(atomic_read(&crtc->unpin_work_count) == 0); |
10916 | atomic_dec(&crtc->unpin_work_count); | |
b4a98e57 | 10917 | |
6b95a207 KH |
10918 | kfree(work); |
10919 | } | |
10920 | ||
1afe3e9d | 10921 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 10922 | struct drm_crtc *crtc) |
6b95a207 | 10923 | { |
6b95a207 KH |
10924 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
10925 | struct intel_unpin_work *work; | |
6b95a207 KH |
10926 | unsigned long flags; |
10927 | ||
10928 | /* Ignore early vblank irqs */ | |
10929 | if (intel_crtc == NULL) | |
10930 | return; | |
10931 | ||
f326038a DV |
10932 | /* |
10933 | * This is called both by irq handlers and the reset code (to complete | |
10934 | * lost pageflips) so needs the full irqsave spinlocks. | |
10935 | */ | |
6b95a207 KH |
10936 | spin_lock_irqsave(&dev->event_lock, flags); |
10937 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
10938 | |
10939 | /* Ensure we don't miss a work->pending update ... */ | |
10940 | smp_rmb(); | |
10941 | ||
10942 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
10943 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10944 | return; | |
10945 | } | |
10946 | ||
d6bbafa1 | 10947 | page_flip_completed(intel_crtc); |
0af7e4df | 10948 | |
6b95a207 | 10949 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
10950 | } |
10951 | ||
1afe3e9d JB |
10952 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
10953 | { | |
fbee40df | 10954 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10955 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
10956 | ||
49b14a5c | 10957 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10958 | } |
10959 | ||
10960 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
10961 | { | |
fbee40df | 10962 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
10963 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
10964 | ||
49b14a5c | 10965 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
10966 | } |
10967 | ||
75f7f3ec VS |
10968 | /* Is 'a' after or equal to 'b'? */ |
10969 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
10970 | { | |
10971 | return !((a - b) & 0x80000000); | |
10972 | } | |
10973 | ||
10974 | static bool page_flip_finished(struct intel_crtc *crtc) | |
10975 | { | |
10976 | struct drm_device *dev = crtc->base.dev; | |
10977 | struct drm_i915_private *dev_priv = dev->dev_private; | |
10978 | ||
bdfa7542 VS |
10979 | if (i915_reset_in_progress(&dev_priv->gpu_error) || |
10980 | crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
10981 | return true; | |
10982 | ||
75f7f3ec VS |
10983 | /* |
10984 | * The relevant registers doen't exist on pre-ctg. | |
10985 | * As the flip done interrupt doesn't trigger for mmio | |
10986 | * flips on gmch platforms, a flip count check isn't | |
10987 | * really needed there. But since ctg has the registers, | |
10988 | * include it in the check anyway. | |
10989 | */ | |
10990 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
10991 | return true; | |
10992 | ||
10993 | /* | |
10994 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
10995 | * used the same base address. In that case the mmio flip might | |
10996 | * have completed, but the CS hasn't even executed the flip yet. | |
10997 | * | |
10998 | * A flip count check isn't enough as the CS might have updated | |
10999 | * the base address just after start of vblank, but before we | |
11000 | * managed to process the interrupt. This means we'd complete the | |
11001 | * CS flip too soon. | |
11002 | * | |
11003 | * Combining both checks should get us a good enough result. It may | |
11004 | * still happen that the CS flip has been executed, but has not | |
11005 | * yet actually completed. But in case the base address is the same | |
11006 | * anyway, we don't really care. | |
11007 | */ | |
11008 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
11009 | crtc->unpin_work->gtt_offset && | |
fd8f507c | 11010 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)), |
75f7f3ec VS |
11011 | crtc->unpin_work->flip_count); |
11012 | } | |
11013 | ||
6b95a207 KH |
11014 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
11015 | { | |
fbee40df | 11016 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
11017 | struct intel_crtc *intel_crtc = |
11018 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
11019 | unsigned long flags; | |
11020 | ||
f326038a DV |
11021 | |
11022 | /* | |
11023 | * This is called both by irq handlers and the reset code (to complete | |
11024 | * lost pageflips) so needs the full irqsave spinlocks. | |
11025 | * | |
11026 | * NB: An MMIO update of the plane base pointer will also | |
e7d841ca CW |
11027 | * generate a page-flip completion irq, i.e. every modeset |
11028 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
11029 | */ | |
6b95a207 | 11030 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 11031 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 11032 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
11033 | spin_unlock_irqrestore(&dev->event_lock, flags); |
11034 | } | |
11035 | ||
6042639c | 11036 | static inline void intel_mark_page_flip_active(struct intel_unpin_work *work) |
e7d841ca CW |
11037 | { |
11038 | /* Ensure that the work item is consistent when activating it ... */ | |
11039 | smp_wmb(); | |
6042639c | 11040 | atomic_set(&work->pending, INTEL_FLIP_PENDING); |
e7d841ca CW |
11041 | /* and that it is marked active as soon as the irq could fire. */ |
11042 | smp_wmb(); | |
11043 | } | |
11044 | ||
8c9f3aaf JB |
11045 | static int intel_gen2_queue_flip(struct drm_device *dev, |
11046 | struct drm_crtc *crtc, | |
11047 | struct drm_framebuffer *fb, | |
ed8d1975 | 11048 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11049 | struct drm_i915_gem_request *req, |
ed8d1975 | 11050 | uint32_t flags) |
8c9f3aaf | 11051 | { |
6258fbe2 | 11052 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf | 11053 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
11054 | u32 flip_mask; |
11055 | int ret; | |
11056 | ||
5fb9de1a | 11057 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 11058 | if (ret) |
4fa62c89 | 11059 | return ret; |
8c9f3aaf JB |
11060 | |
11061 | /* Can't queue multiple flips, so wait for the previous | |
11062 | * one to finish before executing the next. | |
11063 | */ | |
11064 | if (intel_crtc->plane) | |
11065 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11066 | else | |
11067 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
11068 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11069 | intel_ring_emit(ring, MI_NOOP); | |
11070 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
11071 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11072 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11073 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 11074 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca | 11075 | |
6042639c | 11076 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11077 | return 0; |
8c9f3aaf JB |
11078 | } |
11079 | ||
11080 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
11081 | struct drm_crtc *crtc, | |
11082 | struct drm_framebuffer *fb, | |
ed8d1975 | 11083 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11084 | struct drm_i915_gem_request *req, |
ed8d1975 | 11085 | uint32_t flags) |
8c9f3aaf | 11086 | { |
6258fbe2 | 11087 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf | 11088 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
11089 | u32 flip_mask; |
11090 | int ret; | |
11091 | ||
5fb9de1a | 11092 | ret = intel_ring_begin(req, 6); |
8c9f3aaf | 11093 | if (ret) |
4fa62c89 | 11094 | return ret; |
8c9f3aaf JB |
11095 | |
11096 | if (intel_crtc->plane) | |
11097 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
11098 | else | |
11099 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
11100 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
11101 | intel_ring_emit(ring, MI_NOOP); | |
11102 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
11103 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11104 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11105 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
11106 | intel_ring_emit(ring, MI_NOOP); |
11107 | ||
6042639c | 11108 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11109 | return 0; |
8c9f3aaf JB |
11110 | } |
11111 | ||
11112 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
11113 | struct drm_crtc *crtc, | |
11114 | struct drm_framebuffer *fb, | |
ed8d1975 | 11115 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11116 | struct drm_i915_gem_request *req, |
ed8d1975 | 11117 | uint32_t flags) |
8c9f3aaf | 11118 | { |
6258fbe2 | 11119 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf JB |
11120 | struct drm_i915_private *dev_priv = dev->dev_private; |
11121 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11122 | uint32_t pf, pipesrc; | |
11123 | int ret; | |
11124 | ||
5fb9de1a | 11125 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11126 | if (ret) |
4fa62c89 | 11127 | return ret; |
8c9f3aaf JB |
11128 | |
11129 | /* i965+ uses the linear or tiled offsets from the | |
11130 | * Display Registers (which do not change across a page-flip) | |
11131 | * so we need only reprogram the base address. | |
11132 | */ | |
6d90c952 DV |
11133 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
11134 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11135 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 11136 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 11137 | obj->tiling_mode); |
8c9f3aaf JB |
11138 | |
11139 | /* XXX Enabling the panel-fitter across page-flip is so far | |
11140 | * untested on non-native modes, so ignore it for now. | |
11141 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
11142 | */ | |
11143 | pf = 0; | |
11144 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 11145 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca | 11146 | |
6042639c | 11147 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11148 | return 0; |
8c9f3aaf JB |
11149 | } |
11150 | ||
11151 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
11152 | struct drm_crtc *crtc, | |
11153 | struct drm_framebuffer *fb, | |
ed8d1975 | 11154 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11155 | struct drm_i915_gem_request *req, |
ed8d1975 | 11156 | uint32_t flags) |
8c9f3aaf | 11157 | { |
6258fbe2 | 11158 | struct intel_engine_cs *ring = req->ring; |
8c9f3aaf JB |
11159 | struct drm_i915_private *dev_priv = dev->dev_private; |
11160 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11161 | uint32_t pf, pipesrc; | |
11162 | int ret; | |
11163 | ||
5fb9de1a | 11164 | ret = intel_ring_begin(req, 4); |
8c9f3aaf | 11165 | if (ret) |
4fa62c89 | 11166 | return ret; |
8c9f3aaf | 11167 | |
6d90c952 DV |
11168 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
11169 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
11170 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 11171 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 11172 | |
dc257cf1 DV |
11173 | /* Contrary to the suggestions in the documentation, |
11174 | * "Enable Panel Fitter" does not seem to be required when page | |
11175 | * flipping with a non-native mode, and worse causes a normal | |
11176 | * modeset to fail. | |
11177 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
11178 | */ | |
11179 | pf = 0; | |
8c9f3aaf | 11180 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 11181 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca | 11182 | |
6042639c | 11183 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11184 | return 0; |
8c9f3aaf JB |
11185 | } |
11186 | ||
7c9017e5 JB |
11187 | static int intel_gen7_queue_flip(struct drm_device *dev, |
11188 | struct drm_crtc *crtc, | |
11189 | struct drm_framebuffer *fb, | |
ed8d1975 | 11190 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11191 | struct drm_i915_gem_request *req, |
ed8d1975 | 11192 | uint32_t flags) |
7c9017e5 | 11193 | { |
6258fbe2 | 11194 | struct intel_engine_cs *ring = req->ring; |
7c9017e5 | 11195 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 11196 | uint32_t plane_bit = 0; |
ffe74d75 CW |
11197 | int len, ret; |
11198 | ||
eba905b2 | 11199 | switch (intel_crtc->plane) { |
cb05d8de DV |
11200 | case PLANE_A: |
11201 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
11202 | break; | |
11203 | case PLANE_B: | |
11204 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
11205 | break; | |
11206 | case PLANE_C: | |
11207 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
11208 | break; | |
11209 | default: | |
11210 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 11211 | return -ENODEV; |
cb05d8de DV |
11212 | } |
11213 | ||
ffe74d75 | 11214 | len = 4; |
f476828a | 11215 | if (ring->id == RCS) { |
ffe74d75 | 11216 | len += 6; |
f476828a DL |
11217 | /* |
11218 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
11219 | * 48bits addresses, and we need a NOOP for the batch size to | |
11220 | * stay even. | |
11221 | */ | |
11222 | if (IS_GEN8(dev)) | |
11223 | len += 2; | |
11224 | } | |
ffe74d75 | 11225 | |
f66fab8e VS |
11226 | /* |
11227 | * BSpec MI_DISPLAY_FLIP for IVB: | |
11228 | * "The full packet must be contained within the same cache line." | |
11229 | * | |
11230 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
11231 | * cacheline, if we ever start emitting more commands before | |
11232 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
11233 | * then do the cacheline alignment, and finally emit the | |
11234 | * MI_DISPLAY_FLIP. | |
11235 | */ | |
bba09b12 | 11236 | ret = intel_ring_cacheline_align(req); |
f66fab8e | 11237 | if (ret) |
4fa62c89 | 11238 | return ret; |
f66fab8e | 11239 | |
5fb9de1a | 11240 | ret = intel_ring_begin(req, len); |
7c9017e5 | 11241 | if (ret) |
4fa62c89 | 11242 | return ret; |
7c9017e5 | 11243 | |
ffe74d75 CW |
11244 | /* Unmask the flip-done completion message. Note that the bspec says that |
11245 | * we should do this for both the BCS and RCS, and that we must not unmask | |
11246 | * more than one flip event at any time (or ensure that one flip message | |
11247 | * can be sent by waiting for flip-done prior to queueing new flips). | |
11248 | * Experimentation says that BCS works despite DERRMR masking all | |
11249 | * flip-done completion events and that unmasking all planes at once | |
11250 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
11251 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
11252 | */ | |
11253 | if (ring->id == RCS) { | |
11254 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
f92a9162 | 11255 | intel_ring_emit_reg(ring, DERRMR); |
ffe74d75 CW |
11256 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | |
11257 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
11258 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a | 11259 | if (IS_GEN8(dev)) |
f1afe24f | 11260 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 | |
f476828a DL |
11261 | MI_SRM_LRM_GLOBAL_GTT); |
11262 | else | |
f1afe24f | 11263 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM | |
f476828a | 11264 | MI_SRM_LRM_GLOBAL_GTT); |
f92a9162 | 11265 | intel_ring_emit_reg(ring, DERRMR); |
ffe74d75 | 11266 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); |
f476828a DL |
11267 | if (IS_GEN8(dev)) { |
11268 | intel_ring_emit(ring, 0); | |
11269 | intel_ring_emit(ring, MI_NOOP); | |
11270 | } | |
ffe74d75 CW |
11271 | } |
11272 | ||
cb05d8de | 11273 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 11274 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 11275 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 11276 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca | 11277 | |
6042639c | 11278 | intel_mark_page_flip_active(intel_crtc->unpin_work); |
83d4092b | 11279 | return 0; |
7c9017e5 JB |
11280 | } |
11281 | ||
84c33a64 SG |
11282 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
11283 | struct drm_i915_gem_object *obj) | |
11284 | { | |
11285 | /* | |
11286 | * This is not being used for older platforms, because | |
11287 | * non-availability of flip done interrupt forces us to use | |
11288 | * CS flips. Older platforms derive flip done using some clever | |
11289 | * tricks involving the flip_pending status bits and vblank irqs. | |
11290 | * So using MMIO flips there would disrupt this mechanism. | |
11291 | */ | |
11292 | ||
8e09bf83 CW |
11293 | if (ring == NULL) |
11294 | return true; | |
11295 | ||
84c33a64 SG |
11296 | if (INTEL_INFO(ring->dev)->gen < 5) |
11297 | return false; | |
11298 | ||
11299 | if (i915.use_mmio_flip < 0) | |
11300 | return false; | |
11301 | else if (i915.use_mmio_flip > 0) | |
11302 | return true; | |
14bf993e OM |
11303 | else if (i915.enable_execlists) |
11304 | return true; | |
fd8e058a AG |
11305 | else if (obj->base.dma_buf && |
11306 | !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv, | |
11307 | false)) | |
11308 | return true; | |
84c33a64 | 11309 | else |
b4716185 | 11310 | return ring != i915_gem_request_get_ring(obj->last_write_req); |
84c33a64 SG |
11311 | } |
11312 | ||
6042639c | 11313 | static void skl_do_mmio_flip(struct intel_crtc *intel_crtc, |
86efe24a | 11314 | unsigned int rotation, |
6042639c | 11315 | struct intel_unpin_work *work) |
ff944564 DL |
11316 | { |
11317 | struct drm_device *dev = intel_crtc->base.dev; | |
11318 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11319 | struct drm_framebuffer *fb = intel_crtc->base.primary->fb; | |
ff944564 | 11320 | const enum pipe pipe = intel_crtc->pipe; |
86efe24a | 11321 | u32 ctl, stride, tile_height; |
ff944564 DL |
11322 | |
11323 | ctl = I915_READ(PLANE_CTL(pipe, 0)); | |
11324 | ctl &= ~PLANE_CTL_TILED_MASK; | |
2ebef630 TU |
11325 | switch (fb->modifier[0]) { |
11326 | case DRM_FORMAT_MOD_NONE: | |
11327 | break; | |
11328 | case I915_FORMAT_MOD_X_TILED: | |
ff944564 | 11329 | ctl |= PLANE_CTL_TILED_X; |
2ebef630 TU |
11330 | break; |
11331 | case I915_FORMAT_MOD_Y_TILED: | |
11332 | ctl |= PLANE_CTL_TILED_Y; | |
11333 | break; | |
11334 | case I915_FORMAT_MOD_Yf_TILED: | |
11335 | ctl |= PLANE_CTL_TILED_YF; | |
11336 | break; | |
11337 | default: | |
11338 | MISSING_CASE(fb->modifier[0]); | |
11339 | } | |
ff944564 DL |
11340 | |
11341 | /* | |
11342 | * The stride is either expressed as a multiple of 64 bytes chunks for | |
11343 | * linear buffers or in number of tiles for tiled buffers. | |
11344 | */ | |
86efe24a TU |
11345 | if (intel_rotation_90_or_270(rotation)) { |
11346 | /* stride = Surface height in tiles */ | |
832be82f | 11347 | tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0); |
86efe24a TU |
11348 | stride = DIV_ROUND_UP(fb->height, tile_height); |
11349 | } else { | |
11350 | stride = fb->pitches[0] / | |
7b49f948 VS |
11351 | intel_fb_stride_alignment(dev_priv, fb->modifier[0], |
11352 | fb->pixel_format); | |
86efe24a | 11353 | } |
ff944564 DL |
11354 | |
11355 | /* | |
11356 | * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on | |
11357 | * PLANE_SURF updates, the update is then guaranteed to be atomic. | |
11358 | */ | |
11359 | I915_WRITE(PLANE_CTL(pipe, 0), ctl); | |
11360 | I915_WRITE(PLANE_STRIDE(pipe, 0), stride); | |
11361 | ||
6042639c | 11362 | I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset); |
ff944564 DL |
11363 | POSTING_READ(PLANE_SURF(pipe, 0)); |
11364 | } | |
11365 | ||
6042639c CW |
11366 | static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc, |
11367 | struct intel_unpin_work *work) | |
84c33a64 SG |
11368 | { |
11369 | struct drm_device *dev = intel_crtc->base.dev; | |
11370 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11371 | struct intel_framebuffer *intel_fb = | |
11372 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
11373 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
f0f59a00 | 11374 | i915_reg_t reg = DSPCNTR(intel_crtc->plane); |
84c33a64 | 11375 | u32 dspcntr; |
84c33a64 | 11376 | |
84c33a64 SG |
11377 | dspcntr = I915_READ(reg); |
11378 | ||
c5d97472 DL |
11379 | if (obj->tiling_mode != I915_TILING_NONE) |
11380 | dspcntr |= DISPPLANE_TILED; | |
11381 | else | |
11382 | dspcntr &= ~DISPPLANE_TILED; | |
11383 | ||
84c33a64 SG |
11384 | I915_WRITE(reg, dspcntr); |
11385 | ||
6042639c | 11386 | I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset); |
84c33a64 | 11387 | POSTING_READ(DSPSURF(intel_crtc->plane)); |
ff944564 DL |
11388 | } |
11389 | ||
11390 | /* | |
11391 | * XXX: This is the temporary way to update the plane registers until we get | |
11392 | * around to using the usual plane update functions for MMIO flips | |
11393 | */ | |
6042639c | 11394 | static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip) |
ff944564 | 11395 | { |
6042639c CW |
11396 | struct intel_crtc *crtc = mmio_flip->crtc; |
11397 | struct intel_unpin_work *work; | |
11398 | ||
11399 | spin_lock_irq(&crtc->base.dev->event_lock); | |
11400 | work = crtc->unpin_work; | |
11401 | spin_unlock_irq(&crtc->base.dev->event_lock); | |
11402 | if (work == NULL) | |
11403 | return; | |
ff944564 | 11404 | |
6042639c | 11405 | intel_mark_page_flip_active(work); |
ff944564 | 11406 | |
6042639c | 11407 | intel_pipe_update_start(crtc); |
ff944564 | 11408 | |
6042639c | 11409 | if (INTEL_INFO(mmio_flip->i915)->gen >= 9) |
86efe24a | 11410 | skl_do_mmio_flip(crtc, mmio_flip->rotation, work); |
ff944564 DL |
11411 | else |
11412 | /* use_mmio_flip() retricts MMIO flips to ilk+ */ | |
6042639c | 11413 | ilk_do_mmio_flip(crtc, work); |
ff944564 | 11414 | |
6042639c | 11415 | intel_pipe_update_end(crtc); |
84c33a64 SG |
11416 | } |
11417 | ||
9362c7c5 | 11418 | static void intel_mmio_flip_work_func(struct work_struct *work) |
84c33a64 | 11419 | { |
b2cfe0ab CW |
11420 | struct intel_mmio_flip *mmio_flip = |
11421 | container_of(work, struct intel_mmio_flip, work); | |
fd8e058a AG |
11422 | struct intel_framebuffer *intel_fb = |
11423 | to_intel_framebuffer(mmio_flip->crtc->base.primary->fb); | |
11424 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
84c33a64 | 11425 | |
6042639c | 11426 | if (mmio_flip->req) { |
eed29a5b | 11427 | WARN_ON(__i915_wait_request(mmio_flip->req, |
b2cfe0ab | 11428 | mmio_flip->crtc->reset_counter, |
bcafc4e3 CW |
11429 | false, NULL, |
11430 | &mmio_flip->i915->rps.mmioflips)); | |
6042639c CW |
11431 | i915_gem_request_unreference__unlocked(mmio_flip->req); |
11432 | } | |
84c33a64 | 11433 | |
fd8e058a AG |
11434 | /* For framebuffer backed by dmabuf, wait for fence */ |
11435 | if (obj->base.dma_buf) | |
11436 | WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
11437 | false, false, | |
11438 | MAX_SCHEDULE_TIMEOUT) < 0); | |
11439 | ||
6042639c | 11440 | intel_do_mmio_flip(mmio_flip); |
b2cfe0ab | 11441 | kfree(mmio_flip); |
84c33a64 SG |
11442 | } |
11443 | ||
11444 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
11445 | struct drm_crtc *crtc, | |
86efe24a | 11446 | struct drm_i915_gem_object *obj) |
84c33a64 | 11447 | { |
b2cfe0ab CW |
11448 | struct intel_mmio_flip *mmio_flip; |
11449 | ||
11450 | mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL); | |
11451 | if (mmio_flip == NULL) | |
11452 | return -ENOMEM; | |
84c33a64 | 11453 | |
bcafc4e3 | 11454 | mmio_flip->i915 = to_i915(dev); |
eed29a5b | 11455 | mmio_flip->req = i915_gem_request_reference(obj->last_write_req); |
b2cfe0ab | 11456 | mmio_flip->crtc = to_intel_crtc(crtc); |
86efe24a | 11457 | mmio_flip->rotation = crtc->primary->state->rotation; |
536f5b5e | 11458 | |
b2cfe0ab CW |
11459 | INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func); |
11460 | schedule_work(&mmio_flip->work); | |
84c33a64 | 11461 | |
84c33a64 SG |
11462 | return 0; |
11463 | } | |
11464 | ||
8c9f3aaf JB |
11465 | static int intel_default_queue_flip(struct drm_device *dev, |
11466 | struct drm_crtc *crtc, | |
11467 | struct drm_framebuffer *fb, | |
ed8d1975 | 11468 | struct drm_i915_gem_object *obj, |
6258fbe2 | 11469 | struct drm_i915_gem_request *req, |
ed8d1975 | 11470 | uint32_t flags) |
8c9f3aaf JB |
11471 | { |
11472 | return -ENODEV; | |
11473 | } | |
11474 | ||
d6bbafa1 CW |
11475 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
11476 | struct drm_crtc *crtc) | |
11477 | { | |
11478 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11479 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11480 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
11481 | u32 addr; | |
11482 | ||
11483 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
11484 | return true; | |
11485 | ||
908565c2 CW |
11486 | if (atomic_read(&work->pending) < INTEL_FLIP_PENDING) |
11487 | return false; | |
11488 | ||
d6bbafa1 CW |
11489 | if (!work->enable_stall_check) |
11490 | return false; | |
11491 | ||
11492 | if (work->flip_ready_vblank == 0) { | |
3a8a946e DV |
11493 | if (work->flip_queued_req && |
11494 | !i915_gem_request_completed(work->flip_queued_req, true)) | |
d6bbafa1 CW |
11495 | return false; |
11496 | ||
1e3feefd | 11497 | work->flip_ready_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 CW |
11498 | } |
11499 | ||
1e3feefd | 11500 | if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3) |
d6bbafa1 CW |
11501 | return false; |
11502 | ||
11503 | /* Potential stall - if we see that the flip has happened, | |
11504 | * assume a missed interrupt. */ | |
11505 | if (INTEL_INFO(dev)->gen >= 4) | |
11506 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
11507 | else | |
11508 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
11509 | ||
11510 | /* There is a potential issue here with a false positive after a flip | |
11511 | * to the same address. We could address this by checking for a | |
11512 | * non-incrementing frame counter. | |
11513 | */ | |
11514 | return addr == work->gtt_offset; | |
11515 | } | |
11516 | ||
11517 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
11518 | { | |
11519 | struct drm_i915_private *dev_priv = dev->dev_private; | |
11520 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
11521 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6ad790c0 | 11522 | struct intel_unpin_work *work; |
f326038a | 11523 | |
6c51d46f | 11524 | WARN_ON(!in_interrupt()); |
d6bbafa1 CW |
11525 | |
11526 | if (crtc == NULL) | |
11527 | return; | |
11528 | ||
f326038a | 11529 | spin_lock(&dev->event_lock); |
6ad790c0 CW |
11530 | work = intel_crtc->unpin_work; |
11531 | if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) { | |
d6bbafa1 | 11532 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", |
6ad790c0 | 11533 | work->flip_queued_vblank, drm_vblank_count(dev, pipe)); |
d6bbafa1 | 11534 | page_flip_completed(intel_crtc); |
6ad790c0 | 11535 | work = NULL; |
d6bbafa1 | 11536 | } |
6ad790c0 CW |
11537 | if (work != NULL && |
11538 | drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1) | |
11539 | intel_queue_rps_boost_for_request(dev, work->flip_queued_req); | |
f326038a | 11540 | spin_unlock(&dev->event_lock); |
d6bbafa1 CW |
11541 | } |
11542 | ||
6b95a207 KH |
11543 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
11544 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
11545 | struct drm_pending_vblank_event *event, |
11546 | uint32_t page_flip_flags) | |
6b95a207 KH |
11547 | { |
11548 | struct drm_device *dev = crtc->dev; | |
11549 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 11550 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 11551 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 11552 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
455a6808 | 11553 | struct drm_plane *primary = crtc->primary; |
a071fa00 | 11554 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 11555 | struct intel_unpin_work *work; |
a4872ba6 | 11556 | struct intel_engine_cs *ring; |
cf5d8a46 | 11557 | bool mmio_flip; |
91af127f | 11558 | struct drm_i915_gem_request *request = NULL; |
52e68630 | 11559 | int ret; |
6b95a207 | 11560 | |
2ff8fde1 MR |
11561 | /* |
11562 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
11563 | * check to be safe. In the future we may enable pageflipping from | |
11564 | * a disabled primary plane. | |
11565 | */ | |
11566 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
11567 | return -EBUSY; | |
11568 | ||
e6a595d2 | 11569 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 11570 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
11571 | return -EINVAL; |
11572 | ||
11573 | /* | |
11574 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
11575 | * Note that pitch changes could also affect these register. | |
11576 | */ | |
11577 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
11578 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
11579 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
11580 | return -EINVAL; |
11581 | ||
f900db47 CW |
11582 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
11583 | goto out_hang; | |
11584 | ||
b14c5679 | 11585 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
11586 | if (work == NULL) |
11587 | return -ENOMEM; | |
11588 | ||
6b95a207 | 11589 | work->event = event; |
b4a98e57 | 11590 | work->crtc = crtc; |
ab8d6675 | 11591 | work->old_fb = old_fb; |
6b95a207 KH |
11592 | INIT_WORK(&work->work, intel_unpin_work_fn); |
11593 | ||
87b6b101 | 11594 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
11595 | if (ret) |
11596 | goto free_work; | |
11597 | ||
6b95a207 | 11598 | /* We borrow the event spin lock for protecting unpin_work */ |
5e2d7afc | 11599 | spin_lock_irq(&dev->event_lock); |
6b95a207 | 11600 | if (intel_crtc->unpin_work) { |
d6bbafa1 CW |
11601 | /* Before declaring the flip queue wedged, check if |
11602 | * the hardware completed the operation behind our backs. | |
11603 | */ | |
11604 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
11605 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
11606 | page_flip_completed(intel_crtc); | |
11607 | } else { | |
11608 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
5e2d7afc | 11609 | spin_unlock_irq(&dev->event_lock); |
468f0b44 | 11610 | |
d6bbafa1 CW |
11611 | drm_crtc_vblank_put(crtc); |
11612 | kfree(work); | |
11613 | return -EBUSY; | |
11614 | } | |
6b95a207 KH |
11615 | } |
11616 | intel_crtc->unpin_work = work; | |
5e2d7afc | 11617 | spin_unlock_irq(&dev->event_lock); |
6b95a207 | 11618 | |
b4a98e57 CW |
11619 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
11620 | flush_workqueue(dev_priv->wq); | |
11621 | ||
75dfca80 | 11622 | /* Reference the objects for the scheduled work. */ |
ab8d6675 | 11623 | drm_framebuffer_reference(work->old_fb); |
05394f39 | 11624 | drm_gem_object_reference(&obj->base); |
6b95a207 | 11625 | |
f4510a27 | 11626 | crtc->primary->fb = fb; |
afd65eb4 | 11627 | update_state_fb(crtc->primary); |
e8216e50 | 11628 | intel_fbc_pre_update(intel_crtc); |
1ed1f968 | 11629 | |
e1f99ce6 | 11630 | work->pending_flip_obj = obj; |
e1f99ce6 | 11631 | |
89ed88ba CW |
11632 | ret = i915_mutex_lock_interruptible(dev); |
11633 | if (ret) | |
11634 | goto cleanup; | |
11635 | ||
b4a98e57 | 11636 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 11637 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 11638 | |
75f7f3ec | 11639 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
fd8f507c | 11640 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1; |
75f7f3ec | 11641 | |
666a4537 | 11642 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
4fa62c89 | 11643 | ring = &dev_priv->ring[BCS]; |
ab8d6675 | 11644 | if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode) |
8e09bf83 CW |
11645 | /* vlv: DISPLAY_FLIP fails to change tiling */ |
11646 | ring = NULL; | |
48bf5b2d | 11647 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
2a92d5bc | 11648 | ring = &dev_priv->ring[BCS]; |
4fa62c89 | 11649 | } else if (INTEL_INFO(dev)->gen >= 7) { |
b4716185 | 11650 | ring = i915_gem_request_get_ring(obj->last_write_req); |
4fa62c89 VS |
11651 | if (ring == NULL || ring->id != RCS) |
11652 | ring = &dev_priv->ring[BCS]; | |
11653 | } else { | |
11654 | ring = &dev_priv->ring[RCS]; | |
11655 | } | |
11656 | ||
cf5d8a46 CW |
11657 | mmio_flip = use_mmio_flip(ring, obj); |
11658 | ||
11659 | /* When using CS flips, we want to emit semaphores between rings. | |
11660 | * However, when using mmio flips we will create a task to do the | |
11661 | * synchronisation, so all we want here is to pin the framebuffer | |
11662 | * into the display plane and skip any waits. | |
11663 | */ | |
7580d774 ML |
11664 | if (!mmio_flip) { |
11665 | ret = i915_gem_object_sync(obj, ring, &request); | |
11666 | if (ret) | |
11667 | goto cleanup_pending; | |
11668 | } | |
11669 | ||
82bc3b2d | 11670 | ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, |
7580d774 | 11671 | crtc->primary->state); |
8c9f3aaf JB |
11672 | if (ret) |
11673 | goto cleanup_pending; | |
6b95a207 | 11674 | |
dedf278c TU |
11675 | work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), |
11676 | obj, 0); | |
11677 | work->gtt_offset += intel_crtc->dspaddr_offset; | |
4fa62c89 | 11678 | |
cf5d8a46 | 11679 | if (mmio_flip) { |
86efe24a | 11680 | ret = intel_queue_mmio_flip(dev, crtc, obj); |
d6bbafa1 CW |
11681 | if (ret) |
11682 | goto cleanup_unpin; | |
11683 | ||
f06cc1b9 JH |
11684 | i915_gem_request_assign(&work->flip_queued_req, |
11685 | obj->last_write_req); | |
d6bbafa1 | 11686 | } else { |
6258fbe2 | 11687 | if (!request) { |
26827088 DG |
11688 | request = i915_gem_request_alloc(ring, NULL); |
11689 | if (IS_ERR(request)) { | |
11690 | ret = PTR_ERR(request); | |
6258fbe2 | 11691 | goto cleanup_unpin; |
26827088 | 11692 | } |
6258fbe2 JH |
11693 | } |
11694 | ||
11695 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request, | |
d6bbafa1 CW |
11696 | page_flip_flags); |
11697 | if (ret) | |
11698 | goto cleanup_unpin; | |
11699 | ||
6258fbe2 | 11700 | i915_gem_request_assign(&work->flip_queued_req, request); |
d6bbafa1 CW |
11701 | } |
11702 | ||
91af127f | 11703 | if (request) |
75289874 | 11704 | i915_add_request_no_flush(request); |
91af127f | 11705 | |
1e3feefd | 11706 | work->flip_queued_vblank = drm_crtc_vblank_count(crtc); |
d6bbafa1 | 11707 | work->enable_stall_check = true; |
4fa62c89 | 11708 | |
ab8d6675 | 11709 | i915_gem_track_fb(intel_fb_obj(work->old_fb), obj, |
a9ff8714 | 11710 | to_intel_plane(primary)->frontbuffer_bit); |
c80ac854 | 11711 | mutex_unlock(&dev->struct_mutex); |
a071fa00 | 11712 | |
a9ff8714 VS |
11713 | intel_frontbuffer_flip_prepare(dev, |
11714 | to_intel_plane(primary)->frontbuffer_bit); | |
6b95a207 | 11715 | |
e5510fac JB |
11716 | trace_i915_flip_request(intel_crtc->plane, obj); |
11717 | ||
6b95a207 | 11718 | return 0; |
96b099fd | 11719 | |
4fa62c89 | 11720 | cleanup_unpin: |
82bc3b2d | 11721 | intel_unpin_fb_obj(fb, crtc->primary->state); |
8c9f3aaf | 11722 | cleanup_pending: |
0aa498d5 | 11723 | if (!IS_ERR_OR_NULL(request)) |
91af127f | 11724 | i915_gem_request_cancel(request); |
b4a98e57 | 11725 | atomic_dec(&intel_crtc->unpin_work_count); |
89ed88ba CW |
11726 | mutex_unlock(&dev->struct_mutex); |
11727 | cleanup: | |
f4510a27 | 11728 | crtc->primary->fb = old_fb; |
afd65eb4 | 11729 | update_state_fb(crtc->primary); |
89ed88ba CW |
11730 | |
11731 | drm_gem_object_unreference_unlocked(&obj->base); | |
ab8d6675 | 11732 | drm_framebuffer_unreference(work->old_fb); |
96b099fd | 11733 | |
5e2d7afc | 11734 | spin_lock_irq(&dev->event_lock); |
96b099fd | 11735 | intel_crtc->unpin_work = NULL; |
5e2d7afc | 11736 | spin_unlock_irq(&dev->event_lock); |
96b099fd | 11737 | |
87b6b101 | 11738 | drm_crtc_vblank_put(crtc); |
7317c75e | 11739 | free_work: |
96b099fd CW |
11740 | kfree(work); |
11741 | ||
f900db47 | 11742 | if (ret == -EIO) { |
02e0efb5 ML |
11743 | struct drm_atomic_state *state; |
11744 | struct drm_plane_state *plane_state; | |
11745 | ||
f900db47 | 11746 | out_hang: |
02e0efb5 ML |
11747 | state = drm_atomic_state_alloc(dev); |
11748 | if (!state) | |
11749 | return -ENOMEM; | |
11750 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); | |
11751 | ||
11752 | retry: | |
11753 | plane_state = drm_atomic_get_plane_state(state, primary); | |
11754 | ret = PTR_ERR_OR_ZERO(plane_state); | |
11755 | if (!ret) { | |
11756 | drm_atomic_set_fb_for_plane(plane_state, fb); | |
11757 | ||
11758 | ret = drm_atomic_set_crtc_for_plane(plane_state, crtc); | |
11759 | if (!ret) | |
11760 | ret = drm_atomic_commit(state); | |
11761 | } | |
11762 | ||
11763 | if (ret == -EDEADLK) { | |
11764 | drm_modeset_backoff(state->acquire_ctx); | |
11765 | drm_atomic_state_clear(state); | |
11766 | goto retry; | |
11767 | } | |
11768 | ||
11769 | if (ret) | |
11770 | drm_atomic_state_free(state); | |
11771 | ||
f0d3dad3 | 11772 | if (ret == 0 && event) { |
5e2d7afc | 11773 | spin_lock_irq(&dev->event_lock); |
a071fa00 | 11774 | drm_send_vblank_event(dev, pipe, event); |
5e2d7afc | 11775 | spin_unlock_irq(&dev->event_lock); |
f0d3dad3 | 11776 | } |
f900db47 | 11777 | } |
96b099fd | 11778 | return ret; |
6b95a207 KH |
11779 | } |
11780 | ||
da20eabd ML |
11781 | |
11782 | /** | |
11783 | * intel_wm_need_update - Check whether watermarks need updating | |
11784 | * @plane: drm plane | |
11785 | * @state: new plane state | |
11786 | * | |
11787 | * Check current plane state versus the new one to determine whether | |
11788 | * watermarks need to be recalculated. | |
11789 | * | |
11790 | * Returns true or false. | |
11791 | */ | |
11792 | static bool intel_wm_need_update(struct drm_plane *plane, | |
11793 | struct drm_plane_state *state) | |
11794 | { | |
d21fbe87 MR |
11795 | struct intel_plane_state *new = to_intel_plane_state(state); |
11796 | struct intel_plane_state *cur = to_intel_plane_state(plane->state); | |
11797 | ||
11798 | /* Update watermarks on tiling or size changes. */ | |
92826fcd ML |
11799 | if (new->visible != cur->visible) |
11800 | return true; | |
11801 | ||
11802 | if (!cur->base.fb || !new->base.fb) | |
11803 | return false; | |
11804 | ||
11805 | if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] || | |
11806 | cur->base.rotation != new->base.rotation || | |
d21fbe87 MR |
11807 | drm_rect_width(&new->src) != drm_rect_width(&cur->src) || |
11808 | drm_rect_height(&new->src) != drm_rect_height(&cur->src) || | |
11809 | drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) || | |
11810 | drm_rect_height(&new->dst) != drm_rect_height(&cur->dst)) | |
2791a16c | 11811 | return true; |
7809e5ae | 11812 | |
2791a16c | 11813 | return false; |
7809e5ae MR |
11814 | } |
11815 | ||
d21fbe87 MR |
11816 | static bool needs_scaling(struct intel_plane_state *state) |
11817 | { | |
11818 | int src_w = drm_rect_width(&state->src) >> 16; | |
11819 | int src_h = drm_rect_height(&state->src) >> 16; | |
11820 | int dst_w = drm_rect_width(&state->dst); | |
11821 | int dst_h = drm_rect_height(&state->dst); | |
11822 | ||
11823 | return (src_w != dst_w || src_h != dst_h); | |
11824 | } | |
11825 | ||
da20eabd ML |
11826 | int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state, |
11827 | struct drm_plane_state *plane_state) | |
11828 | { | |
ab1d3a0e | 11829 | struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state); |
da20eabd ML |
11830 | struct drm_crtc *crtc = crtc_state->crtc; |
11831 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11832 | struct drm_plane *plane = plane_state->plane; | |
11833 | struct drm_device *dev = crtc->dev; | |
da20eabd ML |
11834 | struct intel_plane_state *old_plane_state = |
11835 | to_intel_plane_state(plane->state); | |
11836 | int idx = intel_crtc->base.base.id, ret; | |
11837 | int i = drm_plane_index(plane); | |
11838 | bool mode_changed = needs_modeset(crtc_state); | |
11839 | bool was_crtc_enabled = crtc->state->active; | |
11840 | bool is_crtc_enabled = crtc_state->active; | |
da20eabd ML |
11841 | bool turn_off, turn_on, visible, was_visible; |
11842 | struct drm_framebuffer *fb = plane_state->fb; | |
11843 | ||
11844 | if (crtc_state && INTEL_INFO(dev)->gen >= 9 && | |
11845 | plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11846 | ret = skl_update_scaler_plane( | |
11847 | to_intel_crtc_state(crtc_state), | |
11848 | to_intel_plane_state(plane_state)); | |
11849 | if (ret) | |
11850 | return ret; | |
11851 | } | |
11852 | ||
da20eabd ML |
11853 | was_visible = old_plane_state->visible; |
11854 | visible = to_intel_plane_state(plane_state)->visible; | |
11855 | ||
11856 | if (!was_crtc_enabled && WARN_ON(was_visible)) | |
11857 | was_visible = false; | |
11858 | ||
35c08f43 ML |
11859 | /* |
11860 | * Visibility is calculated as if the crtc was on, but | |
11861 | * after scaler setup everything depends on it being off | |
11862 | * when the crtc isn't active. | |
11863 | */ | |
11864 | if (!is_crtc_enabled) | |
11865 | to_intel_plane_state(plane_state)->visible = visible = false; | |
da20eabd ML |
11866 | |
11867 | if (!was_visible && !visible) | |
11868 | return 0; | |
11869 | ||
11870 | turn_off = was_visible && (!visible || mode_changed); | |
11871 | turn_on = visible && (!was_visible || mode_changed); | |
11872 | ||
11873 | DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx, | |
11874 | plane->base.id, fb ? fb->base.id : -1); | |
11875 | ||
11876 | DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n", | |
11877 | plane->base.id, was_visible, visible, | |
11878 | turn_off, turn_on, mode_changed); | |
11879 | ||
92826fcd ML |
11880 | if (turn_on || turn_off) { |
11881 | pipe_config->wm_changed = true; | |
11882 | ||
852eb00d VS |
11883 | /* must disable cxsr around plane enable/disable */ |
11884 | if (plane->type != DRM_PLANE_TYPE_CURSOR) { | |
11885 | if (is_crtc_enabled) | |
11886 | intel_crtc->atomic.wait_vblank = true; | |
ab1d3a0e | 11887 | pipe_config->disable_cxsr = true; |
852eb00d VS |
11888 | } |
11889 | } else if (intel_wm_need_update(plane, plane_state)) { | |
92826fcd | 11890 | pipe_config->wm_changed = true; |
852eb00d | 11891 | } |
da20eabd | 11892 | |
8be6ca85 | 11893 | if (visible || was_visible) |
a9ff8714 VS |
11894 | intel_crtc->atomic.fb_bits |= |
11895 | to_intel_plane(plane)->frontbuffer_bit; | |
11896 | ||
da20eabd ML |
11897 | switch (plane->type) { |
11898 | case DRM_PLANE_TYPE_PRIMARY: | |
da20eabd | 11899 | intel_crtc->atomic.post_enable_primary = turn_on; |
fcf38d13 | 11900 | intel_crtc->atomic.update_fbc = true; |
da20eabd | 11901 | |
da20eabd ML |
11902 | /* |
11903 | * BDW signals flip done immediately if the plane | |
11904 | * is disabled, even if the plane enable is already | |
11905 | * armed to occur at the next vblank :( | |
11906 | */ | |
11907 | if (turn_on && IS_BROADWELL(dev)) | |
11908 | intel_crtc->atomic.wait_vblank = true; | |
11909 | ||
da20eabd ML |
11910 | break; |
11911 | case DRM_PLANE_TYPE_CURSOR: | |
da20eabd ML |
11912 | break; |
11913 | case DRM_PLANE_TYPE_OVERLAY: | |
d21fbe87 MR |
11914 | /* |
11915 | * WaCxSRDisabledForSpriteScaling:ivb | |
11916 | * | |
11917 | * cstate->update_wm was already set above, so this flag will | |
11918 | * take effect when we commit and program watermarks. | |
11919 | */ | |
11920 | if (IS_IVYBRIDGE(dev) && | |
11921 | needs_scaling(to_intel_plane_state(plane_state)) && | |
11922 | !needs_scaling(old_plane_state)) { | |
11923 | to_intel_crtc_state(crtc_state)->disable_lp_wm = true; | |
11924 | } else if (turn_off && !mode_changed) { | |
da20eabd ML |
11925 | intel_crtc->atomic.wait_vblank = true; |
11926 | intel_crtc->atomic.update_sprite_watermarks |= | |
11927 | 1 << i; | |
11928 | } | |
d21fbe87 MR |
11929 | |
11930 | break; | |
da20eabd ML |
11931 | } |
11932 | return 0; | |
11933 | } | |
11934 | ||
6d3a1ce7 ML |
11935 | static bool encoders_cloneable(const struct intel_encoder *a, |
11936 | const struct intel_encoder *b) | |
11937 | { | |
11938 | /* masks could be asymmetric, so check both ways */ | |
11939 | return a == b || (a->cloneable & (1 << b->type) && | |
11940 | b->cloneable & (1 << a->type)); | |
11941 | } | |
11942 | ||
11943 | static bool check_single_encoder_cloning(struct drm_atomic_state *state, | |
11944 | struct intel_crtc *crtc, | |
11945 | struct intel_encoder *encoder) | |
11946 | { | |
11947 | struct intel_encoder *source_encoder; | |
11948 | struct drm_connector *connector; | |
11949 | struct drm_connector_state *connector_state; | |
11950 | int i; | |
11951 | ||
11952 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11953 | if (connector_state->crtc != &crtc->base) | |
11954 | continue; | |
11955 | ||
11956 | source_encoder = | |
11957 | to_intel_encoder(connector_state->best_encoder); | |
11958 | if (!encoders_cloneable(encoder, source_encoder)) | |
11959 | return false; | |
11960 | } | |
11961 | ||
11962 | return true; | |
11963 | } | |
11964 | ||
11965 | static bool check_encoder_cloning(struct drm_atomic_state *state, | |
11966 | struct intel_crtc *crtc) | |
11967 | { | |
11968 | struct intel_encoder *encoder; | |
11969 | struct drm_connector *connector; | |
11970 | struct drm_connector_state *connector_state; | |
11971 | int i; | |
11972 | ||
11973 | for_each_connector_in_state(state, connector, connector_state, i) { | |
11974 | if (connector_state->crtc != &crtc->base) | |
11975 | continue; | |
11976 | ||
11977 | encoder = to_intel_encoder(connector_state->best_encoder); | |
11978 | if (!check_single_encoder_cloning(state, crtc, encoder)) | |
11979 | return false; | |
11980 | } | |
11981 | ||
11982 | return true; | |
11983 | } | |
11984 | ||
11985 | static int intel_crtc_atomic_check(struct drm_crtc *crtc, | |
11986 | struct drm_crtc_state *crtc_state) | |
11987 | { | |
cf5a15be | 11988 | struct drm_device *dev = crtc->dev; |
ad421372 | 11989 | struct drm_i915_private *dev_priv = dev->dev_private; |
6d3a1ce7 | 11990 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cf5a15be ML |
11991 | struct intel_crtc_state *pipe_config = |
11992 | to_intel_crtc_state(crtc_state); | |
6d3a1ce7 | 11993 | struct drm_atomic_state *state = crtc_state->state; |
4d20cd86 | 11994 | int ret; |
6d3a1ce7 ML |
11995 | bool mode_changed = needs_modeset(crtc_state); |
11996 | ||
11997 | if (mode_changed && !check_encoder_cloning(state, intel_crtc)) { | |
11998 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); | |
11999 | return -EINVAL; | |
12000 | } | |
12001 | ||
852eb00d | 12002 | if (mode_changed && !crtc_state->active) |
92826fcd | 12003 | pipe_config->wm_changed = true; |
eddfcbcd | 12004 | |
ad421372 ML |
12005 | if (mode_changed && crtc_state->enable && |
12006 | dev_priv->display.crtc_compute_clock && | |
12007 | !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) { | |
12008 | ret = dev_priv->display.crtc_compute_clock(intel_crtc, | |
12009 | pipe_config); | |
12010 | if (ret) | |
12011 | return ret; | |
12012 | } | |
12013 | ||
e435d6e5 | 12014 | ret = 0; |
86c8bbbe MR |
12015 | if (dev_priv->display.compute_pipe_wm) { |
12016 | ret = dev_priv->display.compute_pipe_wm(intel_crtc, state); | |
bf220452 | 12017 | if (ret) |
86c8bbbe MR |
12018 | return ret; |
12019 | } | |
12020 | ||
e435d6e5 ML |
12021 | if (INTEL_INFO(dev)->gen >= 9) { |
12022 | if (mode_changed) | |
12023 | ret = skl_update_scaler_crtc(pipe_config); | |
12024 | ||
12025 | if (!ret) | |
12026 | ret = intel_atomic_setup_scalers(dev, intel_crtc, | |
12027 | pipe_config); | |
12028 | } | |
12029 | ||
12030 | return ret; | |
6d3a1ce7 ML |
12031 | } |
12032 | ||
65b38e0d | 12033 | static const struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
12034 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
12035 | .load_lut = intel_crtc_load_lut, | |
ea2c67bb MR |
12036 | .atomic_begin = intel_begin_crtc_commit, |
12037 | .atomic_flush = intel_finish_crtc_commit, | |
6d3a1ce7 | 12038 | .atomic_check = intel_crtc_atomic_check, |
f6e5b160 CW |
12039 | }; |
12040 | ||
d29b2f9d ACO |
12041 | static void intel_modeset_update_connector_atomic_state(struct drm_device *dev) |
12042 | { | |
12043 | struct intel_connector *connector; | |
12044 | ||
12045 | for_each_intel_connector(dev, connector) { | |
12046 | if (connector->base.encoder) { | |
12047 | connector->base.state->best_encoder = | |
12048 | connector->base.encoder; | |
12049 | connector->base.state->crtc = | |
12050 | connector->base.encoder->crtc; | |
12051 | } else { | |
12052 | connector->base.state->best_encoder = NULL; | |
12053 | connector->base.state->crtc = NULL; | |
12054 | } | |
12055 | } | |
12056 | } | |
12057 | ||
050f7aeb | 12058 | static void |
eba905b2 | 12059 | connected_sink_compute_bpp(struct intel_connector *connector, |
5cec258b | 12060 | struct intel_crtc_state *pipe_config) |
050f7aeb DV |
12061 | { |
12062 | int bpp = pipe_config->pipe_bpp; | |
12063 | ||
12064 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
12065 | connector->base.base.id, | |
c23cc417 | 12066 | connector->base.name); |
050f7aeb DV |
12067 | |
12068 | /* Don't use an invalid EDID bpc value */ | |
12069 | if (connector->base.display_info.bpc && | |
12070 | connector->base.display_info.bpc * 3 < bpp) { | |
12071 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
12072 | bpp, connector->base.display_info.bpc*3); | |
12073 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
12074 | } | |
12075 | ||
013dd9e0 JN |
12076 | /* Clamp bpp to default limit on screens without EDID 1.4 */ |
12077 | if (connector->base.display_info.bpc == 0) { | |
12078 | int type = connector->base.connector_type; | |
12079 | int clamp_bpp = 24; | |
12080 | ||
12081 | /* Fall back to 18 bpp when DP sink capability is unknown. */ | |
12082 | if (type == DRM_MODE_CONNECTOR_DisplayPort || | |
12083 | type == DRM_MODE_CONNECTOR_eDP) | |
12084 | clamp_bpp = 18; | |
12085 | ||
12086 | if (bpp > clamp_bpp) { | |
12087 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n", | |
12088 | bpp, clamp_bpp); | |
12089 | pipe_config->pipe_bpp = clamp_bpp; | |
12090 | } | |
050f7aeb DV |
12091 | } |
12092 | } | |
12093 | ||
4e53c2e0 | 12094 | static int |
050f7aeb | 12095 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
5cec258b | 12096 | struct intel_crtc_state *pipe_config) |
4e53c2e0 | 12097 | { |
050f7aeb | 12098 | struct drm_device *dev = crtc->base.dev; |
1486017f | 12099 | struct drm_atomic_state *state; |
da3ced29 ACO |
12100 | struct drm_connector *connector; |
12101 | struct drm_connector_state *connector_state; | |
1486017f | 12102 | int bpp, i; |
4e53c2e0 | 12103 | |
666a4537 | 12104 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))) |
4e53c2e0 | 12105 | bpp = 10*3; |
d328c9d7 DV |
12106 | else if (INTEL_INFO(dev)->gen >= 5) |
12107 | bpp = 12*3; | |
12108 | else | |
12109 | bpp = 8*3; | |
12110 | ||
4e53c2e0 | 12111 | |
4e53c2e0 DV |
12112 | pipe_config->pipe_bpp = bpp; |
12113 | ||
1486017f ACO |
12114 | state = pipe_config->base.state; |
12115 | ||
4e53c2e0 | 12116 | /* Clamp display bpp to EDID value */ |
da3ced29 ACO |
12117 | for_each_connector_in_state(state, connector, connector_state, i) { |
12118 | if (connector_state->crtc != &crtc->base) | |
4e53c2e0 DV |
12119 | continue; |
12120 | ||
da3ced29 ACO |
12121 | connected_sink_compute_bpp(to_intel_connector(connector), |
12122 | pipe_config); | |
4e53c2e0 DV |
12123 | } |
12124 | ||
12125 | return bpp; | |
12126 | } | |
12127 | ||
644db711 DV |
12128 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
12129 | { | |
12130 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
12131 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 12132 | mode->crtc_clock, |
644db711 DV |
12133 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
12134 | mode->crtc_hsync_end, mode->crtc_htotal, | |
12135 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
12136 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
12137 | } | |
12138 | ||
c0b03411 | 12139 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
5cec258b | 12140 | struct intel_crtc_state *pipe_config, |
c0b03411 DV |
12141 | const char *context) |
12142 | { | |
6a60cd87 CK |
12143 | struct drm_device *dev = crtc->base.dev; |
12144 | struct drm_plane *plane; | |
12145 | struct intel_plane *intel_plane; | |
12146 | struct intel_plane_state *state; | |
12147 | struct drm_framebuffer *fb; | |
12148 | ||
12149 | DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id, | |
12150 | context, pipe_config, pipe_name(crtc->pipe)); | |
c0b03411 DV |
12151 | |
12152 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
12153 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
12154 | pipe_config->pipe_bpp, pipe_config->dither); | |
12155 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
12156 | pipe_config->has_pch_encoder, | |
12157 | pipe_config->fdi_lanes, | |
12158 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
12159 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
12160 | pipe_config->fdi_m_n.tu); | |
90a6b7b0 | 12161 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
eb14cb74 | 12162 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12163 | pipe_config->lane_count, |
eb14cb74 VS |
12164 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, |
12165 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
12166 | pipe_config->dp_m_n.tu); | |
b95af8be | 12167 | |
90a6b7b0 | 12168 | DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", |
b95af8be | 12169 | pipe_config->has_dp_encoder, |
90a6b7b0 | 12170 | pipe_config->lane_count, |
b95af8be VK |
12171 | pipe_config->dp_m2_n2.gmch_m, |
12172 | pipe_config->dp_m2_n2.gmch_n, | |
12173 | pipe_config->dp_m2_n2.link_m, | |
12174 | pipe_config->dp_m2_n2.link_n, | |
12175 | pipe_config->dp_m2_n2.tu); | |
12176 | ||
55072d19 DV |
12177 | DRM_DEBUG_KMS("audio: %i, infoframes: %i\n", |
12178 | pipe_config->has_audio, | |
12179 | pipe_config->has_infoframe); | |
12180 | ||
c0b03411 | 12181 | DRM_DEBUG_KMS("requested mode:\n"); |
2d112de7 | 12182 | drm_mode_debug_printmodeline(&pipe_config->base.mode); |
c0b03411 | 12183 | DRM_DEBUG_KMS("adjusted mode:\n"); |
2d112de7 ACO |
12184 | drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode); |
12185 | intel_dump_crtc_timings(&pipe_config->base.adjusted_mode); | |
d71b8d4a | 12186 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
12187 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
12188 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
0ec463d3 TU |
12189 | DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n", |
12190 | crtc->num_scalers, | |
12191 | pipe_config->scaler_state.scaler_users, | |
12192 | pipe_config->scaler_state.scaler_id); | |
c0b03411 DV |
12193 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
12194 | pipe_config->gmch_pfit.control, | |
12195 | pipe_config->gmch_pfit.pgm_ratios, | |
12196 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 12197 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 12198 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
12199 | pipe_config->pch_pfit.size, |
12200 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 12201 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 12202 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
6a60cd87 | 12203 | |
415ff0f6 | 12204 | if (IS_BROXTON(dev)) { |
05712c15 | 12205 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x," |
415ff0f6 | 12206 | "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, " |
c8453338 | 12207 | "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n", |
415ff0f6 TU |
12208 | pipe_config->ddi_pll_sel, |
12209 | pipe_config->dpll_hw_state.ebb0, | |
05712c15 | 12210 | pipe_config->dpll_hw_state.ebb4, |
415ff0f6 TU |
12211 | pipe_config->dpll_hw_state.pll0, |
12212 | pipe_config->dpll_hw_state.pll1, | |
12213 | pipe_config->dpll_hw_state.pll2, | |
12214 | pipe_config->dpll_hw_state.pll3, | |
12215 | pipe_config->dpll_hw_state.pll6, | |
12216 | pipe_config->dpll_hw_state.pll8, | |
05712c15 | 12217 | pipe_config->dpll_hw_state.pll9, |
c8453338 | 12218 | pipe_config->dpll_hw_state.pll10, |
415ff0f6 | 12219 | pipe_config->dpll_hw_state.pcsdw12); |
ef11bdb3 | 12220 | } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { |
415ff0f6 TU |
12221 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: " |
12222 | "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n", | |
12223 | pipe_config->ddi_pll_sel, | |
12224 | pipe_config->dpll_hw_state.ctrl1, | |
12225 | pipe_config->dpll_hw_state.cfgcr1, | |
12226 | pipe_config->dpll_hw_state.cfgcr2); | |
12227 | } else if (HAS_DDI(dev)) { | |
00490c22 | 12228 | DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n", |
415ff0f6 | 12229 | pipe_config->ddi_pll_sel, |
00490c22 ML |
12230 | pipe_config->dpll_hw_state.wrpll, |
12231 | pipe_config->dpll_hw_state.spll); | |
415ff0f6 TU |
12232 | } else { |
12233 | DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, " | |
12234 | "fp0: 0x%x, fp1: 0x%x\n", | |
12235 | pipe_config->dpll_hw_state.dpll, | |
12236 | pipe_config->dpll_hw_state.dpll_md, | |
12237 | pipe_config->dpll_hw_state.fp0, | |
12238 | pipe_config->dpll_hw_state.fp1); | |
12239 | } | |
12240 | ||
6a60cd87 CK |
12241 | DRM_DEBUG_KMS("planes on this crtc\n"); |
12242 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
12243 | intel_plane = to_intel_plane(plane); | |
12244 | if (intel_plane->pipe != crtc->pipe) | |
12245 | continue; | |
12246 | ||
12247 | state = to_intel_plane_state(plane->state); | |
12248 | fb = state->base.fb; | |
12249 | if (!fb) { | |
12250 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d " | |
12251 | "disabled, scaler_id = %d\n", | |
12252 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12253 | plane->base.id, intel_plane->pipe, | |
12254 | (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1, | |
12255 | drm_plane_index(plane), state->scaler_id); | |
12256 | continue; | |
12257 | } | |
12258 | ||
12259 | DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled", | |
12260 | plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD", | |
12261 | plane->base.id, intel_plane->pipe, | |
12262 | crtc->base.primary == plane ? 0 : intel_plane->plane + 1, | |
12263 | drm_plane_index(plane)); | |
12264 | DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x", | |
12265 | fb->base.id, fb->width, fb->height, fb->pixel_format); | |
12266 | DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n", | |
12267 | state->scaler_id, | |
12268 | state->src.x1 >> 16, state->src.y1 >> 16, | |
12269 | drm_rect_width(&state->src) >> 16, | |
12270 | drm_rect_height(&state->src) >> 16, | |
12271 | state->dst.x1, state->dst.y1, | |
12272 | drm_rect_width(&state->dst), drm_rect_height(&state->dst)); | |
12273 | } | |
c0b03411 DV |
12274 | } |
12275 | ||
5448a00d | 12276 | static bool check_digital_port_conflicts(struct drm_atomic_state *state) |
00f0b378 | 12277 | { |
5448a00d | 12278 | struct drm_device *dev = state->dev; |
da3ced29 | 12279 | struct drm_connector *connector; |
00f0b378 VS |
12280 | unsigned int used_ports = 0; |
12281 | ||
12282 | /* | |
12283 | * Walk the connector list instead of the encoder | |
12284 | * list to detect the problem on ddi platforms | |
12285 | * where there's just one encoder per digital port. | |
12286 | */ | |
0bff4858 VS |
12287 | drm_for_each_connector(connector, dev) { |
12288 | struct drm_connector_state *connector_state; | |
12289 | struct intel_encoder *encoder; | |
12290 | ||
12291 | connector_state = drm_atomic_get_existing_connector_state(state, connector); | |
12292 | if (!connector_state) | |
12293 | connector_state = connector->state; | |
12294 | ||
5448a00d | 12295 | if (!connector_state->best_encoder) |
00f0b378 VS |
12296 | continue; |
12297 | ||
5448a00d ACO |
12298 | encoder = to_intel_encoder(connector_state->best_encoder); |
12299 | ||
12300 | WARN_ON(!connector_state->crtc); | |
00f0b378 VS |
12301 | |
12302 | switch (encoder->type) { | |
12303 | unsigned int port_mask; | |
12304 | case INTEL_OUTPUT_UNKNOWN: | |
12305 | if (WARN_ON(!HAS_DDI(dev))) | |
12306 | break; | |
12307 | case INTEL_OUTPUT_DISPLAYPORT: | |
12308 | case INTEL_OUTPUT_HDMI: | |
12309 | case INTEL_OUTPUT_EDP: | |
12310 | port_mask = 1 << enc_to_dig_port(&encoder->base)->port; | |
12311 | ||
12312 | /* the same port mustn't appear more than once */ | |
12313 | if (used_ports & port_mask) | |
12314 | return false; | |
12315 | ||
12316 | used_ports |= port_mask; | |
12317 | default: | |
12318 | break; | |
12319 | } | |
12320 | } | |
12321 | ||
12322 | return true; | |
12323 | } | |
12324 | ||
83a57153 ACO |
12325 | static void |
12326 | clear_intel_crtc_state(struct intel_crtc_state *crtc_state) | |
12327 | { | |
12328 | struct drm_crtc_state tmp_state; | |
663a3640 | 12329 | struct intel_crtc_scaler_state scaler_state; |
4978cc93 ACO |
12330 | struct intel_dpll_hw_state dpll_hw_state; |
12331 | enum intel_dpll_id shared_dpll; | |
8504c74c | 12332 | uint32_t ddi_pll_sel; |
c4e2d043 | 12333 | bool force_thru; |
83a57153 | 12334 | |
7546a384 ACO |
12335 | /* FIXME: before the switch to atomic started, a new pipe_config was |
12336 | * kzalloc'd. Code that depends on any field being zero should be | |
12337 | * fixed, so that the crtc_state can be safely duplicated. For now, | |
12338 | * only fields that are know to not cause problems are preserved. */ | |
12339 | ||
83a57153 | 12340 | tmp_state = crtc_state->base; |
663a3640 | 12341 | scaler_state = crtc_state->scaler_state; |
4978cc93 ACO |
12342 | shared_dpll = crtc_state->shared_dpll; |
12343 | dpll_hw_state = crtc_state->dpll_hw_state; | |
8504c74c | 12344 | ddi_pll_sel = crtc_state->ddi_pll_sel; |
c4e2d043 | 12345 | force_thru = crtc_state->pch_pfit.force_thru; |
4978cc93 | 12346 | |
83a57153 | 12347 | memset(crtc_state, 0, sizeof *crtc_state); |
4978cc93 | 12348 | |
83a57153 | 12349 | crtc_state->base = tmp_state; |
663a3640 | 12350 | crtc_state->scaler_state = scaler_state; |
4978cc93 ACO |
12351 | crtc_state->shared_dpll = shared_dpll; |
12352 | crtc_state->dpll_hw_state = dpll_hw_state; | |
8504c74c | 12353 | crtc_state->ddi_pll_sel = ddi_pll_sel; |
c4e2d043 | 12354 | crtc_state->pch_pfit.force_thru = force_thru; |
83a57153 ACO |
12355 | } |
12356 | ||
548ee15b | 12357 | static int |
b8cecdf5 | 12358 | intel_modeset_pipe_config(struct drm_crtc *crtc, |
b359283a | 12359 | struct intel_crtc_state *pipe_config) |
ee7b9f93 | 12360 | { |
b359283a | 12361 | struct drm_atomic_state *state = pipe_config->base.state; |
7758a113 | 12362 | struct intel_encoder *encoder; |
da3ced29 | 12363 | struct drm_connector *connector; |
0b901879 | 12364 | struct drm_connector_state *connector_state; |
d328c9d7 | 12365 | int base_bpp, ret = -EINVAL; |
0b901879 | 12366 | int i; |
e29c22c0 | 12367 | bool retry = true; |
ee7b9f93 | 12368 | |
83a57153 | 12369 | clear_intel_crtc_state(pipe_config); |
7758a113 | 12370 | |
e143a21c DV |
12371 | pipe_config->cpu_transcoder = |
12372 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
b8cecdf5 | 12373 | |
2960bc9c ID |
12374 | /* |
12375 | * Sanitize sync polarity flags based on requested ones. If neither | |
12376 | * positive or negative polarity is requested, treat this as meaning | |
12377 | * negative polarity. | |
12378 | */ | |
2d112de7 | 12379 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12380 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) |
2d112de7 | 12381 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; |
2960bc9c | 12382 | |
2d112de7 | 12383 | if (!(pipe_config->base.adjusted_mode.flags & |
2960bc9c | 12384 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) |
2d112de7 | 12385 | pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; |
2960bc9c | 12386 | |
d328c9d7 DV |
12387 | base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), |
12388 | pipe_config); | |
12389 | if (base_bpp < 0) | |
4e53c2e0 DV |
12390 | goto fail; |
12391 | ||
e41a56be VS |
12392 | /* |
12393 | * Determine the real pipe dimensions. Note that stereo modes can | |
12394 | * increase the actual pipe size due to the frame doubling and | |
12395 | * insertion of additional space for blanks between the frame. This | |
12396 | * is stored in the crtc timings. We use the requested mode to do this | |
12397 | * computation to clearly distinguish it from the adjusted mode, which | |
12398 | * can be changed by the connectors in the below retry loop. | |
12399 | */ | |
2d112de7 | 12400 | drm_crtc_get_hv_timing(&pipe_config->base.mode, |
ecb7e16b GP |
12401 | &pipe_config->pipe_src_w, |
12402 | &pipe_config->pipe_src_h); | |
e41a56be | 12403 | |
e29c22c0 | 12404 | encoder_retry: |
ef1b460d | 12405 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 12406 | pipe_config->port_clock = 0; |
ef1b460d | 12407 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 12408 | |
135c81b8 | 12409 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
2d112de7 ACO |
12410 | drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode, |
12411 | CRTC_STEREO_DOUBLE); | |
135c81b8 | 12412 | |
7758a113 DV |
12413 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
12414 | * adjust it according to limitations or connector properties, and also | |
12415 | * a chance to reject the mode entirely. | |
47f1c6c9 | 12416 | */ |
da3ced29 | 12417 | for_each_connector_in_state(state, connector, connector_state, i) { |
0b901879 | 12418 | if (connector_state->crtc != crtc) |
7758a113 | 12419 | continue; |
7ae89233 | 12420 | |
0b901879 ACO |
12421 | encoder = to_intel_encoder(connector_state->best_encoder); |
12422 | ||
efea6e8e DV |
12423 | if (!(encoder->compute_config(encoder, pipe_config))) { |
12424 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
12425 | goto fail; |
12426 | } | |
ee7b9f93 | 12427 | } |
47f1c6c9 | 12428 | |
ff9a6750 DV |
12429 | /* Set default port clock if not overwritten by the encoder. Needs to be |
12430 | * done afterwards in case the encoder adjusts the mode. */ | |
12431 | if (!pipe_config->port_clock) | |
2d112de7 | 12432 | pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock |
241bfc38 | 12433 | * pipe_config->pixel_multiplier; |
ff9a6750 | 12434 | |
a43f6e0f | 12435 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 12436 | if (ret < 0) { |
7758a113 DV |
12437 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
12438 | goto fail; | |
ee7b9f93 | 12439 | } |
e29c22c0 DV |
12440 | |
12441 | if (ret == RETRY) { | |
12442 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
12443 | ret = -EINVAL; | |
12444 | goto fail; | |
12445 | } | |
12446 | ||
12447 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
12448 | retry = false; | |
12449 | goto encoder_retry; | |
12450 | } | |
12451 | ||
e8fa4270 DV |
12452 | /* Dithering seems to not pass-through bits correctly when it should, so |
12453 | * only enable it on 6bpc panels. */ | |
12454 | pipe_config->dither = pipe_config->pipe_bpp == 6*3; | |
62f0ace5 | 12455 | DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n", |
d328c9d7 | 12456 | base_bpp, pipe_config->pipe_bpp, pipe_config->dither); |
4e53c2e0 | 12457 | |
7758a113 | 12458 | fail: |
548ee15b | 12459 | return ret; |
ee7b9f93 | 12460 | } |
47f1c6c9 | 12461 | |
ea9d758d | 12462 | static void |
4740b0f2 | 12463 | intel_modeset_update_crtc_state(struct drm_atomic_state *state) |
ea9d758d | 12464 | { |
0a9ab303 ACO |
12465 | struct drm_crtc *crtc; |
12466 | struct drm_crtc_state *crtc_state; | |
8a75d157 | 12467 | int i; |
ea9d758d | 12468 | |
7668851f | 12469 | /* Double check state. */ |
8a75d157 | 12470 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
3cb480bc | 12471 | to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state); |
fc467a22 ML |
12472 | |
12473 | /* Update hwmode for vblank functions */ | |
12474 | if (crtc->state->active) | |
12475 | crtc->hwmode = crtc->state->adjusted_mode; | |
12476 | else | |
12477 | crtc->hwmode.crtc_clock = 0; | |
61067a5e ML |
12478 | |
12479 | /* | |
12480 | * Update legacy state to satisfy fbc code. This can | |
12481 | * be removed when fbc uses the atomic state. | |
12482 | */ | |
12483 | if (drm_atomic_get_existing_plane_state(state, crtc->primary)) { | |
12484 | struct drm_plane_state *plane_state = crtc->primary->state; | |
12485 | ||
12486 | crtc->primary->fb = plane_state->fb; | |
12487 | crtc->x = plane_state->src_x >> 16; | |
12488 | crtc->y = plane_state->src_y >> 16; | |
12489 | } | |
ea9d758d | 12490 | } |
ea9d758d DV |
12491 | } |
12492 | ||
3bd26263 | 12493 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 12494 | { |
3bd26263 | 12495 | int diff; |
f1f644dc JB |
12496 | |
12497 | if (clock1 == clock2) | |
12498 | return true; | |
12499 | ||
12500 | if (!clock1 || !clock2) | |
12501 | return false; | |
12502 | ||
12503 | diff = abs(clock1 - clock2); | |
12504 | ||
12505 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
12506 | return true; | |
12507 | ||
12508 | return false; | |
12509 | } | |
12510 | ||
25c5b266 DV |
12511 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
12512 | list_for_each_entry((intel_crtc), \ | |
12513 | &(dev)->mode_config.crtc_list, \ | |
12514 | base.head) \ | |
95150bdf | 12515 | for_each_if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 12516 | |
cfb23ed6 ML |
12517 | static bool |
12518 | intel_compare_m_n(unsigned int m, unsigned int n, | |
12519 | unsigned int m2, unsigned int n2, | |
12520 | bool exact) | |
12521 | { | |
12522 | if (m == m2 && n == n2) | |
12523 | return true; | |
12524 | ||
12525 | if (exact || !m || !n || !m2 || !n2) | |
12526 | return false; | |
12527 | ||
12528 | BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX); | |
12529 | ||
31d10b57 ML |
12530 | if (n > n2) { |
12531 | while (n > n2) { | |
cfb23ed6 ML |
12532 | m2 <<= 1; |
12533 | n2 <<= 1; | |
12534 | } | |
31d10b57 ML |
12535 | } else if (n < n2) { |
12536 | while (n < n2) { | |
cfb23ed6 ML |
12537 | m <<= 1; |
12538 | n <<= 1; | |
12539 | } | |
12540 | } | |
12541 | ||
31d10b57 ML |
12542 | if (n != n2) |
12543 | return false; | |
12544 | ||
12545 | return intel_fuzzy_clock_check(m, m2); | |
cfb23ed6 ML |
12546 | } |
12547 | ||
12548 | static bool | |
12549 | intel_compare_link_m_n(const struct intel_link_m_n *m_n, | |
12550 | struct intel_link_m_n *m2_n2, | |
12551 | bool adjust) | |
12552 | { | |
12553 | if (m_n->tu == m2_n2->tu && | |
12554 | intel_compare_m_n(m_n->gmch_m, m_n->gmch_n, | |
12555 | m2_n2->gmch_m, m2_n2->gmch_n, !adjust) && | |
12556 | intel_compare_m_n(m_n->link_m, m_n->link_n, | |
12557 | m2_n2->link_m, m2_n2->link_n, !adjust)) { | |
12558 | if (adjust) | |
12559 | *m2_n2 = *m_n; | |
12560 | ||
12561 | return true; | |
12562 | } | |
12563 | ||
12564 | return false; | |
12565 | } | |
12566 | ||
0e8ffe1b | 12567 | static bool |
2fa2fe9a | 12568 | intel_pipe_config_compare(struct drm_device *dev, |
5cec258b | 12569 | struct intel_crtc_state *current_config, |
cfb23ed6 ML |
12570 | struct intel_crtc_state *pipe_config, |
12571 | bool adjust) | |
0e8ffe1b | 12572 | { |
cfb23ed6 ML |
12573 | bool ret = true; |
12574 | ||
12575 | #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \ | |
12576 | do { \ | |
12577 | if (!adjust) \ | |
12578 | DRM_ERROR(fmt, ##__VA_ARGS__); \ | |
12579 | else \ | |
12580 | DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \ | |
12581 | } while (0) | |
12582 | ||
66e985c0 DV |
12583 | #define PIPE_CONF_CHECK_X(name) \ |
12584 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12585 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
66e985c0 DV |
12586 | "(expected 0x%08x, found 0x%08x)\n", \ |
12587 | current_config->name, \ | |
12588 | pipe_config->name); \ | |
cfb23ed6 | 12589 | ret = false; \ |
66e985c0 DV |
12590 | } |
12591 | ||
08a24034 DV |
12592 | #define PIPE_CONF_CHECK_I(name) \ |
12593 | if (current_config->name != pipe_config->name) { \ | |
cfb23ed6 | 12594 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
08a24034 DV |
12595 | "(expected %i, found %i)\n", \ |
12596 | current_config->name, \ | |
12597 | pipe_config->name); \ | |
cfb23ed6 ML |
12598 | ret = false; \ |
12599 | } | |
12600 | ||
12601 | #define PIPE_CONF_CHECK_M_N(name) \ | |
12602 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12603 | &pipe_config->name,\ | |
12604 | adjust)) { \ | |
12605 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12606 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12607 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12608 | current_config->name.tu, \ | |
12609 | current_config->name.gmch_m, \ | |
12610 | current_config->name.gmch_n, \ | |
12611 | current_config->name.link_m, \ | |
12612 | current_config->name.link_n, \ | |
12613 | pipe_config->name.tu, \ | |
12614 | pipe_config->name.gmch_m, \ | |
12615 | pipe_config->name.gmch_n, \ | |
12616 | pipe_config->name.link_m, \ | |
12617 | pipe_config->name.link_n); \ | |
12618 | ret = false; \ | |
12619 | } | |
12620 | ||
12621 | #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \ | |
12622 | if (!intel_compare_link_m_n(¤t_config->name, \ | |
12623 | &pipe_config->name, adjust) && \ | |
12624 | !intel_compare_link_m_n(¤t_config->alt_name, \ | |
12625 | &pipe_config->name, adjust)) { \ | |
12626 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ | |
12627 | "(expected tu %i gmch %i/%i link %i/%i, " \ | |
12628 | "or tu %i gmch %i/%i link %i/%i, " \ | |
12629 | "found tu %i, gmch %i/%i link %i/%i)\n", \ | |
12630 | current_config->name.tu, \ | |
12631 | current_config->name.gmch_m, \ | |
12632 | current_config->name.gmch_n, \ | |
12633 | current_config->name.link_m, \ | |
12634 | current_config->name.link_n, \ | |
12635 | current_config->alt_name.tu, \ | |
12636 | current_config->alt_name.gmch_m, \ | |
12637 | current_config->alt_name.gmch_n, \ | |
12638 | current_config->alt_name.link_m, \ | |
12639 | current_config->alt_name.link_n, \ | |
12640 | pipe_config->name.tu, \ | |
12641 | pipe_config->name.gmch_m, \ | |
12642 | pipe_config->name.gmch_n, \ | |
12643 | pipe_config->name.link_m, \ | |
12644 | pipe_config->name.link_n); \ | |
12645 | ret = false; \ | |
88adfff1 DV |
12646 | } |
12647 | ||
b95af8be VK |
12648 | /* This is required for BDW+ where there is only one set of registers for |
12649 | * switching between high and low RR. | |
12650 | * This macro can be used whenever a comparison has to be made between one | |
12651 | * hw state and multiple sw state variables. | |
12652 | */ | |
12653 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
12654 | if ((current_config->name != pipe_config->name) && \ | |
12655 | (current_config->alt_name != pipe_config->name)) { \ | |
cfb23ed6 | 12656 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
b95af8be VK |
12657 | "(expected %i or %i, found %i)\n", \ |
12658 | current_config->name, \ | |
12659 | current_config->alt_name, \ | |
12660 | pipe_config->name); \ | |
cfb23ed6 | 12661 | ret = false; \ |
b95af8be VK |
12662 | } |
12663 | ||
1bd1bd80 DV |
12664 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
12665 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
cfb23ed6 | 12666 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
12667 | "(expected %i, found %i)\n", \ |
12668 | current_config->name & (mask), \ | |
12669 | pipe_config->name & (mask)); \ | |
cfb23ed6 | 12670 | ret = false; \ |
1bd1bd80 DV |
12671 | } |
12672 | ||
5e550656 VS |
12673 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
12674 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
cfb23ed6 | 12675 | INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \ |
5e550656 VS |
12676 | "(expected %i, found %i)\n", \ |
12677 | current_config->name, \ | |
12678 | pipe_config->name); \ | |
cfb23ed6 | 12679 | ret = false; \ |
5e550656 VS |
12680 | } |
12681 | ||
bb760063 DV |
12682 | #define PIPE_CONF_QUIRK(quirk) \ |
12683 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
12684 | ||
eccb140b DV |
12685 | PIPE_CONF_CHECK_I(cpu_transcoder); |
12686 | ||
08a24034 DV |
12687 | PIPE_CONF_CHECK_I(has_pch_encoder); |
12688 | PIPE_CONF_CHECK_I(fdi_lanes); | |
cfb23ed6 | 12689 | PIPE_CONF_CHECK_M_N(fdi_m_n); |
08a24034 | 12690 | |
eb14cb74 | 12691 | PIPE_CONF_CHECK_I(has_dp_encoder); |
90a6b7b0 | 12692 | PIPE_CONF_CHECK_I(lane_count); |
b95af8be VK |
12693 | |
12694 | if (INTEL_INFO(dev)->gen < 8) { | |
cfb23ed6 ML |
12695 | PIPE_CONF_CHECK_M_N(dp_m_n); |
12696 | ||
cfb23ed6 ML |
12697 | if (current_config->has_drrs) |
12698 | PIPE_CONF_CHECK_M_N(dp_m2_n2); | |
12699 | } else | |
12700 | PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2); | |
eb14cb74 | 12701 | |
a65347ba JN |
12702 | PIPE_CONF_CHECK_I(has_dsi_encoder); |
12703 | ||
2d112de7 ACO |
12704 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay); |
12705 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal); | |
12706 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start); | |
12707 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end); | |
12708 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start); | |
12709 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end); | |
1bd1bd80 | 12710 | |
2d112de7 ACO |
12711 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay); |
12712 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal); | |
12713 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start); | |
12714 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end); | |
12715 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start); | |
12716 | PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end); | |
1bd1bd80 | 12717 | |
c93f54cf | 12718 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 12719 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 | 12720 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
666a4537 | 12721 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
b5a9fa09 | 12722 | PIPE_CONF_CHECK_I(limited_color_range); |
e43823ec | 12723 | PIPE_CONF_CHECK_I(has_infoframe); |
6c49f241 | 12724 | |
9ed109a7 DV |
12725 | PIPE_CONF_CHECK_I(has_audio); |
12726 | ||
2d112de7 | 12727 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
1bd1bd80 DV |
12728 | DRM_MODE_FLAG_INTERLACE); |
12729 | ||
bb760063 | 12730 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
2d112de7 | 12731 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12732 | DRM_MODE_FLAG_PHSYNC); |
2d112de7 | 12733 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12734 | DRM_MODE_FLAG_NHSYNC); |
2d112de7 | 12735 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 | 12736 | DRM_MODE_FLAG_PVSYNC); |
2d112de7 | 12737 | PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags, |
bb760063 DV |
12738 | DRM_MODE_FLAG_NVSYNC); |
12739 | } | |
045ac3b5 | 12740 | |
333b8ca8 | 12741 | PIPE_CONF_CHECK_X(gmch_pfit.control); |
e2ff2d4a DV |
12742 | /* pfit ratios are autocomputed by the hw on gen4+ */ |
12743 | if (INTEL_INFO(dev)->gen < 4) | |
12744 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
333b8ca8 | 12745 | PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits); |
9953599b | 12746 | |
bfd16b2a ML |
12747 | if (!adjust) { |
12748 | PIPE_CONF_CHECK_I(pipe_src_w); | |
12749 | PIPE_CONF_CHECK_I(pipe_src_h); | |
12750 | ||
12751 | PIPE_CONF_CHECK_I(pch_pfit.enabled); | |
12752 | if (current_config->pch_pfit.enabled) { | |
12753 | PIPE_CONF_CHECK_X(pch_pfit.pos); | |
12754 | PIPE_CONF_CHECK_X(pch_pfit.size); | |
12755 | } | |
2fa2fe9a | 12756 | |
7aefe2b5 ML |
12757 | PIPE_CONF_CHECK_I(scaler_state.scaler_id); |
12758 | } | |
a1b2278e | 12759 | |
e59150dc JB |
12760 | /* BDW+ don't expose a synchronous way to read the state */ |
12761 | if (IS_HASWELL(dev)) | |
12762 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 12763 | |
282740f7 VS |
12764 | PIPE_CONF_CHECK_I(double_wide); |
12765 | ||
26804afd DV |
12766 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
12767 | ||
c0d43d62 | 12768 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 12769 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 12770 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
12771 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
12772 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 12773 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
00490c22 | 12774 | PIPE_CONF_CHECK_X(dpll_hw_state.spll); |
3f4cd19f DL |
12775 | PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); |
12776 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); | |
12777 | PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); | |
c0d43d62 | 12778 | |
42571aef VS |
12779 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
12780 | PIPE_CONF_CHECK_I(pipe_bpp); | |
12781 | ||
2d112de7 | 12782 | PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock); |
a9a7e98a | 12783 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); |
5e550656 | 12784 | |
66e985c0 | 12785 | #undef PIPE_CONF_CHECK_X |
08a24034 | 12786 | #undef PIPE_CONF_CHECK_I |
b95af8be | 12787 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 12788 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 12789 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 12790 | #undef PIPE_CONF_QUIRK |
cfb23ed6 | 12791 | #undef INTEL_ERR_OR_DBG_KMS |
88adfff1 | 12792 | |
cfb23ed6 | 12793 | return ret; |
0e8ffe1b DV |
12794 | } |
12795 | ||
08db6652 DL |
12796 | static void check_wm_state(struct drm_device *dev) |
12797 | { | |
12798 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12799 | struct skl_ddb_allocation hw_ddb, *sw_ddb; | |
12800 | struct intel_crtc *intel_crtc; | |
12801 | int plane; | |
12802 | ||
12803 | if (INTEL_INFO(dev)->gen < 9) | |
12804 | return; | |
12805 | ||
12806 | skl_ddb_get_hw_state(dev_priv, &hw_ddb); | |
12807 | sw_ddb = &dev_priv->wm.skl_hw.ddb; | |
12808 | ||
12809 | for_each_intel_crtc(dev, intel_crtc) { | |
12810 | struct skl_ddb_entry *hw_entry, *sw_entry; | |
12811 | const enum pipe pipe = intel_crtc->pipe; | |
12812 | ||
12813 | if (!intel_crtc->active) | |
12814 | continue; | |
12815 | ||
12816 | /* planes */ | |
dd740780 | 12817 | for_each_plane(dev_priv, pipe, plane) { |
08db6652 DL |
12818 | hw_entry = &hw_ddb.plane[pipe][plane]; |
12819 | sw_entry = &sw_ddb->plane[pipe][plane]; | |
12820 | ||
12821 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12822 | continue; | |
12823 | ||
12824 | DRM_ERROR("mismatch in DDB state pipe %c plane %d " | |
12825 | "(expected (%u,%u), found (%u,%u))\n", | |
12826 | pipe_name(pipe), plane + 1, | |
12827 | sw_entry->start, sw_entry->end, | |
12828 | hw_entry->start, hw_entry->end); | |
12829 | } | |
12830 | ||
12831 | /* cursor */ | |
4969d33e MR |
12832 | hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR]; |
12833 | sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR]; | |
08db6652 DL |
12834 | |
12835 | if (skl_ddb_entry_equal(hw_entry, sw_entry)) | |
12836 | continue; | |
12837 | ||
12838 | DRM_ERROR("mismatch in DDB state pipe %c cursor " | |
12839 | "(expected (%u,%u), found (%u,%u))\n", | |
12840 | pipe_name(pipe), | |
12841 | sw_entry->start, sw_entry->end, | |
12842 | hw_entry->start, hw_entry->end); | |
12843 | } | |
12844 | } | |
12845 | ||
91d1b4bd | 12846 | static void |
35dd3c64 ML |
12847 | check_connector_state(struct drm_device *dev, |
12848 | struct drm_atomic_state *old_state) | |
8af6cf88 | 12849 | { |
35dd3c64 ML |
12850 | struct drm_connector_state *old_conn_state; |
12851 | struct drm_connector *connector; | |
12852 | int i; | |
8af6cf88 | 12853 | |
35dd3c64 ML |
12854 | for_each_connector_in_state(old_state, connector, old_conn_state, i) { |
12855 | struct drm_encoder *encoder = connector->encoder; | |
12856 | struct drm_connector_state *state = connector->state; | |
ad3c558f | 12857 | |
8af6cf88 DV |
12858 | /* This also checks the encoder/connector hw state with the |
12859 | * ->get_hw_state callbacks. */ | |
35dd3c64 | 12860 | intel_connector_check_state(to_intel_connector(connector)); |
8af6cf88 | 12861 | |
ad3c558f | 12862 | I915_STATE_WARN(state->best_encoder != encoder, |
35dd3c64 | 12863 | "connector's atomic encoder doesn't match legacy encoder\n"); |
8af6cf88 | 12864 | } |
91d1b4bd DV |
12865 | } |
12866 | ||
12867 | static void | |
12868 | check_encoder_state(struct drm_device *dev) | |
12869 | { | |
12870 | struct intel_encoder *encoder; | |
12871 | struct intel_connector *connector; | |
8af6cf88 | 12872 | |
b2784e15 | 12873 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 | 12874 | bool enabled = false; |
4d20cd86 | 12875 | enum pipe pipe; |
8af6cf88 DV |
12876 | |
12877 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
12878 | encoder->base.base.id, | |
8e329a03 | 12879 | encoder->base.name); |
8af6cf88 | 12880 | |
3a3371ff | 12881 | for_each_intel_connector(dev, connector) { |
4d20cd86 | 12882 | if (connector->base.state->best_encoder != &encoder->base) |
8af6cf88 DV |
12883 | continue; |
12884 | enabled = true; | |
ad3c558f ML |
12885 | |
12886 | I915_STATE_WARN(connector->base.state->crtc != | |
12887 | encoder->base.crtc, | |
12888 | "connector's crtc doesn't match encoder crtc\n"); | |
8af6cf88 | 12889 | } |
0e32b39c | 12890 | |
e2c719b7 | 12891 | I915_STATE_WARN(!!encoder->base.crtc != enabled, |
8af6cf88 DV |
12892 | "encoder's enabled state mismatch " |
12893 | "(expected %i, found %i)\n", | |
12894 | !!encoder->base.crtc, enabled); | |
7c60d198 ML |
12895 | |
12896 | if (!encoder->base.crtc) { | |
4d20cd86 | 12897 | bool active; |
7c60d198 | 12898 | |
4d20cd86 ML |
12899 | active = encoder->get_hw_state(encoder, &pipe); |
12900 | I915_STATE_WARN(active, | |
12901 | "encoder detached but still enabled on pipe %c.\n", | |
12902 | pipe_name(pipe)); | |
7c60d198 | 12903 | } |
8af6cf88 | 12904 | } |
91d1b4bd DV |
12905 | } |
12906 | ||
12907 | static void | |
4d20cd86 | 12908 | check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state) |
91d1b4bd | 12909 | { |
fbee40df | 12910 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd | 12911 | struct intel_encoder *encoder; |
4d20cd86 ML |
12912 | struct drm_crtc_state *old_crtc_state; |
12913 | struct drm_crtc *crtc; | |
12914 | int i; | |
8af6cf88 | 12915 | |
4d20cd86 ML |
12916 | for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) { |
12917 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12918 | struct intel_crtc_state *pipe_config, *sw_config; | |
7b89b8de | 12919 | bool active; |
8af6cf88 | 12920 | |
bfd16b2a ML |
12921 | if (!needs_modeset(crtc->state) && |
12922 | !to_intel_crtc_state(crtc->state)->update_pipe) | |
4d20cd86 | 12923 | continue; |
045ac3b5 | 12924 | |
4d20cd86 ML |
12925 | __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state); |
12926 | pipe_config = to_intel_crtc_state(old_crtc_state); | |
12927 | memset(pipe_config, 0, sizeof(*pipe_config)); | |
12928 | pipe_config->base.crtc = crtc; | |
12929 | pipe_config->base.state = old_state; | |
8af6cf88 | 12930 | |
4d20cd86 ML |
12931 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
12932 | crtc->base.id); | |
8af6cf88 | 12933 | |
4d20cd86 ML |
12934 | active = dev_priv->display.get_pipe_config(intel_crtc, |
12935 | pipe_config); | |
d62cf62a | 12936 | |
b6b5d049 | 12937 | /* hw state is inconsistent with the pipe quirk */ |
4d20cd86 ML |
12938 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
12939 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
12940 | active = crtc->state->active; | |
6c49f241 | 12941 | |
4d20cd86 | 12942 | I915_STATE_WARN(crtc->state->active != active, |
0e8ffe1b | 12943 | "crtc active state doesn't match with hw state " |
4d20cd86 | 12944 | "(expected %i, found %i)\n", crtc->state->active, active); |
0e8ffe1b | 12945 | |
4d20cd86 | 12946 | I915_STATE_WARN(intel_crtc->active != crtc->state->active, |
53d9f4e9 | 12947 | "transitional active state does not match atomic hw state " |
4d20cd86 ML |
12948 | "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active); |
12949 | ||
12950 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
12951 | enum pipe pipe; | |
12952 | ||
12953 | active = encoder->get_hw_state(encoder, &pipe); | |
12954 | I915_STATE_WARN(active != crtc->state->active, | |
12955 | "[ENCODER:%i] active %i with crtc active %i\n", | |
12956 | encoder->base.base.id, active, crtc->state->active); | |
12957 | ||
12958 | I915_STATE_WARN(active && intel_crtc->pipe != pipe, | |
12959 | "Encoder connected to wrong pipe %c\n", | |
12960 | pipe_name(pipe)); | |
12961 | ||
12962 | if (active) | |
12963 | encoder->get_config(encoder, pipe_config); | |
12964 | } | |
53d9f4e9 | 12965 | |
4d20cd86 | 12966 | if (!crtc->state->active) |
cfb23ed6 ML |
12967 | continue; |
12968 | ||
4d20cd86 ML |
12969 | sw_config = to_intel_crtc_state(crtc->state); |
12970 | if (!intel_pipe_config_compare(dev, sw_config, | |
12971 | pipe_config, false)) { | |
e2c719b7 | 12972 | I915_STATE_WARN(1, "pipe state doesn't match!\n"); |
4d20cd86 | 12973 | intel_dump_pipe_config(intel_crtc, pipe_config, |
c0b03411 | 12974 | "[hw state]"); |
4d20cd86 | 12975 | intel_dump_pipe_config(intel_crtc, sw_config, |
c0b03411 DV |
12976 | "[sw state]"); |
12977 | } | |
8af6cf88 DV |
12978 | } |
12979 | } | |
12980 | ||
91d1b4bd DV |
12981 | static void |
12982 | check_shared_dpll_state(struct drm_device *dev) | |
12983 | { | |
fbee40df | 12984 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
12985 | struct intel_crtc *crtc; |
12986 | struct intel_dpll_hw_state dpll_hw_state; | |
12987 | int i; | |
5358901f DV |
12988 | |
12989 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
12990 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
12991 | int enabled_crtcs = 0, active_crtcs = 0; | |
12992 | bool active; | |
12993 | ||
12994 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
12995 | ||
12996 | DRM_DEBUG_KMS("%s\n", pll->name); | |
12997 | ||
12998 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
12999 | ||
e2c719b7 | 13000 | I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask), |
5358901f | 13001 | "more active pll users than references: %i vs %i\n", |
3e369b76 | 13002 | pll->active, hweight32(pll->config.crtc_mask)); |
e2c719b7 | 13003 | I915_STATE_WARN(pll->active && !pll->on, |
5358901f | 13004 | "pll in active use but not on in sw tracking\n"); |
e2c719b7 | 13005 | I915_STATE_WARN(pll->on && !pll->active, |
35c95375 | 13006 | "pll in on but not on in use in sw tracking\n"); |
e2c719b7 | 13007 | I915_STATE_WARN(pll->on != active, |
5358901f DV |
13008 | "pll on state mismatch (expected %i, found %i)\n", |
13009 | pll->on, active); | |
13010 | ||
d3fcc808 | 13011 | for_each_intel_crtc(dev, crtc) { |
83d65738 | 13012 | if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll) |
5358901f DV |
13013 | enabled_crtcs++; |
13014 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
13015 | active_crtcs++; | |
13016 | } | |
e2c719b7 | 13017 | I915_STATE_WARN(pll->active != active_crtcs, |
5358901f DV |
13018 | "pll active crtcs mismatch (expected %i, found %i)\n", |
13019 | pll->active, active_crtcs); | |
e2c719b7 | 13020 | I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs, |
5358901f | 13021 | "pll enabled crtcs mismatch (expected %i, found %i)\n", |
3e369b76 | 13022 | hweight32(pll->config.crtc_mask), enabled_crtcs); |
66e985c0 | 13023 | |
e2c719b7 | 13024 | I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state, |
66e985c0 DV |
13025 | sizeof(dpll_hw_state)), |
13026 | "pll hw state mismatch\n"); | |
5358901f | 13027 | } |
8af6cf88 DV |
13028 | } |
13029 | ||
ee165b1a ML |
13030 | static void |
13031 | intel_modeset_check_state(struct drm_device *dev, | |
13032 | struct drm_atomic_state *old_state) | |
91d1b4bd | 13033 | { |
08db6652 | 13034 | check_wm_state(dev); |
35dd3c64 | 13035 | check_connector_state(dev, old_state); |
91d1b4bd | 13036 | check_encoder_state(dev); |
4d20cd86 | 13037 | check_crtc_state(dev, old_state); |
91d1b4bd DV |
13038 | check_shared_dpll_state(dev); |
13039 | } | |
13040 | ||
5cec258b | 13041 | void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config, |
18442d08 VS |
13042 | int dotclock) |
13043 | { | |
13044 | /* | |
13045 | * FDI already provided one idea for the dotclock. | |
13046 | * Yell if the encoder disagrees. | |
13047 | */ | |
2d112de7 | 13048 | WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock), |
18442d08 | 13049 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
2d112de7 | 13050 | pipe_config->base.adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
13051 | } |
13052 | ||
80715b2f VS |
13053 | static void update_scanline_offset(struct intel_crtc *crtc) |
13054 | { | |
13055 | struct drm_device *dev = crtc->base.dev; | |
13056 | ||
13057 | /* | |
13058 | * The scanline counter increments at the leading edge of hsync. | |
13059 | * | |
13060 | * On most platforms it starts counting from vtotal-1 on the | |
13061 | * first active line. That means the scanline counter value is | |
13062 | * always one less than what we would expect. Ie. just after | |
13063 | * start of vblank, which also occurs at start of hsync (on the | |
13064 | * last active line), the scanline counter will read vblank_start-1. | |
13065 | * | |
13066 | * On gen2 the scanline counter starts counting from 1 instead | |
13067 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
13068 | * to keep the value positive), instead of adding one. | |
13069 | * | |
13070 | * On HSW+ the behaviour of the scanline counter depends on the output | |
13071 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
13072 | * there's an extra 1 line difference. So we need to add two instead of | |
13073 | * one to the value. | |
13074 | */ | |
13075 | if (IS_GEN2(dev)) { | |
124abe07 | 13076 | const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
80715b2f VS |
13077 | int vtotal; |
13078 | ||
124abe07 VS |
13079 | vtotal = adjusted_mode->crtc_vtotal; |
13080 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) | |
80715b2f VS |
13081 | vtotal /= 2; |
13082 | ||
13083 | crtc->scanline_offset = vtotal - 1; | |
13084 | } else if (HAS_DDI(dev) && | |
409ee761 | 13085 | intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) { |
80715b2f VS |
13086 | crtc->scanline_offset = 2; |
13087 | } else | |
13088 | crtc->scanline_offset = 1; | |
13089 | } | |
13090 | ||
ad421372 | 13091 | static void intel_modeset_clear_plls(struct drm_atomic_state *state) |
ed6739ef | 13092 | { |
225da59b | 13093 | struct drm_device *dev = state->dev; |
ed6739ef | 13094 | struct drm_i915_private *dev_priv = to_i915(dev); |
ad421372 | 13095 | struct intel_shared_dpll_config *shared_dpll = NULL; |
ed6739ef | 13096 | struct intel_crtc *intel_crtc; |
0a9ab303 ACO |
13097 | struct intel_crtc_state *intel_crtc_state; |
13098 | struct drm_crtc *crtc; | |
13099 | struct drm_crtc_state *crtc_state; | |
0a9ab303 | 13100 | int i; |
ed6739ef ACO |
13101 | |
13102 | if (!dev_priv->display.crtc_compute_clock) | |
ad421372 | 13103 | return; |
ed6739ef | 13104 | |
0a9ab303 | 13105 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
ad421372 ML |
13106 | int dpll; |
13107 | ||
0a9ab303 | 13108 | intel_crtc = to_intel_crtc(crtc); |
4978cc93 | 13109 | intel_crtc_state = to_intel_crtc_state(crtc_state); |
ad421372 | 13110 | dpll = intel_crtc_state->shared_dpll; |
0a9ab303 | 13111 | |
ad421372 | 13112 | if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE) |
225da59b ACO |
13113 | continue; |
13114 | ||
ad421372 | 13115 | intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE; |
0a9ab303 | 13116 | |
ad421372 ML |
13117 | if (!shared_dpll) |
13118 | shared_dpll = intel_atomic_get_shared_dpll_state(state); | |
ed6739ef | 13119 | |
ad421372 ML |
13120 | shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe); |
13121 | } | |
ed6739ef ACO |
13122 | } |
13123 | ||
99d736a2 ML |
13124 | /* |
13125 | * This implements the workaround described in the "notes" section of the mode | |
13126 | * set sequence documentation. When going from no pipes or single pipe to | |
13127 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
13128 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
13129 | */ | |
13130 | static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state) | |
13131 | { | |
13132 | struct drm_crtc_state *crtc_state; | |
13133 | struct intel_crtc *intel_crtc; | |
13134 | struct drm_crtc *crtc; | |
13135 | struct intel_crtc_state *first_crtc_state = NULL; | |
13136 | struct intel_crtc_state *other_crtc_state = NULL; | |
13137 | enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE; | |
13138 | int i; | |
13139 | ||
13140 | /* look at all crtc's that are going to be enabled in during modeset */ | |
13141 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13142 | intel_crtc = to_intel_crtc(crtc); | |
13143 | ||
13144 | if (!crtc_state->active || !needs_modeset(crtc_state)) | |
13145 | continue; | |
13146 | ||
13147 | if (first_crtc_state) { | |
13148 | other_crtc_state = to_intel_crtc_state(crtc_state); | |
13149 | break; | |
13150 | } else { | |
13151 | first_crtc_state = to_intel_crtc_state(crtc_state); | |
13152 | first_pipe = intel_crtc->pipe; | |
13153 | } | |
13154 | } | |
13155 | ||
13156 | /* No workaround needed? */ | |
13157 | if (!first_crtc_state) | |
13158 | return 0; | |
13159 | ||
13160 | /* w/a possibly needed, check how many crtc's are already enabled. */ | |
13161 | for_each_intel_crtc(state->dev, intel_crtc) { | |
13162 | struct intel_crtc_state *pipe_config; | |
13163 | ||
13164 | pipe_config = intel_atomic_get_crtc_state(state, intel_crtc); | |
13165 | if (IS_ERR(pipe_config)) | |
13166 | return PTR_ERR(pipe_config); | |
13167 | ||
13168 | pipe_config->hsw_workaround_pipe = INVALID_PIPE; | |
13169 | ||
13170 | if (!pipe_config->base.active || | |
13171 | needs_modeset(&pipe_config->base)) | |
13172 | continue; | |
13173 | ||
13174 | /* 2 or more enabled crtcs means no need for w/a */ | |
13175 | if (enabled_pipe != INVALID_PIPE) | |
13176 | return 0; | |
13177 | ||
13178 | enabled_pipe = intel_crtc->pipe; | |
13179 | } | |
13180 | ||
13181 | if (enabled_pipe != INVALID_PIPE) | |
13182 | first_crtc_state->hsw_workaround_pipe = enabled_pipe; | |
13183 | else if (other_crtc_state) | |
13184 | other_crtc_state->hsw_workaround_pipe = first_pipe; | |
13185 | ||
13186 | return 0; | |
13187 | } | |
13188 | ||
27c329ed ML |
13189 | static int intel_modeset_all_pipes(struct drm_atomic_state *state) |
13190 | { | |
13191 | struct drm_crtc *crtc; | |
13192 | struct drm_crtc_state *crtc_state; | |
13193 | int ret = 0; | |
13194 | ||
13195 | /* add all active pipes to the state */ | |
13196 | for_each_crtc(state->dev, crtc) { | |
13197 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13198 | if (IS_ERR(crtc_state)) | |
13199 | return PTR_ERR(crtc_state); | |
13200 | ||
13201 | if (!crtc_state->active || needs_modeset(crtc_state)) | |
13202 | continue; | |
13203 | ||
13204 | crtc_state->mode_changed = true; | |
13205 | ||
13206 | ret = drm_atomic_add_affected_connectors(state, crtc); | |
13207 | if (ret) | |
13208 | break; | |
13209 | ||
13210 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13211 | if (ret) | |
13212 | break; | |
13213 | } | |
13214 | ||
13215 | return ret; | |
13216 | } | |
13217 | ||
c347a676 | 13218 | static int intel_modeset_checks(struct drm_atomic_state *state) |
054518dd | 13219 | { |
565602d7 ML |
13220 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
13221 | struct drm_i915_private *dev_priv = state->dev->dev_private; | |
13222 | struct drm_crtc *crtc; | |
13223 | struct drm_crtc_state *crtc_state; | |
13224 | int ret = 0, i; | |
054518dd | 13225 | |
b359283a ML |
13226 | if (!check_digital_port_conflicts(state)) { |
13227 | DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n"); | |
13228 | return -EINVAL; | |
13229 | } | |
13230 | ||
565602d7 ML |
13231 | intel_state->modeset = true; |
13232 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
13233 | ||
13234 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13235 | if (crtc_state->active) | |
13236 | intel_state->active_crtcs |= 1 << i; | |
13237 | else | |
13238 | intel_state->active_crtcs &= ~(1 << i); | |
13239 | } | |
13240 | ||
054518dd ACO |
13241 | /* |
13242 | * See if the config requires any additional preparation, e.g. | |
13243 | * to adjust global state with pipes off. We need to do this | |
13244 | * here so we can get the modeset_pipe updated config for the new | |
13245 | * mode set on this crtc. For other crtcs we need to use the | |
13246 | * adjusted_mode bits in the crtc directly. | |
13247 | */ | |
27c329ed | 13248 | if (dev_priv->display.modeset_calc_cdclk) { |
27c329ed ML |
13249 | ret = dev_priv->display.modeset_calc_cdclk(state); |
13250 | ||
1a617b77 | 13251 | if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq) |
27c329ed ML |
13252 | ret = intel_modeset_all_pipes(state); |
13253 | ||
13254 | if (ret < 0) | |
054518dd | 13255 | return ret; |
27c329ed | 13256 | } else |
1a617b77 | 13257 | to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq; |
054518dd | 13258 | |
ad421372 | 13259 | intel_modeset_clear_plls(state); |
054518dd | 13260 | |
565602d7 | 13261 | if (IS_HASWELL(dev_priv)) |
ad421372 | 13262 | return haswell_mode_set_planes_workaround(state); |
99d736a2 | 13263 | |
ad421372 | 13264 | return 0; |
c347a676 ACO |
13265 | } |
13266 | ||
aa363136 MR |
13267 | /* |
13268 | * Handle calculation of various watermark data at the end of the atomic check | |
13269 | * phase. The code here should be run after the per-crtc and per-plane 'check' | |
13270 | * handlers to ensure that all derived state has been updated. | |
13271 | */ | |
13272 | static void calc_watermark_data(struct drm_atomic_state *state) | |
13273 | { | |
13274 | struct drm_device *dev = state->dev; | |
13275 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
13276 | struct drm_crtc *crtc; | |
13277 | struct drm_crtc_state *cstate; | |
13278 | struct drm_plane *plane; | |
13279 | struct drm_plane_state *pstate; | |
13280 | ||
13281 | /* | |
13282 | * Calculate watermark configuration details now that derived | |
13283 | * plane/crtc state is all properly updated. | |
13284 | */ | |
13285 | drm_for_each_crtc(crtc, dev) { | |
13286 | cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?: | |
13287 | crtc->state; | |
13288 | ||
13289 | if (cstate->active) | |
13290 | intel_state->wm_config.num_pipes_active++; | |
13291 | } | |
13292 | drm_for_each_legacy_plane(plane, dev) { | |
13293 | pstate = drm_atomic_get_existing_plane_state(state, plane) ?: | |
13294 | plane->state; | |
13295 | ||
13296 | if (!to_intel_plane_state(pstate)->visible) | |
13297 | continue; | |
13298 | ||
13299 | intel_state->wm_config.sprites_enabled = true; | |
13300 | if (pstate->crtc_w != pstate->src_w >> 16 || | |
13301 | pstate->crtc_h != pstate->src_h >> 16) | |
13302 | intel_state->wm_config.sprites_scaled = true; | |
13303 | } | |
13304 | } | |
13305 | ||
74c090b1 ML |
13306 | /** |
13307 | * intel_atomic_check - validate state object | |
13308 | * @dev: drm device | |
13309 | * @state: state to validate | |
13310 | */ | |
13311 | static int intel_atomic_check(struct drm_device *dev, | |
13312 | struct drm_atomic_state *state) | |
c347a676 | 13313 | { |
dd8b3bdb | 13314 | struct drm_i915_private *dev_priv = to_i915(dev); |
aa363136 | 13315 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
c347a676 ACO |
13316 | struct drm_crtc *crtc; |
13317 | struct drm_crtc_state *crtc_state; | |
13318 | int ret, i; | |
61333b60 | 13319 | bool any_ms = false; |
c347a676 | 13320 | |
74c090b1 | 13321 | ret = drm_atomic_helper_check_modeset(dev, state); |
054518dd ACO |
13322 | if (ret) |
13323 | return ret; | |
13324 | ||
c347a676 | 13325 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
cfb23ed6 ML |
13326 | struct intel_crtc_state *pipe_config = |
13327 | to_intel_crtc_state(crtc_state); | |
1ed51de9 | 13328 | |
ba8af3e5 ML |
13329 | memset(&to_intel_crtc(crtc)->atomic, 0, |
13330 | sizeof(struct intel_crtc_atomic_commit)); | |
13331 | ||
1ed51de9 DV |
13332 | /* Catch I915_MODE_FLAG_INHERITED */ |
13333 | if (crtc_state->mode.private_flags != crtc->state->mode.private_flags) | |
13334 | crtc_state->mode_changed = true; | |
cfb23ed6 | 13335 | |
61333b60 ML |
13336 | if (!crtc_state->enable) { |
13337 | if (needs_modeset(crtc_state)) | |
13338 | any_ms = true; | |
c347a676 | 13339 | continue; |
61333b60 | 13340 | } |
c347a676 | 13341 | |
26495481 | 13342 | if (!needs_modeset(crtc_state)) |
cfb23ed6 ML |
13343 | continue; |
13344 | ||
26495481 DV |
13345 | /* FIXME: For only active_changed we shouldn't need to do any |
13346 | * state recomputation at all. */ | |
13347 | ||
1ed51de9 DV |
13348 | ret = drm_atomic_add_affected_connectors(state, crtc); |
13349 | if (ret) | |
13350 | return ret; | |
b359283a | 13351 | |
cfb23ed6 | 13352 | ret = intel_modeset_pipe_config(crtc, pipe_config); |
c347a676 ACO |
13353 | if (ret) |
13354 | return ret; | |
13355 | ||
73831236 | 13356 | if (i915.fastboot && |
dd8b3bdb | 13357 | intel_pipe_config_compare(dev, |
cfb23ed6 | 13358 | to_intel_crtc_state(crtc->state), |
1ed51de9 | 13359 | pipe_config, true)) { |
26495481 | 13360 | crtc_state->mode_changed = false; |
bfd16b2a | 13361 | to_intel_crtc_state(crtc_state)->update_pipe = true; |
26495481 DV |
13362 | } |
13363 | ||
13364 | if (needs_modeset(crtc_state)) { | |
13365 | any_ms = true; | |
cfb23ed6 ML |
13366 | |
13367 | ret = drm_atomic_add_affected_planes(state, crtc); | |
13368 | if (ret) | |
13369 | return ret; | |
13370 | } | |
61333b60 | 13371 | |
26495481 DV |
13372 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
13373 | needs_modeset(crtc_state) ? | |
13374 | "[modeset]" : "[fastset]"); | |
c347a676 ACO |
13375 | } |
13376 | ||
61333b60 ML |
13377 | if (any_ms) { |
13378 | ret = intel_modeset_checks(state); | |
13379 | ||
13380 | if (ret) | |
13381 | return ret; | |
27c329ed | 13382 | } else |
dd8b3bdb | 13383 | intel_state->cdclk = dev_priv->cdclk_freq; |
76305b1a | 13384 | |
dd8b3bdb | 13385 | ret = drm_atomic_helper_check_planes(dev, state); |
aa363136 MR |
13386 | if (ret) |
13387 | return ret; | |
13388 | ||
f51be2e0 | 13389 | intel_fbc_choose_crtc(dev_priv, state); |
aa363136 MR |
13390 | calc_watermark_data(state); |
13391 | ||
13392 | return 0; | |
054518dd ACO |
13393 | } |
13394 | ||
5008e874 ML |
13395 | static int intel_atomic_prepare_commit(struct drm_device *dev, |
13396 | struct drm_atomic_state *state, | |
13397 | bool async) | |
13398 | { | |
7580d774 ML |
13399 | struct drm_i915_private *dev_priv = dev->dev_private; |
13400 | struct drm_plane_state *plane_state; | |
5008e874 | 13401 | struct drm_crtc_state *crtc_state; |
7580d774 | 13402 | struct drm_plane *plane; |
5008e874 ML |
13403 | struct drm_crtc *crtc; |
13404 | int i, ret; | |
13405 | ||
13406 | if (async) { | |
13407 | DRM_DEBUG_KMS("i915 does not yet support async commit\n"); | |
13408 | return -EINVAL; | |
13409 | } | |
13410 | ||
13411 | for_each_crtc_in_state(state, crtc, crtc_state, i) { | |
13412 | ret = intel_crtc_wait_for_pending_flips(crtc); | |
13413 | if (ret) | |
13414 | return ret; | |
7580d774 ML |
13415 | |
13416 | if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2) | |
13417 | flush_workqueue(dev_priv->wq); | |
5008e874 ML |
13418 | } |
13419 | ||
f935675f ML |
13420 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
13421 | if (ret) | |
13422 | return ret; | |
13423 | ||
5008e874 | 13424 | ret = drm_atomic_helper_prepare_planes(dev, state); |
7580d774 ML |
13425 | if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) { |
13426 | u32 reset_counter; | |
13427 | ||
13428 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); | |
13429 | mutex_unlock(&dev->struct_mutex); | |
13430 | ||
13431 | for_each_plane_in_state(state, plane, plane_state, i) { | |
13432 | struct intel_plane_state *intel_plane_state = | |
13433 | to_intel_plane_state(plane_state); | |
13434 | ||
13435 | if (!intel_plane_state->wait_req) | |
13436 | continue; | |
13437 | ||
13438 | ret = __i915_wait_request(intel_plane_state->wait_req, | |
13439 | reset_counter, true, | |
13440 | NULL, NULL); | |
13441 | ||
13442 | /* Swallow -EIO errors to allow updates during hw lockup. */ | |
13443 | if (ret == -EIO) | |
13444 | ret = 0; | |
13445 | ||
13446 | if (ret) | |
13447 | break; | |
13448 | } | |
13449 | ||
13450 | if (!ret) | |
13451 | return 0; | |
13452 | ||
13453 | mutex_lock(&dev->struct_mutex); | |
13454 | drm_atomic_helper_cleanup_planes(dev, state); | |
13455 | } | |
5008e874 | 13456 | |
f935675f | 13457 | mutex_unlock(&dev->struct_mutex); |
5008e874 ML |
13458 | return ret; |
13459 | } | |
13460 | ||
74c090b1 ML |
13461 | /** |
13462 | * intel_atomic_commit - commit validated state object | |
13463 | * @dev: DRM device | |
13464 | * @state: the top-level driver state object | |
13465 | * @async: asynchronous commit | |
13466 | * | |
13467 | * This function commits a top-level state object that has been validated | |
13468 | * with drm_atomic_helper_check(). | |
13469 | * | |
13470 | * FIXME: Atomic modeset support for i915 is not yet complete. At the moment | |
13471 | * we can only handle plane-related operations and do not yet support | |
13472 | * asynchronous commit. | |
13473 | * | |
13474 | * RETURNS | |
13475 | * Zero for success or -errno. | |
13476 | */ | |
13477 | static int intel_atomic_commit(struct drm_device *dev, | |
13478 | struct drm_atomic_state *state, | |
13479 | bool async) | |
a6778b3c | 13480 | { |
565602d7 | 13481 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
fbee40df | 13482 | struct drm_i915_private *dev_priv = dev->dev_private; |
0a9ab303 | 13483 | struct drm_crtc_state *crtc_state; |
7580d774 | 13484 | struct drm_crtc *crtc; |
565602d7 ML |
13485 | int ret = 0, i; |
13486 | bool hw_check = intel_state->modeset; | |
a6778b3c | 13487 | |
5008e874 | 13488 | ret = intel_atomic_prepare_commit(dev, state, async); |
7580d774 ML |
13489 | if (ret) { |
13490 | DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret); | |
d4afb8cc | 13491 | return ret; |
7580d774 | 13492 | } |
d4afb8cc | 13493 | |
1c5e19f8 | 13494 | drm_atomic_helper_swap_state(dev, state); |
aa363136 | 13495 | dev_priv->wm.config = to_intel_atomic_state(state)->wm_config; |
1c5e19f8 | 13496 | |
565602d7 ML |
13497 | if (intel_state->modeset) { |
13498 | memcpy(dev_priv->min_pixclk, intel_state->min_pixclk, | |
13499 | sizeof(intel_state->min_pixclk)); | |
13500 | dev_priv->active_crtcs = intel_state->active_crtcs; | |
1a617b77 | 13501 | dev_priv->atomic_cdclk_freq = intel_state->cdclk; |
565602d7 ML |
13502 | } |
13503 | ||
0a9ab303 | 13504 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
a539205a ML |
13505 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13506 | ||
61333b60 ML |
13507 | if (!needs_modeset(crtc->state)) |
13508 | continue; | |
13509 | ||
5c74cd73 | 13510 | intel_pre_plane_update(to_intel_crtc_state(crtc_state)); |
460da916 | 13511 | |
a539205a ML |
13512 | if (crtc_state->active) { |
13513 | intel_crtc_disable_planes(crtc, crtc_state->plane_mask); | |
13514 | dev_priv->display.crtc_disable(crtc); | |
eddfcbcd | 13515 | intel_crtc->active = false; |
58f9c0bc | 13516 | intel_fbc_disable(intel_crtc); |
eddfcbcd | 13517 | intel_disable_shared_dpll(intel_crtc); |
9bbc8258 VS |
13518 | |
13519 | /* | |
13520 | * Underruns don't always raise | |
13521 | * interrupts, so check manually. | |
13522 | */ | |
13523 | intel_check_cpu_fifo_underruns(dev_priv); | |
13524 | intel_check_pch_fifo_underruns(dev_priv); | |
b9001114 ML |
13525 | |
13526 | if (!crtc->state->active) | |
13527 | intel_update_watermarks(crtc); | |
a539205a | 13528 | } |
b8cecdf5 | 13529 | } |
7758a113 | 13530 | |
ea9d758d DV |
13531 | /* Only after disabling all output pipelines that will be changed can we |
13532 | * update the the output configuration. */ | |
4740b0f2 | 13533 | intel_modeset_update_crtc_state(state); |
f6e5b160 | 13534 | |
565602d7 | 13535 | if (intel_state->modeset) { |
4740b0f2 ML |
13536 | intel_shared_dpll_commit(state); |
13537 | ||
13538 | drm_atomic_helper_update_legacy_modeset_state(state->dev, state); | |
61333b60 | 13539 | modeset_update_crtc_power_domains(state); |
4740b0f2 | 13540 | } |
47fab737 | 13541 | |
a6778b3c | 13542 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ |
0a9ab303 | 13543 | for_each_crtc_in_state(state, crtc, crtc_state, i) { |
f6ac4b2a ML |
13544 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
13545 | bool modeset = needs_modeset(crtc->state); | |
bfd16b2a ML |
13546 | bool update_pipe = !modeset && |
13547 | to_intel_crtc_state(crtc->state)->update_pipe; | |
13548 | unsigned long put_domains = 0; | |
f6ac4b2a | 13549 | |
9f836f90 PJ |
13550 | if (modeset) |
13551 | intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET); | |
13552 | ||
f6ac4b2a | 13553 | if (modeset && crtc->state->active) { |
a539205a ML |
13554 | update_scanline_offset(to_intel_crtc(crtc)); |
13555 | dev_priv->display.crtc_enable(crtc); | |
13556 | } | |
80715b2f | 13557 | |
bfd16b2a ML |
13558 | if (update_pipe) { |
13559 | put_domains = modeset_get_crtc_power_domains(crtc); | |
13560 | ||
13561 | /* make sure intel_modeset_check_state runs */ | |
565602d7 | 13562 | hw_check = true; |
bfd16b2a ML |
13563 | } |
13564 | ||
f6ac4b2a | 13565 | if (!modeset) |
5c74cd73 | 13566 | intel_pre_plane_update(to_intel_crtc_state(crtc_state)); |
f6ac4b2a | 13567 | |
49227c4a PZ |
13568 | if (crtc->state->active && intel_crtc->atomic.update_fbc) |
13569 | intel_fbc_enable(intel_crtc); | |
13570 | ||
6173ee28 ML |
13571 | if (crtc->state->active && |
13572 | (crtc->state->planes_changed || update_pipe)) | |
62852622 | 13573 | drm_atomic_helper_commit_planes_on_crtc(crtc_state); |
bfd16b2a ML |
13574 | |
13575 | if (put_domains) | |
13576 | modeset_put_power_domains(dev_priv, put_domains); | |
13577 | ||
f6ac4b2a | 13578 | intel_post_plane_update(intel_crtc); |
9f836f90 PJ |
13579 | |
13580 | if (modeset) | |
13581 | intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET); | |
80715b2f | 13582 | } |
a6778b3c | 13583 | |
a6778b3c | 13584 | /* FIXME: add subpixel order */ |
83a57153 | 13585 | |
74c090b1 | 13586 | drm_atomic_helper_wait_for_vblanks(dev, state); |
f935675f ML |
13587 | |
13588 | mutex_lock(&dev->struct_mutex); | |
d4afb8cc | 13589 | drm_atomic_helper_cleanup_planes(dev, state); |
f935675f | 13590 | mutex_unlock(&dev->struct_mutex); |
2bfb4627 | 13591 | |
565602d7 | 13592 | if (hw_check) |
ee165b1a ML |
13593 | intel_modeset_check_state(dev, state); |
13594 | ||
13595 | drm_atomic_state_free(state); | |
f30da187 | 13596 | |
75714940 MK |
13597 | /* As one of the primary mmio accessors, KMS has a high likelihood |
13598 | * of triggering bugs in unclaimed access. After we finish | |
13599 | * modesetting, see if an error has been flagged, and if so | |
13600 | * enable debugging for the next modeset - and hope we catch | |
13601 | * the culprit. | |
13602 | * | |
13603 | * XXX note that we assume display power is on at this point. | |
13604 | * This might hold true now but we need to add pm helper to check | |
13605 | * unclaimed only when the hardware is on, as atomic commits | |
13606 | * can happen also when the device is completely off. | |
13607 | */ | |
13608 | intel_uncore_arm_unclaimed_mmio_detection(dev_priv); | |
13609 | ||
74c090b1 | 13610 | return 0; |
7f27126e JB |
13611 | } |
13612 | ||
c0c36b94 CW |
13613 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
13614 | { | |
83a57153 ACO |
13615 | struct drm_device *dev = crtc->dev; |
13616 | struct drm_atomic_state *state; | |
e694eb02 | 13617 | struct drm_crtc_state *crtc_state; |
2bfb4627 | 13618 | int ret; |
83a57153 ACO |
13619 | |
13620 | state = drm_atomic_state_alloc(dev); | |
13621 | if (!state) { | |
e694eb02 | 13622 | DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory", |
83a57153 ACO |
13623 | crtc->base.id); |
13624 | return; | |
13625 | } | |
13626 | ||
e694eb02 | 13627 | state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc); |
83a57153 | 13628 | |
e694eb02 ML |
13629 | retry: |
13630 | crtc_state = drm_atomic_get_crtc_state(state, crtc); | |
13631 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
13632 | if (!ret) { | |
13633 | if (!crtc_state->active) | |
13634 | goto out; | |
83a57153 | 13635 | |
e694eb02 | 13636 | crtc_state->mode_changed = true; |
74c090b1 | 13637 | ret = drm_atomic_commit(state); |
83a57153 ACO |
13638 | } |
13639 | ||
e694eb02 ML |
13640 | if (ret == -EDEADLK) { |
13641 | drm_atomic_state_clear(state); | |
13642 | drm_modeset_backoff(state->acquire_ctx); | |
13643 | goto retry; | |
4ed9fb37 | 13644 | } |
4be07317 | 13645 | |
2bfb4627 | 13646 | if (ret) |
e694eb02 | 13647 | out: |
2bfb4627 | 13648 | drm_atomic_state_free(state); |
c0c36b94 CW |
13649 | } |
13650 | ||
25c5b266 DV |
13651 | #undef for_each_intel_crtc_masked |
13652 | ||
f6e5b160 | 13653 | static const struct drm_crtc_funcs intel_crtc_funcs = { |
f6e5b160 | 13654 | .gamma_set = intel_crtc_gamma_set, |
74c090b1 | 13655 | .set_config = drm_atomic_helper_set_config, |
f6e5b160 CW |
13656 | .destroy = intel_crtc_destroy, |
13657 | .page_flip = intel_crtc_page_flip, | |
1356837e MR |
13658 | .atomic_duplicate_state = intel_crtc_duplicate_state, |
13659 | .atomic_destroy_state = intel_crtc_destroy_state, | |
f6e5b160 CW |
13660 | }; |
13661 | ||
5358901f DV |
13662 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
13663 | struct intel_shared_dpll *pll, | |
13664 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 13665 | { |
5358901f | 13666 | uint32_t val; |
ee7b9f93 | 13667 | |
f458ebbc | 13668 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
bd2bb1b9 PZ |
13669 | return false; |
13670 | ||
5358901f | 13671 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
13672 | hw_state->dpll = val; |
13673 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
13674 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
13675 | |
13676 | return val & DPLL_VCO_ENABLE; | |
13677 | } | |
13678 | ||
15bdd4cf DV |
13679 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
13680 | struct intel_shared_dpll *pll) | |
13681 | { | |
3e369b76 ACO |
13682 | I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0); |
13683 | I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1); | |
15bdd4cf DV |
13684 | } |
13685 | ||
e7b903d2 DV |
13686 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
13687 | struct intel_shared_dpll *pll) | |
13688 | { | |
e7b903d2 | 13689 | /* PCH refclock must be enabled first */ |
89eff4be | 13690 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 13691 | |
3e369b76 | 13692 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf DV |
13693 | |
13694 | /* Wait for the clocks to stabilize. */ | |
13695 | POSTING_READ(PCH_DPLL(pll->id)); | |
13696 | udelay(150); | |
13697 | ||
13698 | /* The pixel multiplier can only be updated once the | |
13699 | * DPLL is enabled and the clocks are stable. | |
13700 | * | |
13701 | * So write it again. | |
13702 | */ | |
3e369b76 | 13703 | I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll); |
15bdd4cf | 13704 | POSTING_READ(PCH_DPLL(pll->id)); |
e7b903d2 DV |
13705 | udelay(200); |
13706 | } | |
13707 | ||
13708 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
13709 | struct intel_shared_dpll *pll) | |
13710 | { | |
13711 | struct drm_device *dev = dev_priv->dev; | |
13712 | struct intel_crtc *crtc; | |
e7b903d2 DV |
13713 | |
13714 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 13715 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
13716 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
13717 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
13718 | } |
13719 | ||
15bdd4cf DV |
13720 | I915_WRITE(PCH_DPLL(pll->id), 0); |
13721 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
13722 | udelay(200); |
13723 | } | |
13724 | ||
46edb027 DV |
13725 | static char *ibx_pch_dpll_names[] = { |
13726 | "PCH DPLL A", | |
13727 | "PCH DPLL B", | |
13728 | }; | |
13729 | ||
7c74ade1 | 13730 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 13731 | { |
e7b903d2 | 13732 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
13733 | int i; |
13734 | ||
7c74ade1 | 13735 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 13736 | |
e72f9fbf | 13737 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
13738 | dev_priv->shared_dplls[i].id = i; |
13739 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 13740 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
13741 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
13742 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
13743 | dev_priv->shared_dplls[i].get_hw_state = |
13744 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
13745 | } |
13746 | } | |
13747 | ||
7c74ade1 DV |
13748 | static void intel_shared_dpll_init(struct drm_device *dev) |
13749 | { | |
e7b903d2 | 13750 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 13751 | |
9cd86933 DV |
13752 | if (HAS_DDI(dev)) |
13753 | intel_ddi_pll_init(dev); | |
13754 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
13755 | ibx_pch_dpll_init(dev); |
13756 | else | |
13757 | dev_priv->num_shared_dpll = 0; | |
13758 | ||
13759 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
13760 | } |
13761 | ||
6beb8c23 MR |
13762 | /** |
13763 | * intel_prepare_plane_fb - Prepare fb for usage on plane | |
13764 | * @plane: drm plane to prepare for | |
13765 | * @fb: framebuffer to prepare for presentation | |
13766 | * | |
13767 | * Prepares a framebuffer for usage on a display plane. Generally this | |
13768 | * involves pinning the underlying object and updating the frontbuffer tracking | |
13769 | * bits. Some older platforms need special physical address handling for | |
13770 | * cursor planes. | |
13771 | * | |
f935675f ML |
13772 | * Must be called with struct_mutex held. |
13773 | * | |
6beb8c23 MR |
13774 | * Returns 0 on success, negative error code on failure. |
13775 | */ | |
13776 | int | |
13777 | intel_prepare_plane_fb(struct drm_plane *plane, | |
d136dfee | 13778 | const struct drm_plane_state *new_state) |
465c120c MR |
13779 | { |
13780 | struct drm_device *dev = plane->dev; | |
844f9111 | 13781 | struct drm_framebuffer *fb = new_state->fb; |
6beb8c23 | 13782 | struct intel_plane *intel_plane = to_intel_plane(plane); |
6beb8c23 | 13783 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
1ee49399 | 13784 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); |
6beb8c23 | 13785 | int ret = 0; |
465c120c | 13786 | |
1ee49399 | 13787 | if (!obj && !old_obj) |
465c120c MR |
13788 | return 0; |
13789 | ||
5008e874 ML |
13790 | if (old_obj) { |
13791 | struct drm_crtc_state *crtc_state = | |
13792 | drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc); | |
13793 | ||
13794 | /* Big Hammer, we also need to ensure that any pending | |
13795 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
13796 | * current scanout is retired before unpinning the old | |
13797 | * framebuffer. Note that we rely on userspace rendering | |
13798 | * into the buffer attached to the pipe they are waiting | |
13799 | * on. If not, userspace generates a GPU hang with IPEHR | |
13800 | * point to the MI_WAIT_FOR_EVENT. | |
13801 | * | |
13802 | * This should only fail upon a hung GPU, in which case we | |
13803 | * can safely continue. | |
13804 | */ | |
13805 | if (needs_modeset(crtc_state)) | |
13806 | ret = i915_gem_object_wait_rendering(old_obj, true); | |
13807 | ||
13808 | /* Swallow -EIO errors to allow updates during hw lockup. */ | |
13809 | if (ret && ret != -EIO) | |
f935675f | 13810 | return ret; |
5008e874 ML |
13811 | } |
13812 | ||
3c28ff22 AG |
13813 | /* For framebuffer backed by dmabuf, wait for fence */ |
13814 | if (obj && obj->base.dma_buf) { | |
bcf8be27 ML |
13815 | long lret; |
13816 | ||
13817 | lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv, | |
13818 | false, true, | |
13819 | MAX_SCHEDULE_TIMEOUT); | |
13820 | if (lret == -ERESTARTSYS) | |
13821 | return lret; | |
3c28ff22 | 13822 | |
bcf8be27 | 13823 | WARN(lret < 0, "waiting returns %li\n", lret); |
3c28ff22 AG |
13824 | } |
13825 | ||
1ee49399 ML |
13826 | if (!obj) { |
13827 | ret = 0; | |
13828 | } else if (plane->type == DRM_PLANE_TYPE_CURSOR && | |
6beb8c23 MR |
13829 | INTEL_INFO(dev)->cursor_needs_physical) { |
13830 | int align = IS_I830(dev) ? 16 * 1024 : 256; | |
13831 | ret = i915_gem_object_attach_phys(obj, align); | |
13832 | if (ret) | |
13833 | DRM_DEBUG_KMS("failed to attach phys object\n"); | |
13834 | } else { | |
7580d774 | 13835 | ret = intel_pin_and_fence_fb_obj(plane, fb, new_state); |
6beb8c23 | 13836 | } |
465c120c | 13837 | |
7580d774 ML |
13838 | if (ret == 0) { |
13839 | if (obj) { | |
13840 | struct intel_plane_state *plane_state = | |
13841 | to_intel_plane_state(new_state); | |
13842 | ||
13843 | i915_gem_request_assign(&plane_state->wait_req, | |
13844 | obj->last_write_req); | |
13845 | } | |
13846 | ||
a9ff8714 | 13847 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); |
7580d774 | 13848 | } |
fdd508a6 | 13849 | |
6beb8c23 MR |
13850 | return ret; |
13851 | } | |
13852 | ||
38f3ce3a MR |
13853 | /** |
13854 | * intel_cleanup_plane_fb - Cleans up an fb after plane use | |
13855 | * @plane: drm plane to clean up for | |
13856 | * @fb: old framebuffer that was on plane | |
13857 | * | |
13858 | * Cleans up a framebuffer that has just been removed from a plane. | |
f935675f ML |
13859 | * |
13860 | * Must be called with struct_mutex held. | |
38f3ce3a MR |
13861 | */ |
13862 | void | |
13863 | intel_cleanup_plane_fb(struct drm_plane *plane, | |
d136dfee | 13864 | const struct drm_plane_state *old_state) |
38f3ce3a MR |
13865 | { |
13866 | struct drm_device *dev = plane->dev; | |
1ee49399 | 13867 | struct intel_plane *intel_plane = to_intel_plane(plane); |
7580d774 | 13868 | struct intel_plane_state *old_intel_state; |
1ee49399 ML |
13869 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb); |
13870 | struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb); | |
38f3ce3a | 13871 | |
7580d774 ML |
13872 | old_intel_state = to_intel_plane_state(old_state); |
13873 | ||
1ee49399 | 13874 | if (!obj && !old_obj) |
38f3ce3a MR |
13875 | return; |
13876 | ||
1ee49399 ML |
13877 | if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR || |
13878 | !INTEL_INFO(dev)->cursor_needs_physical)) | |
844f9111 | 13879 | intel_unpin_fb_obj(old_state->fb, old_state); |
1ee49399 ML |
13880 | |
13881 | /* prepare_fb aborted? */ | |
13882 | if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) || | |
13883 | (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit))) | |
13884 | i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit); | |
7580d774 ML |
13885 | |
13886 | i915_gem_request_assign(&old_intel_state->wait_req, NULL); | |
13887 | ||
465c120c MR |
13888 | } |
13889 | ||
6156a456 CK |
13890 | int |
13891 | skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state) | |
13892 | { | |
13893 | int max_scale; | |
13894 | struct drm_device *dev; | |
13895 | struct drm_i915_private *dev_priv; | |
13896 | int crtc_clock, cdclk; | |
13897 | ||
bf8a0af0 | 13898 | if (!intel_crtc || !crtc_state->base.enable) |
6156a456 CK |
13899 | return DRM_PLANE_HELPER_NO_SCALING; |
13900 | ||
13901 | dev = intel_crtc->base.dev; | |
13902 | dev_priv = dev->dev_private; | |
13903 | crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; | |
27c329ed | 13904 | cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk; |
6156a456 | 13905 | |
54bf1ce6 | 13906 | if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock)) |
6156a456 CK |
13907 | return DRM_PLANE_HELPER_NO_SCALING; |
13908 | ||
13909 | /* | |
13910 | * skl max scale is lower of: | |
13911 | * close to 3 but not 3, -1 is for that purpose | |
13912 | * or | |
13913 | * cdclk/crtc_clock | |
13914 | */ | |
13915 | max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock)); | |
13916 | ||
13917 | return max_scale; | |
13918 | } | |
13919 | ||
465c120c | 13920 | static int |
3c692a41 | 13921 | intel_check_primary_plane(struct drm_plane *plane, |
061e4b8d | 13922 | struct intel_crtc_state *crtc_state, |
3c692a41 GP |
13923 | struct intel_plane_state *state) |
13924 | { | |
2b875c22 MR |
13925 | struct drm_crtc *crtc = state->base.crtc; |
13926 | struct drm_framebuffer *fb = state->base.fb; | |
6156a456 | 13927 | int min_scale = DRM_PLANE_HELPER_NO_SCALING; |
061e4b8d ML |
13928 | int max_scale = DRM_PLANE_HELPER_NO_SCALING; |
13929 | bool can_position = false; | |
465c120c | 13930 | |
693bdc28 VS |
13931 | if (INTEL_INFO(plane->dev)->gen >= 9) { |
13932 | /* use scaler when colorkey is not required */ | |
13933 | if (state->ckey.flags == I915_SET_COLORKEY_NONE) { | |
13934 | min_scale = 1; | |
13935 | max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state); | |
13936 | } | |
d8106366 | 13937 | can_position = true; |
6156a456 | 13938 | } |
d8106366 | 13939 | |
061e4b8d ML |
13940 | return drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
13941 | &state->dst, &state->clip, | |
da20eabd ML |
13942 | min_scale, max_scale, |
13943 | can_position, true, | |
13944 | &state->visible); | |
14af293f GP |
13945 | } |
13946 | ||
613d2b27 ML |
13947 | static void intel_begin_crtc_commit(struct drm_crtc *crtc, |
13948 | struct drm_crtc_state *old_crtc_state) | |
3c692a41 | 13949 | { |
32b7eeec | 13950 | struct drm_device *dev = crtc->dev; |
3c692a41 | 13951 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
bfd16b2a ML |
13952 | struct intel_crtc_state *old_intel_state = |
13953 | to_intel_crtc_state(old_crtc_state); | |
13954 | bool modeset = needs_modeset(crtc->state); | |
3c692a41 | 13955 | |
c34c9ee4 | 13956 | /* Perform vblank evasion around commit operation */ |
62852622 | 13957 | intel_pipe_update_start(intel_crtc); |
0583236e | 13958 | |
bfd16b2a ML |
13959 | if (modeset) |
13960 | return; | |
13961 | ||
13962 | if (to_intel_crtc_state(crtc->state)->update_pipe) | |
13963 | intel_update_pipe_config(intel_crtc, old_intel_state); | |
13964 | else if (INTEL_INFO(dev)->gen >= 9) | |
0583236e | 13965 | skl_detach_scalers(intel_crtc); |
32b7eeec MR |
13966 | } |
13967 | ||
613d2b27 ML |
13968 | static void intel_finish_crtc_commit(struct drm_crtc *crtc, |
13969 | struct drm_crtc_state *old_crtc_state) | |
32b7eeec | 13970 | { |
32b7eeec | 13971 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
32b7eeec | 13972 | |
62852622 | 13973 | intel_pipe_update_end(intel_crtc); |
3c692a41 GP |
13974 | } |
13975 | ||
cf4c7c12 | 13976 | /** |
4a3b8769 MR |
13977 | * intel_plane_destroy - destroy a plane |
13978 | * @plane: plane to destroy | |
cf4c7c12 | 13979 | * |
4a3b8769 MR |
13980 | * Common destruction function for all types of planes (primary, cursor, |
13981 | * sprite). | |
cf4c7c12 | 13982 | */ |
4a3b8769 | 13983 | void intel_plane_destroy(struct drm_plane *plane) |
465c120c MR |
13984 | { |
13985 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
13986 | drm_plane_cleanup(plane); | |
13987 | kfree(intel_plane); | |
13988 | } | |
13989 | ||
65a3fea0 | 13990 | const struct drm_plane_funcs intel_plane_funcs = { |
70a101f8 MR |
13991 | .update_plane = drm_atomic_helper_update_plane, |
13992 | .disable_plane = drm_atomic_helper_disable_plane, | |
3d7d6510 | 13993 | .destroy = intel_plane_destroy, |
c196e1d6 | 13994 | .set_property = drm_atomic_helper_plane_set_property, |
a98b3431 MR |
13995 | .atomic_get_property = intel_plane_atomic_get_property, |
13996 | .atomic_set_property = intel_plane_atomic_set_property, | |
ea2c67bb MR |
13997 | .atomic_duplicate_state = intel_plane_duplicate_state, |
13998 | .atomic_destroy_state = intel_plane_destroy_state, | |
13999 | ||
465c120c MR |
14000 | }; |
14001 | ||
14002 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
14003 | int pipe) | |
14004 | { | |
14005 | struct intel_plane *primary; | |
8e7d688b | 14006 | struct intel_plane_state *state; |
465c120c | 14007 | const uint32_t *intel_primary_formats; |
45e3743a | 14008 | unsigned int num_formats; |
465c120c MR |
14009 | |
14010 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
14011 | if (primary == NULL) | |
14012 | return NULL; | |
14013 | ||
8e7d688b MR |
14014 | state = intel_create_plane_state(&primary->base); |
14015 | if (!state) { | |
ea2c67bb MR |
14016 | kfree(primary); |
14017 | return NULL; | |
14018 | } | |
8e7d688b | 14019 | primary->base.state = &state->base; |
ea2c67bb | 14020 | |
465c120c MR |
14021 | primary->can_scale = false; |
14022 | primary->max_downscale = 1; | |
6156a456 CK |
14023 | if (INTEL_INFO(dev)->gen >= 9) { |
14024 | primary->can_scale = true; | |
af99ceda | 14025 | state->scaler_id = -1; |
6156a456 | 14026 | } |
465c120c MR |
14027 | primary->pipe = pipe; |
14028 | primary->plane = pipe; | |
a9ff8714 | 14029 | primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); |
c59cb179 | 14030 | primary->check_plane = intel_check_primary_plane; |
465c120c MR |
14031 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
14032 | primary->plane = !pipe; | |
14033 | ||
6c0fd451 DL |
14034 | if (INTEL_INFO(dev)->gen >= 9) { |
14035 | intel_primary_formats = skl_primary_formats; | |
14036 | num_formats = ARRAY_SIZE(skl_primary_formats); | |
a8d201af ML |
14037 | |
14038 | primary->update_plane = skylake_update_primary_plane; | |
14039 | primary->disable_plane = skylake_disable_primary_plane; | |
14040 | } else if (HAS_PCH_SPLIT(dev)) { | |
14041 | intel_primary_formats = i965_primary_formats; | |
14042 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
14043 | ||
14044 | primary->update_plane = ironlake_update_primary_plane; | |
14045 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 | 14046 | } else if (INTEL_INFO(dev)->gen >= 4) { |
568db4f2 DL |
14047 | intel_primary_formats = i965_primary_formats; |
14048 | num_formats = ARRAY_SIZE(i965_primary_formats); | |
a8d201af ML |
14049 | |
14050 | primary->update_plane = i9xx_update_primary_plane; | |
14051 | primary->disable_plane = i9xx_disable_primary_plane; | |
6c0fd451 DL |
14052 | } else { |
14053 | intel_primary_formats = i8xx_primary_formats; | |
14054 | num_formats = ARRAY_SIZE(i8xx_primary_formats); | |
a8d201af ML |
14055 | |
14056 | primary->update_plane = i9xx_update_primary_plane; | |
14057 | primary->disable_plane = i9xx_disable_primary_plane; | |
465c120c MR |
14058 | } |
14059 | ||
14060 | drm_universal_plane_init(dev, &primary->base, 0, | |
65a3fea0 | 14061 | &intel_plane_funcs, |
465c120c | 14062 | intel_primary_formats, num_formats, |
b0b3b795 | 14063 | DRM_PLANE_TYPE_PRIMARY, NULL); |
48404c1e | 14064 | |
3b7a5119 SJ |
14065 | if (INTEL_INFO(dev)->gen >= 4) |
14066 | intel_create_rotation_property(dev, primary); | |
48404c1e | 14067 | |
ea2c67bb MR |
14068 | drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs); |
14069 | ||
465c120c MR |
14070 | return &primary->base; |
14071 | } | |
14072 | ||
3b7a5119 SJ |
14073 | void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane) |
14074 | { | |
14075 | if (!dev->mode_config.rotation_property) { | |
14076 | unsigned long flags = BIT(DRM_ROTATE_0) | | |
14077 | BIT(DRM_ROTATE_180); | |
14078 | ||
14079 | if (INTEL_INFO(dev)->gen >= 9) | |
14080 | flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270); | |
14081 | ||
14082 | dev->mode_config.rotation_property = | |
14083 | drm_mode_create_rotation_property(dev, flags); | |
14084 | } | |
14085 | if (dev->mode_config.rotation_property) | |
14086 | drm_object_attach_property(&plane->base.base, | |
14087 | dev->mode_config.rotation_property, | |
14088 | plane->base.state->rotation); | |
14089 | } | |
14090 | ||
3d7d6510 | 14091 | static int |
852e787c | 14092 | intel_check_cursor_plane(struct drm_plane *plane, |
061e4b8d | 14093 | struct intel_crtc_state *crtc_state, |
852e787c | 14094 | struct intel_plane_state *state) |
3d7d6510 | 14095 | { |
061e4b8d | 14096 | struct drm_crtc *crtc = crtc_state->base.crtc; |
2b875c22 | 14097 | struct drm_framebuffer *fb = state->base.fb; |
757f9a3e | 14098 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
b29ec92c | 14099 | enum pipe pipe = to_intel_plane(plane)->pipe; |
757f9a3e GP |
14100 | unsigned stride; |
14101 | int ret; | |
3d7d6510 | 14102 | |
061e4b8d ML |
14103 | ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src, |
14104 | &state->dst, &state->clip, | |
3d7d6510 MR |
14105 | DRM_PLANE_HELPER_NO_SCALING, |
14106 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c | 14107 | true, true, &state->visible); |
757f9a3e GP |
14108 | if (ret) |
14109 | return ret; | |
14110 | ||
757f9a3e GP |
14111 | /* if we want to turn off the cursor ignore width and height */ |
14112 | if (!obj) | |
da20eabd | 14113 | return 0; |
757f9a3e | 14114 | |
757f9a3e | 14115 | /* Check for which cursor types we support */ |
061e4b8d | 14116 | if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) { |
ea2c67bb MR |
14117 | DRM_DEBUG("Cursor dimension %dx%d not supported\n", |
14118 | state->base.crtc_w, state->base.crtc_h); | |
757f9a3e GP |
14119 | return -EINVAL; |
14120 | } | |
14121 | ||
ea2c67bb MR |
14122 | stride = roundup_pow_of_two(state->base.crtc_w) * 4; |
14123 | if (obj->base.size < stride * state->base.crtc_h) { | |
757f9a3e GP |
14124 | DRM_DEBUG_KMS("buffer is too small\n"); |
14125 | return -ENOMEM; | |
14126 | } | |
14127 | ||
3a656b54 | 14128 | if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) { |
757f9a3e | 14129 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
da20eabd | 14130 | return -EINVAL; |
32b7eeec MR |
14131 | } |
14132 | ||
b29ec92c VS |
14133 | /* |
14134 | * There's something wrong with the cursor on CHV pipe C. | |
14135 | * If it straddles the left edge of the screen then | |
14136 | * moving it away from the edge or disabling it often | |
14137 | * results in a pipe underrun, and often that can lead to | |
14138 | * dead pipe (constant underrun reported, and it scans | |
14139 | * out just a solid color). To recover from that, the | |
14140 | * display power well must be turned off and on again. | |
14141 | * Refuse the put the cursor into that compromised position. | |
14142 | */ | |
14143 | if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C && | |
14144 | state->visible && state->base.crtc_x < 0) { | |
14145 | DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n"); | |
14146 | return -EINVAL; | |
14147 | } | |
14148 | ||
da20eabd | 14149 | return 0; |
852e787c | 14150 | } |
3d7d6510 | 14151 | |
a8ad0d8e ML |
14152 | static void |
14153 | intel_disable_cursor_plane(struct drm_plane *plane, | |
7fabf5ef | 14154 | struct drm_crtc *crtc) |
a8ad0d8e | 14155 | { |
f2858021 ML |
14156 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
14157 | ||
14158 | intel_crtc->cursor_addr = 0; | |
55a08b3f | 14159 | intel_crtc_update_cursor(crtc, NULL); |
a8ad0d8e ML |
14160 | } |
14161 | ||
f4a2cf29 | 14162 | static void |
55a08b3f ML |
14163 | intel_update_cursor_plane(struct drm_plane *plane, |
14164 | const struct intel_crtc_state *crtc_state, | |
14165 | const struct intel_plane_state *state) | |
852e787c | 14166 | { |
55a08b3f ML |
14167 | struct drm_crtc *crtc = crtc_state->base.crtc; |
14168 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ea2c67bb | 14169 | struct drm_device *dev = plane->dev; |
2b875c22 | 14170 | struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb); |
a912f12f | 14171 | uint32_t addr; |
852e787c | 14172 | |
f4a2cf29 | 14173 | if (!obj) |
a912f12f | 14174 | addr = 0; |
f4a2cf29 | 14175 | else if (!INTEL_INFO(dev)->cursor_needs_physical) |
a912f12f | 14176 | addr = i915_gem_obj_ggtt_offset(obj); |
f4a2cf29 | 14177 | else |
a912f12f | 14178 | addr = obj->phys_handle->busaddr; |
852e787c | 14179 | |
a912f12f | 14180 | intel_crtc->cursor_addr = addr; |
55a08b3f | 14181 | intel_crtc_update_cursor(crtc, state); |
852e787c GP |
14182 | } |
14183 | ||
3d7d6510 MR |
14184 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, |
14185 | int pipe) | |
14186 | { | |
14187 | struct intel_plane *cursor; | |
8e7d688b | 14188 | struct intel_plane_state *state; |
3d7d6510 MR |
14189 | |
14190 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
14191 | if (cursor == NULL) | |
14192 | return NULL; | |
14193 | ||
8e7d688b MR |
14194 | state = intel_create_plane_state(&cursor->base); |
14195 | if (!state) { | |
ea2c67bb MR |
14196 | kfree(cursor); |
14197 | return NULL; | |
14198 | } | |
8e7d688b | 14199 | cursor->base.state = &state->base; |
ea2c67bb | 14200 | |
3d7d6510 MR |
14201 | cursor->can_scale = false; |
14202 | cursor->max_downscale = 1; | |
14203 | cursor->pipe = pipe; | |
14204 | cursor->plane = pipe; | |
a9ff8714 | 14205 | cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe); |
c59cb179 | 14206 | cursor->check_plane = intel_check_cursor_plane; |
55a08b3f | 14207 | cursor->update_plane = intel_update_cursor_plane; |
a8ad0d8e | 14208 | cursor->disable_plane = intel_disable_cursor_plane; |
3d7d6510 MR |
14209 | |
14210 | drm_universal_plane_init(dev, &cursor->base, 0, | |
65a3fea0 | 14211 | &intel_plane_funcs, |
3d7d6510 MR |
14212 | intel_cursor_formats, |
14213 | ARRAY_SIZE(intel_cursor_formats), | |
b0b3b795 | 14214 | DRM_PLANE_TYPE_CURSOR, NULL); |
4398ad45 VS |
14215 | |
14216 | if (INTEL_INFO(dev)->gen >= 4) { | |
14217 | if (!dev->mode_config.rotation_property) | |
14218 | dev->mode_config.rotation_property = | |
14219 | drm_mode_create_rotation_property(dev, | |
14220 | BIT(DRM_ROTATE_0) | | |
14221 | BIT(DRM_ROTATE_180)); | |
14222 | if (dev->mode_config.rotation_property) | |
14223 | drm_object_attach_property(&cursor->base.base, | |
14224 | dev->mode_config.rotation_property, | |
8e7d688b | 14225 | state->base.rotation); |
4398ad45 VS |
14226 | } |
14227 | ||
af99ceda CK |
14228 | if (INTEL_INFO(dev)->gen >=9) |
14229 | state->scaler_id = -1; | |
14230 | ||
ea2c67bb MR |
14231 | drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs); |
14232 | ||
3d7d6510 MR |
14233 | return &cursor->base; |
14234 | } | |
14235 | ||
549e2bfb CK |
14236 | static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc, |
14237 | struct intel_crtc_state *crtc_state) | |
14238 | { | |
14239 | int i; | |
14240 | struct intel_scaler *intel_scaler; | |
14241 | struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state; | |
14242 | ||
14243 | for (i = 0; i < intel_crtc->num_scalers; i++) { | |
14244 | intel_scaler = &scaler_state->scalers[i]; | |
14245 | intel_scaler->in_use = 0; | |
549e2bfb CK |
14246 | intel_scaler->mode = PS_SCALER_MODE_DYN; |
14247 | } | |
14248 | ||
14249 | scaler_state->scaler_id = -1; | |
14250 | } | |
14251 | ||
b358d0a6 | 14252 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 14253 | { |
fbee40df | 14254 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 14255 | struct intel_crtc *intel_crtc; |
f5de6e07 | 14256 | struct intel_crtc_state *crtc_state = NULL; |
3d7d6510 MR |
14257 | struct drm_plane *primary = NULL; |
14258 | struct drm_plane *cursor = NULL; | |
465c120c | 14259 | int i, ret; |
79e53945 | 14260 | |
955382f3 | 14261 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
14262 | if (intel_crtc == NULL) |
14263 | return; | |
14264 | ||
f5de6e07 ACO |
14265 | crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL); |
14266 | if (!crtc_state) | |
14267 | goto fail; | |
550acefd ACO |
14268 | intel_crtc->config = crtc_state; |
14269 | intel_crtc->base.state = &crtc_state->base; | |
07878248 | 14270 | crtc_state->base.crtc = &intel_crtc->base; |
f5de6e07 | 14271 | |
549e2bfb CK |
14272 | /* initialize shared scalers */ |
14273 | if (INTEL_INFO(dev)->gen >= 9) { | |
14274 | if (pipe == PIPE_C) | |
14275 | intel_crtc->num_scalers = 1; | |
14276 | else | |
14277 | intel_crtc->num_scalers = SKL_NUM_SCALERS; | |
14278 | ||
14279 | skl_init_scalers(dev, intel_crtc, crtc_state); | |
14280 | } | |
14281 | ||
465c120c | 14282 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
14283 | if (!primary) |
14284 | goto fail; | |
14285 | ||
14286 | cursor = intel_cursor_plane_create(dev, pipe); | |
14287 | if (!cursor) | |
14288 | goto fail; | |
14289 | ||
465c120c | 14290 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
f9882876 | 14291 | cursor, &intel_crtc_funcs, NULL); |
3d7d6510 MR |
14292 | if (ret) |
14293 | goto fail; | |
79e53945 JB |
14294 | |
14295 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
14296 | for (i = 0; i < 256; i++) { |
14297 | intel_crtc->lut_r[i] = i; | |
14298 | intel_crtc->lut_g[i] = i; | |
14299 | intel_crtc->lut_b[i] = i; | |
14300 | } | |
14301 | ||
1f1c2e24 VS |
14302 | /* |
14303 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 14304 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 14305 | */ |
80824003 JB |
14306 | intel_crtc->pipe = pipe; |
14307 | intel_crtc->plane = pipe; | |
3a77c4c4 | 14308 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 14309 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 14310 | intel_crtc->plane = !pipe; |
80824003 JB |
14311 | } |
14312 | ||
4b0e333e CW |
14313 | intel_crtc->cursor_base = ~0; |
14314 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 14315 | intel_crtc->cursor_size = ~0; |
8d7849db | 14316 | |
852eb00d VS |
14317 | intel_crtc->wm.cxsr_allowed = true; |
14318 | ||
22fd0fab JB |
14319 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
14320 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
14321 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
14322 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
14323 | ||
79e53945 | 14324 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
14325 | |
14326 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
14327 | return; |
14328 | ||
14329 | fail: | |
14330 | if (primary) | |
14331 | drm_plane_cleanup(primary); | |
14332 | if (cursor) | |
14333 | drm_plane_cleanup(cursor); | |
f5de6e07 | 14334 | kfree(crtc_state); |
3d7d6510 | 14335 | kfree(intel_crtc); |
79e53945 JB |
14336 | } |
14337 | ||
752aa88a JB |
14338 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
14339 | { | |
14340 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 14341 | struct drm_device *dev = connector->base.dev; |
752aa88a | 14342 | |
51fd371b | 14343 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a | 14344 | |
d3babd3f | 14345 | if (!encoder || WARN_ON(!encoder->crtc)) |
752aa88a JB |
14346 | return INVALID_PIPE; |
14347 | ||
14348 | return to_intel_crtc(encoder->crtc)->pipe; | |
14349 | } | |
14350 | ||
08d7b3d1 | 14351 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 14352 | struct drm_file *file) |
08d7b3d1 | 14353 | { |
08d7b3d1 | 14354 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 14355 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 14356 | struct intel_crtc *crtc; |
08d7b3d1 | 14357 | |
7707e653 | 14358 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 14359 | |
7707e653 | 14360 | if (!drmmode_crtc) { |
08d7b3d1 | 14361 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 14362 | return -ENOENT; |
08d7b3d1 CW |
14363 | } |
14364 | ||
7707e653 | 14365 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 14366 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 14367 | |
c05422d5 | 14368 | return 0; |
08d7b3d1 CW |
14369 | } |
14370 | ||
66a9278e | 14371 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 14372 | { |
66a9278e DV |
14373 | struct drm_device *dev = encoder->base.dev; |
14374 | struct intel_encoder *source_encoder; | |
79e53945 | 14375 | int index_mask = 0; |
79e53945 JB |
14376 | int entry = 0; |
14377 | ||
b2784e15 | 14378 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 14379 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
14380 | index_mask |= (1 << entry); |
14381 | ||
79e53945 JB |
14382 | entry++; |
14383 | } | |
4ef69c7a | 14384 | |
79e53945 JB |
14385 | return index_mask; |
14386 | } | |
14387 | ||
4d302442 CW |
14388 | static bool has_edp_a(struct drm_device *dev) |
14389 | { | |
14390 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14391 | ||
14392 | if (!IS_MOBILE(dev)) | |
14393 | return false; | |
14394 | ||
14395 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
14396 | return false; | |
14397 | ||
e3589908 | 14398 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
14399 | return false; |
14400 | ||
14401 | return true; | |
14402 | } | |
14403 | ||
84b4e042 JB |
14404 | static bool intel_crt_present(struct drm_device *dev) |
14405 | { | |
14406 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14407 | ||
884497ed DL |
14408 | if (INTEL_INFO(dev)->gen >= 9) |
14409 | return false; | |
14410 | ||
cf404ce4 | 14411 | if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
84b4e042 JB |
14412 | return false; |
14413 | ||
14414 | if (IS_CHERRYVIEW(dev)) | |
14415 | return false; | |
14416 | ||
65e472e4 VS |
14417 | if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED) |
14418 | return false; | |
14419 | ||
70ac54d0 VS |
14420 | /* DDI E can't be used if DDI A requires 4 lanes */ |
14421 | if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) | |
14422 | return false; | |
14423 | ||
e4abb733 | 14424 | if (!dev_priv->vbt.int_crt_support) |
84b4e042 JB |
14425 | return false; |
14426 | ||
14427 | return true; | |
14428 | } | |
14429 | ||
79e53945 JB |
14430 | static void intel_setup_outputs(struct drm_device *dev) |
14431 | { | |
725e30ad | 14432 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 14433 | struct intel_encoder *encoder; |
cb0953d7 | 14434 | bool dpd_is_edp = false; |
79e53945 | 14435 | |
c9093354 | 14436 | intel_lvds_init(dev); |
79e53945 | 14437 | |
84b4e042 | 14438 | if (intel_crt_present(dev)) |
79935fca | 14439 | intel_crt_init(dev); |
cb0953d7 | 14440 | |
c776eb2e VK |
14441 | if (IS_BROXTON(dev)) { |
14442 | /* | |
14443 | * FIXME: Broxton doesn't support port detection via the | |
14444 | * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to | |
14445 | * detect the ports. | |
14446 | */ | |
14447 | intel_ddi_init(dev, PORT_A); | |
14448 | intel_ddi_init(dev, PORT_B); | |
14449 | intel_ddi_init(dev, PORT_C); | |
14450 | } else if (HAS_DDI(dev)) { | |
0e72a5b5 ED |
14451 | int found; |
14452 | ||
de31facd JB |
14453 | /* |
14454 | * Haswell uses DDI functions to detect digital outputs. | |
14455 | * On SKL pre-D0 the strap isn't connected, so we assume | |
14456 | * it's there. | |
14457 | */ | |
77179400 | 14458 | found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED; |
de31facd | 14459 | /* WaIgnoreDDIAStrap: skl */ |
ef11bdb3 | 14460 | if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
0e72a5b5 ED |
14461 | intel_ddi_init(dev, PORT_A); |
14462 | ||
14463 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
14464 | * register */ | |
14465 | found = I915_READ(SFUSE_STRAP); | |
14466 | ||
14467 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
14468 | intel_ddi_init(dev, PORT_B); | |
14469 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
14470 | intel_ddi_init(dev, PORT_C); | |
14471 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
14472 | intel_ddi_init(dev, PORT_D); | |
2800e4c2 RV |
14473 | /* |
14474 | * On SKL we don't have a way to detect DDI-E so we rely on VBT. | |
14475 | */ | |
ef11bdb3 | 14476 | if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) && |
2800e4c2 RV |
14477 | (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp || |
14478 | dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi || | |
14479 | dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi)) | |
14480 | intel_ddi_init(dev, PORT_E); | |
14481 | ||
0e72a5b5 | 14482 | } else if (HAS_PCH_SPLIT(dev)) { |
cb0953d7 | 14483 | int found; |
5d8a7752 | 14484 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
14485 | |
14486 | if (has_edp_a(dev)) | |
14487 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 14488 | |
dc0fa718 | 14489 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 14490 | /* PCH SDVOB multiplex with HDMIB */ |
2a5c0832 | 14491 | found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B); |
30ad48b7 | 14492 | if (!found) |
e2debe91 | 14493 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 14494 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 14495 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
14496 | } |
14497 | ||
dc0fa718 | 14498 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 14499 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 14500 | |
dc0fa718 | 14501 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 14502 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 14503 | |
5eb08b69 | 14504 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 14505 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 14506 | |
270b3042 | 14507 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 14508 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
666a4537 | 14509 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
e17ac6db VS |
14510 | /* |
14511 | * The DP_DETECTED bit is the latched state of the DDC | |
14512 | * SDA pin at boot. However since eDP doesn't require DDC | |
14513 | * (no way to plug in a DP->HDMI dongle) the DDC pins for | |
14514 | * eDP ports may have been muxed to an alternate function. | |
14515 | * Thus we can't rely on the DP_DETECTED bit alone to detect | |
14516 | * eDP ports. Consult the VBT as well as DP_DETECTED to | |
14517 | * detect eDP ports. | |
14518 | */ | |
e66eb81d | 14519 | if (I915_READ(VLV_HDMIB) & SDVO_DETECTED && |
d2182a66 | 14520 | !intel_dp_is_edp(dev, PORT_B)) |
e66eb81d VS |
14521 | intel_hdmi_init(dev, VLV_HDMIB, PORT_B); |
14522 | if (I915_READ(VLV_DP_B) & DP_DETECTED || | |
e17ac6db | 14523 | intel_dp_is_edp(dev, PORT_B)) |
e66eb81d | 14524 | intel_dp_init(dev, VLV_DP_B, PORT_B); |
585a94b8 | 14525 | |
e66eb81d | 14526 | if (I915_READ(VLV_HDMIC) & SDVO_DETECTED && |
d2182a66 | 14527 | !intel_dp_is_edp(dev, PORT_C)) |
e66eb81d VS |
14528 | intel_hdmi_init(dev, VLV_HDMIC, PORT_C); |
14529 | if (I915_READ(VLV_DP_C) & DP_DETECTED || | |
e17ac6db | 14530 | intel_dp_is_edp(dev, PORT_C)) |
e66eb81d | 14531 | intel_dp_init(dev, VLV_DP_C, PORT_C); |
19c03924 | 14532 | |
9418c1f1 | 14533 | if (IS_CHERRYVIEW(dev)) { |
e17ac6db | 14534 | /* eDP not supported on port D, so don't check VBT */ |
e66eb81d VS |
14535 | if (I915_READ(CHV_HDMID) & SDVO_DETECTED) |
14536 | intel_hdmi_init(dev, CHV_HDMID, PORT_D); | |
14537 | if (I915_READ(CHV_DP_D) & DP_DETECTED) | |
14538 | intel_dp_init(dev, CHV_DP_D, PORT_D); | |
9418c1f1 VS |
14539 | } |
14540 | ||
3cfca973 | 14541 | intel_dsi_init(dev); |
09da55dc | 14542 | } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) { |
27185ae1 | 14543 | bool found = false; |
7d57382e | 14544 | |
e2debe91 | 14545 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14546 | DRM_DEBUG_KMS("probing SDVOB\n"); |
2a5c0832 | 14547 | found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B); |
3fec3d2f | 14548 | if (!found && IS_G4X(dev)) { |
b01f2c3a | 14549 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); |
e2debe91 | 14550 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 14551 | } |
27185ae1 | 14552 | |
3fec3d2f | 14553 | if (!found && IS_G4X(dev)) |
ab9d7c30 | 14554 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 14555 | } |
13520b05 KH |
14556 | |
14557 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 14558 | |
e2debe91 | 14559 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 14560 | DRM_DEBUG_KMS("probing SDVOC\n"); |
2a5c0832 | 14561 | found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C); |
b01f2c3a | 14562 | } |
27185ae1 | 14563 | |
e2debe91 | 14564 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 14565 | |
3fec3d2f | 14566 | if (IS_G4X(dev)) { |
b01f2c3a | 14567 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); |
e2debe91 | 14568 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 14569 | } |
3fec3d2f | 14570 | if (IS_G4X(dev)) |
ab9d7c30 | 14571 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 14572 | } |
27185ae1 | 14573 | |
3fec3d2f | 14574 | if (IS_G4X(dev) && |
e7281eab | 14575 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 14576 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 14577 | } else if (IS_GEN2(dev)) |
79e53945 JB |
14578 | intel_dvo_init(dev); |
14579 | ||
103a196f | 14580 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
14581 | intel_tv_init(dev); |
14582 | ||
0bc12bcb | 14583 | intel_psr_init(dev); |
7c8f8a70 | 14584 | |
b2784e15 | 14585 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
14586 | encoder->base.possible_crtcs = encoder->crtc_mask; |
14587 | encoder->base.possible_clones = | |
66a9278e | 14588 | intel_encoder_clones(encoder); |
79e53945 | 14589 | } |
47356eb6 | 14590 | |
dde86e2d | 14591 | intel_init_pch_refclk(dev); |
270b3042 DV |
14592 | |
14593 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
14594 | } |
14595 | ||
14596 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
14597 | { | |
60a5ca01 | 14598 | struct drm_device *dev = fb->dev; |
79e53945 | 14599 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 14600 | |
ef2d633e | 14601 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 14602 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 14603 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
14604 | drm_gem_object_unreference(&intel_fb->obj->base); |
14605 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
14606 | kfree(intel_fb); |
14607 | } | |
14608 | ||
14609 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 14610 | struct drm_file *file, |
79e53945 JB |
14611 | unsigned int *handle) |
14612 | { | |
14613 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 14614 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 14615 | |
cc917ab4 CW |
14616 | if (obj->userptr.mm) { |
14617 | DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n"); | |
14618 | return -EINVAL; | |
14619 | } | |
14620 | ||
05394f39 | 14621 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
14622 | } |
14623 | ||
86c98588 RV |
14624 | static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb, |
14625 | struct drm_file *file, | |
14626 | unsigned flags, unsigned color, | |
14627 | struct drm_clip_rect *clips, | |
14628 | unsigned num_clips) | |
14629 | { | |
14630 | struct drm_device *dev = fb->dev; | |
14631 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
14632 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
14633 | ||
14634 | mutex_lock(&dev->struct_mutex); | |
74b4ea1e | 14635 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); |
86c98588 RV |
14636 | mutex_unlock(&dev->struct_mutex); |
14637 | ||
14638 | return 0; | |
14639 | } | |
14640 | ||
79e53945 JB |
14641 | static const struct drm_framebuffer_funcs intel_fb_funcs = { |
14642 | .destroy = intel_user_framebuffer_destroy, | |
14643 | .create_handle = intel_user_framebuffer_create_handle, | |
86c98588 | 14644 | .dirty = intel_user_framebuffer_dirty, |
79e53945 JB |
14645 | }; |
14646 | ||
b321803d DL |
14647 | static |
14648 | u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier, | |
14649 | uint32_t pixel_format) | |
14650 | { | |
14651 | u32 gen = INTEL_INFO(dev)->gen; | |
14652 | ||
14653 | if (gen >= 9) { | |
ac484963 VS |
14654 | int cpp = drm_format_plane_cpp(pixel_format, 0); |
14655 | ||
b321803d DL |
14656 | /* "The stride in bytes must not exceed the of the size of 8K |
14657 | * pixels and 32K bytes." | |
14658 | */ | |
ac484963 | 14659 | return min(8192 * cpp, 32768); |
666a4537 | 14660 | } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
b321803d DL |
14661 | return 32*1024; |
14662 | } else if (gen >= 4) { | |
14663 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14664 | return 16*1024; | |
14665 | else | |
14666 | return 32*1024; | |
14667 | } else if (gen >= 3) { | |
14668 | if (fb_modifier == I915_FORMAT_MOD_X_TILED) | |
14669 | return 8*1024; | |
14670 | else | |
14671 | return 16*1024; | |
14672 | } else { | |
14673 | /* XXX DSPC is limited to 4k tiled */ | |
14674 | return 8*1024; | |
14675 | } | |
14676 | } | |
14677 | ||
b5ea642a DV |
14678 | static int intel_framebuffer_init(struct drm_device *dev, |
14679 | struct intel_framebuffer *intel_fb, | |
14680 | struct drm_mode_fb_cmd2 *mode_cmd, | |
14681 | struct drm_i915_gem_object *obj) | |
79e53945 | 14682 | { |
7b49f948 | 14683 | struct drm_i915_private *dev_priv = to_i915(dev); |
6761dd31 | 14684 | unsigned int aligned_height; |
79e53945 | 14685 | int ret; |
b321803d | 14686 | u32 pitch_limit, stride_alignment; |
79e53945 | 14687 | |
dd4916c5 DV |
14688 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
14689 | ||
2a80eada DV |
14690 | if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) { |
14691 | /* Enforce that fb modifier and tiling mode match, but only for | |
14692 | * X-tiled. This is needed for FBC. */ | |
14693 | if (!!(obj->tiling_mode == I915_TILING_X) != | |
14694 | !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) { | |
14695 | DRM_DEBUG("tiling_mode doesn't match fb modifier\n"); | |
14696 | return -EINVAL; | |
14697 | } | |
14698 | } else { | |
14699 | if (obj->tiling_mode == I915_TILING_X) | |
14700 | mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED; | |
14701 | else if (obj->tiling_mode == I915_TILING_Y) { | |
14702 | DRM_DEBUG("No Y tiling for legacy addfb\n"); | |
14703 | return -EINVAL; | |
14704 | } | |
14705 | } | |
14706 | ||
9a8f0a12 TU |
14707 | /* Passed in modifier sanity checking. */ |
14708 | switch (mode_cmd->modifier[0]) { | |
14709 | case I915_FORMAT_MOD_Y_TILED: | |
14710 | case I915_FORMAT_MOD_Yf_TILED: | |
14711 | if (INTEL_INFO(dev)->gen < 9) { | |
14712 | DRM_DEBUG("Unsupported tiling 0x%llx!\n", | |
14713 | mode_cmd->modifier[0]); | |
14714 | return -EINVAL; | |
14715 | } | |
14716 | case DRM_FORMAT_MOD_NONE: | |
14717 | case I915_FORMAT_MOD_X_TILED: | |
14718 | break; | |
14719 | default: | |
c0f40428 JB |
14720 | DRM_DEBUG("Unsupported fb modifier 0x%llx!\n", |
14721 | mode_cmd->modifier[0]); | |
57cd6508 | 14722 | return -EINVAL; |
c16ed4be | 14723 | } |
57cd6508 | 14724 | |
7b49f948 VS |
14725 | stride_alignment = intel_fb_stride_alignment(dev_priv, |
14726 | mode_cmd->modifier[0], | |
b321803d DL |
14727 | mode_cmd->pixel_format); |
14728 | if (mode_cmd->pitches[0] & (stride_alignment - 1)) { | |
14729 | DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n", | |
14730 | mode_cmd->pitches[0], stride_alignment); | |
57cd6508 | 14731 | return -EINVAL; |
c16ed4be | 14732 | } |
57cd6508 | 14733 | |
b321803d DL |
14734 | pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0], |
14735 | mode_cmd->pixel_format); | |
a35cdaa0 | 14736 | if (mode_cmd->pitches[0] > pitch_limit) { |
b321803d DL |
14737 | DRM_DEBUG("%s pitch (%u) must be at less than %d\n", |
14738 | mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ? | |
2a80eada | 14739 | "tiled" : "linear", |
a35cdaa0 | 14740 | mode_cmd->pitches[0], pitch_limit); |
5d7bd705 | 14741 | return -EINVAL; |
c16ed4be | 14742 | } |
5d7bd705 | 14743 | |
2a80eada | 14744 | if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED && |
c16ed4be CW |
14745 | mode_cmd->pitches[0] != obj->stride) { |
14746 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
14747 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 14748 | return -EINVAL; |
c16ed4be | 14749 | } |
5d7bd705 | 14750 | |
57779d06 | 14751 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 14752 | switch (mode_cmd->pixel_format) { |
57779d06 | 14753 | case DRM_FORMAT_C8: |
04b3924d VS |
14754 | case DRM_FORMAT_RGB565: |
14755 | case DRM_FORMAT_XRGB8888: | |
14756 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
14757 | break; |
14758 | case DRM_FORMAT_XRGB1555: | |
c16ed4be | 14759 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
14760 | DRM_DEBUG("unsupported pixel format: %s\n", |
14761 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14762 | return -EINVAL; |
c16ed4be | 14763 | } |
57779d06 | 14764 | break; |
57779d06 | 14765 | case DRM_FORMAT_ABGR8888: |
666a4537 WB |
14766 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && |
14767 | INTEL_INFO(dev)->gen < 9) { | |
6c0fd451 DL |
14768 | DRM_DEBUG("unsupported pixel format: %s\n", |
14769 | drm_get_format_name(mode_cmd->pixel_format)); | |
14770 | return -EINVAL; | |
14771 | } | |
14772 | break; | |
14773 | case DRM_FORMAT_XBGR8888: | |
04b3924d | 14774 | case DRM_FORMAT_XRGB2101010: |
57779d06 | 14775 | case DRM_FORMAT_XBGR2101010: |
c16ed4be | 14776 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
14777 | DRM_DEBUG("unsupported pixel format: %s\n", |
14778 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14779 | return -EINVAL; |
c16ed4be | 14780 | } |
b5626747 | 14781 | break; |
7531208b | 14782 | case DRM_FORMAT_ABGR2101010: |
666a4537 | 14783 | if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
7531208b DL |
14784 | DRM_DEBUG("unsupported pixel format: %s\n", |
14785 | drm_get_format_name(mode_cmd->pixel_format)); | |
14786 | return -EINVAL; | |
14787 | } | |
14788 | break; | |
04b3924d VS |
14789 | case DRM_FORMAT_YUYV: |
14790 | case DRM_FORMAT_UYVY: | |
14791 | case DRM_FORMAT_YVYU: | |
14792 | case DRM_FORMAT_VYUY: | |
c16ed4be | 14793 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
14794 | DRM_DEBUG("unsupported pixel format: %s\n", |
14795 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 14796 | return -EINVAL; |
c16ed4be | 14797 | } |
57cd6508 CW |
14798 | break; |
14799 | default: | |
4ee62c76 VS |
14800 | DRM_DEBUG("unsupported pixel format: %s\n", |
14801 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
14802 | return -EINVAL; |
14803 | } | |
14804 | ||
90f9a336 VS |
14805 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
14806 | if (mode_cmd->offsets[0] != 0) | |
14807 | return -EINVAL; | |
14808 | ||
ec2c981e | 14809 | aligned_height = intel_fb_align_height(dev, mode_cmd->height, |
091df6cb DV |
14810 | mode_cmd->pixel_format, |
14811 | mode_cmd->modifier[0]); | |
53155c0a DV |
14812 | /* FIXME drm helper for size checks (especially planar formats)? */ |
14813 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
14814 | return -EINVAL; | |
14815 | ||
c7d73f6a DV |
14816 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
14817 | intel_fb->obj = obj; | |
14818 | ||
79e53945 JB |
14819 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
14820 | if (ret) { | |
14821 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
14822 | return ret; | |
14823 | } | |
14824 | ||
0b05e1e0 VS |
14825 | intel_fb->obj->framebuffer_references++; |
14826 | ||
79e53945 JB |
14827 | return 0; |
14828 | } | |
14829 | ||
79e53945 JB |
14830 | static struct drm_framebuffer * |
14831 | intel_user_framebuffer_create(struct drm_device *dev, | |
14832 | struct drm_file *filp, | |
1eb83451 | 14833 | const struct drm_mode_fb_cmd2 *user_mode_cmd) |
79e53945 | 14834 | { |
dcb1394e | 14835 | struct drm_framebuffer *fb; |
05394f39 | 14836 | struct drm_i915_gem_object *obj; |
76dc3769 | 14837 | struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd; |
79e53945 | 14838 | |
308e5bcb | 14839 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
76dc3769 | 14840 | mode_cmd.handles[0])); |
c8725226 | 14841 | if (&obj->base == NULL) |
cce13ff7 | 14842 | return ERR_PTR(-ENOENT); |
79e53945 | 14843 | |
92907cbb | 14844 | fb = intel_framebuffer_create(dev, &mode_cmd, obj); |
dcb1394e LW |
14845 | if (IS_ERR(fb)) |
14846 | drm_gem_object_unreference_unlocked(&obj->base); | |
14847 | ||
14848 | return fb; | |
79e53945 JB |
14849 | } |
14850 | ||
0695726e | 14851 | #ifndef CONFIG_DRM_FBDEV_EMULATION |
0632fef6 | 14852 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
14853 | { |
14854 | } | |
14855 | #endif | |
14856 | ||
79e53945 | 14857 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 14858 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 14859 | .output_poll_changed = intel_fbdev_output_poll_changed, |
5ee67f1c MR |
14860 | .atomic_check = intel_atomic_check, |
14861 | .atomic_commit = intel_atomic_commit, | |
de419ab6 ML |
14862 | .atomic_state_alloc = intel_atomic_state_alloc, |
14863 | .atomic_state_clear = intel_atomic_state_clear, | |
79e53945 JB |
14864 | }; |
14865 | ||
e70236a8 JB |
14866 | /* Set up chip specific display functions */ |
14867 | static void intel_init_display(struct drm_device *dev) | |
14868 | { | |
14869 | struct drm_i915_private *dev_priv = dev->dev_private; | |
14870 | ||
ee9300bb DV |
14871 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
14872 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
14873 | else if (IS_CHERRYVIEW(dev)) |
14874 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
14875 | else if (IS_VALLEYVIEW(dev)) |
14876 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
14877 | else if (IS_PINEVIEW(dev)) | |
14878 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
14879 | else | |
14880 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
14881 | ||
bc8d7dff DL |
14882 | if (INTEL_INFO(dev)->gen >= 9) { |
14883 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; | |
5724dbd1 DL |
14884 | dev_priv->display.get_initial_plane_config = |
14885 | skylake_get_initial_plane_config; | |
bc8d7dff DL |
14886 | dev_priv->display.crtc_compute_clock = |
14887 | haswell_crtc_compute_clock; | |
14888 | dev_priv->display.crtc_enable = haswell_crtc_enable; | |
14889 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
bc8d7dff | 14890 | } else if (HAS_DDI(dev)) { |
0e8ffe1b | 14891 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
5724dbd1 DL |
14892 | dev_priv->display.get_initial_plane_config = |
14893 | ironlake_get_initial_plane_config; | |
797d0259 ACO |
14894 | dev_priv->display.crtc_compute_clock = |
14895 | haswell_crtc_compute_clock; | |
4f771f10 PZ |
14896 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
14897 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
09b4ddf9 | 14898 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 14899 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
5724dbd1 DL |
14900 | dev_priv->display.get_initial_plane_config = |
14901 | ironlake_get_initial_plane_config; | |
3fb37703 ACO |
14902 | dev_priv->display.crtc_compute_clock = |
14903 | ironlake_crtc_compute_clock; | |
76e5a89c DV |
14904 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
14905 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
666a4537 | 14906 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
89b667f8 | 14907 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14908 | dev_priv->display.get_initial_plane_config = |
14909 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14910 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
89b667f8 JB |
14911 | dev_priv->display.crtc_enable = valleyview_crtc_enable; |
14912 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 14913 | } else { |
0e8ffe1b | 14914 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
5724dbd1 DL |
14915 | dev_priv->display.get_initial_plane_config = |
14916 | i9xx_get_initial_plane_config; | |
d6dfee7a | 14917 | dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; |
76e5a89c DV |
14918 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
14919 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
f564048e | 14920 | } |
e70236a8 | 14921 | |
e70236a8 | 14922 | /* Returns the core display clock speed */ |
ef11bdb3 | 14923 | if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) |
1652d19e VS |
14924 | dev_priv->display.get_display_clock_speed = |
14925 | skylake_get_display_clock_speed; | |
acd3f3d3 BP |
14926 | else if (IS_BROXTON(dev)) |
14927 | dev_priv->display.get_display_clock_speed = | |
14928 | broxton_get_display_clock_speed; | |
1652d19e VS |
14929 | else if (IS_BROADWELL(dev)) |
14930 | dev_priv->display.get_display_clock_speed = | |
14931 | broadwell_get_display_clock_speed; | |
14932 | else if (IS_HASWELL(dev)) | |
14933 | dev_priv->display.get_display_clock_speed = | |
14934 | haswell_get_display_clock_speed; | |
666a4537 | 14935 | else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
25eb05fc JB |
14936 | dev_priv->display.get_display_clock_speed = |
14937 | valleyview_get_display_clock_speed; | |
b37a6434 VS |
14938 | else if (IS_GEN5(dev)) |
14939 | dev_priv->display.get_display_clock_speed = | |
14940 | ilk_get_display_clock_speed; | |
a7c66cd8 | 14941 | else if (IS_I945G(dev) || IS_BROADWATER(dev) || |
34edce2f | 14942 | IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
e70236a8 JB |
14943 | dev_priv->display.get_display_clock_speed = |
14944 | i945_get_display_clock_speed; | |
34edce2f VS |
14945 | else if (IS_GM45(dev)) |
14946 | dev_priv->display.get_display_clock_speed = | |
14947 | gm45_get_display_clock_speed; | |
14948 | else if (IS_CRESTLINE(dev)) | |
14949 | dev_priv->display.get_display_clock_speed = | |
14950 | i965gm_get_display_clock_speed; | |
14951 | else if (IS_PINEVIEW(dev)) | |
14952 | dev_priv->display.get_display_clock_speed = | |
14953 | pnv_get_display_clock_speed; | |
14954 | else if (IS_G33(dev) || IS_G4X(dev)) | |
14955 | dev_priv->display.get_display_clock_speed = | |
14956 | g33_get_display_clock_speed; | |
e70236a8 JB |
14957 | else if (IS_I915G(dev)) |
14958 | dev_priv->display.get_display_clock_speed = | |
14959 | i915_get_display_clock_speed; | |
257a7ffc | 14960 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
14961 | dev_priv->display.get_display_clock_speed = |
14962 | i9xx_misc_get_display_clock_speed; | |
14963 | else if (IS_I915GM(dev)) | |
14964 | dev_priv->display.get_display_clock_speed = | |
14965 | i915gm_get_display_clock_speed; | |
14966 | else if (IS_I865G(dev)) | |
14967 | dev_priv->display.get_display_clock_speed = | |
14968 | i865_get_display_clock_speed; | |
f0f8a9ce | 14969 | else if (IS_I85X(dev)) |
e70236a8 | 14970 | dev_priv->display.get_display_clock_speed = |
1b1d2716 | 14971 | i85x_get_display_clock_speed; |
623e01e5 VS |
14972 | else { /* 830 */ |
14973 | WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n"); | |
e70236a8 JB |
14974 | dev_priv->display.get_display_clock_speed = |
14975 | i830_get_display_clock_speed; | |
623e01e5 | 14976 | } |
e70236a8 | 14977 | |
7c10a2b5 | 14978 | if (IS_GEN5(dev)) { |
3bb11b53 | 14979 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; |
3bb11b53 SJ |
14980 | } else if (IS_GEN6(dev)) { |
14981 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
3bb11b53 SJ |
14982 | } else if (IS_IVYBRIDGE(dev)) { |
14983 | /* FIXME: detect B0+ stepping and use auto training */ | |
14984 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
059b2fe9 | 14985 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 | 14986 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
27c329ed ML |
14987 | if (IS_BROADWELL(dev)) { |
14988 | dev_priv->display.modeset_commit_cdclk = | |
14989 | broadwell_modeset_commit_cdclk; | |
14990 | dev_priv->display.modeset_calc_cdclk = | |
14991 | broadwell_modeset_calc_cdclk; | |
14992 | } | |
666a4537 | 14993 | } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
27c329ed ML |
14994 | dev_priv->display.modeset_commit_cdclk = |
14995 | valleyview_modeset_commit_cdclk; | |
14996 | dev_priv->display.modeset_calc_cdclk = | |
14997 | valleyview_modeset_calc_cdclk; | |
f8437dd1 | 14998 | } else if (IS_BROXTON(dev)) { |
27c329ed ML |
14999 | dev_priv->display.modeset_commit_cdclk = |
15000 | broxton_modeset_commit_cdclk; | |
15001 | dev_priv->display.modeset_calc_cdclk = | |
15002 | broxton_modeset_calc_cdclk; | |
e70236a8 | 15003 | } |
8c9f3aaf | 15004 | |
8c9f3aaf JB |
15005 | switch (INTEL_INFO(dev)->gen) { |
15006 | case 2: | |
15007 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
15008 | break; | |
15009 | ||
15010 | case 3: | |
15011 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
15012 | break; | |
15013 | ||
15014 | case 4: | |
15015 | case 5: | |
15016 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
15017 | break; | |
15018 | ||
15019 | case 6: | |
15020 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
15021 | break; | |
7c9017e5 | 15022 | case 7: |
4e0bbc31 | 15023 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
15024 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
15025 | break; | |
830c81db | 15026 | case 9: |
ba343e02 TU |
15027 | /* Drop through - unsupported since execlist only. */ |
15028 | default: | |
15029 | /* Default just returns -ENODEV to indicate unsupported */ | |
15030 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
8c9f3aaf | 15031 | } |
7bd688cd | 15032 | |
e39b999a | 15033 | mutex_init(&dev_priv->pps_mutex); |
e70236a8 JB |
15034 | } |
15035 | ||
b690e96c JB |
15036 | /* |
15037 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
15038 | * resume, or other times. This quirk makes sure that's the case for | |
15039 | * affected systems. | |
15040 | */ | |
0206e353 | 15041 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
15042 | { |
15043 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15044 | ||
15045 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 15046 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
15047 | } |
15048 | ||
b6b5d049 VS |
15049 | static void quirk_pipeb_force(struct drm_device *dev) |
15050 | { | |
15051 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15052 | ||
15053 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
15054 | DRM_INFO("applying pipe b force quirk\n"); | |
15055 | } | |
15056 | ||
435793df KP |
15057 | /* |
15058 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
15059 | */ | |
15060 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
15061 | { | |
15062 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15063 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 15064 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
15065 | } |
15066 | ||
4dca20ef | 15067 | /* |
5a15ab5b CE |
15068 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
15069 | * brightness value | |
4dca20ef CE |
15070 | */ |
15071 | static void quirk_invert_brightness(struct drm_device *dev) | |
15072 | { | |
15073 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15074 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 15075 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
15076 | } |
15077 | ||
9c72cc6f SD |
15078 | /* Some VBT's incorrectly indicate no backlight is present */ |
15079 | static void quirk_backlight_present(struct drm_device *dev) | |
15080 | { | |
15081 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15082 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
15083 | DRM_INFO("applying backlight present quirk\n"); | |
15084 | } | |
15085 | ||
b690e96c JB |
15086 | struct intel_quirk { |
15087 | int device; | |
15088 | int subsystem_vendor; | |
15089 | int subsystem_device; | |
15090 | void (*hook)(struct drm_device *dev); | |
15091 | }; | |
15092 | ||
5f85f176 EE |
15093 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
15094 | struct intel_dmi_quirk { | |
15095 | void (*hook)(struct drm_device *dev); | |
15096 | const struct dmi_system_id (*dmi_id_list)[]; | |
15097 | }; | |
15098 | ||
15099 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
15100 | { | |
15101 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
15102 | return 1; | |
15103 | } | |
15104 | ||
15105 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
15106 | { | |
15107 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
15108 | { | |
15109 | .callback = intel_dmi_reverse_brightness, | |
15110 | .ident = "NCR Corporation", | |
15111 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
15112 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
15113 | }, | |
15114 | }, | |
15115 | { } /* terminating entry */ | |
15116 | }, | |
15117 | .hook = quirk_invert_brightness, | |
15118 | }, | |
15119 | }; | |
15120 | ||
c43b5634 | 15121 | static struct intel_quirk intel_quirks[] = { |
b690e96c JB |
15122 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
15123 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
15124 | ||
b690e96c JB |
15125 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
15126 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
15127 | ||
5f080c0f VS |
15128 | /* 830 needs to leave pipe A & dpll A up */ |
15129 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
15130 | ||
b6b5d049 VS |
15131 | /* 830 needs to leave pipe B & dpll B up */ |
15132 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
15133 | ||
435793df KP |
15134 | /* Lenovo U160 cannot use SSC on LVDS */ |
15135 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
15136 | |
15137 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
15138 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 15139 | |
be505f64 AH |
15140 | /* Acer Aspire 5734Z must invert backlight brightness */ |
15141 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
15142 | ||
15143 | /* Acer/eMachines G725 */ | |
15144 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
15145 | ||
15146 | /* Acer/eMachines e725 */ | |
15147 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
15148 | ||
15149 | /* Acer/Packard Bell NCL20 */ | |
15150 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
15151 | ||
15152 | /* Acer Aspire 4736Z */ | |
15153 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
15154 | |
15155 | /* Acer Aspire 5336 */ | |
15156 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
15157 | |
15158 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
15159 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 15160 | |
dfb3d47b SD |
15161 | /* Acer C720 Chromebook (Core i3 4005U) */ |
15162 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
15163 | ||
b2a9601c | 15164 | /* Apple Macbook 2,1 (Core 2 T7400) */ |
15165 | { 0x27a2, 0x8086, 0x7270, quirk_backlight_present }, | |
15166 | ||
1b9448b0 JN |
15167 | /* Apple Macbook 4,1 */ |
15168 | { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present }, | |
15169 | ||
d4967d8c SD |
15170 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
15171 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
15172 | |
15173 | /* HP Chromebook 14 (Celeron 2955U) */ | |
15174 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
cf6f0af9 JN |
15175 | |
15176 | /* Dell Chromebook 11 */ | |
15177 | { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present }, | |
9be64eee JN |
15178 | |
15179 | /* Dell Chromebook 11 (2015 version) */ | |
15180 | { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present }, | |
b690e96c JB |
15181 | }; |
15182 | ||
15183 | static void intel_init_quirks(struct drm_device *dev) | |
15184 | { | |
15185 | struct pci_dev *d = dev->pdev; | |
15186 | int i; | |
15187 | ||
15188 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
15189 | struct intel_quirk *q = &intel_quirks[i]; | |
15190 | ||
15191 | if (d->device == q->device && | |
15192 | (d->subsystem_vendor == q->subsystem_vendor || | |
15193 | q->subsystem_vendor == PCI_ANY_ID) && | |
15194 | (d->subsystem_device == q->subsystem_device || | |
15195 | q->subsystem_device == PCI_ANY_ID)) | |
15196 | q->hook(dev); | |
15197 | } | |
5f85f176 EE |
15198 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
15199 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
15200 | intel_dmi_quirks[i].hook(dev); | |
15201 | } | |
b690e96c JB |
15202 | } |
15203 | ||
9cce37f4 JB |
15204 | /* Disable the VGA plane that we never use */ |
15205 | static void i915_disable_vga(struct drm_device *dev) | |
15206 | { | |
15207 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15208 | u8 sr1; | |
f0f59a00 | 15209 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 15210 | |
2b37c616 | 15211 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 15212 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 15213 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
15214 | sr1 = inb(VGA_SR_DATA); |
15215 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
15216 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
15217 | udelay(300); | |
15218 | ||
01f5a626 | 15219 | I915_WRITE(vga_reg, VGA_DISP_DISABLE); |
9cce37f4 JB |
15220 | POSTING_READ(vga_reg); |
15221 | } | |
15222 | ||
f817586c DV |
15223 | void intel_modeset_init_hw(struct drm_device *dev) |
15224 | { | |
1a617b77 ML |
15225 | struct drm_i915_private *dev_priv = dev->dev_private; |
15226 | ||
b6283055 | 15227 | intel_update_cdclk(dev); |
1a617b77 ML |
15228 | |
15229 | dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq; | |
15230 | ||
f817586c | 15231 | intel_init_clock_gating(dev); |
8090c6b9 | 15232 | intel_enable_gt_powersave(dev); |
f817586c DV |
15233 | } |
15234 | ||
d93c0372 MR |
15235 | /* |
15236 | * Calculate what we think the watermarks should be for the state we've read | |
15237 | * out of the hardware and then immediately program those watermarks so that | |
15238 | * we ensure the hardware settings match our internal state. | |
15239 | * | |
15240 | * We can calculate what we think WM's should be by creating a duplicate of the | |
15241 | * current state (which was constructed during hardware readout) and running it | |
15242 | * through the atomic check code to calculate new watermark values in the | |
15243 | * state object. | |
15244 | */ | |
15245 | static void sanitize_watermarks(struct drm_device *dev) | |
15246 | { | |
15247 | struct drm_i915_private *dev_priv = to_i915(dev); | |
15248 | struct drm_atomic_state *state; | |
15249 | struct drm_crtc *crtc; | |
15250 | struct drm_crtc_state *cstate; | |
15251 | struct drm_modeset_acquire_ctx ctx; | |
15252 | int ret; | |
15253 | int i; | |
15254 | ||
15255 | /* Only supported on platforms that use atomic watermark design */ | |
bf220452 | 15256 | if (!dev_priv->display.program_watermarks) |
d93c0372 MR |
15257 | return; |
15258 | ||
15259 | /* | |
15260 | * We need to hold connection_mutex before calling duplicate_state so | |
15261 | * that the connector loop is protected. | |
15262 | */ | |
15263 | drm_modeset_acquire_init(&ctx, 0); | |
15264 | retry: | |
0cd1262d | 15265 | ret = drm_modeset_lock_all_ctx(dev, &ctx); |
d93c0372 MR |
15266 | if (ret == -EDEADLK) { |
15267 | drm_modeset_backoff(&ctx); | |
15268 | goto retry; | |
15269 | } else if (WARN_ON(ret)) { | |
0cd1262d | 15270 | goto fail; |
d93c0372 MR |
15271 | } |
15272 | ||
15273 | state = drm_atomic_helper_duplicate_state(dev, &ctx); | |
15274 | if (WARN_ON(IS_ERR(state))) | |
0cd1262d | 15275 | goto fail; |
d93c0372 MR |
15276 | |
15277 | ret = intel_atomic_check(dev, state); | |
15278 | if (ret) { | |
15279 | /* | |
15280 | * If we fail here, it means that the hardware appears to be | |
15281 | * programmed in a way that shouldn't be possible, given our | |
15282 | * understanding of watermark requirements. This might mean a | |
15283 | * mistake in the hardware readout code or a mistake in the | |
15284 | * watermark calculations for a given platform. Raise a WARN | |
15285 | * so that this is noticeable. | |
15286 | * | |
15287 | * If this actually happens, we'll have to just leave the | |
15288 | * BIOS-programmed watermarks untouched and hope for the best. | |
15289 | */ | |
15290 | WARN(true, "Could not determine valid watermarks for inherited state\n"); | |
0cd1262d | 15291 | goto fail; |
d93c0372 MR |
15292 | } |
15293 | ||
15294 | /* Write calculated watermark values back */ | |
15295 | to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config; | |
15296 | for_each_crtc_in_state(state, crtc, cstate, i) { | |
15297 | struct intel_crtc_state *cs = to_intel_crtc_state(cstate); | |
15298 | ||
bf220452 | 15299 | dev_priv->display.program_watermarks(cs); |
d93c0372 MR |
15300 | } |
15301 | ||
15302 | drm_atomic_state_free(state); | |
0cd1262d | 15303 | fail: |
d93c0372 MR |
15304 | drm_modeset_drop_locks(&ctx); |
15305 | drm_modeset_acquire_fini(&ctx); | |
15306 | } | |
15307 | ||
79e53945 JB |
15308 | void intel_modeset_init(struct drm_device *dev) |
15309 | { | |
652c393a | 15310 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 15311 | int sprite, ret; |
8cc87b75 | 15312 | enum pipe pipe; |
46f297fb | 15313 | struct intel_crtc *crtc; |
79e53945 JB |
15314 | |
15315 | drm_mode_config_init(dev); | |
15316 | ||
15317 | dev->mode_config.min_width = 0; | |
15318 | dev->mode_config.min_height = 0; | |
15319 | ||
019d96cb DA |
15320 | dev->mode_config.preferred_depth = 24; |
15321 | dev->mode_config.prefer_shadow = 1; | |
15322 | ||
25bab385 TU |
15323 | dev->mode_config.allow_fb_modifiers = true; |
15324 | ||
e6ecefaa | 15325 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 15326 | |
b690e96c JB |
15327 | intel_init_quirks(dev); |
15328 | ||
1fa61106 ED |
15329 | intel_init_pm(dev); |
15330 | ||
e3c74757 BW |
15331 | if (INTEL_INFO(dev)->num_pipes == 0) |
15332 | return; | |
15333 | ||
69f92f67 LW |
15334 | /* |
15335 | * There may be no VBT; and if the BIOS enabled SSC we can | |
15336 | * just keep using it to avoid unnecessary flicker. Whereas if the | |
15337 | * BIOS isn't using it, don't assume it will work even if the VBT | |
15338 | * indicates as much. | |
15339 | */ | |
15340 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { | |
15341 | bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) & | |
15342 | DREF_SSC1_ENABLE); | |
15343 | ||
15344 | if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) { | |
15345 | DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n", | |
15346 | bios_lvds_use_ssc ? "en" : "dis", | |
15347 | dev_priv->vbt.lvds_use_ssc ? "en" : "dis"); | |
15348 | dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc; | |
15349 | } | |
15350 | } | |
15351 | ||
e70236a8 | 15352 | intel_init_display(dev); |
7c10a2b5 | 15353 | intel_init_audio(dev); |
e70236a8 | 15354 | |
a6c45cf0 CW |
15355 | if (IS_GEN2(dev)) { |
15356 | dev->mode_config.max_width = 2048; | |
15357 | dev->mode_config.max_height = 2048; | |
15358 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
15359 | dev->mode_config.max_width = 4096; |
15360 | dev->mode_config.max_height = 4096; | |
79e53945 | 15361 | } else { |
a6c45cf0 CW |
15362 | dev->mode_config.max_width = 8192; |
15363 | dev->mode_config.max_height = 8192; | |
79e53945 | 15364 | } |
068be561 | 15365 | |
dc41c154 VS |
15366 | if (IS_845G(dev) || IS_I865G(dev)) { |
15367 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
15368 | dev->mode_config.cursor_height = 1023; | |
15369 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
15370 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
15371 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
15372 | } else { | |
15373 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
15374 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
15375 | } | |
15376 | ||
5d4545ae | 15377 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 15378 | |
28c97730 | 15379 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
15380 | INTEL_INFO(dev)->num_pipes, |
15381 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 15382 | |
055e393f | 15383 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 15384 | intel_crtc_init(dev, pipe); |
3bdcfc0c | 15385 | for_each_sprite(dev_priv, pipe, sprite) { |
1fe47785 | 15386 | ret = intel_plane_init(dev, pipe, sprite); |
7f1f3851 | 15387 | if (ret) |
06da8da2 | 15388 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 15389 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 15390 | } |
79e53945 JB |
15391 | } |
15392 | ||
bfa7df01 VS |
15393 | intel_update_czclk(dev_priv); |
15394 | intel_update_cdclk(dev); | |
15395 | ||
e72f9fbf | 15396 | intel_shared_dpll_init(dev); |
ee7b9f93 | 15397 | |
9cce37f4 JB |
15398 | /* Just disable it once at startup */ |
15399 | i915_disable_vga(dev); | |
79e53945 | 15400 | intel_setup_outputs(dev); |
11be49eb | 15401 | |
6e9f798d | 15402 | drm_modeset_lock_all(dev); |
043e9bda | 15403 | intel_modeset_setup_hw_state(dev); |
6e9f798d | 15404 | drm_modeset_unlock_all(dev); |
46f297fb | 15405 | |
d3fcc808 | 15406 | for_each_intel_crtc(dev, crtc) { |
eeebeac5 ML |
15407 | struct intel_initial_plane_config plane_config = {}; |
15408 | ||
46f297fb JB |
15409 | if (!crtc->active) |
15410 | continue; | |
15411 | ||
46f297fb | 15412 | /* |
46f297fb JB |
15413 | * Note that reserving the BIOS fb up front prevents us |
15414 | * from stuffing other stolen allocations like the ring | |
15415 | * on top. This prevents some ugliness at boot time, and | |
15416 | * can even allow for smooth boot transitions if the BIOS | |
15417 | * fb is large enough for the active pipe configuration. | |
15418 | */ | |
eeebeac5 ML |
15419 | dev_priv->display.get_initial_plane_config(crtc, |
15420 | &plane_config); | |
15421 | ||
15422 | /* | |
15423 | * If the fb is shared between multiple heads, we'll | |
15424 | * just get the first one. | |
15425 | */ | |
15426 | intel_find_initial_plane_obj(crtc, &plane_config); | |
46f297fb | 15427 | } |
d93c0372 MR |
15428 | |
15429 | /* | |
15430 | * Make sure hardware watermarks really match the state we read out. | |
15431 | * Note that we need to do this after reconstructing the BIOS fb's | |
15432 | * since the watermark calculation done here will use pstate->fb. | |
15433 | */ | |
15434 | sanitize_watermarks(dev); | |
2c7111db CW |
15435 | } |
15436 | ||
7fad798e DV |
15437 | static void intel_enable_pipe_a(struct drm_device *dev) |
15438 | { | |
15439 | struct intel_connector *connector; | |
15440 | struct drm_connector *crt = NULL; | |
15441 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 15442 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
15443 | |
15444 | /* We can't just switch on the pipe A, we need to set things up with a | |
15445 | * proper mode and output configuration. As a gross hack, enable pipe A | |
15446 | * by enabling the load detect pipe once. */ | |
3a3371ff | 15447 | for_each_intel_connector(dev, connector) { |
7fad798e DV |
15448 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { |
15449 | crt = &connector->base; | |
15450 | break; | |
15451 | } | |
15452 | } | |
15453 | ||
15454 | if (!crt) | |
15455 | return; | |
15456 | ||
208bf9fd | 15457 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
49172fee | 15458 | intel_release_load_detect_pipe(crt, &load_detect_temp, ctx); |
7fad798e DV |
15459 | } |
15460 | ||
fa555837 DV |
15461 | static bool |
15462 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
15463 | { | |
7eb552ae BW |
15464 | struct drm_device *dev = crtc->base.dev; |
15465 | struct drm_i915_private *dev_priv = dev->dev_private; | |
649636ef | 15466 | u32 val; |
fa555837 | 15467 | |
7eb552ae | 15468 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
15469 | return true; |
15470 | ||
649636ef | 15471 | val = I915_READ(DSPCNTR(!crtc->plane)); |
fa555837 DV |
15472 | |
15473 | if ((val & DISPLAY_PLANE_ENABLE) && | |
15474 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
15475 | return false; | |
15476 | ||
15477 | return true; | |
15478 | } | |
15479 | ||
02e93c35 VS |
15480 | static bool intel_crtc_has_encoders(struct intel_crtc *crtc) |
15481 | { | |
15482 | struct drm_device *dev = crtc->base.dev; | |
15483 | struct intel_encoder *encoder; | |
15484 | ||
15485 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) | |
15486 | return true; | |
15487 | ||
15488 | return false; | |
15489 | } | |
15490 | ||
24929352 DV |
15491 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
15492 | { | |
15493 | struct drm_device *dev = crtc->base.dev; | |
15494 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 15495 | i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder); |
24929352 | 15496 | |
24929352 | 15497 | /* Clear any frame start delays used for debugging left by the BIOS */ |
24929352 DV |
15498 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
15499 | ||
d3eaf884 | 15500 | /* restore vblank interrupts to correct state */ |
9625604c | 15501 | drm_crtc_vblank_reset(&crtc->base); |
d297e103 | 15502 | if (crtc->active) { |
f9cd7b88 VS |
15503 | struct intel_plane *plane; |
15504 | ||
9625604c | 15505 | drm_crtc_vblank_on(&crtc->base); |
f9cd7b88 VS |
15506 | |
15507 | /* Disable everything but the primary plane */ | |
15508 | for_each_intel_plane_on_crtc(dev, crtc, plane) { | |
15509 | if (plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
15510 | continue; | |
15511 | ||
15512 | plane->disable_plane(&plane->base, &crtc->base); | |
15513 | } | |
9625604c | 15514 | } |
d3eaf884 | 15515 | |
24929352 | 15516 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
15517 | * disable the crtc (and hence change the state) if it is wrong. Note |
15518 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
15519 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
15520 | bool plane; |
15521 | ||
24929352 DV |
15522 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
15523 | crtc->base.base.id); | |
15524 | ||
15525 | /* Pipe has the wrong plane attached and the plane is active. | |
15526 | * Temporarily change the plane mapping and disable everything | |
15527 | * ... */ | |
15528 | plane = crtc->plane; | |
b70709a6 | 15529 | to_intel_plane_state(crtc->base.primary->state)->visible = true; |
24929352 | 15530 | crtc->plane = !plane; |
b17d48e2 | 15531 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15532 | crtc->plane = plane; |
24929352 | 15533 | } |
24929352 | 15534 | |
7fad798e DV |
15535 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
15536 | crtc->pipe == PIPE_A && !crtc->active) { | |
15537 | /* BIOS forgot to enable pipe A, this mostly happens after | |
15538 | * resume. Force-enable the pipe to fix this, the update_dpms | |
15539 | * call below we restore the pipe to the right state, but leave | |
15540 | * the required bits on. */ | |
15541 | intel_enable_pipe_a(dev); | |
15542 | } | |
15543 | ||
24929352 DV |
15544 | /* Adjust the state of the output pipe according to whether we |
15545 | * have active connectors/encoders. */ | |
02e93c35 | 15546 | if (!intel_crtc_has_encoders(crtc)) |
b17d48e2 | 15547 | intel_crtc_disable_noatomic(&crtc->base); |
24929352 | 15548 | |
53d9f4e9 | 15549 | if (crtc->active != crtc->base.state->active) { |
02e93c35 | 15550 | struct intel_encoder *encoder; |
24929352 DV |
15551 | |
15552 | /* This can happen either due to bugs in the get_hw_state | |
b17d48e2 ML |
15553 | * functions or because of calls to intel_crtc_disable_noatomic, |
15554 | * or because the pipe is force-enabled due to the | |
24929352 DV |
15555 | * pipe A quirk. */ |
15556 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
15557 | crtc->base.base.id, | |
83d65738 | 15558 | crtc->base.state->enable ? "enabled" : "disabled", |
24929352 DV |
15559 | crtc->active ? "enabled" : "disabled"); |
15560 | ||
4be40c98 | 15561 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0); |
49d6fa21 | 15562 | crtc->base.state->active = crtc->active; |
24929352 | 15563 | crtc->base.enabled = crtc->active; |
2aa974c9 | 15564 | crtc->base.state->connector_mask = 0; |
24929352 DV |
15565 | |
15566 | /* Because we only establish the connector -> encoder -> | |
15567 | * crtc links if something is active, this means the | |
15568 | * crtc is now deactivated. Break the links. connector | |
15569 | * -> encoder links are only establish when things are | |
15570 | * actually up, hence no need to break them. */ | |
15571 | WARN_ON(crtc->active); | |
15572 | ||
2d406bb0 | 15573 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) |
24929352 | 15574 | encoder->base.crtc = NULL; |
24929352 | 15575 | } |
c5ab3bc0 | 15576 | |
a3ed6aad | 15577 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
15578 | /* |
15579 | * We start out with underrun reporting disabled to avoid races. | |
15580 | * For correct bookkeeping mark this on active crtcs. | |
15581 | * | |
c5ab3bc0 DV |
15582 | * Also on gmch platforms we dont have any hardware bits to |
15583 | * disable the underrun reporting. Which means we need to start | |
15584 | * out with underrun reporting disabled also on inactive pipes, | |
15585 | * since otherwise we'll complain about the garbage we read when | |
15586 | * e.g. coming up after runtime pm. | |
15587 | * | |
4cc31489 DV |
15588 | * No protection against concurrent access is required - at |
15589 | * worst a fifo underrun happens which also sets this to false. | |
15590 | */ | |
15591 | crtc->cpu_fifo_underrun_disabled = true; | |
15592 | crtc->pch_fifo_underrun_disabled = true; | |
15593 | } | |
24929352 DV |
15594 | } |
15595 | ||
15596 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
15597 | { | |
15598 | struct intel_connector *connector; | |
15599 | struct drm_device *dev = encoder->base.dev; | |
873ffe69 | 15600 | bool active = false; |
24929352 DV |
15601 | |
15602 | /* We need to check both for a crtc link (meaning that the | |
15603 | * encoder is active and trying to read from a pipe) and the | |
15604 | * pipe itself being active. */ | |
15605 | bool has_active_crtc = encoder->base.crtc && | |
15606 | to_intel_crtc(encoder->base.crtc)->active; | |
15607 | ||
873ffe69 ML |
15608 | for_each_intel_connector(dev, connector) { |
15609 | if (connector->base.encoder != &encoder->base) | |
15610 | continue; | |
15611 | ||
15612 | active = true; | |
15613 | break; | |
15614 | } | |
15615 | ||
15616 | if (active && !has_active_crtc) { | |
24929352 DV |
15617 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", |
15618 | encoder->base.base.id, | |
8e329a03 | 15619 | encoder->base.name); |
24929352 DV |
15620 | |
15621 | /* Connector is active, but has no active pipe. This is | |
15622 | * fallout from our resume register restoring. Disable | |
15623 | * the encoder manually again. */ | |
15624 | if (encoder->base.crtc) { | |
15625 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
15626 | encoder->base.base.id, | |
8e329a03 | 15627 | encoder->base.name); |
24929352 | 15628 | encoder->disable(encoder); |
a62d1497 VS |
15629 | if (encoder->post_disable) |
15630 | encoder->post_disable(encoder); | |
24929352 | 15631 | } |
7f1950fb | 15632 | encoder->base.crtc = NULL; |
24929352 DV |
15633 | |
15634 | /* Inconsistent output/port/pipe state happens presumably due to | |
15635 | * a bug in one of the get_hw_state functions. Or someplace else | |
15636 | * in our code, like the register restore mess on resume. Clamp | |
15637 | * things to off as a safer default. */ | |
3a3371ff | 15638 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15639 | if (connector->encoder != encoder) |
15640 | continue; | |
7f1950fb EE |
15641 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
15642 | connector->base.encoder = NULL; | |
24929352 DV |
15643 | } |
15644 | } | |
15645 | /* Enabled encoders without active connectors will be fixed in | |
15646 | * the crtc fixup. */ | |
15647 | } | |
15648 | ||
04098753 | 15649 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
15650 | { |
15651 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f0f59a00 | 15652 | i915_reg_t vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 15653 | |
04098753 ID |
15654 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
15655 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
15656 | i915_disable_vga(dev); | |
15657 | } | |
15658 | } | |
15659 | ||
15660 | void i915_redisable_vga(struct drm_device *dev) | |
15661 | { | |
15662 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15663 | ||
8dc8a27c PZ |
15664 | /* This function can be called both from intel_modeset_setup_hw_state or |
15665 | * at a very early point in our resume sequence, where the power well | |
15666 | * structures are not yet restored. Since this function is at a very | |
15667 | * paranoid "someone might have enabled VGA while we were not looking" | |
15668 | * level, just check if the power well is enabled instead of trying to | |
15669 | * follow the "don't touch the power well if we don't need it" policy | |
15670 | * the rest of the driver uses. */ | |
f458ebbc | 15671 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
15672 | return; |
15673 | ||
04098753 | 15674 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
15675 | } |
15676 | ||
f9cd7b88 | 15677 | static bool primary_get_hw_state(struct intel_plane *plane) |
98ec7739 | 15678 | { |
f9cd7b88 | 15679 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
98ec7739 | 15680 | |
f9cd7b88 | 15681 | return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE; |
d032ffa0 ML |
15682 | } |
15683 | ||
f9cd7b88 VS |
15684 | /* FIXME read out full plane state for all planes */ |
15685 | static void readout_plane_state(struct intel_crtc *crtc) | |
d032ffa0 | 15686 | { |
b26d3ea3 | 15687 | struct drm_plane *primary = crtc->base.primary; |
f9cd7b88 | 15688 | struct intel_plane_state *plane_state = |
b26d3ea3 | 15689 | to_intel_plane_state(primary->state); |
d032ffa0 | 15690 | |
19b8d387 | 15691 | plane_state->visible = crtc->active && |
b26d3ea3 ML |
15692 | primary_get_hw_state(to_intel_plane(primary)); |
15693 | ||
15694 | if (plane_state->visible) | |
15695 | crtc->base.state->plane_mask |= 1 << drm_plane_index(primary); | |
98ec7739 VS |
15696 | } |
15697 | ||
30e984df | 15698 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
15699 | { |
15700 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15701 | enum pipe pipe; | |
24929352 DV |
15702 | struct intel_crtc *crtc; |
15703 | struct intel_encoder *encoder; | |
15704 | struct intel_connector *connector; | |
5358901f | 15705 | int i; |
24929352 | 15706 | |
565602d7 ML |
15707 | dev_priv->active_crtcs = 0; |
15708 | ||
d3fcc808 | 15709 | for_each_intel_crtc(dev, crtc) { |
565602d7 ML |
15710 | struct intel_crtc_state *crtc_state = crtc->config; |
15711 | int pixclk = 0; | |
3b117c8f | 15712 | |
565602d7 ML |
15713 | __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base); |
15714 | memset(crtc_state, 0, sizeof(*crtc_state)); | |
15715 | crtc_state->base.crtc = &crtc->base; | |
24929352 | 15716 | |
565602d7 ML |
15717 | crtc_state->base.active = crtc_state->base.enable = |
15718 | dev_priv->display.get_pipe_config(crtc, crtc_state); | |
15719 | ||
15720 | crtc->base.enabled = crtc_state->base.enable; | |
15721 | crtc->active = crtc_state->base.active; | |
15722 | ||
15723 | if (crtc_state->base.active) { | |
15724 | dev_priv->active_crtcs |= 1 << crtc->pipe; | |
15725 | ||
15726 | if (IS_BROADWELL(dev_priv)) { | |
15727 | pixclk = ilk_pipe_pixel_rate(crtc_state); | |
15728 | ||
15729 | /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */ | |
15730 | if (crtc_state->ips_enabled) | |
15731 | pixclk = DIV_ROUND_UP(pixclk * 100, 95); | |
15732 | } else if (IS_VALLEYVIEW(dev_priv) || | |
15733 | IS_CHERRYVIEW(dev_priv) || | |
15734 | IS_BROXTON(dev_priv)) | |
15735 | pixclk = crtc_state->base.adjusted_mode.crtc_clock; | |
15736 | else | |
15737 | WARN_ON(dev_priv->display.modeset_calc_cdclk); | |
15738 | } | |
15739 | ||
15740 | dev_priv->min_pixclk[crtc->pipe] = pixclk; | |
b70709a6 | 15741 | |
f9cd7b88 | 15742 | readout_plane_state(crtc); |
24929352 DV |
15743 | |
15744 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
15745 | crtc->base.base.id, | |
15746 | crtc->active ? "enabled" : "disabled"); | |
15747 | } | |
15748 | ||
5358901f DV |
15749 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15750 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15751 | ||
3e369b76 ACO |
15752 | pll->on = pll->get_hw_state(dev_priv, pll, |
15753 | &pll->config.hw_state); | |
5358901f | 15754 | pll->active = 0; |
3e369b76 | 15755 | pll->config.crtc_mask = 0; |
d3fcc808 | 15756 | for_each_intel_crtc(dev, crtc) { |
1e6f2ddc | 15757 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) { |
5358901f | 15758 | pll->active++; |
3e369b76 | 15759 | pll->config.crtc_mask |= 1 << crtc->pipe; |
1e6f2ddc | 15760 | } |
5358901f | 15761 | } |
5358901f | 15762 | |
1e6f2ddc | 15763 | DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n", |
3e369b76 | 15764 | pll->name, pll->config.crtc_mask, pll->on); |
bd2bb1b9 | 15765 | |
3e369b76 | 15766 | if (pll->config.crtc_mask) |
bd2bb1b9 | 15767 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
5358901f DV |
15768 | } |
15769 | ||
b2784e15 | 15770 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15771 | pipe = 0; |
15772 | ||
15773 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
15774 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15775 | encoder->base.crtc = &crtc->base; | |
6e3c9717 | 15776 | encoder->get_config(encoder, crtc->config); |
24929352 DV |
15777 | } else { |
15778 | encoder->base.crtc = NULL; | |
15779 | } | |
15780 | ||
6f2bcceb | 15781 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 15782 | encoder->base.base.id, |
8e329a03 | 15783 | encoder->base.name, |
24929352 | 15784 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 15785 | pipe_name(pipe)); |
24929352 DV |
15786 | } |
15787 | ||
3a3371ff | 15788 | for_each_intel_connector(dev, connector) { |
24929352 DV |
15789 | if (connector->get_hw_state(connector)) { |
15790 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
2aa974c9 ML |
15791 | |
15792 | encoder = connector->encoder; | |
15793 | connector->base.encoder = &encoder->base; | |
15794 | ||
15795 | if (encoder->base.crtc && | |
15796 | encoder->base.crtc->state->active) { | |
15797 | /* | |
15798 | * This has to be done during hardware readout | |
15799 | * because anything calling .crtc_disable may | |
15800 | * rely on the connector_mask being accurate. | |
15801 | */ | |
15802 | encoder->base.crtc->state->connector_mask |= | |
15803 | 1 << drm_connector_index(&connector->base); | |
15804 | } | |
15805 | ||
24929352 DV |
15806 | } else { |
15807 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
15808 | connector->base.encoder = NULL; | |
15809 | } | |
15810 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
15811 | connector->base.base.id, | |
c23cc417 | 15812 | connector->base.name, |
24929352 DV |
15813 | connector->base.encoder ? "enabled" : "disabled"); |
15814 | } | |
7f4c6284 VS |
15815 | |
15816 | for_each_intel_crtc(dev, crtc) { | |
15817 | crtc->base.hwmode = crtc->config->base.adjusted_mode; | |
15818 | ||
15819 | memset(&crtc->base.mode, 0, sizeof(crtc->base.mode)); | |
15820 | if (crtc->base.state->active) { | |
15821 | intel_mode_from_pipe_config(&crtc->base.mode, crtc->config); | |
15822 | intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config); | |
15823 | WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode)); | |
15824 | ||
15825 | /* | |
15826 | * The initial mode needs to be set in order to keep | |
15827 | * the atomic core happy. It wants a valid mode if the | |
15828 | * crtc's enabled, so we do the above call. | |
15829 | * | |
15830 | * At this point some state updated by the connectors | |
15831 | * in their ->detect() callback has not run yet, so | |
15832 | * no recalculation can be done yet. | |
15833 | * | |
15834 | * Even if we could do a recalculation and modeset | |
15835 | * right now it would cause a double modeset if | |
15836 | * fbdev or userspace chooses a different initial mode. | |
15837 | * | |
15838 | * If that happens, someone indicated they wanted a | |
15839 | * mode change, which means it's safe to do a full | |
15840 | * recalculation. | |
15841 | */ | |
15842 | crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED; | |
9eca6832 VS |
15843 | |
15844 | drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode); | |
15845 | update_scanline_offset(crtc); | |
7f4c6284 VS |
15846 | } |
15847 | } | |
30e984df DV |
15848 | } |
15849 | ||
043e9bda ML |
15850 | /* Scan out the current hw modeset state, |
15851 | * and sanitizes it to the current state | |
15852 | */ | |
15853 | static void | |
15854 | intel_modeset_setup_hw_state(struct drm_device *dev) | |
30e984df DV |
15855 | { |
15856 | struct drm_i915_private *dev_priv = dev->dev_private; | |
15857 | enum pipe pipe; | |
30e984df DV |
15858 | struct intel_crtc *crtc; |
15859 | struct intel_encoder *encoder; | |
35c95375 | 15860 | int i; |
30e984df DV |
15861 | |
15862 | intel_modeset_readout_hw_state(dev); | |
24929352 DV |
15863 | |
15864 | /* HW state is read out, now we need to sanitize this mess. */ | |
b2784e15 | 15865 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
15866 | intel_sanitize_encoder(encoder); |
15867 | } | |
15868 | ||
055e393f | 15869 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
15870 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
15871 | intel_sanitize_crtc(crtc); | |
6e3c9717 ACO |
15872 | intel_dump_pipe_config(crtc, crtc->config, |
15873 | "[setup_hw_state]"); | |
24929352 | 15874 | } |
9a935856 | 15875 | |
d29b2f9d ACO |
15876 | intel_modeset_update_connector_atomic_state(dev); |
15877 | ||
35c95375 DV |
15878 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
15879 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
15880 | ||
15881 | if (!pll->on || pll->active) | |
15882 | continue; | |
15883 | ||
15884 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
15885 | ||
15886 | pll->disable(dev_priv, pll); | |
15887 | pll->on = false; | |
15888 | } | |
15889 | ||
666a4537 | 15890 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6eb1a681 VS |
15891 | vlv_wm_get_hw_state(dev); |
15892 | else if (IS_GEN9(dev)) | |
3078999f PB |
15893 | skl_wm_get_hw_state(dev); |
15894 | else if (HAS_PCH_SPLIT(dev)) | |
243e6a44 | 15895 | ilk_wm_get_hw_state(dev); |
292b990e ML |
15896 | |
15897 | for_each_intel_crtc(dev, crtc) { | |
15898 | unsigned long put_domains; | |
15899 | ||
15900 | put_domains = modeset_get_crtc_power_domains(&crtc->base); | |
15901 | if (WARN_ON(put_domains)) | |
15902 | modeset_put_power_domains(dev_priv, put_domains); | |
15903 | } | |
15904 | intel_display_set_init_power(dev_priv, false); | |
010cf73d PZ |
15905 | |
15906 | intel_fbc_init_pipe_state(dev_priv); | |
043e9bda | 15907 | } |
7d0bc1ea | 15908 | |
043e9bda ML |
15909 | void intel_display_resume(struct drm_device *dev) |
15910 | { | |
15911 | struct drm_atomic_state *state = drm_atomic_state_alloc(dev); | |
15912 | struct intel_connector *conn; | |
15913 | struct intel_plane *plane; | |
15914 | struct drm_crtc *crtc; | |
15915 | int ret; | |
f30da187 | 15916 | |
043e9bda ML |
15917 | if (!state) |
15918 | return; | |
15919 | ||
15920 | state->acquire_ctx = dev->mode_config.acquire_ctx; | |
15921 | ||
15922 | /* preserve complete old state, including dpll */ | |
15923 | intel_atomic_get_shared_dpll_state(state); | |
15924 | ||
15925 | for_each_crtc(dev, crtc) { | |
15926 | struct drm_crtc_state *crtc_state = | |
15927 | drm_atomic_get_crtc_state(state, crtc); | |
15928 | ||
15929 | ret = PTR_ERR_OR_ZERO(crtc_state); | |
15930 | if (ret) | |
15931 | goto err; | |
15932 | ||
15933 | /* force a restore */ | |
15934 | crtc_state->mode_changed = true; | |
45e2b5f6 | 15935 | } |
8af6cf88 | 15936 | |
043e9bda ML |
15937 | for_each_intel_plane(dev, plane) { |
15938 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base)); | |
15939 | if (ret) | |
15940 | goto err; | |
15941 | } | |
15942 | ||
15943 | for_each_intel_connector(dev, conn) { | |
15944 | ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base)); | |
15945 | if (ret) | |
15946 | goto err; | |
15947 | } | |
15948 | ||
15949 | intel_modeset_setup_hw_state(dev); | |
15950 | ||
15951 | i915_redisable_vga(dev); | |
74c090b1 | 15952 | ret = drm_atomic_commit(state); |
043e9bda ML |
15953 | if (!ret) |
15954 | return; | |
15955 | ||
15956 | err: | |
15957 | DRM_ERROR("Restoring old state failed with %i\n", ret); | |
15958 | drm_atomic_state_free(state); | |
2c7111db CW |
15959 | } |
15960 | ||
15961 | void intel_modeset_gem_init(struct drm_device *dev) | |
15962 | { | |
484b41dd | 15963 | struct drm_crtc *c; |
2ff8fde1 | 15964 | struct drm_i915_gem_object *obj; |
e0d6149b | 15965 | int ret; |
484b41dd | 15966 | |
ae48434c ID |
15967 | mutex_lock(&dev->struct_mutex); |
15968 | intel_init_gt_powersave(dev); | |
15969 | mutex_unlock(&dev->struct_mutex); | |
15970 | ||
1833b134 | 15971 | intel_modeset_init_hw(dev); |
02e792fb DV |
15972 | |
15973 | intel_setup_overlay(dev); | |
484b41dd JB |
15974 | |
15975 | /* | |
15976 | * Make sure any fbs we allocated at startup are properly | |
15977 | * pinned & fenced. When we do the allocation it's too early | |
15978 | * for this. | |
15979 | */ | |
70e1e0ec | 15980 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
15981 | obj = intel_fb_obj(c->primary->fb); |
15982 | if (obj == NULL) | |
484b41dd JB |
15983 | continue; |
15984 | ||
e0d6149b TU |
15985 | mutex_lock(&dev->struct_mutex); |
15986 | ret = intel_pin_and_fence_fb_obj(c->primary, | |
15987 | c->primary->fb, | |
7580d774 | 15988 | c->primary->state); |
e0d6149b TU |
15989 | mutex_unlock(&dev->struct_mutex); |
15990 | if (ret) { | |
484b41dd JB |
15991 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
15992 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
15993 | drm_framebuffer_unreference(c->primary->fb); |
15994 | c->primary->fb = NULL; | |
36750f28 | 15995 | c->primary->crtc = c->primary->state->crtc = NULL; |
afd65eb4 | 15996 | update_state_fb(c->primary); |
36750f28 | 15997 | c->state->plane_mask &= ~(1 << drm_plane_index(c->primary)); |
484b41dd JB |
15998 | } |
15999 | } | |
0962c3c9 VS |
16000 | |
16001 | intel_backlight_register(dev); | |
79e53945 JB |
16002 | } |
16003 | ||
4932e2c3 ID |
16004 | void intel_connector_unregister(struct intel_connector *intel_connector) |
16005 | { | |
16006 | struct drm_connector *connector = &intel_connector->base; | |
16007 | ||
16008 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 16009 | drm_connector_unregister(connector); |
4932e2c3 ID |
16010 | } |
16011 | ||
79e53945 JB |
16012 | void intel_modeset_cleanup(struct drm_device *dev) |
16013 | { | |
652c393a | 16014 | struct drm_i915_private *dev_priv = dev->dev_private; |
19c8054c | 16015 | struct intel_connector *connector; |
652c393a | 16016 | |
2eb5252e ID |
16017 | intel_disable_gt_powersave(dev); |
16018 | ||
0962c3c9 VS |
16019 | intel_backlight_unregister(dev); |
16020 | ||
fd0c0642 DV |
16021 | /* |
16022 | * Interrupts and polling as the first thing to avoid creating havoc. | |
2eb5252e | 16023 | * Too much stuff here (turning of connectors, ...) would |
fd0c0642 DV |
16024 | * experience fancy races otherwise. |
16025 | */ | |
2aeb7d3a | 16026 | intel_irq_uninstall(dev_priv); |
eb21b92b | 16027 | |
fd0c0642 DV |
16028 | /* |
16029 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
16030 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
16031 | */ | |
f87ea761 | 16032 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 16033 | |
723bfd70 JB |
16034 | intel_unregister_dsm_handler(); |
16035 | ||
c937ab3e | 16036 | intel_fbc_global_disable(dev_priv); |
69341a5e | 16037 | |
1630fe75 CW |
16038 | /* flush any delayed tasks or pending work */ |
16039 | flush_scheduled_work(); | |
16040 | ||
db31af1d | 16041 | /* destroy the backlight and sysfs files before encoders/connectors */ |
19c8054c JN |
16042 | for_each_intel_connector(dev, connector) |
16043 | connector->unregister(connector); | |
d9255d57 | 16044 | |
79e53945 | 16045 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
16046 | |
16047 | intel_cleanup_overlay(dev); | |
ae48434c ID |
16048 | |
16049 | mutex_lock(&dev->struct_mutex); | |
16050 | intel_cleanup_gt_powersave(dev); | |
16051 | mutex_unlock(&dev->struct_mutex); | |
f5949141 DV |
16052 | |
16053 | intel_teardown_gmbus(dev); | |
79e53945 JB |
16054 | } |
16055 | ||
f1c79df3 ZW |
16056 | /* |
16057 | * Return which encoder is currently attached for connector. | |
16058 | */ | |
df0e9248 | 16059 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 16060 | { |
df0e9248 CW |
16061 | return &intel_attached_encoder(connector)->base; |
16062 | } | |
f1c79df3 | 16063 | |
df0e9248 CW |
16064 | void intel_connector_attach_encoder(struct intel_connector *connector, |
16065 | struct intel_encoder *encoder) | |
16066 | { | |
16067 | connector->encoder = encoder; | |
16068 | drm_mode_connector_attach_encoder(&connector->base, | |
16069 | &encoder->base); | |
79e53945 | 16070 | } |
28d52043 DA |
16071 | |
16072 | /* | |
16073 | * set vga decode state - true == enable VGA decode | |
16074 | */ | |
16075 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
16076 | { | |
16077 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 16078 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
16079 | u16 gmch_ctrl; |
16080 | ||
75fa041d CW |
16081 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
16082 | DRM_ERROR("failed to read control word\n"); | |
16083 | return -EIO; | |
16084 | } | |
16085 | ||
c0cc8a55 CW |
16086 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
16087 | return 0; | |
16088 | ||
28d52043 DA |
16089 | if (state) |
16090 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
16091 | else | |
16092 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
16093 | |
16094 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
16095 | DRM_ERROR("failed to write control word\n"); | |
16096 | return -EIO; | |
16097 | } | |
16098 | ||
28d52043 DA |
16099 | return 0; |
16100 | } | |
c4a1d9e4 | 16101 | |
c4a1d9e4 | 16102 | struct intel_display_error_state { |
ff57f1b0 PZ |
16103 | |
16104 | u32 power_well_driver; | |
16105 | ||
63b66e5b CW |
16106 | int num_transcoders; |
16107 | ||
c4a1d9e4 CW |
16108 | struct intel_cursor_error_state { |
16109 | u32 control; | |
16110 | u32 position; | |
16111 | u32 base; | |
16112 | u32 size; | |
52331309 | 16113 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16114 | |
16115 | struct intel_pipe_error_state { | |
ddf9c536 | 16116 | bool power_domain_on; |
c4a1d9e4 | 16117 | u32 source; |
f301b1e1 | 16118 | u32 stat; |
52331309 | 16119 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
16120 | |
16121 | struct intel_plane_error_state { | |
16122 | u32 control; | |
16123 | u32 stride; | |
16124 | u32 size; | |
16125 | u32 pos; | |
16126 | u32 addr; | |
16127 | u32 surface; | |
16128 | u32 tile_offset; | |
52331309 | 16129 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
16130 | |
16131 | struct intel_transcoder_error_state { | |
ddf9c536 | 16132 | bool power_domain_on; |
63b66e5b CW |
16133 | enum transcoder cpu_transcoder; |
16134 | ||
16135 | u32 conf; | |
16136 | ||
16137 | u32 htotal; | |
16138 | u32 hblank; | |
16139 | u32 hsync; | |
16140 | u32 vtotal; | |
16141 | u32 vblank; | |
16142 | u32 vsync; | |
16143 | } transcoder[4]; | |
c4a1d9e4 CW |
16144 | }; |
16145 | ||
16146 | struct intel_display_error_state * | |
16147 | intel_display_capture_error_state(struct drm_device *dev) | |
16148 | { | |
fbee40df | 16149 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 16150 | struct intel_display_error_state *error; |
63b66e5b CW |
16151 | int transcoders[] = { |
16152 | TRANSCODER_A, | |
16153 | TRANSCODER_B, | |
16154 | TRANSCODER_C, | |
16155 | TRANSCODER_EDP, | |
16156 | }; | |
c4a1d9e4 CW |
16157 | int i; |
16158 | ||
63b66e5b CW |
16159 | if (INTEL_INFO(dev)->num_pipes == 0) |
16160 | return NULL; | |
16161 | ||
9d1cb914 | 16162 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
16163 | if (error == NULL) |
16164 | return NULL; | |
16165 | ||
190be112 | 16166 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
16167 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
16168 | ||
055e393f | 16169 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 16170 | error->pipe[i].power_domain_on = |
f458ebbc DV |
16171 | __intel_display_power_is_enabled(dev_priv, |
16172 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 16173 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
16174 | continue; |
16175 | ||
5efb3e28 VS |
16176 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
16177 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
16178 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
16179 | |
16180 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
16181 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 16182 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 16183 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
16184 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
16185 | } | |
ca291363 PZ |
16186 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
16187 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
16188 | if (INTEL_INFO(dev)->gen >= 4) { |
16189 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
16190 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
16191 | } | |
16192 | ||
c4a1d9e4 | 16193 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 16194 | |
3abfce77 | 16195 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 16196 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
16197 | } |
16198 | ||
16199 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
16200 | if (HAS_DDI(dev_priv->dev)) | |
16201 | error->num_transcoders++; /* Account for eDP. */ | |
16202 | ||
16203 | for (i = 0; i < error->num_transcoders; i++) { | |
16204 | enum transcoder cpu_transcoder = transcoders[i]; | |
16205 | ||
ddf9c536 | 16206 | error->transcoder[i].power_domain_on = |
f458ebbc | 16207 | __intel_display_power_is_enabled(dev_priv, |
38cc1daf | 16208 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 16209 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
16210 | continue; |
16211 | ||
63b66e5b CW |
16212 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
16213 | ||
16214 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
16215 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
16216 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
16217 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
16218 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
16219 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
16220 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
16221 | } |
16222 | ||
16223 | return error; | |
16224 | } | |
16225 | ||
edc3d884 MK |
16226 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
16227 | ||
c4a1d9e4 | 16228 | void |
edc3d884 | 16229 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
16230 | struct drm_device *dev, |
16231 | struct intel_display_error_state *error) | |
16232 | { | |
055e393f | 16233 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
16234 | int i; |
16235 | ||
63b66e5b CW |
16236 | if (!error) |
16237 | return; | |
16238 | ||
edc3d884 | 16239 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 16240 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 16241 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 16242 | error->power_well_driver); |
055e393f | 16243 | for_each_pipe(dev_priv, i) { |
edc3d884 | 16244 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 | 16245 | err_printf(m, " Power: %s\n", |
87ad3212 | 16246 | onoff(error->pipe[i].power_domain_on)); |
edc3d884 | 16247 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 16248 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
16249 | |
16250 | err_printf(m, "Plane [%d]:\n", i); | |
16251 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
16252 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 16253 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
16254 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
16255 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 16256 | } |
4b71a570 | 16257 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 16258 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 16259 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
16260 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
16261 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
16262 | } |
16263 | ||
edc3d884 MK |
16264 | err_printf(m, "Cursor [%d]:\n", i); |
16265 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
16266 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
16267 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 16268 | } |
63b66e5b CW |
16269 | |
16270 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 16271 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 16272 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 | 16273 | err_printf(m, " Power: %s\n", |
87ad3212 | 16274 | onoff(error->transcoder[i].power_domain_on)); |
63b66e5b CW |
16275 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
16276 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
16277 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
16278 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
16279 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
16280 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
16281 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
16282 | } | |
c4a1d9e4 | 16283 | } |
e2fcdaa9 VS |
16284 | |
16285 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) | |
16286 | { | |
16287 | struct intel_crtc *crtc; | |
16288 | ||
16289 | for_each_intel_crtc(dev, crtc) { | |
16290 | struct intel_unpin_work *work; | |
e2fcdaa9 | 16291 | |
5e2d7afc | 16292 | spin_lock_irq(&dev->event_lock); |
e2fcdaa9 VS |
16293 | |
16294 | work = crtc->unpin_work; | |
16295 | ||
16296 | if (work && work->event && | |
16297 | work->event->base.file_priv == file) { | |
16298 | kfree(work->event); | |
16299 | work->event = NULL; | |
16300 | } | |
16301 | ||
5e2d7afc | 16302 | spin_unlock_irq(&dev->event_lock); |
e2fcdaa9 VS |
16303 | } |
16304 | } |